Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes

1648 files changed, 146884 insertions, 9586 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c8f528284a94..4b8acd2851f4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -17,6 +17,7 @@ config ARM
         select HAVE_KRETPROBES if (HAVE_KPROBES)
         select HAVE_FTRACE if (!XIP_KERNEL)
         select HAVE_DYNAMIC_FTRACE if (HAVE_FTRACE)
+        select HAVE_GENERIC_DMA_COHERENT
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -234,6 +235,7 @@ config ARCH_VERSATILE
 config ARCH_AT91
         bool "Atmel AT91"
         select GENERIC_GPIO
+        select HAVE_CLK
         help
           This enables support for systems based on the Atmel AT91RM9200,
           AT91SAM9 and AT91CAP9 processors.
@@ -267,7 +269,6 @@ config ARCH_EP93XX
         select ARM_VIC
         select GENERIC_GPIO
         select HAVE_CLK
-        select HAVE_CLK
         select ARCH_REQUIRE_GPIOLIB
         help
           This enables support for the Cirrus EP93xx series of CPUs.
@@ -1224,6 +1225,8 @@ source "drivers/dma/Kconfig"
 
 source "drivers/dca/Kconfig"
 
+source "drivers/regulator/Kconfig"
+
 source "drivers/uio/Kconfig"
 
 endmenu
diff --git a/arch/arm/configs/at91cap9adk_defconfig b/arch/arm/configs/at91cap9adk_defconfig
index be2b2f38fd94..bf97801a1068 100644
--- a/arch/arm/configs/at91cap9adk_defconfig
+++ b/arch/arm/configs/at91cap9adk_defconfig
@@ -170,7 +170,7 @@ CONFIG_MACH_AT91CAP9ADK=y
 # AT91 Board Options
 #
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
-# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
@@ -442,7 +442,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_ATMEL=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index 2011adfa6758..38e6a0abeb4e 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -176,7 +176,7 @@ CONFIG_MACH_AT91SAM9260EK=y
 # AT91 Board Options
 #
 # CONFIG_MTD_AT91_DATAFLASH_CARD is not set
-# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index 4049768962d2..93b779f94b41 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -169,7 +169,7 @@ CONFIG_MACH_AT91SAM9261EK=y
 # AT91 Board Options
 #
 # CONFIG_MTD_AT91_DATAFLASH_CARD is not set
-# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
@@ -433,7 +433,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_ATMEL=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index fa1c5aecb5a8..a7ddd94363ca 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -169,7 +169,7 @@ CONFIG_MACH_AT91SAM9263EK=y
 # AT91 Board Options
 #
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
-# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
@@ -428,7 +428,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_ATMEL=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index c06863847364..df0d6ee672b3 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -168,7 +168,7 @@ CONFIG_MACH_AT91SAM9G20EK=y
 # AT91 Board Options
 #
 # CONFIG_MTD_AT91_DATAFLASH_CARD is not set
-# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
@@ -442,10 +442,10 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
-CONFIG_MTD_NAND_AT91_ECC_SOFT=y
-# CONFIG_MTD_NAND_AT91_ECC_HW is not set
-# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index d8ec5f9ca6ec..1c76642272a1 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -392,7 +392,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_ATMEL=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ONENAND is not set
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
index f3cd4a95373a..f945105d6cd6 100644
--- a/arch/arm/configs/cam60_defconfig
+++ b/arch/arm/configs/cam60_defconfig
@@ -466,10 +466,10 @@ CONFIG_MTD_NAND_VERIFY_WRITE=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
-# CONFIG_MTD_NAND_AT91_ECC_SOFT is not set
-CONFIG_MTD_NAND_AT91_ECC_HW=y
-# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+CONFIG_MTD_NAND_ATMEL=y
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
index ef903bed061e..5cbd81589647 100644
--- a/arch/arm/configs/qil-a9260_defconfig
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -458,10 +458,10 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
-CONFIG_MTD_NAND_AT91_ECC_SOFT=y
-# CONFIG_MTD_NAND_AT91_ECC_HW is not set
-# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index 8688362bcf7b..1174e2764875 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -429,7 +429,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_ATMEL=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 CONFIG_MTD_NAND_PLATFORM=y
 # CONFIG_MTD_ONENAND is not set
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
index 3680bd2df26d..fcb4aaabd439 100644
--- a/arch/arm/configs/usb-a9260_defconfig
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -458,10 +458,10 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
-CONFIG_MTD_NAND_AT91_ECC_SOFT=y
-# CONFIG_MTD_NAND_AT91_ECC_HW is not set
-# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/usb-a9263_defconfig b/arch/arm/configs/usb-a9263_defconfig
index 48d455bc7363..b786e0407e8e 100644
--- a/arch/arm/configs/usb-a9263_defconfig
+++ b/arch/arm/configs/usb-a9263_defconfig
@@ -450,10 +450,10 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_AT91=y
-CONFIG_MTD_NAND_AT91_ECC_SOFT=y
-# CONFIG_MTD_NAND_AT91_ECC_HW is not set
-# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/configs/yl9200_defconfig b/arch/arm/configs/yl9200_defconfig
index 26de37f74686..a9f41c24c9dc 100644
--- a/arch/arm/configs/yl9200_defconfig
+++ b/arch/arm/configs/yl9200_defconfig
@@ -421,7 +421,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_NAND_AT91=y
+CONFIG_MTD_NAND_ATMEL=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 CONFIG_MTD_NAND_PLATFORM=y
 # CONFIG_MTD_ALAUDA is not set
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index f41335ba6337..45329fca1b64 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -7,6 +7,8 @@
 
 #include <linux/scatterlist.h>
 
+#include <asm-generic/dma-coherent.h>
+
 /*
  * DMA-consistent mapping functions.  These allocate/free a region of
  * uncached, unwrite-buffered mapped memory space for use with DMA
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5bad6b9b00d7..a048b92cb407 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -297,7 +297,7 @@ config MTD_AT91_DATAFLASH_CARD
         help
           Enable support for the DataFlash card.
 
-config MTD_NAND_AT91_BUSWIDTH_16
+config MTD_NAND_ATMEL_BUSWIDTH_16
         bool "Enable 16-bit data bus interface to NAND flash"
         depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK)
         help
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index dc8b40783d94..25765f1afca9 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -376,7 +376,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  *  NAND / SmartMedia
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 static struct atmel_nand_data nand_data;
 
 #define NAND_BASE       AT91_CHIPSELECT_3
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 8ced9bc82099..d2c5c84bf6b8 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -368,7 +368,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  *  NAND / SmartMedia
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 static struct atmel_nand_data nand_data;
 
 #define NAND_BASE       AT91_CHIPSELECT_3
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index cae5f52f1278..f5fec0a9cf49 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -283,7 +283,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  *  NAND / SmartMedia
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 static struct atmel_nand_data nand_data;
 
 #define NAND_BASE       AT91_CHIPSELECT_3
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 483d436af22d..b80860e31383 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -198,7 +198,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  *  NAND / SmartMedia
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 static struct atmel_nand_data nand_data;
 
 #define NAND_BASE       AT91_CHIPSELECT_3
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 9762b15f658a..42108d02f593 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -352,7 +352,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  *  NAND / SmartMedia
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 static struct atmel_nand_data nand_data;
 
 #define NAND_BASE       AT91_CHIPSELECT_3
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 5f3094870cad..9c61576f1c8d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -194,7 +194,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  *  NAND / SmartMedia
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 static struct atmel_nand_data nand_data;
 
 #define NAND_BASE       AT91_CHIPSELECT_3
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 83a4494adc9e..fd21d4240e8e 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -188,7 +188,7 @@ static struct atmel_nand_data __initdata cap9adk_nand_data = {
 //      .rdy_pin        = ... not connected
         .enable_pin     = AT91_PIN_PD15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index cb3e48cd1d5b..5393b8079bd7 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -147,7 +147,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 61eab0deb353..fe8a8ac89d64 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -148,7 +148,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index de5b072dad3a..6f3b377dc378 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -185,7 +185,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 9a67434a1264..9d3c65e79c36 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -190,7 +190,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC15,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index cc925eca1116..334b159285c3 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -194,7 +194,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PA22,
         .enable_pin     = AT91_PIN_PD15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 688295f104ce..f0975bba6d51 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -149,7 +149,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
index aed31f863600..4048e47c5190 100644
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -121,7 +121,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
index e37343aedf1b..a2b94947f575 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -134,7 +134,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PA22,
         .enable_pin     = AT91_PIN_PD15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
         .bus_width_16   = 1,
 #else
         .bus_width_16   = 0,
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index e1f8de2c74a2..b6437f47a77f 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -18,6 +18,7 @@
 #include <linux/timer.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
@@ -69,6 +70,8 @@ static struct platform_device rd88f6281_nand_flash = {
 
 static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
         .phy_addr       = -1,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
 };
 
 static struct mv_sata_platform_data rd88f6281_sata_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index d50e3650a09e..73e9242da7ad 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -15,6 +15,7 @@
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/leds.h>
@@ -88,6 +89,8 @@ static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
 
 static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
         .phy_addr       = -1,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
 };
 
 static void __init rd88f5181l_fxo_init(void)
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index b56447d32e17..ac482019abbf 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -15,6 +15,7 @@
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
 #include <linux/i2c.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
@@ -89,6 +90,8 @@ static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
 
 static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
         .phy_addr       = -1,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
 };
 
 static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 1af093ff8cf3..25568c2a3d29 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -14,6 +14,7 @@
 #include <linux/delay.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -92,6 +93,8 @@ static struct platform_device wnr854t_nor_flash = {
 
 static struct mv643xx_eth_platform_data wnr854t_eth_data = {
         .phy_addr       = -1,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
 };
 
 static void __init wnr854t_init(void)
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index aeab55c6a82d..9b8ee8c48bf0 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -14,6 +14,7 @@
 #include <linux/delay.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -100,6 +101,8 @@ static struct platform_device wrt350n_v2_nor_flash = {
 
 static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
         .phy_addr       = -1,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
 };
 
 static void __init wrt350n_v2_init(void)
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 30023b00e476..90056d56b210 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -22,7 +22,6 @@
 
 #include <linux/irq.h>
 #include <linux/platform_device.h>
-#include <linux/ide.h>
 #include <linux/i2c.h>
 #include <linux/pwm_backlight.h>
 
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
index 333a82a3717e..db7b3e38ef1d 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/consistent.c
@@ -274,6 +274,11 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
 void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
 {
+        void *memory;
+
+        if (dma_alloc_from_coherent(dev, size, handle, &memory))
+                return memory;
+
         if (arch_is_coherent()) {
                 void *virt;
 
@@ -362,6 +367,9 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
 
         WARN_ON(irqs_disabled());
 
+        if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
+                return;
+
         if (arch_is_coherent()) {
                 kfree(cpu_addr);
                 return;
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
index 2a92cb1886ca..7a64fcef9d07 100644
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -641,6 +641,7 @@ config PCI
        bool
        depends on ETRAX_CARDBUS
        default y
+       select HAVE_GENERIC_DMA_COHERENT
 
 config ETRAX_IOP_FW_LOAD
         tristate "IO-processor hotplug firmware loading support"
diff --git a/arch/cris/arch-v32/drivers/pci/dma.c b/arch/cris/arch-v32/drivers/pci/dma.c
index e0364654fc44..fbe65954ee6c 100644
--- a/arch/cris/arch-v32/drivers/pci/dma.c
+++ b/arch/cris/arch-v32/drivers/pci/dma.c
@@ -15,35 +15,16 @@
 #include <linux/pci.h>
 #include <asm/io.h>
 
-struct dma_coherent_mem {
-        void            *virt_base;
-        u32             device_base;
-        int             size;
-        int             flags;
-        unsigned long   *bitmap;
-};
-
 void *dma_alloc_coherent(struct device *dev, size_t size,
                            dma_addr_t *dma_handle, gfp_t gfp)
 {
         void *ret;
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
         int order = get_order(size);
         /* ignore region specifiers */
         gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
 
-        if (mem) {
-                int page = bitmap_find_free_region(mem->bitmap, mem->size,
-                                                     order);
-                if (page >= 0) {
-                        *dma_handle = mem->device_base + (page << PAGE_SHIFT);
-                        ret = mem->virt_base + (page << PAGE_SHIFT);
-                        memset(ret, 0, size);
-                        return ret;
-                }
-                if (mem->flags & DMA_MEMORY_EXCLUSIVE)
-                        return NULL;
-        }
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+                return ret;
 
         if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
                 gfp |= GFP_DMA;
@@ -60,90 +41,9 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
 void dma_free_coherent(struct device *dev, size_t size,
                          void *vaddr, dma_addr_t dma_handle)
 {
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
         int order = get_order(size);
 
-        if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) {
-                int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
-
-                bitmap_release_region(mem->bitmap, page, order);
-        } else
+        if (!dma_release_from_coherent(dev, order, vaddr))
                 free_pages((unsigned long)vaddr, order);
 }
 
-int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
-                                dma_addr_t device_addr, size_t size, int flags)
-{
-        void __iomem *mem_base;
-        int pages = size >> PAGE_SHIFT;
-        int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
-
-        if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
-                goto out;
-        if (!size)
-                goto out;
-        if (dev->dma_mem)
-                goto out;
-
-        /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
-
-        mem_base = ioremap(bus_addr, size);
-        if (!mem_base)
-                goto out;
-
-        dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
-        if (!dev->dma_mem)
-                goto iounmap_out;
-        dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-        if (!dev->dma_mem->bitmap)
-                goto free1_out;
-
-        dev->dma_mem->virt_base = mem_base;
-        dev->dma_mem->device_base = device_addr;
-        dev->dma_mem->size = pages;
-        dev->dma_mem->flags = flags;
-
-        if (flags & DMA_MEMORY_MAP)
-                return DMA_MEMORY_MAP;
-
-        return DMA_MEMORY_IO;
-
- free1_out:
-        kfree(dev->dma_mem);
- iounmap_out:
-        iounmap(mem_base);
- out:
-        return 0;
-}
-EXPORT_SYMBOL(dma_declare_coherent_memory);
-
-void dma_release_declared_memory(struct device *dev)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-
-        if(!mem)
-                return;
-        dev->dma_mem = NULL;
-        iounmap(mem->virt_base);
-        kfree(mem->bitmap);
-        kfree(mem);
-}
-EXPORT_SYMBOL(dma_release_declared_memory);
-
-void *dma_mark_declared_memory_occupied(struct device *dev,
-                                        dma_addr_t device_addr, size_t size)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-        int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT;
-        int pos, err;
-
-        if (!mem)
-                return ERR_PTR(-EINVAL);
-
-        pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
-        err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
-        if (err != 0)
-                return ERR_PTR(err);
-        return mem->virt_base + (pos << PAGE_SHIFT);
-}
-EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
index b8a4b94779b1..99060ab507ee 100644
--- a/arch/frv/kernel/entry.S
+++ b/arch/frv/kernel/entry.S
@@ -1519,6 +1519,11 @@ sys_call_table:
         .long sys_fallocate
         .long sys_timerfd_settime       /* 325 */
         .long sys_timerfd_gettime
-
+        .long sys_signalfd4
+        .long sys_eventfd2
+        .long sys_epoll_create1
+        .long sys_dup3                  /* 330 */
+        .long sys_pipe2
+        .long sys_inotify_init1
 
 syscall_table_size = (. - sys_call_table)
diff --git a/arch/ia64/include/asm/Kbuild b/arch/ia64/include/asm/Kbuild
new file mode 100644
index 000000000000..ccbe8ae47a61
--- /dev/null
+++ b/arch/ia64/include/asm/Kbuild
@@ -0,0 +1,16 @@
+include include/asm-generic/Kbuild.asm
+
+header-y += break.h
+header-y += fpu.h
+header-y += fpswa.h
+header-y += ia64regs.h
+header-y += intel_intrin.h
+header-y += perfmon_default_smpl.h
+header-y += ptrace_offsets.h
+header-y += rse.h
+header-y += ucontext.h
+
+unifdef-y += gcc_intrin.h
+unifdef-y += intrinsics.h
+unifdef-y += perfmon.h
+unifdef-y += ustack.h
diff --git a/arch/ia64/include/asm/a.out.h b/arch/ia64/include/asm/a.out.h
new file mode 100644
index 000000000000..193dcfb67596
--- /dev/null
+++ b/arch/ia64/include/asm/a.out.h
@@ -0,0 +1,32 @@
+#ifndef _ASM_IA64_A_OUT_H
+#define _ASM_IA64_A_OUT_H
+
+/*
+ * No a.out format has been (or should be) defined so this file is
+ * just a dummy that allows us to get binfmt_elf compiled.  It
+ * probably would be better to clean up binfmt_elf.c so it does not
+ * necessarily depend on there being a.out support.
+ *
+ * Modified 1998-2002
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
+ */
+
+#include <linux/types.h>
+
+struct exec {
+        unsigned long a_info;
+        unsigned long a_text;
+        unsigned long a_data;
+        unsigned long a_bss;
+        unsigned long a_entry;
+};
+
+#define N_TXTADDR(x)    0
+#define N_DATADDR(x)    0
+#define N_BSSADDR(x)    0
+#define N_DRSIZE(x)     0
+#define N_TRSIZE(x)     0
+#define N_SYMSIZE(x)    0
+#define N_TXTOFF(x)     0
+
+#endif /* _ASM_IA64_A_OUT_H */
diff --git a/arch/ia64/include/asm/acpi-ext.h b/arch/ia64/include/asm/acpi-ext.h
new file mode 100644
index 000000000000..734d137dda6e
--- /dev/null
+++ b/arch/ia64/include/asm/acpi-ext.h
@@ -0,0 +1,21 @@
+/*
+ * (c) Copyright 2003, 2006 Hewlett-Packard Development Company, L.P.
+ *      Alex Williamson <alex.williamson@hp.com>
+ *      Bjorn Helgaas <bjorn.helgaas@hp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Vendor specific extensions to ACPI.
+ */
+
+#ifndef _ASM_IA64_ACPI_EXT_H
+#define _ASM_IA64_ACPI_EXT_H
+
+#include <linux/types.h>
+#include <acpi/actypes.h>
+
+extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length);
+
+#endif /* _ASM_IA64_ACPI_EXT_H */
diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h
new file mode 100644
index 000000000000..0f82cc2934e1
--- /dev/null
+++ b/arch/ia64/include/asm/acpi.h
@@ -0,0 +1,165 @@
+/*
+ *  Copyright (C) 1999 VA Linux Systems
+ *  Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ *  Copyright (C) 2000,2001 J.I. Lee <jung-ik.lee@intel.com>
+ *  Copyright (C) 2001,2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#ifndef _ASM_ACPI_H
+#define _ASM_ACPI_H
+
+#ifdef __KERNEL__
+
+#include <acpi/pdc_intel.h>
+
+#include <linux/init.h>
+#include <linux/numa.h>
+#include <asm/system.h>
+#include <asm/numa.h>
+
+#define COMPILER_DEPENDENT_INT64        long
+#define COMPILER_DEPENDENT_UINT64       unsigned long
+
+/*
+ * Calling conventions:
+ *
+ * ACPI_SYSTEM_XFACE        - Interfaces to host OS (handlers, threads)
+ * ACPI_EXTERNAL_XFACE      - External ACPI interfaces
+ * ACPI_INTERNAL_XFACE      - Internal ACPI interfaces
+ * ACPI_INTERNAL_VAR_XFACE  - Internal variable-parameter list interfaces
+ */
+#define ACPI_SYSTEM_XFACE
+#define ACPI_EXTERNAL_XFACE
+#define ACPI_INTERNAL_XFACE
+#define ACPI_INTERNAL_VAR_XFACE
+
+/* Asm macros */
+
+#define ACPI_ASM_MACROS
+#define BREAKPOINT3
+#define ACPI_DISABLE_IRQS() local_irq_disable()
+#define ACPI_ENABLE_IRQS()  local_irq_enable()
+#define ACPI_FLUSH_CPU_CACHE()
+
+static inline int
+ia64_acpi_acquire_global_lock (unsigned int *lock)
+{
+        unsigned int old, new, val;
+        do {
+                old = *lock;
+                new = (((old & ~0x3) + 2) + ((old >> 1) & 0x1));
+                val = ia64_cmpxchg4_acq(lock, new, old);
+        } while (unlikely (val != old));
+        return (new < 3) ? -1 : 0;
+}
+
+static inline int
+ia64_acpi_release_global_lock (unsigned int *lock)
+{
+        unsigned int old, new, val;
+        do {
+                old = *lock;
+                new = old & ~0x3;
+                val = ia64_cmpxchg4_acq(lock, new, old);
+        } while (unlikely (val != old));
+        return old & 0x1;
+}
+
+#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq)                             \
+        ((Acq) = ia64_acpi_acquire_global_lock(&facs->global_lock))
+
+#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq)                             \
+        ((Acq) = ia64_acpi_release_global_lock(&facs->global_lock))
+
+#define acpi_disabled 0 /* ACPI always enabled on IA64 */
+#define acpi_noirq 0    /* ACPI always enabled on IA64 */
+#define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */
+#define acpi_strict 1   /* no ACPI spec workarounds on IA64 */
+#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
+static inline void disable_acpi(void) { }
+
+const char *acpi_get_sysname (void);
+int acpi_request_vector (u32 int_type);
+int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
+
+/* routines for saving/restoring kernel state */
+extern int acpi_save_state_mem(void);
+extern void acpi_restore_state_mem(void);
+extern unsigned long acpi_wakeup_address;
+
+/*
+ * Record the cpei override flag and current logical cpu. This is
+ * useful for CPU removal.
+ */
+extern unsigned int can_cpei_retarget(void);
+extern unsigned int is_cpu_cpei_target(unsigned int cpu);
+extern void set_cpei_target_cpu(unsigned int cpu);
+extern unsigned int get_cpei_target_cpu(void);
+extern void prefill_possible_map(void);
+#ifdef CONFIG_ACPI_HOTPLUG_CPU
+extern int additional_cpus;
+#else
+#define additional_cpus 0
+#endif
+
+#ifdef CONFIG_ACPI_NUMA
+#if MAX_NUMNODES > 256
+#define MAX_PXM_DOMAINS MAX_NUMNODES
+#else
+#define MAX_PXM_DOMAINS (256)
+#endif
+extern int __devinitdata pxm_to_nid_map[MAX_PXM_DOMAINS];
+extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
+#endif
+
+#define acpi_unlazy_tlb(x)
+
+#ifdef CONFIG_ACPI_NUMA
+extern cpumask_t early_cpu_possible_map;
+#define for_each_possible_early_cpu(cpu)  \
+        for_each_cpu_mask((cpu), early_cpu_possible_map)
+
+static inline void per_cpu_scan_finalize(int min_cpus, int reserve_cpus)
+{
+        int low_cpu, high_cpu;
+        int cpu;
+        int next_nid = 0;
+
+        low_cpu = cpus_weight(early_cpu_possible_map);
+
+        high_cpu = max(low_cpu, min_cpus);
+        high_cpu = min(high_cpu + reserve_cpus, NR_CPUS);
+
+        for (cpu = low_cpu; cpu < high_cpu; cpu++) {
+                cpu_set(cpu, early_cpu_possible_map);
+                if (node_cpuid[cpu].nid == NUMA_NO_NODE) {
+                        node_cpuid[cpu].nid = next_nid;
+                        next_nid++;
+                        if (next_nid >= num_online_nodes())
+                                next_nid = 0;
+                }
+        }
+}
+#endif /* CONFIG_ACPI_NUMA */
+
+#endif /*__KERNEL__*/
+
+#endif /*_ASM_ACPI_H*/
diff --git a/arch/ia64/include/asm/agp.h b/arch/ia64/include/asm/agp.h
new file mode 100644
index 000000000000..c11fdd8ab4d7
--- /dev/null
+++ b/arch/ia64/include/asm/agp.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_IA64_AGP_H
+#define _ASM_IA64_AGP_H
+
+/*
+ * IA-64 specific AGP definitions.
+ *
+ * Copyright (C) 2002-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+/*
+ * To avoid memory-attribute aliasing issues, we require that the AGPGART engine operate
+ * in coherent mode, which lets us map the AGP memory as normal (write-back) memory
+ * (unlike x86, where it gets mapped "write-coalescing").
+ */
+#define map_page_into_agp(page)         /* nothing */
+#define unmap_page_from_agp(page)       /* nothing */
+#define flush_agp_cache()               mb()
+
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
+#endif /* _ASM_IA64_AGP_H */
diff --git a/arch/ia64/include/asm/asmmacro.h b/arch/ia64/include/asm/asmmacro.h
new file mode 100644
index 000000000000..c1642fd64029
--- /dev/null
+++ b/arch/ia64/include/asm/asmmacro.h
@@ -0,0 +1,135 @@
+#ifndef _ASM_IA64_ASMMACRO_H
+#define _ASM_IA64_ASMMACRO_H
+
+/*
+ * Copyright (C) 2000-2001, 2003-2004 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+
+#define ENTRY(name)                             \
+        .align 32;                              \
+        .proc name;                             \
+name:
+
+#define ENTRY_MIN_ALIGN(name)                   \
+        .align 16;                              \
+        .proc name;                             \
+name:
+
+#define GLOBAL_ENTRY(name)                      \
+        .global name;                           \
+        ENTRY(name)
+
+#define END(name)                               \
+        .endp name
+
+/*
+ * Helper macros to make unwind directives more readable:
+ */
+
+/* prologue_gr: */
+#define ASM_UNW_PRLG_RP                 0x8
+#define ASM_UNW_PRLG_PFS                0x4
+#define ASM_UNW_PRLG_PSP                0x2
+#define ASM_UNW_PRLG_PR                 0x1
+#define ASM_UNW_PRLG_GRSAVE(ninputs)    (32+(ninputs))
+
+/*
+ * Helper macros for accessing user memory.
+ *
+ * When adding any new .section/.previous entries here, make sure to
+ * also add it to the DISCARD section in arch/ia64/kernel/gate.lds.S or
+ * unpleasant things will happen.
+ */
+
+        .section "__ex_table", "a"              // declare section & section attributes
+        .previous
+
+# define EX(y,x...)                             \
+        .xdata4 "__ex_table", 99f-., y-.;       \
+  [99:] x
+# define EXCLR(y,x...)                          \
+        .xdata4 "__ex_table", 99f-., y-.+4;     \
+  [99:] x
+
+/*
+ * Tag MCA recoverable instruction ranges.
+ */
+
+        .section "__mca_table", "a"             // declare section & section attributes
+        .previous
+
+# define MCA_RECOVER_RANGE(y)                   \
+        .xdata4 "__mca_table", y-., 99f-.;      \
+  [99:]
+
+/*
+ * Mark instructions that need a load of a virtual address patched to be
+ * a load of a physical address.  We use this either in critical performance
+ * path (ivt.S - TLB miss processing) or in places where it might not be
+ * safe to use a "tpa" instruction (mca_asm.S - error recovery).
+ */
+        .section ".data.patch.vtop", "a"        // declare section & section attributes
+        .previous
+
+#define LOAD_PHYSICAL(pr, reg, obj)             \
+[1:](pr)movl reg = obj;                         \
+        .xdata4 ".data.patch.vtop", 1b-.
+
+/*
+ * For now, we always put in the McKinley E9 workaround.  On CPUs that don't need it,
+ * we'll patch out the work-around bundles with NOPs, so their impact is minimal.
+ */
+#define DO_MCKINLEY_E9_WORKAROUND
+
+#ifdef DO_MCKINLEY_E9_WORKAROUND
+        .section ".data.patch.mckinley_e9", "a"
+        .previous
+/* workaround for Itanium 2 Errata 9: */
+# define FSYS_RETURN                                    \
+        .xdata4 ".data.patch.mckinley_e9", 1f-.;        \
+1:{ .mib;                                               \
+        nop.m 0;                                        \
+        mov r16=ar.pfs;                                 \
+        br.call.sptk.many b7=2f;;                       \
+  };                                                    \
+2:{ .mib;                                               \
+        nop.m 0;                                        \
+        mov ar.pfs=r16;                                 \
+        br.ret.sptk.many b6;;                           \
+  }
+#else
+# define FSYS_RETURN    br.ret.sptk.many b6
+#endif
+
+/*
+ * If physical stack register size is different from DEF_NUM_STACK_REG,
+ * dynamically patch the kernel for correct size.
+ */
+        .section ".data.patch.phys_stack_reg", "a"
+        .previous
+#define LOAD_PHYS_STACK_REG_SIZE(reg)                   \
+[1:]    adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0;        \
+        .xdata4 ".data.patch.phys_stack_reg", 1b-.
+
+/*
+ * Up until early 2004, use of .align within a function caused bad unwind info.
+ * TEXT_ALIGN(n) expands into ".align n" if a fixed GAS is available or into nothing
+ * otherwise.
+ */
+#ifdef HAVE_WORKING_TEXT_ALIGN
+# define TEXT_ALIGN(n)  .align n
+#else
+# define TEXT_ALIGN(n)
+#endif
+
+#ifdef HAVE_SERIALIZE_DIRECTIVE
+# define dv_serialize_data              .serialize.data
+# define dv_serialize_instruction       .serialize.instruction
+#else
+# define dv_serialize_data
+# define dv_serialize_instruction
+#endif
+
+#endif /* _ASM_IA64_ASMMACRO_H */
diff --git a/arch/ia64/include/asm/atomic.h b/arch/ia64/include/asm/atomic.h
new file mode 100644
index 000000000000..50c2b83fd5a0
--- /dev/null
+++ b/arch/ia64/include/asm/atomic.h
@@ -0,0 +1,226 @@
+#ifndef _ASM_IA64_ATOMIC_H
+#define _ASM_IA64_ATOMIC_H
+
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ *
+ * NOTE: don't mess with the types below!  The "unsigned long" and
+ * "int" types were carefully placed so as to ensure proper operation
+ * of the macros.
+ *
+ * Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#include <linux/types.h>
+
+#include <asm/intrinsics.h>
+#include <asm/system.h>
+
+/*
+ * On IA-64, counter must always be volatile to ensure that that the
+ * memory accesses are ordered.
+ */
+typedef struct { volatile __s32 counter; } atomic_t;
+typedef struct { volatile __s64 counter; } atomic64_t;
+
+#define ATOMIC_INIT(i)          ((atomic_t) { (i) })
+#define ATOMIC64_INIT(i)        ((atomic64_t) { (i) })
+
+#define atomic_read(v)          ((v)->counter)
+#define atomic64_read(v)        ((v)->counter)
+
+#define atomic_set(v,i)         (((v)->counter) = (i))
+#define atomic64_set(v,i)       (((v)->counter) = (i))
+
+static __inline__ int
+ia64_atomic_add (int i, atomic_t *v)
+{
+        __s32 old, new;
+        CMPXCHG_BUGCHECK_DECL
+
+        do {
+                CMPXCHG_BUGCHECK(v);
+                old = atomic_read(v);
+                new = old + i;
+        } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old);
+        return new;
+}
+
+static __inline__ int
+ia64_atomic64_add (__s64 i, atomic64_t *v)
+{
+        __s64 old, new;
+        CMPXCHG_BUGCHECK_DECL
+
+        do {
+                CMPXCHG_BUGCHECK(v);
+                old = atomic64_read(v);
+                new = old + i;
+        } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
+        return new;
+}
+
+static __inline__ int
+ia64_atomic_sub (int i, atomic_t *v)
+{
+        __s32 old, new;
+        CMPXCHG_BUGCHECK_DECL
+
+        do {
+                CMPXCHG_BUGCHECK(v);
+                old = atomic_read(v);
+                new = old - i;
+        } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old);
+        return new;
+}
+
+static __inline__ int
+ia64_atomic64_sub (__s64 i, atomic64_t *v)
+{
+        __s64 old, new;
+        CMPXCHG_BUGCHECK_DECL
+
+        do {
+                CMPXCHG_BUGCHECK(v);
+                old = atomic64_read(v);
+                new = old - i;
+        } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
+        return new;
+}
+
+#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+#define atomic64_cmpxchg(v, old, new) \
+        (cmpxchg(&((v)->counter), old, new))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+#define atomic_add_return(i,v)                                          \
+({                                                                      \
+        int __ia64_aar_i = (i);                                         \
+        (__builtin_constant_p(i)                                        \
+         && (   (__ia64_aar_i ==  1) || (__ia64_aar_i ==   4)           \
+             || (__ia64_aar_i ==  8) || (__ia64_aar_i ==  16)           \
+             || (__ia64_aar_i == -1) || (__ia64_aar_i ==  -4)           \
+             || (__ia64_aar_i == -8) || (__ia64_aar_i == -16)))         \
+                ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter)       \
+                : ia64_atomic_add(__ia64_aar_i, v);                     \
+})
+
+#define atomic64_add_return(i,v)                                        \
+({                                                                      \
+        long __ia64_aar_i = (i);                                        \
+        (__builtin_constant_p(i)                                        \
+         && (   (__ia64_aar_i ==  1) || (__ia64_aar_i ==   4)           \
+             || (__ia64_aar_i ==  8) || (__ia64_aar_i ==  16)           \
+             || (__ia64_aar_i == -1) || (__ia64_aar_i ==  -4)           \
+             || (__ia64_aar_i == -8) || (__ia64_aar_i == -16)))         \
+                ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter)       \
+                : ia64_atomic64_add(__ia64_aar_i, v);                   \
+})
+
+/*
+ * Atomically add I to V and return TRUE if the resulting value is
+ * negative.
+ */
+static __inline__ int
+atomic_add_negative (int i, atomic_t *v)
+{
+        return atomic_add_return(i, v) < 0;
+}
+
+static __inline__ int
+atomic64_add_negative (__s64 i, atomic64_t *v)
+{
+        return atomic64_add_return(i, v) < 0;
+}
+
+#define atomic_sub_return(i,v)                                          \
+({                                                                      \
+        int __ia64_asr_i = (i);                                         \
+        (__builtin_constant_p(i)                                        \
+         && (   (__ia64_asr_i ==   1) || (__ia64_asr_i ==   4)          \
+             || (__ia64_asr_i ==   8) || (__ia64_asr_i ==  16)          \
+             || (__ia64_asr_i ==  -1) || (__ia64_asr_i ==  -4)          \
+             || (__ia64_asr_i ==  -8) || (__ia64_asr_i == -16)))        \
+                ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter)      \
+                : ia64_atomic_sub(__ia64_asr_i, v);                     \
+})
+
+#define atomic64_sub_return(i,v)                                        \
+({                                                                      \
+        long __ia64_asr_i = (i);                                        \
+        (__builtin_constant_p(i)                                        \
+         && (   (__ia64_asr_i ==   1) || (__ia64_asr_i ==   4)          \
+             || (__ia64_asr_i ==   8) || (__ia64_asr_i ==  16)          \
+             || (__ia64_asr_i ==  -1) || (__ia64_asr_i ==  -4)          \
+             || (__ia64_asr_i ==  -8) || (__ia64_asr_i == -16)))        \
+                ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter)      \
+                : ia64_atomic64_sub(__ia64_asr_i, v);                   \
+})
+
+#define atomic_dec_return(v)            atomic_sub_return(1, (v))
+#define atomic_inc_return(v)            atomic_add_return(1, (v))
+#define atomic64_dec_return(v)          atomic64_sub_return(1, (v))
+#define atomic64_inc_return(v)          atomic64_add_return(1, (v))
+
+#define atomic_sub_and_test(i,v)        (atomic_sub_return((i), (v)) == 0)
+#define atomic_dec_and_test(v)          (atomic_sub_return(1, (v)) == 0)
+#define atomic_inc_and_test(v)          (atomic_add_return(1, (v)) == 0)
+#define atomic64_sub_and_test(i,v)      (atomic64_sub_return((i), (v)) == 0)
+#define atomic64_dec_and_test(v)        (atomic64_sub_return(1, (v)) == 0)
+#define atomic64_inc_and_test(v)        (atomic64_add_return(1, (v)) == 0)
+
+#define atomic_add(i,v)                 atomic_add_return((i), (v))
+#define atomic_sub(i,v)                 atomic_sub_return((i), (v))
+#define atomic_inc(v)                   atomic_add(1, (v))
+#define atomic_dec(v)                   atomic_sub(1, (v))
+
+#define atomic64_add(i,v)               atomic64_add_return((i), (v))
+#define atomic64_sub(i,v)               atomic64_sub_return((i), (v))
+#define atomic64_inc(v)                 atomic64_add(1, (v))
+#define atomic64_dec(v)                 atomic64_sub(1, (v))
+
+/* Atomic operations are already serializing */
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+
+#include <asm-generic/atomic.h>
+#endif /* _ASM_IA64_ATOMIC_H */
diff --git a/arch/ia64/include/asm/auxvec.h b/arch/ia64/include/asm/auxvec.h
new file mode 100644
index 000000000000..23cebe5685b9
--- /dev/null
+++ b/arch/ia64/include/asm/auxvec.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_IA64_AUXVEC_H
+#define _ASM_IA64_AUXVEC_H
+
+/*
+ * Architecture-neutral AT_ values are in the range 0-17.  Leave some room for more of
+ * them, start the architecture-specific ones at 32.
+ */
+#define AT_SYSINFO      32
+#define AT_SYSINFO_EHDR 33
+
+#endif /* _ASM_IA64_AUXVEC_H */
diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h
new file mode 100644
index 000000000000..e2ca80037335
--- /dev/null
+++ b/arch/ia64/include/asm/bitops.h
@@ -0,0 +1,468 @@
+#ifndef _ASM_IA64_BITOPS_H
+#define _ASM_IA64_BITOPS_H
+
+/*
+ * Copyright (C) 1998-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
+ * O(1) scheduler patch
+ */
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/intrinsics.h>
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ *
+ * The address must be (at least) "long" aligned.
+ * Note that there are driver (e.g., eepro100) which use these operations to
+ * operate on hw-defined data-structures, so we can't easily change these
+ * operations to force a bigger alignment.
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ */
+static __inline__ void
+set_bit (int nr, volatile void *addr)
+{
+        __u32 bit, old, new;
+        volatile __u32 *m;
+        CMPXCHG_BUGCHECK_DECL
+
+        m = (volatile __u32 *) addr + (nr >> 5);
+        bit = 1 << (nr & 31);
+        do {
+                CMPXCHG_BUGCHECK(m);
+                old = *m;
+                new = old | bit;
+        } while (cmpxchg_acq(m, old, new) != old);
+}
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void
+__set_bit (int nr, volatile void *addr)
+{
+        *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
+}
+
+/*
+ * clear_bit() has "acquire" semantics.
+ */
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       do { /* skip */; } while (0)
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static __inline__ void
+clear_bit (int nr, volatile void *addr)
+{
+        __u32 mask, old, new;
+        volatile __u32 *m;
+        CMPXCHG_BUGCHECK_DECL
+
+        m = (volatile __u32 *) addr + (nr >> 5);
+        mask = ~(1 << (nr & 31));
+        do {
+                CMPXCHG_BUGCHECK(m);
+                old = *m;
+                new = old & mask;
+        } while (cmpxchg_acq(m, old, new) != old);
+}
+
+/**
+ * clear_bit_unlock - Clears a bit in memory with release
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit_unlock() is atomic and may not be reordered.  It does
+ * contain a memory barrier suitable for unlock type operations.
+ */
+static __inline__ void
+clear_bit_unlock (int nr, volatile void *addr)
+{
+        __u32 mask, old, new;
+        volatile __u32 *m;
+        CMPXCHG_BUGCHECK_DECL
+
+        m = (volatile __u32 *) addr + (nr >> 5);
+        mask = ~(1 << (nr & 31));
+        do {
+                CMPXCHG_BUGCHECK(m);
+                old = *m;
+                new = old & mask;
+        } while (cmpxchg_rel(m, old, new) != old);
+}
+
+/**
+ * __clear_bit_unlock - Non-atomically clears a bit in memory with release
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * Similarly to clear_bit_unlock, the implementation uses a store
+ * with release semantics. See also __raw_spin_unlock().
+ */
+static __inline__ void
+__clear_bit_unlock(int nr, void *addr)
+{
+        __u32 * const m = (__u32 *) addr + (nr >> 5);
+        __u32 const new = *m & ~(1 << (nr & 31));
+
+        ia64_st4_rel_nta(m, new);
+}
+
+/**
+ * __clear_bit - Clears a bit in memory (non-atomic version)
+ * @nr: the bit to clear
+ * @addr: the address to start counting from
+ *
+ * Unlike clear_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void
+__clear_bit (int nr, volatile void *addr)
+{
+        *((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31));
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to toggle
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void
+change_bit (int nr, volatile void *addr)
+{
+        __u32 bit, old, new;
+        volatile __u32 *m;
+        CMPXCHG_BUGCHECK_DECL
+
+        m = (volatile __u32 *) addr + (nr >> 5);
+        bit = (1 << (nr & 31));
+        do {
+                CMPXCHG_BUGCHECK(m);
+                old = *m;
+                new = old ^ bit;
+        } while (cmpxchg_acq(m, old, new) != old);
+}
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to toggle
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void
+__change_bit (int nr, volatile void *addr)
+{
+        *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
+}
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.  
+ * It also implies the acquisition side of the memory barrier.
+ */
+static __inline__ int
+test_and_set_bit (int nr, volatile void *addr)
+{
+        __u32 bit, old, new;
+        volatile __u32 *m;
+        CMPXCHG_BUGCHECK_DECL
+
+        m = (volatile __u32 *) addr + (nr >> 5);
+        bit = 1 << (nr & 31);
+        do {
+                CMPXCHG_BUGCHECK(m);
+                old = *m;
+                new = old | bit;
+        } while (cmpxchg_acq(m, old, new) != old);
+        return (old & bit) != 0;
+}
+
+/**
+ * test_and_set_bit_lock - Set a bit and return its old value for lock
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This is the same as test_and_set_bit on ia64
+ */
+#define test_and_set_bit_lock test_and_set_bit
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.  
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int
+__test_and_set_bit (int nr, volatile void *addr)
+{
+        __u32 *p = (__u32 *) addr + (nr >> 5);
+        __u32 m = 1 << (nr & 31);
+        int oldbitset = (*p & m) != 0;
+
+        *p |= m;
+        return oldbitset;
+}
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.  
+ * It also implies the acquisition side of the memory barrier.
+ */
+static __inline__ int
+test_and_clear_bit (int nr, volatile void *addr)
+{
+        __u32 mask, old, new;
+        volatile __u32 *m;
+        CMPXCHG_BUGCHECK_DECL
+
+        m = (volatile __u32 *) addr + (nr >> 5);
+        mask = ~(1 << (nr & 31));
+        do {
+                CMPXCHG_BUGCHECK(m);
+                old = *m;
+                new = old & mask;
+        } while (cmpxchg_acq(m, old, new) != old);
+        return (old & ~mask) != 0;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.  
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int
+__test_and_clear_bit(int nr, volatile void * addr)
+{
+        __u32 *p = (__u32 *) addr + (nr >> 5);
+        __u32 m = 1 << (nr & 31);
+        int oldbitset = *p & m;
+
+        *p &= ~m;
+        return oldbitset;
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.  
+ * It also implies the acquisition side of the memory barrier.
+ */
+static __inline__ int
+test_and_change_bit (int nr, volatile void *addr)
+{
+        __u32 bit, old, new;
+        volatile __u32 *m;
+        CMPXCHG_BUGCHECK_DECL
+
+        m = (volatile __u32 *) addr + (nr >> 5);
+        bit = (1 << (nr & 31));
+        do {
+                CMPXCHG_BUGCHECK(m);
+                old = *m;
+                new = old ^ bit;
+        } while (cmpxchg_acq(m, old, new) != old);
+        return (old & bit) != 0;
+}
+
+/**
+ * __test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ */
+static __inline__ int
+__test_and_change_bit (int nr, void *addr)
+{
+        __u32 old, bit = (1 << (nr & 31));
+        __u32 *m = (__u32 *) addr + (nr >> 5);
+
+        old = *m;
+        *m = old ^ bit;
+        return (old & bit) != 0;
+}
+
+static __inline__ int
+test_bit (int nr, const volatile void *addr)
+{
+        return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
+}
+
+/**
+ * ffz - find the first zero bit in a long word
+ * @x: The long word to find the bit in
+ *
+ * Returns the bit-number (0..63) of the first (least significant) zero bit.
+ * Undefined if no zero exists, so code should check against ~0UL first...
+ */
+static inline unsigned long
+ffz (unsigned long x)
+{
+        unsigned long result;
+
+        result = ia64_popcnt(x & (~x - 1));
+        return result;
+}
+
+/**
+ * __ffs - find first bit in word.
+ * @x: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __inline__ unsigned long
+__ffs (unsigned long x)
+{
+        unsigned long result;
+
+        result = ia64_popcnt((x-1) & ~x);
+        return result;
+}
+
+#ifdef __KERNEL__
+
+/*
+ * Return bit number of last (most-significant) bit set.  Undefined
+ * for x==0.  Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
+ */
+static inline unsigned long
+ia64_fls (unsigned long x)
+{
+        long double d = x;
+        long exp;
+
+        exp = ia64_getf_exp(d);
+        return exp - 0xffff;
+}
+
+/*
+ * Find the last (most significant) bit set.  Returns 0 for x==0 and
+ * bits are numbered from 1..32 (e.g., fls(9) == 4).
+ */
+static inline int
+fls (int t)
+{
+        unsigned long x = t & 0xffffffffu;
+
+        if (!x)
+                return 0;
+        x |= x >> 1;
+        x |= x >> 2;
+        x |= x >> 4;
+        x |= x >> 8;
+        x |= x >> 16;
+        return ia64_popcnt(x);
+}
+
+/*
+ * Find the last (most significant) bit set.  Undefined for x==0.
+ * Bits are numbered from 0..63 (e.g., __fls(9) == 3).
+ */
+static inline unsigned long
+__fls (unsigned long x)
+{
+        x |= x >> 1;
+        x |= x >> 2;
+        x |= x >> 4;
+        x |= x >> 8;
+        x |= x >> 16;
+        x |= x >> 32;
+        return ia64_popcnt(x) - 1;
+}
+
+#include <asm-generic/bitops/fls64.h>
+
+/*
+ * ffs: find first bit set. This is defined the same way as the libc and
+ * compiler builtin ffs routines, therefore differs in spirit from the above
+ * ffz (man ffs): it operates on "int" values only and the result value is the
+ * bit number + 1.  ffs(0) is defined to return zero.
+ */
+#define ffs(x)  __builtin_ffs(x)
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+static __inline__ unsigned long
+hweight64 (unsigned long x)
+{
+        unsigned long result;
+        result = ia64_popcnt(x);
+        return result;
+}
+
+#define hweight32(x)    (unsigned int) hweight64((x) & 0xfffffffful)
+#define hweight16(x)    (unsigned int) hweight64((x) & 0xfffful)
+#define hweight8(x)     (unsigned int) hweight64((x) & 0xfful)
+
+#endif /* __KERNEL__ */
+
+#include <asm-generic/bitops/find.h>
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/ext2-non-atomic.h>
+
+#define ext2_set_bit_atomic(l,n,a)      test_and_set_bit(n,a)
+#define ext2_clear_bit_atomic(l,n,a)    test_and_clear_bit(n,a)
+
+#include <asm-generic/bitops/minix.h>
+#include <asm-generic/bitops/sched.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_BITOPS_H */
diff --git a/arch/ia64/include/asm/break.h b/arch/ia64/include/asm/break.h
new file mode 100644
index 000000000000..f03402039896
--- /dev/null
+++ b/arch/ia64/include/asm/break.h
@@ -0,0 +1,23 @@
+#ifndef _ASM_IA64_BREAK_H
+#define _ASM_IA64_BREAK_H
+
+/*
+ * IA-64 Linux break numbers.
+ *
+ * Copyright (C) 1999 Hewlett-Packard Co
+ * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+/*
+ * OS-specific debug break numbers:
+ */
+#define __IA64_BREAK_KDB                0x80100
+#define __IA64_BREAK_KPROBE             0x81000 /* .. 0x81fff */
+#define __IA64_BREAK_JPROBE             0x82000
+
+/*
+ * OS-specific break numbers:
+ */
+#define __IA64_BREAK_SYSCALL            0x100000
+
+#endif /* _ASM_IA64_BREAK_H */
diff --git a/arch/ia64/include/asm/bug.h b/arch/ia64/include/asm/bug.h
new file mode 100644
index 000000000000..823616b5020b
--- /dev/null
+++ b/arch/ia64/include/asm/bug.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_IA64_BUG_H
+#define _ASM_IA64_BUG_H
+
+#ifdef CONFIG_BUG
+#define ia64_abort()    __builtin_trap()
+#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); ia64_abort(); } while (0)
+
+/* should this BUG be made generic? */
+#define HAVE_ARCH_BUG
+#endif
+
+#include <asm-generic/bug.h>
+
+#endif
diff --git a/arch/ia64/include/asm/bugs.h b/arch/ia64/include/asm/bugs.h
new file mode 100644
index 000000000000..433523e3b2ed
--- /dev/null
+++ b/arch/ia64/include/asm/bugs.h
@@ -0,0 +1,19 @@
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ *      void check_bugs(void);
+ *
+ * Based on <asm-alpha/bugs.h>.
+ *
+ * Modified 1998, 1999, 2003
+ *      David Mosberger-Tang <davidm@hpl.hp.com>,  Hewlett-Packard Co.
+ */
+#ifndef _ASM_IA64_BUGS_H
+#define _ASM_IA64_BUGS_H
+
+#include <asm/processor.h>
+
+extern void check_bugs (void);
+
+#endif /* _ASM_IA64_BUGS_H */
diff --git a/arch/ia64/include/asm/byteorder.h b/arch/ia64/include/asm/byteorder.h
new file mode 100644
index 000000000000..69bd41d7c26e
--- /dev/null
+++ b/arch/ia64/include/asm/byteorder.h
@@ -0,0 +1,42 @@
+#ifndef _ASM_IA64_BYTEORDER_H
+#define _ASM_IA64_BYTEORDER_H
+
+/*
+ * Modified 1998, 1999
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
+ */
+
+#include <asm/types.h>
+#include <asm/intrinsics.h>
+#include <linux/compiler.h>
+
+static __inline__ __attribute_const__ __u64
+__ia64_swab64 (__u64 x)
+{
+        __u64 result;
+
+        result = ia64_mux1(x, ia64_mux1_rev);
+        return result;
+}
+
+static __inline__ __attribute_const__ __u32
+__ia64_swab32 (__u32 x)
+{
+        return __ia64_swab64(x) >> 32;
+}
+
+static __inline__ __attribute_const__ __u16
+__ia64_swab16(__u16 x)
+{
+        return __ia64_swab64(x) >> 48;
+}
+
+#define __arch__swab64(x) __ia64_swab64(x)
+#define __arch__swab32(x) __ia64_swab32(x)
+#define __arch__swab16(x) __ia64_swab16(x)
+
+#define __BYTEORDER_HAS_U64__
+
+#include <linux/byteorder/little_endian.h>
+
+#endif /* _ASM_IA64_BYTEORDER_H */
diff --git a/arch/ia64/include/asm/cache.h b/arch/ia64/include/asm/cache.h
new file mode 100644
index 000000000000..e7482bd628ff
--- /dev/null
+++ b/arch/ia64/include/asm/cache.h
@@ -0,0 +1,29 @@
+#ifndef _ASM_IA64_CACHE_H
+#define _ASM_IA64_CACHE_H
+
+
+/*
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+/* Bytes per L1 (data) cache line.  */
+#define L1_CACHE_SHIFT          CONFIG_IA64_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#ifdef CONFIG_SMP
+# define SMP_CACHE_SHIFT        L1_CACHE_SHIFT
+# define SMP_CACHE_BYTES        L1_CACHE_BYTES
+#else
+  /*
+   * The "aligned" directive can only _increase_ alignment, so this is
+   * safe and provides an easy way to avoid wasting space on a
+   * uni-processor:
+   */
+# define SMP_CACHE_SHIFT        3
+# define SMP_CACHE_BYTES        (1 << 3)
+#endif
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+#endif /* _ASM_IA64_CACHE_H */
diff --git a/arch/ia64/include/asm/cacheflush.h b/arch/ia64/include/asm/cacheflush.h
new file mode 100644
index 000000000000..afcfbda76e20
--- /dev/null
+++ b/arch/ia64/include/asm/cacheflush.h
@@ -0,0 +1,51 @@
+#ifndef _ASM_IA64_CACHEFLUSH_H
+#define _ASM_IA64_CACHEFLUSH_H
+
+/*
+ * Copyright (C) 2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <linux/page-flags.h>
+#include <linux/bitops.h>
+
+#include <asm/page.h>
+
+/*
+ * Cache flushing routines.  This is the kind of stuff that can be very expensive, so try
+ * to avoid them whenever possible.
+ */
+
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_icache_page(vma,page)             do { } while (0)
+#define flush_cache_vmap(start, end)            do { } while (0)
+#define flush_cache_vunmap(start, end)          do { } while (0)
+
+#define flush_dcache_page(page)                 \
+do {                                            \
+        clear_bit(PG_arch_1, &(page)->flags);   \
+} while (0)
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+extern void flush_icache_range (unsigned long start, unsigned long end);
+
+#define flush_icache_user_range(vma, page, user_addr, len)                                      \
+do {                                                                                            \
+        unsigned long _addr = (unsigned long) page_address(page) + ((user_addr) & ~PAGE_MASK);  \
+        flush_icache_range(_addr, _addr + (len));                                               \
+} while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do { memcpy(dst, src, len); \
+     flush_icache_user_range(vma, page, vaddr, len); \
+} while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+
+#endif /* _ASM_IA64_CACHEFLUSH_H */
diff --git a/arch/ia64/include/asm/checksum.h b/arch/ia64/include/asm/checksum.h
new file mode 100644
index 000000000000..97af155057e4
--- /dev/null
+++ b/arch/ia64/include/asm/checksum.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_IA64_CHECKSUM_H
+#define _ASM_IA64_CHECKSUM_H
+
+/*
+ * Modified 1998, 1999
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+/*
+ * This is a version of ip_compute_csum() optimized for IP headers,
+ * which always checksum on 4 octet boundaries.
+ */
+extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+
+/*
+ * Computes the checksum of the TCP/UDP pseudo-header returns a 16-bit
+ * checksum, already complemented
+ */
+extern __sum16 csum_tcpudp_magic (__be32 saddr, __be32 daddr,
+                                             unsigned short len,
+                                             unsigned short proto,
+                                             __wsum sum);
+
+extern __wsum csum_tcpudp_nofold (__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        __wsum sum);
+
+/*
+ * Computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+extern __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ * Same as csum_partial, but copies from src while it checksums.
+ *
+ * Here it is even more important to align src and dst on a 32-bit (or
+ * even better 64-bit) boundary.
+ */
+extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
+                                                 int len, __wsum sum,
+                                                 int *errp);
+
+extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
+                                               int len, __wsum sum);
+
+/*
+ * This routine is used for miscellaneous IP-like checksums, mainly in
+ * icmp.c
+ */
+extern __sum16 ip_compute_csum(const void *buff, int len);
+
+/*
+ * Fold a partial checksum without adding pseudo headers.
+ */
+static inline __sum16 csum_fold(__wsum csum)
+{
+        u32 sum = (__force u32)csum;
+        sum = (sum & 0xffff) + (sum >> 16);
+        sum = (sum & 0xffff) + (sum >> 16);
+        return (__force __sum16)~sum;
+}
+
+#define _HAVE_ARCH_IPV6_CSUM    1
+struct in6_addr;
+extern __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+        const struct in6_addr *daddr, __u32 len, unsigned short proto,
+        __wsum csum);
+
+#endif /* _ASM_IA64_CHECKSUM_H */
diff --git a/arch/ia64/include/asm/compat.h b/arch/ia64/include/asm/compat.h
new file mode 100644
index 000000000000..dfcf75b8426d
--- /dev/null
+++ b/arch/ia64/include/asm/compat.h
@@ -0,0 +1,207 @@
+#ifndef _ASM_IA64_COMPAT_H
+#define _ASM_IA64_COMPAT_H
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+
+#define COMPAT_USER_HZ  100
+
+typedef u32             compat_size_t;
+typedef s32             compat_ssize_t;
+typedef s32             compat_time_t;
+typedef s32             compat_clock_t;
+typedef s32             compat_key_t;
+typedef s32             compat_pid_t;
+typedef u16             __compat_uid_t;
+typedef u16             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
+typedef u16             compat_mode_t;
+typedef u32             compat_ino_t;
+typedef u16             compat_dev_t;
+typedef s32             compat_off_t;
+typedef s64             compat_loff_t;
+typedef u16             compat_nlink_t;
+typedef u16             compat_ipc_pid_t;
+typedef s32             compat_daddr_t;
+typedef u32             compat_caddr_t;
+typedef __kernel_fsid_t compat_fsid_t;
+typedef s32             compat_timer_t;
+
+typedef s32             compat_int_t;
+typedef s32             compat_long_t;
+typedef s64 __attribute__((aligned(4))) compat_s64;
+typedef u32             compat_uint_t;
+typedef u32             compat_ulong_t;
+typedef u64 __attribute__((aligned(4))) compat_u64;
+
+struct compat_timespec {
+        compat_time_t   tv_sec;
+        s32             tv_nsec;
+};
+
+struct compat_timeval {
+        compat_time_t   tv_sec;
+        s32             tv_usec;
+};
+
+struct compat_stat {
+        compat_dev_t    st_dev;
+        u16             __pad1;
+        compat_ino_t    st_ino;
+        compat_mode_t   st_mode;
+        compat_nlink_t  st_nlink;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
+        compat_dev_t    st_rdev;
+        u16             __pad2;
+        u32             st_size;
+        u32             st_blksize;
+        u32             st_blocks;
+        u32             st_atime;
+        u32             st_atime_nsec;
+        u32             st_mtime;
+        u32             st_mtime_nsec;
+        u32             st_ctime;
+        u32             st_ctime_nsec;
+        u32             __unused4;
+        u32             __unused5;
+};
+
+struct compat_flock {
+        short           l_type;
+        short           l_whence;
+        compat_off_t    l_start;
+        compat_off_t    l_len;
+        compat_pid_t    l_pid;
+};
+
+#define F_GETLK64       12
+#define F_SETLK64       13
+#define F_SETLKW64      14
+
+/*
+ * IA32 uses 4 byte alignment for 64 bit quantities,
+ * so we need to pack this structure.
+ */
+struct compat_flock64 {
+        short           l_type;
+        short           l_whence;
+        compat_loff_t   l_start;
+        compat_loff_t   l_len;
+        compat_pid_t    l_pid;
+} __attribute__((packed));
+
+struct compat_statfs {
+        int             f_type;
+        int             f_bsize;
+        int             f_blocks;
+        int             f_bfree;
+        int             f_bavail;
+        int             f_files;
+        int             f_ffree;
+        compat_fsid_t   f_fsid;
+        int             f_namelen;      /* SunOS ignores this field. */
+        int             f_frsize;
+        int             f_spare[5];
+};
+
+#define COMPAT_RLIM_OLD_INFINITY       0x7fffffff
+#define COMPAT_RLIM_INFINITY           0xffffffff
+
+typedef u32             compat_old_sigset_t;    /* at least 32 bits */
+
+#define _COMPAT_NSIG            64
+#define _COMPAT_NSIG_BPW        32
+
+typedef u32             compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX        0x7fffffff
+#define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
+
+struct compat_ipc64_perm {
+        compat_key_t key;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
+        unsigned short mode;
+        unsigned short __pad1;
+        unsigned short seq;
+        unsigned short __pad2;
+        compat_ulong_t unused1;
+        compat_ulong_t unused2;
+};
+
+struct compat_semid64_ds {
+        struct compat_ipc64_perm sem_perm;
+        compat_time_t  sem_otime;
+        compat_ulong_t __unused1;
+        compat_time_t  sem_ctime;
+        compat_ulong_t __unused2;
+        compat_ulong_t sem_nsems;
+        compat_ulong_t __unused3;
+        compat_ulong_t __unused4;
+};
+
+struct compat_msqid64_ds {
+        struct compat_ipc64_perm msg_perm;
+        compat_time_t  msg_stime;
+        compat_ulong_t __unused1;
+        compat_time_t  msg_rtime;
+        compat_ulong_t __unused2;
+        compat_time_t  msg_ctime;
+        compat_ulong_t __unused3;
+        compat_ulong_t msg_cbytes;
+        compat_ulong_t msg_qnum;
+        compat_ulong_t msg_qbytes;
+        compat_pid_t   msg_lspid;
+        compat_pid_t   msg_lrpid;
+        compat_ulong_t __unused4;
+        compat_ulong_t __unused5;
+};
+
+struct compat_shmid64_ds {
+        struct compat_ipc64_perm shm_perm;
+        compat_size_t  shm_segsz;
+        compat_time_t  shm_atime;
+        compat_ulong_t __unused1;
+        compat_time_t  shm_dtime;
+        compat_ulong_t __unused2;
+        compat_time_t  shm_ctime;
+        compat_ulong_t __unused3;
+        compat_pid_t   shm_cpid;
+        compat_pid_t   shm_lpid;
+        compat_ulong_t shm_nattch;
+        compat_ulong_t __unused4;
+        compat_ulong_t __unused5;
+};
+
+/*
+ * A pointer passed in from user mode. This should not be used for syscall parameters,
+ * just declare them as pointers because the syscall entry code will have appropriately
+ * converted them already.
+ */
+typedef u32             compat_uptr_t;
+
+static inline void __user *
+compat_ptr (compat_uptr_t uptr)
+{
+        return (void __user *) (unsigned long) uptr;
+}
+
+static inline compat_uptr_t
+ptr_to_compat(void __user *uptr)
+{
+        return (u32)(unsigned long)uptr;
+}
+
+static __inline__ void __user *
+compat_alloc_user_space (long len)
+{
+        struct pt_regs *regs = task_pt_regs(current);
+        return (void __user *) (((regs->r12 & 0xffffffff) & -16) - len);
+}
+
+#endif /* _ASM_IA64_COMPAT_H */
diff --git a/arch/ia64/include/asm/cpu.h b/arch/ia64/include/asm/cpu.h
new file mode 100644
index 000000000000..fcca30b9f110
--- /dev/null
+++ b/arch/ia64/include/asm/cpu.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_IA64_CPU_H_
+#define _ASM_IA64_CPU_H_
+
+#include <linux/device.h>
+#include <linux/cpu.h>
+#include <linux/topology.h>
+#include <linux/percpu.h>
+
+struct ia64_cpu {
+        struct cpu cpu;
+};
+
+DECLARE_PER_CPU(struct ia64_cpu, cpu_devices);
+
+DECLARE_PER_CPU(int, cpu_state);
+
+#ifdef CONFIG_HOTPLUG_CPU
+extern int arch_register_cpu(int num);
+extern void arch_unregister_cpu(int);
+#endif
+
+#endif /* _ASM_IA64_CPU_H_ */
diff --git a/arch/ia64/include/asm/cputime.h b/arch/ia64/include/asm/cputime.h
new file mode 100644
index 000000000000..d20b998cb91d
--- /dev/null
+++ b/arch/ia64/include/asm/cputime.h
@@ -0,0 +1,109 @@
+/*
+ * Definitions for measuring cputime on ia64 machines.
+ *
+ * Based on <asm-powerpc/cputime.h>.
+ *
+ * Copyright (C) 2007 FUJITSU LIMITED
+ * Copyright (C) 2007 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in nsec.
+ * Otherwise we measure cpu time in jiffies using the generic definitions.
+ */
+
+#ifndef __IA64_CPUTIME_H
+#define __IA64_CPUTIME_H
+
+#ifndef CONFIG_VIRT_CPU_ACCOUNTING
+#include <asm-generic/cputime.h>
+#else
+
+#include <linux/time.h>
+#include <linux/jiffies.h>
+#include <asm/processor.h>
+
+typedef u64 cputime_t;
+typedef u64 cputime64_t;
+
+#define cputime_zero                    ((cputime_t)0)
+#define cputime_max                     ((~((cputime_t)0) >> 1) - 1)
+#define cputime_add(__a, __b)           ((__a) +  (__b))
+#define cputime_sub(__a, __b)           ((__a) -  (__b))
+#define cputime_div(__a, __n)           ((__a) /  (__n))
+#define cputime_halve(__a)              ((__a) >> 1)
+#define cputime_eq(__a, __b)            ((__a) == (__b))
+#define cputime_gt(__a, __b)            ((__a) >  (__b))
+#define cputime_ge(__a, __b)            ((__a) >= (__b))
+#define cputime_lt(__a, __b)            ((__a) <  (__b))
+#define cputime_le(__a, __b)            ((__a) <= (__b))
+
+#define cputime64_zero                  ((cputime64_t)0)
+#define cputime64_add(__a, __b)         ((__a) + (__b))
+#define cputime64_sub(__a, __b)         ((__a) - (__b))
+#define cputime_to_cputime64(__ct)      (__ct)
+
+/*
+ * Convert cputime <-> jiffies (HZ)
+ */
+#define cputime_to_jiffies(__ct)        ((__ct) / (NSEC_PER_SEC / HZ))
+#define jiffies_to_cputime(__jif)       ((__jif) * (NSEC_PER_SEC / HZ))
+#define cputime64_to_jiffies64(__ct)    ((__ct) / (NSEC_PER_SEC / HZ))
+#define jiffies64_to_cputime64(__jif)   ((__jif) * (NSEC_PER_SEC / HZ))
+
+/*
+ * Convert cputime <-> milliseconds
+ */
+#define cputime_to_msecs(__ct)          ((__ct) / NSEC_PER_MSEC)
+#define msecs_to_cputime(__msecs)       ((__msecs) * NSEC_PER_MSEC)
+
+/*
+ * Convert cputime <-> seconds
+ */
+#define cputime_to_secs(__ct)           ((__ct) / NSEC_PER_SEC)
+#define secs_to_cputime(__secs)         ((__secs) * NSEC_PER_SEC)
+
+/*
+ * Convert cputime <-> timespec (nsec)
+ */
+static inline cputime_t timespec_to_cputime(const struct timespec *val)
+{
+        cputime_t ret = val->tv_sec * NSEC_PER_SEC;
+        return (ret + val->tv_nsec);
+}
+static inline void cputime_to_timespec(const cputime_t ct, struct timespec *val)
+{
+        val->tv_sec  = ct / NSEC_PER_SEC;
+        val->tv_nsec = ct % NSEC_PER_SEC;
+}
+
+/*
+ * Convert cputime <-> timeval (msec)
+ */
+static inline cputime_t timeval_to_cputime(struct timeval *val)
+{
+        cputime_t ret = val->tv_sec * NSEC_PER_SEC;
+        return (ret + val->tv_usec * NSEC_PER_USEC);
+}
+static inline void cputime_to_timeval(const cputime_t ct, struct timeval *val)
+{
+        val->tv_sec = ct / NSEC_PER_SEC;
+        val->tv_usec = (ct % NSEC_PER_SEC) / NSEC_PER_USEC;
+}
+
+/*
+ * Convert cputime <-> clock (USER_HZ)
+ */
+#define cputime_to_clock_t(__ct)        ((__ct) / (NSEC_PER_SEC / USER_HZ))
+#define clock_t_to_cputime(__x)         ((__x) * (NSEC_PER_SEC / USER_HZ))
+
+/*
+ * Convert cputime64 to clock.
+ */
+#define cputime64_to_clock_t(__ct)      cputime_to_clock_t((cputime_t)__ct)
+
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* __IA64_CPUTIME_H */
diff --git a/arch/ia64/include/asm/current.h b/arch/ia64/include/asm/current.h
new file mode 100644
index 000000000000..c659f90fbfd9
--- /dev/null
+++ b/arch/ia64/include/asm/current.h
@@ -0,0 +1,17 @@
+#ifndef _ASM_IA64_CURRENT_H
+#define _ASM_IA64_CURRENT_H
+
+/*
+ * Modified 1998-2000
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#include <asm/intrinsics.h>
+
+/*
+ * In kernel mode, thread pointer (r13) is used to point to the current task
+ * structure.
+ */
+#define current ((struct task_struct *) ia64_getreg(_IA64_REG_TP))
+
+#endif /* _ASM_IA64_CURRENT_H */
diff --git a/arch/ia64/include/asm/cyclone.h b/arch/ia64/include/asm/cyclone.h
new file mode 100644
index 000000000000..88f6500e84ab
--- /dev/null
+++ b/arch/ia64/include/asm/cyclone.h
@@ -0,0 +1,15 @@
+#ifndef ASM_IA64_CYCLONE_H
+#define ASM_IA64_CYCLONE_H
+
+#ifdef  CONFIG_IA64_CYCLONE
+extern int use_cyclone;
+extern void __init cyclone_setup(void);
+#else   /* CONFIG_IA64_CYCLONE */
+#define use_cyclone 0
+static inline void cyclone_setup(void)
+{
+        printk(KERN_ERR "Cyclone Counter: System not configured"
+                                        " w/ CONFIG_IA64_CYCLONE.\n");
+}
+#endif  /* CONFIG_IA64_CYCLONE */
+#endif  /* !ASM_IA64_CYCLONE_H */
diff --git a/arch/ia64/include/asm/delay.h b/arch/ia64/include/asm/delay.h
new file mode 100644
index 000000000000..a30a62f235e1
--- /dev/null
+++ b/arch/ia64/include/asm/delay.h
@@ -0,0 +1,88 @@
+#ifndef _ASM_IA64_DELAY_H
+#define _ASM_IA64_DELAY_H
+
+/*
+ * Delay routines using a pre-computed "cycles/usec" value.
+ *
+ * Copyright (C) 1998, 1999 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999 VA Linux Systems
+ * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
+ * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/compiler.h>
+
+#include <asm/intrinsics.h>
+#include <asm/processor.h>
+
+static __inline__ void
+ia64_set_itm (unsigned long val)
+{
+        ia64_setreg(_IA64_REG_CR_ITM, val);
+        ia64_srlz_d();
+}
+
+static __inline__ unsigned long
+ia64_get_itm (void)
+{
+        unsigned long result;
+
+        result = ia64_getreg(_IA64_REG_CR_ITM);
+        ia64_srlz_d();
+        return result;
+}
+
+static __inline__ void
+ia64_set_itv (unsigned long val)
+{
+        ia64_setreg(_IA64_REG_CR_ITV, val);
+        ia64_srlz_d();
+}
+
+static __inline__ unsigned long
+ia64_get_itv (void)
+{
+        return ia64_getreg(_IA64_REG_CR_ITV);
+}
+
+static __inline__ void
+ia64_set_itc (unsigned long val)
+{
+        ia64_setreg(_IA64_REG_AR_ITC, val);
+        ia64_srlz_d();
+}
+
+static __inline__ unsigned long
+ia64_get_itc (void)
+{
+        unsigned long result;
+
+        result = ia64_getreg(_IA64_REG_AR_ITC);
+        ia64_barrier();
+#ifdef CONFIG_ITANIUM
+        while (unlikely((__s32) result == -1)) {
+                result = ia64_getreg(_IA64_REG_AR_ITC);
+                ia64_barrier();
+        }
+#endif
+        return result;
+}
+
+extern void ia64_delay_loop (unsigned long loops);
+
+static __inline__ void
+__delay (unsigned long loops)
+{
+        if (unlikely(loops < 1))
+                return;
+
+        ia64_delay_loop (loops - 1);
+}
+
+extern void udelay (unsigned long usecs);
+
+#endif /* _ASM_IA64_DELAY_H */
diff --git a/arch/ia64/include/asm/device.h b/arch/ia64/include/asm/device.h
new file mode 100644
index 000000000000..3db6daf7f251
--- /dev/null
+++ b/arch/ia64/include/asm/device.h
@@ -0,0 +1,15 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#ifndef _ASM_IA64_DEVICE_H
+#define _ASM_IA64_DEVICE_H
+
+struct dev_archdata {
+#ifdef CONFIG_ACPI
+        void    *acpi_handle;
+#endif
+};
+
+#endif /* _ASM_IA64_DEVICE_H */
diff --git a/arch/ia64/include/asm/div64.h b/arch/ia64/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/ia64/include/asm/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..9f0df9bd46b7
--- /dev/null
+++ b/arch/ia64/include/asm/dma-mapping.h
@@ -0,0 +1,97 @@
+#ifndef _ASM_IA64_DMA_MAPPING_H
+#define _ASM_IA64_DMA_MAPPING_H
+
+/*
+ * Copyright (C) 2003-2004 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#include <asm/machvec.h>
+#include <linux/scatterlist.h>
+
+#define dma_alloc_coherent      platform_dma_alloc_coherent
+/* coherent mem. is cheap */
+static inline void *
+dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
+                      gfp_t flag)
+{
+        return dma_alloc_coherent(dev, size, dma_handle, flag);
+}
+#define dma_free_coherent       platform_dma_free_coherent
+static inline void
+dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
+                     dma_addr_t dma_handle)
+{
+        dma_free_coherent(dev, size, cpu_addr, dma_handle);
+}
+#define dma_map_single_attrs    platform_dma_map_single_attrs
+static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                                        size_t size, int dir)
+{
+        return dma_map_single_attrs(dev, cpu_addr, size, dir, NULL);
+}
+#define dma_map_sg_attrs        platform_dma_map_sg_attrs
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sgl,
+                             int nents, int dir)
+{
+        return dma_map_sg_attrs(dev, sgl, nents, dir, NULL);
+}
+#define dma_unmap_single_attrs  platform_dma_unmap_single_attrs
+static inline void dma_unmap_single(struct device *dev, dma_addr_t cpu_addr,
+                                    size_t size, int dir)
+{
+        return dma_unmap_single_attrs(dev, cpu_addr, size, dir, NULL);
+}
+#define dma_unmap_sg_attrs      platform_dma_unmap_sg_attrs
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
+                                int nents, int dir)
+{
+        return dma_unmap_sg_attrs(dev, sgl, nents, dir, NULL);
+}
+#define dma_sync_single_for_cpu platform_dma_sync_single_for_cpu
+#define dma_sync_sg_for_cpu     platform_dma_sync_sg_for_cpu
+#define dma_sync_single_for_device platform_dma_sync_single_for_device
+#define dma_sync_sg_for_device  platform_dma_sync_sg_for_device
+#define dma_mapping_error       platform_dma_mapping_error
+
+#define dma_map_page(dev, pg, off, size, dir)                           \
+        dma_map_single(dev, page_address(pg) + (off), (size), (dir))
+#define dma_unmap_page(dev, dma_addr, size, dir)                        \
+        dma_unmap_single(dev, dma_addr, size, dir)
+
+/*
+ * Rest of this file is part of the "Advanced DMA API".  Use at your own risk.
+ * See Documentation/DMA-API.txt for details.
+ */
+
+#define dma_sync_single_range_for_cpu(dev, dma_handle, offset, size, dir)       \
+        dma_sync_single_for_cpu(dev, dma_handle, size, dir)
+#define dma_sync_single_range_for_device(dev, dma_handle, offset, size, dir)    \
+        dma_sync_single_for_device(dev, dma_handle, size, dir)
+
+#define dma_supported           platform_dma_supported
+
+static inline int
+dma_set_mask (struct device *dev, u64 mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+        *dev->dma_mask = mask;
+        return 0;
+}
+
+extern int dma_get_cache_alignment(void);
+
+static inline void
+dma_cache_sync (struct device *dev, void *vaddr, size_t size,
+        enum dma_data_direction dir)
+{
+        /*
+         * IA-64 is cache-coherent, so this is mostly a no-op.  However, we do need to
+         * ensure that dma_cache_sync() enforces order, hence the mb().
+         */
+        mb();
+}
+
+#define dma_is_consistent(d, h) (1)     /* all we do is coherent memory... */
+
+#endif /* _ASM_IA64_DMA_MAPPING_H */
diff --git a/arch/ia64/include/asm/dma.h b/arch/ia64/include/asm/dma.h
new file mode 100644
index 000000000000..4d97f60f1ef5
--- /dev/null
+++ b/arch/ia64/include/asm/dma.h
@@ -0,0 +1,24 @@
+#ifndef _ASM_IA64_DMA_H
+#define _ASM_IA64_DMA_H
+
+/*
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+
+#include <asm/io.h>             /* need byte IO */
+
+extern unsigned long MAX_DMA_ADDRESS;
+
+#ifdef CONFIG_PCI
+  extern int isa_dma_bridge_buggy;
+#else
+# define isa_dma_bridge_buggy   (0)
+#endif
+
+#define free_dma(x)
+
+void dma_mark_clean(void *addr, size_t size);
+
+#endif /* _ASM_IA64_DMA_H */
diff --git a/arch/ia64/include/asm/dmi.h b/arch/ia64/include/asm/dmi.h
new file mode 100644
index 000000000000..00eb1b130b63
--- /dev/null
+++ b/arch/ia64/include/asm/dmi.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_DMI_H
+#define _ASM_DMI_H 1
+
+#include <asm/io.h>
+
+/* Use normal IO mappings for DMI */
+#define dmi_ioremap ioremap
+#define dmi_iounmap(x,l) iounmap(x)
+#define dmi_alloc(l) kmalloc(l, GFP_ATOMIC)
+
+#endif
diff --git a/arch/ia64/include/asm/elf.h b/arch/ia64/include/asm/elf.h
new file mode 100644
index 000000000000..5e0c1a6bce8d
--- /dev/null
+++ b/arch/ia64/include/asm/elf.h
@@ -0,0 +1,269 @@
+#ifndef _ASM_IA64_ELF_H
+#define _ASM_IA64_ELF_H
+
+/*
+ * ELF-specific definitions.
+ *
+ * Copyright (C) 1998-1999, 2002-2004 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+
+#include <asm/fpu.h>
+#include <asm/page.h>
+#include <asm/auxvec.h>
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_IA_64)
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS64
+#define ELF_DATA        ELFDATA2LSB
+#define ELF_ARCH        EM_IA_64
+
+#define USE_ELF_CORE_DUMP
+#define CORE_DUMP_USE_REGSET
+
+/* Least-significant four bits of ELF header's e_flags are OS-specific.  The bits are
+   interpreted as follows by Linux: */
+#define EF_IA_64_LINUX_EXECUTABLE_STACK 0x1     /* is stack (& heap) executable by default? */
+
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/*
+ * This is the location that an ET_DYN program is loaded if exec'ed.
+ * Typical use of this is to invoke "./ld.so someprog" to test out a
+ * new version of the loader.  We need to make sure that it is out of
+ * the way of the program that it will "exec", and that there is
+ * sufficient room for the brk.
+ */
+#define ELF_ET_DYN_BASE         (TASK_UNMAPPED_BASE + 0x800000000UL)
+
+#define PT_IA_64_UNWIND         0x70000001
+
+/* IA-64 relocations: */
+#define R_IA64_NONE             0x00    /* none */
+#define R_IA64_IMM14            0x21    /* symbol + addend, add imm14 */
+#define R_IA64_IMM22            0x22    /* symbol + addend, add imm22 */
+#define R_IA64_IMM64            0x23    /* symbol + addend, mov imm64 */
+#define R_IA64_DIR32MSB         0x24    /* symbol + addend, data4 MSB */
+#define R_IA64_DIR32LSB         0x25    /* symbol + addend, data4 LSB */
+#define R_IA64_DIR64MSB         0x26    /* symbol + addend, data8 MSB */
+#define R_IA64_DIR64LSB         0x27    /* symbol + addend, data8 LSB */
+#define R_IA64_GPREL22          0x2a    /* @gprel(sym+add), add imm22 */
+#define R_IA64_GPREL64I         0x2b    /* @gprel(sym+add), mov imm64 */
+#define R_IA64_GPREL32MSB       0x2c    /* @gprel(sym+add), data4 MSB */
+#define R_IA64_GPREL32LSB       0x2d    /* @gprel(sym+add), data4 LSB */
+#define R_IA64_GPREL64MSB       0x2e    /* @gprel(sym+add), data8 MSB */
+#define R_IA64_GPREL64LSB       0x2f    /* @gprel(sym+add), data8 LSB */
+#define R_IA64_LTOFF22          0x32    /* @ltoff(sym+add), add imm22 */
+#define R_IA64_LTOFF64I         0x33    /* @ltoff(sym+add), mov imm64 */
+#define R_IA64_PLTOFF22         0x3a    /* @pltoff(sym+add), add imm22 */
+#define R_IA64_PLTOFF64I        0x3b    /* @pltoff(sym+add), mov imm64 */
+#define R_IA64_PLTOFF64MSB      0x3e    /* @pltoff(sym+add), data8 MSB */
+#define R_IA64_PLTOFF64LSB      0x3f    /* @pltoff(sym+add), data8 LSB */
+#define R_IA64_FPTR64I          0x43    /* @fptr(sym+add), mov imm64 */
+#define R_IA64_FPTR32MSB        0x44    /* @fptr(sym+add), data4 MSB */
+#define R_IA64_FPTR32LSB        0x45    /* @fptr(sym+add), data4 LSB */
+#define R_IA64_FPTR64MSB        0x46    /* @fptr(sym+add), data8 MSB */
+#define R_IA64_FPTR64LSB        0x47    /* @fptr(sym+add), data8 LSB */
+#define R_IA64_PCREL60B         0x48    /* @pcrel(sym+add), brl */
+#define R_IA64_PCREL21B         0x49    /* @pcrel(sym+add), ptb, call */
+#define R_IA64_PCREL21M         0x4a    /* @pcrel(sym+add), chk.s */
+#define R_IA64_PCREL21F         0x4b    /* @pcrel(sym+add), fchkf */
+#define R_IA64_PCREL32MSB       0x4c    /* @pcrel(sym+add), data4 MSB */
+#define R_IA64_PCREL32LSB       0x4d    /* @pcrel(sym+add), data4 LSB */
+#define R_IA64_PCREL64MSB       0x4e    /* @pcrel(sym+add), data8 MSB */
+#define R_IA64_PCREL64LSB       0x4f    /* @pcrel(sym+add), data8 LSB */
+#define R_IA64_LTOFF_FPTR22     0x52    /* @ltoff(@fptr(s+a)), imm22 */
+#define R_IA64_LTOFF_FPTR64I    0x53    /* @ltoff(@fptr(s+a)), imm64 */
+#define R_IA64_LTOFF_FPTR32MSB  0x54    /* @ltoff(@fptr(s+a)), 4 MSB */
+#define R_IA64_LTOFF_FPTR32LSB  0x55    /* @ltoff(@fptr(s+a)), 4 LSB */
+#define R_IA64_LTOFF_FPTR64MSB  0x56    /* @ltoff(@fptr(s+a)), 8 MSB */
+#define R_IA64_LTOFF_FPTR64LSB  0x57    /* @ltoff(@fptr(s+a)), 8 LSB */
+#define R_IA64_SEGREL32MSB      0x5c    /* @segrel(sym+add), data4 MSB */
+#define R_IA64_SEGREL32LSB      0x5d    /* @segrel(sym+add), data4 LSB */
+#define R_IA64_SEGREL64MSB      0x5e    /* @segrel(sym+add), data8 MSB */
+#define R_IA64_SEGREL64LSB      0x5f    /* @segrel(sym+add), data8 LSB */
+#define R_IA64_SECREL32MSB      0x64    /* @secrel(sym+add), data4 MSB */
+#define R_IA64_SECREL32LSB      0x65    /* @secrel(sym+add), data4 LSB */
+#define R_IA64_SECREL64MSB      0x66    /* @secrel(sym+add), data8 MSB */
+#define R_IA64_SECREL64LSB      0x67    /* @secrel(sym+add), data8 LSB */
+#define R_IA64_REL32MSB         0x6c    /* data 4 + REL */
+#define R_IA64_REL32LSB         0x6d    /* data 4 + REL */
+#define R_IA64_REL64MSB         0x6e    /* data 8 + REL */
+#define R_IA64_REL64LSB         0x6f    /* data 8 + REL */
+#define R_IA64_LTV32MSB         0x74    /* symbol + addend, data4 MSB */
+#define R_IA64_LTV32LSB         0x75    /* symbol + addend, data4 LSB */
+#define R_IA64_LTV64MSB         0x76    /* symbol + addend, data8 MSB */
+#define R_IA64_LTV64LSB         0x77    /* symbol + addend, data8 LSB */
+#define R_IA64_PCREL21BI        0x79    /* @pcrel(sym+add), ptb, call */
+#define R_IA64_PCREL22          0x7a    /* @pcrel(sym+add), imm22 */
+#define R_IA64_PCREL64I         0x7b    /* @pcrel(sym+add), imm64 */
+#define R_IA64_IPLTMSB          0x80    /* dynamic reloc, imported PLT, MSB */
+#define R_IA64_IPLTLSB          0x81    /* dynamic reloc, imported PLT, LSB */
+#define R_IA64_COPY             0x84    /* dynamic reloc, data copy */
+#define R_IA64_SUB              0x85    /* -symbol + addend, add imm22 */
+#define R_IA64_LTOFF22X         0x86    /* LTOFF22, relaxable.  */
+#define R_IA64_LDXMOV           0x87    /* Use of LTOFF22X.  */
+#define R_IA64_TPREL14          0x91    /* @tprel(sym+add), add imm14 */
+#define R_IA64_TPREL22          0x92    /* @tprel(sym+add), add imm22 */
+#define R_IA64_TPREL64I         0x93    /* @tprel(sym+add), add imm64 */
+#define R_IA64_TPREL64MSB       0x96    /* @tprel(sym+add), data8 MSB */
+#define R_IA64_TPREL64LSB       0x97    /* @tprel(sym+add), data8 LSB */
+#define R_IA64_LTOFF_TPREL22    0x9a    /* @ltoff(@tprel(s+a)), add imm22 */
+#define R_IA64_DTPMOD64MSB      0xa6    /* @dtpmod(sym+add), data8 MSB */
+#define R_IA64_DTPMOD64LSB      0xa7    /* @dtpmod(sym+add), data8 LSB */
+#define R_IA64_LTOFF_DTPMOD22   0xaa    /* @ltoff(@dtpmod(s+a)), imm22 */
+#define R_IA64_DTPREL14         0xb1    /* @dtprel(sym+add), imm14 */
+#define R_IA64_DTPREL22         0xb2    /* @dtprel(sym+add), imm22 */
+#define R_IA64_DTPREL64I        0xb3    /* @dtprel(sym+add), imm64 */
+#define R_IA64_DTPREL32MSB      0xb4    /* @dtprel(sym+add), data4 MSB */
+#define R_IA64_DTPREL32LSB      0xb5    /* @dtprel(sym+add), data4 LSB */
+#define R_IA64_DTPREL64MSB      0xb6    /* @dtprel(sym+add), data8 MSB */
+#define R_IA64_DTPREL64LSB      0xb7    /* @dtprel(sym+add), data8 LSB */
+#define R_IA64_LTOFF_DTPREL22   0xba    /* @ltoff(@dtprel(s+a)), imm22 */
+
+/* IA-64 specific section flags: */
+#define SHF_IA_64_SHORT         0x10000000      /* section near gp */
+
+/*
+ * We use (abuse?) this macro to insert the (empty) vm_area that is
+ * used to map the register backing store.  I don't see any better
+ * place to do this, but we should discuss this with Linus once we can
+ * talk to him...
+ */
+extern void ia64_init_addr_space (void);
+#define ELF_PLAT_INIT(_r, load_addr)    ia64_init_addr_space()
+
+/* ELF register definitions.  This is needed for core dump support.  */
+
+/*
+ * elf_gregset_t contains the application-level state in the following order:
+ *      r0-r31
+ *      NaT bits (for r0-r31; bit N == 1 iff rN is a NaT)
+ *      predicate registers (p0-p63)
+ *      b0-b7
+ *      ip cfm psr
+ *      ar.rsc ar.bsp ar.bspstore ar.rnat
+ *      ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
+ */
+#define ELF_NGREG       128     /* we really need just 72 but let's leave some headroom... */
+#define ELF_NFPREG      128     /* f0 and f1 could be omitted, but so what... */
+
+/* elf_gregset_t register offsets */
+#define ELF_GR_0_OFFSET     0
+#define ELF_NAT_OFFSET     (32 * sizeof(elf_greg_t))
+#define ELF_PR_OFFSET      (33 * sizeof(elf_greg_t))
+#define ELF_BR_0_OFFSET    (34 * sizeof(elf_greg_t))
+#define ELF_CR_IIP_OFFSET  (42 * sizeof(elf_greg_t))
+#define ELF_CFM_OFFSET     (43 * sizeof(elf_greg_t))
+#define ELF_CR_IPSR_OFFSET (44 * sizeof(elf_greg_t))
+#define ELF_GR_OFFSET(i)   (ELF_GR_0_OFFSET + i * sizeof(elf_greg_t))
+#define ELF_BR_OFFSET(i)   (ELF_BR_0_OFFSET + i * sizeof(elf_greg_t))
+#define ELF_AR_RSC_OFFSET  (45 * sizeof(elf_greg_t))
+#define ELF_AR_BSP_OFFSET  (46 * sizeof(elf_greg_t))
+#define ELF_AR_BSPSTORE_OFFSET (47 * sizeof(elf_greg_t))
+#define ELF_AR_RNAT_OFFSET (48 * sizeof(elf_greg_t))
+#define ELF_AR_CCV_OFFSET  (49 * sizeof(elf_greg_t))
+#define ELF_AR_UNAT_OFFSET (50 * sizeof(elf_greg_t))
+#define ELF_AR_FPSR_OFFSET (51 * sizeof(elf_greg_t))
+#define ELF_AR_PFS_OFFSET  (52 * sizeof(elf_greg_t))
+#define ELF_AR_LC_OFFSET   (53 * sizeof(elf_greg_t))
+#define ELF_AR_EC_OFFSET   (54 * sizeof(elf_greg_t))
+#define ELF_AR_CSD_OFFSET  (55 * sizeof(elf_greg_t))
+#define ELF_AR_SSD_OFFSET  (56 * sizeof(elf_greg_t))
+#define ELF_AR_END_OFFSET  (57 * sizeof(elf_greg_t))
+
+typedef unsigned long elf_fpxregset_t;
+
+typedef unsigned long elf_greg_t;
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct ia64_fpreg elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+
+
+struct pt_regs; /* forward declaration... */
+extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
+#define ELF_CORE_COPY_REGS(_dest,_regs) ia64_elf_core_copy_regs(_regs, _dest);
+
+/* This macro yields a bitmask that programs can use to figure out
+   what instruction set this CPU supports.  */
+#define ELF_HWCAP       0
+
+/* This macro yields a string that ld.so will use to load
+   implementation specific libraries for optimization.  Not terribly
+   relevant until we have real hardware to play with... */
+#define ELF_PLATFORM    NULL
+
+#define SET_PERSONALITY(ex, ibcs2)      set_personality(PER_LINUX)
+#define elf_read_implies_exec(ex, executable_stack)                                     \
+        ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0)
+
+struct task_struct;
+
+#define GATE_EHDR       ((const struct elfhdr *) GATE_ADDR)
+
+/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
+#define ARCH_DLINFO                                                             \
+do {                                                                            \
+        extern char __kernel_syscall_via_epc[];                                 \
+        NEW_AUX_ENT(AT_SYSINFO, (unsigned long) __kernel_syscall_via_epc);      \
+        NEW_AUX_ENT(AT_SYSINFO_EHDR, (unsigned long) GATE_EHDR);                \
+} while (0)
+
+
+/*
+ * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out
+ * extra segments containing the gate DSO contents.  Dumping its
+ * contents makes post-mortem fully interpretable later without matching up
+ * the same kernel and hardware config to see what PC values meant.
+ * Dumping its extra ELF program headers includes all the other information
+ * a debugger needs to easily find how the gate DSO was being used.
+ */
+#define ELF_CORE_EXTRA_PHDRS            (GATE_EHDR->e_phnum)
+#define ELF_CORE_WRITE_EXTRA_PHDRS                                              \
+do {                                                                            \
+        const struct elf_phdr *const gate_phdrs =                             \
+                (const struct elf_phdr *) (GATE_ADDR + GATE_EHDR->e_phoff);   \
+        int i;                                                                  \
+        Elf64_Off ofs = 0;                                                    \
+        for (i = 0; i < GATE_EHDR->e_phnum; ++i) {                              \
+                struct elf_phdr phdr = gate_phdrs[i];                         \
+                if (phdr.p_type == PT_LOAD) {                                   \
+                        phdr.p_memsz = PAGE_ALIGN(phdr.p_memsz);              \
+                        phdr.p_filesz = phdr.p_memsz;                         \
+                        if (ofs == 0) {                                       \
+                                ofs = phdr.p_offset = offset;                 \
+                        offset += phdr.p_filesz;                                \
+                }                                                             \
+                else                                                          \
+                                phdr.p_offset = ofs;                          \
+                }                                                             \
+                else                                                          \
+                        phdr.p_offset += ofs;                                   \
+                phdr.p_paddr = 0; /* match other core phdrs */                  \
+                DUMP_WRITE(&phdr, sizeof(phdr));                                \
+        }                                                                       \
+} while (0)
+#define ELF_CORE_WRITE_EXTRA_DATA                                       \
+do {                                                                    \
+        const struct elf_phdr *const gate_phdrs =                             \
+                (const struct elf_phdr *) (GATE_ADDR + GATE_EHDR->e_phoff);   \
+        int i;                                                          \
+        for (i = 0; i < GATE_EHDR->e_phnum; ++i) {                      \
+                if (gate_phdrs[i].p_type == PT_LOAD) {                        \
+                        DUMP_WRITE((void *) gate_phdrs[i].p_vaddr,            \
+                                   PAGE_ALIGN(gate_phdrs[i].p_memsz));        \
+                        break;                                                \
+                }                                                             \
+        }                                                               \
+} while (0)
+
+#endif /* _ASM_IA64_ELF_H */
diff --git a/arch/ia64/include/asm/emergency-restart.h b/arch/ia64/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/ia64/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/ia64/include/asm/errno.h b/arch/ia64/include/asm/errno.h
new file mode 100644
index 000000000000..4c82b503d92f
--- /dev/null
+++ b/arch/ia64/include/asm/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/arch/ia64/include/asm/esi.h b/arch/ia64/include/asm/esi.h
new file mode 100644
index 000000000000..40991c6ba647
--- /dev/null
+++ b/arch/ia64/include/asm/esi.h
@@ -0,0 +1,29 @@
+/*
+ * ESI service calls.
+ *
+ * Copyright (c) Copyright 2005-2006 Hewlett-Packard Development Company, L.P.
+ *      Alex Williamson <alex.williamson@hp.com>
+ */
+#ifndef esi_h
+#define esi_h
+
+#include <linux/efi.h>
+
+#define ESI_QUERY                       0x00000001
+#define ESI_OPEN_HANDLE                 0x02000000
+#define ESI_CLOSE_HANDLE                0x02000001
+
+enum esi_proc_type {
+        ESI_PROC_SERIALIZED,    /* calls need to be serialized */
+        ESI_PROC_MP_SAFE,       /* MP-safe, but not reentrant */
+        ESI_PROC_REENTRANT      /* MP-safe and reentrant */
+};
+
+extern struct ia64_sal_retval esi_call_phys (void *, u64 *);
+extern int ia64_esi_call(efi_guid_t, struct ia64_sal_retval *,
+                         enum esi_proc_type,
+                         u64, u64, u64, u64, u64, u64, u64, u64);
+extern int ia64_esi_call_phys(efi_guid_t, struct ia64_sal_retval *, u64, u64,
+                              u64, u64, u64, u64, u64, u64);
+
+#endif /* esi_h */
diff --git a/arch/ia64/include/asm/fb.h b/arch/ia64/include/asm/fb.h
new file mode 100644
index 000000000000..89a397cee90a
--- /dev/null
+++ b/arch/ia64/include/asm/fb.h
@@ -0,0 +1,23 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <linux/efi.h>
+#include <asm/page.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+        if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
+                vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+        else
+                vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/ia64/include/asm/fcntl.h b/arch/ia64/include/asm/fcntl.h
new file mode 100644
index 000000000000..1dd275dc8f65
--- /dev/null
+++ b/arch/ia64/include/asm/fcntl.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_IA64_FCNTL_H
+#define _ASM_IA64_FCNTL_H
+/*
+ * Modified 1998-2000
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
+ */
+
+#define force_o_largefile()     \
+                (personality(current->personality) != PER_LINUX32)
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _ASM_IA64_FCNTL_H */
diff --git a/arch/ia64/include/asm/fpswa.h b/arch/ia64/include/asm/fpswa.h
new file mode 100644
index 000000000000..62edfceadaa6
--- /dev/null
+++ b/arch/ia64/include/asm/fpswa.h
@@ -0,0 +1,73 @@
+#ifndef _ASM_IA64_FPSWA_H
+#define _ASM_IA64_FPSWA_H
+
+/*
+ * Floating-point Software Assist
+ *
+ * Copyright (C) 1999 Intel Corporation.
+ * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
+ * Copyright (C) 1999 Goutham Rao <goutham.rao@intel.com>
+ */
+
+typedef struct {
+        /* 4 * 128 bits */
+        unsigned long fp_lp[4*2];
+} fp_state_low_preserved_t;
+
+typedef struct {
+        /* 10 * 128 bits */
+        unsigned long fp_lv[10 * 2];
+} fp_state_low_volatile_t;
+
+typedef struct {
+        /* 16 * 128 bits */
+        unsigned long fp_hp[16 * 2];
+} fp_state_high_preserved_t;
+
+typedef struct {
+        /* 96 * 128 bits */
+        unsigned long fp_hv[96 * 2];
+} fp_state_high_volatile_t;
+
+/**
+ * floating point state to be passed to the FP emulation library by
+ * the trap/fault handler
+ */
+typedef struct {
+        unsigned long                   bitmask_low64;
+        unsigned long                   bitmask_high64;
+        fp_state_low_preserved_t        *fp_state_low_preserved;
+        fp_state_low_volatile_t         *fp_state_low_volatile;
+        fp_state_high_preserved_t       *fp_state_high_preserved;
+        fp_state_high_volatile_t        *fp_state_high_volatile;
+} fp_state_t;
+
+typedef struct {
+        unsigned long status;
+        unsigned long err0;
+        unsigned long err1;
+        unsigned long err2;
+} fpswa_ret_t;
+
+/**
+ * function header for the Floating Point software assist
+ * library. This function is invoked by the Floating point software
+ * assist trap/fault handler.
+ */
+typedef fpswa_ret_t (*efi_fpswa_t) (unsigned long trap_type, void *bundle, unsigned long *ipsr,
+                                    unsigned long *fsr, unsigned long *isr, unsigned long *preds,
+                                    unsigned long *ifs, fp_state_t *fp_state);
+
+/**
+ * This is the FPSWA library interface as defined by EFI.  We need to pass a 
+ * pointer to the interface itself on a call to the assist library
+ */
+typedef struct {
+        unsigned int     revision;
+        unsigned int     reserved;
+        efi_fpswa_t      fpswa;
+} fpswa_interface_t;
+
+extern fpswa_interface_t *fpswa_interface;
+
+#endif /* _ASM_IA64_FPSWA_H */
diff --git a/arch/ia64/include/asm/fpu.h b/arch/ia64/include/asm/fpu.h
new file mode 100644
index 000000000000..3859558ff0a4
--- /dev/null
+++ b/arch/ia64/include/asm/fpu.h
@@ -0,0 +1,66 @@
+#ifndef _ASM_IA64_FPU_H
+#define _ASM_IA64_FPU_H
+
+/*
+ * Copyright (C) 1998, 1999, 2002, 2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <asm/types.h>
+
+/* floating point status register: */
+#define FPSR_TRAP_VD    (1 << 0)        /* invalid op trap disabled */
+#define FPSR_TRAP_DD    (1 << 1)        /* denormal trap disabled */
+#define FPSR_TRAP_ZD    (1 << 2)        /* zero-divide trap disabled */
+#define FPSR_TRAP_OD    (1 << 3)        /* overflow trap disabled */
+#define FPSR_TRAP_UD    (1 << 4)        /* underflow trap disabled */
+#define FPSR_TRAP_ID    (1 << 5)        /* inexact trap disabled */
+#define FPSR_S0(x)      ((x) <<  6)
+#define FPSR_S1(x)      ((x) << 19)
+#define FPSR_S2(x)      (__IA64_UL(x) << 32)
+#define FPSR_S3(x)      (__IA64_UL(x) << 45)
+
+/* floating-point status field controls: */
+#define FPSF_FTZ        (1 << 0)                /* flush-to-zero */
+#define FPSF_WRE        (1 << 1)                /* widest-range exponent */
+#define FPSF_PC(x)      (((x) & 0x3) << 2)      /* precision control */
+#define FPSF_RC(x)      (((x) & 0x3) << 4)      /* rounding control */
+#define FPSF_TD         (1 << 6)                /* trap disabled */
+
+/* floating-point status field flags: */
+#define FPSF_V          (1 <<  7)               /* invalid operation flag */
+#define FPSF_D          (1 <<  8)               /* denormal/unnormal operand flag */
+#define FPSF_Z          (1 <<  9)               /* zero divide (IEEE) flag */
+#define FPSF_O          (1 << 10)               /* overflow (IEEE) flag */
+#define FPSF_U          (1 << 11)               /* underflow (IEEE) flag */
+#define FPSF_I          (1 << 12)               /* inexact (IEEE) flag) */
+
+/* floating-point rounding control: */
+#define FPRC_NEAREST    0x0
+#define FPRC_NEGINF     0x1
+#define FPRC_POSINF     0x2
+#define FPRC_TRUNC      0x3
+
+#define FPSF_DEFAULT    (FPSF_PC (0x3) | FPSF_RC (FPRC_NEAREST))
+
+/* This default value is the same as HP-UX uses.  Don't change it
+   without a very good reason.  */
+#define FPSR_DEFAULT    (FPSR_TRAP_VD | FPSR_TRAP_DD | FPSR_TRAP_ZD     \
+                         | FPSR_TRAP_OD | FPSR_TRAP_UD | FPSR_TRAP_ID   \
+                         | FPSR_S0 (FPSF_DEFAULT)                       \
+                         | FPSR_S1 (FPSF_DEFAULT | FPSF_TD | FPSF_WRE)  \
+                         | FPSR_S2 (FPSF_DEFAULT | FPSF_TD)             \
+                         | FPSR_S3 (FPSF_DEFAULT | FPSF_TD))
+
+# ifndef __ASSEMBLY__
+
+struct ia64_fpreg {
+        union {
+                unsigned long bits[2];
+                long double __dummy;    /* force 16-byte alignment */
+        } u;
+};
+
+# endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_IA64_FPU_H */
diff --git a/arch/ia64/include/asm/futex.h b/arch/ia64/include/asm/futex.h
new file mode 100644
index 000000000000..c7f0f062239c
--- /dev/null
+++ b/arch/ia64/include/asm/futex.h
@@ -0,0 +1,124 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+#include <asm/system.h>
+
+#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
+do {                                                                    \
+        register unsigned long r8 __asm ("r8") = 0;                     \
+        __asm__ __volatile__(                                           \
+                "       mf;;                                    \n"     \
+                "[1:] " insn ";;                                \n"     \
+                "       .xdata4 \"__ex_table\", 1b-., 2f-.      \n"     \
+                "[2:]"                                                  \
+                : "+r" (r8), "=r" (oldval)                              \
+                : "r" (uaddr), "r" (oparg)                              \
+                : "memory");                                            \
+        ret = r8;                                                       \
+} while (0)
+
+#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
+do {                                                                    \
+        register unsigned long r8 __asm ("r8") = 0;                     \
+        int val, newval;                                                \
+        do {                                                            \
+                __asm__ __volatile__(                                   \
+                        "       mf;;                              \n"   \
+                        "[1:]   ld4 %3=[%4];;                     \n"   \
+                        "       mov %2=%3                         \n"   \
+                                insn    ";;                       \n"   \
+                        "       mov ar.ccv=%2;;                   \n"   \
+                        "[2:]   cmpxchg4.acq %1=[%4],%3,ar.ccv;;  \n"   \
+                        "       .xdata4 \"__ex_table\", 1b-., 3f-.\n"   \
+                        "       .xdata4 \"__ex_table\", 2b-., 3f-.\n"   \
+                        "[3:]"                                          \
+                        : "+r" (r8), "=r" (val), "=&r" (oldval),        \
+                           "=&r" (newval)                               \
+                        : "r" (uaddr), "r" (oparg)                      \
+                        : "memory");                                    \
+                if (unlikely (r8))                                      \
+                        break;                                          \
+        } while (unlikely (val != oldval));                             \
+        ret = r8;                                                       \
+} while (0)
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr,
+                                   oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr,
+                                   ~oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        {
+                register unsigned long r8 __asm ("r8");
+                __asm__ __volatile__(
+                        "       mf;;                                    \n"
+                        "       mov ar.ccv=%3;;                         \n"
+                        "[1:]   cmpxchg4.acq %0=[%1],%2,ar.ccv          \n"
+                        "       .xdata4 \"__ex_table\", 1b-., 2f-.      \n"
+                        "[2:]"
+                        : "=r" (r8)
+                        : "r" (uaddr), "r" (newval),
+                          "rO" ((long) (unsigned) oldval)
+                        : "memory");
+                return r8;
+        }
+}
+
+#endif /* _ASM_FUTEX_H */
diff --git a/arch/ia64/include/asm/gcc_intrin.h b/arch/ia64/include/asm/gcc_intrin.h
new file mode 100644
index 000000000000..0f5b55921758
--- /dev/null
+++ b/arch/ia64/include/asm/gcc_intrin.h
@@ -0,0 +1,620 @@
+#ifndef _ASM_IA64_GCC_INTRIN_H
+#define _ASM_IA64_GCC_INTRIN_H
+/*
+ *
+ * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
+ * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
+ */
+
+#include <linux/compiler.h>
+
+/* define this macro to get some asm stmts included in 'c' files */
+#define ASM_SUPPORTED
+
+/* Optimization barrier */
+/* The "volatile" is due to gcc bugs */
+#define ia64_barrier()  asm volatile ("":::"memory")
+
+#define ia64_stop()     asm volatile (";;"::)
+
+#define ia64_invala_gr(regnum)  asm volatile ("invala.e r%0" :: "i"(regnum))
+
+#define ia64_invala_fr(regnum)  asm volatile ("invala.e f%0" :: "i"(regnum))
+
+#define ia64_flushrs() asm volatile ("flushrs;;":::"memory")
+
+#define ia64_loadrs() asm volatile ("loadrs;;":::"memory")
+
+extern void ia64_bad_param_for_setreg (void);
+extern void ia64_bad_param_for_getreg (void);
+
+#ifdef __KERNEL__
+register unsigned long ia64_r13 asm ("r13") __used;
+#endif
+
+#define ia64_native_setreg(regnum, val)                                         \
+({                                                                              \
+        switch (regnum) {                                                       \
+            case _IA64_REG_PSR_L:                                               \
+                    asm volatile ("mov psr.l=%0" :: "r"(val) : "memory");       \
+                    break;                                                      \
+            case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC:                          \
+                    asm volatile ("mov ar%0=%1" ::                              \
+                                          "i" (regnum - _IA64_REG_AR_KR0),      \
+                                          "r"(val): "memory");                  \
+                    break;                                                      \
+            case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1:                        \
+                    asm volatile ("mov cr%0=%1" ::                              \
+                                          "i" (regnum - _IA64_REG_CR_DCR),      \
+                                          "r"(val): "memory" );                 \
+                    break;                                                      \
+            case _IA64_REG_SP:                                                  \
+                    asm volatile ("mov r12=%0" ::                               \
+                                          "r"(val): "memory");                  \
+                    break;                                                      \
+            case _IA64_REG_GP:                                                  \
+                    asm volatile ("mov gp=%0" :: "r"(val) : "memory");          \
+                break;                                                          \
+            default:                                                            \
+                    ia64_bad_param_for_setreg();                                \
+                    break;                                                      \
+        }                                                                       \
+})
+
+#define ia64_native_getreg(regnum)                                              \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+                                                                                \
+        switch (regnum) {                                                       \
+        case _IA64_REG_GP:                                                      \
+                asm volatile ("mov %0=gp" : "=r"(ia64_intri_res));              \
+                break;                                                          \
+        case _IA64_REG_IP:                                                      \
+                asm volatile ("mov %0=ip" : "=r"(ia64_intri_res));              \
+                break;                                                          \
+        case _IA64_REG_PSR:                                                     \
+                asm volatile ("mov %0=psr" : "=r"(ia64_intri_res));             \
+                break;                                                          \
+        case _IA64_REG_TP:      /* for current() */                             \
+                ia64_intri_res = ia64_r13;                                      \
+                break;                                                          \
+        case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC:                              \
+                asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res)             \
+                                      : "i"(regnum - _IA64_REG_AR_KR0));        \
+                break;                                                          \
+        case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1:                            \
+                asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res)             \
+                                      : "i" (regnum - _IA64_REG_CR_DCR));       \
+                break;                                                          \
+        case _IA64_REG_SP:                                                      \
+                asm volatile ("mov %0=sp" : "=r" (ia64_intri_res));             \
+                break;                                                          \
+        default:                                                                \
+                ia64_bad_param_for_getreg();                                    \
+                break;                                                          \
+        }                                                                       \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_hint_pause 0
+
+#define ia64_hint(mode)                                         \
+({                                                              \
+        switch (mode) {                                         \
+        case ia64_hint_pause:                                   \
+                asm volatile ("hint @pause" ::: "memory");      \
+                break;                                          \
+        }                                                       \
+})
+
+
+/* Integer values for mux1 instruction */
+#define ia64_mux1_brcst 0
+#define ia64_mux1_mix   8
+#define ia64_mux1_shuf  9
+#define ia64_mux1_alt  10
+#define ia64_mux1_rev  11
+
+#define ia64_mux1(x, mode)                                                      \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+                                                                                \
+        switch (mode) {                                                         \
+        case ia64_mux1_brcst:                                                   \
+                asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x));    \
+                break;                                                          \
+        case ia64_mux1_mix:                                                     \
+                asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x));      \
+                break;                                                          \
+        case ia64_mux1_shuf:                                                    \
+                asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x));     \
+                break;                                                          \
+        case ia64_mux1_alt:                                                     \
+                asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x));      \
+                break;                                                          \
+        case ia64_mux1_rev:                                                     \
+                asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x));      \
+                break;                                                          \
+        }                                                                       \
+        ia64_intri_res;                                                         \
+})
+
+#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
+# define ia64_popcnt(x)         __builtin_popcountl(x)
+#else
+# define ia64_popcnt(x)                                         \
+  ({                                                            \
+        __u64 ia64_intri_res;                                   \
+        asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \
+                                                                \
+        ia64_intri_res;                                         \
+  })
+#endif
+
+#define ia64_getf_exp(x)                                        \
+({                                                              \
+        long ia64_intri_res;                                    \
+                                                                \
+        asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \
+                                                                \
+        ia64_intri_res;                                         \
+})
+
+#define ia64_shrp(a, b, count)                                                          \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count));   \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_ldfs(regnum, x)                                    \
+({                                                              \
+        register double __f__ asm ("f"#regnum);                 \
+        asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x));     \
+})
+
+#define ia64_ldfd(regnum, x)                                    \
+({                                                              \
+        register double __f__ asm ("f"#regnum);                 \
+        asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x));     \
+})
+
+#define ia64_ldfe(regnum, x)                                    \
+({                                                              \
+        register double __f__ asm ("f"#regnum);                 \
+        asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x));     \
+})
+
+#define ia64_ldf8(regnum, x)                                    \
+({                                                              \
+        register double __f__ asm ("f"#regnum);                 \
+        asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x));     \
+})
+
+#define ia64_ldf_fill(regnum, x)                                \
+({                                                              \
+        register double __f__ asm ("f"#regnum);                 \
+        asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
+})
+
+#define ia64_st4_rel_nta(m, val)                                        \
+({                                                                      \
+        asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
+})
+
+#define ia64_stfs(x, regnum)                                            \
+({                                                                      \
+        register double __f__ asm ("f"#regnum);                         \
+        asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
+})
+
+#define ia64_stfd(x, regnum)                                            \
+({                                                                      \
+        register double __f__ asm ("f"#regnum);                         \
+        asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
+})
+
+#define ia64_stfe(x, regnum)                                            \
+({                                                                      \
+        register double __f__ asm ("f"#regnum);                         \
+        asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
+})
+
+#define ia64_stf8(x, regnum)                                            \
+({                                                                      \
+        register double __f__ asm ("f"#regnum);                         \
+        asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
+})
+
+#define ia64_stf_spill(x, regnum)                                               \
+({                                                                              \
+        register double __f__ asm ("f"#regnum);                                 \
+        asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory");    \
+})
+
+#define ia64_fetchadd4_acq(p, inc)                                              \
+({                                                                              \
+                                                                                \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("fetchadd4.acq %0=[%1],%2"                                \
+                                : "=r"(ia64_intri_res) : "r"(p), "i" (inc)      \
+                                : "memory");                                    \
+                                                                                \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_fetchadd4_rel(p, inc)                                              \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("fetchadd4.rel %0=[%1],%2"                                \
+                                : "=r"(ia64_intri_res) : "r"(p), "i" (inc)      \
+                                : "memory");                                    \
+                                                                                \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_fetchadd8_acq(p, inc)                                              \
+({                                                                              \
+                                                                                \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("fetchadd8.acq %0=[%1],%2"                                \
+                                : "=r"(ia64_intri_res) : "r"(p), "i" (inc)      \
+                                : "memory");                                    \
+                                                                                \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_fetchadd8_rel(p, inc)                                              \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("fetchadd8.rel %0=[%1],%2"                                \
+                                : "=r"(ia64_intri_res) : "r"(p), "i" (inc)      \
+                                : "memory");                                    \
+                                                                                \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_xchg1(ptr,x)                                                       \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("xchg1 %0=[%1],%2"                                        \
+                      : "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory"); \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_xchg2(ptr,x)                                               \
+({                                                                      \
+        __u64 ia64_intri_res;                                           \
+        asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res)        \
+                      : "r" (ptr), "r" (x) : "memory");                 \
+        ia64_intri_res;                                                 \
+})
+
+#define ia64_xchg4(ptr,x)                                               \
+({                                                                      \
+        __u64 ia64_intri_res;                                           \
+        asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res)        \
+                      : "r" (ptr), "r" (x) : "memory");                 \
+        ia64_intri_res;                                                 \
+})
+
+#define ia64_xchg8(ptr,x)                                               \
+({                                                                      \
+        __u64 ia64_intri_res;                                           \
+        asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res)        \
+                      : "r" (ptr), "r" (x) : "memory");                 \
+        ia64_intri_res;                                                 \
+})
+
+#define ia64_cmpxchg1_acq(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+        asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_cmpxchg1_rel(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+        asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_cmpxchg2_acq(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+        asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_cmpxchg2_rel(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+                                                                                        \
+        asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_cmpxchg4_acq(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+        asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_cmpxchg4_rel(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+        asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_cmpxchg8_acq(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+        asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_cmpxchg8_rel(ptr, new, old)                                                \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));                                  \
+                                                                                        \
+        asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv":                                 \
+                              "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");    \
+        ia64_intri_res;                                                                 \
+})
+
+#define ia64_mf()       asm volatile ("mf" ::: "memory")
+#define ia64_mfa()      asm volatile ("mf.a" ::: "memory")
+
+#define ia64_invala() asm volatile ("invala" ::: "memory")
+
+#define ia64_native_thash(addr)                                                 \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr));       \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_srlz_i()   asm volatile (";; srlz.i ;;" ::: "memory")
+#define ia64_srlz_d()   asm volatile (";; srlz.d" ::: "memory");
+
+#ifdef HAVE_SERIALIZE_DIRECTIVE
+# define ia64_dv_serialize_data()               asm volatile (".serialize.data");
+# define ia64_dv_serialize_instruction()        asm volatile (".serialize.instruction");
+#else
+# define ia64_dv_serialize_data()
+# define ia64_dv_serialize_instruction()
+#endif
+
+#define ia64_nop(x)     asm volatile ("nop %0"::"i"(x));
+
+#define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")
+
+#define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory")
+
+
+#define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1"                         \
+                                             :: "r"(trnum), "r"(addr) : "memory")
+
+#define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1"                         \
+                                             :: "r"(trnum), "r"(addr) : "memory")
+
+#define ia64_tpa(addr)                                                          \
+({                                                                              \
+        __u64 ia64_pa;                                                          \
+        asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory");    \
+        ia64_pa;                                                                \
+})
+
+#define __ia64_set_dbr(index, val)                                              \
+        asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
+
+#define ia64_set_ibr(index, val)                                                \
+        asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
+
+#define ia64_set_pkr(index, val)                                                \
+        asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
+
+#define ia64_set_pmc(index, val)                                                \
+        asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
+
+#define ia64_set_pmd(index, val)                                                \
+        asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
+
+#define ia64_native_set_rr(index, val)                                                  \
+        asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
+
+#define ia64_native_get_cpuid(index)                                                    \
+({                                                                                      \
+        __u64 ia64_intri_res;                                                           \
+        asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index));        \
+        ia64_intri_res;                                                                 \
+})
+
+#define __ia64_get_dbr(index)                                                   \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index));    \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_get_ibr(index)                                                     \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index));    \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_get_pkr(index)                                                     \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index));    \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_get_pmc(index)                                                     \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index));    \
+        ia64_intri_res;                                                         \
+})
+
+
+#define ia64_native_get_pmd(index)                                              \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index));    \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_native_get_rr(index)                                               \
+({                                                                              \
+        __u64 ia64_intri_res;                                                   \
+        asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index));    \
+        ia64_intri_res;                                                         \
+})
+
+#define ia64_native_fc(addr)    asm volatile ("fc %0" :: "r"(addr) : "memory")
+
+
+#define ia64_sync_i()   asm volatile (";; sync.i" ::: "memory")
+
+#define ia64_native_ssm(mask)   asm volatile ("ssm %0":: "i"((mask)) : "memory")
+#define ia64_native_rsm(mask)   asm volatile ("rsm %0":: "i"((mask)) : "memory")
+#define ia64_sum(mask)  asm volatile ("sum %0":: "i"((mask)) : "memory")
+#define ia64_rum(mask)  asm volatile ("rum %0":: "i"((mask)) : "memory")
+
+#define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr))
+
+#define ia64_native_ptcga(addr, size)                                           \
+do {                                                                            \
+        asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory");       \
+        ia64_dv_serialize_data();                                               \
+} while (0)
+
+#define ia64_ptcl(addr, size)                                                   \
+do {                                                                            \
+        asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory");        \
+        ia64_dv_serialize_data();                                               \
+} while (0)
+
+#define ia64_ptri(addr, size)                                           \
+        asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
+
+#define ia64_ptrd(addr, size)                                           \
+        asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
+
+#define ia64_ttag(addr)                                                 \
+({                                                                        \
+        __u64 ia64_intri_res;                                              \
+        asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr));   \
+        ia64_intri_res;                                                  \
+})
+
+
+/* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */
+
+#define ia64_lfhint_none   0
+#define ia64_lfhint_nt1    1
+#define ia64_lfhint_nt2    2
+#define ia64_lfhint_nta    3
+
+#define ia64_lfetch(lfhint, y)                                  \
+({                                                              \
+        switch (lfhint) {                                       \
+        case ia64_lfhint_none:                                  \
+                asm volatile ("lfetch [%0]" : : "r"(y));        \
+                break;                                          \
+        case ia64_lfhint_nt1:                                   \
+                asm volatile ("lfetch.nt1 [%0]" : : "r"(y));    \
+                break;                                          \
+        case ia64_lfhint_nt2:                                   \
+                asm volatile ("lfetch.nt2 [%0]" : : "r"(y));    \
+                break;                                          \
+        case ia64_lfhint_nta:                                   \
+                asm volatile ("lfetch.nta [%0]" : : "r"(y));    \
+                break;                                          \
+        }                                                       \
+})
+
+#define ia64_lfetch_excl(lfhint, y)                                     \
+({                                                                      \
+        switch (lfhint) {                                               \
+        case ia64_lfhint_none:                                          \
+                asm volatile ("lfetch.excl [%0]" :: "r"(y));            \
+                break;                                                  \
+        case ia64_lfhint_nt1:                                           \
+                asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y));        \
+                break;                                                  \
+        case ia64_lfhint_nt2:                                           \
+                asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y));        \
+                break;                                                  \
+        case ia64_lfhint_nta:                                           \
+                asm volatile ("lfetch.excl.nta [%0]" :: "r"(y));        \
+                break;                                                  \
+        }                                                               \
+})
+
+#define ia64_lfetch_fault(lfhint, y)                                    \
+({                                                                      \
+        switch (lfhint) {                                               \
+        case ia64_lfhint_none:                                          \
+                asm volatile ("lfetch.fault [%0]" : : "r"(y));          \
+                break;                                                  \
+        case ia64_lfhint_nt1:                                           \
+                asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y));      \
+                break;                                                  \
+        case ia64_lfhint_nt2:                                           \
+                asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y));      \
+                break;                                                  \
+        case ia64_lfhint_nta:                                           \
+                asm volatile ("lfetch.fault.nta [%0]" : : "r"(y));      \
+                break;                                                  \
+        }                                                               \
+})
+
+#define ia64_lfetch_fault_excl(lfhint, y)                               \
+({                                                                      \
+        switch (lfhint) {                                               \
+        case ia64_lfhint_none:                                          \
+                asm volatile ("lfetch.fault.excl [%0]" :: "r"(y));      \
+                break;                                                  \
+        case ia64_lfhint_nt1:                                           \
+                asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y));  \
+                break;                                                  \
+        case ia64_lfhint_nt2:                                           \
+                asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y));  \
+                break;                                                  \
+        case ia64_lfhint_nta:                                           \
+                asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y));  \
+                break;                                                  \
+        }                                                               \
+})
+
+#define ia64_native_intrin_local_irq_restore(x)                 \
+do {                                                            \
+        asm volatile (";;   cmp.ne p6,p7=%0,r0;;"               \
+                      "(p6) ssm psr.i;"                         \
+                      "(p7) rsm psr.i;;"                        \
+                      "(p6) srlz.d"                             \
+                      :: "r"((x)) : "p6", "p7", "memory");      \
+} while (0)
+
+#endif /* _ASM_IA64_GCC_INTRIN_H */
diff --git a/arch/ia64/include/asm/hardirq.h b/arch/ia64/include/asm/hardirq.h
new file mode 100644
index 000000000000..140e495b8e0e
--- /dev/null
+++ b/arch/ia64/include/asm/hardirq.h
@@ -0,0 +1,37 @@
+#ifndef _ASM_IA64_HARDIRQ_H
+#define _ASM_IA64_HARDIRQ_H
+
+/*
+ * Modified 1998-2002, 2004 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+
+#include <linux/threads.h>
+#include <linux/irq.h>
+
+#include <asm/processor.h>
+
+/*
+ * No irq_cpustat_t for IA-64.  The data is held in the per-CPU data structure.
+ */
+
+#define __ARCH_IRQ_STAT 1
+
+#define local_softirq_pending()         (local_cpu_data->softirq_pending)
+
+#define HARDIRQ_BITS    14
+
+/*
+ * The hardirq mask has to be large enough to have space for potentially all IRQ sources
+ * in the system nesting on a single CPU:
+ */
+#if (1 << HARDIRQ_BITS) < NR_IRQS
+# error HARDIRQ_BITS is too low!
+#endif
+
+extern void __iomem *ipi_base_addr;
+
+void ack_bad_irq(unsigned int irq);
+
+#endif /* _ASM_IA64_HARDIRQ_H */
diff --git a/arch/ia64/include/asm/hpsim.h b/arch/ia64/include/asm/hpsim.h
new file mode 100644
index 000000000000..892ab198a9da
--- /dev/null
+++ b/arch/ia64/include/asm/hpsim.h
@@ -0,0 +1,16 @@
+#ifndef _ASMIA64_HPSIM_H
+#define _ASMIA64_HPSIM_H
+
+#ifndef CONFIG_HP_SIMSERIAL_CONSOLE
+static inline int simcons_register(void) { return 1; }
+#else
+int simcons_register(void);
+#endif
+
+struct tty_driver;
+extern struct tty_driver *hp_simserial_driver;
+
+void ia64_ssc_connect_irq(long intr, long irq);
+void ia64_ctl_trace(long on);
+
+#endif
diff --git a/arch/ia64/include/asm/hugetlb.h b/arch/ia64/include/asm/hugetlb.h
new file mode 100644
index 000000000000..da55c63728e0
--- /dev/null
+++ b/arch/ia64/include/asm/hugetlb.h
@@ -0,0 +1,80 @@
+#ifndef _ASM_IA64_HUGETLB_H
+#define _ASM_IA64_HUGETLB_H
+
+#include <asm/page.h>
+
+
+void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
+                            unsigned long end, unsigned long floor,
+                            unsigned long ceiling);
+
+int prepare_hugepage_range(struct file *file,
+                        unsigned long addr, unsigned long len);
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr,
+                                         unsigned long len)
+{
+        return (REGION_NUMBER(addr) == RGN_HPAGE ||
+                REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE);
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        return *ptep;
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+#endif /* _ASM_IA64_HUGETLB_H */
diff --git a/arch/ia64/include/asm/hw_irq.h b/arch/ia64/include/asm/hw_irq.h
new file mode 100644
index 000000000000..5c99cbcb8a0d
--- /dev/null
+++ b/arch/ia64/include/asm/hw_irq.h
@@ -0,0 +1,192 @@
+#ifndef _ASM_IA64_HW_IRQ_H
+#define _ASM_IA64_HW_IRQ_H
+
+/*
+ * Copyright (C) 2001-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/profile.h>
+
+#include <asm/machvec.h>
+#include <asm/ptrace.h>
+#include <asm/smp.h>
+
+#ifndef CONFIG_PARAVIRT
+typedef u8 ia64_vector;
+#else
+typedef u16 ia64_vector;
+#endif
+
+/*
+ * 0 special
+ *
+ * 1,3-14 are reserved from firmware
+ *
+ * 16-255 (vectored external interrupts) are available
+ *
+ * 15 spurious interrupt (see IVR)
+ *
+ * 16 lowest priority, 255 highest priority
+ *
+ * 15 classes of 16 interrupts each.
+ */
+#define IA64_MIN_VECTORED_IRQ            16
+#define IA64_MAX_VECTORED_IRQ           255
+#define IA64_NUM_VECTORS                256
+
+#define AUTO_ASSIGN                     -1
+
+#define IA64_SPURIOUS_INT_VECTOR        0x0f
+
+/*
+ * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
+ */
+#define IA64_CPEP_VECTOR                0x1c    /* corrected platform error polling vector */
+#define IA64_CMCP_VECTOR                0x1d    /* corrected machine-check polling vector */
+#define IA64_CPE_VECTOR                 0x1e    /* corrected platform error interrupt vector */
+#define IA64_CMC_VECTOR                 0x1f    /* corrected machine-check interrupt vector */
+/*
+ * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
+ * Use vectors 0x30-0xe7 as the default device vector range for ia64.
+ * Platforms may choose to reduce this range in platform_irq_setup, but the
+ * platform range must fall within
+ *      [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR]
+ */
+extern int ia64_first_device_vector;
+extern int ia64_last_device_vector;
+
+#define IA64_DEF_FIRST_DEVICE_VECTOR    0x30
+#define IA64_DEF_LAST_DEVICE_VECTOR     0xe7
+#define IA64_FIRST_DEVICE_VECTOR        ia64_first_device_vector
+#define IA64_LAST_DEVICE_VECTOR         ia64_last_device_vector
+#define IA64_MAX_DEVICE_VECTORS         (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1)
+#define IA64_NUM_DEVICE_VECTORS         (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
+
+#define IA64_MCA_RENDEZ_VECTOR          0xe8    /* MCA rendez interrupt */
+#define IA64_PERFMON_VECTOR             0xee    /* performance monitor interrupt vector */
+#define IA64_TIMER_VECTOR               0xef    /* use highest-prio group 15 interrupt for timer */
+#define IA64_MCA_WAKEUP_VECTOR          0xf0    /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
+#define IA64_IPI_LOCAL_TLB_FLUSH        0xfc    /* SMP flush local TLB */
+#define IA64_IPI_RESCHEDULE             0xfd    /* SMP reschedule */
+#define IA64_IPI_VECTOR                 0xfe    /* inter-processor interrupt vector */
+
+/* Used for encoding redirected irqs */
+
+#define IA64_IRQ_REDIRECTED             (1 << 31)
+
+/* IA64 inter-cpu interrupt related definitions */
+
+#define IA64_IPI_DEFAULT_BASE_ADDR      0xfee00000
+
+/* Delivery modes for inter-cpu interrupts */
+enum {
+        IA64_IPI_DM_INT =       0x0,    /* pend an external interrupt */
+        IA64_IPI_DM_PMI =       0x2,    /* pend a PMI */
+        IA64_IPI_DM_NMI =       0x4,    /* pend an NMI (vector 2) */
+        IA64_IPI_DM_INIT =      0x5,    /* pend an INIT interrupt */
+        IA64_IPI_DM_EXTINT =    0x7,    /* pend an 8259-compatible interrupt. */
+};
+
+extern __u8 isa_irq_to_vector_map[16];
+#define isa_irq_to_vector(x)    isa_irq_to_vector_map[(x)]
+
+struct irq_cfg {
+        ia64_vector vector;
+        cpumask_t domain;
+        cpumask_t old_domain;
+        unsigned move_cleanup_count;
+        u8 move_in_progress : 1;
+};
+extern spinlock_t vector_lock;
+extern struct irq_cfg irq_cfg[NR_IRQS];
+#define irq_to_domain(x)        irq_cfg[(x)].domain
+DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq);
+
+extern struct hw_interrupt_type irq_type_ia64_lsapic;   /* CPU-internal interrupt controller */
+
+#ifdef CONFIG_PARAVIRT_GUEST
+#include <asm/paravirt.h>
+#else
+#define ia64_register_ipi       ia64_native_register_ipi
+#define assign_irq_vector       ia64_native_assign_irq_vector
+#define free_irq_vector         ia64_native_free_irq_vector
+#define register_percpu_irq     ia64_native_register_percpu_irq
+#define ia64_resend_irq         ia64_native_resend_irq
+#endif
+
+extern void ia64_native_register_ipi(void);
+extern int bind_irq_vector(int irq, int vector, cpumask_t domain);
+extern int ia64_native_assign_irq_vector (int irq);     /* allocate a free vector */
+extern void ia64_native_free_irq_vector (int vector);
+extern int reserve_irq_vector (int vector);
+extern void __setup_vector_irq(int cpu);
+extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
+extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action);
+extern int check_irq_used (int irq);
+extern void destroy_and_reserve_irq (unsigned int irq);
+
+#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
+extern int irq_prepare_move(int irq, int cpu);
+extern void irq_complete_move(unsigned int irq);
+#else
+static inline int irq_prepare_move(int irq, int cpu) { return 0; }
+static inline void irq_complete_move(unsigned int irq) {}
+#endif
+
+static inline void ia64_native_resend_irq(unsigned int vector)
+{
+        platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
+}
+
+/*
+ * Default implementations for the irq-descriptor API:
+ */
+
+extern irq_desc_t irq_desc[NR_IRQS];
+
+#ifndef CONFIG_IA64_GENERIC
+static inline ia64_vector __ia64_irq_to_vector(int irq)
+{
+        return irq_cfg[irq].vector;
+}
+
+static inline unsigned int
+__ia64_local_vector_to_irq (ia64_vector vec)
+{
+        return __get_cpu_var(vector_irq)[vec];
+}
+#endif
+
+/*
+ * Next follows the irq descriptor interface.  On IA-64, each CPU supports 256 interrupt
+ * vectors.  On smaller systems, there is a one-to-one correspondence between interrupt
+ * vectors and the Linux irq numbers.  However, larger systems may have multiple interrupt
+ * domains meaning that the translation from vector number to irq number depends on the
+ * interrupt domain that a CPU belongs to.  This API abstracts such platform-dependent
+ * differences and provides a uniform means to translate between vector and irq numbers
+ * and to obtain the irq descriptor for a given irq number.
+ */
+
+/* Extract the IA-64 vector that corresponds to IRQ.  */
+static inline ia64_vector
+irq_to_vector (int irq)
+{
+        return platform_irq_to_vector(irq);
+}
+
+/*
+ * Convert the local IA-64 vector to the corresponding irq number.  This translation is
+ * done in the context of the interrupt domain that the currently executing CPU belongs
+ * to.
+ */
+static inline unsigned int
+local_vector_to_irq (ia64_vector vec)
+{
+        return platform_local_vector_to_irq(vec);
+}
+
+#endif /* _ASM_IA64_HW_IRQ_H */
diff --git a/arch/ia64/include/asm/ia32.h b/arch/ia64/include/asm/ia32.h
new file mode 100644
index 000000000000..2390ee145aa1
--- /dev/null
+++ b/arch/ia64/include/asm/ia32.h
@@ -0,0 +1,40 @@
+#ifndef _ASM_IA64_IA32_H
+#define _ASM_IA64_IA32_H
+
+
+#include <asm/ptrace.h>
+#include <asm/signal.h>
+
+#define IA32_NR_syscalls                285     /* length of syscall table */
+#define IA32_PAGE_SHIFT                 12      /* 4KB pages */
+
+#ifndef __ASSEMBLY__
+
+# ifdef CONFIG_IA32_SUPPORT
+
+#define IA32_PAGE_OFFSET        0xc0000000
+
+extern void ia32_cpu_init (void);
+extern void ia32_mem_init (void);
+extern void ia32_gdt_init (void);
+extern int ia32_exception (struct pt_regs *regs, unsigned long isr);
+extern int ia32_intercept (struct pt_regs *regs, unsigned long isr);
+extern int ia32_clone_tls (struct task_struct *child, struct pt_regs *childregs);
+
+# endif /* !CONFIG_IA32_SUPPORT */
+
+/* Declare this unconditionally, so we don't get warnings for unreachable code.  */
+extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
+                              sigset_t *set, struct pt_regs *regs);
+#if PAGE_SHIFT > IA32_PAGE_SHIFT
+extern int ia32_copy_ia64_partial_page_list(struct task_struct *,
+                                        unsigned long);
+extern void ia32_drop_ia64_partial_page_list(struct task_struct *);
+#else
+# define ia32_copy_ia64_partial_page_list(a1, a2)       0
+# define ia32_drop_ia64_partial_page_list(a1)   do { ; } while (0)
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_IA64_IA32_H */
diff --git a/arch/ia64/include/asm/ia64regs.h b/arch/ia64/include/asm/ia64regs.h
new file mode 100644
index 000000000000..1757f1c11ad4
--- /dev/null
+++ b/arch/ia64/include/asm/ia64regs.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2002,2003 Intel Corp.
+ *      Jun Nakajima <jun.nakajima@intel.com>
+ *      Suresh Siddha <suresh.b.siddha@intel.com>
+ */
+
+#ifndef _ASM_IA64_IA64REGS_H
+#define _ASM_IA64_IA64REGS_H
+
+/*
+ * Register Names for getreg() and setreg().
+ *
+ * The "magic" numbers happen to match the values used by the Intel compiler's
+ * getreg()/setreg() intrinsics.
+ */
+
+/* Special Registers */
+
+#define _IA64_REG_IP            1016    /* getreg only */
+#define _IA64_REG_PSR           1019
+#define _IA64_REG_PSR_L         1019
+
+/* General Integer Registers */
+
+#define _IA64_REG_GP            1025    /* R1 */
+#define _IA64_REG_R8            1032    /* R8 */
+#define _IA64_REG_R9            1033    /* R9 */
+#define _IA64_REG_SP            1036    /* R12 */
+#define _IA64_REG_TP            1037    /* R13 */
+
+/* Application Registers */
+
+#define _IA64_REG_AR_KR0        3072
+#define _IA64_REG_AR_KR1        3073
+#define _IA64_REG_AR_KR2        3074
+#define _IA64_REG_AR_KR3        3075
+#define _IA64_REG_AR_KR4        3076
+#define _IA64_REG_AR_KR5        3077
+#define _IA64_REG_AR_KR6        3078
+#define _IA64_REG_AR_KR7        3079
+#define _IA64_REG_AR_RSC        3088
+#define _IA64_REG_AR_BSP        3089
+#define _IA64_REG_AR_BSPSTORE   3090
+#define _IA64_REG_AR_RNAT       3091
+#define _IA64_REG_AR_FCR        3093
+#define _IA64_REG_AR_EFLAG      3096
+#define _IA64_REG_AR_CSD        3097
+#define _IA64_REG_AR_SSD        3098
+#define _IA64_REG_AR_CFLAG      3099
+#define _IA64_REG_AR_FSR        3100
+#define _IA64_REG_AR_FIR        3101
+#define _IA64_REG_AR_FDR        3102
+#define _IA64_REG_AR_CCV        3104
+#define _IA64_REG_AR_UNAT       3108
+#define _IA64_REG_AR_FPSR       3112
+#define _IA64_REG_AR_ITC        3116
+#define _IA64_REG_AR_PFS        3136
+#define _IA64_REG_AR_LC         3137
+#define _IA64_REG_AR_EC         3138
+
+/* Control Registers */
+
+#define _IA64_REG_CR_DCR        4096
+#define _IA64_REG_CR_ITM        4097
+#define _IA64_REG_CR_IVA        4098
+#define _IA64_REG_CR_PTA        4104
+#define _IA64_REG_CR_IPSR       4112
+#define _IA64_REG_CR_ISR        4113
+#define _IA64_REG_CR_IIP        4115
+#define _IA64_REG_CR_IFA        4116
+#define _IA64_REG_CR_ITIR       4117
+#define _IA64_REG_CR_IIPA       4118
+#define _IA64_REG_CR_IFS        4119
+#define _IA64_REG_CR_IIM        4120
+#define _IA64_REG_CR_IHA        4121
+#define _IA64_REG_CR_LID        4160
+#define _IA64_REG_CR_IVR        4161    /* getreg only */
+#define _IA64_REG_CR_TPR        4162
+#define _IA64_REG_CR_EOI        4163
+#define _IA64_REG_CR_IRR0       4164    /* getreg only */
+#define _IA64_REG_CR_IRR1       4165    /* getreg only */
+#define _IA64_REG_CR_IRR2       4166    /* getreg only */
+#define _IA64_REG_CR_IRR3       4167    /* getreg only */
+#define _IA64_REG_CR_ITV        4168
+#define _IA64_REG_CR_PMV        4169
+#define _IA64_REG_CR_CMCV       4170
+#define _IA64_REG_CR_LRR0       4176
+#define _IA64_REG_CR_LRR1       4177
+
+/* Indirect Registers for getindreg() and setindreg() */
+
+#define _IA64_REG_INDR_CPUID    9000    /* getindreg only */
+#define _IA64_REG_INDR_DBR      9001
+#define _IA64_REG_INDR_IBR      9002
+#define _IA64_REG_INDR_PKR      9003
+#define _IA64_REG_INDR_PMC      9004
+#define _IA64_REG_INDR_PMD      9005
+#define _IA64_REG_INDR_RR       9006
+
+#endif /* _ASM_IA64_IA64REGS_H */
diff --git a/arch/ia64/include/asm/intel_intrin.h b/arch/ia64/include/asm/intel_intrin.h
new file mode 100644
index 000000000000..53cec577558a
--- /dev/null
+++ b/arch/ia64/include/asm/intel_intrin.h
@@ -0,0 +1,161 @@
+#ifndef _ASM_IA64_INTEL_INTRIN_H
+#define _ASM_IA64_INTEL_INTRIN_H
+/*
+ * Intel Compiler Intrinsics
+ *
+ * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
+ * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
+ * Copyright (C) 2005,2006 Hongjiu Lu <hongjiu.lu@intel.com>
+ *
+ */
+#include <ia64intrin.h>
+
+#define ia64_barrier()          __memory_barrier()
+
+#define ia64_stop()     /* Nothing: As of now stop bit is generated for each
+                         * intrinsic
+                         */
+
+#define ia64_native_getreg      __getReg
+#define ia64_native_setreg      __setReg
+
+#define ia64_hint               __hint
+#define ia64_hint_pause         __hint_pause
+
+#define ia64_mux1_brcst         _m64_mux1_brcst
+#define ia64_mux1_mix           _m64_mux1_mix
+#define ia64_mux1_shuf          _m64_mux1_shuf
+#define ia64_mux1_alt           _m64_mux1_alt
+#define ia64_mux1_rev           _m64_mux1_rev
+
+#define ia64_mux1(x,v)          _m_to_int64(_m64_mux1(_m_from_int64(x), (v)))
+#define ia64_popcnt             _m64_popcnt
+#define ia64_getf_exp           __getf_exp
+#define ia64_shrp               _m64_shrp
+
+#define ia64_tpa                __tpa
+#define ia64_invala             __invala
+#define ia64_invala_gr          __invala_gr
+#define ia64_invala_fr          __invala_fr
+#define ia64_nop                __nop
+#define ia64_sum                __sum
+#define ia64_native_ssm         __ssm
+#define ia64_rum                __rum
+#define ia64_native_rsm         __rsm
+#define ia64_native_fc          __fc
+
+#define ia64_ldfs               __ldfs
+#define ia64_ldfd               __ldfd
+#define ia64_ldfe               __ldfe
+#define ia64_ldf8               __ldf8
+#define ia64_ldf_fill           __ldf_fill
+
+#define ia64_stfs               __stfs
+#define ia64_stfd               __stfd
+#define ia64_stfe               __stfe
+#define ia64_stf8               __stf8
+#define ia64_stf_spill          __stf_spill
+
+#define ia64_mf                 __mf
+#define ia64_mfa                __mfa
+
+#define ia64_fetchadd4_acq      __fetchadd4_acq
+#define ia64_fetchadd4_rel      __fetchadd4_rel
+#define ia64_fetchadd8_acq      __fetchadd8_acq
+#define ia64_fetchadd8_rel      __fetchadd8_rel
+
+#define ia64_xchg1              _InterlockedExchange8
+#define ia64_xchg2              _InterlockedExchange16
+#define ia64_xchg4              _InterlockedExchange
+#define ia64_xchg8              _InterlockedExchange64
+
+#define ia64_cmpxchg1_rel       _InterlockedCompareExchange8_rel
+#define ia64_cmpxchg1_acq       _InterlockedCompareExchange8_acq
+#define ia64_cmpxchg2_rel       _InterlockedCompareExchange16_rel
+#define ia64_cmpxchg2_acq       _InterlockedCompareExchange16_acq
+#define ia64_cmpxchg4_rel       _InterlockedCompareExchange_rel
+#define ia64_cmpxchg4_acq       _InterlockedCompareExchange_acq
+#define ia64_cmpxchg8_rel       _InterlockedCompareExchange64_rel
+#define ia64_cmpxchg8_acq       _InterlockedCompareExchange64_acq
+
+#define __ia64_set_dbr(index, val)      \
+                __setIndReg(_IA64_REG_INDR_DBR, index, val)
+#define ia64_set_ibr(index, val)        \
+                __setIndReg(_IA64_REG_INDR_IBR, index, val)
+#define ia64_set_pkr(index, val)        \
+                __setIndReg(_IA64_REG_INDR_PKR, index, val)
+#define ia64_set_pmc(index, val)        \
+                __setIndReg(_IA64_REG_INDR_PMC, index, val)
+#define ia64_set_pmd(index, val)        \
+                __setIndReg(_IA64_REG_INDR_PMD, index, val)
+#define ia64_native_set_rr(index, val)  \
+                __setIndReg(_IA64_REG_INDR_RR, index, val)
+
+#define ia64_native_get_cpuid(index)    \
+                __getIndReg(_IA64_REG_INDR_CPUID, index)
+#define __ia64_get_dbr(index)           __getIndReg(_IA64_REG_INDR_DBR, index)
+#define ia64_get_ibr(index)             __getIndReg(_IA64_REG_INDR_IBR, index)
+#define ia64_get_pkr(index)             __getIndReg(_IA64_REG_INDR_PKR, index)
+#define ia64_get_pmc(index)             __getIndReg(_IA64_REG_INDR_PMC, index)
+#define ia64_native_get_pmd(index)      __getIndReg(_IA64_REG_INDR_PMD, index)
+#define ia64_native_get_rr(index)       __getIndReg(_IA64_REG_INDR_RR, index)
+
+#define ia64_srlz_d             __dsrlz
+#define ia64_srlz_i             __isrlz
+
+#define ia64_dv_serialize_data()
+#define ia64_dv_serialize_instruction()
+
+#define ia64_st1_rel            __st1_rel
+#define ia64_st2_rel            __st2_rel
+#define ia64_st4_rel            __st4_rel
+#define ia64_st8_rel            __st8_rel
+
+/* FIXME: need st4.rel.nta intrinsic */
+#define ia64_st4_rel_nta        __st4_rel
+
+#define ia64_ld1_acq            __ld1_acq
+#define ia64_ld2_acq            __ld2_acq
+#define ia64_ld4_acq            __ld4_acq
+#define ia64_ld8_acq            __ld8_acq
+
+#define ia64_sync_i             __synci
+#define ia64_native_thash       __thash
+#define ia64_native_ttag        __ttag
+#define ia64_itcd               __itcd
+#define ia64_itci               __itci
+#define ia64_itrd               __itrd
+#define ia64_itri               __itri
+#define ia64_ptce               __ptce
+#define ia64_ptcl               __ptcl
+#define ia64_native_ptcg        __ptcg
+#define ia64_native_ptcga       __ptcga
+#define ia64_ptri               __ptri
+#define ia64_ptrd               __ptrd
+#define ia64_dep_mi             _m64_dep_mi
+
+/* Values for lfhint in __lfetch and __lfetch_fault */
+
+#define ia64_lfhint_none        __lfhint_none
+#define ia64_lfhint_nt1         __lfhint_nt1
+#define ia64_lfhint_nt2         __lfhint_nt2
+#define ia64_lfhint_nta         __lfhint_nta
+
+#define ia64_lfetch             __lfetch
+#define ia64_lfetch_excl        __lfetch_excl
+#define ia64_lfetch_fault       __lfetch_fault
+#define ia64_lfetch_fault_excl  __lfetch_fault_excl
+
+#define ia64_native_intrin_local_irq_restore(x)         \
+do {                                                    \
+        if ((x) != 0) {                                 \
+                ia64_native_ssm(IA64_PSR_I);            \
+                ia64_srlz_d();                          \
+        } else {                                        \
+                ia64_native_rsm(IA64_PSR_I);            \
+        }                                               \
+} while (0)
+
+#define __builtin_trap()        __break(0);
+
+#endif /* _ASM_IA64_INTEL_INTRIN_H */
diff --git a/arch/ia64/include/asm/intrinsics.h b/arch/ia64/include/asm/intrinsics.h
new file mode 100644
index 000000000000..47d686dba1eb
--- /dev/null
+++ b/arch/ia64/include/asm/intrinsics.h
@@ -0,0 +1,241 @@
+#ifndef _ASM_IA64_INTRINSICS_H
+#define _ASM_IA64_INTRINSICS_H
+
+/*
+ * Compiler-dependent intrinsics.
+ *
+ * Copyright (C) 2002-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#ifndef __ASSEMBLY__
+
+/* include compiler specific intrinsics */
+#include <asm/ia64regs.h>
+#ifdef __INTEL_COMPILER
+# include <asm/intel_intrin.h>
+#else
+# include <asm/gcc_intrin.h>
+#endif
+
+#define ia64_native_get_psr_i() (ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I)
+
+#define ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4)        \
+do {                                                                    \
+        ia64_native_set_rr(0x0000000000000000UL, (val0));               \
+        ia64_native_set_rr(0x2000000000000000UL, (val1));               \
+        ia64_native_set_rr(0x4000000000000000UL, (val2));               \
+        ia64_native_set_rr(0x6000000000000000UL, (val3));               \
+        ia64_native_set_rr(0x8000000000000000UL, (val4));               \
+} while (0)
+
+/*
+ * Force an unresolved reference if someone tries to use
+ * ia64_fetch_and_add() with a bad value.
+ */
+extern unsigned long __bad_size_for_ia64_fetch_and_add (void);
+extern unsigned long __bad_increment_for_ia64_fetch_and_add (void);
+
+#define IA64_FETCHADD(tmp,v,n,sz,sem)                                           \
+({                                                                              \
+        switch (sz) {                                                           \
+              case 4:                                                           \
+                tmp = ia64_fetchadd4_##sem((unsigned int *) v, n);              \
+                break;                                                          \
+                                                                                \
+              case 8:                                                           \
+                tmp = ia64_fetchadd8_##sem((unsigned long *) v, n);             \
+                break;                                                          \
+                                                                                \
+              default:                                                          \
+                __bad_size_for_ia64_fetch_and_add();                            \
+        }                                                                       \
+})
+
+#define ia64_fetchadd(i,v,sem)                                                          \
+({                                                                                      \
+        __u64 _tmp;                                                                     \
+        volatile __typeof__(*(v)) *_v = (v);                                            \
+        /* Can't use a switch () here: gcc isn't always smart enough for that... */     \
+        if ((i) == -16)                                                                 \
+                IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v)), sem);                        \
+        else if ((i) == -8)                                                             \
+                IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v)), sem);                         \
+        else if ((i) == -4)                                                             \
+                IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v)), sem);                         \
+        else if ((i) == -1)                                                             \
+                IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v)), sem);                         \
+        else if ((i) == 1)                                                              \
+                IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v)), sem);                          \
+        else if ((i) == 4)                                                              \
+                IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v)), sem);                          \
+        else if ((i) == 8)                                                              \
+                IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v)), sem);                          \
+        else if ((i) == 16)                                                             \
+                IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v)), sem);                         \
+        else                                                                            \
+                _tmp = __bad_increment_for_ia64_fetch_and_add();                        \
+        (__typeof__(*(v))) (_tmp);      /* return old value */                          \
+})
+
+#define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */
+
+/*
+ * This function doesn't exist, so you'll get a linker error if
+ * something tries to do an invalid xchg().
+ */
+extern void ia64_xchg_called_with_bad_pointer (void);
+
+#define __xchg(x,ptr,size)                                              \
+({                                                                      \
+        unsigned long __xchg_result;                                    \
+                                                                        \
+        switch (size) {                                                 \
+              case 1:                                                   \
+                __xchg_result = ia64_xchg1((__u8 *)ptr, x);             \
+                break;                                                  \
+                                                                        \
+              case 2:                                                   \
+                __xchg_result = ia64_xchg2((__u16 *)ptr, x);            \
+                break;                                                  \
+                                                                        \
+              case 4:                                                   \
+                __xchg_result = ia64_xchg4((__u32 *)ptr, x);            \
+                break;                                                  \
+                                                                        \
+              case 8:                                                   \
+                __xchg_result = ia64_xchg8((__u64 *)ptr, x);            \
+                break;                                                  \
+              default:                                                  \
+                ia64_xchg_called_with_bad_pointer();                    \
+        }                                                               \
+        __xchg_result;                                                  \
+})
+
+#define xchg(ptr,x)                                                          \
+  ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr))))
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern long ia64_cmpxchg_called_with_bad_pointer (void);
+
+#define ia64_cmpxchg(sem,ptr,old,new,size)                                              \
+({                                                                                      \
+        __u64 _o_, _r_;                                                                 \
+                                                                                        \
+        switch (size) {                                                                 \
+              case 1: _o_ = (__u8 ) (long) (old); break;                                \
+              case 2: _o_ = (__u16) (long) (old); break;                                \
+              case 4: _o_ = (__u32) (long) (old); break;                                \
+              case 8: _o_ = (__u64) (long) (old); break;                                \
+              default: break;                                                           \
+        }                                                                               \
+        switch (size) {                                                                 \
+              case 1:                                                                   \
+                _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_);                      \
+                break;                                                                  \
+                                                                                        \
+              case 2:                                                                   \
+               _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_);                      \
+                break;                                                                  \
+                                                                                        \
+              case 4:                                                                   \
+                _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_);                     \
+                break;                                                                  \
+                                                                                        \
+              case 8:                                                                   \
+                _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_);                     \
+                break;                                                                  \
+                                                                                        \
+              default:                                                                  \
+                _r_ = ia64_cmpxchg_called_with_bad_pointer();                           \
+                break;                                                                  \
+        }                                                                               \
+        (__typeof__(old)) _r_;                                                          \
+})
+
+#define cmpxchg_acq(ptr, o, n)  \
+        ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr)))
+#define cmpxchg_rel(ptr, o, n)  \
+        ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr)))
+
+/* for compatibility with other platforms: */
+#define cmpxchg(ptr, o, n)      cmpxchg_acq((ptr), (o), (n))
+#define cmpxchg64(ptr, o, n)    cmpxchg_acq((ptr), (o), (n))
+
+#define cmpxchg_local           cmpxchg
+#define cmpxchg64_local         cmpxchg64
+
+#ifdef CONFIG_IA64_DEBUG_CMPXCHG
+# define CMPXCHG_BUGCHECK_DECL  int _cmpxchg_bugcheck_count = 128;
+# define CMPXCHG_BUGCHECK(v)                                                    \
+  do {                                                                          \
+        if (_cmpxchg_bugcheck_count-- <= 0) {                                   \
+                void *ip;                                                       \
+                extern int printk(const char *fmt, ...);                        \
+                ip = (void *) ia64_getreg(_IA64_REG_IP);                        \
+                printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v));  \
+                break;                                                          \
+        }                                                                       \
+  } while (0)
+#else /* !CONFIG_IA64_DEBUG_CMPXCHG */
+# define CMPXCHG_BUGCHECK_DECL
+# define CMPXCHG_BUGCHECK(v)
+#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */
+
+#endif
+
+#ifdef __KERNEL__
+#include <asm/paravirt_privop.h>
+#endif
+
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_PARAVIRT) && defined(__KERNEL__)
+#define IA64_INTRINSIC_API(name)        pv_cpu_ops.name
+#define IA64_INTRINSIC_MACRO(name)      paravirt_ ## name
+#else
+#define IA64_INTRINSIC_API(name)        ia64_native_ ## name
+#define IA64_INTRINSIC_MACRO(name)      ia64_native_ ## name
+#endif
+
+/************************************************/
+/* Instructions paravirtualized for correctness */
+/************************************************/
+/* fc, thash, get_cpuid, get_pmd, get_eflags, set_eflags */
+/* Note that "ttag" and "cover" are also privilege-sensitive; "ttag"
+ * is not currently used (though it may be in a long-format VHPT system!)
+ */
+#define ia64_fc                         IA64_INTRINSIC_API(fc)
+#define ia64_thash                      IA64_INTRINSIC_API(thash)
+#define ia64_get_cpuid                  IA64_INTRINSIC_API(get_cpuid)
+#define ia64_get_pmd                    IA64_INTRINSIC_API(get_pmd)
+
+
+/************************************************/
+/* Instructions paravirtualized for performance */
+/************************************************/
+#define ia64_ssm                        IA64_INTRINSIC_MACRO(ssm)
+#define ia64_rsm                        IA64_INTRINSIC_MACRO(rsm)
+#define ia64_getreg                     IA64_INTRINSIC_API(getreg)
+#define ia64_setreg                     IA64_INTRINSIC_API(setreg)
+#define ia64_set_rr                     IA64_INTRINSIC_API(set_rr)
+#define ia64_get_rr                     IA64_INTRINSIC_API(get_rr)
+#define ia64_ptcga                      IA64_INTRINSIC_API(ptcga)
+#define ia64_get_psr_i                  IA64_INTRINSIC_API(get_psr_i)
+#define ia64_intrin_local_irq_restore   \
+        IA64_INTRINSIC_API(intrin_local_irq_restore)
+#define ia64_set_rr0_to_rr4             IA64_INTRINSIC_API(set_rr0_to_rr4)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_IA64_INTRINSICS_H */
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
new file mode 100644
index 000000000000..260a85ac9d6a
--- /dev/null
+++ b/arch/ia64/include/asm/io.h
@@ -0,0 +1,459 @@
+#ifndef _ASM_IA64_IO_H
+#define _ASM_IA64_IO_H
+
+/*
+ * This file contains the definitions for the emulated IO instructions
+ * inb/inw/inl/outb/outw/outl and the "string versions" of the same
+ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
+ * versions of the single-IO instructions (inb_p/inw_p/..).
+ *
+ * This file is not meant to be obfuscating: it's just complicated to
+ * (a) handle it all in a way that makes gcc able to optimize it as
+ * well as possible and (b) trying to avoid writing the same thing
+ * over and over again with slight variations and possibly making a
+ * mistake somewhere.
+ *
+ * Copyright (C) 1998-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
+ * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
+ */
+
+/* We don't use IO slowdowns on the ia64, but.. */
+#define __SLOW_DOWN_IO  do { } while (0)
+#define SLOW_DOWN_IO    do { } while (0)
+
+#define __IA64_UNCACHED_OFFSET  RGN_BASE(RGN_UNCACHED)
+
+/*
+ * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
+ * large machines may have multiple other I/O spaces so we can't place any a priori limit
+ * on IO_SPACE_LIMIT.  These additional spaces are described in ACPI.
+ */
+#define IO_SPACE_LIMIT          0xffffffffffffffffUL
+
+#define MAX_IO_SPACES_BITS              8
+#define MAX_IO_SPACES                   (1UL << MAX_IO_SPACES_BITS)
+#define IO_SPACE_BITS                   24
+#define IO_SPACE_SIZE                   (1UL << IO_SPACE_BITS)
+
+#define IO_SPACE_NR(port)               ((port) >> IO_SPACE_BITS)
+#define IO_SPACE_BASE(space)            ((space) << IO_SPACE_BITS)
+#define IO_SPACE_PORT(port)             ((port) & (IO_SPACE_SIZE - 1))
+
+#define IO_SPACE_SPARSE_ENCODING(p)     ((((p) >> 2) << 12) | ((p) & 0xfff))
+
+struct io_space {
+        unsigned long mmio_base;        /* base in MMIO space */
+        int sparse;
+};
+
+extern struct io_space io_space[];
+extern unsigned int num_io_spaces;
+
+# ifdef __KERNEL__
+
+/*
+ * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
+ *      0xCxxxxxxxxxxxxxxx      MMIO cookie (return from ioremap)
+ *      0x000000001SPPPPPP      PIO cookie (S=space number, P..P=port)
+ *
+ * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
+ * code that uses bare port numbers without the prerequisite pci_iomap().
+ */
+#define PIO_OFFSET              (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
+#define PIO_MASK                (PIO_OFFSET - 1)
+#define PIO_RESERVED            __IA64_UNCACHED_OFFSET
+#define HAVE_ARCH_PIO_SIZE
+
+#include <asm/intrinsics.h>
+#include <asm/machvec.h>
+#include <asm/page.h>
+#include <asm/system.h>
+#include <asm-generic/iomap.h>
+
+/*
+ * Change virtual addresses to physical addresses and vv.
+ */
+static inline unsigned long
+virt_to_phys (volatile void *address)
+{
+        return (unsigned long) address - PAGE_OFFSET;
+}
+
+static inline void*
+phys_to_virt (unsigned long address)
+{
+        return (void *) (address + PAGE_OFFSET);
+}
+
+#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
+extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
+extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */
+extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);
+
+/*
+ * The following two macros are deprecated and scheduled for removal.
+ * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
+ */
+#define bus_to_virt     phys_to_virt
+#define virt_to_bus     virt_to_phys
+#define page_to_bus     page_to_phys
+
+# endif /* KERNEL */
+
+/*
+ * Memory fence w/accept.  This should never be used in code that is
+ * not IA-64 specific.
+ */
+#define __ia64_mf_a()   ia64_mfa()
+
+/**
+ * ___ia64_mmiowb - I/O write barrier
+ *
+ * Ensure ordering of I/O space writes.  This will make sure that writes
+ * following the barrier will arrive after all previous writes.  For most
+ * ia64 platforms, this is a simple 'mf.a' instruction.
+ *
+ * See Documentation/DocBook/deviceiobook.tmpl for more information.
+ */
+static inline void ___ia64_mmiowb(void)
+{
+        ia64_mfa();
+}
+
+static inline void*
+__ia64_mk_io_addr (unsigned long port)
+{
+        struct io_space *space;
+        unsigned long offset;
+
+        space = &io_space[IO_SPACE_NR(port)];
+        port = IO_SPACE_PORT(port);
+        if (space->sparse)
+                offset = IO_SPACE_SPARSE_ENCODING(port);
+        else
+                offset = port;
+
+        return (void *) (space->mmio_base | offset);
+}
+
+#define __ia64_inb      ___ia64_inb
+#define __ia64_inw      ___ia64_inw
+#define __ia64_inl      ___ia64_inl
+#define __ia64_outb     ___ia64_outb
+#define __ia64_outw     ___ia64_outw
+#define __ia64_outl     ___ia64_outl
+#define __ia64_readb    ___ia64_readb
+#define __ia64_readw    ___ia64_readw
+#define __ia64_readl    ___ia64_readl
+#define __ia64_readq    ___ia64_readq
+#define __ia64_readb_relaxed    ___ia64_readb
+#define __ia64_readw_relaxed    ___ia64_readw
+#define __ia64_readl_relaxed    ___ia64_readl
+#define __ia64_readq_relaxed    ___ia64_readq
+#define __ia64_writeb   ___ia64_writeb
+#define __ia64_writew   ___ia64_writew
+#define __ia64_writel   ___ia64_writel
+#define __ia64_writeq   ___ia64_writeq
+#define __ia64_mmiowb   ___ia64_mmiowb
+
+/*
+ * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
+ * that the access has completed before executing other I/O accesses.  Since we're doing
+ * the accesses through an uncachable (UC) translation, the CPU will execute them in
+ * program order.  However, we still need to tell the compiler not to shuffle them around
+ * during optimization, which is why we use "volatile" pointers.
+ */
+
+static inline unsigned int
+___ia64_inb (unsigned long port)
+{
+        volatile unsigned char *addr = __ia64_mk_io_addr(port);
+        unsigned char ret;
+
+        ret = *addr;
+        __ia64_mf_a();
+        return ret;
+}
+
+static inline unsigned int
+___ia64_inw (unsigned long port)
+{
+        volatile unsigned short *addr = __ia64_mk_io_addr(port);
+        unsigned short ret;
+
+        ret = *addr;
+        __ia64_mf_a();
+        return ret;
+}
+
+static inline unsigned int
+___ia64_inl (unsigned long port)
+{
+        volatile unsigned int *addr = __ia64_mk_io_addr(port);
+        unsigned int ret;
+
+        ret = *addr;
+        __ia64_mf_a();
+        return ret;
+}
+
+static inline void
+___ia64_outb (unsigned char val, unsigned long port)
+{
+        volatile unsigned char *addr = __ia64_mk_io_addr(port);
+
+        *addr = val;
+        __ia64_mf_a();
+}
+
+static inline void
+___ia64_outw (unsigned short val, unsigned long port)
+{
+        volatile unsigned short *addr = __ia64_mk_io_addr(port);
+
+        *addr = val;
+        __ia64_mf_a();
+}
+
+static inline void
+___ia64_outl (unsigned int val, unsigned long port)
+{
+        volatile unsigned int *addr = __ia64_mk_io_addr(port);
+
+        *addr = val;
+        __ia64_mf_a();
+}
+
+static inline void
+__insb (unsigned long port, void *dst, unsigned long count)
+{
+        unsigned char *dp = dst;
+
+        while (count--)
+                *dp++ = platform_inb(port);
+}
+
+static inline void
+__insw (unsigned long port, void *dst, unsigned long count)
+{
+        unsigned short *dp = dst;
+
+        while (count--)
+                *dp++ = platform_inw(port);
+}
+
+static inline void
+__insl (unsigned long port, void *dst, unsigned long count)
+{
+        unsigned int *dp = dst;
+
+        while (count--)
+                *dp++ = platform_inl(port);
+}
+
+static inline void
+__outsb (unsigned long port, const void *src, unsigned long count)
+{
+        const unsigned char *sp = src;
+
+        while (count--)
+                platform_outb(*sp++, port);
+}
+
+static inline void
+__outsw (unsigned long port, const void *src, unsigned long count)
+{
+        const unsigned short *sp = src;
+
+        while (count--)
+                platform_outw(*sp++, port);
+}
+
+static inline void
+__outsl (unsigned long port, const void *src, unsigned long count)
+{
+        const unsigned int *sp = src;
+
+        while (count--)
+                platform_outl(*sp++, port);
+}
+
+/*
+ * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
+ * specification regarding legacy I/O support.  Thus, we have to make these operations
+ * platform dependent...
+ */
+#define __inb           platform_inb
+#define __inw           platform_inw
+#define __inl           platform_inl
+#define __outb          platform_outb
+#define __outw          platform_outw
+#define __outl          platform_outl
+#define __mmiowb        platform_mmiowb
+
+#define inb(p)          __inb(p)
+#define inw(p)          __inw(p)
+#define inl(p)          __inl(p)
+#define insb(p,d,c)     __insb(p,d,c)
+#define insw(p,d,c)     __insw(p,d,c)
+#define insl(p,d,c)     __insl(p,d,c)
+#define outb(v,p)       __outb(v,p)
+#define outw(v,p)       __outw(v,p)
+#define outl(v,p)       __outl(v,p)
+#define outsb(p,s,c)    __outsb(p,s,c)
+#define outsw(p,s,c)    __outsw(p,s,c)
+#define outsl(p,s,c)    __outsl(p,s,c)
+#define mmiowb()        __mmiowb()
+
+/*
+ * The address passed to these functions are ioremap()ped already.
+ *
+ * We need these to be machine vectors since some platforms don't provide
+ * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
+ * a good idea).  Writes are ok though for all existing ia64 platforms (and
+ * hopefully it'll stay that way).
+ */
+static inline unsigned char
+___ia64_readb (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned char __force *)addr;
+}
+
+static inline unsigned short
+___ia64_readw (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned short __force *)addr;
+}
+
+static inline unsigned int
+___ia64_readl (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned int __force *) addr;
+}
+
+static inline unsigned long
+___ia64_readq (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned long __force *) addr;
+}
+
+static inline void
+__writeb (unsigned char val, volatile void __iomem *addr)
+{
+        *(volatile unsigned char __force *) addr = val;
+}
+
+static inline void
+__writew (unsigned short val, volatile void __iomem *addr)
+{
+        *(volatile unsigned short __force *) addr = val;
+}
+
+static inline void
+__writel (unsigned int val, volatile void __iomem *addr)
+{
+        *(volatile unsigned int __force *) addr = val;
+}
+
+static inline void
+__writeq (unsigned long val, volatile void __iomem *addr)
+{
+        *(volatile unsigned long __force *) addr = val;
+}
+
+#define __readb         platform_readb
+#define __readw         platform_readw
+#define __readl         platform_readl
+#define __readq         platform_readq
+#define __readb_relaxed platform_readb_relaxed
+#define __readw_relaxed platform_readw_relaxed
+#define __readl_relaxed platform_readl_relaxed
+#define __readq_relaxed platform_readq_relaxed
+
+#define readb(a)        __readb((a))
+#define readw(a)        __readw((a))
+#define readl(a)        __readl((a))
+#define readq(a)        __readq((a))
+#define readb_relaxed(a)        __readb_relaxed((a))
+#define readw_relaxed(a)        __readw_relaxed((a))
+#define readl_relaxed(a)        __readl_relaxed((a))
+#define readq_relaxed(a)        __readq_relaxed((a))
+#define __raw_readb     readb
+#define __raw_readw     readw
+#define __raw_readl     readl
+#define __raw_readq     readq
+#define __raw_readb_relaxed     readb_relaxed
+#define __raw_readw_relaxed     readw_relaxed
+#define __raw_readl_relaxed     readl_relaxed
+#define __raw_readq_relaxed     readq_relaxed
+#define writeb(v,a)     __writeb((v), (a))
+#define writew(v,a)     __writew((v), (a))
+#define writel(v,a)     __writel((v), (a))
+#define writeq(v,a)     __writeq((v), (a))
+#define __raw_writeb    writeb
+#define __raw_writew    writew
+#define __raw_writel    writel
+#define __raw_writeq    writeq
+
+#ifndef inb_p
+# define inb_p          inb
+#endif
+#ifndef inw_p
+# define inw_p          inw
+#endif
+#ifndef inl_p
+# define inl_p          inl
+#endif
+
+#ifndef outb_p
+# define outb_p         outb
+#endif
+#ifndef outw_p
+# define outw_p         outw
+#endif
+#ifndef outl_p
+# define outl_p         outl
+#endif
+
+# ifdef __KERNEL__
+
+extern void __iomem * ioremap(unsigned long offset, unsigned long size);
+extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
+extern void iounmap (volatile void __iomem *addr);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
+extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
+extern void memset_io(volatile void __iomem *s, int c, long n);
+
+# endif /* __KERNEL__ */
+
+/*
+ * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing.  It is said that
+ * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
+ * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
+ * SPECweb-like workloads on zx1-based machines.  Thus, for now we favor I/O MMU bypassing
+ * over BIO-level virtual merging.
+ */
+extern unsigned long ia64_max_iommu_merge_mask;
+#if 1
+#define BIO_VMERGE_BOUNDARY     0
+#else
+/*
+ * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here.  Should be
+ * replaced by dma_merge_mask() or something of that sort.  Note: the only way
+ * BIO_VMERGE_BOUNDARY is used is to mask off bits.  Effectively, our definition gets
+ * expanded into:
+ *
+ *      addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
+ *
+ * which is precisely what we want.
+ */
+#define BIO_VMERGE_BOUNDARY     (ia64_max_iommu_merge_mask + 1)
+#endif
+
+#endif /* _ASM_IA64_IO_H */
diff --git a/arch/ia64/include/asm/ioctl.h b/arch/ia64/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/ia64/include/asm/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/arch/ia64/include/asm/ioctls.h b/arch/ia64/include/asm/ioctls.h
new file mode 100644
index 000000000000..f41b636a0bf6
--- /dev/null
+++ b/arch/ia64/include/asm/ioctls.h
@@ -0,0 +1,93 @@
+#ifndef _ASM_IA64_IOCTLS_H
+#define _ASM_IA64_IOCTLS_H
+
+/*
+ * Based on <asm-i386/ioctls.h>
+ *
+ * Modified 1998, 1999, 2002
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#include <asm/ioctl.h>
+
+/* 0x54 is just a magic number to make these relatively unique ('T') */
+
+#define TCGETS          0x5401
+#define TCSETS          0x5402  /* Clashes with SNDCTL_TMR_START sound ioctl */
+#define TCSETSW         0x5403
+#define TCSETSF         0x5404
+#define TCGETA          0x5405
+#define TCSETA          0x5406
+#define TCSETAW         0x5407
+#define TCSETAF         0x5408
+#define TCSBRK          0x5409
+#define TCXONC          0x540A
+#define TCFLSH          0x540B
+#define TIOCEXCL        0x540C
+#define TIOCNXCL        0x540D
+#define TIOCSCTTY       0x540E
+#define TIOCGPGRP       0x540F
+#define TIOCSPGRP       0x5410
+#define TIOCOUTQ        0x5411
+#define TIOCSTI         0x5412
+#define TIOCGWINSZ      0x5413
+#define TIOCSWINSZ      0x5414
+#define TIOCMGET        0x5415
+#define TIOCMBIS        0x5416
+#define TIOCMBIC        0x5417
+#define TIOCMSET        0x5418
+#define TIOCGSOFTCAR    0x5419
+#define TIOCSSOFTCAR    0x541A
+#define FIONREAD        0x541B
+#define TIOCINQ         FIONREAD
+#define TIOCLINUX       0x541C
+#define TIOCCONS        0x541D
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TIOCPKT         0x5420
+#define FIONBIO         0x5421
+#define TIOCNOTTY       0x5422
+#define TIOCSETD        0x5423
+#define TIOCGETD        0x5424
+#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T',0x2A, struct termios2)
+#define TCSETS2         _IOW('T',0x2B, struct termios2)
+#define TCSETSW2        _IOW('T',0x2C, struct termios2)
+#define TCSETSF2        _IOW('T',0x2D, struct termios2)
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
+#define FIOCLEX         0x5451
+#define FIOASYNC        0x5452
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
+#define TIOCSERGETLSR   0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+#define TIOCGHAYESESP   0x545E  /* Get Hayes ESP configuration */
+#define TIOCSHAYESESP   0x545F  /* Set Hayes ESP configuration */
+#define FIOQSIZE        0x5460
+
+/* Used for packet mode */
+#define TIOCPKT_DATA             0
+#define TIOCPKT_FLUSHREAD        1
+#define TIOCPKT_FLUSHWRITE       2
+#define TIOCPKT_STOP             4
+#define TIOCPKT_START            8
+#define TIOCPKT_NOSTOP          16
+#define TIOCPKT_DOSTOP          32
+
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+#endif /* _ASM_IA64_IOCTLS_H */
diff --git a/arch/ia64/include/asm/iosapic.h b/arch/ia64/include/asm/iosapic.h
new file mode 100644
index 000000000000..b9c102e15f22
--- /dev/null
+++ b/arch/ia64/include/asm/iosapic.h
@@ -0,0 +1,126 @@
+#ifndef __ASM_IA64_IOSAPIC_H
+#define __ASM_IA64_IOSAPIC_H
+
+#define IOSAPIC_REG_SELECT      0x0
+#define IOSAPIC_WINDOW          0x10
+#define IOSAPIC_EOI             0x40
+
+#define IOSAPIC_VERSION         0x1
+
+/*
+ * Redirection table entry
+ */
+#define IOSAPIC_RTE_LOW(i)      (0x10+i*2)
+#define IOSAPIC_RTE_HIGH(i)     (0x11+i*2)
+
+#define IOSAPIC_DEST_SHIFT              16
+
+/*
+ * Delivery mode
+ */
+#define IOSAPIC_DELIVERY_SHIFT          8
+#define IOSAPIC_FIXED                   0x0
+#define IOSAPIC_LOWEST_PRIORITY 0x1
+#define IOSAPIC_PMI                     0x2
+#define IOSAPIC_NMI                     0x4
+#define IOSAPIC_INIT                    0x5
+#define IOSAPIC_EXTINT                  0x7
+
+/*
+ * Interrupt polarity
+ */
+#define IOSAPIC_POLARITY_SHIFT          13
+#define IOSAPIC_POL_HIGH                0
+#define IOSAPIC_POL_LOW         1
+
+/*
+ * Trigger mode
+ */
+#define IOSAPIC_TRIGGER_SHIFT           15
+#define IOSAPIC_EDGE                    0
+#define IOSAPIC_LEVEL                   1
+
+/*
+ * Mask bit
+ */
+
+#define IOSAPIC_MASK_SHIFT              16
+#define IOSAPIC_MASK                    (1<<IOSAPIC_MASK_SHIFT)
+
+#define IOSAPIC_VECTOR_MASK             0xffffff00
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_IOSAPIC
+
+#define NR_IOSAPICS                     256
+
+#ifdef CONFIG_PARAVIRT_GUEST
+#include <asm/paravirt.h>
+#else
+#define iosapic_pcat_compat_init        ia64_native_iosapic_pcat_compat_init
+#define __iosapic_read                  __ia64_native_iosapic_read
+#define __iosapic_write                 __ia64_native_iosapic_write
+#define iosapic_get_irq_chip            ia64_native_iosapic_get_irq_chip
+#endif
+
+extern void __init ia64_native_iosapic_pcat_compat_init(void);
+extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger);
+
+static inline unsigned int
+__ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
+{
+        writel(reg, iosapic + IOSAPIC_REG_SELECT);
+        return readl(iosapic + IOSAPIC_WINDOW);
+}
+
+static inline void
+__ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
+{
+        writel(reg, iosapic + IOSAPIC_REG_SELECT);
+        writel(val, iosapic + IOSAPIC_WINDOW);
+}
+
+static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
+{
+        writel(vector, iosapic + IOSAPIC_EOI);
+}
+
+extern void __init iosapic_system_init (int pcat_compat);
+extern int __devinit iosapic_init (unsigned long address,
+                                    unsigned int gsi_base);
+#ifdef CONFIG_HOTPLUG
+extern int iosapic_remove (unsigned int gsi_base);
+#else
+#define iosapic_remove(gsi_base)                                (-EINVAL)
+#endif /* CONFIG_HOTPLUG */
+extern int gsi_to_irq (unsigned int gsi);
+extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
+                                  unsigned long trigger);
+extern void iosapic_unregister_intr (unsigned int irq);
+extern void __devinit iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
+                                      unsigned long polarity,
+                                      unsigned long trigger);
+extern int __init iosapic_register_platform_intr (u32 int_type,
+                                           unsigned int gsi,
+                                           int pmi_vector,
+                                           u16 eid, u16 id,
+                                           unsigned long polarity,
+                                           unsigned long trigger);
+
+#ifdef CONFIG_NUMA
+extern void __devinit map_iosapic_to_node (unsigned int, int);
+#endif
+#else
+#define iosapic_system_init(pcat_compat)                        do { } while (0)
+#define iosapic_init(address,gsi_base)                          (-EINVAL)
+#define iosapic_remove(gsi_base)                                (-ENODEV)
+#define iosapic_register_intr(gsi,polarity,trigger)             (gsi)
+#define iosapic_unregister_intr(irq)                            do { } while (0)
+#define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger)  do { } while (0)
+#define iosapic_register_platform_intr(type,gsi,pmi,eid,id, \
+        polarity,trigger)                                       (gsi)
+#endif
+
+# endif /* !__ASSEMBLY__ */
+#endif /* __ASM_IA64_IOSAPIC_H */
diff --git a/arch/ia64/include/asm/ipcbuf.h b/arch/ia64/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..079899ae7d32
--- /dev/null
+++ b/arch/ia64/include/asm/ipcbuf.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_IA64_IPCBUF_H
+#define _ASM_IA64_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for IA-64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+        __kernel_mode_t mode;
+        unsigned short  seq;
+        unsigned short  __pad1;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_IA64_IPCBUF_H */
diff --git a/arch/ia64/include/asm/irq.h b/arch/ia64/include/asm/irq.h
new file mode 100644
index 000000000000..3627116fb0e2
--- /dev/null
+++ b/arch/ia64/include/asm/irq.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_IA64_IRQ_H
+#define _ASM_IA64_IRQ_H
+
+/*
+ * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *      Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * 11/24/98     S.Eranian       updated TIMER_IRQ and irq_canonicalize
+ * 01/20/99     S.Eranian       added keyboard interrupt
+ * 02/29/00     D.Mosberger     moved most things into hw_irq.h
+ */
+
+#include <linux/types.h>
+#include <linux/cpumask.h>
+#include <asm-ia64/nr-irqs.h>
+
+static __inline__ int
+irq_canonicalize (int irq)
+{
+        /*
+         * We do the legacy thing here of pretending that irqs < 16
+         * are 8259 irqs.  This really shouldn't be necessary at all,
+         * but we keep it here as serial.c still uses it...
+         */
+        return ((irq == 2) ? 9 : irq);
+}
+
+extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
+bool is_affinity_mask_valid(cpumask_t cpumask);
+
+#define is_affinity_mask_valid is_affinity_mask_valid
+
+#endif /* _ASM_IA64_IRQ_H */
diff --git a/arch/ia64/include/asm/irq_regs.h b/arch/ia64/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/ia64/include/asm/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/arch/ia64/include/asm/kdebug.h b/arch/ia64/include/asm/kdebug.h
new file mode 100644
index 000000000000..d11a69855036
--- /dev/null
+++ b/arch/ia64/include/asm/kdebug.h
@@ -0,0 +1,57 @@
+#ifndef _IA64_KDEBUG_H
+#define _IA64_KDEBUG_H 1
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) Intel Corporation, 2005
+ *
+ * 2005-Apr     Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
+ *              <anil.s.keshavamurthy@intel.com> adopted from
+ *              include/asm-x86_64/kdebug.h
+ *
+ * 2005-Oct     Keith Owens <kaos@sgi.com>.  Expand notify_die to cover more
+ *              events.
+ */
+
+enum die_val {
+        DIE_BREAK = 1,
+        DIE_FAULT,
+        DIE_OOPS,
+        DIE_MACHINE_HALT,
+        DIE_MACHINE_RESTART,
+        DIE_MCA_MONARCH_ENTER,
+        DIE_MCA_MONARCH_PROCESS,
+        DIE_MCA_MONARCH_LEAVE,
+        DIE_MCA_SLAVE_ENTER,
+        DIE_MCA_SLAVE_PROCESS,
+        DIE_MCA_SLAVE_LEAVE,
+        DIE_MCA_RENDZVOUS_ENTER,
+        DIE_MCA_RENDZVOUS_PROCESS,
+        DIE_MCA_RENDZVOUS_LEAVE,
+        DIE_MCA_NEW_TIMEOUT,
+        DIE_INIT_ENTER,
+        DIE_INIT_MONARCH_ENTER,
+        DIE_INIT_MONARCH_PROCESS,
+        DIE_INIT_MONARCH_LEAVE,
+        DIE_INIT_SLAVE_ENTER,
+        DIE_INIT_SLAVE_PROCESS,
+        DIE_INIT_SLAVE_LEAVE,
+        DIE_KDEBUG_ENTER,
+        DIE_KDEBUG_LEAVE,
+        DIE_KDUMP_ENTER,
+        DIE_KDUMP_LEAVE,
+};
+
+#endif
diff --git a/arch/ia64/include/asm/kexec.h b/arch/ia64/include/asm/kexec.h
new file mode 100644
index 000000000000..541be835fc5a
--- /dev/null
+++ b/arch/ia64/include/asm/kexec.h
@@ -0,0 +1,44 @@
+#ifndef _ASM_IA64_KEXEC_H
+#define _ASM_IA64_KEXEC_H
+
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE (8192 + 8192 + 4096)
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_IA_64
+
+#define kexec_flush_icache_page(page) do { \
+                unsigned long page_addr = (unsigned long)page_address(page); \
+                flush_icache_range(page_addr, page_addr + PAGE_SIZE); \
+        } while(0)
+
+extern struct kimage *ia64_kimage;
+extern const unsigned int relocate_new_kernel_size;
+extern void relocate_new_kernel(unsigned long, unsigned long,
+                struct ia64_boot_param *, unsigned long);
+static inline void
+crash_setup_regs(struct pt_regs *newregs, struct pt_regs *oldregs)
+{
+}
+extern struct resource efi_memmap_res;
+extern struct resource boot_param_res;
+extern void kdump_smp_send_stop(void);
+extern void kdump_smp_send_init(void);
+extern void kexec_disable_iosapic(void);
+extern void crash_save_this_cpu(void);
+struct rsvd_region;
+extern unsigned long kdump_find_rsvd_region(unsigned long size,
+                struct rsvd_region *rsvd_regions, int n);
+extern void kdump_cpu_freeze(struct unw_frame_info *info, void *arg);
+extern int kdump_status[];
+extern atomic_t kdump_cpu_freezed;
+extern atomic_t kdump_in_progress;
+
+#endif /* _ASM_IA64_KEXEC_H */
diff --git a/arch/ia64/include/asm/kmap_types.h b/arch/ia64/include/asm/kmap_types.h
new file mode 100644
index 000000000000..5d1658aa2b3b
--- /dev/null
+++ b/arch/ia64/include/asm/kmap_types.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_IA64_KMAP_TYPES_H
+#define _ASM_IA64_KMAP_TYPES_H
+
+
+#ifdef CONFIG_DEBUG_HIGHMEM
+# define D(n) __KM_FENCE_##n ,
+#else
+# define D(n)
+#endif
+
+enum km_type {
+D(0)    KM_BOUNCE_READ,
+D(1)    KM_SKB_SUNRPC_DATA,
+D(2)    KM_SKB_DATA_SOFTIRQ,
+D(3)    KM_USER0,
+D(4)    KM_USER1,
+D(5)    KM_BIO_SRC_IRQ,
+D(6)    KM_BIO_DST_IRQ,
+D(7)    KM_PTE0,
+D(8)    KM_PTE1,
+D(9)    KM_IRQ0,
+D(10)   KM_IRQ1,
+D(11)   KM_SOFTIRQ0,
+D(12)   KM_SOFTIRQ1,
+D(13)   KM_TYPE_NR
+};
+
+#undef D
+
+#endif /* _ASM_IA64_KMAP_TYPES_H */
diff --git a/arch/ia64/include/asm/kprobes.h b/arch/ia64/include/asm/kprobes.h
new file mode 100644
index 000000000000..dbf83fb28db3
--- /dev/null
+++ b/arch/ia64/include/asm/kprobes.h
@@ -0,0 +1,132 @@
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+/*
+ *  Kernel Probes (KProbes)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2004
+ * Copyright (C) Intel Corporation, 2005
+ *
+ * 2005-Apr     Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
+ *              <anil.s.keshavamurthy@intel.com> adapted from i386
+ */
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/percpu.h>
+#include <asm/break.h>
+
+#define __ARCH_WANT_KPROBES_INSN_SLOT
+#define MAX_INSN_SIZE   2       /* last half is for kprobe-booster */
+#define BREAK_INST      (long)(__IA64_BREAK_KPROBE << 6)
+#define NOP_M_INST      (long)(1<<27)
+#define BRL_INST(i1, i2) ((long)((0xcL << 37) | /* brl */ \
+                                (0x1L << 12) |  /* many */ \
+                                (((i1) & 1) << 36) | ((i2) << 13))) /* imm */
+
+typedef union cmp_inst {
+        struct {
+        unsigned long long qp : 6;
+        unsigned long long p1 : 6;
+        unsigned long long c  : 1;
+        unsigned long long r2 : 7;
+        unsigned long long r3 : 7;
+        unsigned long long p2 : 6;
+        unsigned long long ta : 1;
+        unsigned long long x2 : 2;
+        unsigned long long tb : 1;
+        unsigned long long opcode : 4;
+        unsigned long long reserved : 23;
+        }f;
+        unsigned long long l;
+} cmp_inst_t;
+
+struct kprobe;
+
+typedef struct _bundle {
+        struct {
+                unsigned long long template : 5;
+                unsigned long long slot0 : 41;
+                unsigned long long slot1_p0 : 64-46;
+        } quad0;
+        struct {
+                unsigned long long slot1_p1 : 41 - (64-46);
+                unsigned long long slot2 : 41;
+        } quad1;
+} __attribute__((__aligned__(16)))  bundle_t;
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+};
+
+#define MAX_PARAM_RSE_SIZE      (0x60+0x60/0x3f)
+/* per-cpu kprobe control block */
+#define ARCH_PREV_KPROBE_SZ 2
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        struct pt_regs jprobe_saved_regs;
+        unsigned long jprobes_saved_stacked_regs[MAX_PARAM_RSE_SIZE];
+        unsigned long *bsp;
+        unsigned long cfm;
+        atomic_t prev_kprobe_index;
+        struct prev_kprobe prev_kprobe[ARCH_PREV_KPROBE_SZ];
+};
+
+#define kretprobe_blacklist_size 0
+
+#define SLOT0_OPCODE_SHIFT      (37)
+#define SLOT1_p1_OPCODE_SHIFT   (37 - (64-46))
+#define SLOT2_OPCODE_SHIFT      (37)
+
+#define INDIRECT_CALL_OPCODE            (1)
+#define IP_RELATIVE_CALL_OPCODE         (5)
+#define IP_RELATIVE_BRANCH_OPCODE       (4)
+#define IP_RELATIVE_PREDICT_OPCODE      (7)
+#define LONG_BRANCH_OPCODE              (0xC)
+#define LONG_CALL_OPCODE                (0xD)
+#define flush_insn_slot(p)              do { } while (0)
+
+typedef struct kprobe_opcode {
+        bundle_t bundle;
+} kprobe_opcode_t;
+
+struct fnptr {
+        unsigned long ip;
+        unsigned long gp;
+};
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the instruction to be emulated */
+        kprobe_opcode_t *insn;
+ #define INST_FLAG_FIX_RELATIVE_IP_ADDR         1
+ #define INST_FLAG_FIX_BRANCH_REG               2
+ #define INST_FLAG_BREAK_INST                   4
+ #define INST_FLAG_BOOSTABLE                    8
+        unsigned long inst_flag;
+        unsigned short target_br_reg;
+        unsigned short slot;
+};
+
+extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+
+extern void invalidate_stacked_regs(void);
+extern void flush_register_stack(void);
+extern void arch_remove_kprobe(struct kprobe *p);
+
+#endif                          /* _ASM_KPROBES_H */
diff --git a/arch/ia64/include/asm/kregs.h b/arch/ia64/include/asm/kregs.h
new file mode 100644
index 000000000000..aefcdfee7f23
--- /dev/null
+++ b/arch/ia64/include/asm/kregs.h
@@ -0,0 +1,165 @@
+#ifndef _ASM_IA64_KREGS_H
+#define _ASM_IA64_KREGS_H
+
+/*
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+/*
+ * This file defines the kernel register usage convention used by Linux/ia64.
+ */
+
+/*
+ * Kernel registers:
+ */
+#define IA64_KR_IO_BASE         0       /* ar.k0: legacy I/O base address */
+#define IA64_KR_TSSD            1       /* ar.k1: IVE uses this as the TSSD */
+#define IA64_KR_PER_CPU_DATA    3       /* ar.k3: physical per-CPU base */
+#define IA64_KR_CURRENT_STACK   4       /* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */
+#define IA64_KR_FPU_OWNER       5       /* ar.k5: fpu-owner (UP only, at the moment) */
+#define IA64_KR_CURRENT         6       /* ar.k6: "current" task pointer */
+#define IA64_KR_PT_BASE         7       /* ar.k7: page table base address (physical) */
+
+#define _IA64_KR_PASTE(x,y)     x##y
+#define _IA64_KR_PREFIX(n)      _IA64_KR_PASTE(ar.k, n)
+#define IA64_KR(n)              _IA64_KR_PREFIX(IA64_KR_##n)
+
+/*
+ * Translation registers:
+ */
+#define IA64_TR_KERNEL          0       /* itr0, dtr0: maps kernel image (code & data) */
+#define IA64_TR_PALCODE         1       /* itr1: maps PALcode as required by EFI */
+#define IA64_TR_CURRENT_STACK   1       /* dtr1: maps kernel's memory- & register-stacks */
+
+#define IA64_TR_ALLOC_BASE      2       /* itr&dtr: Base of dynamic TR resource*/
+#define IA64_TR_ALLOC_MAX       32      /* Max number for dynamic use*/
+
+/* Processor status register bits: */
+#define IA64_PSR_BE_BIT         1
+#define IA64_PSR_UP_BIT         2
+#define IA64_PSR_AC_BIT         3
+#define IA64_PSR_MFL_BIT        4
+#define IA64_PSR_MFH_BIT        5
+#define IA64_PSR_IC_BIT         13
+#define IA64_PSR_I_BIT          14
+#define IA64_PSR_PK_BIT         15
+#define IA64_PSR_DT_BIT         17
+#define IA64_PSR_DFL_BIT        18
+#define IA64_PSR_DFH_BIT        19
+#define IA64_PSR_SP_BIT         20
+#define IA64_PSR_PP_BIT         21
+#define IA64_PSR_DI_BIT         22
+#define IA64_PSR_SI_BIT         23
+#define IA64_PSR_DB_BIT         24
+#define IA64_PSR_LP_BIT         25
+#define IA64_PSR_TB_BIT         26
+#define IA64_PSR_RT_BIT         27
+/* The following are not affected by save_flags()/restore_flags(): */
+#define IA64_PSR_CPL0_BIT       32
+#define IA64_PSR_CPL1_BIT       33
+#define IA64_PSR_IS_BIT         34
+#define IA64_PSR_MC_BIT         35
+#define IA64_PSR_IT_BIT         36
+#define IA64_PSR_ID_BIT         37
+#define IA64_PSR_DA_BIT         38
+#define IA64_PSR_DD_BIT         39
+#define IA64_PSR_SS_BIT         40
+#define IA64_PSR_RI_BIT         41
+#define IA64_PSR_ED_BIT         43
+#define IA64_PSR_BN_BIT         44
+#define IA64_PSR_IA_BIT         45
+
+/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
+   execve().  Only list flags here that need to be cleared/set for BOTH clone2() and
+   execve().  */
+#define IA64_PSR_BITS_TO_CLEAR  (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \
+                                 IA64_PSR_TB  | IA64_PSR_ID  | IA64_PSR_DA | IA64_PSR_DD | \
+                                 IA64_PSR_SS  | IA64_PSR_ED  | IA64_PSR_IA)
+#define IA64_PSR_BITS_TO_SET    (IA64_PSR_DFH | IA64_PSR_SP)
+
+#define IA64_PSR_BE     (__IA64_UL(1) << IA64_PSR_BE_BIT)
+#define IA64_PSR_UP     (__IA64_UL(1) << IA64_PSR_UP_BIT)
+#define IA64_PSR_AC     (__IA64_UL(1) << IA64_PSR_AC_BIT)
+#define IA64_PSR_MFL    (__IA64_UL(1) << IA64_PSR_MFL_BIT)
+#define IA64_PSR_MFH    (__IA64_UL(1) << IA64_PSR_MFH_BIT)
+#define IA64_PSR_IC     (__IA64_UL(1) << IA64_PSR_IC_BIT)
+#define IA64_PSR_I      (__IA64_UL(1) << IA64_PSR_I_BIT)
+#define IA64_PSR_PK     (__IA64_UL(1) << IA64_PSR_PK_BIT)
+#define IA64_PSR_DT     (__IA64_UL(1) << IA64_PSR_DT_BIT)
+#define IA64_PSR_DFL    (__IA64_UL(1) << IA64_PSR_DFL_BIT)
+#define IA64_PSR_DFH    (__IA64_UL(1) << IA64_PSR_DFH_BIT)
+#define IA64_PSR_SP     (__IA64_UL(1) << IA64_PSR_SP_BIT)
+#define IA64_PSR_PP     (__IA64_UL(1) << IA64_PSR_PP_BIT)
+#define IA64_PSR_DI     (__IA64_UL(1) << IA64_PSR_DI_BIT)
+#define IA64_PSR_SI     (__IA64_UL(1) << IA64_PSR_SI_BIT)
+#define IA64_PSR_DB     (__IA64_UL(1) << IA64_PSR_DB_BIT)
+#define IA64_PSR_LP     (__IA64_UL(1) << IA64_PSR_LP_BIT)
+#define IA64_PSR_TB     (__IA64_UL(1) << IA64_PSR_TB_BIT)
+#define IA64_PSR_RT     (__IA64_UL(1) << IA64_PSR_RT_BIT)
+/* The following are not affected by save_flags()/restore_flags(): */
+#define IA64_PSR_CPL    (__IA64_UL(3) << IA64_PSR_CPL0_BIT)
+#define IA64_PSR_IS     (__IA64_UL(1) << IA64_PSR_IS_BIT)
+#define IA64_PSR_MC     (__IA64_UL(1) << IA64_PSR_MC_BIT)
+#define IA64_PSR_IT     (__IA64_UL(1) << IA64_PSR_IT_BIT)
+#define IA64_PSR_ID     (__IA64_UL(1) << IA64_PSR_ID_BIT)
+#define IA64_PSR_DA     (__IA64_UL(1) << IA64_PSR_DA_BIT)
+#define IA64_PSR_DD     (__IA64_UL(1) << IA64_PSR_DD_BIT)
+#define IA64_PSR_SS     (__IA64_UL(1) << IA64_PSR_SS_BIT)
+#define IA64_PSR_RI     (__IA64_UL(3) << IA64_PSR_RI_BIT)
+#define IA64_PSR_ED     (__IA64_UL(1) << IA64_PSR_ED_BIT)
+#define IA64_PSR_BN     (__IA64_UL(1) << IA64_PSR_BN_BIT)
+#define IA64_PSR_IA     (__IA64_UL(1) << IA64_PSR_IA_BIT)
+
+/* User mask bits: */
+#define IA64_PSR_UM     (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
+
+/* Default Control Register */
+#define IA64_DCR_PP_BIT          0      /* privileged performance monitor default */
+#define IA64_DCR_BE_BIT          1      /* big-endian default */
+#define IA64_DCR_LC_BIT          2      /* ia32 lock-check enable */
+#define IA64_DCR_DM_BIT          8      /* defer TLB miss faults */
+#define IA64_DCR_DP_BIT          9      /* defer page-not-present faults */
+#define IA64_DCR_DK_BIT         10      /* defer key miss faults */
+#define IA64_DCR_DX_BIT         11      /* defer key permission faults */
+#define IA64_DCR_DR_BIT         12      /* defer access right faults */
+#define IA64_DCR_DA_BIT         13      /* defer access bit faults */
+#define IA64_DCR_DD_BIT         14      /* defer debug faults */
+
+#define IA64_DCR_PP     (__IA64_UL(1) << IA64_DCR_PP_BIT)
+#define IA64_DCR_BE     (__IA64_UL(1) << IA64_DCR_BE_BIT)
+#define IA64_DCR_LC     (__IA64_UL(1) << IA64_DCR_LC_BIT)
+#define IA64_DCR_DM     (__IA64_UL(1) << IA64_DCR_DM_BIT)
+#define IA64_DCR_DP     (__IA64_UL(1) << IA64_DCR_DP_BIT)
+#define IA64_DCR_DK     (__IA64_UL(1) << IA64_DCR_DK_BIT)
+#define IA64_DCR_DX     (__IA64_UL(1) << IA64_DCR_DX_BIT)
+#define IA64_DCR_DR     (__IA64_UL(1) << IA64_DCR_DR_BIT)
+#define IA64_DCR_DA     (__IA64_UL(1) << IA64_DCR_DA_BIT)
+#define IA64_DCR_DD     (__IA64_UL(1) << IA64_DCR_DD_BIT)
+
+/* Interrupt Status Register */
+#define IA64_ISR_X_BIT          32      /* execute access */
+#define IA64_ISR_W_BIT          33      /* write access */
+#define IA64_ISR_R_BIT          34      /* read access */
+#define IA64_ISR_NA_BIT         35      /* non-access */
+#define IA64_ISR_SP_BIT         36      /* speculative load exception */
+#define IA64_ISR_RS_BIT         37      /* mandatory register-stack exception */
+#define IA64_ISR_IR_BIT         38      /* invalid register frame exception */
+#define IA64_ISR_CODE_MASK      0xf
+
+#define IA64_ISR_X      (__IA64_UL(1) << IA64_ISR_X_BIT)
+#define IA64_ISR_W      (__IA64_UL(1) << IA64_ISR_W_BIT)
+#define IA64_ISR_R      (__IA64_UL(1) << IA64_ISR_R_BIT)
+#define IA64_ISR_NA     (__IA64_UL(1) << IA64_ISR_NA_BIT)
+#define IA64_ISR_SP     (__IA64_UL(1) << IA64_ISR_SP_BIT)
+#define IA64_ISR_RS     (__IA64_UL(1) << IA64_ISR_RS_BIT)
+#define IA64_ISR_IR     (__IA64_UL(1) << IA64_ISR_IR_BIT)
+
+/* ISR code field for non-access instructions */
+#define IA64_ISR_CODE_TPA       0
+#define IA64_ISR_CODE_FC        1
+#define IA64_ISR_CODE_PROBE     2
+#define IA64_ISR_CODE_TAK       3
+#define IA64_ISR_CODE_LFETCH    4
+#define IA64_ISR_CODE_PROBEF    5
+
+#endif /* _ASM_IA64_kREGS_H */
diff --git a/arch/ia64/include/asm/kvm.h b/arch/ia64/include/asm/kvm.h
new file mode 100644
index 000000000000..f38472ac2267
--- /dev/null
+++ b/arch/ia64/include/asm/kvm.h
@@ -0,0 +1,211 @@
+#ifndef __ASM_IA64_KVM_H
+#define __ASM_IA64_KVM_H
+
+/*
+ * kvm structure definitions  for ia64
+ *
+ * Copyright (C) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+#include <asm/types.h>
+
+#include <linux/ioctl.h>
+
+/* Architectural interrupt line count. */
+#define KVM_NR_INTERRUPTS 256
+
+#define KVM_IOAPIC_NUM_PINS  48
+
+struct kvm_ioapic_state {
+        __u64 base_address;
+        __u32 ioregsel;
+        __u32 id;
+        __u32 irr;
+        __u32 pad;
+        union {
+                __u64 bits;
+                struct {
+                        __u8 vector;
+                        __u8 delivery_mode:3;
+                        __u8 dest_mode:1;
+                        __u8 delivery_status:1;
+                        __u8 polarity:1;
+                        __u8 remote_irr:1;
+                        __u8 trig_mode:1;
+                        __u8 mask:1;
+                        __u8 reserve:7;
+                        __u8 reserved[4];
+                        __u8 dest_id;
+                } fields;
+        } redirtbl[KVM_IOAPIC_NUM_PINS];
+};
+
+#define KVM_IRQCHIP_PIC_MASTER   0
+#define KVM_IRQCHIP_PIC_SLAVE    1
+#define KVM_IRQCHIP_IOAPIC       2
+
+#define KVM_CONTEXT_SIZE        8*1024
+
+struct kvm_fpreg {
+        union {
+                unsigned long bits[2];
+                long double __dummy;    /* force 16-byte alignment */
+        } u;
+};
+
+union context {
+        /* 8K size */
+        char    dummy[KVM_CONTEXT_SIZE];
+        struct {
+                unsigned long       psr;
+                unsigned long       pr;
+                unsigned long       caller_unat;
+                unsigned long       pad;
+                unsigned long       gr[32];
+                unsigned long       ar[128];
+                unsigned long       br[8];
+                unsigned long       cr[128];
+                unsigned long       rr[8];
+                unsigned long       ibr[8];
+                unsigned long       dbr[8];
+                unsigned long       pkr[8];
+                struct kvm_fpreg   fr[128];
+        };
+};
+
+struct thash_data {
+        union {
+                struct {
+                        unsigned long p    :  1; /* 0 */
+                        unsigned long rv1  :  1; /* 1 */
+                        unsigned long ma   :  3; /* 2-4 */
+                        unsigned long a    :  1; /* 5 */
+                        unsigned long d    :  1; /* 6 */
+                        unsigned long pl   :  2; /* 7-8 */
+                        unsigned long ar   :  3; /* 9-11 */
+                        unsigned long ppn  : 38; /* 12-49 */
+                        unsigned long rv2  :  2; /* 50-51 */
+                        unsigned long ed   :  1; /* 52 */
+                        unsigned long ig1  : 11; /* 53-63 */
+                };
+                struct {
+                        unsigned long __rv1 : 53;     /* 0-52 */
+                        unsigned long contiguous : 1; /*53 */
+                        unsigned long tc : 1;         /* 54 TR or TC */
+                        unsigned long cl : 1;
+                        /* 55 I side or D side cache line */
+                        unsigned long len  :  4;      /* 56-59 */
+                        unsigned long io  : 1;  /* 60 entry is for io or not */
+                        unsigned long nomap : 1;
+                        /* 61 entry cann't be inserted into machine TLB.*/
+                        unsigned long checked : 1;
+                        /* 62 for VTLB/VHPT sanity check */
+                        unsigned long invalid : 1;
+                        /* 63 invalid entry */
+                };
+                unsigned long page_flags;
+        };                  /* same for VHPT and TLB */
+
+        union {
+                struct {
+                        unsigned long rv3  :  2;
+                        unsigned long ps   :  6;
+                        unsigned long key  : 24;
+                        unsigned long rv4  : 32;
+                };
+                unsigned long itir;
+        };
+        union {
+                struct {
+                        unsigned long ig2  :  12;
+                        unsigned long vpn  :  49;
+                        unsigned long vrn  :   3;
+                };
+                unsigned long ifa;
+                unsigned long vadr;
+                struct {
+                        unsigned long tag  :  63;
+                        unsigned long ti   :  1;
+                };
+                unsigned long etag;
+        };
+        union {
+                struct thash_data *next;
+                unsigned long rid;
+                unsigned long gpaddr;
+        };
+};
+
+#define NITRS   8
+#define NDTRS   8
+
+struct saved_vpd {
+        unsigned long  vhpi;
+        unsigned long  vgr[16];
+        unsigned long  vbgr[16];
+        unsigned long  vnat;
+        unsigned long  vbnat;
+        unsigned long  vcpuid[5];
+        unsigned long  vpsr;
+        unsigned long  vpr;
+        unsigned long  vcr[128];
+};
+
+struct kvm_regs {
+        char *saved_guest;
+        char *saved_stack;
+        struct saved_vpd vpd;
+        /*Arch-regs*/
+        int mp_state;
+        unsigned long vmm_rr;
+        /* TR and TC.  */
+        struct thash_data itrs[NITRS];
+        struct thash_data dtrs[NDTRS];
+        /* Bit is set if there is a tr/tc for the region.  */
+        unsigned char itr_regions;
+        unsigned char dtr_regions;
+        unsigned char tc_regions;
+
+        char irq_check;
+        unsigned long saved_itc;
+        unsigned long itc_check;
+        unsigned long timer_check;
+        unsigned long timer_pending;
+        unsigned long last_itc;
+
+        unsigned long vrr[8];
+        unsigned long ibr[8];
+        unsigned long dbr[8];
+        unsigned long insvc[4];         /* Interrupt in service.  */
+        unsigned long xtp;
+
+        unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
+        unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
+        unsigned long metaphysical_saved_rr0; /* from kvm_arch          */
+        unsigned long metaphysical_saved_rr4; /* from kvm_arch          */
+        unsigned long fp_psr;       /*used for lazy float register */
+        unsigned long saved_gp;
+        /*for phycial  emulation */
+};
+
+struct kvm_sregs {
+};
+
+struct kvm_fpu {
+};
+
+#endif
diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h
new file mode 100644
index 000000000000..1efe513a9941
--- /dev/null
+++ b/arch/ia64/include/asm/kvm_host.h
@@ -0,0 +1,527 @@
+/*
+ * kvm_host.h: used for kvm module, and hold ia64-specific sections.
+ *
+ * Copyright (C) 2007, Intel Corporation.
+ *
+ * Xiantao Zhang <xiantao.zhang@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+#ifndef __ASM_KVM_HOST_H
+#define __ASM_KVM_HOST_H
+
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/kvm.h>
+#include <linux/kvm_para.h>
+#include <linux/kvm_types.h>
+
+#include <asm/pal.h>
+#include <asm/sal.h>
+
+#define KVM_MAX_VCPUS 4
+#define KVM_MEMORY_SLOTS 32
+/* memory slots that does not exposed to userspace */
+#define KVM_PRIVATE_MEM_SLOTS 4
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+/* define exit reasons from vmm to kvm*/
+#define EXIT_REASON_VM_PANIC            0
+#define EXIT_REASON_MMIO_INSTRUCTION    1
+#define EXIT_REASON_PAL_CALL            2
+#define EXIT_REASON_SAL_CALL            3
+#define EXIT_REASON_SWITCH_RR6          4
+#define EXIT_REASON_VM_DESTROY          5
+#define EXIT_REASON_EXTERNAL_INTERRUPT  6
+#define EXIT_REASON_IPI                 7
+#define EXIT_REASON_PTC_G               8
+
+/*Define vmm address space and vm data space.*/
+#define KVM_VMM_SIZE (16UL<<20)
+#define KVM_VMM_SHIFT 24
+#define KVM_VMM_BASE 0xD000000000000000UL
+#define VMM_SIZE (8UL<<20)
+
+/*
+ * Define vm_buffer, used by PAL Services, base address.
+ * Note: vmbuffer is in the VMM-BLOCK, the size must be < 8M
+ */
+#define KVM_VM_BUFFER_BASE (KVM_VMM_BASE + VMM_SIZE)
+#define KVM_VM_BUFFER_SIZE (8UL<<20)
+
+/*Define Virtual machine data layout.*/
+#define KVM_VM_DATA_SHIFT  24
+#define KVM_VM_DATA_SIZE (1UL << KVM_VM_DATA_SHIFT)
+#define KVM_VM_DATA_BASE (KVM_VMM_BASE + KVM_VMM_SIZE)
+
+
+#define KVM_P2M_BASE    KVM_VM_DATA_BASE
+#define KVM_P2M_OFS     0
+#define KVM_P2M_SIZE    (8UL << 20)
+
+#define KVM_VHPT_BASE   (KVM_P2M_BASE + KVM_P2M_SIZE)
+#define KVM_VHPT_OFS    KVM_P2M_SIZE
+#define KVM_VHPT_BLOCK_SIZE   (2UL << 20)
+#define VHPT_SHIFT      18
+#define VHPT_SIZE       (1UL << VHPT_SHIFT)
+#define VHPT_NUM_ENTRIES (1<<(VHPT_SHIFT-5))
+
+#define KVM_VTLB_BASE   (KVM_VHPT_BASE+KVM_VHPT_BLOCK_SIZE)
+#define KVM_VTLB_OFS    (KVM_VHPT_OFS+KVM_VHPT_BLOCK_SIZE)
+#define KVM_VTLB_BLOCK_SIZE   (1UL<<20)
+#define VTLB_SHIFT      17
+#define VTLB_SIZE       (1UL<<VTLB_SHIFT)
+#define VTLB_NUM_ENTRIES (1<<(VTLB_SHIFT-5))
+
+#define KVM_VPD_BASE   (KVM_VTLB_BASE+KVM_VTLB_BLOCK_SIZE)
+#define KVM_VPD_OFS    (KVM_VTLB_OFS+KVM_VTLB_BLOCK_SIZE)
+#define KVM_VPD_BLOCK_SIZE   (2UL<<20)
+#define VPD_SHIFT       16
+#define VPD_SIZE        (1UL<<VPD_SHIFT)
+
+#define KVM_VCPU_BASE   (KVM_VPD_BASE+KVM_VPD_BLOCK_SIZE)
+#define KVM_VCPU_OFS    (KVM_VPD_OFS+KVM_VPD_BLOCK_SIZE)
+#define KVM_VCPU_BLOCK_SIZE   (2UL<<20)
+#define VCPU_SHIFT 18
+#define VCPU_SIZE (1UL<<VCPU_SHIFT)
+#define MAX_VCPU_NUM KVM_VCPU_BLOCK_SIZE/VCPU_SIZE
+
+#define KVM_VM_BASE     (KVM_VCPU_BASE+KVM_VCPU_BLOCK_SIZE)
+#define KVM_VM_OFS      (KVM_VCPU_OFS+KVM_VCPU_BLOCK_SIZE)
+#define KVM_VM_BLOCK_SIZE     (1UL<<19)
+
+#define KVM_MEM_DIRTY_LOG_BASE (KVM_VM_BASE+KVM_VM_BLOCK_SIZE)
+#define KVM_MEM_DIRTY_LOG_OFS  (KVM_VM_OFS+KVM_VM_BLOCK_SIZE)
+#define KVM_MEM_DIRTY_LOG_SIZE (1UL<<19)
+
+/* Get vpd, vhpt, tlb, vcpu, base*/
+#define VPD_ADDR(n) (KVM_VPD_BASE+n*VPD_SIZE)
+#define VHPT_ADDR(n) (KVM_VHPT_BASE+n*VHPT_SIZE)
+#define VTLB_ADDR(n) (KVM_VTLB_BASE+n*VTLB_SIZE)
+#define VCPU_ADDR(n) (KVM_VCPU_BASE+n*VCPU_SIZE)
+
+/*IO section definitions*/
+#define IOREQ_READ      1
+#define IOREQ_WRITE     0
+
+#define STATE_IOREQ_NONE        0
+#define STATE_IOREQ_READY       1
+#define STATE_IOREQ_INPROCESS   2
+#define STATE_IORESP_READY      3
+
+/*Guest Physical address layout.*/
+#define GPFN_MEM        (0UL << 60) /* Guest pfn is normal mem */
+#define GPFN_FRAME_BUFFER   (1UL << 60) /* VGA framebuffer */
+#define GPFN_LOW_MMIO       (2UL << 60) /* Low MMIO range */
+#define GPFN_PIB        (3UL << 60) /* PIB base */
+#define GPFN_IOSAPIC        (4UL << 60) /* IOSAPIC base */
+#define GPFN_LEGACY_IO      (5UL << 60) /* Legacy I/O base */
+#define GPFN_GFW        (6UL << 60) /* Guest Firmware */
+#define GPFN_HIGH_MMIO      (7UL << 60) /* High MMIO range */
+
+#define GPFN_IO_MASK        (7UL << 60) /* Guest pfn is I/O type */
+#define GPFN_INV_MASK       (1UL << 63) /* Guest pfn is invalid */
+#define INVALID_MFN       (~0UL)
+#define MEM_G   (1UL << 30)
+#define MEM_M   (1UL << 20)
+#define MMIO_START       (3 * MEM_G)
+#define MMIO_SIZE        (512 * MEM_M)
+#define VGA_IO_START     0xA0000UL
+#define VGA_IO_SIZE      0x20000
+#define LEGACY_IO_START  (MMIO_START + MMIO_SIZE)
+#define LEGACY_IO_SIZE   (64 * MEM_M)
+#define IO_SAPIC_START   0xfec00000UL
+#define IO_SAPIC_SIZE    0x100000
+#define PIB_START 0xfee00000UL
+#define PIB_SIZE 0x200000
+#define GFW_START        (4 * MEM_G - 16 * MEM_M)
+#define GFW_SIZE         (16 * MEM_M)
+
+/*Deliver mode, defined for ioapic.c*/
+#define dest_Fixed IOSAPIC_FIXED
+#define dest_LowestPrio IOSAPIC_LOWEST_PRIORITY
+
+#define NMI_VECTOR                      2
+#define ExtINT_VECTOR                   0
+#define NULL_VECTOR                     (-1)
+#define IA64_SPURIOUS_INT_VECTOR        0x0f
+
+#define VCPU_LID(v) (((u64)(v)->vcpu_id) << 24)
+
+/*
+ *Delivery mode
+ */
+#define SAPIC_DELIV_SHIFT      8
+#define SAPIC_FIXED            0x0
+#define SAPIC_LOWEST_PRIORITY  0x1
+#define SAPIC_PMI              0x2
+#define SAPIC_NMI              0x4
+#define SAPIC_INIT             0x5
+#define SAPIC_EXTINT           0x7
+
+/*
+ * vcpu->requests bit members for arch
+ */
+#define KVM_REQ_PTC_G           32
+#define KVM_REQ_RESUME          33
+
+#define KVM_PAGES_PER_HPAGE     1
+
+struct kvm;
+struct kvm_vcpu;
+struct kvm_guest_debug{
+};
+
+struct kvm_mmio_req {
+        uint64_t addr;          /*  physical address            */
+        uint64_t size;          /*  size in bytes               */
+        uint64_t data;          /*  data (or paddr of data)     */
+        uint8_t state:4;
+        uint8_t dir:1;          /*  1=read, 0=write             */
+};
+
+/*Pal data struct */
+struct kvm_pal_call{
+        /*In area*/
+        uint64_t gr28;
+        uint64_t gr29;
+        uint64_t gr30;
+        uint64_t gr31;
+        /*Out area*/
+        struct ia64_pal_retval ret;
+};
+
+/* Sal data structure */
+struct kvm_sal_call{
+        /*In area*/
+        uint64_t in0;
+        uint64_t in1;
+        uint64_t in2;
+        uint64_t in3;
+        uint64_t in4;
+        uint64_t in5;
+        uint64_t in6;
+        uint64_t in7;
+        struct sal_ret_values ret;
+};
+
+/*Guest change rr6*/
+struct kvm_switch_rr6 {
+        uint64_t old_rr;
+        uint64_t new_rr;
+};
+
+union ia64_ipi_a{
+        unsigned long val;
+        struct {
+                unsigned long rv  : 3;
+                unsigned long ir  : 1;
+                unsigned long eid : 8;
+                unsigned long id  : 8;
+                unsigned long ib_base : 44;
+        };
+};
+
+union ia64_ipi_d {
+        unsigned long val;
+        struct {
+                unsigned long vector : 8;
+                unsigned long dm  : 3;
+                unsigned long ig  : 53;
+        };
+};
+
+/*ipi check exit data*/
+struct kvm_ipi_data{
+        union ia64_ipi_a addr;
+        union ia64_ipi_d data;
+};
+
+/*global purge data*/
+struct kvm_ptc_g {
+        unsigned long vaddr;
+        unsigned long rr;
+        unsigned long ps;
+        struct kvm_vcpu *vcpu;
+};
+
+/*Exit control data */
+struct exit_ctl_data{
+        uint32_t exit_reason;
+        uint32_t vm_status;
+        union {
+                struct kvm_mmio_req     ioreq;
+                struct kvm_pal_call     pal_data;
+                struct kvm_sal_call     sal_data;
+                struct kvm_switch_rr6   rr_data;
+                struct kvm_ipi_data     ipi_data;
+                struct kvm_ptc_g        ptc_g_data;
+        } u;
+};
+
+union pte_flags {
+        unsigned long val;
+        struct {
+                unsigned long p    :  1; /*0      */
+                unsigned long      :  1; /* 1     */
+                unsigned long ma   :  3; /* 2-4   */
+                unsigned long a    :  1; /* 5     */
+                unsigned long d    :  1; /* 6     */
+                unsigned long pl   :  2; /* 7-8   */
+                unsigned long ar   :  3; /* 9-11  */
+                unsigned long ppn  : 38; /* 12-49 */
+                unsigned long      :  2; /* 50-51 */
+                unsigned long ed   :  1; /* 52    */
+        };
+};
+
+union ia64_pta {
+        unsigned long val;
+        struct {
+                unsigned long ve : 1;
+                unsigned long reserved0 : 1;
+                unsigned long size : 6;
+                unsigned long vf : 1;
+                unsigned long reserved1 : 6;
+                unsigned long base : 49;
+        };
+};
+
+struct thash_cb {
+        /* THASH base information */
+        struct thash_data       *hash; /* hash table pointer */
+        union ia64_pta          pta;
+        int           num;
+};
+
+struct kvm_vcpu_stat {
+};
+
+struct kvm_vcpu_arch {
+        int launched;
+        int last_exit;
+        int last_run_cpu;
+        int vmm_tr_slot;
+        int vm_tr_slot;
+
+#define KVM_MP_STATE_RUNNABLE          0
+#define KVM_MP_STATE_UNINITIALIZED     1
+#define KVM_MP_STATE_INIT_RECEIVED     2
+#define KVM_MP_STATE_HALTED            3
+        int mp_state;
+
+#define MAX_PTC_G_NUM                   3
+        int ptc_g_count;
+        struct kvm_ptc_g ptc_g_data[MAX_PTC_G_NUM];
+
+        /*halt timer to wake up sleepy vcpus*/
+        struct hrtimer hlt_timer;
+        long ht_active;
+
+        struct kvm_lapic *apic;    /* kernel irqchip context */
+        struct vpd *vpd;
+
+        /* Exit data for vmm_transition*/
+        struct exit_ctl_data exit_data;
+
+        cpumask_t cache_coherent_map;
+
+        unsigned long vmm_rr;
+        unsigned long host_rr6;
+        unsigned long psbits[8];
+        unsigned long cr_iipa;
+        unsigned long cr_isr;
+        unsigned long vsa_base;
+        unsigned long dirty_log_lock_pa;
+        unsigned long __gp;
+        /* TR and TC.  */
+        struct thash_data itrs[NITRS];
+        struct thash_data dtrs[NDTRS];
+        /* Bit is set if there is a tr/tc for the region.  */
+        unsigned char itr_regions;
+        unsigned char dtr_regions;
+        unsigned char tc_regions;
+        /* purge all */
+        unsigned long ptce_base;
+        unsigned long ptce_count[2];
+        unsigned long ptce_stride[2];
+        /* itc/itm */
+        unsigned long last_itc;
+        long itc_offset;
+        unsigned long itc_check;
+        unsigned long timer_check;
+        unsigned long timer_pending;
+
+        unsigned long vrr[8];
+        unsigned long ibr[8];
+        unsigned long dbr[8];
+        unsigned long insvc[4];         /* Interrupt in service.  */
+        unsigned long xtp;
+
+        unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
+        unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
+        unsigned long metaphysical_saved_rr0; /* from kvm_arch          */
+        unsigned long metaphysical_saved_rr4; /* from kvm_arch          */
+        unsigned long fp_psr;       /*used for lazy float register */
+        unsigned long saved_gp;
+        /*for phycial  emulation */
+        int mode_flags;
+        struct thash_cb vtlb;
+        struct thash_cb vhpt;
+        char irq_check;
+        char irq_new_pending;
+
+        unsigned long opcode;
+        unsigned long cause;
+        union context host;
+        union context guest;
+};
+
+struct kvm_vm_stat {
+        u64 remote_tlb_flush;
+};
+
+struct kvm_sal_data {
+        unsigned long boot_ip;
+        unsigned long boot_gp;
+};
+
+struct kvm_arch {
+        unsigned long   vm_base;
+        unsigned long   metaphysical_rr0;
+        unsigned long   metaphysical_rr4;
+        unsigned long   vmm_init_rr;
+        unsigned long   vhpt_base;
+        unsigned long   vtlb_base;
+        unsigned long   vpd_base;
+        spinlock_t dirty_log_lock;
+        struct kvm_ioapic *vioapic;
+        struct kvm_vm_stat stat;
+        struct kvm_sal_data rdv_sal_data;
+};
+
+union cpuid3_t {
+        u64 value;
+        struct {
+                u64 number : 8;
+                u64 revision : 8;
+                u64 model : 8;
+                u64 family : 8;
+                u64 archrev : 8;
+                u64 rv : 24;
+        };
+};
+
+struct kvm_pt_regs {
+        /* The following registers are saved by SAVE_MIN: */
+        unsigned long b6;  /* scratch */
+        unsigned long b7;  /* scratch */
+
+        unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
+        unsigned long ar_ssd; /* reserved for future use (scratch) */
+
+        unsigned long r8;  /* scratch (return value register 0) */
+        unsigned long r9;  /* scratch (return value register 1) */
+        unsigned long r10; /* scratch (return value register 2) */
+        unsigned long r11; /* scratch (return value register 3) */
+
+        unsigned long cr_ipsr; /* interrupted task's psr */
+        unsigned long cr_iip;  /* interrupted task's instruction pointer */
+        unsigned long cr_ifs;  /* interrupted task's function state */
+
+        unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
+        unsigned long ar_pfs;  /* prev function state  */
+        unsigned long ar_rsc;  /* RSE configuration */
+        /* The following two are valid only if cr_ipsr.cpl > 0: */
+        unsigned long ar_rnat;  /* RSE NaT */
+        unsigned long ar_bspstore; /* RSE bspstore */
+
+        unsigned long pr;  /* 64 predicate registers (1 bit each) */
+        unsigned long b0;  /* return pointer (bp) */
+        unsigned long loadrs;  /* size of dirty partition << 16 */
+
+        unsigned long r1;  /* the gp pointer */
+        unsigned long r12; /* interrupted task's memory stack pointer */
+        unsigned long r13; /* thread pointer */
+
+        unsigned long ar_fpsr;  /* floating point status (preserved) */
+        unsigned long r15;  /* scratch */
+
+        /* The remaining registers are NOT saved for system calls.  */
+        unsigned long r14;  /* scratch */
+        unsigned long r2;  /* scratch */
+        unsigned long r3;  /* scratch */
+        unsigned long r16;  /* scratch */
+        unsigned long r17;  /* scratch */
+        unsigned long r18;  /* scratch */
+        unsigned long r19;  /* scratch */
+        unsigned long r20;  /* scratch */
+        unsigned long r21;  /* scratch */
+        unsigned long r22;  /* scratch */
+        unsigned long r23;  /* scratch */
+        unsigned long r24;  /* scratch */
+        unsigned long r25;  /* scratch */
+        unsigned long r26;  /* scratch */
+        unsigned long r27;  /* scratch */
+        unsigned long r28;  /* scratch */
+        unsigned long r29;  /* scratch */
+        unsigned long r30;  /* scratch */
+        unsigned long r31;  /* scratch */
+        unsigned long ar_ccv;  /* compare/exchange value (scratch) */
+
+        /*
+         * Floating point registers that the kernel considers scratch:
+         */
+        struct ia64_fpreg f6;  /* scratch */
+        struct ia64_fpreg f7;  /* scratch */
+        struct ia64_fpreg f8;  /* scratch */
+        struct ia64_fpreg f9;  /* scratch */
+        struct ia64_fpreg f10;  /* scratch */
+        struct ia64_fpreg f11;  /* scratch */
+
+        unsigned long r4;  /* preserved */
+        unsigned long r5;  /* preserved */
+        unsigned long r6;  /* preserved */
+        unsigned long r7;  /* preserved */
+        unsigned long eml_unat;    /* used for emulating instruction */
+        unsigned long pad0;     /* alignment pad */
+};
+
+static inline struct kvm_pt_regs *vcpu_regs(struct kvm_vcpu *v)
+{
+        return (struct kvm_pt_regs *) ((unsigned long) v + IA64_STK_OFFSET) - 1;
+}
+
+typedef int kvm_vmm_entry(void);
+typedef void kvm_tramp_entry(union context *host, union context *guest);
+
+struct kvm_vmm_info{
+        struct module   *module;
+        kvm_vmm_entry   *vmm_entry;
+        kvm_tramp_entry *tramp_entry;
+        unsigned long   vmm_ivt;
+};
+
+int kvm_highest_pending_irq(struct kvm_vcpu *vcpu);
+int kvm_emulate_halt(struct kvm_vcpu *vcpu);
+int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run);
+void kvm_sal_emul(struct kvm_vcpu *vcpu);
+
+static inline void kvm_inject_nmi(struct kvm_vcpu *vcpu) {}
+
+#endif
diff --git a/arch/ia64/include/asm/kvm_para.h b/arch/ia64/include/asm/kvm_para.h
new file mode 100644
index 000000000000..0d6d8ca07b8c
--- /dev/null
+++ b/arch/ia64/include/asm/kvm_para.h
@@ -0,0 +1,27 @@
+#ifndef __IA64_KVM_PARA_H
+#define __IA64_KVM_PARA_H
+
+/*
+ * Copyright (C) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+static inline unsigned int kvm_arch_para_features(void)
+{
+        return 0;
+}
+
+#endif
diff --git a/arch/ia64/include/asm/libata-portmap.h b/arch/ia64/include/asm/libata-portmap.h
new file mode 100644
index 000000000000..0e00c9a9f410
--- /dev/null
+++ b/arch/ia64/include/asm/libata-portmap.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_IA64_LIBATA_PORTMAP_H
+#define __ASM_IA64_LIBATA_PORTMAP_H
+
+#define ATA_PRIMARY_CMD         0x1F0
+#define ATA_PRIMARY_CTL         0x3F6
+#define ATA_PRIMARY_IRQ(dev)    isa_irq_to_vector(14)
+
+#define ATA_SECONDARY_CMD       0x170
+#define ATA_SECONDARY_CTL       0x376
+#define ATA_SECONDARY_IRQ(dev)  isa_irq_to_vector(15)
+
+#endif
diff --git a/arch/ia64/include/asm/linkage.h b/arch/ia64/include/asm/linkage.h
new file mode 100644
index 000000000000..ef22a45c1890
--- /dev/null
+++ b/arch/ia64/include/asm/linkage.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#ifndef __ASSEMBLY__
+
+#define asmlinkage CPP_ASMLINKAGE __attribute__((syscall_linkage))
+
+#else
+
+#include <asm/asmmacro.h>
+
+#endif
+
+#endif
diff --git a/arch/ia64/include/asm/local.h b/arch/ia64/include/asm/local.h
new file mode 100644
index 000000000000..c11c530f74d0
--- /dev/null
+++ b/arch/ia64/include/asm/local.h
@@ -0,0 +1 @@
+#include <asm-generic/local.h>
diff --git a/arch/ia64/include/asm/machvec.h b/arch/ia64/include/asm/machvec.h
new file mode 100644
index 000000000000..2b850ccafef5
--- /dev/null
+++ b/arch/ia64/include/asm/machvec.h
@@ -0,0 +1,460 @@
+/*
+ * Machine vector for IA-64.
+ *
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
+ * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
+ * Copyright (C) 1999-2001, 2003-2004 Hewlett-Packard Co.
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#ifndef _ASM_IA64_MACHVEC_H
+#define _ASM_IA64_MACHVEC_H
+
+#include <linux/types.h>
+
+/* forward declarations: */
+struct device;
+struct pt_regs;
+struct scatterlist;
+struct page;
+struct mm_struct;
+struct pci_bus;
+struct task_struct;
+struct pci_dev;
+struct msi_desc;
+struct dma_attrs;
+
+typedef void ia64_mv_setup_t (char **);
+typedef void ia64_mv_cpu_init_t (void);
+typedef void ia64_mv_irq_init_t (void);
+typedef void ia64_mv_send_ipi_t (int, int, int, int);
+typedef void ia64_mv_timer_interrupt_t (int, void *);
+typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long);
+typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *);
+typedef u8 ia64_mv_irq_to_vector (int);
+typedef unsigned int ia64_mv_local_vector_to_irq (u8);
+typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *);
+typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val,
+                                       u8 size);
+typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
+                                        u8 size);
+typedef void ia64_mv_migrate_t(struct task_struct * task);
+typedef void ia64_mv_pci_fixup_bus_t (struct pci_bus *);
+typedef void ia64_mv_kernel_launch_event_t(void);
+
+/* DMA-mapping interface: */
+typedef void ia64_mv_dma_init (void);
+typedef void *ia64_mv_dma_alloc_coherent (struct device *, size_t, dma_addr_t *, gfp_t);
+typedef void ia64_mv_dma_free_coherent (struct device *, size_t, void *, dma_addr_t);
+typedef dma_addr_t ia64_mv_dma_map_single (struct device *, void *, size_t, int);
+typedef void ia64_mv_dma_unmap_single (struct device *, dma_addr_t, size_t, int);
+typedef int ia64_mv_dma_map_sg (struct device *, struct scatterlist *, int, int);
+typedef void ia64_mv_dma_unmap_sg (struct device *, struct scatterlist *, int, int);
+typedef void ia64_mv_dma_sync_single_for_cpu (struct device *, dma_addr_t, size_t, int);
+typedef void ia64_mv_dma_sync_sg_for_cpu (struct device *, struct scatterlist *, int, int);
+typedef void ia64_mv_dma_sync_single_for_device (struct device *, dma_addr_t, size_t, int);
+typedef void ia64_mv_dma_sync_sg_for_device (struct device *, struct scatterlist *, int, int);
+typedef int ia64_mv_dma_mapping_error(struct device *, dma_addr_t dma_addr);
+typedef int ia64_mv_dma_supported (struct device *, u64);
+
+typedef dma_addr_t ia64_mv_dma_map_single_attrs (struct device *, void *, size_t, int, struct dma_attrs *);
+typedef void ia64_mv_dma_unmap_single_attrs (struct device *, dma_addr_t, size_t, int, struct dma_attrs *);
+typedef int ia64_mv_dma_map_sg_attrs (struct device *, struct scatterlist *, int, int, struct dma_attrs *);
+typedef void ia64_mv_dma_unmap_sg_attrs (struct device *, struct scatterlist *, int, int, struct dma_attrs *);
+
+/*
+ * WARNING: The legacy I/O space is _architected_.  Platforms are
+ * expected to follow this architected model (see Section 10.7 in the
+ * IA-64 Architecture Software Developer's Manual).  Unfortunately,
+ * some broken machines do not follow that model, which is why we have
+ * to make the inX/outX operations part of the machine vector.
+ * Platform designers should follow the architected model whenever
+ * possible.
+ */
+typedef unsigned int ia64_mv_inb_t (unsigned long);
+typedef unsigned int ia64_mv_inw_t (unsigned long);
+typedef unsigned int ia64_mv_inl_t (unsigned long);
+typedef void ia64_mv_outb_t (unsigned char, unsigned long);
+typedef void ia64_mv_outw_t (unsigned short, unsigned long);
+typedef void ia64_mv_outl_t (unsigned int, unsigned long);
+typedef void ia64_mv_mmiowb_t (void);
+typedef unsigned char ia64_mv_readb_t (const volatile void __iomem *);
+typedef unsigned short ia64_mv_readw_t (const volatile void __iomem *);
+typedef unsigned int ia64_mv_readl_t (const volatile void __iomem *);
+typedef unsigned long ia64_mv_readq_t (const volatile void __iomem *);
+typedef unsigned char ia64_mv_readb_relaxed_t (const volatile void __iomem *);
+typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *);
+typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *);
+typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *);
+
+typedef int ia64_mv_setup_msi_irq_t (struct pci_dev *pdev, struct msi_desc *);
+typedef void ia64_mv_teardown_msi_irq_t (unsigned int irq);
+
+static inline void
+machvec_noop (void)
+{
+}
+
+static inline void
+machvec_noop_mm (struct mm_struct *mm)
+{
+}
+
+static inline void
+machvec_noop_task (struct task_struct *task)
+{
+}
+
+static inline void
+machvec_noop_bus (struct pci_bus *bus)
+{
+}
+
+extern void machvec_setup (char **);
+extern void machvec_timer_interrupt (int, void *);
+extern void machvec_dma_sync_single (struct device *, dma_addr_t, size_t, int);
+extern void machvec_dma_sync_sg (struct device *, struct scatterlist *, int, int);
+extern void machvec_tlb_migrate_finish (struct mm_struct *);
+
+# if defined (CONFIG_IA64_HP_SIM)
+#  include <asm/machvec_hpsim.h>
+# elif defined (CONFIG_IA64_DIG)
+#  include <asm/machvec_dig.h>
+# elif defined (CONFIG_IA64_HP_ZX1)
+#  include <asm/machvec_hpzx1.h>
+# elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
+#  include <asm/machvec_hpzx1_swiotlb.h>
+# elif defined (CONFIG_IA64_SGI_SN2)
+#  include <asm/machvec_sn2.h>
+# elif defined (CONFIG_IA64_SGI_UV)
+#  include <asm/machvec_uv.h>
+# elif defined (CONFIG_IA64_GENERIC)
+
+# ifdef MACHVEC_PLATFORM_HEADER
+#  include MACHVEC_PLATFORM_HEADER
+# else
+#  define platform_name         ia64_mv.name
+#  define platform_setup        ia64_mv.setup
+#  define platform_cpu_init     ia64_mv.cpu_init
+#  define platform_irq_init     ia64_mv.irq_init
+#  define platform_send_ipi     ia64_mv.send_ipi
+#  define platform_timer_interrupt      ia64_mv.timer_interrupt
+#  define platform_global_tlb_purge     ia64_mv.global_tlb_purge
+#  define platform_tlb_migrate_finish   ia64_mv.tlb_migrate_finish
+#  define platform_dma_init             ia64_mv.dma_init
+#  define platform_dma_alloc_coherent   ia64_mv.dma_alloc_coherent
+#  define platform_dma_free_coherent    ia64_mv.dma_free_coherent
+#  define platform_dma_map_single_attrs ia64_mv.dma_map_single_attrs
+#  define platform_dma_unmap_single_attrs       ia64_mv.dma_unmap_single_attrs
+#  define platform_dma_map_sg_attrs     ia64_mv.dma_map_sg_attrs
+#  define platform_dma_unmap_sg_attrs   ia64_mv.dma_unmap_sg_attrs
+#  define platform_dma_sync_single_for_cpu ia64_mv.dma_sync_single_for_cpu
+#  define platform_dma_sync_sg_for_cpu  ia64_mv.dma_sync_sg_for_cpu
+#  define platform_dma_sync_single_for_device ia64_mv.dma_sync_single_for_device
+#  define platform_dma_sync_sg_for_device ia64_mv.dma_sync_sg_for_device
+#  define platform_dma_mapping_error            ia64_mv.dma_mapping_error
+#  define platform_dma_supported        ia64_mv.dma_supported
+#  define platform_irq_to_vector        ia64_mv.irq_to_vector
+#  define platform_local_vector_to_irq  ia64_mv.local_vector_to_irq
+#  define platform_pci_get_legacy_mem   ia64_mv.pci_get_legacy_mem
+#  define platform_pci_legacy_read      ia64_mv.pci_legacy_read
+#  define platform_pci_legacy_write     ia64_mv.pci_legacy_write
+#  define platform_inb          ia64_mv.inb
+#  define platform_inw          ia64_mv.inw
+#  define platform_inl          ia64_mv.inl
+#  define platform_outb         ia64_mv.outb
+#  define platform_outw         ia64_mv.outw
+#  define platform_outl         ia64_mv.outl
+#  define platform_mmiowb       ia64_mv.mmiowb
+#  define platform_readb        ia64_mv.readb
+#  define platform_readw        ia64_mv.readw
+#  define platform_readl        ia64_mv.readl
+#  define platform_readq        ia64_mv.readq
+#  define platform_readb_relaxed        ia64_mv.readb_relaxed
+#  define platform_readw_relaxed        ia64_mv.readw_relaxed
+#  define platform_readl_relaxed        ia64_mv.readl_relaxed
+#  define platform_readq_relaxed        ia64_mv.readq_relaxed
+#  define platform_migrate              ia64_mv.migrate
+#  define platform_setup_msi_irq        ia64_mv.setup_msi_irq
+#  define platform_teardown_msi_irq     ia64_mv.teardown_msi_irq
+#  define platform_pci_fixup_bus        ia64_mv.pci_fixup_bus
+#  define platform_kernel_launch_event  ia64_mv.kernel_launch_event
+# endif
+
+/* __attribute__((__aligned__(16))) is required to make size of the
+ * structure multiple of 16 bytes.
+ * This will fillup the holes created because of section 3.3.1 in
+ * Software Conventions guide.
+ */
+struct ia64_machine_vector {
+        const char *name;
+        ia64_mv_setup_t *setup;
+        ia64_mv_cpu_init_t *cpu_init;
+        ia64_mv_irq_init_t *irq_init;
+        ia64_mv_send_ipi_t *send_ipi;
+        ia64_mv_timer_interrupt_t *timer_interrupt;
+        ia64_mv_global_tlb_purge_t *global_tlb_purge;
+        ia64_mv_tlb_migrate_finish_t *tlb_migrate_finish;
+        ia64_mv_dma_init *dma_init;
+        ia64_mv_dma_alloc_coherent *dma_alloc_coherent;
+        ia64_mv_dma_free_coherent *dma_free_coherent;
+        ia64_mv_dma_map_single_attrs *dma_map_single_attrs;
+        ia64_mv_dma_unmap_single_attrs *dma_unmap_single_attrs;
+        ia64_mv_dma_map_sg_attrs *dma_map_sg_attrs;
+        ia64_mv_dma_unmap_sg_attrs *dma_unmap_sg_attrs;
+        ia64_mv_dma_sync_single_for_cpu *dma_sync_single_for_cpu;
+        ia64_mv_dma_sync_sg_for_cpu *dma_sync_sg_for_cpu;
+        ia64_mv_dma_sync_single_for_device *dma_sync_single_for_device;
+        ia64_mv_dma_sync_sg_for_device *dma_sync_sg_for_device;
+        ia64_mv_dma_mapping_error *dma_mapping_error;
+        ia64_mv_dma_supported *dma_supported;
+        ia64_mv_irq_to_vector *irq_to_vector;
+        ia64_mv_local_vector_to_irq *local_vector_to_irq;
+        ia64_mv_pci_get_legacy_mem_t *pci_get_legacy_mem;
+        ia64_mv_pci_legacy_read_t *pci_legacy_read;
+        ia64_mv_pci_legacy_write_t *pci_legacy_write;
+        ia64_mv_inb_t *inb;
+        ia64_mv_inw_t *inw;
+        ia64_mv_inl_t *inl;
+        ia64_mv_outb_t *outb;
+        ia64_mv_outw_t *outw;
+        ia64_mv_outl_t *outl;
+        ia64_mv_mmiowb_t *mmiowb;
+        ia64_mv_readb_t *readb;
+        ia64_mv_readw_t *readw;
+        ia64_mv_readl_t *readl;
+        ia64_mv_readq_t *readq;
+        ia64_mv_readb_relaxed_t *readb_relaxed;
+        ia64_mv_readw_relaxed_t *readw_relaxed;
+        ia64_mv_readl_relaxed_t *readl_relaxed;
+        ia64_mv_readq_relaxed_t *readq_relaxed;
+        ia64_mv_migrate_t *migrate;
+        ia64_mv_setup_msi_irq_t *setup_msi_irq;
+        ia64_mv_teardown_msi_irq_t *teardown_msi_irq;
+        ia64_mv_pci_fixup_bus_t *pci_fixup_bus;
+        ia64_mv_kernel_launch_event_t *kernel_launch_event;
+} __attribute__((__aligned__(16))); /* align attrib? see above comment */
+
+#define MACHVEC_INIT(name)                      \
+{                                               \
+        #name,                                  \
+        platform_setup,                         \
+        platform_cpu_init,                      \
+        platform_irq_init,                      \
+        platform_send_ipi,                      \
+        platform_timer_interrupt,               \
+        platform_global_tlb_purge,              \
+        platform_tlb_migrate_finish,            \
+        platform_dma_init,                      \
+        platform_dma_alloc_coherent,            \
+        platform_dma_free_coherent,             \
+        platform_dma_map_single_attrs,          \
+        platform_dma_unmap_single_attrs,        \
+        platform_dma_map_sg_attrs,              \
+        platform_dma_unmap_sg_attrs,            \
+        platform_dma_sync_single_for_cpu,       \
+        platform_dma_sync_sg_for_cpu,           \
+        platform_dma_sync_single_for_device,    \
+        platform_dma_sync_sg_for_device,        \
+        platform_dma_mapping_error,                     \
+        platform_dma_supported,                 \
+        platform_irq_to_vector,                 \
+        platform_local_vector_to_irq,           \
+        platform_pci_get_legacy_mem,            \
+        platform_pci_legacy_read,               \
+        platform_pci_legacy_write,              \
+        platform_inb,                           \
+        platform_inw,                           \
+        platform_inl,                           \
+        platform_outb,                          \
+        platform_outw,                          \
+        platform_outl,                          \
+        platform_mmiowb,                        \
+        platform_readb,                         \
+        platform_readw,                         \
+        platform_readl,                         \
+        platform_readq,                         \
+        platform_readb_relaxed,                 \
+        platform_readw_relaxed,                 \
+        platform_readl_relaxed,                 \
+        platform_readq_relaxed,                 \
+        platform_migrate,                       \
+        platform_setup_msi_irq,                 \
+        platform_teardown_msi_irq,              \
+        platform_pci_fixup_bus,                 \
+        platform_kernel_launch_event            \
+}
+
+extern struct ia64_machine_vector ia64_mv;
+extern void machvec_init (const char *name);
+extern void machvec_init_from_cmdline(const char *cmdline);
+
+# else
+#  error Unknown configuration.  Update arch/ia64/include/asm/machvec.h.
+# endif /* CONFIG_IA64_GENERIC */
+
+/*
+ * Declare default routines which aren't declared anywhere else:
+ */
+extern ia64_mv_dma_init                 swiotlb_init;
+extern ia64_mv_dma_alloc_coherent       swiotlb_alloc_coherent;
+extern ia64_mv_dma_free_coherent        swiotlb_free_coherent;
+extern ia64_mv_dma_map_single           swiotlb_map_single;
+extern ia64_mv_dma_map_single_attrs     swiotlb_map_single_attrs;
+extern ia64_mv_dma_unmap_single         swiotlb_unmap_single;
+extern ia64_mv_dma_unmap_single_attrs   swiotlb_unmap_single_attrs;
+extern ia64_mv_dma_map_sg               swiotlb_map_sg;
+extern ia64_mv_dma_map_sg_attrs         swiotlb_map_sg_attrs;
+extern ia64_mv_dma_unmap_sg             swiotlb_unmap_sg;
+extern ia64_mv_dma_unmap_sg_attrs       swiotlb_unmap_sg_attrs;
+extern ia64_mv_dma_sync_single_for_cpu  swiotlb_sync_single_for_cpu;
+extern ia64_mv_dma_sync_sg_for_cpu      swiotlb_sync_sg_for_cpu;
+extern ia64_mv_dma_sync_single_for_device swiotlb_sync_single_for_device;
+extern ia64_mv_dma_sync_sg_for_device   swiotlb_sync_sg_for_device;
+extern ia64_mv_dma_mapping_error        swiotlb_dma_mapping_error;
+extern ia64_mv_dma_supported            swiotlb_dma_supported;
+
+/*
+ * Define default versions so we can extend machvec for new platforms without having
+ * to update the machvec files for all existing platforms.
+ */
+#ifndef platform_setup
+# define platform_setup                 machvec_setup
+#endif
+#ifndef platform_cpu_init
+# define platform_cpu_init              machvec_noop
+#endif
+#ifndef platform_irq_init
+# define platform_irq_init              machvec_noop
+#endif
+
+#ifndef platform_send_ipi
+# define platform_send_ipi              ia64_send_ipi   /* default to architected version */
+#endif
+#ifndef platform_timer_interrupt
+# define platform_timer_interrupt       machvec_timer_interrupt
+#endif
+#ifndef platform_global_tlb_purge
+# define platform_global_tlb_purge      ia64_global_tlb_purge /* default to architected version */
+#endif
+#ifndef platform_tlb_migrate_finish
+# define platform_tlb_migrate_finish    machvec_noop_mm
+#endif
+#ifndef platform_kernel_launch_event
+# define platform_kernel_launch_event   machvec_noop
+#endif
+#ifndef platform_dma_init
+# define platform_dma_init              swiotlb_init
+#endif
+#ifndef platform_dma_alloc_coherent
+# define platform_dma_alloc_coherent    swiotlb_alloc_coherent
+#endif
+#ifndef platform_dma_free_coherent
+# define platform_dma_free_coherent     swiotlb_free_coherent
+#endif
+#ifndef platform_dma_map_single_attrs
+# define platform_dma_map_single_attrs  swiotlb_map_single_attrs
+#endif
+#ifndef platform_dma_unmap_single_attrs
+# define platform_dma_unmap_single_attrs        swiotlb_unmap_single_attrs
+#endif
+#ifndef platform_dma_map_sg_attrs
+# define platform_dma_map_sg_attrs      swiotlb_map_sg_attrs
+#endif
+#ifndef platform_dma_unmap_sg_attrs
+# define platform_dma_unmap_sg_attrs    swiotlb_unmap_sg_attrs
+#endif
+#ifndef platform_dma_sync_single_for_cpu
+# define platform_dma_sync_single_for_cpu       swiotlb_sync_single_for_cpu
+#endif
+#ifndef platform_dma_sync_sg_for_cpu
+# define platform_dma_sync_sg_for_cpu           swiotlb_sync_sg_for_cpu
+#endif
+#ifndef platform_dma_sync_single_for_device
+# define platform_dma_sync_single_for_device    swiotlb_sync_single_for_device
+#endif
+#ifndef platform_dma_sync_sg_for_device
+# define platform_dma_sync_sg_for_device        swiotlb_sync_sg_for_device
+#endif
+#ifndef platform_dma_mapping_error
+# define platform_dma_mapping_error             swiotlb_dma_mapping_error
+#endif
+#ifndef platform_dma_supported
+# define  platform_dma_supported        swiotlb_dma_supported
+#endif
+#ifndef platform_irq_to_vector
+# define platform_irq_to_vector         __ia64_irq_to_vector
+#endif
+#ifndef platform_local_vector_to_irq
+# define platform_local_vector_to_irq   __ia64_local_vector_to_irq
+#endif
+#ifndef platform_pci_get_legacy_mem
+# define platform_pci_get_legacy_mem    ia64_pci_get_legacy_mem
+#endif
+#ifndef platform_pci_legacy_read
+# define platform_pci_legacy_read       ia64_pci_legacy_read
+extern int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size);
+#endif
+#ifndef platform_pci_legacy_write
+# define platform_pci_legacy_write      ia64_pci_legacy_write
+extern int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size);
+#endif
+#ifndef platform_inb
+# define platform_inb           __ia64_inb
+#endif
+#ifndef platform_inw
+# define platform_inw           __ia64_inw
+#endif
+#ifndef platform_inl
+# define platform_inl           __ia64_inl
+#endif
+#ifndef platform_outb
+# define platform_outb          __ia64_outb
+#endif
+#ifndef platform_outw
+# define platform_outw          __ia64_outw
+#endif
+#ifndef platform_outl
+# define platform_outl          __ia64_outl
+#endif
+#ifndef platform_mmiowb
+# define platform_mmiowb        __ia64_mmiowb
+#endif
+#ifndef platform_readb
+# define platform_readb         __ia64_readb
+#endif
+#ifndef platform_readw
+# define platform_readw         __ia64_readw
+#endif
+#ifndef platform_readl
+# define platform_readl         __ia64_readl
+#endif
+#ifndef platform_readq
+# define platform_readq         __ia64_readq
+#endif
+#ifndef platform_readb_relaxed
+# define platform_readb_relaxed __ia64_readb_relaxed
+#endif
+#ifndef platform_readw_relaxed
+# define platform_readw_relaxed __ia64_readw_relaxed
+#endif
+#ifndef platform_readl_relaxed
+# define platform_readl_relaxed __ia64_readl_relaxed
+#endif
+#ifndef platform_readq_relaxed
+# define platform_readq_relaxed __ia64_readq_relaxed
+#endif
+#ifndef platform_migrate
+# define platform_migrate machvec_noop_task
+#endif
+#ifndef platform_setup_msi_irq
+# define platform_setup_msi_irq         ((ia64_mv_setup_msi_irq_t*)NULL)
+#endif
+#ifndef platform_teardown_msi_irq
+# define platform_teardown_msi_irq      ((ia64_mv_teardown_msi_irq_t*)NULL)
+#endif
+#ifndef platform_pci_fixup_bus
+# define platform_pci_fixup_bus machvec_noop_bus
+#endif
+
+#endif /* _ASM_IA64_MACHVEC_H */
diff --git a/arch/ia64/include/asm/machvec_dig.h b/arch/ia64/include/asm/machvec_dig.h
new file mode 100644
index 000000000000..8a0752f40987
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_dig.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_IA64_MACHVEC_DIG_h
+#define _ASM_IA64_MACHVEC_DIG_h
+
+extern ia64_mv_setup_t dig_setup;
+
+/*
+ * This stuff has dual use!
+ *
+ * For a generic kernel, the macros are used to initialize the
+ * platform's machvec structure.  When compiling a non-generic kernel,
+ * the macros are used directly.
+ */
+#define platform_name           "dig"
+#define platform_setup          dig_setup
+
+#endif /* _ASM_IA64_MACHVEC_DIG_h */
diff --git a/arch/ia64/include/asm/machvec_hpsim.h b/arch/ia64/include/asm/machvec_hpsim.h
new file mode 100644
index 000000000000..cf72fc87fdfe
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_hpsim.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_IA64_MACHVEC_HPSIM_h
+#define _ASM_IA64_MACHVEC_HPSIM_h
+
+extern ia64_mv_setup_t hpsim_setup;
+extern ia64_mv_irq_init_t hpsim_irq_init;
+
+/*
+ * This stuff has dual use!
+ *
+ * For a generic kernel, the macros are used to initialize the
+ * platform's machvec structure.  When compiling a non-generic kernel,
+ * the macros are used directly.
+ */
+#define platform_name           "hpsim"
+#define platform_setup          hpsim_setup
+#define platform_irq_init       hpsim_irq_init
+
+#endif /* _ASM_IA64_MACHVEC_HPSIM_h */
diff --git a/arch/ia64/include/asm/machvec_hpzx1.h b/arch/ia64/include/asm/machvec_hpzx1.h
new file mode 100644
index 000000000000..2f57f5144b9f
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_hpzx1.h
@@ -0,0 +1,37 @@
+#ifndef _ASM_IA64_MACHVEC_HPZX1_h
+#define _ASM_IA64_MACHVEC_HPZX1_h
+
+extern ia64_mv_setup_t                  dig_setup;
+extern ia64_mv_dma_alloc_coherent       sba_alloc_coherent;
+extern ia64_mv_dma_free_coherent        sba_free_coherent;
+extern ia64_mv_dma_map_single_attrs     sba_map_single_attrs;
+extern ia64_mv_dma_unmap_single_attrs   sba_unmap_single_attrs;
+extern ia64_mv_dma_map_sg_attrs         sba_map_sg_attrs;
+extern ia64_mv_dma_unmap_sg_attrs       sba_unmap_sg_attrs;
+extern ia64_mv_dma_supported            sba_dma_supported;
+extern ia64_mv_dma_mapping_error        sba_dma_mapping_error;
+
+/*
+ * This stuff has dual use!
+ *
+ * For a generic kernel, the macros are used to initialize the
+ * platform's machvec structure.  When compiling a non-generic kernel,
+ * the macros are used directly.
+ */
+#define platform_name                           "hpzx1"
+#define platform_setup                          dig_setup
+#define platform_dma_init                       machvec_noop
+#define platform_dma_alloc_coherent             sba_alloc_coherent
+#define platform_dma_free_coherent              sba_free_coherent
+#define platform_dma_map_single_attrs           sba_map_single_attrs
+#define platform_dma_unmap_single_attrs         sba_unmap_single_attrs
+#define platform_dma_map_sg_attrs               sba_map_sg_attrs
+#define platform_dma_unmap_sg_attrs             sba_unmap_sg_attrs
+#define platform_dma_sync_single_for_cpu        machvec_dma_sync_single
+#define platform_dma_sync_sg_for_cpu            machvec_dma_sync_sg
+#define platform_dma_sync_single_for_device     machvec_dma_sync_single
+#define platform_dma_sync_sg_for_device         machvec_dma_sync_sg
+#define platform_dma_supported                  sba_dma_supported
+#define platform_dma_mapping_error              sba_dma_mapping_error
+
+#endif /* _ASM_IA64_MACHVEC_HPZX1_h */
diff --git a/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h b/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
new file mode 100644
index 000000000000..a842cdda827b
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
@@ -0,0 +1,42 @@
+#ifndef _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
+#define _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
+
+extern ia64_mv_setup_t                          dig_setup;
+extern ia64_mv_dma_alloc_coherent               hwsw_alloc_coherent;
+extern ia64_mv_dma_free_coherent                hwsw_free_coherent;
+extern ia64_mv_dma_map_single_attrs             hwsw_map_single_attrs;
+extern ia64_mv_dma_unmap_single_attrs           hwsw_unmap_single_attrs;
+extern ia64_mv_dma_map_sg_attrs                 hwsw_map_sg_attrs;
+extern ia64_mv_dma_unmap_sg_attrs               hwsw_unmap_sg_attrs;
+extern ia64_mv_dma_supported                    hwsw_dma_supported;
+extern ia64_mv_dma_mapping_error                hwsw_dma_mapping_error;
+extern ia64_mv_dma_sync_single_for_cpu          hwsw_sync_single_for_cpu;
+extern ia64_mv_dma_sync_sg_for_cpu              hwsw_sync_sg_for_cpu;
+extern ia64_mv_dma_sync_single_for_device       hwsw_sync_single_for_device;
+extern ia64_mv_dma_sync_sg_for_device           hwsw_sync_sg_for_device;
+
+/*
+ * This stuff has dual use!
+ *
+ * For a generic kernel, the macros are used to initialize the
+ * platform's machvec structure.  When compiling a non-generic kernel,
+ * the macros are used directly.
+ */
+#define platform_name                           "hpzx1_swiotlb"
+
+#define platform_setup                          dig_setup
+#define platform_dma_init                       machvec_noop
+#define platform_dma_alloc_coherent             hwsw_alloc_coherent
+#define platform_dma_free_coherent              hwsw_free_coherent
+#define platform_dma_map_single_attrs           hwsw_map_single_attrs
+#define platform_dma_unmap_single_attrs         hwsw_unmap_single_attrs
+#define platform_dma_map_sg_attrs               hwsw_map_sg_attrs
+#define platform_dma_unmap_sg_attrs             hwsw_unmap_sg_attrs
+#define platform_dma_supported                  hwsw_dma_supported
+#define platform_dma_mapping_error              hwsw_dma_mapping_error
+#define platform_dma_sync_single_for_cpu        hwsw_sync_single_for_cpu
+#define platform_dma_sync_sg_for_cpu            hwsw_sync_sg_for_cpu
+#define platform_dma_sync_single_for_device     hwsw_sync_single_for_device
+#define platform_dma_sync_sg_for_device         hwsw_sync_sg_for_device
+
+#endif /* _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h */
diff --git a/arch/ia64/include/asm/machvec_init.h b/arch/ia64/include/asm/machvec_init.h
new file mode 100644
index 000000000000..7f21249fba3f
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_init.h
@@ -0,0 +1,33 @@
+#include <asm/machvec.h>
+
+extern ia64_mv_send_ipi_t ia64_send_ipi;
+extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge;
+extern ia64_mv_irq_to_vector __ia64_irq_to_vector;
+extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq;
+extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem;
+extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read;
+extern ia64_mv_pci_legacy_write_t ia64_pci_legacy_write;
+
+extern ia64_mv_inb_t __ia64_inb;
+extern ia64_mv_inw_t __ia64_inw;
+extern ia64_mv_inl_t __ia64_inl;
+extern ia64_mv_outb_t __ia64_outb;
+extern ia64_mv_outw_t __ia64_outw;
+extern ia64_mv_outl_t __ia64_outl;
+extern ia64_mv_mmiowb_t __ia64_mmiowb;
+extern ia64_mv_readb_t __ia64_readb;
+extern ia64_mv_readw_t __ia64_readw;
+extern ia64_mv_readl_t __ia64_readl;
+extern ia64_mv_readq_t __ia64_readq;
+extern ia64_mv_readb_t __ia64_readb_relaxed;
+extern ia64_mv_readw_t __ia64_readw_relaxed;
+extern ia64_mv_readl_t __ia64_readl_relaxed;
+extern ia64_mv_readq_t __ia64_readq_relaxed;
+
+#define MACHVEC_HELPER(name)                                                                    \
+ struct ia64_machine_vector machvec_##name __attribute__ ((unused, __section__ (".machvec")))   \
+        = MACHVEC_INIT(name);
+
+#define MACHVEC_DEFINE(name)    MACHVEC_HELPER(name)
+
+MACHVEC_DEFINE(MACHVEC_PLATFORM_NAME)
diff --git a/arch/ia64/include/asm/machvec_sn2.h b/arch/ia64/include/asm/machvec_sn2.h
new file mode 100644
index 000000000000..781308ea7b88
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_sn2.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2002-2003,2006 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#ifndef _ASM_IA64_MACHVEC_SN2_H
+#define _ASM_IA64_MACHVEC_SN2_H
+
+extern ia64_mv_setup_t sn_setup;
+extern ia64_mv_cpu_init_t sn_cpu_init;
+extern ia64_mv_irq_init_t sn_irq_init;
+extern ia64_mv_send_ipi_t sn2_send_IPI;
+extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
+extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
+extern ia64_mv_tlb_migrate_finish_t     sn_tlb_migrate_finish;
+extern ia64_mv_irq_to_vector sn_irq_to_vector;
+extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
+extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
+extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
+extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
+extern ia64_mv_inb_t __sn_inb;
+extern ia64_mv_inw_t __sn_inw;
+extern ia64_mv_inl_t __sn_inl;
+extern ia64_mv_outb_t __sn_outb;
+extern ia64_mv_outw_t __sn_outw;
+extern ia64_mv_outl_t __sn_outl;
+extern ia64_mv_mmiowb_t __sn_mmiowb;
+extern ia64_mv_readb_t __sn_readb;
+extern ia64_mv_readw_t __sn_readw;
+extern ia64_mv_readl_t __sn_readl;
+extern ia64_mv_readq_t __sn_readq;
+extern ia64_mv_readb_t __sn_readb_relaxed;
+extern ia64_mv_readw_t __sn_readw_relaxed;
+extern ia64_mv_readl_t __sn_readl_relaxed;
+extern ia64_mv_readq_t __sn_readq_relaxed;
+extern ia64_mv_dma_alloc_coherent       sn_dma_alloc_coherent;
+extern ia64_mv_dma_free_coherent        sn_dma_free_coherent;
+extern ia64_mv_dma_map_single_attrs     sn_dma_map_single_attrs;
+extern ia64_mv_dma_unmap_single_attrs   sn_dma_unmap_single_attrs;
+extern ia64_mv_dma_map_sg_attrs         sn_dma_map_sg_attrs;
+extern ia64_mv_dma_unmap_sg_attrs       sn_dma_unmap_sg_attrs;
+extern ia64_mv_dma_sync_single_for_cpu  sn_dma_sync_single_for_cpu;
+extern ia64_mv_dma_sync_sg_for_cpu      sn_dma_sync_sg_for_cpu;
+extern ia64_mv_dma_sync_single_for_device sn_dma_sync_single_for_device;
+extern ia64_mv_dma_sync_sg_for_device   sn_dma_sync_sg_for_device;
+extern ia64_mv_dma_mapping_error        sn_dma_mapping_error;
+extern ia64_mv_dma_supported            sn_dma_supported;
+extern ia64_mv_migrate_t                sn_migrate;
+extern ia64_mv_kernel_launch_event_t    sn_kernel_launch_event;
+extern ia64_mv_setup_msi_irq_t          sn_setup_msi_irq;
+extern ia64_mv_teardown_msi_irq_t       sn_teardown_msi_irq;
+extern ia64_mv_pci_fixup_bus_t          sn_pci_fixup_bus;
+
+
+/*
+ * This stuff has dual use!
+ *
+ * For a generic kernel, the macros are used to initialize the
+ * platform's machvec structure.  When compiling a non-generic kernel,
+ * the macros are used directly.
+ */
+#define platform_name                   "sn2"
+#define platform_setup                  sn_setup
+#define platform_cpu_init               sn_cpu_init
+#define platform_irq_init               sn_irq_init
+#define platform_send_ipi               sn2_send_IPI
+#define platform_timer_interrupt        sn_timer_interrupt
+#define platform_global_tlb_purge       sn2_global_tlb_purge
+#define platform_tlb_migrate_finish     sn_tlb_migrate_finish
+#define platform_pci_fixup              sn_pci_fixup
+#define platform_inb                    __sn_inb
+#define platform_inw                    __sn_inw
+#define platform_inl                    __sn_inl
+#define platform_outb                   __sn_outb
+#define platform_outw                   __sn_outw
+#define platform_outl                   __sn_outl
+#define platform_mmiowb                 __sn_mmiowb
+#define platform_readb                  __sn_readb
+#define platform_readw                  __sn_readw
+#define platform_readl                  __sn_readl
+#define platform_readq                  __sn_readq
+#define platform_readb_relaxed          __sn_readb_relaxed
+#define platform_readw_relaxed          __sn_readw_relaxed
+#define platform_readl_relaxed          __sn_readl_relaxed
+#define platform_readq_relaxed          __sn_readq_relaxed
+#define platform_irq_to_vector          sn_irq_to_vector
+#define platform_local_vector_to_irq    sn_local_vector_to_irq
+#define platform_pci_get_legacy_mem     sn_pci_get_legacy_mem
+#define platform_pci_legacy_read        sn_pci_legacy_read
+#define platform_pci_legacy_write       sn_pci_legacy_write
+#define platform_dma_init               machvec_noop
+#define platform_dma_alloc_coherent     sn_dma_alloc_coherent
+#define platform_dma_free_coherent      sn_dma_free_coherent
+#define platform_dma_map_single_attrs   sn_dma_map_single_attrs
+#define platform_dma_unmap_single_attrs sn_dma_unmap_single_attrs
+#define platform_dma_map_sg_attrs       sn_dma_map_sg_attrs
+#define platform_dma_unmap_sg_attrs     sn_dma_unmap_sg_attrs
+#define platform_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu
+#define platform_dma_sync_sg_for_cpu    sn_dma_sync_sg_for_cpu
+#define platform_dma_sync_single_for_device sn_dma_sync_single_for_device
+#define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
+#define platform_dma_mapping_error              sn_dma_mapping_error
+#define platform_dma_supported          sn_dma_supported
+#define platform_migrate                sn_migrate
+#define platform_kernel_launch_event    sn_kernel_launch_event
+#ifdef CONFIG_PCI_MSI
+#define platform_setup_msi_irq          sn_setup_msi_irq
+#define platform_teardown_msi_irq       sn_teardown_msi_irq
+#else
+#define platform_setup_msi_irq          ((ia64_mv_setup_msi_irq_t*)NULL)
+#define platform_teardown_msi_irq       ((ia64_mv_teardown_msi_irq_t*)NULL)
+#endif
+#define platform_pci_fixup_bus          sn_pci_fixup_bus
+
+#include <asm/sn/io.h>
+
+#endif /* _ASM_IA64_MACHVEC_SN2_H */
diff --git a/arch/ia64/include/asm/machvec_uv.h b/arch/ia64/include/asm/machvec_uv.h
new file mode 100644
index 000000000000..2931447f3813
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_uv.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI UV Core Functions
+ *
+ * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_MACHVEC_UV_H
+#define _ASM_IA64_MACHVEC_UV_H
+
+extern ia64_mv_setup_t uv_setup;
+
+/*
+ * This stuff has dual use!
+ *
+ * For a generic kernel, the macros are used to initialize the
+ * platform's machvec structure.  When compiling a non-generic kernel,
+ * the macros are used directly.
+ */
+#define platform_name                   "uv"
+#define platform_setup                  uv_setup
+
+#endif /* _ASM_IA64_MACHVEC_UV_H */
diff --git a/arch/ia64/include/asm/mc146818rtc.h b/arch/ia64/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..407787a237ba
--- /dev/null
+++ b/arch/ia64/include/asm/mc146818rtc.h
@@ -0,0 +1,10 @@
+#ifndef _ASM_IA64_MC146818RTC_H
+#define _ASM_IA64_MC146818RTC_H
+
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+
+/* empty include file to satisfy the include in genrtc.c */
+
+#endif /* _ASM_IA64_MC146818RTC_H */
diff --git a/arch/ia64/include/asm/mca.h b/arch/ia64/include/asm/mca.h
new file mode 100644
index 000000000000..18a4321349a3
--- /dev/null
+++ b/arch/ia64/include/asm/mca.h
@@ -0,0 +1,179 @@
+/*
+ * File:        mca.h
+ * Purpose:     Machine check handling specific defines
+ *
+ * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
+ * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
+ * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
+ * Copyright (C) Russ Anderson <rja@sgi.com>
+ */
+
+#ifndef _ASM_IA64_MCA_H
+#define _ASM_IA64_MCA_H
+
+#if !defined(__ASSEMBLY__)
+
+#include <linux/interrupt.h>
+#include <linux/types.h>
+
+#include <asm/param.h>
+#include <asm/sal.h>
+#include <asm/processor.h>
+#include <asm/mca_asm.h>
+
+#define IA64_MCA_RENDEZ_TIMEOUT         (20 * 1000)     /* value in milliseconds - 20 seconds */
+
+typedef struct ia64_fptr {
+        unsigned long fp;
+        unsigned long gp;
+} ia64_fptr_t;
+
+typedef union cmcv_reg_u {
+        u64     cmcv_regval;
+        struct  {
+                u64     cmcr_vector             : 8;
+                u64     cmcr_reserved1          : 4;
+                u64     cmcr_ignored1           : 1;
+                u64     cmcr_reserved2          : 3;
+                u64     cmcr_mask               : 1;
+                u64     cmcr_ignored2           : 47;
+        } cmcv_reg_s;
+
+} cmcv_reg_t;
+
+#define cmcv_mask               cmcv_reg_s.cmcr_mask
+#define cmcv_vector             cmcv_reg_s.cmcr_vector
+
+enum {
+        IA64_MCA_RENDEZ_CHECKIN_NOTDONE =       0x0,
+        IA64_MCA_RENDEZ_CHECKIN_DONE    =       0x1,
+        IA64_MCA_RENDEZ_CHECKIN_INIT    =       0x2,
+        IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA  =       0x3,
+};
+
+/* Information maintained by the MC infrastructure */
+typedef struct ia64_mc_info_s {
+        u64             imi_mca_handler;
+        size_t          imi_mca_handler_size;
+        u64             imi_monarch_init_handler;
+        size_t          imi_monarch_init_handler_size;
+        u64             imi_slave_init_handler;
+        size_t          imi_slave_init_handler_size;
+        u8              imi_rendez_checkin[NR_CPUS];
+
+} ia64_mc_info_t;
+
+/* Handover state from SAL to OS and vice versa, for both MCA and INIT events.
+ * Besides the handover state, it also contains some saved registers from the
+ * time of the event.
+ * Note: mca_asm.S depends on the precise layout of this structure.
+ */
+
+struct ia64_sal_os_state {
+
+        /* SAL to OS */
+        u64                     os_gp;                  /* GP of the os registered with the SAL, physical */
+        u64                     pal_proc;               /* PAL_PROC entry point, physical */
+        u64                     sal_proc;               /* SAL_PROC entry point, physical */
+        u64                     rv_rc;                  /* MCA - Rendezvous state, INIT - reason code */
+        u64                     proc_state_param;       /* from R18 */
+        u64                     monarch;                /* 1 for a monarch event, 0 for a slave */
+
+        /* common */
+        u64                     sal_ra;                 /* Return address in SAL, physical */
+        u64                     sal_gp;                 /* GP of the SAL - physical */
+        pal_min_state_area_t    *pal_min_state;         /* from R17.  physical in asm, virtual in C */
+        /* Previous values of IA64_KR(CURRENT) and IA64_KR(CURRENT_STACK).
+         * Note: if the MCA/INIT recovery code wants to resume to a new context
+         * then it must change these values to reflect the new kernel stack.
+         */
+        u64                     prev_IA64_KR_CURRENT;   /* previous value of IA64_KR(CURRENT) */
+        u64                     prev_IA64_KR_CURRENT_STACK;
+        struct task_struct      *prev_task;             /* previous task, NULL if it is not useful */
+        /* Some interrupt registers are not saved in minstate, pt_regs or
+         * switch_stack.  Because MCA/INIT can occur when interrupts are
+         * disabled, we need to save the additional interrupt registers over
+         * MCA/INIT and resume.
+         */
+        u64                     isr;
+        u64                     ifa;
+        u64                     itir;
+        u64                     iipa;
+        u64                     iim;
+        u64                     iha;
+
+        /* OS to SAL */
+        u64                     os_status;              /* OS status to SAL, enum below */
+        u64                     context;                /* 0 if return to same context
+                                                           1 if return to new context */
+};
+
+enum {
+        IA64_MCA_CORRECTED      =       0x0,    /* Error has been corrected by OS_MCA */
+        IA64_MCA_WARM_BOOT      =       -1,     /* Warm boot of the system need from SAL */
+        IA64_MCA_COLD_BOOT      =       -2,     /* Cold boot of the system need from SAL */
+        IA64_MCA_HALT           =       -3      /* System to be halted by SAL */
+};
+
+enum {
+        IA64_INIT_RESUME        =       0x0,    /* Resume after return from INIT */
+        IA64_INIT_WARM_BOOT     =       -1,     /* Warm boot of the system need from SAL */
+};
+
+enum {
+        IA64_MCA_SAME_CONTEXT   =       0x0,    /* SAL to return to same context */
+        IA64_MCA_NEW_CONTEXT    =       -1      /* SAL to return to new context */
+};
+
+/* Per-CPU MCA state that is too big for normal per-CPU variables.  */
+
+struct ia64_mca_cpu {
+        u64 mca_stack[KERNEL_STACK_SIZE/8];
+        u64 init_stack[KERNEL_STACK_SIZE/8];
+};
+
+/* Array of physical addresses of each CPU's MCA area.  */
+extern unsigned long __per_cpu_mca[NR_CPUS];
+
+extern int cpe_vector;
+extern int ia64_cpe_irq;
+extern void ia64_mca_init(void);
+extern void ia64_mca_cpu_init(void *);
+extern void ia64_os_mca_dispatch(void);
+extern void ia64_os_mca_dispatch_end(void);
+extern void ia64_mca_ucmc_handler(struct pt_regs *, struct ia64_sal_os_state *);
+extern void ia64_init_handler(struct pt_regs *,
+                              struct switch_stack *,
+                              struct ia64_sal_os_state *);
+extern void ia64_monarch_init_handler(void);
+extern void ia64_slave_init_handler(void);
+extern void ia64_mca_cmc_vector_setup(void);
+extern int  ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *));
+extern void ia64_unreg_MCA_extension(void);
+extern u64 ia64_get_rnat(u64 *);
+extern void ia64_mca_printk(const char * fmt, ...)
+         __attribute__ ((format (printf, 1, 2)));
+
+struct ia64_mca_notify_die {
+        struct ia64_sal_os_state *sos;
+        int *monarch_cpu;
+        int *data;
+};
+
+DECLARE_PER_CPU(u64, ia64_mca_pal_base);
+
+#else   /* __ASSEMBLY__ */
+
+#define IA64_MCA_CORRECTED      0x0     /* Error has been corrected by OS_MCA */
+#define IA64_MCA_WARM_BOOT      -1      /* Warm boot of the system need from SAL */
+#define IA64_MCA_COLD_BOOT      -2      /* Cold boot of the system need from SAL */
+#define IA64_MCA_HALT           -3      /* System to be halted by SAL */
+
+#define IA64_INIT_RESUME        0x0     /* Resume after return from INIT */
+#define IA64_INIT_WARM_BOOT     -1      /* Warm boot of the system need from SAL */
+
+#define IA64_MCA_SAME_CONTEXT   0x0     /* SAL to return to same context */
+#define IA64_MCA_NEW_CONTEXT    -1      /* SAL to return to new context */
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_IA64_MCA_H */
diff --git a/arch/ia64/include/asm/mca_asm.h b/arch/ia64/include/asm/mca_asm.h
new file mode 100644
index 000000000000..dd2a5b134390
--- /dev/null
+++ b/arch/ia64/include/asm/mca_asm.h
@@ -0,0 +1,242 @@
+/*
+ * File:        mca_asm.h
+ * Purpose:     Machine check handling specific defines
+ *
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
+ * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
+ * Copyright (C) 2000 Hewlett-Packard Co.
+ * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
+ * Copyright (C) 2005 Silicon Graphics, Inc
+ * Copyright (C) 2005 Keith Owens <kaos@sgi.com>
+ */
+#ifndef _ASM_IA64_MCA_ASM_H
+#define _ASM_IA64_MCA_ASM_H
+
+#define PSR_IC          13
+#define PSR_I           14
+#define PSR_DT          17
+#define PSR_RT          27
+#define PSR_MC          35
+#define PSR_IT          36
+#define PSR_BN          44
+
+/*
+ * This macro converts a instruction virtual address to a physical address
+ * Right now for simulation purposes the virtual addresses are
+ * direct mapped to physical addresses.
+ *      1. Lop off bits 61 thru 63 in the virtual address
+ */
+#define INST_VA_TO_PA(addr)                                                     \
+        dep     addr    = 0, addr, 61, 3
+/*
+ * This macro converts a data virtual address to a physical address
+ * Right now for simulation purposes the virtual addresses are
+ * direct mapped to physical addresses.
+ *      1. Lop off bits 61 thru 63 in the virtual address
+ */
+#define DATA_VA_TO_PA(addr)                                                     \
+        tpa     addr    = addr
+/*
+ * This macro converts a data physical address to a virtual address
+ * Right now for simulation purposes the virtual addresses are
+ * direct mapped to physical addresses.
+ *      1. Put 0x7 in bits 61 thru 63.
+ */
+#define DATA_PA_TO_VA(addr,temp)                                                        \
+        mov     temp    = 0x7   ;;                                                      \
+        dep     addr    = temp, addr, 61, 3
+
+#define GET_THIS_PADDR(reg, var)                \
+        mov     reg = IA64_KR(PER_CPU_DATA);;   \
+        addl    reg = THIS_CPU(var), reg
+
+/*
+ * This macro jumps to the instruction at the given virtual address
+ * and starts execution in physical mode with all the address
+ * translations turned off.
+ *      1.      Save the current psr
+ *      2.      Make sure that all the upper 32 bits are off
+ *
+ *      3.      Clear the interrupt enable and interrupt state collection bits
+ *              in the psr before updating the ipsr and iip.
+ *
+ *      4.      Turn off the instruction, data and rse translation bits of the psr
+ *              and store the new value into ipsr
+ *              Also make sure that the interrupts are disabled.
+ *              Ensure that we are in little endian mode.
+ *              [psr.{rt, it, dt, i, be} = 0]
+ *
+ *      5.      Get the physical address corresponding to the virtual address
+ *              of the next instruction bundle and put it in iip.
+ *              (Using magic numbers 24 and 40 in the deposint instruction since
+ *               the IA64_SDK code directly maps to lower 24bits as physical address
+ *               from a virtual address).
+ *
+ *      6.      Do an rfi to move the values from ipsr to psr and iip to ip.
+ */
+#define  PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr)                         \
+        mov     old_psr = psr;                                                          \
+        ;;                                                                              \
+        dep     old_psr = 0, old_psr, 32, 32;                                           \
+                                                                                        \
+        mov     ar.rsc = 0 ;                                                            \
+        ;;                                                                              \
+        srlz.d;                                                                         \
+        mov     temp2 = ar.bspstore;                                                    \
+        ;;                                                                              \
+        DATA_VA_TO_PA(temp2);                                                           \
+        ;;                                                                              \
+        mov     temp1 = ar.rnat;                                                        \
+        ;;                                                                              \
+        mov     ar.bspstore = temp2;                                                    \
+        ;;                                                                              \
+        mov     ar.rnat = temp1;                                                        \
+        mov     temp1 = psr;                                                            \
+        mov     temp2 = psr;                                                            \
+        ;;                                                                              \
+                                                                                        \
+        dep     temp2 = 0, temp2, PSR_IC, 2;                                            \
+        ;;                                                                              \
+        mov     psr.l = temp2;                                                          \
+        ;;                                                                              \
+        srlz.d;                                                                         \
+        dep     temp1 = 0, temp1, 32, 32;                                               \
+        ;;                                                                              \
+        dep     temp1 = 0, temp1, PSR_IT, 1;                                            \
+        ;;                                                                              \
+        dep     temp1 = 0, temp1, PSR_DT, 1;                                            \
+        ;;                                                                              \
+        dep     temp1 = 0, temp1, PSR_RT, 1;                                            \
+        ;;                                                                              \
+        dep     temp1 = 0, temp1, PSR_I, 1;                                             \
+        ;;                                                                              \
+        dep     temp1 = 0, temp1, PSR_IC, 1;                                            \
+        ;;                                                                              \
+        dep     temp1 = -1, temp1, PSR_MC, 1;                                           \
+        ;;                                                                              \
+        mov     cr.ipsr = temp1;                                                        \
+        ;;                                                                              \
+        LOAD_PHYSICAL(p0, temp2, start_addr);                                           \
+        ;;                                                                              \
+        mov     cr.iip = temp2;                                                         \
+        mov     cr.ifs = r0;                                                            \
+        DATA_VA_TO_PA(sp);                                                              \
+        DATA_VA_TO_PA(gp);                                                              \
+        ;;                                                                              \
+        srlz.i;                                                                         \
+        ;;                                                                              \
+        nop     1;                                                                      \
+        nop     2;                                                                      \
+        nop     1;                                                                      \
+        nop     2;                                                                      \
+        rfi;                                                                            \
+        ;;
+
+/*
+ * This macro jumps to the instruction at the given virtual address
+ * and starts execution in virtual mode with all the address
+ * translations turned on.
+ *      1.      Get the old saved psr
+ *
+ *      2.      Clear the interrupt state collection bit in the current psr.
+ *
+ *      3.      Set the instruction translation bit back in the old psr
+ *              Note we have to do this since we are right now saving only the
+ *              lower 32-bits of old psr.(Also the old psr has the data and
+ *              rse translation bits on)
+ *
+ *      4.      Set ipsr to this old_psr with "it" bit set and "bn" = 1.
+ *
+ *      5.      Reset the current thread pointer (r13).
+ *
+ *      6.      Set iip to the virtual address of the next instruction bundle.
+ *
+ *      7.      Do an rfi to move ipsr to psr and iip to ip.
+ */
+
+#define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr)   \
+        mov     temp2 = psr;                                    \
+        ;;                                                      \
+        mov     old_psr = temp2;                                \
+        ;;                                                      \
+        dep     temp2 = 0, temp2, PSR_IC, 2;                    \
+        ;;                                                      \
+        mov     psr.l = temp2;                                  \
+        mov     ar.rsc = 0;                                     \
+        ;;                                                      \
+        srlz.d;                                                 \
+        mov     r13 = ar.k6;                                    \
+        mov     temp2 = ar.bspstore;                            \
+        ;;                                                      \
+        DATA_PA_TO_VA(temp2,temp1);                             \
+        ;;                                                      \
+        mov     temp1 = ar.rnat;                                \
+        ;;                                                      \
+        mov     ar.bspstore = temp2;                            \
+        ;;                                                      \
+        mov     ar.rnat = temp1;                                \
+        ;;                                                      \
+        mov     temp1 = old_psr;                                \
+        ;;                                                      \
+        mov     temp2 = 1;                                      \
+        ;;                                                      \
+        dep     temp1 = temp2, temp1, PSR_IC, 1;                \
+        ;;                                                      \
+        dep     temp1 = temp2, temp1, PSR_IT, 1;                \
+        ;;                                                      \
+        dep     temp1 = temp2, temp1, PSR_DT, 1;                \
+        ;;                                                      \
+        dep     temp1 = temp2, temp1, PSR_RT, 1;                \
+        ;;                                                      \
+        dep     temp1 = temp2, temp1, PSR_BN, 1;                \
+        ;;                                                      \
+                                                                \
+        mov     cr.ipsr = temp1;                                \
+        movl    temp2 = start_addr;                             \
+        ;;                                                      \
+        mov     cr.iip = temp2;                                 \
+        movl    gp = __gp                                       \
+        ;;                                                      \
+        DATA_PA_TO_VA(sp, temp1);                               \
+        srlz.i;                                                 \
+        ;;                                                      \
+        nop     1;                                              \
+        nop     2;                                              \
+        nop     1;                                              \
+        rfi                                                     \
+        ;;
+
+/*
+ * The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel
+ * stacks, except that the SAL/OS state and a switch_stack are stored near the
+ * top of the MCA/INIT stack.  To support concurrent entry to MCA or INIT, as
+ * well as MCA over INIT, each event needs its own SAL/OS state.  All entries
+ * are 16 byte aligned.
+ *
+ *      +---------------------------+
+ *      |          pt_regs          |
+ *      +---------------------------+
+ *      |        switch_stack       |
+ *      +---------------------------+
+ *      |        SAL/OS state       |
+ *      +---------------------------+
+ *      |    16 byte scratch area   |
+ *      +---------------------------+ <-------- SP at start of C MCA handler
+ *      |           .....           |
+ *      +---------------------------+
+ *      | RBS for MCA/INIT handler  |
+ *      +---------------------------+
+ *      | struct task for MCA/INIT  |
+ *      +---------------------------+ <-------- Bottom of MCA/INIT stack
+ */
+
+#define ALIGN16(x)                      ((x)&~15)
+#define MCA_PT_REGS_OFFSET              ALIGN16(KERNEL_STACK_SIZE-IA64_PT_REGS_SIZE)
+#define MCA_SWITCH_STACK_OFFSET         ALIGN16(MCA_PT_REGS_OFFSET-IA64_SWITCH_STACK_SIZE)
+#define MCA_SOS_OFFSET                  ALIGN16(MCA_SWITCH_STACK_OFFSET-IA64_SAL_OS_STATE_SIZE)
+#define MCA_SP_OFFSET                   ALIGN16(MCA_SOS_OFFSET-16)
+
+#endif /* _ASM_IA64_MCA_ASM_H */
diff --git a/arch/ia64/include/asm/meminit.h b/arch/ia64/include/asm/meminit.h
new file mode 100644
index 000000000000..7245a5781594
--- /dev/null
+++ b/arch/ia64/include/asm/meminit.h
@@ -0,0 +1,75 @@
+#ifndef meminit_h
+#define meminit_h
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+
+/*
+ * Entries defined so far:
+ *      - boot param structure itself
+ *      - memory map
+ *      - initrd (optional)
+ *      - command line string
+ *      - kernel code & data
+ *      - crash dumping code reserved region
+ *      - Kernel memory map built from EFI memory map
+ *      - ELF core header
+ *
+ * More could be added if necessary
+ */
+#define IA64_MAX_RSVD_REGIONS 8
+
+struct rsvd_region {
+        unsigned long start;    /* virtual address of beginning of element */
+        unsigned long end;      /* virtual address of end of element + 1 */
+};
+
+extern struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
+extern int num_rsvd_regions;
+
+extern void find_memory (void);
+extern void reserve_memory (void);
+extern void find_initrd (void);
+extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg);
+extern int filter_memory (unsigned long start, unsigned long end, void *arg);
+extern unsigned long efi_memmap_init(unsigned long *s, unsigned long *e);
+extern int find_max_min_low_pfn (unsigned long , unsigned long, void *);
+
+extern unsigned long vmcore_find_descriptor_size(unsigned long address);
+extern int reserve_elfcorehdr(unsigned long *start, unsigned long *end);
+
+/*
+ * For rounding an address to the next IA64_GRANULE_SIZE or order
+ */
+#define GRANULEROUNDDOWN(n)     ((n) & ~(IA64_GRANULE_SIZE-1))
+#define GRANULEROUNDUP(n)       (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1))
+#define ORDERROUNDDOWN(n)       ((n) & ~((PAGE_SIZE<<MAX_ORDER)-1))
+
+#ifdef CONFIG_NUMA
+  extern void call_pernode_memory (unsigned long start, unsigned long len, void *func);
+#else
+# define call_pernode_memory(start, len, func)  (*func)(start, len, 0)
+#endif
+
+#define IGNORE_PFN0     1       /* XXX fix me: ignore pfn 0 until TLB miss handler is updated... */
+
+extern int register_active_ranges(u64 start, u64 len, int nid);
+
+#ifdef CONFIG_VIRTUAL_MEM_MAP
+# define LARGE_GAP      0x40000000 /* Use virtual mem map if hole is > than this */
+  extern unsigned long vmalloc_end;
+  extern struct page *vmem_map;
+  extern int find_largest_hole (u64 start, u64 end, void *arg);
+  extern int create_mem_map_page_table (u64 start, u64 end, void *arg);
+  extern int vmemmap_find_next_valid_pfn(int, int);
+#else
+static inline int vmemmap_find_next_valid_pfn(int node, int i)
+{
+        return i + 1;
+}
+#endif
+#endif /* meminit_h */
diff --git a/arch/ia64/include/asm/mman.h b/arch/ia64/include/asm/mman.h
new file mode 100644
index 000000000000..c73b87832a1e
--- /dev/null
+++ b/arch/ia64/include/asm/mman.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_IA64_MMAN_H
+#define _ASM_IA64_MMAN_H
+
+/*
+ * Based on <asm-i386/mman.h>.
+ *
+ * Modified 1998-2000, 2002
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#include <asm-generic/mman.h>
+
+#define MAP_GROWSDOWN   0x00100         /* stack-like segment */
+#define MAP_GROWSUP     0x00200         /* register stack-like segment */
+#define MAP_DENYWRITE   0x00800         /* ETXTBSY */
+#define MAP_EXECUTABLE  0x01000         /* mark it as an executable */
+#define MAP_LOCKED      0x02000         /* pages are locked */
+#define MAP_NORESERVE   0x04000         /* don't check for reservations */
+#define MAP_POPULATE    0x08000         /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#define arch_mmap_check ia64_mmap_check
+int ia64_mmap_check(unsigned long addr, unsigned long len,
+                unsigned long flags);
+#endif
+#endif
+
+#endif /* _ASM_IA64_MMAN_H */
diff --git a/arch/ia64/include/asm/mmu.h b/arch/ia64/include/asm/mmu.h
new file mode 100644
index 000000000000..611432ba579c
--- /dev/null
+++ b/arch/ia64/include/asm/mmu.h
@@ -0,0 +1,13 @@
+#ifndef __MMU_H
+#define __MMU_H
+
+/*
+ * Type for a context number.  We declare it volatile to ensure proper
+ * ordering when it's accessed outside of spinlock'd critical sections
+ * (e.g., as done in activate_mm() and init_new_context()).
+ */
+typedef volatile unsigned long mm_context_t;
+
+typedef unsigned long nv_mm_context_t;
+
+#endif
diff --git a/arch/ia64/include/asm/mmu_context.h b/arch/ia64/include/asm/mmu_context.h
new file mode 100644
index 000000000000..040bc87db930
--- /dev/null
+++ b/arch/ia64/include/asm/mmu_context.h
@@ -0,0 +1,198 @@
+#ifndef _ASM_IA64_MMU_CONTEXT_H
+#define _ASM_IA64_MMU_CONTEXT_H
+
+/*
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+/*
+ * Routines to manage the allocation of task context numbers.  Task context
+ * numbers are used to reduce or eliminate the need to perform TLB flushes
+ * due to context switches.  Context numbers are implemented using ia-64
+ * region ids.  Since the IA-64 TLB does not consider the region number when
+ * performing a TLB lookup, we need to assign a unique region id to each
+ * region in a process.  We use the least significant three bits in aregion
+ * id for this purpose.
+ */
+
+#define IA64_REGION_ID_KERNEL   0 /* the kernel's region id (tlb.c depends on this being 0) */
+
+#define ia64_rid(ctx,addr)      (((ctx) << 3) | (addr >> 61))
+
+# include <asm/page.h>
+# ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <linux/percpu.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+
+#include <asm/processor.h>
+#include <asm-generic/mm_hooks.h>
+
+struct ia64_ctx {
+        spinlock_t lock;
+        unsigned int next;      /* next context number to use */
+        unsigned int limit;     /* available free range */
+        unsigned int max_ctx;   /* max. context value supported by all CPUs */
+                                /* call wrap_mmu_context when next >= max */
+        unsigned long *bitmap;  /* bitmap size is max_ctx+1 */
+        unsigned long *flushmap;/* pending rid to be flushed */
+};
+
+extern struct ia64_ctx ia64_ctx;
+DECLARE_PER_CPU(u8, ia64_need_tlb_flush);
+
+extern void mmu_context_init (void);
+extern void wrap_mmu_context (struct mm_struct *mm);
+
+static inline void
+enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/*
+ * When the context counter wraps around all TLBs need to be flushed because
+ * an old context number might have been reused. This is signalled by the
+ * ia64_need_tlb_flush per-CPU variable, which is checked in the routine
+ * below. Called by activate_mm(). <efocht@ess.nec.de>
+ */
+static inline void
+delayed_tlb_flush (void)
+{
+        extern void local_flush_tlb_all (void);
+        unsigned long flags;
+
+        if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
+                spin_lock_irqsave(&ia64_ctx.lock, flags);
+                if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
+                        local_flush_tlb_all();
+                        __ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
+                }
+                spin_unlock_irqrestore(&ia64_ctx.lock, flags);
+        }
+}
+
+static inline nv_mm_context_t
+get_mmu_context (struct mm_struct *mm)
+{
+        unsigned long flags;
+        nv_mm_context_t context = mm->context;
+
+        if (likely(context))
+                goto out;
+
+        spin_lock_irqsave(&ia64_ctx.lock, flags);
+        /* re-check, now that we've got the lock: */
+        context = mm->context;
+        if (context == 0) {
+                cpus_clear(mm->cpu_vm_mask);
+                if (ia64_ctx.next >= ia64_ctx.limit) {
+                        ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
+                                        ia64_ctx.max_ctx, ia64_ctx.next);
+                        ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
+                                        ia64_ctx.max_ctx, ia64_ctx.next);
+                        if (ia64_ctx.next >= ia64_ctx.max_ctx)
+                                wrap_mmu_context(mm);
+                }
+                mm->context = context = ia64_ctx.next++;
+                __set_bit(context, ia64_ctx.bitmap);
+        }
+        spin_unlock_irqrestore(&ia64_ctx.lock, flags);
+out:
+        /*
+         * Ensure we're not starting to use "context" before any old
+         * uses of it are gone from our TLB.
+         */
+        delayed_tlb_flush();
+
+        return context;
+}
+
+/*
+ * Initialize context number to some sane value.  MM is guaranteed to be a
+ * brand-new address-space, so no TLB flushing is needed, ever.
+ */
+static inline int
+init_new_context (struct task_struct *p, struct mm_struct *mm)
+{
+        mm->context = 0;
+        return 0;
+}
+
+static inline void
+destroy_context (struct mm_struct *mm)
+{
+        /* Nothing to do.  */
+}
+
+static inline void
+reload_context (nv_mm_context_t context)
+{
+        unsigned long rid;
+        unsigned long rid_incr = 0;
+        unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
+
+        old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
+        rid = context << 3;     /* make space for encoding the region number */
+        rid_incr = 1 << 8;
+
+        /* encode the region id, preferred page size, and VHPT enable bit: */
+        rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1;
+        rr1 = rr0 + 1*rid_incr;
+        rr2 = rr0 + 2*rid_incr;
+        rr3 = rr0 + 3*rid_incr;
+        rr4 = rr0 + 4*rid_incr;
+#ifdef  CONFIG_HUGETLB_PAGE
+        rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);
+
+#  if RGN_HPAGE != 4
+#    error "reload_context assumes RGN_HPAGE is 4"
+#  endif
+#endif
+
+        ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4);
+        ia64_srlz_i();                  /* srlz.i implies srlz.d */
+}
+
+/*
+ * Must be called with preemption off
+ */
+static inline void
+activate_context (struct mm_struct *mm)
+{
+        nv_mm_context_t context;
+
+        do {
+                context = get_mmu_context(mm);
+                if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
+                        cpu_set(smp_processor_id(), mm->cpu_vm_mask);
+                reload_context(context);
+                /*
+                 * in the unlikely event of a TLB-flush by another thread,
+                 * redo the load.
+                 */
+        } while (unlikely(context != mm->context));
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+/*
+ * Switch from address space PREV to address space NEXT.
+ */
+static inline void
+activate_mm (struct mm_struct *prev, struct mm_struct *next)
+{
+        /*
+         * We may get interrupts here, but that's OK because interrupt
+         * handlers cannot touch user-space.
+         */
+        ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
+        activate_context(next);
+}
+
+#define switch_mm(prev_mm,next_mm,next_task)    activate_mm(prev_mm, next_mm)
+
+# endif /* ! __ASSEMBLY__ */
+#endif /* _ASM_IA64_MMU_CONTEXT_H */
diff --git a/arch/ia64/include/asm/mmzone.h b/arch/ia64/include/asm/mmzone.h
new file mode 100644
index 000000000000..34efe88eb849
--- /dev/null
+++ b/arch/ia64/include/asm/mmzone.h
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000,2003 Silicon Graphics, Inc.  All rights reserved.
+ * Copyright (c) 2002 NEC Corp.
+ * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de>
+ * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com>
+ */
+#ifndef _ASM_IA64_MMZONE_H
+#define _ASM_IA64_MMZONE_H
+
+#include <linux/numa.h>
+#include <asm/page.h>
+#include <asm/meminit.h>
+
+#ifdef CONFIG_NUMA
+
+static inline int pfn_to_nid(unsigned long pfn)
+{
+#ifdef CONFIG_NUMA
+        extern int paddr_to_nid(unsigned long);
+        int nid = paddr_to_nid(pfn << PAGE_SHIFT);
+        if (nid < 0)
+                return 0;
+        else
+                return nid;
+#else
+        return 0;
+#endif
+}
+
+#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
+extern int early_pfn_to_nid(unsigned long pfn);
+#endif
+
+#ifdef CONFIG_IA64_DIG /* DIG systems are small */
+# define MAX_PHYSNODE_ID        8
+# define NR_NODE_MEMBLKS        (MAX_NUMNODES * 8)
+#else /* sn2 is the biggest case, so we use that if !DIG */
+# define MAX_PHYSNODE_ID        2048
+# define NR_NODE_MEMBLKS        (MAX_NUMNODES * 4)
+#endif
+
+#else /* CONFIG_NUMA */
+# define NR_NODE_MEMBLKS        (MAX_NUMNODES * 4)
+#endif /* CONFIG_NUMA */
+
+#endif /* _ASM_IA64_MMZONE_H */
diff --git a/arch/ia64/include/asm/module.h b/arch/ia64/include/asm/module.h
new file mode 100644
index 000000000000..d2da61e4c49b
--- /dev/null
+++ b/arch/ia64/include/asm/module.h
@@ -0,0 +1,36 @@
+#ifndef _ASM_IA64_MODULE_H
+#define _ASM_IA64_MODULE_H
+
+/*
+ * IA-64-specific support for kernel module loader.
+ *
+ * Copyright (C) 2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+struct elf64_shdr;                      /* forward declration */
+
+struct mod_arch_specific {
+        struct elf64_shdr *core_plt;    /* core PLT section */
+        struct elf64_shdr *init_plt;    /* init PLT section */
+        struct elf64_shdr *got;         /* global offset table */
+        struct elf64_shdr *opd;         /* official procedure descriptors */
+        struct elf64_shdr *unwind;      /* unwind-table section */
+        unsigned long gp;               /* global-pointer for module */
+
+        void *core_unw_table;           /* core unwind-table cookie returned by unwinder */
+        void *init_unw_table;           /* init unwind-table cookie returned by unwinder */
+        unsigned int next_got_entry;    /* index of next available got entry */
+};
+
+#define Elf_Shdr        Elf64_Shdr
+#define Elf_Sym         Elf64_Sym
+#define Elf_Ehdr        Elf64_Ehdr
+
+#define MODULE_PROC_FAMILY      "ia64"
+#define MODULE_ARCH_VERMAGIC    MODULE_PROC_FAMILY \
+        "gcc-" __stringify(__GNUC__) "." __stringify(__GNUC_MINOR__)
+
+#define ARCH_SHF_SMALL  SHF_IA_64_SHORT
+
+#endif /* _ASM_IA64_MODULE_H */
diff --git a/arch/ia64/include/asm/msgbuf.h b/arch/ia64/include/asm/msgbuf.h
new file mode 100644
index 000000000000..6c64c0d2aae1
--- /dev/null
+++ b/arch/ia64/include/asm/msgbuf.h
@@ -0,0 +1,27 @@
+#ifndef _ASM_IA64_MSGBUF_H
+#define _ASM_IA64_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for IA-64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused1;
+        unsigned long  __unused2;
+};
+
+#endif /* _ASM_IA64_MSGBUF_H */
diff --git a/arch/ia64/include/asm/mutex.h b/arch/ia64/include/asm/mutex.h
new file mode 100644
index 000000000000..bed73a643a56
--- /dev/null
+++ b/arch/ia64/include/asm/mutex.h
@@ -0,0 +1,92 @@
+/*
+ * ia64 implementation of the mutex fastpath.
+ *
+ * Copyright (C) 2006 Ken Chen <kenneth.w.chen@intel.com>
+ *
+ */
+
+#ifndef _ASM_MUTEX_H
+#define _ASM_MUTEX_H
+
+/**
+ *  __mutex_fastpath_lock - try to take the lock by moving the count
+ *                          from 1 to a 0 value
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: function to call if the original value was not 1
+ *
+ * Change the count from 1 to a value lower than 1, and call <fail_fn> if
+ * it wasn't 1 originally. This function MUST leave the value lower than
+ * 1 even when the "1" assertion wasn't true.
+ */
+static inline void
+__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
+{
+        if (unlikely(ia64_fetchadd4_acq(count, -1) != 1))
+                fail_fn(count);
+}
+
+/**
+ *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
+ *                                 from 1 to a 0 value
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: function to call if the original value was not 1
+ *
+ * Change the count from 1 to a value lower than 1, and call <fail_fn> if
+ * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
+ * or anything the slow path function returns.
+ */
+static inline int
+__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
+{
+        if (unlikely(ia64_fetchadd4_acq(count, -1) != 1))
+                return fail_fn(count);
+        return 0;
+}
+
+/**
+ *  __mutex_fastpath_unlock - try to promote the count from 0 to 1
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: function to call if the original value was not 0
+ *
+ * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>.
+ * In the failure case, this function is allowed to either set the value to
+ * 1, or to set it to a value lower than 1.
+ *
+ * If the implementation sets it to a value of lower than 1, then the
+ * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
+ * to return 0 otherwise.
+ */
+static inline void
+__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
+{
+        int ret = ia64_fetchadd4_rel(count, 1);
+        if (unlikely(ret < 0))
+                fail_fn(count);
+}
+
+#define __mutex_slowpath_needs_to_unlock()              1
+
+/**
+ * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
+ *
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: fallback function
+ *
+ * Change the count from 1 to a value lower than 1, and return 0 (failure)
+ * if it wasn't 1 originally, or return 1 (success) otherwise. This function
+ * MUST leave the value lower than 1 even when the "1" assertion wasn't true.
+ * Additionally, if the value was < 0 originally, this function must not leave
+ * it to 0 on failure.
+ *
+ * If the architecture has no effective trylock variant, it should call the
+ * <fail_fn> spinlock-based trylock variant unconditionally.
+ */
+static inline int
+__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
+{
+        if (cmpxchg_acq(count, 1, 0) == 1)
+                return 1;
+        return 0;
+}
+
+#endif
diff --git a/arch/ia64/include/asm/native/inst.h b/arch/ia64/include/asm/native/inst.h
new file mode 100644
index 000000000000..c8efbf7b849e
--- /dev/null
+++ b/arch/ia64/include/asm/native/inst.h
@@ -0,0 +1,175 @@
+/******************************************************************************
+ * arch/ia64/include/asm/native/inst.h
+ *
+ * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#define DO_SAVE_MIN             IA64_NATIVE_DO_SAVE_MIN
+
+#define __paravirt_switch_to                    ia64_native_switch_to
+#define __paravirt_leave_syscall                ia64_native_leave_syscall
+#define __paravirt_work_processed_syscall       ia64_native_work_processed_syscall
+#define __paravirt_leave_kernel                 ia64_native_leave_kernel
+#define __paravirt_pending_syscall_end          ia64_work_pending_syscall_end
+#define __paravirt_work_processed_syscall_target \
+                                                ia64_work_processed_syscall
+
+#ifdef CONFIG_PARAVIRT_GUEST_ASM_CLOBBER_CHECK
+# define PARAVIRT_POISON        0xdeadbeefbaadf00d
+# define CLOBBER(clob)                          \
+        ;;                                      \
+        movl clob = PARAVIRT_POISON;            \
+        ;;
+#else
+# define CLOBBER(clob)          /* nothing */
+#endif
+
+#define MOV_FROM_IFA(reg)       \
+        mov reg = cr.ifa
+
+#define MOV_FROM_ITIR(reg)      \
+        mov reg = cr.itir
+
+#define MOV_FROM_ISR(reg)       \
+        mov reg = cr.isr
+
+#define MOV_FROM_IHA(reg)       \
+        mov reg = cr.iha
+
+#define MOV_FROM_IPSR(pred, reg)        \
+(pred)  mov reg = cr.ipsr
+
+#define MOV_FROM_IIM(reg)       \
+        mov reg = cr.iim
+
+#define MOV_FROM_IIP(reg)       \
+        mov reg = cr.iip
+
+#define MOV_FROM_IVR(reg, clob) \
+        mov reg = cr.ivr        \
+        CLOBBER(clob)
+
+#define MOV_FROM_PSR(pred, reg, clob)   \
+(pred)  mov reg = psr                   \
+        CLOBBER(clob)
+
+#define MOV_TO_IFA(reg, clob)   \
+        mov cr.ifa = reg        \
+        CLOBBER(clob)
+
+#define MOV_TO_ITIR(pred, reg, clob)    \
+(pred)  mov cr.itir = reg               \
+        CLOBBER(clob)
+
+#define MOV_TO_IHA(pred, reg, clob)     \
+(pred)  mov cr.iha = reg                \
+        CLOBBER(clob)
+
+#define MOV_TO_IPSR(pred, reg, clob)            \
+(pred)  mov cr.ipsr = reg                       \
+        CLOBBER(clob)
+
+#define MOV_TO_IFS(pred, reg, clob)     \
+(pred)  mov cr.ifs = reg                \
+        CLOBBER(clob)
+
+#define MOV_TO_IIP(reg, clob)   \
+        mov cr.iip = reg        \
+        CLOBBER(clob)
+
+#define MOV_TO_KR(kr, reg, clob0, clob1)        \
+        mov IA64_KR(kr) = reg                   \
+        CLOBBER(clob0)                          \
+        CLOBBER(clob1)
+
+#define ITC_I(pred, reg, clob)  \
+(pred)  itc.i reg               \
+        CLOBBER(clob)
+
+#define ITC_D(pred, reg, clob)  \
+(pred)  itc.d reg               \
+        CLOBBER(clob)
+
+#define ITC_I_AND_D(pred_i, pred_d, reg, clob)  \
+(pred_i) itc.i reg;                             \
+(pred_d) itc.d reg                              \
+        CLOBBER(clob)
+
+#define THASH(pred, reg0, reg1, clob)           \
+(pred)  thash reg0 = reg1                       \
+        CLOBBER(clob)
+
+#define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1)            \
+        ssm psr.ic | PSR_DEFAULT_BITS                                   \
+        CLOBBER(clob0)                                                  \
+        CLOBBER(clob1)                                                  \
+        ;;                                                              \
+        srlz.i /* guarantee that interruption collectin is on */        \
+        ;;
+
+#define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1)     \
+        ssm psr.ic                              \
+        CLOBBER(clob0)                          \
+        CLOBBER(clob1)                          \
+        ;;                                      \
+        srlz.d
+
+#define RSM_PSR_IC(clob)        \
+        rsm psr.ic              \
+        CLOBBER(clob)
+
+#define SSM_PSR_I(pred, pred_clob, clob)        \
+(pred)  ssm psr.i                               \
+        CLOBBER(clob)
+
+#define RSM_PSR_I(pred, clob0, clob1)   \
+(pred)  rsm psr.i                       \
+        CLOBBER(clob0)                  \
+        CLOBBER(clob1)
+
+#define RSM_PSR_I_IC(clob0, clob1, clob2)       \
+        rsm psr.i | psr.ic                      \
+        CLOBBER(clob0)                          \
+        CLOBBER(clob1)                          \
+        CLOBBER(clob2)
+
+#define RSM_PSR_DT              \
+        rsm psr.dt
+
+#define SSM_PSR_DT_AND_SRLZ_I   \
+        ssm psr.dt              \
+        ;;                      \
+        srlz.i
+
+#define BSW_0(clob0, clob1, clob2)      \
+        bsw.0                           \
+        CLOBBER(clob0)                  \
+        CLOBBER(clob1)                  \
+        CLOBBER(clob2)
+
+#define BSW_1(clob0, clob1)     \
+        bsw.1                   \
+        CLOBBER(clob0)          \
+        CLOBBER(clob1)
+
+#define COVER   \
+        cover
+
+#define RFI     \
+        rfi
diff --git a/arch/ia64/include/asm/native/irq.h b/arch/ia64/include/asm/native/irq.h
new file mode 100644
index 000000000000..887a228e2edb
--- /dev/null
+++ b/arch/ia64/include/asm/native/irq.h
@@ -0,0 +1,33 @@
+/******************************************************************************
+ * arch/ia64/include/asm/native/irq.h
+ *
+ * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _ASM_IA64_NATIVE_IRQ_H
+#define _ASM_IA64_NATIVE_IRQ_H
+
+#define NR_VECTORS      256
+
+#if (NR_VECTORS + 32 * NR_CPUS) < 1024
+#define IA64_NATIVE_NR_IRQS (NR_VECTORS + 32 * NR_CPUS)
+#else
+#define IA64_NATIVE_NR_IRQS 1024
+#endif
+
+#endif /* _ASM_IA64_NATIVE_IRQ_H */
diff --git a/arch/ia64/include/asm/nodedata.h b/arch/ia64/include/asm/nodedata.h
new file mode 100644
index 000000000000..2fb337b0e9b7
--- /dev/null
+++ b/arch/ia64/include/asm/nodedata.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000 Silicon Graphics, Inc.  All rights reserved.
+ * Copyright (c) 2002 NEC Corp.
+ * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de>
+ * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com>
+ */
+#ifndef _ASM_IA64_NODEDATA_H
+#define _ASM_IA64_NODEDATA_H
+
+#include <linux/numa.h>
+
+#include <asm/percpu.h>
+#include <asm/mmzone.h>
+
+#ifdef CONFIG_NUMA
+
+/*
+ * Node Data. One of these structures is located on each node of a NUMA system.
+ */
+
+struct pglist_data;
+struct ia64_node_data {
+        short                   active_cpu_count;
+        short                   node;
+        struct pglist_data      *pg_data_ptrs[MAX_NUMNODES];
+};
+
+
+/*
+ * Return a pointer to the node_data structure for the executing cpu.
+ */
+#define local_node_data         (local_cpu_data->node_data)
+
+/*
+ * Given a node id, return a pointer to the pg_data_t for the node.
+ *
+ * NODE_DATA    - should be used in all code not related to system
+ *                initialization. It uses pernode data structures to minimize
+ *                offnode memory references. However, these structure are not 
+ *                present during boot. This macro can be used once cpu_init
+ *                completes.
+ */
+#define NODE_DATA(nid)          (local_node_data->pg_data_ptrs[nid])
+
+/*
+ * LOCAL_DATA_ADDR - This is to calculate the address of other node's
+ *                   "local_node_data" at hot-plug phase. The local_node_data
+ *                   is pointed by per_cpu_page. Kernel usually use it for
+ *                   just executing cpu. However, when new node is hot-added,
+ *                   the addresses of local data for other nodes are necessary
+ *                   to update all of them.
+ */
+#define LOCAL_DATA_ADDR(pgdat)                          \
+        ((struct ia64_node_data *)((u64)(pgdat) +       \
+                                   L1_CACHE_ALIGN(sizeof(struct pglist_data))))
+
+#endif /* CONFIG_NUMA */
+
+#endif /* _ASM_IA64_NODEDATA_H */
diff --git a/arch/ia64/include/asm/numa.h b/arch/ia64/include/asm/numa.h
new file mode 100644
index 000000000000..3499ff57bf42
--- /dev/null
+++ b/arch/ia64/include/asm/numa.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file contains NUMA specific prototypes and definitions.
+ *
+ * 2002/08/05 Erich Focht <efocht@ess.nec.de>
+ *
+ */
+#ifndef _ASM_IA64_NUMA_H
+#define _ASM_IA64_NUMA_H
+
+
+#ifdef CONFIG_NUMA
+
+#include <linux/cache.h>
+#include <linux/cpumask.h>
+#include <linux/numa.h>
+#include <linux/smp.h>
+#include <linux/threads.h>
+
+#include <asm/mmzone.h>
+
+#define NUMA_NO_NODE    -1
+
+extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
+extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
+extern pg_data_t *pgdat_list[MAX_NUMNODES];
+
+/* Stuff below this line could be architecture independent */
+
+extern int num_node_memblks;            /* total number of memory chunks */
+
+/*
+ * List of node memory chunks. Filled when parsing SRAT table to
+ * obtain information about memory nodes.
+*/
+
+struct node_memblk_s {
+        unsigned long start_paddr;
+        unsigned long size;
+        int nid;                /* which logical node contains this chunk? */
+        int bank;               /* which mem bank on this node */
+};
+
+struct node_cpuid_s {
+        u16     phys_id;        /* id << 8 | eid */
+        int     nid;            /* logical node containing this CPU */
+};
+
+extern struct node_memblk_s node_memblk[NR_NODE_MEMBLKS];
+extern struct node_cpuid_s node_cpuid[NR_CPUS];
+
+/*
+ * ACPI 2.0 SLIT (System Locality Information Table)
+ * http://devresource.hp.com/devresource/Docs/TechPapers/IA64/slit.pdf
+ *
+ * This is a matrix with "distances" between nodes, they should be
+ * proportional to the memory access latency ratios.
+ */
+
+extern u8 numa_slit[MAX_NUMNODES * MAX_NUMNODES];
+#define node_distance(from,to) (numa_slit[(from) * num_online_nodes() + (to)])
+
+extern int paddr_to_nid(unsigned long paddr);
+
+#define local_nodeid (cpu_to_node_map[smp_processor_id()])
+
+extern void map_cpu_to_node(int cpu, int nid);
+extern void unmap_cpu_from_node(int cpu, int nid);
+
+
+#else /* !CONFIG_NUMA */
+#define map_cpu_to_node(cpu, nid)       do{}while(0)
+#define unmap_cpu_from_node(cpu, nid)   do{}while(0)
+
+#define paddr_to_nid(addr)      0
+
+#endif /* CONFIG_NUMA */
+
+#endif /* _ASM_IA64_NUMA_H */
diff --git a/arch/ia64/include/asm/page.h b/arch/ia64/include/asm/page.h
new file mode 100644
index 000000000000..5f271bc712ee
--- /dev/null
+++ b/arch/ia64/include/asm/page.h
@@ -0,0 +1,223 @@
+#ifndef _ASM_IA64_PAGE_H
+#define _ASM_IA64_PAGE_H
+/*
+ * Pagetable related stuff.
+ *
+ * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <asm/intrinsics.h>
+#include <asm/types.h>
+
+/*
+ * The top three bits of an IA64 address are its Region Number.
+ * Different regions are assigned to different purposes.
+ */
+#define RGN_SHIFT       (61)
+#define RGN_BASE(r)     (__IA64_UL_CONST(r)<<RGN_SHIFT)
+#define RGN_BITS        (RGN_BASE(-1))
+
+#define RGN_KERNEL      7       /* Identity mapped region */
+#define RGN_UNCACHED    6       /* Identity mapped I/O region */
+#define RGN_GATE        5       /* Gate page, Kernel text, etc */
+#define RGN_HPAGE       4       /* For Huge TLB pages */
+
+/*
+ * PAGE_SHIFT determines the actual kernel page size.
+ */
+#if defined(CONFIG_IA64_PAGE_SIZE_4KB)
+# define PAGE_SHIFT     12
+#elif defined(CONFIG_IA64_PAGE_SIZE_8KB)
+# define PAGE_SHIFT     13
+#elif defined(CONFIG_IA64_PAGE_SIZE_16KB)
+# define PAGE_SHIFT     14
+#elif defined(CONFIG_IA64_PAGE_SIZE_64KB)
+# define PAGE_SHIFT     16
+#else
+# error Unsupported page size!
+#endif
+
+#define PAGE_SIZE               (__IA64_UL_CONST(1) << PAGE_SHIFT)
+#define PAGE_MASK               (~(PAGE_SIZE - 1))
+
+#define PERCPU_PAGE_SHIFT       16      /* log2() of max. size of per-CPU area */
+#define PERCPU_PAGE_SIZE        (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
+
+
+#ifdef CONFIG_HUGETLB_PAGE
+# define HPAGE_REGION_BASE      RGN_BASE(RGN_HPAGE)
+# define HPAGE_SHIFT            hpage_shift
+# define HPAGE_SHIFT_DEFAULT    28      /* check ia64 SDM for architecture supported size */
+# define HPAGE_SIZE             (__IA64_UL_CONST(1) << HPAGE_SHIFT)
+# define HPAGE_MASK             (~(HPAGE_SIZE - 1))
+
+# define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+#endif /* CONFIG_HUGETLB_PAGE */
+
+#ifdef __ASSEMBLY__
+# define __pa(x)                ((x) - PAGE_OFFSET)
+# define __va(x)                ((x) + PAGE_OFFSET)
+#else /* !__ASSEMBLY */
+#  define STRICT_MM_TYPECHECKS
+
+extern void clear_page (void *page);
+extern void copy_page (void *to, void *from);
+
+/*
+ * clear_user_page() and copy_user_page() can't be inline functions because
+ * flush_dcache_page() can't be defined until later...
+ */
+#define clear_user_page(addr, vaddr, page)      \
+do {                                            \
+        clear_page(addr);                       \
+        flush_dcache_page(page);                \
+} while (0)
+
+#define copy_user_page(to, from, vaddr, page)   \
+do {                                            \
+        copy_page((to), (from));                \
+        flush_dcache_page(page);                \
+} while (0)
+
+
+#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr)          \
+({                                                                      \
+        struct page *page = alloc_page_vma(                             \
+                GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr);  \
+        if (page)                                                       \
+                flush_dcache_page(page);                                \
+        page;                                                           \
+})
+
+#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
+
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#ifdef CONFIG_VIRTUAL_MEM_MAP
+extern int ia64_pfn_valid (unsigned long pfn);
+#else
+# define ia64_pfn_valid(pfn) 1
+#endif
+
+#ifdef CONFIG_VIRTUAL_MEM_MAP
+extern struct page *vmem_map;
+#ifdef CONFIG_DISCONTIGMEM
+# define page_to_pfn(page)      ((unsigned long) (page - vmem_map))
+# define pfn_to_page(pfn)       (vmem_map + (pfn))
+#else
+# include <asm-generic/memory_model.h>
+#endif
+#else
+# include <asm-generic/memory_model.h>
+#endif
+
+#ifdef CONFIG_FLATMEM
+# define pfn_valid(pfn)         (((pfn) < max_mapnr) && ia64_pfn_valid(pfn))
+#elif defined(CONFIG_DISCONTIGMEM)
+extern unsigned long min_low_pfn;
+extern unsigned long max_low_pfn;
+# define pfn_valid(pfn)         (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn) && ia64_pfn_valid(pfn))
+#endif
+
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+
+typedef union ia64_va {
+        struct {
+                unsigned long off : 61;         /* intra-region offset */
+                unsigned long reg :  3;         /* region number */
+        } f;
+        unsigned long l;
+        void *p;
+} ia64_va;
+
+/*
+ * Note: These macros depend on the fact that PAGE_OFFSET has all
+ * region bits set to 1 and all other bits set to zero.  They are
+ * expressed in this way to ensure they result in a single "dep"
+ * instruction.
+ */
+#define __pa(x)         ({ia64_va _v; _v.l = (long) (x); _v.f.reg = 0; _v.l;})
+#define __va(x)         ({ia64_va _v; _v.l = (long) (x); _v.f.reg = -1; _v.p;})
+
+#define REGION_NUMBER(x)        ({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
+#define REGION_OFFSET(x)        ({ia64_va _v; _v.l = (long) (x); _v.f.off;})
+
+#ifdef CONFIG_HUGETLB_PAGE
+# define htlbpage_to_page(x)    (((unsigned long) REGION_NUMBER(x) << 61)                       \
+                                 | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT)))
+# define HUGETLB_PAGE_ORDER     (HPAGE_SHIFT - PAGE_SHIFT)
+extern unsigned int hpage_shift;
+#endif
+
+static __inline__ int
+get_order (unsigned long size)
+{
+        long double d = size - 1;
+        long order;
+
+        order = ia64_getf_exp(d);
+        order = order - PAGE_SHIFT - 0xffff + 1;
+        if (order < 0)
+                order = 0;
+        return order;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef STRICT_MM_TYPECHECKS
+  /*
+   * These are used to make use of C type-checking..
+   */
+  typedef struct { unsigned long pte; } pte_t;
+  typedef struct { unsigned long pmd; } pmd_t;
+#ifdef CONFIG_PGTABLE_4
+  typedef struct { unsigned long pud; } pud_t;
+#endif
+  typedef struct { unsigned long pgd; } pgd_t;
+  typedef struct { unsigned long pgprot; } pgprot_t;
+  typedef struct page *pgtable_t;
+
+# define pte_val(x)     ((x).pte)
+# define pmd_val(x)     ((x).pmd)
+#ifdef CONFIG_PGTABLE_4
+# define pud_val(x)     ((x).pud)
+#endif
+# define pgd_val(x)     ((x).pgd)
+# define pgprot_val(x)  ((x).pgprot)
+
+# define __pte(x)       ((pte_t) { (x) } )
+# define __pgprot(x)    ((pgprot_t) { (x) } )
+
+#else /* !STRICT_MM_TYPECHECKS */
+  /*
+   * .. while these make it easier on the compiler
+   */
+# ifndef __ASSEMBLY__
+    typedef unsigned long pte_t;
+    typedef unsigned long pmd_t;
+    typedef unsigned long pgd_t;
+    typedef unsigned long pgprot_t;
+    typedef struct page *pgtable_t;
+# endif
+
+# define pte_val(x)     (x)
+# define pmd_val(x)     (x)
+# define pgd_val(x)     (x)
+# define pgprot_val(x)  (x)
+
+# define __pte(x)       (x)
+# define __pgd(x)       (x)
+# define __pgprot(x)    (x)
+#endif /* !STRICT_MM_TYPECHECKS */
+
+#define PAGE_OFFSET                     RGN_BASE(RGN_KERNEL)
+
+#define VM_DATA_DEFAULT_FLAGS           (VM_READ | VM_WRITE |                                   \
+                                         VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC |                \
+                                         (((current->personality & READ_IMPLIES_EXEC) != 0)     \
+                                          ? VM_EXEC : 0))
+
+#endif /* _ASM_IA64_PAGE_H */
diff --git a/arch/ia64/include/asm/pal.h b/arch/ia64/include/asm/pal.h
new file mode 100644
index 000000000000..67b02901ead4
--- /dev/null
+++ b/arch/ia64/include/asm/pal.h
@@ -0,0 +1,1827 @@
+#ifndef _ASM_IA64_PAL_H
+#define _ASM_IA64_PAL_H
+
+/*
+ * Processor Abstraction Layer definitions.
+ *
+ * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
+ * chapter 11 IA-64 Processor Abstraction Layer
+ *
+ * Copyright (C) 1998-2001 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *      Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 1999 VA Linux Systems
+ * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
+ * Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
+ *
+ * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
+ * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
+ * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
+ * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
+ * 00/05/25     eranian Support for stack calls, and static physical calls
+ * 00/06/18     eranian Support for stacked physical calls
+ * 06/10/26     rja     Support for Intel Itanium Architecture Software Developer's
+ *                      Manual Rev 2.2 (Jan 2006)
+ */
+
+/*
+ * Note that some of these calls use a static-register only calling
+ * convention which has nothing to do with the regular calling
+ * convention.
+ */
+#define PAL_CACHE_FLUSH         1       /* flush i/d cache */
+#define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
+#define PAL_CACHE_INIT          3       /* initialize i/d cache */
+#define PAL_CACHE_SUMMARY       4       /* get summary of cache hierarchy */
+#define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
+#define PAL_PTCE_INFO           6       /* purge TLB info */
+#define PAL_VM_INFO             7       /* return supported virtual memory features */
+#define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
+#define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
+#define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
+#define PAL_DEBUG_INFO          11      /* get number of debug registers */
+#define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
+#define PAL_FREQ_BASE           13      /* base frequency of the platform */
+#define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
+#define PAL_PERF_MON_INFO       15      /* return performance monitor info */
+#define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
+#define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
+#define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
+#define PAL_RSE_INFO            19      /* return rse information */
+#define PAL_VERSION             20      /* return version of PAL code */
+#define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
+#define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
+#define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
+#define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
+#define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
+#define PAL_MC_RESUME           26      /* Return to interrupted process */
+#define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
+#define PAL_HALT                28      /* enter the low power HALT state */
+#define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
+#define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
+#define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
+#define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
+#define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
+#define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
+
+#define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
+#define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
+#define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
+#define PAL_SHUTDOWN            40      /* enter processor shutdown state */
+#define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
+#define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
+#define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
+#define PAL_GET_HW_POLICY       48      /* Get current hardware resource sharing policy */
+#define PAL_SET_HW_POLICY       49      /* Set current hardware resource sharing policy */
+#define PAL_VP_INFO             50      /* Information about virtual processor features */
+#define PAL_MC_HW_TRACKING      51      /* Hardware tracking status */
+
+#define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
+#define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
+#define PAL_TEST_PROC           258     /* perform late processor self-test */
+#define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
+#define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
+#define PAL_VM_TR_READ          261     /* read contents of translation register */
+#define PAL_GET_PSTATE          262     /* get the current P-state */
+#define PAL_SET_PSTATE          263     /* set the P-state */
+#define PAL_BRAND_INFO          274     /* Processor branding information */
+
+#define PAL_GET_PSTATE_TYPE_LASTSET     0
+#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
+#define PAL_GET_PSTATE_TYPE_AVGNORESET  2
+#define PAL_GET_PSTATE_TYPE_INSTANT     3
+
+#define PAL_MC_ERROR_INJECT     276     /* Injects processor error or returns injection capabilities */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/fpu.h>
+
+/*
+ * Data types needed to pass information into PAL procedures and
+ * interpret information returned by them.
+ */
+
+/* Return status from the PAL procedure */
+typedef s64                             pal_status_t;
+
+#define PAL_STATUS_SUCCESS              0       /* No error */
+#define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
+#define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
+#define PAL_STATUS_ERROR                (-3)    /* Error */
+#define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
+                                                 * specified level and type of
+                                                 * cache without sideeffects
+                                                 * and "restrict" was 1
+                                                 */
+#define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
+
+/* Processor cache level in the hierarchy */
+typedef u64                             pal_cache_level_t;
+#define PAL_CACHE_LEVEL_L0              0       /* L0 */
+#define PAL_CACHE_LEVEL_L1              1       /* L1 */
+#define PAL_CACHE_LEVEL_L2              2       /* L2 */
+
+
+/* Processor cache type at a particular level in the hierarchy */
+
+typedef u64                             pal_cache_type_t;
+#define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
+#define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
+#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
+
+
+#define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
+#define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
+
+/* Processor cache line size in bytes  */
+typedef int                             pal_cache_line_size_t;
+
+/* Processor cache line state */
+typedef u64                             pal_cache_line_state_t;
+#define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
+#define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
+#define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
+#define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
+
+typedef struct pal_freq_ratio {
+        u32 den, num;           /* numerator & denominator */
+} itc_ratio, proc_ratio;
+
+typedef union  pal_cache_config_info_1_s {
+        struct {
+                u64             u               : 1,    /* 0 Unified cache ? */
+                                at              : 2,    /* 2-1 Cache mem attr*/
+                                reserved        : 5,    /* 7-3 Reserved */
+                                associativity   : 8,    /* 16-8 Associativity*/
+                                line_size       : 8,    /* 23-17 Line size */
+                                stride          : 8,    /* 31-24 Stride */
+                                store_latency   : 8,    /*39-32 Store latency*/
+                                load_latency    : 8,    /* 47-40 Load latency*/
+                                store_hints     : 8,    /* 55-48 Store hints*/
+                                load_hints      : 8;    /* 63-56 Load hints */
+        } pcci1_bits;
+        u64                     pcci1_data;
+} pal_cache_config_info_1_t;
+
+typedef union  pal_cache_config_info_2_s {
+        struct {
+                u32             cache_size;             /*cache size in bytes*/
+
+
+                u32             alias_boundary  : 8,    /* 39-32 aliased addr
+                                                         * separation for max
+                                                         * performance.
+                                                         */
+                                tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
+                                tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
+                                reserved        : 8;    /* 63-56 Reserved */
+        } pcci2_bits;
+        u64                     pcci2_data;
+} pal_cache_config_info_2_t;
+
+
+typedef struct pal_cache_config_info_s {
+        pal_status_t                    pcci_status;
+        pal_cache_config_info_1_t       pcci_info_1;
+        pal_cache_config_info_2_t       pcci_info_2;
+        u64                             pcci_reserved;
+} pal_cache_config_info_t;
+
+#define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
+#define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
+#define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
+#define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
+#define pcci_stride             pcci_info_1.pcci1_bits.stride
+#define pcci_line_size          pcci_info_1.pcci1_bits.line_size
+#define pcci_assoc              pcci_info_1.pcci1_bits.associativity
+#define pcci_cache_attr         pcci_info_1.pcci1_bits.at
+#define pcci_unified            pcci_info_1.pcci1_bits.u
+#define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
+#define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
+#define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
+#define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
+
+
+
+/* Possible values for cache attributes */
+
+#define PAL_CACHE_ATTR_WT               0       /* Write through cache */
+#define PAL_CACHE_ATTR_WB               1       /* Write back cache */
+#define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
+                                                 * back depending on TLB
+                                                 * memory attributes
+                                                 */
+
+
+/* Possible values for cache hints */
+
+#define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
+#define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
+#define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
+
+/* Processor cache protection  information */
+typedef union pal_cache_protection_element_u {
+        u32                     pcpi_data;
+        struct {
+                u32             data_bits       : 8, /* # data bits covered by
+                                                      * each unit of protection
+                                                      */
+
+                                tagprot_lsb     : 6, /* Least -do- */
+                                tagprot_msb     : 6, /* Most Sig. tag address
+                                                      * bit that this
+                                                      * protection covers.
+                                                      */
+                                prot_bits       : 6, /* # of protection bits */
+                                method          : 4, /* Protection method */
+                                t_d             : 2; /* Indicates which part
+                                                      * of the cache this
+                                                      * protection encoding
+                                                      * applies.
+                                                      */
+        } pcp_info;
+} pal_cache_protection_element_t;
+
+#define pcpi_cache_prot_part    pcp_info.t_d
+#define pcpi_prot_method        pcp_info.method
+#define pcpi_prot_bits          pcp_info.prot_bits
+#define pcpi_tagprot_msb        pcp_info.tagprot_msb
+#define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
+#define pcpi_data_bits          pcp_info.data_bits
+
+/* Processor cache part encodings */
+#define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
+#define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
+#define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
+                                                 * more significant )
+                                                 */
+#define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
+                                                 * more significant )
+                                                 */
+#define PAL_CACHE_PROT_PART_MAX         6
+
+
+typedef struct pal_cache_protection_info_s {
+        pal_status_t                    pcpi_status;
+        pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
+} pal_cache_protection_info_t;
+
+
+/* Processor cache protection method encodings */
+#define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
+#define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
+#define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
+#define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
+
+
+/* Processor cache line identification in the hierarchy */
+typedef union pal_cache_line_id_u {
+        u64                     pclid_data;
+        struct {
+                u64             cache_type      : 8,    /* 7-0 cache type */
+                                level           : 8,    /* 15-8 level of the
+                                                         * cache in the
+                                                         * hierarchy.
+                                                         */
+                                way             : 8,    /* 23-16 way in the set
+                                                         */
+                                part            : 8,    /* 31-24 part of the
+                                                         * cache
+                                                         */
+                                reserved        : 32;   /* 63-32 is reserved*/
+        } pclid_info_read;
+        struct {
+                u64             cache_type      : 8,    /* 7-0 cache type */
+                                level           : 8,    /* 15-8 level of the
+                                                         * cache in the
+                                                         * hierarchy.
+                                                         */
+                                way             : 8,    /* 23-16 way in the set
+                                                         */
+                                part            : 8,    /* 31-24 part of the
+                                                         * cache
+                                                         */
+                                mesi            : 8,    /* 39-32 cache line
+                                                         * state
+                                                         */
+                                start           : 8,    /* 47-40 lsb of data to
+                                                         * invert
+                                                         */
+                                length          : 8,    /* 55-48 #bits to
+                                                         * invert
+                                                         */
+                                trigger         : 8;    /* 63-56 Trigger error
+                                                         * by doing a load
+                                                         * after the write
+                                                         */
+
+        } pclid_info_write;
+} pal_cache_line_id_u_t;
+
+#define pclid_read_part         pclid_info_read.part
+#define pclid_read_way          pclid_info_read.way
+#define pclid_read_level        pclid_info_read.level
+#define pclid_read_cache_type   pclid_info_read.cache_type
+
+#define pclid_write_trigger     pclid_info_write.trigger
+#define pclid_write_length      pclid_info_write.length
+#define pclid_write_start       pclid_info_write.start
+#define pclid_write_mesi        pclid_info_write.mesi
+#define pclid_write_part        pclid_info_write.part
+#define pclid_write_way         pclid_info_write.way
+#define pclid_write_level       pclid_info_write.level
+#define pclid_write_cache_type  pclid_info_write.cache_type
+
+/* Processor cache line part encodings */
+#define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
+#define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
+#define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
+#define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
+#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
+                                                         * protection
+                                                         */
+typedef struct pal_cache_line_info_s {
+        pal_status_t            pcli_status;            /* Return status of the read cache line
+                                                         * info call.
+                                                         */
+        u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
+        u64                     pcli_data_len;          /* data length in bits */
+        pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
+
+} pal_cache_line_info_t;
+
+
+/* Machine Check related crap */
+
+/* Pending event status bits  */
+typedef u64                                     pal_mc_pending_events_t;
+
+#define PAL_MC_PENDING_MCA                      (1 << 0)
+#define PAL_MC_PENDING_INIT                     (1 << 1)
+
+/* Error information type */
+typedef u64                                     pal_mc_info_index_t;
+
+#define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
+#define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
+#define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
+#define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
+#define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
+#define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
+#define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
+#define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
+                                                         * dependent
+                                                         */
+
+#define PAL_TLB_CHECK_OP_PURGE                  8
+
+typedef struct pal_process_state_info_s {
+        u64             reserved1       : 2,
+                        rz              : 1,    /* PAL_CHECK processor
+                                                 * rendezvous
+                                                 * successful.
+                                                 */
+
+                        ra              : 1,    /* PAL_CHECK attempted
+                                                 * a rendezvous.
+                                                 */
+                        me              : 1,    /* Distinct multiple
+                                                 * errors occurred
+                                                 */
+
+                        mn              : 1,    /* Min. state save
+                                                 * area has been
+                                                 * registered with PAL
+                                                 */
+
+                        sy              : 1,    /* Storage integrity
+                                                 * synched
+                                                 */
+
+
+                        co              : 1,    /* Continuable */
+                        ci              : 1,    /* MC isolated */
+                        us              : 1,    /* Uncontained storage
+                                                 * damage.
+                                                 */
+
+
+                        hd              : 1,    /* Non-essential hw
+                                                 * lost (no loss of
+                                                 * functionality)
+                                                 * causing the
+                                                 * processor to run in
+                                                 * degraded mode.
+                                                 */
+
+                        tl              : 1,    /* 1 => MC occurred
+                                                 * after an instr was
+                                                 * executed but before
+                                                 * the trap that
+                                                 * resulted from instr
+                                                 * execution was
+                                                 * generated.
+                                                 * (Trap Lost )
+                                                 */
+                        mi              : 1,    /* More information available
+                                                 * call PAL_MC_ERROR_INFO
+                                                 */
+                        pi              : 1,    /* Precise instruction pointer */
+                        pm              : 1,    /* Precise min-state save area */
+
+                        dy              : 1,    /* Processor dynamic
+                                                 * state valid
+                                                 */
+
+
+                        in              : 1,    /* 0 = MC, 1 = INIT */
+                        rs              : 1,    /* RSE valid */
+                        cm              : 1,    /* MC corrected */
+                        ex              : 1,    /* MC is expected */
+                        cr              : 1,    /* Control regs valid*/
+                        pc              : 1,    /* Perf cntrs valid */
+                        dr              : 1,    /* Debug regs valid */
+                        tr              : 1,    /* Translation regs
+                                                 * valid
+                                                 */
+                        rr              : 1,    /* Region regs valid */
+                        ar              : 1,    /* App regs valid */
+                        br              : 1,    /* Branch regs valid */
+                        pr              : 1,    /* Predicate registers
+                                                 * valid
+                                                 */
+
+                        fp              : 1,    /* fp registers valid*/
+                        b1              : 1,    /* Preserved bank one
+                                                 * general registers
+                                                 * are valid
+                                                 */
+                        b0              : 1,    /* Preserved bank zero
+                                                 * general registers
+                                                 * are valid
+                                                 */
+                        gr              : 1,    /* General registers
+                                                 * are valid
+                                                 * (excl. banked regs)
+                                                 */
+                        dsize           : 16,   /* size of dynamic
+                                                 * state returned
+                                                 * by the processor
+                                                 */
+
+                        se              : 1,    /* Shared error.  MCA in a
+                                                   shared structure */
+                        reserved2       : 10,
+                        cc              : 1,    /* Cache check */
+                        tc              : 1,    /* TLB check */
+                        bc              : 1,    /* Bus check */
+                        rc              : 1,    /* Register file check */
+                        uc              : 1;    /* Uarch check */
+
+} pal_processor_state_info_t;
+
+typedef struct pal_cache_check_info_s {
+        u64             op              : 4,    /* Type of cache
+                                                 * operation that
+                                                 * caused the machine
+                                                 * check.
+                                                 */
+                        level           : 2,    /* Cache level */
+                        reserved1       : 2,
+                        dl              : 1,    /* Failure in data part
+                                                 * of cache line
+                                                 */
+                        tl              : 1,    /* Failure in tag part
+                                                 * of cache line
+                                                 */
+                        dc              : 1,    /* Failure in dcache */
+                        ic              : 1,    /* Failure in icache */
+                        mesi            : 3,    /* Cache line state */
+                        mv              : 1,    /* mesi valid */
+                        way             : 5,    /* Way in which the
+                                                 * error occurred
+                                                 */
+                        wiv             : 1,    /* Way field valid */
+                        reserved2       : 1,
+                        dp              : 1,    /* Data poisoned on MBE */
+                        reserved3       : 6,
+                        hlth            : 2,    /* Health indicator */
+
+                        index           : 20,   /* Cache line index */
+                        reserved4       : 2,
+
+                        is              : 1,    /* instruction set (1 == ia32) */
+                        iv              : 1,    /* instruction set field valid */
+                        pl              : 2,    /* privilege level */
+                        pv              : 1,    /* privilege level field valid */
+                        mcc             : 1,    /* Machine check corrected */
+                        tv              : 1,    /* Target address
+                                                 * structure is valid
+                                                 */
+                        rq              : 1,    /* Requester identifier
+                                                 * structure is valid
+                                                 */
+                        rp              : 1,    /* Responder identifier
+                                                 * structure is valid
+                                                 */
+                        pi              : 1;    /* Precise instruction pointer
+                                                 * structure is valid
+                                                 */
+} pal_cache_check_info_t;
+
+typedef struct pal_tlb_check_info_s {
+
+        u64             tr_slot         : 8,    /* Slot# of TR where
+                                                 * error occurred
+                                                 */
+                        trv             : 1,    /* tr_slot field is valid */
+                        reserved1       : 1,
+                        level           : 2,    /* TLB level where failure occurred */
+                        reserved2       : 4,
+                        dtr             : 1,    /* Fail in data TR */
+                        itr             : 1,    /* Fail in inst TR */
+                        dtc             : 1,    /* Fail in data TC */
+                        itc             : 1,    /* Fail in inst. TC */
+                        op              : 4,    /* Cache operation */
+                        reserved3       : 6,
+                        hlth            : 2,    /* Health indicator */
+                        reserved4       : 22,
+
+                        is              : 1,    /* instruction set (1 == ia32) */
+                        iv              : 1,    /* instruction set field valid */
+                        pl              : 2,    /* privilege level */
+                        pv              : 1,    /* privilege level field valid */
+                        mcc             : 1,    /* Machine check corrected */
+                        tv              : 1,    /* Target address
+                                                 * structure is valid
+                                                 */
+                        rq              : 1,    /* Requester identifier
+                                                 * structure is valid
+                                                 */
+                        rp              : 1,    /* Responder identifier
+                                                 * structure is valid
+                                                 */
+                        pi              : 1;    /* Precise instruction pointer
+                                                 * structure is valid
+                                                 */
+} pal_tlb_check_info_t;
+
+typedef struct pal_bus_check_info_s {
+        u64             size            : 5,    /* Xaction size */
+                        ib              : 1,    /* Internal bus error */
+                        eb              : 1,    /* External bus error */
+                        cc              : 1,    /* Error occurred
+                                                 * during cache-cache
+                                                 * transfer.
+                                                 */
+                        type            : 8,    /* Bus xaction type*/
+                        sev             : 5,    /* Bus error severity*/
+                        hier            : 2,    /* Bus hierarchy level */
+                        dp              : 1,    /* Data poisoned on MBE */
+                        bsi             : 8,    /* Bus error status
+                                                 * info
+                                                 */
+                        reserved2       : 22,
+
+                        is              : 1,    /* instruction set (1 == ia32) */
+                        iv              : 1,    /* instruction set field valid */
+                        pl              : 2,    /* privilege level */
+                        pv              : 1,    /* privilege level field valid */
+                        mcc             : 1,    /* Machine check corrected */
+                        tv              : 1,    /* Target address
+                                                 * structure is valid
+                                                 */
+                        rq              : 1,    /* Requester identifier
+                                                 * structure is valid
+                                                 */
+                        rp              : 1,    /* Responder identifier
+                                                 * structure is valid
+                                                 */
+                        pi              : 1;    /* Precise instruction pointer
+                                                 * structure is valid
+                                                 */
+} pal_bus_check_info_t;
+
+typedef struct pal_reg_file_check_info_s {
+        u64             id              : 4,    /* Register file identifier */
+                        op              : 4,    /* Type of register
+                                                 * operation that
+                                                 * caused the machine
+                                                 * check.
+                                                 */
+                        reg_num         : 7,    /* Register number */
+                        rnv             : 1,    /* reg_num valid */
+                        reserved2       : 38,
+
+                        is              : 1,    /* instruction set (1 == ia32) */
+                        iv              : 1,    /* instruction set field valid */
+                        pl              : 2,    /* privilege level */
+                        pv              : 1,    /* privilege level field valid */
+                        mcc             : 1,    /* Machine check corrected */
+                        reserved3       : 3,
+                        pi              : 1;    /* Precise instruction pointer
+                                                 * structure is valid
+                                                 */
+} pal_reg_file_check_info_t;
+
+typedef struct pal_uarch_check_info_s {
+        u64             sid             : 5,    /* Structure identification */
+                        level           : 3,    /* Level of failure */
+                        array_id        : 4,    /* Array identification */
+                        op              : 4,    /* Type of
+                                                 * operation that
+                                                 * caused the machine
+                                                 * check.
+                                                 */
+                        way             : 6,    /* Way of structure */
+                        wv              : 1,    /* way valid */
+                        xv              : 1,    /* index valid */
+                        reserved1       : 6,
+                        hlth            : 2,    /* Health indicator */
+                        index           : 8,    /* Index or set of the uarch
+                                                 * structure that failed.
+                                                 */
+                        reserved2       : 24,
+
+                        is              : 1,    /* instruction set (1 == ia32) */
+                        iv              : 1,    /* instruction set field valid */
+                        pl              : 2,    /* privilege level */
+                        pv              : 1,    /* privilege level field valid */
+                        mcc             : 1,    /* Machine check corrected */
+                        tv              : 1,    /* Target address
+                                                 * structure is valid
+                                                 */
+                        rq              : 1,    /* Requester identifier
+                                                 * structure is valid
+                                                 */
+                        rp              : 1,    /* Responder identifier
+                                                 * structure is valid
+                                                 */
+                        pi              : 1;    /* Precise instruction pointer
+                                                 * structure is valid
+                                                 */
+} pal_uarch_check_info_t;
+
+typedef union pal_mc_error_info_u {
+        u64                             pmei_data;
+        pal_processor_state_info_t      pme_processor;
+        pal_cache_check_info_t          pme_cache;
+        pal_tlb_check_info_t            pme_tlb;
+        pal_bus_check_info_t            pme_bus;
+        pal_reg_file_check_info_t       pme_reg_file;
+        pal_uarch_check_info_t          pme_uarch;
+} pal_mc_error_info_t;
+
+#define pmci_proc_unknown_check                 pme_processor.uc
+#define pmci_proc_bus_check                     pme_processor.bc
+#define pmci_proc_tlb_check                     pme_processor.tc
+#define pmci_proc_cache_check                   pme_processor.cc
+#define pmci_proc_dynamic_state_size            pme_processor.dsize
+#define pmci_proc_gpr_valid                     pme_processor.gr
+#define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
+#define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
+#define pmci_proc_fp_valid                      pme_processor.fp
+#define pmci_proc_predicate_regs_valid          pme_processor.pr
+#define pmci_proc_branch_regs_valid             pme_processor.br
+#define pmci_proc_app_regs_valid                pme_processor.ar
+#define pmci_proc_region_regs_valid             pme_processor.rr
+#define pmci_proc_translation_regs_valid        pme_processor.tr
+#define pmci_proc_debug_regs_valid              pme_processor.dr
+#define pmci_proc_perf_counters_valid           pme_processor.pc
+#define pmci_proc_control_regs_valid            pme_processor.cr
+#define pmci_proc_machine_check_expected        pme_processor.ex
+#define pmci_proc_machine_check_corrected       pme_processor.cm
+#define pmci_proc_rse_valid                     pme_processor.rs
+#define pmci_proc_machine_check_or_init         pme_processor.in
+#define pmci_proc_dynamic_state_valid           pme_processor.dy
+#define pmci_proc_operation                     pme_processor.op
+#define pmci_proc_trap_lost                     pme_processor.tl
+#define pmci_proc_hardware_damage               pme_processor.hd
+#define pmci_proc_uncontained_storage_damage    pme_processor.us
+#define pmci_proc_machine_check_isolated        pme_processor.ci
+#define pmci_proc_continuable                   pme_processor.co
+#define pmci_proc_storage_intergrity_synced     pme_processor.sy
+#define pmci_proc_min_state_save_area_regd      pme_processor.mn
+#define pmci_proc_distinct_multiple_errors      pme_processor.me
+#define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
+#define pmci_proc_pal_rendezvous_complete       pme_processor.rz
+
+
+#define pmci_cache_level                        pme_cache.level
+#define pmci_cache_line_state                   pme_cache.mesi
+#define pmci_cache_line_state_valid             pme_cache.mv
+#define pmci_cache_line_index                   pme_cache.index
+#define pmci_cache_instr_cache_fail             pme_cache.ic
+#define pmci_cache_data_cache_fail              pme_cache.dc
+#define pmci_cache_line_tag_fail                pme_cache.tl
+#define pmci_cache_line_data_fail               pme_cache.dl
+#define pmci_cache_operation                    pme_cache.op
+#define pmci_cache_way_valid                    pme_cache.wv
+#define pmci_cache_target_address_valid         pme_cache.tv
+#define pmci_cache_way                          pme_cache.way
+#define pmci_cache_mc                           pme_cache.mc
+
+#define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
+#define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
+#define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
+#define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
+#define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
+#define pmci_tlb_mc                             pme_tlb.mc
+
+#define pmci_bus_status_info                    pme_bus.bsi
+#define pmci_bus_req_address_valid              pme_bus.rq
+#define pmci_bus_resp_address_valid             pme_bus.rp
+#define pmci_bus_target_address_valid           pme_bus.tv
+#define pmci_bus_error_severity                 pme_bus.sev
+#define pmci_bus_transaction_type               pme_bus.type
+#define pmci_bus_cache_cache_transfer           pme_bus.cc
+#define pmci_bus_transaction_size               pme_bus.size
+#define pmci_bus_internal_error                 pme_bus.ib
+#define pmci_bus_external_error                 pme_bus.eb
+#define pmci_bus_mc                             pme_bus.mc
+
+/*
+ * NOTE: this min_state_save area struct only includes the 1KB
+ * architectural state save area.  The other 3 KB is scratch space
+ * for PAL.
+ */
+
+typedef struct pal_min_state_area_s {
+        u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
+        u64     pmsa_gr[15];            /* GR1  - GR15             */
+        u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
+        u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
+        u64     pmsa_pr;                /* predicate registers     */
+        u64     pmsa_br0;               /* branch register 0       */
+        u64     pmsa_rsc;               /* ar.rsc                  */
+        u64     pmsa_iip;               /* cr.iip                  */
+        u64     pmsa_ipsr;              /* cr.ipsr                 */
+        u64     pmsa_ifs;               /* cr.ifs                  */
+        u64     pmsa_xip;               /* previous iip            */
+        u64     pmsa_xpsr;              /* previous psr            */
+        u64     pmsa_xfs;               /* previous ifs            */
+        u64     pmsa_br1;               /* branch register 1       */
+        u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
+} pal_min_state_area_t;
+
+
+struct ia64_pal_retval {
+        /*
+         * A zero status value indicates call completed without error.
+         * A negative status value indicates reason of call failure.
+         * A positive status value indicates success but an
+         * informational value should be printed (e.g., "reboot for
+         * change to take effect").
+         */
+        s64 status;
+        u64 v0;
+        u64 v1;
+        u64 v2;
+};
+
+/*
+ * Note: Currently unused PAL arguments are generally labeled
+ * "reserved" so the value specified in the PAL documentation
+ * (generally 0) MUST be passed.  Reserved parameters are not optional
+ * parameters.
+ */
+extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
+extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
+extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
+extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
+extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
+extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
+
+#define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
+        struct ia64_fpreg fr[6];                        \
+        ia64_save_scratch_fpregs(fr);                   \
+        iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
+        ia64_load_scratch_fpregs(fr);                   \
+} while (0)
+
+#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
+        struct ia64_fpreg fr[6];                        \
+        ia64_save_scratch_fpregs(fr);                   \
+        iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
+        ia64_load_scratch_fpregs(fr);                   \
+} while (0)
+
+#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
+        struct ia64_fpreg fr[6];                                \
+        ia64_save_scratch_fpregs(fr);                           \
+        iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
+        ia64_load_scratch_fpregs(fr);                           \
+} while (0)
+
+#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
+        struct ia64_fpreg fr[6];                                \
+        ia64_save_scratch_fpregs(fr);                           \
+        iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
+        ia64_load_scratch_fpregs(fr);                           \
+} while (0)
+
+typedef int (*ia64_pal_handler) (u64, ...);
+extern ia64_pal_handler ia64_pal;
+extern void ia64_pal_handler_init (void *);
+
+extern ia64_pal_handler ia64_pal;
+
+extern pal_cache_config_info_t          l0d_cache_config_info;
+extern pal_cache_config_info_t          l0i_cache_config_info;
+extern pal_cache_config_info_t          l1_cache_config_info;
+extern pal_cache_config_info_t          l2_cache_config_info;
+
+extern pal_cache_protection_info_t      l0d_cache_protection_info;
+extern pal_cache_protection_info_t      l0i_cache_protection_info;
+extern pal_cache_protection_info_t      l1_cache_protection_info;
+extern pal_cache_protection_info_t      l2_cache_protection_info;
+
+extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
+                                                                  pal_cache_type_t);
+
+extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
+                                                                      pal_cache_type_t);
+
+
+extern void                             pal_error(int);
+
+
+/* Useful wrappers for the current list of pal procedures */
+
+typedef union pal_bus_features_u {
+        u64     pal_bus_features_val;
+        struct {
+                u64     pbf_reserved1                           :       29;
+                u64     pbf_req_bus_parking                     :       1;
+                u64     pbf_bus_lock_mask                       :       1;
+                u64     pbf_enable_half_xfer_rate               :       1;
+                u64     pbf_reserved2                           :       20;
+                u64     pbf_enable_shared_line_replace          :       1;
+                u64     pbf_enable_exclusive_line_replace       :       1;
+                u64     pbf_disable_xaction_queueing            :       1;
+                u64     pbf_disable_resp_err_check              :       1;
+                u64     pbf_disable_berr_check                  :       1;
+                u64     pbf_disable_bus_req_internal_err_signal :       1;
+                u64     pbf_disable_bus_req_berr_signal         :       1;
+                u64     pbf_disable_bus_init_event_check        :       1;
+                u64     pbf_disable_bus_init_event_signal       :       1;
+                u64     pbf_disable_bus_addr_err_check          :       1;
+                u64     pbf_disable_bus_addr_err_signal         :       1;
+                u64     pbf_disable_bus_data_err_check          :       1;
+        } pal_bus_features_s;
+} pal_bus_features_u_t;
+
+extern void pal_bus_features_print (u64);
+
+/* Provide information about configurable processor bus features */
+static inline s64
+ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
+                           pal_bus_features_u_t *features_status,
+                           pal_bus_features_u_t *features_control)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
+        if (features_avail)
+                features_avail->pal_bus_features_val = iprv.v0;
+        if (features_status)
+                features_status->pal_bus_features_val = iprv.v1;
+        if (features_control)
+                features_control->pal_bus_features_val = iprv.v2;
+        return iprv.status;
+}
+
+/* Enables/disables specific processor bus features */
+static inline s64
+ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
+        return iprv.status;
+}
+
+/* Get detailed cache information */
+static inline s64
+ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
+{
+        struct ia64_pal_retval iprv;
+
+        PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
+
+        if (iprv.status == 0) {
+                conf->pcci_status                 = iprv.status;
+                conf->pcci_info_1.pcci1_data      = iprv.v0;
+                conf->pcci_info_2.pcci2_data      = iprv.v1;
+                conf->pcci_reserved               = iprv.v2;
+        }
+        return iprv.status;
+
+}
+
+/* Get detailed cche protection information */
+static inline s64
+ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
+{
+        struct ia64_pal_retval iprv;
+
+        PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
+
+        if (iprv.status == 0) {
+                prot->pcpi_status           = iprv.status;
+                prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
+                prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
+                prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
+                prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
+                prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
+                prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
+        }
+        return iprv.status;
+}
+
+/*
+ * Flush the processor instruction or data caches.  *PROGRESS must be
+ * initialized to zero before calling this for the first time..
+ */
+static inline s64
+ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
+        if (vector)
+                *vector = iprv.v0;
+        *progress = iprv.v1;
+        return iprv.status;
+}
+
+
+/* Initialize the processor controlled caches */
+static inline s64
+ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
+        return iprv.status;
+}
+
+/* Initialize the tags and data of a data or unified cache line of
+ * processor controlled cache to known values without the availability
+ * of backing memory.
+ */
+static inline s64
+ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
+        return iprv.status;
+}
+
+
+/* Read the data and tag of a processor controlled cache line for diags */
+static inline s64
+ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
+                                physical_addr, 0);
+        return iprv.status;
+}
+
+/* Return summary information about the hierarchy of caches controlled by the processor */
+static inline s64
+ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
+        if (cache_levels)
+                *cache_levels = iprv.v0;
+        if (unique_caches)
+                *unique_caches = iprv.v1;
+        return iprv.status;
+}
+
+/* Write the data and tag of a processor-controlled cache line for diags */
+static inline s64
+ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
+                                physical_addr, data);
+        return iprv.status;
+}
+
+
+/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
+static inline s64
+ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
+                    u64 *buffer_size, u64 *buffer_align)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
+        if (buffer_size)
+                *buffer_size = iprv.v0;
+        if (buffer_align)
+                *buffer_align = iprv.v1;
+        return iprv.status;
+}
+
+/* Copy relocatable PAL procedures from ROM to memory */
+static inline s64
+ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
+        if (pal_proc_offset)
+                *pal_proc_offset = iprv.v0;
+        return iprv.status;
+}
+
+/* Return the number of instruction and data debug register pairs */
+static inline s64
+ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
+        if (inst_regs)
+                *inst_regs = iprv.v0;
+        if (data_regs)
+                *data_regs = iprv.v1;
+
+        return iprv.status;
+}
+
+#ifdef TBD
+/* Switch from IA64-system environment to IA-32 system environment */
+static inline s64
+ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
+        return iprv.status;
+}
+#endif
+
+/* Get unique geographical address of this processor on its bus */
+static inline s64
+ia64_pal_fixed_addr (u64 *global_unique_addr)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
+        if (global_unique_addr)
+                *global_unique_addr = iprv.v0;
+        return iprv.status;
+}
+
+/* Get base frequency of the platform if generated by the processor */
+static inline s64
+ia64_pal_freq_base (u64 *platform_base_freq)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
+        if (platform_base_freq)
+                *platform_base_freq = iprv.v0;
+        return iprv.status;
+}
+
+/*
+ * Get the ratios for processor frequency, bus frequency and interval timer to
+ * to base frequency of the platform
+ */
+static inline s64
+ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
+                      struct pal_freq_ratio *itc_ratio)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
+        if (proc_ratio)
+                *(u64 *)proc_ratio = iprv.v0;
+        if (bus_ratio)
+                *(u64 *)bus_ratio = iprv.v1;
+        if (itc_ratio)
+                *(u64 *)itc_ratio = iprv.v2;
+        return iprv.status;
+}
+
+/*
+ * Get the current hardware resource sharing policy of the processor
+ */
+static inline s64
+ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
+                        u64 *la)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
+        if (cur_policy)
+                *cur_policy = iprv.v0;
+        if (num_impacted)
+                *num_impacted = iprv.v1;
+        if (la)
+                *la = iprv.v2;
+        return iprv.status;
+}
+
+/* Make the processor enter HALT or one of the implementation dependent low
+ * power states where prefetching and execution are suspended and cache and
+ * TLB coherency is not maintained.
+ */
+static inline s64
+ia64_pal_halt (u64 halt_state)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
+        return iprv.status;
+}
+
+typedef union pal_power_mgmt_info_u {
+        u64                     ppmi_data;
+        struct {
+               u64              exit_latency            : 16,
+                                entry_latency           : 16,
+                                power_consumption       : 28,
+                                im                      : 1,
+                                co                      : 1,
+                                reserved                : 2;
+        } pal_power_mgmt_info_s;
+} pal_power_mgmt_info_u_t;
+
+/* Return information about processor's optional power management capabilities. */
+static inline s64
+ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
+        return iprv.status;
+}
+
+/* Get the current P-state information */
+static inline s64
+ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
+        *pstate_index = iprv.v0;
+        return iprv.status;
+}
+
+/* Set the P-state */
+static inline s64
+ia64_pal_set_pstate (u64 pstate_index)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
+        return iprv.status;
+}
+
+/* Processor branding information*/
+static inline s64
+ia64_pal_get_brand_info (char *brand_info)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
+        return iprv.status;
+}
+
+/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
+ * suspended, but cache and TLB coherency is maintained.
+ */
+static inline s64
+ia64_pal_halt_light (void)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
+        return iprv.status;
+}
+
+/* Clear all the processor error logging   registers and reset the indicator that allows
+ * the error logging registers to be written. This procedure also checks the pending
+ * machine check bit and pending INIT bit and reports their states.
+ */
+static inline s64
+ia64_pal_mc_clear_log (u64 *pending_vector)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
+        if (pending_vector)
+                *pending_vector = iprv.v0;
+        return iprv.status;
+}
+
+/* Ensure that all outstanding transactions in a processor are completed or that any
+ * MCA due to thes outstanding transaction is taken.
+ */
+static inline s64
+ia64_pal_mc_drain (void)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
+        return iprv.status;
+}
+
+/* Return the machine check dynamic processor state */
+static inline s64
+ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
+        if (size)
+                *size = iprv.v0;
+        return iprv.status;
+}
+
+/* Return processor machine check information */
+static inline s64
+ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
+        if (size)
+                *size = iprv.v0;
+        if (error_info)
+                *error_info = iprv.v1;
+        return iprv.status;
+}
+
+/* Injects the requested processor error or returns info on
+ * supported injection capabilities for current processor implementation
+ */
+static inline s64
+ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
+                        u64 err_data_buffer, u64 *capabilities, u64 *resources)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
+                          err_struct_info, err_data_buffer);
+        if (capabilities)
+                *capabilities= iprv.v0;
+        if (resources)
+                *resources= iprv.v1;
+        return iprv.status;
+}
+
+static inline s64
+ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
+                        u64 err_data_buffer, u64 *capabilities, u64 *resources)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
+                          err_struct_info, err_data_buffer);
+        if (capabilities)
+                *capabilities= iprv.v0;
+        if (resources)
+                *resources= iprv.v1;
+        return iprv.status;
+}
+
+/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
+ * attempt to correct any expected machine checks.
+ */
+static inline s64
+ia64_pal_mc_expected (u64 expected, u64 *previous)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
+        if (previous)
+                *previous = iprv.v0;
+        return iprv.status;
+}
+
+typedef union pal_hw_tracking_u {
+        u64                     pht_data;
+        struct {
+                u64             itc     :4,     /* Instruction cache tracking */
+                                dct     :4,     /* Date cache tracking */
+                                itt     :4,     /* Instruction TLB tracking */
+                                ddt     :4,     /* Data TLB tracking */
+                                reserved:48;
+        } pal_hw_tracking_s;
+} pal_hw_tracking_u_t;
+
+/*
+ * Hardware tracking status.
+ */
+static inline s64
+ia64_pal_mc_hw_tracking (u64 *status)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
+        if (status)
+                *status = iprv.v0;
+        return iprv.status;
+}
+
+/* Register a platform dependent location with PAL to which it can save
+ * minimal processor state in the event of a machine check or initialization
+ * event.
+ */
+static inline s64
+ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
+        if (req_size)
+                *req_size = iprv.v0;
+        return iprv.status;
+}
+
+/* Restore minimal architectural processor state, set CMC interrupt if necessary
+ * and resume execution
+ */
+static inline s64
+ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
+        return iprv.status;
+}
+
+/* Return the memory attributes implemented by the processor */
+static inline s64
+ia64_pal_mem_attrib (u64 *mem_attrib)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
+        if (mem_attrib)
+                *mem_attrib = iprv.v0 & 0xff;
+        return iprv.status;
+}
+
+/* Return the amount of memory needed for second phase of processor
+ * self-test and the required alignment of memory.
+ */
+static inline s64
+ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
+        if (bytes_needed)
+                *bytes_needed = iprv.v0;
+        if (alignment)
+                *alignment = iprv.v1;
+        return iprv.status;
+}
+
+typedef union pal_perf_mon_info_u {
+        u64                       ppmi_data;
+        struct {
+               u64              generic         : 8,
+                                width           : 8,
+                                cycles          : 8,
+                                retired         : 8,
+                                reserved        : 32;
+        } pal_perf_mon_info_s;
+} pal_perf_mon_info_u_t;
+
+/* Return the performance monitor information about what can be counted
+ * and how to configure the monitors to count the desired events.
+ */
+static inline s64
+ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
+        if (pm_info)
+                pm_info->ppmi_data = iprv.v0;
+        return iprv.status;
+}
+
+/* Specifies the physical address of the processor interrupt block
+ * and I/O port space.
+ */
+static inline s64
+ia64_pal_platform_addr (u64 type, u64 physical_addr)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
+        return iprv.status;
+}
+
+/* Set the SAL PMI entrypoint in memory */
+static inline s64
+ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
+        return iprv.status;
+}
+
+struct pal_features_s;
+/* Provide information about configurable processor features */
+static inline s64
+ia64_pal_proc_get_features (u64 *features_avail,
+                            u64 *features_status,
+                            u64 *features_control,
+                            u64 features_set)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0);
+        if (iprv.status == 0) {
+                *features_avail   = iprv.v0;
+                *features_status  = iprv.v1;
+                *features_control = iprv.v2;
+        }
+        return iprv.status;
+}
+
+/* Enable/disable processor dependent features */
+static inline s64
+ia64_pal_proc_set_features (u64 feature_select)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
+        return iprv.status;
+}
+
+/*
+ * Put everything in a struct so we avoid the global offset table whenever
+ * possible.
+ */
+typedef struct ia64_ptce_info_s {
+        u64             base;
+        u32             count[2];
+        u32             stride[2];
+} ia64_ptce_info_t;
+
+/* Return the information required for the architected loop used to purge
+ * (initialize) the entire TC
+ */
+static inline s64
+ia64_get_ptce (ia64_ptce_info_t *ptce)
+{
+        struct ia64_pal_retval iprv;
+
+        if (!ptce)
+                return -1;
+
+        PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
+        if (iprv.status == 0) {
+                ptce->base = iprv.v0;
+                ptce->count[0] = iprv.v1 >> 32;
+                ptce->count[1] = iprv.v1 & 0xffffffff;
+                ptce->stride[0] = iprv.v2 >> 32;
+                ptce->stride[1] = iprv.v2 & 0xffffffff;
+        }
+        return iprv.status;
+}
+
+/* Return info about implemented application and control registers. */
+static inline s64
+ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
+        if (reg_info_1)
+                *reg_info_1 = iprv.v0;
+        if (reg_info_2)
+                *reg_info_2 = iprv.v1;
+        return iprv.status;
+}
+
+typedef union pal_hints_u {
+        u64                     ph_data;
+        struct {
+               u64              si              : 1,
+                                li              : 1,
+                                reserved        : 62;
+        } pal_hints_s;
+} pal_hints_u_t;
+
+/* Return information about the register stack and RSE for this processor
+ * implementation.
+ */
+static inline s64
+ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
+        if (num_phys_stacked)
+                *num_phys_stacked = iprv.v0;
+        if (hints)
+                hints->ph_data = iprv.v1;
+        return iprv.status;
+}
+
+/*
+ * Set the current hardware resource sharing policy of the processor
+ */
+static inline s64
+ia64_pal_set_hw_policy (u64 policy)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
+        return iprv.status;
+}
+
+/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
+ * suspended, but cause cache and TLB coherency to be maintained.
+ * This is usually called in IA-32 mode.
+ */
+static inline s64
+ia64_pal_shutdown (void)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
+        return iprv.status;
+}
+
+/* Perform the second phase of processor self-test. */
+static inline s64
+ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
+        if (self_test_state)
+                *self_test_state = iprv.v0;
+        return iprv.status;
+}
+
+typedef union  pal_version_u {
+        u64     pal_version_val;
+        struct {
+                u64     pv_pal_b_rev            :       8;
+                u64     pv_pal_b_model          :       8;
+                u64     pv_reserved1            :       8;
+                u64     pv_pal_vendor           :       8;
+                u64     pv_pal_a_rev            :       8;
+                u64     pv_pal_a_model          :       8;
+                u64     pv_reserved2            :       16;
+        } pal_version_s;
+} pal_version_u_t;
+
+
+/*
+ * Return PAL version information.  While the documentation states that
+ * PAL_VERSION can be called in either physical or virtual mode, some
+ * implementations only allow physical calls.  We don't call it very often,
+ * so the overhead isn't worth eliminating.
+ */
+static inline s64
+ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
+        if (pal_min_version)
+                pal_min_version->pal_version_val = iprv.v0;
+
+        if (pal_cur_version)
+                pal_cur_version->pal_version_val = iprv.v1;
+
+        return iprv.status;
+}
+
+typedef union pal_tc_info_u {
+        u64                     pti_val;
+        struct {
+               u64              num_sets        :       8,
+                                associativity   :       8,
+                                num_entries     :       16,
+                                pf              :       1,
+                                unified         :       1,
+                                reduce_tr       :       1,
+                                reserved        :       29;
+        } pal_tc_info_s;
+} pal_tc_info_u_t;
+
+#define tc_reduce_tr            pal_tc_info_s.reduce_tr
+#define tc_unified              pal_tc_info_s.unified
+#define tc_pf                   pal_tc_info_s.pf
+#define tc_num_entries          pal_tc_info_s.num_entries
+#define tc_associativity        pal_tc_info_s.associativity
+#define tc_num_sets             pal_tc_info_s.num_sets
+
+
+/* Return information about the virtual memory characteristics of the processor
+ * implementation.
+ */
+static inline s64
+ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
+        if (tc_info)
+                tc_info->pti_val = iprv.v0;
+        if (tc_pages)
+                *tc_pages = iprv.v1;
+        return iprv.status;
+}
+
+/* Get page size information about the virtual memory characteristics of the processor
+ * implementation.
+ */
+static inline s64
+ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
+        if (tr_pages)
+                *tr_pages = iprv.v0;
+        if (vw_pages)
+                *vw_pages = iprv.v1;
+        return iprv.status;
+}
+
+typedef union pal_vm_info_1_u {
+        u64                     pvi1_val;
+        struct {
+                u64             vw              : 1,
+                                phys_add_size   : 7,
+                                key_size        : 8,
+                                max_pkr         : 8,
+                                hash_tag_id     : 8,
+                                max_dtr_entry   : 8,
+                                max_itr_entry   : 8,
+                                max_unique_tcs  : 8,
+                                num_tc_levels   : 8;
+        } pal_vm_info_1_s;
+} pal_vm_info_1_u_t;
+
+#define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
+
+typedef union pal_vm_info_2_u {
+        u64                     pvi2_val;
+        struct {
+                u64             impl_va_msb     : 8,
+                                rid_size        : 8,
+                                max_purges      : 16,
+                                reserved        : 32;
+        } pal_vm_info_2_s;
+} pal_vm_info_2_u_t;
+
+/* Get summary information about the virtual memory characteristics of the processor
+ * implementation.
+ */
+static inline s64
+ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
+        if (vm_info_1)
+                vm_info_1->pvi1_val = iprv.v0;
+        if (vm_info_2)
+                vm_info_2->pvi2_val = iprv.v1;
+        return iprv.status;
+}
+
+typedef union pal_vp_info_u {
+        u64                     pvi_val;
+        struct {
+                u64             index:          48,     /* virtual feature set info */
+                                vmm_id:         16;     /* feature set id */
+        } pal_vp_info_s;
+} pal_vp_info_u_t;
+
+/*
+ * Returns infomation about virtual processor features
+ */
+static inline s64
+ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
+        if (vp_info)
+                *vp_info = iprv.v0;
+        if (vmm_id)
+                *vmm_id = iprv.v1;
+        return iprv.status;
+}
+
+typedef union pal_itr_valid_u {
+        u64                     piv_val;
+        struct {
+               u64              access_rights_valid     : 1,
+                                priv_level_valid        : 1,
+                                dirty_bit_valid         : 1,
+                                mem_attr_valid          : 1,
+                                reserved                : 60;
+        } pal_tr_valid_s;
+} pal_tr_valid_u_t;
+
+/* Read a translation register */
+static inline s64
+ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
+        if (tr_valid)
+                tr_valid->piv_val = iprv.v0;
+        return iprv.status;
+}
+
+/*
+ * PAL_PREFETCH_VISIBILITY transaction types
+ */
+#define PAL_VISIBILITY_VIRTUAL          0
+#define PAL_VISIBILITY_PHYSICAL         1
+
+/*
+ * PAL_PREFETCH_VISIBILITY return codes
+ */
+#define PAL_VISIBILITY_OK               1
+#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
+#define PAL_VISIBILITY_INVAL_ARG        -2
+#define PAL_VISIBILITY_ERROR            -3
+
+static inline s64
+ia64_pal_prefetch_visibility (s64 trans_type)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
+        return iprv.status;
+}
+
+/* data structure for getting information on logical to physical mappings */
+typedef union pal_log_overview_u {
+        struct {
+                u64     num_log         :16,    /* Total number of logical
+                                                 * processors on this die
+                                                 */
+                        tpc             :8,     /* Threads per core */
+                        reserved3       :8,     /* Reserved */
+                        cpp             :8,     /* Cores per processor */
+                        reserved2       :8,     /* Reserved */
+                        ppid            :8,     /* Physical processor ID */
+                        reserved1       :8;     /* Reserved */
+        } overview_bits;
+        u64 overview_data;
+} pal_log_overview_t;
+
+typedef union pal_proc_n_log_info1_u{
+        struct {
+                u64     tid             :16,    /* Thread id */
+                        reserved2       :16,    /* Reserved */
+                        cid             :16,    /* Core id */
+                        reserved1       :16;    /* Reserved */
+        } ppli1_bits;
+        u64     ppli1_data;
+} pal_proc_n_log_info1_t;
+
+typedef union pal_proc_n_log_info2_u {
+        struct {
+                u64     la              :16,    /* Logical address */
+                        reserved        :48;    /* Reserved */
+        } ppli2_bits;
+        u64     ppli2_data;
+} pal_proc_n_log_info2_t;
+
+typedef struct pal_logical_to_physical_s
+{
+        pal_log_overview_t overview;
+        pal_proc_n_log_info1_t ppli1;
+        pal_proc_n_log_info2_t ppli2;
+} pal_logical_to_physical_t;
+
+#define overview_num_log        overview.overview_bits.num_log
+#define overview_tpc            overview.overview_bits.tpc
+#define overview_cpp            overview.overview_bits.cpp
+#define overview_ppid           overview.overview_bits.ppid
+#define log1_tid                ppli1.ppli1_bits.tid
+#define log1_cid                ppli1.ppli1_bits.cid
+#define log2_la                 ppli2.ppli2_bits.la
+
+/* Get information on logical to physical processor mappings. */
+static inline s64
+ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
+{
+        struct ia64_pal_retval iprv;
+
+        PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
+
+        if (iprv.status == PAL_STATUS_SUCCESS)
+        {
+                mapping->overview.overview_data = iprv.v0;
+                mapping->ppli1.ppli1_data = iprv.v1;
+                mapping->ppli2.ppli2_data = iprv.v2;
+        }
+
+        return iprv.status;
+}
+
+typedef struct pal_cache_shared_info_s
+{
+        u64 num_shared;
+        pal_proc_n_log_info1_t ppli1;
+        pal_proc_n_log_info2_t ppli2;
+} pal_cache_shared_info_t;
+
+/* Get information on logical to physical processor mappings. */
+static inline s64
+ia64_pal_cache_shared_info(u64 level,
+                u64 type,
+                u64 proc_number,
+                pal_cache_shared_info_t *info)
+{
+        struct ia64_pal_retval iprv;
+
+        PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
+
+        if (iprv.status == PAL_STATUS_SUCCESS) {
+                info->num_shared = iprv.v0;
+                info->ppli1.ppli1_data = iprv.v1;
+                info->ppli2.ppli2_data = iprv.v2;
+        }
+
+        return iprv.status;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_IA64_PAL_H */
diff --git a/arch/ia64/include/asm/param.h b/arch/ia64/include/asm/param.h
new file mode 100644
index 000000000000..0964c32c1358
--- /dev/null
+++ b/arch/ia64/include/asm/param.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_IA64_PARAM_H
+#define _ASM_IA64_PARAM_H
+
+/*
+ * Fundamental kernel parameters.
+ *
+ * Based on <asm-i386/param.h>.
+ *
+ * Modified 1998, 1999, 2002-2003
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#define EXEC_PAGESIZE   65536
+
+#ifndef NOGROUP
+# define NOGROUP        (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#ifdef __KERNEL__
+# define HZ             CONFIG_HZ
+# define USER_HZ        HZ
+# define CLOCKS_PER_SEC HZ      /* frequency at which times() counts */
+#else
+   /*
+    * Technically, this is wrong, but some old apps still refer to it.  The proper way to
+    * get the HZ value is via sysconf(_SC_CLK_TCK).
+    */
+# define HZ 1024
+#endif
+
+#endif /* _ASM_IA64_PARAM_H */
diff --git a/arch/ia64/include/asm/paravirt.h b/arch/ia64/include/asm/paravirt.h
new file mode 100644
index 000000000000..660cab044834
--- /dev/null
+++ b/arch/ia64/include/asm/paravirt.h
@@ -0,0 +1,253 @@
+/******************************************************************************
+ * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+
+#ifndef __ASM_PARAVIRT_H
+#define __ASM_PARAVIRT_H
+
+#ifdef CONFIG_PARAVIRT_GUEST
+
+#define PARAVIRT_HYPERVISOR_TYPE_DEFAULT        0
+#define PARAVIRT_HYPERVISOR_TYPE_XEN            1
+
+#ifndef __ASSEMBLY__
+
+#include <asm/hw_irq.h>
+#include <asm/meminit.h>
+
+/******************************************************************************
+ * general info
+ */
+struct pv_info {
+        unsigned int kernel_rpl;
+        int paravirt_enabled;
+        const char *name;
+};
+
+extern struct pv_info pv_info;
+
+static inline int paravirt_enabled(void)
+{
+        return pv_info.paravirt_enabled;
+}
+
+static inline unsigned int get_kernel_rpl(void)
+{
+        return pv_info.kernel_rpl;
+}
+
+/******************************************************************************
+ * initialization hooks.
+ */
+struct rsvd_region;
+
+struct pv_init_ops {
+        void (*banner)(void);
+
+        int (*reserve_memory)(struct rsvd_region *region);
+
+        void (*arch_setup_early)(void);
+        void (*arch_setup_console)(char **cmdline_p);
+        int (*arch_setup_nomca)(void);
+
+        void (*post_smp_prepare_boot_cpu)(void);
+};
+
+extern struct pv_init_ops pv_init_ops;
+
+static inline void paravirt_banner(void)
+{
+        if (pv_init_ops.banner)
+                pv_init_ops.banner();
+}
+
+static inline int paravirt_reserve_memory(struct rsvd_region *region)
+{
+        if (pv_init_ops.reserve_memory)
+                return pv_init_ops.reserve_memory(region);
+        return 0;
+}
+
+static inline void paravirt_arch_setup_early(void)
+{
+        if (pv_init_ops.arch_setup_early)
+                pv_init_ops.arch_setup_early();
+}
+
+static inline void paravirt_arch_setup_console(char **cmdline_p)
+{
+        if (pv_init_ops.arch_setup_console)
+                pv_init_ops.arch_setup_console(cmdline_p);
+}
+
+static inline int paravirt_arch_setup_nomca(void)
+{
+        if (pv_init_ops.arch_setup_nomca)
+                return pv_init_ops.arch_setup_nomca();
+        return 0;
+}
+
+static inline void paravirt_post_smp_prepare_boot_cpu(void)
+{
+        if (pv_init_ops.post_smp_prepare_boot_cpu)
+                pv_init_ops.post_smp_prepare_boot_cpu();
+}
+
+/******************************************************************************
+ * replacement of iosapic operations.
+ */
+
+struct pv_iosapic_ops {
+        void (*pcat_compat_init)(void);
+
+        struct irq_chip *(*get_irq_chip)(unsigned long trigger);
+
+        unsigned int (*__read)(char __iomem *iosapic, unsigned int reg);
+        void (*__write)(char __iomem *iosapic, unsigned int reg, u32 val);
+};
+
+extern struct pv_iosapic_ops pv_iosapic_ops;
+
+static inline void
+iosapic_pcat_compat_init(void)
+{
+        if (pv_iosapic_ops.pcat_compat_init)
+                pv_iosapic_ops.pcat_compat_init();
+}
+
+static inline struct irq_chip*
+iosapic_get_irq_chip(unsigned long trigger)
+{
+        return pv_iosapic_ops.get_irq_chip(trigger);
+}
+
+static inline unsigned int
+__iosapic_read(char __iomem *iosapic, unsigned int reg)
+{
+        return pv_iosapic_ops.__read(iosapic, reg);
+}
+
+static inline void
+__iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
+{
+        return pv_iosapic_ops.__write(iosapic, reg, val);
+}
+
+/******************************************************************************
+ * replacement of irq operations.
+ */
+
+struct pv_irq_ops {
+        void (*register_ipi)(void);
+
+        int (*assign_irq_vector)(int irq);
+        void (*free_irq_vector)(int vector);
+
+        void (*register_percpu_irq)(ia64_vector vec,
+                                    struct irqaction *action);
+
+        void (*resend_irq)(unsigned int vector);
+};
+
+extern struct pv_irq_ops pv_irq_ops;
+
+static inline void
+ia64_register_ipi(void)
+{
+        pv_irq_ops.register_ipi();
+}
+
+static inline int
+assign_irq_vector(int irq)
+{
+        return pv_irq_ops.assign_irq_vector(irq);
+}
+
+static inline void
+free_irq_vector(int vector)
+{
+        return pv_irq_ops.free_irq_vector(vector);
+}
+
+static inline void
+register_percpu_irq(ia64_vector vec, struct irqaction *action)
+{
+        pv_irq_ops.register_percpu_irq(vec, action);
+}
+
+static inline void
+ia64_resend_irq(unsigned int vector)
+{
+        pv_irq_ops.resend_irq(vector);
+}
+
+/******************************************************************************
+ * replacement of time operations.
+ */
+
+extern struct itc_jitter_data_t itc_jitter_data;
+extern volatile int time_keeper_id;
+
+struct pv_time_ops {
+        void (*init_missing_ticks_accounting)(int cpu);
+        int (*do_steal_accounting)(unsigned long *new_itm);
+
+        void (*clocksource_resume)(void);
+};
+
+extern struct pv_time_ops pv_time_ops;
+
+static inline void
+paravirt_init_missing_ticks_accounting(int cpu)
+{
+        if (pv_time_ops.init_missing_ticks_accounting)
+                pv_time_ops.init_missing_ticks_accounting(cpu);
+}
+
+static inline int
+paravirt_do_steal_accounting(unsigned long *new_itm)
+{
+        return pv_time_ops.do_steal_accounting(new_itm);
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#else
+/* fallback for native case */
+
+#ifndef __ASSEMBLY__
+
+#define paravirt_banner()                               do { } while (0)
+#define paravirt_reserve_memory(region)                 0
+
+#define paravirt_arch_setup_early()                     do { } while (0)
+#define paravirt_arch_setup_console(cmdline_p)          do { } while (0)
+#define paravirt_arch_setup_nomca()                     0
+#define paravirt_post_smp_prepare_boot_cpu()            do { } while (0)
+
+#define paravirt_init_missing_ticks_accounting(cpu)     do { } while (0)
+#define paravirt_do_steal_accounting(new_itm)           0
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* CONFIG_PARAVIRT_GUEST */
+
+#endif /* __ASM_PARAVIRT_H */
diff --git a/arch/ia64/include/asm/paravirt_privop.h b/arch/ia64/include/asm/paravirt_privop.h
new file mode 100644
index 000000000000..d577aac11835
--- /dev/null
+++ b/arch/ia64/include/asm/paravirt_privop.h
@@ -0,0 +1,112 @@
+/******************************************************************************
+ * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _ASM_IA64_PARAVIRT_PRIVOP_H
+#define _ASM_IA64_PARAVIRT_PRIVOP_H
+
+#ifdef CONFIG_PARAVIRT
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/kregs.h> /* for IA64_PSR_I */
+
+/******************************************************************************
+ * replacement of intrinsics operations.
+ */
+
+struct pv_cpu_ops {
+        void (*fc)(unsigned long addr);
+        unsigned long (*thash)(unsigned long addr);
+        unsigned long (*get_cpuid)(int index);
+        unsigned long (*get_pmd)(int index);
+        unsigned long (*getreg)(int reg);
+        void (*setreg)(int reg, unsigned long val);
+        void (*ptcga)(unsigned long addr, unsigned long size);
+        unsigned long (*get_rr)(unsigned long index);
+        void (*set_rr)(unsigned long index, unsigned long val);
+        void (*set_rr0_to_rr4)(unsigned long val0, unsigned long val1,
+                               unsigned long val2, unsigned long val3,
+                               unsigned long val4);
+        void (*ssm_i)(void);
+        void (*rsm_i)(void);
+        unsigned long (*get_psr_i)(void);
+        void (*intrin_local_irq_restore)(unsigned long flags);
+};
+
+extern struct pv_cpu_ops pv_cpu_ops;
+
+extern void ia64_native_setreg_func(int regnum, unsigned long val);
+extern unsigned long ia64_native_getreg_func(int regnum);
+
+/************************************************/
+/* Instructions paravirtualized for performance */
+/************************************************/
+
+/* mask for ia64_native_ssm/rsm() must be constant.("i" constraing).
+ * static inline function doesn't satisfy it. */
+#define paravirt_ssm(mask)                      \
+        do {                                    \
+                if ((mask) == IA64_PSR_I)       \
+                        pv_cpu_ops.ssm_i();     \
+                else                            \
+                        ia64_native_ssm(mask);  \
+        } while (0)
+
+#define paravirt_rsm(mask)                      \
+        do {                                    \
+                if ((mask) == IA64_PSR_I)       \
+                        pv_cpu_ops.rsm_i();     \
+                else                            \
+                        ia64_native_rsm(mask);  \
+        } while (0)
+
+/******************************************************************************
+ * replacement of hand written assembly codes.
+ */
+struct pv_cpu_asm_switch {
+        unsigned long switch_to;
+        unsigned long leave_syscall;
+        unsigned long work_processed_syscall;
+        unsigned long leave_kernel;
+};
+void paravirt_cpu_asm_init(const struct pv_cpu_asm_switch *cpu_asm_switch);
+
+#endif /* __ASSEMBLY__ */
+
+#define IA64_PARAVIRT_ASM_FUNC(name)    paravirt_ ## name
+
+#else
+
+/* fallback for native case */
+#define IA64_PARAVIRT_ASM_FUNC(name)    ia64_native_ ## name
+
+#endif /* CONFIG_PARAVIRT */
+
+/* these routines utilize privilege-sensitive or performance-sensitive
+ * privileged instructions so the code must be replaced with
+ * paravirtualized versions */
+#define ia64_switch_to                  IA64_PARAVIRT_ASM_FUNC(switch_to)
+#define ia64_leave_syscall              IA64_PARAVIRT_ASM_FUNC(leave_syscall)
+#define ia64_work_processed_syscall     \
+        IA64_PARAVIRT_ASM_FUNC(work_processed_syscall)
+#define ia64_leave_kernel               IA64_PARAVIRT_ASM_FUNC(leave_kernel)
+
+#endif /* _ASM_IA64_PARAVIRT_PRIVOP_H */
diff --git a/arch/ia64/include/asm/parport.h b/arch/ia64/include/asm/parport.h
new file mode 100644
index 000000000000..67e16adfcd25
--- /dev/null
+++ b/arch/ia64/include/asm/parport.h
@@ -0,0 +1,20 @@
+/*
+ * parport.h: platform-specific PC-style parport initialisation
+ *
+ * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+
+#ifndef _ASM_IA64_PARPORT_H
+#define _ASM_IA64_PARPORT_H 1
+
+static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
+
+static int __devinit
+parport_pc_find_nonpci_ports (int autoirq, int autodma)
+{
+        return parport_pc_find_isa_ports(autoirq, autodma);
+}
+
+#endif /* _ASM_IA64_PARPORT_H */
diff --git a/arch/ia64/include/asm/patch.h b/arch/ia64/include/asm/patch.h
new file mode 100644
index 000000000000..295fe6ab4584
--- /dev/null
+++ b/arch/ia64/include/asm/patch.h
@@ -0,0 +1,27 @@
+#ifndef _ASM_IA64_PATCH_H
+#define _ASM_IA64_PATCH_H
+
+/*
+ * Copyright (C) 2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * There are a number of reasons for patching instructions.  Rather than duplicating code
+ * all over the place, we put the common stuff here.  Reasons for patching: in-kernel
+ * module-loader, virtual-to-physical patch-list, McKinley Errata 9 workaround, and gate
+ * shared library.  Undoubtedly, some of these reasons will disappear and others will
+ * be added over time.
+ */
+#include <linux/elf.h>
+#include <linux/types.h>
+
+extern void ia64_patch (u64 insn_addr, u64 mask, u64 val);      /* patch any insn slot */
+extern void ia64_patch_imm64 (u64 insn_addr, u64 val);          /* patch "movl" w/abs. value*/
+extern void ia64_patch_imm60 (u64 insn_addr, u64 val);          /* patch "brl" w/ip-rel value */
+
+extern void ia64_patch_mckinley_e9 (unsigned long start, unsigned long end);
+extern void ia64_patch_vtop (unsigned long start, unsigned long end);
+extern void ia64_patch_phys_stack_reg(unsigned long val);
+extern void ia64_patch_rse (unsigned long start, unsigned long end);
+extern void ia64_patch_gate (void);
+
+#endif /* _ASM_IA64_PATCH_H */
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
new file mode 100644
index 000000000000..0149097b736d
--- /dev/null
+++ b/arch/ia64/include/asm/pci.h
@@ -0,0 +1,167 @@
+#ifndef _ASM_IA64_PCI_H
+#define _ASM_IA64_PCI_H
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include <asm/io.h>
+#include <asm/scatterlist.h>
+#include <asm/hw_irq.h>
+
+/*
+ * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
+ * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
+ * loader.
+ */
+#define pcibios_assign_all_busses()     0
+#define pcibios_scan_all_fns(a, b)      0
+
+#define PCIBIOS_MIN_IO          0x1000
+#define PCIBIOS_MIN_MEM         0x10000000
+
+void pcibios_config_init(void);
+
+struct pci_dev;
+
+/*
+ * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
+ * correspondence between device bus addresses and CPU physical addresses.
+ * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
+ * bounce buffer handling code in the block and network device layers.
+ * Platforms with separate bus address spaces _must_ turn this off and provide
+ * a device DMA mapping implementation that takes care of the necessary
+ * address translation.
+ *
+ * For now, the ia64 platforms which may have separate/multiple bus address
+ * spaces all have I/O MMUs which support the merging of physically
+ * discontiguous buffers, so we can use that as the sole factor to determine
+ * the setting of PCI_DMA_BUS_IS_PHYS.
+ */
+extern unsigned long ia64_max_iommu_merge_mask;
+#define PCI_DMA_BUS_IS_PHYS     (ia64_max_iommu_merge_mask == ~0UL)
+
+static inline void
+pcibios_set_master (struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+
+static inline void
+pcibios_penalize_isa_irq (int irq, int active)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+#include <asm-generic/pci-dma-compat.h>
+
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_MULTIPLE;
+        *strategy_parameter = cacheline_size;
+}
+#endif
+
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
+                                enum pci_mmap_state mmap_state, int write_combine);
+#define HAVE_PCI_LEGACY
+extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
+                                      struct vm_area_struct *vma);
+extern ssize_t pci_read_legacy_io(struct kobject *kobj,
+                                  struct bin_attribute *bin_attr,
+                                  char *buf, loff_t off, size_t count);
+extern ssize_t pci_write_legacy_io(struct kobject *kobj,
+                                   struct bin_attribute *bin_attr,
+                                   char *buf, loff_t off, size_t count);
+extern int pci_mmap_legacy_mem(struct kobject *kobj,
+                               struct bin_attribute *attr,
+                               struct vm_area_struct *vma);
+
+#define pci_get_legacy_mem platform_pci_get_legacy_mem
+#define pci_legacy_read platform_pci_legacy_read
+#define pci_legacy_write platform_pci_legacy_write
+
+struct pci_window {
+        struct resource resource;
+        u64 offset;
+};
+
+struct pci_controller {
+        void *acpi_handle;
+        void *iommu;
+        int segment;
+        int node;               /* nearest node with memory or -1 for global allocation */
+
+        unsigned int windows;
+        struct pci_window *window;
+
+        void *platform_data;
+};
+
+#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
+#define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
+
+extern struct pci_ops pci_root_ops;
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        return (pci_domain_nr(bus) != 0);
+}
+
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+                struct pci_bus_region *region, struct resource *res);
+
+extern void pcibios_bus_to_resource(struct pci_dev *dev,
+                struct resource *res, struct pci_bus_region *region);
+
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
+
+#define pcibios_scan_all_fns(a, b)      0
+
+#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
+}
+
+#endif /* _ASM_IA64_PCI_H */
diff --git a/arch/ia64/include/asm/percpu.h b/arch/ia64/include/asm/percpu.h
new file mode 100644
index 000000000000..77f30b664b4e
--- /dev/null
+++ b/arch/ia64/include/asm/percpu.h
@@ -0,0 +1,51 @@
+#ifndef _ASM_IA64_PERCPU_H
+#define _ASM_IA64_PERCPU_H
+
+/*
+ * Copyright (C) 2002-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#define PERCPU_ENOUGH_ROOM PERCPU_PAGE_SIZE
+
+#ifdef __ASSEMBLY__
+# define THIS_CPU(var)  (per_cpu__##var)  /* use this to mark accesses to per-CPU variables... */
+#else /* !__ASSEMBLY__ */
+
+
+#include <linux/threads.h>
+
+#ifdef CONFIG_SMP
+
+#ifdef HAVE_MODEL_SMALL_ATTRIBUTE
+# define PER_CPU_ATTRIBUTES     __attribute__((__model__ (__small__)))
+#endif
+
+#define __my_cpu_offset __ia64_per_cpu_var(local_per_cpu_offset)
+
+extern void *per_cpu_init(void);
+
+#else /* ! SMP */
+
+#define PER_CPU_ATTRIBUTES      __attribute__((__section__(".data.percpu")))
+
+#define per_cpu_init()                          (__phys_per_cpu_start)
+
+#endif  /* SMP */
+
+/*
+ * Be extremely careful when taking the address of this variable!  Due to virtual
+ * remapping, it is different from the canonical address returned by __get_cpu_var(var)!
+ * On the positive side, using __ia64_per_cpu_var() instead of __get_cpu_var() is slightly
+ * more efficient.
+ */
+#define __ia64_per_cpu_var(var) per_cpu__##var
+
+#include <asm-generic/percpu.h>
+
+/* Equal to __per_cpu_offset[smp_processor_id()], but faster to access: */
+DECLARE_PER_CPU(unsigned long, local_per_cpu_offset);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_IA64_PERCPU_H */
diff --git a/arch/ia64/include/asm/perfmon.h b/arch/ia64/include/asm/perfmon.h
new file mode 100644
index 000000000000..7f3333dd00e4
--- /dev/null
+++ b/arch/ia64/include/asm/perfmon.h
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2001-2003 Hewlett-Packard Co
+ *               Stephane Eranian <eranian@hpl.hp.com>
+ */
+
+#ifndef _ASM_IA64_PERFMON_H
+#define _ASM_IA64_PERFMON_H
+
+/*
+ * perfmon comamnds supported on all CPU models
+ */
+#define PFM_WRITE_PMCS          0x01
+#define PFM_WRITE_PMDS          0x02
+#define PFM_READ_PMDS           0x03
+#define PFM_STOP                0x04
+#define PFM_START               0x05
+#define PFM_ENABLE              0x06 /* obsolete */
+#define PFM_DISABLE             0x07 /* obsolete */
+#define PFM_CREATE_CONTEXT      0x08
+#define PFM_DESTROY_CONTEXT     0x09 /* obsolete use close() */
+#define PFM_RESTART             0x0a
+#define PFM_PROTECT_CONTEXT     0x0b /* obsolete */
+#define PFM_GET_FEATURES        0x0c
+#define PFM_DEBUG               0x0d
+#define PFM_UNPROTECT_CONTEXT   0x0e /* obsolete */
+#define PFM_GET_PMC_RESET_VAL   0x0f
+#define PFM_LOAD_CONTEXT        0x10
+#define PFM_UNLOAD_CONTEXT      0x11
+
+/*
+ * PMU model specific commands (may not be supported on all PMU models)
+ */
+#define PFM_WRITE_IBRS          0x20
+#define PFM_WRITE_DBRS          0x21
+
+/*
+ * context flags
+ */
+#define PFM_FL_NOTIFY_BLOCK      0x01   /* block task on user level notifications */
+#define PFM_FL_SYSTEM_WIDE       0x02   /* create a system wide context */
+#define PFM_FL_OVFL_NO_MSG       0x80   /* do not post overflow/end messages for notification */
+
+/*
+ * event set flags
+ */
+#define PFM_SETFL_EXCL_IDLE      0x01   /* exclude idle task (syswide only) XXX: DO NOT USE YET */
+
+/*
+ * PMC flags
+ */
+#define PFM_REGFL_OVFL_NOTIFY   0x1     /* send notification on overflow */
+#define PFM_REGFL_RANDOM        0x2     /* randomize sampling interval   */
+
+/*
+ * PMD/PMC/IBR/DBR return flags (ignored on input)
+ *
+ * Those flags are used on output and must be checked in case EAGAIN is returned
+ * by any of the calls using a pfarg_reg_t or pfarg_dbreg_t structure.
+ */
+#define PFM_REG_RETFL_NOTAVAIL  (1UL<<31) /* set if register is implemented but not available */
+#define PFM_REG_RETFL_EINVAL    (1UL<<30) /* set if register entry is invalid */
+#define PFM_REG_RETFL_MASK      (PFM_REG_RETFL_NOTAVAIL|PFM_REG_RETFL_EINVAL)
+
+#define PFM_REG_HAS_ERROR(flag) (((flag) & PFM_REG_RETFL_MASK) != 0)
+
+typedef unsigned char pfm_uuid_t[16];   /* custom sampling buffer identifier type */
+
+/*
+ * Request structure used to define a context
+ */
+typedef struct {
+        pfm_uuid_t     ctx_smpl_buf_id;  /* which buffer format to use (if needed) */
+        unsigned long  ctx_flags;        /* noblock/block */
+        unsigned short ctx_nextra_sets;  /* number of extra event sets (you always get 1) */
+        unsigned short ctx_reserved1;    /* for future use */
+        int            ctx_fd;           /* return arg: unique identification for context */
+        void           *ctx_smpl_vaddr;  /* return arg: virtual address of sampling buffer, is used */
+        unsigned long  ctx_reserved2[11];/* for future use */
+} pfarg_context_t;
+
+/*
+ * Request structure used to write/read a PMC or PMD
+ */
+typedef struct {
+        unsigned int    reg_num;           /* which register */
+        unsigned short  reg_set;           /* event set for this register */
+        unsigned short  reg_reserved1;     /* for future use */
+
+        unsigned long   reg_value;         /* initial pmc/pmd value */
+        unsigned long   reg_flags;         /* input: pmc/pmd flags, return: reg error */
+
+        unsigned long   reg_long_reset;    /* reset after buffer overflow notification */
+        unsigned long   reg_short_reset;   /* reset after counter overflow */
+
+        unsigned long   reg_reset_pmds[4]; /* which other counters to reset on overflow */
+        unsigned long   reg_random_seed;   /* seed value when randomization is used */
+        unsigned long   reg_random_mask;   /* bitmask used to limit random value */
+        unsigned long   reg_last_reset_val;/* return: PMD last reset value */
+
+        unsigned long   reg_smpl_pmds[4];  /* which pmds are accessed when PMC overflows */
+        unsigned long   reg_smpl_eventid;  /* opaque sampling event identifier */
+
+        unsigned long   reg_reserved2[3];   /* for future use */
+} pfarg_reg_t;
+
+typedef struct {
+        unsigned int    dbreg_num;              /* which debug register */
+        unsigned short  dbreg_set;              /* event set for this register */
+        unsigned short  dbreg_reserved1;        /* for future use */
+        unsigned long   dbreg_value;            /* value for debug register */
+        unsigned long   dbreg_flags;            /* return: dbreg error */
+        unsigned long   dbreg_reserved2[1];     /* for future use */
+} pfarg_dbreg_t;
+
+typedef struct {
+        unsigned int    ft_version;     /* perfmon: major [16-31], minor [0-15] */
+        unsigned int    ft_reserved;    /* reserved for future use */
+        unsigned long   reserved[4];    /* for future use */
+} pfarg_features_t;
+
+typedef struct {
+        pid_t           load_pid;          /* process to load the context into */
+        unsigned short  load_set;          /* first event set to load */
+        unsigned short  load_reserved1;    /* for future use */
+        unsigned long   load_reserved2[3]; /* for future use */
+} pfarg_load_t;
+
+typedef struct {
+        int             msg_type;               /* generic message header */
+        int             msg_ctx_fd;             /* generic message header */
+        unsigned long   msg_ovfl_pmds[4];       /* which PMDs overflowed */
+        unsigned short  msg_active_set;         /* active set at the time of overflow */
+        unsigned short  msg_reserved1;          /* for future use */
+        unsigned int    msg_reserved2;          /* for future use */
+        unsigned long   msg_tstamp;             /* for perf tuning/debug */
+} pfm_ovfl_msg_t;
+
+typedef struct {
+        int             msg_type;               /* generic message header */
+        int             msg_ctx_fd;             /* generic message header */
+        unsigned long   msg_tstamp;             /* for perf tuning */
+} pfm_end_msg_t;
+
+typedef struct {
+        int             msg_type;               /* type of the message */
+        int             msg_ctx_fd;             /* unique identifier for the context */
+        unsigned long   msg_tstamp;             /* for perf tuning */
+} pfm_gen_msg_t;
+
+#define PFM_MSG_OVFL    1       /* an overflow happened */
+#define PFM_MSG_END     2       /* task to which context was attached ended */
+
+typedef union {
+        pfm_ovfl_msg_t  pfm_ovfl_msg;
+        pfm_end_msg_t   pfm_end_msg;
+        pfm_gen_msg_t   pfm_gen_msg;
+} pfm_msg_t;
+
+/*
+ * Define the version numbers for both perfmon as a whole and the sampling buffer format.
+ */
+#define PFM_VERSION_MAJ          2U
+#define PFM_VERSION_MIN          0U
+#define PFM_VERSION              (((PFM_VERSION_MAJ&0xffff)<<16)|(PFM_VERSION_MIN & 0xffff))
+#define PFM_VERSION_MAJOR(x)     (((x)>>16) & 0xffff)
+#define PFM_VERSION_MINOR(x)     ((x) & 0xffff)
+
+
+/*
+ * miscellaneous architected definitions
+ */
+#define PMU_FIRST_COUNTER       4       /* first counting monitor (PMC/PMD) */
+#define PMU_MAX_PMCS            256     /* maximum architected number of PMC registers */
+#define PMU_MAX_PMDS            256     /* maximum architected number of PMD registers */
+
+#ifdef __KERNEL__
+
+extern long perfmonctl(int fd, int cmd, void *arg, int narg);
+
+typedef struct {
+        void (*handler)(int irq, void *arg, struct pt_regs *regs);
+} pfm_intr_handler_desc_t;
+
+extern void pfm_save_regs (struct task_struct *);
+extern void pfm_load_regs (struct task_struct *);
+
+extern void pfm_exit_thread(struct task_struct *);
+extern int  pfm_use_debug_registers(struct task_struct *);
+extern int  pfm_release_debug_registers(struct task_struct *);
+extern void pfm_syst_wide_update_task(struct task_struct *, unsigned long info, int is_ctxswin);
+extern void pfm_inherit(struct task_struct *task, struct pt_regs *regs);
+extern void pfm_init_percpu(void);
+extern void pfm_handle_work(void);
+extern int  pfm_install_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
+extern int  pfm_remove_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
+
+
+
+/*
+ * Reset PMD register flags
+ */
+#define PFM_PMD_SHORT_RESET     0
+#define PFM_PMD_LONG_RESET      1
+
+typedef union {
+        unsigned int val;
+        struct {
+                unsigned int notify_user:1;     /* notify user program of overflow */
+                unsigned int reset_ovfl_pmds:1; /* reset overflowed PMDs */
+                unsigned int block_task:1;      /* block monitored task on kernel exit */
+                unsigned int mask_monitoring:1; /* mask monitors via PMCx.plm */
+                unsigned int reserved:28;       /* for future use */
+        } bits;
+} pfm_ovfl_ctrl_t;
+
+typedef struct {
+        unsigned char   ovfl_pmd;                       /* index of overflowed PMD  */
+        unsigned char   ovfl_notify;                    /* =1 if monitor requested overflow notification */
+        unsigned short  active_set;                     /* event set active at the time of the overflow */
+        pfm_ovfl_ctrl_t ovfl_ctrl;                      /* return: perfmon controls to set by handler */
+
+        unsigned long   pmd_last_reset;                 /* last reset value of of the PMD */
+        unsigned long   smpl_pmds[4];                   /* bitmask of other PMD of interest on overflow */
+        unsigned long   smpl_pmds_values[PMU_MAX_PMDS]; /* values for the other PMDs of interest */
+        unsigned long   pmd_value;                      /* current 64-bit value of the PMD */
+        unsigned long   pmd_eventid;                    /* eventid associated with PMD */
+} pfm_ovfl_arg_t;
+
+
+typedef struct {
+        char            *fmt_name;
+        pfm_uuid_t      fmt_uuid;
+        size_t          fmt_arg_size;
+        unsigned long   fmt_flags;
+
+        int             (*fmt_validate)(struct task_struct *task, unsigned int flags, int cpu, void *arg);
+        int             (*fmt_getsize)(struct task_struct *task, unsigned int flags, int cpu, void *arg, unsigned long *size);
+        int             (*fmt_init)(struct task_struct *task, void *buf, unsigned int flags, int cpu, void *arg);
+        int             (*fmt_handler)(struct task_struct *task, void *buf, pfm_ovfl_arg_t *arg, struct pt_regs *regs, unsigned long stamp);
+        int             (*fmt_restart)(struct task_struct *task, pfm_ovfl_ctrl_t *ctrl, void *buf, struct pt_regs *regs);
+        int             (*fmt_restart_active)(struct task_struct *task, pfm_ovfl_ctrl_t *ctrl, void *buf, struct pt_regs *regs);
+        int             (*fmt_exit)(struct task_struct *task, void *buf, struct pt_regs *regs);
+
+        struct list_head fmt_list;
+} pfm_buffer_fmt_t;
+
+extern int pfm_register_buffer_fmt(pfm_buffer_fmt_t *fmt);
+extern int pfm_unregister_buffer_fmt(pfm_uuid_t uuid);
+
+/*
+ * perfmon interface exported to modules
+ */
+extern int pfm_mod_read_pmds(struct task_struct *, void *req, unsigned int nreq, struct pt_regs *regs);
+extern int pfm_mod_write_pmcs(struct task_struct *, void *req, unsigned int nreq, struct pt_regs *regs);
+extern int pfm_mod_write_ibrs(struct task_struct *task, void *req, unsigned int nreq, struct pt_regs *regs);
+extern int pfm_mod_write_dbrs(struct task_struct *task, void *req, unsigned int nreq, struct pt_regs *regs);
+
+/*
+ * describe the content of the local_cpu_date->pfm_syst_info field
+ */
+#define PFM_CPUINFO_SYST_WIDE   0x1     /* if set a system wide session exists */
+#define PFM_CPUINFO_DCR_PP      0x2     /* if set the system wide session has started */
+#define PFM_CPUINFO_EXCL_IDLE   0x4     /* the system wide session excludes the idle task */
+
+/*
+ * sysctl control structure. visible to sampling formats
+ */
+typedef struct {
+        int     debug;          /* turn on/off debugging via syslog */
+        int     debug_ovfl;     /* turn on/off debug printk in overflow handler */
+        int     fastctxsw;      /* turn on/off fast (unsecure) ctxsw */
+        int     expert_mode;    /* turn on/off value checking */
+} pfm_sysctl_t;
+extern pfm_sysctl_t pfm_sysctl;
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_PERFMON_H */
diff --git a/arch/ia64/include/asm/perfmon_default_smpl.h b/arch/ia64/include/asm/perfmon_default_smpl.h
new file mode 100644
index 000000000000..48822c0811d8
--- /dev/null
+++ b/arch/ia64/include/asm/perfmon_default_smpl.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2002-2003 Hewlett-Packard Co
+ *               Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * This file implements the default sampling buffer format
+ * for Linux/ia64 perfmon subsystem.
+ */
+#ifndef __PERFMON_DEFAULT_SMPL_H__
+#define __PERFMON_DEFAULT_SMPL_H__ 1
+
+#define PFM_DEFAULT_SMPL_UUID { \
+                0x4d, 0x72, 0xbe, 0xc0, 0x06, 0x64, 0x41, 0x43, 0x82, 0xb4, 0xd3, 0xfd, 0x27, 0x24, 0x3c, 0x97}
+
+/*
+ * format specific parameters (passed at context creation)
+ */
+typedef struct {
+        unsigned long buf_size;         /* size of the buffer in bytes */
+        unsigned int  flags;            /* buffer specific flags */
+        unsigned int  res1;             /* for future use */
+        unsigned long reserved[2];      /* for future use */
+} pfm_default_smpl_arg_t;
+
+/*
+ * combined context+format specific structure. Can be passed
+ * to PFM_CONTEXT_CREATE
+ */
+typedef struct {
+        pfarg_context_t         ctx_arg;
+        pfm_default_smpl_arg_t  buf_arg;
+} pfm_default_smpl_ctx_arg_t;
+
+/*
+ * This header is at the beginning of the sampling buffer returned to the user.
+ * It is directly followed by the first record.
+ */
+typedef struct {
+        unsigned long   hdr_count;              /* how many valid entries */
+        unsigned long   hdr_cur_offs;           /* current offset from top of buffer */
+        unsigned long   hdr_reserved2;          /* reserved for future use */
+
+        unsigned long   hdr_overflows;          /* how many times the buffer overflowed */
+        unsigned long   hdr_buf_size;           /* how many bytes in the buffer */
+
+        unsigned int    hdr_version;            /* contains perfmon version (smpl format diffs) */
+        unsigned int    hdr_reserved1;          /* for future use */
+        unsigned long   hdr_reserved[10];       /* for future use */
+} pfm_default_smpl_hdr_t;
+
+/*
+ * Entry header in the sampling buffer.  The header is directly followed
+ * with the values of the PMD registers of interest saved in increasing 
+ * index order: PMD4, PMD5, and so on. How many PMDs are present depends 
+ * on how the session was programmed.
+ *
+ * In the case where multiple counters overflow at the same time, multiple
+ * entries are written consecutively.
+ *
+ * last_reset_value member indicates the initial value of the overflowed PMD. 
+ */
+typedef struct {
+        int             pid;                    /* thread id (for NPTL, this is gettid()) */
+        unsigned char   reserved1[3];           /* reserved for future use */
+        unsigned char   ovfl_pmd;               /* index of overflowed PMD */
+
+        unsigned long   last_reset_val;         /* initial value of overflowed PMD */
+        unsigned long   ip;                     /* where did the overflow interrupt happened  */
+        unsigned long   tstamp;                 /* ar.itc when entering perfmon intr. handler */
+
+        unsigned short  cpu;                    /* cpu on which the overfow occured */
+        unsigned short  set;                    /* event set active when overflow ocurred   */
+        int             tgid;                   /* thread group id (for NPTL, this is getpid()) */
+} pfm_default_smpl_entry_t;
+
+#define PFM_DEFAULT_MAX_PMDS            64 /* how many pmds supported by data structures (sizeof(unsigned long) */
+#define PFM_DEFAULT_MAX_ENTRY_SIZE      (sizeof(pfm_default_smpl_entry_t)+(sizeof(unsigned long)*PFM_DEFAULT_MAX_PMDS))
+#define PFM_DEFAULT_SMPL_MIN_BUF_SIZE   (sizeof(pfm_default_smpl_hdr_t)+PFM_DEFAULT_MAX_ENTRY_SIZE)
+
+#define PFM_DEFAULT_SMPL_VERSION_MAJ    2U
+#define PFM_DEFAULT_SMPL_VERSION_MIN    0U
+#define PFM_DEFAULT_SMPL_VERSION        (((PFM_DEFAULT_SMPL_VERSION_MAJ&0xffff)<<16)|(PFM_DEFAULT_SMPL_VERSION_MIN & 0xffff))
+
+#endif /* __PERFMON_DEFAULT_SMPL_H__ */
diff --git a/arch/ia64/include/asm/pgalloc.h b/arch/ia64/include/asm/pgalloc.h
new file mode 100644
index 000000000000..b9ac1a6fc216
--- /dev/null
+++ b/arch/ia64/include/asm/pgalloc.h
@@ -0,0 +1,122 @@
+#ifndef _ASM_IA64_PGALLOC_H
+#define _ASM_IA64_PGALLOC_H
+
+/*
+ * This file contains the functions and defines necessary to allocate
+ * page tables.
+ *
+ * This hopefully works with any (fixed) ia-64 page-size, as defined
+ * in <asm/page.h> (currently 8192).
+ *
+ * Copyright (C) 1998-2001 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2000, Goutham Rao <goutham.rao@intel.com>
+ */
+
+
+#include <linux/compiler.h>
+#include <linux/mm.h>
+#include <linux/page-flags.h>
+#include <linux/threads.h>
+#include <linux/quicklist.h>
+
+#include <asm/mmu_context.h>
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        quicklist_free(0, NULL, pgd);
+}
+
+#ifdef CONFIG_PGTABLE_4
+static inline void
+pgd_populate(struct mm_struct *mm, pgd_t * pgd_entry, pud_t * pud)
+{
+        pgd_val(*pgd_entry) = __pa(pud);
+}
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pud_free(struct mm_struct *mm, pud_t *pud)
+{
+        quicklist_free(0, NULL, pud);
+}
+#define __pud_free_tlb(tlb, pud)        pud_free((tlb)->mm, pud)
+#endif /* CONFIG_PGTABLE_4 */
+
+static inline void
+pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd)
+{
+        pud_val(*pud_entry) = __pa(pmd);
+}
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+        quicklist_free(0, NULL, pmd);
+}
+
+#define __pmd_free_tlb(tlb, pmd)        pmd_free((tlb)->mm, pmd)
+
+static inline void
+pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte)
+{
+        pmd_val(*pmd_entry) = page_to_phys(pte);
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte)
+{
+        pmd_val(*pmd_entry) = __pa(pte);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        struct page *page;
+        void *pg;
+
+        pg = quicklist_alloc(0, GFP_KERNEL, NULL);
+        if (!pg)
+                return NULL;
+        page = virt_to_page(pg);
+        pgtable_page_ctor(page);
+        return page;
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long addr)
+{
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+{
+        pgtable_page_dtor(pte);
+        quicklist_free_page(0, NULL, pte);
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        quicklist_free(0, NULL, pte);
+}
+
+static inline void check_pgt_cache(void)
+{
+        quicklist_trim(0, NULL, 25, 16);
+}
+
+#define __pte_free_tlb(tlb, pte)        pte_free((tlb)->mm, pte)
+
+#endif                          /* _ASM_IA64_PGALLOC_H */
diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h
new file mode 100644
index 000000000000..7a9bff47564f
--- /dev/null
+++ b/arch/ia64/include/asm/pgtable.h
@@ -0,0 +1,615 @@
+#ifndef _ASM_IA64_PGTABLE_H
+#define _ASM_IA64_PGTABLE_H
+
+/*
+ * This file contains the functions and defines necessary to modify and use
+ * the IA-64 page table tree.
+ *
+ * This hopefully works with any (fixed) IA-64 page-size, as defined
+ * in <asm/page.h>.
+ *
+ * Copyright (C) 1998-2005 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+
+#include <asm/mman.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/types.h>
+
+#define IA64_MAX_PHYS_BITS      50      /* max. number of physical address bits (architected) */
+
+/*
+ * First, define the various bits in a PTE.  Note that the PTE format
+ * matches the VHPT short format, the firt doubleword of the VHPD long
+ * format, and the first doubleword of the TLB insertion format.
+ */
+#define _PAGE_P_BIT             0
+#define _PAGE_A_BIT             5
+#define _PAGE_D_BIT             6
+
+#define _PAGE_P                 (1 << _PAGE_P_BIT)      /* page present bit */
+#define _PAGE_MA_WB             (0x0 <<  2)     /* write back memory attribute */
+#define _PAGE_MA_UC             (0x4 <<  2)     /* uncacheable memory attribute */
+#define _PAGE_MA_UCE            (0x5 <<  2)     /* UC exported attribute */
+#define _PAGE_MA_WC             (0x6 <<  2)     /* write coalescing memory attribute */
+#define _PAGE_MA_NAT            (0x7 <<  2)     /* not-a-thing attribute */
+#define _PAGE_MA_MASK           (0x7 <<  2)
+#define _PAGE_PL_0              (0 <<  7)       /* privilege level 0 (kernel) */
+#define _PAGE_PL_1              (1 <<  7)       /* privilege level 1 (unused) */
+#define _PAGE_PL_2              (2 <<  7)       /* privilege level 2 (unused) */
+#define _PAGE_PL_3              (3 <<  7)       /* privilege level 3 (user) */
+#define _PAGE_PL_MASK           (3 <<  7)
+#define _PAGE_AR_R              (0 <<  9)       /* read only */
+#define _PAGE_AR_RX             (1 <<  9)       /* read & execute */
+#define _PAGE_AR_RW             (2 <<  9)       /* read & write */
+#define _PAGE_AR_RWX            (3 <<  9)       /* read, write & execute */
+#define _PAGE_AR_R_RW           (4 <<  9)       /* read / read & write */
+#define _PAGE_AR_RX_RWX         (5 <<  9)       /* read & exec / read, write & exec */
+#define _PAGE_AR_RWX_RW         (6 <<  9)       /* read, write & exec / read & write */
+#define _PAGE_AR_X_RX           (7 <<  9)       /* exec & promote / read & exec */
+#define _PAGE_AR_MASK           (7 <<  9)
+#define _PAGE_AR_SHIFT          9
+#define _PAGE_A                 (1 << _PAGE_A_BIT)      /* page accessed bit */
+#define _PAGE_D                 (1 << _PAGE_D_BIT)      /* page dirty bit */
+#define _PAGE_PPN_MASK          (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
+#define _PAGE_ED                (__IA64_UL(1) << 52)    /* exception deferral */
+#define _PAGE_PROTNONE          (__IA64_UL(1) << 63)
+
+/* Valid only for a PTE with the present bit cleared: */
+#define _PAGE_FILE              (1 << 1)                /* see swap & file pte remarks below */
+
+#define _PFN_MASK               _PAGE_PPN_MASK
+/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
+#define _PAGE_CHG_MASK  (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
+
+#define _PAGE_SIZE_4K   12
+#define _PAGE_SIZE_8K   13
+#define _PAGE_SIZE_16K  14
+#define _PAGE_SIZE_64K  16
+#define _PAGE_SIZE_256K 18
+#define _PAGE_SIZE_1M   20
+#define _PAGE_SIZE_4M   22
+#define _PAGE_SIZE_16M  24
+#define _PAGE_SIZE_64M  26
+#define _PAGE_SIZE_256M 28
+#define _PAGE_SIZE_1G   30
+#define _PAGE_SIZE_4G   32
+
+#define __ACCESS_BITS           _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
+#define __DIRTY_BITS_NO_ED      _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
+#define __DIRTY_BITS            _PAGE_ED | __DIRTY_BITS_NO_ED
+
+/*
+ * How many pointers will a page table level hold expressed in shift
+ */
+#define PTRS_PER_PTD_SHIFT      (PAGE_SHIFT-3)
+
+/*
+ * Definitions for fourth level:
+ */
+#define PTRS_PER_PTE    (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
+
+/*
+ * Definitions for third level:
+ *
+ * PMD_SHIFT determines the size of the area a third-level page table
+ * can map.
+ */
+#define PMD_SHIFT       (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+#define PTRS_PER_PMD    (1UL << (PTRS_PER_PTD_SHIFT))
+
+#ifdef CONFIG_PGTABLE_4
+/*
+ * Definitions for second level:
+ *
+ * PUD_SHIFT determines the size of the area a second-level page table
+ * can map.
+ */
+#define PUD_SHIFT       (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
+#define PUD_SIZE        (1UL << PUD_SHIFT)
+#define PUD_MASK        (~(PUD_SIZE-1))
+#define PTRS_PER_PUD    (1UL << (PTRS_PER_PTD_SHIFT))
+#endif
+
+/*
+ * Definitions for first level:
+ *
+ * PGDIR_SHIFT determines what a first-level page table entry can map.
+ */
+#ifdef CONFIG_PGTABLE_4
+#define PGDIR_SHIFT             (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
+#else
+#define PGDIR_SHIFT             (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
+#endif
+#define PGDIR_SIZE              (__IA64_UL(1) << PGDIR_SHIFT)
+#define PGDIR_MASK              (~(PGDIR_SIZE-1))
+#define PTRS_PER_PGD_SHIFT      PTRS_PER_PTD_SHIFT
+#define PTRS_PER_PGD            (1UL << PTRS_PER_PGD_SHIFT)
+#define USER_PTRS_PER_PGD       (5*PTRS_PER_PGD/8)      /* regions 0-4 are user regions */
+#define FIRST_USER_ADDRESS      0
+
+/*
+ * All the normal masks have the "page accessed" bits on, as any time
+ * they are used, the page is accessed. They are cleared only by the
+ * page-out routines.
+ */
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_A)
+#define PAGE_SHARED     __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
+#define PAGE_READONLY   __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
+#define PAGE_COPY       __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
+#define PAGE_COPY_EXEC  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
+#define PAGE_GATE       __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
+#define PAGE_KERNEL     __pgprot(__DIRTY_BITS  | _PAGE_PL_0 | _PAGE_AR_RWX)
+#define PAGE_KERNELRX   __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
+
+# ifndef __ASSEMBLY__
+
+#include <linux/sched.h>        /* for mm_struct */
+#include <linux/bitops.h>
+#include <asm/cacheflush.h>
+#include <asm/mmu_context.h>
+#include <asm/processor.h>
+
+/*
+ * Next come the mappings that determine how mmap() protection bits
+ * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented.  The
+ * _P version gets used for a private shared memory segment, the _S
+ * version gets used for a shared memory segment with MAP_SHARED on.
+ * In a private shared memory segment, we do a copy-on-write if a task
+ * attempts to write to the page.
+ */
+        /* xwr */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_READONLY   /* write to priv pg -> copy & make writable */
+#define __P011  PAGE_READONLY   /* ditto */
+#define __P100  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
+#define __P101  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
+#define __P110  PAGE_COPY_EXEC
+#define __P111  PAGE_COPY_EXEC
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_SHARED     /* we don't have (and don't need) write-only */
+#define __S011  PAGE_SHARED
+#define __S100  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
+#define __S101  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
+#define __S110  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
+#define __S111  __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
+
+#define pgd_ERROR(e)    printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
+#ifdef CONFIG_PGTABLE_4
+#define pud_ERROR(e)    printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
+#endif
+#define pmd_ERROR(e)    printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pte_ERROR(e)    printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+
+
+/*
+ * Some definitions to translate between mem_map, PTEs, and page addresses:
+ */
+
+
+/* Quick test to see if ADDR is a (potentially) valid physical address. */
+static inline long
+ia64_phys_addr_valid (unsigned long addr)
+{
+        return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
+}
+
+/*
+ * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
+ * memory.  For the return value to be meaningful, ADDR must be >=
+ * PAGE_OFFSET.  This operation can be relatively expensive (e.g.,
+ * require a hash-, or multi-level tree-lookup or something of that
+ * sort) but it guarantees to return TRUE only if accessing the page
+ * at that address does not cause an error.  Note that there may be
+ * addresses for which kern_addr_valid() returns FALSE even though an
+ * access would not cause an error (e.g., this is typically true for
+ * memory mapped I/O regions.
+ *
+ * XXX Need to implement this for IA-64.
+ */
+#define kern_addr_valid(addr)   (1)
+
+
+/*
+ * Now come the defines and routines to manage and access the three-level
+ * page table.
+ */
+
+
+#define VMALLOC_START           (RGN_BASE(RGN_GATE) + 0x200000000UL)
+#ifdef CONFIG_VIRTUAL_MEM_MAP
+# define VMALLOC_END_INIT       (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
+# define VMALLOC_END            vmalloc_end
+  extern unsigned long vmalloc_end;
+#else
+#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
+/* SPARSEMEM_VMEMMAP uses half of vmalloc... */
+# define VMALLOC_END            (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10)))
+# define vmemmap                ((struct page *)VMALLOC_END)
+#else
+# define VMALLOC_END            (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
+#endif
+#endif
+
+/* fs/proc/kcore.c */
+#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
+#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
+
+#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
+#define RGN_MAP_LIMIT   ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE)    /* per region addr limit */
+
+/*
+ * Conversion functions: convert page frame number (pfn) and a protection value to a page
+ * table entry (pte).
+ */
+#define pfn_pte(pfn, pgprot) \
+({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
+
+/* Extract pfn from pte.  */
+#define pte_pfn(_pte)           ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
+
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+/* This takes a physical page address that is used by the remapping functions */
+#define mk_pte_phys(physpage, pgprot) \
+({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
+
+#define pte_modify(_pte, newprot) \
+        (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
+
+#define pte_none(pte)                   (!pte_val(pte))
+#define pte_present(pte)                (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
+#define pte_clear(mm,addr,pte)          (pte_val(*(pte)) = 0UL)
+/* pte_page() returns the "struct page *" corresponding to the PTE: */
+#define pte_page(pte)                   virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
+
+#define pmd_none(pmd)                   (!pmd_val(pmd))
+#define pmd_bad(pmd)                    (!ia64_phys_addr_valid(pmd_val(pmd)))
+#define pmd_present(pmd)                (pmd_val(pmd) != 0UL)
+#define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0UL)
+#define pmd_page_vaddr(pmd)             ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
+#define pmd_page(pmd)                   virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
+
+#define pud_none(pud)                   (!pud_val(pud))
+#define pud_bad(pud)                    (!ia64_phys_addr_valid(pud_val(pud)))
+#define pud_present(pud)                (pud_val(pud) != 0UL)
+#define pud_clear(pudp)                 (pud_val(*(pudp)) = 0UL)
+#define pud_page_vaddr(pud)             ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
+#define pud_page(pud)                   virt_to_page((pud_val(pud) + PAGE_OFFSET))
+
+#ifdef CONFIG_PGTABLE_4
+#define pgd_none(pgd)                   (!pgd_val(pgd))
+#define pgd_bad(pgd)                    (!ia64_phys_addr_valid(pgd_val(pgd)))
+#define pgd_present(pgd)                (pgd_val(pgd) != 0UL)
+#define pgd_clear(pgdp)                 (pgd_val(*(pgdp)) = 0UL)
+#define pgd_page_vaddr(pgd)             ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
+#define pgd_page(pgd)                   virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
+#endif
+
+/*
+ * The following have defined behavior only work if pte_present() is true.
+ */
+#define pte_write(pte)  ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
+#define pte_exec(pte)           ((pte_val(pte) & _PAGE_AR_RX) != 0)
+#define pte_dirty(pte)          ((pte_val(pte) & _PAGE_D) != 0)
+#define pte_young(pte)          ((pte_val(pte) & _PAGE_A) != 0)
+#define pte_file(pte)           ((pte_val(pte) & _PAGE_FILE) != 0)
+#define pte_special(pte)        0
+
+/*
+ * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
+ * access rights:
+ */
+#define pte_wrprotect(pte)      (__pte(pte_val(pte) & ~_PAGE_AR_RW))
+#define pte_mkwrite(pte)        (__pte(pte_val(pte) | _PAGE_AR_RW))
+#define pte_mkold(pte)          (__pte(pte_val(pte) & ~_PAGE_A))
+#define pte_mkyoung(pte)        (__pte(pte_val(pte) | _PAGE_A))
+#define pte_mkclean(pte)        (__pte(pte_val(pte) & ~_PAGE_D))
+#define pte_mkdirty(pte)        (__pte(pte_val(pte) | _PAGE_D))
+#define pte_mkhuge(pte)         (__pte(pte_val(pte)))
+#define pte_mkspecial(pte)      (pte)
+
+/*
+ * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
+ * sync icache and dcache when we insert *new* executable page.
+ *  __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache
+ * if necessary.
+ *
+ *  set_pte() is also called by the kernel, but we can expect that the kernel
+ *  flushes icache explicitly if necessary.
+ */
+#define pte_present_exec_user(pte)\
+        ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
+                (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
+
+extern void __ia64_sync_icache_dcache(pte_t pteval);
+static inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+        /* page is present && page is user  && page is executable
+         * && (page swapin or new page or page migraton
+         *      || copy_on_write with page copying.)
+         */
+        if (pte_present_exec_user(pteval) &&
+            (!pte_present(*ptep) ||
+                pte_pfn(*ptep) != pte_pfn(pteval)))
+                /* load_module() calles flush_icache_range() explicitly*/
+                __ia64_sync_icache_dcache(pteval);
+        *ptep = pteval;
+}
+
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+/*
+ * Make page protection values cacheable, uncacheable, or write-
+ * combining.  Note that "protection" is really a misnomer here as the
+ * protection value contains the memory attribute bits, dirty bits, and
+ * various other bits as well.
+ */
+#define pgprot_cacheable(prot)          __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
+#define pgprot_noncached(prot)          __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
+#define pgprot_writecombine(prot)       __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+static inline unsigned long
+pgd_index (unsigned long address)
+{
+        unsigned long region = address >> 61;
+        unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
+
+        return (region << (PAGE_SHIFT - 6)) | l1index;
+}
+
+/* The offset in the 1-level directory is given by the 3 region bits
+   (61..63) and the level-1 bits.  */
+static inline pgd_t*
+pgd_offset (const struct mm_struct *mm, unsigned long address)
+{
+        return mm->pgd + pgd_index(address);
+}
+
+/* In the kernel's mapped region we completely ignore the region number
+   (since we know it's in region number 5). */
+#define pgd_offset_k(addr) \
+        (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
+
+/* Look up a pgd entry in the gate area.  On IA-64, the gate-area
+   resides in the kernel-mapped segment, hence we use pgd_offset_k()
+   here.  */
+#define pgd_offset_gate(mm, addr)       pgd_offset_k(addr)
+
+#ifdef CONFIG_PGTABLE_4
+/* Find an entry in the second-level page table.. */
+#define pud_offset(dir,addr) \
+        ((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
+#endif
+
+/* Find an entry in the third-level page table.. */
+#define pmd_offset(dir,addr) \
+        ((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
+
+/*
+ * Find an entry in the third-level page table.  This looks more complicated than it
+ * should be because some platforms place page tables in high memory.
+ */
+#define pte_index(addr)         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir,addr)     ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
+#define pte_offset_map(dir,addr)        pte_offset_kernel(dir, addr)
+#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
+#define pte_unmap(pte)                  do { } while (0)
+#define pte_unmap_nested(pte)           do { } while (0)
+
+/* atomic versions of the some PTE manipulations: */
+
+static inline int
+ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+        if (!pte_young(*ptep))
+                return 0;
+        return test_and_clear_bit(_PAGE_A_BIT, ptep);
+#else
+        pte_t pte = *ptep;
+        if (!pte_young(pte))
+                return 0;
+        set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
+        return 1;
+#endif
+}
+
+static inline pte_t
+ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+        return __pte(xchg((long *) ptep, 0));
+#else
+        pte_t pte = *ptep;
+        pte_clear(mm, addr, ptep);
+        return pte;
+#endif
+}
+
+static inline void
+ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+#ifdef CONFIG_SMP
+        unsigned long new, old;
+
+        do {
+                old = pte_val(*ptep);
+                new = pte_val(pte_wrprotect(__pte (old)));
+        } while (cmpxchg((unsigned long *) ptep, old, new) != old);
+#else
+        pte_t old_pte = *ptep;
+        set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
+#endif
+}
+
+static inline int
+pte_same (pte_t a, pte_t b)
+{
+        return pte_val(a) == pte_val(b);
+}
+
+#define update_mmu_cache(vma, address, pte) do { } while (0)
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern void paging_init (void);
+
+/*
+ * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
+ *       bits in the swap-type field of the swap pte.  It would be nice to
+ *       enforce that, but we can't easily include <linux/swap.h> here.
+ *       (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
+ *
+ * Format of swap pte:
+ *      bit   0   : present bit (must be zero)
+ *      bit   1   : _PAGE_FILE (must be zero)
+ *      bits  2- 8: swap-type
+ *      bits  9-62: swap offset
+ *      bit  63   : _PAGE_PROTNONE bit
+ *
+ * Format of file pte:
+ *      bit   0   : present bit (must be zero)
+ *      bit   1   : _PAGE_FILE (must be one)
+ *      bits  2-62: file_offset/PAGE_SIZE
+ *      bit  63   : _PAGE_PROTNONE bit
+ */
+#define __swp_type(entry)               (((entry).val >> 2) & 0x7f)
+#define __swp_offset(entry)             (((entry).val << 1) >> 10)
+#define __swp_entry(type,offset)        ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
+
+#define PTE_FILE_MAX_BITS               61
+#define pte_to_pgoff(pte)               ((pte_val(pte) << 1) >> 3)
+#define pgoff_to_pte(off)               ((pte_t) { ((off) << 2) | _PAGE_FILE })
+
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
+extern struct page *zero_page_memmap_ptr;
+#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
+
+/* We provide our own get_unmapped_area to cope with VA holes for userland */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define HUGETLB_PGDIR_SHIFT     (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
+#define HUGETLB_PGDIR_SIZE      (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
+#define HUGETLB_PGDIR_MASK      (~(HUGETLB_PGDIR_SIZE-1))
+#endif
+
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+/*
+ * Update PTEP with ENTRY, which is guaranteed to be a less
+ * restrictive PTE.  That is, ENTRY may have the ACCESSED, DIRTY, and
+ * WRITABLE bits turned on, when the value at PTEP did not.  The
+ * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
+ *
+ * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
+ * having to worry about races.  On SMP machines, there are only two
+ * cases where this is true:
+ *
+ *      (1) *PTEP has the PRESENT bit turned OFF
+ *      (2) ENTRY has the DIRTY bit turned ON
+ *
+ * On ia64, we could implement this routine with a cmpxchg()-loop
+ * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
+ * However, like on x86, we can get a more streamlined version by
+ * observing that it is OK to drop ACCESSED bit updates when
+ * SAFELY_WRITABLE is FALSE.  Besides being rare, all that would do is
+ * result in an extra Access-bit fault, which would then turn on the
+ * ACCESSED bit in the low-level fault handler (iaccess_bit or
+ * daccess_bit in ivt.S).
+ */
+#ifdef CONFIG_SMP
+# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
+({                                                                      \
+        int __changed = !pte_same(*(__ptep), __entry);                  \
+        if (__changed && __safely_writable) {                           \
+                set_pte(__ptep, __entry);                               \
+                flush_tlb_page(__vma, __addr);                          \
+        }                                                               \
+        __changed;                                                      \
+})
+#else
+# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
+({                                                                      \
+        int __changed = !pte_same(*(__ptep), __entry);                  \
+        if (__changed) {                                                \
+                set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry);  \
+                flush_tlb_page(__vma, __addr);                          \
+        }                                                               \
+        __changed;                                                      \
+})
+#endif
+
+#  ifdef CONFIG_VIRTUAL_MEM_MAP
+  /* arch mem_map init routine is needed due to holes in a virtual mem_map */
+#   define __HAVE_ARCH_MEMMAP_INIT
+    extern void memmap_init (unsigned long size, int nid, unsigned long zone,
+                             unsigned long start_pfn);
+#  endif /* CONFIG_VIRTUAL_MEM_MAP */
+# endif /* !__ASSEMBLY__ */
+
+/*
+ * Identity-mapped regions use a large page size.  We'll call such large pages
+ * "granules".  If you can think of a better name that's unambiguous, let me
+ * know...
+ */
+#if defined(CONFIG_IA64_GRANULE_64MB)
+# define IA64_GRANULE_SHIFT     _PAGE_SIZE_64M
+#elif defined(CONFIG_IA64_GRANULE_16MB)
+# define IA64_GRANULE_SHIFT     _PAGE_SIZE_16M
+#endif
+#define IA64_GRANULE_SIZE       (1 << IA64_GRANULE_SHIFT)
+/*
+ * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
+ */
+#define KERNEL_TR_PAGE_SHIFT    _PAGE_SIZE_64M
+#define KERNEL_TR_PAGE_SIZE     (1 << KERNEL_TR_PAGE_SHIFT)
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+/* These tell get_user_pages() that the first gate page is accessible from user-level.  */
+#define FIXADDR_USER_START      GATE_ADDR
+#ifdef HAVE_BUGGY_SEGREL
+# define FIXADDR_USER_END       (GATE_ADDR + 2*PAGE_SIZE)
+#else
+# define FIXADDR_USER_END       (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
+#endif
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+#define __HAVE_ARCH_PTE_SAME
+#define __HAVE_ARCH_PGD_OFFSET_GATE
+
+
+#ifndef CONFIG_PGTABLE_4
+#include <asm-generic/pgtable-nopud.h>
+#endif
+#include <asm-generic/pgtable.h>
+
+#endif /* _ASM_IA64_PGTABLE_H */
diff --git a/arch/ia64/include/asm/poll.h b/arch/ia64/include/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/ia64/include/asm/poll.h
@@ -0,0 +1 @@
+#include <asm-generic/poll.h>
diff --git a/arch/ia64/include/asm/posix_types.h b/arch/ia64/include/asm/posix_types.h
new file mode 100644
index 000000000000..17885567b731
--- /dev/null
+++ b/arch/ia64/include/asm/posix_types.h
@@ -0,0 +1,126 @@
+#ifndef _ASM_IA64_POSIX_TYPES_H
+#define _ASM_IA64_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ *
+ * Based on <asm-alpha/posix_types.h>.
+ *
+ * Modified 1998-2000, 2003
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+typedef unsigned int    __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef long long       __kernel_loff_t;
+typedef int             __kernel_pid_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
+typedef long            __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned long   __kernel_sigset_t;      /* at least 32 bits */
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+typedef __kernel_uid_t __kernel_old_uid_t;
+typedef __kernel_gid_t __kernel_old_gid_t;
+typedef __kernel_uid_t __kernel_uid32_t;
+typedef __kernel_gid_t __kernel_gid32_t;
+
+typedef unsigned int    __kernel_old_dev_t;
+
+# ifdef __KERNEL__
+
+#  ifndef __GNUC__
+
+#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define __FD_ISSET(d, set)      (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
+#define __FD_ZERO(set)  \
+  ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
+
+#  else /* !__GNUC__ */
+
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, const __kernel_fd_set *p)
+{ 
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+        unsigned long *tmp = p->fds_bits;
+        int i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                      case 16:
+                        tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                        tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                        tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+                        tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                        return;
+
+                      case 8:
+                        tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                        tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                        return;
+
+                      case 4:
+                        tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                        return;
+                }
+        }
+        i = __FDSET_LONGS;
+        while (i) {
+                i--;
+                *tmp = 0;
+                tmp++;
+        }
+}
+
+#  endif /* !__GNUC__ */
+# endif /* __KERNEL__ */
+#endif /* _ASM_IA64_POSIX_TYPES_H */
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
new file mode 100644
index 000000000000..f88fa054d01d
--- /dev/null
+++ b/arch/ia64/include/asm/processor.h
@@ -0,0 +1,771 @@
+#ifndef _ASM_IA64_PROCESSOR_H
+#define _ASM_IA64_PROCESSOR_H
+
+/*
+ * Copyright (C) 1998-2004 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *      Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
+ * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
+ *
+ * 11/24/98     S.Eranian       added ia64_set_iva()
+ * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
+ * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
+ */
+
+
+#include <asm/intrinsics.h>
+#include <asm/kregs.h>
+#include <asm/ptrace.h>
+#include <asm/ustack.h>
+
+#define IA64_NUM_PHYS_STACK_REG 96
+#define IA64_NUM_DBG_REGS       8
+
+#define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
+#define DEFAULT_TASK_SIZE       __IA64_UL_CONST(0xa000000000000000)
+
+/*
+ * TASK_SIZE really is a mis-named.  It really is the maximum user
+ * space address (plus one).  On IA-64, there are five regions of 2TB
+ * each (assuming 8KB page size), for a total of 8TB of user virtual
+ * address space.
+ */
+#define TASK_SIZE_OF(tsk)       ((tsk)->thread.task_size)
+#define TASK_SIZE               TASK_SIZE_OF(current)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (current->thread.map_base)
+
+#define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
+#define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
+#define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
+#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
+#define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
+#define IA64_THREAD_MIGRATION   (__IA64_UL(1) << 5)     /* require migration
+                                                           sync at ctx sw */
+#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
+#define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
+
+#define IA64_THREAD_UAC_SHIFT   3
+#define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
+#define IA64_THREAD_FPEMU_SHIFT 6
+#define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
+
+
+/*
+ * This shift should be large enough to be able to represent 1000000000/itc_freq with good
+ * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
+ * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
+ */
+#define IA64_NSEC_PER_CYC_SHIFT 30
+
+#ifndef __ASSEMBLY__
+
+#include <linux/cache.h>
+#include <linux/compiler.h>
+#include <linux/threads.h>
+#include <linux/types.h>
+
+#include <asm/fpu.h>
+#include <asm/page.h>
+#include <asm/percpu.h>
+#include <asm/rse.h>
+#include <asm/unwind.h>
+#include <asm/atomic.h>
+#ifdef CONFIG_NUMA
+#include <asm/nodedata.h>
+#endif
+
+/* like above but expressed as bitfields for more efficient access: */
+struct ia64_psr {
+        __u64 reserved0 : 1;
+        __u64 be : 1;
+        __u64 up : 1;
+        __u64 ac : 1;
+        __u64 mfl : 1;
+        __u64 mfh : 1;
+        __u64 reserved1 : 7;
+        __u64 ic : 1;
+        __u64 i : 1;
+        __u64 pk : 1;
+        __u64 reserved2 : 1;
+        __u64 dt : 1;
+        __u64 dfl : 1;
+        __u64 dfh : 1;
+        __u64 sp : 1;
+        __u64 pp : 1;
+        __u64 di : 1;
+        __u64 si : 1;
+        __u64 db : 1;
+        __u64 lp : 1;
+        __u64 tb : 1;
+        __u64 rt : 1;
+        __u64 reserved3 : 4;
+        __u64 cpl : 2;
+        __u64 is : 1;
+        __u64 mc : 1;
+        __u64 it : 1;
+        __u64 id : 1;
+        __u64 da : 1;
+        __u64 dd : 1;
+        __u64 ss : 1;
+        __u64 ri : 2;
+        __u64 ed : 1;
+        __u64 bn : 1;
+        __u64 reserved4 : 19;
+};
+
+union ia64_isr {
+        __u64  val;
+        struct {
+                __u64 code : 16;
+                __u64 vector : 8;
+                __u64 reserved1 : 8;
+                __u64 x : 1;
+                __u64 w : 1;
+                __u64 r : 1;
+                __u64 na : 1;
+                __u64 sp : 1;
+                __u64 rs : 1;
+                __u64 ir : 1;
+                __u64 ni : 1;
+                __u64 so : 1;
+                __u64 ei : 2;
+                __u64 ed : 1;
+                __u64 reserved2 : 20;
+        };
+};
+
+union ia64_lid {
+        __u64 val;
+        struct {
+                __u64  rv  : 16;
+                __u64  eid : 8;
+                __u64  id  : 8;
+                __u64  ig  : 32;
+        };
+};
+
+union ia64_tpr {
+        __u64 val;
+        struct {
+                __u64 ig0 : 4;
+                __u64 mic : 4;
+                __u64 rsv : 8;
+                __u64 mmi : 1;
+                __u64 ig1 : 47;
+        };
+};
+
+union ia64_itir {
+        __u64 val;
+        struct {
+                __u64 rv3  :  2; /* 0-1 */
+                __u64 ps   :  6; /* 2-7 */
+                __u64 key  : 24; /* 8-31 */
+                __u64 rv4  : 32; /* 32-63 */
+        };
+};
+
+union  ia64_rr {
+        __u64 val;
+        struct {
+                __u64  ve       :  1;  /* enable hw walker */
+                __u64  reserved0:  1;  /* reserved */
+                __u64  ps       :  6;  /* log page size */
+                __u64  rid      : 24;  /* region id */
+                __u64  reserved1: 32;  /* reserved */
+        };
+};
+
+/*
+ * CPU type, hardware bug flags, and per-CPU state.  Frequently used
+ * state comes earlier:
+ */
+struct cpuinfo_ia64 {
+        __u32 softirq_pending;
+        __u64 itm_delta;        /* # of clock cycles between clock ticks */
+        __u64 itm_next;         /* interval timer mask value to use for next clock tick */
+        __u64 nsec_per_cyc;     /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
+        __u64 unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
+        __u64 unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
+        __u64 itc_freq;         /* frequency of ITC counter */
+        __u64 proc_freq;        /* frequency of processor */
+        __u64 cyc_per_usec;     /* itc_freq/1000000 */
+        __u64 ptce_base;
+        __u32 ptce_count[2];
+        __u32 ptce_stride[2];
+        struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
+
+#ifdef CONFIG_SMP
+        __u64 loops_per_jiffy;
+        int cpu;
+        __u32 socket_id;        /* physical processor socket id */
+        __u16 core_id;          /* core id */
+        __u16 thread_id;        /* thread id */
+        __u16 num_log;          /* Total number of logical processors on
+                                 * this socket that were successfully booted */
+        __u8  cores_per_socket; /* Cores per processor socket */
+        __u8  threads_per_core; /* Threads per core */
+#endif
+
+        /* CPUID-derived information: */
+        __u64 ppn;
+        __u64 features;
+        __u8 number;
+        __u8 revision;
+        __u8 model;
+        __u8 family;
+        __u8 archrev;
+        char vendor[16];
+        char *model_name;
+
+#ifdef CONFIG_NUMA
+        struct ia64_node_data *node_data;
+#endif
+};
+
+DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
+
+/*
+ * The "local" data variable.  It refers to the per-CPU data of the currently executing
+ * CPU, much like "current" points to the per-task data of the currently executing task.
+ * Do not use the address of local_cpu_data, since it will be different from
+ * cpu_data(smp_processor_id())!
+ */
+#define local_cpu_data          (&__ia64_per_cpu_var(cpu_info))
+#define cpu_data(cpu)           (&per_cpu(cpu_info, cpu))
+
+extern void print_cpu_info (struct cpuinfo_ia64 *);
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+#define SET_UNALIGN_CTL(task,value)                                                             \
+({                                                                                              \
+        (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
+                                | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
+        0;                                                                                      \
+})
+#define GET_UNALIGN_CTL(task,addr)                                                              \
+({                                                                                              \
+        put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
+                 (int __user *) (addr));                                                        \
+})
+
+#define SET_FPEMU_CTL(task,value)                                                               \
+({                                                                                              \
+        (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
+                          | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
+        0;                                                                                      \
+})
+#define GET_FPEMU_CTL(task,addr)                                                                \
+({                                                                                              \
+        put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
+                 (int __user *) (addr));                                                        \
+})
+
+#ifdef CONFIG_IA32_SUPPORT
+struct desc_struct {
+        unsigned int a, b;
+};
+
+#define desc_empty(desc)                (!((desc)->a | (desc)->b))
+#define desc_equal(desc1, desc2)        (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
+
+#define GDT_ENTRY_TLS_ENTRIES   3
+#define GDT_ENTRY_TLS_MIN       6
+#define GDT_ENTRY_TLS_MAX       (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
+
+#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
+
+struct ia64_partial_page_list;
+#endif
+
+struct thread_struct {
+        __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
+        /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
+        __u8 on_ustack;                 /* executing on user-stacks? */
+        __u8 pad[3];
+        __u64 ksp;                      /* kernel stack pointer */
+        __u64 map_base;                 /* base address for get_unmapped_area() */
+        __u64 task_size;                /* limit for task size */
+        __u64 rbs_bot;                  /* the base address for the RBS */
+        int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
+
+#ifdef CONFIG_IA32_SUPPORT
+        __u64 eflag;                    /* IA32 EFLAGS reg */
+        __u64 fsr;                      /* IA32 floating pt status reg */
+        __u64 fcr;                      /* IA32 floating pt control reg */
+        __u64 fir;                      /* IA32 fp except. instr. reg */
+        __u64 fdr;                      /* IA32 fp except. data reg */
+        __u64 old_k1;                   /* old value of ar.k1 */
+        __u64 old_iob;                  /* old IOBase value */
+        struct ia64_partial_page_list *ppl; /* partial page list for 4K page size issue */
+        /* cached TLS descriptors. */
+        struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
+
+# define INIT_THREAD_IA32       .eflag =        0,                      \
+                                .fsr =          0,                      \
+                                .fcr =          0x17800000037fULL,      \
+                                .fir =          0,                      \
+                                .fdr =          0,                      \
+                                .old_k1 =       0,                      \
+                                .old_iob =      0,                      \
+                                .ppl =          NULL,
+#else
+# define INIT_THREAD_IA32
+#endif /* CONFIG_IA32_SUPPORT */
+#ifdef CONFIG_PERFMON
+        void *pfm_context;                   /* pointer to detailed PMU context */
+        unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
+# define INIT_THREAD_PM         .pfm_context =          NULL,     \
+                                .pfm_needs_checking =   0UL,
+#else
+# define INIT_THREAD_PM
+#endif
+        __u64 dbr[IA64_NUM_DBG_REGS];
+        __u64 ibr[IA64_NUM_DBG_REGS];
+        struct ia64_fpreg fph[96];      /* saved/loaded on demand */
+};
+
+#define INIT_THREAD {                                           \
+        .flags =        0,                                      \
+        .on_ustack =    0,                                      \
+        .ksp =          0,                                      \
+        .map_base =     DEFAULT_MAP_BASE,                       \
+        .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
+        .task_size =    DEFAULT_TASK_SIZE,                      \
+        .last_fph_cpu =  -1,                                    \
+        INIT_THREAD_IA32                                        \
+        INIT_THREAD_PM                                          \
+        .dbr =          {0, },                                  \
+        .ibr =          {0, },                                  \
+        .fph =          {{{{0}}}, }                             \
+}
+
+#define start_thread(regs,new_ip,new_sp) do {                                                   \
+        set_fs(USER_DS);                                                                        \
+        regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))                \
+                         & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));              \
+        regs->cr_iip = new_ip;                                                                  \
+        regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
+        regs->ar_rnat = 0;                                                                      \
+        regs->ar_bspstore = current->thread.rbs_bot;                                            \
+        regs->ar_fpsr = FPSR_DEFAULT;                                                           \
+        regs->loadrs = 0;                                                                       \
+        regs->r8 = get_dumpable(current->mm);   /* set "don't zap registers" flag */            \
+        regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
+        if (unlikely(!get_dumpable(current->mm))) {                                                     \
+                /*                                                                              \
+                 * Zap scratch regs to avoid leaking bits between processes with different      \
+                 * uid/privileges.                                                              \
+                 */                                                                             \
+                regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;                                   \
+                regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;       \
+        }                                                                                       \
+} while (0)
+
+/* Forward declarations, a strange C thing... */
+struct mm_struct;
+struct task_struct;
+
+/*
+ * Free all resources held by a thread. This is called after the
+ * parent of DEAD_TASK has collected the exit status of the task via
+ * wait().
+ */
+#define release_thread(dead_task)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+/*
+ * This is the mechanism for creating a new kernel thread.
+ *
+ * NOTE 1: Only a kernel-only process (ie the swapper or direct
+ * descendants who haven't done an "execve()") should use this: it
+ * will work within a system call from a "real" process, but the
+ * process memory space will not be free'd until both the parent and
+ * the child have exited.
+ *
+ * NOTE 2: This MUST NOT be an inlined function.  Otherwise, we get
+ * into trouble in init/main.c when the child thread returns to
+ * do_basic_setup() and the timing is such that free_initmem() has
+ * been called already.
+ */
+extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
+
+/* Get wait channel for task P.  */
+extern unsigned long get_wchan (struct task_struct *p);
+
+/* Return instruction pointer of blocked task TSK.  */
+#define KSTK_EIP(tsk)                                   \
+  ({                                                    \
+        struct pt_regs *_regs = task_pt_regs(tsk);      \
+        _regs->cr_iip + ia64_psr(_regs)->ri;            \
+  })
+
+/* Return stack pointer of blocked task TSK.  */
+#define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
+
+extern void ia64_getreg_unknown_kr (void);
+extern void ia64_setreg_unknown_kr (void);
+
+#define ia64_get_kr(regnum)                                     \
+({                                                              \
+        unsigned long r = 0;                                    \
+                                                                \
+        switch (regnum) {                                       \
+            case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;   \
+            case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;   \
+            case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;   \
+            case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;   \
+            case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;   \
+            case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;   \
+            case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;   \
+            case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;   \
+            default: ia64_getreg_unknown_kr(); break;           \
+        }                                                       \
+        r;                                                      \
+})
+
+#define ia64_set_kr(regnum, r)                                  \
+({                                                              \
+        switch (regnum) {                                       \
+            case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;    \
+            case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;    \
+            case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;    \
+            case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;    \
+            case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;    \
+            case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;    \
+            case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;    \
+            case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;    \
+            default: ia64_setreg_unknown_kr(); break;           \
+        }                                                       \
+})
+
+/*
+ * The following three macros can't be inline functions because we don't have struct
+ * task_struct at this point.
+ */
+
+/*
+ * Return TRUE if task T owns the fph partition of the CPU we're running on.
+ * Must be called from code that has preemption disabled.
+ */
+#define ia64_is_local_fpu_owner(t)                                                              \
+({                                                                                              \
+        struct task_struct *__ia64_islfo_task = (t);                                            \
+        (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()                           \
+         && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
+})
+
+/*
+ * Mark task T as owning the fph partition of the CPU we're running on.
+ * Must be called from code that has preemption disabled.
+ */
+#define ia64_set_local_fpu_owner(t) do {                                                \
+        struct task_struct *__ia64_slfo_task = (t);                                     \
+        __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
+        ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);               \
+} while (0)
+
+/* Mark the fph partition of task T as being invalid on all CPUs.  */
+#define ia64_drop_fpu(t)        ((t)->thread.last_fph_cpu = -1)
+
+extern void __ia64_init_fpu (void);
+extern void __ia64_save_fpu (struct ia64_fpreg *fph);
+extern void __ia64_load_fpu (struct ia64_fpreg *fph);
+extern void ia64_save_debug_regs (unsigned long *save_area);
+extern void ia64_load_debug_regs (unsigned long *save_area);
+
+#ifdef CONFIG_IA32_SUPPORT
+extern void ia32_save_state (struct task_struct *task);
+extern void ia32_load_state (struct task_struct *task);
+#endif
+
+#define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
+#define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
+
+/* load fp 0.0 into fph */
+static inline void
+ia64_init_fpu (void) {
+        ia64_fph_enable();
+        __ia64_init_fpu();
+        ia64_fph_disable();
+}
+
+/* save f32-f127 at FPH */
+static inline void
+ia64_save_fpu (struct ia64_fpreg *fph) {
+        ia64_fph_enable();
+        __ia64_save_fpu(fph);
+        ia64_fph_disable();
+}
+
+/* load f32-f127 from FPH */
+static inline void
+ia64_load_fpu (struct ia64_fpreg *fph) {
+        ia64_fph_enable();
+        __ia64_load_fpu(fph);
+        ia64_fph_disable();
+}
+
+static inline __u64
+ia64_clear_ic (void)
+{
+        __u64 psr;
+        psr = ia64_getreg(_IA64_REG_PSR);
+        ia64_stop();
+        ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
+        ia64_srlz_i();
+        return psr;
+}
+
+/*
+ * Restore the psr.
+ */
+static inline void
+ia64_set_psr (__u64 psr)
+{
+        ia64_stop();
+        ia64_setreg(_IA64_REG_PSR_L, psr);
+        ia64_srlz_i();
+}
+
+/*
+ * Insert a translation into an instruction and/or data translation
+ * register.
+ */
+static inline void
+ia64_itr (__u64 target_mask, __u64 tr_num,
+          __u64 vmaddr, __u64 pte,
+          __u64 log_page_size)
+{
+        ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
+        ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
+        ia64_stop();
+        if (target_mask & 0x1)
+                ia64_itri(tr_num, pte);
+        if (target_mask & 0x2)
+                ia64_itrd(tr_num, pte);
+}
+
+/*
+ * Insert a translation into the instruction and/or data translation
+ * cache.
+ */
+static inline void
+ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
+          __u64 log_page_size)
+{
+        ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
+        ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
+        ia64_stop();
+        /* as per EAS2.6, itc must be the last instruction in an instruction group */
+        if (target_mask & 0x1)
+                ia64_itci(pte);
+        if (target_mask & 0x2)
+                ia64_itcd(pte);
+}
+
+/*
+ * Purge a range of addresses from instruction and/or data translation
+ * register(s).
+ */
+static inline void
+ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
+{
+        if (target_mask & 0x1)
+                ia64_ptri(vmaddr, (log_size << 2));
+        if (target_mask & 0x2)
+                ia64_ptrd(vmaddr, (log_size << 2));
+}
+
+/* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
+static inline void
+ia64_set_iva (void *ivt_addr)
+{
+        ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
+        ia64_srlz_i();
+}
+
+/* Set the page table address and control bits.  */
+static inline void
+ia64_set_pta (__u64 pta)
+{
+        /* Note: srlz.i implies srlz.d */
+        ia64_setreg(_IA64_REG_CR_PTA, pta);
+        ia64_srlz_i();
+}
+
+static inline void
+ia64_eoi (void)
+{
+        ia64_setreg(_IA64_REG_CR_EOI, 0);
+        ia64_srlz_d();
+}
+
+#define cpu_relax()     ia64_hint(ia64_hint_pause)
+
+static inline int
+ia64_get_irr(unsigned int vector)
+{
+        unsigned int reg = vector / 64;
+        unsigned int bit = vector % 64;
+        u64 irr;
+
+        switch (reg) {
+        case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
+        case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
+        case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
+        case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
+        }
+
+        return test_bit(bit, &irr);
+}
+
+static inline void
+ia64_set_lrr0 (unsigned long val)
+{
+        ia64_setreg(_IA64_REG_CR_LRR0, val);
+        ia64_srlz_d();
+}
+
+static inline void
+ia64_set_lrr1 (unsigned long val)
+{
+        ia64_setreg(_IA64_REG_CR_LRR1, val);
+        ia64_srlz_d();
+}
+
+
+/*
+ * Given the address to which a spill occurred, return the unat bit
+ * number that corresponds to this address.
+ */
+static inline __u64
+ia64_unat_pos (void *spill_addr)
+{
+        return ((__u64) spill_addr >> 3) & 0x3f;
+}
+
+/*
+ * Set the NaT bit of an integer register which was spilled at address
+ * SPILL_ADDR.  UNAT is the mask to be updated.
+ */
+static inline void
+ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
+{
+        __u64 bit = ia64_unat_pos(spill_addr);
+        __u64 mask = 1UL << bit;
+
+        *unat = (*unat & ~mask) | (nat << bit);
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ * Note that the only way T can block is through a call to schedule() -> switch_to().
+ */
+static inline unsigned long
+thread_saved_pc (struct task_struct *t)
+{
+        struct unw_frame_info info;
+        unsigned long ip;
+
+        unw_init_from_blocked_task(&info, t);
+        if (unw_unwind(&info) < 0)
+                return 0;
+        unw_get_ip(&info, &ip);
+        return ip;
+}
+
+/*
+ * Get the current instruction/program counter value.
+ */
+#define current_text_addr() \
+        ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
+
+static inline __u64
+ia64_get_ivr (void)
+{
+        __u64 r;
+        ia64_srlz_d();
+        r = ia64_getreg(_IA64_REG_CR_IVR);
+        ia64_srlz_d();
+        return r;
+}
+
+static inline void
+ia64_set_dbr (__u64 regnum, __u64 value)
+{
+        __ia64_set_dbr(regnum, value);
+#ifdef CONFIG_ITANIUM
+        ia64_srlz_d();
+#endif
+}
+
+static inline __u64
+ia64_get_dbr (__u64 regnum)
+{
+        __u64 retval;
+
+        retval = __ia64_get_dbr(regnum);
+#ifdef CONFIG_ITANIUM
+        ia64_srlz_d();
+#endif
+        return retval;
+}
+
+static inline __u64
+ia64_rotr (__u64 w, __u64 n)
+{
+        return (w >> n) | (w << (64 - n));
+}
+
+#define ia64_rotl(w,n)  ia64_rotr((w), (64) - (n))
+
+/*
+ * Take a mapped kernel address and return the equivalent address
+ * in the region 7 identity mapped virtual area.
+ */
+static inline void *
+ia64_imva (void *addr)
+{
+        void *result;
+        result = (void *) ia64_tpa(addr);
+        return __va(result);
+}
+
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+#define ARCH_HAS_SPINLOCK_PREFETCH
+#define PREFETCH_STRIDE                 L1_CACHE_BYTES
+
+static inline void
+prefetch (const void *x)
+{
+         ia64_lfetch(ia64_lfhint_none, x);
+}
+
+static inline void
+prefetchw (const void *x)
+{
+        ia64_lfetch_excl(ia64_lfhint_none, x);
+}
+
+#define spin_lock_prefetch(x)   prefetchw(x)
+
+extern unsigned long boot_option_idle_override;
+extern unsigned long idle_halt;
+extern unsigned long idle_nomwait;
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_IA64_PROCESSOR_H */
diff --git a/arch/ia64/include/asm/ptrace.h b/arch/ia64/include/asm/ptrace.h
new file mode 100644
index 000000000000..15f8dcfe6eee
--- /dev/null
+++ b/arch/ia64/include/asm/ptrace.h
@@ -0,0 +1,364 @@
+#ifndef _ASM_IA64_PTRACE_H
+#define _ASM_IA64_PTRACE_H
+
+/*
+ * Copyright (C) 1998-2004 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *      Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 2003 Intel Co
+ *      Suresh Siddha <suresh.b.siddha@intel.com>
+ *      Fenghua Yu <fenghua.yu@intel.com>
+ *      Arun Sharma <arun.sharma@intel.com>
+ *
+ * 12/07/98     S. Eranian      added pt_regs & switch_stack
+ * 12/21/98     D. Mosberger    updated to match latest code
+ *  6/17/99     D. Mosberger    added second unat member to "struct switch_stack"
+ *
+ */
+/*
+ * When a user process is blocked, its state looks as follows:
+ *
+ *            +----------------------+  ------- IA64_STK_OFFSET
+ *            |                      |   ^
+ *            | struct pt_regs       |   |
+ *            |                      |   |
+ *            +----------------------+   |
+ *            |                      |   |
+ *            |    memory stack      |   |
+ *            | (growing downwards)  |   |
+ *            //.....................//  |
+ *                                       |
+ *            //.....................//  |
+ *            |                      |   |
+ *            +----------------------+   |
+ *            | struct switch_stack  |   |
+ *            |                      |   |
+ *            +----------------------+   |
+ *            |                      |   |
+ *            //.....................//  |
+ *                                       |
+ *            //.....................//  |
+ *            |                      |   |
+ *            |  register stack      |   |
+ *            | (growing upwards)    |   |
+ *            |                      |   |
+ *            +----------------------+   |  --- IA64_RBS_OFFSET
+ *            |  struct thread_info  |   |  ^
+ *            +----------------------+   |  |
+ *            |                      |   |  |
+ *            |  struct task_struct  |   |  |
+ * current -> |                      |   |  |
+ *            +----------------------+ -------
+ *
+ * Note that ar.ec is not saved explicitly in pt_reg or switch_stack.
+ * This is because ar.ec is saved as part of ar.pfs.
+ */
+
+
+#include <asm/fpu.h>
+
+#ifdef __KERNEL__
+#ifndef ASM_OFFSETS_C
+#include <asm/asm-offsets.h>
+#endif
+
+/*
+ * Base-2 logarithm of number of pages to allocate per task structure
+ * (including register backing store and memory stack):
+ */
+#if defined(CONFIG_IA64_PAGE_SIZE_4KB)
+# define KERNEL_STACK_SIZE_ORDER                3
+#elif defined(CONFIG_IA64_PAGE_SIZE_8KB)
+# define KERNEL_STACK_SIZE_ORDER                2
+#elif defined(CONFIG_IA64_PAGE_SIZE_16KB)
+# define KERNEL_STACK_SIZE_ORDER                1
+#else
+# define KERNEL_STACK_SIZE_ORDER                0
+#endif
+
+#define IA64_RBS_OFFSET                 ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 31) & ~31)
+#define IA64_STK_OFFSET                 ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE)
+
+#define KERNEL_STACK_SIZE               IA64_STK_OFFSET
+
+#endif /* __KERNEL__ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are saved on system
+ * calls.
+ *
+ * We don't save all floating point register because the kernel
+ * is compiled to use only a very small subset, so the other are
+ * untouched.
+ *
+ * THIS STRUCTURE MUST BE A MULTIPLE 16-BYTE IN SIZE
+ * (because the memory stack pointer MUST ALWAYS be aligned this way)
+ *
+ */
+struct pt_regs {
+        /* The following registers are saved by SAVE_MIN: */
+        unsigned long b6;               /* scratch */
+        unsigned long b7;               /* scratch */
+
+        unsigned long ar_csd;           /* used by cmp8xchg16 (scratch) */
+        unsigned long ar_ssd;           /* reserved for future use (scratch) */
+
+        unsigned long r8;               /* scratch (return value register 0) */
+        unsigned long r9;               /* scratch (return value register 1) */
+        unsigned long r10;              /* scratch (return value register 2) */
+        unsigned long r11;              /* scratch (return value register 3) */
+
+        unsigned long cr_ipsr;          /* interrupted task's psr */
+        unsigned long cr_iip;           /* interrupted task's instruction pointer */
+        /*
+         * interrupted task's function state; if bit 63 is cleared, it
+         * contains syscall's ar.pfs.pfm:
+         */
+        unsigned long cr_ifs;
+
+        unsigned long ar_unat;          /* interrupted task's NaT register (preserved) */
+        unsigned long ar_pfs;           /* prev function state  */
+        unsigned long ar_rsc;           /* RSE configuration */
+        /* The following two are valid only if cr_ipsr.cpl > 0 || ti->flags & _TIF_MCA_INIT */
+        unsigned long ar_rnat;          /* RSE NaT */
+        unsigned long ar_bspstore;      /* RSE bspstore */
+
+        unsigned long pr;               /* 64 predicate registers (1 bit each) */
+        unsigned long b0;               /* return pointer (bp) */
+        unsigned long loadrs;           /* size of dirty partition << 16 */
+
+        unsigned long r1;               /* the gp pointer */
+        unsigned long r12;              /* interrupted task's memory stack pointer */
+        unsigned long r13;              /* thread pointer */
+
+        unsigned long ar_fpsr;          /* floating point status (preserved) */
+        unsigned long r15;              /* scratch */
+
+        /* The remaining registers are NOT saved for system calls.  */
+
+        unsigned long r14;              /* scratch */
+        unsigned long r2;               /* scratch */
+        unsigned long r3;               /* scratch */
+
+        /* The following registers are saved by SAVE_REST: */
+        unsigned long r16;              /* scratch */
+        unsigned long r17;              /* scratch */
+        unsigned long r18;              /* scratch */
+        unsigned long r19;              /* scratch */
+        unsigned long r20;              /* scratch */
+        unsigned long r21;              /* scratch */
+        unsigned long r22;              /* scratch */
+        unsigned long r23;              /* scratch */
+        unsigned long r24;              /* scratch */
+        unsigned long r25;              /* scratch */
+        unsigned long r26;              /* scratch */
+        unsigned long r27;              /* scratch */
+        unsigned long r28;              /* scratch */
+        unsigned long r29;              /* scratch */
+        unsigned long r30;              /* scratch */
+        unsigned long r31;              /* scratch */
+
+        unsigned long ar_ccv;           /* compare/exchange value (scratch) */
+
+        /*
+         * Floating point registers that the kernel considers scratch:
+         */
+        struct ia64_fpreg f6;           /* scratch */
+        struct ia64_fpreg f7;           /* scratch */
+        struct ia64_fpreg f8;           /* scratch */
+        struct ia64_fpreg f9;           /* scratch */
+        struct ia64_fpreg f10;          /* scratch */
+        struct ia64_fpreg f11;          /* scratch */
+};
+
+/*
+ * This structure contains the addition registers that need to
+ * preserved across a context switch.  This generally consists of
+ * "preserved" registers.
+ */
+struct switch_stack {
+        unsigned long caller_unat;      /* user NaT collection register (preserved) */
+        unsigned long ar_fpsr;          /* floating-point status register */
+
+        struct ia64_fpreg f2;           /* preserved */
+        struct ia64_fpreg f3;           /* preserved */
+        struct ia64_fpreg f4;           /* preserved */
+        struct ia64_fpreg f5;           /* preserved */
+
+        struct ia64_fpreg f12;          /* scratch, but untouched by kernel */
+        struct ia64_fpreg f13;          /* scratch, but untouched by kernel */
+        struct ia64_fpreg f14;          /* scratch, but untouched by kernel */
+        struct ia64_fpreg f15;          /* scratch, but untouched by kernel */
+        struct ia64_fpreg f16;          /* preserved */
+        struct ia64_fpreg f17;          /* preserved */
+        struct ia64_fpreg f18;          /* preserved */
+        struct ia64_fpreg f19;          /* preserved */
+        struct ia64_fpreg f20;          /* preserved */
+        struct ia64_fpreg f21;          /* preserved */
+        struct ia64_fpreg f22;          /* preserved */
+        struct ia64_fpreg f23;          /* preserved */
+        struct ia64_fpreg f24;          /* preserved */
+        struct ia64_fpreg f25;          /* preserved */
+        struct ia64_fpreg f26;          /* preserved */
+        struct ia64_fpreg f27;          /* preserved */
+        struct ia64_fpreg f28;          /* preserved */
+        struct ia64_fpreg f29;          /* preserved */
+        struct ia64_fpreg f30;          /* preserved */
+        struct ia64_fpreg f31;          /* preserved */
+
+        unsigned long r4;               /* preserved */
+        unsigned long r5;               /* preserved */
+        unsigned long r6;               /* preserved */
+        unsigned long r7;               /* preserved */
+
+        unsigned long b0;               /* so we can force a direct return in copy_thread */
+        unsigned long b1;
+        unsigned long b2;
+        unsigned long b3;
+        unsigned long b4;
+        unsigned long b5;
+
+        unsigned long ar_pfs;           /* previous function state */
+        unsigned long ar_lc;            /* loop counter (preserved) */
+        unsigned long ar_unat;          /* NaT bits for r4-r7 */
+        unsigned long ar_rnat;          /* RSE NaT collection register */
+        unsigned long ar_bspstore;      /* RSE dirty base (preserved) */
+        unsigned long pr;               /* 64 predicate registers (1 bit each) */
+};
+
+#ifdef __KERNEL__
+
+#include <asm/current.h>
+#include <asm/page.h>
+
+/*
+ * We use the ia64_psr(regs)->ri to determine which of the three
+ * instructions in bundle (16 bytes) took the sample. Generate
+ * the canonical representation by adding to instruction pointer.
+ */
+# define instruction_pointer(regs) ((regs)->cr_iip + ia64_psr(regs)->ri)
+
+#define regs_return_value(regs) ((regs)->r8)
+
+/* Conserve space in histogram by encoding slot bits in address
+ * bits 2 and 3 rather than bits 0 and 1.
+ */
+#define profile_pc(regs)                                                \
+({                                                                      \
+        unsigned long __ip = instruction_pointer(regs);                 \
+        (__ip & ~3UL) + ((__ip & 3UL) << 2);                            \
+})
+
+  /* given a pointer to a task_struct, return the user's pt_regs */
+# define task_pt_regs(t)                (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1)
+# define ia64_psr(regs)                 ((struct ia64_psr *) &(regs)->cr_ipsr)
+# define user_mode(regs)                (((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0)
+# define user_stack(task,regs)  ((long) regs - (long) task == IA64_STK_OFFSET - sizeof(*regs))
+# define fsys_mode(task,regs)                                   \
+  ({                                                            \
+          struct task_struct *_task = (task);                   \
+          struct pt_regs *_regs = (regs);                       \
+          !user_mode(_regs) && user_stack(_task, _regs);        \
+  })
+
+  /*
+   * System call handlers that, upon successful completion, need to return a negative value
+   * should call force_successful_syscall_return() right before returning.  On architectures
+   * where the syscall convention provides for a separate error flag (e.g., alpha, ia64,
+   * ppc{,64}, sparc{,64}, possibly others), this macro can be used to ensure that the error
+   * flag will not get set.  On architectures which do not support a separate error flag,
+   * the macro is a no-op and the spurious error condition needs to be filtered out by some
+   * other means (e.g., in user-level, by passing an extra argument to the syscall handler,
+   * or something along those lines).
+   *
+   * On ia64, we can clear the user's pt_regs->r8 to force a successful syscall.
+   */
+# define force_successful_syscall_return()      (task_pt_regs(current)->r8 = 0)
+
+  struct task_struct;                   /* forward decl */
+  struct unw_frame_info;                /* forward decl */
+
+  extern void show_regs (struct pt_regs *);
+  extern void ia64_do_show_stack (struct unw_frame_info *, void *);
+  extern unsigned long ia64_get_user_rbs_end (struct task_struct *, struct pt_regs *,
+                                              unsigned long *);
+  extern long ia64_peek (struct task_struct *, struct switch_stack *, unsigned long,
+                         unsigned long, long *);
+  extern long ia64_poke (struct task_struct *, struct switch_stack *, unsigned long,
+                         unsigned long, long);
+  extern void ia64_flush_fph (struct task_struct *);
+  extern void ia64_sync_fph (struct task_struct *);
+  extern void ia64_sync_krbs(void);
+  extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *,
+                                  unsigned long, unsigned long);
+
+  /* get nat bits for scratch registers such that bit N==1 iff scratch register rN is a NaT */
+  extern unsigned long ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat);
+  /* put nat bits for scratch registers such that scratch register rN is a NaT iff bit N==1 */
+  extern unsigned long ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat);
+
+  extern void ia64_increment_ip (struct pt_regs *pt);
+  extern void ia64_decrement_ip (struct pt_regs *pt);
+
+  extern void ia64_ptrace_stop(void);
+  #define arch_ptrace_stop(code, info) \
+        ia64_ptrace_stop()
+  #define arch_ptrace_stop_needed(code, info) \
+        (!test_thread_flag(TIF_RESTORE_RSE))
+
+  extern void ptrace_attach_sync_user_rbs (struct task_struct *);
+  #define arch_ptrace_attach(child) \
+        ptrace_attach_sync_user_rbs(child)
+
+  #define arch_has_single_step()  (1)
+  extern void user_enable_single_step(struct task_struct *);
+  extern void user_disable_single_step(struct task_struct *);
+
+  #define arch_has_block_step()   (1)
+  extern void user_enable_block_step(struct task_struct *);
+
+#endif /* !__KERNEL__ */
+
+/* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */
+struct pt_all_user_regs {
+        unsigned long nat;
+        unsigned long cr_iip;
+        unsigned long cfm;
+        unsigned long cr_ipsr;
+        unsigned long pr;
+
+        unsigned long gr[32];
+        unsigned long br[8];
+        unsigned long ar[128];
+        struct ia64_fpreg fr[128];
+};
+
+#endif /* !__ASSEMBLY__ */
+
+/* indices to application-registers array in pt_all_user_regs */
+#define PT_AUR_RSC      16
+#define PT_AUR_BSP      17
+#define PT_AUR_BSPSTORE 18
+#define PT_AUR_RNAT     19
+#define PT_AUR_CCV      32
+#define PT_AUR_UNAT     36
+#define PT_AUR_FPSR     40
+#define PT_AUR_PFS      64
+#define PT_AUR_LC       65
+#define PT_AUR_EC       66
+
+/*
+ * The numbers chosen here are somewhat arbitrary but absolutely MUST
+ * not overlap with any of the number assigned in <linux/ptrace.h>.
+ */
+#define PTRACE_SINGLEBLOCK      12      /* resume execution until next branch */
+#define PTRACE_OLD_GETSIGINFO   13      /* (replaced by PTRACE_GETSIGINFO in <linux/ptrace.h>)  */
+#define PTRACE_OLD_SETSIGINFO   14      /* (replaced by PTRACE_SETSIGINFO in <linux/ptrace.h>)  */
+#define PTRACE_GETREGS          18      /* get all registers (pt_all_user_regs) in one shot */
+#define PTRACE_SETREGS          19      /* set all registers (pt_all_user_regs) in one shot */
+
+#define PTRACE_OLDSETOPTIONS    21
+
+#endif /* _ASM_IA64_PTRACE_H */
diff --git a/arch/ia64/include/asm/ptrace_offsets.h b/arch/ia64/include/asm/ptrace_offsets.h
new file mode 100644
index 000000000000..b712773c759e
--- /dev/null
+++ b/arch/ia64/include/asm/ptrace_offsets.h
@@ -0,0 +1,268 @@
+#ifndef _ASM_IA64_PTRACE_OFFSETS_H
+#define _ASM_IA64_PTRACE_OFFSETS_H
+
+/*
+ * Copyright (C) 1999, 2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+/*
+ * The "uarea" that can be accessed via PEEKUSER and POKEUSER is a
+ * virtual structure that would have the following definition:
+ *
+ *      struct uarea {
+ *              struct ia64_fpreg fph[96];              // f32-f127
+ *              unsigned long nat_bits;
+ *              unsigned long empty1;
+ *              struct ia64_fpreg f2;                   // f2-f5
+ *                      :
+ *              struct ia64_fpreg f5;
+ *              struct ia64_fpreg f10;                  // f10-f31
+ *                      :
+ *              struct ia64_fpreg f31;
+ *              unsigned long r4;                       // r4-r7
+ *                      :
+ *              unsigned long r7;
+ *              unsigned long b1;                       // b1-b5
+ *                      :
+ *              unsigned long b5;
+ *              unsigned long ar_ec;
+ *              unsigned long ar_lc;
+ *              unsigned long empty2[5];
+ *              unsigned long cr_ipsr;
+ *              unsigned long cr_iip;
+ *              unsigned long cfm;
+ *              unsigned long ar_unat;
+ *              unsigned long ar_pfs;
+ *              unsigned long ar_rsc;
+ *              unsigned long ar_rnat;
+ *              unsigned long ar_bspstore;
+ *              unsigned long pr;
+ *              unsigned long b6;
+ *              unsigned long ar_bsp;
+ *              unsigned long r1;
+ *              unsigned long r2;
+ *              unsigned long r3;
+ *              unsigned long r12;
+ *              unsigned long r13;
+ *              unsigned long r14;
+ *              unsigned long r15;
+ *              unsigned long r8;
+ *              unsigned long r9;
+ *              unsigned long r10;
+ *              unsigned long r11;
+ *              unsigned long r16;
+ *                      :
+ *              unsigned long r31;
+ *              unsigned long ar_ccv;
+ *              unsigned long ar_fpsr;
+ *              unsigned long b0;
+ *              unsigned long b7;
+ *              unsigned long f6;
+ *              unsigned long f7;
+ *              unsigned long f8;
+ *              unsigned long f9;
+ *              unsigned long ar_csd;
+ *              unsigned long ar_ssd;
+ *              unsigned long rsvd1[710];
+ *              unsigned long dbr[8];
+ *              unsigned long rsvd2[504];
+ *              unsigned long ibr[8];
+ *              unsigned long rsvd3[504];
+ *              unsigned long pmd[4];
+ *      }
+ */
+
+/* fph: */
+#define PT_F32                  0x0000
+#define PT_F33                  0x0010
+#define PT_F34                  0x0020
+#define PT_F35                  0x0030
+#define PT_F36                  0x0040
+#define PT_F37                  0x0050
+#define PT_F38                  0x0060
+#define PT_F39                  0x0070
+#define PT_F40                  0x0080
+#define PT_F41                  0x0090
+#define PT_F42                  0x00a0
+#define PT_F43                  0x00b0
+#define PT_F44                  0x00c0
+#define PT_F45                  0x00d0
+#define PT_F46                  0x00e0
+#define PT_F47                  0x00f0
+#define PT_F48                  0x0100
+#define PT_F49                  0x0110
+#define PT_F50                  0x0120
+#define PT_F51                  0x0130
+#define PT_F52                  0x0140
+#define PT_F53                  0x0150
+#define PT_F54                  0x0160
+#define PT_F55                  0x0170
+#define PT_F56                  0x0180
+#define PT_F57                  0x0190
+#define PT_F58                  0x01a0
+#define PT_F59                  0x01b0
+#define PT_F60                  0x01c0
+#define PT_F61                  0x01d0
+#define PT_F62                  0x01e0
+#define PT_F63                  0x01f0
+#define PT_F64                  0x0200
+#define PT_F65                  0x0210
+#define PT_F66                  0x0220
+#define PT_F67                  0x0230
+#define PT_F68                  0x0240
+#define PT_F69                  0x0250
+#define PT_F70                  0x0260
+#define PT_F71                  0x0270
+#define PT_F72                  0x0280
+#define PT_F73                  0x0290
+#define PT_F74                  0x02a0
+#define PT_F75                  0x02b0
+#define PT_F76                  0x02c0
+#define PT_F77                  0x02d0
+#define PT_F78                  0x02e0
+#define PT_F79                  0x02f0
+#define PT_F80                  0x0300
+#define PT_F81                  0x0310
+#define PT_F82                  0x0320
+#define PT_F83                  0x0330
+#define PT_F84                  0x0340
+#define PT_F85                  0x0350
+#define PT_F86                  0x0360
+#define PT_F87                  0x0370
+#define PT_F88                  0x0380
+#define PT_F89                  0x0390
+#define PT_F90                  0x03a0
+#define PT_F91                  0x03b0
+#define PT_F92                  0x03c0
+#define PT_F93                  0x03d0
+#define PT_F94                  0x03e0
+#define PT_F95                  0x03f0
+#define PT_F96                  0x0400
+#define PT_F97                  0x0410
+#define PT_F98                  0x0420
+#define PT_F99                  0x0430
+#define PT_F100                 0x0440
+#define PT_F101                 0x0450
+#define PT_F102                 0x0460
+#define PT_F103                 0x0470
+#define PT_F104                 0x0480
+#define PT_F105                 0x0490
+#define PT_F106                 0x04a0
+#define PT_F107                 0x04b0
+#define PT_F108                 0x04c0
+#define PT_F109                 0x04d0
+#define PT_F110                 0x04e0
+#define PT_F111                 0x04f0
+#define PT_F112                 0x0500
+#define PT_F113                 0x0510
+#define PT_F114                 0x0520
+#define PT_F115                 0x0530
+#define PT_F116                 0x0540
+#define PT_F117                 0x0550
+#define PT_F118                 0x0560
+#define PT_F119                 0x0570
+#define PT_F120                 0x0580
+#define PT_F121                 0x0590
+#define PT_F122                 0x05a0
+#define PT_F123                 0x05b0
+#define PT_F124                 0x05c0
+#define PT_F125                 0x05d0
+#define PT_F126                 0x05e0
+#define PT_F127                 0x05f0
+
+#define PT_NAT_BITS             0x0600
+
+#define PT_F2                   0x0610
+#define PT_F3                   0x0620
+#define PT_F4                   0x0630
+#define PT_F5                   0x0640
+#define PT_F10                  0x0650
+#define PT_F11                  0x0660
+#define PT_F12                  0x0670
+#define PT_F13                  0x0680
+#define PT_F14                  0x0690
+#define PT_F15                  0x06a0
+#define PT_F16                  0x06b0
+#define PT_F17                  0x06c0
+#define PT_F18                  0x06d0
+#define PT_F19                  0x06e0
+#define PT_F20                  0x06f0
+#define PT_F21                  0x0700
+#define PT_F22                  0x0710
+#define PT_F23                  0x0720
+#define PT_F24                  0x0730
+#define PT_F25                  0x0740
+#define PT_F26                  0x0750
+#define PT_F27                  0x0760
+#define PT_F28                  0x0770
+#define PT_F29                  0x0780
+#define PT_F30                  0x0790
+#define PT_F31                  0x07a0
+#define PT_R4                   0x07b0
+#define PT_R5                   0x07b8
+#define PT_R6                   0x07c0
+#define PT_R7                   0x07c8
+
+#define PT_B1                   0x07d8
+#define PT_B2                   0x07e0
+#define PT_B3                   0x07e8
+#define PT_B4                   0x07f0
+#define PT_B5                   0x07f8
+
+#define PT_AR_EC                0x0800
+#define PT_AR_LC                0x0808
+
+#define PT_CR_IPSR              0x0830
+#define PT_CR_IIP               0x0838
+#define PT_CFM                  0x0840
+#define PT_AR_UNAT              0x0848
+#define PT_AR_PFS               0x0850
+#define PT_AR_RSC               0x0858
+#define PT_AR_RNAT              0x0860
+#define PT_AR_BSPSTORE          0x0868
+#define PT_PR                   0x0870
+#define PT_B6                   0x0878
+#define PT_AR_BSP               0x0880  /* note: this points to the *end* of the backing store! */
+#define PT_R1                   0x0888
+#define PT_R2                   0x0890
+#define PT_R3                   0x0898
+#define PT_R12                  0x08a0
+#define PT_R13                  0x08a8
+#define PT_R14                  0x08b0
+#define PT_R15                  0x08b8
+#define PT_R8                   0x08c0
+#define PT_R9                   0x08c8
+#define PT_R10                  0x08d0
+#define PT_R11                  0x08d8
+#define PT_R16                  0x08e0
+#define PT_R17                  0x08e8
+#define PT_R18                  0x08f0
+#define PT_R19                  0x08f8
+#define PT_R20                  0x0900
+#define PT_R21                  0x0908
+#define PT_R22                  0x0910
+#define PT_R23                  0x0918
+#define PT_R24                  0x0920
+#define PT_R25                  0x0928
+#define PT_R26                  0x0930
+#define PT_R27                  0x0938
+#define PT_R28                  0x0940
+#define PT_R29                  0x0948
+#define PT_R30                  0x0950
+#define PT_R31                  0x0958
+#define PT_AR_CCV               0x0960
+#define PT_AR_FPSR              0x0968
+#define PT_B0                   0x0970
+#define PT_B7                   0x0978
+#define PT_F6                   0x0980
+#define PT_F7                   0x0990
+#define PT_F8                   0x09a0
+#define PT_F9                   0x09b0
+#define PT_AR_CSD               0x09c0
+#define PT_AR_SSD               0x09c8
+
+#define PT_DBR                  0x2000  /* data breakpoint registers */
+#define PT_IBR                  0x3000  /* instruction breakpoint registers */
+#define PT_PMD                  0x4000  /* performance monitoring counters */
+
+#endif /* _ASM_IA64_PTRACE_OFFSETS_H */
diff --git a/arch/ia64/include/asm/resource.h b/arch/ia64/include/asm/resource.h
new file mode 100644
index 000000000000..ba2272a87fc7
--- /dev/null
+++ b/arch/ia64/include/asm/resource.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_IA64_RESOURCE_H
+#define _ASM_IA64_RESOURCE_H
+
+#include <asm/ustack.h>
+#include <asm-generic/resource.h>
+
+#endif /* _ASM_IA64_RESOURCE_H */
diff --git a/arch/ia64/include/asm/rse.h b/arch/ia64/include/asm/rse.h
new file mode 100644
index 000000000000..02830a3b0196
--- /dev/null
+++ b/arch/ia64/include/asm/rse.h
@@ -0,0 +1,66 @@
+#ifndef _ASM_IA64_RSE_H
+#define _ASM_IA64_RSE_H
+
+/*
+ * Copyright (C) 1998, 1999 Hewlett-Packard Co
+ * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * Register stack engine related helper functions.  This file may be
+ * used in applications, so be careful about the name-space and give
+ * some consideration to non-GNU C compilers (though __inline__ is
+ * fine).
+ */
+
+static __inline__ unsigned long
+ia64_rse_slot_num (unsigned long *addr)
+{
+        return (((unsigned long) addr) >> 3) & 0x3f;
+}
+
+/*
+ * Return TRUE if ADDR is the address of an RNAT slot.
+ */
+static __inline__ unsigned long
+ia64_rse_is_rnat_slot (unsigned long *addr)
+{
+        return ia64_rse_slot_num(addr) == 0x3f;
+}
+
+/*
+ * Returns the address of the RNAT slot that covers the slot at
+ * address SLOT_ADDR.
+ */
+static __inline__ unsigned long *
+ia64_rse_rnat_addr (unsigned long *slot_addr)
+{
+        return (unsigned long *) ((unsigned long) slot_addr | (0x3f << 3));
+}
+
+/*
+ * Calculate the number of registers in the dirty partition starting at BSPSTORE and
+ * ending at BSP.  This isn't simply (BSP-BSPSTORE)/8 because every 64th slot stores
+ * ar.rnat.
+ */
+static __inline__ unsigned long
+ia64_rse_num_regs (unsigned long *bspstore, unsigned long *bsp)
+{
+        unsigned long slots = (bsp - bspstore);
+
+        return slots - (ia64_rse_slot_num(bspstore) + slots)/0x40;
+}
+
+/*
+ * The inverse of the above: given bspstore and the number of
+ * registers, calculate ar.bsp.
+ */
+static __inline__ unsigned long *
+ia64_rse_skip_regs (unsigned long *addr, long num_regs)
+{
+        long delta = ia64_rse_slot_num(addr) + num_regs;
+
+        if (num_regs < 0)
+                delta -= 0x3e;
+        return addr + num_regs + delta/0x3f;
+}
+
+#endif /* _ASM_IA64_RSE_H */
diff --git a/arch/ia64/include/asm/rwsem.h b/arch/ia64/include/asm/rwsem.h
new file mode 100644
index 000000000000..fbee74b15782
--- /dev/null
+++ b/arch/ia64/include/asm/rwsem.h
@@ -0,0 +1,182 @@
+/*
+ * R/W semaphores for ia64
+ *
+ * Copyright (C) 2003 Ken Chen <kenneth.w.chen@intel.com>
+ * Copyright (C) 2003 Asit Mallick <asit.k.mallick@intel.com>
+ * Copyright (C) 2005 Christoph Lameter <clameter@sgi.com>
+ *
+ * Based on asm-i386/rwsem.h and other architecture implementation.
+ *
+ * The MSW of the count is the negated number of active writers and
+ * waiting lockers, and the LSW is the total number of active locks.
+ *
+ * The lock count is initialized to 0 (no active and no waiting lockers).
+ *
+ * When a writer subtracts WRITE_BIAS, it'll get 0xffffffff00000001 for
+ * the case of an uncontended lock. Readers increment by 1 and see a positive
+ * value when uncontended, negative if there are writers (and maybe) readers
+ * waiting (in which case it goes to sleep).
+ */
+
+#ifndef _ASM_IA64_RWSEM_H
+#define _ASM_IA64_RWSEM_H
+
+#ifndef _LINUX_RWSEM_H
+#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
+#endif
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+
+#include <asm/intrinsics.h>
+
+/*
+ * the semaphore definition
+ */
+struct rw_semaphore {
+        signed long             count;
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+};
+
+#define RWSEM_UNLOCKED_VALUE            __IA64_UL_CONST(0x0000000000000000)
+#define RWSEM_ACTIVE_BIAS               __IA64_UL_CONST(0x0000000000000001)
+#define RWSEM_ACTIVE_MASK               __IA64_UL_CONST(0x00000000ffffffff)
+#define RWSEM_WAITING_BIAS              -__IA64_UL_CONST(0x0000000100000000)
+#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+
+#define __RWSEM_INITIALIZER(name) \
+        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
+          LIST_HEAD_INIT((name).wait_list) }
+
+#define DECLARE_RWSEM(name) \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+
+static inline void
+init_rwsem (struct rw_semaphore *sem)
+{
+        sem->count = RWSEM_UNLOCKED_VALUE;
+        spin_lock_init(&sem->wait_lock);
+        INIT_LIST_HEAD(&sem->wait_list);
+}
+
+/*
+ * lock for reading
+ */
+static inline void
+__down_read (struct rw_semaphore *sem)
+{
+        long result = ia64_fetchadd8_acq((unsigned long *)&sem->count, 1);
+
+        if (result < 0)
+                rwsem_down_read_failed(sem);
+}
+
+/*
+ * lock for writing
+ */
+static inline void
+__down_write (struct rw_semaphore *sem)
+{
+        long old, new;
+
+        do {
+                old = sem->count;
+                new = old + RWSEM_ACTIVE_WRITE_BIAS;
+        } while (cmpxchg_acq(&sem->count, old, new) != old);
+
+        if (old != 0)
+                rwsem_down_write_failed(sem);
+}
+
+/*
+ * unlock after reading
+ */
+static inline void
+__up_read (struct rw_semaphore *sem)
+{
+        long result = ia64_fetchadd8_rel((unsigned long *)&sem->count, -1);
+
+        if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * unlock after writing
+ */
+static inline void
+__up_write (struct rw_semaphore *sem)
+{
+        long old, new;
+
+        do {
+                old = sem->count;
+                new = old - RWSEM_ACTIVE_WRITE_BIAS;
+        } while (cmpxchg_rel(&sem->count, old, new) != old);
+
+        if (new < 0 && (new & RWSEM_ACTIVE_MASK) == 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * trylock for reading -- returns 1 if successful, 0 if contention
+ */
+static inline int
+__down_read_trylock (struct rw_semaphore *sem)
+{
+        long tmp;
+        while ((tmp = sem->count) >= 0) {
+                if (tmp == cmpxchg_acq(&sem->count, tmp, tmp+1)) {
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/*
+ * trylock for writing -- returns 1 if successful, 0 if contention
+ */
+static inline int
+__down_write_trylock (struct rw_semaphore *sem)
+{
+        long tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE,
+                              RWSEM_ACTIVE_WRITE_BIAS);
+        return tmp == RWSEM_UNLOCKED_VALUE;
+}
+
+/*
+ * downgrade write lock to read lock
+ */
+static inline void
+__downgrade_write (struct rw_semaphore *sem)
+{
+        long old, new;
+
+        do {
+                old = sem->count;
+                new = old - RWSEM_WAITING_BIAS;
+        } while (cmpxchg_rel(&sem->count, old, new) != old);
+
+        if (old < 0)
+                rwsem_downgrade_wake(sem);
+}
+
+/*
+ * Implement atomic add functionality.  These used to be "inline" functions, but GCC v3.1
+ * doesn't quite optimize this stuff right and ends up with bad calls to fetchandadd.
+ */
+#define rwsem_atomic_add(delta, sem)    atomic64_add(delta, (atomic64_t *)(&(sem)->count))
+#define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count))
+
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
+#endif /* _ASM_IA64_RWSEM_H */
diff --git a/arch/ia64/include/asm/sal.h b/arch/ia64/include/asm/sal.h
new file mode 100644
index 000000000000..89594b442f83
--- /dev/null
+++ b/arch/ia64/include/asm/sal.h
@@ -0,0 +1,905 @@
+#ifndef _ASM_IA64_SAL_H
+#define _ASM_IA64_SAL_H
+
+/*
+ * System Abstraction Layer definitions.
+ *
+ * This is based on version 2.5 of the manual "IA-64 System
+ * Abstraction Layer".
+ *
+ * Copyright (C) 2001 Intel
+ * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
+ * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
+ * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
+ *
+ * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
+ *                  revision of the SAL spec.
+ * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
+ *                  revision of the SAL spec.
+ * 99/09/29 davidm      Updated for SAL 2.6.
+ * 00/03/29 cfleck      Updated SAL Error Logging info for processor (SAL 2.6)
+ *                      (plus examples of platform error info structures from smariset @ Intel)
+ */
+
+#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT          0
+#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT    1
+#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT    2
+#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT         3
+
+#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK        (1<<IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT)
+#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT)
+#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT)
+#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT       (1<<IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/bcd.h>
+#include <linux/spinlock.h>
+#include <linux/efi.h>
+
+#include <asm/pal.h>
+#include <asm/system.h>
+#include <asm/fpu.h>
+
+extern spinlock_t sal_lock;
+
+/* SAL spec _requires_ eight args for each call. */
+#define __IA64_FW_CALL(entry,result,a0,a1,a2,a3,a4,a5,a6,a7)    \
+        result = (*entry)(a0,a1,a2,a3,a4,a5,a6,a7)
+
+# define IA64_FW_CALL(entry,result,args...) do {                \
+        unsigned long __ia64_sc_flags;                          \
+        struct ia64_fpreg __ia64_sc_fr[6];                      \
+        ia64_save_scratch_fpregs(__ia64_sc_fr);                 \
+        spin_lock_irqsave(&sal_lock, __ia64_sc_flags);          \
+        __IA64_FW_CALL(entry, result, args);                    \
+        spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags);     \
+        ia64_load_scratch_fpregs(__ia64_sc_fr);                 \
+} while (0)
+
+# define SAL_CALL(result,args...)                       \
+        IA64_FW_CALL(ia64_sal, result, args);
+
+# define SAL_CALL_NOLOCK(result,args...) do {           \
+        unsigned long __ia64_scn_flags;                 \
+        struct ia64_fpreg __ia64_scn_fr[6];             \
+        ia64_save_scratch_fpregs(__ia64_scn_fr);        \
+        local_irq_save(__ia64_scn_flags);               \
+        __IA64_FW_CALL(ia64_sal, result, args);         \
+        local_irq_restore(__ia64_scn_flags);            \
+        ia64_load_scratch_fpregs(__ia64_scn_fr);        \
+} while (0)
+
+# define SAL_CALL_REENTRANT(result,args...) do {        \
+        struct ia64_fpreg __ia64_scs_fr[6];             \
+        ia64_save_scratch_fpregs(__ia64_scs_fr);        \
+        preempt_disable();                              \
+        __IA64_FW_CALL(ia64_sal, result, args);         \
+        preempt_enable();                               \
+        ia64_load_scratch_fpregs(__ia64_scs_fr);        \
+} while (0)
+
+#define SAL_SET_VECTORS                 0x01000000
+#define SAL_GET_STATE_INFO              0x01000001
+#define SAL_GET_STATE_INFO_SIZE         0x01000002
+#define SAL_CLEAR_STATE_INFO            0x01000003
+#define SAL_MC_RENDEZ                   0x01000004
+#define SAL_MC_SET_PARAMS               0x01000005
+#define SAL_REGISTER_PHYSICAL_ADDR      0x01000006
+
+#define SAL_CACHE_FLUSH                 0x01000008
+#define SAL_CACHE_INIT                  0x01000009
+#define SAL_PCI_CONFIG_READ             0x01000010
+#define SAL_PCI_CONFIG_WRITE            0x01000011
+#define SAL_FREQ_BASE                   0x01000012
+#define SAL_PHYSICAL_ID_INFO            0x01000013
+
+#define SAL_UPDATE_PAL                  0x01000020
+
+struct ia64_sal_retval {
+        /*
+         * A zero status value indicates call completed without error.
+         * A negative status value indicates reason of call failure.
+         * A positive status value indicates success but an
+         * informational value should be printed (e.g., "reboot for
+         * change to take effect").
+         */
+        s64 status;
+        u64 v0;
+        u64 v1;
+        u64 v2;
+};
+
+typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
+
+enum {
+        SAL_FREQ_BASE_PLATFORM = 0,
+        SAL_FREQ_BASE_INTERVAL_TIMER = 1,
+        SAL_FREQ_BASE_REALTIME_CLOCK = 2
+};
+
+/*
+ * The SAL system table is followed by a variable number of variable
+ * length descriptors.  The structure of these descriptors follows
+ * below.
+ * The defininition follows SAL specs from July 2000
+ */
+struct ia64_sal_systab {
+        u8 signature[4];        /* should be "SST_" */
+        u32 size;               /* size of this table in bytes */
+        u8 sal_rev_minor;
+        u8 sal_rev_major;
+        u16 entry_count;        /* # of entries in variable portion */
+        u8 checksum;
+        u8 reserved1[7];
+        u8 sal_a_rev_minor;
+        u8 sal_a_rev_major;
+        u8 sal_b_rev_minor;
+        u8 sal_b_rev_major;
+        /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
+        u8 oem_id[32];
+        u8 product_id[32];      /* ASCII product id  */
+        u8 reserved2[8];
+};
+
+enum sal_systab_entry_type {
+        SAL_DESC_ENTRY_POINT = 0,
+        SAL_DESC_MEMORY = 1,
+        SAL_DESC_PLATFORM_FEATURE = 2,
+        SAL_DESC_TR = 3,
+        SAL_DESC_PTC = 4,
+        SAL_DESC_AP_WAKEUP = 5
+};
+
+/*
+ * Entry type:  Size:
+ *      0       48
+ *      1       32
+ *      2       16
+ *      3       32
+ *      4       16
+ *      5       16
+ */
+#define SAL_DESC_SIZE(type)     "\060\040\020\040\020\020"[(unsigned) type]
+
+typedef struct ia64_sal_desc_entry_point {
+        u8 type;
+        u8 reserved1[7];
+        u64 pal_proc;
+        u64 sal_proc;
+        u64 gp;
+        u8 reserved2[16];
+}ia64_sal_desc_entry_point_t;
+
+typedef struct ia64_sal_desc_memory {
+        u8 type;
+        u8 used_by_sal; /* needs to be mapped for SAL? */
+        u8 mem_attr;            /* current memory attribute setting */
+        u8 access_rights;       /* access rights set up by SAL */
+        u8 mem_attr_mask;       /* mask of supported memory attributes */
+        u8 reserved1;
+        u8 mem_type;            /* memory type */
+        u8 mem_usage;           /* memory usage */
+        u64 addr;               /* physical address of memory */
+        u32 length;     /* length (multiple of 4KB pages) */
+        u32 reserved2;
+        u8 oem_reserved[8];
+} ia64_sal_desc_memory_t;
+
+typedef struct ia64_sal_desc_platform_feature {
+        u8 type;
+        u8 feature_mask;
+        u8 reserved1[14];
+} ia64_sal_desc_platform_feature_t;
+
+typedef struct ia64_sal_desc_tr {
+        u8 type;
+        u8 tr_type;             /* 0 == instruction, 1 == data */
+        u8 regnum;              /* translation register number */
+        u8 reserved1[5];
+        u64 addr;               /* virtual address of area covered */
+        u64 page_size;          /* encoded page size */
+        u8 reserved2[8];
+} ia64_sal_desc_tr_t;
+
+typedef struct ia64_sal_desc_ptc {
+        u8 type;
+        u8 reserved1[3];
+        u32 num_domains;        /* # of coherence domains */
+        u64 domain_info;        /* physical address of domain info table */
+} ia64_sal_desc_ptc_t;
+
+typedef struct ia64_sal_ptc_domain_info {
+        u64 proc_count;         /* number of processors in domain */
+        u64 proc_list;          /* physical address of LID array */
+} ia64_sal_ptc_domain_info_t;
+
+typedef struct ia64_sal_ptc_domain_proc_entry {
+        u64 id  : 8;            /* id of processor */
+        u64 eid : 8;            /* eid of processor */
+} ia64_sal_ptc_domain_proc_entry_t;
+
+
+#define IA64_SAL_AP_EXTERNAL_INT 0
+
+typedef struct ia64_sal_desc_ap_wakeup {
+        u8 type;
+        u8 mechanism;           /* 0 == external interrupt */
+        u8 reserved1[6];
+        u64 vector;             /* interrupt vector in range 0x10-0xff */
+} ia64_sal_desc_ap_wakeup_t ;
+
+extern ia64_sal_handler ia64_sal;
+extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
+
+extern unsigned short sal_revision;     /* supported SAL spec revision */
+extern unsigned short sal_version;      /* SAL version; OEM dependent */
+#define SAL_VERSION_CODE(major, minor) ((BIN2BCD(major) << 8) | BIN2BCD(minor))
+
+extern const char *ia64_sal_strerror (long status);
+extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
+
+/* SAL information type encodings */
+enum {
+        SAL_INFO_TYPE_MCA  = 0,         /* Machine check abort information */
+        SAL_INFO_TYPE_INIT = 1,         /* Init information */
+        SAL_INFO_TYPE_CMC  = 2,         /* Corrected machine check information */
+        SAL_INFO_TYPE_CPE  = 3          /* Corrected platform error information */
+};
+
+/* Encodings for machine check parameter types */
+enum {
+        SAL_MC_PARAM_RENDEZ_INT    = 1, /* Rendezvous interrupt */
+        SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */
+        SAL_MC_PARAM_CPE_INT       = 3  /* Corrected Platform Error Int */
+};
+
+/* Encodings for rendezvous mechanisms */
+enum {
+        SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
+        SAL_MC_PARAM_MECHANISM_MEM = 2  /* Use memory synchronization variable*/
+};
+
+/* Encodings for vectors which can be registered by the OS with SAL */
+enum {
+        SAL_VECTOR_OS_MCA         = 0,
+        SAL_VECTOR_OS_INIT        = 1,
+        SAL_VECTOR_OS_BOOT_RENDEZ = 2
+};
+
+/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
+#define SAL_MC_PARAM_RZ_ALWAYS          0x1
+#define SAL_MC_PARAM_BINIT_ESCALATE     0x10
+
+/*
+ * Definition of the SAL Error Log from the SAL spec
+ */
+
+/* SAL Error Record Section GUID Definitions */
+#define SAL_PROC_DEV_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define SAL_PLAT_BUS_ERR_SECT_GUID  \
+    EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
+    EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
+                0xca, 0x4d)
+
+#define MAX_CACHE_ERRORS        6
+#define MAX_TLB_ERRORS          6
+#define MAX_BUS_ERRORS          1
+
+/* Definition of version  according to SAL spec for logging purposes */
+typedef struct sal_log_revision {
+        u8 minor;               /* BCD (0..99) */
+        u8 major;               /* BCD (0..99) */
+} sal_log_revision_t;
+
+/* Definition of timestamp according to SAL spec for logging purposes */
+typedef struct sal_log_timestamp {
+        u8 slh_second;          /* Second (0..59) */
+        u8 slh_minute;          /* Minute (0..59) */
+        u8 slh_hour;            /* Hour (0..23) */
+        u8 slh_reserved;
+        u8 slh_day;             /* Day (1..31) */
+        u8 slh_month;           /* Month (1..12) */
+        u8 slh_year;            /* Year (00..99) */
+        u8 slh_century;         /* Century (19, 20, 21, ...) */
+} sal_log_timestamp_t;
+
+/* Definition of log record  header structures */
+typedef struct sal_log_record_header {
+        u64 id;                         /* Unique monotonically increasing ID */
+        sal_log_revision_t revision;    /* Major and Minor revision of header */
+        u8 severity;                    /* Error Severity */
+        u8 validation_bits;             /* 0: platform_guid, 1: !timestamp */
+        u32 len;                        /* Length of this error log in bytes */
+        sal_log_timestamp_t timestamp;  /* Timestamp */
+        efi_guid_t platform_guid;       /* Unique OEM Platform ID */
+} sal_log_record_header_t;
+
+#define sal_log_severity_recoverable    0
+#define sal_log_severity_fatal          1
+#define sal_log_severity_corrected      2
+
+/* Definition of log section header structures */
+typedef struct sal_log_sec_header {
+    efi_guid_t guid;                    /* Unique Section ID */
+    sal_log_revision_t revision;        /* Major and Minor revision of Section */
+    u16 reserved;
+    u32 len;                            /* Section length */
+} sal_log_section_hdr_t;
+
+typedef struct sal_log_mod_error_info {
+        struct {
+                u64 check_info              : 1,
+                    requestor_identifier    : 1,
+                    responder_identifier    : 1,
+                    target_identifier       : 1,
+                    precise_ip              : 1,
+                    reserved                : 59;
+        } valid;
+        u64 check_info;
+        u64 requestor_identifier;
+        u64 responder_identifier;
+        u64 target_identifier;
+        u64 precise_ip;
+} sal_log_mod_error_info_t;
+
+typedef struct sal_processor_static_info {
+        struct {
+                u64 minstate        : 1,
+                    br              : 1,
+                    cr              : 1,
+                    ar              : 1,
+                    rr              : 1,
+                    fr              : 1,
+                    reserved        : 58;
+        } valid;
+        pal_min_state_area_t min_state_area;
+        u64 br[8];
+        u64 cr[128];
+        u64 ar[128];
+        u64 rr[8];
+        struct ia64_fpreg __attribute__ ((packed)) fr[128];
+} sal_processor_static_info_t;
+
+struct sal_cpuid_info {
+        u64 regs[5];
+        u64 reserved;
+};
+
+typedef struct sal_log_processor_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 proc_error_map      : 1,
+                    proc_state_param    : 1,
+                    proc_cr_lid         : 1,
+                    psi_static_struct   : 1,
+                    num_cache_check     : 4,
+                    num_tlb_check       : 4,
+                    num_bus_check       : 4,
+                    num_reg_file_check  : 4,
+                    num_ms_check        : 4,
+                    cpuid_info          : 1,
+                    reserved1           : 39;
+        } valid;
+        u64 proc_error_map;
+        u64 proc_state_parameter;
+        u64 proc_cr_lid;
+        /*
+         * The rest of this structure consists of variable-length arrays, which can't be
+         * expressed in C.
+         */
+        sal_log_mod_error_info_t info[0];
+        /*
+         * This is what the rest looked like if C supported variable-length arrays:
+         *
+         * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check];
+         * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check];
+         * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check];
+         * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check];
+         * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check];
+         * struct sal_cpuid_info cpuid_info;
+         * sal_processor_static_info_t processor_static_info;
+         */
+} sal_log_processor_info_t;
+
+/* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */
+#define SAL_LPI_PSI_INFO(l)                                                                     \
+({      sal_log_processor_info_t *_l = (l);                                                     \
+        ((sal_processor_static_info_t *)                                                        \
+         ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check             \
+                                + _l->valid.num_bus_check + _l->valid.num_reg_file_check        \
+                                + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t)    \
+                               + sizeof(struct sal_cpuid_info))));                              \
+})
+
+/* platform error log structures */
+
+typedef struct sal_log_mem_dev_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 error_status    : 1,
+                    physical_addr   : 1,
+                    addr_mask       : 1,
+                    node            : 1,
+                    card            : 1,
+                    module          : 1,
+                    bank            : 1,
+                    device          : 1,
+                    row             : 1,
+                    column          : 1,
+                    bit_position    : 1,
+                    requestor_id    : 1,
+                    responder_id    : 1,
+                    target_id       : 1,
+                    bus_spec_data   : 1,
+                    oem_id          : 1,
+                    oem_data        : 1,
+                    reserved        : 47;
+        } valid;
+        u64 error_status;
+        u64 physical_addr;
+        u64 addr_mask;
+        u16 node;
+        u16 card;
+        u16 module;
+        u16 bank;
+        u16 device;
+        u16 row;
+        u16 column;
+        u16 bit_position;
+        u64 requestor_id;
+        u64 responder_id;
+        u64 target_id;
+        u64 bus_spec_data;
+        u8 oem_id[16];
+        u8 oem_data[1];                 /* Variable length data */
+} sal_log_mem_dev_err_info_t;
+
+typedef struct sal_log_sel_dev_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 record_id       : 1,
+                    record_type     : 1,
+                    generator_id    : 1,
+                    evm_rev         : 1,
+                    sensor_type     : 1,
+                    sensor_num      : 1,
+                    event_dir       : 1,
+                    event_data1     : 1,
+                    event_data2     : 1,
+                    event_data3     : 1,
+                    reserved        : 54;
+        } valid;
+        u16 record_id;
+        u8 record_type;
+        u8 timestamp[4];
+        u16 generator_id;
+        u8 evm_rev;
+        u8 sensor_type;
+        u8 sensor_num;
+        u8 event_dir;
+        u8 event_data1;
+        u8 event_data2;
+        u8 event_data3;
+} sal_log_sel_dev_err_info_t;
+
+typedef struct sal_log_pci_bus_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 err_status      : 1,
+                    err_type        : 1,
+                    bus_id          : 1,
+                    bus_address     : 1,
+                    bus_data        : 1,
+                    bus_cmd         : 1,
+                    requestor_id    : 1,
+                    responder_id    : 1,
+                    target_id       : 1,
+                    oem_data        : 1,
+                    reserved        : 54;
+        } valid;
+        u64 err_status;
+        u16 err_type;
+        u16 bus_id;
+        u32 reserved;
+        u64 bus_address;
+        u64 bus_data;
+        u64 bus_cmd;
+        u64 requestor_id;
+        u64 responder_id;
+        u64 target_id;
+        u8 oem_data[1];                 /* Variable length data */
+} sal_log_pci_bus_err_info_t;
+
+typedef struct sal_log_smbios_dev_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 event_type      : 1,
+                    length          : 1,
+                    time_stamp      : 1,
+                    data            : 1,
+                    reserved1       : 60;
+        } valid;
+        u8 event_type;
+        u8 length;
+        u8 time_stamp[6];
+        u8 data[1];                     /* data of variable length, length == slsmb_length */
+} sal_log_smbios_dev_err_info_t;
+
+typedef struct sal_log_pci_comp_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 err_status      : 1,
+                    comp_info       : 1,
+                    num_mem_regs    : 1,
+                    num_io_regs     : 1,
+                    reg_data_pairs  : 1,
+                    oem_data        : 1,
+                    reserved        : 58;
+        } valid;
+        u64 err_status;
+        struct {
+                u16 vendor_id;
+                u16 device_id;
+                u8 class_code[3];
+                u8 func_num;
+                u8 dev_num;
+                u8 bus_num;
+                u8 seg_num;
+                u8 reserved[5];
+        } comp_info;
+        u32 num_mem_regs;
+        u32 num_io_regs;
+        u64 reg_data_pairs[1];
+        /*
+         * array of address/data register pairs is num_mem_regs + num_io_regs elements
+         * long.  Each array element consists of a u64 address followed by a u64 data
+         * value.  The oem_data array immediately follows the reg_data_pairs array
+         */
+        u8 oem_data[1];                 /* Variable length data */
+} sal_log_pci_comp_err_info_t;
+
+typedef struct sal_log_plat_specific_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 err_status      : 1,
+                    guid            : 1,
+                    oem_data        : 1,
+                    reserved        : 61;
+        } valid;
+        u64 err_status;
+        efi_guid_t guid;
+        u8 oem_data[1];                 /* platform specific variable length data */
+} sal_log_plat_specific_err_info_t;
+
+typedef struct sal_log_host_ctlr_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 err_status      : 1,
+                    requestor_id    : 1,
+                    responder_id    : 1,
+                    target_id       : 1,
+                    bus_spec_data   : 1,
+                    oem_data        : 1,
+                    reserved        : 58;
+        } valid;
+        u64 err_status;
+        u64 requestor_id;
+        u64 responder_id;
+        u64 target_id;
+        u64 bus_spec_data;
+        u8 oem_data[1];                 /* Variable length OEM data */
+} sal_log_host_ctlr_err_info_t;
+
+typedef struct sal_log_plat_bus_err_info {
+        sal_log_section_hdr_t header;
+        struct {
+                u64 err_status      : 1,
+                    requestor_id    : 1,
+                    responder_id    : 1,
+                    target_id       : 1,
+                    bus_spec_data   : 1,
+                    oem_data        : 1,
+                    reserved        : 58;
+        } valid;
+        u64 err_status;
+        u64 requestor_id;
+        u64 responder_id;
+        u64 target_id;
+        u64 bus_spec_data;
+        u8 oem_data[1];                 /* Variable length OEM data */
+} sal_log_plat_bus_err_info_t;
+
+/* Overall platform error section structure */
+typedef union sal_log_platform_err_info {
+        sal_log_mem_dev_err_info_t mem_dev_err;
+        sal_log_sel_dev_err_info_t sel_dev_err;
+        sal_log_pci_bus_err_info_t pci_bus_err;
+        sal_log_smbios_dev_err_info_t smbios_dev_err;
+        sal_log_pci_comp_err_info_t pci_comp_err;
+        sal_log_plat_specific_err_info_t plat_specific_err;
+        sal_log_host_ctlr_err_info_t host_ctlr_err;
+        sal_log_plat_bus_err_info_t plat_bus_err;
+} sal_log_platform_err_info_t;
+
+/* SAL log over-all, multi-section error record structure (processor+platform) */
+typedef struct err_rec {
+        sal_log_record_header_t sal_elog_header;
+        sal_log_processor_info_t proc_err;
+        sal_log_platform_err_info_t plat_err;
+        u8 oem_data_pad[1024];
+} ia64_err_rec_t;
+
+/*
+ * Now define a couple of inline functions for improved type checking
+ * and convenience.
+ */
+
+extern s64 ia64_sal_cache_flush (u64 cache_type);
+extern void __init check_sal_cache_flush (void);
+
+/* Initialize all the processor and platform level instruction and data caches */
+static inline s64
+ia64_sal_cache_init (void)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
+        return isrv.status;
+}
+
+/*
+ * Clear the processor and platform information logged by SAL with respect to the machine
+ * state at the time of MCA's, INITs, CMCs, or CPEs.
+ */
+static inline s64
+ia64_sal_clear_state_info (u64 sal_info_type)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL_REENTRANT(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
+                      0, 0, 0, 0, 0);
+        return isrv.status;
+}
+
+
+/* Get the processor and platform information logged by SAL with respect to the machine
+ * state at the time of the MCAs, INITs, CMCs, or CPEs.
+ */
+static inline u64
+ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
+                      sal_info, 0, 0, 0, 0);
+        if (isrv.status)
+                return 0;
+
+        return isrv.v0;
+}
+
+/*
+ * Get the maximum size of the information logged by SAL with respect to the machine state
+ * at the time of MCAs, INITs, CMCs, or CPEs.
+ */
+static inline u64
+ia64_sal_get_state_info_size (u64 sal_info_type)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
+                      0, 0, 0, 0, 0);
+        if (isrv.status)
+                return 0;
+        return isrv.v0;
+}
+
+/*
+ * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
+ * the monarch processor.  Must not lock, because it will not return on any cpu until the
+ * monarch processor sends a wake up.
+ */
+static inline s64
+ia64_sal_mc_rendez (void)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
+        return isrv.status;
+}
+
+/*
+ * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
+ * the machine check rendezvous sequence as well as the mechanism to wake up the
+ * non-monarch processor at the end of machine check processing.
+ * Returns the complete ia64_sal_retval because some calls return more than just a status
+ * value.
+ */
+static inline struct ia64_sal_retval
+ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
+                 timeout, rz_always, 0, 0);
+        return isrv;
+}
+
+/* Read from PCI configuration space */
+static inline s64
+ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, type, 0, 0, 0, 0);
+        if (value)
+                *value = isrv.v0;
+        return isrv.status;
+}
+
+/* Write to PCI configuration space */
+static inline s64
+ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
+                 type, 0, 0, 0);
+        return isrv.status;
+}
+
+/*
+ * Register physical addresses of locations needed by SAL when SAL procedures are invoked
+ * in virtual mode.
+ */
+static inline s64
+ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
+                 0, 0, 0, 0, 0);
+        return isrv.status;
+}
+
+/*
+ * Register software dependent code locations within SAL. These locations are handlers or
+ * entry points where SAL will pass control for the specified event. These event handlers
+ * are for the bott rendezvous, MCAs and INIT scenarios.
+ */
+static inline s64
+ia64_sal_set_vectors (u64 vector_type,
+                      u64 handler_addr1, u64 gp1, u64 handler_len1,
+                      u64 handler_addr2, u64 gp2, u64 handler_len2)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
+                        handler_addr1, gp1, handler_len1,
+                        handler_addr2, gp2, handler_len2);
+
+        return isrv.status;
+}
+
+/* Update the contents of PAL block in the non-volatile storage device */
+static inline s64
+ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
+                     u64 *error_code, u64 *scratch_buf_size_needed)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
+                 0, 0, 0, 0);
+        if (error_code)
+                *error_code = isrv.v0;
+        if (scratch_buf_size_needed)
+                *scratch_buf_size_needed = isrv.v1;
+        return isrv.status;
+}
+
+/* Get physical processor die mapping in the platform. */
+static inline s64
+ia64_sal_physical_id_info(u16 *splid)
+{
+        struct ia64_sal_retval isrv;
+
+        if (sal_revision < SAL_VERSION_CODE(3,2))
+                return -1;
+
+        SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
+        if (splid)
+                *splid = isrv.v0;
+        return isrv.status;
+}
+
+extern unsigned long sal_platform_features;
+
+extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
+
+struct sal_ret_values {
+        long r8; long r9; long r10; long r11;
+};
+
+#define IA64_SAL_OEMFUNC_MIN            0x02000000
+#define IA64_SAL_OEMFUNC_MAX            0x03ffffff
+
+extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
+                            u64, u64, u64);
+extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
+                                   u64, u64, u64, u64, u64);
+extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
+                                      u64, u64, u64, u64, u64);
+extern long
+ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
+                    unsigned long *drift_info);
+#ifdef CONFIG_HOTPLUG_CPU
+/*
+ * System Abstraction Layer Specification
+ * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State.
+ * Note: region regs are stored first in head.S _start. Hence they must
+ * stay up front.
+ */
+struct sal_to_os_boot {
+        u64 rr[8];              /* Region Registers */
+        u64 br[6];              /* br0:
+                                 * return addr into SAL boot rendez routine */
+        u64 gr1;                /* SAL:GP */
+        u64 gr12;               /* SAL:SP */
+        u64 gr13;               /* SAL: Task Pointer */
+        u64 fpsr;
+        u64 pfs;
+        u64 rnat;
+        u64 unat;
+        u64 bspstore;
+        u64 dcr;                /* Default Control Register */
+        u64 iva;
+        u64 pta;
+        u64 itv;
+        u64 pmv;
+        u64 cmcv;
+        u64 lrr[2];
+        u64 gr[4];
+        u64 pr;                 /* Predicate registers */
+        u64 lc;                 /* Loop Count */
+        struct ia64_fpreg fp[20];
+};
+
+/*
+ * Global array allocated for NR_CPUS at boot time
+ */
+extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
+
+extern void ia64_jump_to_sal(struct sal_to_os_boot *);
+#endif
+
+extern void ia64_sal_handler_init(void *entry_point, void *gpval);
+
+#define PALO_MAX_TLB_PURGES     0xFFFF
+#define PALO_SIG        "PALO"
+
+struct palo_table {
+        u8  signature[4];       /* Should be "PALO" */
+        u32 length;
+        u8  minor_revision;
+        u8  major_revision;
+        u8  checksum;
+        u8  reserved1[5];
+        u16 max_tlb_purges;
+        u8  reserved2[6];
+};
+
+#define NPTCG_FROM_PAL                  0
+#define NPTCG_FROM_PALO                 1
+#define NPTCG_FROM_KERNEL_PARAMETER     2
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_IA64_SAL_H */
diff --git a/arch/ia64/include/asm/scatterlist.h b/arch/ia64/include/asm/scatterlist.h
new file mode 100644
index 000000000000..d6f57874041d
--- /dev/null
+++ b/arch/ia64/include/asm/scatterlist.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_IA64_SCATTERLIST_H
+#define _ASM_IA64_SCATTERLIST_H
+
+/*
+ * Modified 1998-1999, 2001-2002, 2004
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#include <asm/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+        unsigned long sg_magic;
+#endif
+        unsigned long page_link;
+        unsigned int offset;
+        unsigned int length;    /* buffer length */
+
+        dma_addr_t dma_address;
+        unsigned int dma_length;
+};
+
+/*
+ * It used to be that ISA_DMA_THRESHOLD had something to do with the
+ * DMA-limits of ISA-devices.  Nowadays, its only remaining use (apart
+ * from the aha1542.c driver, which isn't 64-bit clean anyhow) is to
+ * tell the block-layer (via BLK_BOUNCE_ISA) what the max. physical
+ * address of a page is that is allocated with GFP_DMA.  On IA-64,
+ * that's 4GB - 1.
+ */
+#define ISA_DMA_THRESHOLD       0xffffffff
+
+#define sg_dma_len(sg)          ((sg)->dma_length)
+#define sg_dma_address(sg)      ((sg)->dma_address)
+
+#define ARCH_HAS_SG_CHAIN
+
+#endif /* _ASM_IA64_SCATTERLIST_H */
diff --git a/arch/ia64/include/asm/sections.h b/arch/ia64/include/asm/sections.h
new file mode 100644
index 000000000000..7286e4a9fe84
--- /dev/null
+++ b/arch/ia64/include/asm/sections.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_IA64_SECTIONS_H
+#define _ASM_IA64_SECTIONS_H
+
+/*
+ * Copyright (C) 1998-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <asm-generic/sections.h>
+
+extern char __per_cpu_start[], __per_cpu_end[], __phys_per_cpu_start[];
+extern char __start___vtop_patchlist[], __end___vtop_patchlist[];
+extern char __start___rse_patchlist[], __end___rse_patchlist[];
+extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[];
+extern char __start___phys_stack_reg_patchlist[], __end___phys_stack_reg_patchlist[];
+extern char __start_gate_section[];
+extern char __start_gate_mckinley_e9_patchlist[], __end_gate_mckinley_e9_patchlist[];
+extern char __start_gate_vtop_patchlist[], __end_gate_vtop_patchlist[];
+extern char __start_gate_fsyscall_patchlist[], __end_gate_fsyscall_patchlist[];
+extern char __start_gate_brl_fsys_bubble_down_patchlist[], __end_gate_brl_fsys_bubble_down_patchlist[];
+extern char __start_unwind[], __end_unwind[];
+extern char __start_ivt_text[], __end_ivt_text[];
+
+#endif /* _ASM_IA64_SECTIONS_H */
+
diff --git a/arch/ia64/include/asm/segment.h b/arch/ia64/include/asm/segment.h
new file mode 100644
index 000000000000..b89e2b3d648f
--- /dev/null
+++ b/arch/ia64/include/asm/segment.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_IA64_SEGMENT_H
+#define _ASM_IA64_SEGMENT_H
+
+/* Only here because we have some old header files that expect it.. */
+
+#endif /* _ASM_IA64_SEGMENT_H */
diff --git a/arch/ia64/include/asm/sembuf.h b/arch/ia64/include/asm/sembuf.h
new file mode 100644
index 000000000000..1340fbc04d3e
--- /dev/null
+++ b/arch/ia64/include/asm/sembuf.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_IA64_SEMBUF_H
+#define _ASM_IA64_SEMBUF_H
+
+/*
+ * The semid64_ds structure for IA-64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_IA64_SEMBUF_H */
diff --git a/arch/ia64/include/asm/serial.h b/arch/ia64/include/asm/serial.h
new file mode 100644
index 000000000000..068be11583df
--- /dev/null
+++ b/arch/ia64/include/asm/serial.h
@@ -0,0 +1,17 @@
+/*
+ * Derived from the i386 version.
+ */
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+/*
+ * All legacy serial ports should be enumerated via ACPI namespace, so
+ * we need not list them here.
+ */
diff --git a/arch/ia64/include/asm/setup.h b/arch/ia64/include/asm/setup.h
new file mode 100644
index 000000000000..4399a44355b3
--- /dev/null
+++ b/arch/ia64/include/asm/setup.h
@@ -0,0 +1,6 @@
+#ifndef __IA64_SETUP_H
+#define __IA64_SETUP_H
+
+#define COMMAND_LINE_SIZE       2048
+
+#endif
diff --git a/arch/ia64/include/asm/shmbuf.h b/arch/ia64/include/asm/shmbuf.h
new file mode 100644
index 000000000000..585002a77acd
--- /dev/null
+++ b/arch/ia64/include/asm/shmbuf.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_IA64_SHMBUF_H
+#define _ASM_IA64_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for IA-64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        __kernel_time_t         shm_ctime;      /* last change time */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _ASM_IA64_SHMBUF_H */
diff --git a/arch/ia64/include/asm/shmparam.h b/arch/ia64/include/asm/shmparam.h
new file mode 100644
index 000000000000..d07508dc54ae
--- /dev/null
+++ b/arch/ia64/include/asm/shmparam.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_IA64_SHMPARAM_H
+#define _ASM_IA64_SHMPARAM_H
+
+/*
+ * SHMLBA controls minimum alignment at which shared memory segments
+ * get attached.  The IA-64 architecture says that there may be a
+ * performance degradation when there are virtual aliases within 1MB.
+ * To reduce the chance of this, we set SHMLBA to 1MB. --davidm 00/12/20
+ */
+#define SHMLBA  (1024*1024)
+
+#endif /* _ASM_IA64_SHMPARAM_H */
diff --git a/arch/ia64/include/asm/sigcontext.h b/arch/ia64/include/asm/sigcontext.h
new file mode 100644
index 000000000000..57ff777bcc40
--- /dev/null
+++ b/arch/ia64/include/asm/sigcontext.h
@@ -0,0 +1,70 @@
+#ifndef _ASM_IA64_SIGCONTEXT_H
+#define _ASM_IA64_SIGCONTEXT_H
+
+/*
+ * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
+ * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <asm/fpu.h>
+
+#define IA64_SC_FLAG_ONSTACK_BIT                0       /* is handler running on signal stack? */
+#define IA64_SC_FLAG_IN_SYSCALL_BIT             1       /* did signal interrupt a syscall? */
+#define IA64_SC_FLAG_FPH_VALID_BIT              2       /* is state in f[32]-f[127] valid? */
+
+#define IA64_SC_FLAG_ONSTACK            (1 << IA64_SC_FLAG_ONSTACK_BIT)
+#define IA64_SC_FLAG_IN_SYSCALL         (1 << IA64_SC_FLAG_IN_SYSCALL_BIT)
+#define IA64_SC_FLAG_FPH_VALID          (1 << IA64_SC_FLAG_FPH_VALID_BIT)
+
+# ifndef __ASSEMBLY__
+
+/*
+ * Note on handling of register backing store: sc_ar_bsp contains the address that would
+ * be found in ar.bsp after executing a "cover" instruction the context in which the
+ * signal was raised.  If signal delivery required switching to an alternate signal stack
+ * (sc_rbs_base is not NULL), the "dirty" partition (as it would exist after executing the
+ * imaginary "cover" instruction) is backed by the *alternate* signal stack, not the
+ * original one.  In this case, sc_rbs_base contains the base address of the new register
+ * backing store.  The number of registers in the dirty partition can be calculated as:
+ *
+ *   ndirty = ia64_rse_num_regs(sc_rbs_base, sc_rbs_base + (sc_loadrs >> 16))
+ *
+ */
+
+struct sigcontext {
+        unsigned long           sc_flags;       /* see manifest constants above */
+        unsigned long           sc_nat;         /* bit i == 1 iff scratch reg gr[i] is a NaT */
+        stack_t                 sc_stack;       /* previously active stack */
+
+        unsigned long           sc_ip;          /* instruction pointer */
+        unsigned long           sc_cfm;         /* current frame marker */
+        unsigned long           sc_um;          /* user mask bits */
+        unsigned long           sc_ar_rsc;      /* register stack configuration register */
+        unsigned long           sc_ar_bsp;      /* backing store pointer */
+        unsigned long           sc_ar_rnat;     /* RSE NaT collection register */
+        unsigned long           sc_ar_ccv;      /* compare and exchange compare value register */
+        unsigned long           sc_ar_unat;     /* ar.unat of interrupted context */
+        unsigned long           sc_ar_fpsr;     /* floating-point status register */
+        unsigned long           sc_ar_pfs;      /* previous function state */
+        unsigned long           sc_ar_lc;       /* loop count register */
+        unsigned long           sc_pr;          /* predicate registers */
+        unsigned long           sc_br[8];       /* branch registers */
+        /* Note: sc_gr[0] is used as the "uc_link" member of ucontext_t */
+        unsigned long           sc_gr[32];      /* general registers (static partition) */
+        struct ia64_fpreg       sc_fr[128];     /* floating-point registers */
+
+        unsigned long           sc_rbs_base;    /* NULL or new base of sighandler's rbs */
+        unsigned long           sc_loadrs;      /* see description above */
+
+        unsigned long           sc_ar25;        /* cmp8xchg16 uses this */
+        unsigned long           sc_ar26;        /* rsvd for scratch use */
+        unsigned long           sc_rsvd[12];    /* reserved for future use */
+        /*
+         * The mask must come last so we can increase _NSIG_WORDS
+         * without breaking binary compatibility.
+         */
+        sigset_t                sc_mask;        /* signal mask to restore after handler returns */
+};
+
+# endif /* __ASSEMBLY__ */
+#endif /* _ASM_IA64_SIGCONTEXT_H */
diff --git a/arch/ia64/include/asm/siginfo.h b/arch/ia64/include/asm/siginfo.h
new file mode 100644
index 000000000000..9294e4b0c8bc
--- /dev/null
+++ b/arch/ia64/include/asm/siginfo.h
@@ -0,0 +1,139 @@
+#ifndef _ASM_IA64_SIGINFO_H
+#define _ASM_IA64_SIGINFO_H
+
+/*
+ * Based on <asm-i386/siginfo.h>.
+ *
+ * Modified 1998-2002
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+
+#define HAVE_ARCH_SIGINFO_T
+#define HAVE_ARCH_COPY_SIGINFO
+#define HAVE_ARCH_COPY_SIGINFO_TO_USER
+
+#include <asm-generic/siginfo.h>
+
+typedef struct siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+        int __pad0;
+
+        union {
+                int _pad[SI_PAD_SIZE];
+
+                /* kill() */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        uid_t _uid;             /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        char _pad[sizeof(__ARCH_SI_UID_T) - sizeof(int)];
+                        sigval_t _sigval;       /* must overlay ._rt._sigval! */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        uid_t _uid;             /* sender's uid */
+                        sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        pid_t _pid;             /* which child */
+                        uid_t _uid;             /* sender's uid */
+                        int _status;            /* exit code */
+                        clock_t _utime;
+                        clock_t _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        void __user *_addr;     /* faulting insn/memory ref. */
+                        int _imm;               /* immediate value for "break" */
+                        unsigned int _flags;    /* see below */
+                        unsigned long _isr;     /* isr */
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        long _band;     /* POLL_IN, POLL_OUT, POLL_MSG (XPG requires a "long") */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} siginfo_t;
+
+#define si_imm          _sifields._sigfault._imm        /* as per UNIX SysV ABI spec */
+#define si_flags        _sifields._sigfault._flags
+/*
+ * si_isr is valid for SIGILL, SIGFPE, SIGSEGV, SIGBUS, and SIGTRAP provided that
+ * si_code is non-zero and __ISR_VALID is set in si_flags.
+ */
+#define si_isr          _sifields._sigfault._isr
+
+/*
+ * Flag values for si_flags:
+ */
+#define __ISR_VALID_BIT 0
+#define __ISR_VALID     (1 << __ISR_VALID_BIT)
+
+/*
+ * SIGILL si_codes
+ */
+#define ILL_BADIADDR    (__SI_FAULT|9)  /* unimplemented instruction address */
+#define __ILL_BREAK     (__SI_FAULT|10) /* illegal break */
+#define __ILL_BNDMOD    (__SI_FAULT|11) /* bundle-update (modification) in progress */
+#undef NSIGILL
+#define NSIGILL         11
+
+/*
+ * SIGFPE si_codes
+ */
+#define __FPE_DECOVF    (__SI_FAULT|9)  /* decimal overflow */
+#define __FPE_DECDIV    (__SI_FAULT|10) /* decimal division by zero */
+#define __FPE_DECERR    (__SI_FAULT|11) /* packed decimal error */
+#define __FPE_INVASC    (__SI_FAULT|12) /* invalid ASCII digit */
+#define __FPE_INVDEC    (__SI_FAULT|13) /* invalid decimal digit */
+#undef NSIGFPE
+#define NSIGFPE         13
+
+/*
+ * SIGSEGV si_codes
+ */
+#define __SEGV_PSTKOVF  (__SI_FAULT|3)  /* paragraph stack overflow */
+#undef NSIGSEGV
+#define NSIGSEGV        3
+
+/*
+ * SIGTRAP si_codes
+ */
+#define TRAP_BRANCH     (__SI_FAULT|3)  /* process taken branch trap */
+#define TRAP_HWBKPT     (__SI_FAULT|4)  /* hardware breakpoint or watchpoint */
+#undef NSIGTRAP
+#define NSIGTRAP        4
+
+#ifdef __KERNEL__
+#include <linux/string.h>
+
+static inline void
+copy_siginfo (siginfo_t *to, siginfo_t *from)
+{
+        if (from->si_code < 0)
+                memcpy(to, from, sizeof(siginfo_t));
+        else
+                /* _sigchld is currently the largest know union member */
+                memcpy(to, from, 4*sizeof(int) + sizeof(from->_sifields._sigchld));
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_SIGINFO_H */
diff --git a/arch/ia64/include/asm/signal.h b/arch/ia64/include/asm/signal.h
new file mode 100644
index 000000000000..4f5ca5643cb1
--- /dev/null
+++ b/arch/ia64/include/asm/signal.h
@@ -0,0 +1,160 @@
+#ifndef _ASM_IA64_SIGNAL_H
+#define _ASM_IA64_SIGNAL_H
+
+/*
+ * Modified 1998-2001, 2003
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ *
+ * Unfortunately, this file is being included by bits/signal.h in
+ * glibc-2.x.  Hence the #ifdef __KERNEL__ ugliness.
+ */
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+/* signal 31 is no longer "unused", but the SIGUNUSED macro remains for backwards compatibility */
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002
+#define SA_SIGINFO      0x00000004
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+/*
+ * The minimum stack size needs to be fairly large because we want to
+ * be sure that an app compiled for today's CPUs will continue to run
+ * on all future CPU models.  The CPU model matters because the signal
+ * frame needs to have space for the complete machine state, including
+ * all physical stacked registers.  The number of physical stacked
+ * registers is CPU model dependent, but given that the width of
+ * ar.rsc.loadrs is 14 bits, we can assume that they'll never take up
+ * more than 16KB of space.
+ */
+#if 1
+  /*
+   * This is a stupid typo: the value was _meant_ to be 131072 (0x20000), but I typed it
+   * in wrong. ;-(  To preserve backwards compatibility, we leave the kernel at the
+   * incorrect value and fix libc only.
+   */
+# define MINSIGSTKSZ    131027  /* min. stack size for sigaltstack() */
+#else
+# define MINSIGSTKSZ    131072  /* min. stack size for sigaltstack() */
+#endif
+#define SIGSTKSZ        262144  /* default stack size for sigaltstack() */
+
+#ifdef __KERNEL__
+
+#define _NSIG           64
+#define _NSIG_BPW       64
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+#endif /* __KERNEL__ */
+
+#include <asm-generic/signal.h>
+
+# ifndef __ASSEMBLY__
+
+#  include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+typedef unsigned long old_sigset_t;
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+#  include <asm/sigcontext.h>
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
+# endif /* !__ASSEMBLY__ */
+#endif /* _ASM_IA64_SIGNAL_H */
diff --git a/arch/ia64/include/asm/smp.h b/arch/ia64/include/asm/smp.h
new file mode 100644
index 000000000000..12d96e0cd513
--- /dev/null
+++ b/arch/ia64/include/asm/smp.h
@@ -0,0 +1,138 @@
+/*
+ * SMP Support
+ *
+ * Copyright (C) 1999 VA Linux Systems
+ * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ * (c) Copyright 2001-2003, 2005 Hewlett-Packard Development Company, L.P.
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *      Bjorn Helgaas <bjorn.helgaas@hp.com>
+ */
+#ifndef _ASM_IA64_SMP_H
+#define _ASM_IA64_SMP_H
+
+#include <linux/init.h>
+#include <linux/threads.h>
+#include <linux/kernel.h>
+#include <linux/cpumask.h>
+#include <linux/bitops.h>
+#include <linux/irqreturn.h>
+
+#include <asm/io.h>
+#include <asm/param.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+
+static inline unsigned int
+ia64_get_lid (void)
+{
+        union {
+                struct {
+                        unsigned long reserved : 16;
+                        unsigned long eid : 8;
+                        unsigned long id : 8;
+                        unsigned long ignored : 32;
+                } f;
+                unsigned long bits;
+        } lid;
+
+        lid.bits = ia64_getreg(_IA64_REG_CR_LID);
+        return lid.f.id << 8 | lid.f.eid;
+}
+
+#define hard_smp_processor_id()         ia64_get_lid()
+
+#ifdef CONFIG_SMP
+
+#define XTP_OFFSET              0x1e0008
+
+#define SMP_IRQ_REDIRECTION     (1 << 0)
+#define SMP_IPI_REDIRECTION     (1 << 1)
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+extern struct smp_boot_data {
+        int cpu_count;
+        int cpu_phys_id[NR_CPUS];
+} smp_boot_data __initdata;
+
+extern char no_int_routing __devinitdata;
+
+extern cpumask_t cpu_online_map;
+extern cpumask_t cpu_core_map[NR_CPUS];
+DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
+extern int smp_num_siblings;
+extern void __iomem *ipi_base_addr;
+extern unsigned char smp_int_redirect;
+
+extern volatile int ia64_cpu_to_sapicid[];
+#define cpu_physical_id(i)      ia64_cpu_to_sapicid[i]
+
+extern unsigned long ap_wakeup_vector;
+
+/*
+ * Function to map hard smp processor id to logical id.  Slow, so don't use this in
+ * performance-critical code.
+ */
+static inline int
+cpu_logical_id (int cpuid)
+{
+        int i;
+
+        for (i = 0; i < NR_CPUS; ++i)
+                if (cpu_physical_id(i) == cpuid)
+                        break;
+        return i;
+}
+
+/*
+ * XTP control functions:
+ *      min_xtp   : route all interrupts to this CPU
+ *      normal_xtp: nominal XTP value
+ *      max_xtp   : never deliver interrupts to this CPU.
+ */
+
+static inline void
+min_xtp (void)
+{
+        if (smp_int_redirect & SMP_IRQ_REDIRECTION)
+                writeb(0x00, ipi_base_addr + XTP_OFFSET); /* XTP to min */
+}
+
+static inline void
+normal_xtp (void)
+{
+        if (smp_int_redirect & SMP_IRQ_REDIRECTION)
+                writeb(0x08, ipi_base_addr + XTP_OFFSET); /* XTP normal */
+}
+
+static inline void
+max_xtp (void)
+{
+        if (smp_int_redirect & SMP_IRQ_REDIRECTION)
+                writeb(0x0f, ipi_base_addr + XTP_OFFSET); /* Set XTP to max */
+}
+
+/* Upping and downing of CPUs */
+extern int __cpu_disable (void);
+extern void __cpu_die (unsigned int cpu);
+extern void cpu_die (void) __attribute__ ((noreturn));
+extern void __init smp_build_cpu_map(void);
+
+extern void __init init_smp_config (void);
+extern void smp_do_timer (struct pt_regs *regs);
+
+extern irqreturn_t handle_IPI(int irq, void *dev_id);
+extern void smp_send_reschedule (int cpu);
+extern void identify_siblings (struct cpuinfo_ia64 *);
+extern int is_multithreading_enabled(void);
+
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
+#else /* CONFIG_SMP */
+
+#define cpu_logical_id(i)               0
+#define cpu_physical_id(i)              ia64_get_lid()
+
+#endif /* CONFIG_SMP */
+#endif /* _ASM_IA64_SMP_H */
diff --git a/arch/ia64/include/asm/sn/acpi.h b/arch/ia64/include/asm/sn/acpi.h
new file mode 100644
index 000000000000..9ce2801cbd57
--- /dev/null
+++ b/arch/ia64/include/asm/sn/acpi.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_ACPI_H
+#define _ASM_IA64_SN_ACPI_H
+
+#include "acpi/acglobal.h"
+
+extern int sn_acpi_rev;
+#define SN_ACPI_BASE_SUPPORT()   (sn_acpi_rev >= 0x20101)
+
+#endif /* _ASM_IA64_SN_ACPI_H */
diff --git a/arch/ia64/include/asm/sn/addrs.h b/arch/ia64/include/asm/sn/addrs.h
new file mode 100644
index 000000000000..e715c794b186
--- /dev/null
+++ b/arch/ia64/include/asm/sn/addrs.h
@@ -0,0 +1,299 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_ADDRS_H
+#define _ASM_IA64_SN_ADDRS_H
+
+#include <asm/percpu.h>
+#include <asm/sn/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/pda.h>
+
+/*
+ *  Memory/SHUB Address Format:
+ *  +-+---------+--+--------------+
+ *  |0|  NASID  |AS| NodeOffset   |
+ *  +-+---------+--+--------------+
+ *
+ *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
+ *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
+ *     00: Local Resources and MMR space
+ *           Top bit of NodeOffset
+ *               0: Local resources space
+ *                  node id:
+ *                        0: IA64/NT compatibility space
+ *                        2: Local MMR Space
+ *                        4: Local memory, regardless of local node id
+ *               1: Global MMR space
+ *     01: GET space.
+ *     10: AMO space.
+ *     11: Cacheable memory space.
+ *
+ *   NodeOffset: byte offset
+ *
+ *
+ *  TIO address format:
+ *  +-+----------+--+--------------+
+ *  |0|  NASID   |AS| Nodeoffset   |
+ *  +-+----------+--+--------------+
+ *
+ *  NASID: (low NASID bit is 1) TIO
+ *   AS: 2-bit Chiplet Identifier
+ *     00: TIO LB (Indicates TIO MMR access.)
+ *     01: TIO ICE (indicates coretalk space access.)
+ * 
+ *   NodeOffset: top bit must be set.
+ *
+ *
+ * Note that in both of the above address formats, the low
+ * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
+ */
+
+
+/*
+ * Define basic shift & mask constants for manipulating NASIDs and AS values.
+ */
+#define NASID_BITMASK           (sn_hub_info->nasid_bitmask)
+#define NASID_SHIFT             (sn_hub_info->nasid_shift)
+#define AS_SHIFT                (sn_hub_info->as_shift)
+#define AS_BITMASK              0x3UL
+
+#define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
+#define AS_MASK                 ((u64)AS_BITMASK << AS_SHIFT)
+
+
+/*
+ * AS values. These are the same on both SHUB1 & SHUB2.
+ */
+#define AS_GET_VAL              1UL
+#define AS_AMO_VAL              2UL
+#define AS_CAC_VAL              3UL
+#define AS_GET_SPACE            (AS_GET_VAL << AS_SHIFT)
+#define AS_AMO_SPACE            (AS_AMO_VAL << AS_SHIFT)
+#define AS_CAC_SPACE            (AS_CAC_VAL << AS_SHIFT)
+
+
+/* 
+ * Virtual Mode Local & Global MMR space.  
+ */
+#define SH1_LOCAL_MMR_OFFSET    0x8000000000UL
+#define SH2_LOCAL_MMR_OFFSET    0x0200000000UL
+#define LOCAL_MMR_OFFSET        (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
+#define LOCAL_MMR_SPACE         (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
+#define LOCAL_PHYS_MMR_SPACE    (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
+
+#define SH1_GLOBAL_MMR_OFFSET   0x0800000000UL
+#define SH2_GLOBAL_MMR_OFFSET   0x0300000000UL
+#define GLOBAL_MMR_OFFSET       (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
+#define GLOBAL_MMR_SPACE        (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
+
+/*
+ * Physical mode addresses
+ */
+#define GLOBAL_PHYS_MMR_SPACE   (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
+
+
+/*
+ * Clear region & AS bits.
+ */
+#define TO_PHYS_MASK            (~(RGN_BITS | AS_MASK))
+
+
+/*
+ * Misc NASID manipulation.
+ */
+#define NASID_SPACE(n)          ((u64)(n) << NASID_SHIFT)
+#define REMOTE_ADDR(n,a)        (NASID_SPACE(n) | (a))
+#define NODE_OFFSET(x)          ((x) & (NODE_ADDRSPACE_SIZE - 1))
+#define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
+#define NASID_GET(x)            (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
+#define LOCAL_MMR_ADDR(a)       (LOCAL_MMR_SPACE | (a))
+#define GLOBAL_MMR_ADDR(n,a)    (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_CAC_ADDR(n,a)    (CAC_BASE | REMOTE_ADDR(n,a))
+#define CHANGE_NASID(n,x)       ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
+#define IS_TIO_NASID(n)         ((n) & 1)
+
+
+/* non-II mmr's start at top of big window space (4G) */
+#define BWIN_TOP                0x0000000100000000UL
+
+/*
+ * general address defines
+ */
+#define CAC_BASE                (PAGE_OFFSET | AS_CAC_SPACE)
+#define AMO_BASE                (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
+#define AMO_PHYS_BASE           (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
+#define GET_BASE                (PAGE_OFFSET | AS_GET_SPACE)
+
+/*
+ * Convert Memory addresses between various addressing modes.
+ */
+#define TO_PHYS(x)              (TO_PHYS_MASK & (x))
+#define TO_CAC(x)               (CAC_BASE     | TO_PHYS(x))
+#ifdef CONFIG_SGI_SN
+#define TO_AMO(x)               (AMO_BASE     | TO_PHYS(x))
+#define TO_GET(x)               (GET_BASE     | TO_PHYS(x))
+#else
+#define TO_AMO(x)               ({ BUG(); x; })
+#define TO_GET(x)               ({ BUG(); x; })
+#endif
+
+/*
+ * Covert from processor physical address to II/TIO physical address:
+ *      II - squeeze out the AS bits
+ *      TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
+ *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
+ *           to insert a chiplet id into this macro.  However, it is our belief
+ *           right now that this chiplet id will be ICE, which is also zero.
+ */
+#define SH1_TIO_PHYS_TO_DMA(x)                                          \
+        ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
+
+#define SH2_NETWORK_BANK_OFFSET(x)                                      \
+        ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
+
+#define SH2_NETWORK_BANK_SELECT(x)                                      \
+        ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4)))        \
+                >> (sn_hub_info->nasid_shift - 4)) << 36)
+
+#define SH2_NETWORK_ADDRESS(x)                                          \
+        (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
+
+#define SH2_TIO_PHYS_TO_DMA(x)                                          \
+        (((u64)(NASID_GET(x)) << 40) |  SH2_NETWORK_ADDRESS(x))
+
+#define PHYS_TO_TIODMA(x)                                               \
+        (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
+
+#define PHYS_TO_DMA(x)                                                  \
+        ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
+
+
+/*
+ * Macros to test for address type.
+ */
+#define IS_AMO_ADDRESS(x)       (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
+#define IS_AMO_PHYS_ADDRESS(x)  (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
+
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+#define BWIN_SIZE_BITS                  29      /* big window size: 512M */
+#define TIO_BWIN_SIZE_BITS              30      /* big window size: 1G */
+#define NODE_SWIN_BASE(n, w)            ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
+                : RAW_NODE_SWIN_BASE(n, w))
+#define TIO_SWIN_BASE(n, w)             (TIO_IO_BASE(n) + \
+                                            ((u64) (w) << TIO_SWIN_SIZE_BITS))
+#define NODE_IO_BASE(n)                 (GLOBAL_MMR_SPACE | NASID_SPACE(n))
+#define TIO_IO_BASE(n)                  (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
+#define BWIN_SIZE                       (1UL << BWIN_SIZE_BITS)
+#define NODE_BWIN_BASE0(n)              (NODE_IO_BASE(n) + BWIN_SIZE)
+#define NODE_BWIN_BASE(n, w)            (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
+#define RAW_NODE_SWIN_BASE(n, w)        (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
+#define BWIN_WIDGET_MASK                0x7
+#define BWIN_WINDOWNUM(x)               (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+#define SH1_IS_BIG_WINDOW_ADDR(x)       ((x) & BWIN_TOP)
+
+#define TIO_BWIN_WINDOW_SELECT_MASK     0x7
+#define TIO_BWIN_WINDOWNUM(x)           (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
+
+#define TIO_HWIN_SHIFT_BITS             33
+#define TIO_HWIN(x)                     (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define SWIN_SIZE_BITS                  24
+#define SWIN_WIDGET_MASK                0xF
+
+#define TIO_SWIN_SIZE_BITS              28
+#define TIO_SWIN_SIZE                   (1UL << TIO_SWIN_SIZE_BITS)
+#define TIO_SWIN_WIDGET_MASK            0x3
+
+/*
+ * Convert smallwindow address to xtalk address.
+ *
+ * 'addr' can be physical or virtual address, but will be converted
+ * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
+ */
+#define SWIN_WIDGETNUM(x)               (((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+#define TIO_SWIN_WIDGETNUM(x)           (((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
+
+
+/*
+ * The following macros produce the correct base virtual address for
+ * the hub registers. The REMOTE_HUB_* macro produce
+ * the address for the specified hub's registers.  The intent is
+ * that the appropriate PI, MD, NI, or II register would be substituted
+ * for x.
+ *
+ *   WARNING:
+ *      When certain Hub chip workaround are defined, it's not sufficient
+ *      to dereference the *_HUB_ADDR() macros.  You should instead use
+ *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
+ *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
+ *      They're always safe.
+ */
+/* Shub1 TIO & MMR addressing macros */
+#define SH1_TIO_IOSPACE_ADDR(n,x)                                       \
+        GLOBAL_MMR_ADDR(n,x)
+
+#define SH1_REMOTE_BWIN_MMR(n,x)                                        \
+        GLOBAL_MMR_ADDR(n,x)
+
+#define SH1_REMOTE_SWIN_MMR(n,x)                                        \
+        (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
+
+#define SH1_REMOTE_MMR(n,x)                                             \
+        (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) :         \
+                SH1_REMOTE_SWIN_MMR(n,x))
+
+/* Shub1 TIO & MMR addressing macros */
+#define SH2_TIO_IOSPACE_ADDR(n,x)                                       \
+        ((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
+
+#define SH2_REMOTE_MMR(n,x)                                             \
+        GLOBAL_MMR_ADDR(n,x)
+
+
+/* TIO & MMR addressing macros that work on both shub1 & shub2 */
+#define TIO_IOSPACE_ADDR(n,x)                                           \
+        ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) :               \
+                 SH2_TIO_IOSPACE_ADDR(n,x)))
+
+#define SH_REMOTE_MMR(n,x)                                              \
+        (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
+
+#define REMOTE_HUB_ADDR(n,x)                                            \
+        (IS_TIO_NASID(n) ?  ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) :    \
+         ((volatile u64*)SH_REMOTE_MMR(n,x)))
+
+
+#define HUB_L(x)                        (*((volatile typeof(*x) *)x))
+#define HUB_S(x,d)                      (*((volatile typeof(*x) *)x) = (d))
+
+#define REMOTE_HUB_L(n, a)              HUB_L(REMOTE_HUB_ADDR((n), (a)))
+#define REMOTE_HUB_S(n, a, d)           HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
+
+/*
+ * Coretalk address breakdown
+ */
+#define CTALK_NASID_SHFT                40
+#define CTALK_NASID_MASK                (0x3FFFULL << CTALK_NASID_SHFT)
+#define CTALK_CID_SHFT                  38
+#define CTALK_CID_MASK                  (0x3ULL << CTALK_CID_SHFT)
+#define CTALK_NODE_OFFSET               0x3FFFFFFFFF
+
+#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/arch/ia64/include/asm/sn/arch.h b/arch/ia64/include/asm/sn/arch.h
new file mode 100644
index 000000000000..7caa1f44cd95
--- /dev/null
+++ b/arch/ia64/include/asm/sn/arch.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI specific setup.
+ *
+ * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc.  All rights reserved.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_IA64_SN_ARCH_H
+#define _ASM_IA64_SN_ARCH_H
+
+#include <linux/numa.h>
+#include <asm/types.h>
+#include <asm/percpu.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sn_cpuid.h>
+
+/*
+ * This is the maximum number of NUMALINK nodes that can be part of a single
+ * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
+ * remote partitions are NOT included in this number.
+ * The number of compact nodes cannot exceed size of a coherency domain.
+ * The purpose of this define is to specify a node count that includes
+ * all C/M/TIO nodes in an SSI system.
+ *
+ * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
+ *
+ *      Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
+ *      to ACPI3.0, this limit will be removed. The notion of "compact nodes"
+ *      should be deleted and TIOs should be included in MAX_NUMNODES.
+ */
+#define MAX_TIO_NODES           MAX_NUMNODES
+#define MAX_COMPACT_NODES       (MAX_NUMNODES + MAX_TIO_NODES)
+
+/*
+ * Maximum number of nodes in all partitions and in all coherency domains.
+ * This is the total number of nodes accessible in the numalink fabric. It
+ * includes all C & M bricks, plus all TIOs.
+ *
+ * This value is also the value of the maximum number of NASIDs in the numalink
+ * fabric.
+ */
+#define MAX_NUMALINK_NODES      16384
+
+/*
+ * The following defines attributes of the HUB chip. These attributes are
+ * frequently referenced. They are kept in the per-cpu data areas of each cpu.
+ * They are kept together in a struct to minimize cache misses.
+ */
+struct sn_hub_info_s {
+        u8 shub2;
+        u8 nasid_shift;
+        u8 as_shift;
+        u8 shub_1_1_found;
+        u16 nasid_bitmask;
+};
+DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
+#define sn_hub_info     (&__get_cpu_var(__sn_hub_info))
+#define is_shub2()      (sn_hub_info->shub2)
+#define is_shub1()      (sn_hub_info->shub2 == 0)
+
+/*
+ * Use this macro to test if shub 1.1 wars should be enabled
+ */
+#define enable_shub_wars_1_1()  (sn_hub_info->shub_1_1_found)
+
+
+/*
+ * Compact node ID to nasid mappings kept in the per-cpu data areas of each
+ * cpu.
+ */
+DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
+#define sn_cnodeid_to_nasid     (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
+
+
+extern u8 sn_partition_id;
+extern u8 sn_system_size;
+extern u8 sn_sharing_domain_size;
+extern u8 sn_region_size;
+
+extern void sn_flush_all_caches(long addr, long bytes);
+extern bool sn_cpu_disable_allowed(int cpu);
+
+#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h
new file mode 100644
index 000000000000..a0d214f43115
--- /dev/null
+++ b/arch/ia64/include/asm/sn/bte.h
@@ -0,0 +1,233 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2007 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_BTE_H
+#define _ASM_IA64_SN_BTE_H
+
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/cache.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/types.h>
+#include <asm/sn/shub_mmr.h>
+
+#define IBCT_NOTIFY             (0x1UL << 4)
+#define IBCT_ZFIL_MODE          (0x1UL << 0)
+
+/* #define BTE_DEBUG */
+/* #define BTE_DEBUG_VERBOSE */
+
+#ifdef BTE_DEBUG
+#  define BTE_PRINTK(x) printk x        /* Terse */
+#  ifdef BTE_DEBUG_VERBOSE
+#    define BTE_PRINTKV(x) printk x     /* Verbose */
+#  else
+#    define BTE_PRINTKV(x)
+#  endif /* BTE_DEBUG_VERBOSE */
+#else
+#  define BTE_PRINTK(x)
+#  define BTE_PRINTKV(x)
+#endif  /* BTE_DEBUG */
+
+
+/* BTE status register only supports 16 bits for length field */
+#define BTE_LEN_BITS (16)
+#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
+#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES)
+
+
+/* Define hardware */
+#define BTES_PER_NODE (is_shub2() ? 4 : 2)
+#define MAX_BTES_PER_NODE 4
+
+#define BTE2OFF_CTRL    0
+#define BTE2OFF_SRC     (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
+#define BTE2OFF_DEST    (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
+#define BTE2OFF_NOTIFY  (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
+
+#define BTE_BASE_ADDR(interface)                                \
+    (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 :         \
+                  (interface == 1) ? SH2_BT_ENG_CSR_1 :         \
+                  (interface == 2) ? SH2_BT_ENG_CSR_2 :         \
+                                     SH2_BT_ENG_CSR_3           \
+                : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
+
+#define BTE_SOURCE_ADDR(base)                                   \
+    (is_shub2() ? base + (BTE2OFF_SRC/8)                        \
+                : base + (BTEOFF_SRC/8))
+
+#define BTE_DEST_ADDR(base)                                     \
+    (is_shub2() ? base + (BTE2OFF_DEST/8)                       \
+                : base + (BTEOFF_DEST/8))
+
+#define BTE_CTRL_ADDR(base)                                     \
+    (is_shub2() ? base + (BTE2OFF_CTRL/8)                       \
+                : base + (BTEOFF_CTRL/8))
+
+#define BTE_NOTIF_ADDR(base)                                    \
+    (is_shub2() ? base + (BTE2OFF_NOTIFY/8)                     \
+                : base + (BTEOFF_NOTIFY/8))
+
+/* Define hardware modes */
+#define BTE_NOTIFY IBCT_NOTIFY
+#define BTE_NORMAL BTE_NOTIFY
+#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
+/* Use a reserved bit to let the caller specify a wait for any BTE */
+#define BTE_WACQUIRE 0x4000
+/* Use the BTE on the node with the destination memory */
+#define BTE_USE_DEST (BTE_WACQUIRE << 1)
+/* Use any available BTE interface on any node for the transfer */
+#define BTE_USE_ANY (BTE_USE_DEST << 1)
+/* macro to force the IBCT0 value valid */
+#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
+
+#define BTE_ACTIVE              (IBLS_BUSY | IBLS_ERROR)
+#define BTE_WORD_AVAILABLE      (IBLS_BUSY << 1)
+#define BTE_WORD_BUSY           (~BTE_WORD_AVAILABLE)
+
+/*
+ * Some macros to simplify reading.
+ * Start with macros to locate the BTE control registers.
+ */
+#define BTE_LNSTAT_LOAD(_bte)                                           \
+                        HUB_L(_bte->bte_base_addr)
+#define BTE_LNSTAT_STORE(_bte, _x)                                      \
+                        HUB_S(_bte->bte_base_addr, (_x))
+#define BTE_SRC_STORE(_bte, _x)                                         \
+({                                                                      \
+                u64 __addr = ((_x) & ~AS_MASK);                         \
+                if (is_shub2())                                         \
+                        __addr = SH2_TIO_PHYS_TO_DMA(__addr);           \
+                HUB_S(_bte->bte_source_addr, __addr);                   \
+})
+#define BTE_DEST_STORE(_bte, _x)                                        \
+({                                                                      \
+                u64 __addr = ((_x) & ~AS_MASK);                         \
+                if (is_shub2())                                         \
+                        __addr = SH2_TIO_PHYS_TO_DMA(__addr);           \
+                HUB_S(_bte->bte_destination_addr, __addr);              \
+})
+#define BTE_CTRL_STORE(_bte, _x)                                        \
+                        HUB_S(_bte->bte_control_addr, (_x))
+#define BTE_NOTIF_STORE(_bte, _x)                                       \
+({                                                                      \
+                u64 __addr = ia64_tpa((_x) & ~AS_MASK);                 \
+                if (is_shub2())                                         \
+                        __addr = SH2_TIO_PHYS_TO_DMA(__addr);           \
+                HUB_S(_bte->bte_notify_addr, __addr);                   \
+})
+
+#define BTE_START_TRANSFER(_bte, _len, _mode)                           \
+        is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
+                : BTE_LNSTAT_STORE(_bte, _len);                         \
+                  BTE_CTRL_STORE(_bte, _mode)
+
+/* Possible results from bte_copy and bte_unaligned_copy */
+/* The following error codes map into the BTE hardware codes
+ * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
+ * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
+ * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
+ * codes to give the following error codes.
+ */
+#define BTEFAIL_OFFSET  1
+
+typedef enum {
+        BTE_SUCCESS,            /* 0 is success */
+        BTEFAIL_DIR,            /* Directory error due to IIO access*/
+        BTEFAIL_POISON,         /* poison error on IO access (write to poison page) */
+        BTEFAIL_WERR,           /* Write error (ie WINV to a Read only line) */
+        BTEFAIL_ACCESS,         /* access error (protection violation) */
+        BTEFAIL_PWERR,          /* Partial Write Error */
+        BTEFAIL_PRERR,          /* Partial Read Error */
+        BTEFAIL_TOUT,           /* CRB Time out */
+        BTEFAIL_XTERR,          /* Incoming xtalk pkt had error bit */
+        BTEFAIL_NOTAVAIL,       /* BTE not available */
+} bte_result_t;
+
+#define BTEFAIL_SH2_RESP_SHORT  0x1     /* bit 000001 */
+#define BTEFAIL_SH2_RESP_LONG   0x2     /* bit 000010 */
+#define BTEFAIL_SH2_RESP_DSP    0x4     /* bit 000100 */
+#define BTEFAIL_SH2_RESP_ACCESS 0x8     /* bit 001000 */
+#define BTEFAIL_SH2_CRB_TO      0x10    /* bit 010000 */
+#define BTEFAIL_SH2_NACK_LIMIT  0x20    /* bit 100000 */
+#define BTEFAIL_SH2_ALL         0x3F    /* bit 111111 */
+
+#define BTE_ERR_BITS    0x3FUL
+#define BTE_ERR_SHIFT   36
+#define BTE_ERR_MASK    (BTE_ERR_BITS << BTE_ERR_SHIFT)
+
+#define BTE_ERROR_RETRY(value)                                          \
+        (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO)                     \
+                : (value != BTEFAIL_TOUT))
+
+/*
+ * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
+ */
+#define BTE_SHUB2_ERROR(_status)                                        \
+        ((_status & BTE_ERR_MASK)                                       \
+           ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
+           : _status)
+
+#define BTE_GET_ERROR_STATUS(_status)                                   \
+        (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
+
+#define BTE_VALID_SH2_ERROR(value)                                      \
+        ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
+
+/*
+ * Structure defining a bte.  An instance of this
+ * structure is created in the nodepda for each
+ * bte on that node (as defined by BTES_PER_NODE)
+ * This structure contains everything necessary
+ * to work with a BTE.
+ */
+struct bteinfo_s {
+        volatile u64 notify ____cacheline_aligned;
+        u64 *bte_base_addr ____cacheline_aligned;
+        u64 *bte_source_addr;
+        u64 *bte_destination_addr;
+        u64 *bte_control_addr;
+        u64 *bte_notify_addr;
+        spinlock_t spinlock;
+        cnodeid_t bte_cnode;    /* cnode                            */
+        int bte_error_count;    /* Number of errors encountered     */
+        int bte_num;            /* 0 --> BTE0, 1 --> BTE1           */
+        int cleanup_active;     /* Interface is locked for cleanup  */
+        volatile bte_result_t bh_error; /* error while processing   */
+        volatile u64 *most_rcnt_na;
+        struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
+};
+
+
+/*
+ * Function prototypes (functions defined in bte.c, used elsewhere)
+ */
+extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
+extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
+extern void bte_error_handler(unsigned long);
+
+#define bte_zero(dest, len, mode, notification) \
+        bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
+
+/*
+ * The following is the prefered way of calling bte_unaligned_copy
+ * If the copy is fully cache line aligned, then bte_copy is
+ * used instead.  Since bte_copy is inlined, this saves a call
+ * stack.  NOTE: bte_copy is called synchronously and does block
+ * until the transfer is complete.  In order to get the asynch
+ * version of bte_copy, you must perform this check yourself.
+ */
+#define BTE_UNALIGNED_COPY(src, dest, len, mode)                        \
+        (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) ||             \
+          (dest & L1_CACHE_MASK)) ?                                     \
+         bte_unaligned_copy(src, dest, len, mode) :                     \
+         bte_copy(src, dest, len, mode, NULL))
+
+
+#endif  /* _ASM_IA64_SN_BTE_H */
diff --git a/arch/ia64/include/asm/sn/clksupport.h b/arch/ia64/include/asm/sn/clksupport.h
new file mode 100644
index 000000000000..d340c365a824
--- /dev/null
+++ b/arch/ia64/include/asm/sn/clksupport.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * This file contains definitions for accessing a platform supported high resolution
+ * clock. The clock is monitonically increasing and can be accessed from any node
+ * in the system. The clock is synchronized across nodes - all nodes see the
+ * same value.
+ * 
+ *      RTC_COUNTER_ADDR - contains the address of the counter 
+ *
+ */
+
+#ifndef _ASM_IA64_SN_CLKSUPPORT_H
+#define _ASM_IA64_SN_CLKSUPPORT_H
+
+extern unsigned long sn_rtc_cycles_per_second;
+
+#define RTC_COUNTER_ADDR        ((long *)LOCAL_MMR_ADDR(SH_RTC))
+
+#define rtc_time()              (*RTC_COUNTER_ADDR)
+
+#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff --git a/arch/ia64/include/asm/sn/geo.h b/arch/ia64/include/asm/sn/geo.h
new file mode 100644
index 000000000000..f083c9434066
--- /dev/null
+++ b/arch/ia64/include/asm/sn/geo.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_GEO_H
+#define _ASM_IA64_SN_GEO_H
+
+/* The geoid_t implementation below is based loosely on the pcfg_t
+   implementation in sys/SN/promcfg.h. */
+
+/* Type declaractions */
+
+/* Size of a geoid_t structure (must be before decl. of geoid_u) */
+#define GEOID_SIZE      8       /* Would 16 be better?  The size can
+                                   be different on different platforms. */
+
+#define MAX_SLOTS       0xf     /* slots per module */
+#define MAX_SLABS       0xf     /* slabs per slot */
+
+typedef unsigned char   geo_type_t;
+
+/* Fields common to all substructures */
+typedef struct geo_common_s {
+    moduleid_t  module;         /* The module (box) this h/w lives in */
+    geo_type_t  type;           /* What type of h/w is named by this geoid_t */
+    slabid_t    slab:4;         /* slab (ASIC), 0 .. 15 within slot */
+    slotid_t    slot:4;         /* slot (Blade), 0 .. 15 within module */
+} geo_common_t;
+
+/* Additional fields for particular types of hardware */
+typedef struct geo_node_s {
+    geo_common_t        common;         /* No additional fields needed */
+} geo_node_t;
+
+typedef struct geo_rtr_s {
+    geo_common_t        common;         /* No additional fields needed */
+} geo_rtr_t;
+
+typedef struct geo_iocntl_s {
+    geo_common_t        common;         /* No additional fields needed */
+} geo_iocntl_t;
+
+typedef struct geo_pcicard_s {
+    geo_iocntl_t        common;
+    char                bus;    /* Bus/widget number */
+    char                slot;   /* PCI slot number */
+} geo_pcicard_t;
+
+/* Subcomponents of a node */
+typedef struct geo_cpu_s {
+    geo_node_t  node;
+    char        slice;          /* Which CPU on the node */
+} geo_cpu_t;
+
+typedef struct geo_mem_s {
+    geo_node_t  node;
+    char        membus;         /* The memory bus on the node */
+    char        memslot;        /* The memory slot on the bus */
+} geo_mem_t;
+
+
+typedef union geoid_u {
+    geo_common_t        common;
+    geo_node_t          node;
+    geo_iocntl_t        iocntl;
+    geo_pcicard_t       pcicard;
+    geo_rtr_t           rtr;
+    geo_cpu_t           cpu;
+    geo_mem_t           mem;
+    char                padsize[GEOID_SIZE];
+} geoid_t;
+
+
+/* Preprocessor macros */
+
+#define GEO_MAX_LEN     48      /* max. formatted length, plus some pad:
+                                   module/001c07/slab/5/node/memory/2/slot/4 */
+
+/* Values for geo_type_t */
+#define GEO_TYPE_INVALID        0
+#define GEO_TYPE_MODULE         1
+#define GEO_TYPE_NODE           2
+#define GEO_TYPE_RTR            3
+#define GEO_TYPE_IOCNTL         4
+#define GEO_TYPE_IOCARD         5
+#define GEO_TYPE_CPU            6
+#define GEO_TYPE_MEM            7
+#define GEO_TYPE_MAX            (GEO_TYPE_MEM+1)
+
+/* Parameter for hwcfg_format_geoid_compt() */
+#define GEO_COMPT_MODULE        1
+#define GEO_COMPT_SLAB          2
+#define GEO_COMPT_IOBUS         3
+#define GEO_COMPT_IOSLOT        4
+#define GEO_COMPT_CPU           5
+#define GEO_COMPT_MEMBUS        6
+#define GEO_COMPT_MEMSLOT       7
+
+#define GEO_INVALID_STR         "<invalid>"
+
+#define INVALID_NASID           ((nasid_t)-1)
+#define INVALID_CNODEID         ((cnodeid_t)-1)
+#define INVALID_PNODEID         ((pnodeid_t)-1)
+#define INVALID_SLAB            (slabid_t)-1
+#define INVALID_SLOT            (slotid_t)-1
+#define INVALID_MODULE          ((moduleid_t)-1)
+
+static inline slabid_t geo_slab(geoid_t g)
+{
+        return (g.common.type == GEO_TYPE_INVALID) ?
+                INVALID_SLAB : g.common.slab;
+}
+
+static inline slotid_t geo_slot(geoid_t g)
+{
+        return (g.common.type == GEO_TYPE_INVALID) ?
+                INVALID_SLOT : g.common.slot;
+}
+
+static inline moduleid_t geo_module(geoid_t g)
+{
+        return (g.common.type == GEO_TYPE_INVALID) ?
+                INVALID_MODULE : g.common.module;
+}
+
+extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
+
+#endif /* _ASM_IA64_SN_GEO_H */
diff --git a/arch/ia64/include/asm/sn/intr.h b/arch/ia64/include/asm/sn/intr.h
new file mode 100644
index 000000000000..e0487aa97418
--- /dev/null
+++ b/arch/ia64/include/asm/sn/intr.h
@@ -0,0 +1,68 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_INTR_H
+#define _ASM_IA64_SN_INTR_H
+
+#include <linux/rcupdate.h>
+#include <asm/sn/types.h>
+
+#define SGI_UART_VECTOR         0xe9
+
+/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
+#define SGI_XPC_ACTIVATE        0x30
+#define SGI_II_ERROR            0x31
+#define SGI_XBOW_ERROR          0x32
+#define SGI_PCIASIC_ERROR       0x33
+#define SGI_ACPI_SCI_INT        0x34
+#define SGI_TIOCA_ERROR         0x35
+#define SGI_TIO_ERROR           0x36
+#define SGI_TIOCX_ERROR         0x37
+#define SGI_MMTIMER_VECTOR      0x38
+#define SGI_XPC_NOTIFY          0xe7
+
+#define IA64_SN2_FIRST_DEVICE_VECTOR    0x3c
+#define IA64_SN2_LAST_DEVICE_VECTOR     0xe6
+
+#define SN2_IRQ_RESERVED        0x1
+#define SN2_IRQ_CONNECTED       0x2
+#define SN2_IRQ_SHARED          0x4
+
+// The SN PROM irq struct
+struct sn_irq_info {
+        struct sn_irq_info *irq_next;   /* deprecated DO NOT USE     */
+        short           irq_nasid;      /* Nasid IRQ is assigned to  */
+        int             irq_slice;      /* slice IRQ is assigned to  */
+        int             irq_cpuid;      /* kernel logical cpuid      */
+        int             irq_irq;        /* the IRQ number */
+        int             irq_int_bit;    /* Bridge interrupt pin */
+                                        /* <0 means MSI */
+        u64     irq_xtalkaddr;  /* xtalkaddr IRQ is sent to  */
+        int             irq_bridge_type;/* pciio asic type (pciio.h) */
+        void           *irq_bridge;     /* bridge generating irq     */
+        void           *irq_pciioinfo;  /* associated pciio_info_t   */
+        int             irq_last_intr;  /* For Shub lb lost intr WAR */
+        int             irq_cookie;     /* unique cookie             */
+        int             irq_flags;      /* flags */
+        int             irq_share_cnt;  /* num devices sharing IRQ   */
+        struct list_head        list;   /* list of sn_irq_info structs */
+        struct rcu_head         rcu;    /* rcu callback list */
+};
+
+extern void sn_send_IPI_phys(int, long, int, int);
+extern u64 sn_intr_alloc(nasid_t, int,
+                              struct sn_irq_info *,
+                              int, nasid_t, int);
+extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
+extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
+extern void sn_set_err_irq_affinity(unsigned int);
+extern struct list_head **sn_irq_lh;
+
+#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
+
+#endif /* _ASM_IA64_SN_INTR_H */
diff --git a/arch/ia64/include/asm/sn/io.h b/arch/ia64/include/asm/sn/io.h
new file mode 100644
index 000000000000..41c73a735628
--- /dev/null
+++ b/arch/ia64/include/asm/sn/io.h
@@ -0,0 +1,274 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_SN_IO_H
+#define _ASM_SN_IO_H
+#include <linux/compiler.h>
+#include <asm/intrinsics.h>
+
+extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
+extern void __sn_mmiowb(void); /* Forward definition */
+
+extern int num_cnodes;
+
+#define __sn_mf_a()   ia64_mfa()
+
+extern void sn_dma_flush(unsigned long);
+
+#define __sn_inb ___sn_inb
+#define __sn_inw ___sn_inw
+#define __sn_inl ___sn_inl
+#define __sn_outb ___sn_outb
+#define __sn_outw ___sn_outw
+#define __sn_outl ___sn_outl
+#define __sn_readb ___sn_readb
+#define __sn_readw ___sn_readw
+#define __sn_readl ___sn_readl
+#define __sn_readq ___sn_readq
+#define __sn_readb_relaxed ___sn_readb_relaxed
+#define __sn_readw_relaxed ___sn_readw_relaxed
+#define __sn_readl_relaxed ___sn_readl_relaxed
+#define __sn_readq_relaxed ___sn_readq_relaxed
+
+/*
+ * Convenience macros for setting/clearing bits using the above accessors
+ */
+
+#define __sn_setq_relaxed(addr, val) \
+        writeq((__sn_readq_relaxed(addr) | (val)), (addr))
+#define __sn_clrq_relaxed(addr, val) \
+        writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
+
+/*
+ * The following routines are SN Platform specific, called when
+ * a reference is made to inX/outX set macros.  SN Platform
+ * inX set of macros ensures that Posted DMA writes on the
+ * Bridge is flushed.
+ *
+ * The routines should be self explainatory.
+ */
+
+static inline unsigned int
+___sn_inb (unsigned long port)
+{
+        volatile unsigned char *addr;
+        unsigned char ret = -1;
+
+        if ((addr = sn_io_addr(port))) {
+                ret = *addr;
+                __sn_mf_a();
+                sn_dma_flush((unsigned long)addr);
+        }
+        return ret;
+}
+
+static inline unsigned int
+___sn_inw (unsigned long port)
+{
+        volatile unsigned short *addr;
+        unsigned short ret = -1;
+
+        if ((addr = sn_io_addr(port))) {
+                ret = *addr;
+                __sn_mf_a();
+                sn_dma_flush((unsigned long)addr);
+        }
+        return ret;
+}
+
+static inline unsigned int
+___sn_inl (unsigned long port)
+{
+        volatile unsigned int *addr;
+        unsigned int ret = -1;
+
+        if ((addr = sn_io_addr(port))) {
+                ret = *addr;
+                __sn_mf_a();
+                sn_dma_flush((unsigned long)addr);
+        }
+        return ret;
+}
+
+static inline void
+___sn_outb (unsigned char val, unsigned long port)
+{
+        volatile unsigned char *addr;
+
+        if ((addr = sn_io_addr(port))) {
+                *addr = val;
+                __sn_mmiowb();
+        }
+}
+
+static inline void
+___sn_outw (unsigned short val, unsigned long port)
+{
+        volatile unsigned short *addr;
+
+        if ((addr = sn_io_addr(port))) {
+                *addr = val;
+                __sn_mmiowb();
+        }
+}
+
+static inline void
+___sn_outl (unsigned int val, unsigned long port)
+{
+        volatile unsigned int *addr;
+
+        if ((addr = sn_io_addr(port))) {
+                *addr = val;
+                __sn_mmiowb();
+        }
+}
+
+/*
+ * The following routines are SN Platform specific, called when 
+ * a reference is made to readX/writeX set macros.  SN Platform 
+ * readX set of macros ensures that Posted DMA writes on the 
+ * Bridge is flushed.
+ * 
+ * The routines should be self explainatory.
+ */
+
+static inline unsigned char
+___sn_readb (const volatile void __iomem *addr)
+{
+        unsigned char val;
+
+        val = *(volatile unsigned char __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+static inline unsigned short
+___sn_readw (const volatile void __iomem *addr)
+{
+        unsigned short val;
+
+        val = *(volatile unsigned short __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+static inline unsigned int
+___sn_readl (const volatile void __iomem *addr)
+{
+        unsigned int val;
+
+        val = *(volatile unsigned int __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+static inline unsigned long
+___sn_readq (const volatile void __iomem *addr)
+{
+        unsigned long val;
+
+        val = *(volatile unsigned long __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+/*
+ * For generic and SN2 kernels, we have a set of fast access
+ * PIO macros.  These macros are provided on SN Platform
+ * because the normal inX and readX macros perform an
+ * additional task of flushing Post DMA request on the Bridge.
+ *
+ * These routines should be self explainatory.
+ */
+
+static inline unsigned int
+sn_inb_fast (unsigned long port)
+{
+        volatile unsigned char *addr = (unsigned char *)port;
+        unsigned char ret;
+
+        ret = *addr;
+        __sn_mf_a();
+        return ret;
+}
+
+static inline unsigned int
+sn_inw_fast (unsigned long port)
+{
+        volatile unsigned short *addr = (unsigned short *)port;
+        unsigned short ret;
+
+        ret = *addr;
+        __sn_mf_a();
+        return ret;
+}
+
+static inline unsigned int
+sn_inl_fast (unsigned long port)
+{
+        volatile unsigned int *addr = (unsigned int *)port;
+        unsigned int ret;
+
+        ret = *addr;
+        __sn_mf_a();
+        return ret;
+}
+
+static inline unsigned char
+___sn_readb_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned char __force *)addr;
+}
+
+static inline unsigned short
+___sn_readw_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned short __force *)addr;
+}
+
+static inline unsigned int
+___sn_readl_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned int __force *) addr;
+}
+
+static inline unsigned long
+___sn_readq_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned long __force *) addr;
+}
+
+struct pci_dev;
+
+static inline int
+sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
+{
+
+        if (vchan > 1) {
+                return -1;
+        }
+
+        if (!(*addr >> 32))     /* Using a mask here would be cleaner */
+                return 0;       /* but this generates better code */
+
+        if (vchan == 1) {
+                /* Set Bit 57 */
+                *addr |= (1UL << 57);
+        } else {
+                /* Clear Bit 57 */
+                *addr &= ~(1UL << 57);
+        }
+
+        return 0;
+}
+
+#endif  /* _ASM_SN_IO_H */
diff --git a/arch/ia64/include/asm/sn/ioc3.h b/arch/ia64/include/asm/sn/ioc3.h
new file mode 100644
index 000000000000..95ed6cc83cf1
--- /dev/null
+++ b/arch/ia64/include/asm/sn/ioc3.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2005 Silicon Graphics, Inc.
+ */
+#ifndef IA64_SN_IOC3_H
+#define IA64_SN_IOC3_H
+
+/* serial port register map */
+struct ioc3_serialregs {
+        uint32_t sscr;
+        uint32_t stpir;
+        uint32_t stcir;
+        uint32_t srpir;
+        uint32_t srcir;
+        uint32_t srtr;
+        uint32_t shadow;
+};
+
+/* SUPERIO uart register map */
+struct ioc3_uartregs {
+        char iu_lcr;
+        union {
+                char iir;       /* read only */
+                char fcr;       /* write only */
+        } u3;
+        union {
+                char ier;       /* DLAB == 0 */
+                char dlm;       /* DLAB == 1 */
+        } u2;
+        union {
+                char rbr;       /* read only, DLAB == 0 */
+                char thr;       /* write only, DLAB == 0 */
+                char dll;       /* DLAB == 1 */
+        } u1;
+        char iu_scr;
+        char iu_msr;
+        char iu_lsr;
+        char iu_mcr;
+};
+
+#define iu_rbr u1.rbr
+#define iu_thr u1.thr
+#define iu_dll u1.dll
+#define iu_ier u2.ier
+#define iu_dlm u2.dlm
+#define iu_iir u3.iir
+#define iu_fcr u3.fcr
+
+struct ioc3_sioregs {
+        char fill[0x170];
+        struct ioc3_uartregs uartb;
+        struct ioc3_uartregs uarta;
+};
+
+/* PCI IO/mem space register map */
+struct ioc3 {
+        uint32_t pci_id;
+        uint32_t pci_scr;
+        uint32_t pci_rev;
+        uint32_t pci_lat;
+        uint32_t pci_addr;
+        uint32_t pci_err_addr_l;
+        uint32_t pci_err_addr_h;
+
+        uint32_t sio_ir;
+        /* these registers are read-only for general kernel code. To
+         * modify them use the functions in ioc3.c
+         */
+        uint32_t sio_ies;
+        uint32_t sio_iec;
+        uint32_t sio_cr;
+        uint32_t int_out;
+        uint32_t mcr;
+        uint32_t gpcr_s;
+        uint32_t gpcr_c;
+        uint32_t gpdr;
+        uint32_t gppr[9];
+        char fill[0x4c];
+
+        /* serial port registers */
+        uint32_t sbbr_h;
+        uint32_t sbbr_l;
+
+        struct ioc3_serialregs port_a;
+        struct ioc3_serialregs port_b;
+        char fill1[0x1ff10];
+        /* superio registers */
+        struct ioc3_sioregs sregs;
+};
+
+/* These don't exist on the ioc3 serial card... */
+#define eier    fill1[8]
+#define eisr    fill1[4]
+
+#define PCI_LAT                 0xc     /* Latency Timer */
+#define PCI_SCR_DROP_MODE_EN    0x00008000 /* drop pios on parity err */
+#define UARTA_BASE              0x178
+#define UARTB_BASE              0x170
+
+
+/* bitmasks for serial RX status byte */
+#define RXSB_OVERRUN            0x01    /* char(s) lost */
+#define RXSB_PAR_ERR            0x02    /* parity error */
+#define RXSB_FRAME_ERR          0x04    /* framing error */
+#define RXSB_BREAK              0x08    /* break character */
+#define RXSB_CTS                0x10    /* state of CTS */
+#define RXSB_DCD                0x20    /* state of DCD */
+#define RXSB_MODEM_VALID        0x40    /* DCD, CTS and OVERRUN are valid */
+#define RXSB_DATA_VALID         0x80    /* FRAME_ERR PAR_ERR & BREAK valid */
+
+/* bitmasks for serial TX control byte */
+#define TXCB_INT_WHEN_DONE      0x20    /* interrupt after this byte is sent */
+#define TXCB_INVALID            0x00    /* byte is invalid */
+#define TXCB_VALID              0x40    /* byte is valid */
+#define TXCB_MCR                0x80    /* data<7:0> to modem cntrl register */
+#define TXCB_DELAY              0xc0    /* delay data<7:0> mSec */
+
+/* bitmasks for SBBR_L */
+#define SBBR_L_SIZE             0x00000001      /* 0 1KB rings, 1 4KB rings */
+
+/* bitmasks for SSCR_<A:B> */
+#define SSCR_RX_THRESHOLD       0x000001ff      /* hiwater mark */
+#define SSCR_TX_TIMER_BUSY      0x00010000      /* TX timer in progress */
+#define SSCR_HFC_EN             0x00020000      /* h/w flow cntrl enabled */
+#define SSCR_RX_RING_DCD        0x00040000      /* postRX record on delta-DCD */
+#define SSCR_RX_RING_CTS        0x00080000      /* postRX record on delta-CTS */
+#define SSCR_HIGH_SPD           0x00100000      /* 4X speed */
+#define SSCR_DIAG               0x00200000      /* bypass clock divider */
+#define SSCR_RX_DRAIN           0x08000000      /* drain RX buffer to memory */
+#define SSCR_DMA_EN             0x10000000      /* enable ring buffer DMA */
+#define SSCR_DMA_PAUSE          0x20000000      /* pause DMA */
+#define SSCR_PAUSE_STATE        0x40000000      /* set when PAUSE takes effect*/
+#define SSCR_RESET              0x80000000      /* reset DMA channels */
+
+/* all producer/comsumer pointers are the same bitfield */
+#define PROD_CONS_PTR_4K        0x00000ff8      /* for 4K buffers */
+#define PROD_CONS_PTR_1K        0x000003f8      /* for 1K buffers */
+#define PROD_CONS_PTR_OFF       3
+
+/* bitmasks for SRCIR_<A:B> */
+#define SRCIR_ARM               0x80000000      /* arm RX timer */
+
+/* bitmasks for SHADOW_<A:B> */
+#define SHADOW_DR               0x00000001      /* data ready */
+#define SHADOW_OE               0x00000002      /* overrun error */
+#define SHADOW_PE               0x00000004      /* parity error */
+#define SHADOW_FE               0x00000008      /* framing error */
+#define SHADOW_BI               0x00000010      /* break interrupt */
+#define SHADOW_THRE             0x00000020      /* transmit holding reg empty */
+#define SHADOW_TEMT             0x00000040      /* transmit shift reg empty */
+#define SHADOW_RFCE             0x00000080      /* char in RX fifo has error */
+#define SHADOW_DCTS             0x00010000      /* delta clear to send */
+#define SHADOW_DDCD             0x00080000      /* delta data carrier detect */
+#define SHADOW_CTS              0x00100000      /* clear to send */
+#define SHADOW_DCD              0x00800000      /* data carrier detect */
+#define SHADOW_DTR              0x01000000      /* data terminal ready */
+#define SHADOW_RTS              0x02000000      /* request to send */
+#define SHADOW_OUT1             0x04000000      /* 16550 OUT1 bit */
+#define SHADOW_OUT2             0x08000000      /* 16550 OUT2 bit */
+#define SHADOW_LOOP             0x10000000      /* loopback enabled */
+
+/* bitmasks for SRTR_<A:B> */
+#define SRTR_CNT                0x00000fff      /* reload value for RX timer */
+#define SRTR_CNT_VAL            0x0fff0000      /* current value of RX timer */
+#define SRTR_CNT_VAL_SHIFT      16
+#define SRTR_HZ                 16000           /* SRTR clock frequency */
+
+/* bitmasks for SIO_IR, SIO_IEC and SIO_IES  */
+#define SIO_IR_SA_TX_MT         0x00000001      /* Serial port A TX empty */
+#define SIO_IR_SA_RX_FULL       0x00000002      /* port A RX buf full */
+#define SIO_IR_SA_RX_HIGH       0x00000004      /* port A RX hiwat */
+#define SIO_IR_SA_RX_TIMER      0x00000008      /* port A RX timeout */
+#define SIO_IR_SA_DELTA_DCD     0x00000010      /* port A delta DCD */
+#define SIO_IR_SA_DELTA_CTS     0x00000020      /* port A delta CTS */
+#define SIO_IR_SA_INT           0x00000040      /* port A pass-thru intr */
+#define SIO_IR_SA_TX_EXPLICIT   0x00000080      /* port A explicit TX thru */
+#define SIO_IR_SA_MEMERR        0x00000100      /* port A PCI error */
+#define SIO_IR_SB_TX_MT         0x00000200
+#define SIO_IR_SB_RX_FULL       0x00000400
+#define SIO_IR_SB_RX_HIGH       0x00000800
+#define SIO_IR_SB_RX_TIMER      0x00001000
+#define SIO_IR_SB_DELTA_DCD     0x00002000
+#define SIO_IR_SB_DELTA_CTS     0x00004000
+#define SIO_IR_SB_INT           0x00008000
+#define SIO_IR_SB_TX_EXPLICIT   0x00010000
+#define SIO_IR_SB_MEMERR        0x00020000
+#define SIO_IR_PP_INT           0x00040000      /* P port pass-thru intr */
+#define SIO_IR_PP_INTA          0x00080000      /* PP context A thru */
+#define SIO_IR_PP_INTB          0x00100000      /* PP context B thru */
+#define SIO_IR_PP_MEMERR        0x00200000      /* PP PCI error */
+#define SIO_IR_KBD_INT          0x00400000      /* kbd/mouse intr */
+#define SIO_IR_RT_INT           0x08000000      /* RT output pulse */
+#define SIO_IR_GEN_INT1         0x10000000      /* RT input pulse */
+#define SIO_IR_GEN_INT_SHIFT    28
+
+/* per device interrupt masks */
+#define SIO_IR_SA               (SIO_IR_SA_TX_MT | \
+                                 SIO_IR_SA_RX_FULL | \
+                                 SIO_IR_SA_RX_HIGH | \
+                                 SIO_IR_SA_RX_TIMER | \
+                                 SIO_IR_SA_DELTA_DCD | \
+                                 SIO_IR_SA_DELTA_CTS | \
+                                 SIO_IR_SA_INT | \
+                                 SIO_IR_SA_TX_EXPLICIT | \
+                                 SIO_IR_SA_MEMERR)
+
+#define SIO_IR_SB               (SIO_IR_SB_TX_MT | \
+                                 SIO_IR_SB_RX_FULL | \
+                                 SIO_IR_SB_RX_HIGH | \
+                                 SIO_IR_SB_RX_TIMER | \
+                                 SIO_IR_SB_DELTA_DCD | \
+                                 SIO_IR_SB_DELTA_CTS | \
+                                 SIO_IR_SB_INT | \
+                                 SIO_IR_SB_TX_EXPLICIT | \
+                                 SIO_IR_SB_MEMERR)
+
+#define SIO_IR_PP               (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
+                                 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
+#define SIO_IR_RT               (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
+
+/* bitmasks for SIO_CR */
+#define SIO_CR_CMD_PULSE_SHIFT 15
+#define SIO_CR_SER_A_BASE_SHIFT 1
+#define SIO_CR_SER_B_BASE_SHIFT 8
+#define SIO_CR_ARB_DIAG         0x00380000      /* cur !enet PCI requet (ro) */
+#define SIO_CR_ARB_DIAG_TXA     0x00000000
+#define SIO_CR_ARB_DIAG_RXA     0x00080000
+#define SIO_CR_ARB_DIAG_TXB     0x00100000
+#define SIO_CR_ARB_DIAG_RXB     0x00180000
+#define SIO_CR_ARB_DIAG_PP      0x00200000
+#define SIO_CR_ARB_DIAG_IDLE    0x00400000      /* 0 -> active request (ro) */
+
+/* defs for some of the generic I/O pins */
+#define GPCR_PHY_RESET          0x20    /* pin is output to PHY reset */
+#define GPCR_UARTB_MODESEL      0x40    /* pin is output to port B mode sel */
+#define GPCR_UARTA_MODESEL      0x80    /* pin is output to port A mode sel */
+
+#define GPPR_PHY_RESET_PIN      5       /* GIO pin controlling phy reset */
+#define GPPR_UARTB_MODESEL_PIN  6       /* GIO pin cntrling uartb modeselect */
+#define GPPR_UARTA_MODESEL_PIN  7       /* GIO pin cntrling uarta modeselect */
+
+#endif /* IA64_SN_IOC3_H */
diff --git a/arch/ia64/include/asm/sn/klconfig.h b/arch/ia64/include/asm/sn/klconfig.h
new file mode 100644
index 000000000000..bcbf209d63be
--- /dev/null
+++ b/arch/ia64/include/asm/sn/klconfig.h
@@ -0,0 +1,246 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/klconfig.h>.
+ *
+ * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_KLCONFIG_H
+#define _ASM_IA64_SN_KLCONFIG_H
+
+/*
+ * The KLCONFIG structures store info about the various BOARDs found
+ * during Hardware Discovery. In addition, it stores info about the
+ * components found on the BOARDs.
+ */
+
+typedef s32 klconf_off_t;
+
+
+/* Functions/macros needed to use this structure */
+
+typedef struct kl_config_hdr {
+        char            pad[20];
+        klconf_off_t    ch_board_info;  /* the link list of boards */
+        char            pad0[88];
+} kl_config_hdr_t;
+
+
+#define NODE_OFFSET_TO_LBOARD(nasid,off)        (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
+
+/*
+ * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
+ * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to 
+ * the LOCAL/current NODE. REMOTE means it is attached to a different
+ * node.(TBD - Need a way to treat ROUTER boards.)
+ *
+ * There are 2 different structures to represent these boards -
+ * lboard - Local board, rboard - remote board. These 2 structures
+ * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
+ * Figure below). The first byte of the rboard or lboard structure
+ * is used to find out its type - no unions are used.
+ * If it is a lboard, then the config info of this board will be found
+ * on the local node. (LOCAL NODE BASE + offset value gives pointer to 
+ * the structure.
+ * If it is a rboard, the local structure contains the node number
+ * and the offset of the beginning of the LINKED LIST on the remote node.
+ * The details of the hardware on a remote node can be built locally,
+ * if required, by reading the LINKED LIST on the remote node and 
+ * ignoring all the rboards on that node.
+ *
+ * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the 
+ * First board info on the remote node. The remote node list is 
+ * traversed as the local list, using the REMOTE BASE ADDRESS and not
+ * the local base address and ignoring all rboard values.
+ *
+ * 
+ KLCONFIG
+
+ +------------+      +------------+      +------------+      +------------+
+ |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+      +------------+      +------------+      +------------+
+
+
+ +------------+
+ | board info |
+ +------------+       +--------------------------------+
+ | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
+ +------------+       +--------------------------------+
+ | compt 2    |--+
+ +------------+  |    +--------------------------------+
+ |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+       +--------------------------------+
+ | errinfo    |--+
+ +------------+  |    +--------------------------------+
+                 +--->|r/l brd errinfo,compt err flags |
+                      +--------------------------------+
+
+ *
+ * Each BOARD consists of COMPONENTs and the BOARD structure has 
+ * pointers (offsets) to its COMPONENT structure.
+ * The COMPONENT structure has version info, size and speed info, revision,
+ * error info and the NIC info. This structure can accommodate any
+ * BOARD with arbitrary COMPONENT composition.
+ *
+ * The ERRORINFO part of each BOARD has error information
+ * that describes errors about the BOARD itself. It also has flags to
+ * indicate the COMPONENT(s) on the board that have errors. The error 
+ * information specific to the COMPONENT is present in the respective 
+ * COMPONENT structure.
+ *
+ * The ERRORINFO structure is also treated like a COMPONENT, ie. the 
+ * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
+ * structure also has a pointer to the ERRORINFO structure. This is 
+ * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
+ * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where 
+ * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
+ * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info 
+ * which is present on the REMOTE NODE.(TBD)
+ * REMOTE ERRINFO can be stored on any of the nearest nodes 
+ * or on all the nearest nodes.(TBD)
+ * Like BOARD structures, REMOTE ERRINFO structures can be built locally
+ * using the rboard errinfo pointer.
+ *
+ * In order to get useful information from this Data organization, a set of
+ * interface routines are provided (TBD). The important thing to remember while
+ * manipulating the structures, is that, the NODE number information should
+ * be used. If the NODE is non-zero (remote) then each offset should
+ * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR. 
+ * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
+ * 
+ * Note that these structures do not provide much info about connectivity.
+ * That info will be part of HWGRAPH, which is an extension of the cfg_t
+ * data structure. (ref IP27prom/cfg.h) It has to be extended to include
+ * the IO part of the Network(TBD).
+ *
+ * The data structures below define the above concepts.
+ */
+
+
+/*
+ * BOARD classes
+ */
+
+#define KLCLASS_MASK    0xf0   
+#define KLCLASS_NONE    0x00
+#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_CPU     KLCLASS_NODE    
+#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI 
+                                            and the non-graphics widget boards */
+#define KLCLASS_ROUTER  0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
+                                            so that we can record error info */
+#define KLCLASS_IOBRICK 0x70            /* IP35 iobrick */
+#define KLCLASS_MAX     8               /* Bump this if a new CLASS is added */
+
+#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
+
+
+/*
+ * board types
+ */
+
+#define KLTYPE_MASK     0x0f
+#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
+
+#define KLTYPE_SNIA     (KLCLASS_CPU | 0x1)
+#define KLTYPE_TIO      (KLCLASS_CPU | 0x2)
+
+#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
+#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
+
+#define KLTYPE_IOBRICK_XBOW     (KLCLASS_MIDPLANE | 0x2)
+
+#define KLTYPE_IOBRICK          (KLCLASS_IOBRICK | 0x0)
+#define KLTYPE_NBRICK           (KLCLASS_IOBRICK | 0x4)
+#define KLTYPE_PXBRICK          (KLCLASS_IOBRICK | 0x6)
+#define KLTYPE_IXBRICK          (KLCLASS_IOBRICK | 0x7)
+#define KLTYPE_CGBRICK          (KLCLASS_IOBRICK | 0x8)
+#define KLTYPE_OPUSBRICK        (KLCLASS_IOBRICK | 0x9)
+#define KLTYPE_SABRICK          (KLCLASS_IOBRICK | 0xa)
+#define KLTYPE_IABRICK          (KLCLASS_IOBRICK | 0xb)
+#define KLTYPE_PABRICK          (KLCLASS_IOBRICK | 0xc)
+#define KLTYPE_GABRICK          (KLCLASS_IOBRICK | 0xd)
+
+
+/* 
+ * board structures
+ */
+
+#define MAX_COMPTS_PER_BRD 24
+
+typedef struct lboard_s {
+        klconf_off_t    brd_next_any;     /* Next BOARD */
+        unsigned char   struct_type;      /* type of structure, local or remote */
+        unsigned char   brd_type;         /* type+class */
+        unsigned char   brd_sversion;     /* version of this structure */
+        unsigned char   brd_brevision;    /* board revision */
+        unsigned char   brd_promver;      /* board prom version, if any */
+        unsigned char   brd_flags;        /* Enabled, Disabled etc */
+        unsigned char   brd_slot;         /* slot number */
+        unsigned short  brd_debugsw;      /* Debug switches */
+        geoid_t         brd_geoid;        /* geo id */
+        partid_t        brd_partition;    /* Partition number */
+        unsigned short  brd_diagval;      /* diagnostic value */
+        unsigned short  brd_diagparm;     /* diagnostic parameter */
+        unsigned char   brd_inventory;    /* inventory history */
+        unsigned char   brd_numcompts;    /* Number of components */
+        nic_t           brd_nic;          /* Number in CAN */
+        nasid_t         brd_nasid;        /* passed parameter */
+        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+        klconf_off_t    brd_errinfo;      /* Board's error information */
+        struct lboard_s *brd_parent;      /* Logical parent for this brd */
+        char            pad0[4];
+        unsigned char   brd_confidence;   /* confidence that the board is bad */
+        nasid_t         brd_owner;        /* who owns this board */
+        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
+        char            pad1[24];         /* future expansion */
+        char            brd_name[32];
+        nasid_t         brd_next_same_host; /* host of next brd w/same nasid */
+        klconf_off_t    brd_next_same;    /* Next BOARD with same nasid */
+} lboard_t;
+
+/*
+ * Generic info structure. This stores common info about a 
+ * component.
+ */
+ 
+typedef struct klinfo_s {                  /* Generic info */
+        unsigned char   struct_type;       /* type of this structure */
+        unsigned char   struct_version;    /* version of this structure */
+        unsigned char   flags;            /* Enabled, disabled etc */
+        unsigned char   revision;         /* component revision */
+        unsigned short  diagval;          /* result of diagnostics */
+        unsigned short  diagparm;         /* diagnostic parameter */
+        unsigned char   inventory;        /* previous inventory status */
+        unsigned short  partid;            /* widget part number */
+        nic_t           nic;              /* MUst be aligned properly */
+        unsigned char   physid;           /* physical id of component */
+        unsigned int    virtid;           /* virtual id as seen by system */
+        unsigned char   widid;            /* Widget id - if applicable */
+        nasid_t         nasid;            /* node number - from parent */
+        char            pad1;             /* pad out structure. */
+        char            pad2;             /* pad out structure. */
+        void            *data;
+        klconf_off_t    errinfo;          /* component specific errors */
+        unsigned short  pad3;             /* pci fields have moved over to */
+        unsigned short  pad4;             /* klbri_t */
+} klinfo_t ;
+
+
+static inline lboard_t *find_lboard_next(lboard_t * brd)
+{
+        if (brd && brd->brd_next_any)
+                return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
+        return NULL;
+}
+
+#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/arch/ia64/include/asm/sn/l1.h b/arch/ia64/include/asm/sn/l1.h
new file mode 100644
index 000000000000..344bf44bb356
--- /dev/null
+++ b/arch/ia64/include/asm/sn/l1.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#ifndef _ASM_IA64_SN_L1_H
+#define _ASM_IA64_SN_L1_H
+
+/* brick type response codes */
+#define L1_BRICKTYPE_PX         0x23            /* # */
+#define L1_BRICKTYPE_PE         0x25            /* % */
+#define L1_BRICKTYPE_N_p0       0x26            /* & */
+#define L1_BRICKTYPE_IP45       0x34            /* 4 */
+#define L1_BRICKTYPE_IP41       0x35            /* 5 */
+#define L1_BRICKTYPE_TWISTER    0x36            /* 6 */ /* IP53 & ROUTER */
+#define L1_BRICKTYPE_IX         0x3d            /* = */
+#define L1_BRICKTYPE_IP34       0x61            /* a */
+#define L1_BRICKTYPE_GA         0x62            /* b */
+#define L1_BRICKTYPE_C          0x63            /* c */
+#define L1_BRICKTYPE_OPUS_TIO   0x66            /* f */
+#define L1_BRICKTYPE_I          0x69            /* i */
+#define L1_BRICKTYPE_N          0x6e            /* n */
+#define L1_BRICKTYPE_OPUS       0x6f            /* o */
+#define L1_BRICKTYPE_P          0x70            /* p */
+#define L1_BRICKTYPE_R          0x72            /* r */
+#define L1_BRICKTYPE_CHI_CG     0x76            /* v */
+#define L1_BRICKTYPE_X          0x78            /* x */
+#define L1_BRICKTYPE_X2         0x79            /* y */
+#define L1_BRICKTYPE_SA         0x5e            /* ^ */
+#define L1_BRICKTYPE_PA         0x6a            /* j */
+#define L1_BRICKTYPE_IA         0x6b            /* k */
+#define L1_BRICKTYPE_ATHENA     0x2b            /* + */
+#define L1_BRICKTYPE_DAYTONA    0x7a            /* z */
+#define L1_BRICKTYPE_1932       0x2c            /* . */
+#define L1_BRICKTYPE_191010     0x2e            /* , */
+
+/* board type response codes */
+#define L1_BOARDTYPE_IP69       0x0100          /* CA */
+#define L1_BOARDTYPE_IP63       0x0200          /* CB */
+#define L1_BOARDTYPE_BASEIO     0x0300          /* IB */
+#define L1_BOARDTYPE_PCIE2SLOT  0x0400          /* IC */
+#define L1_BOARDTYPE_PCIX3SLOT  0x0500          /* ID */
+#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600       /* IE */
+#define L1_BOARDTYPE_ABACUS     0x0700          /* AB */
+#define L1_BOARDTYPE_DAYTONA    0x0800          /* AD */
+#define L1_BOARDTYPE_INVAL      (-1)            /* invalid brick type */
+
+#endif /* _ASM_IA64_SN_L1_H */
diff --git a/arch/ia64/include/asm/sn/leds.h b/arch/ia64/include/asm/sn/leds.h
new file mode 100644
index 000000000000..66cf8c4d92c9
--- /dev/null
+++ b/arch/ia64/include/asm/sn/leds.h
@@ -0,0 +1,33 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_LEDS_H
+#define _ASM_IA64_SN_LEDS_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/shub_mmr.h>
+
+#define LED0            (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
+#define LED_CPU_SHIFT   16
+
+#define LED_CPU_HEARTBEAT       0x01
+#define LED_CPU_ACTIVITY        0x02
+#define LED_ALWAYS_SET          0x00
+
+/*
+ * Basic macros for flashing the LEDS on an SGI SN.
+ */
+
+static __inline__ void
+set_led_bits(u8 value, u8 mask)
+{
+        pda->led_state = (pda->led_state & ~mask) | (value & mask);
+        *pda->led_address = (short) pda->led_state;
+}
+
+#endif /* _ASM_IA64_SN_LEDS_H */
+
diff --git a/arch/ia64/include/asm/sn/module.h b/arch/ia64/include/asm/sn/module.h
new file mode 100644
index 000000000000..734e980ece2f
--- /dev/null
+++ b/arch/ia64/include/asm/sn/module.h
@@ -0,0 +1,127 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_MODULE_H
+#define _ASM_IA64_SN_MODULE_H
+
+/* parameter for format_module_id() */
+#define MODULE_FORMAT_BRIEF     1
+#define MODULE_FORMAT_LONG      2
+#define MODULE_FORMAT_LCD       3
+
+/*
+ *      Module id format
+ *
+ *      31-16   Rack ID (encoded class, group, number - 16-bit unsigned int)
+ *       15-8   Brick type (8-bit ascii character)
+ *        7-0   Bay (brick position in rack (0-63) - 8-bit unsigned int)
+ *
+ */
+
+/*
+ * Macros for getting the brick type
+ */
+#define MODULE_BTYPE_MASK       0xff00
+#define MODULE_BTYPE_SHFT       8
+#define MODULE_GET_BTYPE(_m)    (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
+#define MODULE_BT_TO_CHAR(_b)   ((char)(_b))
+#define MODULE_GET_BTCHAR(_m)   (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
+
+/*
+ * Macros for getting the rack ID.
+ */
+#define MODULE_RACK_MASK        0xffff0000
+#define MODULE_RACK_SHFT        16
+#define MODULE_GET_RACK(_m)     (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
+
+/*
+ * Macros for getting the brick position
+ */
+#define MODULE_BPOS_MASK        0x00ff
+#define MODULE_BPOS_SHFT        0
+#define MODULE_GET_BPOS(_m)     (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
+
+/*
+ * Macros for encoding and decoding rack IDs
+ * A rack number consists of three parts:
+ *   class (0==CPU/mixed, 1==I/O), group, number
+ *
+ * Rack number is stored just as it is displayed on the screen:
+ * a 3-decimal-digit number.
+ */
+#define RACK_CLASS_DVDR         100
+#define RACK_GROUP_DVDR         10
+#define RACK_NUM_DVDR           1
+
+#define RACK_CREATE_RACKID(_c, _g, _n)  ((_c) * RACK_CLASS_DVDR +       \
+        (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
+
+#define RACK_GET_CLASS(_r)              ((_r) / RACK_CLASS_DVDR)
+#define RACK_GET_GROUP(_r)              (((_r) - RACK_GET_CLASS(_r) *   \
+            RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
+#define RACK_GET_NUM(_r)                (((_r) - RACK_GET_CLASS(_r) *   \
+            RACK_CLASS_DVDR - RACK_GET_GROUP(_r) *      \
+            RACK_GROUP_DVDR) / RACK_NUM_DVDR)
+
+/*
+ * Macros for encoding and decoding rack IDs
+ * A rack number consists of three parts:
+ *   class      1 bit, 0==CPU/mixed, 1==I/O
+ *   group      2 bits for CPU/mixed, 3 bits for I/O
+ *   number     3 bits for CPU/mixed, 2 bits for I/O (1 based)
+ */
+#define RACK_GROUP_BITS(_r)     (RACK_GET_CLASS(_r) ? 3 : 2)
+#define RACK_NUM_BITS(_r)       (RACK_GET_CLASS(_r) ? 2 : 3)
+
+#define RACK_CLASS_MASK(_r)     0x20
+#define RACK_CLASS_SHFT(_r)     5
+#define RACK_ADD_CLASS(_r, _c)  \
+        ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
+
+#define RACK_GROUP_SHFT(_r)     RACK_NUM_BITS(_r)
+#define RACK_GROUP_MASK(_r)     \
+        ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
+#define RACK_ADD_GROUP(_r, _g)  \
+        ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
+
+#define RACK_NUM_SHFT(_r)       0
+#define RACK_NUM_MASK(_r)       \
+        ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
+#define RACK_ADD_NUM(_r, _n)    \
+        ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
+
+
+/*
+ * Brick type definitions
+ */
+#define MAX_BRICK_TYPES         256 /* brick type is stored as uchar */
+
+extern char brick_types[];
+
+#define MODULE_CBRICK           0
+#define MODULE_RBRICK           1
+#define MODULE_IBRICK           2
+#define MODULE_KBRICK           3
+#define MODULE_XBRICK           4
+#define MODULE_DBRICK           5
+#define MODULE_PBRICK           6
+#define MODULE_NBRICK           7
+#define MODULE_PEBRICK          8
+#define MODULE_PXBRICK          9
+#define MODULE_IXBRICK          10
+#define MODULE_CGBRICK          11
+#define MODULE_OPUSBRICK        12
+#define MODULE_SABRICK          13      /* TIO BringUp Brick */
+#define MODULE_IABRICK          14
+#define MODULE_PABRICK          15
+#define MODULE_GABRICK          16
+#define MODULE_OPUS_TIO         17      /* OPUS TIO Riser */
+
+extern char brick_types[];
+extern void format_module_id(char *, moduleid_t, int);
+
+#endif /* _ASM_IA64_SN_MODULE_H */
diff --git a/arch/ia64/include/asm/sn/mspec.h b/arch/ia64/include/asm/sn/mspec.h
new file mode 100644
index 000000000000..c1d3c50c3223
--- /dev/null
+++ b/arch/ia64/include/asm/sn/mspec.h
@@ -0,0 +1,59 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2008 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_MSPEC_H
+#define _ASM_IA64_SN_MSPEC_H
+
+#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
+
+#define FETCHOP_LOAD            0
+#define FETCHOP_INCREMENT       8
+#define FETCHOP_DECREMENT       16
+#define FETCHOP_CLEAR           24
+
+#define FETCHOP_STORE           0
+#define FETCHOP_AND             24
+#define FETCHOP_OR              32
+
+#define FETCHOP_CLEAR_CACHE     56
+
+#define FETCHOP_LOAD_OP(addr, op) ( \
+         *(volatile long *)((char*) (addr) + (op)))
+
+#define FETCHOP_STORE_OP(addr, op, x) ( \
+         *(volatile long *)((char*) (addr) + (op)) = (long) (x))
+
+#ifdef __KERNEL__
+
+/*
+ * Each Atomic Memory Operation (amo, formerly known as fetchop)
+ * variable is 64 bytes long.  The first 8 bytes are used.  The
+ * remaining 56 bytes are unaddressable due to the operation taking
+ * that portion of the address.
+ *
+ * NOTE: The amo structure _MUST_ be placed in either the first or second
+ * half of the cache line.  The cache line _MUST NOT_ be used for anything
+ * other than additional amo entries.  This is because there are two
+ * addresses which reference the same physical cache line.  One will
+ * be a cached entry with the memory type bits all set.  This address
+ * may be loaded into processor cache.  The amo will be referenced
+ * uncached via the memory special memory type.  If any portion of the
+ * cached cache-line is modified, when that line is flushed, it will
+ * overwrite the uncached value in physical memory and lead to
+ * inconsistency.
+ */
+struct amo {
+        u64 variable;
+        u64 unused[7];
+};
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_SN_MSPEC_H */
diff --git a/arch/ia64/include/asm/sn/nodepda.h b/arch/ia64/include/asm/sn/nodepda.h
new file mode 100644
index 000000000000..ee118b901de4
--- /dev/null
+++ b/arch/ia64/include/asm/sn/nodepda.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_NODEPDA_H
+#define _ASM_IA64_SN_NODEPDA_H
+
+
+#include <asm/irq.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/bte.h>
+
+/*
+ * NUMA Node-Specific Data structures are defined in this file.
+ * In particular, this is the location of the node PDA.
+ * A pointer to the right node PDA is saved in each CPU PDA.
+ */
+
+/*
+ * Node-specific data structure.
+ *
+ * One of these structures is allocated on each node of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together 
+ * all per-node data structures. 
+ */
+struct phys_cpuid {
+        short                   nasid;
+        char                    subnode;
+        char                    slice;
+};
+
+struct nodepda_s {
+        void            *pdinfo;        /* Platform-dependent per-node info */
+
+        /*
+         * The BTEs on this node are shared by the local cpus
+         */
+        struct bteinfo_s        bte_if[MAX_BTES_PER_NODE];      /* Virtual Interface */
+        struct timer_list       bte_recovery_timer;
+        spinlock_t              bte_recovery_lock;
+
+        /* 
+         * Array of pointers to the nodepdas for each node.
+         */
+        struct nodepda_s        *pernode_pdaindr[MAX_COMPACT_NODES]; 
+
+        /*
+         * Array of physical cpu identifiers. Indexed by cpuid.
+         */
+        struct phys_cpuid       phys_cpuid[NR_CPUS];
+        spinlock_t              ptc_lock ____cacheline_aligned_in_smp;
+};
+
+typedef struct nodepda_s nodepda_t;
+
+/*
+ * Access Functions for node PDA.
+ * Since there is one nodepda for each node, we need a convenient mechanism
+ * to access these nodepdas without cluttering code with #ifdefs.
+ * The next set of definitions provides this.
+ * Routines are expected to use 
+ *
+ *      sn_nodepda   - to access node PDA for the node on which code is running
+ *      NODEPDA(cnodeid)   - to access node PDA for cnodeid
+ */
+
+DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
+#define sn_nodepda              (__get_cpu_var(__sn_nodepda))
+#define NODEPDA(cnodeid)        (sn_nodepda->pernode_pdaindr[cnodeid])
+
+/*
+ * Check if given a compact node id the corresponding node has all the
+ * cpus disabled. 
+ */
+#define is_headless_node(cnodeid)       (nr_cpus_node(cnodeid) == 0)
+
+#endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/arch/ia64/include/asm/sn/pcibr_provider.h b/arch/ia64/include/asm/sn/pcibr_provider.h
new file mode 100644
index 000000000000..da205b7cdaac
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pcibr_provider.h
@@ -0,0 +1,150 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+
+#include <asm/sn/intr.h>
+#include <asm/sn/pcibus_provider_defs.h>
+
+/* Workarounds */
+#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
+
+#define BUSTYPE_MASK                    0x1
+
+/* Macros given a pcibus structure */
+#define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
+#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
+                asic == PCIIO_ASIC_TYPE_TIOCP)
+#define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
+#define IS_TIOCP_SOFT(ps)   (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
+
+
+/*
+ * The different PCI Bridge types supported on the SGI Altix platforms
+ */
+#define PCIBR_BRIDGETYPE_UNKNOWN       -1
+#define PCIBR_BRIDGETYPE_PIC            2
+#define PCIBR_BRIDGETYPE_TIOCP          3
+
+/*
+ * Bridge 64bit Direct Map Attributes
+ */
+#define PCI64_ATTR_PREF                 (1ull << 59)
+#define PCI64_ATTR_PREC                 (1ull << 58)
+#define PCI64_ATTR_VIRTUAL              (1ull << 57)
+#define PCI64_ATTR_BAR                  (1ull << 56)
+#define PCI64_ATTR_SWAP                 (1ull << 55)
+#define PCI64_ATTR_VIRTUAL1             (1ull << 54)
+
+#define PCI32_LOCAL_BASE                0
+#define PCI32_MAPPED_BASE               0x40000000
+#define PCI32_DIRECT_BASE               0x80000000
+
+#define IS_PCI32_MAPPED(x)              ((u64)(x) < PCI32_DIRECT_BASE && \
+                                         (u64)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)              ((u64)(x) >= PCI32_MAPPED_BASE)
+
+
+/*
+ * Bridge PMU Address Transaltion Entry Attibutes
+ */
+#define PCI32_ATE_V                     (0x1 << 0)
+#define PCI32_ATE_CO                    (0x1 << 1)      /* PIC ASIC ONLY */
+#define PCI32_ATE_PIO                   (0x1 << 1)      /* TIOCP ASIC ONLY */
+#define PCI32_ATE_MSI                   (0x1 << 2)
+#define PCI32_ATE_PREF                  (0x1 << 3)
+#define PCI32_ATE_BAR                   (0x1 << 4)
+#define PCI32_ATE_ADDR_SHFT             12
+
+#define MINIMAL_ATES_REQUIRED(addr, size) \
+        (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
+
+#define MINIMAL_ATE_FLAG(addr, size) \
+        (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
+
+/* bit 29 of the pci address is the SWAP bit */
+#define ATE_SWAPSHIFT                   29
+#define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
+#define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
+
+/*
+ * I/O page size
+ */
+#if PAGE_SIZE < 16384
+#define IOPFNSHIFT                      12      /* 4K per mapped page */
+#else
+#define IOPFNSHIFT                      14      /* 16K per mapped page */
+#endif
+
+#define IOPGSIZE                        (1 << IOPFNSHIFT)
+#define IOPG(x)                         ((x) >> IOPFNSHIFT)
+#define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
+
+#define PCIBR_DEV_SWAP_DIR              (1ull << 19)
+#define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
+
+/*
+ * PMU resources.
+ */
+struct ate_resource{
+        u64 *ate;
+        u64 num_ate;
+        u64 lowest_free_index;
+};
+
+struct pcibus_info {
+        struct pcibus_bussoft   pbi_buscommon;   /* common header */
+        u32                pbi_moduleid;
+        short                   pbi_bridge_type;
+        short                   pbi_bridge_mode;
+
+        struct ate_resource     pbi_int_ate_resource;
+        u64                pbi_int_ate_size;
+
+        u64                pbi_dir_xbase;
+        char                    pbi_hub_xid;
+
+        u64                pbi_devreg[8];
+
+        u32             pbi_valid_devices;
+        u32             pbi_enabled_devices;
+
+        spinlock_t              pbi_lock;
+};
+
+extern int  pcibr_init_provider(void);
+extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
+extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
+extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
+extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
+
+/*
+ * prototypes for the bridge asic register access routines in pcibr_reg.c
+ */
+extern void             pcireg_control_bit_clr(struct pcibus_info *, u64);
+extern void             pcireg_control_bit_set(struct pcibus_info *, u64);
+extern u64         pcireg_tflush_get(struct pcibus_info *);
+extern u64         pcireg_intr_status_get(struct pcibus_info *);
+extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
+extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
+extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
+extern void             pcireg_force_intr_set(struct pcibus_info *, int);
+extern u64         pcireg_wrb_flush_get(struct pcibus_info *, int);
+extern void             pcireg_int_ate_set(struct pcibus_info *, int, u64);
+extern u64 __iomem *    pcireg_int_ate_addr(struct pcibus_info *, int);
+extern void             pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
+extern void             pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
+extern int              pcibr_ate_alloc(struct pcibus_info *, int);
+extern void             pcibr_ate_free(struct pcibus_info *, int);
+extern void             ate_write(struct pcibus_info *, int, int, u64);
+extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
+                                 void *resp, char **ssdt);
+extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
+                                  int action, void *resp);
+extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
+#endif
diff --git a/arch/ia64/include/asm/sn/pcibus_provider_defs.h b/arch/ia64/include/asm/sn/pcibus_provider_defs.h
new file mode 100644
index 000000000000..8f7c83d0f6d3
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pcibus_provider_defs.h
@@ -0,0 +1,68 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
+#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
+
+/*
+ * SN pci asic types.  Do not ever renumber these or reuse values.  The
+ * values must agree with what prom thinks they are.
+ */
+
+#define PCIIO_ASIC_TYPE_UNKNOWN 0
+#define PCIIO_ASIC_TYPE_PPB     1
+#define PCIIO_ASIC_TYPE_PIC     2
+#define PCIIO_ASIC_TYPE_TIOCP   3
+#define PCIIO_ASIC_TYPE_TIOCA   4
+#define PCIIO_ASIC_TYPE_TIOCE   5
+
+#define PCIIO_ASIC_MAX_TYPES    6
+
+/*
+ * Common pciio bus provider data.  There should be one of these as the
+ * first field in any pciio based provider soft structure (e.g. pcibr_soft
+ * tioca_soft, etc).
+ */
+
+struct pcibus_bussoft {
+        u32             bs_asic_type;   /* chipset type */
+        u32             bs_xid;         /* xwidget id */
+        u32             bs_persist_busnum; /* Persistent Bus Number */
+        u32             bs_persist_segment; /* Segment Number */
+        u64             bs_legacy_io;   /* legacy io pio addr */
+        u64             bs_legacy_mem;  /* legacy mem pio addr */
+        u64             bs_base;        /* widget base */
+        struct xwidget_info     *bs_xwidget_info;
+};
+
+struct pci_controller;
+/*
+ * SN pci bus indirection
+ */
+
+struct sn_pcibus_provider {
+        dma_addr_t      (*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
+        dma_addr_t      (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
+        void            (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
+        void *          (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
+        void            (*force_interrupt)(struct sn_irq_info *);
+        void            (*target_interrupt)(struct sn_irq_info *);
+};
+
+/*
+ * Flags used by the map interfaces
+ * bits 3:0 specifies format of passed in address
+ * bit  4   specifies that address is to be used for MSI
+ */
+
+#define SN_DMA_ADDRTYPE(x)      ((x) & 0xf)
+#define     SN_DMA_ADDR_PHYS    1       /* address is an xio address. */
+#define     SN_DMA_ADDR_XIO     2       /* address is phys memory */
+#define SN_DMA_MSI              0x10    /* Bus address is to be used for MSI */
+
+extern struct sn_pcibus_provider *sn_pci_provider[];
+#endif                          /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/pcidev.h b/arch/ia64/include/asm/sn/pcidev.h
new file mode 100644
index 000000000000..1c2382cea807
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pcidev.h
@@ -0,0 +1,85 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
+#define _ASM_IA64_SN_PCI_PCIDEV_H
+
+#include <linux/pci.h>
+
+/*
+ * In ia64, pci_dev->sysdata must be a *pci_controller. To provide access to
+ * the pcidev_info structs for all devices under a controller, we keep a
+ * list of pcidev_info under pci_controller->platform_data.
+ */
+struct sn_platform_data {
+        void *provider_soft;
+        struct list_head pcidev_info;
+};
+
+#define SN_PLATFORM_DATA(busdev) \
+        ((struct sn_platform_data *)(PCI_CONTROLLER(busdev)->platform_data))
+
+#define SN_PCIDEV_INFO(dev)     sn_pcidev_info_get(dev)
+
+/*
+ * Given a pci_bus, return the sn pcibus_bussoft struct.  Note that
+ * this only works for root busses, not for busses represented by PPB's.
+ */
+
+#define SN_PCIBUS_BUSSOFT(pci_bus) \
+        ((struct pcibus_bussoft *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
+
+#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
+        ((struct pcibus_info *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
+/*
+ * Given a struct pci_dev, return the sn pcibus_bussoft struct.  Note
+ * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
+ * due to possible PPB's in the path.
+ */
+
+#define SN_PCIDEV_BUSSOFT(pci_dev) \
+        (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
+
+#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
+        (SN_PCIDEV_INFO(pci_dev)->pdi_provider)
+
+#define PCIIO_BUS_NONE  255      /* bus 255 reserved */
+#define PCIIO_SLOT_NONE 255
+#define PCIIO_FUNC_NONE 255
+#define PCIIO_VENDOR_ID_NONE    (-1)
+
+struct pcidev_info {
+        u64             pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
+        u64             pdi_slot_host_handle;   /* Bus and devfn Host pci_dev */
+
+        struct pcibus_bussoft   *pdi_pcibus_info;       /* Kernel common bus soft */
+        struct pcidev_info      *pdi_host_pcidev_info;  /* Kernel Host pci_dev */
+        struct pci_dev          *pdi_linux_pcidev;      /* Kernel pci_dev */
+
+        struct sn_irq_info      *pdi_sn_irq_info;
+        struct sn_pcibus_provider *pdi_provider;        /* sn pci ops */
+        struct pci_dev          *host_pci_dev;          /* host bus link */
+        struct list_head        pdi_list;               /* List of pcidev_info */
+};
+
+extern void sn_irq_fixup(struct pci_dev *pci_dev,
+                         struct sn_irq_info *sn_irq_info);
+extern void sn_irq_unfixup(struct pci_dev *pci_dev);
+extern struct pcidev_info * sn_pcidev_info_get(struct pci_dev *);
+extern void sn_bus_fixup(struct pci_bus *);
+extern void sn_acpi_bus_fixup(struct pci_bus *);
+extern void sn_common_bus_fixup(struct pci_bus *, struct pcibus_bussoft *);
+extern void sn_bus_store_sysdata(struct pci_dev *dev);
+extern void sn_bus_free_sysdata(void);
+extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
+extern void sn_io_slot_fixup(struct pci_dev *);
+extern void sn_acpi_slot_fixup(struct pci_dev *);
+extern void sn_pci_fixup_slot(struct pci_dev *dev, struct pcidev_info *,
+                              struct sn_irq_info *);
+extern void sn_pci_unfixup_slot(struct pci_dev *dev);
+extern void sn_irq_lh_init(void);
+#endif                          /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/arch/ia64/include/asm/sn/pda.h b/arch/ia64/include/asm/sn/pda.h
new file mode 100644
index 000000000000..1c5108d44d8b
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pda.h
@@ -0,0 +1,69 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PDA_H
+#define _ASM_IA64_SN_PDA_H
+
+#include <linux/cache.h>
+#include <asm/percpu.h>
+#include <asm/system.h>
+
+
+/*
+ * CPU-specific data structure.
+ *
+ * One of these structures is allocated for each cpu of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together 
+ * all SN per-cpu data structures. 
+ */
+
+typedef struct pda_s {
+
+        /*
+         * Support for SN LEDs
+         */
+        volatile short  *led_address;
+        u8              led_state;
+        u8              hb_state;       /* supports blinking heartbeat leds */
+        unsigned int    hb_count;
+
+        unsigned int    idle_flag;
+        
+        volatile unsigned long *bedrock_rev_id;
+        volatile unsigned long *pio_write_status_addr;
+        unsigned long pio_write_status_val;
+        volatile unsigned long *pio_shub_war_cam_addr;
+
+        unsigned long   sn_in_service_ivecs[4];
+        int             sn_lb_int_war_ticks;
+        int             sn_last_irq;
+        int             sn_first_irq;
+} pda_t;
+
+
+#define CACHE_ALIGN(x)  (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
+
+/*
+ * PDA
+ * Per-cpu private data area for each cpu. The PDA is located immediately after
+ * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
+ * cpu but only a small amout of the page is actually used. We put the SNIA PDA
+ * in the same page as the cpu_data area. Note that there is a check in the setup
+ * code to verify that we don't overflow the page.
+ *
+ * Seems like we should should cache-line align the pda so that any changes in the
+ * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
+ * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
+ */
+DECLARE_PER_CPU(struct pda_s, pda_percpu);
+
+#define pda             (&__ia64_per_cpu_var(pda_percpu))
+
+#define pdacpu(cpu)     (&per_cpu(pda_percpu, cpu))
+
+#endif /* _ASM_IA64_SN_PDA_H */
diff --git a/arch/ia64/include/asm/sn/pic.h b/arch/ia64/include/asm/sn/pic.h
new file mode 100644
index 000000000000..5f9da5fd6e56
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pic.h
@@ -0,0 +1,261 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PIC_H
+#define _ASM_IA64_SN_PCI_PIC_H
+
+/*
+ * PIC AS DEVICE ZERO
+ * ------------------
+ *
+ * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
+ * be designated as 'device 0'.   That is a departure from earlier SGI
+ * PCI bridges.  Because of that we use config space 1 to access the
+ * config space of the first actual PCI device on the bus.
+ * Here's what the PIC manual says:
+ *
+ *     The current PCI-X bus specification now defines that the parent
+ *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
+ *     reduced the total number of devices from 8 to 4 and removed the
+ *     device registers and windows, now only supporting devices 0,1,2, and
+ *     3. PIC did leave all 8 configuration space windows. The reason was
+ *     there was nothing to gain by removing them. Here in lies the problem.
+ *     The device numbering we do using 0 through 3 is unrelated to the device
+ *     numbering which PCI-X requires in configuration space. In the past we
+ *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
+ *     PCI-X requires we start a 1, not 0 and currently the PX brick
+ *     does associate our:
+ *
+ *         device 0 with configuration space window 1,
+ *         device 1 with configuration space window 2,
+ *         device 2 with configuration space window 3,
+ *         device 3 with configuration space window 4.
+ *
+ * The net effect is that all config space access are off-by-one with
+ * relation to other per-slot accesses on the PIC.
+ * Here is a table that shows some of that:
+ *
+ *                               Internal Slot#
+ *           |
+ *           |     0         1        2         3
+ * ----------|---------------------------------------
+ * config    |  0x21000   0x22000  0x23000   0x24000
+ *           |
+ * even rrb  |  0[0]      n/a      1[0]      n/a        [] == implied even/odd
+ *           |
+ * odd rrb   |  n/a       0[1]     n/a       1[1]
+ *           |
+ * int dev   |  00       01        10        11
+ *           |
+ * ext slot# |  1        2         3         4
+ * ----------|---------------------------------------
+ */
+
+#define PIC_ATE_TARGETID_SHFT           8
+#define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFFUL
+#define PIC_PCI64_ATTR_TARG_SHFT        60
+
+
+/*****************************************************************************
+ *********************** PIC MMR structure mapping ***************************
+ *****************************************************************************/
+
+/* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
+ * of a 64-bit register.  When writing PIC registers, always write the
+ * entire 64 bits.
+ */
+
+struct pic {
+
+    /* 0x000000-0x00FFFF -- Local Registers */
+
+    /* 0x000000-0x000057 -- Standard Widget Configuration */
+    u64         p_wid_id;                       /* 0x000000 */
+    u64         p_wid_stat;                     /* 0x000008 */
+    u64         p_wid_err_upper;                /* 0x000010 */
+    u64         p_wid_err_lower;                /* 0x000018 */
+    #define p_wid_err p_wid_err_lower
+    u64         p_wid_control;                  /* 0x000020 */
+    u64         p_wid_req_timeout;              /* 0x000028 */
+    u64         p_wid_int_upper;                /* 0x000030 */
+    u64         p_wid_int_lower;                /* 0x000038 */
+    #define p_wid_int p_wid_int_lower
+    u64         p_wid_err_cmdword;              /* 0x000040 */
+    u64         p_wid_llp;                      /* 0x000048 */
+    u64         p_wid_tflush;                   /* 0x000050 */
+
+    /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
+    u64         p_wid_aux_err;                  /* 0x000058 */
+    u64         p_wid_resp_upper;               /* 0x000060 */
+    u64         p_wid_resp_lower;               /* 0x000068 */
+    #define p_wid_resp p_wid_resp_lower
+    u64         p_wid_tst_pin_ctrl;             /* 0x000070 */
+    u64         p_wid_addr_lkerr;               /* 0x000078 */
+
+    /* 0x000080-0x00008F -- PMU & MAP */
+    u64         p_dir_map;                      /* 0x000080 */
+    u64         _pad_000088;                    /* 0x000088 */
+
+    /* 0x000090-0x00009F -- SSRAM */
+    u64         p_map_fault;                    /* 0x000090 */
+    u64         _pad_000098;                    /* 0x000098 */
+
+    /* 0x0000A0-0x0000AF -- Arbitration */
+    u64         p_arb;                          /* 0x0000A0 */
+    u64         _pad_0000A8;                    /* 0x0000A8 */
+
+    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+    u64         p_ate_parity_err;               /* 0x0000B0 */
+    u64         _pad_0000B8;                    /* 0x0000B8 */
+
+    /* 0x0000C0-0x0000FF -- PCI/GIO */
+    u64         p_bus_timeout;                  /* 0x0000C0 */
+    u64         p_pci_cfg;                      /* 0x0000C8 */
+    u64         p_pci_err_upper;                /* 0x0000D0 */
+    u64         p_pci_err_lower;                /* 0x0000D8 */
+    #define p_pci_err p_pci_err_lower
+    u64         _pad_0000E0[4];                 /* 0x0000{E0..F8} */
+
+    /* 0x000100-0x0001FF -- Interrupt */
+    u64         p_int_status;                   /* 0x000100 */
+    u64         p_int_enable;                   /* 0x000108 */
+    u64         p_int_rst_stat;                 /* 0x000110 */
+    u64         p_int_mode;                     /* 0x000118 */
+    u64         p_int_device;                   /* 0x000120 */
+    u64         p_int_host_err;                 /* 0x000128 */
+    u64         p_int_addr[8];                  /* 0x0001{30,,,68} */
+    u64         p_err_int_view;                 /* 0x000170 */
+    u64         p_mult_int;                     /* 0x000178 */
+    u64         p_force_always[8];              /* 0x0001{80,,,B8} */
+    u64         p_force_pin[8];                 /* 0x0001{C0,,,F8} */
+
+    /* 0x000200-0x000298 -- Device */
+    u64         p_device[4];                    /* 0x0002{00,,,18} */
+    u64         _pad_000220[4];                 /* 0x0002{20,,,38} */
+    u64         p_wr_req_buf[4];                /* 0x0002{40,,,58} */
+    u64         _pad_000260[4];                 /* 0x0002{60,,,78} */
+    u64         p_rrb_map[2];                   /* 0x0002{80,,,88} */
+    #define p_even_resp p_rrb_map[0]                    /* 0x000280 */
+    #define p_odd_resp  p_rrb_map[1]                    /* 0x000288 */
+    u64         p_resp_status;                  /* 0x000290 */
+    u64         p_resp_clear;                   /* 0x000298 */
+
+    u64         _pad_0002A0[12];                /* 0x0002{A0..F8} */
+
+    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
+    struct {
+        u64     upper;                          /* 0x0003{00,,,F0} */
+        u64     lower;                          /* 0x0003{08,,,F8} */
+    } p_buf_addr_match[16];
+
+    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+    struct {
+        u64     flush_w_touch;                  /* 0x000{400,,,5C0} */
+        u64     flush_wo_touch;                 /* 0x000{408,,,5C8} */
+        u64     inflight;                       /* 0x000{410,,,5D0} */
+        u64     prefetch;                       /* 0x000{418,,,5D8} */
+        u64     total_pci_retry;                /* 0x000{420,,,5E0} */
+        u64     max_pci_retry;                  /* 0x000{428,,,5E8} */
+        u64     max_latency;                    /* 0x000{430,,,5F0} */
+        u64     clear_all;                      /* 0x000{438,,,5F8} */
+    } p_buf_count[8];
+
+
+    /* 0x000600-0x0009FF -- PCI/X registers */
+    u64         p_pcix_bus_err_addr;            /* 0x000600 */
+    u64         p_pcix_bus_err_attr;            /* 0x000608 */
+    u64         p_pcix_bus_err_data;            /* 0x000610 */
+    u64         p_pcix_pio_split_addr;          /* 0x000618 */
+    u64         p_pcix_pio_split_attr;          /* 0x000620 */
+    u64         p_pcix_dma_req_err_attr;        /* 0x000628 */
+    u64         p_pcix_dma_req_err_addr;        /* 0x000630 */
+    u64         p_pcix_timeout;                 /* 0x000638 */
+
+    u64         _pad_000640[120];               /* 0x000{640,,,9F8} */
+
+    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+    struct {
+        u64     p_buf_addr;                     /* 0x000{A00,,,AF0} */
+        u64     p_buf_attr;                     /* 0X000{A08,,,AF8} */
+    } p_pcix_read_buf_64[16];
+
+    struct {
+        u64     p_buf_addr;                     /* 0x000{B00,,,BE0} */
+        u64     p_buf_attr;                     /* 0x000{B08,,,BE8} */
+        u64     p_buf_valid;                    /* 0x000{B10,,,BF0} */
+        u64     __pad1;                         /* 0x000{B18,,,BF8} */
+    } p_pcix_write_buf_64[8];
+
+    /* End of Local Registers -- Start of Address Map space */
+
+    char                _pad_000c00[0x010000 - 0x000c00];
+
+    /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
+    u64         p_int_ate_ram[1024];            /* 0x010000-0x011fff */
+
+    /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
+    u64         p_int_ate_ram_mp[1024];         /* 0x012000-0x013fff */
+
+    char                _pad_014000[0x18000 - 0x014000];
+
+    /* 0x18000-0x197F8 -- PIC Write Request Ram */
+    u64         p_wr_req_lower[256];            /* 0x18000 - 0x187F8 */
+    u64         p_wr_req_upper[256];            /* 0x18800 - 0x18FF8 */
+    u64         p_wr_req_parity[256];           /* 0x19000 - 0x197F8 */
+
+    char                _pad_019800[0x20000 - 0x019800];
+
+    /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
+    union {
+        u8              c[0x1000 / 1];                  /* 0x02{0000,,,7FFF} */
+        u16     s[0x1000 / 2];                  /* 0x02{0000,,,7FFF} */
+        u32     l[0x1000 / 4];                  /* 0x02{0000,,,7FFF} */
+        u64     d[0x1000 / 8];                  /* 0x02{0000,,,7FFF} */
+        union {
+            u8  c[0x100 / 1];
+            u16 s[0x100 / 2];
+            u32 l[0x100 / 4];
+            u64 d[0x100 / 8];
+        } f[8];
+    } p_type0_cfg_dev[8];                               /* 0x02{0000,,,7FFF} */
+
+    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+    union {
+        u8              c[0x1000 / 1];                  /* 0x028000-0x029000 */
+        u16     s[0x1000 / 2];                  /* 0x028000-0x029000 */
+        u32     l[0x1000 / 4];                  /* 0x028000-0x029000 */
+        u64     d[0x1000 / 8];                  /* 0x028000-0x029000 */
+        union {
+            u8  c[0x100 / 1];
+            u16 s[0x100 / 2];
+            u32 l[0x100 / 4];
+            u64 d[0x100 / 8];
+        } f[8];
+    } p_type1_cfg;                                      /* 0x028000-0x029000 */
+
+    char                _pad_029000[0x030000-0x029000];
+
+    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+    union {
+        u8              c[8 / 1];
+        u16     s[8 / 2];
+        u32     l[8 / 4];
+        u64     d[8 / 8];
+    } p_pci_iack;                                       /* 0x030000-0x030007 */
+
+    char                _pad_030007[0x040000-0x030008];
+
+    /* 0x040000-0x030007 -- PCIX Special Cycle */
+    union {
+        u8              c[8 / 1];
+        u16     s[8 / 2];
+        u32     l[8 / 4];
+        u64     d[8 / 8];
+    } p_pcix_cycle;                                     /* 0x040000-0x040007 */
+};
+
+#endif                          /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/arch/ia64/include/asm/sn/rw_mmr.h b/arch/ia64/include/asm/sn/rw_mmr.h
new file mode 100644
index 000000000000..2d78f4c5a45e
--- /dev/null
+++ b/arch/ia64/include/asm/sn/rw_mmr.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002-2006 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+#ifndef _ASM_IA64_SN_RW_MMR_H
+#define _ASM_IA64_SN_RW_MMR_H
+
+
+/*
+ * This file that access MMRs via uncached physical addresses.
+ *      pio_phys_read_mmr  - read an MMR
+ *      pio_phys_write_mmr - write an MMR
+ *      pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
+ *              Second MMR will be skipped if address is NULL
+ *
+ * Addresses passed to these routines should be uncached physical addresses
+ * ie., 0x80000....
+ */
+
+
+extern long pio_phys_read_mmr(volatile long *mmr); 
+extern void pio_phys_write_mmr(volatile long *mmr, long val);
+extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2); 
+
+#endif /* _ASM_IA64_SN_RW_MMR_H */
diff --git a/arch/ia64/include/asm/sn/shub_mmr.h b/arch/ia64/include/asm/sn/shub_mmr.h
new file mode 100644
index 000000000000..7de1d1d4b71a
--- /dev/null
+++ b/arch/ia64/include/asm/sn/shub_mmr.h
@@ -0,0 +1,502 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2005 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SHUB_MMR_H
+#define _ASM_IA64_SN_SHUB_MMR_H
+
+/* ==================================================================== */
+/*                        Register "SH_IPI_INT"                         */
+/*               SHub Inter-Processor Interrupt Registers               */
+/* ==================================================================== */
+#define SH1_IPI_INT                     __IA64_UL_CONST(0x0000000110000380)
+#define SH2_IPI_INT                     __IA64_UL_CONST(0x0000000010000380)
+
+/*   SH_IPI_INT_TYPE                                                    */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_IPI_INT_TYPE_SHFT                            0
+#define SH_IPI_INT_TYPE_MASK            __IA64_UL_CONST(0x0000000000000007)
+
+/*   SH_IPI_INT_AGT                                                     */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_IPI_INT_AGT_SHFT                             3
+#define SH_IPI_INT_AGT_MASK             __IA64_UL_CONST(0x0000000000000008)
+
+/*   SH_IPI_INT_PID                                                     */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_IPI_INT_PID_SHFT                             4
+#define SH_IPI_INT_PID_MASK             __IA64_UL_CONST(0x00000000000ffff0)
+
+/*   SH_IPI_INT_BASE                                                    */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_IPI_INT_BASE_SHFT                            21
+#define SH_IPI_INT_BASE_MASK            __IA64_UL_CONST(0x0003ffffffe00000)
+
+/*   SH_IPI_INT_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_IPI_INT_IDX_SHFT                             52
+#define SH_IPI_INT_IDX_MASK             __IA64_UL_CONST(0x0ff0000000000000)
+
+/*   SH_IPI_INT_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_IPI_INT_SEND_SHFT                            63
+#define SH_IPI_INT_SEND_MASK            __IA64_UL_CONST(0x8000000000000000)
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+#define SH1_EVENT_OCCURRED              __IA64_UL_CONST(0x0000000110010000)
+#define SH1_EVENT_OCCURRED_ALIAS        __IA64_UL_CONST(0x0000000110010008)
+#define SH2_EVENT_OCCURRED              __IA64_UL_CONST(0x0000000010010000)
+#define SH2_EVENT_OCCURRED_ALIAS        __IA64_UL_CONST(0x0000000010010008)
+
+/* ==================================================================== */
+/*                     Register "SH_PI_CAM_CONTROL"                     */
+/*                      CRB CAM MMR Access Control                      */
+/* ==================================================================== */
+#define SH1_PI_CAM_CONTROL              __IA64_UL_CONST(0x0000000120050300)
+
+/* ==================================================================== */
+/*                        Register "SH_SHUB_ID"                         */
+/*                            SHub ID Number                            */
+/* ==================================================================== */
+#define SH1_SHUB_ID                     __IA64_UL_CONST(0x0000000110060580)
+#define SH1_SHUB_ID_REVISION_SHFT                       28
+#define SH1_SHUB_ID_REVISION_MASK       __IA64_UL_CONST(0x00000000f0000000)
+
+/* ==================================================================== */
+/*                          Register "SH_RTC"                           */
+/*                           Real-time Clock                            */
+/* ==================================================================== */
+#define SH1_RTC                         __IA64_UL_CONST(0x00000001101c0000)
+#define SH2_RTC                         __IA64_UL_CONST(0x00000002101c0000)
+#define SH_RTC_MASK                     __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
+/*                      PIO Write Status for CPU 0 & 1                  */
+/* ==================================================================== */
+#define SH1_PIO_WRITE_STATUS_0          __IA64_UL_CONST(0x0000000120070200)
+#define SH1_PIO_WRITE_STATUS_1          __IA64_UL_CONST(0x0000000120070280)
+#define SH2_PIO_WRITE_STATUS_0          __IA64_UL_CONST(0x0000000020070200)
+#define SH2_PIO_WRITE_STATUS_1          __IA64_UL_CONST(0x0000000020070280)
+#define SH2_PIO_WRITE_STATUS_2          __IA64_UL_CONST(0x0000000020070300)
+#define SH2_PIO_WRITE_STATUS_3          __IA64_UL_CONST(0x0000000020070380)
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
+/*   Description:  Deadlock response detected                           */
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT         1
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
+                                        __IA64_UL_CONST(0x0000000000000002)
+
+/*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
+/*   Description:  Count of currently pending PIO writes                */
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT    56
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
+                                        __IA64_UL_CONST(0x3f00000000000000)
+
+/* ==================================================================== */
+/*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
+/* ==================================================================== */
+#define SH1_PIO_WRITE_STATUS_0_ALIAS    __IA64_UL_CONST(0x0000000120070208)
+#define SH2_PIO_WRITE_STATUS_0_ALIAS    __IA64_UL_CONST(0x0000000020070208)
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+/*   SH_EVENT_OCCURRED_UART_INT                                         */
+/*   Description:  Pending Junk Bus UART Interrupt                      */
+#define SH_EVENT_OCCURRED_UART_INT_SHFT                 20
+#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
+
+/*   SH_EVENT_OCCURRED_IPI_INT                                          */
+/*   Description:  Pending IPI Interrupt                                */
+#define SH_EVENT_OCCURRED_IPI_INT_SHFT                  28
+#define SH_EVENT_OCCURRED_IPI_INT_MASK  __IA64_UL_CONST(0x0000000010000000)
+
+/*   SH_EVENT_OCCURRED_II_INT0                                          */
+/*   Description:  Pending II 0 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT0_SHFT                  29
+#define SH_EVENT_OCCURRED_II_INT0_MASK  __IA64_UL_CONST(0x0000000020000000)
+
+/*   SH_EVENT_OCCURRED_II_INT1                                          */
+/*   Description:  Pending II 1 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT1_SHFT                  30
+#define SH_EVENT_OCCURRED_II_INT1_MASK  __IA64_UL_CONST(0x0000000040000000)
+
+/*   SH2_EVENT_OCCURRED_EXTIO_INT2                                      */
+/*   Description:  Pending SHUB 2 EXT IO INT2                           */
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT              33
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
+
+/*   SH2_EVENT_OCCURRED_EXTIO_INT3                                      */
+/*   Description:  Pending SHUB 2 EXT IO INT3                           */
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT              34
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
+
+#define SH_ALL_INT_MASK \
+        (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
+         SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
+         SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
+         SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
+
+
+/* ==================================================================== */
+/*                         LEDS                                         */
+/* ==================================================================== */
+#define SH1_REAL_JUNK_BUS_LED0                  0x7fed00000UL
+#define SH1_REAL_JUNK_BUS_LED1                  0x7fed10000UL
+#define SH1_REAL_JUNK_BUS_LED2                  0x7fed20000UL
+#define SH1_REAL_JUNK_BUS_LED3                  0x7fed30000UL
+
+#define SH2_REAL_JUNK_BUS_LED0                  0xf0000000UL
+#define SH2_REAL_JUNK_BUS_LED1                  0xf0010000UL
+#define SH2_REAL_JUNK_BUS_LED2                  0xf0020000UL
+#define SH2_REAL_JUNK_BUS_LED3                  0xf0030000UL
+
+/* ==================================================================== */
+/*                         Register "SH1_PTC_0"                         */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+#define SH1_PTC_0                       __IA64_UL_CONST(0x00000001101a0000)
+
+/*   SH1_PTC_0_A                                                        */
+/*   Description:  Type                                                 */
+#define SH1_PTC_0_A_SHFT                                0
+
+/*   SH1_PTC_0_PS                                                       */
+/*   Description:  Page Size                                            */
+#define SH1_PTC_0_PS_SHFT                               2
+
+/*   SH1_PTC_0_RID                                                      */
+/*   Description:  Region ID                                            */
+#define SH1_PTC_0_RID_SHFT                              8
+
+/*   SH1_PTC_0_START                                                    */
+/*   Description:  Start                                                */
+#define SH1_PTC_0_START_SHFT                            63
+
+/* ==================================================================== */
+/*                         Register "SH1_PTC_1"                         */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+#define SH1_PTC_1                       __IA64_UL_CONST(0x00000001101a0080)
+
+/*   SH1_PTC_1_START                                                    */
+/*   Description:  PTC_1 Start                                          */
+#define SH1_PTC_1_START_SHFT                            63
+
+/* ==================================================================== */
+/*                         Register "SH2_PTC"                           */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+#define SH2_PTC                         __IA64_UL_CONST(0x0000000170000000)
+
+/*   SH2_PTC_A                                                          */
+/*   Description:  Type                                                 */
+#define SH2_PTC_A_SHFT                                  0
+
+/*   SH2_PTC_PS                                                         */
+/*   Description:  Page Size                                            */
+#define SH2_PTC_PS_SHFT                                 2
+
+/*   SH2_PTC_RID                                                      */
+/*   Description:  Region ID                                            */
+#define SH2_PTC_RID_SHFT                                4
+
+/*   SH2_PTC_START                                                      */
+/*   Description:  Start                                                */
+#define SH2_PTC_START_SHFT                              63
+
+/*   SH2_PTC_ADDR_RID                                                   */
+/*   Description:  Region ID                                            */
+#define SH2_PTC_ADDR_SHFT                               4
+#define SH2_PTC_ADDR_MASK               __IA64_UL_CONST(0x1ffffffffffff000)
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_CONFIG"                     */
+/*                SHub RTC 1 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC1_INT_CONFIG             __IA64_UL_CONST(0x0000000110001480)
+#define SH2_RTC1_INT_CONFIG             __IA64_UL_CONST(0x0000000010001480)
+#define SH_RTC1_INT_CONFIG_MASK         __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC1_INT_CONFIG_INIT         __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_RTC1_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC1_INT_CONFIG_TYPE_SHFT                    0
+#define SH_RTC1_INT_CONFIG_TYPE_MASK    __IA64_UL_CONST(0x0000000000000007)
+
+/*   SH_RTC1_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC1_INT_CONFIG_AGT_SHFT                     3
+#define SH_RTC1_INT_CONFIG_AGT_MASK     __IA64_UL_CONST(0x0000000000000008)
+
+/*   SH_RTC1_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC1_INT_CONFIG_PID_SHFT                     4
+#define SH_RTC1_INT_CONFIG_PID_MASK     __IA64_UL_CONST(0x00000000000ffff0)
+
+/*   SH_RTC1_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC1_INT_CONFIG_BASE_SHFT                    21
+#define SH_RTC1_INT_CONFIG_BASE_MASK    __IA64_UL_CONST(0x0003ffffffe00000)
+
+/*   SH_RTC1_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC1_INT_CONFIG_IDX_SHFT                     52
+#define SH_RTC1_INT_CONFIG_IDX_MASK     __IA64_UL_CONST(0x0ff0000000000000)
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_ENABLE"                     */
+/*                SHub RTC 1 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC1_INT_ENABLE             __IA64_UL_CONST(0x0000000110001500)
+#define SH2_RTC1_INT_ENABLE             __IA64_UL_CONST(0x0000000010001500)
+#define SH_RTC1_INT_ENABLE_MASK         __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC1_INT_ENABLE_INIT         __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
+/*   Description:  Enable RTC 1 Interrupt                               */
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT             0
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
+                                        __IA64_UL_CONST(0x0000000000000001)
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_CONFIG"                     */
+/*                SHub RTC 2 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC2_INT_CONFIG             __IA64_UL_CONST(0x0000000110001580)
+#define SH2_RTC2_INT_CONFIG             __IA64_UL_CONST(0x0000000010001580)
+#define SH_RTC2_INT_CONFIG_MASK         __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC2_INT_CONFIG_INIT         __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_RTC2_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC2_INT_CONFIG_TYPE_SHFT                    0
+#define SH_RTC2_INT_CONFIG_TYPE_MASK    __IA64_UL_CONST(0x0000000000000007)
+
+/*   SH_RTC2_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC2_INT_CONFIG_AGT_SHFT                     3
+#define SH_RTC2_INT_CONFIG_AGT_MASK     __IA64_UL_CONST(0x0000000000000008)
+
+/*   SH_RTC2_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC2_INT_CONFIG_PID_SHFT                     4
+#define SH_RTC2_INT_CONFIG_PID_MASK     __IA64_UL_CONST(0x00000000000ffff0)
+
+/*   SH_RTC2_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC2_INT_CONFIG_BASE_SHFT                    21
+#define SH_RTC2_INT_CONFIG_BASE_MASK    __IA64_UL_CONST(0x0003ffffffe00000)
+
+/*   SH_RTC2_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC2_INT_CONFIG_IDX_SHFT                     52
+#define SH_RTC2_INT_CONFIG_IDX_MASK     __IA64_UL_CONST(0x0ff0000000000000)
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_ENABLE"                     */
+/*                SHub RTC 2 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC2_INT_ENABLE             __IA64_UL_CONST(0x0000000110001600)
+#define SH2_RTC2_INT_ENABLE             __IA64_UL_CONST(0x0000000010001600)
+#define SH_RTC2_INT_ENABLE_MASK         __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC2_INT_ENABLE_INIT         __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
+/*   Description:  Enable RTC 2 Interrupt                               */
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT             0
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
+                                        __IA64_UL_CONST(0x0000000000000001)
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_CONFIG"                     */
+/*                SHub RTC 3 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC3_INT_CONFIG             __IA64_UL_CONST(0x0000000110001680)
+#define SH2_RTC3_INT_CONFIG             __IA64_UL_CONST(0x0000000010001680)
+#define SH_RTC3_INT_CONFIG_MASK         __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC3_INT_CONFIG_INIT         __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_RTC3_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC3_INT_CONFIG_TYPE_SHFT                    0
+#define SH_RTC3_INT_CONFIG_TYPE_MASK    __IA64_UL_CONST(0x0000000000000007)
+
+/*   SH_RTC3_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC3_INT_CONFIG_AGT_SHFT                     3
+#define SH_RTC3_INT_CONFIG_AGT_MASK     __IA64_UL_CONST(0x0000000000000008)
+
+/*   SH_RTC3_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC3_INT_CONFIG_PID_SHFT                     4
+#define SH_RTC3_INT_CONFIG_PID_MASK     __IA64_UL_CONST(0x00000000000ffff0)
+
+/*   SH_RTC3_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC3_INT_CONFIG_BASE_SHFT                    21
+#define SH_RTC3_INT_CONFIG_BASE_MASK    __IA64_UL_CONST(0x0003ffffffe00000)
+
+/*   SH_RTC3_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC3_INT_CONFIG_IDX_SHFT                     52
+#define SH_RTC3_INT_CONFIG_IDX_MASK     __IA64_UL_CONST(0x0ff0000000000000)
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_ENABLE"                     */
+/*                SHub RTC 3 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC3_INT_ENABLE             __IA64_UL_CONST(0x0000000110001700)
+#define SH2_RTC3_INT_ENABLE             __IA64_UL_CONST(0x0000000010001700)
+#define SH_RTC3_INT_ENABLE_MASK         __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC3_INT_ENABLE_INIT         __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
+/*   Description:  Enable RTC 3 Interrupt                               */
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT             0
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
+                                        __IA64_UL_CONST(0x0000000000000001)
+
+/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
+/*   Description:  Pending RTC 1 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC1_INT_SHFT                 24
+#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
+
+/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
+/*   Description:  Pending RTC 2 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC2_INT_SHFT                 25
+#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
+
+/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
+/*   Description:  Pending RTC 3 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC3_INT_SHFT                 26
+#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
+
+/* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#define SH1_IPI_ACCESS                  __IA64_UL_CONST(0x0000000110060480)
+#define SH2_IPI_ACCESS0                 __IA64_UL_CONST(0x0000000010060c00)
+#define SH2_IPI_ACCESS1                 __IA64_UL_CONST(0x0000000010060c80)
+#define SH2_IPI_ACCESS2                 __IA64_UL_CONST(0x0000000010060d00)
+#define SH2_IPI_ACCESS3                 __IA64_UL_CONST(0x0000000010060d80)
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPB"                        */
+/*                  RTC Compare Value for Processor B                   */
+/* ==================================================================== */
+
+#define SH1_INT_CMPB                    __IA64_UL_CONST(0x00000001101b0080)
+#define SH2_INT_CMPB                    __IA64_UL_CONST(0x00000000101b0080)
+#define SH_INT_CMPB_MASK                __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPB_INIT                __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT                 0
+#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPC"                        */
+/*                  RTC Compare Value for Processor C                   */
+/* ==================================================================== */
+
+#define SH1_INT_CMPC                    __IA64_UL_CONST(0x00000001101b0100)
+#define SH2_INT_CMPC                    __IA64_UL_CONST(0x00000000101b0100)
+#define SH_INT_CMPC_MASK                __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPC_INIT                __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT                 0
+#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPD"                        */
+/*                  RTC Compare Value for Processor D                   */
+/* ==================================================================== */
+
+#define SH1_INT_CMPD                    __IA64_UL_CONST(0x00000001101b0180)
+#define SH2_INT_CMPD                    __IA64_UL_CONST(0x00000000101b0180)
+#define SH_INT_CMPD_MASK                __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPD_INIT                __IA64_UL_CONST(0x0000000000000000)
+
+/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT                 0
+#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+#define SH1_MD_DQLP_MMR_DIR_PRIVEC0     __IA64_UL_CONST(0x0000000100030300)
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+#define SH1_MD_DQRP_MMR_DIR_PRIVEC0     __IA64_UL_CONST(0x0000000100050300)
+
+/* ==================================================================== */
+/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
+/* and SHUB2 that it makes sense to define a geberic name for the MMR.  */
+/* It is acceptible to use (for example) SH_IPI_INT to reference the    */
+/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based  */
+/* on the type of the SHUB. Do not use these #defines in performance    */
+/* critical code  or loops - there is a small performance penalty.      */
+/* ==================================================================== */
+#define shubmmr(a,b)            (is_shub2() ? a##2_##b : a##1_##b)
+
+#define SH_REAL_JUNK_BUS_LED0   shubmmr(SH, REAL_JUNK_BUS_LED0)
+#define SH_IPI_INT              shubmmr(SH, IPI_INT)
+#define SH_EVENT_OCCURRED       shubmmr(SH, EVENT_OCCURRED)
+#define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
+#define SH_RTC                  shubmmr(SH, RTC)
+#define SH_RTC1_INT_CONFIG      shubmmr(SH, RTC1_INT_CONFIG)
+#define SH_RTC1_INT_ENABLE      shubmmr(SH, RTC1_INT_ENABLE)
+#define SH_RTC2_INT_CONFIG      shubmmr(SH, RTC2_INT_CONFIG)
+#define SH_RTC2_INT_ENABLE      shubmmr(SH, RTC2_INT_ENABLE)
+#define SH_RTC3_INT_CONFIG      shubmmr(SH, RTC3_INT_CONFIG)
+#define SH_RTC3_INT_ENABLE      shubmmr(SH, RTC3_INT_ENABLE)
+#define SH_INT_CMPB             shubmmr(SH, INT_CMPB)
+#define SH_INT_CMPC             shubmmr(SH, INT_CMPC)
+#define SH_INT_CMPD             shubmmr(SH, INT_CMPD)
+
+/* ========================================================================== */
+/*                        Register "SH2_BT_ENG_CSR_0"                         */
+/*                    Engine 0 Control and Status Register                    */
+/* ========================================================================== */
+
+#define SH2_BT_ENG_CSR_0                __IA64_UL_CONST(0x0000000030040000)
+#define SH2_BT_ENG_SRC_ADDR_0           __IA64_UL_CONST(0x0000000030040080)
+#define SH2_BT_ENG_DEST_ADDR_0          __IA64_UL_CONST(0x0000000030040100)
+#define SH2_BT_ENG_NOTIF_ADDR_0         __IA64_UL_CONST(0x0000000030040180)
+
+/* ========================================================================== */
+/*                       BTE interfaces 1-3                                   */
+/* ========================================================================== */
+
+#define SH2_BT_ENG_CSR_1                __IA64_UL_CONST(0x0000000030050000)
+#define SH2_BT_ENG_CSR_2                __IA64_UL_CONST(0x0000000030060000)
+#define SH2_BT_ENG_CSR_3                __IA64_UL_CONST(0x0000000030070000)
+
+#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/arch/ia64/include/asm/sn/shubio.h b/arch/ia64/include/asm/sn/shubio.h
new file mode 100644
index 000000000000..22a6f18a5313
--- /dev/null
+++ b/arch/ia64/include/asm/sn/shubio.h
@@ -0,0 +1,3358 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SHUBIO_H
+#define _ASM_IA64_SN_SHUBIO_H
+
+#define HUB_WIDGET_ID_MAX       0xf
+#define IIO_NUM_ITTES           7
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+#define         IIO_WID                 0x00400000      /* Crosstalk Widget Identification */
+                                                        /* This register is also accessible from
+                                                         * Crosstalk at address 0x0.  */
+#define         IIO_WSTAT               0x00400008      /* Crosstalk Widget Status */
+#define         IIO_WCR                 0x00400020      /* Crosstalk Widget Control Register */
+#define         IIO_ILAPR               0x00400100      /* IO Local Access Protection Register */
+#define         IIO_ILAPO               0x00400108      /* IO Local Access Protection Override */
+#define         IIO_IOWA                0x00400110      /* IO Outbound Widget Access */
+#define         IIO_IIWA                0x00400118      /* IO Inbound Widget Access */
+#define         IIO_IIDEM               0x00400120      /* IO Inbound Device Error Mask */
+#define         IIO_ILCSR               0x00400128      /* IO LLP Control and Status Register */
+#define         IIO_ILLR                0x00400130      /* IO LLP Log Register    */
+#define         IIO_IIDSR               0x00400138      /* IO Interrupt Destination */
+
+#define         IIO_IGFX0               0x00400140      /* IO Graphics Node-Widget Map 0 */
+#define         IIO_IGFX1               0x00400148      /* IO Graphics Node-Widget Map 1 */
+
+#define         IIO_ISCR0               0x00400150      /* IO Scratch Register 0 */
+#define         IIO_ISCR1               0x00400158      /* IO Scratch Register 1 */
+
+#define         IIO_ITTE1               0x00400160      /* IO Translation Table Entry 1 */
+#define         IIO_ITTE2               0x00400168      /* IO Translation Table Entry 2 */
+#define         IIO_ITTE3               0x00400170      /* IO Translation Table Entry 3 */
+#define         IIO_ITTE4               0x00400178      /* IO Translation Table Entry 4 */
+#define         IIO_ITTE5               0x00400180      /* IO Translation Table Entry 5 */
+#define         IIO_ITTE6               0x00400188      /* IO Translation Table Entry 6 */
+#define         IIO_ITTE7               0x00400190      /* IO Translation Table Entry 7 */
+
+#define         IIO_IPRB0               0x00400198      /* IO PRB Entry 0   */
+#define         IIO_IPRB8               0x004001A0      /* IO PRB Entry 8   */
+#define         IIO_IPRB9               0x004001A8      /* IO PRB Entry 9   */
+#define         IIO_IPRBA               0x004001B0      /* IO PRB Entry A   */
+#define         IIO_IPRBB               0x004001B8      /* IO PRB Entry B   */
+#define         IIO_IPRBC               0x004001C0      /* IO PRB Entry C   */
+#define         IIO_IPRBD               0x004001C8      /* IO PRB Entry D   */
+#define         IIO_IPRBE               0x004001D0      /* IO PRB Entry E   */
+#define         IIO_IPRBF               0x004001D8      /* IO PRB Entry F   */
+
+#define         IIO_IXCC                0x004001E0      /* IO Crosstalk Credit Count Timeout */
+#define         IIO_IMEM                0x004001E8      /* IO Miscellaneous Error Mask */
+#define         IIO_IXTT                0x004001F0      /* IO Crosstalk Timeout Threshold */
+#define         IIO_IECLR               0x004001F8      /* IO Error Clear Register */
+#define         IIO_IBCR                0x00400200      /* IO BTE Control Register */
+
+#define         IIO_IXSM                0x00400208      /* IO Crosstalk Spurious Message */
+#define         IIO_IXSS                0x00400210      /* IO Crosstalk Spurious Sideband */
+
+#define         IIO_ILCT                0x00400218      /* IO LLP Channel Test    */
+
+#define         IIO_IIEPH1              0x00400220      /* IO Incoming Error Packet Header, Part 1 */
+#define         IIO_IIEPH2              0x00400228      /* IO Incoming Error Packet Header, Part 2 */
+
+#define         IIO_ISLAPR              0x00400230      /* IO SXB Local Access Protection Regster */
+#define         IIO_ISLAPO              0x00400238      /* IO SXB Local Access Protection Override */
+
+#define         IIO_IWI                 0x00400240      /* IO Wrapper Interrupt Register */
+#define         IIO_IWEL                0x00400248      /* IO Wrapper Error Log Register */
+#define         IIO_IWC                 0x00400250      /* IO Wrapper Control Register */
+#define         IIO_IWS                 0x00400258      /* IO Wrapper Status Register */
+#define         IIO_IWEIM               0x00400260      /* IO Wrapper Error Interrupt Masking Register */
+
+#define         IIO_IPCA                0x00400300      /* IO PRB Counter Adjust */
+
+#define         IIO_IPRTE0_A            0x00400308      /* IO PIO Read Address Table Entry 0, Part A */
+#define         IIO_IPRTE1_A            0x00400310      /* IO PIO Read Address Table Entry 1, Part A */
+#define         IIO_IPRTE2_A            0x00400318      /* IO PIO Read Address Table Entry 2, Part A */
+#define         IIO_IPRTE3_A            0x00400320      /* IO PIO Read Address Table Entry 3, Part A */
+#define         IIO_IPRTE4_A            0x00400328      /* IO PIO Read Address Table Entry 4, Part A */
+#define         IIO_IPRTE5_A            0x00400330      /* IO PIO Read Address Table Entry 5, Part A */
+#define         IIO_IPRTE6_A            0x00400338      /* IO PIO Read Address Table Entry 6, Part A */
+#define         IIO_IPRTE7_A            0x00400340      /* IO PIO Read Address Table Entry 7, Part A */
+
+#define         IIO_IPRTE0_B            0x00400348      /* IO PIO Read Address Table Entry 0, Part B */
+#define         IIO_IPRTE1_B            0x00400350      /* IO PIO Read Address Table Entry 1, Part B */
+#define         IIO_IPRTE2_B            0x00400358      /* IO PIO Read Address Table Entry 2, Part B */
+#define         IIO_IPRTE3_B            0x00400360      /* IO PIO Read Address Table Entry 3, Part B */
+#define         IIO_IPRTE4_B            0x00400368      /* IO PIO Read Address Table Entry 4, Part B */
+#define         IIO_IPRTE5_B            0x00400370      /* IO PIO Read Address Table Entry 5, Part B */
+#define         IIO_IPRTE6_B            0x00400378      /* IO PIO Read Address Table Entry 6, Part B */
+#define         IIO_IPRTE7_B            0x00400380      /* IO PIO Read Address Table Entry 7, Part B */
+
+#define         IIO_IPDR                0x00400388      /* IO PIO Deallocation Register */
+#define         IIO_ICDR                0x00400390      /* IO CRB Entry Deallocation Register */
+#define         IIO_IFDR                0x00400398      /* IO IOQ FIFO Depth Register */
+#define         IIO_IIAP                0x004003A0      /* IO IIQ Arbitration Parameters */
+#define         IIO_ICMR                0x004003A8      /* IO CRB Management Register */
+#define         IIO_ICCR                0x004003B0      /* IO CRB Control Register */
+#define         IIO_ICTO                0x004003B8      /* IO CRB Timeout   */
+#define         IIO_ICTP                0x004003C0      /* IO CRB Timeout Prescalar */
+
+#define         IIO_ICRB0_A             0x00400400      /* IO CRB Entry 0_A */
+#define         IIO_ICRB0_B             0x00400408      /* IO CRB Entry 0_B */
+#define         IIO_ICRB0_C             0x00400410      /* IO CRB Entry 0_C */
+#define         IIO_ICRB0_D             0x00400418      /* IO CRB Entry 0_D */
+#define         IIO_ICRB0_E             0x00400420      /* IO CRB Entry 0_E */
+
+#define         IIO_ICRB1_A             0x00400430      /* IO CRB Entry 1_A */
+#define         IIO_ICRB1_B             0x00400438      /* IO CRB Entry 1_B */
+#define         IIO_ICRB1_C             0x00400440      /* IO CRB Entry 1_C */
+#define         IIO_ICRB1_D             0x00400448      /* IO CRB Entry 1_D */
+#define         IIO_ICRB1_E             0x00400450      /* IO CRB Entry 1_E */
+
+#define         IIO_ICRB2_A             0x00400460      /* IO CRB Entry 2_A */
+#define         IIO_ICRB2_B             0x00400468      /* IO CRB Entry 2_B */
+#define         IIO_ICRB2_C             0x00400470      /* IO CRB Entry 2_C */
+#define         IIO_ICRB2_D             0x00400478      /* IO CRB Entry 2_D */
+#define         IIO_ICRB2_E             0x00400480      /* IO CRB Entry 2_E */
+
+#define         IIO_ICRB3_A             0x00400490      /* IO CRB Entry 3_A */
+#define         IIO_ICRB3_B             0x00400498      /* IO CRB Entry 3_B */
+#define         IIO_ICRB3_C             0x004004a0      /* IO CRB Entry 3_C */
+#define         IIO_ICRB3_D             0x004004a8      /* IO CRB Entry 3_D */
+#define         IIO_ICRB3_E             0x004004b0      /* IO CRB Entry 3_E */
+
+#define         IIO_ICRB4_A             0x004004c0      /* IO CRB Entry 4_A */
+#define         IIO_ICRB4_B             0x004004c8      /* IO CRB Entry 4_B */
+#define         IIO_ICRB4_C             0x004004d0      /* IO CRB Entry 4_C */
+#define         IIO_ICRB4_D             0x004004d8      /* IO CRB Entry 4_D */
+#define         IIO_ICRB4_E             0x004004e0      /* IO CRB Entry 4_E */
+
+#define         IIO_ICRB5_A             0x004004f0      /* IO CRB Entry 5_A */
+#define         IIO_ICRB5_B             0x004004f8      /* IO CRB Entry 5_B */
+#define         IIO_ICRB5_C             0x00400500      /* IO CRB Entry 5_C */
+#define         IIO_ICRB5_D             0x00400508      /* IO CRB Entry 5_D */
+#define         IIO_ICRB5_E             0x00400510      /* IO CRB Entry 5_E */
+
+#define         IIO_ICRB6_A             0x00400520      /* IO CRB Entry 6_A */
+#define         IIO_ICRB6_B             0x00400528      /* IO CRB Entry 6_B */
+#define         IIO_ICRB6_C             0x00400530      /* IO CRB Entry 6_C */
+#define         IIO_ICRB6_D             0x00400538      /* IO CRB Entry 6_D */
+#define         IIO_ICRB6_E             0x00400540      /* IO CRB Entry 6_E */
+
+#define         IIO_ICRB7_A             0x00400550      /* IO CRB Entry 7_A */
+#define         IIO_ICRB7_B             0x00400558      /* IO CRB Entry 7_B */
+#define         IIO_ICRB7_C             0x00400560      /* IO CRB Entry 7_C */
+#define         IIO_ICRB7_D             0x00400568      /* IO CRB Entry 7_D */
+#define         IIO_ICRB7_E             0x00400570      /* IO CRB Entry 7_E */
+
+#define         IIO_ICRB8_A             0x00400580      /* IO CRB Entry 8_A */
+#define         IIO_ICRB8_B             0x00400588      /* IO CRB Entry 8_B */
+#define         IIO_ICRB8_C             0x00400590      /* IO CRB Entry 8_C */
+#define         IIO_ICRB8_D             0x00400598      /* IO CRB Entry 8_D */
+#define         IIO_ICRB8_E             0x004005a0      /* IO CRB Entry 8_E */
+
+#define         IIO_ICRB9_A             0x004005b0      /* IO CRB Entry 9_A */
+#define         IIO_ICRB9_B             0x004005b8      /* IO CRB Entry 9_B */
+#define         IIO_ICRB9_C             0x004005c0      /* IO CRB Entry 9_C */
+#define         IIO_ICRB9_D             0x004005c8      /* IO CRB Entry 9_D */
+#define         IIO_ICRB9_E             0x004005d0      /* IO CRB Entry 9_E */
+
+#define         IIO_ICRBA_A             0x004005e0      /* IO CRB Entry A_A */
+#define         IIO_ICRBA_B             0x004005e8      /* IO CRB Entry A_B */
+#define         IIO_ICRBA_C             0x004005f0      /* IO CRB Entry A_C */
+#define         IIO_ICRBA_D             0x004005f8      /* IO CRB Entry A_D */
+#define         IIO_ICRBA_E             0x00400600      /* IO CRB Entry A_E */
+
+#define         IIO_ICRBB_A             0x00400610      /* IO CRB Entry B_A */
+#define         IIO_ICRBB_B             0x00400618      /* IO CRB Entry B_B */
+#define         IIO_ICRBB_C             0x00400620      /* IO CRB Entry B_C */
+#define         IIO_ICRBB_D             0x00400628      /* IO CRB Entry B_D */
+#define         IIO_ICRBB_E             0x00400630      /* IO CRB Entry B_E */
+
+#define         IIO_ICRBC_A             0x00400640      /* IO CRB Entry C_A */
+#define         IIO_ICRBC_B             0x00400648      /* IO CRB Entry C_B */
+#define         IIO_ICRBC_C             0x00400650      /* IO CRB Entry C_C */
+#define         IIO_ICRBC_D             0x00400658      /* IO CRB Entry C_D */
+#define         IIO_ICRBC_E             0x00400660      /* IO CRB Entry C_E */
+
+#define         IIO_ICRBD_A             0x00400670      /* IO CRB Entry D_A */
+#define         IIO_ICRBD_B             0x00400678      /* IO CRB Entry D_B */
+#define         IIO_ICRBD_C             0x00400680      /* IO CRB Entry D_C */
+#define         IIO_ICRBD_D             0x00400688      /* IO CRB Entry D_D */
+#define         IIO_ICRBD_E             0x00400690      /* IO CRB Entry D_E */
+
+#define         IIO_ICRBE_A             0x004006a0      /* IO CRB Entry E_A */
+#define         IIO_ICRBE_B             0x004006a8      /* IO CRB Entry E_B */
+#define         IIO_ICRBE_C             0x004006b0      /* IO CRB Entry E_C */
+#define         IIO_ICRBE_D             0x004006b8      /* IO CRB Entry E_D */
+#define         IIO_ICRBE_E             0x004006c0      /* IO CRB Entry E_E */
+
+#define         IIO_ICSML               0x00400700      /* IO CRB Spurious Message Low */
+#define         IIO_ICSMM               0x00400708      /* IO CRB Spurious Message Middle */
+#define         IIO_ICSMH               0x00400710      /* IO CRB Spurious Message High */
+
+#define         IIO_IDBSS               0x00400718      /* IO Debug Submenu Select */
+
+#define         IIO_IBLS0               0x00410000      /* IO BTE Length Status 0 */
+#define         IIO_IBSA0               0x00410008      /* IO BTE Source Address 0 */
+#define         IIO_IBDA0               0x00410010      /* IO BTE Destination Address 0 */
+#define         IIO_IBCT0               0x00410018      /* IO BTE Control Terminate 0 */
+#define         IIO_IBNA0               0x00410020      /* IO BTE Notification Address 0 */
+#define         IIO_IBIA0               0x00410028      /* IO BTE Interrupt Address 0 */
+#define         IIO_IBLS1               0x00420000      /* IO BTE Length Status 1 */
+#define         IIO_IBSA1               0x00420008      /* IO BTE Source Address 1 */
+#define         IIO_IBDA1               0x00420010      /* IO BTE Destination Address 1 */
+#define         IIO_IBCT1               0x00420018      /* IO BTE Control Terminate 1 */
+#define         IIO_IBNA1               0x00420020      /* IO BTE Notification Address 1 */
+#define         IIO_IBIA1               0x00420028      /* IO BTE Interrupt Address 1 */
+
+#define         IIO_IPCR                0x00430000      /* IO Performance Control */
+#define         IIO_IPPR                0x00430008      /* IO Performance Profiling */
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register echoes some information from the         *
+ * LB_REV_ID register. It is available through Crosstalk as described   *
+ * above. The REV_NUM and MFG_NUM fields receive their values from      *
+ * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
+ * The PART_NUM field's value is the Crosstalk device ID number that    *
+ * Steve Miller assigned to the SHub chip.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wid_u {
+        u64 ii_wid_regval;
+        struct {
+                u64 w_rsvd_1:1;
+                u64 w_mfg_num:11;
+                u64 w_part_num:16;
+                u64 w_rev_num:4;
+                u64 w_rsvd:32;
+        } ii_wid_fld_s;
+} ii_wid_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  The fields in this register are set upon detection of an error      *
+ * and cleared by various mechanisms, as explained in the               *
+ * description.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wstat_u {
+        u64 ii_wstat_regval;
+        struct {
+                u64 w_pending:4;
+                u64 w_xt_crd_to:1;
+                u64 w_xt_tail_to:1;
+                u64 w_rsvd_3:3;
+                u64 w_tx_mx_rty:1;
+                u64 w_rsvd_2:6;
+                u64 w_llp_tx_cnt:8;
+                u64 w_rsvd_1:8;
+                u64 w_crazy:1;
+                u64 w_rsvd:31;
+        } ii_wstat_fld_s;
+} ii_wstat_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This is a read-write enabled register. It controls     *
+ * various aspects of the Crosstalk flow control.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wcr_u {
+        u64 ii_wcr_regval;
+        struct {
+                u64 w_wid:4;
+                u64 w_tag:1;
+                u64 w_rsvd_1:8;
+                u64 w_dst_crd:3;
+                u64 w_f_bad_pkt:1;
+                u64 w_dir_con:1;
+                u64 w_e_thresh:5;
+                u64 w_rsvd:41;
+        } ii_wcr_fld_s;
+} ii_wcr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register's value is a bit vector that guards      *
+ * access to local registers within the II as well as to external       *
+ * Crosstalk widgets. Each bit in the register corresponds to a         *
+ * particular region in the system; a region consists of one, two or    *
+ * four nodes (depending on the value of the REGION_SIZE field in the   *
+ * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
+ * protection provided by this register applies to PIO read             *
+ * operations as well as PIO write operations. The II will perform a    *
+ * PIO read or write request only if the bit for the requestor's        *
+ * region is set; otherwise, the II will not perform the requested      *
+ * operation and will return an error response. When a PIO read or      *
+ * write request targets an external Crosstalk widget, then not only    *
+ * must the bit for the requestor's region be set in the ILAPR, but     *
+ * also the target widget's bit in the IOWA register must be set in     *
+ * order for the II to perform the requested operation; otherwise,      *
+ * the II will return an error response. Hence, the protection          *
+ * provided by the IOWA register supplements the protection provided    *
+ * by the ILAPR for requests that target external Crosstalk widgets.    *
+ * This register itself can be accessed only by the nodes whose         *
+ * region ID bits are enabled in this same register. It can also be     *
+ * accessed through the IAlias space by the local processors.           *
+ * The reset value of this register allows access by all nodes.         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapr_u {
+        u64 ii_ilapr_regval;
+        struct {
+                u64 i_region:64;
+        } ii_ilapr_fld_s;
+} ii_ilapr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  A write to this register of the 64-bit value           *
+ * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
+ * corresponding to the region of the requestor to be set (allow        *
+ * access). A write of any other value will be ignored. Access          *
+ * protection for this register is "SGIrules".                          *
+ * This register can also be accessed through the IAlias space.         *
+ * However, this access will not change the access permissions in the   *
+ * ILAPR.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapo_u {
+        u64 ii_ilapo_regval;
+        struct {
+                u64 i_io_ovrride:64;
+        } ii_ilapo_fld_s;
+} ii_ilapo_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register qualifies all the PIO and Graphics writes launched    *
+ * from the SHUB towards a widget.                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iowa_u {
+        u64 ii_iowa_regval;
+        struct {
+                u64 i_w0_oac:1;
+                u64 i_rsvd_1:7;
+                u64 i_wx_oac:8;
+                u64 i_rsvd:48;
+        } ii_iowa_fld_s;
+} ii_iowa_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the requests launched      *
+ * from a widget towards the Shub. This register is intended to be      *
+ * used by software in case of misbehaving widgets.                     *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiwa_u {
+        u64 ii_iiwa_regval;
+        struct {
+                u64 i_w0_iac:1;
+                u64 i_rsvd_1:7;
+                u64 i_wx_iac:8;
+                u64 i_rsvd:48;
+        } ii_iiwa_fld_s;
+} ii_iiwa_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the operations launched    *
+ * from a widget towards the SHub. It allows individual access          *
+ * control for up to 8 devices per widget. A device refers to           *
+ * individual DMA master hosted by a widget.                            *
+ * The bits in each field of this register are cleared by the Shub      *
+ * upon detection of an error which requires the device to be           *
+ * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
+ * Crosstalk). Whether or not a device has access rights to this        *
+ * Shub is determined by an AND of the device enable bit in the         *
+ * appropriate field of this register and the corresponding bit in      *
+ * the Wx_IAC field (for the widget which this device belongs to).      *
+ * The bits in this field are set by writing a 1 to them. Incoming      *
+ * replies from Crosstalk are not subject to this access control        *
+ * mechanism.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidem_u {
+        u64 ii_iidem_regval;
+        struct {
+                u64 i_w8_dxs:8;
+                u64 i_w9_dxs:8;
+                u64 i_wa_dxs:8;
+                u64 i_wb_dxs:8;
+                u64 i_wc_dxs:8;
+                u64 i_wd_dxs:8;
+                u64 i_we_dxs:8;
+                u64 i_wf_dxs:8;
+        } ii_iidem_fld_s;
+} ii_iidem_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the various programmable fields necessary    *
+ * for controlling and observing the LLP signals.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilcsr_u {
+        u64 ii_ilcsr_regval;
+        struct {
+                u64 i_nullto:6;
+                u64 i_rsvd_4:2;
+                u64 i_wrmrst:1;
+                u64 i_rsvd_3:1;
+                u64 i_llp_en:1;
+                u64 i_bm8:1;
+                u64 i_llp_stat:2;
+                u64 i_remote_power:1;
+                u64 i_rsvd_2:1;
+                u64 i_maxrtry:10;
+                u64 i_d_avail_sel:2;
+                u64 i_rsvd_1:4;
+                u64 i_maxbrst:10;
+                u64 i_rsvd:22;
+
+        } ii_ilcsr_fld_s;
+} ii_ilcsr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This is simply a status registers that monitors the LLP error       *
+ * rate.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_illr_u {
+        u64 ii_illr_regval;
+        struct {
+                u64 i_sn_cnt:16;
+                u64 i_cb_cnt:16;
+                u64 i_rsvd:32;
+        } ii_illr_fld_s;
+} ii_illr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  All II-detected non-BTE error interrupts are           *
+ * specified via this register.                                         *
+ * NOTE: The PI interrupt register address is hardcoded in the II. If   *
+ * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
+ * packet) to address offset 0x0180_0090 within the local register      *
+ * address space of PI0 on the node specified by the NODE field. If     *
+ * PI_ID==1, then the II sends the interrupt request to address         *
+ * offset 0x01A0_0090 within the local register address space of PI1    *
+ * on the node specified by the NODE field.                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidsr_u {
+        u64 ii_iidsr_regval;
+        struct {
+                u64 i_level:8;
+                u64 i_pi_id:1;
+                u64 i_node:11;
+                u64 i_rsvd_3:4;
+                u64 i_enable:1;
+                u64 i_rsvd_2:3;
+                u64 i_int_sent:2;
+                u64 i_rsvd_1:2;
+                u64 i_pi0_forward_int:1;
+                u64 i_pi1_forward_int:1;
+                u64 i_rsvd:30;
+        } ii_iidsr_fld_s;
+} ii_iidsr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx0_u {
+        u64 ii_igfx0_regval;
+        struct {
+                u64 i_w_num:4;
+                u64 i_pi_id:1;
+                u64 i_n_num:12;
+                u64 i_p_num:1;
+                u64 i_rsvd:46;
+        } ii_igfx0_fld_s;
+} ii_igfx0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx1_u {
+        u64 ii_igfx1_regval;
+        struct {
+                u64 i_w_num:4;
+                u64 i_pi_id:1;
+                u64 i_n_num:12;
+                u64 i_p_num:1;
+                u64 i_rsvd:46;
+        } ii_igfx1_fld_s;
+} ii_igfx1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr0_u {
+        u64 ii_iscr0_regval;
+        struct {
+                u64 i_scratch:64;
+        } ii_iscr0_fld_s;
+} ii_iscr0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr1_u {
+        u64 ii_iscr1_regval;
+        struct {
+                u64 i_scratch:64;
+        } ii_iscr1_fld_s;
+} ii_iscr1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       * 
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte1_u {
+        u64 ii_itte1_regval;
+        struct {
+                u64 i_offset:5;
+                u64 i_rsvd_1:3;
+                u64 i_w_num:4;
+                u64 i_iosp:1;
+                u64 i_rsvd:51;
+        } ii_itte1_fld_s;
+} ii_itte1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte2_u {
+        u64 ii_itte2_regval;
+        struct {
+                u64 i_offset:5;
+                u64 i_rsvd_1:3;
+                u64 i_w_num:4;
+                u64 i_iosp:1;
+                u64 i_rsvd:51;
+        } ii_itte2_fld_s;
+} ii_itte2_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte3_u {
+        u64 ii_itte3_regval;
+        struct {
+                u64 i_offset:5;
+                u64 i_rsvd_1:3;
+                u64 i_w_num:4;
+                u64 i_iosp:1;
+                u64 i_rsvd:51;
+        } ii_itte3_fld_s;
+} ii_itte3_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte4_u {
+        u64 ii_itte4_regval;
+        struct {
+                u64 i_offset:5;
+                u64 i_rsvd_1:3;
+                u64 i_w_num:4;
+                u64 i_iosp:1;
+                u64 i_rsvd:51;
+        } ii_itte4_fld_s;
+} ii_itte4_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte5_u {
+        u64 ii_itte5_regval;
+        struct {
+                u64 i_offset:5;
+                u64 i_rsvd_1:3;
+                u64 i_w_num:4;
+                u64 i_iosp:1;
+                u64 i_rsvd:51;
+        } ii_itte5_fld_s;
+} ii_itte5_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte6_u {
+        u64 ii_itte6_regval;
+        struct {
+                u64 i_offset:5;
+                u64 i_rsvd_1:3;
+                u64 i_w_num:4;
+                u64 i_iosp:1;
+                u64 i_rsvd:51;
+        } ii_itte6_fld_s;
+} ii_itte6_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte7_u {
+        u64 ii_itte7_regval;
+        struct {
+                u64 i_offset:5;
+                u64 i_rsvd_1:3;
+                u64 i_w_num:4;
+                u64 i_iosp:1;
+                u64 i_rsvd:51;
+        } ii_itte7_fld_s;
+} ii_itte7_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb0_u {
+        u64 ii_iprb0_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprb0_fld_s;
+} ii_iprb0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb8_u {
+        u64 ii_iprb8_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprb8_fld_s;
+} ii_iprb8_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb9_u {
+        u64 ii_iprb9_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprb9_fld_s;
+} ii_iprb9_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprba_u {
+        u64 ii_iprba_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprba_fld_s;
+} ii_iprba_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbb_u {
+        u64 ii_iprbb_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprbb_fld_s;
+} ii_iprbb_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbc_u {
+        u64 ii_iprbc_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprbc_fld_s;
+} ii_iprbc_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbd_u {
+        u64 ii_iprbd_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprbd_fld_s;
+} ii_iprbd_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbe_u {
+        u64 ii_iprbe_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprbe_fld_s;
+} ii_iprbe_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Shub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbf_u {
+        u64 ii_iprbf_regval;
+        struct {
+                u64 i_c:8;
+                u64 i_na:14;
+                u64 i_rsvd_2:2;
+                u64 i_nb:14;
+                u64 i_rsvd_1:2;
+                u64 i_m:2;
+                u64 i_f:1;
+                u64 i_of_cnt:5;
+                u64 i_error:1;
+                u64 i_rd_to:1;
+                u64 i_spur_wr:1;
+                u64 i_spur_rd:1;
+                u64 i_rsvd:11;
+                u64 i_mult_err:1;
+        } ii_iprbe_fld_s;
+} ii_iprbf_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register specifies the timeout value to use for monitoring     *
+ * Crosstalk credits which are used outbound to Crosstalk. An           *
+ * internal counter called the Crosstalk Credit Timeout Counter         *
+ * increments every 128 II clocks. The counter starts counting          *
+ * anytime the credit count drops below a threshold, and resets to      *
+ * zero (stops counting) anytime the credit count is at or above the    *
+ * threshold. The threshold is 1 credit in direct connect mode and 2    *
+ * in Crossbow connect mode. When the internal Crosstalk Credit         *
+ * Timeout Counter reaches the value programmed in this register, a     *
+ * Crosstalk Credit Timeout has occurred. The internal counter is not   *
+ * readable from software, and stops counting at its maximum value,     *
+ * so it cannot cause more than one interrupt.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixcc_u {
+        u64 ii_ixcc_regval;
+        struct {
+                u64 i_time_out:26;
+                u64 i_rsvd:38;
+        } ii_ixcc_fld_s;
+} ii_ixcc_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the PIO and DMA            *
+ * operations launched from widget 0 towards the SHub. In               *
+ * addition, it also qualifies accesses by the BTE streams.             *
+ * The bits in each field of this register are cleared by the SHub      *
+ * upon detection of an error which requires widget 0 or the BTE        *
+ * streams to be terminated. Whether or not widget x has access         *
+ * rights to this SHub is determined by an AND of the device            *
+ * enable bit in the appropriate field of this register and bit 0 in    *
+ * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
+ * them. Incoming replies from Crosstalk are not subject to this        *
+ * access control mechanism.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_imem_u {
+        u64 ii_imem_regval;
+        struct {
+                u64 i_w0_esd:1;
+                u64 i_rsvd_3:3;
+                u64 i_b0_esd:1;
+                u64 i_rsvd_2:3;
+                u64 i_b1_esd:1;
+                u64 i_rsvd_1:3;
+                u64 i_clr_precise:1;
+                u64 i_rsvd:51;
+        } ii_imem_fld_s;
+} ii_imem_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register specifies the timeout value to use for   *
+ * monitoring Crosstalk tail flits coming into the Shub in the          *
+ * TAIL_TO field. An internal counter associated with this register     *
+ * is incremented every 128 II internal clocks (7 bits). The counter    *
+ * starts counting anytime a header micropacket is received and stops   *
+ * counting (and resets to zero) any time a micropacket with a Tail     *
+ * bit is received. Once the counter reaches the threshold value        *
+ * programmed in this register, it generates an interrupt to the        *
+ * processor that is programmed into the IIDSR. The counter saturates   *
+ * (does not roll over) at its maximum value, so it cannot cause        *
+ * another interrupt until after it is cleared.                         *
+ * The register also contains the Read Response Timeout values. The     *
+ * Prescalar is 23 bits, and counts II clocks. An internal counter      *
+ * increments on every II clock and when it reaches the value in the    *
+ * Prescalar field, all IPRTE registers with their valid bits set       *
+ * have their Read Response timers bumped. Whenever any of them match   *
+ * the value in the RRSP_TO field, a Read Response Timeout has          *
+ * occurred, and error handling occurs as described in the Error        *
+ * Handling section of this document.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixtt_u {
+        u64 ii_ixtt_regval;
+        struct {
+                u64 i_tail_to:26;
+                u64 i_rsvd_1:6;
+                u64 i_rrsp_ps:23;
+                u64 i_rrsp_to:5;
+                u64 i_rsvd:4;
+        } ii_ixtt_fld_s;
+} ii_ixtt_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Writing a 1 to the fields of this register clears the appropriate   *
+ * error bits in other areas of SHub. Note that when the                *
+ * E_PRB_x bits are used to clear error bits in PRB registers,          *
+ * SPUR_RD and SPUR_WR may persist, because they require additional     *
+ * action to clear them. See the IPRBx and IXSS Register                *
+ * specifications.                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ieclr_u {
+        u64 ii_ieclr_regval;
+        struct {
+                u64 i_e_prb_0:1;
+                u64 i_rsvd:7;
+                u64 i_e_prb_8:1;
+                u64 i_e_prb_9:1;
+                u64 i_e_prb_a:1;
+                u64 i_e_prb_b:1;
+                u64 i_e_prb_c:1;
+                u64 i_e_prb_d:1;
+                u64 i_e_prb_e:1;
+                u64 i_e_prb_f:1;
+                u64 i_e_crazy:1;
+                u64 i_e_bte_0:1;
+                u64 i_e_bte_1:1;
+                u64 i_reserved_1:10;
+                u64 i_spur_rd_hdr:1;
+                u64 i_cam_intr_to:1;
+                u64 i_cam_overflow:1;
+                u64 i_cam_read_miss:1;
+                u64 i_ioq_rep_underflow:1;
+                u64 i_ioq_req_underflow:1;
+                u64 i_ioq_rep_overflow:1;
+                u64 i_ioq_req_overflow:1;
+                u64 i_iiq_rep_overflow:1;
+                u64 i_iiq_req_overflow:1;
+                u64 i_ii_xn_rep_cred_overflow:1;
+                u64 i_ii_xn_req_cred_overflow:1;
+                u64 i_ii_xn_invalid_cmd:1;
+                u64 i_xn_ii_invalid_cmd:1;
+                u64 i_reserved_2:21;
+        } ii_ieclr_fld_s;
+} ii_ieclr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls both BTEs. SOFT_RESET is intended for        *
+ * recovery after an error. COUNT controls the total number of CRBs     *
+ * that both BTEs (combined) can use, which affects total BTE           *
+ * bandwidth.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibcr_u {
+        u64 ii_ibcr_regval;
+        struct {
+                u64 i_count:4;
+                u64 i_rsvd_1:4;
+                u64 i_soft_reset:1;
+                u64 i_rsvd:55;
+        } ii_ibcr_fld_s;
+} ii_ibcr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the header of a spurious read response       *
+ * received from Crosstalk. A spurious read response is defined as a    *
+ * read response received by II from a widget for which (1) the SIDN    *
+ * has a value between 1 and 7, inclusive (II never sends requests to   *
+ * these widgets (2) there is no valid IPRTE register which             *
+ * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
+ * not the same as the widget recorded in the IPRTE register            *
+ * referenced by the TNUM. If this condition is true, and if the        *
+ * IXSS[VALID] bit is clear, then the header of the spurious read       *
+ * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
+ * errant header is thereby captured, and no further spurious read      *
+ * respones are captured until IXSS[VALID] is cleared by setting the    *
+ * appropriate bit in IECLR.Everytime a spurious read response is       *
+ * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
+ * message's SIDN field is set. This always happens, regarless of       *
+ * whether a header is captured. The programmer should check            *
+ * IXSM[SIDN] to determine which widget sent the spurious response,     *
+ * because there may be more than one SPUR_RD bit set in the PRB        *
+ * registers. The widget indicated by IXSM[SIDN] was the first          *
+ * spurious read response to be received since the last time            *
+ * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
+ * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
+ * spurious messages from other widets which were detected after the    *
+ * header was captured..                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixsm_u {
+        u64 ii_ixsm_regval;
+        struct {
+                u64 i_byte_en:32;
+                u64 i_reserved:1;
+                u64 i_tag:3;
+                u64 i_alt_pactyp:4;
+                u64 i_bo:1;
+                u64 i_error:1;
+                u64 i_vbpm:1;
+                u64 i_gbr:1;
+                u64 i_ds:2;
+                u64 i_ct:1;
+                u64 i_tnum:5;
+                u64 i_pactyp:4;
+                u64 i_sidn:4;
+                u64 i_didn:4;
+        } ii_ixsm_fld_s;
+} ii_ixsm_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the sideband bits of a spurious read         *
+ * response received from Crosstalk.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixss_u {
+        u64 ii_ixss_regval;
+        struct {
+                u64 i_sideband:8;
+                u64 i_rsvd:55;
+                u64 i_valid:1;
+        } ii_ixss_fld_s;
+} ii_ixss_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register enables software to access the II LLP's test port.    *
+ * Refer to the LLP 2.5 documentation for an explanation of the test    *
+ * port. Software can write to this register to program the values      *
+ * for the control fields (TestErrCapture, TestClear, TestFlit,         *
+ * TestMask and TestSeed). Similarly, software can read from this       *
+ * register to obtain the values of the test port's status outputs      *
+ * (TestCBerr, TestValid and TestData).                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilct_u {
+        u64 ii_ilct_regval;
+        struct {
+                u64 i_test_seed:20;
+                u64 i_test_mask:8;
+                u64 i_test_data:20;
+                u64 i_test_valid:1;
+                u64 i_test_cberr:1;
+                u64 i_test_flit:3;
+                u64 i_test_clear:1;
+                u64 i_test_err_capture:1;
+                u64 i_rsvd:9;
+        } ii_ilct_fld_s;
+} ii_ilct_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  If the II detects an illegal incoming Duplonet packet (request or   *
+ * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
+ * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
+ * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
+ * and assigns a value to the ERR_TYPE field which indicates the        *
+ * specific nature of the error. The II recognizes four different       *
+ * types of errors: short request packets (ERR_TYPE==2), short reply    *
+ * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
+ * reply packets (ERR_TYPE==5). The encodings for these types of        *
+ * errors were chosen to be consistent with the same types of errors    *
+ * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
+ * the LB unit). If the II detects an illegal incoming Duplonet         *
+ * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
+ * the OVERRUN bit to indicate that a subsequent error has happened,    *
+ * and does nothing further.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph1_u {
+        u64 ii_iieph1_regval;
+        struct {
+                u64 i_command:7;
+                u64 i_rsvd_5:1;
+                u64 i_suppl:14;
+                u64 i_rsvd_4:1;
+                u64 i_source:14;
+                u64 i_rsvd_3:1;
+                u64 i_err_type:4;
+                u64 i_rsvd_2:4;
+                u64 i_overrun:1;
+                u64 i_rsvd_1:3;
+                u64 i_valid:1;
+                u64 i_rsvd:13;
+        } ii_iieph1_fld_s;
+} ii_iieph1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register holds the Address field from the header flit of an    *
+ * incoming erroneous Duplonet packet, along with the tail bit which    *
+ * accompanied this header flit. This register is essentially an        *
+ * extension of IIEPH1. Two registers were necessary because the 64     *
+ * bits available in only a single register were insufficient to        *
+ * capture the entire header flit of an erroneous packet.               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph2_u {
+        u64 ii_iieph2_regval;
+        struct {
+                u64 i_rsvd_0:3;
+                u64 i_address:47;
+                u64 i_rsvd_1:10;
+                u64 i_tail:1;
+                u64 i_rsvd:3;
+        } ii_iieph2_fld_s;
+} ii_iieph2_u_t;
+
+/******************************/
+
+/************************************************************************
+ *                                                                      *
+ *  This register's value is a bit vector that guards access from SXBs  *
+ * to local registers within the II as well as to external Crosstalk    *
+ * widgets                                                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapr_u {
+        u64 ii_islapr_regval;
+        struct {
+                u64 i_region:64;
+        } ii_islapr_fld_s;
+} ii_islapr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register of the 56-bit value "Pup+Bun" will cause   *
+ * the bit in the ISLAPR register corresponding to the region of the    *
+ * requestor to be set (access allowed).                                (
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapo_u {
+        u64 ii_islapo_regval;
+        struct {
+                u64 i_io_sbx_ovrride:56;
+                u64 i_rsvd:8;
+        } ii_islapo_fld_s;
+} ii_islapo_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Determines how long the wrapper will wait aftr an interrupt is      *
+ * initially issued from the II before it times out the outstanding     *
+ * interrupt and drops it from the interrupt queue.                     * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwi_u {
+        u64 ii_iwi_regval;
+        struct {
+                u64 i_prescale:24;
+                u64 i_rsvd:8;
+                u64 i_timeout:8;
+                u64 i_rsvd1:8;
+                u64 i_intrpt_retry_period:8;
+                u64 i_rsvd2:8;
+        } ii_iwi_fld_s;
+} ii_iwi_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Log errors which have occurred in the II wrapper. The errors are    *
+ * cleared by writing to the IECLR register.                            * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwel_u {
+        u64 ii_iwel_regval;
+        struct {
+                u64 i_intr_timed_out:1;
+                u64 i_rsvd:7;
+                u64 i_cam_overflow:1;
+                u64 i_cam_read_miss:1;
+                u64 i_rsvd1:2;
+                u64 i_ioq_rep_underflow:1;
+                u64 i_ioq_req_underflow:1;
+                u64 i_ioq_rep_overflow:1;
+                u64 i_ioq_req_overflow:1;
+                u64 i_iiq_rep_overflow:1;
+                u64 i_iiq_req_overflow:1;
+                u64 i_rsvd2:6;
+                u64 i_ii_xn_rep_cred_over_under:1;
+                u64 i_ii_xn_req_cred_over_under:1;
+                u64 i_rsvd3:6;
+                u64 i_ii_xn_invalid_cmd:1;
+                u64 i_xn_ii_invalid_cmd:1;
+                u64 i_rsvd4:30;
+        } ii_iwel_fld_s;
+} ii_iwel_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Controls the II wrapper.                                            * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwc_u {
+        u64 ii_iwc_regval;
+        struct {
+                u64 i_dma_byte_swap:1;
+                u64 i_rsvd:3;
+                u64 i_cam_read_lines_reset:1;
+                u64 i_rsvd1:3;
+                u64 i_ii_xn_cred_over_under_log:1;
+                u64 i_rsvd2:19;
+                u64 i_xn_rep_iq_depth:5;
+                u64 i_rsvd3:3;
+                u64 i_xn_req_iq_depth:5;
+                u64 i_rsvd4:3;
+                u64 i_iiq_depth:6;
+                u64 i_rsvd5:12;
+                u64 i_force_rep_cred:1;
+                u64 i_force_req_cred:1;
+        } ii_iwc_fld_s;
+} ii_iwc_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Status in the II wrapper.                                           * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iws_u {
+        u64 ii_iws_regval;
+        struct {
+                u64 i_xn_rep_iq_credits:5;
+                u64 i_rsvd:3;
+                u64 i_xn_req_iq_credits:5;
+                u64 i_rsvd1:51;
+        } ii_iws_fld_s;
+} ii_iws_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Masks errors in the IWEL register.                                  *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iweim_u {
+        u64 ii_iweim_regval;
+        struct {
+                u64 i_intr_timed_out:1;
+                u64 i_rsvd:7;
+                u64 i_cam_overflow:1;
+                u64 i_cam_read_miss:1;
+                u64 i_rsvd1:2;
+                u64 i_ioq_rep_underflow:1;
+                u64 i_ioq_req_underflow:1;
+                u64 i_ioq_rep_overflow:1;
+                u64 i_ioq_req_overflow:1;
+                u64 i_iiq_rep_overflow:1;
+                u64 i_iiq_req_overflow:1;
+                u64 i_rsvd2:6;
+                u64 i_ii_xn_rep_cred_overflow:1;
+                u64 i_ii_xn_req_cred_overflow:1;
+                u64 i_rsvd3:6;
+                u64 i_ii_xn_invalid_cmd:1;
+                u64 i_xn_ii_invalid_cmd:1;
+                u64 i_rsvd4:30;
+        } ii_iweim_fld_s;
+} ii_iweim_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a particular field in the           *
+ * corresponding widget's PRB entry to be adjusted up or down by 1.     *
+ * This counter should be used when recovering from error and reset     *
+ * conditions. Note that software would be capable of causing           *
+ * inadvertent overflow or underflow of these counters.                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipca_u {
+        u64 ii_ipca_regval;
+        struct {
+                u64 i_wid:4;
+                u64 i_adjust:1;
+                u64 i_rsvd_1:3;
+                u64 i_field:2;
+                u64 i_rsvd:54;
+        } ii_ipca_fld_s;
+} ii_ipca_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte0a_u {
+        u64 ii_iprte0a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprte0a_fld_s;
+} ii_iprte0a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1a_u {
+        u64 ii_iprte1a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprte1a_fld_s;
+} ii_iprte1a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2a_u {
+        u64 ii_iprte2a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprte2a_fld_s;
+} ii_iprte2a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3a_u {
+        u64 ii_iprte3a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprte3a_fld_s;
+} ii_iprte3a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4a_u {
+        u64 ii_iprte4a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprte4a_fld_s;
+} ii_iprte4a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5a_u {
+        u64 ii_iprte5a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprte5a_fld_s;
+} ii_iprte5a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6a_u {
+        u64 ii_iprte6a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprte6a_fld_s;
+} ii_iprte6a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7a_u {
+        u64 ii_iprte7a_regval;
+        struct {
+                u64 i_rsvd_1:54;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } ii_iprtea7_fld_s;
+} ii_iprte7a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte0b_u {
+        u64 ii_iprte0b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+        } ii_iprte0b_fld_s;
+} ii_iprte0b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1b_u {
+        u64 ii_iprte1b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+        } ii_iprte1b_fld_s;
+} ii_iprte1b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2b_u {
+        u64 ii_iprte2b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+        } ii_iprte2b_fld_s;
+} ii_iprte2b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3b_u {
+        u64 ii_iprte3b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+        } ii_iprte3b_fld_s;
+} ii_iprte3b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4b_u {
+        u64 ii_iprte4b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+        } ii_iprte4b_fld_s;
+} ii_iprte4b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5b_u {
+        u64 ii_iprte5b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+        } ii_iprte5b_fld_s;
+} ii_iprte5b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6b_u {
+        u64 ii_iprte6b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+
+        } ii_iprte6b_fld_s;
+} ii_iprte6b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7b_u {
+        u64 ii_iprte7b_regval;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_address:47;
+                u64 i_init:3;
+                u64 i_source:11;
+        } ii_iprte7b_fld_s;
+} ii_iprte7b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  SHub II contains a feature which did not exist in      *
+ * the Hub which automatically cleans up after a Read Response          *
+ * timeout, including deallocation of the IPRTE and recovery of IBuf    *
+ * space. The inclusion of this register in SHub is for backward        *
+ * compatibility                                                        *
+ * A write to this register causes an entry from the table of           *
+ * outstanding PIO Read Requests to be freed and returned to the        *
+ * stack of free entries. This register is used in handling the         *
+ * timeout errors that result in a PIO Reply never returning from       *
+ * Crosstalk.                                                           *
+ * Note that this register does not affect the contents of the IPRTE    *
+ * registers. The Valid bits in those registers have to be              *
+ * specifically turned off by software.                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipdr_u {
+        u64 ii_ipdr_regval;
+        struct {
+                u64 i_te:3;
+                u64 i_rsvd_1:1;
+                u64 i_pnd:1;
+                u64 i_init_rpcnt:1;
+                u64 i_rsvd:58;
+        } ii_ipdr_fld_s;
+} ii_ipdr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a CRB entry to be returned to the   *
+ * queue of free CRBs. The entry should have previously been cleared    *
+ * (mark bit) via backdoor access to the pertinent CRB entry. This      *
+ * register is used in the last step of handling the errors that are    *
+ * captured and marked in CRB entries.  Briefly: 1) first error for     *
+ * DMA write from a particular device, and first error for a            *
+ * particular BTE stream, lead to a marked CRB entry, and processor     *
+ * interrupt, 2) software reads the error information captured in the   *
+ * CRB entry, and presumably takes some corrective action, 3)           *
+ * software clears the mark bit, and finally 4) software writes to      *
+ * the ICDR register to return the CRB entry to the list of free CRB    *
+ * entries.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icdr_u {
+        u64 ii_icdr_regval;
+        struct {
+                u64 i_crb_num:4;
+                u64 i_pnd:1;
+                u64 i_rsvd:59;
+        } ii_icdr_fld_s;
+} ii_icdr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register provides debug access to two FIFOs inside of II.      *
+ * Both IOQ_MAX* fields of this register contain the instantaneous      *
+ * depth (in units of the number of available entries) of the           *
+ * associated IOQ FIFO.  A read of this register will return the        *
+ * number of free entries on each FIFO at the time of the read.  So     *
+ * when a FIFO is idle, the associated field contains the maximum       *
+ * depth of the FIFO.  This register is writable for debug reasons      *
+ * and is intended to be written with the maximum desired FIFO depth    *
+ * while the FIFO is idle. Software must assure that II is idle when    *
+ * this register is written. If there are any active entries in any     *
+ * of these FIFOs when this register is written, the results are        *
+ * undefined.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ifdr_u {
+        u64 ii_ifdr_regval;
+        struct {
+                u64 i_ioq_max_rq:7;
+                u64 i_set_ioq_rq:1;
+                u64 i_ioq_max_rp:7;
+                u64 i_set_ioq_rp:1;
+                u64 i_rsvd:48;
+        } ii_ifdr_fld_s;
+} ii_ifdr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the II to become sluggish in removing          *
+ * messages from its inbound queue (IIQ). This will cause messages to   *
+ * back up in either virtual channel. Disabling the "molasses" mode     *
+ * subsequently allows the II to be tested under stress. In the         *
+ * sluggish ("Molasses") mode, the localized effects of congestion      *
+ * can be observed.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiap_u {
+        u64 ii_iiap_regval;
+        struct {
+                u64 i_rq_mls:6;
+                u64 i_rsvd_1:2;
+                u64 i_rp_mls:6;
+                u64 i_rsvd:50;
+        } ii_iiap_fld_s;
+} ii_iiap_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows several parameters of CRB operation to be      *
+ * set. Note that writing to this register can have catastrophic side   *
+ * effects, if the CRB is not quiescent, i.e. if the CRB is             *
+ * processing protocol messages when the write occurs.                  *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icmr_u {
+        u64 ii_icmr_regval;
+        struct {
+                u64 i_sp_msg:1;
+                u64 i_rd_hdr:1;
+                u64 i_rsvd_4:2;
+                u64 i_c_cnt:4;
+                u64 i_rsvd_3:4;
+                u64 i_clr_rqpd:1;
+                u64 i_clr_rppd:1;
+                u64 i_rsvd_2:2;
+                u64 i_fc_cnt:4;
+                u64 i_crb_vld:15;
+                u64 i_crb_mark:15;
+                u64 i_rsvd_1:2;
+                u64 i_precise:1;
+                u64 i_rsvd:11;
+        } ii_icmr_fld_s;
+} ii_icmr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows control of the table portion of the CRB        *
+ * logic via software. Control operations from this register have       *
+ * priority over all incoming Crosstalk or BTE requests.                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iccr_u {
+        u64 ii_iccr_regval;
+        struct {
+                u64 i_crb_num:4;
+                u64 i_rsvd_1:4;
+                u64 i_cmd:8;
+                u64 i_pending:1;
+                u64 i_rsvd:47;
+        } ii_iccr_fld_s;
+} ii_iccr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the maximum timeout value to be programmed.    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icto_u {
+        u64 ii_icto_regval;
+        struct {
+                u64 i_timeout:8;
+                u64 i_rsvd:56;
+        } ii_icto_fld_s;
+} ii_icto_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the timeout prescalar to be programmed. An     *
+ * internal counter is associated with this register. When the          *
+ * internal counter reaches the value of the PRESCALE field, the        *
+ * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
+ * field). The internal counter resets to zero, and then continues      *
+ * counting.                                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ictp_u {
+        u64 ii_ictp_regval;
+        struct {
+                u64 i_prescale:24;
+                u64 i_rsvd:40;
+        } ii_ictp_fld_s;
+} ii_ictp_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ * The CRB Entry registers can be conceptualized as rows and columns    *
+ * (illustrated in the table above). Each row contains the 4            *
+ * registers required for a single CRB Entry. The first doubleword      *
+ * (column) for each entry is labeled A, and the second doubleword      *
+ * (higher address) is labeled B, the third doubleword is labeled C,    *
+ * the fourth doubleword is labeled D and the fifth doubleword is       *
+ * labeled E. All CRB entries have their addresses on a quarter         *
+ * cacheline aligned boundary.                   *
+ * Upon reset, only the following fields are initialized: valid         *
+ * (VLD), priority count, timeout, timeout valid, and context valid.    *
+ * All other bits should be cleared by software before use (after       *
+ * recovering any potential error state from before the reset).         *
+ * The following four tables summarize the format for the four          *
+ * registers that are used for each ICRB# Entry.                        *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_a_u {
+        u64 ii_icrb0_a_regval;
+        struct {
+                u64 ia_iow:1;
+                u64 ia_vld:1;
+                u64 ia_addr:47;
+                u64 ia_tnum:5;
+                u64 ia_sidn:4;
+                u64 ia_rsvd:6;
+        } ii_icrb0_a_fld_s;
+} ii_icrb0_a_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_b_u {
+        u64 ii_icrb0_b_regval;
+        struct {
+                u64 ib_xt_err:1;
+                u64 ib_mark:1;
+                u64 ib_ln_uce:1;
+                u64 ib_errcode:3;
+                u64 ib_error:1;
+                u64 ib_stall__bte_1:1;
+                u64 ib_stall__bte_0:1;
+                u64 ib_stall__intr:1;
+                u64 ib_stall_ib:1;
+                u64 ib_intvn:1;
+                u64 ib_wb:1;
+                u64 ib_hold:1;
+                u64 ib_ack:1;
+                u64 ib_resp:1;
+                u64 ib_ack_cnt:11;
+                u64 ib_rsvd:7;
+                u64 ib_exc:5;
+                u64 ib_init:3;
+                u64 ib_imsg:8;
+                u64 ib_imsgtype:2;
+                u64 ib_use_old:1;
+                u64 ib_rsvd_1:11;
+        } ii_icrb0_b_fld_s;
+} ii_icrb0_b_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_c_u {
+        u64 ii_icrb0_c_regval;
+        struct {
+                u64 ic_source:15;
+                u64 ic_size:2;
+                u64 ic_ct:1;
+                u64 ic_bte_num:1;
+                u64 ic_gbr:1;
+                u64 ic_resprqd:1;
+                u64 ic_bo:1;
+                u64 ic_suppl:15;
+                u64 ic_rsvd:27;
+        } ii_icrb0_c_fld_s;
+} ii_icrb0_c_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_d_u {
+        u64 ii_icrb0_d_regval;
+        struct {
+                u64 id_pa_be:43;
+                u64 id_bte_op:1;
+                u64 id_pr_psc:4;
+                u64 id_pr_cnt:4;
+                u64 id_sleep:1;
+                u64 id_rsvd:11;
+        } ii_icrb0_d_fld_s;
+} ii_icrb0_d_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_e_u {
+        u64 ii_icrb0_e_regval;
+        struct {
+                u64 ie_timeout:8;
+                u64 ie_context:15;
+                u64 ie_rsvd:1;
+                u64 ie_tvld:1;
+                u64 ie_cvld:1;
+                u64 ie_rsvd_0:38;
+        } ii_icrb0_e_fld_s;
+} ii_icrb0_e_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the lower 64 bits of the header of the       *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsml_u {
+        u64 ii_icsml_regval;
+        struct {
+                u64 i_tt_addr:47;
+                u64 i_newsuppl_ex:14;
+                u64 i_reserved:2;
+                u64 i_overflow:1;
+        } ii_icsml_fld_s;
+} ii_icsml_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the middle 64 bits of the header of the      *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmm_u {
+        u64 ii_icsmm_regval;
+        struct {
+                u64 i_tt_ack_cnt:11;
+                u64 i_reserved:53;
+        } ii_icsmm_fld_s;
+} ii_icsmm_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the microscopic state, all the inputs to     *
+ * the protocol table, captured with the spurious message. Valid when   *
+ * the SP_MSG bit in the ICMR register is set.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmh_u {
+        u64 ii_icsmh_regval;
+        struct {
+                u64 i_tt_vld:1;
+                u64 i_xerr:1;
+                u64 i_ft_cwact_o:1;
+                u64 i_ft_wact_o:1;
+                u64 i_ft_active_o:1;
+                u64 i_sync:1;
+                u64 i_mnusg:1;
+                u64 i_mnusz:1;
+                u64 i_plusz:1;
+                u64 i_plusg:1;
+                u64 i_tt_exc:5;
+                u64 i_tt_wb:1;
+                u64 i_tt_hold:1;
+                u64 i_tt_ack:1;
+                u64 i_tt_resp:1;
+                u64 i_tt_intvn:1;
+                u64 i_g_stall_bte1:1;
+                u64 i_g_stall_bte0:1;
+                u64 i_g_stall_il:1;
+                u64 i_g_stall_ib:1;
+                u64 i_tt_imsg:8;
+                u64 i_tt_imsgtype:2;
+                u64 i_tt_use_old:1;
+                u64 i_tt_respreqd:1;
+                u64 i_tt_bte_num:1;
+                u64 i_cbn:1;
+                u64 i_match:1;
+                u64 i_rpcnt_lt_34:1;
+                u64 i_rpcnt_ge_34:1;
+                u64 i_rpcnt_lt_18:1;
+                u64 i_rpcnt_ge_18:1;
+                u64 i_rpcnt_lt_2:1;
+                u64 i_rpcnt_ge_2:1;
+                u64 i_rqcnt_lt_18:1;
+                u64 i_rqcnt_ge_18:1;
+                u64 i_rqcnt_lt_2:1;
+                u64 i_rqcnt_ge_2:1;
+                u64 i_tt_device:7;
+                u64 i_tt_init:3;
+                u64 i_reserved:5;
+        } ii_icsmh_fld_s;
+} ii_icsmh_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
+ * II core and a 3-bit selection signal to the fsbclk domain in the II  *
+ * wrapper.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_idbss_u {
+        u64 ii_idbss_regval;
+        struct {
+                u64 i_iioclk_core_submenu:3;
+                u64 i_rsvd:5;
+                u64 i_fsbclk_wrapper_submenu:3;
+                u64 i_rsvd_1:5;
+                u64 i_iioclk_menu:5;
+                u64 i_rsvd_2:43;
+        } ii_idbss_fld_s;
+} ii_idbss_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls0_u {
+        u64 ii_ibls0_regval;
+        struct {
+                u64 i_length:16;
+                u64 i_error:1;
+                u64 i_rsvd_1:3;
+                u64 i_busy:1;
+                u64 i_rsvd:43;
+        } ii_ibls0_fld_s;
+} ii_ibls0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa0_u {
+        u64 ii_ibsa0_regval;
+        struct {
+                u64 i_rsvd_1:7;
+                u64 i_addr:42;
+                u64 i_rsvd:15;
+        } ii_ibsa0_fld_s;
+} ii_ibsa0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda0_u {
+        u64 ii_ibda0_regval;
+        struct {
+                u64 i_rsvd_1:7;
+                u64 i_addr:42;
+                u64 i_rsvd:15;
+        } ii_ibda0_fld_s;
+} ii_ibda0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct0_u {
+        u64 ii_ibct0_regval;
+        struct {
+                u64 i_zerofill:1;
+                u64 i_rsvd_2:3;
+                u64 i_notify:1;
+                u64 i_rsvd_1:3;
+                u64 i_poison:1;
+                u64 i_rsvd:55;
+        } ii_ibct0_fld_s;
+} ii_ibct0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna0_u {
+        u64 ii_ibna0_regval;
+        struct {
+                u64 i_rsvd_1:7;
+                u64 i_addr:42;
+                u64 i_rsvd:15;
+        } ii_ibna0_fld_s;
+} ii_ibna0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia0_u {
+        u64 ii_ibia0_regval;
+        struct {
+                u64 i_rsvd_2:1;
+                u64 i_node_id:11;
+                u64 i_rsvd_1:4;
+                u64 i_level:7;
+                u64 i_rsvd:41;
+        } ii_ibia0_fld_s;
+} ii_ibia0_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls1_u {
+        u64 ii_ibls1_regval;
+        struct {
+                u64 i_length:16;
+                u64 i_error:1;
+                u64 i_rsvd_1:3;
+                u64 i_busy:1;
+                u64 i_rsvd:43;
+        } ii_ibls1_fld_s;
+} ii_ibls1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa1_u {
+        u64 ii_ibsa1_regval;
+        struct {
+                u64 i_rsvd_1:7;
+                u64 i_addr:33;
+                u64 i_rsvd:24;
+        } ii_ibsa1_fld_s;
+} ii_ibsa1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda1_u {
+        u64 ii_ibda1_regval;
+        struct {
+                u64 i_rsvd_1:7;
+                u64 i_addr:33;
+                u64 i_rsvd:24;
+        } ii_ibda1_fld_s;
+} ii_ibda1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct1_u {
+        u64 ii_ibct1_regval;
+        struct {
+                u64 i_zerofill:1;
+                u64 i_rsvd_2:3;
+                u64 i_notify:1;
+                u64 i_rsvd_1:3;
+                u64 i_poison:1;
+                u64 i_rsvd:55;
+        } ii_ibct1_fld_s;
+} ii_ibct1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna1_u {
+        u64 ii_ibna1_regval;
+        struct {
+                u64 i_rsvd_1:7;
+                u64 i_addr:33;
+                u64 i_rsvd:24;
+        } ii_ibna1_fld_s;
+} ii_ibna1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia1_u {
+        u64 ii_ibia1_regval;
+        struct {
+                u64 i_pi_id:1;
+                u64 i_node_id:8;
+                u64 i_rsvd_1:7;
+                u64 i_level:7;
+                u64 i_rsvd:41;
+        } ii_ibia1_fld_s;
+} ii_ibia1_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  This register defines the resources that feed information into      *
+ * the two performance counters located in the IO Performance           *
+ * Profiling Register. There are 17 different quantities that can be    *
+ * measured. Given these 17 different options, the two performance      *
+ * counters have 15 of them in common; menu selections 0 through 0xE    *
+ * are identical for each performance counter. As for the other two     *
+ * options, one is available from one performance counter and the       *
+ * other is available from the other performance counter. Hence, the    *
+ * II supports all 17*16=272 possible combinations of quantities to     *
+ * measure.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipcr_u {
+        u64 ii_ipcr_regval;
+        struct {
+                u64 i_ippr0_c:4;
+                u64 i_ippr1_c:4;
+                u64 i_icct:8;
+                u64 i_rsvd:48;
+        } ii_ipcr_fld_s;
+} ii_ipcr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ippr_u {
+        u64 ii_ippr_regval;
+        struct {
+                u64 i_ippr0:32;
+                u64 i_ippr1:32;
+        } ii_ippr_fld_s;
+} ii_ippr_u_t;
+
+/************************************************************************
+ *                                                                      *
+ * The following defines which were not formed into structures are      *
+ * probably indentical to another register, and the name of the         *
+ * register is provided against each of these registers. This           *
+ * information needs to be checked carefully                            *
+ *                                                                      *
+ *              IIO_ICRB1_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB1_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB1_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB1_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB1_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB2_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB2_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB2_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB2_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB2_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB3_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB3_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB3_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB3_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB3_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB4_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB4_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB4_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB4_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB4_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB5_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB5_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB5_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB5_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB5_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB6_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB6_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB6_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB6_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB6_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB7_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB7_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB7_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB7_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB7_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB8_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB8_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB8_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB8_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB8_E             IIO_ICRB0_E                     *
+ *              IIO_ICRB9_A             IIO_ICRB0_A                     *
+ *              IIO_ICRB9_B             IIO_ICRB0_B                     *
+ *              IIO_ICRB9_C             IIO_ICRB0_C                     *
+ *              IIO_ICRB9_D             IIO_ICRB0_D                     *
+ *              IIO_ICRB9_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBA_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBA_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBA_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBA_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBA_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBB_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBB_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBB_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBB_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBB_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBC_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBC_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBC_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBC_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBC_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBD_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBD_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBD_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBD_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBD_E             IIO_ICRB0_E                     *
+ *              IIO_ICRBE_A             IIO_ICRB0_A                     *
+ *              IIO_ICRBE_B             IIO_ICRB0_B                     *
+ *              IIO_ICRBE_C             IIO_ICRB0_C                     *
+ *              IIO_ICRBE_D             IIO_ICRB0_D                     *
+ *              IIO_ICRBE_E             IIO_ICRB0_E                     *
+ *                                                                      *
+ ************************************************************************/
+
+/*
+ * Slightly friendlier names for some common registers.
+ */
+#define IIO_WIDGET              IIO_WID         /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT       /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR         /* Widget control register */
+#define IIO_PROTECT             IIO_ILAPR       /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO       /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA        /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA        /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM       /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR       /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR        /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC        /* Xtalk credit count timeout */
+#define IIO_XTALKTT_TOUT        IIO_IXTT        /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR       /* IO error clear */
+#define IIO_IGFX_0              IIO_IGFX0
+#define IIO_IGFX_1              IIO_IGFX1
+#define IIO_IBCT_0              IIO_IBCT0
+#define IIO_IBCT_1              IIO_IBCT1
+#define IIO_IBLS_0              IIO_IBLS0
+#define IIO_IBLS_1              IIO_IBLS1
+#define IIO_IBSA_0              IIO_IBSA0
+#define IIO_IBSA_1              IIO_IBSA1
+#define IIO_IBDA_0              IIO_IBDA0
+#define IIO_IBDA_1              IIO_IBDA1
+#define IIO_IBNA_0              IIO_IBNA0
+#define IIO_IBNA_1              IIO_IBNA1
+#define IIO_IBIA_0              IIO_IBIA0
+#define IIO_IBIA_1              IIO_IBIA1
+#define IIO_IOPRB_0             IIO_IPRB0
+
+#define IIO_PRTE_A(_x)          (IIO_IPRTE0_A + (8 * (_x)))
+#define IIO_PRTE_B(_x)          (IIO_IPRTE0_B + (8 * (_x)))
+#define IIO_NUM_PRTES           8       /* Total number of PRB table entries */
+#define IIO_WIDPRTE_A(x)        IIO_PRTE_A(((x) - 8))   /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_B(x)        IIO_PRTE_B(((x) - 8))   /* widget ID to its PRTE num */
+
+#define IIO_NUM_IPRBS           9
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+#define IIO_LLP_CB_MAX  0xffff  /* in ILLR CB_CNT, Max Check Bit errors */
+#define IIO_LLP_SN_MAX  0xffff  /* in ILLR SN_CNT, Max Sequence Number errors */
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0      /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0      /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0      /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0      /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0      /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0      /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0       /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1           (IIO_IBLS_1 - IIO_IBLS_0)       /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+/* names used in shub diags */
+#define IIO_BASE_BTE0   IIO_IBLS_0
+#define IIO_BASE_BTE1   IIO_IBLS_1
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK     ((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT    0
+#define IIO_IGFX_PI_NUM_BITS    1       /* size of PI num field */
+#define IIO_IGFX_PI_NUM_MASK    ((1<<IIO_IGFX_PI_NUM_BITS)-1)
+#define IIO_IGFX_PI_NUM_SHIFT   4
+#define IIO_IGFX_N_NUM_BITS     8       /* size of node num field */
+#define IIO_IGFX_N_NUM_MASK     ((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT    5
+#define IIO_IGFX_P_NUM_BITS     1       /* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK     ((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT    16
+#define IIO_IGFX_INIT(widget, pi, node, cpu)                            (\
+        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
+        (((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|     \
+        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
+        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
+
+/* Scratch registers (all bits available) */
+#define IIO_SCRATCH_REG0        IIO_ISCR0
+#define IIO_SCRATCH_REG1        IIO_ISCR1
+#define IIO_SCRATCH_MASK        0xffffffffffffffffUL
+
+#define IIO_SCRATCH_BIT0_0      0x0000000000000001UL
+#define IIO_SCRATCH_BIT0_1      0x0000000000000002UL
+#define IIO_SCRATCH_BIT0_2      0x0000000000000004UL
+#define IIO_SCRATCH_BIT0_3      0x0000000000000008UL
+#define IIO_SCRATCH_BIT0_4      0x0000000000000010UL
+#define IIO_SCRATCH_BIT0_5      0x0000000000000020UL
+#define IIO_SCRATCH_BIT0_6      0x0000000000000040UL
+#define IIO_SCRATCH_BIT0_7      0x0000000000000080UL
+#define IIO_SCRATCH_BIT0_8      0x0000000000000100UL
+#define IIO_SCRATCH_BIT0_9      0x0000000000000200UL
+#define IIO_SCRATCH_BIT0_A      0x0000000000000400UL
+
+#define IIO_SCRATCH_BIT1_0      0x0000000000000001UL
+#define IIO_SCRATCH_BIT1_1      0x0000000000000002UL
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7       /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1UL   /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1UL << 4)      /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1UL << 8)      /* BTE 1 Shut down due to error */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the shub, we've
+ * redefined big window 7 as small window 0.
+ XXX does this still apply for SN1??
+ */
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              IIO_ICRB0_A
+#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
+#define IIO_ICRB_B(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
+#define IIO_ICRB_C(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
+#define IIO_ICRB_D(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
+#define IIO_ICRB_E(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
+
+#define TNUM_TO_WIDGET_DEV(_tnum)       (_tnum & 0x7)
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read  */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message from SN1 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN1NET    0x2     /* Message originated in SN1net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define            HUBII_XBOW_CREDIT       3
+#define            HUBII_XBOW_REV2_CREDIT  4
+
+/*
+ * Number of credits that xtalk devices should use when communicating
+ * with a SHub (depth of SHub's queue).
+ */
+#define HUB_CREDIT 4
+
+/*
+ * Some IIO_PRB fields
+ */
+#define IIO_PRB_MULTI_ERR       (1LL << 63)
+#define IIO_PRB_SPUR_RD         (1LL << 51)
+#define IIO_PRB_SPUR_WR         (1LL << 50)
+#define IIO_PRB_RD_TO           (1LL << 49)
+#define IIO_PRB_ERROR           (1LL << 48)
+
+/*************************************************************************
+
+ Some of the IIO field masks and shifts are defined here.
+ This is in order to maintain compatibility in SN0 and SN1 code
+ 
+**************************************************************************/
+
+/*
+ * ICMR register fields
+ * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
+ * present in SHub)
+ */
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ XXX present but not needed in bedrock?  See the manual.
+ */
+#define IIO_IPDR_PND            (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND            (1 << 4)
+
+/* 
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY               (0x1UL << 20)
+#define IBLS_ERROR_SHFT         16
+#define IBLS_ERROR              (0x1UL << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK        0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON             (0x1UL << 8)
+#define IBCT_NOTIFY             (0x1UL << 4)
+#define IBCT_ZFIL_MODE          (0x1UL << 0)
+
+/*
+ * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
+ */
+#define IIEPH1_VALID            (1UL << 44)
+#define IIEPH1_OVERRUN          (1UL << 40)
+#define IIEPH1_ERR_TYPE_SHFT    32
+#define IIEPH1_ERR_TYPE_MASK    0xf
+#define IIEPH1_SOURCE_SHFT      20
+#define IIEPH1_SOURCE_MASK      11
+#define IIEPH1_SUPPL_SHFT       8
+#define IIEPH1_SUPPL_MASK       11
+#define IIEPH1_CMD_SHFT         0
+#define IIEPH1_CMD_MASK         7
+
+#define IIEPH2_TAIL             (1UL << 40)
+#define IIEPH2_ADDRESS_SHFT     0
+#define IIEPH2_ADDRESS_MASK     38
+
+#define IIEPH1_ERR_SHORT_REQ    2
+#define IIEPH1_ERR_SHORT_REPLY  3
+#define IIEPH1_ERR_LONG_REQ     4
+#define IIEPH1_ERR_LONG_REPLY   5
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_PI1_FWD_INT       (1UL << 31)     /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT       (1UL << 30)     /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR       (1UL << 29)     /* clear valid bit in ixss reg */
+#define IECLR_BTE1              (1UL << 18)     /* clear bte error 1 */
+#define IECLR_BTE0              (1UL << 17)     /* clear bte error 0 */
+#define IECLR_CRAZY             (1UL << 16)     /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F             (1UL << 15)     /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E             (1UL << 14)     /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D             (1UL << 13)     /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C             (1UL << 12)     /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B             (1UL << 11)     /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A             (1UL << 10)     /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9             (1UL << 9)      /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8             (1UL << 8)      /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0             (1UL << 0)      /* clear err bit in PRB_0 reg */
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR 
+ */
+#define IIO_ICCR_PENDING        0x10000
+#define IIO_ICCR_CMD_MASK       0xFF
+#define IIO_ICCR_CMD_SHFT       7
+#define IIO_ICCR_CMD_NOP        0x0     /* No Op */
+#define IIO_ICCR_CMD_WAKE       0x100   /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    0x200   /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      0x400   /* Contents of entry written to memory
+                                         * via a WB
+                                         */
+#define IIO_ICCR_CMD_FLUSH      0x800
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to shub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+/*
+ * Easy access macros for CRBs, all 5 registers (A-E)
+ */
+typedef ii_icrb0_a_u_t icrba_t;
+#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
+#define a_addr          ii_icrb0_a_fld_s.ia_addr
+#define a_valid         ii_icrb0_a_fld_s.ia_vld
+#define a_iow           ii_icrb0_a_fld_s.ia_iow
+#define a_regvalue      ii_icrb0_a_regval
+
+typedef ii_icrb0_b_u_t icrbb_t;
+#define b_use_old       ii_icrb0_b_fld_s.ib_use_old
+#define b_imsgtype      ii_icrb0_b_fld_s.ib_imsgtype
+#define b_imsg          ii_icrb0_b_fld_s.ib_imsg
+#define b_initiator     ii_icrb0_b_fld_s.ib_init
+#define b_exc           ii_icrb0_b_fld_s.ib_exc
+#define b_ackcnt        ii_icrb0_b_fld_s.ib_ack_cnt
+#define b_resp          ii_icrb0_b_fld_s.ib_resp
+#define b_ack           ii_icrb0_b_fld_s.ib_ack
+#define b_hold          ii_icrb0_b_fld_s.ib_hold
+#define b_wb            ii_icrb0_b_fld_s.ib_wb
+#define b_intvn         ii_icrb0_b_fld_s.ib_intvn
+#define b_stall_ib      ii_icrb0_b_fld_s.ib_stall_ib
+#define b_stall_int     ii_icrb0_b_fld_s.ib_stall__intr
+#define b_stall_bte_0   ii_icrb0_b_fld_s.ib_stall__bte_0
+#define b_stall_bte_1   ii_icrb0_b_fld_s.ib_stall__bte_1
+#define b_error         ii_icrb0_b_fld_s.ib_error
+#define b_ecode         ii_icrb0_b_fld_s.ib_errcode
+#define b_lnetuce       ii_icrb0_b_fld_s.ib_ln_uce
+#define b_mark          ii_icrb0_b_fld_s.ib_mark
+#define b_xerr          ii_icrb0_b_fld_s.ib_xt_err
+#define b_regvalue      ii_icrb0_b_regval
+
+typedef ii_icrb0_c_u_t icrbc_t;
+#define c_suppl         ii_icrb0_c_fld_s.ic_suppl
+#define c_barrop        ii_icrb0_c_fld_s.ic_bo
+#define c_doresp        ii_icrb0_c_fld_s.ic_resprqd
+#define c_gbr           ii_icrb0_c_fld_s.ic_gbr
+#define c_btenum        ii_icrb0_c_fld_s.ic_bte_num
+#define c_cohtrans      ii_icrb0_c_fld_s.ic_ct
+#define c_xtsize        ii_icrb0_c_fld_s.ic_size
+#define c_source        ii_icrb0_c_fld_s.ic_source
+#define c_regvalue      ii_icrb0_c_regval
+
+typedef ii_icrb0_d_u_t icrbd_t;
+#define d_sleep         ii_icrb0_d_fld_s.id_sleep
+#define d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt
+#define d_pripsc        ii_icrb0_d_fld_s.id_pr_psc
+#define d_bteop         ii_icrb0_d_fld_s.id_bte_op
+#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be       /* ic_pa_be fld has 2 names */
+#define d_benable       ii_icrb0_d_fld_s.id_pa_be       /* ic_pa_be fld has 2 names */
+#define d_regvalue      ii_icrb0_d_regval
+
+typedef ii_icrb0_e_u_t icrbe_t;
+#define icrbe_ctxtvld   ii_icrb0_e_fld_s.ie_cvld
+#define icrbe_toutvld   ii_icrb0_e_fld_s.ie_tvld
+#define icrbe_context   ii_icrb0_e_fld_s.ie_context
+#define icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout
+#define e_regvalue      ii_icrb0_e_regval
+
+/* Number of widgets supported by shub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc120
+#define MAX_HUBS_PER_XBOW       2
+
+/* A few more #defines for backwards compatibility */
+#define iprb_t          ii_iprb0_u_t
+#define iprb_regval     ii_iprb0_regval
+#define iprb_mult_err   ii_iprb0_fld_s.i_mult_err
+#define iprb_spur_rd    ii_iprb0_fld_s.i_spur_rd
+#define iprb_spur_wr    ii_iprb0_fld_s.i_spur_wr
+#define iprb_rd_to      ii_iprb0_fld_s.i_rd_to
+#define iprb_ovflow     ii_iprb0_fld_s.i_of_cnt
+#define iprb_error      ii_iprb0_fld_s.i_error
+#define iprb_ff         ii_iprb0_fld_s.i_f
+#define iprb_mode       ii_iprb0_fld_s.i_m
+#define iprb_bnakctr    ii_iprb0_fld_s.i_nb
+#define iprb_anakctr    ii_iprb0_fld_s.i_na
+#define iprb_xtalkctr   ii_iprb0_fld_s.i_c
+
+#define LNK_STAT_WORKING        0x2             /* LLP is working */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  0x7F            /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT  16
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                        IIO_WSTAT_TXRETRY_MASK)
+
+/* Number of II perf. counters we can multiplex at once */
+
+#define IO_PERF_SETS    32
+
+/* Bit for the widget in inbound access register */
+#define IIO_IIWA_WIDGET(_w)     ((u64)(1ULL << _w))
+/* Bit for the widget in outbound access register */
+#define IIO_IOWA_WIDGET(_w)     ((u64)(1ULL << _w))
+
+/* NOTE: The following define assumes that we are going to get
+ * widget numbers from 8 thru F and the device numbers within
+ * widget from 0 thru 7.
+ */
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((u64)(1ULL << (8 * ((w) - 8) + (d))))
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x30000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    9
+#define IIO_IIDSR_NODE_MASK     0x000ff700
+#define IIO_IIDSR_PI_ID_SHIFT   8
+#define IIO_IIDSR_PI_ID_MASK    0x00000100
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x000000ff
+
+/* Xtalk timeout threshhold register (IIO_IXTT) */
+#define IXTT_RRSP_TO_SHFT       55      /* read response timeout */
+#define IXTT_RRSP_TO_MASK       (0x1FULL << IXTT_RRSP_TO_SHFT)
+#define IXTT_RRSP_PS_SHFT       32      /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_MASK       (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
+#define IXTT_TAIL_TO_SHFT       0       /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_MASK       (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
+
+/*
+ * The IO LLP control status register and widget control register
+ */
+
+typedef union hubii_wcr_u {
+        u64 wcr_reg_value;
+        struct {
+                u64 wcr_widget_id:4,    /* LLP crossbar credit */
+                 wcr_tag_mode:1,        /* Tag mode */
+                 wcr_rsvd1:8,   /* Reserved */
+                 wcr_xbar_crd:3,        /* LLP crossbar credit */
+                 wcr_f_bad_pkt:1,       /* Force bad llp pkt enable */
+                 wcr_dir_con:1, /* widget direct connect */
+                 wcr_e_thresh:5,        /* elasticity threshold */
+                 wcr_rsvd:41;   /* unused */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+
+typedef union io_perf_sel {
+        u64 perf_sel_reg;
+        struct {
+                u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the shub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        u64 perf_cnt;
+        struct {
+                u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
+        } perf_cnt_bits;
+
+} io_perf_cnt_t;
+
+typedef union iprte_a {
+        u64 entry;
+        struct {
+                u64 i_rsvd_1:3;
+                u64 i_addr:38;
+                u64 i_init:3;
+                u64 i_source:8;
+                u64 i_rsvd:2;
+                u64 i_widget:4;
+                u64 i_to_cnt:5;
+                u64 i_vld:1;
+        } iprte_fields;
+} iprte_a_t;
+
+#endif                          /* _ASM_IA64_SN_SHUBIO_H */
diff --git a/arch/ia64/include/asm/sn/simulator.h b/arch/ia64/include/asm/sn/simulator.h
new file mode 100644
index 000000000000..c2611f6cfe33
--- /dev/null
+++ b/arch/ia64/include/asm/sn/simulator.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SIMULATOR_H
+#define _ASM_IA64_SN_SIMULATOR_H
+
+#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_SGI_UV)
+#define SNMAGIC 0xaeeeeeee8badbeefL
+#define IS_MEDUSA()                     ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
+
+#define SIMULATOR_SLEEP()               asm("nop.i 0x8beef")
+#define IS_RUNNING_ON_SIMULATOR()       (sn_prom_type)
+#define IS_RUNNING_ON_FAKE_PROM()       (sn_prom_type == 2)
+extern int sn_prom_type;                /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
+#else
+#define IS_MEDUSA()                     0
+#define SIMULATOR_SLEEP()
+#define IS_RUNNING_ON_SIMULATOR()       0
+#endif
+
+#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/arch/ia64/include/asm/sn/sn2/sn_hwperf.h b/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
new file mode 100644
index 000000000000..e61ebac38cdd
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
@@ -0,0 +1,242 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
+ *
+ * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
+ * SGI Altix node and router hardware
+ *
+ * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
+ */
+
+#ifndef SN_HWPERF_H
+#define SN_HWPERF_H
+
+/*
+ * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
+ * return an array of these. Do not change this without also
+ * changing the corresponding SAL code.
+ */
+#define SN_HWPERF_MAXSTRING             128
+struct sn_hwperf_object_info {
+        u32 id;
+        union {
+                struct {
+                        u64 this_part:1;
+                        u64 is_shared:1;
+                } fields;
+                struct {
+                        u64 flags;
+                        u64 reserved;
+                } b;
+        } f;
+        char name[SN_HWPERF_MAXSTRING];
+        char location[SN_HWPERF_MAXSTRING];
+        u32 ports;
+};
+
+#define sn_hwp_this_part        f.fields.this_part
+#define sn_hwp_is_shared        f.fields.is_shared
+#define sn_hwp_flags            f.b.flags
+
+/* macros for object classification */
+#define SN_HWPERF_IS_NODE(x)            ((x) && strstr((x)->name, "SHub"))
+#define SN_HWPERF_IS_NODE_SHUB2(x)      ((x) && strstr((x)->name, "SHub 2."))
+#define SN_HWPERF_IS_IONODE(x)          ((x) && strstr((x)->name, "TIO"))
+#define SN_HWPERF_IS_NL3ROUTER(x)       ((x) && strstr((x)->name, "NL3Router"))
+#define SN_HWPERF_IS_NL4ROUTER(x)       ((x) && strstr((x)->name, "NL4Router"))
+#define SN_HWPERF_IS_OLDROUTER(x)       ((x) && strstr((x)->name, "Router"))
+#define SN_HWPERF_IS_ROUTER(x)          (SN_HWPERF_IS_NL3ROUTER(x) ||           \
+                                                SN_HWPERF_IS_NL4ROUTER(x) ||    \
+                                                SN_HWPERF_IS_OLDROUTER(x))
+#define SN_HWPERF_FOREIGN(x)            ((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
+#define SN_HWPERF_SAME_OBJTYPE(x,y)     ((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
+                                        (SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
+                                        (SN_HWPERF_IS_ROUTER(x) && SN_HWPERF_IS_ROUTER(y)))
+
+/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
+struct sn_hwperf_port_info {
+        u32 port;
+        u32 conn_id;
+        u32 conn_port;
+};
+
+/* for HWPERF_{GET,SET}_MMRS */
+struct sn_hwperf_data {
+        u64 addr;
+        u64 data;
+};
+
+/* user ioctl() argument, see below */
+struct sn_hwperf_ioctl_args {
+        u64 arg;                /* argument, usually an object id */
+        u64 sz;                 /* size of transfer */
+        void *ptr;              /* pointer to source/target */
+        u32 v0;                 /* second return value */
+};
+
+/*
+ * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
+ * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
+ * to call SAL, and whether to use an interprocessor interrupt
+ * or task migration in order to do so. If the CPU specified is
+ * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
+ */
+#define SN_HWPERF_ARG_ANY_CPU           0x7fffffffUL
+#define SN_HWPERF_ARG_CPU_MASK          0x7fffffff00000000ULL
+#define SN_HWPERF_ARG_USE_IPI_MASK      0x8000000000000000ULL
+#define SN_HWPERF_ARG_OBJID_MASK        0x00000000ffffffffULL
+
+/* 
+ * ioctl requests on the "sn_hwperf" misc device that call SAL.
+ */
+#define SN_HWPERF_OP_MEM_COPYIN         0x1000
+#define SN_HWPERF_OP_MEM_COPYOUT        0x2000
+#define SN_HWPERF_OP_MASK               0x0fff
+
+/*
+ * Determine mem requirement.
+ * arg  don't care
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_GET_HEAPSIZE          1
+
+/*
+ * Install mem for SAL drvr
+ * arg  don't care
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to buffer for scratch area
+ */
+#define SN_HWPERF_INSTALL_HEAP          2
+
+/*
+ * Determine number of objects
+ * arg  don't care
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_COUNT          (10|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Determine object "distance", relative to a cpu. This operation can
+ * execute on a designated logical cpu number, using either an IPI or
+ * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg  bitmap of IPI flag, cpu number and object id
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_DISTANCE       (11|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate objects. Special case if sz == 8, returns the required
+ * buffer size.
+ * arg  don't care
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_ENUM_OBJECTS          (12|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate NumaLink ports for an object. Special case if sz == 8,
+ * returns the required buffer size.
+ * arg  object id
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_port_info
+ */
+#define SN_HWPERF_ENUM_PORTS            (13|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * SET/GET memory mapped registers. These operations can execute
+ * on a designated logical cpu number, using either an IPI or via
+ * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg  bitmap of ipi flag, cpu number and object id
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_data
+ */
+#define SN_HWPERF_SET_MMRS              (14|SN_HWPERF_OP_MEM_COPYIN)
+#define SN_HWPERF_GET_MMRS              (15|SN_HWPERF_OP_MEM_COPYOUT| \
+                                            SN_HWPERF_OP_MEM_COPYIN)
+/*
+ * Lock a shared object
+ * arg  object id
+ * sz   don't care
+ * p    don't care
+ */
+#define SN_HWPERF_ACQUIRE               16
+
+/*
+ * Unlock a shared object
+ * arg  object id
+ * sz   don't care
+ * p    don't care
+ */
+#define SN_HWPERF_RELEASE               17
+
+/*
+ * Break a lock on a shared object
+ * arg  object id
+ * sz   don't care
+ * p    don't care
+ */
+#define SN_HWPERF_FORCE_RELEASE         18
+
+/*
+ * ioctl requests on "sn_hwperf" that do not call SAL
+ */
+
+/*
+ * get cpu info as an array of hwperf_object_info_t. 
+ * id is logical CPU number, name is description, location
+ * is geoid (e.g. 001c04#1c). Special case if sz == 8,
+ * returns the required buffer size.
+ *
+ * arg  don't care
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_GET_CPU_INFO          (100|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given an object id, return it's node number (aka cnode).
+ * arg  object id
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_GET_OBJ_NODE          (101|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given a node number (cnode), return it's nasid.
+ * arg  ordinal node number (aka cnodeid)
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_GET_NODE_NASID        (102|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given a node id, determine the id of the nearest node with CPUs
+ * and the id of the nearest node that has memory. The argument
+ * node would normally be a "headless" node, e.g. an "IO node".
+ * Return 0 on success.
+ */
+extern int sn_hwperf_get_nearest_node(cnodeid_t node,
+        cnodeid_t *near_mem, cnodeid_t *near_cpu);
+
+/* return codes */
+#define SN_HWPERF_OP_OK                 0
+#define SN_HWPERF_OP_NOMEM              1
+#define SN_HWPERF_OP_NO_PERM            2
+#define SN_HWPERF_OP_IO_ERROR           3
+#define SN_HWPERF_OP_BUSY               4
+#define SN_HWPERF_OP_RECONFIGURE        253
+#define SN_HWPERF_OP_INVAL              254
+
+int sn_topology_open(struct inode *inode, struct file *file);
+int sn_topology_release(struct inode *inode, struct file *file);
+#endif                          /* SN_HWPERF_H */
diff --git a/arch/ia64/include/asm/sn/sn_cpuid.h b/arch/ia64/include/asm/sn/sn_cpuid.h
new file mode 100644
index 000000000000..a676dd9ace3e
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn_cpuid.h
@@ -0,0 +1,132 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN_CPUID_H
+#define _ASM_IA64_SN_SN_CPUID_H
+
+#include <linux/smp.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/intrinsics.h>
+
+
+/*
+ * Functions for converting between cpuids, nodeids and NASIDs.
+ * 
+ * These are for SGI platforms only.
+ *
+ */
+
+
+
+
+/*
+ *  Definitions of terms (these definitions are for IA64 ONLY. Other architectures
+ *  use cpuid/cpunum quite defferently):
+ *
+ *         CPUID - a number in range of 0..NR_CPUS-1 that uniquely identifies
+ *              the cpu. The value cpuid has no significance on IA64 other than
+ *              the boot cpu is 0.
+ *                      smp_processor_id() returns the cpuid of the current cpu.
+ *
+ *         CPU_PHYSICAL_ID (also known as HARD_PROCESSOR_ID)
+ *              This is the same as 31:24 of the processor LID register
+ *                      hard_smp_processor_id()- cpu_physical_id of current processor
+ *                      cpu_physical_id(cpuid) - convert a <cpuid> to a <physical_cpuid>
+ *                      cpu_logical_id(phy_id) - convert a <physical_cpuid> to a <cpuid> 
+ *                              * not real efficient - don't use in perf critical code
+ *
+ *         SLICE - a number in the range of 0 - 3 (typically) that represents the
+ *              cpu number on a brick.
+ *
+ *         SUBNODE - (almost obsolete) the number of the FSB that a cpu is
+ *              connected to. This is also the same as the PI number. Usually 0 or 1.
+ *
+ *      NOTE!!!: the value of the bits in the cpu physical id (SAPICid or LID) of a cpu has no 
+ *      significance. The SAPIC id (LID) is a 16-bit cookie that has meaning only to the PROM.
+ *
+ *
+ * The macros convert between cpu physical ids & slice/nasid/cnodeid.
+ * These terms are described below:
+ *
+ *
+ * Brick
+ *          -----   -----           -----   -----       CPU
+ *          | 0 |   | 1 |           | 0 |   | 1 |       SLICE
+ *          -----   -----           -----   -----
+ *            |       |               |       |
+ *            |       |               |       |
+ *          0 |       | 2           0 |       | 2       FSB SLOT
+ *             -------                 -------  
+ *                |                       |
+ *                |                       |
+ *                |                       |
+ *             ------------      -------------
+ *             |          |      |           |
+ *             |    SHUB  |      |   SHUB    |        NASID   (0..MAX_NASIDS)
+ *             |          |----- |           |        CNODEID (0..num_compact_nodes-1)
+ *             |          |      |           |
+ *             |          |      |           |
+ *             ------------      -------------
+ *                   |                 |
+ *                           
+ *
+ */
+
+#define get_node_number(addr)                   NASID_GET(addr)
+
+/*
+ * NOTE: on non-MP systems, only cpuid 0 exists
+ */
+
+extern short physical_node_map[];       /* indexed by nasid to get cnode */
+
+/*
+ * Macros for retrieving info about current cpu
+ */
+#define get_nasid()     (sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
+#define get_subnode()   (sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
+#define get_slice()     (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
+#define get_cnode()     (sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
+#define get_sapicid()   ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
+
+/*
+ * Macros for retrieving info about an arbitrary cpu
+ *      cpuid - logical cpu id
+ */
+#define cpuid_to_nasid(cpuid)           (sn_nodepda->phys_cpuid[cpuid].nasid)
+#define cpuid_to_subnode(cpuid)         (sn_nodepda->phys_cpuid[cpuid].subnode)
+#define cpuid_to_slice(cpuid)           (sn_nodepda->phys_cpuid[cpuid].slice)
+
+
+/*
+ * Dont use the following in performance critical code. They require scans
+ * of potentially large tables.
+ */
+extern int nasid_slice_to_cpuid(int, int);
+
+/*
+ * cnodeid_to_nasid - convert a cnodeid to a NASID
+ */
+#define cnodeid_to_nasid(cnodeid)       (sn_cnodeid_to_nasid[cnodeid])
+ 
+/*
+ * nasid_to_cnodeid - convert a NASID to a cnodeid
+ */
+#define nasid_to_cnodeid(nasid)         (physical_node_map[nasid])
+
+/*
+ * partition_coherence_id - get the coherence ID of the current partition
+ */
+extern u8 sn_coherency_id;
+#define partition_coherence_id()        (sn_coherency_id)
+
+#endif /* _ASM_IA64_SN_SN_CPUID_H */
+
diff --git a/arch/ia64/include/asm/sn/sn_feature_sets.h b/arch/ia64/include/asm/sn/sn_feature_sets.h
new file mode 100644
index 000000000000..8e83ac117ace
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn_feature_sets.h
@@ -0,0 +1,58 @@
+#ifndef _ASM_IA64_SN_FEATURE_SETS_H
+#define _ASM_IA64_SN_FEATURE_SETS_H
+
+/*
+ * SN PROM Features
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2005-2006 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+/* --------------------- PROM Features -----------------------------*/
+extern int sn_prom_feature_available(int id);
+
+#define MAX_PROM_FEATURE_SETS                   2
+
+/*
+ * The following defines features that may or may not be supported by the
+ * current PROM. The OS uses sn_prom_feature_available(feature) to test for
+ * the presence of a PROM feature. Down rev (old) PROMs will always test
+ * "false" for new features.
+ *
+ * Use:
+ *              if (sn_prom_feature_available(PRF_XXX))
+ *                      ...
+ */
+
+#define PRF_PAL_CACHE_FLUSH_SAFE        0
+#define PRF_DEVICE_FLUSH_LIST           1
+#define PRF_HOTPLUG_SUPPORT             2
+#define PRF_CPU_DISABLE_SUPPORT         3
+
+/* --------------------- OS Features -------------------------------*/
+
+/*
+ * The following defines OS features that are optionally present in
+ * the operating system.
+ * During boot, PROM is notified of these features via a series of calls:
+ *
+ *              ia64_sn_set_os_feature(feature1);
+ *
+ * Once enabled, a feature cannot be disabled.
+ *
+ * By default, features are disabled unless explicitly enabled.
+ *
+ * These defines must be kept in sync with the corresponding
+ * PROM definitions in feature_sets.h.
+ */
+#define  OSF_MCA_SLV_TO_OS_INIT_SLV     0
+#define  OSF_FEAT_LOG_SBES              1
+#define  OSF_ACPI_ENABLE                2
+#define  OSF_PCISEGMENT_ENABLE          3
+
+
+#endif /* _ASM_IA64_SN_FEATURE_SETS_H */
diff --git a/arch/ia64/include/asm/sn/sn_sal.h b/arch/ia64/include/asm/sn/sn_sal.h
new file mode 100644
index 000000000000..57e649d388b8
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn_sal.h
@@ -0,0 +1,1188 @@
+#ifndef _ASM_IA64_SN_SN_SAL_H
+#define _ASM_IA64_SN_SN_SAL_H
+
+/*
+ * System Abstraction Layer definitions for IA64
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#include <asm/sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/geo.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/shub_mmr.h>
+
+// SGI Specific Calls
+#define  SN_SAL_POD_MODE                           0x02000001
+#define  SN_SAL_SYSTEM_RESET                       0x02000002
+#define  SN_SAL_PROBE                              0x02000003
+#define  SN_SAL_GET_MASTER_NASID                   0x02000004
+#define  SN_SAL_GET_KLCONFIG_ADDR                  0x02000005
+#define  SN_SAL_LOG_CE                             0x02000006
+#define  SN_SAL_REGISTER_CE                        0x02000007
+#define  SN_SAL_GET_PARTITION_ADDR                 0x02000009
+#define  SN_SAL_XP_ADDR_REGION                     0x0200000f
+#define  SN_SAL_NO_FAULT_ZONE_VIRTUAL              0x02000010
+#define  SN_SAL_NO_FAULT_ZONE_PHYSICAL             0x02000011
+#define  SN_SAL_PRINT_ERROR                        0x02000012
+#define  SN_SAL_REGISTER_PMI_HANDLER               0x02000014
+#define  SN_SAL_SET_ERROR_HANDLING_FEATURES        0x0200001a   // reentrant
+#define  SN_SAL_GET_FIT_COMPT                      0x0200001b   // reentrant
+#define  SN_SAL_GET_SAPIC_INFO                     0x0200001d
+#define  SN_SAL_GET_SN_INFO                        0x0200001e
+#define  SN_SAL_CONSOLE_PUTC                       0x02000021
+#define  SN_SAL_CONSOLE_GETC                       0x02000022
+#define  SN_SAL_CONSOLE_PUTS                       0x02000023
+#define  SN_SAL_CONSOLE_GETS                       0x02000024
+#define  SN_SAL_CONSOLE_GETS_TIMEOUT               0x02000025
+#define  SN_SAL_CONSOLE_POLL                       0x02000026
+#define  SN_SAL_CONSOLE_INTR                       0x02000027
+#define  SN_SAL_CONSOLE_PUTB                       0x02000028
+#define  SN_SAL_CONSOLE_XMIT_CHARS                 0x0200002a
+#define  SN_SAL_CONSOLE_READC                      0x0200002b
+#define  SN_SAL_SYSCTL_OP                          0x02000030
+#define  SN_SAL_SYSCTL_MODID_GET                   0x02000031
+#define  SN_SAL_SYSCTL_GET                         0x02000032
+#define  SN_SAL_SYSCTL_IOBRICK_MODULE_GET          0x02000033
+#define  SN_SAL_SYSCTL_IO_PORTSPEED_GET            0x02000035
+#define  SN_SAL_SYSCTL_SLAB_GET                    0x02000036
+#define  SN_SAL_BUS_CONFIG                         0x02000037
+#define  SN_SAL_SYS_SERIAL_GET                     0x02000038
+#define  SN_SAL_PARTITION_SERIAL_GET               0x02000039
+#define  SN_SAL_SYSCTL_PARTITION_GET               0x0200003a
+#define  SN_SAL_SYSTEM_POWER_DOWN                  0x0200003b
+#define  SN_SAL_GET_MASTER_BASEIO_NASID            0x0200003c
+#define  SN_SAL_COHERENCE                          0x0200003d
+#define  SN_SAL_MEMPROTECT                         0x0200003e
+#define  SN_SAL_SYSCTL_FRU_CAPTURE                 0x0200003f
+
+#define  SN_SAL_SYSCTL_IOBRICK_PCI_OP              0x02000042   // reentrant
+#define  SN_SAL_IROUTER_OP                         0x02000043
+#define  SN_SAL_SYSCTL_EVENT                       0x02000044
+#define  SN_SAL_IOIF_INTERRUPT                     0x0200004a
+#define  SN_SAL_HWPERF_OP                          0x02000050   // lock
+#define  SN_SAL_IOIF_ERROR_INTERRUPT               0x02000051
+#define  SN_SAL_IOIF_PCI_SAFE                      0x02000052
+#define  SN_SAL_IOIF_SLOT_ENABLE                   0x02000053
+#define  SN_SAL_IOIF_SLOT_DISABLE                  0x02000054
+#define  SN_SAL_IOIF_GET_HUBDEV_INFO               0x02000055
+#define  SN_SAL_IOIF_GET_PCIBUS_INFO               0x02000056
+#define  SN_SAL_IOIF_GET_PCIDEV_INFO               0x02000057
+#define  SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST      0x02000058   // deprecated
+#define  SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST      0x0200005a
+
+#define SN_SAL_IOIF_INIT                           0x0200005f
+#define SN_SAL_HUB_ERROR_INTERRUPT                 0x02000060
+#define SN_SAL_BTE_RECOVER                         0x02000061
+#define SN_SAL_RESERVED_DO_NOT_USE                 0x02000062
+#define SN_SAL_IOIF_GET_PCI_TOPOLOGY               0x02000064
+
+#define  SN_SAL_GET_PROM_FEATURE_SET               0x02000065
+#define  SN_SAL_SET_OS_FEATURE_SET                 0x02000066
+#define  SN_SAL_INJECT_ERROR                       0x02000067
+#define  SN_SAL_SET_CPU_NUMBER                     0x02000068
+
+#define  SN_SAL_KERNEL_LAUNCH_EVENT                0x02000069
+
+/*
+ * Service-specific constants
+ */
+
+/* Console interrupt manipulation */
+        /* action codes */
+#define SAL_CONSOLE_INTR_OFF    0       /* turn the interrupt off */
+#define SAL_CONSOLE_INTR_ON     1       /* turn the interrupt on */
+#define SAL_CONSOLE_INTR_STATUS 2       /* retrieve the interrupt status */
+        /* interrupt specification & status return codes */
+#define SAL_CONSOLE_INTR_XMIT   1       /* output interrupt */
+#define SAL_CONSOLE_INTR_RECV   2       /* input interrupt */
+
+/* interrupt handling */
+#define SAL_INTR_ALLOC          1
+#define SAL_INTR_FREE           2
+#define SAL_INTR_REDIRECT       3
+
+/*
+ * operations available on the generic SN_SAL_SYSCTL_OP
+ * runtime service
+ */
+#define SAL_SYSCTL_OP_IOBOARD           0x0001  /*  retrieve board type */
+#define SAL_SYSCTL_OP_TIO_JLCK_RST      0x0002  /* issue TIO clock reset */
+
+/*
+ * IRouter (i.e. generalized system controller) operations
+ */
+#define SAL_IROUTER_OPEN        0       /* open a subchannel */
+#define SAL_IROUTER_CLOSE       1       /* close a subchannel */
+#define SAL_IROUTER_SEND        2       /* send part of an IRouter packet */
+#define SAL_IROUTER_RECV        3       /* receive part of an IRouter packet */
+#define SAL_IROUTER_INTR_STATUS 4       /* check the interrupt status for
+                                         * an open subchannel
+                                         */
+#define SAL_IROUTER_INTR_ON     5       /* enable an interrupt */
+#define SAL_IROUTER_INTR_OFF    6       /* disable an interrupt */
+#define SAL_IROUTER_INIT        7       /* initialize IRouter driver */
+
+/* IRouter interrupt mask bits */
+#define SAL_IROUTER_INTR_XMIT   SAL_CONSOLE_INTR_XMIT
+#define SAL_IROUTER_INTR_RECV   SAL_CONSOLE_INTR_RECV
+
+/*
+ * Error Handling Features
+ */
+#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV     0x1     // obsolete
+#define SAL_ERR_FEAT_LOG_SBES                   0x2     // obsolete
+#define SAL_ERR_FEAT_MFR_OVERRIDE               0x4
+#define SAL_ERR_FEAT_SBE_THRESHOLD              0xffff0000
+
+/*
+ * SAL Error Codes
+ */
+#define SALRET_MORE_PASSES      1
+#define SALRET_OK               0
+#define SALRET_NOT_IMPLEMENTED  (-1)
+#define SALRET_INVALID_ARG      (-2)
+#define SALRET_ERROR            (-3)
+
+#define SN_SAL_FAKE_PROM                           0x02009999
+
+/**
+  * sn_sal_revision - get the SGI SAL revision number
+  *
+  * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
+  * This routine simply extracts the major and minor values and
+  * presents them in a u32 format.
+  *
+  * For example, version 4.05 would be represented at 0x0405.
+  */
+static inline u32
+sn_sal_rev(void)
+{
+        struct ia64_sal_systab *systab = __va(efi.sal_systab);
+
+        return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
+}
+
+/*
+ * Returns the master console nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_console_nasid(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        /* Master console nasid is in 'v0' */
+        return ret_stuff.v0;
+}
+
+/*
+ * Returns the master baseio nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_master_baseio_nasid(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        /* Master baseio nasid is in 'v0' */
+        return ret_stuff.v0;
+}
+
+static inline void *
+ia64_sn_get_klconfig_addr(nasid_t nasid)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
+        return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
+}
+
+/*
+ * Returns the next console character.
+ */
+static inline u64
+ia64_sn_console_getc(int *ch)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0);
+
+        /* character is in 'v0' */
+        *ch = (int)ret_stuff.v0;
+
+        return ret_stuff.status;
+}
+
+/*
+ * Read a character from the SAL console device, after a previous interrupt
+ * or poll operation has given us to know that a character is available
+ * to be read.
+ */
+static inline u64
+ia64_sn_console_readc(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0);
+
+        /* character is in 'v0' */
+        return ret_stuff.v0;
+}
+
+/*
+ * Sends the given character to the console.
+ */
+static inline u64
+ia64_sn_console_putc(char ch)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
+ * Sends the given buffer to the console.
+ */
+static inline u64
+ia64_sn_console_putb(const char *buf, int len)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0; 
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
+
+        if ( ret_stuff.status == 0 ) {
+                return ret_stuff.v0;
+        }
+        return (u64)0;
+}
+
+/*
+ * Print a platform error record
+ */
+static inline u64
+ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
+ * Check for Platform errors
+ */
+static inline u64
+ia64_sn_plat_cpei_handler(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
+ * Set Error Handling Features  (Obsolete)
+ */
+static inline u64
+ia64_sn_plat_set_error_handling_features(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
+                SAL_ERR_FEAT_LOG_SBES,
+                0, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
+ * Checks for console input.
+ */
+static inline u64
+ia64_sn_console_check(int *result)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0);
+
+        /* result is in 'v0' */
+        *result = (int)ret_stuff.v0;
+
+        return ret_stuff.status;
+}
+
+/*
+ * Checks console interrupt status
+ */
+static inline u64
+ia64_sn_console_intr_status(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
+                 0, SAL_CONSOLE_INTR_STATUS,
+                 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status == 0) {
+            return ret_stuff.v0;
+        }
+        
+        return 0;
+}
+
+/*
+ * Enable an interrupt on the SAL console device.
+ */
+static inline void
+ia64_sn_console_intr_enable(u64 intr)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
+                 intr, SAL_CONSOLE_INTR_ON,
+                 0, 0, 0, 0, 0);
+}
+
+/*
+ * Disable an interrupt on the SAL console device.
+ */
+static inline void
+ia64_sn_console_intr_disable(u64 intr)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
+                 intr, SAL_CONSOLE_INTR_OFF,
+                 0, 0, 0, 0, 0);
+}
+
+/*
+ * Sends a character buffer to the console asynchronously.
+ */
+static inline u64
+ia64_sn_console_xmit_chars(char *buf, int len)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
+                 (u64)buf, (u64)len,
+                 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status == 0) {
+            return ret_stuff.v0;
+        }
+
+        return 0;
+}
+
+/*
+ * Returns the iobrick module Id
+ */
+static inline u64
+ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0);
+
+        /* result is in 'v0' */
+        *result = (int)ret_stuff.v0;
+
+        return ret_stuff.status;
+}
+
+/**
+ * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function
+ *
+ * SN_SAL_POD_MODE actually takes an argument, but it's always
+ * 0 when we call it from the kernel, so we don't have to expose
+ * it to the caller.
+ */
+static inline u64
+ia64_sn_pod_mode(void)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
+        if (isrv.status)
+                return 0;
+        return isrv.v0;
+}
+
+/**
+ * ia64_sn_probe_mem - read from memory safely
+ * @addr: address to probe
+ * @size: number bytes to read (1,2,4,8)
+ * @data_ptr: address to store value read by probe (-1 returned if probe fails)
+ *
+ * Call into the SAL to do a memory read.  If the read generates a machine
+ * check, this routine will recover gracefully and return -1 to the caller.
+ * @addr is usually a kernel virtual address in uncached space (i.e. the
+ * address starts with 0xc), but if called in physical mode, @addr should
+ * be a physical address.
+ *
+ * Return values:
+ *  0 - probe successful
+ *  1 - probe failed (generated MCA)
+ *  2 - Bad arg
+ * <0 - PAL error
+ */
+static inline u64
+ia64_sn_probe_mem(long addr, long size, void *data_ptr)
+{
+        struct ia64_sal_retval isrv;
+
+        SAL_CALL(isrv, SN_SAL_PROBE, addr, size, 0, 0, 0, 0, 0);
+
+        if (data_ptr) {
+                switch (size) {
+                case 1:
+                        *((u8*)data_ptr) = (u8)isrv.v0;
+                        break;
+                case 2:
+                        *((u16*)data_ptr) = (u16)isrv.v0;
+                        break;
+                case 4:
+                        *((u32*)data_ptr) = (u32)isrv.v0;
+                        break;
+                case 8:
+                        *((u64*)data_ptr) = (u64)isrv.v0;
+                        break;
+                default:
+                        isrv.status = 2;
+                }
+        }
+        return isrv.status;
+}
+
+/*
+ * Retrieve the system serial number as an ASCII string.
+ */
+static inline u64
+ia64_sn_sys_serial_get(char *buf)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+extern char sn_system_serial_number_string[];
+extern u64 sn_partition_serial_number;
+
+static inline char *
+sn_system_serial_number(void) {
+        if (sn_system_serial_number_string[0]) {
+                return(sn_system_serial_number_string);
+        } else {
+                ia64_sn_sys_serial_get(sn_system_serial_number_string);
+                return(sn_system_serial_number_string);
+        }
+}
+        
+
+/*
+ * Returns a unique id number for this system and partition (suitable for
+ * use with license managers), based in part on the system serial number.
+ */
+static inline u64
+ia64_sn_partition_serial_get(void)
+{
+        struct ia64_sal_retval ret_stuff;
+        ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
+                                   0, 0, 0, 0, 0, 0);
+        if (ret_stuff.status != 0)
+            return 0;
+        return ret_stuff.v0;
+}
+
+static inline u64
+sn_partition_serial_number_val(void) {
+        if (unlikely(sn_partition_serial_number == 0)) {
+                sn_partition_serial_number = ia64_sn_partition_serial_get();
+        }
+        return sn_partition_serial_number;
+}
+
+/*
+ * Returns the partition id of the nasid passed in as an argument,
+ * or INVALID_PARTID if the partition id cannot be retrieved.
+ */
+static inline partid_t
+ia64_sn_sysctl_partition_get(nasid_t nasid)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
+                0, 0, 0, 0, 0, 0);
+        if (ret_stuff.status != 0)
+            return -1;
+        return ((partid_t)ret_stuff.v0);
+}
+
+/*
+ * Returns the physical address of the partition's reserved page through
+ * an iterative number of calls.
+ *
+ * On first call, 'cookie' and 'len' should be set to 0, and 'addr'
+ * set to the nasid of the partition whose reserved page's address is
+ * being sought.
+ * On subsequent calls, pass the values, that were passed back on the
+ * previous call.
+ *
+ * While the return status equals SALRET_MORE_PASSES, keep calling
+ * this function after first copying 'len' bytes starting at 'addr'
+ * into 'buf'. Once the return status equals SALRET_OK, 'addr' will
+ * be the physical address of the partition's reserved page. If the
+ * return status equals neither of these, an error as occurred.
+ */
+static inline s64
+sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
+{
+        struct ia64_sal_retval rv;
+        ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie,
+                                   *addr, buf, *len, 0, 0, 0);
+        *cookie = rv.v0;
+        *addr = rv.v1;
+        *len = rv.v2;
+        return rv.status;
+}
+
+/*
+ * Register or unregister a physical address range being referenced across
+ * a partition boundary for which certain SAL errors should be scanned for,
+ * cleaned up and ignored.  This is of value for kernel partitioning code only.
+ * Values for the operation argument:
+ *      1 = register this address range with SAL
+ *      0 = unregister this address range with SAL
+ * 
+ * SAL maintains a reference count on an address range in case it is registered
+ * multiple times.
+ * 
+ * On success, returns the reference count of the address range after the SAL
+ * call has performed the current registration/unregistration.  Returns a
+ * negative value if an error occurred.
+ */
+static inline int
+sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
+{
+        struct ia64_sal_retval ret_stuff;
+        ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
+                         (u64)operation, 0, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+/*
+ * Register or unregister an instruction range for which SAL errors should
+ * be ignored.  If an error occurs while in the registered range, SAL jumps
+ * to return_addr after ignoring the error.  Values for the operation argument:
+ *      1 = register this instruction range with SAL
+ *      0 = unregister this instruction range with SAL
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
+                         int virtual, int operation)
+{
+        struct ia64_sal_retval ret_stuff;
+        u64 call;
+        if (virtual) {
+                call = SN_SAL_NO_FAULT_ZONE_VIRTUAL;
+        } else {
+                call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
+        }
+        ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
+                         (u64)1, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+/*
+ * Register or unregister a function to handle a PMI received by a CPU.
+ * Before calling the registered handler, SAL sets r1 to the value that
+ * was passed in as the global_pointer.
+ *
+ * If the handler pointer is NULL, then the currently registered handler
+ * will be unregistered.
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_register_pmi_handler(u64 handler, u64 global_pointer)
+{
+        struct ia64_sal_retval ret_stuff;
+        ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler,
+                         global_pointer, 0, 0, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+/*
+ * Change or query the coherence domain for this partition. Each cpu-based
+ * nasid is represented by a bit in an array of 64-bit words:
+ *      0 = not in this partition's coherency domain
+ *      1 = in this partition's coherency domain
+ *
+ * It is not possible for the local system's nasids to be removed from
+ * the coherency domain.  Purpose of the domain arguments:
+ *      new_domain = set the coherence domain to the given nasids
+ *      old_domain = return the current coherence domain
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_change_coherence(u64 *new_domain, u64 *old_domain)
+{
+        struct ia64_sal_retval ret_stuff;
+        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
+                                (u64)old_domain, 0, 0, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+/*
+ * Change memory access protections for a physical address range.
+ * nasid_array is not used on Altix, but may be in future architectures.
+ * Available memory protection access classes are defined after the function.
+ */
+static inline int
+sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
+                                (u64)nasid_array, perms, 0, 0, 0);
+        return ret_stuff.status;
+}
+#define SN_MEMPROT_ACCESS_CLASS_0               0x14a080
+#define SN_MEMPROT_ACCESS_CLASS_1               0x2520c2
+#define SN_MEMPROT_ACCESS_CLASS_2               0x14a1ca
+#define SN_MEMPROT_ACCESS_CLASS_3               0x14a290
+#define SN_MEMPROT_ACCESS_CLASS_6               0x084080
+#define SN_MEMPROT_ACCESS_CLASS_7               0x021080
+
+/*
+ * Turns off system power.
+ */
+static inline void
+ia64_sn_power_down(void)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
+        while(1)
+                cpu_relax();
+        /* never returns */
+}
+
+/**
+ * ia64_sn_fru_capture - tell the system controller to capture hw state
+ *
+ * This routine will call the SAL which will tell the system controller(s)
+ * to capture hw mmr information from each SHub in the system.
+ */
+static inline u64
+ia64_sn_fru_capture(void)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0);
+        if (isrv.status)
+                return 0;
+        return isrv.v0;
+}
+
+/*
+ * Performs an operation on a PCI bus or slot -- power up, power down
+ * or reset.
+ */
+static inline u64
+ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type, 
+                              u64 bus, char slot, 
+                              u64 action)
+{
+        struct ia64_sal_retval rv = {0, 0, 0, 0};
+
+        SAL_CALL_NOLOCK(rv, SN_SAL_SYSCTL_IOBRICK_PCI_OP, connection_type, n, action,
+                 bus, (u64) slot, 0, 0);
+        if (rv.status)
+                return rv.v0;
+        return 0;
+}
+
+
+/*
+ * Open a subchannel for sending arbitrary data to the system
+ * controller network via the system controller device associated with
+ * 'nasid'.  Return the subchannel number or a negative error code.
+ */
+static inline int
+ia64_sn_irtr_open(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_OPEN, nasid,
+                           0, 0, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Close system controller subchannel 'subch' previously opened on 'nasid'.
+ */
+static inline int
+ia64_sn_irtr_close(nasid_t nasid, int subch)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_CLOSE,
+                           (u64) nasid, (u64) subch, 0, 0, 0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Read data from system controller associated with 'nasid' on
+ * subchannel 'subch'.  The buffer to be filled is pointed to by
+ * 'buf', and its capacity is in the integer pointed to by 'len'.  The
+ * referent of 'len' is set to the number of bytes read by the SAL
+ * call.  The return value is either SALRET_OK (for bytes read) or
+ * SALRET_ERROR (for error or "no data available").
+ */
+static inline int
+ia64_sn_irtr_recv(nasid_t nasid, int subch, char *buf, int *len)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_RECV,
+                           (u64) nasid, (u64) subch, (u64) buf, (u64) len,
+                           0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Write data to the system controller network via the system
+ * controller associated with 'nasid' on suchannel 'subch'.  The
+ * buffer to be written out is pointed to by 'buf', and 'len' is the
+ * number of bytes to be written.  The return value is either the
+ * number of bytes written (which could be zero) or a negative error
+ * code.
+ */
+static inline int
+ia64_sn_irtr_send(nasid_t nasid, int subch, char *buf, int len)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_SEND,
+                           (u64) nasid, (u64) subch, (u64) buf, (u64) len,
+                           0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Check whether any interrupts are pending for the system controller
+ * associated with 'nasid' and its subchannel 'subch'.  The return
+ * value is a mask of pending interrupts (SAL_IROUTER_INTR_XMIT and/or
+ * SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr(nasid_t nasid, int subch)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_STATUS,
+                           (u64) nasid, (u64) subch, 0, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Enable the interrupt indicated by the intr parameter (either
+ * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_ON,
+                           (u64) nasid, (u64) subch, intr, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Disable the interrupt indicated by the intr parameter (either
+ * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_OFF,
+                           (u64) nasid, (u64) subch, intr, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Set up a node as the point of contact for system controller
+ * environmental event delivery.
+ */
+static inline int
+ia64_sn_sysctl_event_init(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
+                           0, 0, 0, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Ask the system controller on the specified nasid to reset
+ * the CX corelet clock.  Only valid on TIO nodes.
+ */
+static inline int
+ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
+                        nasid, 0, 0, 0, 0, 0);
+        if (rv.status != 0)
+                return (int)rv.status;
+        if (rv.v0 != 0)
+                return (int)rv.v0;
+
+        return 0;
+}
+
+/*
+ * Get the associated ioboard type for a given nasid.
+ */
+static inline s64
+ia64_sn_sysctl_ioboard_get(nasid_t nasid, u16 *ioboard)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL_REENTRANT(isrv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
+                           nasid, 0, 0, 0, 0, 0);
+        if (isrv.v0 != 0) {
+                *ioboard = isrv.v0;
+                return isrv.status;
+        }
+        if (isrv.v1 != 0) {
+                *ioboard = isrv.v1;
+                return isrv.status;
+        }
+
+        return isrv.status;
+}
+
+/**
+ * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
+ * @nasid: NASID of node to read
+ * @index: FIT entry index to be retrieved (0..n)
+ * @fitentry: 16 byte buffer where FIT entry will be stored.
+ * @banbuf: optional buffer for retrieving banner
+ * @banlen: length of banner buffer
+ *
+ * Access to the physical PROM chips needs to be serialized since reads and
+ * writes can't occur at the same time, so we need to call into the SAL when
+ * we want to look at the FIT entries on the chips.
+ *
+ * Returns:
+ *      %SALRET_OK if ok
+ *      %SALRET_INVALID_ARG if index too big
+ *      %SALRET_NOT_IMPLEMENTED if running on older PROM
+ *      ??? if nasid invalid OR banner buffer not large enough
+ */
+static inline int
+ia64_sn_get_fit_compt(u64 nasid, u64 index, void *fitentry, void *banbuf,
+                      u64 banlen)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_GET_FIT_COMPT, nasid, index, fitentry,
+                        banbuf, banlen, 0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Initialize the SAL components of the system controller
+ * communication driver; specifically pass in a sizable buffer that
+ * can be used for allocation of subchannel queues as new subchannels
+ * are opened.  "buf" points to the buffer, and "len" specifies its
+ * length.
+ */
+static inline int
+ia64_sn_irtr_init(nasid_t nasid, void *buf, int len)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INIT,
+                           (u64) nasid, (u64) buf, (u64) len, 0, 0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Returns the nasid, subnode & slice corresponding to a SAPIC ID
+ *
+ *  In:
+ *      arg0 - SN_SAL_GET_SAPIC_INFO
+ *      arg1 - sapicid (lid >> 16) 
+ *  Out:
+ *      v0 - nasid
+ *      v1 - subnode
+ *      v2 - slice
+ */
+static inline u64
+ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
+
+/***** BEGIN HACK - temp til old proms no longer supported ********/
+        if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
+                if (nasid) *nasid = sapicid & 0xfff;
+                if (subnode) *subnode = (sapicid >> 13) & 1;
+                if (slice) *slice = (sapicid >> 12) & 3;
+                return 0;
+        }
+/***** END HACK *******/
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        if (nasid) *nasid = (int) ret_stuff.v0;
+        if (subnode) *subnode = (int) ret_stuff.v1;
+        if (slice) *slice = (int) ret_stuff.v2;
+        return 0;
+}
+ 
+/*
+ * Returns information about the HUB/SHUB.
+ *  In:
+ *      arg0 - SN_SAL_GET_SN_INFO
+ *      arg1 - 0 (other values reserved for future use)
+ *  Out:
+ *      v0 
+ *              [7:0]   - shub type (0=shub1, 1=shub2)
+ *              [15:8]  - Log2 max number of nodes in entire system (includes
+ *                        C-bricks, I-bricks, etc)
+ *              [23:16] - Log2 of nodes per sharing domain                       
+ *              [31:24] - partition ID
+ *              [39:32] - coherency_id
+ *              [47:40] - regionsize
+ *      v1 
+ *              [15:0]  - nasid mask (ex., 0x7ff for 11 bit nasid)
+ *              [23:15] - bit position of low nasid bit
+ */
+static inline u64
+ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift, 
+                u8 *systemsize, u8 *sharing_domain_size, u8 *partid, u8 *coher, u8 *reg)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
+
+/***** BEGIN HACK - temp til old proms no longer supported ********/
+        if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
+                int nasid = get_sapicid() & 0xfff;
+#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
+#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
+                if (shubtype) *shubtype = 0;
+                if (nasid_bitmask) *nasid_bitmask = 0x7ff;
+                if (nasid_shift) *nasid_shift = 38;
+                if (systemsize) *systemsize = 10;
+                if (sharing_domain_size) *sharing_domain_size = 8;
+                if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
+                if (coher) *coher = nasid >> 9;
+                if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
+                        SH_SHUB_ID_NODES_PER_BIT_SHFT;
+                return 0;
+        }
+/***** END HACK *******/
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        if (shubtype) *shubtype = ret_stuff.v0 & 0xff;
+        if (systemsize) *systemsize = (ret_stuff.v0 >> 8) & 0xff;
+        if (sharing_domain_size) *sharing_domain_size = (ret_stuff.v0 >> 16) & 0xff;
+        if (partid) *partid = (ret_stuff.v0 >> 24) & 0xff;
+        if (coher) *coher = (ret_stuff.v0 >> 32) & 0xff;
+        if (reg) *reg = (ret_stuff.v0 >> 40) & 0xff;
+        if (nasid_bitmask) *nasid_bitmask = (ret_stuff.v1 & 0xffff);
+        if (nasid_shift) *nasid_shift = (ret_stuff.v1 >> 16) & 0xff;
+        return 0;
+}
+ 
+/*
+ * This is the access point to the Altix PROM hardware performance
+ * and status monitoring interface. For info on using this, see
+ * arch/ia64/include/asm/sn/sn2/sn_hwperf.h
+ */
+static inline int
+ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
+                  u64 a3, u64 a4, int *v0)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_HWPERF_OP, (u64)nasid,
+                opcode, a0, a1, a2, a3, a4);
+        if (v0)
+                *v0 = (int) rv.v0;
+        return (int) rv.status;
+}
+
+static inline int
+ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * BTE error recovery is implemented in SAL
+ */
+static inline int
+ia64_sn_bte_recovery(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+
+        rv.status = 0;
+        SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, (u64)nasid, 0, 0, 0, 0, 0, 0);
+        if (rv.status == SALRET_NOT_IMPLEMENTED)
+                return 0;
+        return (int) rv.status;
+}
+
+static inline int
+ia64_sn_is_fake_prom(void)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
+        return (rv.status == 0);
+}
+
+static inline int
+ia64_sn_get_prom_feature_set(int set, unsigned long *feature_set)
+{
+        struct ia64_sal_retval rv;
+
+        SAL_CALL_NOLOCK(rv, SN_SAL_GET_PROM_FEATURE_SET, set, 0, 0, 0, 0, 0, 0);
+        if (rv.status != 0)
+                return rv.status;
+        *feature_set = rv.v0;
+        return 0;
+}
+
+static inline int
+ia64_sn_set_os_feature(int feature)
+{
+        struct ia64_sal_retval rv;
+
+        SAL_CALL_NOLOCK(rv, SN_SAL_SET_OS_FEATURE_SET, feature, 0, 0, 0, 0, 0, 0);
+        return rv.status;
+}
+
+static inline int
+sn_inject_error(u64 paddr, u64 *data, u64 *ecc)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_INJECT_ERROR, paddr, (u64)data,
+                                (u64)ecc, 0, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+static inline int
+ia64_sn_set_cpu_number(int cpu)
+{
+        struct ia64_sal_retval rv;
+
+        SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
+        return rv.status;
+}
+static inline int
+ia64_sn_kernel_launch_event(void)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
+        return rv.status;
+}
+#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/arch/ia64/include/asm/sn/tioca.h b/arch/ia64/include/asm/sn/tioca.h
new file mode 100644
index 000000000000..666222d7f0f6
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioca.h
@@ -0,0 +1,596 @@
+#ifndef _ASM_IA64_SN_TIO_TIOCA_H
+#define _ASM_IA64_SN_TIO_TIOCA_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#define TIOCA_PART_NUM  0xE020
+#define TIOCA_MFGR_NUM  0x24
+#define TIOCA_REV_A     0x1
+
+/*
+ * Register layout for TIO:CA.  See below for bitmasks for each register.
+ */
+
+struct tioca {
+        u64     ca_id;                          /* 0x000000 */
+        u64     ca_control1;                    /* 0x000008 */
+        u64     ca_control2;                    /* 0x000010 */
+        u64     ca_status1;                     /* 0x000018 */
+        u64     ca_status2;                     /* 0x000020 */
+        u64     ca_gart_aperature;              /* 0x000028 */
+        u64     ca_gfx_detach;                  /* 0x000030 */
+        u64     ca_inta_dest_addr;              /* 0x000038 */
+        u64     ca_intb_dest_addr;              /* 0x000040 */
+        u64     ca_err_int_dest_addr;           /* 0x000048 */
+        u64     ca_int_status;                  /* 0x000050 */
+        u64     ca_int_status_alias;            /* 0x000058 */
+        u64     ca_mult_error;                  /* 0x000060 */
+        u64     ca_mult_error_alias;            /* 0x000068 */
+        u64     ca_first_error;                 /* 0x000070 */
+        u64     ca_int_mask;                    /* 0x000078 */
+        u64     ca_crm_pkterr_type;             /* 0x000080 */
+        u64     ca_crm_pkterr_type_alias;       /* 0x000088 */
+        u64     ca_crm_ct_error_detail_1;       /* 0x000090 */
+        u64     ca_crm_ct_error_detail_2;       /* 0x000098 */
+        u64     ca_crm_tnumto;                  /* 0x0000A0 */
+        u64     ca_gart_err;                    /* 0x0000A8 */
+        u64     ca_pcierr_type;                 /* 0x0000B0 */
+        u64     ca_pcierr_addr;                 /* 0x0000B8 */
+
+        u64     ca_pad_0000C0[3];               /* 0x0000{C0..D0} */
+
+        u64     ca_pci_rd_buf_flush;            /* 0x0000D8 */
+        u64     ca_pci_dma_addr_extn;           /* 0x0000E0 */
+        u64     ca_agp_dma_addr_extn;           /* 0x0000E8 */
+        u64     ca_force_inta;                  /* 0x0000F0 */
+        u64     ca_force_intb;                  /* 0x0000F8 */
+        u64     ca_debug_vector_sel;            /* 0x000100 */
+        u64     ca_debug_mux_core_sel;          /* 0x000108 */
+        u64     ca_debug_mux_pci_sel;           /* 0x000110 */
+        u64     ca_debug_domain_sel;            /* 0x000118 */
+
+        u64     ca_pad_000120[28];              /* 0x0001{20..F8} */
+
+        u64     ca_gart_ptr_table;              /* 0x200 */
+        u64     ca_gart_tlb_addr[8];            /* 0x2{08..40} */
+};
+
+/*
+ * Mask/shift definitions for TIO:CA registers.  The convention here is
+ * to mainly use the names as they appear in the "TIO AEGIS Programmers'
+ * Reference" with a CA_ prefix added.  Some exceptions were made to fix
+ * duplicate field names or to generalize fields that are common to
+ * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
+ * example).
+ *
+ * Fields consisting of a single bit have a single #define have a single
+ * macro declaration to mask the bit.  Fields consisting of multiple bits
+ * have two declarations: one to mask the proper bits in a register, and 
+ * a second with the suffix "_SHFT" to identify how far the mask needs to
+ * be shifted right to get its base value.
+ */
+
+/* ==== ca_control1 */
+#define CA_SYS_BIG_END                  (1ull << 0)
+#define CA_DMA_AGP_SWAP                 (1ull << 1)
+#define CA_DMA_PCI_SWAP                 (1ull << 2)
+#define CA_PIO_IO_SWAP                  (1ull << 3)
+#define CA_PIO_MEM_SWAP                 (1ull << 4)
+#define CA_GFX_WR_SWAP                  (1ull << 5)
+#define CA_AGP_FW_ENABLE                (1ull << 6)
+#define CA_AGP_CAL_CYCLE                (0x7ull << 7)
+#define CA_AGP_CAL_CYCLE_SHFT           7
+#define CA_AGP_CAL_PRSCL_BYP            (1ull << 10)
+#define CA_AGP_INIT_CAL_ENB             (1ull << 11)
+#define CA_INJ_ADDR_PERR                (1ull << 12)
+#define CA_INJ_DATA_PERR                (1ull << 13)
+        /* bits 15:14 unused */
+#define CA_PCIM_IO_NBE_AD               (0x7ull << 16)
+#define CA_PCIM_IO_NBE_AD_SHFT          16
+#define CA_PCIM_FAST_BTB_ENB            (1ull << 19)
+        /* bits 23:20 unused */
+#define CA_PIO_ADDR_OFFSET              (0xffull << 24)
+#define CA_PIO_ADDR_OFFSET_SHFT         24
+        /* bits 35:32 unused */
+#define CA_AGPDMA_OP_COMBDELAY          (0x1full << 36)
+#define CA_AGPDMA_OP_COMBDELAY_SHFT     36
+        /* bit 41 unused */
+#define CA_AGPDMA_OP_ENB_COMBDELAY      (1ull << 42)
+#define CA_PCI_INT_LPCNT                (0xffull << 44)
+#define CA_PCI_INT_LPCNT_SHFT           44
+        /* bits 63:52 unused */
+
+/* ==== ca_control2 */
+#define CA_AGP_LATENCY_TO               (0xffull << 0)
+#define CA_AGP_LATENCY_TO_SHFT          0
+#define CA_PCI_LATENCY_TO               (0xffull << 8)
+#define CA_PCI_LATENCY_TO_SHFT          8
+#define CA_PCI_MAX_RETRY                (0x3ffull << 16)
+#define CA_PCI_MAX_RETRY_SHFT           16
+        /* bits 27:26 unused */
+#define CA_RT_INT_EN                    (0x3ull << 28)
+#define CA_RT_INT_EN_SHFT                       28
+#define CA_MSI_INT_ENB                  (1ull << 30)
+#define CA_PCI_ARB_ERR_ENB              (1ull << 31)
+#define CA_GART_MEM_PARAM               (0x3ull << 32)
+#define CA_GART_MEM_PARAM_SHFT          32
+#define CA_GART_RD_PREFETCH_ENB         (1ull << 34)
+#define CA_GART_WR_PREFETCH_ENB         (1ull << 35)
+#define CA_GART_FLUSH_TLB               (1ull << 36)
+        /* bits 39:37 unused */
+#define CA_CRM_TNUMTO_PERIOD            (0x1fffull << 40)
+#define CA_CRM_TNUMTO_PERIOD_SHFT       40
+        /* bits 55:53 unused */
+#define CA_CRM_TNUMTO_ENB               (1ull << 56)
+#define CA_CRM_PRESCALER_BYP            (1ull << 57)
+        /* bits 59:58 unused */
+#define CA_CRM_MAX_CREDIT               (0x7ull << 60)
+#define CA_CRM_MAX_CREDIT_SHFT          60
+        /* bit 63 unused */
+
+/* ==== ca_status1 */
+#define CA_CORELET_ID                   (0x3ull << 0)
+#define CA_CORELET_ID_SHFT              0
+#define CA_INTA_N                       (1ull << 2)
+#define CA_INTB_N                       (1ull << 3)
+#define CA_CRM_CREDIT_AVAIL             (0x7ull << 4)
+#define CA_CRM_CREDIT_AVAIL_SHFT        4
+        /* bit 7 unused */
+#define CA_CRM_SPACE_AVAIL              (0x7full << 8)
+#define CA_CRM_SPACE_AVAIL_SHFT         8
+        /* bit 15 unused */
+#define CA_GART_TLB_VAL                 (0xffull << 16)
+#define CA_GART_TLB_VAL_SHFT            16
+        /* bits 63:24 unused */
+
+/* ==== ca_status2 */
+#define CA_GFX_CREDIT_AVAIL             (0xffull << 0)
+#define CA_GFX_CREDIT_AVAIL_SHFT        0
+#define CA_GFX_OPQ_AVAIL                (0xffull << 8)
+#define CA_GFX_OPQ_AVAIL_SHFT           8
+#define CA_GFX_WRBUFF_AVAIL             (0xffull << 16)
+#define CA_GFX_WRBUFF_AVAIL_SHFT        16
+#define CA_ADMA_OPQ_AVAIL               (0xffull << 24)
+#define CA_ADMA_OPQ_AVAIL_SHFT          24
+#define CA_ADMA_WRBUFF_AVAIL            (0xffull << 32)
+#define CA_ADMA_WRBUFF_AVAIL_SHFT       32
+#define CA_ADMA_RDBUFF_AVAIL            (0x7full << 40)
+#define CA_ADMA_RDBUFF_AVAIL_SHFT       40
+#define CA_PCI_PIO_OP_STAT              (1ull << 47)
+#define CA_PDMA_OPQ_AVAIL               (0xfull << 48)
+#define CA_PDMA_OPQ_AVAIL_SHFT          48
+#define CA_PDMA_WRBUFF_AVAIL            (0xfull << 52)
+#define CA_PDMA_WRBUFF_AVAIL_SHFT       52
+#define CA_PDMA_RDBUFF_AVAIL            (0x3ull << 56)
+#define CA_PDMA_RDBUFF_AVAIL_SHFT       56
+        /* bits 63:58 unused */
+
+/* ==== ca_gart_aperature */
+#define CA_GART_AP_ENB_AGP              (1ull << 0)
+#define CA_GART_PAGE_SIZE               (1ull << 1)
+#define CA_GART_AP_ENB_PCI              (1ull << 2)
+        /* bits 11:3 unused */
+#define CA_GART_AP_SIZE                 (0x3ffull << 12)
+#define CA_GART_AP_SIZE_SHFT            12
+#define CA_GART_AP_BASE                 (0x3ffffffffffull << 22)
+#define CA_GART_AP_BASE_SHFT            22
+
+/* ==== ca_inta_dest_addr
+   ==== ca_intb_dest_addr 
+   ==== ca_err_int_dest_addr */
+        /* bits 2:0 unused */
+#define CA_INT_DEST_ADDR                (0x7ffffffffffffull << 3)
+#define CA_INT_DEST_ADDR_SHFT           3
+        /* bits 55:54 unused */
+#define CA_INT_DEST_VECT                (0xffull << 56)
+#define CA_INT_DEST_VECT_SHFT           56
+
+/* ==== ca_int_status */
+/* ==== ca_int_status_alias */
+/* ==== ca_mult_error */
+/* ==== ca_mult_error_alias */
+/* ==== ca_first_error */
+/* ==== ca_int_mask */
+#define CA_PCI_ERR                      (1ull << 0)
+        /* bits 3:1 unused */
+#define CA_GART_FETCH_ERR               (1ull << 4)
+#define CA_GFX_WR_OVFLW                 (1ull << 5)
+#define CA_PIO_REQ_OVFLW                (1ull << 6)
+#define CA_CRM_PKTERR                   (1ull << 7)
+#define CA_CRM_DVERR                    (1ull << 8)
+#define CA_TNUMTO                       (1ull << 9)
+#define CA_CXM_RSP_CRED_OVFLW           (1ull << 10)
+#define CA_CXM_REQ_CRED_OVFLW           (1ull << 11)
+#define CA_PIO_INVALID_ADDR             (1ull << 12)
+#define CA_PCI_ARB_TO                   (1ull << 13)
+#define CA_AGP_REQ_OFLOW                (1ull << 14)
+#define CA_SBA_TYPE1_ERR                (1ull << 15)
+        /* bit 16 unused */
+#define CA_INTA                         (1ull << 17)
+#define CA_INTB                         (1ull << 18)
+#define CA_MULT_INTA                    (1ull << 19)
+#define CA_MULT_INTB                    (1ull << 20)
+#define CA_GFX_CREDIT_OVFLW             (1ull << 21)
+        /* bits 63:22 unused */
+
+/* ==== ca_crm_pkterr_type */
+/* ==== ca_crm_pkterr_type_alias */
+#define CA_CRM_PKTERR_SBERR_HDR         (1ull << 0)
+#define CA_CRM_PKTERR_DIDN              (1ull << 1)
+#define CA_CRM_PKTERR_PACTYPE           (1ull << 2)
+#define CA_CRM_PKTERR_INV_TNUM          (1ull << 3)
+#define CA_CRM_PKTERR_ADDR_RNG          (1ull << 4)
+#define CA_CRM_PKTERR_ADDR_ALGN         (1ull << 5)
+#define CA_CRM_PKTERR_HDR_PARAM         (1ull << 6)
+#define CA_CRM_PKTERR_CW_ERR            (1ull << 7)
+#define CA_CRM_PKTERR_SBERR_NH          (1ull << 8)
+#define CA_CRM_PKTERR_EARLY_TERM        (1ull << 9)
+#define CA_CRM_PKTERR_EARLY_TAIL        (1ull << 10)
+#define CA_CRM_PKTERR_MSSNG_TAIL        (1ull << 11)
+#define CA_CRM_PKTERR_MSSNG_HDR         (1ull << 12)
+        /* bits 15:13 unused */
+#define CA_FIRST_CRM_PKTERR_SBERR_HDR   (1ull << 16)
+#define CA_FIRST_CRM_PKTERR_DIDN        (1ull << 17)
+#define CA_FIRST_CRM_PKTERR_PACTYPE     (1ull << 18)
+#define CA_FIRST_CRM_PKTERR_INV_TNUM    (1ull << 19)
+#define CA_FIRST_CRM_PKTERR_ADDR_RNG    (1ull << 20)
+#define CA_FIRST_CRM_PKTERR_ADDR_ALGN   (1ull << 21)
+#define CA_FIRST_CRM_PKTERR_HDR_PARAM   (1ull << 22)
+#define CA_FIRST_CRM_PKTERR_CW_ERR      (1ull << 23)
+#define CA_FIRST_CRM_PKTERR_SBERR_NH    (1ull << 24)
+#define CA_FIRST_CRM_PKTERR_EARLY_TERM  (1ull << 25)
+#define CA_FIRST_CRM_PKTERR_EARLY_TAIL  (1ull << 26)
+#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL  (1ull << 27)
+#define CA_FIRST_CRM_PKTERR_MSSNG_HDR   (1ull << 28)
+        /* bits 63:29 unused */
+
+/* ==== ca_crm_ct_error_detail_1 */
+#define CA_PKT_TYPE                     (0xfull << 0)
+#define CA_PKT_TYPE_SHFT                0
+#define CA_SRC_ID                       (0x3ull << 4)
+#define CA_SRC_ID_SHFT                  4
+#define CA_DATA_SZ                      (0x3ull << 6)
+#define CA_DATA_SZ_SHFT                 6
+#define CA_TNUM                         (0xffull << 8)
+#define CA_TNUM_SHFT                    8
+#define CA_DW_DATA_EN                   (0xffull << 16)
+#define CA_DW_DATA_EN_SHFT              16
+#define CA_GFX_CRED                     (0xffull << 24)
+#define CA_GFX_CRED_SHFT                24
+#define CA_MEM_RD_PARAM                 (0x3ull << 32)
+#define CA_MEM_RD_PARAM_SHFT            32
+#define CA_PIO_OP                       (1ull << 34)
+#define CA_CW_ERR                       (1ull << 35)
+        /* bits 62:36 unused */
+#define CA_VALID                        (1ull << 63)
+
+/* ==== ca_crm_ct_error_detail_2 */
+        /* bits 2:0 unused */
+#define CA_PKT_ADDR                     (0x1fffffffffffffull << 3)
+#define CA_PKT_ADDR_SHFT                3
+        /* bits 63:56 unused */
+
+/* ==== ca_crm_tnumto */
+#define CA_CRM_TNUMTO_VAL               (0xffull << 0)
+#define CA_CRM_TNUMTO_VAL_SHFT          0
+#define CA_CRM_TNUMTO_WR                (1ull << 8)
+        /* bits 63:9 unused */
+
+/* ==== ca_gart_err */
+#define CA_GART_ERR_SOURCE              (0x3ull << 0)
+#define CA_GART_ERR_SOURCE_SHFT         0
+        /* bits 3:2 unused */
+#define CA_GART_ERR_ADDR                (0xfffffffffull << 4)
+#define CA_GART_ERR_ADDR_SHFT           4
+        /* bits 63:40 unused */
+
+/* ==== ca_pcierr_type */
+#define CA_PCIERR_DATA                  (0xffffffffull << 0)
+#define CA_PCIERR_DATA_SHFT             0
+#define CA_PCIERR_ENB                   (0xfull << 32)
+#define CA_PCIERR_ENB_SHFT              32
+#define CA_PCIERR_CMD                   (0xfull << 36)
+#define CA_PCIERR_CMD_SHFT              36
+#define CA_PCIERR_A64                   (1ull << 40)
+#define CA_PCIERR_SLV_SERR              (1ull << 41)
+#define CA_PCIERR_SLV_WR_PERR           (1ull << 42)
+#define CA_PCIERR_SLV_RD_PERR           (1ull << 43)
+#define CA_PCIERR_MST_SERR              (1ull << 44)
+#define CA_PCIERR_MST_WR_PERR           (1ull << 45)
+#define CA_PCIERR_MST_RD_PERR           (1ull << 46)
+#define CA_PCIERR_MST_MABT              (1ull << 47)
+#define CA_PCIERR_MST_TABT              (1ull << 48)
+#define CA_PCIERR_MST_RETRY_TOUT        (1ull << 49)
+
+#define CA_PCIERR_TYPES \
+        (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
+         CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
+         CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
+         CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
+
+        /* bits 63:50 unused */
+
+/* ==== ca_pci_dma_addr_extn */
+#define CA_UPPER_NODE_OFFSET            (0x3full << 0)
+#define CA_UPPER_NODE_OFFSET_SHFT       0
+        /* bits 7:6 unused */
+#define CA_CHIPLET_ID                   (0x3ull << 8)
+#define CA_CHIPLET_ID_SHFT              8
+        /* bits 11:10 unused */
+#define CA_PCI_DMA_NODE_ID              (0xffffull << 12)
+#define CA_PCI_DMA_NODE_ID_SHFT         12
+        /* bits 27:26 unused */
+#define CA_PCI_DMA_PIO_MEM_TYPE         (1ull << 28)
+        /* bits 63:29 unused */
+
+
+/* ==== ca_agp_dma_addr_extn */
+        /* bits 19:0 unused */
+#define CA_AGP_DMA_NODE_ID              (0xffffull << 20)
+#define CA_AGP_DMA_NODE_ID_SHFT         20
+        /* bits 27:26 unused */
+#define CA_AGP_DMA_PIO_MEM_TYPE         (1ull << 28)
+        /* bits 63:29 unused */
+
+/* ==== ca_debug_vector_sel */
+#define CA_DEBUG_MN_VSEL                (0xfull << 0)
+#define CA_DEBUG_MN_VSEL_SHFT           0
+#define CA_DEBUG_PP_VSEL                (0xfull << 4)
+#define CA_DEBUG_PP_VSEL_SHFT           4
+#define CA_DEBUG_GW_VSEL                (0xfull << 8)
+#define CA_DEBUG_GW_VSEL_SHFT           8
+#define CA_DEBUG_GT_VSEL                (0xfull << 12)
+#define CA_DEBUG_GT_VSEL_SHFT           12
+#define CA_DEBUG_PD_VSEL                (0xfull << 16)
+#define CA_DEBUG_PD_VSEL_SHFT           16
+#define CA_DEBUG_AD_VSEL                (0xfull << 20)
+#define CA_DEBUG_AD_VSEL_SHFT           20
+#define CA_DEBUG_CX_VSEL                (0xfull << 24)
+#define CA_DEBUG_CX_VSEL_SHFT           24
+#define CA_DEBUG_CR_VSEL                (0xfull << 28)
+#define CA_DEBUG_CR_VSEL_SHFT           28
+#define CA_DEBUG_BA_VSEL                (0xfull << 32)
+#define CA_DEBUG_BA_VSEL_SHFT           32
+#define CA_DEBUG_PE_VSEL                (0xfull << 36)
+#define CA_DEBUG_PE_VSEL_SHFT           36
+#define CA_DEBUG_BO_VSEL                (0xfull << 40)
+#define CA_DEBUG_BO_VSEL_SHFT           40
+#define CA_DEBUG_BI_VSEL                (0xfull << 44)
+#define CA_DEBUG_BI_VSEL_SHFT           44
+#define CA_DEBUG_AS_VSEL                (0xfull << 48)
+#define CA_DEBUG_AS_VSEL_SHFT           48
+#define CA_DEBUG_PS_VSEL                (0xfull << 52)
+#define CA_DEBUG_PS_VSEL_SHFT           52
+#define CA_DEBUG_PM_VSEL                (0xfull << 56)
+#define CA_DEBUG_PM_VSEL_SHFT           56
+        /* bits 63:60 unused */
+
+/* ==== ca_debug_mux_core_sel */
+/* ==== ca_debug_mux_pci_sel */
+#define CA_DEBUG_MSEL0                  (0x7ull << 0)
+#define CA_DEBUG_MSEL0_SHFT             0
+        /* bit 3 unused */
+#define CA_DEBUG_NSEL0                  (0x7ull << 4)
+#define CA_DEBUG_NSEL0_SHFT             4
+        /* bit 7 unused */
+#define CA_DEBUG_MSEL1                  (0x7ull << 8)
+#define CA_DEBUG_MSEL1_SHFT             8
+        /* bit 11 unused */
+#define CA_DEBUG_NSEL1                  (0x7ull << 12)
+#define CA_DEBUG_NSEL1_SHFT             12
+        /* bit 15 unused */
+#define CA_DEBUG_MSEL2                  (0x7ull << 16)
+#define CA_DEBUG_MSEL2_SHFT             16
+        /* bit 19 unused */
+#define CA_DEBUG_NSEL2                  (0x7ull << 20)
+#define CA_DEBUG_NSEL2_SHFT             20
+        /* bit 23 unused */
+#define CA_DEBUG_MSEL3                  (0x7ull << 24)
+#define CA_DEBUG_MSEL3_SHFT             24
+        /* bit 27 unused */
+#define CA_DEBUG_NSEL3                  (0x7ull << 28)
+#define CA_DEBUG_NSEL3_SHFT             28
+        /* bit 31 unused */
+#define CA_DEBUG_MSEL4                  (0x7ull << 32)
+#define CA_DEBUG_MSEL4_SHFT             32
+        /* bit 35 unused */
+#define CA_DEBUG_NSEL4                  (0x7ull << 36)
+#define CA_DEBUG_NSEL4_SHFT             36
+        /* bit 39 unused */
+#define CA_DEBUG_MSEL5                  (0x7ull << 40)
+#define CA_DEBUG_MSEL5_SHFT             40
+        /* bit 43 unused */
+#define CA_DEBUG_NSEL5                  (0x7ull << 44)
+#define CA_DEBUG_NSEL5_SHFT             44
+        /* bit 47 unused */
+#define CA_DEBUG_MSEL6                  (0x7ull << 48)
+#define CA_DEBUG_MSEL6_SHFT             48
+        /* bit 51 unused */
+#define CA_DEBUG_NSEL6                  (0x7ull << 52)
+#define CA_DEBUG_NSEL6_SHFT             52
+        /* bit 55 unused */
+#define CA_DEBUG_MSEL7                  (0x7ull << 56)
+#define CA_DEBUG_MSEL7_SHFT             56
+        /* bit 59 unused */
+#define CA_DEBUG_NSEL7                  (0x7ull << 60)
+#define CA_DEBUG_NSEL7_SHFT             60
+        /* bit 63 unused */
+
+
+/* ==== ca_debug_domain_sel */
+#define CA_DEBUG_DOMAIN_L               (1ull << 0)
+#define CA_DEBUG_DOMAIN_H               (1ull << 1)
+        /* bits 63:2 unused */
+
+/* ==== ca_gart_ptr_table */
+#define CA_GART_PTR_VAL                 (1ull << 0)
+        /* bits 11:1 unused */
+#define CA_GART_PTR_ADDR                (0xfffffffffffull << 12)
+#define CA_GART_PTR_ADDR_SHFT           12
+        /* bits 63:56 unused */
+
+/* ==== ca_gart_tlb_addr[0-7] */
+#define CA_GART_TLB_ADDR                (0xffffffffffffffull << 0)
+#define CA_GART_TLB_ADDR_SHFT           0
+        /* bits 62:56 unused */
+#define CA_GART_TLB_ENTRY_VAL           (1ull << 63)
+
+/*
+ * PIO address space ranges for TIO:CA
+ */
+
+/* CA internal registers */
+#define CA_PIO_ADMIN                    0x00000000
+#define CA_PIO_ADMIN_LEN                0x00010000
+
+/* GFX Write Buffer - Diagnostics */
+#define CA_PIO_GFX                      0x00010000
+#define CA_PIO_GFX_LEN                  0x00010000
+
+/* AGP DMA Write Buffer - Diagnostics */
+#define CA_PIO_AGP_DMAWRITE             0x00020000
+#define CA_PIO_AGP_DMAWRITE_LEN         0x00010000
+
+/* AGP DMA READ Buffer - Diagnostics */
+#define CA_PIO_AGP_DMAREAD              0x00030000
+#define CA_PIO_AGP_DMAREAD_LEN          0x00010000
+
+/* PCI Config Type 0 */
+#define CA_PIO_PCI_TYPE0_CONFIG         0x01000000
+#define CA_PIO_PCI_TYPE0_CONFIG_LEN     0x01000000
+
+/* PCI Config Type 1 */
+#define CA_PIO_PCI_TYPE1_CONFIG         0x02000000
+#define CA_PIO_PCI_TYPE1_CONFIG_LEN     0x01000000
+
+/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
+#define CA_PIO_PCI_IO                   0x03000000
+#define CA_PIO_PCI_IO_LEN               0x05000000
+
+/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
+/*      use Fast Write if enabled and coretalk packet type is a GFX request */
+#define CA_PIO_PCI_MEM_OFFSET           0x08000000
+#define CA_PIO_PCI_MEM_OFFSET_LEN       0x08000000
+
+/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
+/*      use Fast Write if enabled and coretalk packet type is a GFX request */
+#define CA_PIO_PCI_MEM                  0x40000000
+#define CA_PIO_PCI_MEM_LEN              0xc0000000
+
+/*
+ * DMA space
+ *
+ * The CA aperature (ie. bus address range) mapped by the GART is segmented into
+ * two parts.  The lower portion of the aperature is used for mapping 32 bit
+ * PCI addresses which are managed by the dma interfaces in this file.  The
+ * upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
+ * The AGP portion of the aperature is managed by the agpgart_be.c driver
+ * in drivers/linux/agp.  There are ca-specific hooks in that driver to
+ * manipulate the gart, but management of the AGP portion of the aperature
+ * is the responsibility of that driver.
+ *
+ * CA allows three main types of DMA mapping:
+ *
+ * PCI 64-bit   Managed by this driver
+ * PCI 32-bit   Managed by this driver
+ * AGP 48-bit   Managed by hooks in the /dev/agpgart driver
+ *
+ * All of the above can optionally be remapped through the GART.  The following
+ * table lists the combinations of addressing types and GART remapping that
+ * is currently supported by the driver (h/w supports all, s/w limits this):
+ *
+ *              PCI64           PCI32           AGP48
+ * GART         no              yes             yes
+ * Direct       yes             yes             no
+ *
+ * GART remapping of PCI64 is not done because there is no need to.  The
+ * 64 bit PCI address holds all of the information necessary to target any
+ * memory in the system.
+ *
+ * AGP48 is always mapped through the GART.  Management of the AGP48 portion
+ * of the aperature is the responsibility of code in the agpgart_be driver.
+ *
+ * The non-64 bit bus address space will currently be partitioned like this:
+ *
+ *      0xffff_ffff_ffff        +--------
+ *                              | AGP48 direct
+ *                              | Space managed by this driver
+ *      CA_AGP_DIRECT_BASE      +--------
+ *                              | AGP GART mapped (gfx aperature)
+ *                              | Space managed by /dev/agpgart driver
+ *                              | This range is exposed to the agpgart
+ *                              | driver as the "graphics aperature"
+ *      CA_AGP_MAPPED_BASE      +-----
+ *                              | PCI GART mapped
+ *                              | Space managed by this driver          
+ *      CA_PCI32_MAPPED_BASE    +----
+ *                              | PCI32 direct
+ *                              | Space managed by this driver
+ *      0xC000_0000             +--------
+ *      (CA_PCI32_DIRECT_BASE)
+ *
+ * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
+ * is what we call the CA aperature.  Addresses falling in this range will
+ * be remapped using the GART.
+ *
+ * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
+ * is what we call the graphics aperature.  This is a subset of the CA
+ * aperature and is under the control of the agpgart_be driver.
+ *
+ * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
+ * somewhat arbitrary values.  The known constraints on choosing these is:
+ *
+ * 1)  CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
+ *     must be one of the values supported by the ca_gart_aperature register.
+ *     Currently valid values are: 4MB through 4096MB in powers of 2 increments
+ *
+ * 2)  CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
+ *     must be in MB units since that's what the agpgart driver assumes.
+ */
+
+/*
+ * Define Bus DMA ranges.  These are configurable (see constraints above)
+ * and will probably need tuning based on experience.
+ */
+
+
+/*
+ * 11/24/03
+ * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
+ * generally unusable.  The problem is that for PCI direct 32 
+ * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
+ * of the coretalk address, and coretalk bits 38:32 come from a register.
+ * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
+ * for DMA (the rest is allocated to PIO), host node addresses need to be
+ * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
+ * as well.  So there can be no PCI32 direct DMA below 3GB!!  For this
+ * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
+ * tioca_dma_direct32() a noop but preserves the code flow should this issue
+ * be fixed in a respin.
+ *
+ * For now, all PCI32 DMA's must be mapped through the GART.
+ */
+
+#define CA_PCI32_DIRECT_BASE    0xC0000000UL    /* BASE not configurable */
+#define CA_PCI32_DIRECT_SIZE    0x00000000UL    /* 0 MB */
+
+#define CA_PCI32_MAPPED_BASE    0xC0000000UL
+#define CA_PCI32_MAPPED_SIZE    0x40000000UL    /* 2GB */
+
+#define CA_AGP_MAPPED_BASE      0x80000000UL
+#define CA_AGP_MAPPED_SIZE      0x40000000UL    /* 2GB */
+
+#define CA_AGP_DIRECT_BASE      0x40000000UL    /* 2GB */
+#define CA_AGP_DIRECT_SIZE      0x40000000UL
+
+#define CA_APERATURE_BASE       (CA_AGP_MAPPED_BASE)
+#define CA_APERATURE_SIZE       (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
+
+#endif  /* _ASM_IA64_SN_TIO_TIOCA_H */
diff --git a/arch/ia64/include/asm/sn/tioca_provider.h b/arch/ia64/include/asm/sn/tioca_provider.h
new file mode 100644
index 000000000000..9a820ac61be3
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioca_provider.h
@@ -0,0 +1,207 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
+#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
+
+#include <asm/sn/tioca.h>
+
+/*
+ * WAR enables
+ * Defines for individual WARs. Each is a bitmask of applicable
+ * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
+ * (3 << 1) == (rev A or rev B), etc
+ */
+
+#define TIOCA_WAR_ENABLED(pv, tioca_common) \
+        ((1 << tioca_common->ca_rev) & pv)
+
+  /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
+#define PV907908 (1 << 1)
+  /* ATI config space problems after BIOS execution starts */
+#define PV908234 (1 << 1)
+  /* CA:AGPDMA write request data mismatch with ABC1CL merge */
+#define PV895469 (1 << 1)
+  /* TIO:CA TLB invalidate of written GART entries possibly not occurring in CA*/
+#define PV910244 (1 << 1)
+
+struct tioca_dmamap{
+        struct list_head        cad_list;       /* headed by ca_list */
+
+        dma_addr_t              cad_dma_addr;   /* Linux dma handle */
+        uint                    cad_gart_entry; /* start entry in ca_gart_pagemap */
+        uint                    cad_gart_size;  /* #entries for this map */
+};
+
+/*
+ * Kernel only fields.  Prom may look at this stuff for debugging only.
+ * Access this structure through the ca_kernel_private ptr.
+ */
+
+struct tioca_common ;
+
+struct tioca_kernel {
+        struct tioca_common     *ca_common;     /* tioca this belongs to */
+        struct list_head        ca_list;        /* list of all ca's */
+        struct list_head        ca_dmamaps;
+        spinlock_t              ca_lock;        /* Kernel lock */
+        cnodeid_t               ca_closest_node;
+        struct list_head        *ca_devices;    /* bus->devices */
+
+        /*
+         * General GART stuff
+         */
+        u64     ca_ap_size;             /* size of aperature in bytes */
+        u32     ca_gart_entries;        /* # u64 entries in gart */
+        u32     ca_ap_pagesize;         /* aperature page size in bytes */
+        u64     ca_ap_bus_base;         /* bus address of CA aperature */
+        u64     ca_gart_size;           /* gart size in bytes */
+        u64     *ca_gart;               /* gart table vaddr */
+        u64     ca_gart_coretalk_addr;  /* gart coretalk addr */
+        u8              ca_gart_iscoherent;     /* used in tioca_tlbflush */
+
+        /* PCI GART convenience values */
+        u64     ca_pciap_base;          /* pci aperature bus base address */
+        u64     ca_pciap_size;          /* pci aperature size (bytes) */
+        u64     ca_pcigart_base;        /* gfx GART bus base address */
+        u64     *ca_pcigart;            /* gfx GART vm address */
+        u32     ca_pcigart_entries;
+        u32     ca_pcigart_start;       /* PCI start index in ca_gart */
+        void            *ca_pcigart_pagemap;
+
+        /* AGP GART convenience values */
+        u64     ca_gfxap_base;          /* gfx aperature bus base address */
+        u64     ca_gfxap_size;          /* gfx aperature size (bytes) */
+        u64     ca_gfxgart_base;        /* gfx GART bus base address */
+        u64     *ca_gfxgart;            /* gfx GART vm address */
+        u32     ca_gfxgart_entries;
+        u32     ca_gfxgart_start;       /* agpgart start index in ca_gart */
+};
+
+/*
+ * Common tioca info shared between kernel and prom
+ *
+ * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
+ * TO THE PROM VERSION.
+ */
+
+struct tioca_common {
+        struct pcibus_bussoft   ca_common;      /* common pciio header */
+
+        u32             ca_rev;
+        u32             ca_closest_nasid;
+
+        u64             ca_prom_private;
+        u64             ca_kernel_private;
+};
+
+/**
+ * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
+ * @paddr: page address to convert
+ *
+ * Convert a system [coretalk] address to a GART entry.  GART entries are
+ * formed using the following:
+ *
+ *     data = ( (1<<63) |  ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) | 
+ * (REMAP_SYS_ADDR) ) >> 12 )
+ *
+ * DATA written to 1 GART TABLE Entry in system memory is remapped system
+ * addr for 1 page 
+ *
+ * The data is for coretalk address format right shifted 12 bits with a
+ * valid bit.
+ *
+ *      GART_TABLE_ENTRY [ 25:0 ]  -- REMAP_SYS_ADDRESS[37:12].
+ *      GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
+ *      GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
+ *      GART_TABLE_ENTRY [ 63 ]    -- Valid Bit 
+ */
+static inline u64
+tioca_paddr_to_gart(unsigned long paddr)
+{
+        /*
+         * We are assuming right now that paddr already has the correct
+         * format since the address from xtalk_dmaXXX should already have
+         * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
+         */
+
+        return ((paddr) >> 12) | (1UL << 63);
+}
+
+/**
+ * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
+ * @page_addr: system page address to map
+ */
+
+static inline unsigned long
+tioca_physpage_to_gart(u64 page_addr)
+{
+        u64 coretalk_addr;
+
+        coretalk_addr = PHYS_TO_TIODMA(page_addr);
+        if (!coretalk_addr) {
+                return 0;
+        }
+
+        return tioca_paddr_to_gart(coretalk_addr);
+}
+
+/**
+ * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
+ * @tioca_kernel: CA context 
+ *
+ * Invalidate tlb entries for a given CA GART.  Main complexity is to account
+ * for revA bug.
+ */
+static inline void
+tioca_tlbflush(struct tioca_kernel *tioca_kernel)
+{
+        volatile u64 tmp;
+        volatile struct tioca __iomem *ca_base;
+        struct tioca_common *tioca_common;
+
+        tioca_common = tioca_kernel->ca_common;
+        ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
+
+        /*
+         * Explicit flushes not needed if GART is in cached mode
+         */
+        if (tioca_kernel->ca_gart_iscoherent) {
+                if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
+                        /*
+                         * PV910244:  RevA CA needs explicit flushes.
+                         * Need to put GART into uncached mode before
+                         * flushing otherwise the explicit flush is ignored.
+                         *
+                         * Alternate WAR would be to leave GART cached and
+                         * touch every CL aligned GART entry.
+                         */
+
+                        __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
+                        __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
+                        __sn_setq_relaxed(&ca_base->ca_control2,
+                            (0x2ull << CA_GART_MEM_PARAM_SHFT));
+                        tmp = __sn_readq_relaxed(&ca_base->ca_control2);
+                }
+
+                return;
+        }
+
+        /*
+         * Gart in uncached mode ... need an explicit flush.
+         */
+
+        __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
+        tmp = __sn_readq_relaxed(&ca_base->ca_control2);
+}
+
+extern u32      tioca_gart_found;
+extern struct list_head tioca_list;
+extern int tioca_init_provider(void);
+extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
+#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/tioce.h b/arch/ia64/include/asm/sn/tioce.h
new file mode 100644
index 000000000000..893468e1b41b
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioce.h
@@ -0,0 +1,760 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_IA64_SN_TIOCE_H__
+#define __ASM_IA64_SN_TIOCE_H__
+
+/* CE ASIC part & mfgr information  */
+#define TIOCE_PART_NUM                  0xCE00
+#define TIOCE_SRC_ID                    0x01
+#define TIOCE_REV_A                     0x1
+
+/* CE Virtual PPB Vendor/Device IDs */
+#define CE_VIRT_PPB_VENDOR_ID           0x10a9
+#define CE_VIRT_PPB_DEVICE_ID           0x4002
+
+/* CE Host Bridge Vendor/Device IDs */
+#define CE_HOST_BRIDGE_VENDOR_ID        0x10a9
+#define CE_HOST_BRIDGE_DEVICE_ID        0x4001
+
+
+#define TIOCE_NUM_M40_ATES              4096
+#define TIOCE_NUM_M3240_ATES            2048
+#define TIOCE_NUM_PORTS                 2
+
+/*
+ * Register layout for TIOCE.  MMR offsets are shown at the far right of the
+ * structure definition.
+ */
+typedef volatile struct tioce {
+        /*
+         * ADMIN : Administration Registers
+         */
+        u64     ce_adm_id;                              /* 0x000000 */
+        u64     ce_pad_000008;                          /* 0x000008 */
+        u64     ce_adm_dyn_credit_status;               /* 0x000010 */
+        u64     ce_adm_last_credit_status;              /* 0x000018 */
+        u64     ce_adm_credit_limit;                    /* 0x000020 */
+        u64     ce_adm_force_credit;                    /* 0x000028 */
+        u64     ce_adm_control;                         /* 0x000030 */
+        u64     ce_adm_mmr_chn_timeout;                 /* 0x000038 */
+        u64     ce_adm_ssp_ure_timeout;                 /* 0x000040 */
+        u64     ce_adm_ssp_dre_timeout;                 /* 0x000048 */
+        u64     ce_adm_ssp_debug_sel;                   /* 0x000050 */
+        u64     ce_adm_int_status;                      /* 0x000058 */
+        u64     ce_adm_int_status_alias;                /* 0x000060 */
+        u64     ce_adm_int_mask;                        /* 0x000068 */
+        u64     ce_adm_int_pending;                     /* 0x000070 */
+        u64     ce_adm_force_int;                       /* 0x000078 */
+        u64     ce_adm_ure_ups_buf_barrier_flush;       /* 0x000080 */
+        u64     ce_adm_int_dest[15];        /* 0x000088 -- 0x0000F8 */
+        u64     ce_adm_error_summary;                   /* 0x000100 */
+        u64     ce_adm_error_summary_alias;             /* 0x000108 */
+        u64     ce_adm_error_mask;                      /* 0x000110 */
+        u64     ce_adm_first_error;                     /* 0x000118 */
+        u64     ce_adm_error_overflow;                  /* 0x000120 */
+        u64     ce_adm_error_overflow_alias;            /* 0x000128 */
+        u64     ce_pad_000130[2];           /* 0x000130 -- 0x000138 */
+        u64     ce_adm_tnum_error;                      /* 0x000140 */
+        u64     ce_adm_mmr_err_detail;                  /* 0x000148 */
+        u64     ce_adm_msg_sram_perr_detail;            /* 0x000150 */
+        u64     ce_adm_bap_sram_perr_detail;            /* 0x000158 */
+        u64     ce_adm_ce_sram_perr_detail;             /* 0x000160 */
+        u64     ce_adm_ce_credit_oflow_detail;          /* 0x000168 */
+        u64     ce_adm_tx_link_idle_max_timer;          /* 0x000170 */
+        u64     ce_adm_pcie_debug_sel;                  /* 0x000178 */
+        u64     ce_pad_000180[16];          /* 0x000180 -- 0x0001F8 */
+
+        u64     ce_adm_pcie_debug_sel_top;              /* 0x000200 */
+        u64     ce_adm_pcie_debug_lat_sel_lo_top;       /* 0x000208 */
+        u64     ce_adm_pcie_debug_lat_sel_hi_top;       /* 0x000210 */
+        u64     ce_adm_pcie_debug_trig_sel_top;         /* 0x000218 */
+        u64     ce_adm_pcie_debug_trig_lat_sel_lo_top;  /* 0x000220 */
+        u64     ce_adm_pcie_debug_trig_lat_sel_hi_top;  /* 0x000228 */
+        u64     ce_adm_pcie_trig_compare_top;           /* 0x000230 */
+        u64     ce_adm_pcie_trig_compare_en_top;        /* 0x000238 */
+        u64     ce_adm_ssp_debug_sel_top;               /* 0x000240 */
+        u64     ce_adm_ssp_debug_lat_sel_lo_top;        /* 0x000248 */
+        u64     ce_adm_ssp_debug_lat_sel_hi_top;        /* 0x000250 */
+        u64     ce_adm_ssp_debug_trig_sel_top;          /* 0x000258 */
+        u64     ce_adm_ssp_debug_trig_lat_sel_lo_top;   /* 0x000260 */
+        u64     ce_adm_ssp_debug_trig_lat_sel_hi_top;   /* 0x000268 */
+        u64     ce_adm_ssp_trig_compare_top;            /* 0x000270 */
+        u64     ce_adm_ssp_trig_compare_en_top;         /* 0x000278 */
+        u64     ce_pad_000280[48];          /* 0x000280 -- 0x0003F8 */
+
+        u64     ce_adm_bap_ctrl;                        /* 0x000400 */
+        u64     ce_pad_000408[127];         /* 0x000408 -- 0x0007F8 */
+
+        u64     ce_msg_buf_data63_0[35];    /* 0x000800 -- 0x000918 */
+        u64     ce_pad_000920[29];          /* 0x000920 -- 0x0009F8 */
+
+        u64     ce_msg_buf_data127_64[35];  /* 0x000A00 -- 0x000B18 */
+        u64     ce_pad_000B20[29];          /* 0x000B20 -- 0x000BF8 */
+
+        u64     ce_msg_buf_parity[35];      /* 0x000C00 -- 0x000D18 */
+        u64     ce_pad_000D20[29];          /* 0x000D20 -- 0x000DF8 */
+
+        u64     ce_pad_000E00[576];         /* 0x000E00 -- 0x001FF8 */
+
+        /*
+         * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
+         * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
+         * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
+         */
+        #define ce_lsi(link_num)        ce_lsi[link_num-1]
+        struct ce_lsi_reg {
+                u64     ce_lsi_lpu_id;                  /* 0x00z000 */
+                u64     ce_lsi_rst;                     /* 0x00z008 */
+                u64     ce_lsi_dbg_stat;                /* 0x00z010 */
+                u64     ce_lsi_dbg_cfg;                 /* 0x00z018 */
+                u64     ce_lsi_ltssm_ctrl;              /* 0x00z020 */
+                u64     ce_lsi_lk_stat;                 /* 0x00z028 */
+                u64     ce_pad_00z030[2];   /* 0x00z030 -- 0x00z038 */
+                u64     ce_lsi_int_and_stat;            /* 0x00z040 */
+                u64     ce_lsi_int_mask;                /* 0x00z048 */
+                u64     ce_pad_00z050[22];  /* 0x00z050 -- 0x00z0F8 */
+                u64     ce_lsi_lk_perf_cnt_sel;         /* 0x00z100 */
+                u64     ce_pad_00z108;                  /* 0x00z108 */
+                u64     ce_lsi_lk_perf_cnt_ctrl;        /* 0x00z110 */
+                u64     ce_pad_00z118;                  /* 0x00z118 */
+                u64     ce_lsi_lk_perf_cnt1;            /* 0x00z120 */
+                u64     ce_lsi_lk_perf_cnt1_test;       /* 0x00z128 */
+                u64     ce_lsi_lk_perf_cnt2;            /* 0x00z130 */
+                u64     ce_lsi_lk_perf_cnt2_test;       /* 0x00z138 */
+                u64     ce_pad_00z140[24];  /* 0x00z140 -- 0x00z1F8 */
+                u64     ce_lsi_lk_lyr_cfg;              /* 0x00z200 */
+                u64     ce_lsi_lk_lyr_status;           /* 0x00z208 */
+                u64     ce_lsi_lk_lyr_int_stat;         /* 0x00z210 */
+                u64     ce_lsi_lk_ly_int_stat_test;     /* 0x00z218 */
+                u64     ce_lsi_lk_ly_int_stat_mask;     /* 0x00z220 */
+                u64     ce_pad_00z228[3];   /* 0x00z228 -- 0x00z238 */
+                u64     ce_lsi_fc_upd_ctl;              /* 0x00z240 */
+                u64     ce_pad_00z248[3];   /* 0x00z248 -- 0x00z258 */
+                u64     ce_lsi_flw_ctl_upd_to_timer;    /* 0x00z260 */
+                u64     ce_lsi_flw_ctl_upd_timer0;      /* 0x00z268 */
+                u64     ce_lsi_flw_ctl_upd_timer1;      /* 0x00z270 */
+                u64     ce_pad_00z278[49];  /* 0x00z278 -- 0x00z3F8 */
+                u64     ce_lsi_freq_nak_lat_thrsh;      /* 0x00z400 */
+                u64     ce_lsi_ack_nak_lat_tmr;         /* 0x00z408 */
+                u64     ce_lsi_rply_tmr_thr;            /* 0x00z410 */
+                u64     ce_lsi_rply_tmr;                /* 0x00z418 */
+                u64     ce_lsi_rply_num_stat;           /* 0x00z420 */
+                u64     ce_lsi_rty_buf_max_addr;        /* 0x00z428 */
+                u64     ce_lsi_rty_fifo_ptr;            /* 0x00z430 */
+                u64     ce_lsi_rty_fifo_rd_wr_ptr;      /* 0x00z438 */
+                u64     ce_lsi_rty_fifo_cred;           /* 0x00z440 */
+                u64     ce_lsi_seq_cnt;                 /* 0x00z448 */
+                u64     ce_lsi_ack_sent_seq_num;        /* 0x00z450 */
+                u64     ce_lsi_seq_cnt_fifo_max_addr;   /* 0x00z458 */
+                u64     ce_lsi_seq_cnt_fifo_ptr;        /* 0x00z460 */
+                u64     ce_lsi_seq_cnt_rd_wr_ptr;       /* 0x00z468 */
+                u64     ce_lsi_tx_lk_ts_ctl;            /* 0x00z470 */
+                u64     ce_pad_00z478;                  /* 0x00z478 */
+                u64     ce_lsi_mem_addr_ctl;            /* 0x00z480 */
+                u64     ce_lsi_mem_d_ld0;               /* 0x00z488 */
+                u64     ce_lsi_mem_d_ld1;               /* 0x00z490 */
+                u64     ce_lsi_mem_d_ld2;               /* 0x00z498 */
+                u64     ce_lsi_mem_d_ld3;               /* 0x00z4A0 */
+                u64     ce_lsi_mem_d_ld4;               /* 0x00z4A8 */
+                u64     ce_pad_00z4B0[2];   /* 0x00z4B0 -- 0x00z4B8 */
+                u64     ce_lsi_rty_d_cnt;               /* 0x00z4C0 */
+                u64     ce_lsi_seq_buf_cnt;             /* 0x00z4C8 */
+                u64     ce_lsi_seq_buf_bt_d;            /* 0x00z4D0 */
+                u64     ce_pad_00z4D8;                  /* 0x00z4D8 */
+                u64     ce_lsi_ack_lat_thr;             /* 0x00z4E0 */
+                u64     ce_pad_00z4E8[3];   /* 0x00z4E8 -- 0x00z4F8 */
+                u64     ce_lsi_nxt_rcv_seq_1_cntr;      /* 0x00z500 */
+                u64     ce_lsi_unsp_dllp_rcvd;          /* 0x00z508 */
+                u64     ce_lsi_rcv_lk_ts_ctl;           /* 0x00z510 */
+                u64     ce_pad_00z518[29];  /* 0x00z518 -- 0x00z5F8 */
+                u64     ce_lsi_phy_lyr_cfg;             /* 0x00z600 */
+                u64     ce_pad_00z608;                  /* 0x00z608 */
+                u64     ce_lsi_phy_lyr_int_stat;        /* 0x00z610 */
+                u64     ce_lsi_phy_lyr_int_stat_test;   /* 0x00z618 */
+                u64     ce_lsi_phy_lyr_int_mask;        /* 0x00z620 */
+                u64     ce_pad_00z628[11];  /* 0x00z628 -- 0x00z678 */
+                u64     ce_lsi_rcv_phy_cfg;             /* 0x00z680 */
+                u64     ce_lsi_rcv_phy_stat1;           /* 0x00z688 */
+                u64     ce_lsi_rcv_phy_stat2;           /* 0x00z690 */
+                u64     ce_lsi_rcv_phy_stat3;           /* 0x00z698 */
+                u64     ce_lsi_rcv_phy_int_stat;        /* 0x00z6A0 */
+                u64     ce_lsi_rcv_phy_int_stat_test;   /* 0x00z6A8 */
+                u64     ce_lsi_rcv_phy_int_mask;        /* 0x00z6B0 */
+                u64     ce_pad_00z6B8[9];   /* 0x00z6B8 -- 0x00z6F8 */
+                u64     ce_lsi_tx_phy_cfg;              /* 0x00z700 */
+                u64     ce_lsi_tx_phy_stat;             /* 0x00z708 */
+                u64     ce_lsi_tx_phy_int_stat;         /* 0x00z710 */
+                u64     ce_lsi_tx_phy_int_stat_test;    /* 0x00z718 */
+                u64     ce_lsi_tx_phy_int_mask;         /* 0x00z720 */
+                u64     ce_lsi_tx_phy_stat2;            /* 0x00z728 */
+                u64     ce_pad_00z730[10];  /* 0x00z730 -- 0x00z77F */
+                u64     ce_lsi_ltssm_cfg1;              /* 0x00z780 */
+                u64     ce_lsi_ltssm_cfg2;              /* 0x00z788 */
+                u64     ce_lsi_ltssm_cfg3;              /* 0x00z790 */
+                u64     ce_lsi_ltssm_cfg4;              /* 0x00z798 */
+                u64     ce_lsi_ltssm_cfg5;              /* 0x00z7A0 */
+                u64     ce_lsi_ltssm_stat1;             /* 0x00z7A8 */
+                u64     ce_lsi_ltssm_stat2;             /* 0x00z7B0 */
+                u64     ce_lsi_ltssm_int_stat;          /* 0x00z7B8 */
+                u64     ce_lsi_ltssm_int_stat_test;     /* 0x00z7C0 */
+                u64     ce_lsi_ltssm_int_mask;          /* 0x00z7C8 */
+                u64     ce_lsi_ltssm_stat_wr_en;        /* 0x00z7D0 */
+                u64     ce_pad_00z7D8[5];   /* 0x00z7D8 -- 0x00z7F8 */
+                u64     ce_lsi_gb_cfg1;                 /* 0x00z800 */
+                u64     ce_lsi_gb_cfg2;                 /* 0x00z808 */
+                u64     ce_lsi_gb_cfg3;                 /* 0x00z810 */
+                u64     ce_lsi_gb_cfg4;                 /* 0x00z818 */
+                u64     ce_lsi_gb_stat;                 /* 0x00z820 */
+                u64     ce_lsi_gb_int_stat;             /* 0x00z828 */
+                u64     ce_lsi_gb_int_stat_test;        /* 0x00z830 */
+                u64     ce_lsi_gb_int_mask;             /* 0x00z838 */
+                u64     ce_lsi_gb_pwr_dn1;              /* 0x00z840 */
+                u64     ce_lsi_gb_pwr_dn2;              /* 0x00z848 */
+                u64     ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
+        } ce_lsi[2];
+
+        u64     ce_pad_004000[10];          /* 0x004000 -- 0x004048 */
+
+        /*
+         * CRM: Coretalk Receive Module Registers
+         */
+        u64     ce_crm_debug_mux;                       /* 0x004050 */
+        u64     ce_pad_004058;                          /* 0x004058 */
+        u64     ce_crm_ssp_err_cmd_wrd;                 /* 0x004060 */
+        u64     ce_crm_ssp_err_addr;                    /* 0x004068 */
+        u64     ce_crm_ssp_err_syn;                     /* 0x004070 */
+
+        u64     ce_pad_004078[499];         /* 0x004078 -- 0x005008 */
+
+        /*
+         * CXM: Coretalk Xmit Module Registers
+         */
+        u64     ce_cxm_dyn_credit_status;               /* 0x005010 */
+        u64     ce_cxm_last_credit_status;              /* 0x005018 */
+        u64     ce_cxm_credit_limit;                    /* 0x005020 */
+        u64     ce_cxm_force_credit;                    /* 0x005028 */
+        u64     ce_cxm_disable_bypass;                  /* 0x005030 */
+        u64     ce_pad_005038[3];           /* 0x005038 -- 0x005048 */
+        u64     ce_cxm_debug_mux;                       /* 0x005050 */
+
+        u64        ce_pad_005058[501];         /* 0x005058 -- 0x005FF8 */
+
+        /*
+         * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
+         * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
+         * DTL: the comment offsets at far right: let 'y' = {6 or 8}
+         *
+         * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
+         * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
+         * UTL: the comment offsets at far right: let 'z' = {7 or 9}
+         */
+        #define ce_dtl(link_num)        ce_dtl_utl[link_num-1]
+        #define ce_utl(link_num)        ce_dtl_utl[link_num-1]
+        struct ce_dtl_utl_reg {
+                /* DTL */
+                u64     ce_dtl_dtdr_credit_limit;       /* 0x00y000 */
+                u64     ce_dtl_dtdr_credit_force;       /* 0x00y008 */
+                u64     ce_dtl_dyn_credit_status;       /* 0x00y010 */
+                u64     ce_dtl_dtl_last_credit_stat;    /* 0x00y018 */
+                u64     ce_dtl_dtl_ctrl;                /* 0x00y020 */
+                u64     ce_pad_00y028[5];   /* 0x00y028 -- 0x00y048 */
+                u64     ce_dtl_debug_sel;               /* 0x00y050 */
+                u64     ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
+
+                /* UTL */
+                u64     ce_utl_utl_ctrl;                /* 0x00z000 */
+                u64     ce_utl_debug_sel;               /* 0x00z008 */
+                u64     ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
+        } ce_dtl_utl[2];
+
+        u64     ce_pad_00A000[514];         /* 0x00A000 -- 0x00B008 */
+
+        /*
+         * URE: Upstream Request Engine
+         */
+        u64     ce_ure_dyn_credit_status;               /* 0x00B010 */
+        u64     ce_ure_last_credit_status;              /* 0x00B018 */
+        u64     ce_ure_credit_limit;                    /* 0x00B020 */
+        u64     ce_pad_00B028;                          /* 0x00B028 */
+        u64     ce_ure_control;                         /* 0x00B030 */
+        u64     ce_ure_status;                          /* 0x00B038 */
+        u64     ce_pad_00B040[2];           /* 0x00B040 -- 0x00B048 */
+        u64     ce_ure_debug_sel;                       /* 0x00B050 */
+        u64     ce_ure_pcie_debug_sel;                  /* 0x00B058 */
+        u64     ce_ure_ssp_err_cmd_wrd;                 /* 0x00B060 */
+        u64     ce_ure_ssp_err_addr;                    /* 0x00B068 */
+        u64     ce_ure_page_map;                        /* 0x00B070 */
+        u64     ce_ure_dir_map[TIOCE_NUM_PORTS];        /* 0x00B078 */
+        u64     ce_ure_pipe_sel1;                       /* 0x00B088 */
+        u64     ce_ure_pipe_mask1;                      /* 0x00B090 */
+        u64     ce_ure_pipe_sel2;                       /* 0x00B098 */
+        u64     ce_ure_pipe_mask2;                      /* 0x00B0A0 */
+        u64     ce_ure_pcie1_credits_sent;              /* 0x00B0A8 */
+        u64     ce_ure_pcie1_credits_used;              /* 0x00B0B0 */
+        u64     ce_ure_pcie1_credit_limit;              /* 0x00B0B8 */
+        u64     ce_ure_pcie2_credits_sent;              /* 0x00B0C0 */
+        u64     ce_ure_pcie2_credits_used;              /* 0x00B0C8 */
+        u64     ce_ure_pcie2_credit_limit;              /* 0x00B0D0 */
+        u64     ce_ure_pcie_force_credit;               /* 0x00B0D8 */
+        u64     ce_ure_rd_tnum_val;                     /* 0x00B0E0 */
+        u64     ce_ure_rd_tnum_rsp_rcvd;                /* 0x00B0E8 */
+        u64     ce_ure_rd_tnum_esent_timer;             /* 0x00B0F0 */
+        u64     ce_ure_rd_tnum_error;                   /* 0x00B0F8 */
+        u64     ce_ure_rd_tnum_first_cl;                /* 0x00B100 */
+        u64     ce_ure_rd_tnum_link_buf;                /* 0x00B108 */
+        u64     ce_ure_wr_tnum_val;                     /* 0x00B110 */
+        u64     ce_ure_sram_err_addr0;                  /* 0x00B118 */
+        u64     ce_ure_sram_err_addr1;                  /* 0x00B120 */
+        u64     ce_ure_sram_err_addr2;                  /* 0x00B128 */
+        u64     ce_ure_sram_rd_addr0;                   /* 0x00B130 */
+        u64     ce_ure_sram_rd_addr1;                   /* 0x00B138 */
+        u64     ce_ure_sram_rd_addr2;                   /* 0x00B140 */
+        u64     ce_ure_sram_wr_addr0;                   /* 0x00B148 */
+        u64     ce_ure_sram_wr_addr1;                   /* 0x00B150 */
+        u64     ce_ure_sram_wr_addr2;                   /* 0x00B158 */
+        u64     ce_ure_buf_flush10;                     /* 0x00B160 */
+        u64     ce_ure_buf_flush11;                     /* 0x00B168 */
+        u64     ce_ure_buf_flush12;                     /* 0x00B170 */
+        u64     ce_ure_buf_flush13;                     /* 0x00B178 */
+        u64     ce_ure_buf_flush20;                     /* 0x00B180 */
+        u64     ce_ure_buf_flush21;                     /* 0x00B188 */
+        u64     ce_ure_buf_flush22;                     /* 0x00B190 */
+        u64     ce_ure_buf_flush23;                     /* 0x00B198 */
+        u64     ce_ure_pcie_control1;                   /* 0x00B1A0 */
+        u64     ce_ure_pcie_control2;                   /* 0x00B1A8 */
+
+        u64     ce_pad_00B1B0[458];         /* 0x00B1B0 -- 0x00BFF8 */
+
+        /* Upstream Data Buffer, Port1 */
+        struct ce_ure_maint_ups_dat1_data {
+                u64     data63_0[512];      /* 0x00C000 -- 0x00CFF8 */
+                u64     data127_64[512];    /* 0x00D000 -- 0x00DFF8 */
+                u64     parity[512];        /* 0x00E000 -- 0x00EFF8 */
+        } ce_ure_maint_ups_dat1;
+
+        /* Upstream Header Buffer, Port1 */
+        struct ce_ure_maint_ups_hdr1_data {
+                u64     data63_0[512];      /* 0x00F000 -- 0x00FFF8 */
+                u64     data127_64[512];    /* 0x010000 -- 0x010FF8 */
+                u64     parity[512];        /* 0x011000 -- 0x011FF8 */
+        } ce_ure_maint_ups_hdr1;
+
+        /* Upstream Data Buffer, Port2 */
+        struct ce_ure_maint_ups_dat2_data {
+                u64     data63_0[512];      /* 0x012000 -- 0x012FF8 */
+                u64     data127_64[512];    /* 0x013000 -- 0x013FF8 */
+                u64     parity[512];        /* 0x014000 -- 0x014FF8 */
+        } ce_ure_maint_ups_dat2;
+
+        /* Upstream Header Buffer, Port2 */
+        struct ce_ure_maint_ups_hdr2_data {
+                u64     data63_0[512];      /* 0x015000 -- 0x015FF8 */
+                u64     data127_64[512];    /* 0x016000 -- 0x016FF8 */
+                u64     parity[512];        /* 0x017000 -- 0x017FF8 */
+        } ce_ure_maint_ups_hdr2;
+
+        /* Downstream Data Buffer */
+        struct ce_ure_maint_dns_dat_data {
+                u64     data63_0[512];      /* 0x018000 -- 0x018FF8 */
+                u64     data127_64[512];    /* 0x019000 -- 0x019FF8 */
+                u64     parity[512];        /* 0x01A000 -- 0x01AFF8 */
+        } ce_ure_maint_dns_dat;
+
+        /* Downstream Header Buffer */
+        struct  ce_ure_maint_dns_hdr_data {
+                u64     data31_0[64];       /* 0x01B000 -- 0x01B1F8 */
+                u64     data95_32[64];      /* 0x01B200 -- 0x01B3F8 */
+                u64     parity[64];         /* 0x01B400 -- 0x01B5F8 */
+        } ce_ure_maint_dns_hdr;
+
+        /* RCI Buffer Data */
+        struct  ce_ure_maint_rci_data {
+                u64     data41_0[64];       /* 0x01B600 -- 0x01B7F8 */
+                u64     data69_42[64];      /* 0x01B800 -- 0x01B9F8 */
+        } ce_ure_maint_rci;
+
+        /* Response Queue */
+        u64     ce_ure_maint_rspq[64];      /* 0x01BA00 -- 0x01BBF8 */
+
+        u64     ce_pad_01C000[4224];        /* 0x01BC00 -- 0x023FF8 */
+
+        /* Admin Build-a-Packet Buffer */
+        struct  ce_adm_maint_bap_buf_data {
+                u64     data63_0[258];      /* 0x024000 -- 0x024808 */
+                u64     data127_64[258];    /* 0x024810 -- 0x025018 */
+                u64     parity[258];        /* 0x025020 -- 0x025828 */
+        } ce_adm_maint_bap_buf;
+
+        u64     ce_pad_025830[5370];        /* 0x025830 -- 0x02FFF8 */
+
+        /* URE: 40bit PMU ATE Buffer */             /* 0x030000 -- 0x037FF8 */
+        u64     ce_ure_ate40[TIOCE_NUM_M40_ATES];
+
+        /* URE: 32/40bit PMU ATE Buffer */          /* 0x038000 -- 0x03BFF8 */
+        u64     ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
+
+        u64     ce_pad_03C000[2050];        /* 0x03C000 -- 0x040008 */
+
+        /*
+         * DRE: Down Stream Request Engine
+         */
+        u64     ce_dre_dyn_credit_status1;              /* 0x040010 */
+        u64     ce_dre_dyn_credit_status2;              /* 0x040018 */
+        u64     ce_dre_last_credit_status1;             /* 0x040020 */
+        u64     ce_dre_last_credit_status2;             /* 0x040028 */
+        u64     ce_dre_credit_limit1;                   /* 0x040030 */
+        u64     ce_dre_credit_limit2;                   /* 0x040038 */
+        u64     ce_dre_force_credit1;                   /* 0x040040 */
+        u64     ce_dre_force_credit2;                   /* 0x040048 */
+        u64     ce_dre_debug_mux1;                      /* 0x040050 */
+        u64     ce_dre_debug_mux2;                      /* 0x040058 */
+        u64     ce_dre_ssp_err_cmd_wrd;                 /* 0x040060 */
+        u64     ce_dre_ssp_err_addr;                    /* 0x040068 */
+        u64     ce_dre_comp_err_cmd_wrd;                /* 0x040070 */
+        u64     ce_dre_comp_err_addr;                   /* 0x040078 */
+        u64     ce_dre_req_status;                      /* 0x040080 */
+        u64     ce_dre_config1;                         /* 0x040088 */
+        u64     ce_dre_config2;                         /* 0x040090 */
+        u64     ce_dre_config_req_status;               /* 0x040098 */
+        u64     ce_pad_0400A0[12];          /* 0x0400A0 -- 0x0400F8 */
+        u64     ce_dre_dyn_fifo;                        /* 0x040100 */
+        u64     ce_pad_040108[3];           /* 0x040108 -- 0x040118 */
+        u64     ce_dre_last_fifo;                       /* 0x040120 */
+
+        u64     ce_pad_040128[27];          /* 0x040128 -- 0x0401F8 */
+
+        /* DRE Downstream Head Queue */
+        struct  ce_dre_maint_ds_head_queue {
+                u64     data63_0[32];       /* 0x040200 -- 0x0402F8 */
+                u64     data127_64[32];     /* 0x040300 -- 0x0403F8 */
+                u64     parity[32];         /* 0x040400 -- 0x0404F8 */
+        } ce_dre_maint_ds_head_q;
+
+        u64     ce_pad_040500[352];         /* 0x040500 -- 0x040FF8 */
+
+        /* DRE Downstream Data Queue */
+        struct  ce_dre_maint_ds_data_queue {
+                u64     data63_0[256];      /* 0x041000 -- 0x0417F8 */
+                u64     ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
+                u64     data127_64[256];    /* 0x042000 -- 0x0427F8 */
+                u64     ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
+                u64     parity[256];        /* 0x043000 -- 0x0437F8 */
+                u64     ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
+        } ce_dre_maint_ds_data_q;
+
+        /* DRE URE Upstream Response Queue */
+        struct  ce_dre_maint_ure_us_rsp_queue {
+                u64     data63_0[8];        /* 0x044000 -- 0x044038 */
+                u64     ce_pad_044040[24];  /* 0x044040 -- 0x0440F8 */
+                u64     data127_64[8];      /* 0x044100 -- 0x044138 */
+                u64     ce_pad_044140[24];  /* 0x044140 -- 0x0441F8 */
+                u64     parity[8];          /* 0x044200 -- 0x044238 */
+                u64     ce_pad_044240[24];  /* 0x044240 -- 0x0442F8 */
+        } ce_dre_maint_ure_us_rsp_q;
+
+        u64     ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
+
+        u64     ce_end_of_struct;                       /* 0x044400 */
+} tioce_t;
+
+/* ce_lsiX_gb_cfg1 register bit masks & shifts */
+#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT   0
+#define CE_LSI_GB_CFG1_RXL0S_THS_MASK   (0xffULL << 0)
+#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT   8
+#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK   (0xfULL << 8);
+#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT   12
+#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK   (0x7ULL << 12)
+#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT   15
+#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK   (0x1ULL << 15)
+#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT    16
+#define CE_LSI_GB_CFG1_LPBK_SEL_MASK    (0x3ULL << 16)
+#define CE_LSI_GB_CFG1_LPBK_EN_SHFT     18
+#define CE_LSI_GB_CFG1_LPBK_EN_MASK     (0x1ULL << 18)
+#define CE_LSI_GB_CFG1_RVRS_LB_SHFT     19
+#define CE_LSI_GB_CFG1_RVRS_LB_MASK     (0x1ULL << 19)
+#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT    20
+#define CE_LSI_GB_CFG1_RVRS_CLK_MASK    (0x3ULL << 20)
+#define CE_LSI_GB_CFG1_SLF_TS_SHFT      24
+#define CE_LSI_GB_CFG1_SLF_TS_MASK      (0xfULL << 24)
+
+/* ce_adm_int_mask/ce_adm_int_status register bit defines */
+#define CE_ADM_INT_CE_ERROR_SHFT                0
+#define CE_ADM_INT_LSI1_IP_ERROR_SHFT           1
+#define CE_ADM_INT_LSI2_IP_ERROR_SHFT           2
+#define CE_ADM_INT_PCIE_ERROR_SHFT              3
+#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT     4
+#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT     5
+#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT        6
+#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT        7
+#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT        8
+#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT        9
+#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT        10
+#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT        11
+#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT        12
+#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT        13
+#define CE_ADM_INT_PCIE_MSG_SHFT                14 /*see int_dest_14*/
+#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT         14
+#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT         15
+#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT         16
+#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT         17
+#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT        22
+#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT        23
+
+/* ce_adm_force_int register bit defines */
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT  0
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT  1
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT  2
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT  3
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT  4
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT  5
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT  6
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT  7
+#define CE_ADM_FORCE_INT_ALWAYS_SHFT            8
+
+/* ce_adm_int_dest register bit masks & shifts */
+#define INTR_VECTOR_SHFT                        56
+
+/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
+#define CE_ADM_ERR_CRM_SSP_REQ_INVALID                  (0x1ULL <<  0)
+#define CE_ADM_ERR_SSP_REQ_HEADER                       (0x1ULL <<  1)
+#define CE_ADM_ERR_SSP_RSP_HEADER                       (0x1ULL <<  2)
+#define CE_ADM_ERR_SSP_PROTOCOL_ERROR                   (0x1ULL <<  3)
+#define CE_ADM_ERR_SSP_SBE                              (0x1ULL <<  4)
+#define CE_ADM_ERR_SSP_MBE                              (0x1ULL <<  5)
+#define CE_ADM_ERR_CXM_CREDIT_OFLOW                     (0x1ULL <<  6)
+#define CE_ADM_ERR_DRE_SSP_REQ_INVAL                    (0x1ULL <<  7)
+#define CE_ADM_ERR_SSP_REQ_LONG                         (0x1ULL <<  8)
+#define CE_ADM_ERR_SSP_REQ_OFLOW                        (0x1ULL <<  9)
+#define CE_ADM_ERR_SSP_REQ_SHORT                        (0x1ULL << 10)
+#define CE_ADM_ERR_SSP_REQ_SIDEBAND                     (0x1ULL << 11)
+#define CE_ADM_ERR_SSP_REQ_ADDR_ERR                     (0x1ULL << 12)
+#define CE_ADM_ERR_SSP_REQ_BAD_BE                       (0x1ULL << 13)
+#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT                   (0x1ULL << 14)
+#define CE_ADM_ERR_PCIE_UNEXP_COMPL                     (0x1ULL << 15)
+#define CE_ADM_ERR_PCIE_ERR_COMPL                       (0x1ULL << 16)
+#define CE_ADM_ERR_DRE_CREDIT_OFLOW                     (0x1ULL << 17)
+#define CE_ADM_ERR_DRE_SRAM_PE                          (0x1ULL << 18)
+#define CE_ADM_ERR_SSP_RSP_INVALID                      (0x1ULL << 19)
+#define CE_ADM_ERR_SSP_RSP_LONG                         (0x1ULL << 20)
+#define CE_ADM_ERR_SSP_RSP_SHORT                        (0x1ULL << 21)
+#define CE_ADM_ERR_SSP_RSP_SIDEBAND                     (0x1ULL << 22)
+#define CE_ADM_ERR_URE_SSP_RSP_UNEXP                    (0x1ULL << 23)
+#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT               (0x1ULL << 24)
+#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT               (0x1ULL << 25)
+#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT               (0x1ULL << 26)
+#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT                 (0x1ULL << 27)
+#define CE_ADM_ERR_URE_CREDIT_OFLOW                     (0x1ULL << 28)
+#define CE_ADM_ERR_URE_SRAM_PE                          (0x1ULL << 29)
+#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP                    (0x1ULL << 30)
+#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT                  (0x1ULL << 31)
+#define CE_ADM_ERR_MMR_ACCESS_ERROR                     (0x1ULL << 32)
+#define CE_ADM_ERR_MMR_ADDR_ERROR                       (0x1ULL << 33)
+#define CE_ADM_ERR_ADM_CREDIT_OFLOW                     (0x1ULL << 34)
+#define CE_ADM_ERR_ADM_SRAM_PE                          (0x1ULL << 35)
+#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR            (0x1ULL << 36)
+#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR         (0x1ULL << 37)
+#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR        (0x1ULL << 38)
+#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR       (0x1ULL << 39)
+#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR            (0x1ULL << 40)
+#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR             (0x1ULL << 41)
+#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR         (0x1ULL << 42)
+#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR          (0x1ULL << 43)
+#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR          (0x1ULL << 44)
+#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR           (0x1ULL << 45)
+#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR            (0x1ULL << 46)
+#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR         (0x1ULL << 47)
+#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR        (0x1ULL << 48)
+#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR       (0x1ULL << 49)
+#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR            (0x1ULL << 50)
+#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR             (0x1ULL << 51)
+#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR         (0x1ULL << 52)
+#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR          (0x1ULL << 53)
+#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR          (0x1ULL << 54)
+#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR           (0x1ULL << 55)
+#define CE_ADM_ERR_PORT1_PCIE_COR_ERR                   (0x1ULL << 56)
+#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR                  (0x1ULL << 57)
+#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR                   (0x1ULL << 58)
+#define CE_ADM_ERR_PORT2_PCIE_COR_ERR                   (0x1ULL << 59)
+#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR                  (0x1ULL << 60)
+#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR                   (0x1ULL << 61)
+
+/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
+#define FLUSH_SEL_PORT1_PIPE0_SHFT      0
+#define FLUSH_SEL_PORT1_PIPE1_SHFT      4
+#define FLUSH_SEL_PORT1_PIPE2_SHFT      8
+#define FLUSH_SEL_PORT1_PIPE3_SHFT      12
+#define FLUSH_SEL_PORT2_PIPE0_SHFT      16
+#define FLUSH_SEL_PORT2_PIPE1_SHFT      20
+#define FLUSH_SEL_PORT2_PIPE2_SHFT      24
+#define FLUSH_SEL_PORT2_PIPE3_SHFT      28
+
+/* ce_dre_config1 register bit masks and shifts */
+#define CE_DRE_RO_ENABLE                (0x1ULL << 0)
+#define CE_DRE_DYN_RO_ENABLE            (0x1ULL << 1)
+#define CE_DRE_SUP_CONFIG_COMP_ERROR    (0x1ULL << 2)
+#define CE_DRE_SUP_IO_COMP_ERROR        (0x1ULL << 3)
+#define CE_DRE_ADDR_MODE_SHFT           4
+
+/* ce_dre_config_req_status register bit masks */
+#define CE_DRE_LAST_CONFIG_COMPLETION   (0x7ULL << 0)
+#define CE_DRE_DOWNSTREAM_CONFIG_ERROR  (0x1ULL << 3)
+#define CE_DRE_CONFIG_COMPLETION_VALID  (0x1ULL << 4)
+#define CE_DRE_CONFIG_REQUEST_ACTIVE    (0x1ULL << 5)
+
+/* ce_ure_control register bit masks & shifts */
+#define CE_URE_RD_MRG_ENABLE            (0x1ULL << 0)
+#define CE_URE_WRT_MRG_ENABLE1          (0x1ULL << 4)
+#define CE_URE_WRT_MRG_ENABLE2          (0x1ULL << 5)
+#define CE_URE_WRT_MRG_TIMER_SHFT       12
+#define CE_URE_WRT_MRG_TIMER_MASK       (0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
+#define CE_URE_WRT_MRG_TIMER(x)         (((u64)(x) << \
+                                          CE_URE_WRT_MRG_TIMER_SHFT) & \
+                                         CE_URE_WRT_MRG_TIMER_MASK)
+#define CE_URE_RSPQ_BYPASS_DISABLE      (0x1ULL << 24)
+#define CE_URE_UPS_DAT1_PAR_DISABLE     (0x1ULL << 32)
+#define CE_URE_UPS_HDR1_PAR_DISABLE     (0x1ULL << 33)
+#define CE_URE_UPS_DAT2_PAR_DISABLE     (0x1ULL << 34)
+#define CE_URE_UPS_HDR2_PAR_DISABLE     (0x1ULL << 35)
+#define CE_URE_ATE_PAR_DISABLE          (0x1ULL << 36)
+#define CE_URE_RCI_PAR_DISABLE          (0x1ULL << 37)
+#define CE_URE_RSPQ_PAR_DISABLE         (0x1ULL << 38)
+#define CE_URE_DNS_DAT_PAR_DISABLE      (0x1ULL << 39)
+#define CE_URE_DNS_HDR_PAR_DISABLE      (0x1ULL << 40)
+#define CE_URE_MALFORM_DISABLE          (0x1ULL << 44)
+#define CE_URE_UNSUP_DISABLE            (0x1ULL << 45)
+
+/* ce_ure_page_map register bit masks & shifts */
+#define CE_URE_ATE3240_ENABLE           (0x1ULL << 0)
+#define CE_URE_ATE40_ENABLE             (0x1ULL << 1)
+#define CE_URE_PAGESIZE_SHFT            4
+#define CE_URE_PAGESIZE_MASK            (0x7ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_4K_PAGESIZE              (0x0ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_16K_PAGESIZE             (0x1ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_64K_PAGESIZE             (0x2ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_128K_PAGESIZE            (0x3ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_256K_PAGESIZE            (0x4ULL << CE_URE_PAGESIZE_SHFT)
+
+/* ce_ure_pipe_sel register bit masks & shifts */
+#define PKT_TRAFIC_SHRT                 16
+#define BUS_SRC_ID_SHFT                 8
+#define DEV_SRC_ID_SHFT                 3
+#define FNC_SRC_ID_SHFT                 0
+#define CE_URE_TC_MASK                  (0x07ULL << PKT_TRAFIC_SHRT)
+#define CE_URE_BUS_MASK                 (0xFFULL << BUS_SRC_ID_SHFT)
+#define CE_URE_DEV_MASK                 (0x1FULL << DEV_SRC_ID_SHFT)
+#define CE_URE_FNC_MASK                 (0x07ULL << FNC_SRC_ID_SHFT)
+#define CE_URE_PIPE_BUS(b)              (((u64)(b) << BUS_SRC_ID_SHFT) & \
+                                         CE_URE_BUS_MASK)
+#define CE_URE_PIPE_DEV(d)              (((u64)(d) << DEV_SRC_ID_SHFT) & \
+                                         CE_URE_DEV_MASK)
+#define CE_URE_PIPE_FNC(f)              (((u64)(f) << FNC_SRC_ID_SHFT) & \
+                                         CE_URE_FNC_MASK)
+
+#define CE_URE_SEL1_SHFT                0
+#define CE_URE_SEL2_SHFT                20
+#define CE_URE_SEL3_SHFT                40
+#define CE_URE_SEL1_MASK                (0x7FFFFULL << CE_URE_SEL1_SHFT)
+#define CE_URE_SEL2_MASK                (0x7FFFFULL << CE_URE_SEL2_SHFT)
+#define CE_URE_SEL3_MASK                (0x7FFFFULL << CE_URE_SEL3_SHFT)
+
+
+/* ce_ure_pipe_mask register bit masks & shifts */
+#define CE_URE_MASK1_SHFT               0
+#define CE_URE_MASK2_SHFT               20
+#define CE_URE_MASK3_SHFT               40
+#define CE_URE_MASK1_MASK               (0x7FFFFULL << CE_URE_MASK1_SHFT)
+#define CE_URE_MASK2_MASK               (0x7FFFFULL << CE_URE_MASK2_SHFT)
+#define CE_URE_MASK3_MASK               (0x7FFFFULL << CE_URE_MASK3_SHFT)
+
+
+/* ce_ure_pcie_control1 register bit masks & shifts */
+#define CE_URE_SI                       (0x1ULL << 0)
+#define CE_URE_ELAL_SHFT                4
+#define CE_URE_ELAL_MASK                (0x7ULL << CE_URE_ELAL_SHFT)
+#define CE_URE_ELAL_SET(n)              (((u64)(n) << CE_URE_ELAL_SHFT) & \
+                                         CE_URE_ELAL_MASK)
+#define CE_URE_ELAL1_SHFT               8
+#define CE_URE_ELAL1_MASK               (0x7ULL << CE_URE_ELAL1_SHFT)
+#define CE_URE_ELAL1_SET(n)             (((u64)(n) << CE_URE_ELAL1_SHFT) & \
+                                         CE_URE_ELAL1_MASK)
+#define CE_URE_SCC                      (0x1ULL << 12)
+#define CE_URE_PN1_SHFT                 16
+#define CE_URE_PN1_MASK                 (0xFFULL << CE_URE_PN1_SHFT)
+#define CE_URE_PN2_SHFT                 24
+#define CE_URE_PN2_MASK                 (0xFFULL << CE_URE_PN2_SHFT)
+#define CE_URE_PN1_SET(n)               (((u64)(n) << CE_URE_PN1_SHFT) & \
+                                         CE_URE_PN1_MASK)
+#define CE_URE_PN2_SET(n)               (((u64)(n) << CE_URE_PN2_SHFT) & \
+                                         CE_URE_PN2_MASK)
+
+/* ce_ure_pcie_control2 register bit masks & shifts */
+#define CE_URE_ABP                      (0x1ULL << 0)
+#define CE_URE_PCP                      (0x1ULL << 1)
+#define CE_URE_MSP                      (0x1ULL << 2)
+#define CE_URE_AIP                      (0x1ULL << 3)
+#define CE_URE_PIP                      (0x1ULL << 4)
+#define CE_URE_HPS                      (0x1ULL << 5)
+#define CE_URE_HPC                      (0x1ULL << 6)
+#define CE_URE_SPLV_SHFT                7
+#define CE_URE_SPLV_MASK                (0xFFULL << CE_URE_SPLV_SHFT)
+#define CE_URE_SPLV_SET(n)              (((u64)(n) << CE_URE_SPLV_SHFT) & \
+                                         CE_URE_SPLV_MASK)
+#define CE_URE_SPLS_SHFT                15
+#define CE_URE_SPLS_MASK                (0x3ULL << CE_URE_SPLS_SHFT)
+#define CE_URE_SPLS_SET(n)              (((u64)(n) << CE_URE_SPLS_SHFT) & \
+                                         CE_URE_SPLS_MASK)
+#define CE_URE_PSN1_SHFT                19
+#define CE_URE_PSN1_MASK                (0x1FFFULL << CE_URE_PSN1_SHFT)
+#define CE_URE_PSN2_SHFT                32
+#define CE_URE_PSN2_MASK                (0x1FFFULL << CE_URE_PSN2_SHFT)
+#define CE_URE_PSN1_SET(n)              (((u64)(n) << CE_URE_PSN1_SHFT) & \
+                                         CE_URE_PSN1_MASK)
+#define CE_URE_PSN2_SET(n)              (((u64)(n) << CE_URE_PSN2_SHFT) & \
+                                         CE_URE_PSN2_MASK)
+
+/*
+ * PIO address space ranges for CE
+ */
+
+/* Local CE Registers Space */
+#define CE_PIO_MMR                      0x00000000
+#define CE_PIO_MMR_LEN                  0x04000000
+
+/* PCI Compatible Config Space */
+#define CE_PIO_CONFIG_SPACE             0x04000000
+#define CE_PIO_CONFIG_SPACE_LEN         0x04000000
+
+/* PCI I/O Space Alias */
+#define CE_PIO_IO_SPACE_ALIAS           0x08000000
+#define CE_PIO_IO_SPACE_ALIAS_LEN       0x08000000
+
+/* PCI Enhanced Config Space */
+#define CE_PIO_E_CONFIG_SPACE           0x10000000
+#define CE_PIO_E_CONFIG_SPACE_LEN       0x10000000
+
+/* PCI I/O Space */
+#define CE_PIO_IO_SPACE                 0x100000000
+#define CE_PIO_IO_SPACE_LEN             0x100000000
+
+/* PCI MEM Space */
+#define CE_PIO_MEM_SPACE                0x200000000
+#define CE_PIO_MEM_SPACE_LEN            TIO_HWIN_SIZE
+
+
+/*
+ * CE PCI Enhanced Config Space shifts & masks
+ */
+#define CE_E_CONFIG_BUS_SHFT            20
+#define CE_E_CONFIG_BUS_MASK            (0xFF << CE_E_CONFIG_BUS_SHFT)
+#define CE_E_CONFIG_DEVICE_SHFT         15
+#define CE_E_CONFIG_DEVICE_MASK         (0x1F << CE_E_CONFIG_DEVICE_SHFT)
+#define CE_E_CONFIG_FUNC_SHFT           12
+#define CE_E_CONFIG_FUNC_MASK           (0x7  << CE_E_CONFIG_FUNC_SHFT)
+
+#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/arch/ia64/include/asm/sn/tioce_provider.h b/arch/ia64/include/asm/sn/tioce_provider.h
new file mode 100644
index 000000000000..32c32f30b099
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioce_provider.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_CE_PROVIDER_H
+#define _ASM_IA64_SN_CE_PROVIDER_H
+
+#include <asm/sn/pcibus_provider_defs.h>
+#include <asm/sn/tioce.h>
+
+/*
+ * Common TIOCE structure shared between the prom and kernel
+ *
+ * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
+ * PROM VERSION.
+ */
+struct tioce_common {
+        struct pcibus_bussoft   ce_pcibus;      /* common pciio header */
+
+        u32             ce_rev;
+        u64             ce_kernel_private;
+        u64             ce_prom_private;
+};
+
+struct tioce_kernel {
+        struct tioce_common     *ce_common;
+        spinlock_t              ce_lock;
+        struct list_head        ce_dmamap_list;
+
+        u64             ce_ate40_shadow[TIOCE_NUM_M40_ATES];
+        u64             ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
+        u32             ce_ate3240_pagesize;
+
+        u8                      ce_port1_secondary;
+
+        /* per-port resources */
+        struct {
+                int             dirmap_refcnt;
+                u64     dirmap_shadow;
+        } ce_port[TIOCE_NUM_PORTS];
+};
+
+struct tioce_dmamap {
+        struct list_head        ce_dmamap_list; /* headed by tioce_kernel */
+        u32             refcnt;
+
+        u64             nbytes;         /* # bytes mapped */
+
+        u64             ct_start;       /* coretalk start address */
+        u64             pci_start;      /* bus start address */
+
+        u64             __iomem *ate_hw;/* hw ptr of first ate in map */
+        u64             *ate_shadow;    /* shadow ptr of firat ate */
+        u16             ate_count;      /* # ate's in the map */
+};
+
+extern int tioce_init_provider(void);
+
+#endif  /* __ASM_IA64_SN_CE_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/tiocp.h b/arch/ia64/include/asm/sn/tiocp.h
new file mode 100644
index 000000000000..e8ad0bb5b6c5
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tiocp.h
@@ -0,0 +1,257 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_TIOCP_H
+#define _ASM_IA64_SN_PCI_TIOCP_H
+
+#define TIOCP_HOST_INTR_ADDR            0x003FFFFFFFFFFFFFUL
+#define TIOCP_PCI64_CMDTYPE_MEM         (0x1ull << 60)
+#define TIOCP_PCI64_CMDTYPE_MSI         (0x3ull << 60)
+
+
+/*****************************************************************************
+ *********************** TIOCP MMR structure mapping ***************************
+ *****************************************************************************/
+
+struct tiocp{
+
+    /* 0x000000-0x00FFFF -- Local Registers */
+
+    /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
+    u64         cp_id;                          /* 0x000000 */
+    u64         cp_stat;                        /* 0x000008 */
+    u64         cp_err_upper;                   /* 0x000010 */
+    u64         cp_err_lower;                   /* 0x000018 */
+    #define cp_err cp_err_lower
+    u64         cp_control;                     /* 0x000020 */
+    u64         cp_req_timeout;                 /* 0x000028 */
+    u64         cp_intr_upper;                  /* 0x000030 */
+    u64         cp_intr_lower;                  /* 0x000038 */
+    #define cp_intr cp_intr_lower
+    u64         cp_err_cmdword;                 /* 0x000040 */
+    u64         _pad_000048;                    /* 0x000048 */
+    u64         cp_tflush;                      /* 0x000050 */
+
+    /* 0x000058-0x00007F -- Bridge-specific Configuration */
+    u64         cp_aux_err;                     /* 0x000058 */
+    u64         cp_resp_upper;                  /* 0x000060 */
+    u64         cp_resp_lower;                  /* 0x000068 */
+    #define cp_resp cp_resp_lower
+    u64         cp_tst_pin_ctrl;                /* 0x000070 */
+    u64         cp_addr_lkerr;                  /* 0x000078 */
+
+    /* 0x000080-0x00008F -- PMU & MAP */
+    u64         cp_dir_map;                     /* 0x000080 */
+    u64         _pad_000088;                    /* 0x000088 */
+
+    /* 0x000090-0x00009F -- SSRAM */
+    u64         cp_map_fault;                   /* 0x000090 */
+    u64         _pad_000098;                    /* 0x000098 */
+
+    /* 0x0000A0-0x0000AF -- Arbitration */
+    u64         cp_arb;                         /* 0x0000A0 */
+    u64         _pad_0000A8;                    /* 0x0000A8 */
+
+    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+    u64         cp_ate_parity_err;              /* 0x0000B0 */
+    u64         _pad_0000B8;                    /* 0x0000B8 */
+
+    /* 0x0000C0-0x0000FF -- PCI/GIO */
+    u64         cp_bus_timeout;                 /* 0x0000C0 */
+    u64         cp_pci_cfg;                     /* 0x0000C8 */
+    u64         cp_pci_err_upper;               /* 0x0000D0 */
+    u64         cp_pci_err_lower;               /* 0x0000D8 */
+    #define cp_pci_err cp_pci_err_lower
+    u64         _pad_0000E0[4];                 /* 0x0000{E0..F8} */
+
+    /* 0x000100-0x0001FF -- Interrupt */
+    u64         cp_int_status;                  /* 0x000100 */
+    u64         cp_int_enable;                  /* 0x000108 */
+    u64         cp_int_rst_stat;                /* 0x000110 */
+    u64         cp_int_mode;                    /* 0x000118 */
+    u64         cp_int_device;                  /* 0x000120 */
+    u64         cp_int_host_err;                /* 0x000128 */
+    u64         cp_int_addr[8];                 /* 0x0001{30,,,68} */
+    u64         cp_err_int_view;                /* 0x000170 */
+    u64         cp_mult_int;                    /* 0x000178 */
+    u64         cp_force_always[8];             /* 0x0001{80,,,B8} */
+    u64         cp_force_pin[8];                /* 0x0001{C0,,,F8} */
+
+    /* 0x000200-0x000298 -- Device */
+    u64         cp_device[4];                   /* 0x0002{00,,,18} */
+    u64         _pad_000220[4];                 /* 0x0002{20,,,38} */
+    u64         cp_wr_req_buf[4];               /* 0x0002{40,,,58} */
+    u64         _pad_000260[4];                 /* 0x0002{60,,,78} */
+    u64         cp_rrb_map[2];                  /* 0x0002{80,,,88} */
+    #define cp_even_resp cp_rrb_map[0]                  /* 0x000280 */
+    #define cp_odd_resp  cp_rrb_map[1]                  /* 0x000288 */
+    u64         cp_resp_status;                 /* 0x000290 */
+    u64         cp_resp_clear;                  /* 0x000298 */
+
+    u64         _pad_0002A0[12];                /* 0x0002{A0..F8} */
+
+    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
+    struct {
+        u64     upper;                          /* 0x0003{00,,,F0} */
+        u64     lower;                          /* 0x0003{08,,,F8} */
+    } cp_buf_addr_match[16];
+
+    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+    struct {
+        u64     flush_w_touch;                  /* 0x000{400,,,5C0} */
+        u64     flush_wo_touch;                 /* 0x000{408,,,5C8} */
+        u64     inflight;                       /* 0x000{410,,,5D0} */
+        u64     prefetch;                       /* 0x000{418,,,5D8} */
+        u64     total_pci_retry;                /* 0x000{420,,,5E0} */
+        u64     max_pci_retry;                  /* 0x000{428,,,5E8} */
+        u64     max_latency;                    /* 0x000{430,,,5F0} */
+        u64     clear_all;                      /* 0x000{438,,,5F8} */
+    } cp_buf_count[8];
+
+
+    /* 0x000600-0x0009FF -- PCI/X registers */
+    u64         cp_pcix_bus_err_addr;           /* 0x000600 */
+    u64         cp_pcix_bus_err_attr;           /* 0x000608 */
+    u64         cp_pcix_bus_err_data;           /* 0x000610 */
+    u64         cp_pcix_pio_split_addr;         /* 0x000618 */
+    u64         cp_pcix_pio_split_attr;         /* 0x000620 */
+    u64         cp_pcix_dma_req_err_attr;       /* 0x000628 */
+    u64         cp_pcix_dma_req_err_addr;       /* 0x000630 */
+    u64         cp_pcix_timeout;                /* 0x000638 */
+
+    u64         _pad_000640[24];                /* 0x000{640,,,6F8} */
+
+    /* 0x000700-0x000737 -- Debug Registers */
+    u64         cp_ct_debug_ctl;                /* 0x000700 */
+    u64         cp_br_debug_ctl;                /* 0x000708 */
+    u64         cp_mux3_debug_ctl;              /* 0x000710 */
+    u64         cp_mux4_debug_ctl;              /* 0x000718 */
+    u64         cp_mux5_debug_ctl;              /* 0x000720 */
+    u64         cp_mux6_debug_ctl;              /* 0x000728 */
+    u64         cp_mux7_debug_ctl;              /* 0x000730 */
+
+    u64         _pad_000738[89];                /* 0x000{738,,,9F8} */
+
+    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+    struct {
+        u64     cp_buf_addr;                    /* 0x000{A00,,,AF0} */
+        u64     cp_buf_attr;                    /* 0X000{A08,,,AF8} */
+    } cp_pcix_read_buf_64[16];
+
+    struct {
+        u64     cp_buf_addr;                    /* 0x000{B00,,,BE0} */
+        u64     cp_buf_attr;                    /* 0x000{B08,,,BE8} */
+        u64     cp_buf_valid;                   /* 0x000{B10,,,BF0} */
+        u64     __pad1;                         /* 0x000{B18,,,BF8} */
+    } cp_pcix_write_buf_64[8];
+
+    /* End of Local Registers -- Start of Address Map space */
+
+    char        _pad_000c00[0x010000 - 0x000c00];
+
+    /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
+    u64         cp_int_ate_ram[1024];           /* 0x010000-0x011FF8 */
+
+    char        _pad_012000[0x14000 - 0x012000];
+
+    /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
+    u64         cp_int_ate_ram_mp[1024];        /* 0x014000-0x015FF8 */
+
+    char        _pad_016000[0x18000 - 0x016000];
+
+    /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
+    u64         cp_wr_req_lower[256];           /* 0x18000 - 0x187F8 */
+    u64         cp_wr_req_upper[256];           /* 0x18800 - 0x18FF8 */
+    u64         cp_wr_req_parity[256];          /* 0x19000 - 0x197F8 */
+
+    char        _pad_019800[0x1C000 - 0x019800];
+
+    /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
+    u64         cp_rd_resp_lower[512];          /* 0x1C000 - 0x1CFF8 */
+    u64         cp_rd_resp_upper[512];          /* 0x1D000 - 0x1DFF8 */
+    u64         cp_rd_resp_parity[512];         /* 0x1E000 - 0x1EFF8 */
+
+    char        _pad_01F000[0x20000 - 0x01F000];
+
+    /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used)  */
+    char        _pad_020000[0x021000 - 0x20000];
+
+    /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
+    union {
+        u8      c[0x1000 / 1];                  /* 0x02{0000,,,7FFF} */
+        u16     s[0x1000 / 2];                  /* 0x02{0000,,,7FFF} */
+        u32     l[0x1000 / 4];                  /* 0x02{0000,,,7FFF} */
+        u64     d[0x1000 / 8];                  /* 0x02{0000,,,7FFF} */
+        union {
+            u8  c[0x100 / 1];
+            u16 s[0x100 / 2];
+            u32 l[0x100 / 4];
+            u64 d[0x100 / 8];
+        } f[8];
+    } cp_type0_cfg_dev[7];                              /* 0x02{1000,,,7FFF} */
+
+    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+    union {
+        u8      c[0x1000 / 1];                  /* 0x028000-0x029000 */
+        u16     s[0x1000 / 2];                  /* 0x028000-0x029000 */
+        u32     l[0x1000 / 4];                  /* 0x028000-0x029000 */
+        u64     d[0x1000 / 8];                  /* 0x028000-0x029000 */
+        union {
+            u8  c[0x100 / 1];
+            u16 s[0x100 / 2];
+            u32 l[0x100 / 4];
+            u64 d[0x100 / 8];
+        } f[8];
+    } cp_type1_cfg;                                     /* 0x028000-0x029000 */
+
+    char                _pad_029000[0x030000-0x029000];
+
+    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+    union {
+        u8      c[8 / 1];
+        u16     s[8 / 2];
+        u32     l[8 / 4];
+        u64     d[8 / 8];
+    } cp_pci_iack;                                      /* 0x030000-0x030007 */
+
+    char                _pad_030007[0x040000-0x030008];
+
+    /* 0x040000-0x040007 -- PCIX Special Cycle */
+    union {
+        u8      c[8 / 1];
+        u16     s[8 / 2];
+        u32     l[8 / 4];
+        u64     d[8 / 8];
+    } cp_pcix_cycle;                                    /* 0x040000-0x040007 */
+
+    char                _pad_040007[0x200000-0x040008];
+
+    /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
+    union {
+        u8      c[0x100000 / 1];
+        u16     s[0x100000 / 2];
+        u32     l[0x100000 / 4];
+        u64     d[0x100000 / 8];
+    } cp_devio_raw[6];                                  /* 0x200000-0x7FFFFF */
+
+    #define cp_devio(n)  cp_devio_raw[((n)<2)?(n*2):(n+2)]
+
+    char                _pad_800000[0xA00000-0x800000];
+
+    /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush  */
+    union {
+        u8      c[0x100000 / 1];
+        u16     s[0x100000 / 2];
+        u32     l[0x100000 / 4];
+        u64     d[0x100000 / 8];
+    } cp_devio_raw_flush[6];                            /* 0xA00000-0xBFFFFF */
+
+    #define cp_devio_flush(n)  cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
+
+};
+
+#endif  /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/arch/ia64/include/asm/sn/tiocx.h b/arch/ia64/include/asm/sn/tiocx.h
new file mode 100644
index 000000000000..d29728492f36
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tiocx.h
@@ -0,0 +1,72 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_TIO_TIOCX_H
+#define _ASM_IA64_SN_TIO_TIOCX_H
+
+#ifdef __KERNEL__
+
+struct cx_id_s {
+        unsigned int part_num;
+        unsigned int mfg_num;
+        int nasid;
+};
+
+struct cx_dev {
+        struct cx_id_s cx_id;
+        int bt;                         /* board/blade type */
+        void *soft;                     /* driver specific */
+        struct hubdev_info *hubdev;
+        struct device dev;
+        struct cx_drv *driver;
+};
+
+struct cx_device_id {
+        unsigned int part_num;
+        unsigned int mfg_num;
+};
+
+struct cx_drv {
+        char *name;
+        const struct cx_device_id *id_table;
+        struct device_driver driver;
+        int (*probe) (struct cx_dev * dev, const struct cx_device_id * id);
+        int (*remove) (struct cx_dev * dev);
+};
+
+/* create DMA address by stripping AS bits */
+#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
+
+#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) |  \
+                                  ((((u64)(a)) & 0xffffc000000000UL) <<2))
+
+#define TIO_CE_ASIC_PARTNUM 0xce00
+#define TIOCX_CORELET 3
+
+/* These are taken from tio_mmr_as.h */
+#define TIO_ICE_FRZ_CFG               TIO_MMR_ADDR_MOD(0x00000000b0008100UL)
+#define TIO_ICE_PMI_TX_CFG            TIO_MMR_ADDR_MOD(0x00000000b000b100UL)
+#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL)
+#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL
+
+#define to_cx_dev(n) container_of(n, struct cx_dev, dev)
+#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver)
+
+extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
+extern void tiocx_irq_free(struct sn_irq_info *);
+extern int cx_device_unregister(struct cx_dev *);
+extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
+extern int cx_driver_unregister(struct cx_drv *);
+extern int cx_driver_register(struct cx_drv *);
+extern u64 tiocx_dma_addr(u64 addr);
+extern u64 tiocx_swin_base(int nasid);
+extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
+extern u64 tiocx_mmr_load(int nasid, u64 offset);
+
+#endif                          //  __KERNEL__
+#endif                          // _ASM_IA64_SN_TIO_TIOCX__
diff --git a/arch/ia64/include/asm/sn/types.h b/arch/ia64/include/asm/sn/types.h
new file mode 100644
index 000000000000..8e04ee211e59
--- /dev/null
+++ b/arch/ia64/include/asm/sn/types.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc.  All Rights Reserved.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_TYPES_H
+#define _ASM_IA64_SN_TYPES_H
+
+#include <linux/types.h>
+
+typedef unsigned long   cpuid_t;
+typedef signed short    nasid_t;        /* node id in numa-as-id space */
+typedef signed char     partid_t;       /* partition ID type */
+typedef unsigned int    moduleid_t;     /* user-visible module number type */
+typedef unsigned int    cmoduleid_t;    /* kernel compact module id type */
+typedef unsigned char   slotid_t;       /* slot (blade) within module */
+typedef unsigned char   slabid_t;       /* slab (asic) within slot */
+typedef u64 nic_t;
+typedef unsigned long iopaddr_t;
+typedef unsigned long paddr_t;
+typedef short cnodeid_t;
+
+#endif /* _ASM_IA64_SN_TYPES_H */
diff --git a/arch/ia64/include/asm/socket.h b/arch/ia64/include/asm/socket.h
new file mode 100644
index 000000000000..d5ef0aa3e312
--- /dev/null
+++ b/arch/ia64/include/asm/socket.h
@@ -0,0 +1,66 @@
+#ifndef _ASM_IA64_SOCKET_H
+#define _ASM_IA64_SOCKET_H
+
+/*
+ * Socket related defines.
+ *
+ * Based on <asm-i386/socket.h>.
+ *
+ * Modified 1998-2000
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE         25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC             31
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#endif /* _ASM_IA64_SOCKET_H */
diff --git a/arch/ia64/include/asm/sockios.h b/arch/ia64/include/asm/sockios.h
new file mode 100644
index 000000000000..15c92468ad38
--- /dev/null
+++ b/arch/ia64/include/asm/sockios.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_IA64_SOCKIOS_H
+#define _ASM_IA64_SOCKIOS_H
+
+/*
+ * Socket-level I/O control calls.
+ *
+ * Based on <asm-i386/sockios.h>.
+ *
+ * Modified 1998, 1999
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif /* _ASM_IA64_SOCKIOS_H */
diff --git a/arch/ia64/include/asm/sparsemem.h b/arch/ia64/include/asm/sparsemem.h
new file mode 100644
index 000000000000..67a7c40ec27f
--- /dev/null
+++ b/arch/ia64/include/asm/sparsemem.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_IA64_SPARSEMEM_H
+#define _ASM_IA64_SPARSEMEM_H
+
+#ifdef CONFIG_SPARSEMEM
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+
+#define SECTION_SIZE_BITS       (30)
+#define MAX_PHYSMEM_BITS        (50)
+#ifdef CONFIG_FORCE_MAX_ZONEORDER
+#if ((CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS)
+#undef SECTION_SIZE_BITS
+#define SECTION_SIZE_BITS (CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT)
+#endif
+#endif
+
+#endif /* CONFIG_SPARSEMEM */
+#endif /* _ASM_IA64_SPARSEMEM_H */
diff --git a/arch/ia64/include/asm/spinlock.h b/arch/ia64/include/asm/spinlock.h
new file mode 100644
index 000000000000..0229fb95fb38
--- /dev/null
+++ b/arch/ia64/include/asm/spinlock.h
@@ -0,0 +1,220 @@
+#ifndef _ASM_IA64_SPINLOCK_H
+#define _ASM_IA64_SPINLOCK_H
+
+/*
+ * Copyright (C) 1998-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ *
+ * This file is used for SMP configurations only.
+ */
+
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+
+#include <asm/atomic.h>
+#include <asm/intrinsics.h>
+#include <asm/system.h>
+
+#define __raw_spin_lock_init(x)                 ((x)->lock = 0)
+
+#ifdef ASM_SUPPORTED
+/*
+ * Try to get the lock.  If we fail to get the lock, make a non-standard call to
+ * ia64_spinlock_contention().  We do not use a normal call because that would force all
+ * callers of __raw_spin_lock() to be non-leaf routines.  Instead, ia64_spinlock_contention() is
+ * carefully coded to touch only those registers that __raw_spin_lock() marks "clobbered".
+ */
+
+#define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
+
+static inline void
+__raw_spin_lock_flags (raw_spinlock_t *lock, unsigned long flags)
+{
+        register volatile unsigned int *ptr asm ("r31") = &lock->lock;
+
+#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
+# ifdef CONFIG_ITANIUM
+        /* don't use brl on Itanium... */
+        asm volatile ("{\n\t"
+                      "  mov ar.ccv = r0\n\t"
+                      "  mov r28 = ip\n\t"
+                      "  mov r30 = 1;;\n\t"
+                      "}\n\t"
+                      "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
+                      "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
+                      "cmp4.ne p14, p0 = r30, r0\n\t"
+                      "mov b6 = r29;;\n\t"
+                      "mov r27=%2\n\t"
+                      "(p14) br.cond.spnt.many b6"
+                      : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
+# else
+        asm volatile ("{\n\t"
+                      "  mov ar.ccv = r0\n\t"
+                      "  mov r28 = ip\n\t"
+                      "  mov r30 = 1;;\n\t"
+                      "}\n\t"
+                      "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
+                      "cmp4.ne p14, p0 = r30, r0\n\t"
+                      "mov r27=%2\n\t"
+                      "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
+                      : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
+# endif /* CONFIG_MCKINLEY */
+#else
+# ifdef CONFIG_ITANIUM
+        /* don't use brl on Itanium... */
+        /* mis-declare, so we get the entry-point, not it's function descriptor: */
+        asm volatile ("mov r30 = 1\n\t"
+                      "mov r27=%2\n\t"
+                      "mov ar.ccv = r0;;\n\t"
+                      "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
+                      "movl r29 = ia64_spinlock_contention;;\n\t"
+                      "cmp4.ne p14, p0 = r30, r0\n\t"
+                      "mov b6 = r29;;\n\t"
+                      "(p14) br.call.spnt.many b6 = b6"
+                      : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
+# else
+        asm volatile ("mov r30 = 1\n\t"
+                      "mov r27=%2\n\t"
+                      "mov ar.ccv = r0;;\n\t"
+                      "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
+                      "cmp4.ne p14, p0 = r30, r0\n\t"
+                      "(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
+                      : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
+# endif /* CONFIG_MCKINLEY */
+#endif
+}
+
+#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
+
+/* Unlock by doing an ordered store and releasing the cacheline with nta */
+static inline void __raw_spin_unlock(raw_spinlock_t *x) {
+        barrier();
+        asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
+}
+
+#else /* !ASM_SUPPORTED */
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+# define __raw_spin_lock(x)                                                             \
+do {                                                                                    \
+        __u32 *ia64_spinlock_ptr = (__u32 *) (x);                                       \
+        __u64 ia64_spinlock_val;                                                        \
+        ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);                 \
+        if (unlikely(ia64_spinlock_val)) {                                              \
+                do {                                                                    \
+                        while (*ia64_spinlock_ptr)                                      \
+                                ia64_barrier();                                         \
+                        ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
+                } while (ia64_spinlock_val);                                            \
+        }                                                                               \
+} while (0)
+#define __raw_spin_unlock(x)    do { barrier(); ((raw_spinlock_t *) x)->lock = 0; } while (0)
+#endif /* !ASM_SUPPORTED */
+
+#define __raw_spin_is_locked(x)         ((x)->lock != 0)
+#define __raw_spin_trylock(x)           (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
+#define __raw_spin_unlock_wait(lock) \
+        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+
+#define __raw_read_can_lock(rw)         (*(volatile int *)(rw) >= 0)
+#define __raw_write_can_lock(rw)        (*(volatile int *)(rw) == 0)
+
+#define __raw_read_lock(rw)                                                             \
+do {                                                                                    \
+        raw_rwlock_t *__read_lock_ptr = (rw);                                           \
+                                                                                        \
+        while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) {          \
+                ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);                        \
+                while (*(volatile int *)__read_lock_ptr < 0)                            \
+                        cpu_relax();                                                    \
+        }                                                                               \
+} while (0)
+
+#define __raw_read_unlock(rw)                                   \
+do {                                                            \
+        raw_rwlock_t *__read_lock_ptr = (rw);                   \
+        ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);        \
+} while (0)
+
+#ifdef ASM_SUPPORTED
+#define __raw_write_lock(rw)                                                    \
+do {                                                                            \
+        __asm__ __volatile__ (                                                  \
+                "mov ar.ccv = r0\n"                                             \
+                "dep r29 = -1, r0, 31, 1;;\n"                                   \
+                "1:\n"                                                          \
+                "ld4 r2 = [%0];;\n"                                             \
+                "cmp4.eq p0,p7 = r0,r2\n"                                       \
+                "(p7) br.cond.spnt.few 1b \n"                                   \
+                "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"                       \
+                "cmp4.eq p0,p7 = r0, r2\n"                                      \
+                "(p7) br.cond.spnt.few 1b;;\n"                                  \
+                :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory");            \
+} while(0)
+
+#define __raw_write_trylock(rw)                                                 \
+({                                                                              \
+        register long result;                                                   \
+                                                                                \
+        __asm__ __volatile__ (                                                  \
+                "mov ar.ccv = r0\n"                                             \
+                "dep r29 = -1, r0, 31, 1;;\n"                                   \
+                "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n"                         \
+                : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory");          \
+        (result == 0);                                                          \
+})
+
+static inline void __raw_write_unlock(raw_rwlock_t *x)
+{
+        u8 *y = (u8 *)x;
+        barrier();
+        asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
+}
+
+#else /* !ASM_SUPPORTED */
+
+#define __raw_write_lock(l)                                                             \
+({                                                                                      \
+        __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1);                       \
+        __u32 *ia64_write_lock_ptr = (__u32 *) (l);                                     \
+        do {                                                                            \
+                while (*ia64_write_lock_ptr)                                            \
+                        ia64_barrier();                                                 \
+                ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0);     \
+        } while (ia64_val);                                                             \
+})
+
+#define __raw_write_trylock(rw)                                         \
+({                                                                      \
+        __u64 ia64_val;                                                 \
+        __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1);                  \
+        ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0);   \
+        (ia64_val == 0);                                                \
+})
+
+static inline void __raw_write_unlock(raw_rwlock_t *x)
+{
+        barrier();
+        x->write_lock = 0;
+}
+
+#endif /* !ASM_SUPPORTED */
+
+static inline int __raw_read_trylock(raw_rwlock_t *x)
+{
+        union {
+                raw_rwlock_t lock;
+                __u32 word;
+        } old, new;
+        old.lock = new.lock = *x;
+        old.lock.write_lock = new.lock.write_lock = 0;
+        ++new.lock.read_counter;
+        return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
+}
+
+#define _raw_spin_relax(lock)   cpu_relax()
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#endif /*  _ASM_IA64_SPINLOCK_H */
diff --git a/arch/ia64/include/asm/spinlock_types.h b/arch/ia64/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..474e46f1ab4a
--- /dev/null
+++ b/arch/ia64/include/asm/spinlock_types.h
@@ -0,0 +1,21 @@
+#ifndef _ASM_IA64_SPINLOCK_TYPES_H
+#define _ASM_IA64_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+
+typedef struct {
+        volatile unsigned int read_counter      : 31;
+        volatile unsigned int write_lock        :  1;
+} raw_rwlock_t;
+
+#define __RAW_RW_LOCK_UNLOCKED          { 0, 0 }
+
+#endif
diff --git a/arch/ia64/include/asm/stat.h b/arch/ia64/include/asm/stat.h
new file mode 100644
index 000000000000..367bb90cdffa
--- /dev/null
+++ b/arch/ia64/include/asm/stat.h
@@ -0,0 +1,51 @@
+#ifndef _ASM_IA64_STAT_H
+#define _ASM_IA64_STAT_H
+
+/*
+ * Modified 1998, 1999
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+struct stat {
+        unsigned long   st_dev;
+        unsigned long   st_ino;
+        unsigned long   st_nlink;
+        unsigned int    st_mode;
+        unsigned int    st_uid;
+        unsigned int    st_gid;
+        unsigned int    __pad0;
+        unsigned long   st_rdev;
+        unsigned long   st_size;
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+        unsigned long   st_blksize;
+        long            st_blocks;
+        unsigned long   __unused[3];
+};
+
+#define STAT_HAVE_NSEC 1
+
+struct ia64_oldstat {
+        unsigned int    st_dev;
+        unsigned int    st_ino;
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+        unsigned int    st_uid;
+        unsigned int    st_gid;
+        unsigned int    st_rdev;
+        unsigned int    __pad1;
+        unsigned long   st_size;
+        unsigned long   st_atime;
+        unsigned long   st_mtime;
+        unsigned long   st_ctime;
+        unsigned int    st_blksize;
+        int             st_blocks;
+        unsigned int    __unused1;
+        unsigned int    __unused2;
+};
+
+#endif /* _ASM_IA64_STAT_H */
diff --git a/arch/ia64/include/asm/statfs.h b/arch/ia64/include/asm/statfs.h
new file mode 100644
index 000000000000..811097974f31
--- /dev/null
+++ b/arch/ia64/include/asm/statfs.h
@@ -0,0 +1,62 @@
+#ifndef _ASM_IA64_STATFS_H
+#define _ASM_IA64_STATFS_H
+
+/*
+ * Based on <asm-i386/statfs.h>.
+ *
+ * Modified 1998, 1999, 2003
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#ifndef __KERNEL_STRICT_NAMES
+# include <linux/types.h>
+typedef __kernel_fsid_t fsid_t;
+#endif
+
+/*
+ * This is ugly --- we're already 64-bit, so just duplicate the definitions
+ */
+struct statfs {
+        long f_type;
+        long f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        long f_namelen;
+        long f_frsize;
+        long f_spare[5];
+};
+
+
+struct statfs64 {
+        long f_type;
+        long f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        long f_namelen;
+        long f_frsize;
+        long f_spare[5];
+};
+
+struct compat_statfs64 {
+        __u32 f_type;
+        __u32 f_bsize;
+        __u64 f_blocks;
+        __u64 f_bfree;
+        __u64 f_bavail;
+        __u64 f_files;
+        __u64 f_ffree;
+        __kernel_fsid_t f_fsid;
+        __u32 f_namelen;
+        __u32 f_frsize;
+        __u32 f_spare[5];
+} __attribute__((packed));
+
+#endif /* _ASM_IA64_STATFS_H */
diff --git a/arch/ia64/include/asm/string.h b/arch/ia64/include/asm/string.h
new file mode 100644
index 000000000000..85fd65c52a8c
--- /dev/null
+++ b/arch/ia64/include/asm/string.h
@@ -0,0 +1,21 @@
+#ifndef _ASM_IA64_STRING_H
+#define _ASM_IA64_STRING_H
+
+/*
+ * Here is where we want to put optimized versions of the string
+ * routines.
+ *
+ * Copyright (C) 1998-2000, 2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+
+#define __HAVE_ARCH_STRLEN      1 /* see arch/ia64/lib/strlen.S */
+#define __HAVE_ARCH_MEMSET      1 /* see arch/ia64/lib/memset.S */
+#define __HAVE_ARCH_MEMCPY      1 /* see arch/ia64/lib/memcpy.S */
+
+extern __kernel_size_t strlen (const char *);
+extern void *memcpy (void *, const void *, __kernel_size_t);
+extern void *memset (void *, int, __kernel_size_t);
+
+#endif /* _ASM_IA64_STRING_H */
diff --git a/arch/ia64/include/asm/suspend.h b/arch/ia64/include/asm/suspend.h
new file mode 100644
index 000000000000..b05bbb6074e2
--- /dev/null
+++ b/arch/ia64/include/asm/suspend.h
@@ -0,0 +1 @@
+/* dummy (must be non-empty to prevent prejudicial removal...) */
diff --git a/arch/ia64/include/asm/system.h b/arch/ia64/include/asm/system.h
new file mode 100644
index 000000000000..927a381c20ca
--- /dev/null
+++ b/arch/ia64/include/asm/system.h
@@ -0,0 +1,292 @@
+#ifndef _ASM_IA64_SYSTEM_H
+#define _ASM_IA64_SYSTEM_H
+
+/*
+ * System defines. Note that this is included both from .c and .S
+ * files, so it does only defines, not any C code.  This is based
+ * on information published in the Processor Abstraction Layer
+ * and the System Abstraction Layer manual.
+ *
+ * Copyright (C) 1998-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
+ * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
+ */
+
+#include <asm/kregs.h>
+#include <asm/page.h>
+#include <asm/pal.h>
+#include <asm/percpu.h>
+
+#define GATE_ADDR               RGN_BASE(RGN_GATE)
+
+/*
+ * 0xa000000000000000+2*PERCPU_PAGE_SIZE
+ * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
+ */
+#define KERNEL_START             (GATE_ADDR+__IA64_UL_CONST(0x100000000))
+#define PERCPU_ADDR             (-PERCPU_PAGE_SIZE)
+#define LOAD_OFFSET             (KERNEL_START - KERNEL_TR_PAGE_SIZE)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
+
+struct pci_vector_struct {
+        __u16 segment;  /* PCI Segment number */
+        __u16 bus;      /* PCI Bus number */
+        __u32 pci_id;   /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
+        __u8 pin;       /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
+        __u32 irq;      /* IRQ assigned */
+};
+
+extern struct ia64_boot_param {
+        __u64 command_line;             /* physical address of command line arguments */
+        __u64 efi_systab;               /* physical address of EFI system table */
+        __u64 efi_memmap;               /* physical address of EFI memory map */
+        __u64 efi_memmap_size;          /* size of EFI memory map */
+        __u64 efi_memdesc_size;         /* size of an EFI memory map descriptor */
+        __u32 efi_memdesc_version;      /* memory descriptor version */
+        struct {
+                __u16 num_cols; /* number of columns on console output device */
+                __u16 num_rows; /* number of rows on console output device */
+                __u16 orig_x;   /* cursor's x position */
+                __u16 orig_y;   /* cursor's y position */
+        } console_info;
+        __u64 fpswa;            /* physical address of the fpswa interface */
+        __u64 initrd_start;
+        __u64 initrd_size;
+} *ia64_boot_param;
+
+/*
+ * Macros to force memory ordering.  In these descriptions, "previous"
+ * and "subsequent" refer to program order; "visible" means that all
+ * architecturally visible effects of a memory access have occurred
+ * (at a minimum, this means the memory has been read or written).
+ *
+ *   wmb():     Guarantees that all preceding stores to memory-
+ *              like regions are visible before any subsequent
+ *              stores and that all following stores will be
+ *              visible only after all previous stores.
+ *   rmb():     Like wmb(), but for reads.
+ *   mb():      wmb()/rmb() combo, i.e., all previous memory
+ *              accesses are visible before all subsequent
+ *              accesses and vice versa.  This is also known as
+ *              a "fence."
+ *
+ * Note: "mb()" and its variants cannot be used as a fence to order
+ * accesses to memory mapped I/O registers.  For that, mf.a needs to
+ * be used.  However, we don't want to always use mf.a because (a)
+ * it's (presumably) much slower than mf and (b) mf.a is supported for
+ * sequential memory pages only.
+ */
+#define mb()    ia64_mf()
+#define rmb()   mb()
+#define wmb()   mb()
+#define read_barrier_depends()  do { } while(0)
+
+#ifdef CONFIG_SMP
+# define smp_mb()       mb()
+# define smp_rmb()      rmb()
+# define smp_wmb()      wmb()
+# define smp_read_barrier_depends()     read_barrier_depends()
+#else
+# define smp_mb()       barrier()
+# define smp_rmb()      barrier()
+# define smp_wmb()      barrier()
+# define smp_read_barrier_depends()     do { } while(0)
+#endif
+
+/*
+ * XXX check on this ---I suspect what Linus really wants here is
+ * acquire vs release semantics but we can't discuss this stuff with
+ * Linus just yet.  Grrr...
+ */
+#define set_mb(var, value)      do { (var) = (value); mb(); } while (0)
+
+#define safe_halt()         ia64_pal_halt_light()    /* PAL_HALT_LIGHT */
+
+/*
+ * The group barrier in front of the rsm & ssm are necessary to ensure
+ * that none of the previous instructions in the same group are
+ * affected by the rsm/ssm.
+ */
+/* For spinlocks etc */
+
+/*
+ * - clearing psr.i is implicitly serialized (visible by next insn)
+ * - setting psr.i requires data serialization
+ * - we need a stop-bit before reading PSR because we sometimes
+ *   write a floating-point register right before reading the PSR
+ *   and that writes to PSR.mfl
+ */
+#ifdef CONFIG_PARAVIRT
+#define __local_save_flags()    ia64_get_psr_i()
+#else
+#define __local_save_flags()    ia64_getreg(_IA64_REG_PSR)
+#endif
+
+#define __local_irq_save(x)                     \
+do {                                            \
+        ia64_stop();                            \
+        (x) = __local_save_flags();             \
+        ia64_stop();                            \
+        ia64_rsm(IA64_PSR_I);                   \
+} while (0)
+
+#define __local_irq_disable()                   \
+do {                                            \
+        ia64_stop();                            \
+        ia64_rsm(IA64_PSR_I);                   \
+} while (0)
+
+#define __local_irq_restore(x)  ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
+
+#ifdef CONFIG_IA64_DEBUG_IRQ
+
+  extern unsigned long last_cli_ip;
+
+# define __save_ip()            last_cli_ip = ia64_getreg(_IA64_REG_IP)
+
+# define local_irq_save(x)                                      \
+do {                                                            \
+        unsigned long __psr;                                    \
+                                                                \
+        __local_irq_save(__psr);                                \
+        if (__psr & IA64_PSR_I)                                 \
+                __save_ip();                                    \
+        (x) = __psr;                                            \
+} while (0)
+
+# define local_irq_disable()    do { unsigned long __x; local_irq_save(__x); } while (0)
+
+# define local_irq_restore(x)                                   \
+do {                                                            \
+        unsigned long __old_psr, __psr = (x);                   \
+                                                                \
+        local_save_flags(__old_psr);                            \
+        __local_irq_restore(__psr);                             \
+        if ((__old_psr & IA64_PSR_I) && !(__psr & IA64_PSR_I))  \
+                __save_ip();                                    \
+} while (0)
+
+#else /* !CONFIG_IA64_DEBUG_IRQ */
+# define local_irq_save(x)      __local_irq_save(x)
+# define local_irq_disable()    __local_irq_disable()
+# define local_irq_restore(x)   __local_irq_restore(x)
+#endif /* !CONFIG_IA64_DEBUG_IRQ */
+
+#define local_irq_enable()      ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
+#define local_save_flags(flags) ({ ia64_stop(); (flags) = __local_save_flags(); })
+
+#define irqs_disabled()                         \
+({                                              \
+        unsigned long __ia64_id_flags;          \
+        local_save_flags(__ia64_id_flags);      \
+        (__ia64_id_flags & IA64_PSR_I) == 0;    \
+})
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_IA32_SUPPORT
+# define IS_IA32_PROCESS(regs)  (ia64_psr(regs)->is != 0)
+#else
+# define IS_IA32_PROCESS(regs)          0
+struct task_struct;
+static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
+static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
+#endif
+
+/*
+ * Context switch from one thread to another.  If the two threads have
+ * different address spaces, schedule() has already taken care of
+ * switching to the new address space by calling switch_mm().
+ *
+ * Disabling access to the fph partition and the debug-register
+ * context switch MUST be done before calling ia64_switch_to() since a
+ * newly created thread returns directly to
+ * ia64_ret_from_syscall_clear_r8.
+ */
+extern struct task_struct *ia64_switch_to (void *next_task);
+
+struct task_struct;
+
+extern void ia64_save_extra (struct task_struct *task);
+extern void ia64_load_extra (struct task_struct *task);
+
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct *next);
+# define IA64_ACCOUNT_ON_SWITCH(p,n) ia64_account_on_switch(p,n)
+#else
+# define IA64_ACCOUNT_ON_SWITCH(p,n)
+#endif
+
+#ifdef CONFIG_PERFMON
+  DECLARE_PER_CPU(unsigned long, pfm_syst_info);
+# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
+#else
+# define PERFMON_IS_SYSWIDE() (0)
+#endif
+
+#define IA64_HAS_EXTRA_STATE(t)                                                 \
+        ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID)       \
+         || IS_IA32_PROCESS(task_pt_regs(t)) || PERFMON_IS_SYSWIDE())
+
+#define __switch_to(prev,next,last) do {                                                         \
+        IA64_ACCOUNT_ON_SWITCH(prev, next);                                                      \
+        if (IA64_HAS_EXTRA_STATE(prev))                                                          \
+                ia64_save_extra(prev);                                                           \
+        if (IA64_HAS_EXTRA_STATE(next))                                                          \
+                ia64_load_extra(next);                                                           \
+        ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next);                      \
+        (last) = ia64_switch_to((next));                                                         \
+} while (0)
+
+#ifdef CONFIG_SMP
+/*
+ * In the SMP case, we save the fph state when context-switching away from a thread that
+ * modified fph.  This way, when the thread gets scheduled on another CPU, the CPU can
+ * pick up the state from task->thread.fph, avoiding the complication of having to fetch
+ * the latest fph state from another CPU.  In other words: eager save, lazy restore.
+ */
+# define switch_to(prev,next,last) do {                                         \
+        if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) {                               \
+                ia64_psr(task_pt_regs(prev))->mfh = 0;                  \
+                (prev)->thread.flags |= IA64_THREAD_FPH_VALID;                  \
+                __ia64_save_fpu((prev)->thread.fph);                            \
+        }                                                                       \
+        __switch_to(prev, next, last);                                          \
+        /* "next" in old context is "current" in new context */                 \
+        if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) &&        \
+                     (task_cpu(current) !=                                     \
+                                      task_thread_info(current)->last_cpu))) { \
+                platform_migrate(current);                                     \
+                task_thread_info(current)->last_cpu = task_cpu(current);       \
+        }                                                                      \
+} while (0)
+#else
+# define switch_to(prev,next,last)      __switch_to(prev, next, last)
+#endif
+
+#define __ARCH_WANT_UNLOCKED_CTXSW
+#define ARCH_HAS_PREFETCH_SWITCH_STACK
+#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
+
+void cpu_idle_wait(void);
+
+#define arch_align_stack(x) (x)
+
+void default_idle(void);
+
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+extern void account_system_vtime(struct task_struct *);
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_IA64_SYSTEM_H */
diff --git a/arch/ia64/include/asm/termbits.h b/arch/ia64/include/asm/termbits.h
new file mode 100644
index 000000000000..9f162e0089ad
--- /dev/null
+++ b/arch/ia64/include/asm/termbits.h
@@ -0,0 +1,207 @@
+#ifndef _ASM_IA64_TERMBITS_H
+#define _ASM_IA64_TERMBITS_H
+
+/*
+ * Based on <asm-i386/termbits.h>.
+ *
+ * Modified 1999
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ *
+ * 99/01/28     Added new baudrates
+ */
+
+#include <linux/posix_types.h>
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define    BOTHER 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000          /* input baud rate */
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif /* _ASM_IA64_TERMBITS_H */
diff --git a/arch/ia64/include/asm/termios.h b/arch/ia64/include/asm/termios.h
new file mode 100644
index 000000000000..689d218c0c28
--- /dev/null
+++ b/arch/ia64/include/asm/termios.h
@@ -0,0 +1,97 @@
+#ifndef _ASM_IA64_TERMIOS_H
+#define _ASM_IA64_TERMIOS_H
+
+/*
+ * Modified 1999
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ *
+ * 99/01/28     Added N_IRDA and N_SMSBLOCK
+ */
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+# ifdef __KERNEL__
+
+/*      intr=^C         quit=^\         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) {      \
+        unsigned short __tmp;                           \
+        get_user(__tmp,&(termio)->x);                   \
+        *(unsigned short *) &(termios)->x = __tmp;      \
+}
+
+#define user_termio_to_kernel_termios(termios, termio)          \
+({                                                              \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag);         \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag);         \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag);         \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag);         \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC);   \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios)          \
+({                                                              \
+        put_user((termios)->c_iflag, &(termio)->c_iflag);       \
+        put_user((termios)->c_oflag, &(termio)->c_oflag);       \
+        put_user((termios)->c_cflag, &(termio)->c_cflag);       \
+        put_user((termios)->c_lflag, &(termio)->c_lflag);       \
+        put_user((termios)->c_line,  &(termio)->c_line);        \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC);     \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+# endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_TERMIOS_H */
diff --git a/arch/ia64/include/asm/thread_info.h b/arch/ia64/include/asm/thread_info.h
new file mode 100644
index 000000000000..7c60fcdd2efd
--- /dev/null
+++ b/arch/ia64/include/asm/thread_info.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2002-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#ifndef _ASM_IA64_THREAD_INFO_H
+#define _ASM_IA64_THREAD_INFO_H
+
+#ifndef ASM_OFFSETS_C
+#include <asm/asm-offsets.h>
+#endif
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+
+#define PREEMPT_ACTIVE_BIT 30
+#define PREEMPT_ACTIVE  (1 << PREEMPT_ACTIVE_BIT)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * On IA-64, we want to keep the task structure and kernel stack together, so they can be
+ * mapped by a single TLB entry and so they can be addressed by the "current" pointer
+ * without having to do pointer masking.
+ */
+struct thread_info {
+        struct task_struct *task;       /* XXX not really needed, except for dup_task_struct() */
+        struct exec_domain *exec_domain;/* execution domain */
+        __u32 flags;                    /* thread_info flags (see TIF_*) */
+        __u32 cpu;                      /* current CPU */
+        __u32 last_cpu;                 /* Last CPU thread ran on */
+        __u32 status;                   /* Thread synchronous flags */
+        mm_segment_t addr_limit;        /* user-level address space limit */
+        int preempt_count;              /* 0=premptable, <0=BUG; will also serve as bh-counter */
+        struct restart_block restart_block;
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+        __u64 ac_stamp;
+        __u64 ac_leave;
+        __u64 ac_stime;
+        __u64 ac_utime;
+#endif
+};
+
+#define THREAD_SIZE                     KERNEL_STACK_SIZE
+
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .addr_limit     = KERNEL_DS,            \
+        .preempt_count  = 0,                    \
+        .restart_block = {                      \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+#ifndef ASM_OFFSETS_C
+/* how to get the thread information struct from C */
+#define current_thread_info()   ((struct thread_info *) ((char *) current + IA64_TASK_SIZE))
+#define alloc_thread_info(tsk)  ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE))
+#define task_thread_info(tsk)   ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE))
+#else
+#define current_thread_info()   ((struct thread_info *) 0)
+#define alloc_thread_info(tsk)  ((struct thread_info *) 0)
+#define task_thread_info(tsk)   ((struct thread_info *) 0)
+#endif
+#define free_thread_info(ti)    /* nothing */
+#define task_stack_page(tsk)    ((void *)(tsk))
+
+#define __HAVE_THREAD_FUNCTIONS
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#define setup_thread_stack(p, org)                      \
+        *task_thread_info(p) = *task_thread_info(org);  \
+        task_thread_info(p)->ac_stime = 0;              \
+        task_thread_info(p)->ac_utime = 0;              \
+        task_thread_info(p)->task = (p);
+#else
+#define setup_thread_stack(p, org) \
+        *task_thread_info(p) = *task_thread_info(org); \
+        task_thread_info(p)->task = (p);
+#endif
+#define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET)
+
+#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
+#define alloc_task_struct()     ((struct task_struct *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER))
+#define free_task_struct(tsk)   free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER)
+
+#define tsk_set_notify_resume(tsk) \
+        set_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME)
+extern void tsk_clear_notify_resume(struct task_struct *tsk);
+#endif /* !__ASSEMBLY */
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to access
+ * - pending work-to-be-done flags are in least-significant 16 bits, other flags
+ *   in top 16 bits
+ */
+#define TIF_SIGPENDING          0       /* signal pending */
+#define TIF_NEED_RESCHED        1       /* rescheduling necessary */
+#define TIF_SYSCALL_TRACE       2       /* syscall trace active */
+#define TIF_SYSCALL_AUDIT       3       /* syscall auditing active */
+#define TIF_SINGLESTEP          4       /* restore singlestep on return to user mode */
+#define TIF_NOTIFY_RESUME       6       /* resumption notification requested */
+#define TIF_POLLING_NRFLAG      16      /* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE              17
+#define TIF_MCA_INIT            18      /* this task is processing MCA or INIT */
+#define TIF_DB_DISABLED         19      /* debug trap disabled for fsyscall */
+#define TIF_FREEZE              20      /* is freezing for suspend */
+#define TIF_RESTORE_RSE         21      /* user RBS is newer than kernel RBS */
+
+#define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
+#define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SINGLESTEP         (1 << TIF_SINGLESTEP)
+#define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
+#define _TIF_MCA_INIT           (1 << TIF_MCA_INIT)
+#define _TIF_DB_DISABLED        (1 << TIF_DB_DISABLED)
+#define _TIF_FREEZE             (1 << TIF_FREEZE)
+#define _TIF_RESTORE_RSE        (1 << TIF_RESTORE_RSE)
+
+/* "work to do on user-return" bits */
+#define TIF_ALLWORK_MASK        (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SYSCALL_AUDIT|\
+                                 _TIF_NEED_RESCHED|_TIF_SYSCALL_TRACE)
+/* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */
+#define TIF_WORK_MASK           (TIF_ALLWORK_MASK&~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT))
+
+#define TS_POLLING              1       /* true if in idle loop and not sleeping */
+#define TS_RESTORE_SIGMASK      2       /* restore signal mask in do_signal() */
+
+#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
+
+#ifndef __ASSEMBLY__
+#define HAVE_SET_RESTORE_SIGMASK        1
+static inline void set_restore_sigmask(void)
+{
+        struct thread_info *ti = current_thread_info();
+        ti->status |= TS_RESTORE_SIGMASK;
+        set_bit(TIF_SIGPENDING, &ti->flags);
+}
+#endif  /* !__ASSEMBLY__ */
+
+#endif /* _ASM_IA64_THREAD_INFO_H */
diff --git a/arch/ia64/include/asm/timex.h b/arch/ia64/include/asm/timex.h
new file mode 100644
index 000000000000..05a6baf8a472
--- /dev/null
+++ b/arch/ia64/include/asm/timex.h
@@ -0,0 +1,42 @@
+#ifndef _ASM_IA64_TIMEX_H
+#define _ASM_IA64_TIMEX_H
+
+/*
+ * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+/*
+ * 2001/01/18 davidm    Removed CLOCK_TICK_RATE.  It makes no sense on IA-64.
+ *                      Also removed cacheflush_time as it's entirely unused.
+ */
+
+#include <asm/intrinsics.h>
+#include <asm/processor.h>
+
+typedef unsigned long cycles_t;
+
+extern void (*ia64_udelay)(unsigned long usecs);
+
+/*
+ * For performance reasons, we don't want to define CLOCK_TICK_TRATE as
+ * local_cpu_data->itc_rate.  Fortunately, we don't have to, either: according to George
+ * Anzinger, 1/CLOCK_TICK_RATE is taken as the resolution of the timer clock.  The time
+ * calculation assumes that you will use enough of these so that your tick size <= 1/HZ.
+ * If the calculation shows that your CLOCK_TICK_RATE can not supply exactly 1/HZ ticks,
+ * the actual value is calculated and used to update the wall clock each jiffie.  Setting
+ * the CLOCK_TICK_RATE to x*HZ insures that the calculation will find no errors.  Hence we
+ * pick a multiple of HZ which gives us a (totally virtual) CLOCK_TICK_RATE of about
+ * 100MHz.
+ */
+#define CLOCK_TICK_RATE         (HZ * 100000UL)
+
+static inline cycles_t
+get_cycles (void)
+{
+        cycles_t ret;
+
+        ret = ia64_getreg(_IA64_REG_AR_ITC);
+        return ret;
+}
+
+#endif /* _ASM_IA64_TIMEX_H */
diff --git a/arch/ia64/include/asm/tlb.h b/arch/ia64/include/asm/tlb.h
new file mode 100644
index 000000000000..20d8a39680c2
--- /dev/null
+++ b/arch/ia64/include/asm/tlb.h
@@ -0,0 +1,257 @@
+#ifndef _ASM_IA64_TLB_H
+#define _ASM_IA64_TLB_H
+/*
+ * Based on <asm-generic/tlb.h>.
+ *
+ * Copyright (C) 2002-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+/*
+ * Removing a translation from a page table (including TLB-shootdown) is a four-step
+ * procedure:
+ *
+ *      (1) Flush (virtual) caches --- ensures virtual memory is coherent with kernel memory
+ *          (this is a no-op on ia64).
+ *      (2) Clear the relevant portions of the page-table
+ *      (3) Flush the TLBs --- ensures that stale content is gone from CPU TLBs
+ *      (4) Release the pages that were freed up in step (2).
+ *
+ * Note that the ordering of these steps is crucial to avoid races on MP machines.
+ *
+ * The Linux kernel defines several platform-specific hooks for TLB-shootdown.  When
+ * unmapping a portion of the virtual address space, these hooks are called according to
+ * the following template:
+ *
+ *      tlb <- tlb_gather_mmu(mm, full_mm_flush);       // start unmap for address space MM
+ *      {
+ *        for each vma that needs a shootdown do {
+ *          tlb_start_vma(tlb, vma);
+ *            for each page-table-entry PTE that needs to be removed do {
+ *              tlb_remove_tlb_entry(tlb, pte, address);
+ *              if (pte refers to a normal page) {
+ *                tlb_remove_page(tlb, page);
+ *              }
+ *            }
+ *          tlb_end_vma(tlb, vma);
+ *        }
+ *      }
+ *      tlb_finish_mmu(tlb, start, end);        // finish unmap for address space MM
+ */
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+#include <linux/swap.h>
+
+#include <asm/pgalloc.h>
+#include <asm/processor.h>
+#include <asm/tlbflush.h>
+#include <asm/machvec.h>
+
+#ifdef CONFIG_SMP
+# define FREE_PTE_NR            2048
+# define tlb_fast_mode(tlb)     ((tlb)->nr == ~0U)
+#else
+# define FREE_PTE_NR            0
+# define tlb_fast_mode(tlb)     (1)
+#endif
+
+struct mmu_gather {
+        struct mm_struct        *mm;
+        unsigned int            nr;             /* == ~0U => fast mode */
+        unsigned char           fullmm;         /* non-zero means full mm flush */
+        unsigned char           need_flush;     /* really unmapped some PTEs? */
+        unsigned long           start_addr;
+        unsigned long           end_addr;
+        struct page             *pages[FREE_PTE_NR];
+};
+
+struct ia64_tr_entry {
+        u64 ifa;
+        u64 itir;
+        u64 pte;
+        u64 rr;
+}; /*Record for tr entry!*/
+
+extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
+extern void ia64_ptr_entry(u64 target_mask, int slot);
+
+extern struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
+
+/*
+ region register macros
+*/
+#define RR_TO_VE(val)   (((val) >> 0) & 0x0000000000000001)
+#define RR_VE(val)      (((val) & 0x0000000000000001) << 0)
+#define RR_VE_MASK      0x0000000000000001L
+#define RR_VE_SHIFT     0
+#define RR_TO_PS(val)   (((val) >> 2) & 0x000000000000003f)
+#define RR_PS(val)      (((val) & 0x000000000000003f) << 2)
+#define RR_PS_MASK      0x00000000000000fcL
+#define RR_PS_SHIFT     2
+#define RR_RID_MASK     0x00000000ffffff00L
+#define RR_TO_RID(val)  ((val >> 8) & 0xffffff)
+
+/* Users of the generic TLB shootdown code must declare this storage space. */
+DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+/*
+ * Flush the TLB for address range START to END and, if not in fast mode, release the
+ * freed pages that where gathered up to this point.
+ */
+static inline void
+ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
+{
+        unsigned int nr;
+
+        if (!tlb->need_flush)
+                return;
+        tlb->need_flush = 0;
+
+        if (tlb->fullmm) {
+                /*
+                 * Tearing down the entire address space.  This happens both as a result
+                 * of exit() and execve().  The latter case necessitates the call to
+                 * flush_tlb_mm() here.
+                 */
+                flush_tlb_mm(tlb->mm);
+        } else if (unlikely (end - start >= 1024*1024*1024*1024UL
+                             || REGION_NUMBER(start) != REGION_NUMBER(end - 1)))
+        {
+                /*
+                 * If we flush more than a tera-byte or across regions, we're probably
+                 * better off just flushing the entire TLB(s).  This should be very rare
+                 * and is not worth optimizing for.
+                 */
+                flush_tlb_all();
+        } else {
+                /*
+                 * XXX fix me: flush_tlb_range() should take an mm pointer instead of a
+                 * vma pointer.
+                 */
+                struct vm_area_struct vma;
+
+                vma.vm_mm = tlb->mm;
+                /* flush the address range from the tlb: */
+                flush_tlb_range(&vma, start, end);
+                /* now flush the virt. page-table area mapping the address range: */
+                flush_tlb_range(&vma, ia64_thash(start), ia64_thash(end));
+        }
+
+        /* lastly, release the freed pages */
+        nr = tlb->nr;
+        if (!tlb_fast_mode(tlb)) {
+                unsigned long i;
+                tlb->nr = 0;
+                tlb->start_addr = ~0UL;
+                for (i = 0; i < nr; ++i)
+                        free_page_and_swap_cache(tlb->pages[i]);
+        }
+}
+
+/*
+ * Return a pointer to an initialized struct mmu_gather.
+ */
+static inline struct mmu_gather *
+tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
+{
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
+
+        tlb->mm = mm;
+        /*
+         * Use fast mode if only 1 CPU is online.
+         *
+         * It would be tempting to turn on fast-mode for full_mm_flush as well.  But this
+         * doesn't work because of speculative accesses and software prefetching: the page
+         * table of "mm" may (and usually is) the currently active page table and even
+         * though the kernel won't do any user-space accesses during the TLB shoot down, a
+         * compiler might use speculation or lfetch.fault on what happens to be a valid
+         * user-space address.  This in turn could trigger a TLB miss fault (or a VHPT
+         * walk) and re-insert a TLB entry we just removed.  Slow mode avoids such
+         * problems.  (We could make fast-mode work by switching the current task to a
+         * different "mm" during the shootdown.) --davidm 08/02/2002
+         */
+        tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
+        tlb->fullmm = full_mm_flush;
+        tlb->start_addr = ~0UL;
+        return tlb;
+}
+
+/*
+ * Called at the end of the shootdown operation to free up any resources that were
+ * collected.
+ */
+static inline void
+tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
+{
+        /*
+         * Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
+         * tlb->end_addr.
+         */
+        ia64_tlb_flush_mmu(tlb, start, end);
+
+        /* keep the page table cache within bounds */
+        check_pgt_cache();
+
+        put_cpu_var(mmu_gathers);
+}
+
+/*
+ * Logically, this routine frees PAGE.  On MP machines, the actual freeing of the page
+ * must be delayed until after the TLB has been flushed (see comments at the beginning of
+ * this file).
+ */
+static inline void
+tlb_remove_page (struct mmu_gather *tlb, struct page *page)
+{
+        tlb->need_flush = 1;
+
+        if (tlb_fast_mode(tlb)) {
+                free_page_and_swap_cache(page);
+                return;
+        }
+        tlb->pages[tlb->nr++] = page;
+        if (tlb->nr >= FREE_PTE_NR)
+                ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
+}
+
+/*
+ * Remove TLB entry for PTE mapped at virtual address ADDRESS.  This is called for any
+ * PTE, not just those pointing to (normal) physical memory.
+ */
+static inline void
+__tlb_remove_tlb_entry (struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
+{
+        if (tlb->start_addr == ~0UL)
+                tlb->start_addr = address;
+        tlb->end_addr = address + PAGE_SIZE;
+}
+
+#define tlb_migrate_finish(mm)  platform_tlb_migrate_finish(mm)
+
+#define tlb_start_vma(tlb, vma)                 do { } while (0)
+#define tlb_end_vma(tlb, vma)                   do { } while (0)
+
+#define tlb_remove_tlb_entry(tlb, ptep, addr)           \
+do {                                                    \
+        tlb->need_flush = 1;                            \
+        __tlb_remove_tlb_entry(tlb, ptep, addr);        \
+} while (0)
+
+#define pte_free_tlb(tlb, ptep)                         \
+do {                                                    \
+        tlb->need_flush = 1;                            \
+        __pte_free_tlb(tlb, ptep);                      \
+} while (0)
+
+#define pmd_free_tlb(tlb, ptep)                         \
+do {                                                    \
+        tlb->need_flush = 1;                            \
+        __pmd_free_tlb(tlb, ptep);                      \
+} while (0)
+
+#define pud_free_tlb(tlb, pudp)                         \
+do {                                                    \
+        tlb->need_flush = 1;                            \
+        __pud_free_tlb(tlb, pudp);                      \
+} while (0)
+
+#endif /* _ASM_IA64_TLB_H */
diff --git a/arch/ia64/include/asm/tlbflush.h b/arch/ia64/include/asm/tlbflush.h
new file mode 100644
index 000000000000..3be25dfed164
--- /dev/null
+++ b/arch/ia64/include/asm/tlbflush.h
@@ -0,0 +1,102 @@
+#ifndef _ASM_IA64_TLBFLUSH_H
+#define _ASM_IA64_TLBFLUSH_H
+
+/*
+ * Copyright (C) 2002 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+
+#include <linux/mm.h>
+
+#include <asm/intrinsics.h>
+#include <asm/mmu_context.h>
+#include <asm/page.h>
+
+/*
+ * Now for some TLB flushing routines.  This is the kind of stuff that
+ * can be very expensive, so try to avoid them whenever possible.
+ */
+extern void setup_ptcg_sem(int max_purges, int from_palo);
+
+/*
+ * Flush everything (kernel mapping may also have changed due to
+ * vmalloc/vfree).
+ */
+extern void local_flush_tlb_all (void);
+
+#ifdef CONFIG_SMP
+  extern void smp_flush_tlb_all (void);
+  extern void smp_flush_tlb_mm (struct mm_struct *mm);
+  extern void smp_flush_tlb_cpumask (cpumask_t xcpumask);
+# define flush_tlb_all()        smp_flush_tlb_all()
+#else
+# define flush_tlb_all()        local_flush_tlb_all()
+# define smp_flush_tlb_cpumask(m) local_flush_tlb_all()
+#endif
+
+static inline void
+local_finish_flush_tlb_mm (struct mm_struct *mm)
+{
+        if (mm == current->active_mm)
+                activate_context(mm);
+}
+
+/*
+ * Flush a specified user mapping.  This is called, e.g., as a result of fork() and
+ * exit().  fork() ends up here because the copy-on-write mechanism needs to write-protect
+ * the PTEs of the parent task.
+ */
+static inline void
+flush_tlb_mm (struct mm_struct *mm)
+{
+        if (!mm)
+                return;
+
+        set_bit(mm->context, ia64_ctx.flushmap);
+        mm->context = 0;
+
+        if (atomic_read(&mm->mm_users) == 0)
+                return;         /* happens as a result of exit_mmap() */
+
+#ifdef CONFIG_SMP
+        smp_flush_tlb_mm(mm);
+#else
+        local_finish_flush_tlb_mm(mm);
+#endif
+}
+
+extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end);
+
+/*
+ * Page-granular tlb flush.
+ */
+static inline void
+flush_tlb_page (struct vm_area_struct *vma, unsigned long addr)
+{
+#ifdef CONFIG_SMP
+        flush_tlb_range(vma, (addr & PAGE_MASK), (addr & PAGE_MASK) + PAGE_SIZE);
+#else
+        if (vma->vm_mm == current->active_mm)
+                ia64_ptcl(addr, (PAGE_SHIFT << 2));
+        else
+                vma->vm_mm->context = 0;
+#endif
+}
+
+/*
+ * Flush the local TLB. Invoked from another cpu using an IPI.
+ */
+#ifdef CONFIG_SMP
+void smp_local_flush_tlb(void);
+#else
+#define smp_local_flush_tlb()
+#endif
+
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+        flush_tlb_all();        /* XXX fix me */
+}
+
+#endif /* _ASM_IA64_TLBFLUSH_H */
diff --git a/arch/ia64/include/asm/topology.h b/arch/ia64/include/asm/topology.h
new file mode 100644
index 000000000000..35bcb641c9e5
--- /dev/null
+++ b/arch/ia64/include/asm/topology.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2002, Erich Focht, NEC
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef _ASM_IA64_TOPOLOGY_H
+#define _ASM_IA64_TOPOLOGY_H
+
+#include <asm/acpi.h>
+#include <asm/numa.h>
+#include <asm/smp.h>
+
+#ifdef CONFIG_NUMA
+
+/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
+#define PENALTY_FOR_NODE_WITH_CPUS 255
+
+/*
+ * Distance above which we begin to use zone reclaim
+ */
+#define RECLAIM_DISTANCE 15
+
+/*
+ * Returns the number of the node containing CPU 'cpu'
+ */
+#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
+
+/*
+ * Returns a bitmask of CPUs on Node 'node'.
+ */
+#define node_to_cpumask(node) (node_to_cpu_mask[node])
+
+/*
+ * Returns the number of the node containing Node 'nid'.
+ * Not implemented here. Multi-level hierarchies detected with
+ * the help of node_distance().
+ */
+#define parent_node(nid) (nid)
+
+/*
+ * Returns the number of the first CPU on Node 'node'.
+ */
+#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
+
+/*
+ * Determines the node for a given pci bus
+ */
+#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
+
+void build_cpu_to_node_map(void);
+
+#define SD_CPU_INIT (struct sched_domain) {             \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .child                  = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 1,                    \
+        .max_interval           = 4,                    \
+        .busy_factor            = 64,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 2,                    \
+        .idle_idx               = 1,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_NEWIDLE    \
+                                | SD_BALANCE_EXEC       \
+                                | SD_WAKE_AFFINE,       \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+        .nr_balance_failed      = 0,                    \
+}
+
+/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .child                  = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 8,                    \
+        .max_interval           = 8*(min(num_online_cpus(), 32)), \
+        .busy_factor            = 64,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 2,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_EXEC       \
+                                | SD_BALANCE_FORK       \
+                                | SD_SERIALIZE          \
+                                | SD_WAKE_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 64,                   \
+        .nr_balance_failed      = 0,                    \
+}
+
+#endif /* CONFIG_NUMA */
+
+#ifdef CONFIG_SMP
+#define topology_physical_package_id(cpu)       (cpu_data(cpu)->socket_id)
+#define topology_core_id(cpu)                   (cpu_data(cpu)->core_id)
+#define topology_core_siblings(cpu)             (cpu_core_map[cpu])
+#define topology_thread_siblings(cpu)           (per_cpu(cpu_sibling_map, cpu))
+#define smt_capable()                           (smp_num_siblings > 1)
+#endif
+
+extern void arch_fix_phys_package_id(int num, u32 slot);
+
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_IA64_TOPOLOGY_H */
diff --git a/arch/ia64/include/asm/types.h b/arch/ia64/include/asm/types.h
new file mode 100644
index 000000000000..e36b3716e718
--- /dev/null
+++ b/arch/ia64/include/asm/types.h
@@ -0,0 +1,46 @@
+#ifndef _ASM_IA64_TYPES_H
+#define _ASM_IA64_TYPES_H
+
+/*
+ * This file is never included by application software unless explicitly requested (e.g.,
+ * via linux/types.h) in which case the application is Linux specific so (user-) name
+ * space pollution is not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ *
+ * Based on <asm-alpha/types.h>.
+ *
+ * Modified 1998-2000, 2002
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#include <asm-generic/int-l64.h>
+
+#ifdef __ASSEMBLY__
+# define __IA64_UL(x)           (x)
+# define __IA64_UL_CONST(x)     x
+
+# ifdef __KERNEL__
+#  define BITS_PER_LONG 64
+# endif
+
+#else
+# define __IA64_UL(x)           ((unsigned long)(x))
+# define __IA64_UL_CONST(x)     x##UL
+
+typedef unsigned int umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+# ifdef __KERNEL__
+
+#define BITS_PER_LONG 64
+
+/* DMA addresses are 64-bits wide, in general.  */
+
+typedef u64 dma_addr_t;
+
+# endif /* __KERNEL__ */
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_IA64_TYPES_H */
diff --git a/arch/ia64/include/asm/uaccess.h b/arch/ia64/include/asm/uaccess.h
new file mode 100644
index 000000000000..449c8c0fa2bd
--- /dev/null
+++ b/arch/ia64/include/asm/uaccess.h
@@ -0,0 +1,401 @@
+#ifndef _ASM_IA64_UACCESS_H
+#define _ASM_IA64_UACCESS_H
+
+/*
+ * This file defines various macros to transfer memory areas across
+ * the user/kernel boundary.  This needs to be done carefully because
+ * this code is executed in kernel mode and uses user-specified
+ * addresses.  Thus, we need to be careful not to let the user to
+ * trick us into accessing kernel memory that would normally be
+ * inaccessible.  This code is also fairly performance sensitive,
+ * so we want to spend as little time doing safety checks as
+ * possible.
+ *
+ * To make matters a bit more interesting, these macros sometimes also
+ * called from within the kernel itself, in which case the address
+ * validity check must be skipped.  The get_fs() macro tells us what
+ * to do: if get_fs()==USER_DS, checking is performed, if
+ * get_fs()==KERNEL_DS, checking is bypassed.
+ *
+ * Note that even if the memory area specified by the user is in a
+ * valid address range, it is still possible that we'll get a page
+ * fault while accessing it.  This is handled by filling out an
+ * exception handler fixup entry for each instruction that has the
+ * potential to fault.  When such a fault occurs, the page fault
+ * handler checks to see whether the faulting instruction has a fixup
+ * associated and, if so, sets r8 to -EFAULT and clears r9 to 0 and
+ * then resumes execution at the continuation point.
+ *
+ * Based on <asm-alpha/uaccess.h>.
+ *
+ * Copyright (C) 1998, 1999, 2001-2004 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <linux/compiler.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/page-flags.h>
+#include <linux/mm.h>
+
+#include <asm/intrinsics.h>
+#include <asm/pgtable.h>
+#include <asm/io.h>
+
+/*
+ * For historical reasons, the following macros are grossly misnamed:
+ */
+#define KERNEL_DS       ((mm_segment_t) { ~0UL })               /* cf. access_ok() */
+#define USER_DS         ((mm_segment_t) { TASK_SIZE-1 })        /* cf. access_ok() */
+
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+
+#define get_ds()  (KERNEL_DS)
+#define get_fs()  (current_thread_info()->addr_limit)
+#define set_fs(x) (current_thread_info()->addr_limit = (x))
+
+#define segment_eq(a, b)        ((a).seg == (b).seg)
+
+/*
+ * When accessing user memory, we need to make sure the entire area really is in
+ * user-level space.  In order to do this efficiently, we make sure that the page at
+ * address TASK_SIZE is never valid.  We also need to make sure that the address doesn't
+ * point inside the virtually mapped linear page table.
+ */
+#define __access_ok(addr, size, segment)                                                \
+({                                                                                      \
+        __chk_user_ptr(addr);                                                           \
+        (likely((unsigned long) (addr) <= (segment).seg)                                \
+         && ((segment).seg == KERNEL_DS.seg                                             \
+             || likely(REGION_OFFSET((unsigned long) (addr)) < RGN_MAP_LIMIT)));        \
+})
+#define access_ok(type, addr, size)     __access_ok((addr), (size), get_fs())
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * Careful to not
+ * (a) re-use the arguments for side effects (sizeof/typeof is ok)
+ * (b) require any knowledge of processes at this stage
+ */
+#define put_user(x, ptr)        __put_user_check((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr)), get_fs())
+#define get_user(x, ptr)        __get_user_check((x), (ptr), sizeof(*(ptr)), get_fs())
+
+/*
+ * The "__xxx" versions do not do address space checking, useful when
+ * doing multiple accesses to the same area (the programmer has to do the
+ * checks by hand with "access_ok()")
+ */
+#define __put_user(x, ptr)      __put_user_nocheck((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr)))
+#define __get_user(x, ptr)      __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+extern long __put_user_unaligned_unknown (void);
+
+#define __put_user_unaligned(x, ptr)                                                            \
+({                                                                                              \
+        long __ret;                                                                             \
+        switch (sizeof(*(ptr))) {                                                               \
+                case 1: __ret = __put_user((x), (ptr)); break;                                  \
+                case 2: __ret = (__put_user((x), (u8 __user *)(ptr)))                           \
+                        | (__put_user((x) >> 8, ((u8 __user *)(ptr) + 1))); break;              \
+                case 4: __ret = (__put_user((x), (u16 __user *)(ptr)))                          \
+                        | (__put_user((x) >> 16, ((u16 __user *)(ptr) + 1))); break;            \
+                case 8: __ret = (__put_user((x), (u32 __user *)(ptr)))                          \
+                        | (__put_user((x) >> 32, ((u32 __user *)(ptr) + 1))); break;            \
+                default: __ret = __put_user_unaligned_unknown();                                \
+        }                                                                                       \
+        __ret;                                                                                  \
+})
+
+extern long __get_user_unaligned_unknown (void);
+
+#define __get_user_unaligned(x, ptr)                                                            \
+({                                                                                              \
+        long __ret;                                                                             \
+        switch (sizeof(*(ptr))) {                                                               \
+                case 1: __ret = __get_user((x), (ptr)); break;                                  \
+                case 2: __ret = (__get_user((x), (u8 __user *)(ptr)))                           \
+                        | (__get_user((x) >> 8, ((u8 __user *)(ptr) + 1))); break;              \
+                case 4: __ret = (__get_user((x), (u16 __user *)(ptr)))                          \
+                        | (__get_user((x) >> 16, ((u16 __user *)(ptr) + 1))); break;            \
+                case 8: __ret = (__get_user((x), (u32 __user *)(ptr)))                          \
+                        | (__get_user((x) >> 32, ((u32 __user *)(ptr) + 1))); break;            \
+                default: __ret = __get_user_unaligned_unknown();                                \
+        }                                                                                       \
+        __ret;                                                                                  \
+})
+
+#ifdef ASM_SUPPORTED
+  struct __large_struct { unsigned long buf[100]; };
+# define __m(x) (*(struct __large_struct __user *)(x))
+
+/* We need to declare the __ex_table section before we can use it in .xdata.  */
+asm (".section \"__ex_table\", \"a\"\n\t.previous");
+
+# define __get_user_size(val, addr, n, err)                                                     \
+do {                                                                                            \
+        register long __gu_r8 asm ("r8") = 0;                                                   \
+        register long __gu_r9 asm ("r9");                                                       \
+        asm ("\n[1:]\tld"#n" %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n"     \
+             "\t.xdata4 \"__ex_table\", 1b-., 1f-.+4\n"                                         \
+             "[1:]"                                                                             \
+             : "=r"(__gu_r9), "=r"(__gu_r8) : "m"(__m(addr)), "1"(__gu_r8));                    \
+        (err) = __gu_r8;                                                                        \
+        (val) = __gu_r9;                                                                        \
+} while (0)
+
+/*
+ * The "__put_user_size()" macro tells gcc it reads from memory instead of writing it.  This
+ * is because they do not write to any memory gcc knows about, so there are no aliasing
+ * issues.
+ */
+# define __put_user_size(val, addr, n, err)                                                     \
+do {                                                                                            \
+        register long __pu_r8 asm ("r8") = 0;                                                   \
+        asm volatile ("\n[1:]\tst"#n" %1=%r2%P1\t// %0 gets overwritten by exception handler\n" \
+                      "\t.xdata4 \"__ex_table\", 1b-., 1f-.\n"                                  \
+                      "[1:]"                                                                    \
+                      : "=r"(__pu_r8) : "m"(__m(addr)), "rO"(val), "0"(__pu_r8));               \
+        (err) = __pu_r8;                                                                        \
+} while (0)
+
+#else /* !ASM_SUPPORTED */
+# define RELOC_TYPE     2       /* ip-rel */
+# define __get_user_size(val, addr, n, err)                             \
+do {                                                                    \
+        __ld_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE);   \
+        (err) = ia64_getreg(_IA64_REG_R8);                              \
+        (val) = ia64_getreg(_IA64_REG_R9);                              \
+} while (0)
+# define __put_user_size(val, addr, n, err)                                                     \
+do {                                                                                            \
+        __st_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE, (unsigned long) (val));    \
+        (err) = ia64_getreg(_IA64_REG_R8);                                                      \
+} while (0)
+#endif /* !ASM_SUPPORTED */
+
+extern void __get_user_unknown (void);
+
+/*
+ * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which
+ * could clobber r8 and r9 (among others).  Thus, be careful not to evaluate it while
+ * using r8/r9.
+ */
+#define __do_get_user(check, x, ptr, size, segment)                                     \
+({                                                                                      \
+        const __typeof__(*(ptr)) __user *__gu_ptr = (ptr);                              \
+        __typeof__ (size) __gu_size = (size);                                           \
+        long __gu_err = -EFAULT;                                                        \
+        unsigned long __gu_val = 0;                                                     \
+        if (!check || __access_ok(__gu_ptr, size, segment))                             \
+                switch (__gu_size) {                                                    \
+                      case 1: __get_user_size(__gu_val, __gu_ptr, 1, __gu_err); break;  \
+                      case 2: __get_user_size(__gu_val, __gu_ptr, 2, __gu_err); break;  \
+                      case 4: __get_user_size(__gu_val, __gu_ptr, 4, __gu_err); break;  \
+                      case 8: __get_user_size(__gu_val, __gu_ptr, 8, __gu_err); break;  \
+                      default: __get_user_unknown(); break;                             \
+                }                                                                       \
+        (x) = (__typeof__(*(__gu_ptr))) __gu_val;                                       \
+        __gu_err;                                                                       \
+})
+
+#define __get_user_nocheck(x, ptr, size)        __do_get_user(0, x, ptr, size, KERNEL_DS)
+#define __get_user_check(x, ptr, size, segment) __do_get_user(1, x, ptr, size, segment)
+
+extern void __put_user_unknown (void);
+
+/*
+ * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which
+ * could clobber r8 (among others).  Thus, be careful not to evaluate them while using r8.
+ */
+#define __do_put_user(check, x, ptr, size, segment)                                     \
+({                                                                                      \
+        __typeof__ (x) __pu_x = (x);                                                    \
+        __typeof__ (*(ptr)) __user *__pu_ptr = (ptr);                                   \
+        __typeof__ (size) __pu_size = (size);                                           \
+        long __pu_err = -EFAULT;                                                        \
+                                                                                        \
+        if (!check || __access_ok(__pu_ptr, __pu_size, segment))                        \
+                switch (__pu_size) {                                                    \
+                      case 1: __put_user_size(__pu_x, __pu_ptr, 1, __pu_err); break;    \
+                      case 2: __put_user_size(__pu_x, __pu_ptr, 2, __pu_err); break;    \
+                      case 4: __put_user_size(__pu_x, __pu_ptr, 4, __pu_err); break;    \
+                      case 8: __put_user_size(__pu_x, __pu_ptr, 8, __pu_err); break;    \
+                      default: __put_user_unknown(); break;                             \
+                }                                                                       \
+        __pu_err;                                                                       \
+})
+
+#define __put_user_nocheck(x, ptr, size)        __do_put_user(0, x, ptr, size, KERNEL_DS)
+#define __put_user_check(x, ptr, size, segment) __do_put_user(1, x, ptr, size, segment)
+
+/*
+ * Complex access routines
+ */
+extern unsigned long __must_check __copy_user (void __user *to, const void __user *from,
+                                               unsigned long count);
+
+static inline unsigned long
+__copy_to_user (void __user *to, const void *from, unsigned long count)
+{
+        return __copy_user(to, (__force void __user *) from, count);
+}
+
+static inline unsigned long
+__copy_from_user (void *to, const void __user *from, unsigned long count)
+{
+        return __copy_user((__force void __user *) to, from, count);
+}
+
+#define __copy_to_user_inatomic         __copy_to_user
+#define __copy_from_user_inatomic       __copy_from_user
+#define copy_to_user(to, from, n)                                                       \
+({                                                                                      \
+        void __user *__cu_to = (to);                                                    \
+        const void *__cu_from = (from);                                                 \
+        long __cu_len = (n);                                                            \
+                                                                                        \
+        if (__access_ok(__cu_to, __cu_len, get_fs()))                                   \
+                __cu_len = __copy_user(__cu_to, (__force void __user *) __cu_from, __cu_len);   \
+        __cu_len;                                                                       \
+})
+
+#define copy_from_user(to, from, n)                                                     \
+({                                                                                      \
+        void *__cu_to = (to);                                                           \
+        const void __user *__cu_from = (from);                                          \
+        long __cu_len = (n);                                                            \
+                                                                                        \
+        __chk_user_ptr(__cu_from);                                                      \
+        if (__access_ok(__cu_from, __cu_len, get_fs()))                                 \
+                __cu_len = __copy_user((__force void __user *) __cu_to, __cu_from, __cu_len);   \
+        __cu_len;                                                                       \
+})
+
+#define __copy_in_user(to, from, size)  __copy_user((to), (from), (size))
+
+static inline unsigned long
+copy_in_user (void __user *to, const void __user *from, unsigned long n)
+{
+        if (likely(access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)))
+                n = __copy_user(to, from, n);
+        return n;
+}
+
+extern unsigned long __do_clear_user (void __user *, unsigned long);
+
+#define __clear_user(to, n)             __do_clear_user(to, n)
+
+#define clear_user(to, n)                                       \
+({                                                              \
+        unsigned long __cu_len = (n);                           \
+        if (__access_ok(to, __cu_len, get_fs()))                \
+                __cu_len = __do_clear_user(to, __cu_len);       \
+        __cu_len;                                               \
+})
+
+
+/*
+ * Returns: -EFAULT if exception before terminator, N if the entire buffer filled, else
+ * strlen.
+ */
+extern long __must_check __strncpy_from_user (char *to, const char __user *from, long to_len);
+
+#define strncpy_from_user(to, from, n)                                  \
+({                                                                      \
+        const char __user * __sfu_from = (from);                        \
+        long __sfu_ret = -EFAULT;                                       \
+        if (__access_ok(__sfu_from, 0, get_fs()))                       \
+                __sfu_ret = __strncpy_from_user((to), __sfu_from, (n)); \
+        __sfu_ret;                                                      \
+})
+
+/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
+extern unsigned long __strlen_user (const char __user *);
+
+#define strlen_user(str)                                \
+({                                                      \
+        const char __user *__su_str = (str);            \
+        unsigned long __su_ret = 0;                     \
+        if (__access_ok(__su_str, 0, get_fs()))         \
+                __su_ret = __strlen_user(__su_str);     \
+        __su_ret;                                       \
+})
+
+/*
+ * Returns: 0 if exception before NUL or reaching the supplied limit
+ * (N), a value greater than N if the limit would be exceeded, else
+ * strlen.
+ */
+extern unsigned long __strnlen_user (const char __user *, long);
+
+#define strnlen_user(str, len)                                  \
+({                                                              \
+        const char __user *__su_str = (str);                    \
+        unsigned long __su_ret = 0;                             \
+        if (__access_ok(__su_str, 0, get_fs()))                 \
+                __su_ret = __strnlen_user(__su_str, len);       \
+        __su_ret;                                               \
+})
+
+/* Generic code can't deal with the location-relative format that we use for compactness.  */
+#define ARCH_HAS_SORT_EXTABLE
+#define ARCH_HAS_SEARCH_EXTABLE
+
+struct exception_table_entry {
+        int addr;       /* location-relative address of insn this fixup is for */
+        int cont;       /* location-relative continuation addr.; if bit 2 is set, r9 is set to 0 */
+};
+
+extern void ia64_handle_exception (struct pt_regs *regs, const struct exception_table_entry *e);
+extern const struct exception_table_entry *search_exception_tables (unsigned long addr);
+
+static inline int
+ia64_done_with_exception (struct pt_regs *regs)
+{
+        const struct exception_table_entry *e;
+        e = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri);
+        if (e) {
+                ia64_handle_exception(regs, e);
+                return 1;
+        }
+        return 0;
+}
+
+#define ARCH_HAS_TRANSLATE_MEM_PTR      1
+static __inline__ char *
+xlate_dev_mem_ptr (unsigned long p)
+{
+        struct page *page;
+        char * ptr;
+
+        page = pfn_to_page(p >> PAGE_SHIFT);
+        if (PageUncached(page))
+                ptr = (char *)p + __IA64_UNCACHED_OFFSET;
+        else
+                ptr = __va(p);
+
+        return ptr;
+}
+
+/*
+ * Convert a virtual cached kernel memory pointer to an uncached pointer
+ */
+static __inline__ char *
+xlate_dev_kmem_ptr (char * p)
+{
+        struct page *page;
+        char * ptr;
+
+        page = virt_to_page((unsigned long)p);
+        if (PageUncached(page))
+                ptr = (char *)__pa(p) + __IA64_UNCACHED_OFFSET;
+        else
+                ptr = p;
+
+        return ptr;
+}
+
+#endif /* _ASM_IA64_UACCESS_H */
diff --git a/arch/ia64/include/asm/ucontext.h b/arch/ia64/include/asm/ucontext.h
new file mode 100644
index 000000000000..bf573dc8ca6a
--- /dev/null
+++ b/arch/ia64/include/asm/ucontext.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_IA64_UCONTEXT_H
+#define _ASM_IA64_UCONTEXT_H
+
+struct ucontext {
+        struct sigcontext uc_mcontext;
+};
+
+#define uc_link         uc_mcontext.sc_gr[0]    /* wrong type; nobody cares */
+#define uc_sigmask      uc_mcontext.sc_sigmask
+#define uc_stack        uc_mcontext.sc_stack
+
+#endif /* _ASM_IA64_UCONTEXT_H */
diff --git a/arch/ia64/include/asm/unaligned.h b/arch/ia64/include/asm/unaligned.h
new file mode 100644
index 000000000000..7bddc7f58584
--- /dev/null
+++ b/arch/ia64/include/asm/unaligned.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_IA64_UNALIGNED_H
+#define _ASM_IA64_UNALIGNED_H
+
+#include <linux/unaligned/le_struct.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned   __get_unaligned_le
+#define put_unaligned   __put_unaligned_le
+
+#endif /* _ASM_IA64_UNALIGNED_H */
diff --git a/arch/ia64/include/asm/uncached.h b/arch/ia64/include/asm/uncached.h
new file mode 100644
index 000000000000..13d7e65ca3cc
--- /dev/null
+++ b/arch/ia64/include/asm/uncached.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2001-2008 Silicon Graphics, Inc.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * Prototypes for the uncached page allocator
+ */
+
+extern unsigned long uncached_alloc_page(int starting_nid, int n_pages);
+extern void uncached_free_page(unsigned long uc_addr, int n_pages);
diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h
new file mode 100644
index 000000000000..d535833aab5e
--- /dev/null
+++ b/arch/ia64/include/asm/unistd.h
@@ -0,0 +1,384 @@
+#ifndef _ASM_IA64_UNISTD_H
+#define _ASM_IA64_UNISTD_H
+
+/*
+ * IA-64 Linux syscall numbers and inline-functions.
+ *
+ * Copyright (C) 1998-2005 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+
+#include <asm/break.h>
+
+#define __BREAK_SYSCALL                 __IA64_BREAK_SYSCALL
+
+#define __NR_ni_syscall                 1024
+#define __NR_exit                       1025
+#define __NR_read                       1026
+#define __NR_write                      1027
+#define __NR_open                       1028
+#define __NR_close                      1029
+#define __NR_creat                      1030
+#define __NR_link                       1031
+#define __NR_unlink                     1032
+#define __NR_execve                     1033
+#define __NR_chdir                      1034
+#define __NR_fchdir                     1035
+#define __NR_utimes                     1036
+#define __NR_mknod                      1037
+#define __NR_chmod                      1038
+#define __NR_chown                      1039
+#define __NR_lseek                      1040
+#define __NR_getpid                     1041
+#define __NR_getppid                    1042
+#define __NR_mount                      1043
+#define __NR_umount                     1044
+#define __NR_setuid                     1045
+#define __NR_getuid                     1046
+#define __NR_geteuid                    1047
+#define __NR_ptrace                     1048
+#define __NR_access                     1049
+#define __NR_sync                       1050
+#define __NR_fsync                      1051
+#define __NR_fdatasync                  1052
+#define __NR_kill                       1053
+#define __NR_rename                     1054
+#define __NR_mkdir                      1055
+#define __NR_rmdir                      1056
+#define __NR_dup                        1057
+#define __NR_pipe                       1058
+#define __NR_times                      1059
+#define __NR_brk                        1060
+#define __NR_setgid                     1061
+#define __NR_getgid                     1062
+#define __NR_getegid                    1063
+#define __NR_acct                       1064
+#define __NR_ioctl                      1065
+#define __NR_fcntl                      1066
+#define __NR_umask                      1067
+#define __NR_chroot                     1068
+#define __NR_ustat                      1069
+#define __NR_dup2                       1070
+#define __NR_setreuid                   1071
+#define __NR_setregid                   1072
+#define __NR_getresuid                  1073
+#define __NR_setresuid                  1074
+#define __NR_getresgid                  1075
+#define __NR_setresgid                  1076
+#define __NR_getgroups                  1077
+#define __NR_setgroups                  1078
+#define __NR_getpgid                    1079
+#define __NR_setpgid                    1080
+#define __NR_setsid                     1081
+#define __NR_getsid                     1082
+#define __NR_sethostname                1083
+#define __NR_setrlimit                  1084
+#define __NR_getrlimit                  1085
+#define __NR_getrusage                  1086
+#define __NR_gettimeofday               1087
+#define __NR_settimeofday               1088
+#define __NR_select                     1089
+#define __NR_poll                       1090
+#define __NR_symlink                    1091
+#define __NR_readlink                   1092
+#define __NR_uselib                     1093
+#define __NR_swapon                     1094
+#define __NR_swapoff                    1095
+#define __NR_reboot                     1096
+#define __NR_truncate                   1097
+#define __NR_ftruncate                  1098
+#define __NR_fchmod                     1099
+#define __NR_fchown                     1100
+#define __NR_getpriority                1101
+#define __NR_setpriority                1102
+#define __NR_statfs                     1103
+#define __NR_fstatfs                    1104
+#define __NR_gettid                     1105
+#define __NR_semget                     1106
+#define __NR_semop                      1107
+#define __NR_semctl                     1108
+#define __NR_msgget                     1109
+#define __NR_msgsnd                     1110
+#define __NR_msgrcv                     1111
+#define __NR_msgctl                     1112
+#define __NR_shmget                     1113
+#define __NR_shmat                      1114
+#define __NR_shmdt                      1115
+#define __NR_shmctl                     1116
+/* also known as klogctl() in GNU libc: */
+#define __NR_syslog                     1117
+#define __NR_setitimer                  1118
+#define __NR_getitimer                  1119
+/* 1120 was __NR_old_stat */
+/* 1121 was __NR_old_lstat */
+/* 1122 was __NR_old_fstat */
+#define __NR_vhangup                    1123
+#define __NR_lchown                     1124
+#define __NR_remap_file_pages           1125
+#define __NR_wait4                      1126
+#define __NR_sysinfo                    1127
+#define __NR_clone                      1128
+#define __NR_setdomainname              1129
+#define __NR_uname                      1130
+#define __NR_adjtimex                   1131
+/* 1132 was __NR_create_module */
+#define __NR_init_module                1133
+#define __NR_delete_module              1134
+/* 1135 was __NR_get_kernel_syms */
+/* 1136 was __NR_query_module */
+#define __NR_quotactl                   1137
+#define __NR_bdflush                    1138
+#define __NR_sysfs                      1139
+#define __NR_personality                1140
+#define __NR_afs_syscall                1141
+#define __NR_setfsuid                   1142
+#define __NR_setfsgid                   1143
+#define __NR_getdents                   1144
+#define __NR_flock                      1145
+#define __NR_readv                      1146
+#define __NR_writev                     1147
+#define __NR_pread64                    1148
+#define __NR_pwrite64                   1149
+#define __NR__sysctl                    1150
+#define __NR_mmap                       1151
+#define __NR_munmap                     1152
+#define __NR_mlock                      1153
+#define __NR_mlockall                   1154
+#define __NR_mprotect                   1155
+#define __NR_mremap                     1156
+#define __NR_msync                      1157
+#define __NR_munlock                    1158
+#define __NR_munlockall                 1159
+#define __NR_sched_getparam             1160
+#define __NR_sched_setparam             1161
+#define __NR_sched_getscheduler         1162
+#define __NR_sched_setscheduler         1163
+#define __NR_sched_yield                1164
+#define __NR_sched_get_priority_max     1165
+#define __NR_sched_get_priority_min     1166
+#define __NR_sched_rr_get_interval      1167
+#define __NR_nanosleep                  1168
+#define __NR_nfsservctl                 1169
+#define __NR_prctl                      1170
+/* 1171 is reserved for backwards compatibility with old __NR_getpagesize */
+#define __NR_mmap2                      1172
+#define __NR_pciconfig_read             1173
+#define __NR_pciconfig_write            1174
+#define __NR_perfmonctl                 1175
+#define __NR_sigaltstack                1176
+#define __NR_rt_sigaction               1177
+#define __NR_rt_sigpending              1178
+#define __NR_rt_sigprocmask             1179
+#define __NR_rt_sigqueueinfo            1180
+#define __NR_rt_sigreturn               1181
+#define __NR_rt_sigsuspend              1182
+#define __NR_rt_sigtimedwait            1183
+#define __NR_getcwd                     1184
+#define __NR_capget                     1185
+#define __NR_capset                     1186
+#define __NR_sendfile                   1187
+#define __NR_getpmsg                    1188
+#define __NR_putpmsg                    1189
+#define __NR_socket                     1190
+#define __NR_bind                       1191
+#define __NR_connect                    1192
+#define __NR_listen                     1193
+#define __NR_accept                     1194
+#define __NR_getsockname                1195
+#define __NR_getpeername                1196
+#define __NR_socketpair                 1197
+#define __NR_send                       1198
+#define __NR_sendto                     1199
+#define __NR_recv                       1200
+#define __NR_recvfrom                   1201
+#define __NR_shutdown                   1202
+#define __NR_setsockopt                 1203
+#define __NR_getsockopt                 1204
+#define __NR_sendmsg                    1205
+#define __NR_recvmsg                    1206
+#define __NR_pivot_root                 1207
+#define __NR_mincore                    1208
+#define __NR_madvise                    1209
+#define __NR_stat                       1210
+#define __NR_lstat                      1211
+#define __NR_fstat                      1212
+#define __NR_clone2                     1213
+#define __NR_getdents64                 1214
+#define __NR_getunwind                  1215
+#define __NR_readahead                  1216
+#define __NR_setxattr                   1217
+#define __NR_lsetxattr                  1218
+#define __NR_fsetxattr                  1219
+#define __NR_getxattr                   1220
+#define __NR_lgetxattr                  1221
+#define __NR_fgetxattr                  1222
+#define __NR_listxattr                  1223
+#define __NR_llistxattr                 1224
+#define __NR_flistxattr                 1225
+#define __NR_removexattr                1226
+#define __NR_lremovexattr               1227
+#define __NR_fremovexattr               1228
+#define __NR_tkill                      1229
+#define __NR_futex                      1230
+#define __NR_sched_setaffinity          1231
+#define __NR_sched_getaffinity          1232
+#define __NR_set_tid_address            1233
+#define __NR_fadvise64                  1234
+#define __NR_tgkill                     1235
+#define __NR_exit_group                 1236
+#define __NR_lookup_dcookie             1237
+#define __NR_io_setup                   1238
+#define __NR_io_destroy                 1239
+#define __NR_io_getevents               1240
+#define __NR_io_submit                  1241
+#define __NR_io_cancel                  1242
+#define __NR_epoll_create               1243
+#define __NR_epoll_ctl                  1244
+#define __NR_epoll_wait                 1245
+#define __NR_restart_syscall            1246
+#define __NR_semtimedop                 1247
+#define __NR_timer_create               1248
+#define __NR_timer_settime              1249
+#define __NR_timer_gettime              1250
+#define __NR_timer_getoverrun           1251
+#define __NR_timer_delete               1252
+#define __NR_clock_settime              1253
+#define __NR_clock_gettime              1254
+#define __NR_clock_getres               1255
+#define __NR_clock_nanosleep            1256
+#define __NR_fstatfs64                  1257
+#define __NR_statfs64                   1258
+#define __NR_mbind                      1259
+#define __NR_get_mempolicy              1260
+#define __NR_set_mempolicy              1261
+#define __NR_mq_open                    1262
+#define __NR_mq_unlink                  1263
+#define __NR_mq_timedsend               1264
+#define __NR_mq_timedreceive            1265
+#define __NR_mq_notify                  1266
+#define __NR_mq_getsetattr              1267
+#define __NR_kexec_load                 1268
+#define __NR_vserver                    1269
+#define __NR_waitid                     1270
+#define __NR_add_key                    1271
+#define __NR_request_key                1272
+#define __NR_keyctl                     1273
+#define __NR_ioprio_set                 1274
+#define __NR_ioprio_get                 1275
+#define __NR_move_pages                 1276
+#define __NR_inotify_init               1277
+#define __NR_inotify_add_watch          1278
+#define __NR_inotify_rm_watch           1279
+#define __NR_migrate_pages              1280
+#define __NR_openat                     1281
+#define __NR_mkdirat                    1282
+#define __NR_mknodat                    1283
+#define __NR_fchownat                   1284
+#define __NR_futimesat                  1285
+#define __NR_newfstatat                 1286
+#define __NR_unlinkat                   1287
+#define __NR_renameat                   1288
+#define __NR_linkat                     1289
+#define __NR_symlinkat                  1290
+#define __NR_readlinkat                 1291
+#define __NR_fchmodat                   1292
+#define __NR_faccessat                  1293
+#define __NR_pselect6                   1294
+#define __NR_ppoll                      1295
+#define __NR_unshare                    1296
+#define __NR_splice                     1297
+#define __NR_set_robust_list            1298
+#define __NR_get_robust_list            1299
+#define __NR_sync_file_range            1300
+#define __NR_tee                        1301
+#define __NR_vmsplice                   1302
+#define __NR_fallocate                  1303
+#define __NR_getcpu                     1304
+#define __NR_epoll_pwait                1305
+#define __NR_utimensat                  1306
+#define __NR_signalfd                   1307
+#define __NR_timerfd                    1308
+#define __NR_eventfd                    1309
+#define __NR_timerfd_create             1310
+#define __NR_timerfd_settime            1311
+#define __NR_timerfd_gettime            1312
+#define __NR_signalfd4                  1313
+#define __NR_eventfd2                   1314
+#define __NR_epoll_create1              1315
+#define __NR_dup3                       1316
+#define __NR_pipe2                      1317
+#define __NR_inotify_init1              1318
+
+#ifdef __KERNEL__
+
+
+#define NR_syscalls                     295 /* length of syscall table */
+
+/*
+ * The following defines stop scripts/checksyscalls.sh from complaining about
+ * unimplemented system calls.  Glibc provides for each of these by using
+ * more modern equivalent system calls.
+ */
+#define __IGNORE_fork           /* clone() */
+#define __IGNORE_time           /* gettimeofday() */
+#define __IGNORE_alarm          /* setitimer(ITIMER_REAL, ... */
+#define __IGNORE_pause          /* rt_sigprocmask(), rt_sigsuspend() */
+#define __IGNORE_utime          /* utimes() */
+#define __IGNORE_getpgrp        /* getpgid() */
+#define __IGNORE_vfork          /* clone() */
+
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+
+#ifdef CONFIG_IA32_SUPPORT
+# define __ARCH_WANT_SYS_FADVISE64
+# define __ARCH_WANT_SYS_GETPGRP
+# define __ARCH_WANT_SYS_LLSEEK
+# define __ARCH_WANT_SYS_NICE
+# define __ARCH_WANT_SYS_OLD_GETRLIMIT
+# define __ARCH_WANT_SYS_OLDUMOUNT
+# define __ARCH_WANT_SYS_SIGPENDING
+# define __ARCH_WANT_SYS_SIGPROCMASK
+# define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
+# define __ARCH_WANT_COMPAT_SYS_TIME
+#endif
+
+#if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)
+
+#include <linux/types.h>
+#include <linux/linkage.h>
+#include <linux/compiler.h>
+
+extern long __ia64_syscall (long a0, long a1, long a2, long a3, long a4, long nr);
+
+asmlinkage unsigned long sys_mmap(
+                                unsigned long addr, unsigned long len,
+                                int prot, int flags,
+                                int fd, long off);
+asmlinkage unsigned long sys_mmap2(
+                                unsigned long addr, unsigned long len,
+                                int prot, int flags,
+                                int fd, long pgoff);
+struct pt_regs;
+struct sigaction;
+long sys_execve(char __user *filename, char __user * __user *argv,
+                           char __user * __user *envp, struct pt_regs *regs);
+asmlinkage long sys_pipe(void);
+asmlinkage long sys_rt_sigaction(int sig,
+                                 const struct sigaction __user *act,
+                                 struct sigaction __user *oact,
+                                 size_t sigsetsize);
+
+/*
+ * "Conditional" syscalls
+ *
+ * Note, this macro can only be used in the file which defines sys_ni_syscall, i.e., in
+ * kernel/sys_ni.c.  This version causes warnings because the declaration isn't a
+ * proper prototype, but we can't use __typeof__ either, because not all cond_syscall()
+ * declarations have prototypes at the moment.
+ */
+#define cond_syscall(x) asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
+
+#endif /* !__ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_IA64_UNISTD_H */
diff --git a/arch/ia64/include/asm/unwind.h b/arch/ia64/include/asm/unwind.h
new file mode 100644
index 000000000000..1af3875f1a57
--- /dev/null
+++ b/arch/ia64/include/asm/unwind.h
@@ -0,0 +1,233 @@
+#ifndef _ASM_IA64_UNWIND_H
+#define _ASM_IA64_UNWIND_H
+
+/*
+ * Copyright (C) 1999-2000, 2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * A simple API for unwinding kernel stacks.  This is used for
+ * debugging and error reporting purposes.  The kernel doesn't need
+ * full-blown stack unwinding with all the bells and whitles, so there
+ * is not much point in implementing the full IA-64 unwind API (though
+ * it would of course be possible to implement the kernel API on top
+ * of it).
+ */
+
+struct task_struct;     /* forward declaration */
+struct switch_stack;    /* forward declaration */
+
+enum unw_application_register {
+        UNW_AR_BSP,
+        UNW_AR_BSPSTORE,
+        UNW_AR_PFS,
+        UNW_AR_RNAT,
+        UNW_AR_UNAT,
+        UNW_AR_LC,
+        UNW_AR_EC,
+        UNW_AR_FPSR,
+        UNW_AR_RSC,
+        UNW_AR_CCV,
+        UNW_AR_CSD,
+        UNW_AR_SSD
+};
+
+/*
+ * The following declarations are private to the unwind
+ * implementation:
+ */
+
+struct unw_stack {
+        unsigned long limit;
+        unsigned long top;
+};
+
+#define UNW_FLAG_INTERRUPT_FRAME        (1UL << 0)
+
+/*
+ * No user of this module should every access this structure directly
+ * as it is subject to change.  It is declared here solely so we can
+ * use automatic variables.
+ */
+struct unw_frame_info {
+        struct unw_stack regstk;
+        struct unw_stack memstk;
+        unsigned int flags;
+        short hint;
+        short prev_script;
+
+        /* current frame info: */
+        unsigned long bsp;              /* backing store pointer value */
+        unsigned long sp;               /* stack pointer value */
+        unsigned long psp;              /* previous sp value */
+        unsigned long ip;               /* instruction pointer value */
+        unsigned long pr;               /* current predicate values */
+        unsigned long *cfm_loc;         /* cfm save location (or NULL) */
+        unsigned long pt;               /* struct pt_regs location */
+
+        struct task_struct *task;
+        struct switch_stack *sw;
+
+        /* preserved state: */
+        unsigned long *bsp_loc;         /* previous bsp save location */
+        unsigned long *bspstore_loc;
+        unsigned long *pfs_loc;
+        unsigned long *rnat_loc;
+        unsigned long *rp_loc;
+        unsigned long *pri_unat_loc;
+        unsigned long *unat_loc;
+        unsigned long *pr_loc;
+        unsigned long *lc_loc;
+        unsigned long *fpsr_loc;
+        struct unw_ireg {
+                unsigned long *loc;
+                struct unw_ireg_nat {
+                        unsigned long type : 3;         /* enum unw_nat_type */
+                        signed long off : 61;           /* NaT word is at loc+nat.off */
+                } nat;
+        } r4, r5, r6, r7;
+        unsigned long *b1_loc, *b2_loc, *b3_loc, *b4_loc, *b5_loc;
+        struct ia64_fpreg *f2_loc, *f3_loc, *f4_loc, *f5_loc, *fr_loc[16];
+};
+
+/*
+ * The official API follows below:
+ */
+
+struct unw_table_entry {
+        u64 start_offset;
+        u64 end_offset;
+        u64 info_offset;
+};
+
+/*
+ * Initialize unwind support.
+ */
+extern void unw_init (void);
+
+extern void *unw_add_unwind_table (const char *name, unsigned long segment_base, unsigned long gp,
+                                   const void *table_start, const void *table_end);
+
+extern void unw_remove_unwind_table (void *handle);
+
+/*
+ * Prepare to unwind blocked task t.
+ */
+extern void unw_init_from_blocked_task (struct unw_frame_info *info, struct task_struct *t);
+
+extern void unw_init_frame_info (struct unw_frame_info *info, struct task_struct *t,
+                                 struct switch_stack *sw);
+
+/*
+ * Prepare to unwind the currently running thread.
+ */
+extern void unw_init_running (void (*callback)(struct unw_frame_info *info, void *arg), void *arg);
+
+/*
+ * Unwind to previous to frame.  Returns 0 if successful, negative
+ * number in case of an error.
+ */
+extern int unw_unwind (struct unw_frame_info *info);
+
+/*
+ * Unwind until the return pointer is in user-land (or until an error
+ * occurs).  Returns 0 if successful, negative number in case of
+ * error.
+ */
+extern int unw_unwind_to_user (struct unw_frame_info *info);
+
+#define unw_is_intr_frame(info) (((info)->flags & UNW_FLAG_INTERRUPT_FRAME) != 0)
+
+static inline int
+unw_get_ip (struct unw_frame_info *info, unsigned long *valp)
+{
+        *valp = (info)->ip;
+        return 0;
+}
+
+static inline int
+unw_get_sp (struct unw_frame_info *info, unsigned long *valp)
+{
+        *valp = (info)->sp;
+        return 0;
+}
+
+static inline int
+unw_get_psp (struct unw_frame_info *info, unsigned long *valp)
+{
+        *valp = (info)->psp;
+        return 0;
+}
+
+static inline int
+unw_get_bsp (struct unw_frame_info *info, unsigned long *valp)
+{
+        *valp = (info)->bsp;
+        return 0;
+}
+
+static inline int
+unw_get_cfm (struct unw_frame_info *info, unsigned long *valp)
+{
+        *valp = *(info)->cfm_loc;
+        return 0;
+}
+
+static inline int
+unw_set_cfm (struct unw_frame_info *info, unsigned long val)
+{
+        *(info)->cfm_loc = val;
+        return 0;
+}
+
+static inline int
+unw_get_rp (struct unw_frame_info *info, unsigned long *val)
+{
+        if (!info->rp_loc)
+                return -1;
+        *val = *info->rp_loc;
+        return 0;
+}
+
+extern int unw_access_gr (struct unw_frame_info *, int, unsigned long *, char *, int);
+extern int unw_access_br (struct unw_frame_info *, int, unsigned long *, int);
+extern int unw_access_fr (struct unw_frame_info *, int, struct ia64_fpreg *, int);
+extern int unw_access_ar (struct unw_frame_info *, int, unsigned long *, int);
+extern int unw_access_pr (struct unw_frame_info *, unsigned long *, int);
+
+static inline int
+unw_set_gr (struct unw_frame_info *i, int n, unsigned long v, char nat)
+{
+        return unw_access_gr(i, n, &v, &nat, 1);
+}
+
+static inline int
+unw_set_br (struct unw_frame_info *i, int n, unsigned long v)
+{
+        return unw_access_br(i, n, &v, 1);
+}
+
+static inline int
+unw_set_fr (struct unw_frame_info *i, int n, struct ia64_fpreg v)
+{
+        return unw_access_fr(i, n, &v, 1);
+}
+
+static inline int
+unw_set_ar (struct unw_frame_info *i, int n, unsigned long v)
+{
+        return unw_access_ar(i, n, &v, 1);
+}
+
+static inline int
+unw_set_pr (struct unw_frame_info *i, unsigned long v)
+{
+        return unw_access_pr(i, &v, 1);
+}
+
+#define unw_get_gr(i,n,v,nat)   unw_access_gr(i,n,v,nat,0)
+#define unw_get_br(i,n,v)       unw_access_br(i,n,v,0)
+#define unw_get_fr(i,n,v)       unw_access_fr(i,n,v,0)
+#define unw_get_ar(i,n,v)       unw_access_ar(i,n,v,0)
+#define unw_get_pr(i,v)         unw_access_pr(i,v,0)
+
+#endif /* _ASM_UNWIND_H */
diff --git a/arch/ia64/include/asm/user.h b/arch/ia64/include/asm/user.h
new file mode 100644
index 000000000000..8b9821110348
--- /dev/null
+++ b/arch/ia64/include/asm/user.h
@@ -0,0 +1,58 @@
+#ifndef _ASM_IA64_USER_H
+#define _ASM_IA64_USER_H
+
+/*
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd).  The file contents are as
+ * follows:
+ *
+ *  upage: 1 page consisting of a user struct that tells gdb
+ *      what is present in the file.  Directly after this is a
+ *      copy of the task_struct, which is currently not used by gdb,
+ *      but it may come in handy at some point.  All of the registers
+ *      are stored as part of the upage.  The upage should always be
+ *      only one page long.
+ *  data: The data segment follows next.  We use current->end_text to
+ *      current->brk to pick up all of the user variables, plus any memory
+ *      that may have been sbrk'ed.  No attempt is made to determine if a
+ *      page is demand-zero or if a page is totally unused, we just cover
+ *      the entire range.  All of the addresses are rounded in such a way
+ *      that an integral number of pages is written.
+ *  stack: We need the stack information in order to get a meaningful
+ *      backtrace.  We need to write the data from usp to
+ *      current->start_stack, so we round each of these in order to be able
+ *      to write an integer number of pages.
+ *
+ * Modified 1998, 1999, 2001
+ *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
+ */
+
+#include <linux/ptrace.h>
+#include <linux/types.h>
+
+#include <asm/page.h>
+
+#define EF_SIZE         3072    /* XXX fix me */
+
+struct user {
+        unsigned long   regs[EF_SIZE/8+32];     /* integer and fp regs */
+        size_t          u_tsize;                /* text size (pages) */
+        size_t          u_dsize;                /* data size (pages) */
+        size_t          u_ssize;                /* stack size (pages) */
+        unsigned long   start_code;             /* text starting address */
+        unsigned long   start_data;             /* data starting address */
+        unsigned long   start_stack;            /* stack starting address */
+        long int        signal;                 /* signal causing core dump */
+        unsigned long   u_ar0;                  /* help gdb find registers */
+        unsigned long   magic;                  /* identifies a core file */
+        char            u_comm[32];             /* user command name */
+};
+
+#define NBPG                    PAGE_SIZE
+#define UPAGES                  1
+#define HOST_TEXT_START_ADDR    (u.start_code)
+#define HOST_DATA_START_ADDR    (u.start_data)
+#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _ASM_IA64_USER_H */
diff --git a/arch/ia64/include/asm/ustack.h b/arch/ia64/include/asm/ustack.h
new file mode 100644
index 000000000000..504167c35b8b
--- /dev/null
+++ b/arch/ia64/include/asm/ustack.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_IA64_USTACK_H
+#define _ASM_IA64_USTACK_H
+
+/*
+ * Constants for the user stack size
+ */
+
+#ifdef __KERNEL__
+#include <asm/page.h>
+
+/* The absolute hard limit for stack size is 1/2 of the mappable space in the region */
+#define MAX_USER_STACK_SIZE     (RGN_MAP_LIMIT/2)
+#define STACK_TOP               (0x6000000000000000UL + RGN_MAP_LIMIT)
+#define STACK_TOP_MAX           STACK_TOP
+#endif
+
+/* Make a default stack size of 2GiB */
+#define DEFAULT_USER_STACK_SIZE (1UL << 31)
+
+#endif /* _ASM_IA64_USTACK_H */
diff --git a/arch/ia64/include/asm/uv/uv_hub.h b/arch/ia64/include/asm/uv/uv_hub.h
new file mode 100644
index 000000000000..f607018af4a1
--- /dev/null
+++ b/arch/ia64/include/asm/uv/uv_hub.h
@@ -0,0 +1,309 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI UV architectural definitions
+ *
+ * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_IA64_UV_HUB_H__
+#define __ASM_IA64_UV_HUB_H__
+
+#include <linux/numa.h>
+#include <linux/percpu.h>
+#include <asm/types.h>
+#include <asm/percpu.h>
+
+
+/*
+ * Addressing Terminology
+ *
+ *      M       - The low M bits of a physical address represent the offset
+ *                into the blade local memory. RAM memory on a blade is physically
+ *                contiguous (although various IO spaces may punch holes in
+ *                it)..
+ *
+ *      N       - Number of bits in the node portion of a socket physical
+ *                address.
+ *
+ *      NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
+ *                routers always have low bit of 1, C/MBricks have low bit
+ *                equal to 0. Most addressing macros that target UV hub chips
+ *                right shift the NASID by 1 to exclude the always-zero bit.
+ *                NASIDs contain up to 15 bits.
+ *
+ *      GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
+ *                of nasids.
+ *
+ *      PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
+ *                of the nasid for socket usage.
+ *
+ *
+ *  NumaLink Global Physical Address Format:
+ *  +--------------------------------+---------------------+
+ *  |00..000|      GNODE             |      NodeOffset     |
+ *  +--------------------------------+---------------------+
+ *          |<-------53 - M bits --->|<--------M bits ----->
+ *
+ *      M - number of node offset bits (35 .. 40)
+ *
+ *
+ *  Memory/UV-HUB Processor Socket Address Format:
+ *  +----------------+---------------+---------------------+
+ *  |00..000000000000|   PNODE       |      NodeOffset     |
+ *  +----------------+---------------+---------------------+
+ *                   <--- N bits --->|<--------M bits ----->
+ *
+ *      M - number of node offset bits (35 .. 40)
+ *      N - number of PNODE bits (0 .. 10)
+ *
+ *              Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
+ *              The actual values are configuration dependent and are set at
+ *              boot time. M & N values are set by the hardware/BIOS at boot.
+ */
+
+
+/*
+ * Maximum number of bricks in all partitions and in all coherency domains.
+ * This is the total number of bricks accessible in the numalink fabric. It
+ * includes all C & M bricks. Routers are NOT included.
+ *
+ * This value is also the value of the maximum number of non-router NASIDs
+ * in the numalink fabric.
+ *
+ * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
+ */
+#define UV_MAX_NUMALINK_BLADES  16384
+
+/*
+ * Maximum number of C/Mbricks within a software SSI (hardware may support
+ * more).
+ */
+#define UV_MAX_SSI_BLADES       1
+
+/*
+ * The largest possible NASID of a C or M brick (+ 2)
+ */
+#define UV_MAX_NASID_VALUE      (UV_MAX_NUMALINK_NODES * 2)
+
+/*
+ * The following defines attributes of the HUB chip. These attributes are
+ * frequently referenced and are kept in the per-cpu data areas of each cpu.
+ * They are kept together in a struct to minimize cache misses.
+ */
+struct uv_hub_info_s {
+        unsigned long   global_mmr_base;
+        unsigned long   gpa_mask;
+        unsigned long   gnode_upper;
+        unsigned long   lowmem_remap_top;
+        unsigned long   lowmem_remap_base;
+        unsigned short  pnode;
+        unsigned short  pnode_mask;
+        unsigned short  coherency_domain_number;
+        unsigned short  numa_blade_id;
+        unsigned char   blade_processor_id;
+        unsigned char   m_val;
+        unsigned char   n_val;
+};
+DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
+#define uv_hub_info             (&__get_cpu_var(__uv_hub_info))
+#define uv_cpu_hub_info(cpu)    (&per_cpu(__uv_hub_info, cpu))
+
+/*
+ * Local & Global MMR space macros.
+ *      Note: macros are intended to be used ONLY by inline functions
+ *      in this file - not by other kernel code.
+ *              n -  NASID (full 15-bit global nasid)
+ *              g -  GNODE (full 15-bit global nasid, right shifted 1)
+ *              p -  PNODE (local part of nsids, right shifted 1)
+ */
+#define UV_NASID_TO_PNODE(n)            (((n) >> 1) & uv_hub_info->pnode_mask)
+#define UV_PNODE_TO_NASID(p)            (((p) << 1) | uv_hub_info->gnode_upper)
+
+#define UV_LOCAL_MMR_BASE               0xf4000000UL
+#define UV_GLOBAL_MMR32_BASE            0xf8000000UL
+#define UV_GLOBAL_MMR64_BASE            (uv_hub_info->global_mmr_base)
+
+#define UV_GLOBAL_MMR32_PNODE_SHIFT     15
+#define UV_GLOBAL_MMR64_PNODE_SHIFT     26
+
+#define UV_GLOBAL_MMR32_PNODE_BITS(p)   ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
+
+#define UV_GLOBAL_MMR64_PNODE_BITS(p)                                   \
+        ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
+
+/*
+ * Macros for converting between kernel virtual addresses, socket local physical
+ * addresses, and UV global physical addresses.
+ *      Note: use the standard __pa() & __va() macros for converting
+ *            between socket virtual and socket physical addresses.
+ */
+
+/* socket phys RAM --> UV global physical address */
+static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
+{
+        if (paddr < uv_hub_info->lowmem_remap_top)
+                paddr += uv_hub_info->lowmem_remap_base;
+        return paddr | uv_hub_info->gnode_upper;
+}
+
+
+/* socket virtual --> UV global physical address */
+static inline unsigned long uv_gpa(void *v)
+{
+        return __pa(v) | uv_hub_info->gnode_upper;
+}
+
+/* socket virtual --> UV global physical address */
+static inline void *uv_vgpa(void *v)
+{
+        return (void *)uv_gpa(v);
+}
+
+/* UV global physical address --> socket virtual */
+static inline void *uv_va(unsigned long gpa)
+{
+        return __va(gpa & uv_hub_info->gpa_mask);
+}
+
+/* pnode, offset --> socket virtual */
+static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
+{
+        return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
+}
+
+
+/*
+ * Access global MMRs using the low memory MMR32 space. This region supports
+ * faster MMR access but not all MMRs are accessible in this space.
+ */
+static inline unsigned long *uv_global_mmr32_address(int pnode,
+                                unsigned long offset)
+{
+        return __va(UV_GLOBAL_MMR32_BASE |
+                       UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
+}
+
+static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
+                                 unsigned long val)
+{
+        *uv_global_mmr32_address(pnode, offset) = val;
+}
+
+static inline unsigned long uv_read_global_mmr32(int pnode,
+                                                 unsigned long offset)
+{
+        return *uv_global_mmr32_address(pnode, offset);
+}
+
+/*
+ * Access Global MMR space using the MMR space located at the top of physical
+ * memory.
+ */
+static inline unsigned long *uv_global_mmr64_address(int pnode,
+                                unsigned long offset)
+{
+        return __va(UV_GLOBAL_MMR64_BASE |
+                    UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
+}
+
+static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
+                                unsigned long val)
+{
+        *uv_global_mmr64_address(pnode, offset) = val;
+}
+
+static inline unsigned long uv_read_global_mmr64(int pnode,
+                                                 unsigned long offset)
+{
+        return *uv_global_mmr64_address(pnode, offset);
+}
+
+/*
+ * Access hub local MMRs. Faster than using global space but only local MMRs
+ * are accessible.
+ */
+static inline unsigned long *uv_local_mmr_address(unsigned long offset)
+{
+        return __va(UV_LOCAL_MMR_BASE | offset);
+}
+
+static inline unsigned long uv_read_local_mmr(unsigned long offset)
+{
+        return *uv_local_mmr_address(offset);
+}
+
+static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
+{
+        *uv_local_mmr_address(offset) = val;
+}
+
+/*
+ * Structures and definitions for converting between cpu, node, pnode, and blade
+ * numbers.
+ */
+
+/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
+static inline int uv_blade_processor_id(void)
+{
+        return smp_processor_id();
+}
+
+/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
+static inline int uv_numa_blade_id(void)
+{
+        return 0;
+}
+
+/* Convert a cpu number to the the UV blade number */
+static inline int uv_cpu_to_blade_id(int cpu)
+{
+        return 0;
+}
+
+/* Convert linux node number to the UV blade number */
+static inline int uv_node_to_blade_id(int nid)
+{
+        return 0;
+}
+
+/* Convert a blade id to the PNODE of the blade */
+static inline int uv_blade_to_pnode(int bid)
+{
+        return 0;
+}
+
+/* Determine the number of possible cpus on a blade */
+static inline int uv_blade_nr_possible_cpus(int bid)
+{
+        return num_possible_cpus();
+}
+
+/* Determine the number of online cpus on a blade */
+static inline int uv_blade_nr_online_cpus(int bid)
+{
+        return num_online_cpus();
+}
+
+/* Convert a cpu id to the PNODE of the blade containing the cpu */
+static inline int uv_cpu_to_pnode(int cpu)
+{
+        return 0;
+}
+
+/* Convert a linux node number to the PNODE of the blade */
+static inline int uv_node_to_pnode(int nid)
+{
+        return 0;
+}
+
+/* Maximum possible number of blades */
+static inline int uv_num_possible_blades(void)
+{
+        return 1;
+}
+
+#endif /* __ASM_IA64_UV_HUB__ */
+
diff --git a/arch/ia64/include/asm/uv/uv_mmrs.h b/arch/ia64/include/asm/uv/uv_mmrs.h
new file mode 100644
index 000000000000..c149ef085437
--- /dev/null
+++ b/arch/ia64/include/asm/uv/uv_mmrs.h
@@ -0,0 +1,673 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI UV MMR definitions
+ *
+ * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_IA64_UV_MMRS__
+#define __ASM_IA64_UV_MMRS__
+
+#define UV_MMR_ENABLE           (1UL << 63)
+
+/* ========================================================================= */
+/*                           UVH_BAU_DATA_CONFIG                             */
+/* ========================================================================= */
+#define UVH_BAU_DATA_CONFIG 0x61680UL
+#define UVH_BAU_DATA_CONFIG_32 0x0438
+
+#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
+#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
+#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
+#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
+#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
+#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
+#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
+#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
+#define UVH_BAU_DATA_CONFIG_P_SHFT 13
+#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
+#define UVH_BAU_DATA_CONFIG_T_SHFT 15
+#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
+#define UVH_BAU_DATA_CONFIG_M_SHFT 16
+#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
+#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
+#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+
+union uvh_bau_data_config_u {
+    unsigned long       v;
+    struct uvh_bau_data_config_s {
+        unsigned long   vector_  :  8;  /* RW */
+        unsigned long   dm       :  3;  /* RW */
+        unsigned long   destmode :  1;  /* RW */
+        unsigned long   status   :  1;  /* RO */
+        unsigned long   p        :  1;  /* RO */
+        unsigned long   rsvd_14  :  1;  /*    */
+        unsigned long   t        :  1;  /* RO */
+        unsigned long   m        :  1;  /* RW */
+        unsigned long   rsvd_17_31: 15;  /*    */
+        unsigned long   apic_id  : 32;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                           UVH_EVENT_OCCURRED0                             */
+/* ========================================================================= */
+#define UVH_EVENT_OCCURRED0 0x70000UL
+#define UVH_EVENT_OCCURRED0_32 0x005e8
+
+#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
+#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
+#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
+#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
+#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
+#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
+#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
+#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
+#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
+#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
+#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
+#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
+#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
+#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
+#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
+#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
+#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
+#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
+#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
+#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
+#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
+#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
+#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
+#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
+#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
+#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
+#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
+#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
+#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
+#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
+#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
+#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
+#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
+#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
+#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
+#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
+#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
+#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
+#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
+#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
+#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
+#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
+#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
+#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
+#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
+#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
+#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
+#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
+#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
+#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
+#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
+#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
+#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
+#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
+#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
+#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
+#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
+#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
+#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
+#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
+#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
+#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
+#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
+#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
+#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
+#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
+#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
+#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
+#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
+#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
+#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
+#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
+#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
+#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
+#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
+#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
+#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
+union uvh_event_occurred0_u {
+    unsigned long       v;
+    struct uvh_event_occurred0_s {
+        unsigned long   lb_hcerr             :  1;  /* RW, W1C */
+        unsigned long   gr0_hcerr            :  1;  /* RW, W1C */
+        unsigned long   gr1_hcerr            :  1;  /* RW, W1C */
+        unsigned long   lh_hcerr             :  1;  /* RW, W1C */
+        unsigned long   rh_hcerr             :  1;  /* RW, W1C */
+        unsigned long   xn_hcerr             :  1;  /* RW, W1C */
+        unsigned long   si_hcerr             :  1;  /* RW, W1C */
+        unsigned long   lb_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   gr0_aoerr0           :  1;  /* RW, W1C */
+        unsigned long   gr1_aoerr0           :  1;  /* RW, W1C */
+        unsigned long   lh_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   rh_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   xn_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   si_aoerr0            :  1;  /* RW, W1C */
+        unsigned long   lb_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   gr0_aoerr1           :  1;  /* RW, W1C */
+        unsigned long   gr1_aoerr1           :  1;  /* RW, W1C */
+        unsigned long   lh_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   rh_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   xn_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   si_aoerr1            :  1;  /* RW, W1C */
+        unsigned long   rh_vpi_int           :  1;  /* RW, W1C */
+        unsigned long   system_shutdown_int  :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_0         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_1         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_2         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_3         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_4         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_5         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_6         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_7         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_8         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_9         :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_10        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_11        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_12        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_13        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_14        :  1;  /* RW, W1C */
+        unsigned long   lb_irq_int_15        :  1;  /* RW, W1C */
+        unsigned long   l1_nmi_int           :  1;  /* RW, W1C */
+        unsigned long   stop_clock           :  1;  /* RW, W1C */
+        unsigned long   asic_to_l1           :  1;  /* RW, W1C */
+        unsigned long   l1_to_asic           :  1;  /* RW, W1C */
+        unsigned long   ltc_int              :  1;  /* RW, W1C */
+        unsigned long   la_seq_trigger       :  1;  /* RW, W1C */
+        unsigned long   ipi_int              :  1;  /* RW, W1C */
+        unsigned long   extio_int0           :  1;  /* RW, W1C */
+        unsigned long   extio_int1           :  1;  /* RW, W1C */
+        unsigned long   extio_int2           :  1;  /* RW, W1C */
+        unsigned long   extio_int3           :  1;  /* RW, W1C */
+        unsigned long   profile_int          :  1;  /* RW, W1C */
+        unsigned long   rtc0                 :  1;  /* RW, W1C */
+        unsigned long   rtc1                 :  1;  /* RW, W1C */
+        unsigned long   rtc2                 :  1;  /* RW, W1C */
+        unsigned long   rtc3                 :  1;  /* RW, W1C */
+        unsigned long   bau_data             :  1;  /* RW, W1C */
+        unsigned long   power_management_req :  1;  /* RW, W1C */
+        unsigned long   rsvd_57_63           :  7;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                        UVH_EVENT_OCCURRED0_ALIAS                          */
+/* ========================================================================= */
+#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
+#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
+
+/* ========================================================================= */
+/*                               UVH_INT_CMPB                                */
+/* ========================================================================= */
+#define UVH_INT_CMPB 0x22080UL
+
+#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
+#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
+
+union uvh_int_cmpb_u {
+    unsigned long       v;
+    struct uvh_int_cmpb_s {
+        unsigned long   real_time_cmpb : 56;  /* RW */
+        unsigned long   rsvd_56_63     :  8;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                               UVH_INT_CMPC                                */
+/* ========================================================================= */
+#define UVH_INT_CMPC 0x22100UL
+
+#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
+#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
+
+union uvh_int_cmpc_u {
+    unsigned long       v;
+    struct uvh_int_cmpc_s {
+        unsigned long   real_time_cmpc : 56;  /* RW */
+        unsigned long   rsvd_56_63     :  8;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                               UVH_INT_CMPD                                */
+/* ========================================================================= */
+#define UVH_INT_CMPD 0x22180UL
+
+#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
+#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
+
+union uvh_int_cmpd_u {
+    unsigned long       v;
+    struct uvh_int_cmpd_s {
+        unsigned long   real_time_cmpd : 56;  /* RW */
+        unsigned long   rsvd_56_63     :  8;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                               UVH_NODE_ID                                 */
+/* ========================================================================= */
+#define UVH_NODE_ID 0x0UL
+
+#define UVH_NODE_ID_FORCE1_SHFT 0
+#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
+#define UVH_NODE_ID_MANUFACTURER_SHFT 1
+#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
+#define UVH_NODE_ID_PART_NUMBER_SHFT 12
+#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
+#define UVH_NODE_ID_REVISION_SHFT 28
+#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
+#define UVH_NODE_ID_NODE_ID_SHFT 32
+#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
+#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
+#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
+#define UVH_NODE_ID_NI_PORT_SHFT 56
+#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
+
+union uvh_node_id_u {
+    unsigned long       v;
+    struct uvh_node_id_s {
+        unsigned long   force1        :  1;  /* RO */
+        unsigned long   manufacturer  : 11;  /* RO */
+        unsigned long   part_number   : 16;  /* RO */
+        unsigned long   revision      :  4;  /* RO */
+        unsigned long   node_id       : 15;  /* RW */
+        unsigned long   rsvd_47       :  1;  /*    */
+        unsigned long   nodes_per_bit :  7;  /* RW */
+        unsigned long   rsvd_55       :  1;  /*    */
+        unsigned long   ni_port       :  4;  /* RO */
+        unsigned long   rsvd_60_63    :  4;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
+/* ========================================================================= */
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
+
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
+
+union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
+        unsigned long   rsvd_0_23 : 24;  /*    */
+        unsigned long   dest_base : 22;  /* RW */
+        unsigned long   rsvd_46_63: 18;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
+/* ========================================================================= */
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
+
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
+
+union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
+        unsigned long   rsvd_0_23 : 24;  /*    */
+        unsigned long   dest_base : 22;  /* RW */
+        unsigned long   rsvd_46_63: 18;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
+/* ========================================================================= */
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
+
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
+#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
+
+union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
+        unsigned long   rsvd_0_23 : 24;  /*    */
+        unsigned long   dest_base : 22;  /* RW */
+        unsigned long   rsvd_46_63: 18;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
+/* ========================================================================= */
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
+
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_rh_gam_gru_overlay_config_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_gru_overlay_config_mmr_s {
+        unsigned long   rsvd_0_27: 28;  /*    */
+        unsigned long   base   : 18;  /* RW */
+        unsigned long   rsvd_46_47:  2;  /*    */
+        unsigned long   gr4    :  1;  /* RW */
+        unsigned long   rsvd_49_51:  3;  /*    */
+        unsigned long   n_gru  :  4;  /* RW */
+        unsigned long   rsvd_56_62:  7;  /*    */
+        unsigned long   enable :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
+/* ========================================================================= */
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
+
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_rh_gam_mmr_overlay_config_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_mmr_overlay_config_mmr_s {
+        unsigned long   rsvd_0_25: 26;  /*    */
+        unsigned long   base     : 20;  /* RW */
+        unsigned long   dual_hub :  1;  /* RW */
+        unsigned long   rsvd_47_62: 16;  /*    */
+        unsigned long   enable   :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                                 UVH_RTC                                   */
+/* ========================================================================= */
+#define UVH_RTC 0x340000UL
+
+#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
+#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
+
+union uvh_rtc_u {
+    unsigned long       v;
+    struct uvh_rtc_s {
+        unsigned long   real_time_clock : 56;  /* RW */
+        unsigned long   rsvd_56_63      :  8;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                           UVH_RTC1_INT_CONFIG                             */
+/* ========================================================================= */
+#define UVH_RTC1_INT_CONFIG 0x615c0UL
+
+#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
+#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
+#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
+#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
+#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
+#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
+#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
+#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
+#define UVH_RTC1_INT_CONFIG_P_SHFT 13
+#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
+#define UVH_RTC1_INT_CONFIG_T_SHFT 15
+#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
+#define UVH_RTC1_INT_CONFIG_M_SHFT 16
+#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
+#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
+#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+
+union uvh_rtc1_int_config_u {
+    unsigned long       v;
+    struct uvh_rtc1_int_config_s {
+        unsigned long   vector_  :  8;  /* RW */
+        unsigned long   dm       :  3;  /* RW */
+        unsigned long   destmode :  1;  /* RW */
+        unsigned long   status   :  1;  /* RO */
+        unsigned long   p        :  1;  /* RO */
+        unsigned long   rsvd_14  :  1;  /*    */
+        unsigned long   t        :  1;  /* RO */
+        unsigned long   m        :  1;  /* RW */
+        unsigned long   rsvd_17_31: 15;  /*    */
+        unsigned long   apic_id  : 32;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                           UVH_RTC2_INT_CONFIG                             */
+/* ========================================================================= */
+#define UVH_RTC2_INT_CONFIG 0x61600UL
+
+#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
+#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
+#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
+#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
+#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
+#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
+#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
+#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
+#define UVH_RTC2_INT_CONFIG_P_SHFT 13
+#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
+#define UVH_RTC2_INT_CONFIG_T_SHFT 15
+#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
+#define UVH_RTC2_INT_CONFIG_M_SHFT 16
+#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
+#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
+#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+
+union uvh_rtc2_int_config_u {
+    unsigned long       v;
+    struct uvh_rtc2_int_config_s {
+        unsigned long   vector_  :  8;  /* RW */
+        unsigned long   dm       :  3;  /* RW */
+        unsigned long   destmode :  1;  /* RW */
+        unsigned long   status   :  1;  /* RO */
+        unsigned long   p        :  1;  /* RO */
+        unsigned long   rsvd_14  :  1;  /*    */
+        unsigned long   t        :  1;  /* RO */
+        unsigned long   m        :  1;  /* RW */
+        unsigned long   rsvd_17_31: 15;  /*    */
+        unsigned long   apic_id  : 32;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                           UVH_RTC3_INT_CONFIG                             */
+/* ========================================================================= */
+#define UVH_RTC3_INT_CONFIG 0x61640UL
+
+#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
+#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
+#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
+#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
+#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
+#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
+#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
+#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
+#define UVH_RTC3_INT_CONFIG_P_SHFT 13
+#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
+#define UVH_RTC3_INT_CONFIG_T_SHFT 15
+#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
+#define UVH_RTC3_INT_CONFIG_M_SHFT 16
+#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
+#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
+#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
+
+union uvh_rtc3_int_config_u {
+    unsigned long       v;
+    struct uvh_rtc3_int_config_s {
+        unsigned long   vector_  :  8;  /* RW */
+        unsigned long   dm       :  3;  /* RW */
+        unsigned long   destmode :  1;  /* RW */
+        unsigned long   status   :  1;  /* RO */
+        unsigned long   p        :  1;  /* RO */
+        unsigned long   rsvd_14  :  1;  /*    */
+        unsigned long   t        :  1;  /* RO */
+        unsigned long   m        :  1;  /* RW */
+        unsigned long   rsvd_17_31: 15;  /*    */
+        unsigned long   apic_id  : 32;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                            UVH_RTC_INC_RATIO                              */
+/* ========================================================================= */
+#define UVH_RTC_INC_RATIO 0x350000UL
+
+#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
+#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
+#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
+#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
+
+union uvh_rtc_inc_ratio_u {
+    unsigned long       v;
+    struct uvh_rtc_inc_ratio_s {
+        unsigned long   fraction : 20;  /* RW */
+        unsigned long   ratio    :  3;  /* RW */
+        unsigned long   rsvd_23_63: 41;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                          UVH_SI_ADDR_MAP_CONFIG                           */
+/* ========================================================================= */
+#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
+
+#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
+#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
+#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
+#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
+
+union uvh_si_addr_map_config_u {
+    unsigned long       v;
+    struct uvh_si_addr_map_config_s {
+        unsigned long   m_skt :  6;  /* RW */
+        unsigned long   rsvd_6_7:  2;  /*    */
+        unsigned long   n_skt :  4;  /* RW */
+        unsigned long   rsvd_12_63: 52;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
+/*                       UVH_SI_ALIAS0_OVERLAY_CONFIG                        */
+/* ========================================================================= */
+#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
+
+#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
+#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
+#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
+#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
+#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
+#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_si_alias0_overlay_config_u {
+    unsigned long       v;
+    struct uvh_si_alias0_overlay_config_s {
+        unsigned long   rsvd_0_23: 24;  /*    */
+        unsigned long   base    :  8;  /* RW */
+        unsigned long   rsvd_32_47: 16;  /*    */
+        unsigned long   m_alias :  5;  /* RW */
+        unsigned long   rsvd_53_62: 10;  /*    */
+        unsigned long   enable  :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                       UVH_SI_ALIAS1_OVERLAY_CONFIG                        */
+/* ========================================================================= */
+#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
+
+#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
+#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
+#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
+#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
+#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
+#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_si_alias1_overlay_config_u {
+    unsigned long       v;
+    struct uvh_si_alias1_overlay_config_s {
+        unsigned long   rsvd_0_23: 24;  /*    */
+        unsigned long   base    :  8;  /* RW */
+        unsigned long   rsvd_32_47: 16;  /*    */
+        unsigned long   m_alias :  5;  /* RW */
+        unsigned long   rsvd_53_62: 10;  /*    */
+        unsigned long   enable  :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                       UVH_SI_ALIAS2_OVERLAY_CONFIG                        */
+/* ========================================================================= */
+#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
+
+#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
+#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
+#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
+#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
+#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
+#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_si_alias2_overlay_config_u {
+    unsigned long       v;
+    struct uvh_si_alias2_overlay_config_s {
+        unsigned long   rsvd_0_23: 24;  /*    */
+        unsigned long   base    :  8;  /* RW */
+        unsigned long   rsvd_32_47: 16;  /*    */
+        unsigned long   m_alias :  5;  /* RW */
+        unsigned long   rsvd_53_62: 10;  /*    */
+        unsigned long   enable  :  1;  /* RW */
+    } s;
+};
+
+
+#endif /* __ASM_IA64_UV_MMRS__ */
diff --git a/arch/ia64/include/asm/vga.h b/arch/ia64/include/asm/vga.h
new file mode 100644
index 000000000000..02184ecd8208
--- /dev/null
+++ b/arch/ia64/include/asm/vga.h
@@ -0,0 +1,25 @@
+/*
+ *      Access to VGA videoram
+ *
+ *      (c) 1998 Martin Mares <mj@ucw.cz>
+ *      (c) 1999 Asit Mallick <asit.k.mallick@intel.com>
+ *      (c) 1999 Don Dugger <don.dugger@intel.com>
+ */
+
+#ifndef __ASM_IA64_VGA_H_
+#define __ASM_IA64_VGA_H_
+
+/*
+ * On the PC, we can just recalculate addresses and then access the
+ * videoram directly without any black magic.
+ */
+
+extern unsigned long vga_console_iobase;
+extern unsigned long vga_console_membase;
+
+#define VGA_MAP_MEM(x,s)        ((unsigned long) ioremap_nocache(vga_console_membase + (x), s))
+
+#define vga_readb(x)    (*(x))
+#define vga_writeb(x,y) (*(y) = (x))
+
+#endif /* __ASM_IA64_VGA_H_ */
diff --git a/arch/ia64/include/asm/xor.h b/arch/ia64/include/asm/xor.h
new file mode 100644
index 000000000000..a349e23dea15
--- /dev/null
+++ b/arch/ia64/include/asm/xor.h
@@ -0,0 +1,31 @@
+/*
+ * Optimized RAID-5 checksumming functions for IA-64.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * (for example /usr/src/linux/COPYING); if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+extern void xor_ia64_2(unsigned long, unsigned long *, unsigned long *);
+extern void xor_ia64_3(unsigned long, unsigned long *, unsigned long *,
+                       unsigned long *);
+extern void xor_ia64_4(unsigned long, unsigned long *, unsigned long *,
+                       unsigned long *, unsigned long *);
+extern void xor_ia64_5(unsigned long, unsigned long *, unsigned long *,
+                       unsigned long *, unsigned long *, unsigned long *);
+
+static struct xor_block_template xor_block_ia64 = {
+        .name = "ia64",
+        .do_2 = xor_ia64_2,
+        .do_3 = xor_ia64_3,
+        .do_4 = xor_ia64_4,
+        .do_5 = xor_ia64_5,
+};
+
+#define XOR_TRY_TEMPLATES       xor_speed(&xor_block_ia64)
diff --git a/arch/ia64/kernel/asm-offsets.c b/arch/ia64/kernel/asm-offsets.c
index c64a55af9b95..94c44b1ccfd0 100644
--- a/arch/ia64/kernel/asm-offsets.c
+++ b/arch/ia64/kernel/asm-offsets.c
@@ -10,11 +10,11 @@
 #include <linux/pid.h>
 #include <linux/clocksource.h>
 #include <linux/kbuild.h>
-#include <asm-ia64/processor.h>
-#include <asm-ia64/ptrace.h>
-#include <asm-ia64/siginfo.h>
-#include <asm-ia64/sigcontext.h>
-#include <asm-ia64/mca.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/siginfo.h>
+#include <asm/sigcontext.h>
+#include <asm/mca.h>
 
 #include "../kernel/sigframe.h"
 #include "../kernel/fsyscall_gtod_data.h"
diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
index db540e58c783..41c712917ff7 100644
--- a/arch/ia64/kernel/head.S
+++ b/arch/ia64/kernel/head.S
@@ -1123,7 +1123,7 @@ SET_REG(b5);
          *   p15    - used to track flag status.
          *
          * If you patch this code to use more registers, do not forget to update
-         * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
+         * the clobber lists for spin_lock() in arch/ia64/include/asm/spinlock.h.
          */
 
 #if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index 3bc2fa64f87f..5c4674ae8aea 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -69,7 +69,7 @@
  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  *     platform can implement platform_irq_to_vector(irq) and
  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
- *     Please see also include/asm-ia64/hw_irq.h for those APIs.
+ *     Please see also arch/ia64/include/asm/hw_irq.h for those APIs.
  *
  * To sum up, there are three levels of mappings involved:
  *
diff --git a/arch/ia64/kernel/jprobes.S b/arch/ia64/kernel/jprobes.S
index 621630256c4a..f69389c7be1d 100644
--- a/arch/ia64/kernel/jprobes.S
+++ b/arch/ia64/kernel/jprobes.S
@@ -45,7 +45,7 @@
  * to the correct location.
  */
 #include <asm/asmmacro.h>
-#include <asm-ia64/break.h>
+#include <asm/break.h>
 
         /*
          * void jprobe_break(void)
diff --git a/arch/ia64/kernel/nr-irqs.c b/arch/ia64/kernel/nr-irqs.c
index 1ae049181e83..8273afc32db8 100644
--- a/arch/ia64/kernel/nr-irqs.c
+++ b/arch/ia64/kernel/nr-irqs.c
@@ -9,7 +9,7 @@
 
 #include <linux/kbuild.h>
 #include <linux/threads.h>
-#include <asm-ia64/native/irq.h>
+#include <asm/native/irq.h>
 
 void foo(void)
 {
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index e5c2de9b29a5..593279f33e96 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -314,7 +314,7 @@ static inline void __init setup_crashkernel(unsigned long total, int *n)
  *
  * Setup the reserved memory areas set aside for the boot parameters,
  * initrd, etc.  There are currently %IA64_MAX_RSVD_REGIONS defined,
- * see include/asm-ia64/meminit.h if you need to define more.
+ * see arch/ia64/include/asm/meminit.h if you need to define more.
  */
 void __init
 reserve_memory (void)
diff --git a/arch/ia64/mm/hugetlbpage.c b/arch/ia64/mm/hugetlbpage.c
index c45fc7f5a979..b0f615759e97 100644
--- a/arch/ia64/mm/hugetlbpage.c
+++ b/arch/ia64/mm/hugetlbpage.c
@@ -13,6 +13,7 @@
 #include <linux/mm.h>
 #include <linux/hugetlb.h>
 #include <linux/pagemap.h>
+#include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/sysctl.h>
 #include <linux/log2.h>
@@ -21,7 +22,8 @@
 #include <asm/tlb.h>
 #include <asm/tlbflush.h>
 
-unsigned int hpage_shift=HPAGE_SHIFT_DEFAULT;
+unsigned int hpage_shift = HPAGE_SHIFT_DEFAULT;
+EXPORT_SYMBOL(hpage_shift);
 
 pte_t *
 huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
diff --git a/arch/ia64/sn/kernel/iomv.c b/arch/ia64/sn/kernel/iomv.c
index ab7e2fd40798..c77ebdf98119 100644
--- a/arch/ia64/sn/kernel/iomv.c
+++ b/arch/ia64/sn/kernel/iomv.c
@@ -63,7 +63,7 @@ EXPORT_SYMBOL(sn_io_addr);
 /**
  * __sn_mmiowb - I/O space memory barrier
  *
- * See include/asm-ia64/io.h and Documentation/DocBook/deviceiobook.tmpl
+ * See arch/ia64/include/asm/io.h and Documentation/DocBook/deviceiobook.tmpl
  * for details.
  *
  * On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear.
diff --git a/arch/m68k/mac/baboon.c b/arch/m68k/mac/baboon.c
index dae9c982aa89..c7b25b0aacff 100644
--- a/arch/m68k/mac/baboon.c
+++ b/arch/m68k/mac/baboon.c
@@ -11,7 +11,6 @@
 #include <linux/mm.h>
 #include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/ide.h>
 
 #include <asm/traps.h>
 #include <asm/bootinfo.h>
diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c
index f3b27d04a31f..1bdb03c73c0f 100644
--- a/arch/m68k/mac/via.c
+++ b/arch/m68k/mac/via.c
@@ -27,7 +27,6 @@
 #include <linux/mm.h>
 #include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/ide.h>
 #include <linux/module.h>
 
 #include <asm/bootinfo.h>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b4c4eaa5dd26..4da736e25333 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3,6 +3,7 @@ config MIPS
         default y
         select HAVE_IDE
         select HAVE_OPROFILE
+        select HAVE_ARCH_KGDB
         # Horrible source of confusion.  Die, die, die ...
         select EMBEDDED
         select RTC_LIB
@@ -34,7 +35,6 @@ config BASLER_EXCITE
         select SYS_HAS_CPU_RM9000
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_KGDB
         help
           The eXcite is a smart camera platform manufactured by
           Basler Vision Technologies AG.
@@ -280,7 +280,6 @@ config PMC_MSP
         select SYS_HAS_CPU_MIPS32_R2
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_KGDB
         select IRQ_CPU
         select SERIAL_8250
         select SERIAL_8250_CONSOLE
@@ -306,7 +305,6 @@ config PMC_YOSEMITE
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
-        select SYS_SUPPORTS_KGDB
         select SYS_SUPPORTS_SMP
         help
           Yosemite is an evaluation board for the RM9000x2 processor
@@ -359,7 +357,6 @@ config SGI_IP27
         select SYS_HAS_CPU_R10000
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_KGDB
         select SYS_SUPPORTS_NUMA
         select SYS_SUPPORTS_SMP
         select GENERIC_HARDIRQS_NO__DO_IRQ
@@ -475,7 +472,6 @@ config SIBYTE_SWARM
         select SYS_HAS_CPU_SB1
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
-        select SYS_SUPPORTS_KGDB
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select ZONE_DMA32 if 64BIT
 
@@ -868,7 +864,6 @@ config SOC_PNX8550
         select SYS_HAS_EARLY_PRINTK
         select SYS_SUPPORTS_32BIT_KERNEL
         select GENERIC_HARDIRQS_NO__DO_IRQ
-        select SYS_SUPPORTS_KGDB
         select GENERIC_GPIO
 
 config SWAP_IO_SPACE
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index f18cf92650e3..765c8e287d2b 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -34,28 +34,6 @@ config SMTC_IDLE_HOOK_DEBUG
           arch/mips/kernel/smtc.c.  This debugging option result in significant
           overhead so should be disabled in production kernels.
 
-config KGDB
-        bool "Remote GDB kernel debugging"
-        depends on DEBUG_KERNEL && SYS_SUPPORTS_KGDB
-        select DEBUG_INFO
-        help
-          If you say Y here, it will be possible to remotely debug the MIPS
-          kernel using gdb. This enlarges your kernel image disk size by
-          several megabytes and requires a machine with more than 16 MB,
-          better 32 MB RAM to avoid excessive linking time. This is only
-          useful for kernel hackers. If unsure, say N.
-
-config SYS_SUPPORTS_KGDB
-        bool
-
-config GDB_CONSOLE
-        bool "Console output to GDB"
-        depends on KGDB
-        help
-          If you are using GDB for remote debugging over a serial port and
-          would like kernel messages to be formatted into GDB $O packets so
-          that GDB prints them as program output, say 'Y'.
-
 config SB1XXX_CORELIS
         bool "Corelis Debugger"
         depends on SIBYTE_SB1xxx_SOC
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
index 1fe97cccead1..e4a057d80ab6 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/au1000/Kconfig
@@ -134,4 +134,3 @@ config SOC_AU1X00
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_APM_EMULATION
-        select SYS_SUPPORTS_KGDB
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile
index dd0e19dacfcf..df48fd65bbf3 100644
--- a/arch/mips/au1000/common/Makefile
+++ b/arch/mips/au1000/common/Makefile
@@ -9,7 +9,6 @@ obj-y += prom.o irq.o puts.o time.o reset.o \
         au1xxx_irqmap.o clocks.o platform.o power.o setup.o \
         sleeper.o cputable.o dma.o dbdma.o gpio.o
 
-obj-$(CONFIG_KGDB)              += dbg_io.o
 obj-$(CONFIG_PCI)               += pci.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
deleted file mode 100644
index af5be7df2f2a..000000000000
--- a/arch/mips/au1000/common/dbg_io.c
+++ /dev/null
@@ -1,109 +0,0 @@
-#include <linux/types.h>
-
-#include <asm/mach-au1x00/au1000.h>
-
-#ifdef CONFIG_KGDB
-
-/*
- * FIXME the user should be able to select the
- * uart to be used for debugging.
- */
-#define DEBUG_BASE  UART_DEBUG_BASE
-
-#define         UART16550_BAUD_2400             2400
-#define         UART16550_BAUD_4800             4800
-#define         UART16550_BAUD_9600             9600
-#define         UART16550_BAUD_19200            19200
-#define         UART16550_BAUD_38400            38400
-#define         UART16550_BAUD_57600            57600
-#define         UART16550_BAUD_115200           115200
-
-#define         UART16550_PARITY_NONE           0
-#define         UART16550_PARITY_ODD            0x08
-#define         UART16550_PARITY_EVEN           0x18
-#define         UART16550_PARITY_MARK           0x28
-#define         UART16550_PARITY_SPACE          0x38
-
-#define         UART16550_DATA_5BIT             0x0
-#define         UART16550_DATA_6BIT             0x1
-#define         UART16550_DATA_7BIT             0x2
-#define         UART16550_DATA_8BIT             0x3
-
-#define         UART16550_STOP_1BIT             0x0
-#define         UART16550_STOP_2BIT             0x4
-
-
-#define UART_RX         0       /* Receive buffer */
-#define UART_TX         4       /* Transmit buffer */
-#define UART_IER        8       /* Interrupt Enable Register */
-#define UART_IIR        0xC     /* Interrupt ID Register */
-#define UART_FCR        0x10    /* FIFO Control Register */
-#define UART_LCR        0x14    /* Line Control Register */
-#define UART_MCR        0x18    /* Modem Control Register */
-#define UART_LSR        0x1C    /* Line Status Register */
-#define UART_MSR        0x20    /* Modem Status Register */
-#define UART_CLK        0x28    /* Baud Rat4e Clock Divider */
-#define UART_MOD_CNTRL  0x100   /* Module Control */
-
-/* memory-mapped read/write of the port */
-#define UART16550_READ(y)     (au_readl(DEBUG_BASE + y) & 0xff)
-#define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y))
-
-extern unsigned long calc_clock(void);
-
-void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
-{
-        if (UART16550_READ(UART_MOD_CNTRL) != 0x3)
-                UART16550_WRITE(UART_MOD_CNTRL, 3);
-        calc_clock();
-
-        /* disable interrupts */
-        UART16550_WRITE(UART_IER, 0);
-
-        /* set up baud rate */
-        {
-                u32 divisor;
-
-                /* set divisor */
-                divisor = get_au1x00_uart_baud_base() / baud;
-                UART16550_WRITE(UART_CLK, divisor & 0xffff);
-        }
-
-        /* set data format */
-        UART16550_WRITE(UART_LCR, (data | parity | stop));
-}
-
-static int remoteDebugInitialized;
-
-u8 getDebugChar(void)
-{
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(UART16550_BAUD_115200,
-                          UART16550_DATA_8BIT,
-                          UART16550_PARITY_NONE,
-                          UART16550_STOP_1BIT);
-        }
-
-        while ((UART16550_READ(UART_LSR) & 0x1) == 0);
-        return UART16550_READ(UART_RX);
-}
-
-
-int putDebugChar(u8 byte)
-{
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(UART16550_BAUD_115200,
-                          UART16550_DATA_8BIT,
-                          UART16550_PARITY_NONE,
-                          UART16550_STOP_1BIT);
-        }
-
-        while ((UART16550_READ(UART_LSR) & 0x40) == 0);
-        UART16550_WRITE(UART_TX, byte);
-
-        return 1;
-}
-
-#endif
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index 5ebe0de5e459..847413514964 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -57,6 +57,6 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x04000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c
index 33a4aebe0cba..3bae13c28954 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/au1000/mtx-1/init.c
@@ -55,6 +55,6 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x04000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c
index 3837365d613d..8a9c7d57208d 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/au1000/pb1000/init.c
@@ -52,6 +52,6 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x04000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/au1000/pb1100/init.c
index 8355483f3de2..7c6792308bc5 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/au1000/pb1100/init.c
@@ -54,7 +54,7 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x04000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
 
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
index 09fd63b86062..e9b2a0fd48ae 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/au1000/pb1200/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x08000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/au1000/pb1500/init.c
index 49f51e165863..3b6e395cf952 100644
--- a/arch/mips/au1000/pb1500/init.c
+++ b/arch/mips/au1000/pb1500/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x04000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/au1000/pb1550/init.c
index 1b5f58434bb7..e1055a13a1a0 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/au1000/pb1550/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x08000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c
index b849bf501c04..7516434760a1 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/au1000/xxs1500/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
         if (!memsize_str)
                 memsize = 0x04000000;
         else
-                memsize = strict_strtol(memsize_str, 0, NULL);
+                strict_strtol(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
index 519142c2e4ef..cff29cf46d03 100644
--- a/arch/mips/basler/excite/Makefile
+++ b/arch/mips/basler/excite/Makefile
@@ -5,5 +5,4 @@
 obj-$(CONFIG_BASLER_EXCITE)     += excite_irq.o excite_prom.o excite_setup.o \
                                    excite_device.o excite_procfs.o
 
-obj-$(CONFIG_KGDB)              += excite_dbg_io.o
 obj-m                           += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c
deleted file mode 100644
index d289e3a868cf..000000000000
--- a/arch/mips/basler/excite/excite_dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <asm/gdb-stub.h>
-#include <asm/rm9k-ocd.h>
-#include <excite.h>
-
-#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
-#error Debug port used by serial driver
-#endif
-
-#define UART_CLK                25000000
-#define BASE_BAUD               (UART_CLK / 16)
-#define REGISTER_BASE_0         0x0208UL
-#define REGISTER_BASE_1         0x0238UL
-
-#define REGISTER_BASE_DBG       REGISTER_BASE_1
-
-#define CPRR    0x0004
-#define UACFG   0x0200
-#define UAINTS  0x0204
-#define UARBR   (REGISTER_BASE_DBG + 0x0000)
-#define UATHR   (REGISTER_BASE_DBG + 0x0004)
-#define UADLL   (REGISTER_BASE_DBG + 0x0008)
-#define UAIER   (REGISTER_BASE_DBG + 0x000c)
-#define UADLH   (REGISTER_BASE_DBG + 0x0010)
-#define UAIIR   (REGISTER_BASE_DBG + 0x0014)
-#define UAFCR   (REGISTER_BASE_DBG + 0x0018)
-#define UALCR   (REGISTER_BASE_DBG + 0x001c)
-#define UAMCR   (REGISTER_BASE_DBG + 0x0020)
-#define UALSR   (REGISTER_BASE_DBG + 0x0024)
-#define UAMSR   (REGISTER_BASE_DBG + 0x0028)
-#define UASCR   (REGISTER_BASE_DBG + 0x002c)
-
-#define PARITY_NONE     0
-#define PARITY_ODD      0x08
-#define PARITY_EVEN     0x18
-#define PARITY_MARK     0x28
-#define PARITY_SPACE    0x38
-
-#define DATA_5BIT       0x0
-#define DATA_6BIT       0x1
-#define DATA_7BIT       0x2
-#define DATA_8BIT       0x3
-
-#define STOP_1BIT       0x0
-#define STOP_2BIT       0x4
-
-#define BAUD_DBG        57600
-#define PARITY_DBG      PARITY_NONE
-#define DATA_DBG        DATA_8BIT
-#define STOP_DBG        STOP_1BIT
-
-/* Initialize the serial port for KGDB debugging */
-void __init excite_kgdb_init(void)
-{
-        const u32 divisor = BASE_BAUD / BAUD_DBG;
-
-        /* Take the UART out of reset */
-        titan_writel(0x00ff1cff, CPRR);
-        titan_writel(0x00000000, UACFG);
-        titan_writel(0x00000002, UACFG);
-
-        titan_writel(0x0, UALCR);
-        titan_writel(0x0, UAIER);
-
-        /* Disable FIFOs */
-        titan_writel(0x00, UAFCR);
-
-        titan_writel(0x80, UALCR);
-        titan_writel(divisor & 0xff, UADLL);
-        titan_writel((divisor & 0xff00) >> 8, UADLH);
-        titan_writel(0x0, UALCR);
-
-        titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
-
-        /* Enable receiver interrupt */
-        titan_readl(UARBR);
-        titan_writel(0x1, UAIER);
-}
-
-int getDebugChar(void)
-{
-        while (!(titan_readl(UALSR) & 0x1));
-        return titan_readl(UARBR);
-}
-
-int putDebugChar(int data)
-{
-        while (!(titan_readl(UALSR) & 0x20));
-        titan_writel(data, UATHR);
-        return 1;
-}
-
-/* KGDB interrupt handler */
-asmlinkage void excite_kgdb_inthdl(void)
-{
-        if (unlikely(
-                ((titan_readl(UAIIR) & 0x7) == 4)
-                && ((titan_readl(UARBR) & 0xff) == 0x3)))
-                        set_async_breakpoint(&regs->cp0_epc);
-}
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
index 4903e067916b..934e0a6b1011 100644
--- a/arch/mips/basler/excite/excite_irq.c
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -50,10 +50,6 @@ void __init arch_init_irq(void)
         mips_cpu_irq_init();
         rm7k_cpu_irq_init();
         rm9k_cpu_irq_init();
-
-#ifdef CONFIG_KGDB
-        excite_kgdb_init();
-#endif
 }
 
 asmlinkage void plat_irq_dispatch(void)
@@ -90,9 +86,6 @@ asmlinkage void plat_irq_dispatch(void)
         msgint      = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
         if ((pending & (1 << TITAN_IRQ)) && msgint) {
                 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
-#if defined(CONFIG_KGDB)
-                excite_kgdb_inthdl();
-#endif
                 do_IRQ(TITAN_IRQ);
                 return;
         }
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
index 6dd8f0d46d09..d66b3b8edf2a 100644
--- a/arch/mips/basler/excite/excite_setup.c
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -95,13 +95,13 @@ static int __init excite_init_console(void)
         /* Take the DUART out of reset */
         titan_writel(0x00ff1cff, CPRR);
 
-#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
+#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
         /* Enable both ports */
         titan_writel(MASK_SER0 | MASK_SER1, UACFG);
 #else
         /* Enable port #0 only */
         titan_writel(MASK_SER0, UACFG);
-#endif  /* defined(CONFIG_KGDB) */
+#endif
 
         /*
          * Set up serial port #0. Do not use autodetection; the result is
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 2678b7ec3351..eb44b72254af 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23-rc5
-# Thu Sep  6 13:14:29 2007
+# Linux kernel version: 2.6.26
+# Fri Jul 25 10:25:34 2008
 #
 CONFIG_MIPS=y
 
@@ -10,9 +10,11 @@ CONFIG_MIPS=y
 #
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_BASLER_EXCITE is not set
+# CONFIG_BCM47XX is not set
 CONFIG_MIPS_COBALT=y
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
 # CONFIG_LEMOTE_FULONG is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_MIPS_SIM is not set
@@ -24,6 +26,7 @@ CONFIG_MIPS_COBALT=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
 # CONFIG_SIBYTE_CRHINE is not set
 # CONFIG_SIBYTE_CARMEL is not set
@@ -34,19 +37,25 @@ CONFIG_MIPS_COBALT=y
 # CONFIG_SIBYTE_SENTOSA is not set
 # CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
 # CONFIG_WR_PPMC is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_GT641XX=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
 CONFIG_EARLY_PRINTK=y
@@ -108,6 +117,7 @@ CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -115,10 +125,16 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
 # CONFIG_HZ_100 is not set
 # CONFIG_HZ_128 is not set
@@ -151,23 +167,28 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -177,23 +198,37 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
+CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -207,18 +242,18 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
 CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+CONFIG_I8253=y
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 
@@ -232,8 +267,8 @@ CONFIG_TRAD_SIGNALS=y
 #
 # Power management options
 #
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -250,6 +285,7 @@ CONFIG_XFRM=y
 CONFIG_XFRM_USER=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -269,6 +305,7 @@ CONFIG_IP_FIB_HASH=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
@@ -276,8 +313,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -294,10 +329,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -305,6 +336,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
@@ -326,9 +358,12 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -337,6 +372,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -350,6 +386,7 @@ CONFIG_MTD_BLKDEVS=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -384,6 +421,7 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_PHYSMAP_START=0x0
 CONFIG_MTD_PHYSMAP_LEN=0x0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -423,7 +461,9 @@ CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 # CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -462,10 +502,15 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
 # CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
@@ -475,7 +520,6 @@ CONFIG_ATA=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -504,7 +548,9 @@ CONFIG_ATA=y
 # CONFIG_PATA_MPIIX is not set
 # CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
 # CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
 # CONFIG_PATA_OPTI is not set
 # CONFIG_PATA_OPTIDMA is not set
 # CONFIG_PATA_PDC_OLD is not set
@@ -518,29 +564,27 @@ CONFIG_ATA=y
 CONFIG_PATA_VIA=y
 # CONFIG_PATA_WINBOND is not set
 # CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
+# CONFIG_FUSION is not set
 
 #
-# Fusion MPT device support
+# IEEE 1394 (FireWire) support
 #
-# CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
 
 #
-# IEEE 1394 (FireWire) support
+# Enable only one of the two stacks, unless you know what you are doing
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
@@ -562,7 +606,12 @@ CONFIG_TULIP=y
 # CONFIG_DM9102 is not set
 # CONFIG_ULI526X is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
@@ -572,6 +621,7 @@ CONFIG_TULIP=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -580,7 +630,6 @@ CONFIG_TULIP=y
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
 # CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
@@ -588,7 +637,6 @@ CONFIG_TULIP=y
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -607,7 +655,6 @@ CONFIG_INPUT_POLLDEV=y
 #
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -642,7 +689,9 @@ CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -664,65 +713,122 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-CONFIG_COBALT_LCD=y
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_COBALT=y
+# CONFIG_FB_VIRTUAL is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
 # CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
 # USB Input Devices
@@ -743,6 +849,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=m
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -751,15 +858,18 @@ CONFIG_USB=m
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=m
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -773,6 +883,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -785,6 +896,7 @@ CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -793,6 +905,7 @@ CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -800,15 +913,11 @@ CONFIG_USB_STORAGE=m
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-CONFIG_USB_MON=y
+# CONFIG_USB_MON is not set
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -833,16 +942,10 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 
@@ -858,6 +961,8 @@ CONFIG_LEDS_COBALT_RAQ=y
 CONFIG_LEDS_TRIGGERS=y
 # CONFIG_LEDS_TRIGGER_TIMER is not set
 # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -882,9 +987,10 @@ CONFIG_RTC_INTF_DEV=y
 # Platform RTC drivers
 #
 CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
@@ -892,23 +998,7 @@ CONFIG_RTC_DRV_CMOS=y
 #
 # on-CPU RTC drivers
 #
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -923,22 +1013,22 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
+CONFIG_EXT4DEV_FS=y
+CONFIG_EXT4DEV_FS_XATTR=y
+CONFIG_EXT4DEV_FS_POSIX_ACL=y
+CONFIG_EXT4DEV_FS_SECURITY=y
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -967,7 +1057,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 CONFIG_CONFIGFS_FS=y
 
 #
@@ -983,32 +1072,28 @@ CONFIG_CONFIGFS_FS=y
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
 CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
 CONFIG_NFSD_V3_ACL=y
 # CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
 CONFIG_NFS_ACL_SUPPORT=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1022,34 +1107,26 @@ CONFIG_SUNRPC=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_CROSSCOMPILE=y
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 CONFIG_CMDLINE=""
 
 #
@@ -1057,14 +1134,95 @@ CONFIG_CMDLINE=""
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-# CONFIG_CRYPTO is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index ebb8ad62b3a3..a279165e3a7d 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index ad4e5ef65592..8944d15caf13 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index d0dc2e83ad35..ab17973107fd 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -1174,7 +1174,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE="mem=48M"
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 9155082313c8..b65803f19352 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -1392,7 +1392,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index e4e324422cd9..a190ac07740b 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1209,7 +1209,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 3572e80356d2..4e465e945991 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -1269,7 +1269,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 138c575a0151..831d3e5a1ea6 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -943,7 +943,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index 59d19472b161..dd13db4d0fb9 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -1415,8 +1415,6 @@ CONFIG_FORCED_INLINING=y
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_KGDB is not set
-CONFIG_SYS_SUPPORTS_KGDB=y
 # CONFIG_RUNTIME_DEBUG is not set
 # CONFIG_MIPS_UNCACHED is not set
 
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index bacf0dd0e345..db9272677aa2 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -3020,7 +3020,6 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 6dfe6f793cef..9e21e333a2fc 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -1085,7 +1085,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index c965a87e6a96..af67ed4f71ae 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -1202,7 +1202,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 0778996c682f..7956f56cbf3e 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -1195,7 +1195,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 37c7b5ffd474..723bd5176a35 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -1216,10 +1216,8 @@ CONFIG_DEBUG_MUTEXES=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
+CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_KGDB is not set
-CONFIG_SYS_SUPPORTS_KGDB=y
 # CONFIG_RUNTIME_DEBUG is not set
 
 #
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 893e5c4ab66d..b5052fb42e9e 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -1206,10 +1206,8 @@ CONFIG_DEBUG_SLAB=y
 CONFIG_FORCED_INLINING=y
 # CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
+CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_KGDB is not set
-CONFIG_SYS_SUPPORTS_KGDB=y
 # CONFIG_RUNTIME_DEBUG is not set
 
 #
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index e42aed5a38bb..c7c0864b8ce9 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -742,7 +742,6 @@ CONFIG_DEBUG_FS=y
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 
 #
 # Security options
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 1ea97865f2ce..a9acaa2f9da3 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -963,7 +963,6 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SAMPLES is not set
 CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
 # CONFIG_SB1XXX_CORELIS is not set
 
 #
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 7f86c43d1bda..ea8249c75b3f 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -827,8 +827,6 @@ CONFIG_FORCED_INLINING=y
 CONFIG_CROSSCOMPILE=y
 CONFIG_CMDLINE=""
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_KGDB is not set
-CONFIG_SYS_SUPPORTS_KGDB=y
 # CONFIG_RUNTIME_DEBUG is not set
 
 #
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c
index 11567702b155..d70627de7cfe 100644
--- a/arch/mips/emma2rh/markeins/platform.c
+++ b/arch/mips/emma2rh/markeins/platform.c
@@ -34,7 +34,6 @@
 #include <asm/bcache.h>
 #include <asm/irq.h>
 #include <asm/reboot.h>
-#include <asm/gdb-stub.h>
 #include <asm/traps.h>
 #include <asm/debug.h>
 
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
index 62bfb455d1b1..822a20e21fa4 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -27,7 +27,6 @@
 #include <linux/types.h>
 #include <linux/initrd.h>
 #include <linux/irq.h>
-#include <linux/ide.h>
 #include <linux/ioport.h>
 #include <linux/param.h>        /* for HZ */
 #include <linux/root_dev.h>
@@ -41,7 +40,6 @@
 #include <asm/bcache.h>
 #include <asm/irq.h>
 #include <asm/reboot.h>
-#include <asm/gdb-stub.h>
 #include <asm/traps.h>
 #include <asm/debug.h>
 
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index f60524e8bc44..b59ba6b93cdd 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -10,7 +10,6 @@
  * Copyright (C) 2007 by Thomas Bogendoerfer
  */
 #include <linux/eisa.h>
-#include <linux/hdreg.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/sched.h>
@@ -18,7 +17,6 @@
 #include <linux/mm.h>
 #include <linux/console.h>
 #include <linux/fb.h>
-#include <linux/ide.h>
 #include <linux/pm.h>
 #include <linux/screen_info.h>
 #include <linux/platform_device.h>
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 0fd31974ba28..706f93974797 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -71,7 +71,7 @@ obj-$(CONFIG_MIPS32_COMPAT)	+= linux32.o ptrace32.o signal32.o
 obj-$(CONFIG_MIPS32_N32)        += binfmt_elfn32.o scall64-n32.o signal_n32.o
 obj-$(CONFIG_MIPS32_O32)        += binfmt_elfo32.o scall64-o32.o
 
-obj-$(CONFIG_KGDB)              += gdb-low.o gdb-stub.o
+obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_PROC_FS)           += proc.o
 
 obj-$(CONFIG_64BIT)             += cpu-bugs64.o
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
deleted file mode 100644
index 2c446063636a..000000000000
--- a/arch/mips/kernel/gdb-low.S
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * gdb-low.S contains the low-level trap handler for the GDB stub.
- *
- * Copyright (C) 1995 Andreas Busse
- */
-#include <linux/sys.h>
-
-#include <asm/asm.h>
-#include <asm/errno.h>
-#include <asm/irqflags.h>
-#include <asm/mipsregs.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-#include <asm/gdb-stub.h>
-
-#ifdef CONFIG_32BIT
-#define DMFC0   mfc0
-#define DMTC0   mtc0
-#define LDC1    lwc1
-#define SDC1    lwc1
-#endif
-#ifdef CONFIG_64BIT
-#define DMFC0   dmfc0
-#define DMTC0   dmtc0
-#define LDC1    ldc1
-#define SDC1    ldc1
-#endif
-
-/*
- * [jsun] We reserves about 2x GDB_FR_SIZE in stack.  The lower (addressed)
- * part is used to store registers and passed to exception handler.
- * The upper part is reserved for "call func" feature where gdb client
- * saves some of the regs, setups call frame and passes args.
- *
- * A trace shows about 200 bytes are used to store about half of all regs.
- * The rest should be big enough for frame setup and passing args.
- */
-
-/*
- * The low level trap handler
- */
-                .align  5
-                NESTED(trap_low, GDB_FR_SIZE, sp)
-                .set    noat
-                .set    noreorder
-
-                mfc0    k0, CP0_STATUS
-                sll     k0, 3                   /* extract cu0 bit */
-                bltz    k0, 1f
-                move    k1, sp
-
-                /*
-                 * Called from user mode, go somewhere else.
-                 */
-                mfc0    k0, CP0_CAUSE
-                andi    k0, k0, 0x7c
-#ifdef CONFIG_64BIT
-                dsll    k0, k0, 1
-#endif
-                PTR_L   k1, saved_vectors(k0)
-                jr      k1
-                nop
-1:
-                move    k0, sp
-                PTR_SUBU sp, k1, GDB_FR_SIZE*2  # see comment above
-                LONG_S  k0, GDB_FR_REG29(sp)
-                LONG_S  $2, GDB_FR_REG2(sp)
-
-/*
- * First save the CP0 and special registers
- */
-
-                mfc0    v0, CP0_STATUS
-                LONG_S  v0, GDB_FR_STATUS(sp)
-                mfc0    v0, CP0_CAUSE
-                LONG_S  v0, GDB_FR_CAUSE(sp)
-                DMFC0   v0, CP0_EPC
-                LONG_S  v0, GDB_FR_EPC(sp)
-                DMFC0   v0, CP0_BADVADDR
-                LONG_S  v0, GDB_FR_BADVADDR(sp)
-                mfhi    v0
-                LONG_S  v0, GDB_FR_HI(sp)
-                mflo    v0
-                LONG_S  v0, GDB_FR_LO(sp)
-
-/*
- * Now the integer registers
- */
-
-                LONG_S  zero, GDB_FR_REG0(sp)           /* I know... */
-                LONG_S  $1, GDB_FR_REG1(sp)
-                /* v0 already saved */
-                LONG_S  $3, GDB_FR_REG3(sp)
-                LONG_S  $4, GDB_FR_REG4(sp)
-                LONG_S  $5, GDB_FR_REG5(sp)
-                LONG_S  $6, GDB_FR_REG6(sp)
-                LONG_S  $7, GDB_FR_REG7(sp)
-                LONG_S  $8, GDB_FR_REG8(sp)
-                LONG_S  $9, GDB_FR_REG9(sp)
-                LONG_S  $10, GDB_FR_REG10(sp)
-                LONG_S  $11, GDB_FR_REG11(sp)
-                LONG_S  $12, GDB_FR_REG12(sp)
-                LONG_S  $13, GDB_FR_REG13(sp)
-                LONG_S  $14, GDB_FR_REG14(sp)
-                LONG_S  $15, GDB_FR_REG15(sp)
-                LONG_S  $16, GDB_FR_REG16(sp)
-                LONG_S  $17, GDB_FR_REG17(sp)
-                LONG_S  $18, GDB_FR_REG18(sp)
-                LONG_S  $19, GDB_FR_REG19(sp)
-                LONG_S  $20, GDB_FR_REG20(sp)
-                LONG_S  $21, GDB_FR_REG21(sp)
-                LONG_S  $22, GDB_FR_REG22(sp)
-                LONG_S  $23, GDB_FR_REG23(sp)
-                LONG_S  $24, GDB_FR_REG24(sp)
-                LONG_S  $25, GDB_FR_REG25(sp)
-                LONG_S  $26, GDB_FR_REG26(sp)
-                LONG_S  $27, GDB_FR_REG27(sp)
-                LONG_S  $28, GDB_FR_REG28(sp)
-                /* sp already saved */
-                LONG_S  $30, GDB_FR_REG30(sp)
-                LONG_S  $31, GDB_FR_REG31(sp)
-
-                CLI                             /* disable interrupts */
-                TRACE_IRQS_OFF
-
-/*
- * Followed by the floating point registers
- */
-                mfc0    v0, CP0_STATUS          /* FPU enabled? */
-                srl     v0, v0, 16
-                andi    v0, v0, (ST0_CU1 >> 16)
-
-                beqz    v0,2f                   /* disabled, skip */
-                 nop
-
-                SDC1    $0, GDB_FR_FPR0(sp)
-                SDC1    $1, GDB_FR_FPR1(sp)
-                SDC1    $2, GDB_FR_FPR2(sp)
-                SDC1    $3, GDB_FR_FPR3(sp)
-                SDC1    $4, GDB_FR_FPR4(sp)
-                SDC1    $5, GDB_FR_FPR5(sp)
-                SDC1    $6, GDB_FR_FPR6(sp)
-                SDC1    $7, GDB_FR_FPR7(sp)
-                SDC1    $8, GDB_FR_FPR8(sp)
-                SDC1    $9, GDB_FR_FPR9(sp)
-                SDC1    $10, GDB_FR_FPR10(sp)
-                SDC1    $11, GDB_FR_FPR11(sp)
-                SDC1    $12, GDB_FR_FPR12(sp)
-                SDC1    $13, GDB_FR_FPR13(sp)
-                SDC1    $14, GDB_FR_FPR14(sp)
-                SDC1    $15, GDB_FR_FPR15(sp)
-                SDC1    $16, GDB_FR_FPR16(sp)
-                SDC1    $17, GDB_FR_FPR17(sp)
-                SDC1    $18, GDB_FR_FPR18(sp)
-                SDC1    $19, GDB_FR_FPR19(sp)
-                SDC1    $20, GDB_FR_FPR20(sp)
-                SDC1    $21, GDB_FR_FPR21(sp)
-                SDC1    $22, GDB_FR_FPR22(sp)
-                SDC1    $23, GDB_FR_FPR23(sp)
-                SDC1    $24, GDB_FR_FPR24(sp)
-                SDC1    $25, GDB_FR_FPR25(sp)
-                SDC1    $26, GDB_FR_FPR26(sp)
-                SDC1    $27, GDB_FR_FPR27(sp)
-                SDC1    $28, GDB_FR_FPR28(sp)
-                SDC1    $29, GDB_FR_FPR29(sp)
-                SDC1    $30, GDB_FR_FPR30(sp)
-                SDC1    $31, GDB_FR_FPR31(sp)
-
-/*
- * FPU control registers
- */
-
-                cfc1    v0, CP1_STATUS
-                LONG_S  v0, GDB_FR_FSR(sp)
-                cfc1    v0, CP1_REVISION
-                LONG_S  v0, GDB_FR_FIR(sp)
-
-/*
- * Current stack frame ptr
- */
-
-2:
-                LONG_S  sp, GDB_FR_FRP(sp)
-
-/*
- * CP0 registers (R4000/R4400 unused registers skipped)
- */
-
-                mfc0    v0, CP0_INDEX
-                LONG_S  v0, GDB_FR_CP0_INDEX(sp)
-                mfc0    v0, CP0_RANDOM
-                LONG_S  v0, GDB_FR_CP0_RANDOM(sp)
-                DMFC0   v0, CP0_ENTRYLO0
-                LONG_S  v0, GDB_FR_CP0_ENTRYLO0(sp)
-                DMFC0   v0, CP0_ENTRYLO1
-                LONG_S  v0, GDB_FR_CP0_ENTRYLO1(sp)
-                DMFC0   v0, CP0_CONTEXT
-                LONG_S  v0, GDB_FR_CP0_CONTEXT(sp)
-                mfc0    v0, CP0_PAGEMASK
-                LONG_S  v0, GDB_FR_CP0_PAGEMASK(sp)
-                mfc0    v0, CP0_WIRED
-                LONG_S  v0, GDB_FR_CP0_WIRED(sp)
-                DMFC0   v0, CP0_ENTRYHI
-                LONG_S  v0, GDB_FR_CP0_ENTRYHI(sp)
-                mfc0    v0, CP0_PRID
-                LONG_S  v0, GDB_FR_CP0_PRID(sp)
-
-                .set    at
-
-/*
- * Continue with the higher level handler
- */
-
-                move    a0,sp
-
-                jal     handle_exception
-                 nop
-
-/*
- * Restore all writable registers, in reverse order
- */
-
-                .set    noat
-
-                LONG_L  v0, GDB_FR_CP0_ENTRYHI(sp)
-                LONG_L  v1, GDB_FR_CP0_WIRED(sp)
-                DMTC0   v0, CP0_ENTRYHI
-                mtc0    v1, CP0_WIRED
-                LONG_L  v0, GDB_FR_CP0_PAGEMASK(sp)
-                LONG_L  v1, GDB_FR_CP0_ENTRYLO1(sp)
-                mtc0    v0, CP0_PAGEMASK
-                DMTC0   v1, CP0_ENTRYLO1
-                LONG_L  v0, GDB_FR_CP0_ENTRYLO0(sp)
-                LONG_L  v1, GDB_FR_CP0_INDEX(sp)
-                DMTC0   v0, CP0_ENTRYLO0
-                LONG_L  v0, GDB_FR_CP0_CONTEXT(sp)
-                mtc0    v1, CP0_INDEX
-                DMTC0   v0, CP0_CONTEXT
-
-
-/*
- * Next, the floating point registers
- */
-                mfc0    v0, CP0_STATUS          /* check if the FPU is enabled */
-                srl     v0, v0, 16
-                andi    v0, v0, (ST0_CU1 >> 16)
-
-                beqz    v0, 3f                  /* disabled, skip */
-                 nop
-
-                LDC1    $31, GDB_FR_FPR31(sp)
-                LDC1    $30, GDB_FR_FPR30(sp)
-                LDC1    $29, GDB_FR_FPR29(sp)
-                LDC1    $28, GDB_FR_FPR28(sp)
-                LDC1    $27, GDB_FR_FPR27(sp)
-                LDC1    $26, GDB_FR_FPR26(sp)
-                LDC1    $25, GDB_FR_FPR25(sp)
-                LDC1    $24, GDB_FR_FPR24(sp)
-                LDC1    $23, GDB_FR_FPR23(sp)
-                LDC1    $22, GDB_FR_FPR22(sp)
-                LDC1    $21, GDB_FR_FPR21(sp)
-                LDC1    $20, GDB_FR_FPR20(sp)
-                LDC1    $19, GDB_FR_FPR19(sp)
-                LDC1    $18, GDB_FR_FPR18(sp)
-                LDC1    $17, GDB_FR_FPR17(sp)
-                LDC1    $16, GDB_FR_FPR16(sp)
-                LDC1    $15, GDB_FR_FPR15(sp)
-                LDC1    $14, GDB_FR_FPR14(sp)
-                LDC1    $13, GDB_FR_FPR13(sp)
-                LDC1    $12, GDB_FR_FPR12(sp)
-                LDC1    $11, GDB_FR_FPR11(sp)
-                LDC1    $10, GDB_FR_FPR10(sp)
-                LDC1    $9, GDB_FR_FPR9(sp)
-                LDC1    $8, GDB_FR_FPR8(sp)
-                LDC1    $7, GDB_FR_FPR7(sp)
-                LDC1    $6, GDB_FR_FPR6(sp)
-                LDC1    $5, GDB_FR_FPR5(sp)
-                LDC1    $4, GDB_FR_FPR4(sp)
-                LDC1    $3, GDB_FR_FPR3(sp)
-                LDC1    $2, GDB_FR_FPR2(sp)
-                LDC1    $1, GDB_FR_FPR1(sp)
-                LDC1    $0, GDB_FR_FPR0(sp)
-
-/*
- * Now the CP0 and integer registers
- */
-
-3:
-#ifdef CONFIG_MIPS_MT_SMTC
-                /* Read-modify write of Status must be atomic */
-                mfc0    t2, CP0_TCSTATUS
-                ori     t1, t2, TCSTATUS_IXMT
-                mtc0    t1, CP0_TCSTATUS
-                andi    t2, t2, TCSTATUS_IXMT
-                _ehb
-                DMT     9                               # dmt   t1
-                jal     mips_ihb
-                nop
-#endif /* CONFIG_MIPS_MT_SMTC */
-                mfc0    t0, CP0_STATUS
-                ori     t0, 0x1f
-                xori    t0, 0x1f
-                mtc0    t0, CP0_STATUS
-#ifdef CONFIG_MIPS_MT_SMTC
-                andi    t1, t1, VPECONTROL_TE
-                beqz    t1, 9f
-                nop
-                EMT                                     # emt
-9:
-                mfc0    t1, CP0_TCSTATUS
-                xori    t1, t1, TCSTATUS_IXMT
-                or      t1, t1, t2
-                mtc0    t1, CP0_TCSTATUS
-                _ehb
-#endif /* CONFIG_MIPS_MT_SMTC */
-                LONG_L  v0, GDB_FR_STATUS(sp)
-                LONG_L  v1, GDB_FR_EPC(sp)
-                mtc0    v0, CP0_STATUS
-                DMTC0   v1, CP0_EPC
-                LONG_L  v0, GDB_FR_HI(sp)
-                LONG_L  v1, GDB_FR_LO(sp)
-                mthi    v0
-                mtlo    v1
-                LONG_L  $31, GDB_FR_REG31(sp)
-                LONG_L  $30, GDB_FR_REG30(sp)
-                LONG_L  $28, GDB_FR_REG28(sp)
-                LONG_L  $27, GDB_FR_REG27(sp)
-                LONG_L  $26, GDB_FR_REG26(sp)
-                LONG_L  $25, GDB_FR_REG25(sp)
-                LONG_L  $24, GDB_FR_REG24(sp)
-                LONG_L  $23, GDB_FR_REG23(sp)
-                LONG_L  $22, GDB_FR_REG22(sp)
-                LONG_L  $21, GDB_FR_REG21(sp)
-                LONG_L  $20, GDB_FR_REG20(sp)
-                LONG_L  $19, GDB_FR_REG19(sp)
-                LONG_L  $18, GDB_FR_REG18(sp)
-                LONG_L  $17, GDB_FR_REG17(sp)
-                LONG_L  $16, GDB_FR_REG16(sp)
-                LONG_L  $15, GDB_FR_REG15(sp)
-                LONG_L  $14, GDB_FR_REG14(sp)
-                LONG_L  $13, GDB_FR_REG13(sp)
-                LONG_L  $12, GDB_FR_REG12(sp)
-                LONG_L  $11, GDB_FR_REG11(sp)
-                LONG_L  $10, GDB_FR_REG10(sp)
-                LONG_L  $9, GDB_FR_REG9(sp)
-                LONG_L  $8, GDB_FR_REG8(sp)
-                LONG_L  $7, GDB_FR_REG7(sp)
-                LONG_L  $6, GDB_FR_REG6(sp)
-                LONG_L  $5, GDB_FR_REG5(sp)
-                LONG_L  $4, GDB_FR_REG4(sp)
-                LONG_L  $3, GDB_FR_REG3(sp)
-                LONG_L  $2, GDB_FR_REG2(sp)
-                LONG_L  $1, GDB_FR_REG1(sp)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-                LONG_L  k0, GDB_FR_EPC(sp)
-                LONG_L  $29, GDB_FR_REG29(sp)           /* Deallocate stack */
-                jr      k0
-                rfe
-#else
-                LONG_L  sp, GDB_FR_REG29(sp)            /* Deallocate stack */
-
-                .set    mips3
-                eret
-                .set    mips0
-#endif
-                .set    at
-                .set    reorder
-                END(trap_low)
-
-LEAF(kgdb_read_byte)
-4:              lb      t0, (a0)
-                sb      t0, (a1)
-                li      v0, 0
-                jr      ra
-                .section __ex_table,"a"
-                PTR     4b, kgdbfault
-                .previous
-                END(kgdb_read_byte)
-
-LEAF(kgdb_write_byte)
-5:              sb      a0, (a1)
-                li      v0, 0
-                jr      ra
-                .section __ex_table,"a"
-                PTR     5b, kgdbfault
-                .previous
-                END(kgdb_write_byte)
-
-                .type   kgdbfault@function
-                .ent    kgdbfault
-
-kgdbfault:      li      v0, -EFAULT
-                jr      ra
-                .end    kgdbfault
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
deleted file mode 100644
index 25f4eab8ea9c..000000000000
--- a/arch/mips/kernel/gdb-stub.c
+++ /dev/null
@@ -1,1155 +0,0 @@
-/*
- *  arch/mips/kernel/gdb-stub.c
- *
- *  Originally written by Glenn Engel, Lake Stevens Instrument Division
- *
- *  Contributed by HP Systems
- *
- *  Modified for SPARC by Stu Grossman, Cygnus Support.
- *
- *  Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
- *  Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
- *
- *  Copyright (C) 1995 Andreas Busse
- *
- *  Copyright (C) 2003 MontaVista Software Inc.
- *  Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- */
-
-/*
- *  To enable debugger support, two things need to happen.  One, a
- *  call to set_debug_traps() is necessary in order to allow any breakpoints
- *  or error conditions to be properly intercepted and reported to gdb.
- *  Two, a breakpoint needs to be generated to begin communication.  This
- *  is most easily accomplished by a call to breakpoint().  Breakpoint()
- *  simulates a breakpoint by executing a BREAK instruction.
- *
- *
- *    The following gdb commands are supported:
- *
- * command          function                               Return value
- *
- *    g             return the value of the CPU registers  hex data or ENN
- *    G             set the value of the CPU registers     OK or ENN
- *
- *    mAA..AA,LLLL  Read LLLL bytes at address AA..AA      hex data or ENN
- *    MAA..AA,LLLL: Write LLLL bytes at address AA.AA      OK or ENN
- *
- *    c             Resume at current address              SNN   ( signal NN)
- *    cAA..AA       Continue at address AA..AA             SNN
- *
- *    s             Step one instruction                   SNN
- *    sAA..AA       Step one instruction from AA..AA       SNN
- *
- *    k             kill
- *
- *    ?             What was the last sigval ?             SNN   (signal NN)
- *
- *    bBB..BB       Set baud rate to BB..BB                OK or BNN, then sets
- *                                                         baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum.  A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum>    :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer.  '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host:                  Reply:
- * $m0,10#2a               +$00010203040506070809101112131415#42
- *
- *
- *  ==============
- *  MORE EXAMPLES:
- *  ==============
- *
- *  For reference -- the following are the steps that one
- *  company took (RidgeRun Inc) to get remote gdb debugging
- *  going. In this scenario the host machine was a PC and the
- *  target platform was a Galileo EVB64120A MIPS evaluation
- *  board.
- *
- *  Step 1:
- *  First download gdb-5.0.tar.gz from the internet.
- *  and then build/install the package.
- *
- *  Example:
- *    $ tar zxf gdb-5.0.tar.gz
- *    $ cd gdb-5.0
- *    $ ./configure --target=mips-linux-elf
- *    $ make
- *    $ install
- *    $ which mips-linux-elf-gdb
- *    /usr/local/bin/mips-linux-elf-gdb
- *
- *  Step 2:
- *  Configure linux for remote debugging and build it.
- *
- *  Example:
- *    $ cd ~/linux
- *    $ make menuconfig <go to "Kernel Hacking" and turn on remote debugging>
- *    $ make
- *
- *  Step 3:
- *  Download the kernel to the remote target and start
- *  the kernel running. It will promptly halt and wait
- *  for the host gdb session to connect. It does this
- *  since the "Kernel Hacking" option has defined
- *  CONFIG_KGDB which in turn enables your calls
- *  to:
- *     set_debug_traps();
- *     breakpoint();
- *
- *  Step 4:
- *  Start the gdb session on the host.
- *
- *  Example:
- *    $ mips-linux-elf-gdb vmlinux
- *    (gdb) set remotebaud 115200
- *    (gdb) target remote /dev/ttyS1
- *    ...at this point you are connected to
- *       the remote target and can use gdb
- *       in the normal fasion. Setting
- *       breakpoints, single stepping,
- *       printing variables, etc.
- */
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/reboot.h>
-
-#include <asm/asm.h>
-#include <asm/cacheflush.h>
-#include <asm/mipsregs.h>
-#include <asm/pgtable.h>
-#include <asm/system.h>
-#include <asm/gdb-stub.h>
-#include <asm/inst.h>
-
-/*
- * external low-level support routines
- */
-
-extern int putDebugChar(char c);    /* write a single character      */
-extern char getDebugChar(void);     /* read and return a single char */
-extern void trap_low(void);
-
-/*
- * breakpoint and test functions
- */
-extern void breakpoint(void);
-extern void breakinst(void);
-extern void async_breakpoint(void);
-extern void async_breakinst(void);
-extern void adel(void);
-
-/*
- * local prototypes
- */
-
-static void getpacket(char *buffer);
-static void putpacket(char *buffer);
-static int computeSignal(int tt);
-static int hex(unsigned char ch);
-static int hexToInt(char **ptr, int *intValue);
-static int hexToLong(char **ptr, long *longValue);
-static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault);
-void handle_exception(struct gdb_regs *regs);
-
-int kgdb_enabled;
-
-/*
- * spin locks for smp case
- */
-static DEFINE_SPINLOCK(kgdb_lock);
-static raw_spinlock_t kgdb_cpulock[NR_CPUS] = {
-        [0 ... NR_CPUS-1] = __RAW_SPIN_LOCK_UNLOCKED,
-};
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers
- * at least NUMREGBYTES*2 are needed for register packets
- */
-#define BUFMAX 2048
-
-static char input_buffer[BUFMAX];
-static char output_buffer[BUFMAX];
-static int initialized; /* !0 means we've been initialized */
-static int kgdb_started;
-static const char hexchars[]="0123456789abcdef";
-
-/* Used to prevent crashes in memory access.  Note that they'll crash anyway if
-   we haven't set up fault handlers yet... */
-int kgdb_read_byte(unsigned char *address, unsigned char *dest);
-int kgdb_write_byte(unsigned char val, unsigned char *dest);
-
-/*
- * Convert ch from a hex digit to an int
- */
-static int hex(unsigned char ch)
-{
-        if (ch >= 'a' && ch <= 'f')
-                return ch-'a'+10;
-        if (ch >= '0' && ch <= '9')
-                return ch-'0';
-        if (ch >= 'A' && ch <= 'F')
-                return ch-'A'+10;
-        return -1;
-}
-
-/*
- * scan for the sequence $<data>#<checksum>
- */
-static void getpacket(char *buffer)
-{
-        unsigned char checksum;
-        unsigned char xmitcsum;
-        int i;
-        int count;
-        unsigned char ch;
-
-        do {
-                /*
-                 * wait around for the start character,
-                 * ignore all other characters
-                 */
-                while ((ch = (getDebugChar() & 0x7f)) != '$') ;
-
-                checksum = 0;
-                xmitcsum = -1;
-                count = 0;
-
-                /*
-                 * now, read until a # or end of buffer is found
-                 */
-                while (count < BUFMAX) {
-                        ch = getDebugChar();
-                        if (ch == '#')
-                                break;
-                        checksum = checksum + ch;
-                        buffer[count] = ch;
-                        count = count + 1;
-                }
-
-                if (count >= BUFMAX)
-                        continue;
-
-                buffer[count] = 0;
-
-                if (ch == '#') {
-                        xmitcsum = hex(getDebugChar() & 0x7f) << 4;
-                        xmitcsum |= hex(getDebugChar() & 0x7f);
-
-                        if (checksum != xmitcsum)
-                                putDebugChar('-');      /* failed checksum */
-                        else {
-                                putDebugChar('+'); /* successful transfer */
-
-                                /*
-                                 * if a sequence char is present,
-                                 * reply the sequence ID
-                                 */
-                                if (buffer[2] == ':') {
-                                        putDebugChar(buffer[0]);
-                                        putDebugChar(buffer[1]);
-
-                                        /*
-                                         * remove sequence chars from buffer
-                                         */
-                                        count = strlen(buffer);
-                                        for (i=3; i <= count; i++)
-                                                buffer[i-3] = buffer[i];
-                                }
-                        }
-                }
-        }
-        while (checksum != xmitcsum);
-}
-
-/*
- * send the packet in buffer.
- */
-static void putpacket(char *buffer)
-{
-        unsigned char checksum;
-        int count;
-        unsigned char ch;
-
-        /*
-         * $<packet info>#<checksum>.
-         */
-
-        do {
-                putDebugChar('$');
-                checksum = 0;
-                count = 0;
-
-                while ((ch = buffer[count]) != 0) {
-                        if (!(putDebugChar(ch)))
-                                return;
-                        checksum += ch;
-                        count += 1;
-                }
-
-                putDebugChar('#');
-                putDebugChar(hexchars[checksum >> 4]);
-                putDebugChar(hexchars[checksum & 0xf]);
-
-        }
-        while ((getDebugChar() & 0x7f) != '+');
-}
-
-
-/*
- * Convert the memory pointed to by mem into hex, placing result in buf.
- * Return a pointer to the last char put in buf (null), in case of mem fault,
- * return 0.
- * may_fault is non-zero if we are reading from arbitrary memory, but is currently
- * not used.
- */
-static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault)
-{
-        unsigned char ch;
-
-        while (count-- > 0) {
-                if (kgdb_read_byte(mem++, &ch) != 0)
-                        return 0;
-                *buf++ = hexchars[ch >> 4];
-                *buf++ = hexchars[ch & 0xf];
-        }
-
-        *buf = 0;
-
-        return buf;
-}
-
-/*
- * convert the hex array pointed to by buf into binary to be placed in mem
- * return a pointer to the character AFTER the last byte written
- * may_fault is non-zero if we are reading from arbitrary memory, but is currently
- * not used.
- */
-static char *hex2mem(char *buf, char *mem, int count, int binary, int may_fault)
-{
-        int i;
-        unsigned char ch;
-
-        for (i=0; i<count; i++)
-        {
-                if (binary) {
-                        ch = *buf++;
-                        if (ch == 0x7d)
-                                ch = 0x20 ^ *buf++;
-                }
-                else {
-                        ch = hex(*buf++) << 4;
-                        ch |= hex(*buf++);
-                }
-                if (kgdb_write_byte(ch, mem++) != 0)
-                        return 0;
-        }
-
-        return mem;
-}
-
-/*
- * This table contains the mapping between SPARC hardware trap types, and
- * signals, which are primarily what GDB understands.  It also indicates
- * which hardware traps we need to commandeer when initializing the stub.
- */
-static struct hard_trap_info {
-        unsigned char tt;               /* Trap type code for MIPS R3xxx and R4xxx */
-        unsigned char signo;            /* Signal that we map this trap into */
-} hard_trap_info[] = {
-        { 6, SIGBUS },                  /* instruction bus error */
-        { 7, SIGBUS },                  /* data bus error */
-        { 9, SIGTRAP },                 /* break */
-        { 10, SIGILL },                 /* reserved instruction */
-/*      { 11, SIGILL },         */      /* CPU unusable */
-        { 12, SIGFPE },                 /* overflow */
-        { 13, SIGTRAP },                /* trap */
-        { 14, SIGSEGV },                /* virtual instruction cache coherency */
-        { 15, SIGFPE },                 /* floating point exception */
-        { 23, SIGSEGV },                /* watch */
-        { 31, SIGSEGV },                /* virtual data cache coherency */
-        { 0, 0}                         /* Must be last */
-};
-
-/* Save the normal trap handlers for user-mode traps. */
-void *saved_vectors[32];
-
-/*
- * Set up exception handlers for tracing and breakpoints
- */
-void set_debug_traps(void)
-{
-        struct hard_trap_info *ht;
-        unsigned long flags;
-        unsigned char c;
-
-        local_irq_save(flags);
-        for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
-                saved_vectors[ht->tt] = set_except_vector(ht->tt, trap_low);
-
-        putDebugChar('+'); /* 'hello world' */
-        /*
-         * In case GDB is started before us, ack any packets
-         * (presumably "$?#xx") sitting there.
-         */
-        while((c = getDebugChar()) != '$');
-        while((c = getDebugChar()) != '#');
-        c = getDebugChar(); /* eat first csum byte */
-        c = getDebugChar(); /* eat second csum byte */
-        putDebugChar('+'); /* ack it */
-
-        initialized = 1;
-        local_irq_restore(flags);
-}
-
-void restore_debug_traps(void)
-{
-        struct hard_trap_info *ht;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
-                set_except_vector(ht->tt, saved_vectors[ht->tt]);
-        local_irq_restore(flags);
-}
-
-/*
- * Convert the MIPS hardware trap type code to a Unix signal number.
- */
-static int computeSignal(int tt)
-{
-        struct hard_trap_info *ht;
-
-        for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
-                if (ht->tt == tt)
-                        return ht->signo;
-
-        return SIGHUP;          /* default for things we don't know about */
-}
-
-/*
- * While we find nice hex chars, build an int.
- * Return number of chars processed.
- */
-static int hexToInt(char **ptr, int *intValue)
-{
-        int numChars = 0;
-        int hexValue;
-
-        *intValue = 0;
-
-        while (**ptr) {
-                hexValue = hex(**ptr);
-                if (hexValue < 0)
-                        break;
-
-                *intValue = (*intValue << 4) | hexValue;
-                numChars ++;
-
-                (*ptr)++;
-        }
-
-        return (numChars);
-}
-
-static int hexToLong(char **ptr, long *longValue)
-{
-        int numChars = 0;
-        int hexValue;
-
-        *longValue = 0;
-
-        while (**ptr) {
-                hexValue = hex(**ptr);
-                if (hexValue < 0)
-                        break;
-
-                *longValue = (*longValue << 4) | hexValue;
-                numChars ++;
-
-                (*ptr)++;
-        }
-
-        return numChars;
-}
-
-
-#if 0
-/*
- * Print registers (on target console)
- * Used only to debug the stub...
- */
-void show_gdbregs(struct gdb_regs * regs)
-{
-        /*
-         * Saved main processor registers
-         */
-        printk("$0 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
-               regs->reg0, regs->reg1, regs->reg2, regs->reg3,
-               regs->reg4, regs->reg5, regs->reg6, regs->reg7);
-        printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
-               regs->reg8, regs->reg9, regs->reg10, regs->reg11,
-               regs->reg12, regs->reg13, regs->reg14, regs->reg15);
-        printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
-               regs->reg16, regs->reg17, regs->reg18, regs->reg19,
-               regs->reg20, regs->reg21, regs->reg22, regs->reg23);
-        printk("$24: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
-               regs->reg24, regs->reg25, regs->reg26, regs->reg27,
-               regs->reg28, regs->reg29, regs->reg30, regs->reg31);
-
-        /*
-         * Saved cp0 registers
-         */
-        printk("epc  : %08lx\nStatus: %08lx\nCause : %08lx\n",
-               regs->cp0_epc, regs->cp0_status, regs->cp0_cause);
-}
-#endif /* dead code */
-
-/*
- * We single-step by setting breakpoints. When an exception
- * is handled, we need to restore the instructions hoisted
- * when the breakpoints were set.
- *
- * This is where we save the original instructions.
- */
-static struct gdb_bp_save {
-        unsigned long addr;
-        unsigned int val;
-} step_bp[2];
-
-#define BP 0x0000000d  /* break opcode */
-
-/*
- * Set breakpoint instructions for single stepping.
- */
-static void single_step(struct gdb_regs *regs)
-{
-        union mips_instruction insn;
-        unsigned long targ;
-        int is_branch, is_cond, i;
-
-        targ = regs->cp0_epc;
-        insn.word = *(unsigned int *)targ;
-        is_branch = is_cond = 0;
-
-        switch (insn.i_format.opcode) {
-        /*
-         * jr and jalr are in r_format format.
-         */
-        case spec_op:
-                switch (insn.r_format.func) {
-                case jalr_op:
-                case jr_op:
-                        targ = *(&regs->reg0 + insn.r_format.rs);
-                        is_branch = 1;
-                        break;
-                }
-                break;
-
-        /*
-         * This group contains:
-         * bltz_op, bgez_op, bltzl_op, bgezl_op,
-         * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
-         */
-        case bcond_op:
-                is_branch = is_cond = 1;
-                targ += 4 + (insn.i_format.simmediate << 2);
-                break;
-
-        /*
-         * These are unconditional and in j_format.
-         */
-        case jal_op:
-        case j_op:
-                is_branch = 1;
-                targ += 4;
-                targ >>= 28;
-                targ <<= 28;
-                targ |= (insn.j_format.target << 2);
-                break;
-
-        /*
-         * These are conditional.
-         */
-        case beq_op:
-        case beql_op:
-        case bne_op:
-        case bnel_op:
-        case blez_op:
-        case blezl_op:
-        case bgtz_op:
-        case bgtzl_op:
-        case cop0_op:
-        case cop1_op:
-        case cop2_op:
-        case cop1x_op:
-                is_branch = is_cond = 1;
-                targ += 4 + (insn.i_format.simmediate << 2);
-                break;
-        }
-
-        if (is_branch) {
-                i = 0;
-                if (is_cond && targ != (regs->cp0_epc + 8)) {
-                        step_bp[i].addr = regs->cp0_epc + 8;
-                        step_bp[i++].val = *(unsigned *)(regs->cp0_epc + 8);
-                        *(unsigned *)(regs->cp0_epc + 8) = BP;
-                }
-                step_bp[i].addr = targ;
-                step_bp[i].val  = *(unsigned *)targ;
-                *(unsigned *)targ = BP;
-        } else {
-                step_bp[0].addr = regs->cp0_epc + 4;
-                step_bp[0].val  = *(unsigned *)(regs->cp0_epc + 4);
-                *(unsigned *)(regs->cp0_epc + 4) = BP;
-        }
-}
-
-/*
- *  If asynchronously interrupted by gdb, then we need to set a breakpoint
- *  at the interrupted instruction so that we wind up stopped with a
- *  reasonable stack frame.
- */
-static struct gdb_bp_save async_bp;
-
-/*
- * Swap the interrupted EPC with our asynchronous breakpoint routine.
- * This is safer than stuffing the breakpoint in-place, since no cache
- * flushes (or resulting smp_call_functions) are required.  The
- * assumption is that only one CPU will be handling asynchronous bp's,
- * and only one can be active at a time.
- */
-extern spinlock_t smp_call_lock;
-
-void set_async_breakpoint(unsigned long *epc)
-{
-        /* skip breaking into userland */
-        if ((*epc & 0x80000000) == 0)
-                return;
-
-#ifdef CONFIG_SMP
-        /* avoid deadlock if someone is make IPC */
-        if (spin_is_locked(&smp_call_lock))
-                return;
-#endif
-
-        async_bp.addr = *epc;
-        *epc = (unsigned long)async_breakpoint;
-}
-
-#ifdef CONFIG_SMP
-static void kgdb_wait(void *arg)
-{
-        unsigned flags;
-        int cpu = smp_processor_id();
-
-        local_irq_save(flags);
-
-        __raw_spin_lock(&kgdb_cpulock[cpu]);
-        __raw_spin_unlock(&kgdb_cpulock[cpu]);
-
-        local_irq_restore(flags);
-}
-#endif
-
-/*
- * GDB stub needs to call kgdb_wait on all processor with interrupts
- * disabled, so it uses it's own special variant.
- */
-static int kgdb_smp_call_kgdb_wait(void)
-{
-#ifdef CONFIG_SMP
-        cpumask_t mask = cpu_online_map;
-        struct call_data_struct data;
-        int cpu = smp_processor_id();
-        int cpus;
-
-        /*
-         * Can die spectacularly if this CPU isn't yet marked online
-         */
-        BUG_ON(!cpu_online(cpu));
-
-        cpu_clear(cpu, mask);
-        cpus = cpus_weight(mask);
-        if (!cpus)
-                return 0;
-
-        if (spin_is_locked(&smp_call_lock)) {
-                /*
-                 * Some other processor is trying to make us do something
-                 * but we're not going to respond... give up
-                 */
-                return -1;
-                }
-
-        /*
-         * We will continue here, accepting the fact that
-         * the kernel may deadlock if another CPU attempts
-         * to call smp_call_function now...
-         */
-
-        data.func = kgdb_wait;
-        data.info = NULL;
-        atomic_set(&data.started, 0);
-        data.wait = 0;
-
-        spin_lock(&smp_call_lock);
-        call_data = &data;
-        mb();
-
-        core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
-
-        /* Wait for response */
-        /* FIXME: lock-up detection, backtrace on lock-up */
-        while (atomic_read(&data.started) != cpus)
-                barrier();
-
-        call_data = NULL;
-        spin_unlock(&smp_call_lock);
-#endif
-
-        return 0;
-}
-
-/*
- * This function does all command processing for interfacing to gdb.  It
- * returns 1 if you should skip the instruction at the trap address, 0
- * otherwise.
- */
-void handle_exception(struct gdb_regs *regs)
-{
-        int trap;                       /* Trap type */
-        int sigval;
-        long addr;
-        int length;
-        char *ptr;
-        unsigned long *stack;
-        int i;
-        int bflag = 0;
-
-        kgdb_started = 1;
-
-        /*
-         * acquire the big kgdb spinlock
-         */
-        if (!spin_trylock(&kgdb_lock)) {
-                /*
-                 * some other CPU has the lock, we should go back to
-                 * receive the gdb_wait IPC
-                 */
-                return;
-        }
-
-        /*
-         * If we're in async_breakpoint(), restore the real EPC from
-         * the breakpoint.
-         */
-        if (regs->cp0_epc == (unsigned long)async_breakinst) {
-                regs->cp0_epc = async_bp.addr;
-                async_bp.addr = 0;
-        }
-
-        /*
-         * acquire the CPU spinlocks
-         */
-        for_each_online_cpu(i)
-                if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)
-                        panic("kgdb: couldn't get cpulock %d\n", i);
-
-        /*
-         * force other cpus to enter kgdb
-         */
-        kgdb_smp_call_kgdb_wait();
-
-        /*
-         * If we're in breakpoint() increment the PC
-         */
-        trap = (regs->cp0_cause & 0x7c) >> 2;
-        if (trap == 9 && regs->cp0_epc == (unsigned long)breakinst)
-                regs->cp0_epc += 4;
-
-        /*
-         * If we were single_stepping, restore the opcodes hoisted
-         * for the breakpoint[s].
-         */
-        if (step_bp[0].addr) {
-                *(unsigned *)step_bp[0].addr = step_bp[0].val;
-                step_bp[0].addr = 0;
-
-                if (step_bp[1].addr) {
-                        *(unsigned *)step_bp[1].addr = step_bp[1].val;
-                        step_bp[1].addr = 0;
-                }
-        }
-
-        stack = (long *)regs->reg29;                    /* stack ptr */
-        sigval = computeSignal(trap);
-
-        /*
-         * reply to host that an exception has occurred
-         */
-        ptr = output_buffer;
-
-        /*
-         * Send trap type (converted to signal)
-         */
-        *ptr++ = 'T';
-        *ptr++ = hexchars[sigval >> 4];
-        *ptr++ = hexchars[sigval & 0xf];
-
-        /*
-         * Send Error PC
-         */
-        *ptr++ = hexchars[REG_EPC >> 4];
-        *ptr++ = hexchars[REG_EPC & 0xf];
-        *ptr++ = ':';
-        ptr = mem2hex((char *)&regs->cp0_epc, ptr, sizeof(long), 0);
-        *ptr++ = ';';
-
-        /*
-         * Send frame pointer
-         */
-        *ptr++ = hexchars[REG_FP >> 4];
-        *ptr++ = hexchars[REG_FP & 0xf];
-        *ptr++ = ':';
-        ptr = mem2hex((char *)&regs->reg30, ptr, sizeof(long), 0);
-        *ptr++ = ';';
-
-        /*
-         * Send stack pointer
-         */
-        *ptr++ = hexchars[REG_SP >> 4];
-        *ptr++ = hexchars[REG_SP & 0xf];
-        *ptr++ = ':';
-        ptr = mem2hex((char *)&regs->reg29, ptr, sizeof(long), 0);
-        *ptr++ = ';';
-
-        *ptr++ = 0;
-        putpacket(output_buffer);       /* send it off... */
-
-        /*
-         * Wait for input from remote GDB
-         */
-        while (1) {
-                output_buffer[0] = 0;
-                getpacket(input_buffer);
-
-                switch (input_buffer[0])
-                {
-                case '?':
-                        output_buffer[0] = 'S';
-                        output_buffer[1] = hexchars[sigval >> 4];
-                        output_buffer[2] = hexchars[sigval & 0xf];
-                        output_buffer[3] = 0;
-                        break;
-
-                /*
-                 * Detach debugger; let CPU run
-                 */
-                case 'D':
-                        putpacket(output_buffer);
-                        goto finish_kgdb;
-                        break;
-
-                case 'd':
-                        /* toggle debug flag */
-                        break;
-
-                /*
-                 * Return the value of the CPU registers
-                 */
-                case 'g':
-                        ptr = output_buffer;
-                        ptr = mem2hex((char *)&regs->reg0, ptr, 32*sizeof(long), 0); /* r0...r31 */
-                        ptr = mem2hex((char *)&regs->cp0_status, ptr, 6*sizeof(long), 0); /* cp0 */
-                        ptr = mem2hex((char *)&regs->fpr0, ptr, 32*sizeof(long), 0); /* f0...31 */
-                        ptr = mem2hex((char *)&regs->cp1_fsr, ptr, 2*sizeof(long), 0); /* cp1 */
-                        ptr = mem2hex((char *)&regs->frame_ptr, ptr, 2*sizeof(long), 0); /* frp */
-                        ptr = mem2hex((char *)&regs->cp0_index, ptr, 16*sizeof(long), 0); /* cp0 */
-                        break;
-
-                /*
-                 * set the value of the CPU registers - return OK
-                 */
-                case 'G':
-                {
-                        ptr = &input_buffer[1];
-                        hex2mem(ptr, (char *)&regs->reg0, 32*sizeof(long), 0, 0);
-                        ptr += 32*(2*sizeof(long));
-                        hex2mem(ptr, (char *)&regs->cp0_status, 6*sizeof(long), 0, 0);
-                        ptr += 6*(2*sizeof(long));
-                        hex2mem(ptr, (char *)&regs->fpr0, 32*sizeof(long), 0, 0);
-                        ptr += 32*(2*sizeof(long));
-                        hex2mem(ptr, (char *)&regs->cp1_fsr, 2*sizeof(long), 0, 0);
-                        ptr += 2*(2*sizeof(long));
-                        hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0);
-                        ptr += 2*(2*sizeof(long));
-                        hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0);
-                        strcpy(output_buffer, "OK");
-                 }
-                break;
-
-                /*
-                 * mAA..AA,LLLL  Read LLLL bytes at address AA..AA
-                 */
-                case 'm':
-                        ptr = &input_buffer[1];
-
-                        if (hexToLong(&ptr, &addr)
-                                && *ptr++ == ','
-                                && hexToInt(&ptr, &length)) {
-                                if (mem2hex((char *)addr, output_buffer, length, 1))
-                                        break;
-                                strcpy(output_buffer, "E03");
-                        } else
-                                strcpy(output_buffer, "E01");
-                        break;
-
-                /*
-                 * XAA..AA,LLLL: Write LLLL escaped binary bytes at address AA.AA
-                 */
-                case 'X':
-                        bflag = 1;
-                        /* fall through */
-
-                /*
-                 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK
-                 */
-                case 'M':
-                        ptr = &input_buffer[1];
-
-                        if (hexToLong(&ptr, &addr)
-                                && *ptr++ == ','
-                                && hexToInt(&ptr, &length)
-                                && *ptr++ == ':') {
-                                if (hex2mem(ptr, (char *)addr, length, bflag, 1))
-                                        strcpy(output_buffer, "OK");
-                                else
-                                        strcpy(output_buffer, "E03");
-                        }
-                        else
-                                strcpy(output_buffer, "E02");
-                        break;
-
-                /*
-                 * cAA..AA    Continue at address AA..AA(optional)
-                 */
-                case 'c':
-                        /* try to read optional parameter, pc unchanged if no parm */
-
-                        ptr = &input_buffer[1];
-                        if (hexToLong(&ptr, &addr))
-                                regs->cp0_epc = addr;
-
-                        goto exit_kgdb_exception;
-                        break;
-
-                /*
-                 * kill the program; let us try to restart the machine
-                 * Reset the whole machine.
-                 */
-                case 'k':
-                case 'r':
-                        machine_restart("kgdb restarts machine");
-                        break;
-
-                /*
-                 * Step to next instruction
-                 */
-                case 's':
-                        /*
-                         * There is no single step insn in the MIPS ISA, so we
-                         * use breakpoints and continue, instead.
-                         */
-                        single_step(regs);
-                        goto exit_kgdb_exception;
-                        /* NOTREACHED */
-                        break;
-
-                /*
-                 * Set baud rate (bBB)
-                 * FIXME: Needs to be written
-                 */
-                case 'b':
-                {
-#if 0
-                        int baudrate;
-                        extern void set_timer_3();
-
-                        ptr = &input_buffer[1];
-                        if (!hexToInt(&ptr, &baudrate))
-                        {
-                                strcpy(output_buffer, "B01");
-                                break;
-                        }
-
-                        /* Convert baud rate to uart clock divider */
-
-                        switch (baudrate)
-                        {
-                                case 38400:
-                                        baudrate = 16;
-                                        break;
-                                case 19200:
-                                        baudrate = 33;
-                                        break;
-                                case 9600:
-                                        baudrate = 65;
-                                        break;
-                                default:
-                                        baudrate = 0;
-                                        strcpy(output_buffer, "B02");
-                                        goto x1;
-                        }
-
-                        if (baudrate) {
-                                putpacket("OK");        /* Ack before changing speed */
-                                set_timer_3(baudrate); /* Set it */
-                        }
-#endif
-                }
-                break;
-
-                }                       /* switch */
-
-                /*
-                 * reply to the request
-                 */
-
-                putpacket(output_buffer);
-
-        } /* while */
-
-        return;
-
-finish_kgdb:
-        restore_debug_traps();
-
-exit_kgdb_exception:
-        /* release locks so other CPUs can go */
-        for_each_online_cpu(i)
-                __raw_spin_unlock(&kgdb_cpulock[i]);
-        spin_unlock(&kgdb_lock);
-
-        __flush_cache_all();
-        return;
-}
-
-/*
- * This function will generate a breakpoint exception.  It is used at the
- * beginning of a program to sync up with a debugger and can be used
- * otherwise as a quick means to stop program execution and "break" into
- * the debugger.
- */
-void breakpoint(void)
-{
-        if (!initialized)
-                return;
-
-        __asm__ __volatile__(
-                        ".globl breakinst\n\t"
-                        ".set\tnoreorder\n\t"
-                        "nop\n"
-                        "breakinst:\tbreak\n\t"
-                        "nop\n\t"
-                        ".set\treorder"
-                        );
-}
-
-/* Nothing but the break; don't pollute any registers */
-void async_breakpoint(void)
-{
-        __asm__ __volatile__(
-                        ".globl async_breakinst\n\t"
-                        ".set\tnoreorder\n\t"
-                        "nop\n"
-                        "async_breakinst:\tbreak\n\t"
-                        "nop\n\t"
-                        ".set\treorder"
-                        );
-}
-
-void adel(void)
-{
-        __asm__ __volatile__(
-                        ".globl\tadel\n\t"
-                        "lui\t$8,0x8000\n\t"
-                        "lw\t$9,1($8)\n\t"
-                        );
-}
-
-/*
- * malloc is needed by gdb client in "call func()", even a private one
- * will make gdb happy
- */
-static void __used *malloc(size_t size)
-{
-        return kmalloc(size, GFP_ATOMIC);
-}
-
-static void __used free(void *where)
-{
-        kfree(where);
-}
-
-#ifdef CONFIG_GDB_CONSOLE
-
-void gdb_putsn(const char *str, int l)
-{
-        char outbuf[18];
-
-        if (!kgdb_started)
-                return;
-
-        outbuf[0]='O';
-
-        while(l) {
-                int i = (l>8)?8:l;
-                mem2hex((char *)str, &outbuf[1], i, 0);
-                outbuf[(i*2)+1]=0;
-                putpacket(outbuf);
-                str += i;
-                l -= i;
-        }
-}
-
-static void gdb_console_write(struct console *con, const char *s, unsigned n)
-{
-        gdb_putsn(s, n);
-}
-
-static struct console gdb_console = {
-        .name   = "gdb",
-        .write  = gdb_console_write,
-        .flags  = CON_PRINTBUFFER,
-        .index  = -1
-};
-
-static int __init register_gdb_console(void)
-{
-        register_console(&gdb_console);
-
-        return 0;
-}
-
-console_initcall(register_gdb_console);
-
-#endif
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 6045b9a51a35..4b4007b3083a 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -21,11 +21,16 @@
 #include <linux/sched.h>
 #include <linux/seq_file.h>
 #include <linux/kallsyms.h>
+#include <linux/kgdb.h>
 
 #include <asm/atomic.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
 
+#ifdef CONFIG_KGDB
+int kgdb_early_setup;
+#endif
+
 static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
 
 int allocate_irqno(void)
@@ -126,33 +131,22 @@ asmlinkage void spurious_interrupt(void)
         atomic_inc(&irq_err_count);
 }
 
-#ifdef CONFIG_KGDB
-extern void breakpoint(void);
-extern void set_debug_traps(void);
-
-static int kgdb_flag = 1;
-static int __init nokgdb(char *str)
-{
-        kgdb_flag = 0;
-        return 1;
-}
-__setup("nokgdb", nokgdb);
-#endif
-
 void __init init_IRQ(void)
 {
         int i;
 
+#ifdef CONFIG_KGDB
+        if (kgdb_early_setup)
+                return;
+#endif
+
         for (i = 0; i < NR_IRQS; i++)
                 set_irq_noprobe(i);
 
         arch_init_irq();
 
 #ifdef CONFIG_KGDB
-        if (kgdb_flag) {
-                printk("Wait for gdb client connection ...\n");
-                set_debug_traps();
-                breakpoint();
-        }
+        if (!kgdb_early_setup)
+                kgdb_early_setup = 1;
 #endif
 }
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
new file mode 100644
index 000000000000..c5a8b2d21ca4
--- /dev/null
+++ b/arch/mips/kernel/kgdb.c
@@ -0,0 +1,281 @@
+/*
+ *  Originally written by Glenn Engel, Lake Stevens Instrument Division
+ *
+ *  Contributed by HP Systems
+ *
+ *  Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
+ *  Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
+ *
+ *  Copyright (C) 1995 Andreas Busse
+ *
+ *  Copyright (C) 2003 MontaVista Software Inc.
+ *  Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ *  Copyright (C) 2004-2005 MontaVista Software Inc.
+ *  Author: Manish Lachwani, mlachwani@mvista.com or manish@koffee-break.com
+ *
+ *  Copyright (C) 2007-2008 Wind River Systems, Inc.
+ *  Author/Maintainer: Jason Wessel, jason.wessel@windriver.com
+ *
+ *  This file is licensed under the terms of the GNU General Public License
+ *  version 2. This program is licensed "as is" without any warranty of any
+ *  kind, whether express or implied.
+ */
+
+#include <linux/ptrace.h>               /* for linux pt_regs struct */
+#include <linux/kgdb.h>
+#include <linux/kdebug.h>
+#include <linux/sched.h>
+#include <asm/inst.h>
+#include <asm/fpu.h>
+#include <asm/cacheflush.h>
+#include <asm/processor.h>
+#include <asm/sigcontext.h>
+
+static struct hard_trap_info {
+        unsigned char tt;       /* Trap type code for MIPS R3xxx and R4xxx */
+        unsigned char signo;    /* Signal that we map this trap into */
+} hard_trap_info[] = {
+        { 6, SIGBUS },          /* instruction bus error */
+        { 7, SIGBUS },          /* data bus error */
+        { 9, SIGTRAP },         /* break */
+/*      { 11, SIGILL }, */      /* CPU unusable */
+        { 12, SIGFPE },         /* overflow */
+        { 13, SIGTRAP },        /* trap */
+        { 14, SIGSEGV },        /* virtual instruction cache coherency */
+        { 15, SIGFPE },         /* floating point exception */
+        { 23, SIGSEGV },        /* watch */
+        { 31, SIGSEGV },        /* virtual data cache coherency */
+        { 0, 0}                 /* Must be last */
+};
+
+void arch_kgdb_breakpoint(void)
+{
+        __asm__ __volatile__(
+                ".globl breakinst\n\t"
+                ".set\tnoreorder\n\t"
+                "nop\n"
+                "breakinst:\tbreak\n\t"
+                "nop\n\t"
+                ".set\treorder");
+}
+
+static void kgdb_call_nmi_hook(void *ignored)
+{
+        kgdb_nmicallback(raw_smp_processor_id(), (void *)0);
+}
+
+void kgdb_roundup_cpus(unsigned long flags)
+{
+        local_irq_enable();
+        smp_call_function(kgdb_call_nmi_hook, NULL, NULL);
+        local_irq_disable();
+}
+
+static int compute_signal(int tt)
+{
+        struct hard_trap_info *ht;
+
+        for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
+                if (ht->tt == tt)
+                        return ht->signo;
+
+        return SIGHUP;          /* default for things we don't know about */
+}
+
+void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        int reg;
+
+#if (KGDB_GDB_REG_SIZE == 32)
+        u32 *ptr = (u32 *)gdb_regs;
+#else
+        u64 *ptr = (u64 *)gdb_regs;
+#endif
+
+        for (reg = 0; reg < 32; reg++)
+                *(ptr++) = regs->regs[reg];
+
+        *(ptr++) = regs->cp0_status;
+        *(ptr++) = regs->lo;
+        *(ptr++) = regs->hi;
+        *(ptr++) = regs->cp0_badvaddr;
+        *(ptr++) = regs->cp0_cause;
+        *(ptr++) = regs->cp0_epc;
+
+        /* FP REGS */
+        if (!(current && (regs->cp0_status & ST0_CU1)))
+                return;
+
+        save_fp(current);
+        for (reg = 0; reg < 32; reg++)
+                *(ptr++) = current->thread.fpu.fpr[reg];
+}
+
+void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        int reg;
+
+#if (KGDB_GDB_REG_SIZE == 32)
+        const u32 *ptr = (u32 *)gdb_regs;
+#else
+        const u64 *ptr = (u64 *)gdb_regs;
+#endif
+
+        for (reg = 0; reg < 32; reg++)
+                regs->regs[reg] = *(ptr++);
+
+        regs->cp0_status = *(ptr++);
+        regs->lo = *(ptr++);
+        regs->hi = *(ptr++);
+        regs->cp0_badvaddr = *(ptr++);
+        regs->cp0_cause = *(ptr++);
+        regs->cp0_epc = *(ptr++);
+
+        /* FP REGS from current */
+        if (!(current && (regs->cp0_status & ST0_CU1)))
+                return;
+
+        for (reg = 0; reg < 32; reg++)
+                current->thread.fpu.fpr[reg] = *(ptr++);
+        restore_fp(current);
+}
+
+/*
+ * Similar to regs_to_gdb_regs() except that process is sleeping and so
+ * we may not be able to get all the info.
+ */
+void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
+{
+        int reg;
+        struct thread_info *ti = task_thread_info(p);
+        unsigned long ksp = (unsigned long)ti + THREAD_SIZE - 32;
+        struct pt_regs *regs = (struct pt_regs *)ksp - 1;
+#if (KGDB_GDB_REG_SIZE == 32)
+        u32 *ptr = (u32 *)gdb_regs;
+#else
+        u64 *ptr = (u64 *)gdb_regs;
+#endif
+
+        for (reg = 0; reg < 16; reg++)
+                *(ptr++) = regs->regs[reg];
+
+        /* S0 - S7 */
+        for (reg = 16; reg < 24; reg++)
+                *(ptr++) = regs->regs[reg];
+
+        for (reg = 24; reg < 28; reg++)
+                *(ptr++) = 0;
+
+        /* GP, SP, FP, RA */
+        for (reg = 28; reg < 32; reg++)
+                *(ptr++) = regs->regs[reg];
+
+        *(ptr++) = regs->cp0_status;
+        *(ptr++) = regs->lo;
+        *(ptr++) = regs->hi;
+        *(ptr++) = regs->cp0_badvaddr;
+        *(ptr++) = regs->cp0_cause;
+        *(ptr++) = regs->cp0_epc;
+}
+
+/*
+ * Calls linux_debug_hook before the kernel dies. If KGDB is enabled,
+ * then try to fall into the debugger
+ */
+static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
+                            void *ptr)
+{
+        struct die_args *args = (struct die_args *)ptr;
+        struct pt_regs *regs = args->regs;
+        int trap = (regs->cp0_cause & 0x7c) >> 2;
+
+        if (fixup_exception(regs))
+                return NOTIFY_DONE;
+
+        /* Userpace events, ignore. */
+        if (user_mode(regs))
+                return NOTIFY_DONE;
+
+        if (atomic_read(&kgdb_active) != -1)
+                kgdb_nmicallback(smp_processor_id(), regs);
+
+        if (kgdb_handle_exception(trap, compute_signal(trap), 0, regs))
+                return NOTIFY_DONE;
+
+        if (atomic_read(&kgdb_setting_breakpoint))
+                if ((trap == 9) && (regs->cp0_epc == (unsigned long)breakinst))
+                        regs->cp0_epc += 4;
+
+        /* In SMP mode, __flush_cache_all does IPI */
+        local_irq_enable();
+        __flush_cache_all();
+
+        return NOTIFY_STOP;
+}
+
+static struct notifier_block kgdb_notifier = {
+        .notifier_call = kgdb_mips_notify,
+};
+
+/*
+ * Handle the 's' and 'c' commands
+ */
+int kgdb_arch_handle_exception(int vector, int signo, int err_code,
+                               char *remcom_in_buffer, char *remcom_out_buffer,
+                               struct pt_regs *regs)
+{
+        char *ptr;
+        unsigned long address;
+        int cpu = smp_processor_id();
+
+        switch (remcom_in_buffer[0]) {
+        case 's':
+        case 'c':
+                /* handle the optional parameter */
+                ptr = &remcom_in_buffer[1];
+                if (kgdb_hex2long(&ptr, &address))
+                        regs->cp0_epc = address;
+
+                atomic_set(&kgdb_cpu_doing_single_step, -1);
+                if (remcom_in_buffer[0] == 's')
+                        if (kgdb_contthread)
+                                atomic_set(&kgdb_cpu_doing_single_step, cpu);
+
+                return 0;
+        }
+
+        return -1;
+}
+
+struct kgdb_arch arch_kgdb_ops;
+
+/*
+ * We use kgdb_early_setup so that functions we need to call now don't
+ * cause trouble when called again later.
+ */
+int kgdb_arch_init(void)
+{
+        union mips_instruction insn = {
+                .r_format = {
+                        .opcode = spec_op,
+                        .func   = break_op,
+                }
+        };
+        memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE);
+
+        register_die_notifier(&kgdb_notifier);
+
+        return 0;
+}
+
+/*
+ *      kgdb_arch_exit - Perform any architecture specific uninitalization.
+ *
+ *      This function will handle the uninitalization of any architecture
+ *      specific callbacks, for dynamic registration and unregistration.
+ */
+void kgdb_arch_exit(void)
+{
+        unregister_die_notifier(&kgdb_notifier);
+}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b8ea4e9d0d87..426cced1e9dc 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -23,6 +23,8 @@
 #include <linux/bootmem.h>
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
+#include <linux/kgdb.h>
+#include <linux/kdebug.h>
 
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
@@ -425,6 +427,10 @@ asmlinkage void do_be(struct pt_regs *regs)
         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
                data ? "Data" : "Instruction",
                field, regs->cp0_epc, field, regs->regs[31]);
+        if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
+            == NOTIFY_STOP)
+                return;
+
         die_if_kernel("Oops", regs);
         force_sig(SIGBUS, current);
 }
@@ -623,6 +629,9 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 {
         siginfo_t info;
 
+        if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
+            == NOTIFY_STOP)
+                return;
         die_if_kernel("FP exception in kernel code", regs);
 
         if (fcr31 & FPU_CSR_UNI_X) {
@@ -682,6 +691,9 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
         siginfo_t info;
         char b[40];
 
+        if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
+                return;
+
         /*
          * A short test says that IRIX 5.3 sends SIGTRAP for all trap
          * insns, even for trap and break codes that indicate arithmetic
@@ -762,6 +774,10 @@ asmlinkage void do_ri(struct pt_regs *regs)
         unsigned int opcode = 0;
         int status = -1;
 
+        if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
+            == NOTIFY_STOP)
+                return;
+
         die_if_kernel("Reserved instruction in kernel code", regs);
 
         if (unlikely(compute_return_epc(regs) < 0))
@@ -1537,6 +1553,11 @@ void __init trap_init(void)
         extern char except_vec4;
         unsigned long i;
 
+#if defined(CONFIG_KGDB)
+        if (kgdb_early_setup)
+                return; /* Already done */
+#endif
+
         if (cpu_has_veic || cpu_has_vint)
                 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
         else
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index a782549ac80e..f0cf46adb978 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -246,10 +246,6 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
                 old_pagemask = read_c0_pagemask();
                 w = read_c0_wired();
                 write_c0_wired(w + 1);
-                if (read_c0_wired() != w + 1) {
-                        printk("[tlbwired] No WIRED reg?\n");
-                        return;
-                }
                 write_c0_index(w << 8);
                 write_c0_pagemask(pagemask);
                 write_c0_entryhi(entryhi);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index f8064446e812..3b7dd722c32a 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -13,7 +13,6 @@ obj-y				:= malta-amon.o malta-cmdline.o \
 
 obj-$(CONFIG_EARLY_PRINTK)      += malta-console.o
 obj-$(CONFIG_PCI)               += malta-pci.o
-obj-$(CONFIG_KGDB)              += malta-kgdb.o
 
 # FIXME FIXME FIXME
 obj-$(CONFIG_MIPS_MT_SMTC)      += malta_smtc.o
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index c0653021a171..4832af251668 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -37,15 +37,6 @@
 
 #include <asm/mips-boards/malta.h>
 
-#ifdef CONFIG_KGDB
-extern int rs_kgdb_hook(int, int);
-extern int rs_putDebugChar(char);
-extern char rs_getDebugChar(void);
-extern int saa9730_kgdb_hook(int);
-extern int saa9730_putDebugChar(char);
-extern char saa9730_getDebugChar(void);
-#endif
-
 int prom_argc;
 int *_prom_argv, *_prom_envp;
 
@@ -173,51 +164,6 @@ static void __init console_config(void)
 }
 #endif
 
-#ifdef CONFIG_KGDB
-void __init kgdb_config(void)
-{
-        extern int (*generic_putDebugChar)(char);
-        extern char (*generic_getDebugChar)(void);
-        char *argptr;
-        int line, speed;
-
-        argptr = prom_getcmdline();
-        if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
-                argptr += strlen("kgdb=ttyS");
-                if (*argptr != '0' && *argptr != '1')
-                        printk("KGDB: Unknown serial line /dev/ttyS%c, "
-                               "falling back to /dev/ttyS1\n", *argptr);
-                line = *argptr == '0' ? 0 : 1;
-                printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
-
-                speed = 0;
-                if (*++argptr == ',')
-                {
-                        int c;
-                        while ((c = *++argptr) && ('0' <= c && c <= '9'))
-                                speed = speed * 10 + c - '0';
-                }
-                {
-                        speed = rs_kgdb_hook(line, speed);
-                        generic_putDebugChar = rs_putDebugChar;
-                        generic_getDebugChar = rs_getDebugChar;
-                }
-
-                pr_info("KGDB: Using serial line /dev/ttyS%d at %d for "
-                        "session, please connect your debugger\n",
-                        line ? 1 : 0, speed);
-
-                {
-                        char *s;
-                        for (s = "Please connect GDB to this port\r\n"; *s; )
-                                generic_putDebugChar(*s++);
-                }
-
-                /* Breakpoint is invoked after interrupts are initialised */
-        }
-}
-#endif
-
 static void __init mips_nmi_setup(void)
 {
         void *base;
diff --git a/arch/mips/mti-malta/malta-kgdb.c b/arch/mips/mti-malta/malta-kgdb.c
deleted file mode 100644
index 6a1854de4579..000000000000
--- a/arch/mips/mti-malta/malta-kgdb.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * This is the interface to the remote debugger stub.
- */
-#include <linux/types.h>
-#include <linux/serial.h>
-#include <linux/serialP.h>
-#include <linux/serial_reg.h>
-
-#include <asm/serial.h>
-#include <asm/io.h>
-
-static struct serial_state rs_table[] = {
-        SERIAL_PORT_DFNS        /* Defined in serial.h */
-};
-
-static struct async_struct kdb_port_info = {0};
-
-int (*generic_putDebugChar)(char);
-char (*generic_getDebugChar)(void);
-
-static __inline__ unsigned int serial_in(struct async_struct *info, int offset)
-{
-        return inb(info->port + offset);
-}
-
-static __inline__ void serial_out(struct async_struct *info, int offset,
-                                int value)
-{
-        outb(value, info->port+offset);
-}
-
-int rs_kgdb_hook(int tty_no, int speed) {
-        int t;
-        struct serial_state *ser = &rs_table[tty_no];
-
-        kdb_port_info.state = ser;
-        kdb_port_info.magic = SERIAL_MAGIC;
-        kdb_port_info.port = ser->port;
-        kdb_port_info.flags = ser->flags;
-
-        /*
-         * Clear all interrupts
-         */
-        serial_in(&kdb_port_info, UART_LSR);
-        serial_in(&kdb_port_info, UART_RX);
-        serial_in(&kdb_port_info, UART_IIR);
-        serial_in(&kdb_port_info, UART_MSR);
-
-        /*
-         * Now, initialize the UART
-         */
-        serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);   /* reset DLAB */
-        if (kdb_port_info.flags & ASYNC_FOURPORT) {
-                kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS;
-                t = UART_MCR_DTR | UART_MCR_OUT1;
-        } else {
-                kdb_port_info.MCR
-                        = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2;
-                t = UART_MCR_DTR | UART_MCR_RTS;
-        }
-
-        kdb_port_info.MCR = t;          /* no interrupts, please */
-        serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR);
-
-        /*
-         * and set the speed of the serial port
-         */
-        if (speed == 0)
-                speed = 9600;
-
-        t = kdb_port_info.state->baud_base / speed;
-        /* set DLAB */
-        serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB);
-        serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */
-        serial_out(&kdb_port_info, UART_DLM, t >> 8);  /* MS of divisor */
-        /* reset DLAB */
-        serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);
-
-        return speed;
-}
-
-int putDebugChar(char c)
-{
-        return generic_putDebugChar(c);
-}
-
-char getDebugChar(void)
-{
-        return generic_getDebugChar();
-}
-
-int rs_putDebugChar(char c)
-{
-
-        if (!kdb_port_info.state) {     /* need to init device first */
-                return 0;
-        }
-
-        while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0)
-                ;
-
-        serial_out(&kdb_port_info, UART_TX, c);
-
-        return 1;
-}
-
-char rs_getDebugChar(void)
-{
-        if (!kdb_port_info.state) {     /* need to init device first */
-                return 0;
-        }
-
-        while (!(serial_in(&kdb_port_info, UART_LSR) & 1))
-                ;
-
-        return serial_in(&kdb_port_info, UART_RX);
-}
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index e7cad54936ca..dc78b8983eeb 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -199,10 +199,6 @@ void __init plat_mem_setup(void)
          */
         enable_dma(4);
 
-#ifdef CONFIG_KGDB
-        kgdb_config();
-#endif
-
 #ifdef CONFIG_DMA_COHERENT
         if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
                 panic("Hardware DMA cache coherency not supported");
diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/nxp/pnx8550/common/Makefile
index 31cc1a5cec3b..dd9e7b1f7fd3 100644
--- a/arch/mips/nxp/pnx8550/common/Makefile
+++ b/arch/mips/nxp/pnx8550/common/Makefile
@@ -24,6 +24,5 @@
 
 obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
 obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_KGDB) += gdb_hook.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/common/gdb_hook.c b/arch/mips/nxp/pnx8550/common/gdb_hook.c
deleted file mode 100644
index ad4624f6d9bc..000000000000
--- a/arch/mips/nxp/pnx8550/common/gdb_hook.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * This is the interface to the remote debugger stub.
- *
- */
-#include <linux/types.h>
-#include <linux/serial.h>
-#include <linux/serialP.h>
-#include <linux/serial_reg.h>
-#include <linux/serial_ip3106.h>
-
-#include <asm/serial.h>
-#include <asm/io.h>
-
-#include <uart.h>
-
-static struct serial_state rs_table[IP3106_NR_PORTS] = {
-};
-static struct async_struct kdb_port_info = {0};
-
-void rs_kgdb_hook(int tty_no)
-{
-        struct serial_state *ser = &rs_table[tty_no];
-
-        kdb_port_info.state = ser;
-        kdb_port_info.magic = SERIAL_MAGIC;
-        kdb_port_info.port  = tty_no;
-        kdb_port_info.flags = ser->flags;
-
-        /*
-         * Clear all interrupts
-         */
-        /* Clear all the transmitter FIFO counters (pointer and status) */
-        ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST;
-        /* Clear all the receiver FIFO counters (pointer and status) */
-        ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST;
-        /* Clear all interrupts */
-        ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX |
-                IP3106_UART_INT_ALLTX;
-
-        /*
-         * Now, initialize the UART
-         */
-        ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT;
-        ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud
-}
-
-int putDebugChar(char c)
-{
-        /* Wait until FIFO not full */
-        while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
-                ;
-        /* Send one char */
-        ip3106_fifo(UART_BASE, kdb_port_info.port) = c;
-
-        return 1;
-}
-
-char getDebugChar(void)
-{
-        char ch;
-
-        /* Wait until there is a char in the FIFO */
-        while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) &
-                                        IP3106_UART_FIFO_RXFIFO) >> 8))
-                ;
-        /* Read one char */
-        ch = ip3106_fifo(UART_BASE, kdb_port_info.port) &
-                IP3106_UART_FIFO_RBRTHR;
-        /* Advance the RX FIFO read pointer */
-        ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT;
-        return (ch);
-}
-
-void rs_disable_debug_interrupts(void)
-{
-        ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */
-}
-
-void rs_enable_debug_interrupts(void)
-{
-        /* Clear all the transmitter FIFO counters (pointer and status) */
-        ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST;
-        /* Clear all the receiver FIFO counters (pointer and status) */
-        ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST;
-        /* Clear all interrupts */
-        ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX |
-                IP3106_UART_INT_ALLTX;
-        ip3106_ien(UART_BASE, kdb_port_info.port)  = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */
-}
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c
index aad03429a5e3..f080f114a1bf 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/nxp/pnx8550/common/int.c
@@ -34,7 +34,6 @@
 #include <linux/module.h>
 
 #include <asm/io.h>
-#include <asm/gdb-stub.h>
 #include <int.h>
 #include <uart.h>
 
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/nxp/pnx8550/common/proc.c
index 18b125e3b65d..acf1fa889444 100644
--- a/arch/mips/nxp/pnx8550/common/proc.c
+++ b/arch/mips/nxp/pnx8550/common/proc.c
@@ -22,7 +22,6 @@
 #include <linux/random.h>
 
 #include <asm/io.h>
-#include <asm/gdb-stub.h>
 #include <int.h>
 #include <uart.h>
 
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
index 92d764c97701..2aed50fef10f 100644
--- a/arch/mips/nxp/pnx8550/common/setup.c
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void);
 extern void pnx8550_machine_power_off(void);
 extern struct resource ioport_resource;
 extern struct resource iomem_resource;
-extern void rs_kgdb_hook(int tty_no);
 extern char *prom_getcmdline(void);
 
 struct resource standard_io_resources[] = {
@@ -142,16 +141,5 @@ void __init plat_mem_setup(void)
                 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
         }
 
-#ifdef CONFIG_KGDB
-        argptr = prom_getcmdline();
-        if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
-                int line;
-                argptr += strlen("kgdb=ttyS");
-                line = *argptr == '0' ? 0 : 1;
-                rs_kgdb_hook(line);
-                pr_info("KGDB: Using ttyS%i for session, "
-                        "please connect your debugger\n", line ? 1 : 0);
-        }
-#endif
         return;
 }
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index 8a17a39e5bf2..31c150196595 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -37,45 +37,48 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 
 #include <asm/addrspace.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/pci.h>
 #include <asm/txx9/tx3927.h>
 
-static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
-        unsigned char where)
+static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where)
 {
-        if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) |
-                              ((dev_fn & 0xff) << 0x08) |
-                              (where & 0xfc);
+        if (bus->parent == NULL &&
+            devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
+                return -1;
+        tx3927_pcicptr->ica =
+                ((bus->number & 0xff) << 0x10) |
+                ((devfn & 0xff) << 0x08) |
+                (where & 0xfc) | (bus->parent ? 1 : 0);
 
         /* clear M_ABORT and Disable M_ABORT Int. */
         tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
         tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
-
-        return PCIBIOS_SUCCESSFUL;
+        return 0;
 }
 
 static inline int check_abort(void)
 {
-        if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
+        if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
                 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
                 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
+                /* flush write buffer */
+                iob();
                 return PCIBIOS_DEVICE_NOT_FOUND;
-
+        }
         return PCIBIOS_SUCCESSFUL;
 }
 
 static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
         int where, int size, u32 * val)
 {
-        int ret;
-
-        ret = mkaddr(bus->number, devfn, where);
-        if (ret)
-                return ret;
+        if (mkaddr(bus, devfn, where)) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
 
         switch (size) {
         case 1:
@@ -97,11 +100,8 @@ static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
         int where, int size, u32 val)
 {
-        int ret;
-
-        ret = mkaddr(bus->number, devfn, where);
-        if (ret)
-                return ret;
+        if (mkaddr(bus, devfn, where))
+                return PCIBIOS_DEVICE_NOT_FOUND;
 
         switch (size) {
         case 1:
@@ -117,11 +117,6 @@ static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                 tx3927_pcicptr->icd = cpu_to_le32(val);
         }
 
-        if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
-                tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
-                tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
         return check_abort();
 }
 
@@ -202,3 +197,34 @@ void __init tx3927_pcic_setup(struct pci_controller *channel,
                 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
         local_irq_restore(flags);
 }
+
+static irqreturn_t tx3927_pcierr_interrupt(int irq, void *dev_id)
+{
+        struct pt_regs *regs = get_irq_regs();
+
+        if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
+                printk(KERN_WARNING "PCI error interrupt at 0x%08lx.\n",
+                       regs->cp0_epc);
+                printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
+                       tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
+        }
+        if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
+                /* clear all pci errors */
+                tx3927_pcicptr->pcistat |= TX3927_PCIC_PCISTATIM_ALL;
+                tx3927_pcicptr->istat = TX3927_PCIC_IIM_ALL;
+                tx3927_pcicptr->tstat = TX3927_PCIC_TIM_ALL;
+                tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
+                return IRQ_HANDLED;
+        }
+        console_verbose();
+        panic("PCI error.");
+}
+
+void __init tx3927_setup_pcierr_irq(void)
+{
+        if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI,
+                        tx3927_pcierr_interrupt,
+                        IRQF_DISABLED, "PCI error",
+                        (void *)TX3927_PCIC_REG))
+                printk(KERN_WARNING "Failed to request irq for PCIERR\n");
+}
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index c6b49bccd274..5989e747527f 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -16,6 +16,8 @@
  * option) any later version.
  */
 #include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <asm/txx9/pci.h>
 #include <asm/txx9/tx4927pcic.h>
 
 static struct {
@@ -85,6 +87,8 @@ static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
                 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
                              | (PCI_STATUS_REC_MASTER_ABORT << 16),
                              &pcicptr->pcistatus);
+                /* flush write buffer */
+                iob();
                 code = PCIBIOS_DEVICE_NOT_FOUND;
         }
         return code;
@@ -192,6 +196,28 @@ static struct {
         .gbwc = 0xfe0,  /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
 };
 
+char *__devinit tx4927_pcibios_setup(char *str)
+{
+        unsigned long val;
+
+        if (!strncmp(str, "trdyto=", 7)) {
+                if (strict_strtoul(str + 7, 0, &val) == 0)
+                        tx4927_pci_opts.trdyto = val;
+                return NULL;
+        }
+        if (!strncmp(str, "retryto=", 8)) {
+                if (strict_strtoul(str + 8, 0, &val) == 0)
+                        tx4927_pci_opts.retryto = val;
+                return NULL;
+        }
+        if (!strncmp(str, "gbwc=", 5)) {
+                if (strict_strtoul(str + 5, 0, &val) == 0)
+                        tx4927_pci_opts.gbwc = val;
+                return NULL;
+        }
+        return str;
+}
+
 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
                               struct pci_controller *channel, int extarb)
 {
@@ -406,3 +432,95 @@ void tx4927_report_pcic_status(void)
                         tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
         }
 }
+
+static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
+{
+        int i;
+        __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
+
+        printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
+        for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
+                if (i % 32 == 0) {
+                        printk(KERN_CONT "\n");
+                        printk(KERN_INFO "%04x:", i);
+                }
+                /* skip registers with side-effects */
+                if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
+                    || i == offsetof(struct tx4927_pcic_reg, g2pspc)
+                    || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
+                    || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
+                        printk(KERN_CONT " XXXXXXXX");
+                        continue;
+                }
+                printk(KERN_CONT " %08x", __raw_readl(preg));
+        }
+        printk(KERN_CONT "\n");
+}
+
+void tx4927_dump_pcic_settings(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
+                if (pcicptrs[i].pcicptr)
+                        tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
+        }
+}
+
+irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
+{
+        struct pt_regs *regs = get_irq_regs();
+        struct tx4927_pcic_reg __iomem *pcicptr =
+                (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
+
+        if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
+                printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
+                       (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
+                tx4927_report_pcic_status1(pcicptr);
+        }
+        if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
+                /* clear all pci errors */
+                __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
+                             | (TX4927_PCIC_PCISTATUS_ALL << 16),
+                             &pcicptr->pcistatus);
+                __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
+                __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
+                __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
+                return IRQ_HANDLED;
+        }
+        console_verbose();
+        tx4927_dump_pcic_settings1(pcicptr);
+        panic("PCI error.");
+}
+
+#ifdef CONFIG_TOSHIBA_FPCIB0
+static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
+{
+        struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
+
+        if (!pcicptr)
+                return;
+        if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
+                /* Reset Bus Arbiter */
+                __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
+                /*
+                 * swap reqBP and reqXP (raise priority of SLC90E66).
+                 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
+                 * PCI Backplane board.
+                 */
+                __raw_writel(0x72543610, &pcicptr->pbareqport);
+                __raw_writel(0, &pcicptr->pbabm);
+                /* Use Fixed ParkMaster (required by SLC90E66) */
+                __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
+                /* Enable Bus Arbiter */
+                __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
+                             TX4927_PCIC_PBACFG_PBAEN,
+                             &pcicptr->pbacfg);
+                printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
+                       __raw_readl(&pcicptr->pbareqport));
+        }
+}
+#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
+        tx4927_quirk_slc90e66_bridge);
+#endif
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
index 27e86a09dd41..aaa900596792 100644
--- a/arch/mips/pci/pci-tx4927.c
+++ b/arch/mips/pci/pci-tx4927.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
+#include <linux/interrupt.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/tx4927.h>
 
@@ -81,3 +82,12 @@ int __init tx4927_pciclk66_setup(void)
                 pciclk = -1;
         return pciclk;
 }
+
+void __init tx4927_setup_pcierr_irq(void)
+{
+        if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR,
+                        tx4927_pcierr_interrupt,
+                        IRQF_DISABLED, "PCI error",
+                        (void *)TX4927_PCIC_REG))
+                printk(KERN_WARNING "Failed to request irq for PCIERR\n");
+}
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
index e5375511c2b7..60e2c52c2c5e 100644
--- a/arch/mips/pci/pci-tx4938.c
+++ b/arch/mips/pci/pci-tx4938.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
+#include <linux/interrupt.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/tx4938.h>
 
@@ -132,3 +133,12 @@ int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
         }
         return -1;
 }
+
+void __init tx4938_setup_pcierr_irq(void)
+{
+        if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR,
+                        tx4927_pcierr_interrupt,
+                        IRQF_DISABLED, "PCI error",
+                        (void *)TX4927_PCIC_REG))
+                printk(KERN_WARNING "Failed to request irq for PCIERR\n");
+}
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 77bd5b68dc43..c7fe6ec621e6 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -328,7 +328,11 @@ EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 #endif
 
-char *pcibios_setup(char *str)
+char * (*pcibios_plat_setup)(char *str) __devinitdata;
+
+char *__devinit pcibios_setup(char *str)
 {
+        if (pcibios_plat_setup)
+                return pcibios_plat_setup(str);
         return str;
 }
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index 9de34302e5f4..f7261628d8a6 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -38,68 +38,6 @@
 #include <msp_int.h>
 #include <msp_regs.h>
 
-#ifdef CONFIG_KGDB
-/*
- * kgdb uses serial port 1 so the console can remain on port 0.
- * To use port 0 change the definition to read as follows:
- * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
- */
-#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
-
-int putDebugChar(char c)
-{
-        volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
-        uint32_t val = (uint32_t)c;
-
-        local_irq_disable();
-        while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
-        uart[0] = val;
-        while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
-        local_irq_enable();
-
-        return 1;
-}
-
-char getDebugChar(void)
-{
-        volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
-        uint32_t val;
-
-        while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
-        val = uart[0];
-
-        return (char)val;
-}
-
-void initDebugPort(unsigned int uartclk, unsigned int baudrate)
-{
-        unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
-
-        /* Enable FIFOs */
-        writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
-                        UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
-                (char *)DEBUG_PORT_BASE + (UART_FCR * 4));
-
-        /* Select brtc divisor */
-        writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
-
-        /* Store divisor lsb */
-        writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
-
-        /* Store divisor msb */
-        writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
-
-        /* Set 8N1 mode */
-        writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
-
-        /* Disable flow control */
-        writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
-
-        /* Disable receive interrupt(!) */
-        writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
-}
-#endif
-
 void __init msp_serial_setup(void)
 {
         char    *s;
@@ -139,17 +77,6 @@ void __init msp_serial_setup(void)
                 case MACH_MSP7120_FPGA:
                         /* Enable UART1 on MSP4200 and MSP7120 */
                         *GPIO_CFG2_REG = 0x00002299;
-
-#ifdef CONFIG_KGDB
-                        /* Initialize UART1 for kgdb since PMON doesn't */
-                        if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
-                                if( mips_machtype == MACH_MSP4200_FPGA
-                                 || mips_machtype == MACH_MSP7120_FPGA )
-                                        initDebugPort(uartclk, 19200);
-                                else
-                                        initDebugPort(uartclk, 57600);
-                        }
-#endif
                         break;
 
                 default:
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
index 8fd9a04e3534..b16f95c3df65 100644
--- a/arch/mips/pmc-sierra/yosemite/Makefile
+++ b/arch/mips/pmc-sierra/yosemite/Makefile
@@ -4,7 +4,6 @@
 
 obj-y    += irq.o prom.o py-console.o setup.o
 
-obj-$(CONFIG_KGDB)              += dbg_io.o
 obj-$(CONFIG_SMP)               += smp.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/pmc-sierra/yosemite/dbg_io.c b/arch/mips/pmc-sierra/yosemite/dbg_io.c
deleted file mode 100644
index 6362c702e389..000000000000
--- a/arch/mips/pmc-sierra/yosemite/dbg_io.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Support for KGDB for the Yosemite board. We make use of single serial
- * port to be used for KGDB as well as console. The second serial port
- * seems to be having a problem. Single IRQ is allocated for both the
- * ports. Hence, the interrupt routing code needs to figure out whether
- * the interrupt came from channel A or B.
- */
-
-#include <asm/serial.h>
-
-/*
- * Baud rate, Parity, Data and Stop bit settings for the
- * serial port on the Yosemite. Note that the Early printk
- * patch has been added. So, we should be all set to go
- */
-#define YOSEMITE_BAUD_2400      2400
-#define YOSEMITE_BAUD_4800      4800
-#define YOSEMITE_BAUD_9600      9600
-#define YOSEMITE_BAUD_19200     19200
-#define YOSEMITE_BAUD_38400     38400
-#define YOSEMITE_BAUD_57600     57600
-#define YOSEMITE_BAUD_115200    115200
-
-#define YOSEMITE_PARITY_NONE    0
-#define YOSEMITE_PARITY_ODD     0x08
-#define YOSEMITE_PARITY_EVEN    0x18
-#define YOSEMITE_PARITY_MARK    0x28
-#define YOSEMITE_PARITY_SPACE   0x38
-
-#define YOSEMITE_DATA_5BIT      0x0
-#define YOSEMITE_DATA_6BIT      0x1
-#define YOSEMITE_DATA_7BIT      0x2
-#define YOSEMITE_DATA_8BIT      0x3
-
-#define YOSEMITE_STOP_1BIT      0x0
-#define YOSEMITE_STOP_2BIT      0x4
-
-/* This is crucial */
-#define SERIAL_REG_OFS          0x1
-
-#define SERIAL_RCV_BUFFER       0x0
-#define SERIAL_TRANS_HOLD       0x0
-#define SERIAL_SEND_BUFFER      0x0
-#define SERIAL_INTR_ENABLE      (1 * SERIAL_REG_OFS)
-#define SERIAL_INTR_ID          (2 * SERIAL_REG_OFS)
-#define SERIAL_DATA_FORMAT      (3 * SERIAL_REG_OFS)
-#define SERIAL_LINE_CONTROL     (3 * SERIAL_REG_OFS)
-#define SERIAL_MODEM_CONTROL    (4 * SERIAL_REG_OFS)
-#define SERIAL_RS232_OUTPUT     (4 * SERIAL_REG_OFS)
-#define SERIAL_LINE_STATUS      (5 * SERIAL_REG_OFS)
-#define SERIAL_MODEM_STATUS     (6 * SERIAL_REG_OFS)
-#define SERIAL_RS232_INPUT      (6 * SERIAL_REG_OFS)
-#define SERIAL_SCRATCH_PAD      (7 * SERIAL_REG_OFS)
-
-#define SERIAL_DIVISOR_LSB      (0 * SERIAL_REG_OFS)
-#define SERIAL_DIVISOR_MSB      (1 * SERIAL_REG_OFS)
-
-/*
- * Functions to READ and WRITE to serial port 0
- */
-#define SERIAL_READ(ofs)                (*((volatile unsigned char*)    \
-                                        (TITAN_SERIAL_BASE + ofs)))
-
-#define SERIAL_WRITE(ofs, val)          ((*((volatile unsigned char*)   \
-                                        (TITAN_SERIAL_BASE + ofs))) = val)
-
-/*
- * Functions to READ and WRITE to serial port 1
- */
-#define SERIAL_READ_1(ofs)              (*((volatile unsigned char*)    \
-                                        (TITAN_SERIAL_BASE_1 + ofs)))
-
-#define SERIAL_WRITE_1(ofs, val)        ((*((volatile unsigned char*)   \
-                                        (TITAN_SERIAL_BASE_1 + ofs))) = val)
-
-/*
- * Second serial port initialization
- */
-void init_second_port(void)
-{
-        /* Disable Interrupts */
-        SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
-        SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0x0);
-
-        {
-                unsigned int divisor;
-
-                SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x80);
-                divisor = TITAN_SERIAL_BASE_BAUD / YOSEMITE_BAUD_115200;
-                SERIAL_WRITE_1(SERIAL_DIVISOR_LSB, divisor & 0xff);
-
-                SERIAL_WRITE_1(SERIAL_DIVISOR_MSB,
-                               (divisor & 0xff00) >> 8);
-                SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
-        }
-
-        SERIAL_WRITE_1(SERIAL_DATA_FORMAT, YOSEMITE_DATA_8BIT |
-                       YOSEMITE_PARITY_NONE | YOSEMITE_STOP_1BIT);
-
-        /* Enable Interrupts */
-        SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0xf);
-}
-
-/* Initialize the serial port for KGDB debugging */
-void debugInit(unsigned int baud, unsigned char data, unsigned char parity,
-               unsigned char stop)
-{
-        /* Disable Interrupts */
-        SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
-        SERIAL_WRITE(SERIAL_INTR_ENABLE, 0x0);
-
-        {
-                unsigned int divisor;
-
-                SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x80);
-
-                divisor = TITAN_SERIAL_BASE_BAUD / baud;
-                SERIAL_WRITE(SERIAL_DIVISOR_LSB, divisor & 0xff);
-
-                SERIAL_WRITE(SERIAL_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-                SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
-        }
-
-        SERIAL_WRITE(SERIAL_DATA_FORMAT, data | parity | stop);
-}
-
-static int remoteDebugInitialized = 0;
-
-unsigned char getDebugChar(void)
-{
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(YOSEMITE_BAUD_115200,
-                          YOSEMITE_DATA_8BIT,
-                          YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
-        }
-
-        while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x1) == 0);
-        return SERIAL_READ(SERIAL_RCV_BUFFER);
-}
-
-int putDebugChar(unsigned char byte)
-{
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(YOSEMITE_BAUD_115200,
-                          YOSEMITE_DATA_8BIT,
-                          YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
-        }
-
-        while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x20) == 0);
-        SERIAL_WRITE(SERIAL_SEND_BUFFER, byte);
-
-        return 1;
-}
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index 4decc2807867..5f673eba142c 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -141,10 +141,6 @@ asmlinkage void plat_irq_dispatch(void)
         }
 }
 
-#ifdef CONFIG_KGDB
-extern void init_second_port(void);
-#endif
-
 /*
  * Initialize the next level interrupt handler
  */
@@ -156,11 +152,6 @@ void __init arch_init_irq(void)
         rm7k_cpu_irq_init();
         rm9k_cpu_irq_init();
 
-#ifdef CONFIG_KGDB
-        /* At this point, initialize the second serial port */
-        init_second_port();
-#endif
-
 #ifdef CONFIG_GDB_CONSOLE
         register_gdb_console();
 #endif
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index b2fe82dba0a5..00a1c7877bf4 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -64,7 +64,8 @@ static struct resource rb532_dev3_ctl_res[] = {
 
 void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
 {
-        unsigned flags, data;
+        unsigned long flags;
+        unsigned data;
         unsigned i = 0;
 
         spin_lock_irqsave(&dev3.lock, flags);
@@ -90,7 +91,7 @@ EXPORT_SYMBOL(get_434_reg);
 
 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
 {
-        unsigned flags;
+        unsigned long flags;
 
         spin_lock_irqsave(&dev3.lock, flags);
 
diff --git a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
index db74edf8cefb..8e7a46855b50 100644
--- a/arch/mips/rb532/time.c
+++ b/arch/mips/rb532/time.c
@@ -49,8 +49,8 @@ static unsigned long __init cal_r4koff(void)
 
 void __init plat_time_init(void)
 {
-        unsigned int est_freq, flags;
-        unsigned long r4k_offset;
+        unsigned int est_freq;
+        unsigned long flags, r4k_offset;
 
         local_irq_save(flags);
 
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index 5f389ee26fca..896a1ef84829 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -20,7 +20,6 @@
 #include <asm/irq.h>
 #include <asm/reboot.h>
 #include <asm/time.h>
-#include <asm/gdb-stub.h>
 #include <asm/io.h>
 #include <asm/traps.h>
 #include <asm/sgialib.h>
@@ -81,30 +80,6 @@ void __init plat_mem_setup(void)
                 add_preferred_console("arc", 0, NULL);
         }
 
-#ifdef CONFIG_KGDB
-        {
-        char *kgdb_ttyd = prom_getcmdline();
-
-        if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) {
-                int line;
-                kgdb_ttyd += strlen("kgdb=ttyd");
-                if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2')
-                        printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c"
-                               ", falling back to /dev/ttyd1\n", *kgdb_ttyd);
-                line = *kgdb_ttyd == '2' ? 0 : 1;
-                printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
-                       "session\n", line ? 1 : 2);
-                rs_kgdb_hook(line);
-
-                printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
-                       "session, please connect your debugger\n", line ? 1:2);
-
-                kgdb_enabled = 1;
-                /* Breakpoints and stuff are in sgi_irq_setup() */
-        }
-        }
-#endif
-
 #if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE)
         {
                 ULONG *gfxinfo;
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index e0a6871d56e4..31f4931b8484 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -7,7 +7,6 @@ obj-y	:= ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
            ip27-xtalk.o
 
 obj-$(CONFIG_EARLY_PRINTK)      += ip27-console.o
-obj-$(CONFIG_KGDB)              += ip27-dbgio.o
 obj-$(CONFIG_SMP)               += ip27-smp.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip27/ip27-dbgio.c b/arch/mips/sgi-ip27/ip27-dbgio.c
deleted file mode 100644
index 08fd88b36f80..000000000000
--- a/arch/mips/sgi-ip27/ip27-dbgio.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
- */
-#include <asm/sn/addrs.h>
-#include <asm/sn/sn0/hub.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/ioc3.h>
-#include <asm/sn/sn_private.h>
-
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-
-#define IOC3_CLK        (22000000 / 3)
-#define IOC3_FLAGS      (0)
-
-static inline struct ioc3_uartregs *console_uart(void)
-{
-        struct ioc3 *ioc3;
-
-        ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base;
-
-        return &ioc3->sregs.uarta;
-}
-
-unsigned char getDebugChar(void)
-{
-        struct ioc3_uartregs *uart = console_uart();
-
-        while ((uart->iu_lsr & UART_LSR_DR) == 0);
-        return uart->iu_rbr;
-}
-
-void putDebugChar(unsigned char c)
-{
-        struct ioc3_uartregs *uart = console_uart();
-
-        while ((uart->iu_lsr & UART_LSR_THRE) == 0);
-        uart->iu_thr = c;
-}
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index db372a0f106d..a35818ed4263 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -57,30 +57,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
 extern unsigned long ht_eoi_space;
 #endif
 
-#ifdef CONFIG_KGDB
-#include <asm/gdb-stub.h>
-extern void breakpoint(void);
-static int kgdb_irq;
-#ifdef CONFIG_GDB_CONSOLE
-extern void register_gdb_console(void);
-#endif
-
-/* kgdb is on when configured.  Pass "nokgdb" kernel arg to turn it off */
-static int kgdb_flag = 1;
-static int __init nokgdb(char *str)
-{
-        kgdb_flag = 0;
-        return 1;
-}
-__setup("nokgdb", nokgdb);
-
-/* Default to UART1 */
-int kgdb_port = 1;
-#ifdef CONFIG_SERIAL_SB1250_DUART
-extern char sb1250_duart_present[];
-#endif
-#endif
-
 static struct irq_chip bcm1480_irq_type = {
         .name = "BCM1480-IMR",
         .ack = ack_bcm1480_irq,
@@ -355,61 +331,10 @@ void __init arch_init_irq(void)
          * does its own management of IP7.
          */
 
-#ifdef CONFIG_KGDB
-        imask |= STATUSF_IP6;
-#endif
         /* Enable necessary IPs, disable the rest */
         change_c0_status(ST0_IM, imask);
-
-#ifdef CONFIG_KGDB
-        if (kgdb_flag) {
-                kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
-
-#ifdef CONFIG_SERIAL_SB1250_DUART
-                sb1250_duart_present[kgdb_port] = 0;
-#endif
-                /* Setup uart 1 settings, mapper */
-                /* QQQ FIXME */
-                __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
-
-                __raw_writeq(IMR_IP6_VAL,
-                             IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
-                             (kgdb_irq << 3)));
-                bcm1480_unmask_irq(0, kgdb_irq);
-
-#ifdef CONFIG_GDB_CONSOLE
-                register_gdb_console();
-#endif
-                printk("Waiting for GDB on UART port %d\n", kgdb_port);
-                set_debug_traps();
-                breakpoint();
-        }
-#endif
-}
-
-#ifdef CONFIG_KGDB
-
-#include <linux/delay.h>
-
-#define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
-#define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
-
-static void bcm1480_kgdb_interrupt(void)
-{
-        /*
-         * Clear break-change status (allow some time for the remote
-         * host to stop the break, since we would see another
-         * interrupt on the end-of-break too)
-         */
-        kstat.irqs[smp_processor_id()][kgdb_irq]++;
-        mdelay(500);
-        duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
-                                M_DUART_RX_EN | M_DUART_TX_EN);
-        set_async_breakpoint(&get_irq_regs()->cp0_epc);
 }
 
-#endif  /* CONFIG_KGDB */
-
 extern void bcm1480_mailbox_interrupt(void);
 
 static inline void dispatch_ip2(void)
@@ -462,11 +387,6 @@ asmlinkage void plat_irq_dispatch(void)
                 bcm1480_mailbox_interrupt();
 #endif
 
-#ifdef CONFIG_KGDB
-        else if (pending & CAUSEF_IP6)
-                bcm1480_kgdb_interrupt();               /* KGDB (uart 1) */
-#endif
-
         else if (pending & CAUSEF_IP2)
                 dispatch_ip2();
 }
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index fd9604d5555a..3de30f79db3f 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -59,10 +59,6 @@ int cfe_cons_handle;
 extern unsigned long initrd_start, initrd_end;
 #endif
 
-#ifdef CONFIG_KGDB
-extern int kgdb_port;
-#endif
-
 static void __noreturn cfe_linux_exit(void *arg)
 {
         int warm = *(int *)arg;
@@ -246,9 +242,6 @@ void __init prom_init(void)
         int argc = fw_arg0;
         char **envp = (char **) fw_arg2;
         int *prom_vec = (int *) fw_arg3;
-#ifdef CONFIG_KGDB
-        char *arg;
-#endif
 
         _machine_restart   = cfe_linux_restart;
         _machine_halt      = cfe_linux_halt;
@@ -309,13 +302,6 @@ void __init prom_init(void)
                 }
         }
 
-#ifdef CONFIG_KGDB
-        if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL)
-                kgdb_port = (arg[10] == '0') ? 0 : 1;
-        else
-                kgdb_port = 1;
-#endif
-
 #ifdef CONFIG_BLK_DEV_INITRD
         {
                 char *ptr;
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index eac9065ffe0c..a5158483986e 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -57,16 +57,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
 extern unsigned long ldt_eoi_space;
 #endif
 
-#ifdef CONFIG_KGDB
-static int kgdb_irq;
-
-/* Default to UART1 */
-int kgdb_port = 1;
-#ifdef CONFIG_SERIAL_SB1250_DUART
-extern char sb1250_duart_present[];
-#endif
-#endif
-
 static struct irq_chip sb1250_irq_type = {
         .name = "SB1250-IMR",
         .ack = ack_sb1250_irq,
@@ -313,55 +303,10 @@ void __init arch_init_irq(void)
          * does its own management of IP7.
          */
 
-#ifdef CONFIG_KGDB
-        imask |= STATUSF_IP6;
-#endif
         /* Enable necessary IPs, disable the rest */
         change_c0_status(ST0_IM, imask);
-
-#ifdef CONFIG_KGDB
-        if (kgdb_flag) {
-                kgdb_irq = K_INT_UART_0 + kgdb_port;
-
-#ifdef CONFIG_SERIAL_SB1250_DUART
-                sb1250_duart_present[kgdb_port] = 0;
-#endif
-                /* Setup uart 1 settings, mapper */
-                __raw_writeq(M_DUART_IMR_BRK,
-                             IOADDR(A_DUART_IMRREG(kgdb_port)));
-
-                __raw_writeq(IMR_IP6_VAL,
-                             IOADDR(A_IMR_REGISTER(0,
-                                                   R_IMR_INTERRUPT_MAP_BASE) +
-                                    (kgdb_irq << 3)));
-                sb1250_unmask_irq(0, kgdb_irq);
-        }
-#endif
-}
-
-#ifdef CONFIG_KGDB
-
-#include <linux/delay.h>
-
-#define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
-#define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
-
-static void sb1250_kgdb_interrupt(void)
-{
-        /*
-         * Clear break-change status (allow some time for the remote
-         * host to stop the break, since we would see another
-         * interrupt on the end-of-break too)
-         */
-        kstat_this_cpu.irqs[kgdb_irq]++;
-        mdelay(500);
-        duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
-                                M_DUART_RX_EN | M_DUART_TX_EN);
-        set_async_breakpoint(&get_irq_regs()->cp0_epc);
 }
 
-#endif  /* CONFIG_KGDB */
-
 extern void sb1250_mailbox_interrupt(void);
 
 static inline void dispatch_ip2(void)
@@ -407,11 +352,6 @@ asmlinkage void plat_irq_dispatch(void)
                 sb1250_mailbox_interrupt();
 #endif
 
-#ifdef CONFIG_KGDB
-        else if (pending & CAUSEF_IP6)                  /* KGDB (uart 1) */
-                sb1250_kgdb_interrupt();
-#endif
-
         else if (pending & CAUSEF_IP2)
                 dispatch_ip2();
         else
diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile
index 255d692bfa18..f18ba9201bbc 100644
--- a/arch/mips/sibyte/swarm/Makefile
+++ b/arch/mips/sibyte/swarm/Makefile
@@ -1,4 +1,3 @@
 obj-y                           := setup.o rtc_xicor1241.o rtc_m41t81.o
 
 obj-$(CONFIG_I2C_BOARDINFO)     += swarm-i2c.o
-obj-$(CONFIG_KGDB)              += dbg_io.o
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
deleted file mode 100644
index b97ae3048482..000000000000
--- a/arch/mips/sibyte/swarm/dbg_io.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * kgdb debug routines for SiByte boards.
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-/* -------------------- BEGINNING OF CONFIG --------------------- */
-
-#include <linux/delay.h>
-#include <asm/io.h>
-#include <asm/sibyte/sb1250.h>
-#include <asm/sibyte/sb1250_regs.h>
-#include <asm/sibyte/sb1250_uart.h>
-#include <asm/sibyte/sb1250_int.h>
-#include <asm/addrspace.h>
-
-/*
- * We use the second serial port for kgdb traffic.
- *      115200, 8, N, 1.
- */
-
-#define BAUD_RATE               115200
-#define CLK_DIVISOR             V_DUART_BAUD_RATE(BAUD_RATE)
-#define DATA_BITS               V_DUART_BITS_PER_CHAR_8         /* or 7    */
-#define PARITY                  V_DUART_PARITY_MODE_NONE        /* or even */
-#define STOP_BITS               M_DUART_STOP_BIT_LEN_1          /* or 2    */
-
-static int duart_initialized = 0;       /* 0: need to be init'ed by kgdb */
-
-/* -------------------- END OF CONFIG --------------------- */
-extern int kgdb_port;
-
-#define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
-#define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
-
-void putDebugChar(unsigned char c);
-unsigned char getDebugChar(void);
-static void
-duart_init(int clk_divisor, int data, int parity, int stop)
-{
-        duart_out(R_DUART_MODE_REG_1, data | parity);
-        duart_out(R_DUART_MODE_REG_2, stop);
-        duart_out(R_DUART_CLK_SEL, clk_divisor);
-
-        duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN);  /* enable rx and tx */
-}
-
-void
-putDebugChar(unsigned char c)
-{
-        if (!duart_initialized) {
-                duart_initialized = 1;
-                duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
-        }
-        while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0);
-        duart_out(R_DUART_TX_HOLD, c);
-}
-
-unsigned char
-getDebugChar(void)
-{
-        if (!duart_initialized) {
-                duart_initialized = 1;
-                duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
-        }
-        while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ;
-        return duart_in(R_DUART_RX_HOLD);
-}
-
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 6de4c5aa92be..840fe757c48d 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -1,3 +1,27 @@
+config MACH_TX39XX
+        bool
+        select MACH_TXX9
+        select SYS_HAS_CPU_TX39XX
+
+config MACH_TX49XX
+        bool
+        select MACH_TXX9
+        select CEVT_R4K
+        select CSRC_R4K
+        select IRQ_CPU
+        select SYS_HAS_CPU_TX49XX
+        select SYS_SUPPORTS_64BIT_KERNEL
+
+config MACH_TXX9
+        bool
+        select DMA_NONCOHERENT
+        select SWAP_IO_SPACE
+        select SYS_HAS_EARLY_PRINTK
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select GENERIC_HARDIRQS_NO__DO_IRQ
+
 config TOSHIBA_JMR3927
         bool "Toshiba JMR-TX3927 board"
         depends on MACH_TX39XX
@@ -24,68 +48,37 @@ config TOSHIBA_RBTX4938
 config SOC_TX3927
         bool
         select CEVT_TXX9
-        select DMA_NONCOHERENT
         select HAS_TXX9_SERIAL
         select HW_HAS_PCI
         select IRQ_TXX9
-        select SWAP_IO_SPACE
-        select SYS_HAS_CPU_TX39XX
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_SUPPORTS_BIG_ENDIAN
-        select GENERIC_HARDIRQS_NO__DO_IRQ
         select GPIO_TXX9
 
 config SOC_TX4927
         bool
-        select CEVT_R4K
-        select CSRC_R4K
         select CEVT_TXX9
-        select DMA_NONCOHERENT
         select HAS_TXX9_SERIAL
         select HW_HAS_PCI
-        select IRQ_CPU
         select IRQ_TXX9
         select PCI_TX4927
-        select SWAP_IO_SPACE
-        select SYS_HAS_CPU_TX49XX
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_64BIT_KERNEL
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_KGDB
-        select GENERIC_HARDIRQS_NO__DO_IRQ
         select GPIO_TXX9
 
 config SOC_TX4938
         bool
-        select CEVT_R4K
-        select CSRC_R4K
         select CEVT_TXX9
-        select DMA_NONCOHERENT
         select HAS_TXX9_SERIAL
         select HW_HAS_PCI
-        select IRQ_CPU
         select IRQ_TXX9
         select PCI_TX4927
-        select SWAP_IO_SPACE
-        select SYS_HAS_CPU_TX49XX
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_64BIT_KERNEL
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_KGDB
-        select GENERIC_HARDIRQS_NO__DO_IRQ
         select GPIO_TXX9
 
 config TOSHIBA_FPCIB0
         bool "FPCIB0 Backplane Support"
-        depends on PCI && (MACH_TX39XX || MACH_TX49XX)
+        depends on PCI && MACH_TXX9
         select I8259
 
 config PICMG_PCI_BACKPLANE_DEFAULT
         bool "Support for PICMG PCI Backplane"
-        depends on PCI && (MACH_TX39XX || MACH_TX49XX)
+        depends on PCI && MACH_TXX9
         default y if !TOSHIBA_FPCIB0
 
 if TOSHIBA_RBTX4938
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 9c120771e65f..9bb34af26b73 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -4,9 +4,9 @@
 
 obj-y   += setup.o
 obj-$(CONFIG_PCI)       += pci.o
+obj-$(CONFIG_SOC_TX3927)        += setup_tx3927.o irq_tx3927.o
 obj-$(CONFIG_SOC_TX4927)        += mem_tx4927.o setup_tx4927.o irq_tx4927.o
 obj-$(CONFIG_SOC_TX4938)        += mem_tx4927.o setup_tx4938.o irq_tx4938.o
 obj-$(CONFIG_TOSHIBA_FPCIB0)    += smsc_fdc37m81x.o
-obj-$(CONFIG_KGDB)      += dbgio.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/dbgio.c b/arch/mips/txx9/generic/dbgio.c
deleted file mode 100644
index 33b9c672a322..000000000000
--- a/arch/mips/txx9/generic/dbgio.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * linux/arch/mips/tx4938/common/dbgio.c
- *
- * kgdb interface for gdb
- *
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * Copyright 2005 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License as published by the
- *  Free Software Foundation; either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
- */
-
-#include <linux/types>
-
-extern u8 txx9_sio_kdbg_rd(void);
-extern int txx9_sio_kdbg_wr( u8 ch );
-
-u8 getDebugChar(void)
-{
-        return (txx9_sio_kdbg_rd());
-}
-
-int putDebugChar(u8 byte)
-{
-        return (txx9_sio_kdbg_wr(byte));
-}
-
diff --git a/arch/mips/txx9/generic/irq_tx3927.c b/arch/mips/txx9/generic/irq_tx3927.c
new file mode 100644
index 000000000000..c683f593eda2
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx3927.c
@@ -0,0 +1,25 @@
+/*
+ * Common tx3927 irq handler
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ */
+#include <linux/init.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx3927.h>
+
+void __init tx3927_irq_init(void)
+{
+        int i;
+
+        txx9_irq_init(TX3927_IRC_REG);
+        /* raise priority for timers, sio */
+        for (i = 0; i < TX3927_NR_TMR; i++)
+                txx9_irq_set_pri(TX3927_IR_TMR(i), 6);
+        for (i = 0; i < TX3927_NR_SIO; i++)
+                txx9_irq_set_pri(TX3927_IR_SIO(i), 7);
+}
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 0b92d8c13208..7b637a7c0e66 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -386,3 +386,39 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
         return txx9_board_vec->pci_map_irq(dev, slot, pin);
 }
+
+char * (*txx9_board_pcibios_setup)(char *str) __devinitdata;
+
+char *__devinit txx9_pcibios_setup(char *str)
+{
+        if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
+                return NULL;
+        if (!strcmp(str, "picmg")) {
+                /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
+                   (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
+                txx9_pci_option |= TXX9_PCI_OPT_PICMG;
+                return NULL;
+        } else if (!strcmp(str, "nopicmg")) {
+                /* non-PICMG compliant backplane (TOSHIBA
+                   RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
+                txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
+                return NULL;
+        } else if (!strncmp(str, "clk=", 4)) {
+                char *val = str + 4;
+                txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
+                if (strcmp(val, "33") == 0)
+                        txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
+                else if (strcmp(val, "66") == 0)
+                        txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
+                else /* "auto" */
+                        txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
+                return NULL;
+        } else if (!strncmp(str, "err=", 4)) {
+                if (!strcmp(str + 4, "panic"))
+                        txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
+                else if (!strcmp(str + 4, "ignore"))
+                        txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
+                return NULL;
+        }
+        return str;
+}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8c60c78b9a9e..1bc57d0f4c5c 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -20,9 +20,13 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
 #include <asm/bootinfo.h>
 #include <asm/time.h>
+#include <asm/reboot.h>
 #include <asm/txx9/generic.h>
+#include <asm/txx9/pci.h>
 #ifdef CONFIG_CPU_TX49XX
 #include <asm/txx9/tx4938.h>
 #endif
@@ -187,6 +191,117 @@ char * __init prom_getcmdline(void)
         return &(arcs_cmdline[0]);
 }
 
+static void __noreturn txx9_machine_halt(void)
+{
+        local_irq_disable();
+        clear_c0_status(ST0_IM);
+        while (1) {
+                if (cpu_wait) {
+                        (*cpu_wait)();
+                        if (cpu_has_counter) {
+                                /*
+                                 * Clear counter interrupt while it
+                                 * breaks WAIT instruction even if
+                                 * masked.
+                                 */
+                                write_c0_compare(0);
+                        }
+                }
+        }
+}
+
+/* Watchdog support */
+void __init txx9_wdt_init(unsigned long base)
+{
+        struct resource res = {
+                .start  = base,
+                .end    = base + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        };
+        platform_device_register_simple("txx9wdt", -1, &res, 1);
+}
+
+/* SPI support */
+void __init txx9_spi_init(int busid, unsigned long base, int irq)
+{
+        struct resource res[] = {
+                {
+                        .start  = base,
+                        .end    = base + 0x20 - 1,
+                        .flags  = IORESOURCE_MEM,
+                }, {
+                        .start  = irq,
+                        .flags  = IORESOURCE_IRQ,
+                },
+        };
+        platform_device_register_simple("spi_txx9", busid,
+                                        res, ARRAY_SIZE(res));
+}
+
+void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
+{
+        struct platform_device *pdev =
+                platform_device_alloc("tc35815-mac", id);
+        if (!pdev ||
+            platform_device_add_data(pdev, ethaddr, 6) ||
+            platform_device_add(pdev))
+                platform_device_put(pdev);
+}
+
+void __init txx9_sio_init(unsigned long baseaddr, int irq,
+                          unsigned int line, unsigned int sclk, int nocts)
+{
+#ifdef CONFIG_SERIAL_TXX9
+        struct uart_port req;
+
+        memset(&req, 0, sizeof(req));
+        req.line = line;
+        req.iotype = UPIO_MEM;
+        req.membase = ioremap(baseaddr, 0x24);
+        req.mapbase = baseaddr;
+        req.irq = irq;
+        if (!nocts)
+                req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
+        if (sclk) {
+                req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
+                req.uartclk = sclk;
+        } else
+                req.uartclk = TXX9_IMCLK;
+        early_serial_txx9_setup(&req);
+#endif /* CONFIG_SERIAL_TXX9 */
+}
+
+#ifdef CONFIG_EARLY_PRINTK
+static void __init null_prom_putchar(char c)
+{
+}
+void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar;
+
+void __init prom_putchar(char c)
+{
+        txx9_prom_putchar(c);
+}
+
+static void __iomem *early_txx9_sio_port;
+
+static void __init early_txx9_sio_putchar(char c)
+{
+#define TXX9_SICISR     0x0c
+#define TXX9_SITFIFO    0x1c
+#define TXX9_SICISR_TXALS       0x00000002
+        while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
+                 TXX9_SICISR_TXALS))
+                ;
+        __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
+}
+
+void __init txx9_sio_putchar_init(unsigned long baseaddr)
+{
+        early_txx9_sio_port = ioremap(baseaddr, 0x24);
+        txx9_prom_putchar = early_txx9_sio_putchar;
+}
+#endif /* CONFIG_EARLY_PRINTK */
+
 /* wrappers */
 void __init plat_mem_setup(void)
 {
@@ -194,6 +309,15 @@ void __init plat_mem_setup(void)
         ioport_resource.end = ~0UL;     /* no limit */
         iomem_resource.start = 0;
         iomem_resource.end = ~0UL;      /* no limit */
+
+        /* fallback restart/halt routines */
+        _machine_restart = (void (*)(char *))txx9_machine_halt;
+        _machine_halt = txx9_machine_halt;
+        pm_power_off = txx9_machine_halt;
+
+#ifdef CONFIG_PCI
+        pcibios_plat_setup = txx9_pcibios_setup;
+#endif
         txx9_board_vec->mem_setup();
 }
 
diff --git a/arch/mips/txx9/generic/setup_tx3927.c b/arch/mips/txx9/generic/setup_tx3927.c
new file mode 100644
index 000000000000..7bd963d37fc3
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx3927.c
@@ -0,0 +1,130 @@
+/*
+ * TX3927 setup routines
+ * Based on linux/arch/mips/txx9/jmr3927/setup.c
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/param.h>
+#include <linux/io.h>
+#include <asm/mipsregs.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9tmr.h>
+#include <asm/txx9pio.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx3927.h>
+
+void __init tx3927_wdt_init(void)
+{
+        txx9_wdt_init(TX3927_TMR_REG(2));
+}
+
+void __init tx3927_setup(void)
+{
+        int i;
+        unsigned int conf;
+
+        /* don't enable - see errata */
+        txx9_ccfg_toeon = 0;
+        if (strstr(prom_getcmdline(), "toeon") != NULL)
+                txx9_ccfg_toeon = 1;
+
+        txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE,
+                          TX3927_REG_SIZE);
+
+        /* SDRAMC,ROMC are configured by PROM */
+        for (i = 0; i < 8; i++) {
+                if (!(tx3927_romcptr->cr[i] & 0x8))
+                        continue;       /* disabled */
+                txx9_ce_res[i].start = (unsigned long)TX3927_ROMC_BA(i);
+                txx9_ce_res[i].end =
+                        txx9_ce_res[i].start + TX3927_ROMC_SIZE(i) - 1;
+                request_resource(&iomem_resource, &txx9_ce_res[i]);
+        }
+
+        /* clocks */
+        txx9_gbus_clock = txx9_cpu_clock / 2;
+        /* change default value to udelay/mdelay take reasonable time */
+        loops_per_jiffy = txx9_cpu_clock / HZ / 2;
+
+        /* CCFG */
+        /* enable Timeout BusError */
+        if (txx9_ccfg_toeon)
+                tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
+
+        /* clear BusErrorOnWrite flag */
+        tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
+        if (read_c0_conf() & TX39_CONF_WBON)
+                /* Disable PCI snoop */
+                tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
+        else
+                /* Enable PCI SNOOP - with write through only */
+                tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
+        /* do reset on watchdog */
+        tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
+
+        printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
+               tx3927_ccfgptr->crir,
+               tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
+
+        /* TMR */
+        for (i = 0; i < TX3927_NR_TMR; i++)
+                txx9_tmr_init(TX3927_TMR_REG(i));
+
+        /* DMA */
+        tx3927_dmaptr->mcr = 0;
+        for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
+                /* reset channel */
+                tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
+                tx3927_dmaptr->ch[i].ccr = 0;
+        }
+        /* enable DMA */
+#ifdef __BIG_ENDIAN
+        tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
+#else
+        tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
+#endif
+
+        /* PIO */
+        __raw_writel(0, &tx3927_pioptr->maskcpu);
+        __raw_writel(0, &tx3927_pioptr->maskext);
+        txx9_gpio_init(TX3927_PIO_REG, 0, 16);
+
+        conf = read_c0_conf();
+        if (!(conf & TX39_CONF_ICE))
+                printk(KERN_INFO "TX3927 I-Cache disabled.\n");
+        if (!(conf & TX39_CONF_DCE))
+                printk(KERN_INFO "TX3927 D-Cache disabled.\n");
+        else if (!(conf & TX39_CONF_WBON))
+                printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n");
+        else if (!(conf & TX39_CONF_CWFON))
+                printk(KERN_INFO "TX3927 D-Cache WriteBack.\n");
+        else
+                printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n");
+}
+
+void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
+{
+        txx9_clockevent_init(TX3927_TMR_REG(evt_tmrnr),
+                             TXX9_IRQ_BASE + TX3927_IR_TMR(evt_tmrnr),
+                             TXX9_IMCLK);
+        txx9_clocksource_init(TX3927_TMR_REG(src_tmrnr), TXX9_IMCLK);
+}
+
+void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
+{
+        int i;
+
+        for (i = 0; i < 2; i++)
+                txx9_sio_init(TX3927_SIO_REG(i),
+                              TXX9_IRQ_BASE + TX3927_IR_SIO(i),
+                              i, sclk, (1 << i) & cts_mask);
+}
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index 89d6e28add93..f80d4b7a694d 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -13,7 +13,6 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/delay.h>
-#include <linux/serial_core.h>
 #include <linux/param.h>
 #include <asm/txx9irq.h>
 #include <asm/txx9tmr.h>
@@ -21,7 +20,7 @@
 #include <asm/txx9/generic.h>
 #include <asm/txx9/tx4927.h>
 
-void __init tx4927_wdr_init(void)
+static void __init tx4927_wdr_init(void)
 {
         /* clear WatchDogReset (W1C) */
         tx4927_ccfg_set(TX4927_CCFG_WDRST);
@@ -29,6 +28,11 @@ void __init tx4927_wdr_init(void)
         tx4927_ccfg_set(TX4927_CCFG_WR);
 }
 
+void __init tx4927_wdt_init(void)
+{
+        txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
+}
+
 static struct resource tx4927_sdram_resource[4];
 
 void __init tx4927_setup(void)
@@ -173,22 +177,12 @@ void __init tx4927_time_init(unsigned int tmrnr)
                                      TXX9_IMCLK);
 }
 
-void __init tx4927_setup_serial(void)
+void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
 {
-#ifdef CONFIG_SERIAL_TXX9
         int i;
-        struct uart_port req;
-
-        for (i = 0; i < 2; i++) {
-                memset(&req, 0, sizeof(req));
-                req.line = i;
-                req.iotype = UPIO_MEM;
-                req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
-                req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
-                req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
-                req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
-                req.uartclk = TXX9_IMCLK;
-                early_serial_txx9_setup(&req);
-        }
-#endif /* CONFIG_SERIAL_TXX9 */
+
+        for (i = 0; i < 2; i++)
+                txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
+                              TXX9_IRQ_BASE + TX4927_IR_SIO(i),
+                              i, sclk, (1 << i) & cts_mask);
 }
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index 317378d8579d..f3040b9ba059 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -13,7 +13,6 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/delay.h>
-#include <linux/serial_core.h>
 #include <linux/param.h>
 #include <asm/txx9irq.h>
 #include <asm/txx9tmr.h>
@@ -21,7 +20,7 @@
 #include <asm/txx9/generic.h>
 #include <asm/txx9/tx4938.h>
 
-void __init tx4938_wdr_init(void)
+static void __init tx4938_wdr_init(void)
 {
         /* clear WatchDogReset (W1C) */
         tx4938_ccfg_set(TX4938_CCFG_WDRST);
@@ -29,6 +28,11 @@ void __init tx4938_wdr_init(void)
         tx4938_ccfg_set(TX4938_CCFG_WR);
 }
 
+void __init tx4938_wdt_init(void)
+{
+        txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
+}
+
 static struct resource tx4938_sdram_resource[4];
 static struct resource tx4938_sram_resource;
 
@@ -233,11 +237,9 @@ void __init tx4938_time_init(unsigned int tmrnr)
                                      TXX9_IMCLK);
 }
 
-void __init tx4938_setup_serial(void)
+void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask)
 {
-#ifdef CONFIG_SERIAL_TXX9
         int i;
-        struct uart_port req;
         unsigned int ch_mask = 0;
 
         if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
@@ -245,15 +247,24 @@ void __init tx4938_setup_serial(void)
         for (i = 0; i < 2; i++) {
                 if ((1 << i) & ch_mask)
                         continue;
-                memset(&req, 0, sizeof(req));
-                req.line = i;
-                req.iotype = UPIO_MEM;
-                req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i);
-                req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL;
-                req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i);
-                req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
-                req.uartclk = TXX9_IMCLK;
-                early_serial_txx9_setup(&req);
+                txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL,
+                              TXX9_IRQ_BASE + TX4938_IR_SIO(i),
+                              i, sclk, (1 << i) & cts_mask);
         }
-#endif /* CONFIG_SERIAL_TXX9 */
+}
+
+void __init tx4938_spi_init(int busid)
+{
+        txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL,
+                      TXX9_IRQ_BASE + TX4938_IR_SPI);
+}
+
+void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
+{
+        u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
+
+        if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL))
+                txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0);
+        if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
+                txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
 }
diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c
index 69e487467fa5..a2b2d62d88e3 100644
--- a/arch/mips/txx9/generic/smsc_fdc37m81x.c
+++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c
@@ -15,8 +15,6 @@
 #include <asm/io.h>
 #include <asm/txx9/smsc_fdc37m81x.h>
 
-#define DEBUG
-
 /* Common Registers */
 #define SMSC_FDC37M81X_CONFIG_INDEX  0x00
 #define SMSC_FDC37M81X_CONFIG_DATA   0x01
@@ -55,7 +53,7 @@
 #define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
 #define SMSC_FDC37M81X_CHIP_ID       0x4d
 
-static unsigned long g_smsc_fdc37m81x_base = 0;
+static unsigned long g_smsc_fdc37m81x_base;
 
 static inline unsigned char smsc_fdc37m81x_rd(unsigned char index)
 {
@@ -107,7 +105,8 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
         u8 chip_id;
 
         if (g_smsc_fdc37m81x_base)
-                printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n",
+                printk(KERN_WARNING "%s: stepping on old base=0x%0*lx\n",
+                       __func__,
                        field, g_smsc_fdc37m81x_base);
 
         g_smsc_fdc37m81x_base = port;
@@ -118,7 +117,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
         if (chip_id == SMSC_FDC37M81X_CHIP_ID)
                 smsc_fdc37m81x_config_end();
         else {
-                printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n",
+                printk(KERN_WARNING "%s: unknow chip id 0x%02x\n", __func__,
                        chip_id);
                 g_smsc_fdc37m81x_base = 0;
         }
@@ -127,22 +126,23 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
 }
 
 #ifdef DEBUG
-void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg)
+static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg)
 {
-        printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg,
+        printk(KERN_INFO "%s: dev=0x%02x reg=0x%02x val=0x%02x\n",
+               key, dev, reg,
                smsc_fdc37m81x_rd(reg));
 }
 
 void smsc_fdc37m81x_config_dump(void)
 {
         u8 orig;
-        char *fname = "smsc_fdc37m81x_config_dump()";
+        const char *fname = __func__;
 
         smsc_fdc37m81x_config_beg();
 
         orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM);
 
-        printk("%s: common\n", fname);
+        printk(KERN_INFO "%s: common\n", fname);
         smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
                                        SMSC_FDC37M81X_DNUM);
         smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
@@ -154,7 +154,7 @@ void smsc_fdc37m81x_config_dump(void)
         smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
                                        SMSC_FDC37M81X_PMGT);
 
-        printk("%s: keyboard\n", fname);
+        printk(KERN_INFO "%s: keyboard\n", fname);
         smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD);
         smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
                                        SMSC_FDC37M81X_ACTIVE);
diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile
index ba292c945669..20d61ac543e5 100644
--- a/arch/mips/txx9/jmr3927/Makefile
+++ b/arch/mips/txx9/jmr3927/Makefile
@@ -3,6 +3,5 @@
 #
 
 obj-y   += prom.o irq.o setup.o
-obj-$(CONFIG_KGDB)      += kgdb_io.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 070c9a115e57..6ec626c9473f 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -30,15 +30,11 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/init.h>
-#include <linux/sched.h>
 #include <linux/types.h>
 #include <linux/interrupt.h>
 
 #include <asm/io.h>
 #include <asm/mipsregs.h>
-#include <asm/system.h>
-
-#include <asm/processor.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/jmr3927.h>
 
@@ -46,13 +42,6 @@
 #error JMR3927_IRQ_END > NR_IRQS
 #endif
 
-static unsigned char irc_level[TX3927_NUM_IR] = {
-        5, 5, 5, 5, 5, 5,       /* INT[5:0] */
-        7, 7,                   /* SIO */
-        5, 5, 5, 0, 0,          /* DMA, PIO, PCI */
-        6, 6, 6                 /* TMR */
-};
-
 /*
  * CP0_STATUS is a thread's resource (saved/restored on context switch).
  * So disable_irq/enable_irq MUST handle IOC/IRC registers.
@@ -103,26 +92,18 @@ static int jmr3927_irq_dispatch(int pending)
         return irq;
 }
 
-#ifdef CONFIG_PCI
-static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
-{
-        printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
-        printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
-               tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
-
-        return IRQ_HANDLED;
-}
-static struct irqaction pcierr_action = {
-        .handler = jmr3927_pcierr_interrupt,
-        .mask = CPU_MASK_NONE,
-        .name = "PCI error",
+static struct irq_chip jmr3927_irq_ioc = {
+        .name = "jmr3927_ioc",
+        .ack = mask_irq_ioc,
+        .mask = mask_irq_ioc,
+        .mask_ack = mask_irq_ioc,
+        .unmask = unmask_irq_ioc,
 };
-#endif
-
-static void __init jmr3927_irq_init(void);
 
 void __init jmr3927_irq_setup(void)
 {
+        int i;
+
         txx9_irq_dispatch = jmr3927_irq_dispatch;
         /* Now, interrupt control disabled, */
         /* all IRC interrupts are masked, */
@@ -138,34 +119,10 @@ void __init jmr3927_irq_setup(void)
         /* clear PCI Reset interrupts */
         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 
-        jmr3927_irq_init();
+        tx3927_irq_init();
+        for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
+                set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
 
         /* setup IOC interrupt 1 (PCI, MODEM) */
         set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
-
-#ifdef CONFIG_PCI
-        setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
-#endif
-
-        /* enable all CPU interrupt bits. */
-        set_c0_status(ST0_IM);  /* IE bit is still 0. */
-}
-
-static struct irq_chip jmr3927_irq_ioc = {
-        .name = "jmr3927_ioc",
-        .ack = mask_irq_ioc,
-        .mask = mask_irq_ioc,
-        .mask_ack = mask_irq_ioc,
-        .unmask = unmask_irq_ioc,
-};
-
-static void __init jmr3927_irq_init(void)
-{
-        u32 i;
-
-        txx9_irq_init(TX3927_IRC_REG);
-        for (i = 0; i < TXx9_MAX_IR; i++)
-                txx9_irq_set_pri(i, irc_level[i]);
-        for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
-                set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
 }
diff --git a/arch/mips/txx9/jmr3927/kgdb_io.c b/arch/mips/txx9/jmr3927/kgdb_io.c
deleted file mode 100644
index 5bd757e56f79..000000000000
--- a/arch/mips/txx9/jmr3927/kgdb_io.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Low level uart routines to directly access a TX[34]927 SIO.
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ahennessy@mvista.com or source@mvista.com
- *
- * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/txx9/jmr3927.h>
-
-#define TIMEOUT       0xffffff
-
-static int remoteDebugInitialized = 0;
-static void debugInit(int baud);
-
-int putDebugChar(unsigned char c)
-{
-        int i = 0;
-
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(38400);
-        }
-
-        do {
-            slow_down();
-            i++;
-            if (i>TIMEOUT) {
-                break;
-            }
-        } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
-        tx3927_sioptr(0)->tfifo = c;
-
-        return 1;
-}
-
-unsigned char getDebugChar(void)
-{
-        int i = 0;
-        int dicr;
-        char c;
-
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(38400);
-        }
-
-        /* diable RX int. */
-        dicr = tx3927_sioptr(0)->dicr;
-        tx3927_sioptr(0)->dicr = 0;
-
-        do {
-            slow_down();
-            i++;
-            if (i>TIMEOUT) {
-                break;
-            }
-        } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
-                ;
-        c = tx3927_sioptr(0)->rfifo;
-
-        /* clear RX int. status */
-        tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
-        /* enable RX int. */
-        tx3927_sioptr(0)->dicr = dicr;
-
-        return c;
-}
-
-static void debugInit(int baud)
-{
-        tx3927_sioptr(0)->lcr = 0x020;
-        tx3927_sioptr(0)->dicr = 0;
-        tx3927_sioptr(0)->disr = 0x4100;
-        tx3927_sioptr(0)->cisr = 0x014;
-        tx3927_sioptr(0)->fcr = 0;
-        tx3927_sioptr(0)->flcr = 0x02;
-        tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
-                TXx927_SIBGR_BCLK_T0;
-}
diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c
index 2cadb423face..70c4c8ec3e84 100644
--- a/arch/mips/txx9/jmr3927/prom.c
+++ b/arch/mips/txx9/jmr3927/prom.c
@@ -36,41 +36,18 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/init.h>
+#include <linux/kernel.h>
 #include <asm/bootinfo.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/jmr3927.h>
 
-#define TIMEOUT       0xffffff
-
-void
-prom_putchar(char c)
-{
-        int i = 0;
-
-        do {
-            i++;
-            if (i>TIMEOUT)
-                break;
-        } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
-        tx3927_sioptr(1)->tfifo = c;
-        return;
-}
-
-void
-puts(const char *cp)
-{
-    while (*cp)
-        prom_putchar(*cp++);
-    prom_putchar('\r');
-    prom_putchar('\n');
-}
-
 void __init jmr3927_prom_init(void)
 {
         /* CCFG */
         if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
-                puts("Warning: TX3927 TLB off\n");
+                printk(KERN_ERR "TX3927 TLB off\n");
 
         prom_init_cmdline();
         add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
+        txx9_sio_putchar_init(TX3927_SIO_REG(1));
 }
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 03647ebe4130..87db41be8a56 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -32,27 +32,18 @@
 #include <linux/types.h>
 #include <linux/ioport.h>
 #include <linux/delay.h>
-#include <linux/pm.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#ifdef CONFIG_SERIAL_TXX9
-#include <linux/serial_core.h>
-#endif
-#include <asm/txx9tmr.h>
-#include <asm/txx9pio.h>
 #include <asm/reboot.h>
+#include <asm/txx9pio.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/pci.h>
 #include <asm/txx9/jmr3927.h>
 #include <asm/mipsregs.h>
 
-extern void puts(const char *cp);
-
-/* don't enable - see errata */
-static int jmr3927_ccfg_toeon;
-
-static inline void do_reset(void)
+static void jmr3927_machine_restart(char *command)
 {
+        local_irq_disable();
 #if 1   /* Resetting PCI bus */
         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
@@ -61,33 +52,13 @@ static inline void do_reset(void)
         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 #endif
         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
-}
-
-static void jmr3927_machine_restart(char *command)
-{
-        local_irq_disable();
-        puts("Rebooting...");
-        do_reset();
-}
-
-static void jmr3927_machine_halt(void)
-{
-        puts("JMR-TX3927 halted.\n");
-        while (1);
-}
-
-static void jmr3927_machine_power_off(void)
-{
-        puts("JMR-TX3927 halted. Please turn off the power.\n");
-        while (1);
+        /* fallback */
+        (*_machine_halt)();
 }
 
 static void __init jmr3927_time_init(void)
 {
-        txx9_clockevent_init(TX3927_TMR_REG(0),
-                             TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
-                             JMR3927_IMCLK);
-        txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
+        tx3927_time_init(0, 1);
 }
 
 #define DO_WRITE_THROUGH
@@ -102,11 +73,6 @@ static void __init jmr3927_mem_setup(void)
         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 
         _machine_restart = jmr3927_machine_restart;
-        _machine_halt = jmr3927_machine_halt;
-        pm_power_off = jmr3927_machine_power_off;
-
-        /* Reboot on panic */
-        panic_timeout = 180;
 
         /* cache setup */
         {
@@ -125,7 +91,8 @@ static void __init jmr3927_mem_setup(void)
 #endif
 
                 conf = read_c0_conf();
-                conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
+                conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE |
+                          TX39_CONF_WBON | TX39_CONF_CWFON);
                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
@@ -138,47 +105,14 @@ static void __init jmr3927_mem_setup(void)
         /* initialize board */
         jmr3927_board_init();
 
-        argptr = prom_getcmdline();
-
-        if ((argptr = strstr(argptr, "toeon")) != NULL)
-                jmr3927_ccfg_toeon = 1;
-        argptr = prom_getcmdline();
-        if ((argptr = strstr(argptr, "ip=")) == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " ip=bootp");
-        }
-
-#ifdef CONFIG_SERIAL_TXX9
-        {
-                extern int early_serial_txx9_setup(struct uart_port *port);
-                int i;
-                struct uart_port req;
-                for(i = 0; i < 2; i++) {
-                        memset(&req, 0, sizeof(req));
-                        req.line = i;
-                        req.iotype = UPIO_MEM;
-                        req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
-                        req.mapbase = TX3927_SIO_REG(i);
-                        req.irq = i == 0 ?
-                                JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
-                        if (i == 0)
-                                req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
-                        req.uartclk = JMR3927_IMCLK;
-                        early_serial_txx9_setup(&req);
-                }
-        }
+        tx3927_sio_init(0, 1 << 1); /* ch1: noCTS */
 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
         argptr = prom_getcmdline();
-        if ((argptr = strstr(argptr, "console=")) == NULL) {
-                argptr = prom_getcmdline();
+        if (!strstr(argptr, "console="))
                 strcat(argptr, " console=ttyS1,115200");
-        }
-#endif
 #endif
 }
 
-static void tx3927_setup(void);
-
 static void __init jmr3927_pci_setup(void)
 {
 #ifdef CONFIG_PCI
@@ -199,32 +133,13 @@ static void __init jmr3927_pci_setup(void)
                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
         }
         tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
+        tx3927_setup_pcierr_irq();
 #endif /* CONFIG_PCI */
 }
 
 static void __init jmr3927_board_init(void)
 {
-        tx3927_setup();
-        jmr3927_pci_setup();
-
-        /* SIO0 DTR on */
-        jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
-
-        jmr3927_led_set(0);
-
-        printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
-               jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
-               jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
-               jmr3927_dipsw1(), jmr3927_dipsw2(),
-               jmr3927_dipsw3(), jmr3927_dipsw4());
-}
-
-static void __init tx3927_setup(void)
-{
-        int i;
-
         txx9_cpu_clock = JMR3927_CORECLK;
-        txx9_gbus_clock = JMR3927_GBUSCLK;
         /* SDRAMC are configured by PROM */
 
         /* ROMC */
@@ -233,74 +148,32 @@ static void __init tx3927_setup(void)
         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 
-        /* CCFG */
-        /* enable Timeout BusError */
-        if (jmr3927_ccfg_toeon)
-                tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
-
-        /* clear BusErrorOnWrite flag */
-        tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
-        /* Disable PCI snoop */
-        tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
-        /* do reset on watchdog */
-        tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
-
-#ifdef DO_WRITE_THROUGH
-        /* Enable PCI SNOOP - with write through only */
-        tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
-#endif
-
         /* Pin selection */
         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
         tx3927_ccfgptr->pcfg |=
                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 
-        printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
-               tx3927_ccfgptr->crir,
-               tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
-
-        /* TMR */
-        for (i = 0; i < TX3927_NR_TMR; i++)
-                txx9_tmr_init(TX3927_TMR_REG(i));
-
-        /* DMA */
-        tx3927_dmaptr->mcr = 0;
-        for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
-                /* reset channel */
-                tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
-                tx3927_dmaptr->ch[i].ccr = 0;
-        }
-        /* enable DMA */
-#ifdef __BIG_ENDIAN
-        tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
-#else
-        tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
-#endif
+        tx3927_setup();
 
-        /* PIO */
         /* PIO[15:12] connected to LEDs */
         __raw_writel(0x0000f000, &tx3927_pioptr->dir);
-        __raw_writel(0, &tx3927_pioptr->maskcpu);
-        __raw_writel(0, &tx3927_pioptr->maskext);
-        txx9_gpio_init(TX3927_PIO_REG, 0, 16);
         gpio_request(11, "dipsw1");
         gpio_request(10, "dipsw2");
-        {
-                unsigned int conf;
 
-        conf = read_c0_conf();
-               if (!(conf & TX39_CONF_ICE))
-                       printk("TX3927 I-Cache disabled.\n");
-               if (!(conf & TX39_CONF_DCE))
-                       printk("TX3927 D-Cache disabled.\n");
-               else if (!(conf & TX39_CONF_WBON))
-                       printk("TX3927 D-Cache WriteThrough.\n");
-               else if (!(conf & TX39_CONF_CWFON))
-                       printk("TX3927 D-Cache WriteBack.\n");
-               else
-                       printk("TX3927 D-Cache WriteBack (CWF) .\n");
-        }
+        jmr3927_pci_setup();
+
+        /* SIO0 DTR on */
+        jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
+
+        jmr3927_led_set(0);
+
+        printk(KERN_INFO
+               "JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
+               jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
+               jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
+               jmr3927_dipsw1(), jmr3927_dipsw2(),
+               jmr3927_dipsw3(), jmr3927_dipsw4());
 }
 
 /* This trick makes rtc-ds1742 driver usable as is. */
@@ -316,42 +189,21 @@ static unsigned long jmr3927_swizzle_addr_b(unsigned long port)
 #endif
 }
 
-static int __init jmr3927_rtc_init(void)
+static void __init jmr3927_rtc_init(void)
 {
         static struct resource __initdata res = {
                 .start  = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
                 .end    = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
                 .flags  = IORESOURCE_MEM,
         };
-        struct platform_device *dev;
-        dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
-}
-
-/* Watchdog support */
-
-static int __init txx9_wdt_init(unsigned long base)
-{
-        struct resource res = {
-                .start  = base,
-                .end    = base + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        };
-        struct platform_device *dev =
-                platform_device_register_simple("txx9wdt", -1, &res, 1);
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
-}
-
-static int __init jmr3927_wdt_init(void)
-{
-        return txx9_wdt_init(TX3927_TMR_REG(2));
+        platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 }
 
 static void __init jmr3927_device_init(void)
 {
         __swizzle_addr_b = jmr3927_swizzle_addr_b;
         jmr3927_rtc_init();
-        jmr3927_wdt_init();
+        tx3927_wdt_init();
 }
 
 struct txx9_board_vec jmr3927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index cd748a930328..00cd5231da30 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -27,85 +27,86 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 /*
-IRQ  Device
-00   RBTX4927-ISA/00
-01   RBTX4927-ISA/01 PS2/Keyboard
-02   RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
-03   RBTX4927-ISA/03
-04   RBTX4927-ISA/04
-05   RBTX4927-ISA/05
-06   RBTX4927-ISA/06
-07   RBTX4927-ISA/07
-08   RBTX4927-ISA/08
-09   RBTX4927-ISA/09
-10   RBTX4927-ISA/10
-11   RBTX4927-ISA/11
-12   RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
-13   RBTX4927-ISA/13
-14   RBTX4927-ISA/14 IDE
-15   RBTX4927-ISA/15
-
-16   TX4927-CP0/00 Software 0
-17   TX4927-CP0/01 Software 1
-18   TX4927-CP0/02 Cascade TX4927-CP0
-19   TX4927-CP0/03 Multiplexed -- do not use
-20   TX4927-CP0/04 Multiplexed -- do not use
-21   TX4927-CP0/05 Multiplexed -- do not use
-22   TX4927-CP0/06 Multiplexed -- do not use
-23   TX4927-CP0/07 CPU TIMER
-
-24   TX4927-PIC/00
-25   TX4927-PIC/01
-26   TX4927-PIC/02
-27   TX4927-PIC/03 Cascade RBTX4927-IOC
-28   TX4927-PIC/04
-29   TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
-30   TX4927-PIC/06
-31   TX4927-PIC/07
-32   TX4927-PIC/08 TX4927 SerialIO Channel 0
-33   TX4927-PIC/09 TX4927 SerialIO Channel 1
-34   TX4927-PIC/10
-35   TX4927-PIC/11
-36   TX4927-PIC/12
-37   TX4927-PIC/13
-38   TX4927-PIC/14
-39   TX4927-PIC/15
-40   TX4927-PIC/16 TX4927 PCI PCI-C
-41   TX4927-PIC/17
-42   TX4927-PIC/18
-43   TX4927-PIC/19
-44   TX4927-PIC/20
-45   TX4927-PIC/21
-46   TX4927-PIC/22 TX4927 PCI PCI-ERR
-47   TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
-48   TX4927-PIC/24
-49   TX4927-PIC/25
-50   TX4927-PIC/26
-51   TX4927-PIC/27
-52   TX4927-PIC/28
-53   TX4927-PIC/29
-54   TX4927-PIC/30
-55   TX4927-PIC/31
-
-56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed)        [RTL-8139=PJ4]
-57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed)        [RTL-8139=PJ5]
-58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
-59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4)      [RTL-8139=PJ6]
-60 RBTX4927-IOC/04
-61 RBTX4927-IOC/05
-62 RBTX4927-IOC/06
-63 RBTX4927-IOC/07
-
-NOTES:
-SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
-SouthBridge/ISA/pin=0 no pci irq used by this device
-SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
-SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
-SouthBridge/PMC/pin=0 no pci irq used by this device
-SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
-SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
-JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
-*/
+ * I8259A_IRQ_BASE+00
+ * I8259A_IRQ_BASE+01 PS2/Keyboard
+ * I8259A_IRQ_BASE+02 Cascade RBTX4927-ISA (irqs 8-15)
+ * I8259A_IRQ_BASE+03
+ * I8259A_IRQ_BASE+04
+ * I8259A_IRQ_BASE+05
+ * I8259A_IRQ_BASE+06
+ * I8259A_IRQ_BASE+07
+ * I8259A_IRQ_BASE+08
+ * I8259A_IRQ_BASE+09
+ * I8259A_IRQ_BASE+10
+ * I8259A_IRQ_BASE+11
+ * I8259A_IRQ_BASE+12 PS2/Mouse (not supported at this time)
+ * I8259A_IRQ_BASE+13
+ * I8259A_IRQ_BASE+14 IDE
+ * I8259A_IRQ_BASE+15
+ *
+ * MIPS_CPU_IRQ_BASE+00 Software 0
+ * MIPS_CPU_IRQ_BASE+01 Software 1
+ * MIPS_CPU_IRQ_BASE+02 Cascade TX4927-CP0
+ * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+07 CPU TIMER
+ *
+ * TXX9_IRQ_BASE+00
+ * TXX9_IRQ_BASE+01
+ * TXX9_IRQ_BASE+02
+ * TXX9_IRQ_BASE+03 Cascade RBTX4927-IOC
+ * TXX9_IRQ_BASE+04
+ * TXX9_IRQ_BASE+05 RBTX4927 RTL-8019AS ethernet
+ * TXX9_IRQ_BASE+06
+ * TXX9_IRQ_BASE+07
+ * TXX9_IRQ_BASE+08 TX4927 SerialIO Channel 0
+ * TXX9_IRQ_BASE+09 TX4927 SerialIO Channel 1
+ * TXX9_IRQ_BASE+10
+ * TXX9_IRQ_BASE+11
+ * TXX9_IRQ_BASE+12
+ * TXX9_IRQ_BASE+13
+ * TXX9_IRQ_BASE+14
+ * TXX9_IRQ_BASE+15
+ * TXX9_IRQ_BASE+16 TX4927 PCI PCI-C
+ * TXX9_IRQ_BASE+17
+ * TXX9_IRQ_BASE+18
+ * TXX9_IRQ_BASE+19
+ * TXX9_IRQ_BASE+20
+ * TXX9_IRQ_BASE+21
+ * TXX9_IRQ_BASE+22 TX4927 PCI PCI-ERR
+ * TXX9_IRQ_BASE+23 TX4927 PCI PCI-PMA (not used)
+ * TXX9_IRQ_BASE+24
+ * TXX9_IRQ_BASE+25
+ * TXX9_IRQ_BASE+26
+ * TXX9_IRQ_BASE+27
+ * TXX9_IRQ_BASE+28
+ * TXX9_IRQ_BASE+29
+ * TXX9_IRQ_BASE+30
+ * TXX9_IRQ_BASE+31
+ *
+ * RBTX4927_IRQ_IOC+00 FPCIB0 PCI-D (SouthBridge)
+ * RBTX4927_IRQ_IOC+01 FPCIB0 PCI-C (SouthBridge)
+ * RBTX4927_IRQ_IOC+02 FPCIB0 PCI-B (SouthBridge/IDE/pin=1,INTR)
+ * RBTX4927_IRQ_IOC+03 FPCIB0 PCI-A (SouthBridge/USB/pin=4)
+ * RBTX4927_IRQ_IOC+04
+ * RBTX4927_IRQ_IOC+05
+ * RBTX4927_IRQ_IOC+06
+ * RBTX4927_IRQ_IOC+07
+ *
+ * NOTES:
+ * SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
+ * SouthBridge/ISA/pin=0 no pci irq used by this device
+ * SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR
+ * via ISA IRQ14
+ * SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
+ * SouthBridge/PMC/pin=0 no pci irq used by this device
+ * SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
+ * SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
+ * JP7 is not bus master -- do NOT use -- only 4 pci bus master's
+ * allowed -- SouthBridge, JP4, JP5, JP6
+ */
 
 #include <linux/init.h>
 #include <linux/types.h>
@@ -134,7 +135,7 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
         level3 = readb(rbtx4927_imstat_addr) & 0x1f;
         if (level3)
                 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
-        return (sw_irq);
+        return sw_irq;
 }
 
 static void __init toshiba_rbtx4927_irq_ioc_init(void)
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 5c0de54ebdd2..1dc0a5b1956b 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -38,4 +38,5 @@ void __init rbtx4927_prom_init(void)
 {
         prom_init_cmdline();
         add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
+        txx9_sio_putchar_init(TX4927_SIO_REG(0) & 0xfffffffffULL);
 }
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 3da20ea3e55c..0d39bafea794 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -46,12 +46,9 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/pm.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/pci.h>
@@ -103,6 +100,7 @@ static void __init tx4927_pci_setup(void)
                 tx4927_report_pciclk();
                 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
         }
+        tx4927_setup_pcierr_irq();
 }
 
 static void __init tx4937_pci_setup(void)
@@ -149,6 +147,7 @@ static void __init tx4937_pci_setup(void)
                 tx4938_report_pciclk();
                 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
         }
+        tx4938_setup_pcierr_irq();
 }
 
 static void __init rbtx4927_arch_init(void)
@@ -165,17 +164,8 @@ static void __init rbtx4937_arch_init(void)
 #define rbtx4937_arch_init NULL
 #endif /* CONFIG_PCI */
 
-static void __noreturn wait_forever(void)
-{
-        while (1)
-                if (cpu_wait)
-                        (*cpu_wait)();
-}
-
 static void toshiba_rbtx4927_restart(char *command)
 {
-        printk(KERN_NOTICE "System Rebooting...\n");
-
         /* enable the s/w reset register */
         writeb(1, rbtx4927_softresetlock_addr);
 
@@ -186,24 +176,8 @@ static void toshiba_rbtx4927_restart(char *command)
         /* do a s/w reset */
         writeb(1, rbtx4927_softreset_addr);
 
-        /* do something passive while waiting for reset */
-        local_irq_disable();
-        wait_forever();
-        /* no return */
-}
-
-static void toshiba_rbtx4927_halt(void)
-{
-        printk(KERN_NOTICE "System Halted\n");
-        local_irq_disable();
-        wait_forever();
-        /* no return */
-}
-
-static void toshiba_rbtx4927_power_off(void)
-{
-        toshiba_rbtx4927_halt();
-        /* no return */
+        /* fallback */
+        (*_machine_halt)();
 }
 
 static void __init rbtx4927_clock_init(void);
@@ -214,9 +188,6 @@ static void __init rbtx4927_mem_setup(void)
         u32 cp0_config;
         char *argptr;
 
-        /* f/w leaves this on at startup */
-        clear_c0_status(ST0_ERL);
-
         /* enable caches -- HCP5 does this, pmon does not */
         cp0_config = read_c0_config();
         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
@@ -231,37 +202,21 @@ static void __init rbtx4927_mem_setup(void)
         }
 
         _machine_restart = toshiba_rbtx4927_restart;
-        _machine_halt = toshiba_rbtx4927_halt;
-        pm_power_off = toshiba_rbtx4927_power_off;
 
 #ifdef CONFIG_PCI
         txx9_alloc_pci_controller(&txx9_primary_pcic,
                                   RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
                                   RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
+        txx9_board_pcibios_setup = tx4927_pcibios_setup;
 #else
         set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
 #endif
 
-        tx4927_setup_serial();
+        tx4927_sio_init(0, 0);
 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
-        argptr = prom_getcmdline();
-        if (strstr(argptr, "console=") == NULL) {
-                strcat(argptr, " console=ttyS0,38400");
-        }
-#endif
-
-#ifdef CONFIG_ROOT_NFS
-        argptr = prom_getcmdline();
-        if (strstr(argptr, "root=") == NULL) {
-                strcat(argptr, " root=/dev/nfs rw");
-        }
-#endif
-
-#ifdef CONFIG_IP_PNP
-        argptr = prom_getcmdline();
-        if (strstr(argptr, "ip=") == NULL) {
-                strcat(argptr, " ip=any");
-        }
+        argptr = prom_getcmdline();
+        if (!strstr(argptr, "console="))
+                strcat(argptr, " console=ttyS0,38400");
 #endif
 }
 
@@ -324,19 +279,17 @@ static void __init rbtx4927_time_init(void)
         tx4927_time_init(0);
 }
 
-static int __init toshiba_rbtx4927_rtc_init(void)
+static void __init toshiba_rbtx4927_rtc_init(void)
 {
         struct resource res = {
                 .start  = RBTX4927_BRAMRTC_BASE - IO_BASE,
                 .end    = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
                 .flags  = IORESOURCE_MEM,
         };
-        struct platform_device *dev =
-                platform_device_register_simple("rtc-ds1742", -1, &res, 1);
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+        platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 }
 
-static int __init rbtx4927_ne_init(void)
+static void __init rbtx4927_ne_init(void)
 {
         struct resource res[] = {
                 {
@@ -348,36 +301,14 @@ static int __init rbtx4927_ne_init(void)
                         .flags  = IORESOURCE_IRQ,
                 }
         };
-        struct platform_device *dev =
-                platform_device_register_simple("ne", -1,
-                                                res, ARRAY_SIZE(res));
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
-}
-
-/* Watchdog support */
-
-static int __init txx9_wdt_init(unsigned long base)
-{
-        struct resource res = {
-                .start  = base,
-                .end    = base + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        };
-        struct platform_device *dev =
-                platform_device_register_simple("txx9wdt", -1, &res, 1);
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
-}
-
-static int __init rbtx4927_wdt_init(void)
-{
-        return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
+        platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
 }
 
 static void __init rbtx4927_device_init(void)
 {
         toshiba_rbtx4927_rtc_init();
         rbtx4927_ne_init();
-        rbtx4927_wdt_init();
+        tx4927_wdt_init();
 }
 
 struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index 3971a061657a..ca2f8306ce93 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -11,59 +11,57 @@
  */
 
 /*
-IRQ  Device
-
-16   TX4938-CP0/00 Software 0
-17   TX4938-CP0/01 Software 1
-18   TX4938-CP0/02 Cascade TX4938-CP0
-19   TX4938-CP0/03 Multiplexed -- do not use
-20   TX4938-CP0/04 Multiplexed -- do not use
-21   TX4938-CP0/05 Multiplexed -- do not use
-22   TX4938-CP0/06 Multiplexed -- do not use
-23   TX4938-CP0/07 CPU TIMER
-
-24   TX4938-PIC/00
-25   TX4938-PIC/01
-26   TX4938-PIC/02 Cascade RBTX4938-IOC
-27   TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
-28   TX4938-PIC/04
-29   TX4938-PIC/05 TX4938 ETH1
-30   TX4938-PIC/06 TX4938 ETH0
-31   TX4938-PIC/07
-32   TX4938-PIC/08 TX4938 SIO 0
-33   TX4938-PIC/09 TX4938 SIO 1
-34   TX4938-PIC/10 TX4938 DMA0
-35   TX4938-PIC/11 TX4938 DMA1
-36   TX4938-PIC/12 TX4938 DMA2
-37   TX4938-PIC/13 TX4938 DMA3
-38   TX4938-PIC/14
-39   TX4938-PIC/15
-40   TX4938-PIC/16 TX4938 PCIC
-41   TX4938-PIC/17 TX4938 TMR0
-42   TX4938-PIC/18 TX4938 TMR1
-43   TX4938-PIC/19 TX4938 TMR2
-44   TX4938-PIC/20
-45   TX4938-PIC/21
-46   TX4938-PIC/22 TX4938 PCIERR
-47   TX4938-PIC/23
-48   TX4938-PIC/24
-49   TX4938-PIC/25
-50   TX4938-PIC/26
-51   TX4938-PIC/27
-52   TX4938-PIC/28
-53   TX4938-PIC/29
-54   TX4938-PIC/30
-55   TX4938-PIC/31 TX4938 SPI
-
-56 RBTX4938-IOC/00 PCI-D
-57 RBTX4938-IOC/01 PCI-C
-58 RBTX4938-IOC/02 PCI-B
-59 RBTX4938-IOC/03 PCI-A
-60 RBTX4938-IOC/04 RTC
-61 RBTX4938-IOC/05 ATA
-62 RBTX4938-IOC/06 MODEM
-63 RBTX4938-IOC/07 SWINT
-*/
+ * MIPS_CPU_IRQ_BASE+00 Software 0
+ * MIPS_CPU_IRQ_BASE+01 Software 1
+ * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
+ * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
+ * MIPS_CPU_IRQ_BASE+07 CPU TIMER
+ *
+ * TXX9_IRQ_BASE+00
+ * TXX9_IRQ_BASE+01
+ * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
+ * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
+ * TXX9_IRQ_BASE+04
+ * TXX9_IRQ_BASE+05 TX4938 ETH1
+ * TXX9_IRQ_BASE+06 TX4938 ETH0
+ * TXX9_IRQ_BASE+07
+ * TXX9_IRQ_BASE+08 TX4938 SIO 0
+ * TXX9_IRQ_BASE+09 TX4938 SIO 1
+ * TXX9_IRQ_BASE+10 TX4938 DMA0
+ * TXX9_IRQ_BASE+11 TX4938 DMA1
+ * TXX9_IRQ_BASE+12 TX4938 DMA2
+ * TXX9_IRQ_BASE+13 TX4938 DMA3
+ * TXX9_IRQ_BASE+14
+ * TXX9_IRQ_BASE+15
+ * TXX9_IRQ_BASE+16 TX4938 PCIC
+ * TXX9_IRQ_BASE+17 TX4938 TMR0
+ * TXX9_IRQ_BASE+18 TX4938 TMR1
+ * TXX9_IRQ_BASE+19 TX4938 TMR2
+ * TXX9_IRQ_BASE+20
+ * TXX9_IRQ_BASE+21
+ * TXX9_IRQ_BASE+22 TX4938 PCIERR
+ * TXX9_IRQ_BASE+23
+ * TXX9_IRQ_BASE+24
+ * TXX9_IRQ_BASE+25
+ * TXX9_IRQ_BASE+26
+ * TXX9_IRQ_BASE+27
+ * TXX9_IRQ_BASE+28
+ * TXX9_IRQ_BASE+29
+ * TXX9_IRQ_BASE+30
+ * TXX9_IRQ_BASE+31 TX4938 SPI
+ *
+ * RBTX4938_IRQ_IOC+00 PCI-D
+ * RBTX4938_IRQ_IOC+01 PCI-C
+ * RBTX4938_IRQ_IOC+02 PCI-B
+ * RBTX4938_IRQ_IOC+03 PCI-A
+ * RBTX4938_IRQ_IOC+04 RTC
+ * RBTX4938_IRQ_IOC+05 ATA
+ * RBTX4938_IRQ_IOC+06 MODEM
+ * RBTX4938_IRQ_IOC+07 SWINT
+ */
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <asm/mipsregs.h>
@@ -93,9 +91,6 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
         return sw_irq;
 }
 
-/**********************************************************************************/
-/* Functions for ioc                                                              */
-/**********************************************************************************/
 static void __init
 toshiba_rbtx4938_irq_ioc_init(void)
 {
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index ee189519ce5a..d73123cd2ab9 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -22,4 +22,5 @@ void __init rbtx4938_prom_init(void)
         prom_init_cmdline();
 #endif
         add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
+        txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
 }
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 6c2b99bb8af6..9ab48dec0fe8 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -13,9 +13,6 @@
 #include <linux/types.h>
 #include <linux/ioport.h>
 #include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/console.h>
-#include <linux/pm.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 
@@ -28,33 +25,14 @@
 #include <asm/txx9/spi.h>
 #include <asm/txx9pio.h>
 
-static void rbtx4938_machine_halt(void)
-{
-        printk(KERN_NOTICE "System Halted\n");
-        local_irq_disable();
-
-        while (1)
-                __asm__(".set\tmips3\n\t"
-                        "wait\n\t"
-                        ".set\tmips0");
-}
-
-static void rbtx4938_machine_power_off(void)
-{
-        rbtx4938_machine_halt();
-        /* no return */
-}
-
 static void rbtx4938_machine_restart(char *command)
 {
         local_irq_disable();
-
-        printk("Rebooting...");
         writeb(1, rbtx4938_softresetlock_addr);
         writeb(1, rbtx4938_sfvol_addr);
         writeb(1, rbtx4938_softreset_addr);
-        while(1)
-                ;
+        /* fallback */
+        (*_machine_halt)();
 }
 
 static void __init rbtx4938_pci_setup(void)
@@ -121,6 +99,7 @@ static void __init rbtx4938_pci_setup(void)
                 register_pci_controller(c);
                 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
         }
+        tx4938_setup_pcierr_irq();
 #endif /* CONFIG_PCI */
 }
 
@@ -151,19 +130,7 @@ static int __init rbtx4938_ethaddr_init(void)
                 if (sum)
                         printk(KERN_WARNING "seeprom: bad checksum.\n");
         }
-        for (i = 0; i < 2; i++) {
-                unsigned int id =
-                        TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
-                struct platform_device *pdev;
-                if (!(__raw_readq(&tx4938_ccfgptr->pcfg) &
-                      (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
-                        continue;
-                pdev = platform_device_alloc("tc35815-mac", id);
-                if (!pdev ||
-                    platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
-                    platform_device_add(pdev))
-                        platform_device_put(pdev);
-        }
+        tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
 #endif /* CONFIG_PCI */
         return 0;
 }
@@ -193,51 +160,36 @@ static void __init rbtx4938_mem_setup(void)
 
 #ifdef CONFIG_PCI
         txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
+        txx9_board_pcibios_setup = tx4927_pcibios_setup;
 #else
         set_io_port_base(RBTX4938_ETHER_BASE);
 #endif
 
-        tx4938_setup_serial();
+        tx4938_sio_init(7372800, 0);
 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
-        argptr = prom_getcmdline();
-        if (strstr(argptr, "console=") == NULL) {
-                strcat(argptr, " console=ttyS0,38400");
-        }
+        argptr = prom_getcmdline();
+        if (!strstr(argptr, "console="))
+                strcat(argptr, " console=ttyS0,38400");
 #endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
-        printk("PIOSEL: disabling both ata and nand selection\n");
-        local_irq_disable();
+        printk(KERN_INFO "PIOSEL: disabling both ata and nand selection\n");
         txx9_clear64(&tx4938_ccfgptr->pcfg,
                      TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
 #endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
-        printk("PIOSEL: enabling nand selection\n");
+        printk(KERN_INFO "PIOSEL: enabling nand selection\n");
         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 #endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
-        printk("PIOSEL: enabling ata selection\n");
+        printk(KERN_INFO "PIOSEL: enabling ata selection\n");
         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 #endif
 
-#ifdef CONFIG_IP_PNP
-        argptr = prom_getcmdline();
-        if (strstr(argptr, "ip=") == NULL) {
-                strcat(argptr, " ip=any");
-        }
-#endif
-
-
-#ifdef CONFIG_FB
-        {
-                conswitchp = &dummy_con;
-        }
-#endif
-
         rbtx4938_spi_setup();
         pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);    /* updated */
         /* fixup piosel */
@@ -258,11 +210,9 @@ static void __init rbtx4938_mem_setup(void)
         rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
         rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
         if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
-                printk("request resource for fpga failed\n");
+                printk(KERN_ERR "request resource for fpga failed\n");
 
         _machine_restart = rbtx4938_machine_restart;
-        _machine_halt = rbtx4938_machine_halt;
-        pm_power_off = rbtx4938_machine_power_off;
 
         writeb(0xff, rbtx4938_led_addr);
         printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
@@ -270,7 +220,7 @@ static void __init rbtx4938_mem_setup(void)
                readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
 }
 
-static int __init rbtx4938_ne_init(void)
+static void __init rbtx4938_ne_init(void)
 {
         struct resource res[] = {
                 {
@@ -282,10 +232,7 @@ static int __init rbtx4938_ne_init(void)
                         .flags  = IORESOURCE_IRQ,
                 }
         };
-        struct platform_device *dev =
-                platform_device_register_simple("ne", -1,
-                                                res, ARRAY_SIZE(res));
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+        platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
 }
 
 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
@@ -321,24 +268,6 @@ static struct gpio_chip rbtx4938_spi_gpio_chip = {
         .ngpio = 3,
 };
 
-/* SPI support */
-
-static void __init txx9_spi_init(unsigned long base, int irq)
-{
-        struct resource res[] = {
-                {
-                        .start  = base,
-                        .end    = base + 0x20 - 1,
-                        .flags  = IORESOURCE_MEM,
-                }, {
-                        .start  = irq,
-                        .flags  = IORESOURCE_IRQ,
-                },
-        };
-        platform_device_register_simple("spi_txx9", 0,
-                                        res, ARRAY_SIZE(res));
-}
-
 static int __init rbtx4938_spi_init(void)
 {
         struct spi_board_info srtc_info = {
@@ -361,7 +290,7 @@ static int __init rbtx4938_spi_init(void)
         gpio_direction_output(16 + SEEPROM2_CS, 1);
         gpio_request(16 + SEEPROM3_CS, "seeprom3");
         gpio_direction_output(16 + SEEPROM3_CS, 1);
-        txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
+        tx4938_spi_init(0);
         return 0;
 }
 
@@ -372,30 +301,11 @@ static void __init rbtx4938_arch_init(void)
         rbtx4938_spi_init();
 }
 
-/* Watchdog support */
-
-static int __init txx9_wdt_init(unsigned long base)
-{
-        struct resource res = {
-                .start  = base,
-                .end    = base + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        };
-        struct platform_device *dev =
-                platform_device_register_simple("txx9wdt", -1, &res, 1);
-        return IS_ERR(dev) ? PTR_ERR(dev) : 0;
-}
-
-static int __init rbtx4938_wdt_init(void)
-{
-        return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
-}
-
 static void __init rbtx4938_device_init(void)
 {
         rbtx4938_ethaddr_init();
         rbtx4938_ne_init();
-        rbtx4938_wdt_init();
+        tx4938_wdt_init();
 }
 
 struct txx9_board_vec rbtx4938_vec __initdata = {
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
index 11de3606eee6..b7cbb1487af4 100644
--- a/arch/mn10300/kernel/entry.S
+++ b/arch/mn10300/kernel/entry.S
@@ -716,6 +716,12 @@ ENTRY(sys_call_table)
         .long sys_fallocate             /* 325 */
         .long sys_timerfd_settime
         .long sys_timerfd_gettime
+        .long sys_signalfd4
+        .long sys_eventfd2
+        .long sys_epoll_create1         /* 330 */
+        .long sys_dup3
+        .long sys_pipe2
+        .long sys_inotify_init1
 
 
 nr_syscalls=(.-sys_call_table)/4
diff --git a/arch/mn10300/kernel/module.c b/arch/mn10300/kernel/module.c
index 0e4d2f6fa6e8..8fa36893df7a 100644
--- a/arch/mn10300/kernel/module.c
+++ b/arch/mn10300/kernel/module.c
@@ -24,6 +24,7 @@
 #include <linux/fs.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 
 #if 0
 #define DEBUGP printk
@@ -195,7 +196,7 @@ int module_finalize(const Elf_Ehdr *hdr,
                     const Elf_Shdr *sechdrs,
                     struct module *me)
 {
-        return 0;
+        return module_bug_finalize(hdr, sechdrs, me);
 }
 
 /*
@@ -203,4 +204,5 @@ int module_finalize(const Elf_Ehdr *hdr,
  */
 void module_arch_cleanup(struct module *mod)
 {
+        module_bug_cleanup(mod);
 }
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index fe88418167c5..63c9cafda9c4 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -42,6 +42,9 @@ config GENERIC_HARDIRQS
         bool
         default y
 
+config HAVE_GET_USER_PAGES_FAST
+        def_bool PPC64
+
 config HAVE_SETUP_PER_CPU_AREA
         def_bool PPC64
 
@@ -117,6 +120,7 @@ config PPC
         select HAVE_KPROBES
         select HAVE_ARCH_KGDB
         select HAVE_KRETPROBES
+        select HAVE_ARCH_TRACEHOOK
         select HAVE_LMB
         select HAVE_DMA_ATTRS if PPC64
         select USE_GENERIC_SMP_HELPERS if SMP
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 8c8aadbe9563..4ebc52a19f0a 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -97,7 +97,7 @@ config IRQSTACKS
 
 config VIRQ_DEBUG
         bool "Expose hardware/virtual IRQ mapping via debugfs"
-        depends on DEBUG_FS && PPC_MERGE
+        depends on DEBUG_FS
         help
           This option will show the mapping relationship between hardware irq
           numbers and virtual irq numbers. The mapping is exposed via debugfs
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 7345743d3d96..fbc930410ff6 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -68,6 +68,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <132000000>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index e74c045a0f8c..b157d1885a28 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -51,6 +51,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 8dfab5662585..700e076ef3f5 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -52,6 +52,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;                    // from bootloader
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 49ca3497eefb..cdd3063258ea 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -50,6 +50,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;                    // from bootloader
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index ba586cb7afbb..783241c00240 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -57,6 +57,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 3701dae1ee02..a3b76a709951 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -61,6 +61,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <264000000>;
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 8acd1d6577f2..89c9202f8bd7 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -149,18 +149,14 @@
                 };
 
                 crypto@30000 {
-                        compatible = "fsl,sec2-crypto";
+                        compatible = "fsl,sec2.0";
                         reg = <0x30000 0x10000>;
-                        interrupts = <11 8>;
+                        interrupts = <11 0x8>;
                         interrupt-parent = <&ipic>;
-                        num-channels = <4>;
-                        channel-fifo-len = <24>;
-                        exec-units-mask = <0x7e>;
-                        /*
-                         * desc mask is for rev1.x, we need runtime fixup
-                         * for >=2.x
-                         */
-                        descriptor-types-mask = <0x1010ebf>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x7e>;
+                        fsl,descriptor-types-mask = <0x01010ebf>;
                 };
 
                 ipic: interrupt-controller@700 {
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 0a700cb5f611..432782b6d20a 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -117,6 +117,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 29c8c76a58f7..ed32c8ddafe3 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -117,6 +117,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index d641a8985ea3..f4db9ed4a301 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -117,6 +117,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x00100000>;
                 reg = <0xe0000000 0x00000200>;
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index 02cfa24a1695..1505d6855eff 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -49,6 +49,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xffe00000 0x100000>;
                 reg = <0xffe00000 0x1000>;
                 bus-frequency = <0>;            // Filled out by uboot.
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index f2273a872b11..9568bfaff8f7 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -53,6 +53,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x100000>;
                 reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index c4469f19ff82..6480f4fd96e0 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -53,6 +53,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x100000>;
                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 7d3829d3495e..f1fb20737e3e 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -54,6 +54,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
 
                 ranges = <0x0 0xe0000000 0x100000>;
                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index d84466bb7eca..431b496270dc 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -58,6 +58,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x100000>;
                 reg = <0xe0000000 0x1000>;      // CCSRBAR
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index e03a78006283..d833a5c4f476 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -53,6 +53,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x100000>;
                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index ba8159de040b..4d1f2f284094 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -53,6 +53,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x100000>;
                 reg = <0xe0000000 0x200>;
                 bus-frequency = <330000000>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 9c30a34821dc..a15f10343f53 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -60,6 +60,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xe0000000 0x100000>;
                 reg = <0xe0000000 0x1000>;
                 bus-frequency = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 08c61e3daecc..e124dd18fb5a 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -68,6 +68,7 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
                 device_type = "soc";
+                compatible = "simple-bus";
                 ranges = <0x0 0xffe00000 0x100000>;
                 reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                 bus-frequency = <0>;            // Filled out by uboot.
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 666185f59459..3b3a1062cb25 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -202,6 +202,11 @@
                         fsl,has-rstcr;
                 };
 
+                wdt@e4000 {
+                        compatible = "fsl,mpc8610-wdt";
+                        reg = <0xe4000 0x100>;
+                };
+
                 i2s@16000 {
                         compatible = "fsl,mpc8610-ssi";
                         cell-index = <0>;
diff --git a/arch/powerpc/boot/io.h b/arch/powerpc/boot/io.h
index ccaedaec50d5..7c09f4861fe1 100644
--- a/arch/powerpc/boot/io.h
+++ b/arch/powerpc/boot/io.h
@@ -6,7 +6,7 @@
 /*
  * Low-level I/O routines.
  *
- * Copied from <file:include/asm-powerpc/io.h> (which has no copyright)
+ * Copied from <file:arch/powerpc/include/asm/io.h> (which has no copyright)
  */
 static inline int in_8(const volatile unsigned char *addr)
 {
diff --git a/arch/powerpc/include/asm/8253pit.h b/arch/powerpc/include/asm/8253pit.h
new file mode 100644
index 000000000000..b70d6e53b303
--- /dev/null
+++ b/arch/powerpc/include/asm/8253pit.h
@@ -0,0 +1,10 @@
+#ifndef _ASM_POWERPC_8253PIT_H
+#define _ASM_POWERPC_8253PIT_H
+
+/*
+ * 8253/8254 Programmable Interval Timer
+ */
+
+#define PIT_TICK_RATE   1193182UL
+
+#endif  /* _ASM_POWERPC_8253PIT_H */
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
new file mode 100644
index 000000000000..4b0e15206006
--- /dev/null
+++ b/arch/powerpc/include/asm/8xx_immap.h
@@ -0,0 +1,564 @@
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions.  It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try.  -- Dan
+ */
+#ifdef __KERNEL__
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef struct sys_conf {
+        uint    sc_siumcr;
+        uint    sc_sypcr;
+        uint    sc_swt;
+        char    res1[2];
+        ushort  sc_swsr;
+        uint    sc_sipend;
+        uint    sc_simask;
+        uint    sc_siel;
+        uint    sc_sivec;
+        uint    sc_tesr;
+        char    res2[0xc];
+        uint    sc_sdcr;
+        char    res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+        uint    pcmc_pbr0;
+        uint    pcmc_por0;
+        uint    pcmc_pbr1;
+        uint    pcmc_por1;
+        uint    pcmc_pbr2;
+        uint    pcmc_por2;
+        uint    pcmc_pbr3;
+        uint    pcmc_por3;
+        uint    pcmc_pbr4;
+        uint    pcmc_por4;
+        uint    pcmc_pbr5;
+        uint    pcmc_por5;
+        uint    pcmc_pbr6;
+        uint    pcmc_por6;
+        uint    pcmc_pbr7;
+        uint    pcmc_por7;
+        char    res1[0x20];
+        uint    pcmc_pgcra;
+        uint    pcmc_pgcrb;
+        uint    pcmc_pscr;
+        char    res2[4];
+        uint    pcmc_pipr;
+        char    res3[4];
+        uint    pcmc_per;
+        char    res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct  mem_ctlr {
+        uint    memc_br0;
+        uint    memc_or0;
+        uint    memc_br1;
+        uint    memc_or1;
+        uint    memc_br2;
+        uint    memc_or2;
+        uint    memc_br3;
+        uint    memc_or3;
+        uint    memc_br4;
+        uint    memc_or4;
+        uint    memc_br5;
+        uint    memc_or5;
+        uint    memc_br6;
+        uint    memc_or6;
+        uint    memc_br7;
+        uint    memc_or7;
+        char    res1[0x24];
+        uint    memc_mar;
+        uint    memc_mcr;
+        char    res2[4];
+        uint    memc_mamr;
+        uint    memc_mbmr;
+        ushort  memc_mstat;
+        ushort  memc_mptpr;
+        uint    memc_mdr;
+        char    res3[0x80];
+} memctl8xx_t;
+
+/*-----------------------------------------------------------------------
+ * BR - Memory Controler: Base Register                                 16-9
+ */
+#define BR_BA_MSK       0xffff8000      /* Base Address Mask                    */
+#define BR_AT_MSK       0x00007000      /* Address Type Mask                    */
+#define BR_PS_MSK       0x00000c00      /* Port Size Mask                       */
+#define BR_PS_32        0x00000000      /* 32 bit port size                     */
+#define BR_PS_16        0x00000800      /* 16 bit port size                     */
+#define BR_PS_8         0x00000400      /*  8 bit port size                     */
+#define BR_PARE         0x00000200      /* Parity Enable                        */
+#define BR_WP           0x00000100      /* Write Protect                        */
+#define BR_MS_MSK       0x000000c0      /* Machine Select Mask                  */
+#define BR_MS_GPCM      0x00000000      /* G.P.C.M. Machine Select              */
+#define BR_MS_UPMA      0x00000080      /* U.P.M.A Machine Select               */
+#define BR_MS_UPMB      0x000000c0      /* U.P.M.B Machine Select               */
+#define BR_V            0x00000001      /* Bank Valid                           */
+
+/*-----------------------------------------------------------------------
+ * OR - Memory Controler: Option Register                               16-11
+ */
+#define OR_AM_MSK       0xffff8000      /* Address Mask Mask                    */
+#define OR_ATM_MSK      0x00007000      /* Address Type Mask Mask               */
+#define OR_CSNT_SAM     0x00000800      /* Chip Select Negation Time/ Start     */
+                                        /* Address Multiplex                    */
+#define OR_ACS_MSK      0x00000600      /* Address to Chip Select Setup mask    */
+#define OR_ACS_DIV1     0x00000000      /* CS is output at the same time        */
+#define OR_ACS_DIV4     0x00000400      /* CS is output 1/4 a clock later       */
+#define OR_ACS_DIV2     0x00000600      /* CS is output 1/2 a clock later       */
+#define OR_G5LA         0x00000400      /* Output #GPL5 on #GPL_A5              */
+#define OR_G5LS         0x00000200      /* Drive #GPL high on falling edge of...*/
+#define OR_BI           0x00000100      /* Burst inhibit                        */
+#define OR_SCY_MSK      0x000000f0      /* Cycle Length in Clocks               */
+#define OR_SCY_0_CLK    0x00000000      /* 0 clock cycles wait states           */
+#define OR_SCY_1_CLK    0x00000010      /* 1 clock cycles wait states           */
+#define OR_SCY_2_CLK    0x00000020      /* 2 clock cycles wait states           */
+#define OR_SCY_3_CLK    0x00000030      /* 3 clock cycles wait states           */
+#define OR_SCY_4_CLK    0x00000040      /* 4 clock cycles wait states           */
+#define OR_SCY_5_CLK    0x00000050      /* 5 clock cycles wait states           */
+#define OR_SCY_6_CLK    0x00000060      /* 6 clock cycles wait states           */
+#define OR_SCY_7_CLK    0x00000070      /* 7 clock cycles wait states           */
+#define OR_SCY_8_CLK    0x00000080      /* 8 clock cycles wait states           */
+#define OR_SCY_9_CLK    0x00000090      /* 9 clock cycles wait states           */
+#define OR_SCY_10_CLK   0x000000a0      /* 10 clock cycles wait states          */
+#define OR_SCY_11_CLK   0x000000b0      /* 11 clock cycles wait states          */
+#define OR_SCY_12_CLK   0x000000c0      /* 12 clock cycles wait states          */
+#define OR_SCY_13_CLK   0x000000d0      /* 13 clock cycles wait states          */
+#define OR_SCY_14_CLK   0x000000e0      /* 14 clock cycles wait states          */
+#define OR_SCY_15_CLK   0x000000f0      /* 15 clock cycles wait states          */
+#define OR_SETA         0x00000008      /* External Transfer Acknowledge        */
+#define OR_TRLX         0x00000004      /* Timing Relaxed                       */
+#define OR_EHTR         0x00000002      /* Extended Hold Time on Read           */
+
+/* System Integration Timers.
+*/
+typedef struct  sys_int_timers {
+        ushort  sit_tbscr;
+        char    res0[0x02];
+        uint    sit_tbreff0;
+        uint    sit_tbreff1;
+        char    res1[0x14];
+        ushort  sit_rtcsc;
+        char    res2[0x02];
+        uint    sit_rtc;
+        uint    sit_rtsec;
+        uint    sit_rtcal;
+        char    res3[0x10];
+        ushort  sit_piscr;
+        char    res4[2];
+        uint    sit_pitc;
+        uint    sit_pitr;
+        char    res5[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK        ((ushort)0xff00)
+#define TBSCR_REFA              ((ushort)0x0080)
+#define TBSCR_REFB              ((ushort)0x0040)
+#define TBSCR_REFAE             ((ushort)0x0008)
+#define TBSCR_REFBE             ((ushort)0x0004)
+#define TBSCR_TBF               ((ushort)0x0002)
+#define TBSCR_TBE               ((ushort)0x0001)
+
+#define RTCSC_RTCIRQ_MASK       ((ushort)0xff00)
+#define RTCSC_SEC               ((ushort)0x0080)
+#define RTCSC_ALR               ((ushort)0x0040)
+#define RTCSC_38K               ((ushort)0x0010)
+#define RTCSC_SIE               ((ushort)0x0008)
+#define RTCSC_ALE               ((ushort)0x0004)
+#define RTCSC_RTF               ((ushort)0x0002)
+#define RTCSC_RTE               ((ushort)0x0001)
+
+#define PISCR_PIRQ_MASK         ((ushort)0xff00)
+#define PISCR_PS                ((ushort)0x0080)
+#define PISCR_PIE               ((ushort)0x0004)
+#define PISCR_PTF               ((ushort)0x0002)
+#define PISCR_PTE               ((ushort)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+        uint    car_sccr;
+        uint    car_plprcr;
+        uint    car_rsr;
+        char    res[0x74];        /* Reserved area                  */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+        uint    sitk_tbscrk;
+        uint    sitk_tbreff0k;
+        uint    sitk_tbreff1k;
+        uint    sitk_tbk;
+        char    res1[0x10];
+        uint    sitk_rtcsck;
+        uint    sitk_rtck;
+        uint    sitk_rtseck;
+        uint    sitk_rtcalk;
+        char    res2[0x10];
+        uint    sitk_piscrk;
+        uint    sitk_pitck;
+        char    res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+        uint    cark_sccrk;
+        uint    cark_plprcrk;
+        uint    cark_rsrk;
+        char    res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY       ((unsigned int)0x55ccaa33)
+
+/* Video interface.  MPC823 Only.
+*/
+typedef struct vid823 {
+        ushort  vid_vccr;
+        ushort  res1;
+        u_char  vid_vsr;
+        u_char  res2;
+        u_char  vid_vcmr;
+        u_char  res3;
+        uint    vid_vbcb;
+        uint    res4;
+        uint    vid_vfcr0;
+        uint    vid_vfaa0;
+        uint    vid_vfba0;
+        uint    vid_vfcr1;
+        uint    vid_vfaa1;
+        uint    vid_vfba1;
+        u_char  res5[0x18];
+} vid823_t;
+
+/* LCD interface.  823 Only.
+*/
+typedef struct lcd {
+        uint    lcd_lccr;
+        uint    lcd_lchcr;
+        uint    lcd_lcvcr;
+        char    res1[4];
+        uint    lcd_lcfaa;
+        uint    lcd_lcfba;
+        char    lcd_lcsr;
+        char    res2[0x7];
+} lcd823_t;
+
+/* I2C
+*/
+typedef struct i2c {
+        u_char  i2c_i2mod;
+        char    res1[3];
+        u_char  i2c_i2add;
+        char    res2[3];
+        u_char  i2c_i2brg;
+        char    res3[3];
+        u_char  i2c_i2com;
+        char    res4[3];
+        u_char  i2c_i2cer;
+        char    res5[3];
+        u_char  i2c_i2cmr;
+        char    res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+        char    res1[4];
+        uint    sdma_sdar;
+        u_char  sdma_sdsr;
+        char    res3[3];
+        u_char  sdma_sdmr;
+        char    res4[3];
+        u_char  sdma_idsr1;
+        char    res5[3];
+        u_char  sdma_idmr1;
+        char    res6[3];
+        u_char  sdma_idsr2;
+        char    res7[3];
+        u_char  sdma_idmr2;
+        char    res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+        ushort  cpic_civr;
+        char    res[0xe];
+        uint    cpic_cicr;
+        uint    cpic_cipr;
+        uint    cpic_cimr;
+        uint    cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+        ushort  iop_padir;
+        ushort  iop_papar;
+        ushort  iop_paodr;
+        ushort  iop_padat;
+        char    res1[8];
+        ushort  iop_pcdir;
+        ushort  iop_pcpar;
+        ushort  iop_pcso;
+        ushort  iop_pcdat;
+        ushort  iop_pcint;
+        char    res2[6];
+        ushort  iop_pddir;
+        ushort  iop_pdpar;
+        char    res3[2];
+        ushort  iop_pddat;
+        uint    utmode;
+        char    res4[4];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+        ushort  cpmt_tgcr;
+        char    res1[0xe];
+        ushort  cpmt_tmr1;
+        ushort  cpmt_tmr2;
+        ushort  cpmt_trr1;
+        ushort  cpmt_trr2;
+        ushort  cpmt_tcr1;
+        ushort  cpmt_tcr2;
+        ushort  cpmt_tcn1;
+        ushort  cpmt_tcn2;
+        ushort  cpmt_tmr3;
+        ushort  cpmt_tmr4;
+        ushort  cpmt_trr3;
+        ushort  cpmt_trr4;
+        ushort  cpmt_tcr3;
+        ushort  cpmt_tcr4;
+        ushort  cpmt_tcn3;
+        ushort  cpmt_tcn4;
+        ushort  cpmt_ter1;
+        ushort  cpmt_ter2;
+        ushort  cpmt_ter3;
+        ushort  cpmt_ter4;
+        char    res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc {            /* Serial communication channels */
+        uint    scc_gsmrl;
+        uint    scc_gsmrh;
+        ushort  scc_psmr;
+        char    res1[2];
+        ushort  scc_todr;
+        ushort  scc_dsr;
+        ushort  scc_scce;
+        char    res2[2];
+        ushort  scc_sccm;
+        char    res3;
+        u_char  scc_sccs;
+        char    res4[8];
+} scc_t;
+
+typedef struct smc {            /* Serial management channels */
+        char    res1[2];
+        ushort  smc_smcmr;
+        char    res2[2];
+        u_char  smc_smce;
+        char    res3[3];
+        u_char  smc_smcm;
+        char    res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+
+typedef struct fec {
+        uint    fec_addr_low;           /* lower 32 bits of station address     */
+        ushort  fec_addr_high;          /* upper 16 bits of station address     */
+        ushort  res1;                   /* reserved                             */
+        uint    fec_hash_table_high;    /* upper 32-bits of hash table          */
+        uint    fec_hash_table_low;     /* lower 32-bits of hash table          */
+        uint    fec_r_des_start;        /* beginning of Rx descriptor ring      */
+        uint    fec_x_des_start;        /* beginning of Tx descriptor ring      */
+        uint    fec_r_buff_size;        /* Rx buffer size                       */
+        uint    res2[9];                /* reserved                             */
+        uint    fec_ecntrl;             /* ethernet control register            */
+        uint    fec_ievent;             /* interrupt event register             */
+        uint    fec_imask;              /* interrupt mask register              */
+        uint    fec_ivec;               /* interrupt level and vector status    */
+        uint    fec_r_des_active;       /* Rx ring updated flag                 */
+        uint    fec_x_des_active;       /* Tx ring updated flag                 */
+        uint    res3[10];               /* reserved                             */
+        uint    fec_mii_data;           /* MII data register                    */
+        uint    fec_mii_speed;          /* MII speed control register           */
+        uint    res4[17];               /* reserved                             */
+        uint    fec_r_bound;            /* end of RAM (read-only)               */
+        uint    fec_r_fstart;           /* Rx FIFO start address                */
+        uint    res5[6];                /* reserved                             */
+        uint    fec_x_fstart;           /* Tx FIFO start address                */
+        uint    res6[17];               /* reserved                             */
+        uint    fec_fun_code;           /* fec SDMA function code               */
+        uint    res7[3];                /* reserved                             */
+        uint    fec_r_cntrl;            /* Rx control register                  */
+        uint    fec_r_hash;             /* Rx hash register                     */
+        uint    res8[14];               /* reserved                             */
+        uint    fec_x_cntrl;            /* Tx control register                  */
+        uint    res9[0x1e];             /* reserved                             */
+} fec_t;
+
+/* The FEC and LCD color map share the same address space....
+ * I guess we will never see an 823T :-).
+ */
+union fec_lcd {
+        fec_t   fl_un_fec;
+        u_char  fl_un_cmap[0x200];
+};
+
+typedef struct comm_proc {
+        /* General control and status registers.
+        */
+        ushort  cp_cpcr;
+        u_char  res1[2];
+        ushort  cp_rccr;
+        u_char  res2;
+        u_char  cp_rmds;
+        u_char  res3[4];
+        ushort  cp_cpmcr1;
+        ushort  cp_cpmcr2;
+        ushort  cp_cpmcr3;
+        ushort  cp_cpmcr4;
+        u_char  res4[2];
+        ushort  cp_rter;
+        u_char  res5[2];
+        ushort  cp_rtmr;
+        u_char  res6[0x14];
+
+        /* Baud rate generators.
+        */
+        uint    cp_brgc1;
+        uint    cp_brgc2;
+        uint    cp_brgc3;
+        uint    cp_brgc4;
+
+        /* Serial Communication Channels.
+        */
+        scc_t   cp_scc[4];
+
+        /* Serial Management Channels.
+        */
+        smc_t   cp_smc[2];
+
+        /* Serial Peripheral Interface.
+        */
+        ushort  cp_spmode;
+        u_char  res7[4];
+        u_char  cp_spie;
+        u_char  res8[3];
+        u_char  cp_spim;
+        u_char  res9[2];
+        u_char  cp_spcom;
+        u_char  res10[2];
+
+        /* Parallel Interface Port.
+        */
+        u_char  res11[2];
+        ushort  cp_pipc;
+        u_char  res12[2];
+        ushort  cp_ptpr;
+        uint    cp_pbdir;
+        uint    cp_pbpar;
+        u_char  res13[2];
+        ushort  cp_pbodr;
+        uint    cp_pbdat;
+
+        /* Port E - MPC87x/88x only.
+         */
+        uint    cp_pedir;
+        uint    cp_pepar;
+        uint    cp_peso;
+        uint    cp_peodr;
+        uint    cp_pedat;
+
+        /* Communications Processor Timing Register -
+           Contains RMII Timing for the FECs on MPC87x/88x only.
+        */
+        uint    cp_cptr;
+
+        /* Serial Interface and Time Slot Assignment.
+        */
+        uint    cp_simode;
+        u_char  cp_sigmr;
+        u_char  res15;
+        u_char  cp_sistr;
+        u_char  cp_sicmr;
+        u_char  res16[4];
+        uint    cp_sicr;
+        uint    cp_sirp;
+        u_char  res17[0xc];
+
+        /* 256 bytes of MPC823 video controller RAM array.
+        */
+        u_char  cp_vcram[0x100];
+        u_char  cp_siram[0x200];
+
+        /* The fast ethernet controller is not really part of the CPM,
+         * but it resides in the address space.
+         * The LCD color map is also here.
+         */
+        union   fec_lcd fl_un;
+#define cp_fec          fl_un.fl_un_fec
+#define lcd_cmap        fl_un.fl_un_cmap
+        char    res18[0xE00];
+
+        /* The DUET family has a second FEC here */
+        fec_t   cp_fec2;
+#define cp_fec1 cp_fec  /* consistency macro */
+
+        /* Dual Ported RAM follows.
+         * There are many different formats for this memory area
+         * depending upon the devices used and options chosen.
+         * Some processors don't have all of it populated.
+         */
+        u_char  cp_dpmem[0x1C00];       /* BD / Data / ucode */
+        u_char  cp_dparam[0x400];       /* Parameter RAM */
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+        sysconf8xx_t    im_siu_conf;    /* SIU Configuration */
+        pcmconf8xx_t    im_pcmcia;      /* PCMCIA Configuration */
+        memctl8xx_t     im_memctl;      /* Memory Controller */
+        sit8xx_t        im_sit;         /* System integration timers */
+        car8xx_t        im_clkrst;      /* Clocks and reset */
+        sitk8xx_t       im_sitk;        /* Sys int timer keys */
+        cark8xx_t       im_clkrstk;     /* Clocks and reset keys */
+        vid823_t        im_vid;         /* Video (823 only) */
+        lcd823_t        im_lcd;         /* LCD (823 only) */
+        i2c8xx_t        im_i2c;         /* I2C control/status */
+        sdma8xx_t       im_sdma;        /* SDMA control/status */
+        cpic8xx_t       im_cpic;        /* CPM Interrupt Controller */
+        iop8xx_t        im_ioport;      /* IO Port control/status */
+        cpmtimer8xx_t   im_cpmtimer;    /* CPM timers */
+        cpm8xx_t        im_cpm;         /* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
new file mode 100644
index 000000000000..5ab7d7fe198c
--- /dev/null
+++ b/arch/powerpc/include/asm/Kbuild
@@ -0,0 +1,37 @@
+include include/asm-generic/Kbuild.asm
+
+header-y += auxvec.h
+header-y += ioctls.h
+header-y += sembuf.h
+header-y += siginfo.h
+header-y += stat.h
+header-y += errno.h
+header-y += ipcbuf.h
+header-y += msgbuf.h
+header-y += shmbuf.h
+header-y += socket.h
+header-y += termbits.h
+header-y += fcntl.h
+header-y += poll.h
+header-y += sockios.h
+header-y += ucontext.h
+header-y += ioctl.h
+header-y += linkage.h
+header-y += resource.h
+header-y += sigcontext.h
+header-y += statfs.h
+header-y += ps3fb.h
+
+unifdef-y += bootx.h
+unifdef-y += byteorder.h
+unifdef-y += cputable.h
+unifdef-y += elf.h
+unifdef-y += nvram.h
+unifdef-y += param.h
+unifdef-y += posix_types.h
+unifdef-y += seccomp.h
+unifdef-y += signal.h
+unifdef-y += spu_info.h
+unifdef-y += termios.h
+unifdef-y += types.h
+unifdef-y += unistd.h
diff --git a/arch/powerpc/include/asm/a.out.h b/arch/powerpc/include/asm/a.out.h
new file mode 100644
index 000000000000..89cead6b176e
--- /dev/null
+++ b/arch/powerpc/include/asm/a.out.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_POWERPC_A_OUT_H
+#define _ASM_POWERPC_A_OUT_H
+
+struct exec
+{
+        unsigned long a_info;   /* Use macros N_MAGIC, etc for access */
+        unsigned a_text;        /* length of text, in bytes */
+        unsigned a_data;        /* length of data, in bytes */
+        unsigned a_bss;         /* length of uninitialized data area for file, in bytes */
+        unsigned a_syms;        /* length of symbol table data in file, in bytes */
+        unsigned a_entry;       /* start address */
+        unsigned a_trsize;      /* length of relocation info for text, in bytes */
+        unsigned a_drsize;      /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+#endif /* _ASM_POWERPC_A_OUT_H */
diff --git a/arch/powerpc/include/asm/abs_addr.h b/arch/powerpc/include/asm/abs_addr.h
new file mode 100644
index 000000000000..98324c5a8286
--- /dev/null
+++ b/arch/powerpc/include/asm/abs_addr.h
@@ -0,0 +1,75 @@
+#ifndef _ASM_POWERPC_ABS_ADDR_H
+#define _ASM_POWERPC_ABS_ADDR_H
+#ifdef __KERNEL__
+
+
+/*
+ * c 2001 PPC 64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/lmb.h>
+
+#include <asm/types.h>
+#include <asm/page.h>
+#include <asm/prom.h>
+#include <asm/firmware.h>
+
+struct mschunks_map {
+        unsigned long num_chunks;
+        unsigned long chunk_size;
+        unsigned long chunk_shift;
+        unsigned long chunk_mask;
+        u32 *mapping;
+};
+
+extern struct mschunks_map mschunks_map;
+
+/* Chunks are 256 KB */
+#define MSCHUNKS_CHUNK_SHIFT    (18)
+#define MSCHUNKS_CHUNK_SIZE     (1UL << MSCHUNKS_CHUNK_SHIFT)
+#define MSCHUNKS_OFFSET_MASK    (MSCHUNKS_CHUNK_SIZE - 1)
+
+static inline unsigned long chunk_to_addr(unsigned long chunk)
+{
+        return chunk << MSCHUNKS_CHUNK_SHIFT;
+}
+
+static inline unsigned long addr_to_chunk(unsigned long addr)
+{
+        return addr >> MSCHUNKS_CHUNK_SHIFT;
+}
+
+static inline unsigned long phys_to_abs(unsigned long pa)
+{
+        unsigned long chunk;
+
+        /* This is a no-op on non-iSeries */
+        if (!firmware_has_feature(FW_FEATURE_ISERIES))
+                return pa;
+
+        chunk = addr_to_chunk(pa);
+
+        if (chunk < mschunks_map.num_chunks)
+                chunk = mschunks_map.mapping[chunk];
+
+        return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK);
+}
+
+/* Convenience macros */
+#define virt_to_abs(va) phys_to_abs(__pa(va))
+#define abs_to_virt(aa) __va(aa)
+
+/*
+ * Converts Virtual Address to Real Address for
+ * Legacy iSeries Hypervisor calls
+ */
+#define iseries_hv_addr(virtaddr)       \
+        (0x8000000000000000 | virt_to_abs(virtaddr))
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/arch/powerpc/include/asm/agp.h b/arch/powerpc/include/asm/agp.h
new file mode 100644
index 000000000000..86455c4c31ee
--- /dev/null
+++ b/arch/powerpc/include/asm/agp.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_POWERPC_AGP_H
+#define _ASM_POWERPC_AGP_H
+#ifdef __KERNEL__
+
+#include <asm/io.h>
+
+#define map_page_into_agp(page)
+#define unmap_page_from_agp(page)
+#define flush_agp_cache() mb()
+
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_AGP_H */
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
new file mode 100644
index 000000000000..8f0fe7971949
--- /dev/null
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -0,0 +1,69 @@
+#ifndef _ASM_POWERPC_ASM_COMPAT_H
+#define _ASM_POWERPC_ASM_COMPAT_H
+
+#include <asm/types.h>
+
+#ifdef __ASSEMBLY__
+#  define stringify_in_c(...)   __VA_ARGS__
+#  define ASM_CONST(x)          x
+#else
+/* This version of stringify will deal with commas... */
+#  define __stringify_in_c(...) #__VA_ARGS__
+#  define stringify_in_c(...)   __stringify_in_c(__VA_ARGS__) " "
+#  define __ASM_CONST(x)        x##UL
+#  define ASM_CONST(x)          __ASM_CONST(x)
+#endif
+
+
+#ifdef __powerpc64__
+
+/* operations for longs and pointers */
+#define PPC_LL          stringify_in_c(ld)
+#define PPC_STL         stringify_in_c(std)
+#define PPC_LCMPI       stringify_in_c(cmpdi)
+#define PPC_LONG        stringify_in_c(.llong)
+#define PPC_LONG_ALIGN  stringify_in_c(.balign 8)
+#define PPC_TLNEI       stringify_in_c(tdnei)
+#define PPC_LLARX       stringify_in_c(ldarx)
+#define PPC_STLCX       stringify_in_c(stdcx.)
+#define PPC_CNTLZL      stringify_in_c(cntlzd)
+
+/* Move to CR, single-entry optimized version. Only available
+ * on POWER4 and later.
+ */
+#ifdef CONFIG_POWER4_ONLY
+#define PPC_MTOCRF      stringify_in_c(mtocrf)
+#else
+#define PPC_MTOCRF      stringify_in_c(mtcrf)
+#endif
+
+#else /* 32-bit */
+
+/* operations for longs and pointers */
+#define PPC_LL          stringify_in_c(lwz)
+#define PPC_STL         stringify_in_c(stw)
+#define PPC_LCMPI       stringify_in_c(cmpwi)
+#define PPC_LONG        stringify_in_c(.long)
+#define PPC_LONG_ALIGN  stringify_in_c(.balign 4)
+#define PPC_TLNEI       stringify_in_c(twnei)
+#define PPC_LLARX       stringify_in_c(lwarx)
+#define PPC_STLCX       stringify_in_c(stwcx.)
+#define PPC_CNTLZL      stringify_in_c(cntlzw)
+#define PPC_MTOCRF      stringify_in_c(mtcrf)
+
+#endif
+
+#ifdef __KERNEL__
+#ifdef CONFIG_IBM405_ERR77
+/* Erratum #77 on the 405 means we need a sync or dcbt before every
+ * stwcx.  The old ATOMIC_SYNC_FIX covered some but not all of this.
+ */
+#define PPC405_ERR77(ra,rb)     stringify_in_c(dcbt     ra, rb;)
+#define PPC405_ERR77_SYNC       stringify_in_c(sync;)
+#else
+#define PPC405_ERR77(ra,rb)
+#define PPC405_ERR77_SYNC
+#endif
+#endif
+
+#endif /* _ASM_POWERPC_ASM_COMPAT_H */
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
new file mode 100644
index 000000000000..f3fc733758f5
--- /dev/null
+++ b/arch/powerpc/include/asm/atomic.h
@@ -0,0 +1,479 @@
+#ifndef _ASM_POWERPC_ATOMIC_H_
+#define _ASM_POWERPC_ATOMIC_H_
+
+/*
+ * PowerPC atomic operations
+ */
+
+typedef struct { int counter; } atomic_t;
+
+#ifdef __KERNEL__
+#include <linux/compiler.h>
+#include <asm/synch.h>
+#include <asm/asm-compat.h>
+#include <asm/system.h>
+
+#define ATOMIC_INIT(i)          { (i) }
+
+static __inline__ int atomic_read(const atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
+
+        return t;
+}
+
+static __inline__ void atomic_set(atomic_t *v, int i)
+{
+        __asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
+}
+
+static __inline__ void atomic_add(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%3         # atomic_add\n\
+        add     %0,%2,%0\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_add_return(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%2         # atomic_add_return\n\
+        add     %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %0,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (a), "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
+
+static __inline__ void atomic_sub(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%3         # atomic_sub\n\
+        subf    %0,%2,%0\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_sub_return(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%2         # atomic_sub_return\n\
+        subf    %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %0,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (a), "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+static __inline__ void atomic_inc(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2         # atomic_inc\n\
+        addic   %0,%0,1\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %0,0,%2 \n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_inc_return(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%1         # atomic_inc_return\n\
+        addic   %0,%0,1\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+static __inline__ void atomic_dec(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2         # atomic_dec\n\
+        addic   %0,%0,-1\n"
+        PPC405_ERR77(0,%2)\
+"       stwcx.  %0,0,%2\n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_dec_return(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%1         # atomic_dec_return\n\
+        addic   %0,%0,-1\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+/**
+ * atomic_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int t;
+
+        __asm__ __volatile__ (
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%1         # atomic_add_unless\n\
+        cmpw    0,%0,%3 \n\
+        beq-    2f \n\
+        add     %0,%2,%0 \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %0,0,%1 \n\
+        bne-    1b \n"
+        ISYNC_ON_SMP
+"       subf    %0,%2,%0 \n\
+2:"
+        : "=&r" (t)
+        : "r" (&v->counter), "r" (a), "r" (u)
+        : "cc", "memory");
+
+        return t != u;
+}
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+#define atomic_sub_and_test(a, v)       (atomic_sub_return((a), (v)) == 0)
+#define atomic_dec_and_test(v)          (atomic_dec_return((v)) == 0)
+
+/*
+ * Atomically test *v and decrement if it is greater than 0.
+ * The function returns the old value of *v minus 1, even if
+ * the atomic variable, v, was not decremented.
+ */
+static __inline__ int atomic_dec_if_positive(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
+        cmpwi   %0,1\n\
+        addi    %0,%0,-1\n\
+        blt-    2f\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"     : "=&b" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define smp_mb__before_atomic_dec()     smp_mb()
+#define smp_mb__after_atomic_dec()      smp_mb()
+#define smp_mb__before_atomic_inc()     smp_mb()
+#define smp_mb__after_atomic_inc()      smp_mb()
+
+#ifdef __powerpc64__
+
+typedef struct { long counter; } atomic64_t;
+
+#define ATOMIC64_INIT(i)        { (i) }
+
+static __inline__ long atomic64_read(const atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
+
+        return t;
+}
+
+static __inline__ void atomic64_set(atomic64_t *v, long i)
+{
+        __asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
+}
+
+static __inline__ void atomic64_add(long a, atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:     ldarx   %0,0,%3         # atomic64_add\n\
+        add     %0,%2,%0\n\
+        stdcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ long atomic64_add_return(long a, atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%2         # atomic64_add_return\n\
+        add     %0,%1,%0\n\
+        stdcx.  %0,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (a), "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define atomic64_add_negative(a, v)     (atomic64_add_return((a), (v)) < 0)
+
+static __inline__ void atomic64_sub(long a, atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:     ldarx   %0,0,%3         # atomic64_sub\n\
+        subf    %0,%2,%0\n\
+        stdcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%2         # atomic64_sub_return\n\
+        subf    %0,%1,%0\n\
+        stdcx.  %0,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (a), "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+static __inline__ void atomic64_inc(atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:     ldarx   %0,0,%2         # atomic64_inc\n\
+        addic   %0,%0,1\n\
+        stdcx.  %0,0,%2 \n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ long atomic64_inc_return(atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%1         # atomic64_inc_return\n\
+        addic   %0,%0,1\n\
+        stdcx.  %0,0,%1 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+/*
+ * atomic64_inc_and_test - increment and test
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
+
+static __inline__ void atomic64_dec(atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:     ldarx   %0,0,%2         # atomic64_dec\n\
+        addic   %0,%0,-1\n\
+        stdcx.  %0,0,%2\n\
+        bne-    1b"
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
+        : "cc");
+}
+
+static __inline__ long atomic64_dec_return(atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%1         # atomic64_dec_return\n\
+        addic   %0,%0,-1\n\
+        stdcx.  %0,0,%1\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define atomic64_sub_and_test(a, v)     (atomic64_sub_return((a), (v)) == 0)
+#define atomic64_dec_and_test(v)        (atomic64_dec_return((v)) == 0)
+
+/*
+ * Atomically test *v and decrement if it is greater than 0.
+ * The function returns the old value of *v minus 1.
+ */
+static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
+{
+        long t;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%1         # atomic64_dec_if_positive\n\
+        addic.  %0,%0,-1\n\
+        blt-    2f\n\
+        stdcx.  %0,0,%1\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"     : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+/**
+ * atomic64_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic64_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long t;
+
+        __asm__ __volatile__ (
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%1         # atomic_add_unless\n\
+        cmpd    0,%0,%3 \n\
+        beq-    2f \n\
+        add     %0,%2,%0 \n"
+"       stdcx.  %0,0,%1 \n\
+        bne-    1b \n"
+        ISYNC_ON_SMP
+"       subf    %0,%2,%0 \n\
+2:"
+        : "=&r" (t)
+        : "r" (&v->counter), "r" (a), "r" (u)
+        : "cc", "memory");
+
+        return t != u;
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+#endif /* __powerpc64__ */
+
+#include <asm-generic/atomic.h>
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/arch/powerpc/include/asm/auxvec.h b/arch/powerpc/include/asm/auxvec.h
new file mode 100644
index 000000000000..19a099b62cd6
--- /dev/null
+++ b/arch/powerpc/include/asm/auxvec.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_POWERPC_AUXVEC_H
+#define _ASM_POWERPC_AUXVEC_H
+
+/*
+ * We need to put in some extra aux table entries to tell glibc what
+ * the cache block size is, so it can use the dcbz instruction safely.
+ */
+#define AT_DCACHEBSIZE          19
+#define AT_ICACHEBSIZE          20
+#define AT_UCACHEBSIZE          21
+/* A special ignored type value for PPC, for glibc compatibility.  */
+#define AT_IGNOREPPC            22
+
+/* The vDSO location. We have to use the same value as x86 for glibc's
+ * sake :-)
+ */
+#define AT_SYSINFO_EHDR         33
+
+#endif
diff --git a/arch/powerpc/include/asm/backlight.h b/arch/powerpc/include/asm/backlight.h
new file mode 100644
index 000000000000..8cf5c37c3817
--- /dev/null
+++ b/arch/powerpc/include/asm/backlight.h
@@ -0,0 +1,41 @@
+/*
+ * Routines for handling backlight control on PowerBooks
+ *
+ * For now, implementation resides in
+ * arch/powerpc/platforms/powermac/backlight.c
+ *
+ */
+#ifndef __ASM_POWERPC_BACKLIGHT_H
+#define __ASM_POWERPC_BACKLIGHT_H
+#ifdef __KERNEL__
+
+#include <linux/fb.h>
+#include <linux/mutex.h>
+
+/* For locking instructions, see the implementation file */
+extern struct backlight_device *pmac_backlight;
+extern struct mutex pmac_backlight_mutex;
+
+extern int pmac_backlight_curve_lookup(struct fb_info *info, int value);
+
+extern int pmac_has_backlight_type(const char *type);
+
+extern void pmac_backlight_key(int direction);
+static inline void pmac_backlight_key_up(void)
+{
+        pmac_backlight_key(0);
+}
+static inline void pmac_backlight_key_down(void)
+{
+        pmac_backlight_key(1);
+}
+
+extern void pmac_backlight_set_legacy_brightness_pmu(int brightness);
+extern int pmac_backlight_set_legacy_brightness(int brightness);
+extern int pmac_backlight_get_legacy_brightness(void);
+
+extern void pmac_backlight_enable(void);
+extern void pmac_backlight_disable(void);
+
+#endif /* __KERNEL__ */
+#endif
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
new file mode 100644
index 000000000000..897eade3afbe
--- /dev/null
+++ b/arch/powerpc/include/asm/bitops.h
@@ -0,0 +1,410 @@
+/*
+ * PowerPC atomic bit operations.
+ *
+ * Merged version by David Gibson <david@gibson.dropbear.id.au>.
+ * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
+ * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard.  They
+ * originally took it from the ppc32 code.
+ *
+ * Within a word, bits are numbered LSB first.  Lot's of places make
+ * this assumption by directly testing bits with (val & (1<<nr)).
+ * This can cause confusion for large (> 1 word) bitmaps on a
+ * big-endian system because, unlike little endian, the number of each
+ * bit depends on the word size.
+ *
+ * The bitop functions are defined to work on unsigned longs, so for a
+ * ppc64 system the bits end up numbered:
+ *   |63..............0|127............64|191...........128|255...........196|
+ * and on ppc32:
+ *   |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
+ *
+ * There are a few little-endian macros used mostly for filesystem
+ * bitmaps, these work on similar bit arrays layouts, but
+ * byte-oriented:
+ *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
+ *
+ * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
+ * number field needs to be reversed compared to the big-endian bit
+ * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_POWERPC_BITOPS_H
+#define _ASM_POWERPC_BITOPS_H
+
+#ifdef __KERNEL__
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+#include <asm/asm-compat.h>
+#include <asm/synch.h>
+
+/*
+ * clear_bit doesn't imply a memory barrier
+ */
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
+
+#define BITOP_MASK(nr)          (1UL << ((nr) % BITS_PER_LONG))
+#define BITOP_WORD(nr)          ((nr) / BITS_PER_LONG)
+#define BITOP_LE_SWIZZLE        ((BITS_PER_LONG-1) & ~0x7)
+
+static __inline__ void set_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX "%0,0,%3      # set_bit\n"
+        "or     %0,%0,%2\n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%0,0,%3\n"
+        "bne-   1b"
+        : "=&r" (old), "+m" (*p)
+        : "r" (mask), "r" (p)
+        : "cc" );
+}
+
+static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX "%0,0,%3      # clear_bit\n"
+        "andc   %0,%0,%2\n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%0,0,%3\n"
+        "bne-   1b"
+        : "=&r" (old), "+m" (*p)
+        : "r" (mask), "r" (p)
+        : "cc" );
+}
+
+static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:"    PPC_LLARX "%0,0,%3      # clear_bit_unlock\n"
+        "andc   %0,%0,%2\n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%0,0,%3\n"
+        "bne-   1b"
+        : "=&r" (old), "+m" (*p)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+}
+
+static __inline__ void change_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX "%0,0,%3      # change_bit\n"
+        "xor    %0,%0,%2\n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%0,0,%3\n"
+        "bne-   1b"
+        : "=&r" (old), "+m" (*p)
+        : "r" (mask), "r" (p)
+        : "cc" );
+}
+
+static __inline__ int test_and_set_bit(unsigned long nr,
+                                       volatile unsigned long *addr)
+{
+        unsigned long old, t;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit\n"
+        "or     %1,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%1,0,%3 \n"
+        "bne-   1b"
+        ISYNC_ON_SMP
+        : "=&r" (old), "=&r" (t)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_and_set_bit_lock(unsigned long nr,
+                                       volatile unsigned long *addr)
+{
+        unsigned long old, t;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit_lock\n"
+        "or     %1,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%1,0,%3 \n"
+        "bne-   1b"
+        ISYNC_ON_SMP
+        : "=&r" (old), "=&r" (t)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_and_clear_bit(unsigned long nr,
+                                         volatile unsigned long *addr)
+{
+        unsigned long old, t;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:"    PPC_LLARX "%0,0,%3              # test_and_clear_bit\n"
+        "andc   %1,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%1,0,%3 \n"
+        "bne-   1b"
+        ISYNC_ON_SMP
+        : "=&r" (old), "=&r" (t)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_and_change_bit(unsigned long nr,
+                                          volatile unsigned long *addr)
+{
+        unsigned long old, t;
+        unsigned long mask = BITOP_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:"    PPC_LLARX "%0,0,%3              # test_and_change_bit\n"
+        "xor    %1,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+        PPC_STLCX "%1,0,%3 \n"
+        "bne-   1b"
+        ISYNC_ON_SMP
+        : "=&r" (old), "=&r" (t)
+        : "r" (mask), "r" (p)
+        : "cc", "memory");
+
+        return (old & mask) != 0;
+}
+
+static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
+{
+        unsigned long old;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX "%0,0,%3         # set_bits\n"
+        "or     %0,%0,%2\n"
+        PPC_STLCX "%0,0,%3\n"
+        "bne-   1b"
+        : "=&r" (old), "+m" (*addr)
+        : "r" (mask), "r" (addr)
+        : "cc");
+}
+
+#include <asm-generic/bitops/non-atomic.h>
+
+static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
+{
+        __asm__ __volatile__(LWSYNC_ON_SMP "" ::: "memory");
+        __clear_bit(nr, addr);
+}
+
+/*
+ * Return the zero-based bit position (LE, not IBM bit numbering) of
+ * the most significant 1-bit in a double word.
+ */
+static __inline__ __attribute__((const))
+int __ilog2(unsigned long x)
+{
+        int lz;
+
+        asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
+        return BITS_PER_LONG - 1 - lz;
+}
+
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+        int bit;
+        asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
+        return 31 - bit;
+}
+
+#ifdef __powerpc64__
+static inline __attribute__((const))
+int __ilog2_u64(u64 n)
+{
+        int bit;
+        asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
+        return 63 - bit;
+}
+#endif
+
+/*
+ * Determines the bit position of the least significant 0 bit in the
+ * specified double word. The returned bit position will be
+ * zero-based, starting from the right side (63/31 - 0).
+ */
+static __inline__ unsigned long ffz(unsigned long x)
+{
+        /* no zero exists anywhere in the 8 byte area. */
+        if ((x = ~x) == 0)
+                return BITS_PER_LONG;
+
+        /*
+         * Calculate the bit position of the least signficant '1' bit in x
+         * (since x has been changed this will actually be the least signficant
+         * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
+         * is the least significant * (RIGHT-most) 1-bit of the value in x.
+         */
+        return __ilog2(x & -x);
+}
+
+static __inline__ int __ffs(unsigned long x)
+{
+        return __ilog2(x & -x);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int ffs(int x)
+{
+        unsigned long i = (unsigned long)x;
+        return __ilog2(i & -i) + 1;
+}
+
+/*
+ * fls: find last (most-significant) bit set.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static __inline__ int fls(unsigned int x)
+{
+        int lz;
+
+        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+        return 32 - lz;
+}
+
+static __inline__ unsigned long __fls(unsigned long x)
+{
+        return __ilog2(x);
+}
+
+/*
+ * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
+ * instruction; for 32-bit we use the generic version, which does two
+ * 32-bit fls calls.
+ */
+#ifdef __powerpc64__
+static __inline__ int fls64(__u64 x)
+{
+        int lz;
+
+        asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
+        return 64 - lz;
+}
+#else
+#include <asm-generic/bitops/fls64.h>
+#endif /* __powerpc64__ */
+
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/find.h>
+
+/* Little-endian versions */
+
+static __inline__ int test_le_bit(unsigned long nr,
+                                  __const__ unsigned long *addr)
+{
+        __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
+        return (tmp[nr >> 3] >> (nr & 7)) & 1;
+}
+
+#define __set_le_bit(nr, addr) \
+        __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define __clear_le_bit(nr, addr) \
+        __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+
+#define test_and_set_le_bit(nr, addr) \
+        test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define test_and_clear_le_bit(nr, addr) \
+        test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+
+#define __test_and_set_le_bit(nr, addr) \
+        __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+#define __test_and_clear_le_bit(nr, addr) \
+        __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
+
+#define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0)
+unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
+                                    unsigned long size, unsigned long offset);
+
+unsigned long generic_find_next_le_bit(const unsigned long *addr,
+                                    unsigned long size, unsigned long offset);
+/* Bitmap functions for the ext2 filesystem */
+
+#define ext2_set_bit(nr,addr) \
+        __test_and_set_le_bit((nr), (unsigned long*)addr)
+#define ext2_clear_bit(nr, addr) \
+        __test_and_clear_le_bit((nr), (unsigned long*)addr)
+
+#define ext2_set_bit_atomic(lock, nr, addr) \
+        test_and_set_le_bit((nr), (unsigned long*)addr)
+#define ext2_clear_bit_atomic(lock, nr, addr) \
+        test_and_clear_le_bit((nr), (unsigned long*)addr)
+
+#define ext2_test_bit(nr, addr)      test_le_bit((nr),(unsigned long*)addr)
+
+#define ext2_find_first_zero_bit(addr, size) \
+        find_first_zero_le_bit((unsigned long*)addr, size)
+#define ext2_find_next_zero_bit(addr, size, off) \
+        generic_find_next_zero_le_bit((unsigned long*)addr, size, off)
+
+#define ext2_find_next_bit(addr, size, off) \
+        generic_find_next_le_bit((unsigned long *)addr, size, off)
+/* Bitmap functions for the minix filesystem.  */
+
+#define minix_test_and_set_bit(nr,addr) \
+        __test_and_set_le_bit(nr, (unsigned long *)addr)
+#define minix_set_bit(nr,addr) \
+        __set_le_bit(nr, (unsigned long *)addr)
+#define minix_test_and_clear_bit(nr,addr) \
+        __test_and_clear_le_bit(nr, (unsigned long *)addr)
+#define minix_test_bit(nr,addr) \
+        test_le_bit(nr, (unsigned long *)addr)
+
+#define minix_find_first_zero_bit(addr,size) \
+        find_first_zero_le_bit((unsigned long *)addr, size)
+
+#include <asm-generic/bitops/sched.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_BITOPS_H */
diff --git a/arch/powerpc/include/asm/bootx.h b/arch/powerpc/include/asm/bootx.h
new file mode 100644
index 000000000000..57b82e3f89ce
--- /dev/null
+++ b/arch/powerpc/include/asm/bootx.h
@@ -0,0 +1,171 @@
+/*
+ * This file describes the structure passed from the BootX application
+ * (for MacOS) when it is used to boot Linux.
+ *
+ * Written by Benjamin Herrenschmidt.
+ */
+
+
+#ifndef __ASM_BOOTX_H__
+#define __ASM_BOOTX_H__
+
+#include <asm/types.h>
+
+#ifdef macintosh
+#include <Types.h>
+#include "linux_type_defs.h"
+#endif
+
+#ifdef macintosh
+/* All this requires PowerPC alignment */
+#pragma options align=power
+#endif
+
+/* On kernel entry:
+ *
+ * r3 = 0x426f6f58    ('BooX')
+ * r4 = pointer to boot_infos
+ * r5 = NULL
+ *
+ * Data and instruction translation disabled, interrupts
+ * disabled, kernel loaded at physical 0x00000000 on PCI
+ * machines (will be different on NuBus).
+ */
+
+#define BOOT_INFO_VERSION               5
+#define BOOT_INFO_COMPATIBLE_VERSION    1
+
+/* Bit in the architecture flag mask. More to be defined in
+   future versions. Note that either BOOT_ARCH_PCI or
+   BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
+   set additionally when BOOT_ARCH_NUBUS is set.
+ */
+#define BOOT_ARCH_PCI                   0x00000001UL
+#define BOOT_ARCH_NUBUS                 0x00000002UL
+#define BOOT_ARCH_NUBUS_PDM             0x00000010UL
+#define BOOT_ARCH_NUBUS_PERFORMA        0x00000020UL
+#define BOOT_ARCH_NUBUS_POWERBOOK       0x00000040UL
+
+/*  Maximum number of ranges in phys memory map */
+#define MAX_MEM_MAP_SIZE                                26
+
+/* This is the format of an element in the physical memory map. Note that
+   the map is optional and current BootX will only build it for pre-PCI
+   machines */
+typedef struct boot_info_map_entry
+{
+    __u32       physAddr;                /* Physical starting address */
+    __u32       size;                    /* Size in bytes */
+} boot_info_map_entry_t;
+
+
+/* Here are the boot informations that are passed to the bootstrap
+ * Note that the kernel arguments and the device tree are appended
+ * at the end of this structure. */
+typedef struct boot_infos
+{
+    /* Version of this structure */
+    __u32       version;
+    /* backward compatible down to version: */
+    __u32       compatible_version;
+
+    /* NEW (vers. 2) this holds the current _logical_ base addr of
+       the frame buffer (for use by early boot message) */
+    __u8*       logicalDisplayBase;
+
+    /* NEW (vers. 4) Apple's machine identification */
+    __u32       machineID;
+
+    /* NEW (vers. 4) Detected hw architecture */
+    __u32       architecture;
+
+    /* The device tree (internal addresses relative to the beginning of the tree,
+     * device tree offset relative to the beginning of this structure).
+     * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
+     * field is 0.
+     */
+    __u32       deviceTreeOffset;        /* Device tree offset */
+    __u32       deviceTreeSize;          /* Size of the device tree */
+
+    /* Some infos about the current MacOS display */
+    __u32       dispDeviceRect[4];       /* left,top,right,bottom */
+    __u32       dispDeviceDepth;         /* (8, 16 or 32) */
+    __u8*       dispDeviceBase;          /* base address (physical) */
+    __u32       dispDeviceRowBytes;      /* rowbytes (in bytes) */
+    __u32       dispDeviceColorsOffset;  /* Colormap (8 bits only) or 0 (*) */
+    /* Optional offset in the registry to the current
+     * MacOS display. (Can be 0 when not detected) */
+     __u32      dispDeviceRegEntryOffset;
+
+    /* Optional pointer to boot ramdisk (offset from this structure) */
+    __u32       ramDisk;
+    __u32       ramDiskSize;             /* size of ramdisk image */
+
+    /* Kernel command line arguments (offset from this structure) */
+    __u32       kernelParamsOffset;
+
+    /* ALL BELOW NEW (vers. 4) */
+
+    /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
+       (non-PCI) only. On PCI, memory is contiguous and it's size is in the
+       device-tree. */
+    boot_info_map_entry_t
+                physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
+    __u32       physMemoryMapSize;               /* How many entries in map */
+
+
+    /* The framebuffer size (optional, currently 0) */
+    __u32       frameBufferSize;         /* Represents a max size, can be 0. */
+
+    /* NEW (vers. 5) */
+
+    /* Total params size (args + colormap + device tree + ramdisk) */
+    __u32       totalParamsSize;
+
+} boot_infos_t;
+
+#ifdef __KERNEL__
+/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index
+ * is represented by 3 short words containing a 16 bits (unsigned) color
+ * component. Later versions may contain the gamma table for direct-color
+ * devices here.
+ */
+#define BOOTX_COLORTABLE_SIZE    (256UL*3UL*2UL)
+
+/* BootX passes the device-tree using a format that comes from earlier
+ * ppc32 kernels. This used to match what is in prom.h, but not anymore
+ * so we now define it here
+ */
+struct bootx_dt_prop {
+        u32     name;
+        int     length;
+        u32     value;
+        u32     next;
+};
+
+struct bootx_dt_node {
+        u32     unused0;
+        u32     unused1;
+        u32     phandle;        /* not really available */
+        u32     unused2;
+        u32     unused3;
+        u32     unused4;
+        u32     unused5;
+        u32     full_name;
+        u32     properties;
+        u32     parent;
+        u32     child;
+        u32     sibling;
+        u32     next;
+        u32     allnext;
+};
+
+extern void bootx_init(unsigned long r4, unsigned long phys);
+
+#endif /* __KERNEL__ */
+
+#ifdef macintosh
+#pragma options align=reset
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/btext.h b/arch/powerpc/include/asm/btext.h
new file mode 100644
index 000000000000..906f46e31006
--- /dev/null
+++ b/arch/powerpc/include/asm/btext.h
@@ -0,0 +1,28 @@
+/*
+ * Definitions for using the procedures in btext.c.
+ *
+ * Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ */
+#ifndef __PPC_BTEXT_H
+#define __PPC_BTEXT_H
+#ifdef __KERNEL__
+
+extern int btext_find_display(int allow_nonstdout);
+extern void btext_update_display(unsigned long phys, int width, int height,
+                                 int depth, int pitch);
+extern void btext_setup_display(int width, int height, int depth, int pitch,
+                                unsigned long address);
+extern void btext_prepare_BAT(void);
+extern void btext_unmap(void);
+
+extern void btext_drawchar(char c);
+extern void btext_drawstring(const char *str);
+extern void btext_drawhex(unsigned long v);
+extern void btext_drawtext(const char *c, unsigned int len);
+
+extern void btext_clearscreen(void);
+extern void btext_flushscreen(void);
+extern void btext_flushline(void);
+
+#endif /* __KERNEL__ */
+#endif /* __PPC_BTEXT_H */
diff --git a/arch/powerpc/include/asm/bug.h b/arch/powerpc/include/asm/bug.h
new file mode 100644
index 000000000000..e55d1f66b86f
--- /dev/null
+++ b/arch/powerpc/include/asm/bug.h
@@ -0,0 +1,121 @@
+#ifndef _ASM_POWERPC_BUG_H
+#define _ASM_POWERPC_BUG_H
+#ifdef __KERNEL__
+
+#include <asm/asm-compat.h>
+/*
+ * Define an illegal instr to trap on the bug.
+ * We don't use 0 because that marks the end of a function
+ * in the ELF ABI.  That's "Boo Boo" in case you wonder...
+ */
+#define BUG_OPCODE .long 0x00b00b00  /* For asm */
+#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
+
+#ifdef CONFIG_BUG
+
+#ifdef __ASSEMBLY__
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+.macro EMIT_BUG_ENTRY addr,file,line,flags
+         .section __bug_table,"a"
+5001:    PPC_LONG \addr, 5002f
+         .short \line, \flags
+         .org 5001b+BUG_ENTRY_SIZE
+         .previous
+         .section .rodata,"a"
+5002:    .asciz "\file"
+         .previous
+.endm
+#else
+ .macro EMIT_BUG_ENTRY addr,file,line,flags
+         .section __bug_table,"a"
+5001:    PPC_LONG \addr
+         .short \flags
+         .org 5001b+BUG_ENTRY_SIZE
+         .previous
+.endm
+#endif /* verbose */
+
+#else /* !__ASSEMBLY__ */
+/* _EMIT_BUG_ENTRY expects args %0,%1,%2,%3 to be FILE, LINE, flags and
+   sizeof(struct bug_entry), respectively */
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#define _EMIT_BUG_ENTRY                         \
+        ".section __bug_table,\"a\"\n"          \
+        "2:\t" PPC_LONG "1b, %0\n"              \
+        "\t.short %1, %2\n"                     \
+        ".org 2b+%3\n"                          \
+        ".previous\n"
+#else
+#define _EMIT_BUG_ENTRY                         \
+        ".section __bug_table,\"a\"\n"          \
+        "2:\t" PPC_LONG "1b\n"                  \
+        "\t.short %2\n"                         \
+        ".org 2b+%3\n"                          \
+        ".previous\n"
+#endif
+
+/*
+ * BUG_ON() and WARN_ON() do their best to cooperate with compile-time
+ * optimisations. However depending on the complexity of the condition
+ * some compiler versions may not produce optimal results.
+ */
+
+#define BUG() do {                                              \
+        __asm__ __volatile__(                                   \
+                "1:     twi 31,0,0\n"                           \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__),             \
+                    "i" (0), "i"  (sizeof(struct bug_entry)));  \
+        for(;;) ;                                               \
+} while (0)
+
+#define BUG_ON(x) do {                                          \
+        if (__builtin_constant_p(x)) {                          \
+                if (x)                                          \
+                        BUG();                                  \
+        } else {                                                \
+                __asm__ __volatile__(                           \
+                "1:     "PPC_TLNEI"     %4,0\n"                 \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__), "i" (0),    \
+                  "i" (sizeof(struct bug_entry)),               \
+                  "r" ((__force long)(x)));                     \
+        }                                                       \
+} while (0)
+
+#define __WARN() do {                                           \
+        __asm__ __volatile__(                                   \
+                "1:     twi 31,0,0\n"                           \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__),             \
+                  "i" (BUGFLAG_WARNING),                        \
+                  "i" (sizeof(struct bug_entry)));              \
+} while (0)
+
+#define WARN_ON(x) ({                                           \
+        int __ret_warn_on = !!(x);                              \
+        if (__builtin_constant_p(__ret_warn_on)) {              \
+                if (__ret_warn_on)                              \
+                        __WARN();                               \
+        } else {                                                \
+                __asm__ __volatile__(                           \
+                "1:     "PPC_TLNEI"     %4,0\n"                 \
+                _EMIT_BUG_ENTRY                                 \
+                : : "i" (__FILE__), "i" (__LINE__),             \
+                  "i" (BUGFLAG_WARNING),                        \
+                  "i" (sizeof(struct bug_entry)),               \
+                  "r" (__ret_warn_on));                         \
+        }                                                       \
+        unlikely(__ret_warn_on);                                \
+})
+
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_BUG_ON
+#define HAVE_ARCH_WARN_ON
+#endif /* __ASSEMBLY __ */
+#endif /* CONFIG_BUG */
+
+#include <asm-generic/bug.h>
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_BUG_H */
diff --git a/arch/powerpc/include/asm/bugs.h b/arch/powerpc/include/asm/bugs.h
new file mode 100644
index 000000000000..42fdb73e3068
--- /dev/null
+++ b/arch/powerpc/include/asm/bugs.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_POWERPC_BUGS_H
+#define _ASM_POWERPC_BUGS_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * This file is included by 'init/main.c' to check for
+ * architecture-dependent bugs.
+ */
+
+static inline void check_bugs(void) { }
+
+#endif  /* _ASM_POWERPC_BUGS_H */
diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h
new file mode 100644
index 000000000000..b37752214a16
--- /dev/null
+++ b/arch/powerpc/include/asm/byteorder.h
@@ -0,0 +1,89 @@
+#ifndef _ASM_POWERPC_BYTEORDER_H
+#define _ASM_POWERPC_BYTEORDER_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/types.h>
+#include <linux/compiler.h>
+
+#ifdef __GNUC__
+#ifdef __KERNEL__
+
+static __inline__ __u16 ld_le16(const volatile __u16 *addr)
+{
+        __u16 val;
+
+        __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+        return val;
+}
+
+static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
+{
+        __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+static __inline__ __u32 ld_le32(const volatile __u32 *addr)
+{
+        __u32 val;
+
+        __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+        return val;
+}
+
+static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
+{
+        __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
+{
+        __u16 result;
+
+        __asm__("rlwimi %0,%1,8,16,23"
+            : "=r" (result)
+            : "r" (value), "0" (value >> 8));
+        return result;
+}
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
+{
+        __u32 result;
+
+        __asm__("rlwimi %0,%1,24,16,23\n\t"
+            "rlwimi %0,%1,8,8,15\n\t"
+            "rlwimi %0,%1,24,0,7"
+            : "=r" (result)
+            : "r" (value), "0" (value >> 24));
+        return result;
+}
+
+#define __arch__swab16(x) ___arch__swab16(x)
+#define __arch__swab32(x) ___arch__swab32(x)
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+
+#endif /* __KERNEL__ */
+
+#ifndef __STRICT_ANSI__
+#define __BYTEORDER_HAS_U64__
+#ifndef __powerpc64__
+#define __SWAB_64_THRU_32__
+#endif /* __powerpc64__ */
+#endif /* __STRICT_ANSI__ */
+
+#endif /* __GNUC__ */
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _ASM_POWERPC_BYTEORDER_H */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
new file mode 100644
index 000000000000..81de6eb3455d
--- /dev/null
+++ b/arch/powerpc/include/asm/cache.h
@@ -0,0 +1,45 @@
+#ifndef _ASM_POWERPC_CACHE_H
+#define _ASM_POWERPC_CACHE_H
+
+#ifdef __KERNEL__
+
+
+/* bytes per L1 cache line */
+#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
+#define L1_CACHE_SHIFT          4
+#define MAX_COPY_PREFETCH       1
+#elif defined(CONFIG_PPC_E500MC)
+#define L1_CACHE_SHIFT          6
+#define MAX_COPY_PREFETCH       4
+#elif defined(CONFIG_PPC32)
+#define L1_CACHE_SHIFT          5
+#define MAX_COPY_PREFETCH       4
+#else /* CONFIG_PPC64 */
+#define L1_CACHE_SHIFT          7
+#endif
+
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#define SMP_CACHE_BYTES         L1_CACHE_BYTES
+
+#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
+struct ppc64_caches {
+        u32     dsize;                  /* L1 d-cache size */
+        u32     dline_size;             /* L1 d-cache line size */
+        u32     log_dline_size;
+        u32     dlines_per_page;
+        u32     isize;                  /* L1 i-cache size */
+        u32     iline_size;             /* L1 i-cache line size */
+        u32     log_iline_size;
+        u32     ilines_per_page;
+};
+
+extern struct ppc64_caches ppc64_caches;
+#endif /* __powerpc64__ && ! __ASSEMBLY__ */
+
+#if !defined(__ASSEMBLY__)
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
new file mode 100644
index 000000000000..ba667a383b8c
--- /dev/null
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -0,0 +1,75 @@
+/*
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_CACHEFLUSH_H
+#define _ASM_POWERPC_CACHEFLUSH_H
+
+#ifdef __KERNEL__
+
+#include <linux/mm.h>
+#include <asm/cputable.h>
+
+/*
+ * No cache flushing is required when address mappings are changed,
+ * because the caches on PowerPCs are physically addressed.
+ */
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_icache_page(vma, page)            do { } while (0)
+#define flush_cache_vmap(start, end)            do { } while (0)
+#define flush_cache_vunmap(start, end)          do { } while (0)
+
+extern void flush_dcache_page(struct page *page);
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+extern void __flush_icache_range(unsigned long, unsigned long);
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
+{
+        if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
+                __flush_icache_range(start, stop);
+}
+
+extern void flush_icache_user_range(struct vm_area_struct *vma,
+                                    struct page *page, unsigned long addr,
+                                    int len);
+extern void __flush_dcache_icache(void *page_va);
+extern void flush_dcache_icache_page(struct page *page);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
+extern void __flush_dcache_icache_phys(unsigned long physaddr);
+#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
+
+extern void flush_dcache_range(unsigned long start, unsigned long stop);
+#ifdef CONFIG_PPC32
+extern void clean_dcache_range(unsigned long start, unsigned long stop);
+extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+#endif /* CONFIG_PPC32 */
+#ifdef CONFIG_PPC64
+extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
+#endif
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+        do { \
+                memcpy(dst, src, len); \
+                flush_icache_user_range(vma, page, vaddr, len); \
+        } while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+
+
+
+#ifdef CONFIG_DEBUG_PAGEALLOC
+/* internal debugging function */
+void kernel_map_pages(struct page *page, int numpages, int enable);
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/arch/powerpc/include/asm/cell-pmu.h b/arch/powerpc/include/asm/cell-pmu.h
new file mode 100644
index 000000000000..8066eede3a0c
--- /dev/null
+++ b/arch/powerpc/include/asm/cell-pmu.h
@@ -0,0 +1,105 @@
+/*
+ * Cell Broadband Engine Performance Monitor
+ *
+ * (C) Copyright IBM Corporation 2006
+ *
+ * Author:
+ *   David Erb (djerb@us.ibm.com)
+ *   Kevin Corry (kevcorry@us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_CELL_PMU_H__
+#define __ASM_CELL_PMU_H__
+
+/* The Cell PMU has four hardware performance counters, which can be
+ * configured as four 32-bit counters or eight 16-bit counters.
+ */
+#define NR_PHYS_CTRS 4
+#define NR_CTRS      (NR_PHYS_CTRS * 2)
+
+/* Macros for the pm_control register. */
+#define CBE_PM_16BIT_CTR(ctr)              (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
+#define CBE_PM_ENABLE_PERF_MON             0x80000000
+#define CBE_PM_STOP_AT_MAX                 0x40000000
+#define CBE_PM_TRACE_MODE_GET(pm_control)  (((pm_control) >> 28) & 0x3)
+#define CBE_PM_TRACE_MODE_SET(mode)        (((mode)  & 0x3) << 28)
+#define CBE_PM_COUNT_MODE_SET(count)       (((count) & 0x3) << 18)
+#define CBE_PM_FREEZE_ALL_CTRS             0x00100000
+#define CBE_PM_ENABLE_EXT_TRACE            0x00008000
+
+/* Macros for the trace_address register. */
+#define CBE_PM_TRACE_BUF_FULL              0x00000800
+#define CBE_PM_TRACE_BUF_EMPTY             0x00000400
+#define CBE_PM_TRACE_BUF_DATA_COUNT(ta)    ((ta) & 0x3ff)
+#define CBE_PM_TRACE_BUF_MAX_COUNT         0x400
+
+/* Macros for the pm07_control registers. */
+#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
+#define CBE_PM_CTR_INPUT_CONTROL           0x02000000
+#define CBE_PM_CTR_POLARITY                0x01000000
+#define CBE_PM_CTR_COUNT_CYCLES            0x00800000
+#define CBE_PM_CTR_ENABLE                  0x00400000
+#define PM07_CTR_INPUT_MUX(x)              (((x) & 0x3F) << 26)
+#define PM07_CTR_INPUT_CONTROL(x)          (((x) & 1) << 25)
+#define PM07_CTR_POLARITY(x)               (((x) & 1) << 24)
+#define PM07_CTR_COUNT_CYCLES(x)           (((x) & 1) << 23)
+#define PM07_CTR_ENABLE(x)                 (((x) & 1) << 22)
+
+/* Macros for the pm_status register. */
+#define CBE_PM_CTR_OVERFLOW_INTR(ctr)      (1 << (31 - ((ctr) & 7)))
+
+enum pm_reg_name {
+        group_control,
+        debug_bus_control,
+        trace_address,
+        ext_tr_timer,
+        pm_status,
+        pm_control,
+        pm_interval,
+        pm_start_stop,
+};
+
+/* Routines for reading/writing the PMU registers. */
+extern u32  cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
+extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
+extern u32  cbe_read_ctr(u32 cpu, u32 ctr);
+extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
+
+extern u32  cbe_read_pm07_control(u32 cpu, u32 ctr);
+extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
+extern u32  cbe_read_pm(u32 cpu, enum pm_reg_name reg);
+extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
+
+extern u32  cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
+extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
+
+extern void cbe_enable_pm(u32 cpu);
+extern void cbe_disable_pm(u32 cpu);
+
+extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
+
+extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
+extern void cbe_disable_pm_interrupts(u32 cpu);
+extern u32  cbe_get_and_clear_pm_interrupts(u32 cpu);
+extern void cbe_sync_irq(int node);
+
+#define CBE_COUNT_SUPERVISOR_MODE       0
+#define CBE_COUNT_HYPERVISOR_MODE       1
+#define CBE_COUNT_PROBLEM_MODE          2
+#define CBE_COUNT_ALL_MODES             3
+
+#endif /* __ASM_CELL_PMU_H__ */
diff --git a/arch/powerpc/include/asm/cell-regs.h b/arch/powerpc/include/asm/cell-regs.h
new file mode 100644
index 000000000000..fd6fd00434ef
--- /dev/null
+++ b/arch/powerpc/include/asm/cell-regs.h
@@ -0,0 +1,315 @@
+/*
+ * cbe_regs.h
+ *
+ * This file is intended to hold the various register definitions for CBE
+ * on-chip system devices (memory controller, IO controller, etc...)
+ *
+ * (C) Copyright IBM Corporation 2001,2006
+ *
+ * Authors: Maximino Aguilar (maguilar@us.ibm.com)
+ *          David J. Erb (djerb@us.ibm.com)
+ *
+ * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
+ */
+
+#ifndef CBE_REGS_H
+#define CBE_REGS_H
+
+#include <asm/cell-pmu.h>
+
+/*
+ *
+ * Some HID register definitions
+ *
+ */
+
+/* CBE specific HID0 bits */
+#define HID0_CBE_THERM_WAKEUP   0x0000020000000000ul
+#define HID0_CBE_SYSERR_WAKEUP  0x0000008000000000ul
+#define HID0_CBE_THERM_INT_EN   0x0000000400000000ul
+#define HID0_CBE_SYSERR_INT_EN  0x0000000200000000ul
+
+#define MAX_CBE         2
+
+/*
+ *
+ * Pervasive unit register definitions
+ *
+ */
+
+union spe_reg {
+        u64 val;
+        u8 spe[8];
+};
+
+union ppe_spe_reg {
+        u64 val;
+        struct {
+                u32 ppe;
+                u32 spe;
+        };
+};
+
+
+struct cbe_pmd_regs {
+        /* Debug Bus Control */
+        u64     pad_0x0000;                                     /* 0x0000 */
+
+        u64     group_control;                                  /* 0x0008 */
+
+        u8      pad_0x0010_0x00a8 [0x00a8 - 0x0010];            /* 0x0010 */
+
+        u64     debug_bus_control;                              /* 0x00a8 */
+
+        u8      pad_0x00b0_0x0100 [0x0100 - 0x00b0];            /* 0x00b0 */
+
+        u64     trace_aux_data;                                 /* 0x0100 */
+        u64     trace_buffer_0_63;                              /* 0x0108 */
+        u64     trace_buffer_64_127;                            /* 0x0110 */
+        u64     trace_address;                                  /* 0x0118 */
+        u64     ext_tr_timer;                                   /* 0x0120 */
+
+        u8      pad_0x0128_0x0400 [0x0400 - 0x0128];            /* 0x0128 */
+
+        /* Performance Monitor */
+        u64     pm_status;                                      /* 0x0400 */
+        u64     pm_control;                                     /* 0x0408 */
+        u64     pm_interval;                                    /* 0x0410 */
+        u64     pm_ctr[4];                                      /* 0x0418 */
+        u64     pm_start_stop;                                  /* 0x0438 */
+        u64     pm07_control[8];                                /* 0x0440 */
+
+        u8      pad_0x0480_0x0800 [0x0800 - 0x0480];            /* 0x0480 */
+
+        /* Thermal Sensor Registers */
+        union   spe_reg ts_ctsr1;                               /* 0x0800 */
+        u64     ts_ctsr2;                                       /* 0x0808 */
+        union   spe_reg ts_mtsr1;                               /* 0x0810 */
+        u64     ts_mtsr2;                                       /* 0x0818 */
+        union   spe_reg ts_itr1;                                /* 0x0820 */
+        u64     ts_itr2;                                        /* 0x0828 */
+        u64     ts_gitr;                                        /* 0x0830 */
+        u64     ts_isr;                                         /* 0x0838 */
+        u64     ts_imr;                                         /* 0x0840 */
+        union   spe_reg tm_cr1;                                 /* 0x0848 */
+        u64     tm_cr2;                                         /* 0x0850 */
+        u64     tm_simr;                                        /* 0x0858 */
+        union   ppe_spe_reg tm_tpr;                             /* 0x0860 */
+        union   spe_reg tm_str1;                                /* 0x0868 */
+        u64     tm_str2;                                        /* 0x0870 */
+        union   ppe_spe_reg tm_tsr;                             /* 0x0878 */
+
+        /* Power Management */
+        u64     pmcr;                                           /* 0x0880 */
+#define CBE_PMD_PAUSE_ZERO_CONTROL      0x10000
+        u64     pmsr;                                           /* 0x0888 */
+
+        /* Time Base Register */
+        u64     tbr;                                            /* 0x0890 */
+
+        u8      pad_0x0898_0x0c00 [0x0c00 - 0x0898];            /* 0x0898 */
+
+        /* Fault Isolation Registers */
+        u64     checkstop_fir;                                  /* 0x0c00 */
+        u64     recoverable_fir;                                /* 0x0c08 */
+        u64     spec_att_mchk_fir;                              /* 0x0c10 */
+        u32     fir_mode_reg;                                   /* 0x0c18 */
+        u8      pad_0x0c1c_0x0c20 [4];                          /* 0x0c1c */
+#define CBE_PMD_FIR_MODE_M8             0x00800
+        u64     fir_enable_mask;                                /* 0x0c20 */
+
+        u8      pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];            /* 0x0c28 */
+        u64     ras_esc_0;                                      /* 0x0ca8 */
+        u8      pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];            /* 0x0cb0 */
+};
+
+extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
+extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
+
+/*
+ * PMU shadow registers
+ *
+ * Many of the registers in the performance monitoring unit are write-only,
+ * so we need to save a copy of what we write to those registers.
+ *
+ * The actual data counters are read/write. However, writing to the counters
+ * only takes effect if the PMU is enabled. Otherwise the value is stored in
+ * a hardware latch until the next time the PMU is enabled. So we save a copy
+ * of the counter values if we need to read them back while the PMU is
+ * disabled. The counter_value_in_latch field is a bitmap indicating which
+ * counters currently have a value waiting to be written.
+ */
+
+struct cbe_pmd_shadow_regs {
+        u32 group_control;
+        u32 debug_bus_control;
+        u32 trace_address;
+        u32 ext_tr_timer;
+        u32 pm_status;
+        u32 pm_control;
+        u32 pm_interval;
+        u32 pm_start_stop;
+        u32 pm07_control[NR_CTRS];
+
+        u32 pm_ctr[NR_PHYS_CTRS];
+        u32 counter_value_in_latch;
+};
+
+extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
+extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
+
+/*
+ *
+ * IIC unit register definitions
+ *
+ */
+
+struct cbe_iic_pending_bits {
+        u32 data;
+        u8 flags;
+        u8 class;
+        u8 source;
+        u8 prio;
+};
+
+#define CBE_IIC_IRQ_VALID       0x80
+#define CBE_IIC_IRQ_IPI         0x40
+
+struct cbe_iic_thread_regs {
+        struct cbe_iic_pending_bits pending;
+        struct cbe_iic_pending_bits pending_destr;
+        u64 generate;
+        u64 prio;
+};
+
+struct cbe_iic_regs {
+        u8      pad_0x0000_0x0400[0x0400 - 0x0000];             /* 0x0000 */
+
+        /* IIC interrupt registers */
+        struct  cbe_iic_thread_regs thread[2];                  /* 0x0400 */
+
+        u64     iic_ir;                                         /* 0x0440 */
+#define CBE_IIC_IR_PRIO(x)      (((x) & 0xf) << 12)
+#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
+#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
+#define CBE_IIC_IR_IOC_0        0x0
+#define CBE_IIC_IR_IOC_1S       0xb
+#define CBE_IIC_IR_PT_0         0xe
+#define CBE_IIC_IR_PT_1         0xf
+
+        u64     iic_is;                                         /* 0x0448 */
+#define CBE_IIC_IS_PMI          0x2
+
+        u8      pad_0x0450_0x0500[0x0500 - 0x0450];             /* 0x0450 */
+
+        /* IOC FIR */
+        u64     ioc_fir_reset;                                  /* 0x0500 */
+        u64     ioc_fir_set;                                    /* 0x0508 */
+        u64     ioc_checkstop_enable;                           /* 0x0510 */
+        u64     ioc_fir_error_mask;                             /* 0x0518 */
+        u64     ioc_syserr_enable;                              /* 0x0520 */
+        u64     ioc_fir;                                        /* 0x0528 */
+
+        u8      pad_0x0530_0x1000[0x1000 - 0x0530];             /* 0x0530 */
+};
+
+extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
+extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
+
+
+struct cbe_mic_tm_regs {
+        u8      pad_0x0000_0x0040[0x0040 - 0x0000];             /* 0x0000 */
+
+        u64     mic_ctl_cnfg2;                                  /* 0x0040 */
+#define CBE_MIC_ENABLE_AUX_TRC          0x8000000000000000LL
+#define CBE_MIC_DISABLE_PWR_SAV_2       0x0200000000000000LL
+#define CBE_MIC_DISABLE_AUX_TRC_WRAP    0x0100000000000000LL
+#define CBE_MIC_ENABLE_AUX_TRC_INT      0x0080000000000000LL
+
+        u64     pad_0x0048;                                     /* 0x0048 */
+
+        u64     mic_aux_trc_base;                               /* 0x0050 */
+        u64     mic_aux_trc_max_addr;                           /* 0x0058 */
+        u64     mic_aux_trc_cur_addr;                           /* 0x0060 */
+        u64     mic_aux_trc_grf_addr;                           /* 0x0068 */
+        u64     mic_aux_trc_grf_data;                           /* 0x0070 */
+
+        u64     pad_0x0078;                                     /* 0x0078 */
+
+        u64     mic_ctl_cnfg_0;                                 /* 0x0080 */
+#define CBE_MIC_DISABLE_PWR_SAV_0       0x8000000000000000LL
+
+        u64     pad_0x0088;                                     /* 0x0088 */
+
+        u64     slow_fast_timer_0;                              /* 0x0090 */
+        u64     slow_next_timer_0;                              /* 0x0098 */
+
+        u8      pad_0x00a0_0x00f8[0x00f8 - 0x00a0];             /* 0x00a0 */
+        u64     mic_df_ecc_address_0;                           /* 0x00f8 */
+
+        u8      pad_0x0100_0x01b8[0x01b8 - 0x0100];             /* 0x0100 */
+        u64     mic_df_ecc_address_1;                           /* 0x01b8 */
+
+        u64     mic_ctl_cnfg_1;                                 /* 0x01c0 */
+#define CBE_MIC_DISABLE_PWR_SAV_1       0x8000000000000000LL
+
+        u64     pad_0x01c8;                                     /* 0x01c8 */
+
+        u64     slow_fast_timer_1;                              /* 0x01d0 */
+        u64     slow_next_timer_1;                              /* 0x01d8 */
+
+        u8      pad_0x01e0_0x0208[0x0208 - 0x01e0];             /* 0x01e0 */
+        u64     mic_exc;                                        /* 0x0208 */
+#define CBE_MIC_EXC_BLOCK_SCRUB         0x0800000000000000ULL
+#define CBE_MIC_EXC_FAST_SCRUB          0x0100000000000000ULL
+
+        u64     mic_mnt_cfg;                                    /* 0x0210 */
+#define CBE_MIC_MNT_CFG_CHAN_0_POP      0x0002000000000000ULL
+#define CBE_MIC_MNT_CFG_CHAN_1_POP      0x0004000000000000ULL
+
+        u64     mic_df_config;                                  /* 0x0218 */
+#define CBE_MIC_ECC_DISABLE_0           0x4000000000000000ULL
+#define CBE_MIC_ECC_REP_SINGLE_0        0x2000000000000000ULL
+#define CBE_MIC_ECC_DISABLE_1           0x0080000000000000ULL
+#define CBE_MIC_ECC_REP_SINGLE_1        0x0040000000000000ULL
+
+        u8      pad_0x0220_0x0230[0x0230 - 0x0220];             /* 0x0220 */
+        u64     mic_fir;                                        /* 0x0230 */
+#define CBE_MIC_FIR_ECC_SINGLE_0_ERR    0x0200000000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_ERR     0x0100000000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_ERR    0x0080000000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_ERR     0x0040000000000000ULL
+#define CBE_MIC_FIR_ECC_ERR_MASK        0xffff000000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_CTE    0x0000020000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_CTE     0x0000010000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_CTE    0x0000008000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_CTE     0x0000004000000000ULL
+#define CBE_MIC_FIR_ECC_CTE_MASK        0x0000ffff00000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_RESET  0x0000000002000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_RESET   0x0000000001000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_RESET  0x0000000000800000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_RESET   0x0000000000400000ULL
+#define CBE_MIC_FIR_ECC_RESET_MASK      0x00000000ffff0000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_SET    0x0000000000000200ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_SET     0x0000000000000100ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_SET    0x0000000000000080ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_SET     0x0000000000000040ULL
+#define CBE_MIC_FIR_ECC_SET_MASK        0x000000000000ffffULL
+        u64     mic_fir_debug;                                  /* 0x0238 */
+
+        u8      pad_0x0240_0x1000[0x1000 - 0x0240];             /* 0x0240 */
+};
+
+extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
+extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
+
+/* some utility functions to deal with SMT */
+extern u32 cbe_get_hw_thread_id(int cpu);
+extern u32 cbe_cpu_to_node(int cpu);
+extern u32 cbe_node_to_cpu(int node);
+
+/* Init this module early */
+extern void cbe_regs_init(void);
+
+
+#endif /* CBE_REGS_H */
diff --git a/arch/powerpc/include/asm/checksum.h b/arch/powerpc/include/asm/checksum.h
new file mode 100644
index 000000000000..7cdf358337cf
--- /dev/null
+++ b/arch/powerpc/include/asm/checksum.h
@@ -0,0 +1,117 @@
+#ifndef _ASM_POWERPC_CHECKSUM_H
+#define _ASM_POWERPC_CHECKSUM_H
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * This is a version of ip_compute_csum() optimized for IP headers,
+ * which always checksum on 4 octet boundaries.  ihl is the number
+ * of 32-bit words and is always >= 5.
+ */
+extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+extern __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        __wsum sum);
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+extern __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ * Computes the checksum of a memory block at src, length len,
+ * and adds in "sum" (32-bit), while copying the block to dst.
+ * If an access exception occurs on src or dst, it stores -EFAULT
+ * to *src_err or *dst_err respectively (if that pointer is not
+ * NULL), and, for an error on src, zeroes the rest of dst.
+ *
+ * Like csum_partial, this must be called with even lengths,
+ * except for the last fragment.
+ */
+extern __wsum csum_partial_copy_generic(const void *src, void *dst,
+                                              int len, __wsum sum,
+                                              int *src_err, int *dst_err);
+/*
+ * the same as csum_partial, but copies from src to dst while it
+ * checksums.
+ */
+#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
+        csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
+
+#define csum_partial_copy_nocheck(src, dst, len, sum)   \
+        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
+
+
+/*
+ * turns a 32-bit partial checksum (e.g. from csum_partial) into a
+ * 1's complement 16-bit checksum.
+ */
+static inline __sum16 csum_fold(__wsum sum)
+{
+        unsigned int tmp;
+
+        /* swap the two 16-bit halves of sum */
+        __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
+        /* if there is a carry from adding the two 16-bit halves,
+           it will carry from the lower half into the upper half,
+           giving us the correct sum in the upper half. */
+        return (__force __sum16)(~((__force u32)sum + tmp) >> 16);
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                     unsigned short len,
+                                     unsigned short proto,
+                                     __wsum sum)
+{
+#ifdef __powerpc64__
+        unsigned long s = (__force u32)sum;
+
+        s += (__force u32)saddr;
+        s += (__force u32)daddr;
+        s += proto + len;
+        s += (s >> 32);
+        return (__force __wsum) s;
+#else
+    __asm__("\n\
+        addc %0,%0,%1 \n\
+        adde %0,%0,%2 \n\
+        adde %0,%0,%3 \n\
+        addze %0,%0 \n\
+        "
+        : "=r" (sum)
+        : "r" (daddr), "r"(saddr), "r"(proto + len), "0"(sum));
+        return sum;
+#endif
+}
+#endif /* __KERNEL__ */
+#endif
diff --git a/arch/powerpc/include/asm/clk_interface.h b/arch/powerpc/include/asm/clk_interface.h
new file mode 100644
index 000000000000..ab1882c1e176
--- /dev/null
+++ b/arch/powerpc/include/asm/clk_interface.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_POWERPC_CLK_INTERFACE_H
+#define __ASM_POWERPC_CLK_INTERFACE_H
+
+#include <linux/clk.h>
+
+struct clk_interface {
+        struct clk*     (*clk_get)      (struct device *dev, const char *id);
+        int             (*clk_enable)   (struct clk *clk);
+        void            (*clk_disable)  (struct clk *clk);
+        unsigned long   (*clk_get_rate) (struct clk *clk);
+        void            (*clk_put)      (struct clk *clk);
+        long            (*clk_round_rate) (struct clk *clk, unsigned long rate);
+        int             (*clk_set_rate) (struct clk *clk, unsigned long rate);
+        int             (*clk_set_parent) (struct clk *clk, struct clk *parent);
+        struct clk*     (*clk_get_parent) (struct clk *clk);
+};
+
+extern struct clk_interface clk_functions;
+
+#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
new file mode 100644
index 000000000000..107d9b915e33
--- /dev/null
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -0,0 +1,54 @@
+#ifndef _ASM_POWERPC_CODE_PATCHING_H
+#define _ASM_POWERPC_CODE_PATCHING_H
+
+/*
+ * Copyright 2008, Michael Ellerman, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/types.h>
+
+#define PPC_NOP_INSTR           0x60000000
+#define PPC_LWSYNC_INSTR        0x7c2004ac
+
+/* Flags for create_branch:
+ * "b"   == create_branch(addr, target, 0);
+ * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
+ * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
+ * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
+ */
+#define BRANCH_SET_LINK 0x1
+#define BRANCH_ABSOLUTE 0x2
+
+unsigned int create_branch(const unsigned int *addr,
+                           unsigned long target, int flags);
+unsigned int create_cond_branch(const unsigned int *addr,
+                                unsigned long target, int flags);
+void patch_branch(unsigned int *addr, unsigned long target, int flags);
+void patch_instruction(unsigned int *addr, unsigned int instr);
+
+int instr_is_relative_branch(unsigned int instr);
+int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
+unsigned long branch_target(const unsigned int *instr);
+unsigned int translate_branch(const unsigned int *dest,
+                              const unsigned int *src);
+
+static inline unsigned long ppc_function_entry(void *func)
+{
+#ifdef CONFIG_PPC64
+        /*
+         * On PPC64 the function pointer actually points to the function's
+         * descriptor. The first entry in the descriptor is the address
+         * of the function text.
+         */
+        return ((func_descr_t *)func)->entry;
+#else
+        return (unsigned long)func;
+#endif
+}
+
+#endif /* _ASM_POWERPC_CODE_PATCHING_H */
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
new file mode 100644
index 000000000000..d811a8cd7b58
--- /dev/null
+++ b/arch/powerpc/include/asm/compat.h
@@ -0,0 +1,214 @@
+#ifndef _ASM_POWERPC_COMPAT_H
+#define _ASM_POWERPC_COMPAT_H
+#ifdef __KERNEL__
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+#include <linux/sched.h>
+
+#define COMPAT_USER_HZ  100
+
+typedef u32             compat_size_t;
+typedef s32             compat_ssize_t;
+typedef s32             compat_time_t;
+typedef s32             compat_clock_t;
+typedef s32             compat_pid_t;
+typedef u32             __compat_uid_t;
+typedef u32             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
+typedef u32             compat_mode_t;
+typedef u32             compat_ino_t;
+typedef u32             compat_dev_t;
+typedef s32             compat_off_t;
+typedef s64             compat_loff_t;
+typedef s16             compat_nlink_t;
+typedef u16             compat_ipc_pid_t;
+typedef s32             compat_daddr_t;
+typedef u32             compat_caddr_t;
+typedef __kernel_fsid_t compat_fsid_t;
+typedef s32             compat_key_t;
+typedef s32             compat_timer_t;
+
+typedef s32             compat_int_t;
+typedef s32             compat_long_t;
+typedef s64             compat_s64;
+typedef u32             compat_uint_t;
+typedef u32             compat_ulong_t;
+typedef u64             compat_u64;
+
+struct compat_timespec {
+        compat_time_t   tv_sec;
+        s32             tv_nsec;
+};
+
+struct compat_timeval {
+        compat_time_t   tv_sec;
+        s32             tv_usec;
+};
+
+struct compat_stat {
+        compat_dev_t    st_dev;
+        compat_ino_t    st_ino;
+        compat_mode_t   st_mode;
+        compat_nlink_t  st_nlink;
+        __compat_uid32_t        st_uid;
+        __compat_gid32_t        st_gid;
+        compat_dev_t    st_rdev;
+        compat_off_t    st_size;
+        compat_off_t    st_blksize;
+        compat_off_t    st_blocks;
+        compat_time_t   st_atime;
+        u32             st_atime_nsec;
+        compat_time_t   st_mtime;
+        u32             st_mtime_nsec;
+        compat_time_t   st_ctime;
+        u32             st_ctime_nsec;
+        u32             __unused4[2];
+};
+
+struct compat_flock {
+        short           l_type;
+        short           l_whence;
+        compat_off_t    l_start;
+        compat_off_t    l_len;
+        compat_pid_t    l_pid;
+};
+
+#define F_GETLK64       12      /*  using 'struct flock64' */
+#define F_SETLK64       13
+#define F_SETLKW64      14
+
+struct compat_flock64 {
+        short           l_type;
+        short           l_whence;
+        compat_loff_t   l_start;
+        compat_loff_t   l_len;
+        compat_pid_t    l_pid;
+};
+
+struct compat_statfs {
+        int             f_type;
+        int             f_bsize;
+        int             f_blocks;
+        int             f_bfree;
+        int             f_bavail;
+        int             f_files;
+        int             f_ffree;
+        compat_fsid_t   f_fsid;
+        int             f_namelen;      /* SunOS ignores this field. */
+        int             f_frsize;
+        int             f_spare[5];
+};
+
+#define COMPAT_RLIM_OLD_INFINITY        0x7fffffff
+#define COMPAT_RLIM_INFINITY            0xffffffff
+
+typedef u32             compat_old_sigset_t;
+
+#define _COMPAT_NSIG            64
+#define _COMPAT_NSIG_BPW        32
+
+typedef u32             compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX        0x7fffffff
+#define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
+
+/*
+ * A pointer passed in from user mode. This should not
+ * be used for syscall parameters, just declare them
+ * as pointers because the syscall entry code will have
+ * appropriately converted them already.
+ */
+typedef u32             compat_uptr_t;
+
+static inline void __user *compat_ptr(compat_uptr_t uptr)
+{
+        return (void __user *)(unsigned long)uptr;
+}
+
+static inline compat_uptr_t ptr_to_compat(void __user *uptr)
+{
+        return (u32)(unsigned long)uptr;
+}
+
+static inline void __user *compat_alloc_user_space(long len)
+{
+        struct pt_regs *regs = current->thread.regs;
+        unsigned long usp = regs->gpr[1];
+
+        /*
+         * We cant access below the stack pointer in the 32bit ABI and
+         * can access 288 bytes in the 64bit ABI
+         */
+        if (!(test_thread_flag(TIF_32BIT)))
+                usp -= 288;
+
+        return (void __user *) (usp - len);
+}
+
+/*
+ * ipc64_perm is actually 32/64bit clean but since the compat layer refers to
+ * it we may as well define it.
+ */
+struct compat_ipc64_perm {
+        compat_key_t key;
+        __compat_uid_t uid;
+        __compat_gid_t gid;
+        __compat_uid_t cuid;
+        __compat_gid_t cgid;
+        compat_mode_t mode;
+        unsigned int seq;
+        unsigned int __pad2;
+        unsigned long __unused1;        /* yes they really are 64bit pads */
+        unsigned long __unused2;
+};
+
+struct compat_semid64_ds {
+        struct compat_ipc64_perm sem_perm;
+        unsigned int __unused1;
+        compat_time_t sem_otime;
+        unsigned int __unused2;
+        compat_time_t sem_ctime;
+        compat_ulong_t sem_nsems;
+        compat_ulong_t __unused3;
+        compat_ulong_t __unused4;
+};
+
+struct compat_msqid64_ds {
+        struct compat_ipc64_perm msg_perm;
+        unsigned int __unused1;
+        compat_time_t msg_stime;
+        unsigned int __unused2;
+        compat_time_t msg_rtime;
+        unsigned int __unused3;
+        compat_time_t msg_ctime;
+        compat_ulong_t msg_cbytes;
+        compat_ulong_t msg_qnum;
+        compat_ulong_t msg_qbytes;
+        compat_pid_t msg_lspid;
+        compat_pid_t msg_lrpid;
+        compat_ulong_t __unused4;
+        compat_ulong_t __unused5;
+};
+
+struct compat_shmid64_ds {
+        struct compat_ipc64_perm shm_perm;
+        unsigned int __unused1;
+        compat_time_t shm_atime;
+        unsigned int __unused2;
+        compat_time_t shm_dtime;
+        unsigned int __unused3;
+        compat_time_t shm_ctime;
+        unsigned int __unused4;
+        compat_size_t shm_segsz;
+        compat_pid_t shm_cpid;
+        compat_pid_t shm_lpid;
+        compat_ulong_t shm_nattch;
+        compat_ulong_t __unused5;
+        compat_ulong_t __unused6;
+};
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_COMPAT_H */
diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
new file mode 100644
index 000000000000..24d79e3abd8e
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm.h
@@ -0,0 +1,106 @@
+#ifndef __CPM_H
+#define __CPM_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/of.h>
+
+/* Opcodes common to CPM1 and CPM2
+*/
+#define CPM_CR_INIT_TRX         ((ushort)0x0000)
+#define CPM_CR_INIT_RX          ((ushort)0x0001)
+#define CPM_CR_INIT_TX          ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
+#define CPM_CR_STOP_TX          ((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
+#define CPM_CR_RESTART_TX       ((ushort)0x0006)
+#define CPM_CR_CLOSE_RX_BD      ((ushort)0x0007)
+#define CPM_CR_SET_GADDR        ((ushort)0x0008)
+#define CPM_CR_SET_TIMER        ((ushort)0x0008)
+#define CPM_CR_STOP_IDMA        ((ushort)0x000b)
+
+/* Buffer descriptors used by many of the CPM protocols. */
+typedef struct cpm_buf_desc {
+        ushort  cbd_sc;         /* Status and Control */
+        ushort  cbd_datlen;     /* Data length in buffer */
+        uint    cbd_bufaddr;    /* Buffer address in host memory */
+} cbd_t;
+
+/* Buffer descriptor control/status used by serial
+ */
+
+#define BD_SC_EMPTY     (0x8000)        /* Receive is empty */
+#define BD_SC_READY     (0x8000)        /* Transmit is ready */
+#define BD_SC_WRAP      (0x2000)        /* Last buffer descriptor */
+#define BD_SC_INTRPT    (0x1000)        /* Interrupt on change */
+#define BD_SC_LAST      (0x0800)        /* Last buffer in frame */
+#define BD_SC_TC        (0x0400)        /* Transmit CRC */
+#define BD_SC_CM        (0x0200)        /* Continous mode */
+#define BD_SC_ID        (0x0100)        /* Rec'd too many idles */
+#define BD_SC_P         (0x0100)        /* xmt preamble */
+#define BD_SC_BR        (0x0020)        /* Break received */
+#define BD_SC_FR        (0x0010)        /* Framing error */
+#define BD_SC_PR        (0x0008)        /* Parity error */
+#define BD_SC_NAK       (0x0004)        /* NAK - did not respond */
+#define BD_SC_OV        (0x0002)        /* Overrun */
+#define BD_SC_UN        (0x0002)        /* Underrun */
+#define BD_SC_CD        (0x0001)        /* */
+#define BD_SC_CL        (0x0001)        /* Collision */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY        (0x8000)
+#define BD_ENET_RX_WRAP         (0x2000)
+#define BD_ENET_RX_INTR         (0x1000)
+#define BD_ENET_RX_LAST         (0x0800)
+#define BD_ENET_RX_FIRST        (0x0400)
+#define BD_ENET_RX_MISS         (0x0100)
+#define BD_ENET_RX_BC           (0x0080)        /* FCC Only */
+#define BD_ENET_RX_MC           (0x0040)        /* FCC Only */
+#define BD_ENET_RX_LG           (0x0020)
+#define BD_ENET_RX_NO           (0x0010)
+#define BD_ENET_RX_SH           (0x0008)
+#define BD_ENET_RX_CR           (0x0004)
+#define BD_ENET_RX_OV           (0x0002)
+#define BD_ENET_RX_CL           (0x0001)
+#define BD_ENET_RX_STATS        (0x01ff)        /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY        (0x8000)
+#define BD_ENET_TX_PAD          (0x4000)
+#define BD_ENET_TX_WRAP         (0x2000)
+#define BD_ENET_TX_INTR         (0x1000)
+#define BD_ENET_TX_LAST         (0x0800)
+#define BD_ENET_TX_TC           (0x0400)
+#define BD_ENET_TX_DEF          (0x0200)
+#define BD_ENET_TX_HB           (0x0100)
+#define BD_ENET_TX_LC           (0x0080)
+#define BD_ENET_TX_RL           (0x0040)
+#define BD_ENET_TX_RCMASK       (0x003c)
+#define BD_ENET_TX_UN           (0x0002)
+#define BD_ENET_TX_CSL          (0x0001)
+#define BD_ENET_TX_STATS        (0x03ff)        /* All status bits */
+
+/* Buffer descriptor control/status used by Transparent mode SCC.
+ */
+#define BD_SCC_TX_LAST          (0x0800)
+
+/* Buffer descriptor control/status used by I2C.
+ */
+#define BD_I2C_START            (0x0400)
+
+int cpm_muram_init(void);
+unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
+int cpm_muram_free(unsigned long offset);
+unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
+void __iomem *cpm_muram_addr(unsigned long offset);
+unsigned long cpm_muram_offset(void __iomem *addr);
+dma_addr_t cpm_muram_dma(void __iomem *addr);
+int cpm_command(u32 command, u8 opcode);
+
+int cpm2_gpiochip_add32(struct device_node *np);
+
+#endif
diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
new file mode 100644
index 000000000000..2ff798744c1d
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm1.h
@@ -0,0 +1,652 @@
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels.  Some CPM control and status is available
+ * throught the MPC8xx internal memory map.  See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities.  I (or someone else) will add definitions as they
+ * are needed.  -- Dan
+ *
+ * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
+ * bytes of the DP RAM and relocates the I2C parameter area to the
+ * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
+ * or other use.
+ */
+#ifndef __CPM1__
+#define __CPM1__
+
+#include <asm/8xx_immap.h>
+#include <asm/ptrace.h>
+#include <asm/cpm.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST      ((ushort)0x8000)
+#define CPM_CR_OPCODE   ((ushort)0x0f00)
+#define CPM_CR_CHAN     ((ushort)0x00f0)
+#define CPM_CR_FLG      ((ushort)0x0001)
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1          ((ushort)0x0000)
+#define CPM_CR_CH_I2C           ((ushort)0x0001)        /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2          ((ushort)0x0004)
+#define CPM_CR_CH_SPI           ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
+#define CPM_CR_CH_TIMER         CPM_CR_CH_SPI
+#define CPM_CR_CH_SCC3          ((ushort)0x0008)
+#define CPM_CR_CH_SMC1          ((ushort)0x0009)        /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4          ((ushort)0x000c)
+#define CPM_CR_CH_SMC2          ((ushort)0x000d)        /* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
+
+#define cpm_dpalloc cpm_muram_alloc
+#define cpm_dpfree cpm_muram_free
+#define cpm_dpram_addr cpm_muram_addr
+#define cpm_dpram_phys cpm_muram_dma
+
+extern void cpm_setbrg(uint brg, uint rate);
+
+extern void cpm_load_patch(cpm8xx_t *cp);
+
+extern void cpm_reset(void);
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1      ((uint)0x0000)
+#define PROFF_IIC       ((uint)0x0080)
+#define PROFF_SCC2      ((uint)0x0100)
+#define PROFF_SPI       ((uint)0x0180)
+#define PROFF_SCC3      ((uint)0x0200)
+#define PROFF_SMC1      ((uint)0x0280)
+#define PROFF_SCC4      ((uint)0x0300)
+#define PROFF_SMC2      ((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ * The MBX uses SMC1 as the host serial port.
+ */
+typedef struct smc_uart {
+        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  smc_rfcr;       /* Rx function code */
+        u_char  smc_tfcr;       /* Tx function code */
+        ushort  smc_mrblr;      /* Max receive buffer length */
+        uint    smc_rstate;     /* Internal */
+        uint    smc_idp;        /* Internal */
+        ushort  smc_rbptr;      /* Internal */
+        ushort  smc_ibc;        /* Internal */
+        uint    smc_rxtmp;      /* Internal */
+        uint    smc_tstate;     /* Internal */
+        uint    smc_tdp;        /* Internal */
+        ushort  smc_tbptr;      /* Internal */
+        ushort  smc_tbc;        /* Internal */
+        uint    smc_txtmp;      /* Internal */
+        ushort  smc_maxidl;     /* Maximum idle characters */
+        ushort  smc_tmpidl;     /* Temporary idle counter */
+        ushort  smc_brklen;     /* Last received break length */
+        ushort  smc_brkec;      /* rcv'd break condition counter */
+        ushort  smc_brkcr;      /* xmt break count register */
+        ushort  smc_rmask;      /* Temporary bit mask */
+        char    res1[8];        /* Reserved */
+        ushort  smc_rpbase;     /* Relocation pointer */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define SMCMR_REN       ((ushort)0x0001)
+#define SMCMR_TEN       ((ushort)0x0002)
+#define SMCMR_DM        ((ushort)0x000c)
+#define SMCMR_SM_GCI    ((ushort)0x0000)
+#define SMCMR_SM_UART   ((ushort)0x0020)
+#define SMCMR_SM_TRANS  ((ushort)0x0030)
+#define SMCMR_SM_MASK   ((ushort)0x0030)
+#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
+#define SMCMR_REVD      SMCMR_PM_EVEN
+#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
+#define SMCMR_BS        SMCMR_PEN
+#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
+#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
+#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer.  It is half duplex, in that
+ * it can only receive or transmit.  The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+        ushort  scent_rbase;
+        ushort  scent_tbase;
+        u_char  scent_cfcr;
+        u_char  scent_smask;
+        ushort  scent_mrblr;
+        uint    scent_rstate;
+        uint    scent_r_ptr;
+        ushort  scent_rbptr;
+        ushort  scent_r_cnt;
+        uint    scent_rtemp;
+        uint    scent_tstate;
+        uint    scent_t_ptr;
+        ushort  scent_tbptr;
+        ushort  scent_t_cnt;
+        uint    scent_ttemp;
+        ushort  scent_max_sl;
+        ushort  scent_sl_cnt;
+        ushort  scent_character1;
+        ushort  scent_character2;
+        ushort  scent_character3;
+        ushort  scent_character4;
+        ushort  scent_character5;
+        ushort  scent_character6;
+        ushort  scent_character7;
+        ushort  scent_character8;
+        ushort  scent_rccm;
+        ushort  scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F      ((u_char)0x08)
+#define SMC_CENT_PE     ((u_char)0x04)
+#define SMC_CENT_S      ((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
+#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
+#define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
+#define SMCM_BSY        ((unsigned char)0x04)
+#define SMCM_TX         ((unsigned char)0x02)
+#define SMCM_RX         ((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST             ((uint)0x00020000)
+#define CPM_BRG_EN              ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
+#define CPM_BRG_ATB             ((uint)0x00002000)
+#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
+#define CPM_BRG_DIV16           ((uint)0x00000001)
+
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP           ((uint)0x00040000)
+#define SCC_GSMRH_GDE           ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
+#define SCC_GSMRH_REVD          ((uint)0x00002000)
+#define SCC_GSMRH_TRX           ((uint)0x00001000)
+#define SCC_GSMRH_TTX           ((uint)0x00000800)
+#define SCC_GSMRH_CDP           ((uint)0x00000400)
+#define SCC_GSMRH_CTSP          ((uint)0x00000200)
+#define SCC_GSMRH_CDS           ((uint)0x00000100)
+#define SCC_GSMRH_CTSS          ((uint)0x00000080)
+#define SCC_GSMRH_TFL           ((uint)0x00000040)
+#define SCC_GSMRH_RFW           ((uint)0x00000020)
+#define SCC_GSMRH_TXSY          ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
+#define SCC_GSMRH_RTSM          ((uint)0x00000002)
+#define SCC_GSMRH_RSYN          ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
+#define SCC_GSMRL_TCI           ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
+#define SCC_GSMRL_RINV          ((uint)0x02000000)
+#define SCC_GSMRL_TINV          ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
+#define SCC_GSMRL_TEND          ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
+#define SCC_GSMRL_ENR           ((uint)0x00000020)
+#define SCC_GSMRL_ENT           ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_QMC      ((uint)0x0000000a)
+#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
+
+#define SCC_TODR_TOD            ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE        ((unsigned char)0x10)
+#define SCCM_BSY        ((unsigned char)0x04)
+#define SCCM_TX         ((unsigned char)0x02)
+#define SCCM_RX         ((unsigned char)0x01)
+
+typedef struct scc_param {
+        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  scc_rfcr;       /* Rx function code */
+        u_char  scc_tfcr;       /* Tx function code */
+        ushort  scc_mrblr;      /* Max receive buffer length */
+        uint    scc_rstate;     /* Internal */
+        uint    scc_idp;        /* Internal */
+        ushort  scc_rbptr;      /* Internal */
+        ushort  scc_ibc;        /* Internal */
+        uint    scc_rxtmp;      /* Internal */
+        uint    scc_tstate;     /* Internal */
+        uint    scc_tdp;        /* Internal */
+        ushort  scc_tbptr;      /* Internal */
+        ushort  scc_tbc;        /* Internal */
+        uint    scc_txtmp;      /* Internal */
+        uint    scc_rcrc;       /* Internal */
+        uint    scc_tcrc;       /* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
+
+/* CPM Ethernet through SCCx.
+ */
+typedef struct scc_enet {
+        sccp_t  sen_genscc;
+        uint    sen_cpres;      /* Preset CRC */
+        uint    sen_cmask;      /* Constant mask for CRC */
+        uint    sen_crcec;      /* CRC Error counter */
+        uint    sen_alec;       /* alignment error counter */
+        uint    sen_disfc;      /* discard frame counter */
+        ushort  sen_pads;       /* Tx short frame pad character */
+        ushort  sen_retlim;     /* Retry limit threshold */
+        ushort  sen_retcnt;     /* Retry limit counter */
+        ushort  sen_maxflr;     /* maximum frame length register */
+        ushort  sen_minflr;     /* minimum frame length register */
+        ushort  sen_maxd1;      /* maximum DMA1 length */
+        ushort  sen_maxd2;      /* maximum DMA2 length */
+        ushort  sen_maxd;       /* Rx max DMA */
+        ushort  sen_dmacnt;     /* Rx DMA counter */
+        ushort  sen_maxb;       /* Max BD byte count */
+        ushort  sen_gaddr1;     /* Group address filter */
+        ushort  sen_gaddr2;
+        ushort  sen_gaddr3;
+        ushort  sen_gaddr4;
+        uint    sen_tbuf0data0; /* Save area 0 - current frame */
+        uint    sen_tbuf0data1; /* Save area 1 - current frame */
+        uint    sen_tbuf0rba;   /* Internal */
+        uint    sen_tbuf0crc;   /* Internal */
+        ushort  sen_tbuf0bcnt;  /* Internal */
+        ushort  sen_paddrh;     /* physical address (MSB) */
+        ushort  sen_paddrm;
+        ushort  sen_paddrl;     /* physical address (LSB) */
+        ushort  sen_pper;       /* persistence */
+        ushort  sen_rfbdptr;    /* Rx first BD pointer */
+        ushort  sen_tfbdptr;    /* Tx first BD pointer */
+        ushort  sen_tlbdptr;    /* Tx last BD pointer */
+        uint    sen_tbuf1data0; /* Save area 0 - current frame */
+        uint    sen_tbuf1data1; /* Save area 1 - current frame */
+        uint    sen_tbuf1rba;   /* Internal */
+        uint    sen_tbuf1crc;   /* Internal */
+        ushort  sen_tbuf1bcnt;  /* Internal */
+        ushort  sen_txlen;      /* Tx Frame length counter */
+        ushort  sen_iaddr1;     /* Individual address filter */
+        ushort  sen_iaddr2;
+        ushort  sen_iaddr3;
+        ushort  sen_iaddr4;
+        ushort  sen_boffcnt;    /* Backoff counter */
+
+        /* NOTE: Some versions of the manual have the following items
+         * incorrectly documented.  Below is the proper order.
+         */
+        ushort  sen_taddrh;     /* temp address (MSB) */
+        ushort  sen_taddrm;
+        ushort  sen_taddrl;     /* temp address (LSB) */
+} scc_enet_t;
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
+#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
+#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
+#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
+#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
+#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
+
+/* SCC Mode Register (PMSR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
+#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
+#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
+#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
+#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
+#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
+#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
+#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
+#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
+#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
+#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
+#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
+#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+        sccp_t  scc_genscc;
+        char    res1[8];        /* Reserved */
+        ushort  scc_maxidl;     /* Maximum idle chars */
+        ushort  scc_idlc;       /* temp idle counter */
+        ushort  scc_brkcr;      /* Break count register */
+        ushort  scc_parec;      /* receive parity error counter */
+        ushort  scc_frmec;      /* receive framing error counter */
+        ushort  scc_nosec;      /* receive noise counter */
+        ushort  scc_brkec;      /* receive break condition counter */
+        ushort  scc_brkln;      /* last received break length */
+        ushort  scc_uaddr1;     /* UART address character 1 */
+        ushort  scc_uaddr2;     /* UART address character 2 */
+        ushort  scc_rtemp;      /* Temp storage */
+        ushort  scc_toseq;      /* Transmit out of sequence char */
+        ushort  scc_char1;      /* control character 1 */
+        ushort  scc_char2;      /* control character 2 */
+        ushort  scc_char3;      /* control character 3 */
+        ushort  scc_char4;      /* control character 4 */
+        ushort  scc_char5;      /* control character 5 */
+        ushort  scc_char6;      /* control character 6 */
+        ushort  scc_char7;      /* control character 7 */
+        ushort  scc_char8;      /* control character 8 */
+        ushort  scc_rccm;       /* receive control character mask */
+        ushort  scc_rccr;       /* receive control character register */
+        ushort  scc_rlbc;       /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR           ((ushort)0x1000)
+#define UART_SCCM_GLT           ((ushort)0x0800)
+#define UART_SCCM_AB            ((ushort)0x0200)
+#define UART_SCCM_IDL           ((ushort)0x0100)
+#define UART_SCCM_GRA           ((ushort)0x0080)
+#define UART_SCCM_BRKE          ((ushort)0x0040)
+#define UART_SCCM_BRKS          ((ushort)0x0020)
+#define UART_SCCM_CCR           ((ushort)0x0008)
+#define UART_SCCM_BSY           ((ushort)0x0004)
+#define UART_SCCM_TX            ((ushort)0x0002)
+#define UART_SCCM_RX            ((ushort)0x0001)
+
+/* The SCC PMSR when used as a UART.
+*/
+#define SCU_PSMR_FLC            ((ushort)0x8000)
+#define SCU_PSMR_SL             ((ushort)0x4000)
+#define SCU_PSMR_CL             ((ushort)0x3000)
+#define SCU_PSMR_UM             ((ushort)0x0c00)
+#define SCU_PSMR_FRZ            ((ushort)0x0200)
+#define SCU_PSMR_RZS            ((ushort)0x0100)
+#define SCU_PSMR_SYN            ((ushort)0x0080)
+#define SCU_PSMR_DRT            ((ushort)0x0040)
+#define SCU_PSMR_PEN            ((ushort)0x0010)
+#define SCU_PSMR_RPM            ((ushort)0x000c)
+#define SCU_PSMR_REVP           ((ushort)0x0008)
+#define SCU_PSMR_TPM            ((ushort)0x0003)
+#define SCU_PSMR_TEVP           ((ushort)0x0002)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+        sccp_t  st_genscc;
+        uint    st_cpres;       /* Preset CRC */
+        uint    st_cmask;       /* Constant mask for CRC */
+} scc_trans_t;
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
+        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
+        u_char  iic_rfcr;       /* Rx function code */
+        u_char  iic_tfcr;       /* Tx function code */
+        ushort  iic_mrblr;      /* Max receive buffer length */
+        uint    iic_rstate;     /* Internal */
+        uint    iic_rdp;        /* Internal */
+        ushort  iic_rbptr;      /* Internal */
+        ushort  iic_rbc;        /* Internal */
+        uint    iic_rxtmp;      /* Internal */
+        uint    iic_tstate;     /* Internal */
+        uint    iic_tdp;        /* Internal */
+        ushort  iic_tbptr;      /* Internal */
+        ushort  iic_tbc;        /* Internal */
+        uint    iic_txtmp;      /* Internal */
+        char    res1[4];        /* Reserved */
+        ushort  iic_rpbase;     /* Relocation pointer */
+        char    res2[2];        /* Reserved */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
+        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
+        u_char  spi_rfcr;       /* Rx function code */
+        u_char  spi_tfcr;       /* Tx function code */
+        ushort  spi_mrblr;      /* Max receive buffer length */
+        uint    spi_rstate;     /* Internal */
+        uint    spi_rdp;        /* Internal */
+        ushort  spi_rbptr;      /* Internal */
+        ushort  spi_rbc;        /* Internal */
+        uint    spi_rxtmp;      /* Internal */
+        uint    spi_tstate;     /* Internal */
+        uint    spi_tdp;        /* Internal */
+        ushort  spi_tbptr;      /* Internal */
+        ushort  spi_tbc;        /* Internal */
+        uint    spi_txtmp;      /* Internal */
+        uint    spi_res;
+        ushort  spi_rpbase;     /* Relocation pointer */
+        ushort  spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
+#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
+#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
+#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
+#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
+#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
+#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
+#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
+#define SPMODE_LEN4     ((ushort)0x0030)        /*  4 bits per char */
+#define SPMODE_LEN8     ((ushort)0x0070)        /*  8 bits per char */
+#define SPMODE_LEN16    ((ushort)0x00f0)        /* 16 bits per char */
+#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
+
+/* SPIE fields */
+#define SPIE_MME        0x20
+#define SPIE_TXE        0x10
+#define SPIE_BSY        0x04
+#define SPIE_TXB        0x02
+#define SPIE_RXB        0x01
+
+/*
+ * RISC Controller Configuration Register definitons
+ */
+#define RCCR_TIME       0x8000                  /* RISC Timer Enable */
+#define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)       /* RISC Timer Period */
+#define RCCR_TIME_MASK  0x00FF                  /* not RISC Timer related bits */
+
+/* RISC Timer Parameter RAM offset */
+#define PROFF_RTMR      ((uint)0x01B0)
+
+typedef struct risc_timer_pram {
+        unsigned short  tm_base;        /* RISC Timer Table Base Address */
+        unsigned short  tm_ptr;         /* RISC Timer Table Pointer (internal) */
+        unsigned short  r_tmr;          /* RISC Timer Mode Register */
+        unsigned short  r_tmv;          /* RISC Timer Valid Register */
+        unsigned long   tm_cmd;         /* RISC Timer Command Register */
+        unsigned long   tm_cnt;         /* RISC Timer Internal Count */
+} rt_pram_t;
+
+/* Bits in RISC Timer Command Register */
+#define TM_CMD_VALID    0x80000000      /* Valid - Enables the timer */
+#define TM_CMD_RESTART  0x40000000      /* Restart - for automatic restart */
+#define TM_CMD_PWM      0x20000000      /* Run in Pulse Width Modulation Mode */
+#define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
+#define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
+
+/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
+ * channels or devices.  All of these are presented to the PPC core
+ * as a single interrupt.  The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler.  We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR               32
+#define CPMVEC_PIO_PC15         ((ushort)0x1f)
+#define CPMVEC_SCC1             ((ushort)0x1e)
+#define CPMVEC_SCC2             ((ushort)0x1d)
+#define CPMVEC_SCC3             ((ushort)0x1c)
+#define CPMVEC_SCC4             ((ushort)0x1b)
+#define CPMVEC_PIO_PC14         ((ushort)0x1a)
+#define CPMVEC_TIMER1           ((ushort)0x19)
+#define CPMVEC_PIO_PC13         ((ushort)0x18)
+#define CPMVEC_PIO_PC12         ((ushort)0x17)
+#define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
+#define CPMVEC_IDMA1            ((ushort)0x15)
+#define CPMVEC_IDMA2            ((ushort)0x14)
+#define CPMVEC_TIMER2           ((ushort)0x12)
+#define CPMVEC_RISCTIMER        ((ushort)0x11)
+#define CPMVEC_I2C              ((ushort)0x10)
+#define CPMVEC_PIO_PC11         ((ushort)0x0f)
+#define CPMVEC_PIO_PC10         ((ushort)0x0e)
+#define CPMVEC_TIMER3           ((ushort)0x0c)
+#define CPMVEC_PIO_PC9          ((ushort)0x0b)
+#define CPMVEC_PIO_PC8          ((ushort)0x0a)
+#define CPMVEC_PIO_PC7          ((ushort)0x09)
+#define CPMVEC_TIMER4           ((ushort)0x07)
+#define CPMVEC_PIO_PC6          ((ushort)0x06)
+#define CPMVEC_SPI              ((ushort)0x05)
+#define CPMVEC_SMC1             ((ushort)0x04)
+#define CPMVEC_SMC2             ((ushort)0x03)
+#define CPMVEC_PIO_PC5          ((ushort)0x02)
+#define CPMVEC_PIO_PC4          ((ushort)0x01)
+#define CPMVEC_ERROR            ((ushort)0x00)
+
+/* CPM interrupt configuration vector.
+*/
+#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
+#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
+#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
+#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
+#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
+#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
+#define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
+#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
+
+#define IMAP_ADDR               (get_immrbase())
+
+#define CPM_PIN_INPUT     0
+#define CPM_PIN_OUTPUT    1
+#define CPM_PIN_PRIMARY   0
+#define CPM_PIN_SECONDARY 2
+#define CPM_PIN_GPIO      4
+#define CPM_PIN_OPENDRAIN 8
+
+enum cpm_port {
+        CPM_PORTA,
+        CPM_PORTB,
+        CPM_PORTC,
+        CPM_PORTD,
+        CPM_PORTE,
+};
+
+void cpm1_set_pin(enum cpm_port port, int pin, int flags);
+
+enum cpm_clk_dir {
+        CPM_CLK_RX,
+        CPM_CLK_TX,
+        CPM_CLK_RTX
+};
+
+enum cpm_clk_target {
+        CPM_CLK_SCC1,
+        CPM_CLK_SCC2,
+        CPM_CLK_SCC3,
+        CPM_CLK_SCC4,
+        CPM_CLK_SMC1,
+        CPM_CLK_SMC2,
+};
+
+enum cpm_clk {
+        CPM_BRG1,       /* Baud Rate Generator  1 */
+        CPM_BRG2,       /* Baud Rate Generator  2 */
+        CPM_BRG3,       /* Baud Rate Generator  3 */
+        CPM_BRG4,       /* Baud Rate Generator  4 */
+        CPM_CLK1,       /* Clock  1 */
+        CPM_CLK2,       /* Clock  2 */
+        CPM_CLK3,       /* Clock  3 */
+        CPM_CLK4,       /* Clock  4 */
+        CPM_CLK5,       /* Clock  5 */
+        CPM_CLK6,       /* Clock  6 */
+        CPM_CLK7,       /* Clock  7 */
+        CPM_CLK8,       /* Clock  8 */
+};
+
+int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
+
+#endif /* __CPM1__ */
diff --git a/arch/powerpc/include/asm/cpm2.h b/arch/powerpc/include/asm/cpm2.h
new file mode 100644
index 000000000000..2a6fa0183ac9
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm2.h
@@ -0,0 +1,1195 @@
+/*
+ * Communication Processor Module v2.
+ *
+ * This file contains structures and information for the communication
+ * processor channels found in the dual port RAM or parameter RAM.
+ * All CPM control and status is available through the CPM2 internal
+ * memory map.  See immap_cpm2.h for details.
+ */
+#ifdef __KERNEL__
+#ifndef __CPM2__
+#define __CPM2__
+
+#include <asm/immap_cpm2.h>
+#include <asm/cpm.h>
+#include <sysdev/fsl_soc.h>
+
+#ifdef CONFIG_PPC_85xx
+#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
+#endif
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST      ((uint)0x80000000)
+#define CPM_CR_PAGE     ((uint)0x7c000000)
+#define CPM_CR_SBLOCK   ((uint)0x03e00000)
+#define CPM_CR_FLG      ((uint)0x00010000)
+#define CPM_CR_MCN      ((uint)0x00003fc0)
+#define CPM_CR_OPCODE   ((uint)0x0000000f)
+
+/* Device sub-block and page codes.
+*/
+#define CPM_CR_SCC1_SBLOCK      (0x04)
+#define CPM_CR_SCC2_SBLOCK      (0x05)
+#define CPM_CR_SCC3_SBLOCK      (0x06)
+#define CPM_CR_SCC4_SBLOCK      (0x07)
+#define CPM_CR_SMC1_SBLOCK      (0x08)
+#define CPM_CR_SMC2_SBLOCK      (0x09)
+#define CPM_CR_SPI_SBLOCK       (0x0a)
+#define CPM_CR_I2C_SBLOCK       (0x0b)
+#define CPM_CR_TIMER_SBLOCK     (0x0f)
+#define CPM_CR_RAND_SBLOCK      (0x0e)
+#define CPM_CR_FCC1_SBLOCK      (0x10)
+#define CPM_CR_FCC2_SBLOCK      (0x11)
+#define CPM_CR_FCC3_SBLOCK      (0x12)
+#define CPM_CR_IDMA1_SBLOCK     (0x14)
+#define CPM_CR_IDMA2_SBLOCK     (0x15)
+#define CPM_CR_IDMA3_SBLOCK     (0x16)
+#define CPM_CR_IDMA4_SBLOCK     (0x17)
+#define CPM_CR_MCC1_SBLOCK      (0x1c)
+
+#define CPM_CR_FCC_SBLOCK(x)    (x + 0x10)
+
+#define CPM_CR_SCC1_PAGE        (0x00)
+#define CPM_CR_SCC2_PAGE        (0x01)
+#define CPM_CR_SCC3_PAGE        (0x02)
+#define CPM_CR_SCC4_PAGE        (0x03)
+#define CPM_CR_SMC1_PAGE        (0x07)
+#define CPM_CR_SMC2_PAGE        (0x08)
+#define CPM_CR_SPI_PAGE         (0x09)
+#define CPM_CR_I2C_PAGE         (0x0a)
+#define CPM_CR_TIMER_PAGE       (0x0a)
+#define CPM_CR_RAND_PAGE        (0x0a)
+#define CPM_CR_FCC1_PAGE        (0x04)
+#define CPM_CR_FCC2_PAGE        (0x05)
+#define CPM_CR_FCC3_PAGE        (0x06)
+#define CPM_CR_IDMA1_PAGE       (0x07)
+#define CPM_CR_IDMA2_PAGE       (0x08)
+#define CPM_CR_IDMA3_PAGE       (0x09)
+#define CPM_CR_IDMA4_PAGE       (0x0a)
+#define CPM_CR_MCC1_PAGE        (0x07)
+#define CPM_CR_MCC2_PAGE        (0x08)
+
+#define CPM_CR_FCC_PAGE(x)      (x + 0x04)
+
+/* CPM2-specific opcodes (see cpm.h for common opcodes)
+*/
+#define CPM_CR_START_IDMA       ((ushort)0x0009)
+
+#define mk_cr_cmd(PG, SBC, MCN, OP) \
+        ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+
+/* The number of pages of host memory we allocate for CPM.  This is
+ * done early in kernel initialization to get physically contiguous
+ * pages.
+ */
+#define NUM_CPM_HOST_PAGES      2
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
+
+#define cpm_dpalloc cpm_muram_alloc
+#define cpm_dpfree cpm_muram_free
+#define cpm_dpram_addr cpm_muram_addr
+
+extern void cpm2_reset(void);
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST             ((uint)0x00020000)
+#define CPM_BRG_EN              ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK3_9     ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK5_15    ((uint)0x00008000)
+#define CPM_BRG_ATB             ((uint)0x00002000)
+#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
+#define CPM_BRG_DIV16           ((uint)0x00000001)
+
+#define CPM2_BRG_INT_CLK        (get_brgfreq())
+#define CPM2_BRG_UART_CLK       (CPM2_BRG_INT_CLK/16)
+
+extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
+
+/* This function is used by UARTS, or anything else that uses a 16x
+ * oversampled clock.
+ */
+static inline void cpm_setbrg(uint brg, uint rate)
+{
+        __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
+}
+
+/* This function is used to set high speed synchronous baud rate
+ * clocks.
+ */
+static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
+{
+        __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
+}
+
+/* Function code bits, usually generic to devices.
+*/
+#define CPMFCR_GBL      ((u_char)0x20)  /* Set memory snooping */
+#define CPMFCR_EB       ((u_char)0x10)  /* Set big endian byte order */
+#define CPMFCR_TC2      ((u_char)0x04)  /* Transfer code 2 value */
+#define CPMFCR_DTB      ((u_char)0x02)  /* Use local bus for data when set */
+#define CPMFCR_BDB      ((u_char)0x01)  /* Use local bus for BD when set */
+
+/* Parameter RAM offsets from the base.
+*/
+#define PROFF_SCC1              ((uint)0x8000)
+#define PROFF_SCC2              ((uint)0x8100)
+#define PROFF_SCC3              ((uint)0x8200)
+#define PROFF_SCC4              ((uint)0x8300)
+#define PROFF_FCC1              ((uint)0x8400)
+#define PROFF_FCC2              ((uint)0x8500)
+#define PROFF_FCC3              ((uint)0x8600)
+#define PROFF_MCC1              ((uint)0x8700)
+#define PROFF_SMC1_BASE         ((uint)0x87fc)
+#define PROFF_IDMA1_BASE        ((uint)0x87fe)
+#define PROFF_MCC2              ((uint)0x8800)
+#define PROFF_SMC2_BASE         ((uint)0x88fc)
+#define PROFF_IDMA2_BASE        ((uint)0x88fe)
+#define PROFF_SPI_BASE          ((uint)0x89fc)
+#define PROFF_IDMA3_BASE        ((uint)0x89fe)
+#define PROFF_TIMERS            ((uint)0x8ae0)
+#define PROFF_REVNUM            ((uint)0x8af0)
+#define PROFF_RAND              ((uint)0x8af8)
+#define PROFF_I2C_BASE          ((uint)0x8afc)
+#define PROFF_IDMA4_BASE        ((uint)0x8afe)
+
+#define PROFF_SCC_SIZE          ((uint)0x100)
+#define PROFF_FCC_SIZE          ((uint)0x100)
+#define PROFF_SMC_SIZE          ((uint)64)
+
+/* The SMCs are relocated to any of the first eight DPRAM pages.
+ * We will fix these at the first locations of DPRAM, until we
+ * get some microcode patches :-).
+ * The parameter ram space for the SMCs is fifty-some bytes, and
+ * they are required to start on a 64 byte boundary.
+ */
+#define PROFF_SMC1      (0)
+#define PROFF_SMC2      (64)
+
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  smc_rfcr;       /* Rx function code */
+        u_char  smc_tfcr;       /* Tx function code */
+        ushort  smc_mrblr;      /* Max receive buffer length */
+        uint    smc_rstate;     /* Internal */
+        uint    smc_idp;        /* Internal */
+        ushort  smc_rbptr;      /* Internal */
+        ushort  smc_ibc;        /* Internal */
+        uint    smc_rxtmp;      /* Internal */
+        uint    smc_tstate;     /* Internal */
+        uint    smc_tdp;        /* Internal */
+        ushort  smc_tbptr;      /* Internal */
+        ushort  smc_tbc;        /* Internal */
+        uint    smc_txtmp;      /* Internal */
+        ushort  smc_maxidl;     /* Maximum idle characters */
+        ushort  smc_tmpidl;     /* Temporary idle counter */
+        ushort  smc_brklen;     /* Last received break length */
+        ushort  smc_brkec;      /* rcv'd break condition counter */
+        ushort  smc_brkcr;      /* xmt break count register */
+        ushort  smc_rmask;      /* Temporary bit mask */
+        uint    smc_stmp;       /* SDMA Temp */
+} smc_uart_t;
+
+/* SMC uart mode register (Internal memory map).
+*/
+#define SMCMR_REN       ((ushort)0x0001)
+#define SMCMR_TEN       ((ushort)0x0002)
+#define SMCMR_DM        ((ushort)0x000c)
+#define SMCMR_SM_GCI    ((ushort)0x0000)
+#define SMCMR_SM_UART   ((ushort)0x0020)
+#define SMCMR_SM_TRANS  ((ushort)0x0030)
+#define SMCMR_SM_MASK   ((ushort)0x0030)
+#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
+#define SMCMR_REVD      SMCMR_PM_EVEN
+#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
+#define SMCMR_BS        SMCMR_PEN
+#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
+#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
+#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC Event and Mask register.
+*/
+#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
+#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
+#define SMCM_TXE        ((unsigned char)0x10)
+#define SMCM_BSY        ((unsigned char)0x04)
+#define SMCM_TX         ((unsigned char)0x02)
+#define SMCM_RX         ((unsigned char)0x01)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP           ((uint)0x00040000)
+#define SCC_GSMRH_GDE           ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
+#define SCC_GSMRH_REVD          ((uint)0x00002000)
+#define SCC_GSMRH_TRX           ((uint)0x00001000)
+#define SCC_GSMRH_TTX           ((uint)0x00000800)
+#define SCC_GSMRH_CDP           ((uint)0x00000400)
+#define SCC_GSMRH_CTSP          ((uint)0x00000200)
+#define SCC_GSMRH_CDS           ((uint)0x00000100)
+#define SCC_GSMRH_CTSS          ((uint)0x00000080)
+#define SCC_GSMRH_TFL           ((uint)0x00000040)
+#define SCC_GSMRH_RFW           ((uint)0x00000020)
+#define SCC_GSMRH_TXSY          ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
+#define SCC_GSMRH_RTSM          ((uint)0x00000002)
+#define SCC_GSMRH_RSYN          ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
+#define SCC_GSMRL_TCI           ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
+#define SCC_GSMRL_RINV          ((uint)0x02000000)
+#define SCC_GSMRL_TINV          ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
+#define SCC_GSMRL_TEND          ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
+#define SCC_GSMRL_ENR           ((uint)0x00000020)
+#define SCC_GSMRL_ENT           ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
+
+#define SCC_TODR_TOD            ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE        ((unsigned char)0x10)
+#define SCCM_BSY        ((unsigned char)0x04)
+#define SCCM_TX         ((unsigned char)0x02)
+#define SCCM_RX         ((unsigned char)0x01)
+
+typedef struct scc_param {
+        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  scc_rfcr;       /* Rx function code */
+        u_char  scc_tfcr;       /* Tx function code */
+        ushort  scc_mrblr;      /* Max receive buffer length */
+        uint    scc_rstate;     /* Internal */
+        uint    scc_idp;        /* Internal */
+        ushort  scc_rbptr;      /* Internal */
+        ushort  scc_ibc;        /* Internal */
+        uint    scc_rxtmp;      /* Internal */
+        uint    scc_tstate;     /* Internal */
+        uint    scc_tdp;        /* Internal */
+        ushort  scc_tbptr;      /* Internal */
+        ushort  scc_tbc;        /* Internal */
+        uint    scc_txtmp;      /* Internal */
+        uint    scc_rcrc;       /* Internal */
+        uint    scc_tcrc;       /* Internal */
+} sccp_t;
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+        sccp_t  sen_genscc;
+        uint    sen_cpres;      /* Preset CRC */
+        uint    sen_cmask;      /* Constant mask for CRC */
+        uint    sen_crcec;      /* CRC Error counter */
+        uint    sen_alec;       /* alignment error counter */
+        uint    sen_disfc;      /* discard frame counter */
+        ushort  sen_pads;       /* Tx short frame pad character */
+        ushort  sen_retlim;     /* Retry limit threshold */
+        ushort  sen_retcnt;     /* Retry limit counter */
+        ushort  sen_maxflr;     /* maximum frame length register */
+        ushort  sen_minflr;     /* minimum frame length register */
+        ushort  sen_maxd1;      /* maximum DMA1 length */
+        ushort  sen_maxd2;      /* maximum DMA2 length */
+        ushort  sen_maxd;       /* Rx max DMA */
+        ushort  sen_dmacnt;     /* Rx DMA counter */
+        ushort  sen_maxb;       /* Max BD byte count */
+        ushort  sen_gaddr1;     /* Group address filter */
+        ushort  sen_gaddr2;
+        ushort  sen_gaddr3;
+        ushort  sen_gaddr4;
+        uint    sen_tbuf0data0; /* Save area 0 - current frame */
+        uint    sen_tbuf0data1; /* Save area 1 - current frame */
+        uint    sen_tbuf0rba;   /* Internal */
+        uint    sen_tbuf0crc;   /* Internal */
+        ushort  sen_tbuf0bcnt;  /* Internal */
+        ushort  sen_paddrh;     /* physical address (MSB) */
+        ushort  sen_paddrm;
+        ushort  sen_paddrl;     /* physical address (LSB) */
+        ushort  sen_pper;       /* persistence */
+        ushort  sen_rfbdptr;    /* Rx first BD pointer */
+        ushort  sen_tfbdptr;    /* Tx first BD pointer */
+        ushort  sen_tlbdptr;    /* Tx last BD pointer */
+        uint    sen_tbuf1data0; /* Save area 0 - current frame */
+        uint    sen_tbuf1data1; /* Save area 1 - current frame */
+        uint    sen_tbuf1rba;   /* Internal */
+        uint    sen_tbuf1crc;   /* Internal */
+        ushort  sen_tbuf1bcnt;  /* Internal */
+        ushort  sen_txlen;      /* Tx Frame length counter */
+        ushort  sen_iaddr1;     /* Individual address filter */
+        ushort  sen_iaddr2;
+        ushort  sen_iaddr3;
+        ushort  sen_iaddr4;
+        ushort  sen_boffcnt;    /* Backoff counter */
+
+        /* NOTE: Some versions of the manual have the following items
+         * incorrectly documented.  Below is the proper order.
+         */
+        ushort  sen_taddrh;     /* temp address (MSB) */
+        ushort  sen_taddrm;
+        ushort  sen_taddrl;     /* temp address (LSB) */
+} scc_enet_t;
+
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
+#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
+#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
+#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
+#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
+#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
+#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
+#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
+#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
+#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
+#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
+#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
+#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
+#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
+#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
+#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
+#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
+#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+        sccp_t  scc_genscc;
+        uint    scc_res1;       /* Reserved */
+        uint    scc_res2;       /* Reserved */
+        ushort  scc_maxidl;     /* Maximum idle chars */
+        ushort  scc_idlc;       /* temp idle counter */
+        ushort  scc_brkcr;      /* Break count register */
+        ushort  scc_parec;      /* receive parity error counter */
+        ushort  scc_frmec;      /* receive framing error counter */
+        ushort  scc_nosec;      /* receive noise counter */
+        ushort  scc_brkec;      /* receive break condition counter */
+        ushort  scc_brkln;      /* last received break length */
+        ushort  scc_uaddr1;     /* UART address character 1 */
+        ushort  scc_uaddr2;     /* UART address character 2 */
+        ushort  scc_rtemp;      /* Temp storage */
+        ushort  scc_toseq;      /* Transmit out of sequence char */
+        ushort  scc_char1;      /* control character 1 */
+        ushort  scc_char2;      /* control character 2 */
+        ushort  scc_char3;      /* control character 3 */
+        ushort  scc_char4;      /* control character 4 */
+        ushort  scc_char5;      /* control character 5 */
+        ushort  scc_char6;      /* control character 6 */
+        ushort  scc_char7;      /* control character 7 */
+        ushort  scc_char8;      /* control character 8 */
+        ushort  scc_rccm;       /* receive control character mask */
+        ushort  scc_rccr;       /* receive control character register */
+        ushort  scc_rlbc;       /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR           ((ushort)0x1000)
+#define UART_SCCM_GLT           ((ushort)0x0800)
+#define UART_SCCM_AB            ((ushort)0x0200)
+#define UART_SCCM_IDL           ((ushort)0x0100)
+#define UART_SCCM_GRA           ((ushort)0x0080)
+#define UART_SCCM_BRKE          ((ushort)0x0040)
+#define UART_SCCM_BRKS          ((ushort)0x0020)
+#define UART_SCCM_CCR           ((ushort)0x0008)
+#define UART_SCCM_BSY           ((ushort)0x0004)
+#define UART_SCCM_TX            ((ushort)0x0002)
+#define UART_SCCM_RX            ((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC            ((ushort)0x8000)
+#define SCU_PSMR_SL             ((ushort)0x4000)
+#define SCU_PSMR_CL             ((ushort)0x3000)
+#define SCU_PSMR_UM             ((ushort)0x0c00)
+#define SCU_PSMR_FRZ            ((ushort)0x0200)
+#define SCU_PSMR_RZS            ((ushort)0x0100)
+#define SCU_PSMR_SYN            ((ushort)0x0080)
+#define SCU_PSMR_DRT            ((ushort)0x0040)
+#define SCU_PSMR_PEN            ((ushort)0x0010)
+#define SCU_PSMR_RPM            ((ushort)0x000c)
+#define SCU_PSMR_REVP           ((ushort)0x0008)
+#define SCU_PSMR_TPM            ((ushort)0x0003)
+#define SCU_PSMR_TEVP           ((ushort)0x0002)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+        sccp_t  st_genscc;
+        uint    st_cpres;       /* Preset CRC */
+        uint    st_cmask;       /* Constant mask for CRC */
+} scc_trans_t;
+
+/* How about some FCCs.....
+*/
+#define FCC_GFMR_DIAG_NORM      ((uint)0x00000000)
+#define FCC_GFMR_DIAG_LE        ((uint)0x40000000)
+#define FCC_GFMR_DIAG_AE        ((uint)0x80000000)
+#define FCC_GFMR_DIAG_ALE       ((uint)0xc0000000)
+#define FCC_GFMR_TCI            ((uint)0x20000000)
+#define FCC_GFMR_TRX            ((uint)0x10000000)
+#define FCC_GFMR_TTX            ((uint)0x08000000)
+#define FCC_GFMR_TTX            ((uint)0x08000000)
+#define FCC_GFMR_CDP            ((uint)0x04000000)
+#define FCC_GFMR_CTSP           ((uint)0x02000000)
+#define FCC_GFMR_CDS            ((uint)0x01000000)
+#define FCC_GFMR_CTSS           ((uint)0x00800000)
+#define FCC_GFMR_SYNL_NONE      ((uint)0x00000000)
+#define FCC_GFMR_SYNL_AUTO      ((uint)0x00004000)
+#define FCC_GFMR_SYNL_8         ((uint)0x00008000)
+#define FCC_GFMR_SYNL_16        ((uint)0x0000c000)
+#define FCC_GFMR_RTSM           ((uint)0x00002000)
+#define FCC_GFMR_RENC_NRZ       ((uint)0x00000000)
+#define FCC_GFMR_RENC_NRZI      ((uint)0x00000800)
+#define FCC_GFMR_REVD           ((uint)0x00000400)
+#define FCC_GFMR_TENC_NRZ       ((uint)0x00000000)
+#define FCC_GFMR_TENC_NRZI      ((uint)0x00000100)
+#define FCC_GFMR_TCRC_16        ((uint)0x00000000)
+#define FCC_GFMR_TCRC_32        ((uint)0x00000080)
+#define FCC_GFMR_ENR            ((uint)0x00000020)
+#define FCC_GFMR_ENT            ((uint)0x00000010)
+#define FCC_GFMR_MODE_ENET      ((uint)0x0000000c)
+#define FCC_GFMR_MODE_ATM       ((uint)0x0000000a)
+#define FCC_GFMR_MODE_HDLC      ((uint)0x00000000)
+
+/* Generic FCC parameter ram.
+*/
+typedef struct fcc_param {
+        ushort  fcc_riptr;      /* Rx Internal temp pointer */
+        ushort  fcc_tiptr;      /* Tx Internal temp pointer */
+        ushort  fcc_res1;
+        ushort  fcc_mrblr;      /* Max receive buffer length, mod 32 bytes */
+        uint    fcc_rstate;     /* Upper byte is Func code, must be set */
+        uint    fcc_rbase;      /* Receive BD base */
+        ushort  fcc_rbdstat;    /* RxBD status */
+        ushort  fcc_rbdlen;     /* RxBD down counter */
+        uint    fcc_rdptr;      /* RxBD internal data pointer */
+        uint    fcc_tstate;     /* Upper byte is Func code, must be set */
+        uint    fcc_tbase;      /* Transmit BD base */
+        ushort  fcc_tbdstat;    /* TxBD status */
+        ushort  fcc_tbdlen;     /* TxBD down counter */
+        uint    fcc_tdptr;      /* TxBD internal data pointer */
+        uint    fcc_rbptr;      /* Rx BD Internal buf pointer */
+        uint    fcc_tbptr;      /* Tx BD Internal buf pointer */
+        uint    fcc_rcrc;       /* Rx temp CRC */
+        uint    fcc_res2;
+        uint    fcc_tcrc;       /* Tx temp CRC */
+} fccp_t;
+
+
+/* Ethernet controller through FCC.
+*/
+typedef struct fcc_enet {
+        fccp_t  fen_genfcc;
+        uint    fen_statbuf;    /* Internal status buffer */
+        uint    fen_camptr;     /* CAM address */
+        uint    fen_cmask;      /* Constant mask for CRC */
+        uint    fen_cpres;      /* Preset CRC */
+        uint    fen_crcec;      /* CRC Error counter */
+        uint    fen_alec;       /* alignment error counter */
+        uint    fen_disfc;      /* discard frame counter */
+        ushort  fen_retlim;     /* Retry limit */
+        ushort  fen_retcnt;     /* Retry counter */
+        ushort  fen_pper;       /* Persistence */
+        ushort  fen_boffcnt;    /* backoff counter */
+        uint    fen_gaddrh;     /* Group address filter, high 32-bits */
+        uint    fen_gaddrl;     /* Group address filter, low 32-bits */
+        ushort  fen_tfcstat;    /* out of sequence TxBD */
+        ushort  fen_tfclen;
+        uint    fen_tfcptr;
+        ushort  fen_mflr;       /* Maximum frame length (1518) */
+        ushort  fen_paddrh;     /* MAC address */
+        ushort  fen_paddrm;
+        ushort  fen_paddrl;
+        ushort  fen_ibdcount;   /* Internal BD counter */
+        ushort  fen_ibdstart;   /* Internal BD start pointer */
+        ushort  fen_ibdend;     /* Internal BD end pointer */
+        ushort  fen_txlen;      /* Internal Tx frame length counter */
+        uint    fen_ibdbase[8]; /* Internal use */
+        uint    fen_iaddrh;     /* Individual address filter */
+        uint    fen_iaddrl;
+        ushort  fen_minflr;     /* Minimum frame length (64) */
+        ushort  fen_taddrh;     /* Filter transfer MAC address */
+        ushort  fen_taddrm;
+        ushort  fen_taddrl;
+        ushort  fen_padptr;     /* Pointer to pad byte buffer */
+        ushort  fen_cftype;     /* control frame type */
+        ushort  fen_cfrange;    /* control frame range */
+        ushort  fen_maxb;       /* maximum BD count */
+        ushort  fen_maxd1;      /* Max DMA1 length (1520) */
+        ushort  fen_maxd2;      /* Max DMA2 length (1520) */
+        ushort  fen_maxd;       /* internal max DMA count */
+        ushort  fen_dmacnt;     /* internal DMA counter */
+        uint    fen_octc;       /* Total octect counter */
+        uint    fen_colc;       /* Total collision counter */
+        uint    fen_broc;       /* Total broadcast packet counter */
+        uint    fen_mulc;       /* Total multicast packet count */
+        uint    fen_uspc;       /* Total packets < 64 bytes */
+        uint    fen_frgc;       /* Total packets < 64 bytes with errors */
+        uint    fen_ospc;       /* Total packets > 1518 */
+        uint    fen_jbrc;       /* Total packets > 1518 with errors */
+        uint    fen_p64c;       /* Total packets == 64 bytes */
+        uint    fen_p65c;       /* Total packets 64 < bytes <= 127 */
+        uint    fen_p128c;      /* Total packets 127 < bytes <= 255 */
+        uint    fen_p256c;      /* Total packets 256 < bytes <= 511 */
+        uint    fen_p512c;      /* Total packets 512 < bytes <= 1023 */
+        uint    fen_p1024c;     /* Total packets 1024 < bytes <= 1518 */
+        uint    fen_cambuf;     /* Internal CAM buffer poiner */
+        ushort  fen_rfthr;      /* Received frames threshold */
+        ushort  fen_rfcnt;      /* Received frames count */
+} fcc_enet_t;
+
+/* FCC Event/Mask register as used by Ethernet.
+*/
+#define FCC_ENET_GRA    ((ushort)0x0080)        /* Graceful stop complete */
+#define FCC_ENET_RXC    ((ushort)0x0040)        /* Control Frame Received */
+#define FCC_ENET_TXC    ((ushort)0x0020)        /* Out of seq. Tx sent */
+#define FCC_ENET_TXE    ((ushort)0x0010)        /* Transmit Error */
+#define FCC_ENET_RXF    ((ushort)0x0008)        /* Full frame received */
+#define FCC_ENET_BSY    ((ushort)0x0004)        /* Busy.  Rx Frame dropped */
+#define FCC_ENET_TXB    ((ushort)0x0002)        /* A buffer was transmitted */
+#define FCC_ENET_RXB    ((ushort)0x0001)        /* A buffer was received */
+
+/* FCC Mode Register (FPSMR) as used by Ethernet.
+*/
+#define FCC_PSMR_HBC    ((uint)0x80000000)      /* Enable heartbeat */
+#define FCC_PSMR_FC     ((uint)0x40000000)      /* Force Collision */
+#define FCC_PSMR_SBT    ((uint)0x20000000)      /* Stop backoff timer */
+#define FCC_PSMR_LPB    ((uint)0x10000000)      /* Local protect. 1 = FDX */
+#define FCC_PSMR_LCW    ((uint)0x08000000)      /* Late collision select */
+#define FCC_PSMR_FDE    ((uint)0x04000000)      /* Full Duplex Enable */
+#define FCC_PSMR_MON    ((uint)0x02000000)      /* RMON Enable */
+#define FCC_PSMR_PRO    ((uint)0x00400000)      /* Promiscuous Enable */
+#define FCC_PSMR_FCE    ((uint)0x00200000)      /* Flow Control Enable */
+#define FCC_PSMR_RSH    ((uint)0x00100000)      /* Receive Short Frames */
+#define FCC_PSMR_CAM    ((uint)0x00000400)      /* CAM enable */
+#define FCC_PSMR_BRO    ((uint)0x00000200)      /* Broadcast pkt discard */
+#define FCC_PSMR_ENCRC  ((uint)0x00000080)      /* Use 32-bit CRC */
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
+        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
+        u_char  iic_rfcr;       /* Rx function code */
+        u_char  iic_tfcr;       /* Tx function code */
+        ushort  iic_mrblr;      /* Max receive buffer length */
+        uint    iic_rstate;     /* Internal */
+        uint    iic_rdp;        /* Internal */
+        ushort  iic_rbptr;      /* Internal */
+        ushort  iic_rbc;        /* Internal */
+        uint    iic_rxtmp;      /* Internal */
+        uint    iic_tstate;     /* Internal */
+        uint    iic_tdp;        /* Internal */
+        ushort  iic_tbptr;      /* Internal */
+        ushort  iic_tbc;        /* Internal */
+        uint    iic_txtmp;      /* Internal */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
+        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
+        u_char  spi_rfcr;       /* Rx function code */
+        u_char  spi_tfcr;       /* Tx function code */
+        ushort  spi_mrblr;      /* Max receive buffer length */
+        uint    spi_rstate;     /* Internal */
+        uint    spi_rdp;        /* Internal */
+        ushort  spi_rbptr;      /* Internal */
+        ushort  spi_rbc;        /* Internal */
+        uint    spi_rxtmp;      /* Internal */
+        uint    spi_tstate;     /* Internal */
+        uint    spi_tdp;        /* Internal */
+        ushort  spi_tbptr;      /* Internal */
+        ushort  spi_tbc;        /* Internal */
+        uint    spi_txtmp;      /* Internal */
+        uint    spi_res;        /* Tx temp. */
+        uint    spi_res1[4];    /* SDMA temp. */
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
+#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
+#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
+#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
+#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
+#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
+#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
+#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
+#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
+
+#define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)    ((x) &0xF)
+
+#define SPI_EB          ((u_char)0x10)          /* big endian byte order */
+
+/* IDMA parameter RAM
+*/
+typedef struct idma {
+        ushort ibase;           /* IDMA buffer descriptor table base address */
+        ushort dcm;             /* DMA channel mode */
+        ushort ibdptr;          /* IDMA current buffer descriptor pointer */
+        ushort dpr_buf;         /* IDMA transfer buffer base address */
+        ushort buf_inv;         /* internal buffer inventory */
+        ushort ss_max;          /* steady-state maximum transfer size */
+        ushort dpr_in_ptr;      /* write pointer inside the internal buffer */
+        ushort sts;             /* source transfer size */
+        ushort dpr_out_ptr;     /* read pointer inside the internal buffer */
+        ushort seob;            /* source end of burst */
+        ushort deob;            /* destination end of burst */
+        ushort dts;             /* destination transfer size */
+        ushort ret_add;         /* return address when working in ERM=1 mode */
+        ushort res0;            /* reserved */
+        uint   bd_cnt;          /* internal byte count */
+        uint   s_ptr;           /* source internal data pointer */
+        uint   d_ptr;           /* destination internal data pointer */
+        uint   istate;          /* internal state */
+        u_char res1[20];        /* pad to 64-byte length */
+} idma_t;
+
+/* DMA channel mode bit fields
+*/
+#define IDMA_DCM_FB             ((ushort)0x8000) /* fly-by mode */
+#define IDMA_DCM_LP             ((ushort)0x4000) /* low priority */
+#define IDMA_DCM_TC2            ((ushort)0x0400) /* value driven on TC[2] */
+#define IDMA_DCM_DMA_WRAP_MASK  ((ushort)0x01c0) /* mask for DMA wrap */
+#define IDMA_DCM_DMA_WRAP_64    ((ushort)0x0000) /* 64-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_128   ((ushort)0x0040) /* 128-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_256   ((ushort)0x0080) /* 256-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_512   ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_1024  ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_2048  ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
+#define IDMA_DCM_SINC           ((ushort)0x0020) /* source inc addr */
+#define IDMA_DCM_DINC           ((ushort)0x0010) /* destination inc addr */
+#define IDMA_DCM_ERM            ((ushort)0x0008) /* external request mode */
+#define IDMA_DCM_DT             ((ushort)0x0004) /* DONE treatment */
+#define IDMA_DCM_SD_MASK        ((ushort)0x0003) /* mask for SD bit field */
+#define IDMA_DCM_SD_MEM2MEM     ((ushort)0x0000) /* memory-to-memory xfer */
+#define IDMA_DCM_SD_PER2MEM     ((ushort)0x0002) /* peripheral-to-memory xfer */
+#define IDMA_DCM_SD_MEM2PER     ((ushort)0x0001) /* memory-to-peripheral xfer */
+
+/* IDMA Buffer Descriptors
+*/
+typedef struct idma_bd {
+        uint flags;
+        uint len;       /* data length */
+        uint src;       /* source data buffer pointer */
+        uint dst;       /* destination data buffer pointer */
+} idma_bd_t;
+
+/* IDMA buffer descriptor flag bit fields
+*/
+#define IDMA_BD_V       ((uint)0x80000000)      /* valid */
+#define IDMA_BD_W       ((uint)0x20000000)      /* wrap */
+#define IDMA_BD_I       ((uint)0x10000000)      /* interrupt */
+#define IDMA_BD_L       ((uint)0x08000000)      /* last */
+#define IDMA_BD_CM      ((uint)0x02000000)      /* continuous mode */
+#define IDMA_BD_SDN     ((uint)0x00400000)      /* source done */
+#define IDMA_BD_DDN     ((uint)0x00200000)      /* destination done */
+#define IDMA_BD_DGBL    ((uint)0x00100000)      /* destination global */
+#define IDMA_BD_DBO_LE  ((uint)0x00040000)      /* little-end dest byte order */
+#define IDMA_BD_DBO_BE  ((uint)0x00080000)      /* big-end dest byte order */
+#define IDMA_BD_DDTB    ((uint)0x00010000)      /* destination data bus */
+#define IDMA_BD_SGBL    ((uint)0x00002000)      /* source global */
+#define IDMA_BD_SBO_LE  ((uint)0x00000800)      /* little-end src byte order */
+#define IDMA_BD_SBO_BE  ((uint)0x00001000)      /* big-end src byte order */
+#define IDMA_BD_SDTB    ((uint)0x00000200)      /* source data bus */
+
+/* per-channel IDMA registers
+*/
+typedef struct im_idma {
+        u_char idsr;                    /* IDMAn event status register */
+        u_char res0[3];
+        u_char idmr;                    /* IDMAn event mask register */
+        u_char res1[3];
+} im_idma_t;
+
+/* IDMA event register bit fields
+*/
+#define IDMA_EVENT_SC   ((unsigned char)0x08)   /* stop completed */
+#define IDMA_EVENT_OB   ((unsigned char)0x04)   /* out of buffers */
+#define IDMA_EVENT_EDN  ((unsigned char)0x02)   /* external DONE asserted */
+#define IDMA_EVENT_BC   ((unsigned char)0x01)   /* buffer descriptor complete */
+
+/* RISC Controller Configuration Register (RCCR) bit fields
+*/
+#define RCCR_TIME       ((uint)0x80000000) /* timer enable */
+#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
+#define RCCR_DR0M       ((uint)0x00800000) /* IDMA0 request mode */
+#define RCCR_DR1M       ((uint)0x00400000) /* IDMA1 request mode */
+#define RCCR_DR2M       ((uint)0x00000080) /* IDMA2 request mode */
+#define RCCR_DR3M       ((uint)0x00000040) /* IDMA3 request mode */
+#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
+#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
+#define RCCR_DR0QP_MED  ((uint)0x00100000) /* IDMA0 has medium req priority */
+#define RCCR_DR0QP_LOW  ((uint)0x00200000) /* IDMA0 has low req priority */
+#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
+#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
+#define RCCR_DR1QP_MED  ((uint)0x00010000) /* IDMA1 has medium req priority */
+#define RCCR_DR1QP_LOW  ((uint)0x00020000) /* IDMA1 has low req priority */
+#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
+#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
+#define RCCR_DR2QP_MED  ((uint)0x00000010) /* IDMA2 has medium req priority */
+#define RCCR_DR2QP_LOW  ((uint)0x00000020) /* IDMA2 has low req priority */
+#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
+#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
+#define RCCR_DR3QP_MED  ((uint)0x00000001) /* IDMA3 has medium req priority */
+#define RCCR_DR3QP_LOW  ((uint)0x00000002) /* IDMA3 has low req priority */
+#define RCCR_EIE        ((uint)0x00080000) /* external interrupt enable */
+#define RCCR_SCD        ((uint)0x00040000) /* scheduler configuration */
+#define RCCR_ERAM_MASK  ((uint)0x0000e000) /* mask for enable RAM microcode */
+#define RCCR_ERAM_0KB   ((uint)0x00000000) /* use 0KB of dpram for microcode */
+#define RCCR_ERAM_2KB   ((uint)0x00002000) /* use 2KB of dpram for microcode */
+#define RCCR_ERAM_4KB   ((uint)0x00004000) /* use 4KB of dpram for microcode */
+#define RCCR_ERAM_6KB   ((uint)0x00006000) /* use 6KB of dpram for microcode */
+#define RCCR_ERAM_8KB   ((uint)0x00008000) /* use 8KB of dpram for microcode */
+#define RCCR_ERAM_10KB  ((uint)0x0000a000) /* use 10KB of dpram for microcode */
+#define RCCR_ERAM_12KB  ((uint)0x0000c000) /* use 12KB of dpram for microcode */
+#define RCCR_EDM0       ((uint)0x00000800) /* DREQ0 edge detect mode */
+#define RCCR_EDM1       ((uint)0x00000400) /* DREQ1 edge detect mode */
+#define RCCR_EDM2       ((uint)0x00000200) /* DREQ2 edge detect mode */
+#define RCCR_EDM3       ((uint)0x00000100) /* DREQ3 edge detect mode */
+#define RCCR_DEM01      ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
+#define RCCR_DEM23      ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register
+ */
+#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
+#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
+#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
+#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register
+ */
+#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
+#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
+#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
+#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
+#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
+#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
+#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
+#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
+#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register                            4-31
+ */
+#define SIUMCR_BBD      0x80000000      /* Bus Busy Disable             */
+#define SIUMCR_ESE      0x40000000      /* External Snoop Enable        */
+#define SIUMCR_PBSE     0x20000000      /* Parity Byte Select Enable    */
+#define SIUMCR_CDIS     0x10000000      /* Core Disable                 */
+#define SIUMCR_DPPC00   0x00000000      /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01   0x04000000      /* - " -                        */
+#define SIUMCR_DPPC10   0x08000000      /* - " -                        */
+#define SIUMCR_DPPC11   0x0c000000      /* - " -                        */
+#define SIUMCR_L2CPC00  0x00000000      /* L2 Cache Pins Configuration  */
+#define SIUMCR_L2CPC01  0x01000000      /* - " -                        */
+#define SIUMCR_L2CPC10  0x02000000      /* - " -                        */
+#define SIUMCR_L2CPC11  0x03000000      /* - " -                        */
+#define SIUMCR_LBPC00   0x00000000      /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01   0x00400000      /* - " -                        */
+#define SIUMCR_LBPC10   0x00800000      /* - " -                        */
+#define SIUMCR_LBPC11   0x00c00000      /* - " -                        */
+#define SIUMCR_APPC00   0x00000000      /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01   0x00100000      /* - " -                        */
+#define SIUMCR_APPC10   0x00200000      /* - " -                        */
+#define SIUMCR_APPC11   0x00300000      /* - " -                        */
+#define SIUMCR_CS10PC00 0x00000000      /* CS10 Pin Configuration       */
+#define SIUMCR_CS10PC01 0x00040000      /* - " -                        */
+#define SIUMCR_CS10PC10 0x00080000      /* - " -                        */
+#define SIUMCR_CS10PC11 0x000c0000      /* - " -                        */
+#define SIUMCR_BCTLC00  0x00000000      /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01  0x00010000      /* - " -                        */
+#define SIUMCR_BCTLC10  0x00020000      /* - " -                        */
+#define SIUMCR_BCTLC11  0x00030000      /* - " -                        */
+#define SIUMCR_MMR00    0x00000000      /* Mask Masters Requests        */
+#define SIUMCR_MMR01    0x00004000      /* - " -                        */
+#define SIUMCR_MMR10    0x00008000      /* - " -                        */
+#define SIUMCR_MMR11    0x0000c000      /* - " -                        */
+#define SIUMCR_LPBSE    0x00002000      /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register                                  9-8
+*/
+#define SCCR_PCI_MODE   0x00000100      /* PCI Mode     */
+#define SCCR_PCI_MODCK  0x00000080      /* Value of PCI_MODCK pin       */
+#define SCCR_PCIDF_MSK  0x00000078      /* PCI division factor  */
+#define SCCR_PCIDF_SHIFT 3
+
+#ifndef CPM_IMMR_OFFSET
+#define CPM_IMMR_OFFSET 0x101a8
+#endif
+
+#define FCC_PSMR_RMII   ((uint)0x00020000)      /* Use RMII interface */
+
+/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
+ * in order to use clock-computing stuff below for the FCC x
+ */
+
+/* Automatically generates register configurations */
+#define PC_CLK(x)       ((uint)(1<<(x-1)))      /* FCC CLK I/O ports */
+
+#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27))     /* FCC1 Receive Clock Source */
+#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24))     /* FCC1 Transmit Clock Source */
+#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19))     /* FCC2 Receive Clock Source */
+#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))     /* FCC2 Transmit Clock Source */
+#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11))     /* FCC3 Receive Clock Source */
+#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))      /* FCC3 Transmit Clock Source */
+
+#define PC_F1RXCLK      PC_CLK(F1_RXCLK)
+#define PC_F1TXCLK      PC_CLK(F1_TXCLK)
+#define CMX1_CLK_ROUTE  (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
+#define CMX1_CLK_MASK   ((uint)0xff000000)
+
+#define PC_F2RXCLK      PC_CLK(F2_RXCLK)
+#define PC_F2TXCLK      PC_CLK(F2_TXCLK)
+#define CMX2_CLK_ROUTE  (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
+#define CMX2_CLK_MASK   ((uint)0x00ff0000)
+
+#define PC_F3RXCLK      PC_CLK(F3_RXCLK)
+#define PC_F3TXCLK      PC_CLK(F3_TXCLK)
+#define CMX3_CLK_ROUTE  (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
+#define CMX3_CLK_MASK   ((uint)0x0000ff00)
+
+#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
+#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
+
+#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
+
+/* I/O Pin assignment for FCC1.  I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PA1_COL         0x00000001U
+#define PA1_CRS         0x00000002U
+#define PA1_TXER        0x00000004U
+#define PA1_TXEN        0x00000008U
+#define PA1_RXDV        0x00000010U
+#define PA1_RXER        0x00000020U
+#define PA1_TXDAT       0x00003c00U
+#define PA1_RXDAT       0x0003c000U
+#define PA1_PSORA0      (PA1_RXDAT | PA1_TXDAT)
+#define PA1_PSORA1      (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
+                PA1_RXDV | PA1_RXER)
+#define PA1_DIRA0       (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
+#define PA1_DIRA1       (PA1_TXDAT | PA1_TXEN | PA1_TXER)
+
+
+/* I/O Pin assignment for FCC2.  I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PB2_TXER        0x00000001U
+#define PB2_RXDV        0x00000002U
+#define PB2_TXEN        0x00000004U
+#define PB2_RXER        0x00000008U
+#define PB2_COL         0x00000010U
+#define PB2_CRS         0x00000020U
+#define PB2_TXDAT       0x000003c0U
+#define PB2_RXDAT       0x00003c00U
+#define PB2_PSORB0      (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
+                PB2_RXER | PB2_RXDV | PB2_TXER)
+#define PB2_PSORB1      (PB2_TXEN)
+#define PB2_DIRB0       (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
+#define PB2_DIRB1       (PB2_TXDAT | PB2_TXEN | PB2_TXER)
+
+
+/* I/O Pin assignment for FCC3.  I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PB3_RXDV        0x00004000U
+#define PB3_RXER        0x00008000U
+#define PB3_TXER        0x00010000U
+#define PB3_TXEN        0x00020000U
+#define PB3_COL         0x00040000U
+#define PB3_CRS         0x00080000U
+#define PB3_TXDAT       0x0f000000U
+#define PC3_TXDAT       0x00000010U
+#define PB3_RXDAT       0x00f00000U
+#define PB3_PSORB0      (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
+                PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
+#define PB3_PSORB1      0
+#define PB3_DIRB0       (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
+#define PB3_DIRB1       (PB3_TXDAT | PB3_TXEN | PB3_TXER)
+#define PC3_DIRC1       (PC3_TXDAT)
+
+/* Handy macro to specify mem for FCCs*/
+#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
+#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
+#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
+#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
+
+/* Clocks and GRG's */
+
+enum cpm_clk_dir {
+        CPM_CLK_RX,
+        CPM_CLK_TX,
+        CPM_CLK_RTX
+};
+
+enum cpm_clk_target {
+        CPM_CLK_SCC1,
+        CPM_CLK_SCC2,
+        CPM_CLK_SCC3,
+        CPM_CLK_SCC4,
+        CPM_CLK_FCC1,
+        CPM_CLK_FCC2,
+        CPM_CLK_FCC3,
+        CPM_CLK_SMC1,
+        CPM_CLK_SMC2,
+};
+
+enum cpm_clk {
+        CPM_CLK_NONE = 0,
+        CPM_BRG1,       /* Baud Rate Generator  1 */
+        CPM_BRG2,       /* Baud Rate Generator  2 */
+        CPM_BRG3,       /* Baud Rate Generator  3 */
+        CPM_BRG4,       /* Baud Rate Generator  4 */
+        CPM_BRG5,       /* Baud Rate Generator  5 */
+        CPM_BRG6,       /* Baud Rate Generator  6 */
+        CPM_BRG7,       /* Baud Rate Generator  7 */
+        CPM_BRG8,       /* Baud Rate Generator  8 */
+        CPM_CLK1,       /* Clock  1 */
+        CPM_CLK2,       /* Clock  2 */
+        CPM_CLK3,       /* Clock  3 */
+        CPM_CLK4,       /* Clock  4 */
+        CPM_CLK5,       /* Clock  5 */
+        CPM_CLK6,       /* Clock  6 */
+        CPM_CLK7,       /* Clock  7 */
+        CPM_CLK8,       /* Clock  8 */
+        CPM_CLK9,       /* Clock  9 */
+        CPM_CLK10,      /* Clock 10 */
+        CPM_CLK11,      /* Clock 11 */
+        CPM_CLK12,      /* Clock 12 */
+        CPM_CLK13,      /* Clock 13 */
+        CPM_CLK14,      /* Clock 14 */
+        CPM_CLK15,      /* Clock 15 */
+        CPM_CLK16,      /* Clock 16 */
+        CPM_CLK17,      /* Clock 17 */
+        CPM_CLK18,      /* Clock 18 */
+        CPM_CLK19,      /* Clock 19 */
+        CPM_CLK20,      /* Clock 20 */
+        CPM_CLK_DUMMY
+};
+
+extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
+extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
+
+#define CPM_PIN_INPUT     0
+#define CPM_PIN_OUTPUT    1
+#define CPM_PIN_PRIMARY   0
+#define CPM_PIN_SECONDARY 2
+#define CPM_PIN_GPIO      4
+#define CPM_PIN_OPENDRAIN 8
+
+void cpm2_set_pin(int port, int pin, int flags);
+
+#endif /* __CPM2__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
new file mode 100644
index 000000000000..ef8a248dfd55
--- /dev/null
+++ b/arch/powerpc/include/asm/cputable.h
@@ -0,0 +1,514 @@
+#ifndef __ASM_POWERPC_CPUTABLE_H
+#define __ASM_POWERPC_CPUTABLE_H
+
+#define PPC_FEATURE_32                  0x80000000
+#define PPC_FEATURE_64                  0x40000000
+#define PPC_FEATURE_601_INSTR           0x20000000
+#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
+#define PPC_FEATURE_HAS_FPU             0x08000000
+#define PPC_FEATURE_HAS_MMU             0x04000000
+#define PPC_FEATURE_HAS_4xxMAC          0x02000000
+#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
+#define PPC_FEATURE_HAS_SPE             0x00800000
+#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
+#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
+#define PPC_FEATURE_NO_TB               0x00100000
+#define PPC_FEATURE_POWER4              0x00080000
+#define PPC_FEATURE_POWER5              0x00040000
+#define PPC_FEATURE_POWER5_PLUS         0x00020000
+#define PPC_FEATURE_CELL                0x00010000
+#define PPC_FEATURE_BOOKE               0x00008000
+#define PPC_FEATURE_SMT                 0x00004000
+#define PPC_FEATURE_ICACHE_SNOOP        0x00002000
+#define PPC_FEATURE_ARCH_2_05           0x00001000
+#define PPC_FEATURE_PA6T                0x00000800
+#define PPC_FEATURE_HAS_DFP             0x00000400
+#define PPC_FEATURE_POWER6_EXT          0x00000200
+#define PPC_FEATURE_ARCH_2_06           0x00000100
+#define PPC_FEATURE_HAS_VSX             0x00000080
+
+#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
+                                        0x00000040
+
+#define PPC_FEATURE_TRUE_LE             0x00000002
+#define PPC_FEATURE_PPC_LE              0x00000001
+
+#ifdef __KERNEL__
+
+#include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
+
+#ifndef __ASSEMBLY__
+
+/* This structure can grow, it's real size is used by head.S code
+ * via the mkdefs mechanism.
+ */
+struct cpu_spec;
+
+typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
+typedef void (*cpu_restore_t)(void);
+
+enum powerpc_oprofile_type {
+        PPC_OPROFILE_INVALID = 0,
+        PPC_OPROFILE_RS64 = 1,
+        PPC_OPROFILE_POWER4 = 2,
+        PPC_OPROFILE_G4 = 3,
+        PPC_OPROFILE_FSL_EMB = 4,
+        PPC_OPROFILE_CELL = 5,
+        PPC_OPROFILE_PA6T = 6,
+};
+
+enum powerpc_pmc_type {
+        PPC_PMC_DEFAULT = 0,
+        PPC_PMC_IBM = 1,
+        PPC_PMC_PA6T = 2,
+};
+
+struct pt_regs;
+
+extern int machine_check_generic(struct pt_regs *regs);
+extern int machine_check_4xx(struct pt_regs *regs);
+extern int machine_check_440A(struct pt_regs *regs);
+extern int machine_check_e500(struct pt_regs *regs);
+extern int machine_check_e200(struct pt_regs *regs);
+
+/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
+struct cpu_spec {
+        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
+        unsigned int    pvr_mask;
+        unsigned int    pvr_value;
+
+        char            *cpu_name;
+        unsigned long   cpu_features;           /* Kernel features */
+        unsigned int    cpu_user_features;      /* Userland features */
+
+        /* cache line sizes */
+        unsigned int    icache_bsize;
+        unsigned int    dcache_bsize;
+
+        /* number of performance monitor counters */
+        unsigned int    num_pmcs;
+        enum powerpc_pmc_type pmc_type;
+
+        /* this is called to initialize various CPU bits like L1 cache,
+         * BHT, SPD, etc... from head.S before branching to identify_machine
+         */
+        cpu_setup_t     cpu_setup;
+        /* Used to restore cpu setup on secondary processors and at resume */
+        cpu_restore_t   cpu_restore;
+
+        /* Used by oprofile userspace to select the right counters */
+        char            *oprofile_cpu_type;
+
+        /* Processor specific oprofile operations */
+        enum powerpc_oprofile_type oprofile_type;
+
+        /* Bit locations inside the mmcra change */
+        unsigned long   oprofile_mmcra_sihv;
+        unsigned long   oprofile_mmcra_sipr;
+
+        /* Bits to clear during an oprofile exception */
+        unsigned long   oprofile_mmcra_clear;
+
+        /* Name of processor class, for the ELF AT_PLATFORM entry */
+        char            *platform;
+
+        /* Processor specific machine check handling. Return negative
+         * if the error is fatal, 1 if it was fully recovered and 0 to
+         * pass up (not CPU originated) */
+        int             (*machine_check)(struct pt_regs *regs);
+};
+
+extern struct cpu_spec          *cur_cpu_spec;
+
+extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
+
+extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
+extern void do_feature_fixups(unsigned long value, void *fixup_start,
+                              void *fixup_end);
+
+extern const char *powerpc_base_platform;
+
+#endif /* __ASSEMBLY__ */
+
+/* CPU kernel features */
+
+/* Retain the 32b definitions all use bottom half of word */
+#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000000000000001)
+#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
+#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
+#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
+#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
+#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
+#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
+#define CPU_FTR_L2CSR                   ASM_CONST(0x0000000000000080)
+#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
+#define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
+#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
+#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
+#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
+#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
+#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
+#define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
+#define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
+#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
+#define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
+#define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
+#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
+#define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
+#define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
+#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
+#define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
+#define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
+#define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
+#define CPU_FTR_LWSYNC                  ASM_CONST(0x0000000008000000)
+
+/*
+ * Add the 64-bit processor unique features in the top half of the word;
+ * on 32-bit, make the names available but defined to be 0.
+ */
+#ifdef __powerpc64__
+#define LONG_ASM_CONST(x)               ASM_CONST(x)
+#else
+#define LONG_ASM_CONST(x)               0
+#endif
+
+#define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
+#define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
+#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
+#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
+#define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
+#define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
+#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
+#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
+#define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
+#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
+#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
+#define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
+#define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
+#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0010000000000000)
+#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0020000000000000)
+
+#ifndef __ASSEMBLY__
+
+#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
+                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
+                                 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
+
+/* We only set the altivec features if the kernel was compiled with altivec
+ * support
+ */
+#ifdef CONFIG_ALTIVEC
+#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
+#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
+#else
+#define CPU_FTR_ALTIVEC_COMP    0
+#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
+#endif
+
+/* We only set the VSX features if the kernel was compiled with VSX
+ * support
+ */
+#ifdef CONFIG_VSX
+#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
+#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
+#else
+#define CPU_FTR_VSX_COMP        0
+#define PPC_FEATURE_HAS_VSX_COMP    0
+#endif
+
+/* We only set the spe features if the kernel was compiled with spe
+ * support
+ */
+#ifdef CONFIG_SPE
+#define CPU_FTR_SPE_COMP        CPU_FTR_SPE
+#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
+#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
+#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
+#else
+#define CPU_FTR_SPE_COMP        0
+#define PPC_FEATURE_HAS_SPE_COMP    0
+#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
+#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
+#endif
+
+/* We need to mark all pages as being coherent if we're SMP or we have a
+ * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
+ * require it for PCI "streaming/prefetch" to work properly.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
+        || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
+#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
+#else
+#define CPU_FTR_COMMON                  0
+#endif
+
+/* The powersave features NAP & DOZE seems to confuse BDI when
+   debugging. So if a BDI is used, disable theses
+ */
+#ifndef CONFIG_BDI_SWITCH
+#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
+#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
+#else
+#define CPU_FTR_MAYBE_CAN_DOZE  0
+#define CPU_FTR_MAYBE_CAN_NAP   0
+#endif
+
+#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
+                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
+                     !defined(CONFIG_BOOKE))
+
+#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
+        CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
+#define CPU_FTRS_603    (CPU_FTR_COMMON | \
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
+#define CPU_FTRS_604    (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
+#define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
+#define CPU_FTRS_740    (CPU_FTR_COMMON | \
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
+            CPU_FTR_PPC_LE)
+#define CPU_FTRS_750    (CPU_FTR_COMMON | \
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
+            CPU_FTR_PPC_LE)
+#define CPU_FTRS_750CL  (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
+#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
+#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
+#define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
+                CPU_FTR_HAS_HIGH_BATS)
+#define CPU_FTRS_750GX  (CPU_FTRS_750FX)
+#define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
+#define CPU_FTRS_7400   (CPU_FTR_COMMON | \
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
+#define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
+#define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
+#define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
+            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+#define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
+#define CPU_FTRS_7455   (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
+#define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
+            CPU_FTR_NEED_PAIRED_STWCX)
+#define CPU_FTRS_7447   (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
+#define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
+#define CPU_FTRS_7448   (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
+#define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
+            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
+#define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
+#define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_COMMON)
+#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
+            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
+#define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | \
+            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
+#define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
+#define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
+            CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
+            CPU_FTR_UNIFIED_ID_CACHE)
+#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
+            CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
+            CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
+#define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
+
+/* 64-bit CPUs */
+#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
+#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
+            CPU_FTR_MMCRA | CPU_FTR_CTRL)
+#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_MMCRA)
+#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
+#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_MMCRA | CPU_FTR_SMT | \
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+            CPU_FTR_PURR)
+#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_MMCRA | CPU_FTR_SMT | \
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
+            CPU_FTR_DSCR)
+#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_MMCRA | CPU_FTR_SMT | \
+            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
+            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
+            CPU_FTR_DSCR | CPU_FTR_SAO)
+#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
+            CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
+#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
+            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
+            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
+#define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
+
+#ifdef __powerpc64__
+#define CPU_FTRS_POSSIBLE       \
+            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
+            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
+            CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
+            CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
+#else
+enum {
+        CPU_FTRS_POSSIBLE =
+#if CLASSIC_PPC
+            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
+            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
+            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
+            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
+            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
+            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
+            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
+            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
+            CPU_FTRS_CLASSIC32 |
+#else
+            CPU_FTRS_GENERIC_32 |
+#endif
+#ifdef CONFIG_8xx
+            CPU_FTRS_8XX |
+#endif
+#ifdef CONFIG_40x
+            CPU_FTRS_40X |
+#endif
+#ifdef CONFIG_44x
+            CPU_FTRS_44X |
+#endif
+#ifdef CONFIG_E200
+            CPU_FTRS_E200 |
+#endif
+#ifdef CONFIG_E500
+            CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
+#endif
+            0,
+};
+#endif /* __powerpc64__ */
+
+#ifdef __powerpc64__
+#define CPU_FTRS_ALWAYS         \
+            (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
+            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
+            CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
+#else
+enum {
+        CPU_FTRS_ALWAYS =
+#if CLASSIC_PPC
+            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
+            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
+            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
+            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
+            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
+            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
+            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
+            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
+            CPU_FTRS_CLASSIC32 &
+#else
+            CPU_FTRS_GENERIC_32 &
+#endif
+#ifdef CONFIG_8xx
+            CPU_FTRS_8XX &
+#endif
+#ifdef CONFIG_40x
+            CPU_FTRS_40X &
+#endif
+#ifdef CONFIG_44x
+            CPU_FTRS_44X &
+#endif
+#ifdef CONFIG_E200
+            CPU_FTRS_E200 &
+#endif
+#ifdef CONFIG_E500
+            CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
+#endif
+            CPU_FTRS_POSSIBLE,
+};
+#endif /* __powerpc64__ */
+
+static inline int cpu_has_feature(unsigned long feature)
+{
+        return (CPU_FTRS_ALWAYS & feature) ||
+               (CPU_FTRS_POSSIBLE
+                & cur_cpu_spec->cpu_features
+                & feature);
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
new file mode 100644
index 000000000000..fb11b0c459b8
--- /dev/null
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -0,0 +1,71 @@
+#ifndef _ASM_POWERPC_CPUTHREADS_H
+#define _ASM_POWERPC_CPUTHREADS_H
+
+#include <linux/cpumask.h>
+
+/*
+ * Mapping of threads to cores
+ */
+
+#ifdef CONFIG_SMP
+extern int threads_per_core;
+extern int threads_shift;
+extern cpumask_t threads_core_mask;
+#else
+#define threads_per_core        1
+#define threads_shift           0
+#define threads_core_mask       (CPU_MASK_CPU0)
+#endif
+
+/* cpu_thread_mask_to_cores - Return a cpumask of one per cores
+ *                            hit by the argument
+ *
+ * @threads:    a cpumask of threads
+ *
+ * This function returns a cpumask which will have one "cpu" (or thread)
+ * bit set for each core that has at least one thread set in the argument.
+ *
+ * This can typically be used for things like IPI for tlb invalidations
+ * since those need to be done only once per core/TLB
+ */
+static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
+{
+        cpumask_t       tmp, res;
+        int             i;
+
+        res = CPU_MASK_NONE;
+        for (i = 0; i < NR_CPUS; i += threads_per_core) {
+                cpus_shift_left(tmp, threads_core_mask, i);
+                if (cpus_intersects(threads, tmp))
+                        cpu_set(i, res);
+        }
+        return res;
+}
+
+static inline int cpu_nr_cores(void)
+{
+        return NR_CPUS >> threads_shift;
+}
+
+static inline cpumask_t cpu_online_cores_map(void)
+{
+        return cpu_thread_mask_to_cores(cpu_online_map);
+}
+
+static inline int cpu_thread_to_core(int cpu)
+{
+        return cpu >> threads_shift;
+}
+
+static inline int cpu_thread_in_core(int cpu)
+{
+        return cpu & (threads_per_core - 1);
+}
+
+static inline int cpu_first_thread_in_core(int cpu)
+{
+        return cpu & ~(threads_per_core - 1);
+}
+
+#endif /* _ASM_POWERPC_CPUTHREADS_H */
+
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
new file mode 100644
index 000000000000..f42e623030ee
--- /dev/null
+++ b/arch/powerpc/include/asm/cputime.h
@@ -0,0 +1,235 @@
+/*
+ * Definitions for measuring cputime on powerpc machines.
+ *
+ * Copyright (C) 2006 Paul Mackerras, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in
+ * the same units as the timebase.  Otherwise we measure cpu time
+ * in jiffies using the generic definitions.
+ */
+
+#ifndef __POWERPC_CPUTIME_H
+#define __POWERPC_CPUTIME_H
+
+#ifndef CONFIG_VIRT_CPU_ACCOUNTING
+#include <asm-generic/cputime.h>
+#else
+
+#include <linux/types.h>
+#include <linux/time.h>
+#include <asm/div64.h>
+#include <asm/time.h>
+#include <asm/param.h>
+
+typedef u64 cputime_t;
+typedef u64 cputime64_t;
+
+#define cputime_zero                    ((cputime_t)0)
+#define cputime_max                     ((~((cputime_t)0) >> 1) - 1)
+#define cputime_add(__a, __b)           ((__a) +  (__b))
+#define cputime_sub(__a, __b)           ((__a) -  (__b))
+#define cputime_div(__a, __n)           ((__a) /  (__n))
+#define cputime_halve(__a)              ((__a) >> 1)
+#define cputime_eq(__a, __b)            ((__a) == (__b))
+#define cputime_gt(__a, __b)            ((__a) >  (__b))
+#define cputime_ge(__a, __b)            ((__a) >= (__b))
+#define cputime_lt(__a, __b)            ((__a) <  (__b))
+#define cputime_le(__a, __b)            ((__a) <= (__b))
+
+#define cputime64_zero                  ((cputime64_t)0)
+#define cputime64_add(__a, __b)         ((__a) + (__b))
+#define cputime64_sub(__a, __b)         ((__a) - (__b))
+#define cputime_to_cputime64(__ct)      (__ct)
+
+#ifdef __KERNEL__
+
+/*
+ * Convert cputime <-> jiffies
+ */
+extern u64 __cputime_jiffies_factor;
+DECLARE_PER_CPU(unsigned long, cputime_last_delta);
+DECLARE_PER_CPU(unsigned long, cputime_scaled_last_delta);
+
+static inline unsigned long cputime_to_jiffies(const cputime_t ct)
+{
+        return mulhdu(ct, __cputime_jiffies_factor);
+}
+
+/* Estimate the scaled cputime by scaling the real cputime based on
+ * the last scaled to real ratio */
+static inline cputime_t cputime_to_scaled(const cputime_t ct)
+{
+        if (cpu_has_feature(CPU_FTR_SPURR) &&
+            per_cpu(cputime_last_delta, smp_processor_id()))
+                return ct *
+                        per_cpu(cputime_scaled_last_delta, smp_processor_id())/
+                        per_cpu(cputime_last_delta, smp_processor_id());
+        return ct;
+}
+
+static inline cputime_t jiffies_to_cputime(const unsigned long jif)
+{
+        cputime_t ct;
+        unsigned long sec;
+
+        /* have to be a little careful about overflow */
+        ct = jif % HZ;
+        sec = jif / HZ;
+        if (ct) {
+                ct *= tb_ticks_per_sec;
+                do_div(ct, HZ);
+        }
+        if (sec)
+                ct += (cputime_t) sec * tb_ticks_per_sec;
+        return ct;
+}
+
+static inline cputime64_t jiffies64_to_cputime64(const u64 jif)
+{
+        cputime_t ct;
+        u64 sec;
+
+        /* have to be a little careful about overflow */
+        ct = jif % HZ;
+        sec = jif / HZ;
+        if (ct) {
+                ct *= tb_ticks_per_sec;
+                do_div(ct, HZ);
+        }
+        if (sec)
+                ct += (cputime_t) sec * tb_ticks_per_sec;
+        return ct;
+}
+
+static inline u64 cputime64_to_jiffies64(const cputime_t ct)
+{
+        return mulhdu(ct, __cputime_jiffies_factor);
+}
+
+/*
+ * Convert cputime <-> milliseconds
+ */
+extern u64 __cputime_msec_factor;
+
+static inline unsigned long cputime_to_msecs(const cputime_t ct)
+{
+        return mulhdu(ct, __cputime_msec_factor);
+}
+
+static inline cputime_t msecs_to_cputime(const unsigned long ms)
+{
+        cputime_t ct;
+        unsigned long sec;
+
+        /* have to be a little careful about overflow */
+        ct = ms % 1000;
+        sec = ms / 1000;
+        if (ct) {
+                ct *= tb_ticks_per_sec;
+                do_div(ct, 1000);
+        }
+        if (sec)
+                ct += (cputime_t) sec * tb_ticks_per_sec;
+        return ct;
+}
+
+/*
+ * Convert cputime <-> seconds
+ */
+extern u64 __cputime_sec_factor;
+
+static inline unsigned long cputime_to_secs(const cputime_t ct)
+{
+        return mulhdu(ct, __cputime_sec_factor);
+}
+
+static inline cputime_t secs_to_cputime(const unsigned long sec)
+{
+        return (cputime_t) sec * tb_ticks_per_sec;
+}
+
+/*
+ * Convert cputime <-> timespec
+ */
+static inline void cputime_to_timespec(const cputime_t ct, struct timespec *p)
+{
+        u64 x = ct;
+        unsigned int frac;
+
+        frac = do_div(x, tb_ticks_per_sec);
+        p->tv_sec = x;
+        x = (u64) frac * 1000000000;
+        do_div(x, tb_ticks_per_sec);
+        p->tv_nsec = x;
+}
+
+static inline cputime_t timespec_to_cputime(const struct timespec *p)
+{
+        cputime_t ct;
+
+        ct = (u64) p->tv_nsec * tb_ticks_per_sec;
+        do_div(ct, 1000000000);
+        return ct + (u64) p->tv_sec * tb_ticks_per_sec;
+}
+
+/*
+ * Convert cputime <-> timeval
+ */
+static inline void cputime_to_timeval(const cputime_t ct, struct timeval *p)
+{
+        u64 x = ct;
+        unsigned int frac;
+
+        frac = do_div(x, tb_ticks_per_sec);
+        p->tv_sec = x;
+        x = (u64) frac * 1000000;
+        do_div(x, tb_ticks_per_sec);
+        p->tv_usec = x;
+}
+
+static inline cputime_t timeval_to_cputime(const struct timeval *p)
+{
+        cputime_t ct;
+
+        ct = (u64) p->tv_usec * tb_ticks_per_sec;
+        do_div(ct, 1000000);
+        return ct + (u64) p->tv_sec * tb_ticks_per_sec;
+}
+
+/*
+ * Convert cputime <-> clock_t (units of 1/USER_HZ seconds)
+ */
+extern u64 __cputime_clockt_factor;
+
+static inline unsigned long cputime_to_clock_t(const cputime_t ct)
+{
+        return mulhdu(ct, __cputime_clockt_factor);
+}
+
+static inline cputime_t clock_t_to_cputime(const unsigned long clk)
+{
+        cputime_t ct;
+        unsigned long sec;
+
+        /* have to be a little careful about overflow */
+        ct = clk % USER_HZ;
+        sec = clk / USER_HZ;
+        if (ct) {
+                ct *= tb_ticks_per_sec;
+                do_div(ct, USER_HZ);
+        }
+        if (sec)
+                ct += (cputime_t) sec * tb_ticks_per_sec;
+        return ct;
+}
+
+#define cputime64_to_clock_t(ct)        cputime_to_clock_t((cputime_t)(ct))
+
+#endif /* __KERNEL__ */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* __POWERPC_CPUTIME_H */
diff --git a/arch/powerpc/include/asm/current.h b/arch/powerpc/include/asm/current.h
new file mode 100644
index 000000000000..e2c7f06931e7
--- /dev/null
+++ b/arch/powerpc/include/asm/current.h
@@ -0,0 +1,40 @@
+#ifndef _ASM_POWERPC_CURRENT_H
+#define _ASM_POWERPC_CURRENT_H
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+struct task_struct;
+
+#ifdef __powerpc64__
+#include <linux/stddef.h>
+#include <asm/paca.h>
+
+static inline struct task_struct *get_current(void)
+{
+        struct task_struct *task;
+
+        __asm__ __volatile__("ld %0,%1(13)"
+        : "=r" (task)
+        : "i" (offsetof(struct paca_struct, __current)));
+
+        return task;
+}
+#define current get_current()
+
+#else
+
+/*
+ * We keep `current' in r2 for speed.
+ */
+register struct task_struct *current asm ("r2");
+
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_CURRENT_H */
diff --git a/arch/powerpc/include/asm/dbdma.h b/arch/powerpc/include/asm/dbdma.h
new file mode 100644
index 000000000000..e23f07e73cb3
--- /dev/null
+++ b/arch/powerpc/include/asm/dbdma.h
@@ -0,0 +1,108 @@
+/*
+ * Definitions for using the Apple Descriptor-Based DMA controller
+ * in Power Macintosh computers.
+ *
+ * Copyright (C) 1996 Paul Mackerras.
+ */
+
+#ifdef __KERNEL__
+#ifndef _ASM_DBDMA_H_
+#define _ASM_DBDMA_H_
+/*
+ * DBDMA control/status registers.  All little-endian.
+ */
+struct dbdma_regs {
+    unsigned int control;       /* lets you change bits in status */
+    unsigned int status;        /* DMA and device status bits (see below) */
+    unsigned int cmdptr_hi;     /* upper 32 bits of command address */
+    unsigned int cmdptr;        /* (lower 32 bits of) command address (phys) */
+    unsigned int intr_sel;      /* select interrupt condition bit */
+    unsigned int br_sel;        /* select branch condition bit */
+    unsigned int wait_sel;      /* select wait condition bit */
+    unsigned int xfer_mode;
+    unsigned int data2ptr_hi;
+    unsigned int data2ptr;
+    unsigned int res1;
+    unsigned int address_hi;
+    unsigned int br_addr_hi;
+    unsigned int res2[3];
+};
+
+/* Bits in control and status registers */
+#define RUN     0x8000
+#define PAUSE   0x4000
+#define FLUSH   0x2000
+#define WAKE    0x1000
+#define DEAD    0x0800
+#define ACTIVE  0x0400
+#define BT      0x0100
+#define DEVSTAT 0x00ff
+
+/*
+ * DBDMA command structure.  These fields are all little-endian!
+ */
+struct dbdma_cmd {
+    unsigned short req_count;   /* requested byte transfer count */
+    unsigned short command;     /* command word (has bit-fields) */
+    unsigned int   phy_addr;    /* physical data address */
+    unsigned int   cmd_dep;     /* command-dependent field */
+    unsigned short res_count;   /* residual count after completion */
+    unsigned short xfer_status; /* transfer status */
+};
+
+/* DBDMA command values in command field */
+#define OUTPUT_MORE     0       /* transfer memory data to stream */
+#define OUTPUT_LAST     0x1000  /* ditto followed by end marker */
+#define INPUT_MORE      0x2000  /* transfer stream data to memory */
+#define INPUT_LAST      0x3000  /* ditto, expect end marker */
+#define STORE_WORD      0x4000  /* write word (4 bytes) to device reg */
+#define LOAD_WORD       0x5000  /* read word (4 bytes) from device reg */
+#define DBDMA_NOP       0x6000  /* do nothing */
+#define DBDMA_STOP      0x7000  /* suspend processing */
+
+/* Key values in command field */
+#define KEY_STREAM0     0       /* usual data stream */
+#define KEY_STREAM1     0x100   /* control/status stream */
+#define KEY_STREAM2     0x200   /* device-dependent stream */
+#define KEY_STREAM3     0x300   /* device-dependent stream */
+#define KEY_REGS        0x500   /* device register space */
+#define KEY_SYSTEM      0x600   /* system memory-mapped space */
+#define KEY_DEVICE      0x700   /* device memory-mapped space */
+
+/* Interrupt control values in command field */
+#define INTR_NEVER      0       /* don't interrupt */
+#define INTR_IFSET      0x10    /* intr if condition bit is 1 */
+#define INTR_IFCLR      0x20    /* intr if condition bit is 0 */
+#define INTR_ALWAYS     0x30    /* always interrupt */
+
+/* Branch control values in command field */
+#define BR_NEVER        0       /* don't branch */
+#define BR_IFSET        0x4     /* branch if condition bit is 1 */
+#define BR_IFCLR        0x8     /* branch if condition bit is 0 */
+#define BR_ALWAYS       0xc     /* always branch */
+
+/* Wait control values in command field */
+#define WAIT_NEVER      0       /* don't wait */
+#define WAIT_IFSET      1       /* wait if condition bit is 1 */
+#define WAIT_IFCLR      2       /* wait if condition bit is 0 */
+#define WAIT_ALWAYS     3       /* always wait */
+
+/* Align an address for a DBDMA command structure */
+#define DBDMA_ALIGN(x)  (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
+                         & -sizeof(struct dbdma_cmd))
+
+/* Useful macros */
+#define DBDMA_DO_STOP(regs) do {                                \
+        out_le32(&((regs)->control), (RUN|FLUSH)<<16);          \
+        while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH))      \
+                ; \
+} while(0)
+
+#define DBDMA_DO_RESET(regs) do {                               \
+        out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
+        while(in_le32(&((regs)->status)) & (RUN)) \
+                ; \
+} while(0)
+
+#endif /* _ASM_DBDMA_H_ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/dcr-generic.h b/arch/powerpc/include/asm/dcr-generic.h
new file mode 100644
index 000000000000..35b71599ec46
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-generic.h
@@ -0,0 +1,49 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_DCR_GENERIC_H
+#define _ASM_POWERPC_DCR_GENERIC_H
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID};
+
+typedef struct {
+        enum host_type_t type;
+        union {
+                dcr_host_mmio_t mmio;
+                dcr_host_native_t native;
+        } host;
+} dcr_host_t;
+
+extern bool dcr_map_ok_generic(dcr_host_t host);
+
+extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n,
+                          unsigned int dcr_c);
+extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
+
+extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
+
+extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_GENERIC_H */
+
+
diff --git a/arch/powerpc/include/asm/dcr-mmio.h b/arch/powerpc/include/asm/dcr-mmio.h
new file mode 100644
index 000000000000..acd491dbd45a
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-mmio.h
@@ -0,0 +1,61 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_DCR_MMIO_H
+#define _ASM_POWERPC_DCR_MMIO_H
+#ifdef __KERNEL__
+
+#include <asm/io.h>
+
+typedef struct {
+        void __iomem *token;
+        unsigned int stride;
+        unsigned int base;
+} dcr_host_mmio_t;
+
+static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
+{
+        return host.token != NULL;
+}
+
+extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
+                                    unsigned int dcr_n,
+                                    unsigned int dcr_c);
+extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c);
+
+static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n)
+{
+        return in_be32(host.token + ((host.base + dcr_n) * host.stride));
+}
+
+static inline void dcr_write_mmio(dcr_host_mmio_t host,
+                                  unsigned int dcr_n,
+                                  u32 value)
+{
+        out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
+}
+
+extern u64 of_translate_dcr_address(struct device_node *dev,
+                                    unsigned int dcr_n,
+                                    unsigned int *stride);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_MMIO_H */
+
+
diff --git a/arch/powerpc/include/asm/dcr-native.h b/arch/powerpc/include/asm/dcr-native.h
new file mode 100644
index 000000000000..72d2b72c7390
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-native.h
@@ -0,0 +1,116 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_DCR_NATIVE_H
+#define _ASM_POWERPC_DCR_NATIVE_H
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+#include <linux/spinlock.h>
+
+typedef struct {
+        unsigned int base;
+} dcr_host_native_t;
+
+static inline bool dcr_map_ok_native(dcr_host_native_t host)
+{
+        return 1;
+}
+
+#define dcr_map_native(dev, dcr_n, dcr_c) \
+        ((dcr_host_native_t){ .base = (dcr_n) })
+#define dcr_unmap_native(host, dcr_c)           do {} while (0)
+#define dcr_read_native(host, dcr_n)            mfdcr(dcr_n + host.base)
+#define dcr_write_native(host, dcr_n, value)    mtdcr(dcr_n + host.base, value)
+
+/* Device Control Registers */
+void __mtdcr(int reg, unsigned int val);
+unsigned int __mfdcr(int reg);
+#define mfdcr(rn)                                               \
+        ({unsigned int rval;                                    \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mfdcr %0," __stringify(rn)        \
+                              : "=r" (rval));                   \
+        else                                                    \
+                rval = __mfdcr(rn);                             \
+        rval;})
+
+#define mtdcr(rn, v)                                            \
+do {                                                            \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mtdcr " __stringify(rn) ",%0"     \
+                              : : "r" (v));                     \
+        else                                                    \
+                __mtdcr(rn, v);                                 \
+} while (0)
+
+/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
+extern spinlock_t dcr_ind_lock;
+
+static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
+{
+        unsigned long flags;
+        unsigned int val;
+
+        spin_lock_irqsave(&dcr_ind_lock, flags);
+        __mtdcr(base_addr, reg);
+        val = __mfdcr(base_data);
+        spin_unlock_irqrestore(&dcr_ind_lock, flags);
+        return val;
+}
+
+static inline void __mtdcri(int base_addr, int base_data, int reg,
+                            unsigned val)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&dcr_ind_lock, flags);
+        __mtdcr(base_addr, reg);
+        __mtdcr(base_data, val);
+        spin_unlock_irqrestore(&dcr_ind_lock, flags);
+}
+
+static inline void __dcri_clrset(int base_addr, int base_data, int reg,
+                                 unsigned clr, unsigned set)
+{
+        unsigned long flags;
+        unsigned int val;
+
+        spin_lock_irqsave(&dcr_ind_lock, flags);
+        __mtdcr(base_addr, reg);
+        val = (__mfdcr(base_data) & ~clr) | set;
+        __mtdcr(base_data, val);
+        spin_unlock_irqrestore(&dcr_ind_lock, flags);
+}
+
+#define mfdcri(base, reg)       __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
+                                         DCRN_ ## base ## _CONFIG_DATA, \
+                                         reg)
+
+#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
+                                         DCRN_ ## base ## _CONFIG_DATA, \
+                                         reg, data)
+
+#define dcri_clrset(base, reg, clr, set)        __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR,    \
+                                                              DCRN_ ## base ## _CONFIG_DATA,    \
+                                                              reg, clr, set)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_NATIVE_H */
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
new file mode 100644
index 000000000000..29b0ecef980a
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -0,0 +1,149 @@
+/*
+ * Common DCR / SDR / CPR register definitions used on various IBM/AMCC
+ * 4xx processors
+ *
+ *    Copyright 2007 Benjamin Herrenschmidt, IBM Corp
+ *                   <benh@kernel.crashing.org>
+ *
+ * Mostly lifted from asm-ppc/ibm4xx.h by
+ *
+ *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ *
+ */
+
+#ifndef __DCR_REGS_H__
+#define __DCR_REGS_H__
+
+/*
+ * Most DCRs used for controlling devices such as the MAL, DMA engine,
+ * etc... are obtained for the device tree.
+ *
+ * The definitions in this files are fixed DCRs and indirect DCRs that
+ * are commonly used outside of specific drivers or refer to core
+ * common registers that may occasionally have to be tweaked outside
+ * of the driver main register set
+ */
+
+/* CPRs (440GX and 440SP/440SPe) */
+#define DCRN_CPR0_CONFIG_ADDR   0xc
+#define DCRN_CPR0_CONFIG_DATA   0xd
+
+/* SDRs (440GX and 440SP/440SPe) */
+#define DCRN_SDR0_CONFIG_ADDR   0xe
+#define DCRN_SDR0_CONFIG_DATA   0xf
+
+#define SDR0_PFC0               0x4100
+#define SDR0_PFC1               0x4101
+#define SDR0_PFC1_EPS           0x1c00000
+#define SDR0_PFC1_EPS_SHIFT     22
+#define SDR0_PFC1_RMII          0x02000000
+#define SDR0_MFR                0x4300
+#define SDR0_MFR_TAH0           0x80000000      /* TAHOE0 Enable */
+#define SDR0_MFR_TAH1           0x40000000      /* TAHOE1 Enable */
+#define SDR0_MFR_PCM            0x10000000      /* PPC440GP irq compat mode */
+#define SDR0_MFR_ECS            0x08000000      /* EMAC int clk */
+#define SDR0_MFR_T0TXFL         0x00080000
+#define SDR0_MFR_T0TXFH         0x00040000
+#define SDR0_MFR_T1TXFL         0x00020000
+#define SDR0_MFR_T1TXFH         0x00010000
+#define SDR0_MFR_E0TXFL         0x00008000
+#define SDR0_MFR_E0TXFH         0x00004000
+#define SDR0_MFR_E0RXFL         0x00002000
+#define SDR0_MFR_E0RXFH         0x00001000
+#define SDR0_MFR_E1TXFL         0x00000800
+#define SDR0_MFR_E1TXFH         0x00000400
+#define SDR0_MFR_E1RXFL         0x00000200
+#define SDR0_MFR_E1RXFH         0x00000100
+#define SDR0_MFR_E2TXFL         0x00000080
+#define SDR0_MFR_E2TXFH         0x00000040
+#define SDR0_MFR_E2RXFL         0x00000020
+#define SDR0_MFR_E2RXFH         0x00000010
+#define SDR0_MFR_E3TXFL         0x00000008
+#define SDR0_MFR_E3TXFH         0x00000004
+#define SDR0_MFR_E3RXFL         0x00000002
+#define SDR0_MFR_E3RXFH         0x00000001
+#define SDR0_UART0              0x0120
+#define SDR0_UART1              0x0121
+#define SDR0_UART2              0x0122
+#define SDR0_UART3              0x0123
+#define SDR0_CUST0              0x4000
+
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_SRAM0_SB0CR        0x00
+#define DCRN_SRAM0_SB1CR        0x01
+#define DCRN_SRAM0_SB2CR        0x02
+#define DCRN_SRAM0_SB3CR        0x03
+#define  SRAM_SBCR_BU_MASK      0x00000180
+#define  SRAM_SBCR_BS_64KB      0x00000800
+#define  SRAM_SBCR_BU_RO        0x00000080
+#define  SRAM_SBCR_BU_RW        0x00000180
+#define DCRN_SRAM0_BEAR         0x04
+#define DCRN_SRAM0_BESR0        0x05
+#define DCRN_SRAM0_BESR1        0x06
+#define DCRN_SRAM0_PMEG         0x07
+#define DCRN_SRAM0_CID          0x08
+#define DCRN_SRAM0_REVID        0x09
+#define DCRN_SRAM0_DPC          0x0a
+#define  SRAM_DPC_ENABLE        0x80000000
+
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_L2C0_CFG           0x00
+#define  L2C_CFG_L2M            0x80000000
+#define  L2C_CFG_ICU            0x40000000
+#define  L2C_CFG_DCU            0x20000000
+#define  L2C_CFG_DCW_MASK       0x1e000000
+#define  L2C_CFG_TPC            0x01000000
+#define  L2C_CFG_CPC            0x00800000
+#define  L2C_CFG_FRAN           0x00200000
+#define  L2C_CFG_SS_MASK        0x00180000
+#define  L2C_CFG_SS_256         0x00000000
+#define  L2C_CFG_CPIM           0x00040000
+#define  L2C_CFG_TPIM           0x00020000
+#define  L2C_CFG_LIM            0x00010000
+#define  L2C_CFG_PMUX_MASK      0x00007000
+#define  L2C_CFG_PMUX_SNP       0x00000000
+#define  L2C_CFG_PMUX_IF        0x00001000
+#define  L2C_CFG_PMUX_DF        0x00002000
+#define  L2C_CFG_PMUX_DS        0x00003000
+#define  L2C_CFG_PMIM           0x00000800
+#define  L2C_CFG_TPEI           0x00000400
+#define  L2C_CFG_CPEI           0x00000200
+#define  L2C_CFG_NAM            0x00000100
+#define  L2C_CFG_SMCM           0x00000080
+#define  L2C_CFG_NBRM           0x00000040
+#define  L2C_CFG_RDBW           0x00000008      /* only 460EX/GT */
+#define DCRN_L2C0_CMD           0x01
+#define  L2C_CMD_CLR            0x80000000
+#define  L2C_CMD_DIAG           0x40000000
+#define  L2C_CMD_INV            0x20000000
+#define  L2C_CMD_CCP            0x10000000
+#define  L2C_CMD_CTE            0x08000000
+#define  L2C_CMD_STRC           0x04000000
+#define  L2C_CMD_STPC           0x02000000
+#define  L2C_CMD_RPMC           0x01000000
+#define  L2C_CMD_HCC            0x00800000
+#define DCRN_L2C0_ADDR          0x02
+#define DCRN_L2C0_DATA          0x03
+#define DCRN_L2C0_SR            0x04
+#define  L2C_SR_CC              0x80000000
+#define  L2C_SR_CPE             0x40000000
+#define  L2C_SR_TPE             0x20000000
+#define  L2C_SR_LRU             0x10000000
+#define  L2C_SR_PCS             0x08000000
+#define DCRN_L2C0_REVID         0x05
+#define DCRN_L2C0_SNP0          0x06
+#define DCRN_L2C0_SNP1          0x07
+#define  L2C_SNP_BA_MASK        0xffff0000
+#define  L2C_SNP_SSR_MASK       0x0000f000
+#define  L2C_SNP_SSR_32G        0x0000f000
+#define  L2C_SNP_ESR            0x00000800
+
+#endif /* __DCR_REGS_H__ */
diff --git a/arch/powerpc/include/asm/dcr.h b/arch/powerpc/include/asm/dcr.h
new file mode 100644
index 000000000000..d13fb68bb5c0
--- /dev/null
+++ b/arch/powerpc/include/asm/dcr.h
@@ -0,0 +1,78 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                    <benh@kernel.crashing.org>
+ *
+ *   This program is free software;  you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+ *   the GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program;  if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_DCR_H
+#define _ASM_POWERPC_DCR_H
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC_DCR
+
+#ifdef CONFIG_PPC_DCR_NATIVE
+#include <asm/dcr-native.h>
+#endif
+
+#ifdef CONFIG_PPC_DCR_MMIO
+#include <asm/dcr-mmio.h>
+#endif
+
+
+/* Indirection layer for providing both NATIVE and MMIO support. */
+
+#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
+
+#include <asm/dcr-generic.h>
+
+#define DCR_MAP_OK(host)        dcr_map_ok_generic(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
+
+#else
+
+#ifdef CONFIG_PPC_DCR_NATIVE
+typedef dcr_host_native_t dcr_host_t;
+#define DCR_MAP_OK(host)        dcr_map_ok_native(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
+#else
+typedef dcr_host_mmio_t dcr_host_t;
+#define DCR_MAP_OK(host)        dcr_map_ok_mmio(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
+#endif
+
+#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
+
+/*
+ * additional helpers to read the DCR * base from the device-tree
+ */
+struct device_node;
+extern unsigned int dcr_resource_start(struct device_node *np,
+                                       unsigned int index);
+extern unsigned int dcr_resource_len(struct device_node *np,
+                                     unsigned int index);
+#endif /* CONFIG_PPC_DCR */
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_H */
diff --git a/arch/powerpc/include/asm/delay.h b/arch/powerpc/include/asm/delay.h
new file mode 100644
index 000000000000..f9200a65c632
--- /dev/null
+++ b/arch/powerpc/include/asm/delay.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_POWERPC_DELAY_H
+#define _ASM_POWERPC_DELAY_H
+#ifdef __KERNEL__
+
+/*
+ * Copyright 1996, Paul Mackerras.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * PPC64 Support added by Dave Engebretsen, Todd Inglett, Mike Corrigan,
+ * Anton Blanchard.
+ */
+
+extern void __delay(unsigned long loops);
+extern void udelay(unsigned long usecs);
+
+/*
+ * On shared processor machines the generic implementation of mdelay can
+ * result in large errors. While each iteration of the loop inside mdelay
+ * is supposed to take 1ms, the hypervisor could sleep our partition for
+ * longer (eg 10ms). With the right timing these errors can add up.
+ *
+ * Since there is no 32bit overflow issue on 64bit kernels, just call
+ * udelay directly.
+ */
+#ifdef CONFIG_PPC64
+#define mdelay(n)       udelay((n) * 1000)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DELAY_H */
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
new file mode 100644
index 000000000000..228ab2a315b9
--- /dev/null
+++ b/arch/powerpc/include/asm/device.h
@@ -0,0 +1,24 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#ifndef _ASM_POWERPC_DEVICE_H
+#define _ASM_POWERPC_DEVICE_H
+
+struct dma_mapping_ops;
+struct device_node;
+
+struct dev_archdata {
+        /* Optional pointer to an OF device node */
+        struct device_node      *of_node;
+
+        /* DMA operations on that device */
+        struct dma_mapping_ops  *dma_ops;
+        void                    *dma_data;
+
+        /* NUMA node if applicable */
+        int                     numa_node;
+};
+
+#endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/arch/powerpc/include/asm/div64.h b/arch/powerpc/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/powerpc/include/asm/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..c7ca45f97dd2
--- /dev/null
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -0,0 +1,474 @@
+/*
+ * Copyright (C) 2004 IBM
+ *
+ * Implements the generic device dma API for powerpc.
+ * the pci and vio busses
+ */
+#ifndef _ASM_DMA_MAPPING_H
+#define _ASM_DMA_MAPPING_H
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <linux/cache.h>
+/* need struct page definitions */
+#include <linux/mm.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-attrs.h>
+#include <asm/io.h>
+
+#define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/*
+ * DMA-consistent mapping functions for PowerPCs that don't support
+ * cache snooping.  These allocate/free a region of uncached mapped
+ * memory space for use with DMA devices.  Alternatively, you could
+ * allocate the space "normally" and use the cache management functions
+ * to ensure it is consistent.
+ */
+extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
+extern void __dma_free_coherent(size_t size, void *vaddr);
+extern void __dma_sync(void *vaddr, size_t size, int direction);
+extern void __dma_sync_page(struct page *page, unsigned long offset,
+                                 size_t size, int direction);
+
+#else /* ! CONFIG_NOT_COHERENT_CACHE */
+/*
+ * Cache coherent cores.
+ */
+
+#define __dma_alloc_coherent(gfp, size, handle) NULL
+#define __dma_free_coherent(size, addr)         ((void)0)
+#define __dma_sync(addr, size, rw)              ((void)0)
+#define __dma_sync_page(pg, off, sz, rw)        ((void)0)
+
+#endif /* ! CONFIG_NOT_COHERENT_CACHE */
+
+#ifdef CONFIG_PPC64
+
+static inline unsigned long device_to_mask(struct device *dev)
+{
+        if (dev->dma_mask && *dev->dma_mask)
+                return *dev->dma_mask;
+        /* Assume devices without mask can take 32 bit addresses */
+        return 0xfffffffful;
+}
+
+/*
+ * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
+ */
+struct dma_mapping_ops {
+        void *          (*alloc_coherent)(struct device *dev, size_t size,
+                                dma_addr_t *dma_handle, gfp_t flag);
+        void            (*free_coherent)(struct device *dev, size_t size,
+                                void *vaddr, dma_addr_t dma_handle);
+        dma_addr_t      (*map_single)(struct device *dev, void *ptr,
+                                size_t size, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
+        void            (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
+                                size_t size, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
+        int             (*map_sg)(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
+        void            (*unmap_sg)(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction direction,
+                                struct dma_attrs *attrs);
+        int             (*dma_supported)(struct device *dev, u64 mask);
+        int             (*set_dma_mask)(struct device *dev, u64 dma_mask);
+};
+
+static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
+{
+        /* We don't handle the NULL dev case for ISA for now. We could
+         * do it via an out of line call but it is not needed for now. The
+         * only ISA DMA device we support is the floppy and we have a hack
+         * in the floppy driver directly to get a device for us.
+         */
+        if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL))
+                return NULL;
+        return dev->archdata.dma_ops;
+}
+
+static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops)
+{
+        dev->archdata.dma_ops = ops;
+}
+
+static inline int dma_supported(struct device *dev, u64 mask)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        if (unlikely(dma_ops == NULL))
+                return 0;
+        if (dma_ops->dma_supported == NULL)
+                return 1;
+        return dma_ops->dma_supported(dev, mask);
+}
+
+/* We have our own implementation of pci_set_dma_mask() */
+#define HAVE_ARCH_PCI_SET_DMA_MASK
+
+static inline int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        if (unlikely(dma_ops == NULL))
+                return -EIO;
+        if (dma_ops->set_dma_mask != NULL)
+                return dma_ops->set_dma_mask(dev, dma_mask);
+        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
+                return -EIO;
+        *dev->dma_mask = dma_mask;
+        return 0;
+}
+
+static inline dma_addr_t dma_map_single_attrs(struct device *dev,
+                                              void *cpu_addr,
+                                              size_t size,
+                                              enum dma_data_direction direction,
+                                              struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        return dma_ops->map_single(dev, cpu_addr, size, direction, attrs);
+}
+
+static inline void dma_unmap_single_attrs(struct device *dev,
+                                          dma_addr_t dma_addr,
+                                          size_t size,
+                                          enum dma_data_direction direction,
+                                          struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_single(dev, dma_addr, size, direction, attrs);
+}
+
+static inline dma_addr_t dma_map_page_attrs(struct device *dev,
+                                            struct page *page,
+                                            unsigned long offset, size_t size,
+                                            enum dma_data_direction direction,
+                                            struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        return dma_ops->map_single(dev, page_address(page) + offset, size,
+                        direction, attrs);
+}
+
+static inline void dma_unmap_page_attrs(struct device *dev,
+                                        dma_addr_t dma_address,
+                                        size_t size,
+                                        enum dma_data_direction direction,
+                                        struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_single(dev, dma_address, size, direction, attrs);
+}
+
+static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
+                                   int nents, enum dma_data_direction direction,
+                                   struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        return dma_ops->map_sg(dev, sg, nents, direction, attrs);
+}
+
+static inline void dma_unmap_sg_attrs(struct device *dev,
+                                      struct scatterlist *sg,
+                                      int nhwentries,
+                                      enum dma_data_direction direction,
+                                      struct dma_attrs *attrs)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        dma_ops->unmap_sg(dev, sg, nhwentries, direction, attrs);
+}
+
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t flag)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *cpu_addr, dma_addr_t dma_handle)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+
+        BUG_ON(!dma_ops);
+        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+}
+
+static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                                        size_t size,
+                                        enum dma_data_direction direction)
+{
+        return dma_map_single_attrs(dev, cpu_addr, size, direction, NULL);
+}
+
+static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                                    size_t size,
+                                    enum dma_data_direction direction)
+{
+        dma_unmap_single_attrs(dev, dma_addr, size, direction, NULL);
+}
+
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      unsigned long offset, size_t size,
+                                      enum dma_data_direction direction)
+{
+        return dma_map_page_attrs(dev, page, offset, size, direction, NULL);
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                  size_t size,
+                                  enum dma_data_direction direction)
+{
+        dma_unmap_page_attrs(dev, dma_address, size, direction, NULL);
+}
+
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+                             int nents, enum dma_data_direction direction)
+{
+        return dma_map_sg_attrs(dev, sg, nents, direction, NULL);
+}
+
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+                                int nhwentries,
+                                enum dma_data_direction direction)
+{
+        dma_unmap_sg_attrs(dev, sg, nhwentries, direction, NULL);
+}
+
+/*
+ * Available generic sets of operations
+ */
+extern struct dma_mapping_ops dma_iommu_ops;
+extern struct dma_mapping_ops dma_direct_ops;
+
+#else /* CONFIG_PPC64 */
+
+#define dma_supported(dev, mask)        (1)
+
+static inline int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = dma_mask;
+
+        return 0;
+}
+
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t * dma_handle,
+                                       gfp_t gfp)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+        return __dma_alloc_coherent(size, dma_handle, gfp);
+#else
+        void *ret;
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+
+        if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
+                gfp |= GFP_DMA;
+
+        ret = (void *)__get_free_pages(gfp, get_order(size));
+
+        if (ret != NULL) {
+                memset(ret, 0, size);
+                *dma_handle = virt_to_bus(ret);
+        }
+
+        return ret;
+#endif
+}
+
+static inline void
+dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+                  dma_addr_t dma_handle)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+        __dma_free_coherent(size, vaddr);
+#else
+        free_pages((unsigned long)vaddr, get_order(size));
+#endif
+}
+
+static inline dma_addr_t
+dma_map_single(struct device *dev, void *ptr, size_t size,
+               enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+
+        __dma_sync(ptr, size, direction);
+
+        return virt_to_bus(ptr);
+}
+
+static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                                    size_t size,
+                                    enum dma_data_direction direction)
+{
+        /* We do nothing. */
+}
+
+static inline dma_addr_t
+dma_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size,
+             enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+
+        __dma_sync_page(page, offset, size, direction);
+
+        return page_to_bus(page) + offset;
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                  size_t size,
+                                  enum dma_data_direction direction)
+{
+        /* We do nothing. */
+}
+
+static inline int
+dma_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
+           enum dma_data_direction direction)
+{
+        struct scatterlist *sg;
+        int i;
+
+        BUG_ON(direction == DMA_NONE);
+
+        for_each_sg(sgl, sg, nents, i) {
+                BUG_ON(!sg_page(sg));
+                __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
+                sg->dma_address = page_to_bus(sg_page(sg)) + sg->offset;
+        }
+
+        return nents;
+}
+
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+                                int nhwentries,
+                                enum dma_data_direction direction)
+{
+        /* We don't do anything here. */
+}
+
+#endif /* CONFIG_PPC64 */
+
+static inline void dma_sync_single_for_cpu(struct device *dev,
+                dma_addr_t dma_handle, size_t size,
+                enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+        __dma_sync(bus_to_virt(dma_handle), size, direction);
+}
+
+static inline void dma_sync_single_for_device(struct device *dev,
+                dma_addr_t dma_handle, size_t size,
+                enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+        __dma_sync(bus_to_virt(dma_handle), size, direction);
+}
+
+static inline void dma_sync_sg_for_cpu(struct device *dev,
+                struct scatterlist *sgl, int nents,
+                enum dma_data_direction direction)
+{
+        struct scatterlist *sg;
+        int i;
+
+        BUG_ON(direction == DMA_NONE);
+
+        for_each_sg(sgl, sg, nents, i)
+                __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
+}
+
+static inline void dma_sync_sg_for_device(struct device *dev,
+                struct scatterlist *sgl, int nents,
+                enum dma_data_direction direction)
+{
+        struct scatterlist *sg;
+        int i;
+
+        BUG_ON(direction == DMA_NONE);
+
+        for_each_sg(sgl, sg, nents, i)
+                __dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
+}
+
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+#ifdef CONFIG_PPC64
+        return (dma_addr == DMA_ERROR_CODE);
+#else
+        return 0;
+#endif
+}
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define dma_is_consistent(d, h) (0)
+#else
+#define dma_is_consistent(d, h) (1)
+#endif
+
+static inline int dma_get_cache_alignment(void)
+{
+#ifdef CONFIG_PPC64
+        /* no easy way to get cache size on all processors, so return
+         * the maximum possible, to be safe */
+        return (1 << INTERNODE_CACHE_SHIFT);
+#else
+        /*
+         * Each processor family will define its own L1_CACHE_SHIFT,
+         * L1_CACHE_BYTES wraps to this, so this is always safe.
+         */
+        return L1_CACHE_BYTES;
+#endif
+}
+
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+                dma_addr_t dma_handle, unsigned long offset, size_t size,
+                enum dma_data_direction direction)
+{
+        /* just sync everything for now */
+        dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
+}
+
+static inline void dma_sync_single_range_for_device(struct device *dev,
+                dma_addr_t dma_handle, unsigned long offset, size_t size,
+                enum dma_data_direction direction)
+{
+        /* just sync everything for now */
+        dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
+}
+
+static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+                enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+        __dma_sync(vaddr, size, (int)direction);
+}
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_DMA_MAPPING_H */
diff --git a/arch/powerpc/include/asm/dma.h b/arch/powerpc/include/asm/dma.h
new file mode 100644
index 000000000000..a7e06e25c708
--- /dev/null
+++ b/arch/powerpc/include/asm/dma.h
@@ -0,0 +1,360 @@
+#ifndef _ASM_POWERPC_DMA_H
+#define _ASM_POWERPC_DMA_H
+#ifdef __KERNEL__
+
+/*
+ * Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ * Changes for ppc sound by Christoph Nadig
+ */
+
+/*
+ * Note: Adapted for PowerPC by Gary Thomas
+ * Modified by Cort Dougan <cort@cs.nmt.edu>
+ *
+ * None of this really applies for Power Macintoshes.  There is
+ * basically just enough here to get kernel/dma.c to compile.
+ *
+ * There may be some comments or restrictions made here which are
+ * not valid for the PReP platform.  Take what you read
+ * with a grain of salt.
+ */
+
+#include <asm/io.h>
+#include <linux/spinlock.h>
+#include <asm/system.h>
+
+#ifndef MAX_DMA_CHANNELS
+#define MAX_DMA_CHANNELS        8
+#endif
+
+/* The maximum address that we can perform a DMA transfer to on this platform */
+/* Doesn't really apply... */
+#define MAX_DMA_ADDRESS         (~0UL)
+
+#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
+
+#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
+#define dma_outb        outb_p
+#else
+#define dma_outb        outb
+#endif
+
+#define dma_inb         inb
+
+/*
+ * NOTES about DMA transfers:
+ *
+ *  controller 1: channels 0-3, byte operations, ports 00-1F
+ *  controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ *  - ALL registers are 8 bits only, regardless of transfer size
+ *  - channel 4 is not used - cascades 1 into 2.
+ *  - channels 0-3 are byte - addresses/counts are for physical bytes
+ *  - channels 5-7 are word - addresses/counts are for physical words
+ *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ *  - transfer count loaded to registers is 1 less than actual count
+ *  - controller 2 offsets are all even (2x offsets for controller 1)
+ *  - page registers for 5-7 don't use data bit 0, represent 128K pages
+ *  - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ *  Address mapping for channels 0-3:
+ *
+ *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *   P7  ...  P0  A7 ... A0  A7 ... A0
+ * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *
+ *  Address mapping for channels 5-7:
+ *
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
+ *    |  ...  |   \   \   ... \  \  \  ... \  \
+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |  ...  |     \   \   ... \  \  \  ... \
+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ *
+ */
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG            0x08    /* command register (w) */
+#define DMA1_STAT_REG           0x08    /* status register (r) */
+#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
+#define DMA1_MODE_REG           0x0B    /* mode register (w) */
+#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+
+#define DMA2_CMD_REG            0xD0    /* command register (w) */
+#define DMA2_STAT_REG           0xD0    /* status register (r) */
+#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
+#define DMA2_MODE_REG           0xD6    /* mode register (w) */
+#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
+
+#define DMA_ADDR_0              0x00    /* DMA address registers */
+#define DMA_ADDR_1              0x02
+#define DMA_ADDR_2              0x04
+#define DMA_ADDR_3              0x06
+#define DMA_ADDR_4              0xC0
+#define DMA_ADDR_5              0xC4
+#define DMA_ADDR_6              0xC8
+#define DMA_ADDR_7              0xCC
+
+#define DMA_CNT_0               0x01    /* DMA count registers */
+#define DMA_CNT_1               0x03
+#define DMA_CNT_2               0x05
+#define DMA_CNT_3               0x07
+#define DMA_CNT_4               0xC2
+#define DMA_CNT_5               0xC6
+#define DMA_CNT_6               0xCA
+#define DMA_CNT_7               0xCE
+
+#define DMA_LO_PAGE_0           0x87    /* DMA page registers */
+#define DMA_LO_PAGE_1           0x83
+#define DMA_LO_PAGE_2           0x81
+#define DMA_LO_PAGE_3           0x82
+#define DMA_LO_PAGE_5           0x8B
+#define DMA_LO_PAGE_6           0x89
+#define DMA_LO_PAGE_7           0x8A
+
+#define DMA_HI_PAGE_0           0x487   /* DMA page registers */
+#define DMA_HI_PAGE_1           0x483
+#define DMA_HI_PAGE_2           0x481
+#define DMA_HI_PAGE_3           0x482
+#define DMA_HI_PAGE_5           0x48B
+#define DMA_HI_PAGE_6           0x489
+#define DMA_HI_PAGE_7           0x48A
+
+#define DMA1_EXT_REG            0x40B
+#define DMA2_EXT_REG            0x4D6
+
+#ifndef __powerpc64__
+    /* in arch/ppc/kernel/setup.c -- Cort */
+    extern unsigned int DMA_MODE_WRITE;
+    extern unsigned int DMA_MODE_READ;
+    extern unsigned long ISA_DMA_THRESHOLD;
+#else
+    #define DMA_MODE_READ       0x44    /* I/O to memory, no autoinit, increment, single mode */
+    #define DMA_MODE_WRITE      0x48    /* memory to I/O, no autoinit, increment, single mode */
+#endif
+
+#define DMA_MODE_CASCADE        0xC0    /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+#define DMA_AUTOINIT            0x10
+
+extern spinlock_t dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+        unsigned char ucDmaCmd = 0x00;
+
+        if (dmanr != 4) {
+                dma_outb(0, DMA2_MASK_REG);     /* This may not be enabled */
+                dma_outb(ucDmaCmd, DMA2_CMD_REG);       /* Enable group */
+        }
+        if (dmanr <= 3) {
+                dma_outb(dmanr, DMA1_MASK_REG);
+                dma_outb(ucDmaCmd, DMA1_CMD_REG);       /* Enable group */
+        } else {
+                dma_outb(dmanr & 3, DMA2_MASK_REG);
+        }
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+        if (dmanr <= 3)
+                dma_outb(dmanr | 4, DMA1_MASK_REG);
+        else
+                dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while interrupts are disabled! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+        if (dmanr <= 3)
+                dma_outb(0, DMA1_CLEAR_FF_REG);
+        else
+                dma_outb(0, DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+        if (dmanr <= 3)
+                dma_outb(mode | dmanr, DMA1_MODE_REG);
+        else
+                dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
+}
+
+/* Set only the page register bits of the transfer address.
+ * This is used for successive transfers when we know the contents of
+ * the lower 16 bits of the DMA current address register, but a 64k boundary
+ * may have been crossed.
+ */
+static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
+{
+        switch (dmanr) {
+        case 0:
+                dma_outb(pagenr, DMA_LO_PAGE_0);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
+                break;
+        case 1:
+                dma_outb(pagenr, DMA_LO_PAGE_1);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
+                break;
+        case 2:
+                dma_outb(pagenr, DMA_LO_PAGE_2);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
+                break;
+        case 3:
+                dma_outb(pagenr, DMA_LO_PAGE_3);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
+                break;
+        case 5:
+                dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
+                break;
+        case 6:
+                dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
+                break;
+        case 7:
+                dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
+                break;
+        }
+}
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
+{
+        if (dmanr <= 3) {
+                dma_outb(phys & 0xff,
+                         ((dmanr & 3) << 1) + IO_DMA1_BASE);
+                dma_outb((phys >> 8) & 0xff,
+                         ((dmanr & 3) << 1) + IO_DMA1_BASE);
+        } else {
+                dma_outb((phys >> 1) & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 9) & 0xff,
+                         ((dmanr & 3) << 2) + IO_DMA2_BASE);
+        }
+        set_dma_page(dmanr, phys >> 16);
+}
+
+
+/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        count--;
+        if (dmanr <= 3) {
+                dma_outb(count & 0xff,
+                         ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
+                dma_outb((count >> 8) & 0xff,
+                         ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
+        } else {
+                dma_outb((count >> 1) & 0xff,
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
+                dma_outb((count >> 9) & 0xff,
+                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
+        }
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+        unsigned int io_port = (dmanr <= 3)
+            ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
+            : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
+
+        /* using short to get 16-bit wrap around */
+        unsigned short count;
+
+        count = 1 + dma_inb(io_port);
+        count += dma_inb(io_port) << 8;
+
+        return (dmanr <= 3) ? count : (count << 1);
+}
+
+/* These are in kernel/dma.c: */
+
+/* reserve a DMA channel */
+extern int request_dma(unsigned int dmanr, const char *device_id);
+/* release it again */
+extern void free_dma(unsigned int dmanr);
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_DMA_H */
diff --git a/arch/powerpc/include/asm/edac.h b/arch/powerpc/include/asm/edac.h
new file mode 100644
index 000000000000..6ead88bbfbb8
--- /dev/null
+++ b/arch/powerpc/include/asm/edac.h
@@ -0,0 +1,40 @@
+/*
+ * PPC EDAC common defs
+ *
+ * Author: Dave Jiang <djiang@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef ASM_EDAC_H
+#define ASM_EDAC_H
+/*
+ * ECC atomic, DMA, SMP and interrupt safe scrub function.
+ * Implements the per arch atomic_scrub() that EDAC use for software
+ * ECC scrubbing.  It reads memory and then writes back the original
+ * value, allowing the hardware to detect and correct memory errors.
+ */
+static __inline__ void atomic_scrub(void *va, u32 size)
+{
+        unsigned int *virt_addr = va;
+        unsigned int temp;
+        unsigned int i;
+
+        for (i = 0; i < size / sizeof(*virt_addr); i++, virt_addr++) {
+                /* Very carefully read and write to memory atomically
+                 * so we are interrupt, DMA and SMP safe.
+                 */
+                __asm__ __volatile__ ("\n\
+                                1:      lwarx   %0,0,%1\n\
+                                        stwcx.  %0,0,%1\n\
+                                        bne-    1b\n\
+                                        isync"
+                                        : "=&r"(temp)
+                                        : "r"(virt_addr)
+                                        : "cr0", "memory");
+        }
+}
+
+#endif
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
new file mode 100644
index 000000000000..b886bec67016
--- /dev/null
+++ b/arch/powerpc/include/asm/eeh.h
@@ -0,0 +1,211 @@
+/*
+ * eeh.h
+ * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef _PPC64_EEH_H
+#define _PPC64_EEH_H
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/string.h>
+
+struct pci_dev;
+struct pci_bus;
+struct device_node;
+
+#ifdef CONFIG_EEH
+
+extern int eeh_subsystem_enabled;
+
+/* Values for eeh_mode bits in device_node */
+#define EEH_MODE_SUPPORTED     (1<<0)
+#define EEH_MODE_NOCHECK       (1<<1)
+#define EEH_MODE_ISOLATED      (1<<2)
+#define EEH_MODE_RECOVERING    (1<<3)
+#define EEH_MODE_IRQ_DISABLED  (1<<4)
+
+/* Max number of EEH freezes allowed before we consider the device
+ * to be permanently disabled. */
+#define EEH_MAX_ALLOWED_FREEZES 5
+
+void __init eeh_init(void);
+unsigned long eeh_check_failure(const volatile void __iomem *token,
+                                unsigned long val);
+int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
+void __init pci_addr_cache_build(void);
+
+/**
+ * eeh_add_device_early
+ * eeh_add_device_late
+ *
+ * Perform eeh initialization for devices added after boot.
+ * Call eeh_add_device_early before doing any i/o to the
+ * device (including config space i/o).  Call eeh_add_device_late
+ * to finish the eeh setup for this device.
+ */
+void eeh_add_device_tree_early(struct device_node *);
+void eeh_add_device_tree_late(struct pci_bus *);
+
+/**
+ * eeh_remove_device_recursive - undo EEH for device & children.
+ * @dev: pci device to be removed
+ *
+ * As above, this removes the device; it also removes child
+ * pci devices as well.
+ */
+void eeh_remove_bus_device(struct pci_dev *);
+
+/**
+ * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
+ *
+ * If this macro yields TRUE, the caller relays to eeh_check_failure()
+ * which does further tests out of line.
+ */
+#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_subsystem_enabled)
+
+/*
+ * Reads from a device which has been isolated by EEH will return
+ * all 1s.  This macro gives an all-1s value of the given size (in
+ * bytes: 1, 2, or 4) for comparing with the result of a read.
+ */
+#define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
+
+#else /* !CONFIG_EEH */
+static inline void eeh_init(void) { }
+
+static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
+{
+        return val;
+}
+
+static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
+{
+        return 0;
+}
+
+static inline void pci_addr_cache_build(void) { }
+
+static inline void eeh_add_device_tree_early(struct device_node *dn) { }
+
+static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
+
+static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
+#define EEH_POSSIBLE_ERROR(val, type) (0)
+#define EEH_IO_ERROR_VALUE(size) (-1UL)
+#endif /* CONFIG_EEH */
+
+/*
+ * MMIO read/write operations with EEH support.
+ */
+static inline u8 eeh_readb(const volatile void __iomem *addr)
+{
+        u8 val = in_8(addr);
+        if (EEH_POSSIBLE_ERROR(val, u8))
+                return eeh_check_failure(addr, val);
+        return val;
+}
+
+static inline u16 eeh_readw(const volatile void __iomem *addr)
+{
+        u16 val = in_le16(addr);
+        if (EEH_POSSIBLE_ERROR(val, u16))
+                return eeh_check_failure(addr, val);
+        return val;
+}
+
+static inline u32 eeh_readl(const volatile void __iomem *addr)
+{
+        u32 val = in_le32(addr);
+        if (EEH_POSSIBLE_ERROR(val, u32))
+                return eeh_check_failure(addr, val);
+        return val;
+}
+
+static inline u64 eeh_readq(const volatile void __iomem *addr)
+{
+        u64 val = in_le64(addr);
+        if (EEH_POSSIBLE_ERROR(val, u64))
+                return eeh_check_failure(addr, val);
+        return val;
+}
+
+static inline u16 eeh_readw_be(const volatile void __iomem *addr)
+{
+        u16 val = in_be16(addr);
+        if (EEH_POSSIBLE_ERROR(val, u16))
+                return eeh_check_failure(addr, val);
+        return val;
+}
+
+static inline u32 eeh_readl_be(const volatile void __iomem *addr)
+{
+        u32 val = in_be32(addr);
+        if (EEH_POSSIBLE_ERROR(val, u32))
+                return eeh_check_failure(addr, val);
+        return val;
+}
+
+static inline u64 eeh_readq_be(const volatile void __iomem *addr)
+{
+        u64 val = in_be64(addr);
+        if (EEH_POSSIBLE_ERROR(val, u64))
+                return eeh_check_failure(addr, val);
+        return val;
+}
+
+static inline void eeh_memcpy_fromio(void *dest, const
+                                     volatile void __iomem *src,
+                                     unsigned long n)
+{
+        _memcpy_fromio(dest, src, n);
+
+        /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
+         * were copied. Check all four bytes.
+         */
+        if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
+                eeh_check_failure(src, *((u32 *)(dest + n - 4)));
+}
+
+/* in-string eeh macros */
+static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
+                              int ns)
+{
+        _insb(addr, buf, ns);
+        if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
+                eeh_check_failure(addr, *(u8*)buf);
+}
+
+static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
+                              int ns)
+{
+        _insw(addr, buf, ns);
+        if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
+                eeh_check_failure(addr, *(u16*)buf);
+}
+
+static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
+                              int nl)
+{
+        _insl(addr, buf, nl);
+        if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
+                eeh_check_failure(addr, *(u32*)buf);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _PPC64_EEH_H */
diff --git a/arch/powerpc/include/asm/eeh_event.h b/arch/powerpc/include/asm/eeh_event.h
new file mode 100644
index 000000000000..cc3cb04539ac
--- /dev/null
+++ b/arch/powerpc/include/asm/eeh_event.h
@@ -0,0 +1,53 @@
+/*
+ *      eeh_event.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * Copyright (c) 2005 Linas Vepstas <linas@linas.org>
+ */
+
+#ifndef ASM_POWERPC_EEH_EVENT_H
+#define ASM_POWERPC_EEH_EVENT_H
+#ifdef __KERNEL__
+
+/** EEH event -- structure holding pci controller data that describes
+ *  a change in the isolation status of a PCI slot.  A pointer
+ *  to this struct is passed as the data pointer in a notify callback.
+ */
+struct eeh_event {
+        struct list_head     list;
+        struct device_node      *dn;   /* struct device node */
+        struct pci_dev       *dev;  /* affected device */
+};
+
+/**
+ * eeh_send_failure_event - generate a PCI error event
+ * @dev pci device
+ *
+ * This routine builds a PCI error event which will be delivered
+ * to all listeners on the eeh_notifier_chain.
+ *
+ * This routine can be called within an interrupt context;
+ * the actual event will be delivered in a normal context
+ * (from a workqueue).
+ */
+int eeh_send_failure_event (struct device_node *dn,
+                            struct pci_dev *dev);
+
+/* Main recovery function */
+struct pci_dn * handle_eeh_events (struct eeh_event *);
+
+#endif /* __KERNEL__ */
+#endif /* ASM_POWERPC_EEH_EVENT_H */
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
new file mode 100644
index 000000000000..80d1f399ee51
--- /dev/null
+++ b/arch/powerpc/include/asm/elf.h
@@ -0,0 +1,424 @@
+#ifndef _ASM_POWERPC_ELF_H
+#define _ASM_POWERPC_ELF_H
+
+#ifdef __KERNEL__
+#include <linux/sched.h>        /* for task_struct */
+#include <asm/page.h>
+#include <asm/string.h>
+#endif
+
+#include <asm/types.h>
+#include <asm/ptrace.h>
+#include <asm/cputable.h>
+#include <asm/auxvec.h>
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE              0
+#define R_PPC_ADDR32            1       /* 32bit absolute address */
+#define R_PPC_ADDR24            2       /* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16            3       /* 16bit absolute address */
+#define R_PPC_ADDR16_LO         4       /* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI         5       /* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA         6       /* adjusted high 16bit */
+#define R_PPC_ADDR14            7       /* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN    8
+#define R_PPC_ADDR14_BRNTAKEN   9
+#define R_PPC_REL24             10      /* PC relative 26 bit */
+#define R_PPC_REL14             11      /* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN     12
+#define R_PPC_REL14_BRNTAKEN    13
+#define R_PPC_GOT16             14
+#define R_PPC_GOT16_LO          15
+#define R_PPC_GOT16_HI          16
+#define R_PPC_GOT16_HA          17
+#define R_PPC_PLTREL24          18
+#define R_PPC_COPY              19
+#define R_PPC_GLOB_DAT          20
+#define R_PPC_JMP_SLOT          21
+#define R_PPC_RELATIVE          22
+#define R_PPC_LOCAL24PC         23
+#define R_PPC_UADDR32           24
+#define R_PPC_UADDR16           25
+#define R_PPC_REL32             26
+#define R_PPC_PLT32             27
+#define R_PPC_PLTREL32          28
+#define R_PPC_PLT16_LO          29
+#define R_PPC_PLT16_HI          30
+#define R_PPC_PLT16_HA          31
+#define R_PPC_SDAREL16          32
+#define R_PPC_SECTOFF           33
+#define R_PPC_SECTOFF_LO        34
+#define R_PPC_SECTOFF_HI        35
+#define R_PPC_SECTOFF_HA        36
+
+/* PowerPC relocations defined for the TLS access ABI.  */
+#define R_PPC_TLS               67 /* none      (sym+add)@tls */
+#define R_PPC_DTPMOD32          68 /* word32    (sym+add)@dtpmod */
+#define R_PPC_TPREL16           69 /* half16*   (sym+add)@tprel */
+#define R_PPC_TPREL16_LO        70 /* half16    (sym+add)@tprel@l */
+#define R_PPC_TPREL16_HI        71 /* half16    (sym+add)@tprel@h */
+#define R_PPC_TPREL16_HA        72 /* half16    (sym+add)@tprel@ha */
+#define R_PPC_TPREL32           73 /* word32    (sym+add)@tprel */
+#define R_PPC_DTPREL16          74 /* half16*   (sym+add)@dtprel */
+#define R_PPC_DTPREL16_LO       75 /* half16    (sym+add)@dtprel@l */
+#define R_PPC_DTPREL16_HI       76 /* half16    (sym+add)@dtprel@h */
+#define R_PPC_DTPREL16_HA       77 /* half16    (sym+add)@dtprel@ha */
+#define R_PPC_DTPREL32          78 /* word32    (sym+add)@dtprel */
+#define R_PPC_GOT_TLSGD16       79 /* half16*   (sym+add)@got@tlsgd */
+#define R_PPC_GOT_TLSGD16_LO    80 /* half16    (sym+add)@got@tlsgd@l */
+#define R_PPC_GOT_TLSGD16_HI    81 /* half16    (sym+add)@got@tlsgd@h */
+#define R_PPC_GOT_TLSGD16_HA    82 /* half16    (sym+add)@got@tlsgd@ha */
+#define R_PPC_GOT_TLSLD16       83 /* half16*   (sym+add)@got@tlsld */
+#define R_PPC_GOT_TLSLD16_LO    84 /* half16    (sym+add)@got@tlsld@l */
+#define R_PPC_GOT_TLSLD16_HI    85 /* half16    (sym+add)@got@tlsld@h */
+#define R_PPC_GOT_TLSLD16_HA    86 /* half16    (sym+add)@got@tlsld@ha */
+#define R_PPC_GOT_TPREL16       87 /* half16*   (sym+add)@got@tprel */
+#define R_PPC_GOT_TPREL16_LO    88 /* half16    (sym+add)@got@tprel@l */
+#define R_PPC_GOT_TPREL16_HI    89 /* half16    (sym+add)@got@tprel@h */
+#define R_PPC_GOT_TPREL16_HA    90 /* half16    (sym+add)@got@tprel@ha */
+#define R_PPC_GOT_DTPREL16      91 /* half16*   (sym+add)@got@dtprel */
+#define R_PPC_GOT_DTPREL16_LO   92 /* half16*   (sym+add)@got@dtprel@l */
+#define R_PPC_GOT_DTPREL16_HI   93 /* half16*   (sym+add)@got@dtprel@h */
+#define R_PPC_GOT_DTPREL16_HA   94 /* half16*   (sym+add)@got@dtprel@ha */
+
+/* keep this the last entry. */
+#define R_PPC_NUM               95
+
+/*
+ * ELF register definitions..
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
+#define ELF_NFPREG      33      /* includes fpscr */
+
+typedef unsigned long elf_greg_t64;
+typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
+
+typedef unsigned int elf_greg_t32;
+typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
+typedef elf_gregset_t32 compat_elf_gregset_t;
+
+/*
+ * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
+ */
+#ifdef __powerpc64__
+# define ELF_NVRREG32   33      /* includes vscr & vrsave stuffed together */
+# define ELF_NVRREG     34      /* includes vscr & vrsave in split vectors */
+# define ELF_NVSRHALFREG 32     /* Half the vsx registers */
+# define ELF_GREG_TYPE  elf_greg_t64
+#else
+# define ELF_NEVRREG    34      /* includes acc (as 2) */
+# define ELF_NVRREG     33      /* includes vscr */
+# define ELF_GREG_TYPE  elf_greg_t32
+# define ELF_ARCH       EM_PPC
+# define ELF_CLASS      ELFCLASS32
+# define ELF_DATA       ELFDATA2MSB
+#endif /* __powerpc64__ */
+
+#ifndef ELF_ARCH
+# define ELF_ARCH       EM_PPC64
+# define ELF_CLASS      ELFCLASS64
+# define ELF_DATA       ELFDATA2MSB
+  typedef elf_greg_t64 elf_greg_t;
+  typedef elf_gregset_t64 elf_gregset_t;
+#else
+  /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
+  typedef elf_greg_t32 elf_greg_t;
+  typedef elf_gregset_t32 elf_gregset_t;
+#endif /* ELF_ARCH */
+
+/* Floating point registers */
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+/* Altivec registers */
+/*
+ * The entries with indexes 0-31 contain the corresponding vector registers. 
+ * The entry with index 32 contains the vscr as the last word (offset 12) 
+ * within the quadword.  This allows the vscr to be stored as either a 
+ * quadword (since it must be copied via a vector register to/from storage) 
+ * or as a word.  
+ *
+ * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first  
+ * word (offset 0) within the quadword.
+ *
+ * This definition of the VMX state is compatible with the current PPC32 
+ * ptrace interface.  This allows signal handling and ptrace to use the same 
+ * structures.  This also simplifies the implementation of a bi-arch 
+ * (combined (32- and 64-bit) gdb.
+ *
+ * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
+ * vrsave along with vscr and so only uses 33 vectors for the register set
+ */
+typedef __vector128 elf_vrreg_t;
+typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
+#ifdef __powerpc64__
+typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
+typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
+#endif
+
+#ifdef __KERNEL__
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
+#define compat_elf_check_arch(x)        ((x)->e_machine == EM_PPC)
+
+#define USE_ELF_CORE_DUMP
+#define CORE_DUMP_USE_REGSET
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE         (0x20000000)
+
+/*
+ * Our registers are always unsigned longs, whether we're a 32 bit
+ * process or 64 bit, on either a 64 bit or 32 bit kernel.
+ *
+ * This macro relies on elf_regs[i] having the right type to truncate to,
+ * either u32 or u64.  It defines the body of the elf_core_copy_regs
+ * function, either the native one with elf_gregset_t elf_regs or
+ * the 32-bit one with elf_gregset_t32 elf_regs.
+ */
+#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
+        int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
+                           (size_t)ELF_NGREG);                    \
+        for (i = 0; i < nregs; i++) \
+                elf_regs[i] = ((unsigned long *) regs)[i]; \
+        memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))
+
+/* Common routine for both 32-bit and 64-bit native processes */
+static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
+                                          struct pt_regs *regs)
+{
+        PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
+}
+#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
+
+typedef elf_vrregset_t elf_fpxregset_t;
+
+/* ELF_HWCAP yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  This could be done in userspace,
+   but it's not easy, and we've already done it here.  */
+# define ELF_HWCAP      (cur_cpu_spec->cpu_user_features)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.  */
+
+#define ELF_PLATFORM    (cur_cpu_spec->platform)
+
+/* While ELF_PLATFORM indicates the ISA supported by the platform, it
+ * may not accurately reflect the underlying behavior of the hardware
+ * (as in the case of running in Power5+ compatibility mode on a
+ * Power6 machine).  ELF_BASE_PLATFORM allows ld.so to load libraries
+ * that are tuned for the real hardware.
+ */
+#define ELF_BASE_PLATFORM (powerpc_base_platform)
+
+#ifdef __powerpc64__
+# define ELF_PLAT_INIT(_r, load_addr)   do {    \
+        _r->gpr[2] = load_addr;                 \
+} while (0)
+#endif /* __powerpc64__ */
+
+#ifdef __powerpc64__
+# define SET_PERSONALITY(ex, ibcs2)                             \
+do {                                                            \
+        unsigned long new_flags = 0;                            \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)               \
+                new_flags = _TIF_32BIT;                         \
+        if ((current_thread_info()->flags & _TIF_32BIT)         \
+            != new_flags)                                       \
+                set_thread_flag(TIF_ABI_PENDING);               \
+        else                                                    \
+                clear_thread_flag(TIF_ABI_PENDING);             \
+        if (personality(current->personality) != PER_LINUX32)   \
+                set_personality(PER_LINUX |                     \
+                        (current->personality & (~PER_MASK)));  \
+} while (0)
+/*
+ * An executable for which elf_read_implies_exec() returns TRUE will
+ * have the READ_IMPLIES_EXEC personality flag set automatically. This
+ * is only required to work around bugs in old 32bit toolchains. Since
+ * the 64bit ABI has never had these issues dont enable the workaround
+ * even if we have an executable stack.
+ */
+# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
+                (exec_stk != EXSTACK_DISABLE_X) : 0)
+#else 
+# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#endif /* __powerpc64__ */
+
+extern int dcache_bsize;
+extern int icache_bsize;
+extern int ucache_bsize;
+
+/* vDSO has arch_setup_additional_pages */
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+struct linux_binprm;
+extern int arch_setup_additional_pages(struct linux_binprm *bprm,
+                                       int executable_stack);
+#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
+
+#endif /* __KERNEL__ */
+
+/*
+ * The requirements here are:
+ * - keep the final alignment of sp (sp & 0xf)
+ * - make sure the 32-bit value at the first 16 byte aligned position of
+ *   AUXV is greater than 16 for glibc compatibility.
+ *   AT_IGNOREPPC is used for that.
+ * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
+ *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
+ * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
+ */
+#define ARCH_DLINFO                                                     \
+do {                                                                    \
+        /* Handle glibc compatibility. */                               \
+        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
+        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
+        /* Cache size items */                                          \
+        NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
+        NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
+        NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
+        VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base)   \
+} while (0)
+
+/* PowerPC64 relocations defined by the ABIs */
+#define R_PPC64_NONE    R_PPC_NONE
+#define R_PPC64_ADDR32  R_PPC_ADDR32  /* 32bit absolute address.  */
+#define R_PPC64_ADDR24  R_PPC_ADDR24  /* 26bit address, word aligned.  */
+#define R_PPC64_ADDR16  R_PPC_ADDR16  /* 16bit absolute address. */
+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address.  */
+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits.  */
+#define R_PPC64_ADDR14 R_PPC_ADDR14   /* 16bit address, word aligned.  */
+#define R_PPC64_ADDR14_BRTAKEN  R_PPC_ADDR14_BRTAKEN
+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
+#define R_PPC64_REL24   R_PPC_REL24 /* PC relative 26 bit, word aligned.  */
+#define R_PPC64_REL14   R_PPC_REL14 /* PC relative 16 bit. */
+#define R_PPC64_REL14_BRTAKEN   R_PPC_REL14_BRTAKEN
+#define R_PPC64_REL14_BRNTAKEN  R_PPC_REL14_BRNTAKEN
+#define R_PPC64_GOT16     R_PPC_GOT16
+#define R_PPC64_GOT16_LO  R_PPC_GOT16_LO
+#define R_PPC64_GOT16_HI  R_PPC_GOT16_HI
+#define R_PPC64_GOT16_HA  R_PPC_GOT16_HA
+
+#define R_PPC64_COPY      R_PPC_COPY
+#define R_PPC64_GLOB_DAT  R_PPC_GLOB_DAT
+#define R_PPC64_JMP_SLOT  R_PPC_JMP_SLOT
+#define R_PPC64_RELATIVE  R_PPC_RELATIVE
+
+#define R_PPC64_UADDR32   R_PPC_UADDR32
+#define R_PPC64_UADDR16   R_PPC_UADDR16
+#define R_PPC64_REL32     R_PPC_REL32
+#define R_PPC64_PLT32     R_PPC_PLT32
+#define R_PPC64_PLTREL32  R_PPC_PLTREL32
+#define R_PPC64_PLT16_LO  R_PPC_PLT16_LO
+#define R_PPC64_PLT16_HI  R_PPC_PLT16_HI
+#define R_PPC64_PLT16_HA  R_PPC_PLT16_HA
+
+#define R_PPC64_SECTOFF     R_PPC_SECTOFF
+#define R_PPC64_SECTOFF_LO  R_PPC_SECTOFF_LO
+#define R_PPC64_SECTOFF_HI  R_PPC_SECTOFF_HI
+#define R_PPC64_SECTOFF_HA  R_PPC_SECTOFF_HA
+#define R_PPC64_ADDR30          37  /* word30 (S + A - P) >> 2.  */
+#define R_PPC64_ADDR64          38  /* doubleword64 S + A.  */
+#define R_PPC64_ADDR16_HIGHER   39  /* half16 #higher(S + A).  */
+#define R_PPC64_ADDR16_HIGHERA  40  /* half16 #highera(S + A).  */
+#define R_PPC64_ADDR16_HIGHEST  41  /* half16 #highest(S + A).  */
+#define R_PPC64_ADDR16_HIGHESTA 42  /* half16 #highesta(S + A). */
+#define R_PPC64_UADDR64     43  /* doubleword64 S + A.  */
+#define R_PPC64_REL64       44  /* doubleword64 S + A - P.  */
+#define R_PPC64_PLT64       45  /* doubleword64 L + A.  */
+#define R_PPC64_PLTREL64    46  /* doubleword64 L + A - P.  */
+#define R_PPC64_TOC16       47  /* half16* S + A - .TOC.  */
+#define R_PPC64_TOC16_LO    48  /* half16 #lo(S + A - .TOC.).  */
+#define R_PPC64_TOC16_HI    49  /* half16 #hi(S + A - .TOC.).  */
+#define R_PPC64_TOC16_HA    50  /* half16 #ha(S + A - .TOC.).  */
+#define R_PPC64_TOC         51  /* doubleword64 .TOC. */
+#define R_PPC64_PLTGOT16    52  /* half16* M + A.  */
+#define R_PPC64_PLTGOT16_LO 53  /* half16 #lo(M + A).  */
+#define R_PPC64_PLTGOT16_HI 54  /* half16 #hi(M + A).  */
+#define R_PPC64_PLTGOT16_HA 55  /* half16 #ha(M + A).  */
+
+#define R_PPC64_ADDR16_DS      56 /* half16ds* (S + A) >> 2.  */
+#define R_PPC64_ADDR16_LO_DS   57 /* half16ds  #lo(S + A) >> 2.  */
+#define R_PPC64_GOT16_DS       58 /* half16ds* (G + A) >> 2.  */
+#define R_PPC64_GOT16_LO_DS    59 /* half16ds  #lo(G + A) >> 2.  */
+#define R_PPC64_PLT16_LO_DS    60 /* half16ds  #lo(L + A) >> 2.  */
+#define R_PPC64_SECTOFF_DS     61 /* half16ds* (R + A) >> 2.  */
+#define R_PPC64_SECTOFF_LO_DS  62 /* half16ds  #lo(R + A) >> 2.  */
+#define R_PPC64_TOC16_DS       63 /* half16ds* (S + A - .TOC.) >> 2.  */
+#define R_PPC64_TOC16_LO_DS    64 /* half16ds  #lo(S + A - .TOC.) >> 2.  */
+#define R_PPC64_PLTGOT16_DS    65 /* half16ds* (M + A) >> 2.  */
+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds  #lo(M + A) >> 2.  */
+
+/* PowerPC64 relocations defined for the TLS access ABI.  */
+#define R_PPC64_TLS             67 /* none      (sym+add)@tls */
+#define R_PPC64_DTPMOD64        68 /* doubleword64 (sym+add)@dtpmod */
+#define R_PPC64_TPREL16         69 /* half16*   (sym+add)@tprel */
+#define R_PPC64_TPREL16_LO      70 /* half16    (sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HI      71 /* half16    (sym+add)@tprel@h */
+#define R_PPC64_TPREL16_HA      72 /* half16    (sym+add)@tprel@ha */
+#define R_PPC64_TPREL64         73 /* doubleword64 (sym+add)@tprel */
+#define R_PPC64_DTPREL16        74 /* half16*   (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO     75 /* half16    (sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HI     76 /* half16    (sym+add)@dtprel@h */
+#define R_PPC64_DTPREL16_HA     77 /* half16    (sym+add)@dtprel@ha */
+#define R_PPC64_DTPREL64        78 /* doubleword64 (sym+add)@dtprel */
+#define R_PPC64_GOT_TLSGD16     79 /* half16*   (sym+add)@got@tlsgd */
+#define R_PPC64_GOT_TLSGD16_LO  80 /* half16    (sym+add)@got@tlsgd@l */
+#define R_PPC64_GOT_TLSGD16_HI  81 /* half16    (sym+add)@got@tlsgd@h */
+#define R_PPC64_GOT_TLSGD16_HA  82 /* half16    (sym+add)@got@tlsgd@ha */
+#define R_PPC64_GOT_TLSLD16     83 /* half16*   (sym+add)@got@tlsld */
+#define R_PPC64_GOT_TLSLD16_LO  84 /* half16    (sym+add)@got@tlsld@l */
+#define R_PPC64_GOT_TLSLD16_HI  85 /* half16    (sym+add)@got@tlsld@h */
+#define R_PPC64_GOT_TLSLD16_HA  86 /* half16    (sym+add)@got@tlsld@ha */
+#define R_PPC64_GOT_TPREL16_DS  87 /* half16ds* (sym+add)@got@tprel */
+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
+#define R_PPC64_GOT_TPREL16_HI  89 /* half16    (sym+add)@got@tprel@h */
+#define R_PPC64_GOT_TPREL16_HA  90 /* half16    (sym+add)@got@tprel@ha */
+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16    (sym+add)@got@dtprel@h */
+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16    (sym+add)@got@dtprel@ha */
+#define R_PPC64_TPREL16_DS      95 /* half16ds* (sym+add)@tprel */
+#define R_PPC64_TPREL16_LO_DS   96 /* half16ds  (sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HIGHER  97 /* half16    (sym+add)@tprel@higher */
+#define R_PPC64_TPREL16_HIGHERA 98 /* half16    (sym+add)@tprel@highera */
+#define R_PPC64_TPREL16_HIGHEST 99 /* half16    (sym+add)@tprel@highest */
+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16  (sym+add)@tprel@highesta */
+#define R_PPC64_DTPREL16_DS     101 /* half16ds* (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO_DS  102 /* half16ds (sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HIGHER 103 /* half16   (sym+add)@dtprel@higher */
+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16  (sym+add)@dtprel@highera */
+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16  (sym+add)@dtprel@highest */
+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
+
+/* Keep this the last entry.  */
+#define R_PPC64_NUM             107
+
+#ifdef  __KERNEL__
+
+#ifdef CONFIG_SPU_BASE
+/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
+#define NT_SPU          1
+
+#define ARCH_HAVE_EXTRA_ELF_NOTES
+
+#endif /* CONFIG_SPU_BASE */
+
+#endif /* __KERNEL */
+
+#endif /* _ASM_POWERPC_ELF_H */
diff --git a/arch/powerpc/include/asm/emergency-restart.h b/arch/powerpc/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..3711bd9d50bd
--- /dev/null
+++ b/arch/powerpc/include/asm/emergency-restart.h
@@ -0,0 +1 @@
+#include <asm-generic/emergency-restart.h>
diff --git a/arch/powerpc/include/asm/errno.h b/arch/powerpc/include/asm/errno.h
new file mode 100644
index 000000000000..8c145fd17d86
--- /dev/null
+++ b/arch/powerpc/include/asm/errno.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_POWERPC_ERRNO_H
+#define _ASM_POWERPC_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#undef  EDEADLOCK
+#define EDEADLOCK       58      /* File locking deadlock error */
+
+#define _LAST_ERRNO     516
+
+#endif  /* _ASM_POWERPC_ERRNO_H */
diff --git a/arch/powerpc/include/asm/exception.h b/arch/powerpc/include/asm/exception.h
new file mode 100644
index 000000000000..329148b5acc6
--- /dev/null
+++ b/arch/powerpc/include/asm/exception.h
@@ -0,0 +1,311 @@
+#ifndef _ASM_POWERPC_EXCEPTION_H
+#define _ASM_POWERPC_EXCEPTION_H
+/*
+ * Extracted from head_64.S
+ *
+ *  PowerPC version
+ *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
+ *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
+ *  Adapted for Power Macintosh by Paul Mackerras.
+ *  Low-level exception handlers and MMU support
+ *  rewritten by Paul Mackerras.
+ *    Copyright (C) 1996 Paul Mackerras.
+ *
+ *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
+ *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
+ *
+ *  This file contains the low-level support and setup for the
+ *  PowerPC-64 platform, including trap and interrupt dispatch.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+/*
+ * The following macros define the code that appears as
+ * the prologue to each of the exception handlers.  They
+ * are split into two parts to allow a single kernel binary
+ * to be used for pSeries and iSeries.
+ *
+ * We make as much of the exception code common between native
+ * exception handlers (including pSeries LPAR) and iSeries LPAR
+ * implementations as possible.
+ */
+
+#define EX_R9           0
+#define EX_R10          8
+#define EX_R11          16
+#define EX_R12          24
+#define EX_R13          32
+#define EX_SRR0         40
+#define EX_DAR          48
+#define EX_DSISR        56
+#define EX_CCR          60
+#define EX_R3           64
+#define EX_LR           72
+
+/*
+ * We're short on space and time in the exception prolog, so we can't
+ * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
+ * low halfword of the address, but for Kdump we need the whole low
+ * word.
+ */
+#ifdef CONFIG_CRASH_DUMP
+#define LOAD_HANDLER(reg, label)                                        \
+        oris    reg,reg,(label)@h;      /* virt addr of handler ... */  \
+        ori     reg,reg,(label)@l;      /* .. and the rest */
+#else
+#define LOAD_HANDLER(reg, label)                                        \
+        ori     reg,reg,(label)@l;      /* virt addr of handler ... */
+#endif
+
+#define EXCEPTION_PROLOG_1(area)                                \
+        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
+        std     r10,area+EX_R10(r13);                                   \
+        std     r11,area+EX_R11(r13);                                   \
+        std     r12,area+EX_R12(r13);                                   \
+        mfspr   r9,SPRN_SPRG1;                                          \
+        std     r9,area+EX_R13(r13);                                    \
+        mfcr    r9
+
+/*
+ * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
+ * The firmware calls the registered system_reset_fwnmi and
+ * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
+ * a 32bit application at the time of the event.
+ * This firmware bug is present on POWER4 and JS20.
+ */
+#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label)               \
+        EXCEPTION_PROLOG_1(area);                                       \
+        clrrdi  r12,r13,32;             /* get high part of &label */   \
+        mfmsr   r10;                                                    \
+        /* force 64bit mode */                                          \
+        li      r11,5;                  /* MSR_SF_LG|MSR_ISF_LG */      \
+        rldimi  r10,r11,61,0;           /* insert into top 3 bits */    \
+        /* done 64bit mode */                                           \
+        mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
+        LOAD_HANDLER(r12,label)                                         \
+        ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
+        mtspr   SPRN_SRR0,r12;                                          \
+        mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
+        mtspr   SPRN_SRR1,r10;                                          \
+        rfid;                                                           \
+        b       .       /* prevent speculative execution */
+
+#define EXCEPTION_PROLOG_PSERIES(area, label)                           \
+        EXCEPTION_PROLOG_1(area);                                       \
+        clrrdi  r12,r13,32;             /* get high part of &label */   \
+        mfmsr   r10;                                                    \
+        mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
+        LOAD_HANDLER(r12,label)                                         \
+        ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
+        mtspr   SPRN_SRR0,r12;                                          \
+        mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
+        mtspr   SPRN_SRR1,r10;                                          \
+        rfid;                                                           \
+        b       .       /* prevent speculative execution */
+
+/*
+ * The common exception prolog is used for all except a few exceptions
+ * such as a segment miss on a kernel address.  We have to be prepared
+ * to take another exception from the point where we first touch the
+ * kernel stack onwards.
+ *
+ * On entry r13 points to the paca, r9-r13 are saved in the paca,
+ * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
+ * SRR1, and relocation is on.
+ */
+#define EXCEPTION_PROLOG_COMMON(n, area)                                   \
+        andi.   r10,r12,MSR_PR;         /* See if coming from user      */ \
+        mr      r10,r1;                 /* Save r1                      */ \
+        subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack  */ \
+        beq-    1f;                                                        \
+        ld      r1,PACAKSAVE(r13);      /* kernel stack to use          */ \
+1:      cmpdi   cr1,r1,0;               /* check if r1 is in userspace  */ \
+        bge-    cr1,2f;                 /* abort if it is               */ \
+        b       3f;                                                        \
+2:      li      r1,(n);                 /* will be reloaded later       */ \
+        sth     r1,PACA_TRAP_SAVE(r13);                                    \
+        b       bad_stack;                                                 \
+3:      std     r9,_CCR(r1);            /* save CR in stackframe        */ \
+        std     r11,_NIP(r1);           /* save SRR0 in stackframe      */ \
+        std     r12,_MSR(r1);           /* save SRR1 in stackframe      */ \
+        std     r10,0(r1);              /* make stack chain pointer     */ \
+        std     r0,GPR0(r1);            /* save r0 in stackframe        */ \
+        std     r10,GPR1(r1);           /* save r1 in stackframe        */ \
+        ACCOUNT_CPU_USER_ENTRY(r9, r10);                                   \
+        std     r2,GPR2(r1);            /* save r2 in stackframe        */ \
+        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe   */ \
+        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe    */ \
+        ld      r9,area+EX_R9(r13);     /* move r9, r10 to stackframe   */ \
+        ld      r10,area+EX_R10(r13);                                      \
+        std     r9,GPR9(r1);                                               \
+        std     r10,GPR10(r1);                                             \
+        ld      r9,area+EX_R11(r13);    /* move r11 - r13 to stackframe */ \
+        ld      r10,area+EX_R12(r13);                                      \
+        ld      r11,area+EX_R13(r13);                                      \
+        std     r9,GPR11(r1);                                              \
+        std     r10,GPR12(r1);                                             \
+        std     r11,GPR13(r1);                                             \
+        ld      r2,PACATOC(r13);        /* get kernel TOC into r2       */ \
+        mflr    r9;                     /* save LR in stackframe        */ \
+        std     r9,_LINK(r1);                                              \
+        mfctr   r10;                    /* save CTR in stackframe       */ \
+        std     r10,_CTR(r1);                                              \
+        lbz     r10,PACASOFTIRQEN(r13);                            \
+        mfspr   r11,SPRN_XER;           /* save XER in stackframe       */ \
+        std     r10,SOFTE(r1);                                             \
+        std     r11,_XER(r1);                                              \
+        li      r9,(n)+1;                                                  \
+        std     r9,_TRAP(r1);           /* set trap number              */ \
+        li      r10,0;                                                     \
+        ld      r11,exception_marker@toc(r2);                              \
+        std     r10,RESULT(r1);         /* clear regs->result           */ \
+        std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */
+
+/*
+ * Exception vectors.
+ */
+#define STD_EXCEPTION_PSERIES(n, label)                 \
+        . = n;                                          \
+        .globl label##_pSeries;                         \
+label##_pSeries:                                        \
+        HMT_MEDIUM;                                     \
+        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
+
+#define HSTD_EXCEPTION_PSERIES(n, label)                \
+        . = n;                                          \
+        .globl label##_pSeries;                         \
+label##_pSeries:                                        \
+        HMT_MEDIUM;                                     \
+        mtspr   SPRN_SPRG1,r20;         /* save r20 */  \
+        mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
+        mtspr   SPRN_SRR0,r20;                          \
+        mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
+        mtspr   SPRN_SRR1,r20;                          \
+        mfspr   r20,SPRN_SPRG1;         /* restore r20 */ \
+        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
+
+
+#define MASKABLE_EXCEPTION_PSERIES(n, label)                            \
+        . = n;                                                          \
+        .globl label##_pSeries;                                         \
+label##_pSeries:                                                        \
+        HMT_MEDIUM;                                                     \
+        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
+        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
+        std     r10,PACA_EXGEN+EX_R10(r13);                             \
+        lbz     r10,PACASOFTIRQEN(r13);                                 \
+        mfcr    r9;                                                     \
+        cmpwi   r10,0;                                                  \
+        beq     masked_interrupt;                                       \
+        mfspr   r10,SPRN_SPRG1;                                         \
+        std     r10,PACA_EXGEN+EX_R13(r13);                             \
+        std     r11,PACA_EXGEN+EX_R11(r13);                             \
+        std     r12,PACA_EXGEN+EX_R12(r13);                             \
+        clrrdi  r12,r13,32;             /* get high part of &label */   \
+        mfmsr   r10;                                                    \
+        mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
+        LOAD_HANDLER(r12,label##_common)                                \
+        ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
+        mtspr   SPRN_SRR0,r12;                                          \
+        mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
+        mtspr   SPRN_SRR1,r10;                                          \
+        rfid;                                                           \
+        b       .       /* prevent speculative execution */
+
+#ifdef CONFIG_PPC_ISERIES
+#define DISABLE_INTS                            \
+        li      r11,0;                          \
+        stb     r11,PACASOFTIRQEN(r13);         \
+BEGIN_FW_FTR_SECTION;                           \
+        stb     r11,PACAHARDIRQEN(r13);         \
+END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);   \
+        TRACE_DISABLE_INTS;                     \
+BEGIN_FW_FTR_SECTION;                           \
+        mfmsr   r10;                            \
+        ori     r10,r10,MSR_EE;                 \
+        mtmsrd  r10,1;                          \
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+#else
+#define DISABLE_INTS                            \
+        li      r11,0;                          \
+        stb     r11,PACASOFTIRQEN(r13);         \
+        stb     r11,PACAHARDIRQEN(r13);         \
+        TRACE_DISABLE_INTS
+#endif /* CONFIG_PPC_ISERIES */
+
+#define ENABLE_INTS                             \
+        ld      r12,_MSR(r1);                   \
+        mfmsr   r11;                            \
+        rlwimi  r11,r12,0,MSR_EE;               \
+        mtmsrd  r11,1
+
+#define STD_EXCEPTION_COMMON(trap, label, hdlr)         \
+        .align  7;                                      \
+        .globl label##_common;                          \
+label##_common:                                         \
+        EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
+        DISABLE_INTS;                                   \
+        bl      .save_nvgprs;                           \
+        addi    r3,r1,STACK_FRAME_OVERHEAD;             \
+        bl      hdlr;                                   \
+        b       .ret_from_except
+
+/*
+ * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
+ * in the idle task and therefore need the special idle handling.
+ */
+#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr)    \
+        .align  7;                                      \
+        .globl label##_common;                          \
+label##_common:                                         \
+        EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
+        FINISH_NAP;                                     \
+        DISABLE_INTS;                                   \
+        bl      .save_nvgprs;                           \
+        addi    r3,r1,STACK_FRAME_OVERHEAD;             \
+        bl      hdlr;                                   \
+        b       .ret_from_except
+
+#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr)    \
+        .align  7;                                      \
+        .globl label##_common;                          \
+label##_common:                                         \
+        EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
+        FINISH_NAP;                                     \
+        DISABLE_INTS;                                   \
+BEGIN_FTR_SECTION                                       \
+        bl      .ppc64_runlatch_on;                     \
+END_FTR_SECTION_IFSET(CPU_FTR_CTRL)                     \
+        addi    r3,r1,STACK_FRAME_OVERHEAD;             \
+        bl      hdlr;                                   \
+        b       .ret_from_except_lite
+
+/*
+ * When the idle code in power4_idle puts the CPU into NAP mode,
+ * it has to do so in a loop, and relies on the external interrupt
+ * and decrementer interrupt entry code to get it out of the loop.
+ * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
+ * to signal that it is in the loop and needs help to get out.
+ */
+#ifdef CONFIG_PPC_970_NAP
+#define FINISH_NAP                              \
+BEGIN_FTR_SECTION                               \
+        clrrdi  r11,r1,THREAD_SHIFT;            \
+        ld      r9,TI_LOCAL_FLAGS(r11);         \
+        andi.   r10,r9,_TLF_NAPPING;            \
+        bnel    power4_fixup_nap;               \
+END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
+#else
+#define FINISH_NAP
+#endif
+
+#endif  /* _ASM_POWERPC_EXCEPTION_H */
diff --git a/arch/powerpc/include/asm/fb.h b/arch/powerpc/include/asm/fb.h
new file mode 100644
index 000000000000..411af8d17a69
--- /dev/null
+++ b/arch/powerpc/include/asm/fb.h
@@ -0,0 +1,21 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+        vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT,
+                                                 vma->vm_end - vma->vm_start,
+                                                 vma->vm_page_prot);
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/powerpc/include/asm/fcntl.h b/arch/powerpc/include/asm/fcntl.h
new file mode 100644
index 000000000000..ce5c4516d404
--- /dev/null
+++ b/arch/powerpc/include/asm/fcntl.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_FCNTL_H
+#define _ASM_FCNTL_H
+
+#define O_DIRECTORY      040000 /* must be a directory */
+#define O_NOFOLLOW      0100000 /* don't follow links */
+#define O_LARGEFILE     0200000
+#define O_DIRECT        0400000 /* direct disk access hint */
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _ASM_FCNTL_H */
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
new file mode 100644
index 000000000000..a1029967620b
--- /dev/null
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -0,0 +1,126 @@
+#ifndef __ASM_POWERPC_FEATURE_FIXUPS_H
+#define __ASM_POWERPC_FEATURE_FIXUPS_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifdef __ASSEMBLY__
+
+/*
+ * Feature section common macros
+ *
+ * Note that the entries now contain offsets between the table entry
+ * and the code rather than absolute code pointers in order to be
+ * useable with the vdso shared library. There is also an assumption
+ * that values will be negative, that is, the fixup table has to be
+ * located after the code it fixes up.
+ */
+#if defined(CONFIG_PPC64) && !defined(__powerpc64__)
+/* 64 bits kernel, 32 bits code (ie. vdso32) */
+#define FTR_ENTRY_LONG          .llong
+#define FTR_ENTRY_OFFSET        .long 0xffffffff; .long
+#else
+/* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */
+#define FTR_ENTRY_LONG          PPC_LONG
+#define FTR_ENTRY_OFFSET        PPC_LONG
+#endif
+
+#define START_FTR_SECTION(label)        label##1:
+
+#define FTR_SECTION_ELSE_NESTED(label)                  \
+label##2:                                               \
+        .pushsection __ftr_alt_##label,"a";             \
+        .align 2;                                       \
+label##3:
+
+#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)   \
+label##4:                                               \
+        .popsection;                                    \
+        .pushsection sect,"a";                          \
+        .align 3;                                       \
+label##5:                                               \
+        FTR_ENTRY_LONG msk;                             \
+        FTR_ENTRY_LONG val;                             \
+        FTR_ENTRY_OFFSET label##1b-label##5b;           \
+        FTR_ENTRY_OFFSET label##2b-label##5b;           \
+        FTR_ENTRY_OFFSET label##3b-label##5b;           \
+        FTR_ENTRY_OFFSET label##4b-label##5b;           \
+        .popsection;
+
+
+/* CPU feature dependent sections */
+#define BEGIN_FTR_SECTION_NESTED(label) START_FTR_SECTION(label)
+#define BEGIN_FTR_SECTION               START_FTR_SECTION(97)
+
+#define END_FTR_SECTION_NESTED(msk, val, label)                 \
+        FTR_SECTION_ELSE_NESTED(label)                          \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
+
+#define END_FTR_SECTION(msk, val)               \
+        END_FTR_SECTION_NESTED(msk, val, 97)
+
+#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
+#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
+
+/* CPU feature sections with alternatives, use BEGIN_FTR_SECTION to start */
+#define FTR_SECTION_ELSE        FTR_SECTION_ELSE_NESTED(97)
+#define ALT_FTR_SECTION_END_NESTED(msk, val, label)     \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
+#define ALT_FTR_SECTION_END_NESTED_IFSET(msk, label)    \
+        ALT_FTR_SECTION_END_NESTED(msk, msk, label)
+#define ALT_FTR_SECTION_END_NESTED_IFCLR(msk, label)    \
+        ALT_FTR_SECTION_END_NESTED(msk, 0, label)
+#define ALT_FTR_SECTION_END(msk, val)   \
+        ALT_FTR_SECTION_END_NESTED(msk, val, 97)
+#define ALT_FTR_SECTION_END_IFSET(msk)  \
+        ALT_FTR_SECTION_END_NESTED_IFSET(msk, 97)
+#define ALT_FTR_SECTION_END_IFCLR(msk)  \
+        ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
+
+/* Firmware feature dependent sections */
+#define BEGIN_FW_FTR_SECTION_NESTED(label)      START_FTR_SECTION(label)
+#define BEGIN_FW_FTR_SECTION                    START_FTR_SECTION(97)
+
+#define END_FW_FTR_SECTION_NESTED(msk, val, label)              \
+        FTR_SECTION_ELSE_NESTED(label)                          \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
+
+#define END_FW_FTR_SECTION(msk, val)            \
+        END_FW_FTR_SECTION_NESTED(msk, val, 97)
+
+#define END_FW_FTR_SECTION_IFSET(msk)   END_FW_FTR_SECTION((msk), (msk))
+#define END_FW_FTR_SECTION_IFCLR(msk)   END_FW_FTR_SECTION((msk), 0)
+
+/* Firmware feature sections with alternatives */
+#define FW_FTR_SECTION_ELSE_NESTED(label)       FTR_SECTION_ELSE_NESTED(label)
+#define FW_FTR_SECTION_ELSE     FTR_SECTION_ELSE_NESTED(97)
+#define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label)  \
+        MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
+#define ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, label) \
+        ALT_FW_FTR_SECTION_END_NESTED(msk, msk, label)
+#define ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, label) \
+        ALT_FW_FTR_SECTION_END_NESTED(msk, 0, label)
+#define ALT_FW_FTR_SECTION_END(msk, val)        \
+        ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97)
+#define ALT_FW_FTR_SECTION_END_IFSET(msk)       \
+        ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, 97)
+#define ALT_FW_FTR_SECTION_END_IFCLR(msk)       \
+        ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
+
+#endif /* __ASSEMBLY__ */
+
+/* LWSYNC feature sections */
+#define START_LWSYNC_SECTION(label)     label##1:
+#define MAKE_LWSYNC_SECTION_ENTRY(label, sect)          \
+label##2:                                               \
+        .pushsection sect,"a";                          \
+        .align 2;                                       \
+label##3:                                               \
+        .long label##1b-label##3b;                      \
+        .popsection;
+
+#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
new file mode 100644
index 000000000000..3a179827528d
--- /dev/null
+++ b/arch/powerpc/include/asm/firmware.h
@@ -0,0 +1,132 @@
+/*
+ *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
+ *
+ *  Modifications for ppc64:
+ *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_POWERPC_FIRMWARE_H
+#define __ASM_POWERPC_FIRMWARE_H
+
+#ifdef __KERNEL__
+
+#include <asm/asm-compat.h>
+#include <asm/feature-fixups.h>
+
+/* firmware feature bitmask values */
+#define FIRMWARE_MAX_FEATURES 63
+
+#define FW_FEATURE_PFT          ASM_CONST(0x0000000000000001)
+#define FW_FEATURE_TCE          ASM_CONST(0x0000000000000002)
+#define FW_FEATURE_SPRG0        ASM_CONST(0x0000000000000004)
+#define FW_FEATURE_DABR         ASM_CONST(0x0000000000000008)
+#define FW_FEATURE_COPY         ASM_CONST(0x0000000000000010)
+#define FW_FEATURE_ASR          ASM_CONST(0x0000000000000020)
+#define FW_FEATURE_DEBUG        ASM_CONST(0x0000000000000040)
+#define FW_FEATURE_TERM         ASM_CONST(0x0000000000000080)
+#define FW_FEATURE_PERF         ASM_CONST(0x0000000000000100)
+#define FW_FEATURE_DUMP         ASM_CONST(0x0000000000000200)
+#define FW_FEATURE_INTERRUPT    ASM_CONST(0x0000000000000400)
+#define FW_FEATURE_MIGRATE      ASM_CONST(0x0000000000000800)
+#define FW_FEATURE_PERFMON      ASM_CONST(0x0000000000001000)
+#define FW_FEATURE_CRQ          ASM_CONST(0x0000000000002000)
+#define FW_FEATURE_VIO          ASM_CONST(0x0000000000004000)
+#define FW_FEATURE_RDMA         ASM_CONST(0x0000000000008000)
+#define FW_FEATURE_LLAN         ASM_CONST(0x0000000000010000)
+#define FW_FEATURE_BULK         ASM_CONST(0x0000000000020000)
+#define FW_FEATURE_XDABR        ASM_CONST(0x0000000000040000)
+#define FW_FEATURE_MULTITCE     ASM_CONST(0x0000000000080000)
+#define FW_FEATURE_SPLPAR       ASM_CONST(0x0000000000100000)
+#define FW_FEATURE_ISERIES      ASM_CONST(0x0000000000200000)
+#define FW_FEATURE_LPAR         ASM_CONST(0x0000000000400000)
+#define FW_FEATURE_PS3_LV1      ASM_CONST(0x0000000000800000)
+#define FW_FEATURE_BEAT         ASM_CONST(0x0000000001000000)
+#define FW_FEATURE_BULK_REMOVE  ASM_CONST(0x0000000002000000)
+#define FW_FEATURE_CMO          ASM_CONST(0x0000000004000000)
+
+#ifndef __ASSEMBLY__
+
+enum {
+#ifdef CONFIG_PPC64
+        FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE |
+                FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY |
+                FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM |
+                FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT |
+                FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ |
+                FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
+                FW_FEATURE_BULK | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE |
+                FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | FW_FEATURE_CMO,
+        FW_FEATURE_PSERIES_ALWAYS = 0,
+        FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
+        FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
+        FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
+        FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
+        FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
+        FW_FEATURE_CELLEB_ALWAYS = 0,
+        FW_FEATURE_NATIVE_POSSIBLE = 0,
+        FW_FEATURE_NATIVE_ALWAYS = 0,
+        FW_FEATURE_POSSIBLE =
+#ifdef CONFIG_PPC_PSERIES
+                FW_FEATURE_PSERIES_POSSIBLE |
+#endif
+#ifdef CONFIG_PPC_ISERIES
+                FW_FEATURE_ISERIES_POSSIBLE |
+#endif
+#ifdef CONFIG_PPC_PS3
+                FW_FEATURE_PS3_POSSIBLE |
+#endif
+#ifdef CONFIG_PPC_CELLEB
+                FW_FEATURE_CELLEB_POSSIBLE |
+#endif
+#ifdef CONFIG_PPC_NATIVE
+                FW_FEATURE_NATIVE_ALWAYS |
+#endif
+                0,
+        FW_FEATURE_ALWAYS =
+#ifdef CONFIG_PPC_PSERIES
+                FW_FEATURE_PSERIES_ALWAYS &
+#endif
+#ifdef CONFIG_PPC_ISERIES
+                FW_FEATURE_ISERIES_ALWAYS &
+#endif
+#ifdef CONFIG_PPC_PS3
+                FW_FEATURE_PS3_ALWAYS &
+#endif
+#ifdef CONFIG_PPC_CELLEB
+                FW_FEATURE_CELLEB_ALWAYS &
+#endif
+#ifdef CONFIG_PPC_NATIVE
+                FW_FEATURE_NATIVE_ALWAYS &
+#endif
+                FW_FEATURE_POSSIBLE,
+
+#else /* CONFIG_PPC64 */
+        FW_FEATURE_POSSIBLE = 0,
+        FW_FEATURE_ALWAYS = 0,
+#endif
+};
+
+/* This is used to identify firmware features which are available
+ * to the kernel.
+ */
+extern unsigned long    powerpc_firmware_features;
+
+#define firmware_has_feature(feature)                                   \
+        ((FW_FEATURE_ALWAYS & (feature)) ||                             \
+                (FW_FEATURE_POSSIBLE & powerpc_firmware_features & (feature)))
+
+extern void system_reset_fwnmi(void);
+extern void machine_check_fwnmi(void);
+
+/* This is true if we are using the firmware NMI handler (typically LPAR) */
+extern int fwnmi_active;
+
+extern unsigned int __start___fw_ftr_fixup, __stop___fw_ftr_fixup;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
new file mode 100644
index 000000000000..8428b38a3d30
--- /dev/null
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -0,0 +1,106 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Copyright 2008 Freescale Semiconductor Inc.
+ *   Port to powerpc added by Kumar Gala
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+extern unsigned long FIXADDR_TOP;
+
+#ifndef __ASSEMBLY__
+#include <linux/kernel.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special addresses
+ * from the end of virtual memory (0xfffff000) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+enum fixed_addresses {
+        FIX_HOLE,
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        /* FIX_PCIE_MCFG, */
+        __end_of_fixed_addresses
+};
+
+extern void __set_fixmap (enum fixed_addresses idx,
+                                        phys_addr_t phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
+
+#define clear_fixmap(idx) \
+                __set_fixmap(idx, 0, __pgprot(0))
+
+#define __FIXADDR_SIZE  (__end_of_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START           (FIXADDR_TOP - __FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static __always_inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+#endif /* !__ASSEMBLY__ */
+#endif
diff --git a/arch/powerpc/include/asm/floppy.h b/arch/powerpc/include/asm/floppy.h
new file mode 100644
index 000000000000..24bd34c57e9d
--- /dev/null
+++ b/arch/powerpc/include/asm/floppy.h
@@ -0,0 +1,213 @@
+/*
+ * Architecture specific parts of the Floppy driver
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995
+ */
+#ifndef __ASM_POWERPC_FLOPPY_H
+#define __ASM_POWERPC_FLOPPY_H
+#ifdef __KERNEL__
+
+#include <asm/machdep.h>
+
+#define fd_inb(port)            inb_p(port)
+#define fd_outb(value,port)     outb_p(value,port)
+
+#define fd_enable_dma()         enable_dma(FLOPPY_DMA)
+#define fd_disable_dma()         fd_ops->_disable_dma(FLOPPY_DMA)
+#define fd_free_dma()           fd_ops->_free_dma(FLOPPY_DMA)
+#define fd_clear_dma_ff()       clear_dma_ff(FLOPPY_DMA)
+#define fd_set_dma_mode(mode)   set_dma_mode(FLOPPY_DMA, mode)
+#define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA, count)
+#define fd_get_dma_residue()    fd_ops->_get_dma_residue(FLOPPY_DMA)
+#define fd_enable_irq()         enable_irq(FLOPPY_IRQ)
+#define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
+#define fd_cacheflush(addr,size) /* nothing */
+#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
+
+#include <linux/pci.h>
+#include <asm/ppc-pci.h>        /* for isa_bridge_pcidev */
+
+#define fd_dma_setup(addr,size,mode,io) fd_ops->_dma_setup(addr,size,mode,io)
+
+static int fd_request_dma(void);
+
+struct fd_dma_ops {
+        void (*_disable_dma)(unsigned int dmanr);
+        void (*_free_dma)(unsigned int dmanr);
+        int (*_get_dma_residue)(unsigned int dummy);
+        int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
+};
+
+static int virtual_dma_count;
+static int virtual_dma_residue;
+static char *virtual_dma_addr;
+static int virtual_dma_mode;
+static int doing_vdma;
+static struct fd_dma_ops *fd_ops;
+
+static irqreturn_t floppy_hardint(int irq, void *dev_id)
+{
+        unsigned char st;
+        int lcount;
+        char *lptr;
+
+        if (!doing_vdma)
+                return floppy_interrupt(irq, dev_id);
+
+
+        st = 1;
+        for (lcount=virtual_dma_count, lptr=virtual_dma_addr;
+             lcount; lcount--, lptr++) {
+                st=inb(virtual_dma_port+4) & 0xa0 ;
+                if (st != 0xa0)
+                        break;
+                if (virtual_dma_mode)
+                        outb_p(*lptr, virtual_dma_port+5);
+                else
+                        *lptr = inb_p(virtual_dma_port+5);
+        }
+        virtual_dma_count = lcount;
+        virtual_dma_addr = lptr;
+        st = inb(virtual_dma_port+4);
+
+        if (st == 0x20)
+                return IRQ_HANDLED;
+        if (!(st & 0x20)) {
+                virtual_dma_residue += virtual_dma_count;
+                virtual_dma_count=0;
+                doing_vdma = 0;
+                floppy_interrupt(irq, dev_id);
+                return IRQ_HANDLED;
+        }
+        return IRQ_HANDLED;
+}
+
+static void vdma_disable_dma(unsigned int dummy)
+{
+        doing_vdma = 0;
+        virtual_dma_residue += virtual_dma_count;
+        virtual_dma_count=0;
+}
+
+static void vdma_nop(unsigned int dummy)
+{
+}
+
+
+static int vdma_get_dma_residue(unsigned int dummy)
+{
+        return virtual_dma_count + virtual_dma_residue;
+}
+
+
+static int fd_request_irq(void)
+{
+        if (can_use_virtual_dma)
+                return request_irq(FLOPPY_IRQ, floppy_hardint,
+                                   IRQF_DISABLED, "floppy", NULL);
+        else
+                return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                                   IRQF_DISABLED, "floppy", NULL);
+}
+
+static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
+{
+        doing_vdma = 1;
+        virtual_dma_port = io;
+        virtual_dma_mode = (mode  == DMA_MODE_WRITE);
+        virtual_dma_addr = addr;
+        virtual_dma_count = size;
+        virtual_dma_residue = 0;
+        return 0;
+}
+
+static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
+{
+        static unsigned long prev_size;
+        static dma_addr_t bus_addr = 0;
+        static char *prev_addr;
+        static int prev_dir;
+        int dir;
+
+        doing_vdma = 0;
+        dir = (mode == DMA_MODE_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE;
+
+        if (bus_addr 
+            && (addr != prev_addr || size != prev_size || dir != prev_dir)) {
+                /* different from last time -- unmap prev */
+                pci_unmap_single(isa_bridge_pcidev, bus_addr, prev_size, prev_dir);
+                bus_addr = 0;
+        }
+
+        if (!bus_addr)  /* need to map it */
+                bus_addr = pci_map_single(isa_bridge_pcidev, addr, size, dir);
+
+        /* remember this one as prev */
+        prev_addr = addr;
+        prev_size = size;
+        prev_dir = dir;
+
+        fd_clear_dma_ff();
+        fd_cacheflush(addr, size);
+        fd_set_dma_mode(mode);
+        set_dma_addr(FLOPPY_DMA, bus_addr);
+        fd_set_dma_count(size);
+        virtual_dma_port = io;
+        fd_enable_dma();
+
+        return 0;
+}
+
+static struct fd_dma_ops real_dma_ops =
+{
+        ._disable_dma = disable_dma,
+        ._free_dma = free_dma,
+        ._get_dma_residue = get_dma_residue,
+        ._dma_setup = hard_dma_setup
+};
+
+static struct fd_dma_ops virt_dma_ops =
+{
+        ._disable_dma = vdma_disable_dma,
+        ._free_dma = vdma_nop,
+        ._get_dma_residue = vdma_get_dma_residue,
+        ._dma_setup = vdma_dma_setup
+};
+
+static int fd_request_dma(void)
+{
+        if (can_use_virtual_dma & 1) {
+                fd_ops = &virt_dma_ops;
+                return 0;
+        }
+        else {
+                fd_ops = &real_dma_ops;
+                return request_dma(FLOPPY_DMA, "floppy");
+        }
+}
+
+static int FDC1 = 0x3f0;
+static int FDC2 = -1;
+
+/*
+ * Again, the CMOS information not available
+ */
+#define FLOPPY0_TYPE 6
+#define FLOPPY1_TYPE 0
+
+#define N_FDC 2                 /* Don't change this! */
+#define N_DRIVE 8
+
+/*
+ * The PowerPC has no problems with floppy DMA crossing 64k borders.
+ */
+#define CROSS_64KB(a,s) (0)
+
+#define EXTRA_FLOPPY_PARAMS
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_FLOPPY_H */
diff --git a/arch/powerpc/include/asm/fs_pd.h b/arch/powerpc/include/asm/fs_pd.h
new file mode 100644
index 000000000000..9361cd5342cc
--- /dev/null
+++ b/arch/powerpc/include/asm/fs_pd.h
@@ -0,0 +1,50 @@
+/*
+ * Platform information definitions.
+ *
+ * 2006 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef FS_PD_H
+#define FS_PD_H
+#include <sysdev/fsl_soc.h>
+#include <asm/time.h>
+
+#ifdef CONFIG_CPM2
+#include <asm/cpm2.h>
+
+#if defined(CONFIG_8260)
+#include <asm/mpc8260.h>
+#endif
+
+#define cpm2_map(member) (&cpm2_immr->member)
+#define cpm2_map_size(member, size) (&cpm2_immr->member)
+#define cpm2_unmap(addr) do {} while(0)
+#endif
+
+#ifdef CONFIG_8xx
+#include <asm/8xx_immap.h>
+#include <asm/mpc8xx.h>
+
+extern immap_t __iomem *mpc8xx_immr;
+
+#define immr_map(member) (&mpc8xx_immr->member)
+#define immr_map_size(member, size) (&mpc8xx_immr->member)
+#define immr_unmap(addr) do {} while (0)
+#endif
+
+static inline int uart_baudrate(void)
+{
+        return get_baudrate();
+}
+
+static inline int uart_clock(void)
+{
+        return ppc_proc_freq;
+}
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_gtm.h b/arch/powerpc/include/asm/fsl_gtm.h
new file mode 100644
index 000000000000..8e8c9b5032d3
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_gtm.h
@@ -0,0 +1,47 @@
+/*
+ * Freescale General-purpose Timers Module
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ *               Shlomi Gridish <gridish@freescale.com>
+ *               Jerry Huang <Chang-Ming.Huang@freescale.com>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *               Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_FSL_GTM_H
+#define __ASM_FSL_GTM_H
+
+#include <linux/types.h>
+
+struct gtm;
+
+struct gtm_timer {
+        unsigned int irq;
+
+        struct gtm *gtm;
+        bool requested;
+        u8 __iomem *gtcfr;
+        __be16 __iomem *gtmdr;
+        __be16 __iomem *gtpsr;
+        __be16 __iomem *gtcnr;
+        __be16 __iomem *gtrfr;
+        __be16 __iomem *gtevr;
+};
+
+extern struct gtm_timer *gtm_get_timer16(void);
+extern struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm,
+                                                  unsigned int timer);
+extern void gtm_put_timer16(struct gtm_timer *tmr);
+extern int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec,
+                             bool reload);
+extern int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec,
+                                 bool reload);
+extern void gtm_stop_timer16(struct gtm_timer *tmr);
+extern void gtm_ack_timer16(struct gtm_timer *tmr, u16 events);
+
+#endif /* __ASM_FSL_GTM_H */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
new file mode 100644
index 000000000000..303f5484c050
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -0,0 +1,311 @@
+/* Freescale Local Bus Controller
+ *
+ * Copyright (c) 2006-2007 Freescale Semiconductor
+ *
+ * Authors: Nick Spence <nick.spence@freescale.com>,
+ *          Scott Wood <scottwood@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_FSL_LBC_H
+#define __ASM_FSL_LBC_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+
+struct fsl_lbc_bank {
+        __be32 br;             /**< Base Register  */
+#define BR_BA           0xFFFF8000
+#define BR_BA_SHIFT             15
+#define BR_PS           0x00001800
+#define BR_PS_SHIFT             11
+#define BR_PS_8         0x00000800  /* Port Size 8 bit */
+#define BR_PS_16        0x00001000  /* Port Size 16 bit */
+#define BR_PS_32        0x00001800  /* Port Size 32 bit */
+#define BR_DECC         0x00000600
+#define BR_DECC_SHIFT            9
+#define BR_DECC_OFF     0x00000000  /* HW ECC checking and generation off */
+#define BR_DECC_CHK     0x00000200  /* HW ECC checking on, generation off */
+#define BR_DECC_CHK_GEN 0x00000400  /* HW ECC checking and generation on */
+#define BR_WP           0x00000100
+#define BR_WP_SHIFT              8
+#define BR_MSEL         0x000000E0
+#define BR_MSEL_SHIFT            5
+#define BR_MS_GPCM      0x00000000  /* GPCM */
+#define BR_MS_FCM       0x00000020  /* FCM */
+#define BR_MS_SDRAM     0x00000060  /* SDRAM */
+#define BR_MS_UPMA      0x00000080  /* UPMA */
+#define BR_MS_UPMB      0x000000A0  /* UPMB */
+#define BR_MS_UPMC      0x000000C0  /* UPMC */
+#define BR_V            0x00000001
+#define BR_V_SHIFT               0
+#define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+        __be32 or;             /**< Base Register  */
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_FCM_AM               0xFFFF8000
+#define OR_FCM_AM_SHIFT                 15
+#define OR_FCM_BCTLD            0x00001000
+#define OR_FCM_BCTLD_SHIFT              12
+#define OR_FCM_PGS              0x00000400
+#define OR_FCM_PGS_SHIFT                10
+#define OR_FCM_CSCT             0x00000200
+#define OR_FCM_CSCT_SHIFT                9
+#define OR_FCM_CST              0x00000100
+#define OR_FCM_CST_SHIFT                 8
+#define OR_FCM_CHT              0x00000080
+#define OR_FCM_CHT_SHIFT                 7
+#define OR_FCM_SCY              0x00000070
+#define OR_FCM_SCY_SHIFT                 4
+#define OR_FCM_SCY_1            0x00000010
+#define OR_FCM_SCY_2            0x00000020
+#define OR_FCM_SCY_3            0x00000030
+#define OR_FCM_SCY_4            0x00000040
+#define OR_FCM_SCY_5            0x00000050
+#define OR_FCM_SCY_6            0x00000060
+#define OR_FCM_SCY_7            0x00000070
+#define OR_FCM_RST              0x00000008
+#define OR_FCM_RST_SHIFT                 3
+#define OR_FCM_TRLX             0x00000004
+#define OR_FCM_TRLX_SHIFT                2
+#define OR_FCM_EHTR             0x00000002
+#define OR_FCM_EHTR_SHIFT                1
+};
+
+struct fsl_lbc_regs {
+        struct fsl_lbc_bank bank[8];
+        u8 res0[0x28];
+        __be32 mar;             /**< UPM Address Register */
+        u8 res1[0x4];
+        __be32 mamr;            /**< UPMA Mode Register */
+#define MxMR_OP_NO      (0 << 28) /**< normal operation */
+#define MxMR_OP_WA      (1 << 28) /**< write array */
+#define MxMR_OP_RA      (2 << 28) /**< read array */
+#define MxMR_OP_RP      (3 << 28) /**< run pattern */
+#define MxMR_MAD        0x3f      /**< machine address */
+        __be32 mbmr;            /**< UPMB Mode Register */
+        __be32 mcmr;            /**< UPMC Mode Register */
+        u8 res2[0x8];
+        __be32 mrtpr;           /**< Memory Refresh Timer Prescaler Register */
+        __be32 mdr;             /**< UPM Data Register */
+        u8 res3[0x4];
+        __be32 lsor;            /**< Special Operation Initiation Register */
+        __be32 lsdmr;           /**< SDRAM Mode Register */
+        u8 res4[0x8];
+        __be32 lurt;            /**< UPM Refresh Timer */
+        __be32 lsrt;            /**< SDRAM Refresh Timer */
+        u8 res5[0x8];
+        __be32 ltesr;           /**< Transfer Error Status Register */
+#define LTESR_BM   0x80000000
+#define LTESR_FCT  0x40000000
+#define LTESR_PAR  0x20000000
+#define LTESR_WP   0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS   0x00080000
+#define LTESR_CC   0x00000001
+#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+        __be32 ltedr;           /**< Transfer Error Disable Register */
+        __be32 lteir;           /**< Transfer Error Interrupt Register */
+        __be32 lteatr;          /**< Transfer Error Attributes Register */
+        __be32 ltear;           /**< Transfer Error Address Register */
+        u8 res6[0xC];
+        __be32 lbcr;            /**< Configuration Register */
+#define LBCR_LDIS  0x80000000
+#define LBCR_LDIS_SHIFT    31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT   22
+#define LBCR_AHD   0x00200000
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT   17
+#define LBCR_EPAR  0x00010000
+#define LBCR_EPAR_SHIFT    16
+#define LBCR_BMT   0x0000FF00
+#define LBCR_BMT_SHIFT      8
+#define LBCR_INIT  0x00040000
+        __be32 lcrr;            /**< Clock Ratio Register */
+#define LCRR_DBYP    0x80000000
+#define LCRR_DBYP_SHIFT      31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT   28
+#define LCRR_ECL     0x03000000
+#define LCRR_ECL_SHIFT       24
+#define LCRR_EADC    0x00030000
+#define LCRR_EADC_SHIFT      16
+#define LCRR_CLKDIV  0x0000000F
+#define LCRR_CLKDIV_SHIFT     0
+        u8 res7[0x8];
+        __be32 fmr;             /**< Flash Mode Register */
+#define FMR_CWTO     0x0000F000
+#define FMR_CWTO_SHIFT       12
+#define FMR_BOOT     0x00000800
+#define FMR_ECCM     0x00000100
+#define FMR_AL       0x00000030
+#define FMR_AL_SHIFT          4
+#define FMR_OP       0x00000003
+#define FMR_OP_SHIFT          0
+        __be32 fir;             /**< Flash Instruction Register */
+#define FIR_OP0      0xF0000000
+#define FIR_OP0_SHIFT        28
+#define FIR_OP1      0x0F000000
+#define FIR_OP1_SHIFT        24
+#define FIR_OP2      0x00F00000
+#define FIR_OP2_SHIFT        20
+#define FIR_OP3      0x000F0000
+#define FIR_OP3_SHIFT        16
+#define FIR_OP4      0x0000F000
+#define FIR_OP4_SHIFT        12
+#define FIR_OP5      0x00000F00
+#define FIR_OP5_SHIFT         8
+#define FIR_OP6      0x000000F0
+#define FIR_OP6_SHIFT         4
+#define FIR_OP7      0x0000000F
+#define FIR_OP7_SHIFT         0
+#define FIR_OP_NOP   0x0        /* No operation and end of sequence */
+#define FIR_OP_CA    0x1        /* Issue current column address */
+#define FIR_OP_PA    0x2        /* Issue current block+page address */
+#define FIR_OP_UA    0x3        /* Issue user defined address */
+#define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
+#define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
+        __be32 fcr;             /**< Flash Command Register */
+#define FCR_CMD0     0xFF000000
+#define FCR_CMD0_SHIFT       24
+#define FCR_CMD1     0x00FF0000
+#define FCR_CMD1_SHIFT       16
+#define FCR_CMD2     0x0000FF00
+#define FCR_CMD2_SHIFT        8
+#define FCR_CMD3     0x000000FF
+#define FCR_CMD3_SHIFT        0
+        __be32 fbar;            /**< Flash Block Address Register */
+#define FBAR_BLK     0x00FFFFFF
+        __be32 fpar;            /**< Flash Page Address Register */
+#define FPAR_SP_PI   0x00007C00
+#define FPAR_SP_PI_SHIFT     10
+#define FPAR_SP_MS   0x00000200
+#define FPAR_SP_CI   0x000001FF
+#define FPAR_SP_CI_SHIFT      0
+#define FPAR_LP_PI   0x0003F000
+#define FPAR_LP_PI_SHIFT     12
+#define FPAR_LP_MS   0x00000800
+#define FPAR_LP_CI   0x000007FF
+#define FPAR_LP_CI_SHIFT      0
+        __be32 fbcr;            /**< Flash Byte Count Register */
+#define FBCR_BC      0x00000FFF
+        u8 res11[0x8];
+        u8 res8[0xF00];
+};
+
+extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+extern spinlock_t fsl_lbc_lock;
+
+/*
+ * FSL UPM routines
+ */
+struct fsl_upm {
+        __be32 __iomem *mxmr;
+        int width;
+};
+
+extern int fsl_lbc_find(phys_addr_t addr_base);
+extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
+
+/**
+ * fsl_upm_start_pattern - start UPM patterns execution
+ * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
+ * @pat_offset: UPM pattern offset for the command to be executed
+ *
+ * This routine programmes UPM so the next memory access that hits an UPM
+ * will trigger pattern execution, starting at pat_offset.
+ */
+static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
+{
+        clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
+}
+
+/**
+ * fsl_upm_end_pattern - end UPM patterns execution
+ * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
+ *
+ * This routine reverts UPM to normal operation mode.
+ */
+static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
+{
+        clrbits32(upm->mxmr, MxMR_OP_RP);
+
+        while (in_be32(upm->mxmr) & MxMR_OP_RP)
+                cpu_relax();
+}
+
+/**
+ * fsl_upm_run_pattern - actually run an UPM pattern
+ * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
+ * @io_base:    remapped pointer to where memory access should happen
+ * @mar:        MAR register content during pattern execution
+ *
+ * This function triggers dummy write to the memory specified by the io_base,
+ * thus UPM pattern actually executed. Note that mar usage depends on the
+ * pre-programmed AMX bits in the UPM RAM.
+ */
+static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
+                                      void __iomem *io_base, u32 mar)
+{
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&fsl_lbc_lock, flags);
+
+        out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
+
+        switch (upm->width) {
+        case 8:
+                out_8(io_base, 0x0);
+                break;
+        case 16:
+                out_be16(io_base, 0x0);
+                break;
+        case 32:
+                out_be32(io_base, 0x0);
+                break;
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        spin_unlock_irqrestore(&fsl_lbc_lock, flags);
+
+        return ret;
+}
+
+#endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/include/asm/ftrace.h b/arch/powerpc/include/asm/ftrace.h
new file mode 100644
index 000000000000..de921326cca8
--- /dev/null
+++ b/arch/powerpc/include/asm/ftrace.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_POWERPC_FTRACE
+#define _ASM_POWERPC_FTRACE
+
+#ifdef CONFIG_FTRACE
+#define MCOUNT_ADDR             ((long)(_mcount))
+#define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#endif
+
+#endif
+
+#endif /* _ASM_POWERPC_FTRACE */
diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
new file mode 100644
index 000000000000..6d406c5c5de4
--- /dev/null
+++ b/arch/powerpc/include/asm/futex.h
@@ -0,0 +1,117 @@
+#ifndef _ASM_POWERPC_FUTEX_H
+#define _ASM_POWERPC_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+#include <asm/synch.h>
+#include <asm/asm-compat.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
+  __asm__ __volatile ( \
+        LWSYNC_ON_SMP \
+"1:     lwarx   %0,0,%2\n" \
+        insn \
+        PPC405_ERR77(0, %2) \
+"2:     stwcx.  %1,0,%2\n" \
+        "bne-   1b\n" \
+        "li     %1,0\n" \
+"3:     .section .fixup,\"ax\"\n" \
+"4:     li      %1,%3\n" \
+        "b      3b\n" \
+        ".previous\n" \
+        ".section __ex_table,\"a\"\n" \
+        ".align 3\n" \
+        PPC_LONG "1b,4b,2b,4b\n" \
+        ".previous" \
+        : "=&r" (oldval), "=&r" (ret) \
+        : "b" (uaddr), "i" (-EFAULT), "1" (oparg) \
+        : "cr0", "memory")
+
+static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("add %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("or %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("andc %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("xor %1,%0,%1\n", ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        int prev;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        __asm__ __volatile__ (
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%2         # futex_atomic_cmpxchg_inatomic\n\
+        cmpw    0,%0,%3\n\
+        bne-    3f\n"
+        PPC405_ERR77(0,%2)
+"2:     stwcx.  %4,0,%2\n\
+        bne-    1b\n"
+        ISYNC_ON_SMP
+"3:     .section .fixup,\"ax\"\n\
+4:      li      %0,%5\n\
+        b       3b\n\
+        .previous\n\
+        .section __ex_table,\"a\"\n\
+        .align 3\n\
+        " PPC_LONG "1b,4b,2b,4b\n\
+        .previous" \
+        : "=&r" (prev), "+m" (*uaddr)
+        : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
+        : "cc", "memory");
+
+        return prev;
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_FUTEX_H */
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
new file mode 100644
index 000000000000..ea04632399d8
--- /dev/null
+++ b/arch/powerpc/include/asm/gpio.h
@@ -0,0 +1,56 @@
+/*
+ * Generic GPIO API implementation for PowerPC.
+ *
+ * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_GPIO_H
+#define __ASM_POWERPC_GPIO_H
+
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_GPIOLIB
+
+/*
+ * We don't (yet) implement inlined/rapid versions for on-chip gpios.
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+/*
+ * Not implemented, yet.
+ */
+static inline int gpio_to_irq(unsigned int gpio)
+{
+        return -ENOSYS;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        return -EINVAL;
+}
+
+#endif /* CONFIG_GPIOLIB */
+
+#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/arch/powerpc/include/asm/grackle.h b/arch/powerpc/include/asm/grackle.h
new file mode 100644
index 000000000000..bd7812a519d4
--- /dev/null
+++ b/arch/powerpc/include/asm/grackle.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_POWERPC_GRACKLE_H
+#define _ASM_POWERPC_GRACKLE_H
+#ifdef __KERNEL__
+/*
+ * Functions for setting up and using a MPC106 northbridge
+ */
+
+#include <asm/pci-bridge.h>
+
+extern void setup_grackle(struct pci_controller *hose);
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_GRACKLE_H */
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
new file mode 100644
index 000000000000..288e14d53b7f
--- /dev/null
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -0,0 +1,29 @@
+#ifndef _ASM_POWERPC_HARDIRQ_H
+#define _ASM_POWERPC_HARDIRQ_H
+#ifdef __KERNEL__
+
+#include <asm/irq.h>
+#include <asm/bug.h>
+
+/* The __last_jiffy_stamp field is needed to ensure that no decrementer
+ * interrupt is lost on SMP machines. Since on most CPUs it is in the same
+ * cache line as local_irq_count, it is cheap to access and is also used on UP
+ * for uniformity.
+ */
+typedef struct {
+        unsigned int __softirq_pending; /* set_bit is used on this */
+        unsigned int __last_jiffy_stamp;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
+
+static inline void ack_bad_irq(int irq)
+{
+        printk(KERN_CRIT "illegal vector %d received!\n", irq);
+        BUG();
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/arch/powerpc/include/asm/heathrow.h b/arch/powerpc/include/asm/heathrow.h
new file mode 100644
index 000000000000..93f54958a9d1
--- /dev/null
+++ b/arch/powerpc/include/asm/heathrow.h
@@ -0,0 +1,67 @@
+#ifndef _ASM_POWERPC_HEATHROW_H
+#define _ASM_POWERPC_HEATHROW_H
+#ifdef __KERNEL__
+/*
+ * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
+ *
+ * Grabbed from Open Firmware definitions on a PowerBook G3 Series
+ *
+ * Copyright (C) 1997 Paul Mackerras.
+ */
+
+/* Front light color on Yikes/B&W G3. 32 bits */
+#define HEATHROW_FRONT_LIGHT            0x32 /* (set to 0 or 0xffffffff) */
+
+/* Brightness/contrast (gossamer iMac ?). 8 bits */
+#define HEATHROW_BRIGHTNESS_CNTL        0x32
+#define HEATHROW_CONTRAST_CNTL          0x33
+
+/* offset from ohare base for feature control register */
+#define HEATHROW_MBCR                   0x34    /* Media bay control */
+#define HEATHROW_FCR                    0x38    /* Feature control */
+#define HEATHROW_AUX_CNTL_REG           0x3c    /* Aux control */
+
+/*
+ * Bits in feature control register.
+ * Bits postfixed with a _N are in inverse logic
+ */
+#define HRW_SCC_TRANS_EN_N      0x00000001      /* Also controls modem power */
+#define HRW_BAY_POWER_N         0x00000002
+#define HRW_BAY_PCI_ENABLE      0x00000004
+#define HRW_BAY_IDE_ENABLE      0x00000008
+#define HRW_BAY_FLOPPY_ENABLE   0x00000010
+#define HRW_IDE0_ENABLE         0x00000020
+#define HRW_IDE0_RESET_N        0x00000040
+#define HRW_BAY_DEV_MASK        0x0000001c
+#define HRW_BAY_RESET_N         0x00000080
+#define HRW_IOBUS_ENABLE        0x00000100      /* Internal IDE ? */
+#define HRW_SCC_ENABLE          0x00000200
+#define HRW_MESH_ENABLE         0x00000400
+#define HRW_SWIM_ENABLE         0x00000800
+#define HRW_SOUND_POWER_N       0x00001000
+#define HRW_SOUND_CLK_ENABLE    0x00002000
+#define HRW_SCCA_IO             0x00004000
+#define HRW_SCCB_IO             0x00008000
+#define HRW_PORT_OR_DESK_VIA_N  0x00010000      /* This one is 0 on PowerBook */
+#define HRW_PWM_MON_ID_N        0x00020000      /* ??? (0) */
+#define HRW_HOOK_MB_CNT_N       0x00040000      /* ??? (0) */
+#define HRW_SWIM_CLONE_FLOPPY   0x00080000      /* ??? (0) */
+#define HRW_AUD_RUN22           0x00100000      /* ??? (1) */
+#define HRW_SCSI_LINK_MODE      0x00200000      /* Read ??? (1) */
+#define HRW_ARB_BYPASS          0x00400000      /* Disable internal PCI arbitrer */
+#define HRW_IDE1_RESET_N        0x00800000      /* Media bay */
+#define HRW_SLOW_SCC_PCLK       0x01000000      /* ??? (0) */
+#define HRW_RESET_SCC           0x02000000
+#define HRW_MFDC_CELL_ENABLE    0x04000000      /* ??? (0) */
+#define HRW_USE_MFDC            0x08000000      /* ??? (0) */
+#define HRW_BMAC_IO_ENABLE      0x60000000      /* two bits, not documented in OF */
+#define HRW_BMAC_RESET          0x80000000      /* not documented in OF */
+
+/* We OR those features at boot on desktop G3s */
+#define HRW_DEFAULTS            (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
+
+/* Looks like Heathrow has some sort of GPIOs as well... */
+#define HRW_GPIO_MODEM_RESET    0x6d
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_HEATHROW_H */
diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h
new file mode 100644
index 000000000000..5d99b6489d56
--- /dev/null
+++ b/arch/powerpc/include/asm/highmem.h
@@ -0,0 +1,138 @@
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * PowerPC version, stolen from the i386 version.
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terrabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/kmap_types.h>
+#include <asm/tlbflush.h>
+#include <asm/page.h>
+#include <asm/fixmap.h>
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#define LAST_PKMAP      (1 << PTE_SHIFT)
+#define LAST_PKMAP_MASK (LAST_PKMAP-1)
+#define PKMAP_BASE      ((FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)
+#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+static inline void *kmap(struct page *page)
+{
+        might_sleep();
+        if (!PageHighMem(page))
+                return page_address(page);
+        return kmap_high(page);
+}
+
+static inline void kunmap(struct page *page)
+{
+        BUG_ON(in_interrupt());
+        if (!PageHighMem(page))
+                return;
+        kunmap_high(page);
+}
+
+/*
+ * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
+ * gives a more generic (and caching) interface. But kmap_atomic can
+ * be used in IRQ contexts, so in some (very limited) cases we need
+ * it.
+ */
+static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
+{
+        unsigned int idx;
+        unsigned long vaddr;
+
+        /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
+        pagefault_disable();
+        if (!PageHighMem(page))
+                return page_address(page);
+
+        idx = type + KM_TYPE_NR*smp_processor_id();
+        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+#ifdef CONFIG_DEBUG_HIGHMEM
+        BUG_ON(!pte_none(*(kmap_pte-idx)));
+#endif
+        set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
+        flush_tlb_page(NULL, vaddr);
+
+        return (void*) vaddr;
+}
+
+static inline void *kmap_atomic(struct page *page, enum km_type type)
+{
+        return kmap_atomic_prot(page, type, kmap_prot);
+}
+
+static inline void kunmap_atomic(void *kvaddr, enum km_type type)
+{
+#ifdef CONFIG_DEBUG_HIGHMEM
+        unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
+        enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
+
+        if (vaddr < __fix_to_virt(FIX_KMAP_END)) {
+                pagefault_enable();
+                return;
+        }
+
+        BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
+
+        /*
+         * force other mappings to Oops if they'll try to access
+         * this pte without first remap it
+         */
+        pte_clear(&init_mm, vaddr, kmap_pte-idx);
+        flush_tlb_page(NULL, vaddr);
+#endif
+        pagefault_enable();
+}
+
+static inline struct page *kmap_atomic_to_page(void *ptr)
+{
+        unsigned long idx, vaddr = (unsigned long) ptr;
+        pte_t *pte;
+
+        if (vaddr < FIXADDR_START)
+                return virt_to_page(ptr);
+
+        idx = virt_to_fix(vaddr);
+        pte = kmap_pte - (idx - FIX_KMAP_BEGIN);
+        return pte_page(*pte);
+}
+
+#define flush_cache_kmaps()     flush_cache_all()
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
new file mode 100644
index 000000000000..26f0d0ab27a5
--- /dev/null
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -0,0 +1,75 @@
+#ifndef _ASM_POWERPC_HUGETLB_H
+#define _ASM_POWERPC_HUGETLB_H
+
+#include <asm/page.h>
+
+
+int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
+                           unsigned long len);
+
+void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
+                            unsigned long end, unsigned long floor,
+                            unsigned long ceiling);
+
+void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                     pte_t *ptep, pte_t pte);
+
+pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep);
+
+/*
+ * If the arch doesn't supply something else, assume that hugepage
+ * size aligned regions are ok without further preparation.
+ */
+static inline int prepare_hugepage_range(struct file *file,
+                        unsigned long addr, unsigned long len)
+{
+        struct hstate *h = hstate_file(file);
+        if (len & ~huge_page_mask(h))
+                return -EINVAL;
+        if (addr & ~huge_page_mask(h))
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        return *ptep;
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
new file mode 100644
index 000000000000..fbe2932fa9e9
--- /dev/null
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -0,0 +1,296 @@
+#ifndef _ASM_POWERPC_HVCALL_H
+#define _ASM_POWERPC_HVCALL_H
+#ifdef __KERNEL__
+
+#define HVSC                    .long 0x44000022
+
+#define H_SUCCESS       0
+#define H_BUSY          1       /* Hardware busy -- retry later */
+#define H_CLOSED        2       /* Resource closed */
+#define H_NOT_AVAILABLE 3
+#define H_CONSTRAINED   4       /* Resource request constrained to max allowed */
+#define H_PARTIAL       5
+#define H_IN_PROGRESS   14      /* Kind of like busy */
+#define H_PAGE_REGISTERED 15
+#define H_PARTIAL_STORE   16
+#define H_PENDING       17      /* returned from H_POLL_PENDING */
+#define H_CONTINUE      18      /* Returned from H_Join on success */
+#define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
+#define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
+                                                 is a good time to retry */
+#define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
+                                                 is a good time to retry */
+#define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
+                                                 is a good time to retry */
+#define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
+                                                 is a good time to retry */
+#define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
+                                                 is a good time to retry */
+#define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
+                                                 is a good time to retry */
+#define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
+#define H_HARDWARE      -1      /* Hardware error */
+#define H_FUNCTION      -2      /* Function not supported */
+#define H_PRIVILEGE     -3      /* Caller not privileged */
+#define H_PARAMETER     -4      /* Parameter invalid, out-of-range or conflicting */
+#define H_BAD_MODE      -5      /* Illegal msr value */
+#define H_PTEG_FULL     -6      /* PTEG is full */
+#define H_NOT_FOUND     -7      /* PTE was not found" */
+#define H_RESERVED_DABR -8      /* DABR address is reserved by the hypervisor on this processor" */
+#define H_NO_MEM        -9
+#define H_AUTHORITY     -10
+#define H_PERMISSION    -11
+#define H_DROPPED       -12
+#define H_SOURCE_PARM   -13
+#define H_DEST_PARM     -14
+#define H_REMOTE_PARM   -15
+#define H_RESOURCE      -16
+#define H_ADAPTER_PARM  -17
+#define H_RH_PARM       -18
+#define H_RCQ_PARM      -19
+#define H_SCQ_PARM      -20
+#define H_EQ_PARM       -21
+#define H_RT_PARM       -22
+#define H_ST_PARM       -23
+#define H_SIGT_PARM     -24
+#define H_TOKEN_PARM    -25
+#define H_MLENGTH_PARM  -27
+#define H_MEM_PARM      -28
+#define H_MEM_ACCESS_PARM -29
+#define H_ATTR_PARM     -30
+#define H_PORT_PARM     -31
+#define H_MCG_PARM      -32
+#define H_VL_PARM       -33
+#define H_TSIZE_PARM    -34
+#define H_TRACE_PARM    -35
+
+#define H_MASK_PARM     -37
+#define H_MCG_FULL      -38
+#define H_ALIAS_EXIST   -39
+#define H_P_COUNTER     -40
+#define H_TABLE_FULL    -41
+#define H_ALT_TABLE     -42
+#define H_MR_CONDITION  -43
+#define H_NOT_ENOUGH_RESOURCES -44
+#define H_R_STATE       -45
+#define H_RESCINDEND    -46
+
+
+/* Long Busy is a condition that can be returned by the firmware
+ * when a call cannot be completed now, but the identical call
+ * should be retried later.  This prevents calls blocking in the
+ * firmware for long periods of time.  Annoyingly the firmware can return
+ * a range of return codes, hinting at how long we should wait before
+ * retrying.  If you don't care for the hint, the macro below is a good
+ * way to check for the long_busy return codes
+ */
+#define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
+                             && (x <= H_LONG_BUSY_END_RANGE))
+
+/* Flags */
+#define H_LARGE_PAGE            (1UL<<(63-16))
+#define H_EXACT                 (1UL<<(63-24))  /* Use exact PTE or return H_PTEG_FULL */
+#define H_R_XLATE               (1UL<<(63-25))  /* include a valid logical page num in the pte if the valid bit is set */
+#define H_READ_4                (1UL<<(63-26))  /* Return 4 PTEs */
+#define H_PAGE_STATE_CHANGE     (1UL<<(63-28))
+#define H_PAGE_UNUSED           ((1UL<<(63-29)) | (1UL<<(63-30)))
+#define H_PAGE_SET_UNUSED       (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
+#define H_PAGE_SET_LOANED       (H_PAGE_SET_UNUSED | (1UL<<(63-31)))
+#define H_PAGE_SET_ACTIVE       H_PAGE_STATE_CHANGE
+#define H_AVPN                  (1UL<<(63-32))  /* An avpn is provided as a sanity test */
+#define H_ANDCOND               (1UL<<(63-33))
+#define H_ICACHE_INVALIDATE     (1UL<<(63-40))  /* icbi, etc.  (ignored for IO pages) */
+#define H_ICACHE_SYNCHRONIZE    (1UL<<(63-41))  /* dcbst, icbi, etc (ignored for IO pages */
+#define H_ZERO_PAGE             (1UL<<(63-48))  /* zero the page before mapping (ignored for IO pages) */
+#define H_COPY_PAGE             (1UL<<(63-49))
+#define H_N                     (1UL<<(63-61))
+#define H_PP1                   (1UL<<(63-62))
+#define H_PP2                   (1UL<<(63-63))
+
+/* VASI States */
+#define H_VASI_INVALID          0
+#define H_VASI_ENABLED          1
+#define H_VASI_ABORTED          2
+#define H_VASI_SUSPENDING       3
+#define H_VASI_SUSPENDED        4
+#define H_VASI_RESUMED          5
+#define H_VASI_COMPLETED        6
+
+/* DABRX flags */
+#define H_DABRX_HYPERVISOR      (1UL<<(63-61))
+#define H_DABRX_KERNEL          (1UL<<(63-62))
+#define H_DABRX_USER            (1UL<<(63-63))
+
+/* Each control block has to be on a 4K bondary */
+#define H_CB_ALIGNMENT          4096
+
+/* pSeries hypervisor opcodes */
+#define H_REMOVE                0x04
+#define H_ENTER                 0x08
+#define H_READ                  0x0c
+#define H_CLEAR_MOD             0x10
+#define H_CLEAR_REF             0x14
+#define H_PROTECT               0x18
+#define H_GET_TCE               0x1c
+#define H_PUT_TCE               0x20
+#define H_SET_SPRG0             0x24
+#define H_SET_DABR              0x28
+#define H_PAGE_INIT             0x2c
+#define H_SET_ASR               0x30
+#define H_ASR_ON                0x34
+#define H_ASR_OFF               0x38
+#define H_LOGICAL_CI_LOAD       0x3c
+#define H_LOGICAL_CI_STORE      0x40
+#define H_LOGICAL_CACHE_LOAD    0x44
+#define H_LOGICAL_CACHE_STORE   0x48
+#define H_LOGICAL_ICBI          0x4c
+#define H_LOGICAL_DCBF          0x50
+#define H_GET_TERM_CHAR         0x54
+#define H_PUT_TERM_CHAR         0x58
+#define H_REAL_TO_LOGICAL       0x5c
+#define H_HYPERVISOR_DATA       0x60
+#define H_EOI                   0x64
+#define H_CPPR                  0x68
+#define H_IPI                   0x6c
+#define H_IPOLL                 0x70
+#define H_XIRR                  0x74
+#define H_PERFMON               0x7c
+#define H_MIGRATE_DMA           0x78
+#define H_REGISTER_VPA          0xDC
+#define H_CEDE                  0xE0
+#define H_CONFER                0xE4
+#define H_PROD                  0xE8
+#define H_GET_PPP               0xEC
+#define H_SET_PPP               0xF0
+#define H_PURR                  0xF4
+#define H_PIC                   0xF8
+#define H_REG_CRQ               0xFC
+#define H_FREE_CRQ              0x100
+#define H_VIO_SIGNAL            0x104
+#define H_SEND_CRQ              0x108
+#define H_COPY_RDMA             0x110
+#define H_REGISTER_LOGICAL_LAN  0x114
+#define H_FREE_LOGICAL_LAN      0x118
+#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
+#define H_SEND_LOGICAL_LAN      0x120
+#define H_BULK_REMOVE           0x124
+#define H_MULTICAST_CTRL        0x130
+#define H_SET_XDABR             0x134
+#define H_STUFF_TCE             0x138
+#define H_PUT_TCE_INDIRECT      0x13C
+#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
+#define H_VTERM_PARTNER_INFO    0x150
+#define H_REGISTER_VTERM        0x154
+#define H_FREE_VTERM            0x158
+#define H_RESET_EVENTS          0x15C
+#define H_ALLOC_RESOURCE        0x160
+#define H_FREE_RESOURCE         0x164
+#define H_MODIFY_QP             0x168
+#define H_QUERY_QP              0x16C
+#define H_REREGISTER_PMR        0x170
+#define H_REGISTER_SMR          0x174
+#define H_QUERY_MR              0x178
+#define H_QUERY_MW              0x17C
+#define H_QUERY_HCA             0x180
+#define H_QUERY_PORT            0x184
+#define H_MODIFY_PORT           0x188
+#define H_DEFINE_AQP1           0x18C
+#define H_GET_TRACE_BUFFER      0x190
+#define H_DEFINE_AQP0           0x194
+#define H_RESIZE_MR             0x198
+#define H_ATTACH_MCQP           0x19C
+#define H_DETACH_MCQP           0x1A0
+#define H_CREATE_RPT            0x1A4
+#define H_REMOVE_RPT            0x1A8
+#define H_REGISTER_RPAGES       0x1AC
+#define H_DISABLE_AND_GETC      0x1B0
+#define H_ERROR_DATA            0x1B4
+#define H_GET_HCA_INFO          0x1B8
+#define H_GET_PERF_COUNT        0x1BC
+#define H_MANAGE_TRACE          0x1C0
+#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
+#define H_QUERY_INT_STATE       0x1E4
+#define H_POLL_PENDING          0x1D8
+#define H_ILLAN_ATTRIBUTES      0x244
+#define H_JOIN                  0x298
+#define H_VASI_STATE            0x2A4
+#define H_ENABLE_CRQ            0x2B0
+#define H_SET_MPP               0x2D0
+#define H_GET_MPP               0x2D4
+#define MAX_HCALL_OPCODE        H_GET_MPP
+
+#ifndef __ASSEMBLY__
+
+/**
+ * plpar_hcall_norets: - Make a pseries hypervisor call with no return arguments
+ * @opcode: The hypervisor call to make.
+ *
+ * This call supports up to 7 arguments and only returns the status of
+ * the hcall. Use this version where possible, its slightly faster than
+ * the other plpar_hcalls.
+ */
+long plpar_hcall_norets(unsigned long opcode, ...);
+
+/**
+ * plpar_hcall: - Make a pseries hypervisor call
+ * @opcode: The hypervisor call to make.
+ * @retbuf: Buffer to store up to 4 return arguments in.
+ *
+ * This call supports up to 6 arguments and 4 return arguments. Use
+ * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
+ *
+ * Used for all but the craziest of phyp interfaces (see plpar_hcall9)
+ */
+#define PLPAR_HCALL_BUFSIZE 4
+long plpar_hcall(unsigned long opcode, unsigned long *retbuf, ...);
+
+/**
+ * plpar_hcall_raw: - Make a hypervisor call without calculating hcall stats
+ * @opcode: The hypervisor call to make.
+ * @retbuf: Buffer to store up to 4 return arguments in.
+ *
+ * This call supports up to 6 arguments and 4 return arguments. Use
+ * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
+ *
+ * Used when phyp interface needs to be called in real mode. Similar to
+ * plpar_hcall, but plpar_hcall_raw works in real mode and does not
+ * calculate hypervisor call statistics.
+ */
+long plpar_hcall_raw(unsigned long opcode, unsigned long *retbuf, ...);
+
+/**
+ * plpar_hcall9: - Make a pseries hypervisor call with up to 9 return arguments
+ * @opcode: The hypervisor call to make.
+ * @retbuf: Buffer to store up to 9 return arguments in.
+ *
+ * This call supports up to 9 arguments and 9 return arguments. Use
+ * PLPAR_HCALL9_BUFSIZE to size the return argument buffer.
+ */
+#define PLPAR_HCALL9_BUFSIZE 9
+long plpar_hcall9(unsigned long opcode, unsigned long *retbuf, ...);
+
+/* For hcall instrumentation.  One structure per-hcall, per-CPU */
+struct hcall_stats {
+        unsigned long   num_calls;      /* number of calls (on this CPU) */
+        unsigned long   tb_total;       /* total wall time (mftb) of calls. */
+        unsigned long   purr_total;     /* total cpu time (PURR) of calls. */
+};
+#define HCALL_STAT_ARRAY_SIZE   ((MAX_HCALL_OPCODE >> 2) + 1)
+
+struct hvcall_mpp_data {
+        unsigned long entitled_mem;
+        unsigned long mapped_mem;
+        unsigned short group_num;
+        unsigned short pool_num;
+        unsigned char mem_weight;
+        unsigned char unallocated_mem_weight;
+        unsigned long unallocated_entitlement;  /* value in bytes */
+        unsigned long pool_size;
+        signed long loan_request;
+        unsigned long backing_mem;
+};
+
+int h_get_mpp(struct hvcall_mpp_data *);
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_HVCALL_H */
diff --git a/arch/powerpc/include/asm/hvconsole.h b/arch/powerpc/include/asm/hvconsole.h
new file mode 100644
index 000000000000..35ea69e8121f
--- /dev/null
+++ b/arch/powerpc/include/asm/hvconsole.h
@@ -0,0 +1,41 @@
+/*
+ * hvconsole.h
+ * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
+ *
+ * LPAR console support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef _PPC64_HVCONSOLE_H
+#define _PPC64_HVCONSOLE_H
+#ifdef __KERNEL__
+
+/*
+ * PSeries firmware will only send/recv up to 16 bytes of character data per
+ * hcall.
+ */
+#define MAX_VIO_PUT_CHARS       16
+#define SIZE_VIO_GET_CHARS      16
+
+/*
+ * Vio firmware always attempts to fetch MAX_VIO_GET_CHARS chars.  The 'count'
+ * parm is included to conform to put_chars() function pointer template
+ */
+extern int hvc_get_chars(uint32_t vtermno, char *buf, int count);
+extern int hvc_put_chars(uint32_t vtermno, const char *buf, int count);
+
+#endif /* __KERNEL__ */
+#endif /* _PPC64_HVCONSOLE_H */
diff --git a/arch/powerpc/include/asm/hvcserver.h b/arch/powerpc/include/asm/hvcserver.h
new file mode 100644
index 000000000000..67d7da3a4da4
--- /dev/null
+++ b/arch/powerpc/include/asm/hvcserver.h
@@ -0,0 +1,59 @@
+/*
+ * hvcserver.h
+ * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
+ *
+ * PPC64 virtual I/O console server support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef _PPC64_HVCSERVER_H
+#define _PPC64_HVCSERVER_H
+#ifdef __KERNEL__
+
+#include <linux/list.h>
+
+/* Converged Location Code length */
+#define HVCS_CLC_LENGTH 79
+
+/**
+ * hvcs_partner_info - an element in a list of partner info
+ * @node: list_head denoting this partner_info struct's position in the list of
+ *      partner info.
+ * @unit_address: The partner unit address of this entry.
+ * @partition_ID: The partner partition ID of this entry.
+ * @location_code: The converged location code of this entry + 1 char for the
+ *      null-term.
+ *
+ * This structure outlines the format that partner info is presented to a caller
+ * of the hvcs partner info fetching functions.  These are strung together into
+ * a list using linux kernel lists.
+ */
+struct hvcs_partner_info {
+        struct list_head node;
+        uint32_t unit_address;
+        uint32_t partition_ID;
+        char location_code[HVCS_CLC_LENGTH + 1]; /* CLC + 1 null-term char */
+};
+
+extern int hvcs_free_partner_info(struct list_head *head);
+extern int hvcs_get_partner_info(uint32_t unit_address,
+                struct list_head *head, unsigned long *pi_buff);
+extern int hvcs_register_connection(uint32_t unit_address,
+                uint32_t p_partition_ID, uint32_t p_unit_address);
+extern int hvcs_free_connection(uint32_t unit_address);
+
+#endif /* __KERNEL__ */
+#endif /* _PPC64_HVCSERVER_H */
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
new file mode 100644
index 000000000000..f75a5fc64d2e
--- /dev/null
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
+ */
+#ifndef _ASM_POWERPC_HW_IRQ_H
+#define _ASM_POWERPC_HW_IRQ_H
+
+#ifdef __KERNEL__
+
+#include <linux/errno.h>
+#include <linux/compiler.h>
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+
+extern void timer_interrupt(struct pt_regs *);
+
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+
+static inline unsigned long local_get_flags(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__("lbz %0,%1(13)"
+        : "=r" (flags)
+        : "i" (offsetof(struct paca_struct, soft_enabled)));
+
+        return flags;
+}
+
+static inline unsigned long raw_local_irq_disable(void)
+{
+        unsigned long flags, zero;
+
+        __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
+        : "=r" (flags), "=&r" (zero)
+        : "i" (offsetof(struct paca_struct, soft_enabled))
+        : "memory");
+
+        return flags;
+}
+
+extern void raw_local_irq_restore(unsigned long);
+extern void iseries_handle_interrupts(void);
+
+#define raw_local_irq_enable()          raw_local_irq_restore(1)
+#define raw_local_save_flags(flags)     ((flags) = local_get_flags())
+#define raw_local_irq_save(flags)       ((flags) = raw_local_irq_disable())
+
+#define raw_irqs_disabled()             (local_get_flags() == 0)
+#define raw_irqs_disabled_flags(flags)  ((flags) == 0)
+
+#define __hard_irq_enable()     __mtmsrd(mfmsr() | MSR_EE, 1)
+#define __hard_irq_disable()    __mtmsrd(mfmsr() & ~MSR_EE, 1)
+
+#define  hard_irq_disable()                     \
+        do {                                    \
+                __hard_irq_disable();           \
+                get_paca()->soft_enabled = 0;   \
+                get_paca()->hard_enabled = 0;   \
+        } while(0)
+
+static inline int irqs_disabled_flags(unsigned long flags)
+{
+        return flags == 0;
+}
+
+#else
+
+#if defined(CONFIG_BOOKE)
+#define SET_MSR_EE(x)   mtmsr(x)
+#define local_irq_restore(flags)        __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
+#else
+#define SET_MSR_EE(x)   mtmsr(x)
+#define local_irq_restore(flags)        mtmsr(flags)
+#endif
+
+static inline void local_irq_disable(void)
+{
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 0": : :"memory");
+#else
+        unsigned long msr;
+        __asm__ __volatile__("": : :"memory");
+        msr = mfmsr();
+        SET_MSR_EE(msr & ~MSR_EE);
+#endif
+}
+
+static inline void local_irq_enable(void)
+{
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 1": : :"memory");
+#else
+        unsigned long msr;
+        __asm__ __volatile__("": : :"memory");
+        msr = mfmsr();
+        SET_MSR_EE(msr | MSR_EE);
+#endif
+}
+
+static inline void local_irq_save_ptr(unsigned long *flags)
+{
+        unsigned long msr;
+        msr = mfmsr();
+        *flags = msr;
+#ifdef CONFIG_BOOKE
+        __asm__ __volatile__("wrteei 0": : :"memory");
+#else
+        SET_MSR_EE(msr & ~MSR_EE);
+#endif
+        __asm__ __volatile__("": : :"memory");
+}
+
+#define local_save_flags(flags) ((flags) = mfmsr())
+#define local_irq_save(flags)   local_irq_save_ptr(&flags)
+#define irqs_disabled()         ((mfmsr() & MSR_EE) == 0)
+
+#define hard_irq_enable()       local_irq_enable()
+#define hard_irq_disable()      local_irq_disable()
+
+static inline int irqs_disabled_flags(unsigned long flags)
+{
+        return (flags & MSR_EE) == 0;
+}
+
+#endif /* CONFIG_PPC64 */
+
+/*
+ * interrupt-retrigger: should we handle this via lost interrupts and IPIs
+ * or should we not care like we do now ? --BenH.
+ */
+struct hw_interrupt_type;
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/include/asm/hydra.h b/arch/powerpc/include/asm/hydra.h
new file mode 100644
index 000000000000..1ad4eed07fbe
--- /dev/null
+++ b/arch/powerpc/include/asm/hydra.h
@@ -0,0 +1,102 @@
+/*
+ *  include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
+ *
+ *  Copyright (C) 1997 Geert Uytterhoeven
+ *
+ *  This file is based on the following documentation:
+ *
+ *      Macintosh Technology in the Common Hardware Reference Platform
+ *      Apple Computer, Inc.
+ *
+ *      © Copyright 1995 Apple Computer, Inc. All rights reserved.
+ *
+ *  It's available online from http://chrp.apple.com/MacTech.pdf.
+ *  You can obtain paper copies of this book from computer bookstores or by
+ *  writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
+ *  Francisco, CA 94104. Reference ISBN 1-55860-393-X.
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License.  See the file COPYING in the main directory of this archive
+ *  for more details.
+ */
+
+#ifndef _ASMPPC_HYDRA_H
+#define _ASMPPC_HYDRA_H
+
+#ifdef __KERNEL__
+
+struct Hydra {
+    /* DBDMA Controller Register Space */
+    char Pad1[0x30];
+    u_int CachePD;
+    u_int IDs;
+    u_int Feature_Control;
+    char Pad2[0x7fc4];
+    /* DBDMA Channel Register Space */
+    char SCSI_DMA[0x100];
+    char Pad3[0x300];
+    char SCCA_Tx_DMA[0x100];
+    char SCCA_Rx_DMA[0x100];
+    char SCCB_Tx_DMA[0x100];
+    char SCCB_Rx_DMA[0x100];
+    char Pad4[0x7800];
+    /* Device Register Space */
+    char SCSI[0x1000];
+    char ADB[0x1000];
+    char SCC_Legacy[0x1000];
+    char SCC[0x1000];
+    char Pad9[0x2000];
+    char VIA[0x2000];
+    char Pad10[0x28000];
+    char OpenPIC[0x40000];
+};
+
+extern volatile struct Hydra __iomem *Hydra;
+
+
+    /*
+     *  Feature Control Register
+     */
+
+#define HYDRA_FC_SCC_CELL_EN    0x00000001      /* Enable SCC Clock */
+#define HYDRA_FC_SCSI_CELL_EN   0x00000002      /* Enable SCSI Clock */
+#define HYDRA_FC_SCCA_ENABLE    0x00000004      /* Enable SCC A Lines */
+#define HYDRA_FC_SCCB_ENABLE    0x00000008      /* Enable SCC B Lines */
+#define HYDRA_FC_ARB_BYPASS     0x00000010      /* Bypass Internal Arbiter */
+#define HYDRA_FC_RESET_SCC      0x00000020      /* Reset SCC */
+#define HYDRA_FC_MPIC_ENABLE    0x00000040      /* Enable OpenPIC */
+#define HYDRA_FC_SLOW_SCC_PCLK  0x00000080      /* 1=15.6672, 0=25 MHz */
+#define HYDRA_FC_MPIC_IS_MASTER 0x00000100      /* OpenPIC Master Mode */
+
+
+    /*
+     *  OpenPIC Interrupt Sources
+     */
+
+#define HYDRA_INT_SIO           0
+#define HYDRA_INT_SCSI_DMA      1
+#define HYDRA_INT_SCCA_TX_DMA   2
+#define HYDRA_INT_SCCA_RX_DMA   3
+#define HYDRA_INT_SCCB_TX_DMA   4
+#define HYDRA_INT_SCCB_RX_DMA   5
+#define HYDRA_INT_SCSI          6
+#define HYDRA_INT_SCCA          7
+#define HYDRA_INT_SCCB          8
+#define HYDRA_INT_VIA           9
+#define HYDRA_INT_ADB           10
+#define HYDRA_INT_ADB_NMI       11
+#define HYDRA_INT_EXT1          12      /* PCI IRQW */
+#define HYDRA_INT_EXT2          13      /* PCI IRQX */
+#define HYDRA_INT_EXT3          14      /* PCI IRQY */
+#define HYDRA_INT_EXT4          15      /* PCI IRQZ */
+#define HYDRA_INT_EXT5          16      /* IDE Primay/Secondary */
+#define HYDRA_INT_EXT6          17      /* IDE Secondary */
+#define HYDRA_INT_EXT7          18      /* Power Off Request */
+#define HYDRA_INT_SPARE         19
+
+extern int hydra_init(void);
+extern void macio_adb_init(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASMPPC_HYDRA_H */
diff --git a/arch/powerpc/include/asm/i8259.h b/arch/powerpc/include/asm/i8259.h
new file mode 100644
index 000000000000..105ade297aad
--- /dev/null
+++ b/arch/powerpc/include/asm/i8259.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_POWERPC_I8259_H
+#define _ASM_POWERPC_I8259_H
+#ifdef __KERNEL__
+
+#include <linux/irq.h>
+
+extern void i8259_init(struct device_node *node, unsigned long intack_addr);
+extern unsigned int i8259_irq(void);
+extern struct irq_host *i8259_get_host(void);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_I8259_H */
diff --git a/arch/powerpc/include/asm/ibmebus.h b/arch/powerpc/include/asm/ibmebus.h
new file mode 100644
index 000000000000..1a9d9aea21fa
--- /dev/null
+++ b/arch/powerpc/include/asm/ibmebus.h
@@ -0,0 +1,60 @@
+/*
+ * IBM PowerPC eBus Infrastructure Support.
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *  Joachim Fenkes <fenkes@de.ibm.com>
+ *  Heiko J Schick <schickhj@de.ibm.com>
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_EBUS_H
+#define _ASM_EBUS_H
+#ifdef __KERNEL__
+
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+extern struct bus_type ibmebus_bus_type;
+
+int ibmebus_register_driver(struct of_platform_driver *drv);
+void ibmebus_unregister_driver(struct of_platform_driver *drv);
+
+int ibmebus_request_irq(u32 ist, irq_handler_t handler,
+                        unsigned long irq_flags, const char *devname,
+                        void *dev_id);
+void ibmebus_free_irq(u32 ist, void *dev_id);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_IBMEBUS_H */
diff --git a/arch/powerpc/include/asm/ide.h b/arch/powerpc/include/asm/ide.h
new file mode 100644
index 000000000000..048480e340f2
--- /dev/null
+++ b/arch/powerpc/include/asm/ide.h
@@ -0,0 +1,58 @@
+/*
+ *  Copyright (C) 1994-1996 Linus Torvalds & authors
+ *
+ *  This file contains the powerpc architecture specific IDE code.
+ */
+#ifndef _ASM_POWERPC_IDE_H
+#define _ASM_POWERPC_IDE_H
+
+#ifdef __KERNEL__
+
+#ifndef __powerpc64__
+#include <linux/sched.h>
+#include <asm/mpc8xx.h>
+#endif
+#include <asm/io.h>
+
+#define __ide_mm_insw(p, a, c)  readsw((void __iomem *)(p), (a), (c))
+#define __ide_mm_insl(p, a, c)  readsl((void __iomem *)(p), (a), (c))
+#define __ide_mm_outsw(p, a, c) writesw((void __iomem *)(p), (a), (c))
+#define __ide_mm_outsl(p, a, c) writesl((void __iomem *)(p), (a), (c))
+
+#ifndef  __powerpc64__
+#include <linux/ioport.h>
+
+/* FIXME: use ide_platform host driver */
+static __inline__ int ide_default_irq(unsigned long base)
+{
+#ifdef CONFIG_PPLUS
+        switch (base) {
+        case 0x1f0:     return 14;
+        case 0x170:     return 15;
+        }
+#endif
+        return 0;
+}
+
+/* FIXME: use ide_platform host driver */
+static __inline__ unsigned long ide_default_io_base(int index)
+{
+#ifdef CONFIG_PPLUS
+        switch (index) {
+        case 0:         return 0x1f0;
+        case 1:         return 0x170;
+        }
+#endif
+        return 0;
+}
+
+#ifdef CONFIG_BLK_DEV_MPC8xx_IDE
+#define IDE_ARCH_ACK_INTR  1
+#define ide_ack_intr(hwif) ((hwif)->ack_intr ? (hwif)->ack_intr(hwif) : 1)
+#endif
+
+#endif /* __powerpc64__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_IDE_H */
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
new file mode 100644
index 000000000000..0f165e59c326
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -0,0 +1,156 @@
+/**
+ * MPC86xx Internal Memory Map
+ *
+ * Authors: Jeff Brown
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2004,2007 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This header file defines structures for various 86xx SOC devices that are
+ * used by multiple source files.
+ */
+
+#ifndef __ASM_POWERPC_IMMAP_86XX_H__
+#define __ASM_POWERPC_IMMAP_86XX_H__
+#ifdef __KERNEL__
+
+/* Global Utility Registers */
+struct ccsr_guts {
+        __be32  porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
+        __be32  porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
+        __be32  porimpscr;      /* 0x.0008 - POR I/O Impedance Status and Control Register */
+        __be32  pordevsr;       /* 0x.000c - POR I/O Device Status Register */
+        __be32  pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
+        u8      res1[0x20 - 0x14];
+        __be32  porcir;         /* 0x.0020 - POR Configuration Information Register */
+        u8      res2[0x30 - 0x24];
+        __be32  gpiocr;         /* 0x.0030 - GPIO Control Register */
+        u8      res3[0x40 - 0x34];
+        __be32  gpoutdr;        /* 0x.0040 - General-Purpose Output Data Register */
+        u8      res4[0x50 - 0x44];
+        __be32  gpindr;         /* 0x.0050 - General-Purpose Input Data Register */
+        u8      res5[0x60 - 0x54];
+        __be32  pmuxcr;         /* 0x.0060 - Alternate Function Signal Multiplex Control */
+        u8      res6[0x70 - 0x64];
+        __be32  devdisr;        /* 0x.0070 - Device Disable Control */
+        __be32  devdisr2;       /* 0x.0074 - Device Disable Control 2 */
+        u8      res7[0x80 - 0x78];
+        __be32  powmgtcsr;      /* 0x.0080 - Power Management Status and Control Register */
+        u8      res8[0x90 - 0x84];
+        __be32  mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
+        __be32  rstrscr;        /* 0x.0094 - Reset Request Status and Control Register */
+        u8      res9[0xA0 - 0x98];
+        __be32  pvr;            /* 0x.00a0 - Processor Version Register */
+        __be32  svr;            /* 0x.00a4 - System Version Register */
+        u8      res10[0xB0 - 0xA8];
+        __be32  rstcr;          /* 0x.00b0 - Reset Control Register */
+        u8      res11[0xC0 - 0xB4];
+        __be32  elbcvselcr;     /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
+        u8      res12[0x800 - 0xC4];
+        __be32  clkdvdr;        /* 0x.0800 - Clock Divide Register */
+        u8      res13[0x900 - 0x804];
+        __be32  ircr;           /* 0x.0900 - Infrared Control Register */
+        u8      res14[0x908 - 0x904];
+        __be32  dmacr;          /* 0x.0908 - DMA Control Register */
+        u8      res15[0x914 - 0x90C];
+        __be32  elbccr;         /* 0x.0914 - eLBC Control Register */
+        u8      res16[0xB20 - 0x918];
+        __be32  ddr1clkdr;      /* 0x.0b20 - DDR1 Clock Disable Register */
+        __be32  ddr2clkdr;      /* 0x.0b24 - DDR2 Clock Disable Register */
+        __be32  ddrclkdr;       /* 0x.0b28 - DDR Clock Disable Register */
+        u8      res17[0xE00 - 0xB2C];
+        __be32  clkocr;         /* 0x.0e00 - Clock Out Select Register */
+        u8      res18[0xE10 - 0xE04];
+        __be32  ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
+        u8      res19[0xE20 - 0xE14];
+        __be32  lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
+        u8      res20[0xF04 - 0xE24];
+        __be32  srds1cr0;       /* 0x.0f04 - SerDes1 Control Register 0 */
+        __be32  srds1cr1;       /* 0x.0f08 - SerDes1 Control Register 0 */
+        u8      res21[0xF40 - 0xF0C];
+        __be32  srds2cr0;       /* 0x.0f40 - SerDes1 Control Register 0 */
+        __be32  srds2cr1;       /* 0x.0f44 - SerDes1 Control Register 0 */
+} __attribute__ ((packed));
+
+#define CCSR_GUTS_DMACR_DEV_SSI 0       /* DMA controller/channel set to SSI */
+#define CCSR_GUTS_DMACR_DEV_IR  1       /* DMA controller/channel set to IR */
+
+/*
+ * Set the DMACR register in the GUTS
+ *
+ * The DMACR register determines the source of initiated transfers for each
+ * channel on each DMA controller.  Rather than have a bunch of repetitive
+ * macros for the bit patterns, we just have a function that calculates
+ * them.
+ *
+ * guts: Pointer to GUTS structure
+ * co: The DMA controller (0 or 1)
+ * ch: The channel on the DMA controller (0, 1, 2, or 3)
+ * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
+ */
+static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
+        unsigned int co, unsigned int ch, unsigned int device)
+{
+        unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
+
+        clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
+}
+
+#define CCSR_GUTS_PMUXCR_LDPSEL         0x00010000
+#define CCSR_GUTS_PMUXCR_SSI1_MASK      0x0000C000      /* Bitmask for SSI1 */
+#define CCSR_GUTS_PMUXCR_SSI1_LA        0x00000000      /* Latched address */
+#define CCSR_GUTS_PMUXCR_SSI1_HI        0x00004000      /* High impedance */
+#define CCSR_GUTS_PMUXCR_SSI1_SSI       0x00008000      /* Used for SSI1 */
+#define CCSR_GUTS_PMUXCR_SSI2_MASK      0x00003000      /* Bitmask for SSI2 */
+#define CCSR_GUTS_PMUXCR_SSI2_LA        0x00000000      /* Latched address */
+#define CCSR_GUTS_PMUXCR_SSI2_HI        0x00001000      /* High impedance */
+#define CCSR_GUTS_PMUXCR_SSI2_SSI       0x00002000      /* Used for SSI2 */
+#define CCSR_GUTS_PMUXCR_LA_22_25_LA    0x00000000      /* Latched Address */
+#define CCSR_GUTS_PMUXCR_LA_22_25_HI    0x00000400      /* High impedance */
+#define CCSR_GUTS_PMUXCR_DBGDRV         0x00000200      /* Signals not driven */
+#define CCSR_GUTS_PMUXCR_DMA2_0         0x00000008
+#define CCSR_GUTS_PMUXCR_DMA2_3         0x00000004
+#define CCSR_GUTS_PMUXCR_DMA1_0         0x00000002
+#define CCSR_GUTS_PMUXCR_DMA1_3         0x00000001
+
+/*
+ * Set the DMA external control bits in the GUTS
+ *
+ * The DMA external control bits in the PMUXCR are only meaningful for
+ * channels 0 and 3.  Any other channels are ignored.
+ *
+ * guts: Pointer to GUTS structure
+ * co: The DMA controller (0 or 1)
+ * ch: The channel on the DMA controller (0, 1, 2, or 3)
+ * value: the new value for the bit (0 or 1)
+ */
+static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
+        unsigned int co, unsigned int ch, unsigned int value)
+{
+        if ((ch == 0) || (ch == 3)) {
+                unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
+
+                clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
+        }
+}
+
+#define CCSR_GUTS_CLKDVDR_PXCKEN        0x80000000
+#define CCSR_GUTS_CLKDVDR_SSICKEN       0x20000000
+#define CCSR_GUTS_CLKDVDR_PXCKINV       0x10000000
+#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
+#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK  0x06000000
+#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
+        (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
+#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT   16
+#define CCSR_GUTS_CLKDVDR_PXCLK_MASK    0x001F0000
+#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
+#define CCSR_GUTS_CLKDVDR_SSICLK_MASK   0x000000FF
+#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
+
+#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/immap_cpm2.h b/arch/powerpc/include/asm/immap_cpm2.h
new file mode 100644
index 000000000000..4080bab0468c
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_cpm2.h
@@ -0,0 +1,650 @@
+/*
+ * CPM2 Internal Memory Map
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * The Internal Memory Map for devices with CPM2 on them.  This
+ * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
+ * 8560).
+ */
+#ifdef __KERNEL__
+#ifndef __IMMAP_CPM2__
+#define __IMMAP_CPM2__
+
+#include <linux/types.h>
+
+/* System configuration registers.
+*/
+typedef struct sys_82xx_conf {
+        u32     sc_siumcr;
+        u32     sc_sypcr;
+        u8      res1[6];
+        u16     sc_swsr;
+        u8      res2[20];
+        u32     sc_bcr;
+        u8      sc_ppc_acr;
+        u8      res3[3];
+        u32     sc_ppc_alrh;
+        u32     sc_ppc_alrl;
+        u8      sc_lcl_acr;
+        u8      res4[3];
+        u32     sc_lcl_alrh;
+        u32     sc_lcl_alrl;
+        u32     sc_tescr1;
+        u32     sc_tescr2;
+        u32     sc_ltescr1;
+        u32     sc_ltescr2;
+        u32     sc_pdtea;
+        u8      sc_pdtem;
+        u8      res5[3];
+        u32     sc_ldtea;
+        u8      sc_ldtem;
+        u8      res6[163];
+} sysconf_82xx_cpm2_t;
+
+typedef struct sys_85xx_conf {
+        u32     sc_cear;
+        u16     sc_ceer;
+        u16     sc_cemr;
+        u8      res1[70];
+        u32     sc_smaer;
+        u8      res2[4];
+        u32     sc_smevr;
+        u32     sc_smctr;
+        u32     sc_lmaer;
+        u8      res3[4];
+        u32     sc_lmevr;
+        u32     sc_lmctr;
+        u8      res4[144];
+} sysconf_85xx_cpm2_t;
+
+typedef union sys_conf {
+        sysconf_82xx_cpm2_t     siu_82xx;
+        sysconf_85xx_cpm2_t     siu_85xx;
+} sysconf_cpm2_t;
+
+
+
+/* Memory controller registers.
+*/
+typedef struct  mem_ctlr {
+        u32     memc_br0;
+        u32     memc_or0;
+        u32     memc_br1;
+        u32     memc_or1;
+        u32     memc_br2;
+        u32     memc_or2;
+        u32     memc_br3;
+        u32     memc_or3;
+        u32     memc_br4;
+        u32     memc_or4;
+        u32     memc_br5;
+        u32     memc_or5;
+        u32     memc_br6;
+        u32     memc_or6;
+        u32     memc_br7;
+        u32     memc_or7;
+        u32     memc_br8;
+        u32     memc_or8;
+        u32     memc_br9;
+        u32     memc_or9;
+        u32     memc_br10;
+        u32     memc_or10;
+        u32     memc_br11;
+        u32     memc_or11;
+        u8      res1[8];
+        u32     memc_mar;
+        u8      res2[4];
+        u32     memc_mamr;
+        u32     memc_mbmr;
+        u32     memc_mcmr;
+        u8      res3[8];
+        u16     memc_mptpr;
+        u8      res4[2];
+        u32     memc_mdr;
+        u8      res5[4];
+        u32     memc_psdmr;
+        u32     memc_lsdmr;
+        u8      memc_purt;
+        u8      res6[3];
+        u8      memc_psrt;
+        u8      res7[3];
+        u8      memc_lurt;
+        u8      res8[3];
+        u8      memc_lsrt;
+        u8      res9[3];
+        u32     memc_immr;
+        u32     memc_pcibr0;
+        u32     memc_pcibr1;
+        u8      res10[16];
+        u32     memc_pcimsk0;
+        u32     memc_pcimsk1;
+        u8      res11[52];
+} memctl_cpm2_t;
+
+/* System Integration Timers.
+*/
+typedef struct  sys_int_timers {
+        u8      res1[32];
+        u16     sit_tmcntsc;
+        u8      res2[2];
+        u32     sit_tmcnt;
+        u8      res3[4];
+        u32     sit_tmcntal;
+        u8      res4[16];
+        u16     sit_piscr;
+        u8      res5[2];
+        u32     sit_pitc;
+        u32     sit_pitr;
+        u8      res6[94];
+        u8      res7[390];
+} sit_cpm2_t;
+
+#define PISCR_PIRQ_MASK         ((u16)0xff00)
+#define PISCR_PS                ((u16)0x0080)
+#define PISCR_PIE               ((u16)0x0004)
+#define PISCR_PTF               ((u16)0x0002)
+#define PISCR_PTE               ((u16)0x0001)
+
+/* PCI Controller.
+*/
+typedef struct pci_ctlr {
+        u32     pci_omisr;
+        u32     pci_omimr;
+        u8      res1[8];
+        u32     pci_ifqpr;
+        u32     pci_ofqpr;
+        u8      res2[8];
+        u32     pci_imr0;
+        u32     pci_imr1;
+        u32     pci_omr0;
+        u32     pci_omr1;
+        u32     pci_odr;
+        u8      res3[4];
+        u32     pci_idr;
+        u8      res4[20];
+        u32     pci_imisr;
+        u32     pci_imimr;
+        u8      res5[24];
+        u32     pci_ifhpr;
+        u8      res6[4];
+        u32     pci_iftpr;
+        u8      res7[4];
+        u32     pci_iphpr;
+        u8      res8[4];
+        u32     pci_iptpr;
+        u8      res9[4];
+        u32     pci_ofhpr;
+        u8      res10[4];
+        u32     pci_oftpr;
+        u8      res11[4];
+        u32     pci_ophpr;
+        u8      res12[4];
+        u32     pci_optpr;
+        u8      res13[8];
+        u32     pci_mucr;
+        u8      res14[8];
+        u32     pci_qbar;
+        u8      res15[12];
+        u32     pci_dmamr0;
+        u32     pci_dmasr0;
+        u32     pci_dmacdar0;
+        u8      res16[4];
+        u32     pci_dmasar0;
+        u8      res17[4];
+        u32     pci_dmadar0;
+        u8      res18[4];
+        u32     pci_dmabcr0;
+        u32     pci_dmandar0;
+        u8      res19[86];
+        u32     pci_dmamr1;
+        u32     pci_dmasr1;
+        u32     pci_dmacdar1;
+        u8      res20[4];
+        u32     pci_dmasar1;
+        u8      res21[4];
+        u32     pci_dmadar1;
+        u8      res22[4];
+        u32     pci_dmabcr1;
+        u32     pci_dmandar1;
+        u8      res23[88];
+        u32     pci_dmamr2;
+        u32     pci_dmasr2;
+        u32     pci_dmacdar2;
+        u8      res24[4];
+        u32     pci_dmasar2;
+        u8      res25[4];
+        u32     pci_dmadar2;
+        u8      res26[4];
+        u32     pci_dmabcr2;
+        u32     pci_dmandar2;
+        u8      res27[88];
+        u32     pci_dmamr3;
+        u32     pci_dmasr3;
+        u32     pci_dmacdar3;
+        u8      res28[4];
+        u32     pci_dmasar3;
+        u8      res29[4];
+        u32     pci_dmadar3;
+        u8      res30[4];
+        u32     pci_dmabcr3;
+        u32     pci_dmandar3;
+        u8      res31[344];
+        u32     pci_potar0;
+        u8      res32[4];
+        u32     pci_pobar0;
+        u8      res33[4];
+        u32     pci_pocmr0;
+        u8      res34[4];
+        u32     pci_potar1;
+        u8      res35[4];
+        u32     pci_pobar1;
+        u8      res36[4];
+        u32     pci_pocmr1;
+        u8      res37[4];
+        u32     pci_potar2;
+        u8      res38[4];
+        u32     pci_pobar2;
+        u8      res39[4];
+        u32     pci_pocmr2;
+        u8      res40[50];
+        u32     pci_ptcr;
+        u32     pci_gpcr;
+        u32     pci_gcr;
+        u32     pci_esr;
+        u32     pci_emr;
+        u32     pci_ecr;
+        u32     pci_eacr;
+        u8      res41[4];
+        u32     pci_edcr;
+        u8      res42[4];
+        u32     pci_eccr;
+        u8      res43[44];
+        u32     pci_pitar1;
+        u8      res44[4];
+        u32     pci_pibar1;
+        u8      res45[4];
+        u32     pci_picmr1;
+        u8      res46[4];
+        u32     pci_pitar0;
+        u8      res47[4];
+        u32     pci_pibar0;
+        u8      res48[4];
+        u32     pci_picmr0;
+        u8      res49[4];
+        u32     pci_cfg_addr;
+        u32     pci_cfg_data;
+        u32     pci_int_ack;
+        u8      res50[756];
+} pci_cpm2_t;
+
+/* Interrupt Controller.
+*/
+typedef struct interrupt_controller {
+        u16     ic_sicr;
+        u8      res1[2];
+        u32     ic_sivec;
+        u32     ic_sipnrh;
+        u32     ic_sipnrl;
+        u32     ic_siprr;
+        u32     ic_scprrh;
+        u32     ic_scprrl;
+        u32     ic_simrh;
+        u32     ic_simrl;
+        u32     ic_siexr;
+        u8      res2[88];
+} intctl_cpm2_t;
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+        u32     car_sccr;
+        u8      res1[4];
+        u32     car_scmr;
+        u8      res2[4];
+        u32     car_rsr;
+        u32     car_rmr;
+        u8      res[104];
+} car_cpm2_t;
+
+/* Input/Output Port control/status registers.
+ * Names consistent with processor manual, although they are different
+ * from the original 8xx names.......
+ */
+typedef struct io_port {
+        u32     iop_pdira;
+        u32     iop_ppara;
+        u32     iop_psora;
+        u32     iop_podra;
+        u32     iop_pdata;
+        u8      res1[12];
+        u32     iop_pdirb;
+        u32     iop_pparb;
+        u32     iop_psorb;
+        u32     iop_podrb;
+        u32     iop_pdatb;
+        u8      res2[12];
+        u32     iop_pdirc;
+        u32     iop_pparc;
+        u32     iop_psorc;
+        u32     iop_podrc;
+        u32     iop_pdatc;
+        u8      res3[12];
+        u32     iop_pdird;
+        u32     iop_ppard;
+        u32     iop_psord;
+        u32     iop_podrd;
+        u32     iop_pdatd;
+        u8      res4[12];
+} iop_cpm2_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+        u8      cpmt_tgcr1;
+        u8      res1[3];
+        u8      cpmt_tgcr2;
+        u8      res2[11];
+        u16     cpmt_tmr1;
+        u16     cpmt_tmr2;
+        u16     cpmt_trr1;
+        u16     cpmt_trr2;
+        u16     cpmt_tcr1;
+        u16     cpmt_tcr2;
+        u16     cpmt_tcn1;
+        u16     cpmt_tcn2;
+        u16     cpmt_tmr3;
+        u16     cpmt_tmr4;
+        u16     cpmt_trr3;
+        u16     cpmt_trr4;
+        u16     cpmt_tcr3;
+        u16     cpmt_tcr4;
+        u16     cpmt_tcn3;
+        u16     cpmt_tcn4;
+        u16     cpmt_ter1;
+        u16     cpmt_ter2;
+        u16     cpmt_ter3;
+        u16     cpmt_ter4;
+        u8      res3[584];
+} cpmtimer_cpm2_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+        u8      res0[24];
+        u8      sdma_sdsr;
+        u8      res1[3];
+        u8      sdma_sdmr;
+        u8      res2[3];
+        u8      sdma_idsr1;
+        u8      res3[3];
+        u8      sdma_idmr1;
+        u8      res4[3];
+        u8      sdma_idsr2;
+        u8      res5[3];
+        u8      sdma_idmr2;
+        u8      res6[3];
+        u8      sdma_idsr3;
+        u8      res7[3];
+        u8      sdma_idmr3;
+        u8      res8[3];
+        u8      sdma_idsr4;
+        u8      res9[3];
+        u8      sdma_idmr4;
+        u8      res10[707];
+} sdma_cpm2_t;
+
+/* Fast controllers
+*/
+typedef struct fcc {
+        u32     fcc_gfmr;
+        u32     fcc_fpsmr;
+        u16     fcc_ftodr;
+        u8      res1[2];
+        u16     fcc_fdsr;
+        u8      res2[2];
+        u16     fcc_fcce;
+        u8      res3[2];
+        u16     fcc_fccm;
+        u8      res4[2];
+        u8      fcc_fccs;
+        u8      res5[3];
+        u8      fcc_ftirr_phy[4];
+} fcc_t;
+
+/* Fast controllers continued
+ */
+typedef struct fcc_c {
+        u32     fcc_firper;
+        u32     fcc_firer;
+        u32     fcc_firsr_hi;
+        u32     fcc_firsr_lo;
+        u8      fcc_gfemr;
+        u8      res1[15];
+} fcc_c_t;
+
+/* TC Layer
+ */
+typedef struct tclayer {
+        u16     tc_tcmode;
+        u16     tc_cdsmr;
+        u16     tc_tcer;
+        u16     tc_rcc;
+        u16     tc_tcmr;
+        u16     tc_fcc;
+        u16     tc_ccc;
+        u16     tc_icc;
+        u16     tc_tcc;
+        u16     tc_ecc;
+        u8      res1[12];
+} tclayer_t;
+
+
+/* I2C
+*/
+typedef struct i2c {
+        u8      i2c_i2mod;
+        u8      res1[3];
+        u8      i2c_i2add;
+        u8      res2[3];
+        u8      i2c_i2brg;
+        u8      res3[3];
+        u8      i2c_i2com;
+        u8      res4[3];
+        u8      i2c_i2cer;
+        u8      res5[3];
+        u8      i2c_i2cmr;
+        u8      res6[331];
+} i2c_cpm2_t;
+
+typedef struct scc {            /* Serial communication channels */
+        u32     scc_gsmrl;
+        u32     scc_gsmrh;
+        u16     scc_psmr;
+        u8      res1[2];
+        u16     scc_todr;
+        u16     scc_dsr;
+        u16     scc_scce;
+        u8      res2[2];
+        u16     scc_sccm;
+        u8      res3;
+        u8      scc_sccs;
+        u8      res4[8];
+} scc_t;
+
+typedef struct smc {            /* Serial management channels */
+        u8      res1[2];
+        u16     smc_smcmr;
+        u8      res2[2];
+        u8      smc_smce;
+        u8      res3[3];
+        u8      smc_smcm;
+        u8      res4[5];
+} smc_t;
+
+/* Serial Peripheral Interface.
+*/
+typedef struct spi_ctrl {
+        u16     spi_spmode;
+        u8      res1[4];
+        u8      spi_spie;
+        u8      res2[3];
+        u8      spi_spim;
+        u8      res3[2];
+        u8      spi_spcom;
+        u8      res4[82];
+} spictl_cpm2_t;
+
+/* CPM Mux.
+*/
+typedef struct cpmux {
+        u8      cmx_si1cr;
+        u8      res1;
+        u8      cmx_si2cr;
+        u8      res2;
+        u32     cmx_fcr;
+        u32     cmx_scr;
+        u8      cmx_smr;
+        u8      res3;
+        u16     cmx_uar;
+        u8      res4[16];
+} cpmux_t;
+
+/* SIRAM control
+*/
+typedef struct siram {
+        u16     si_amr;
+        u16     si_bmr;
+        u16     si_cmr;
+        u16     si_dmr;
+        u8      si_gmr;
+        u8      res1;
+        u8      si_cmdr;
+        u8      res2;
+        u8      si_str;
+        u8      res3;
+        u16     si_rsr;
+} siramctl_t;
+
+typedef struct mcc {
+        u16     mcc_mcce;
+        u8      res1[2];
+        u16     mcc_mccm;
+        u8      res2[2];
+        u8      mcc_mccf;
+        u8      res3[7];
+} mcc_t;
+
+typedef struct comm_proc {
+        u32     cp_cpcr;
+        u32     cp_rccr;
+        u8      res1[14];
+        u16     cp_rter;
+        u8      res2[2];
+        u16     cp_rtmr;
+        u16     cp_rtscr;
+        u8      res3[2];
+        u32     cp_rtsr;
+        u8      res4[12];
+} cpm_cpm2_t;
+
+/* USB Controller.
+*/
+typedef struct usb_ctlr {
+        u8      usb_usmod;
+        u8      usb_usadr;
+        u8      usb_uscom;
+        u8      res1[1];
+        u16     usb_usep1;
+        u16     usb_usep2;
+        u16     usb_usep3;
+        u16     usb_usep4;
+        u8      res2[4];
+        u16     usb_usber;
+        u8      res3[2];
+        u16     usb_usbmr;
+        u8      usb_usbs;
+        u8      res4[7];
+} usb_cpm2_t;
+
+/* ...and the whole thing wrapped up....
+*/
+
+typedef struct immap {
+        /* Some references are into the unique and known dpram spaces,
+         * others are from the generic base.
+         */
+#define im_dprambase    im_dpram1
+        u8              im_dpram1[16*1024];
+        u8              res1[16*1024];
+        u8              im_dpram2[4*1024];
+        u8              res2[8*1024];
+        u8              im_dpram3[4*1024];
+        u8              res3[16*1024];
+
+        sysconf_cpm2_t  im_siu_conf;    /* SIU Configuration */
+        memctl_cpm2_t   im_memctl;      /* Memory Controller */
+        sit_cpm2_t      im_sit;         /* System Integration Timers */
+        pci_cpm2_t      im_pci;         /* PCI Controller */
+        intctl_cpm2_t   im_intctl;      /* Interrupt Controller */
+        car_cpm2_t      im_clkrst;      /* Clocks and reset */
+        iop_cpm2_t      im_ioport;      /* IO Port control/status */
+        cpmtimer_cpm2_t im_cpmtimer;    /* CPM timers */
+        sdma_cpm2_t     im_sdma;        /* SDMA control/status */
+
+        fcc_t           im_fcc[3];      /* Three FCCs */
+        u8              res4z[32];
+        fcc_c_t         im_fcc_c[3];    /* Continued FCCs */
+
+        u8              res4[32];
+
+        tclayer_t       im_tclayer[8];  /* Eight TCLayers */
+        u16             tc_tcgsr;
+        u16             tc_tcger;
+
+        /* First set of baud rate generators.
+        */
+        u8              res[236];
+        u32             im_brgc5;
+        u32             im_brgc6;
+        u32             im_brgc7;
+        u32             im_brgc8;
+
+        u8              res5[608];
+
+        i2c_cpm2_t      im_i2c;         /* I2C control/status */
+        cpm_cpm2_t      im_cpm;         /* Communication processor */
+
+        /* Second set of baud rate generators.
+        */
+        u32             im_brgc1;
+        u32             im_brgc2;
+        u32             im_brgc3;
+        u32             im_brgc4;
+
+        scc_t           im_scc[4];      /* Four SCCs */
+        smc_t           im_smc[2];      /* Couple of SMCs */
+        spictl_cpm2_t   im_spi;         /* A SPI */
+        cpmux_t         im_cpmux;       /* CPM clock route mux */
+        siramctl_t      im_siramctl1;   /* First SI RAM Control */
+        mcc_t           im_mcc1;        /* First MCC */
+        siramctl_t      im_siramctl2;   /* Second SI RAM Control */
+        mcc_t           im_mcc2;        /* Second MCC */
+        usb_cpm2_t      im_usb;         /* USB Controller */
+
+        u8              res6[1153];
+
+        u16             im_si1txram[256];
+        u8              res7[512];
+        u16             im_si1rxram[256];
+        u8              res8[512];
+        u16             im_si2txram[256];
+        u8              res9[512];
+        u16             im_si2rxram[256];
+        u8              res10[512];
+        u8              res11[4096];
+} cpm2_map_t;
+
+extern cpm2_map_t __iomem *cpm2_immr;
+
+#endif /* __IMMAP_CPM2__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
new file mode 100644
index 000000000000..3c2fced3ac22
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -0,0 +1,483 @@
+/*
+ * QUICC Engine (QE) Internal Memory Map.
+ * The Internal Memory Map for devices with QE on them. This
+ * is the superset of all QE devices (8360, etc.).
+
+ * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:     Shlomi Gridish <gridish@freescale.com>
+ *              Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_POWERPC_IMMAP_QE_H
+#define _ASM_POWERPC_IMMAP_QE_H
+#ifdef __KERNEL__
+
+#include <linux/kernel.h>
+#include <asm/io.h>
+
+#define QE_IMMAP_SIZE   (1024 * 1024)   /* 1MB from 1MB+IMMR */
+
+/* QE I-RAM */
+struct qe_iram {
+        __be32  iadd;           /* I-RAM Address Register */
+        __be32  idata;          /* I-RAM Data Register */
+        u8      res0[0x78];
+} __attribute__ ((packed));
+
+/* QE Interrupt Controller */
+struct qe_ic_regs {
+        __be32  qicr;
+        __be32  qivec;
+        __be32  qripnr;
+        __be32  qipnr;
+        __be32  qipxcc;
+        __be32  qipycc;
+        __be32  qipwcc;
+        __be32  qipzcc;
+        __be32  qimr;
+        __be32  qrimr;
+        __be32  qicnr;
+        u8      res0[0x4];
+        __be32  qiprta;
+        __be32  qiprtb;
+        u8      res1[0x4];
+        __be32  qricr;
+        u8      res2[0x20];
+        __be32  qhivec;
+        u8      res3[0x1C];
+} __attribute__ ((packed));
+
+/* Communications Processor */
+struct cp_qe {
+        __be32  cecr;           /* QE command register */
+        __be32  ceccr;          /* QE controller configuration register */
+        __be32  cecdr;          /* QE command data register */
+        u8      res0[0xA];
+        __be16  ceter;          /* QE timer event register */
+        u8      res1[0x2];
+        __be16  cetmr;          /* QE timers mask register */
+        __be32  cetscr;         /* QE time-stamp timer control register */
+        __be32  cetsr1;         /* QE time-stamp register 1 */
+        __be32  cetsr2;         /* QE time-stamp register 2 */
+        u8      res2[0x8];
+        __be32  cevter;         /* QE virtual tasks event register */
+        __be32  cevtmr;         /* QE virtual tasks mask register */
+        __be16  cercr;          /* QE RAM control register */
+        u8      res3[0x2];
+        u8      res4[0x24];
+        __be16  ceexe1;         /* QE external request 1 event register */
+        u8      res5[0x2];
+        __be16  ceexm1;         /* QE external request 1 mask register */
+        u8      res6[0x2];
+        __be16  ceexe2;         /* QE external request 2 event register */
+        u8      res7[0x2];
+        __be16  ceexm2;         /* QE external request 2 mask register */
+        u8      res8[0x2];
+        __be16  ceexe3;         /* QE external request 3 event register */
+        u8      res9[0x2];
+        __be16  ceexm3;         /* QE external request 3 mask register */
+        u8      res10[0x2];
+        __be16  ceexe4;         /* QE external request 4 event register */
+        u8      res11[0x2];
+        __be16  ceexm4;         /* QE external request 4 mask register */
+        u8      res12[0x3A];
+        __be32  ceurnr;         /* QE microcode revision number register */
+        u8      res13[0x244];
+} __attribute__ ((packed));
+
+/* QE Multiplexer */
+struct qe_mux {
+        __be32  cmxgcr;         /* CMX general clock route register */
+        __be32  cmxsi1cr_l;     /* CMX SI1 clock route low register */
+        __be32  cmxsi1cr_h;     /* CMX SI1 clock route high register */
+        __be32  cmxsi1syr;      /* CMX SI1 SYNC route register */
+        __be32  cmxucr[4];      /* CMX UCCx clock route registers */
+        __be32  cmxupcr;        /* CMX UPC clock route register */
+        u8      res0[0x1C];
+} __attribute__ ((packed));
+
+/* QE Timers */
+struct qe_timers {
+        u8      gtcfr1;         /* Timer 1 and Timer 2 global config register*/
+        u8      res0[0x3];
+        u8      gtcfr2;         /* Timer 3 and timer 4 global config register*/
+        u8      res1[0xB];
+        __be16  gtmdr1;         /* Timer 1 mode register */
+        __be16  gtmdr2;         /* Timer 2 mode register */
+        __be16  gtrfr1;         /* Timer 1 reference register */
+        __be16  gtrfr2;         /* Timer 2 reference register */
+        __be16  gtcpr1;         /* Timer 1 capture register */
+        __be16  gtcpr2;         /* Timer 2 capture register */
+        __be16  gtcnr1;         /* Timer 1 counter */
+        __be16  gtcnr2;         /* Timer 2 counter */
+        __be16  gtmdr3;         /* Timer 3 mode register */
+        __be16  gtmdr4;         /* Timer 4 mode register */
+        __be16  gtrfr3;         /* Timer 3 reference register */
+        __be16  gtrfr4;         /* Timer 4 reference register */
+        __be16  gtcpr3;         /* Timer 3 capture register */
+        __be16  gtcpr4;         /* Timer 4 capture register */
+        __be16  gtcnr3;         /* Timer 3 counter */
+        __be16  gtcnr4;         /* Timer 4 counter */
+        __be16  gtevr1;         /* Timer 1 event register */
+        __be16  gtevr2;         /* Timer 2 event register */
+        __be16  gtevr3;         /* Timer 3 event register */
+        __be16  gtevr4;         /* Timer 4 event register */
+        __be16  gtps;           /* Timer 1 prescale register */
+        u8 res2[0x46];
+} __attribute__ ((packed));
+
+/* BRG */
+struct qe_brg {
+        __be32  brgc[16];       /* BRG configuration registers */
+        u8      res0[0x40];
+} __attribute__ ((packed));
+
+/* SPI */
+struct spi {
+        u8      res0[0x20];
+        __be32  spmode;         /* SPI mode register */
+        u8      res1[0x2];
+        u8      spie;           /* SPI event register */
+        u8      res2[0x1];
+        u8      res3[0x2];
+        u8      spim;           /* SPI mask register */
+        u8      res4[0x1];
+        u8      res5[0x1];
+        u8      spcom;          /* SPI command register */
+        u8      res6[0x2];
+        __be32  spitd;          /* SPI transmit data register (cpu mode) */
+        __be32  spird;          /* SPI receive data register (cpu mode) */
+        u8      res7[0x8];
+} __attribute__ ((packed));
+
+/* SI */
+struct si1 {
+        __be16  siamr1;         /* SI1 TDMA mode register */
+        __be16  sibmr1;         /* SI1 TDMB mode register */
+        __be16  sicmr1;         /* SI1 TDMC mode register */
+        __be16  sidmr1;         /* SI1 TDMD mode register */
+        u8      siglmr1_h;      /* SI1 global mode register high */
+        u8      res0[0x1];
+        u8      sicmdr1_h;      /* SI1 command register high */
+        u8      res2[0x1];
+        u8      sistr1_h;       /* SI1 status register high */
+        u8      res3[0x1];
+        __be16  sirsr1_h;       /* SI1 RAM shadow address register high */
+        u8      sitarc1;        /* SI1 RAM counter Tx TDMA */
+        u8      sitbrc1;        /* SI1 RAM counter Tx TDMB */
+        u8      sitcrc1;        /* SI1 RAM counter Tx TDMC */
+        u8      sitdrc1;        /* SI1 RAM counter Tx TDMD */
+        u8      sirarc1;        /* SI1 RAM counter Rx TDMA */
+        u8      sirbrc1;        /* SI1 RAM counter Rx TDMB */
+        u8      sircrc1;        /* SI1 RAM counter Rx TDMC */
+        u8      sirdrc1;        /* SI1 RAM counter Rx TDMD */
+        u8      res4[0x8];
+        __be16  siemr1;         /* SI1 TDME mode register 16 bits */
+        __be16  sifmr1;         /* SI1 TDMF mode register 16 bits */
+        __be16  sigmr1;         /* SI1 TDMG mode register 16 bits */
+        __be16  sihmr1;         /* SI1 TDMH mode register 16 bits */
+        u8      siglmg1_l;      /* SI1 global mode register low 8 bits */
+        u8      res5[0x1];
+        u8      sicmdr1_l;      /* SI1 command register low 8 bits */
+        u8      res6[0x1];
+        u8      sistr1_l;       /* SI1 status register low 8 bits */
+        u8      res7[0x1];
+        __be16  sirsr1_l;       /* SI1 RAM shadow address register low 16 bits*/
+        u8      siterc1;        /* SI1 RAM counter Tx TDME 8 bits */
+        u8      sitfrc1;        /* SI1 RAM counter Tx TDMF 8 bits */
+        u8      sitgrc1;        /* SI1 RAM counter Tx TDMG 8 bits */
+        u8      sithrc1;        /* SI1 RAM counter Tx TDMH 8 bits */
+        u8      sirerc1;        /* SI1 RAM counter Rx TDME 8 bits */
+        u8      sirfrc1;        /* SI1 RAM counter Rx TDMF 8 bits */
+        u8      sirgrc1;        /* SI1 RAM counter Rx TDMG 8 bits */
+        u8      sirhrc1;        /* SI1 RAM counter Rx TDMH 8 bits */
+        u8      res8[0x8];
+        __be32  siml1;          /* SI1 multiframe limit register */
+        u8      siedm1;         /* SI1 extended diagnostic mode register */
+        u8      res9[0xBB];
+} __attribute__ ((packed));
+
+/* SI Routing Tables */
+struct sir {
+        u8      tx[0x400];
+        u8      rx[0x400];
+        u8      res0[0x800];
+} __attribute__ ((packed));
+
+/* USB Controller */
+struct usb_ctlr {
+        u8      usb_usmod;
+        u8      usb_usadr;
+        u8      usb_uscom;
+        u8      res1[1];
+        __be16  usb_usep1;
+        __be16  usb_usep2;
+        __be16  usb_usep3;
+        __be16  usb_usep4;
+        u8      res2[4];
+        __be16  usb_usber;
+        u8      res3[2];
+        __be16  usb_usbmr;
+        u8      res4[1];
+        u8      usb_usbs;
+        __be16  usb_ussft;
+        u8      res5[2];
+        __be16  usb_usfrn;
+        u8      res6[0x22];
+} __attribute__ ((packed));
+
+/* MCC */
+struct mcc {
+        __be32  mcce;           /* MCC event register */
+        __be32  mccm;           /* MCC mask register */
+        __be32  mccf;           /* MCC configuration register */
+        __be32  merl;           /* MCC emergency request level register */
+        u8      res0[0xF0];
+} __attribute__ ((packed));
+
+/* QE UCC Slow */
+struct ucc_slow {
+        __be32  gumr_l;         /* UCCx general mode register (low) */
+        __be32  gumr_h;         /* UCCx general mode register (high) */
+        __be16  upsmr;          /* UCCx protocol-specific mode register */
+        u8      res0[0x2];
+        __be16  utodr;          /* UCCx transmit on demand register */
+        __be16  udsr;           /* UCCx data synchronization register */
+        __be16  ucce;           /* UCCx event register */
+        u8      res1[0x2];
+        __be16  uccm;           /* UCCx mask register */
+        u8      res2[0x1];
+        u8      uccs;           /* UCCx status register */
+        u8      res3[0x24];
+        __be16  utpt;
+        u8      res4[0x52];
+        u8      guemr;          /* UCC general extended mode register */
+} __attribute__ ((packed));
+
+/* QE UCC Fast */
+struct ucc_fast {
+        __be32  gumr;           /* UCCx general mode register */
+        __be32  upsmr;          /* UCCx protocol-specific mode register */
+        __be16  utodr;          /* UCCx transmit on demand register */
+        u8      res0[0x2];
+        __be16  udsr;           /* UCCx data synchronization register */
+        u8      res1[0x2];
+        __be32  ucce;           /* UCCx event register */
+        __be32  uccm;           /* UCCx mask register */
+        u8      uccs;           /* UCCx status register */
+        u8      res2[0x7];
+        __be32  urfb;           /* UCC receive FIFO base */
+        __be16  urfs;           /* UCC receive FIFO size */
+        u8      res3[0x2];
+        __be16  urfet;          /* UCC receive FIFO emergency threshold */
+        __be16  urfset;         /* UCC receive FIFO special emergency
+                                   threshold */
+        __be32  utfb;           /* UCC transmit FIFO base */
+        __be16  utfs;           /* UCC transmit FIFO size */
+        u8      res4[0x2];
+        __be16  utfet;          /* UCC transmit FIFO emergency threshold */
+        u8      res5[0x2];
+        __be16  utftt;          /* UCC transmit FIFO transmit threshold */
+        u8      res6[0x2];
+        __be16  utpt;           /* UCC transmit polling timer */
+        u8      res7[0x2];
+        __be32  urtry;          /* UCC retry counter register */
+        u8      res8[0x4C];
+        u8      guemr;          /* UCC general extended mode register */
+} __attribute__ ((packed));
+
+struct ucc {
+        union {
+                struct  ucc_slow slow;
+                struct  ucc_fast fast;
+                u8      res[0x200];     /* UCC blocks are 512 bytes each */
+        };
+} __attribute__ ((packed));
+
+/* MultiPHY UTOPIA POS Controllers (UPC) */
+struct upc {
+        __be32  upgcr;          /* UTOPIA/POS general configuration register */
+        __be32  uplpa;          /* UTOPIA/POS last PHY address */
+        __be32  uphec;          /* ATM HEC register */
+        __be32  upuc;           /* UTOPIA/POS UCC configuration */
+        __be32  updc1;          /* UTOPIA/POS device 1 configuration */
+        __be32  updc2;          /* UTOPIA/POS device 2 configuration */
+        __be32  updc3;          /* UTOPIA/POS device 3 configuration */
+        __be32  updc4;          /* UTOPIA/POS device 4 configuration */
+        __be32  upstpa;         /* UTOPIA/POS STPA threshold */
+        u8      res0[0xC];
+        __be32  updrs1_h;       /* UTOPIA/POS device 1 rate select */
+        __be32  updrs1_l;       /* UTOPIA/POS device 1 rate select */
+        __be32  updrs2_h;       /* UTOPIA/POS device 2 rate select */
+        __be32  updrs2_l;       /* UTOPIA/POS device 2 rate select */
+        __be32  updrs3_h;       /* UTOPIA/POS device 3 rate select */
+        __be32  updrs3_l;       /* UTOPIA/POS device 3 rate select */
+        __be32  updrs4_h;       /* UTOPIA/POS device 4 rate select */
+        __be32  updrs4_l;       /* UTOPIA/POS device 4 rate select */
+        __be32  updrp1;         /* UTOPIA/POS device 1 receive priority low */
+        __be32  updrp2;         /* UTOPIA/POS device 2 receive priority low */
+        __be32  updrp3;         /* UTOPIA/POS device 3 receive priority low */
+        __be32  updrp4;         /* UTOPIA/POS device 4 receive priority low */
+        __be32  upde1;          /* UTOPIA/POS device 1 event */
+        __be32  upde2;          /* UTOPIA/POS device 2 event */
+        __be32  upde3;          /* UTOPIA/POS device 3 event */
+        __be32  upde4;          /* UTOPIA/POS device 4 event */
+        __be16  uprp1;
+        __be16  uprp2;
+        __be16  uprp3;
+        __be16  uprp4;
+        u8      res1[0x8];
+        __be16  uptirr1_0;      /* Device 1 transmit internal rate 0 */
+        __be16  uptirr1_1;      /* Device 1 transmit internal rate 1 */
+        __be16  uptirr1_2;      /* Device 1 transmit internal rate 2 */
+        __be16  uptirr1_3;      /* Device 1 transmit internal rate 3 */
+        __be16  uptirr2_0;      /* Device 2 transmit internal rate 0 */
+        __be16  uptirr2_1;      /* Device 2 transmit internal rate 1 */
+        __be16  uptirr2_2;      /* Device 2 transmit internal rate 2 */
+        __be16  uptirr2_3;      /* Device 2 transmit internal rate 3 */
+        __be16  uptirr3_0;      /* Device 3 transmit internal rate 0 */
+        __be16  uptirr3_1;      /* Device 3 transmit internal rate 1 */
+        __be16  uptirr3_2;      /* Device 3 transmit internal rate 2 */
+        __be16  uptirr3_3;      /* Device 3 transmit internal rate 3 */
+        __be16  uptirr4_0;      /* Device 4 transmit internal rate 0 */
+        __be16  uptirr4_1;      /* Device 4 transmit internal rate 1 */
+        __be16  uptirr4_2;      /* Device 4 transmit internal rate 2 */
+        __be16  uptirr4_3;      /* Device 4 transmit internal rate 3 */
+        __be32  uper1;          /* Device 1 port enable register */
+        __be32  uper2;          /* Device 2 port enable register */
+        __be32  uper3;          /* Device 3 port enable register */
+        __be32  uper4;          /* Device 4 port enable register */
+        u8      res2[0x150];
+} __attribute__ ((packed));
+
+/* SDMA */
+struct sdma {
+        __be32  sdsr;           /* Serial DMA status register */
+        __be32  sdmr;           /* Serial DMA mode register */
+        __be32  sdtr1;          /* SDMA system bus threshold register */
+        __be32  sdtr2;          /* SDMA secondary bus threshold register */
+        __be32  sdhy1;          /* SDMA system bus hysteresis register */
+        __be32  sdhy2;          /* SDMA secondary bus hysteresis register */
+        __be32  sdta1;          /* SDMA system bus address register */
+        __be32  sdta2;          /* SDMA secondary bus address register */
+        __be32  sdtm1;          /* SDMA system bus MSNUM register */
+        __be32  sdtm2;          /* SDMA secondary bus MSNUM register */
+        u8      res0[0x10];
+        __be32  sdaqr;          /* SDMA address bus qualify register */
+        __be32  sdaqmr;         /* SDMA address bus qualify mask register */
+        u8      res1[0x4];
+        __be32  sdebcr;         /* SDMA CAM entries base register */
+        u8      res2[0x38];
+} __attribute__ ((packed));
+
+/* Debug Space */
+struct dbg {
+        __be32  bpdcr;          /* Breakpoint debug command register */
+        __be32  bpdsr;          /* Breakpoint debug status register */
+        __be32  bpdmr;          /* Breakpoint debug mask register */
+        __be32  bprmrr0;        /* Breakpoint request mode risc register 0 */
+        __be32  bprmrr1;        /* Breakpoint request mode risc register 1 */
+        u8      res0[0x8];
+        __be32  bprmtr0;        /* Breakpoint request mode trb register 0 */
+        __be32  bprmtr1;        /* Breakpoint request mode trb register 1 */
+        u8      res1[0x8];
+        __be32  bprmir;         /* Breakpoint request mode immediate register */
+        __be32  bprmsr;         /* Breakpoint request mode serial register */
+        __be32  bpemr;          /* Breakpoint exit mode register */
+        u8      res2[0x48];
+} __attribute__ ((packed));
+
+/*
+ * RISC Special Registers (Trap and Breakpoint).  These are described in
+ * the QE Developer's Handbook.
+ */
+struct rsp {
+        __be32 tibcr[16];       /* Trap/instruction breakpoint control regs */
+        u8 res0[64];
+        __be32 ibcr0;
+        __be32 ibs0;
+        __be32 ibcnr0;
+        u8 res1[4];
+        __be32 ibcr1;
+        __be32 ibs1;
+        __be32 ibcnr1;
+        __be32 npcr;
+        __be32 dbcr;
+        __be32 dbar;
+        __be32 dbamr;
+        __be32 dbsr;
+        __be32 dbcnr;
+        u8 res2[12];
+        __be32 dbdr_h;
+        __be32 dbdr_l;
+        __be32 dbdmr_h;
+        __be32 dbdmr_l;
+        __be32 bsr;
+        __be32 bor;
+        __be32 bior;
+        u8 res3[4];
+        __be32 iatr[4];
+        __be32 eccr;            /* Exception control configuration register */
+        __be32 eicr;
+        u8 res4[0x100-0xf8];
+} __attribute__ ((packed));
+
+struct qe_immap {
+        struct qe_iram          iram;           /* I-RAM */
+        struct qe_ic_regs       ic;             /* Interrupt Controller */
+        struct cp_qe            cp;             /* Communications Processor */
+        struct qe_mux           qmx;            /* QE Multiplexer */
+        struct qe_timers        qet;            /* QE Timers */
+        struct spi              spi[0x2];       /* spi */
+        struct mcc              mcc;            /* mcc */
+        struct qe_brg           brg;            /* brg */
+        struct usb_ctlr         usb;            /* USB */
+        struct si1              si1;            /* SI */
+        u8                      res11[0x800];
+        struct sir              sir;            /* SI Routing Tables */
+        struct ucc              ucc1;           /* ucc1 */
+        struct ucc              ucc3;           /* ucc3 */
+        struct ucc              ucc5;           /* ucc5 */
+        struct ucc              ucc7;           /* ucc7 */
+        u8                      res12[0x600];
+        struct upc              upc1;           /* MultiPHY UTOPIA POS Ctrlr 1*/
+        struct ucc              ucc2;           /* ucc2 */
+        struct ucc              ucc4;           /* ucc4 */
+        struct ucc              ucc6;           /* ucc6 */
+        struct ucc              ucc8;           /* ucc8 */
+        u8                      res13[0x600];
+        struct upc              upc2;           /* MultiPHY UTOPIA POS Ctrlr 2*/
+        struct sdma             sdma;           /* SDMA */
+        struct dbg              dbg;            /* 0x104080 - 0x1040FF
+                                                   Debug Space */
+        struct rsp              rsp[0x2];       /* 0x104100 - 0x1042FF
+                                                   RISC Special Registers
+                                                   (Trap and Breakpoint) */
+        u8                      res14[0x300];   /* 0x104300 - 0x1045FF */
+        u8                      res15[0x3A00];  /* 0x104600 - 0x107FFF */
+        u8                      res16[0x8000];  /* 0x108000 - 0x110000 */
+        u8                      muram[0xC000];  /* 0x110000 - 0x11C000
+                                                   Multi-user RAM */
+        u8                      res17[0x24000]; /* 0x11C000 - 0x140000 */
+        u8                      res18[0xC0000]; /* 0x140000 - 0x200000 */
+} __attribute__ ((packed));
+
+extern struct qe_immap __iomem *qe_immr;
+extern phys_addr_t get_qe_base(void);
+
+static inline unsigned long immrbar_virt_to_phys(void *address)
+{
+        if ( ((u32)address >= (u32)qe_immr) &&
+                        ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
+                return (unsigned long)(address - (u32)qe_immr +
+                                (u32)get_qe_base());
+        return (unsigned long)virt_to_phys(address);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_IMMAP_QE_H */
diff --git a/arch/powerpc/include/asm/io-defs.h b/arch/powerpc/include/asm/io-defs.h
new file mode 100644
index 000000000000..44d7927aec69
--- /dev/null
+++ b/arch/powerpc/include/asm/io-defs.h
@@ -0,0 +1,60 @@
+/* This file is meant to be include multiple times by other headers */
+/* last 2 argments are used by platforms/cell/io-workarounds.[ch] */
+
+DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr), mem, addr)
+DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
+DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
+DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
+DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
+DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
+DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
+DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
+DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
+DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
+
+#ifdef __powerpc64__
+DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
+DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
+DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
+DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
+#endif /* __powerpc64__ */
+
+DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port), pio, port)
+DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port), pio, port)
+DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port), pio, port)
+DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port), pio, port)
+DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port), pio, port)
+DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port), pio, port)
+
+DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c),
+                 (a, b, c), mem, a)
+DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c),
+                 (a, b, c), mem, a)
+DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c),
+                 (a, b, c), mem, a)
+DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c),
+                 (a, b, c), mem, a)
+DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c),
+                 (a, b, c), mem, a)
+DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c),
+                 (a, b, c), mem, a)
+
+DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c),
+                 (p, b, c), pio, p)
+DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
+                 (p, b, c), pio, p)
+DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
+                 (p, b, c), pio, p)
+DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
+                 (p, b, c), pio, p)
+DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
+                 (p, b, c), pio, p)
+DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
+                 (p, b, c), pio, p)
+
+DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n),
+                 (a, c, n), mem, a)
+DEF_PCI_AC_NORET(memcpy_fromio, (void *d, const PCI_IO_ADDR s, unsigned long n),
+                 (d, s, n), mem, s)
+DEF_PCI_AC_NORET(memcpy_toio, (PCI_IO_ADDR d, const void *s, unsigned long n),
+                 (d, s, n), mem, d)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
new file mode 100644
index 000000000000..77c7fa025e65
--- /dev/null
+++ b/arch/powerpc/include/asm/io.h
@@ -0,0 +1,787 @@
+#ifndef _ASM_POWERPC_IO_H
+#define _ASM_POWERPC_IO_H
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/* Check of existence of legacy devices */
+extern int check_legacy_ioport(unsigned long base_port);
+#define I8042_DATA_REG  0x60
+#define FDC_BASE        0x3f0
+/* only relevant for PReP */
+#define _PIDXR          0x279
+#define _PNPWRP         0xa79
+#define PNPBIOS_BASE    0xf000
+
+#include <linux/device.h>
+#include <linux/io.h>
+
+#include <linux/compiler.h>
+#include <asm/page.h>
+#include <asm/byteorder.h>
+#include <asm/synch.h>
+#include <asm/delay.h>
+#include <asm/mmu.h>
+
+#include <asm-generic/iomap.h>
+
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+#endif
+
+#define SIO_CONFIG_RA   0x398
+#define SIO_CONFIG_RD   0x399
+
+#define SLOW_DOWN_IO
+
+/* 32 bits uses slightly different variables for the various IO
+ * bases. Most of this file only uses _IO_BASE though which we
+ * define properly based on the platform
+ */
+#ifndef CONFIG_PCI
+#define _IO_BASE        0
+#define _ISA_MEM_BASE   0
+#define PCI_DRAM_OFFSET 0
+#elif defined(CONFIG_PPC32)
+#define _IO_BASE        isa_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define _IO_BASE        pci_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#define PCI_DRAM_OFFSET 0
+#endif
+
+extern unsigned long isa_io_base;
+extern unsigned long pci_io_base;
+extern unsigned long pci_dram_offset;
+
+extern resource_size_t isa_mem_base;
+
+#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
+#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
+#endif
+
+/*
+ *
+ * Low level MMIO accessors
+ *
+ * This provides the non-bus specific accessors to MMIO. Those are PowerPC
+ * specific and thus shouldn't be used in generic code. The accessors
+ * provided here are:
+ *
+ *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
+ *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
+ *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
+ *
+ * Those operate directly on a kernel virtual address. Note that the prototype
+ * for the out_* accessors has the arguments in opposite order from the usual
+ * linux PCI accessors. Unlike those, they take the address first and the value
+ * next.
+ *
+ * Note: I might drop the _ns suffix on the stream operations soon as it is
+ * simply normal for stream operations to not swap in the first place.
+ *
+ */
+
+#ifdef CONFIG_PPC64
+#define IO_SET_SYNC_FLAG()      do { local_paca->io_sync = 1; } while(0)
+#else
+#define IO_SET_SYNC_FLAG()
+#endif
+
+/* gcc 4.0 and older doesn't have 'Z' constraint */
+#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
+#define DEF_MMIO_IN_LE(name, size, insn)                                \
+static inline u##size name(const volatile u##size __iomem *addr)        \
+{                                                                       \
+        u##size ret;                                                    \
+        __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync"    \
+                : "=r" (ret) : "r" (addr), "m" (*addr) : "memory");     \
+        return ret;                                                     \
+}
+
+#define DEF_MMIO_OUT_LE(name, size, insn)                               \
+static inline void name(volatile u##size __iomem *addr, u##size val)    \
+{                                                                       \
+        __asm__ __volatile__("sync;"#insn" %1,0,%2"                     \
+                : "=m" (*addr) : "r" (val), "r" (addr) : "memory");     \
+        IO_SET_SYNC_FLAG();                                             \
+}
+#else /* newer gcc */
+#define DEF_MMIO_IN_LE(name, size, insn)                                \
+static inline u##size name(const volatile u##size __iomem *addr)        \
+{                                                                       \
+        u##size ret;                                                    \
+        __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"     \
+                : "=r" (ret) : "Z" (*addr) : "memory");                 \
+        return ret;                                                     \
+}
+
+#define DEF_MMIO_OUT_LE(name, size, insn)                               \
+static inline void name(volatile u##size __iomem *addr, u##size val)    \
+{                                                                       \
+        __asm__ __volatile__("sync;"#insn" %1,%y0"                      \
+                : "=Z" (*addr) : "r" (val) : "memory");                 \
+        IO_SET_SYNC_FLAG();                                             \
+}
+#endif
+
+#define DEF_MMIO_IN_BE(name, size, insn)                                \
+static inline u##size name(const volatile u##size __iomem *addr)        \
+{                                                                       \
+        u##size ret;                                                    \
+        __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
+                : "=r" (ret) : "m" (*addr) : "memory");                 \
+        return ret;                                                     \
+}
+
+#define DEF_MMIO_OUT_BE(name, size, insn)                               \
+static inline void name(volatile u##size __iomem *addr, u##size val)    \
+{                                                                       \
+        __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"                 \
+                : "=m" (*addr) : "r" (val) : "memory");                 \
+        IO_SET_SYNC_FLAG();                                             \
+}
+
+
+DEF_MMIO_IN_BE(in_8,     8, lbz);
+DEF_MMIO_IN_BE(in_be16, 16, lhz);
+DEF_MMIO_IN_BE(in_be32, 32, lwz);
+DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
+DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
+
+DEF_MMIO_OUT_BE(out_8,     8, stb);
+DEF_MMIO_OUT_BE(out_be16, 16, sth);
+DEF_MMIO_OUT_BE(out_be32, 32, stw);
+DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
+DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
+
+#ifdef __powerpc64__
+DEF_MMIO_OUT_BE(out_be64, 64, std);
+DEF_MMIO_IN_BE(in_be64, 64, ld);
+
+/* There is no asm instructions for 64 bits reverse loads and stores */
+static inline u64 in_le64(const volatile u64 __iomem *addr)
+{
+        return swab64(in_be64(addr));
+}
+
+static inline void out_le64(volatile u64 __iomem *addr, u64 val)
+{
+        out_be64(addr, swab64(val));
+}
+#endif /* __powerpc64__ */
+
+/*
+ * Low level IO stream instructions are defined out of line for now
+ */
+extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
+extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
+extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
+extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
+extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
+extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
+
+/* The _ns naming is historical and will be removed. For now, just #define
+ * the non _ns equivalent names
+ */
+#define _insw   _insw_ns
+#define _insl   _insl_ns
+#define _outsw  _outsw_ns
+#define _outsl  _outsl_ns
+
+
+/*
+ * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
+ */
+
+extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
+extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
+                           unsigned long n);
+extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
+                         unsigned long n);
+
+/*
+ *
+ * PCI and standard ISA accessors
+ *
+ * Those are globally defined linux accessors for devices on PCI or ISA
+ * busses. They follow the Linux defined semantics. The current implementation
+ * for PowerPC is as close as possible to the x86 version of these, and thus
+ * provides fairly heavy weight barriers for the non-raw versions
+ *
+ * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
+ * allowing the platform to provide its own implementation of some or all
+ * of the accessors.
+ */
+
+/*
+ * Include the EEH definitions when EEH is enabled only so they don't get
+ * in the way when building for 32 bits
+ */
+#ifdef CONFIG_EEH
+#include <asm/eeh.h>
+#endif
+
+/* Shortcut to the MMIO argument pointer */
+#define PCI_IO_ADDR     volatile void __iomem *
+
+/* Indirect IO address tokens:
+ *
+ * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
+ * on all IOs. (Note that this is all 64 bits only for now)
+ *
+ * To help platforms who may need to differenciate MMIO addresses in
+ * their hooks, a bitfield is reserved for use by the platform near the
+ * top of MMIO addresses (not PIO, those have to cope the hard way).
+ *
+ * This bit field is 12 bits and is at the top of the IO virtual
+ * addresses PCI_IO_INDIRECT_TOKEN_MASK.
+ *
+ * The kernel virtual space is thus:
+ *
+ *  0xD000000000000000          : vmalloc
+ *  0xD000080000000000          : PCI PHB IO space
+ *  0xD000080080000000          : ioremap
+ *  0xD0000fffffffffff          : end of ioremap region
+ *
+ * Since the top 4 bits are reserved as the region ID, we use thus
+ * the next 12 bits and keep 4 bits available for the future if the
+ * virtual address space is ever to be extended.
+ *
+ * The direct IO mapping operations will then mask off those bits
+ * before doing the actual access, though that only happen when
+ * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
+ * mechanism
+ */
+
+#ifdef CONFIG_PPC_INDIRECT_IO
+#define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
+#define PCI_IO_IND_TOKEN_SHIFT  48
+#define PCI_FIX_ADDR(addr)                                              \
+        ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
+#define PCI_GET_ADDR_TOKEN(addr)                                        \
+        (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
+                PCI_IO_IND_TOKEN_SHIFT)
+#define PCI_SET_ADDR_TOKEN(addr, token)                                 \
+do {                                                                    \
+        unsigned long __a = (unsigned long)(addr);                      \
+        __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
+        __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
+        (addr) = (void __iomem *)__a;                                   \
+} while(0)
+#else
+#define PCI_FIX_ADDR(addr) (addr)
+#endif
+
+
+/*
+ * Non ordered and non-swapping "raw" accessors
+ */
+
+static inline unsigned char __raw_readb(const volatile void __iomem *addr)
+{
+        return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned short __raw_readw(const volatile void __iomem *addr)
+{
+        return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned int __raw_readl(const volatile void __iomem *addr)
+{
+        return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
+}
+static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
+{
+        *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
+{
+        *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
+{
+        *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
+}
+
+#ifdef __powerpc64__
+static inline unsigned long __raw_readq(const volatile void __iomem *addr)
+{
+        return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
+}
+static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
+{
+        *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
+}
+#endif /* __powerpc64__ */
+
+/*
+ *
+ * PCI PIO and MMIO accessors.
+ *
+ *
+ * On 32 bits, PIO operations have a recovery mechanism in case they trigger
+ * machine checks (which they occasionally do when probing non existing
+ * IO ports on some platforms, like PowerMac and 8xx).
+ * I always found it to be of dubious reliability and I am tempted to get
+ * rid of it one of these days. So if you think it's important to keep it,
+ * please voice up asap. We never had it for 64 bits and I do not intend
+ * to port it over
+ */
+
+#ifdef CONFIG_PPC32
+
+#define __do_in_asm(name, op)                           \
+static inline unsigned int name(unsigned int port)      \
+{                                                       \
+        unsigned int x;                                 \
+        __asm__ __volatile__(                           \
+                "sync\n"                                \
+                "0:"    op "    %0,0,%1\n"              \
+                "1:     twi     0,%0,0\n"               \
+                "2:     isync\n"                        \
+                "3:     nop\n"                          \
+                "4:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "5:     li      %0,-1\n"                \
+                "       b       4b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align  2\n"                    \
+                "       .long   0b,5b\n"                \
+                "       .long   1b,5b\n"                \
+                "       .long   2b,5b\n"                \
+                "       .long   3b,5b\n"                \
+                ".previous"                             \
+                : "=&r" (x)                             \
+                : "r" (port + _IO_BASE)                 \
+                : "memory");                            \
+        return x;                                       \
+}
+
+#define __do_out_asm(name, op)                          \
+static inline void name(unsigned int val, unsigned int port) \
+{                                                       \
+        __asm__ __volatile__(                           \
+                "sync\n"                                \
+                "0:" op " %0,0,%1\n"                    \
+                "1:     sync\n"                         \
+                "2:\n"                                  \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align  2\n"                    \
+                "       .long   0b,2b\n"                \
+                "       .long   1b,2b\n"                \
+                ".previous"                             \
+                : : "r" (val), "r" (port + _IO_BASE)    \
+                : "memory");                            \
+}
+
+__do_in_asm(_rec_inb, "lbzx")
+__do_in_asm(_rec_inw, "lhbrx")
+__do_in_asm(_rec_inl, "lwbrx")
+__do_out_asm(_rec_outb, "stbx")
+__do_out_asm(_rec_outw, "sthbrx")
+__do_out_asm(_rec_outl, "stwbrx")
+
+#endif /* CONFIG_PPC32 */
+
+/* The "__do_*" operations below provide the actual "base" implementation
+ * for each of the defined acccessor. Some of them use the out_* functions
+ * directly, some of them still use EEH, though we might change that in the
+ * future. Those macros below provide the necessary argument swapping and
+ * handling of the IO base for PIO.
+ *
+ * They are themselves used by the macros that define the actual accessors
+ * and can be used by the hooks if any.
+ *
+ * Note that PIO operations are always defined in terms of their corresonding
+ * MMIO operations. That allows platforms like iSeries who want to modify the
+ * behaviour of both to only hook on the MMIO version and get both. It's also
+ * possible to hook directly at the toplevel PIO operation if they have to
+ * be handled differently
+ */
+#define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
+#define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
+#define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
+#define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
+#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
+#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
+#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
+
+#ifdef CONFIG_EEH
+#define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
+#define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
+#define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
+#define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
+#define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
+#define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
+#define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
+#else /* CONFIG_EEH */
+#define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
+#define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
+#define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
+#define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
+#define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
+#define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
+#define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
+#endif /* !defined(CONFIG_EEH) */
+
+#ifdef CONFIG_PPC32
+#define __do_outb(val, port)    _rec_outb(val, port)
+#define __do_outw(val, port)    _rec_outw(val, port)
+#define __do_outl(val, port)    _rec_outl(val, port)
+#define __do_inb(port)          _rec_inb(port)
+#define __do_inw(port)          _rec_inw(port)
+#define __do_inl(port)          _rec_inl(port)
+#else /* CONFIG_PPC32 */
+#define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
+#define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
+#define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
+#define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
+#define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
+#define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
+#endif /* !CONFIG_PPC32 */
+
+#ifdef CONFIG_EEH
+#define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
+#else /* CONFIG_EEH */
+#define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
+#define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
+#endif /* !CONFIG_EEH */
+#define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
+#define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
+#define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
+
+#define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
+#define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
+#define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
+#define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
+#define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
+#define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
+
+#define __do_memset_io(addr, c, n)      \
+                                _memset_io(PCI_FIX_ADDR(addr), c, n)
+#define __do_memcpy_toio(dst, src, n)   \
+                                _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
+
+#ifdef CONFIG_EEH
+#define __do_memcpy_fromio(dst, src, n) \
+                                eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
+#else /* CONFIG_EEH */
+#define __do_memcpy_fromio(dst, src, n) \
+                                _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
+#endif /* !CONFIG_EEH */
+
+#ifdef CONFIG_PPC_INDIRECT_IO
+#define DEF_PCI_HOOK(x)         x
+#else
+#define DEF_PCI_HOOK(x)         NULL
+#endif
+
+/* Structure containing all the hooks */
+extern struct ppc_pci_io {
+
+#define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
+#define DEF_PCI_AC_NORET(name, at, al, space, aa)       void (*name) at;
+
+#include <asm/io-defs.h>
+
+#undef DEF_PCI_AC_RET
+#undef DEF_PCI_AC_NORET
+
+} ppc_pci_io;
+
+/* The inline wrappers */
+#define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
+static inline ret name at                                       \
+{                                                               \
+        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
+                return ppc_pci_io.name al;                      \
+        return __do_##name al;                                  \
+}
+
+#define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
+static inline void name at                                      \
+{                                                               \
+        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
+                ppc_pci_io.name al;                             \
+        else                                                    \
+                __do_##name al;                                 \
+}
+
+#include <asm/io-defs.h>
+
+#undef DEF_PCI_AC_RET
+#undef DEF_PCI_AC_NORET
+
+/* Some drivers check for the presence of readq & writeq with
+ * a #ifdef, so we make them happy here.
+ */
+#ifdef __powerpc64__
+#define readq   readq
+#define writeq  writeq
+#endif
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+/*
+ * We don't do relaxed operations yet, at least not with this semantic
+ */
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+#define readq_relaxed(addr) readq(addr)
+
+#ifdef CONFIG_PPC32
+#define mmiowb()
+#else
+/*
+ * Enforce synchronisation of stores vs. spin_unlock
+ * (this does it explicitly, though our implementation of spin_unlock
+ * does it implicitely too)
+ */
+static inline void mmiowb(void)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
+        : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
+        : "memory");
+}
+#endif /* !CONFIG_PPC32 */
+
+static inline void iosync(void)
+{
+        __asm__ __volatile__ ("sync" : : : "memory");
+}
+
+/* Enforce in-order execution of data I/O.
+ * No distinction between read/write on PPC; use eieio for all three.
+ * Those are fairly week though. They don't provide a barrier between
+ * MMIO and cacheable storage nor do they provide a barrier vs. locks,
+ * they only provide barriers between 2 __raw MMIO operations and
+ * possibly break write combining.
+ */
+#define iobarrier_rw() eieio()
+#define iobarrier_r()  eieio()
+#define iobarrier_w()  eieio()
+
+
+/*
+ * output pause versions need a delay at least for the
+ * w83c105 ide controller in a p610.
+ */
+#define inb_p(port)             inb(port)
+#define outb_p(val, port)       (udelay(1), outb((val), (port)))
+#define inw_p(port)             inw(port)
+#define outw_p(val, port)       (udelay(1), outw((val), (port)))
+#define inl_p(port)             inl(port)
+#define outl_p(val, port)       (udelay(1), outl((val), (port)))
+
+
+#define IO_SPACE_LIMIT ~(0UL)
+
+
+/**
+ * ioremap     -   map bus memory into CPU space
+ * @address:   bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * We provide a few variations of it:
+ *
+ * * ioremap is the standard one and provides non-cacheable guarded mappings
+ *   and can be hooked by the platform via ppc_md
+ *
+ * * ioremap_flags allows to specify the page flags as an argument and can
+ *   also be hooked by the platform via ppc_md. ioremap_prot is the exact
+ *   same thing as ioremap_flags.
+ *
+ * * ioremap_nocache is identical to ioremap
+ *
+ * * iounmap undoes such a mapping and can be hooked
+ *
+ * * __ioremap_at (and the pending __iounmap_at) are low level functions to
+ *   create hand-made mappings for use only by the PCI code and cannot
+ *   currently be hooked. Must be page aligned.
+ *
+ * * __ioremap is the low level implementation used by ioremap and
+ *   ioremap_flags and cannot be hooked (but can be used by a hook on one
+ *   of the previous ones)
+ *
+ * * __iounmap, is the low level implementation used by iounmap and cannot
+ *   be hooked (but can be used by a hook on iounmap)
+ *
+ */
+extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
+extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
+                                   unsigned long flags);
+#define ioremap_nocache(addr, size)     ioremap((addr), (size))
+#define ioremap_prot(addr, size, prot)  ioremap_flags((addr), (size), (prot))
+
+extern void iounmap(volatile void __iomem *addr);
+
+extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
+                               unsigned long flags);
+extern void __iounmap(volatile void __iomem *addr);
+
+extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
+                                   unsigned long size, unsigned long flags);
+extern void __iounmap_at(void *ea, unsigned long size);
+
+/*
+ * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
+ * which needs some additional definitions here. They basically allow PIO
+ * space overall to be 1GB. This will work as long as we never try to use
+ * iomap to map MMIO below 1GB which should be fine on ppc64
+ */
+#define HAVE_ARCH_PIO_SIZE              1
+#define PIO_OFFSET                      0x00000000UL
+#define PIO_MASK                        (FULL_IO_SIZE - 1)
+#define PIO_RESERVED                    (FULL_IO_SIZE)
+
+#define mmio_read16be(addr)             readw_be(addr)
+#define mmio_read32be(addr)             readl_be(addr)
+#define mmio_write16be(val, addr)       writew_be(val, addr)
+#define mmio_write32be(val, addr)       writel_be(val, addr)
+#define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
+#define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
+#define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
+#define mmio_outsb(addr, src, count)    writesb(addr, src, count)
+#define mmio_outsw(addr, src, count)    writesw(addr, src, count)
+#define mmio_outsl(addr, src, count)    writesl(addr, src, count)
+
+/**
+ *      virt_to_phys    -       map virtual addresses to physical
+ *      @address: address to remap
+ *
+ *      The returned physical address is the physical (CPU) mapping for
+ *      the memory address given. It is only valid to use this function on
+ *      addresses directly mapped or allocated via kmalloc.
+ *
+ *      This function does not give bus mappings for DMA transfers. In
+ *      almost all conceivable cases a device driver should not be using
+ *      this function
+ */
+static inline unsigned long virt_to_phys(volatile void * address)
+{
+        return __pa((unsigned long)address);
+}
+
+/**
+ *      phys_to_virt    -       map physical address to virtual
+ *      @address: address to remap
+ *
+ *      The returned virtual address is a current CPU mapping for
+ *      the memory address given. It is only valid to use this function on
+ *      addresses that have a kernel mapping
+ *
+ *      This function does not handle bus mappings for DMA transfers. In
+ *      almost all conceivable cases a device driver should not be using
+ *      this function
+ */
+static inline void * phys_to_virt(unsigned long address)
+{
+        return (void *)__va(address);
+}
+
+/*
+ * Change "struct page" to physical address.
+ */
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+
+/* We do NOT want virtual merging, it would put too much pressure on
+ * our iommu allocator. Instead, we want drivers to be smart enough
+ * to coalesce sglists that happen to have been mapped in a contiguous
+ * way by the iommu
+ */
+#define BIO_VMERGE_BOUNDARY     0
+
+/*
+ * 32 bits still uses virt_to_bus() for it's implementation of DMA
+ * mappings se we have to keep it defined here. We also have some old
+ * drivers (shame shame shame) that use bus_to_virt() and haven't been
+ * fixed yet so I need to define it here.
+ */
+#ifdef CONFIG_PPC32
+
+static inline unsigned long virt_to_bus(volatile void * address)
+{
+        if (address == NULL)
+                return 0;
+        return __pa(address) + PCI_DRAM_OFFSET;
+}
+
+static inline void * bus_to_virt(unsigned long address)
+{
+        if (address == 0)
+                return NULL;
+        return __va(address - PCI_DRAM_OFFSET);
+}
+
+#define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
+
+#endif /* CONFIG_PPC32 */
+
+/* access ports */
+#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
+#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+
+#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
+#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
+
+#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
+#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
+
+/* Clear and set bits in one shot.  These macros can be used to clear and
+ * set multiple bits in a register using a single read-modify-write.  These
+ * macros can also be used to set a multiple-bit bit pattern using a mask,
+ * by specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrsetbits(type, addr, clear, set) \
+        out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#ifdef __powerpc64__
+#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
+#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
+#endif
+
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
+                                size_t size, unsigned long flags);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_IO_H */
diff --git a/arch/powerpc/include/asm/ioctl.h b/arch/powerpc/include/asm/ioctl.h
new file mode 100644
index 000000000000..57d68304218b
--- /dev/null
+++ b/arch/powerpc/include/asm/ioctl.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_POWERPC_IOCTL_H
+#define _ASM_POWERPC_IOCTL_H
+
+#define _IOC_SIZEBITS   13
+#define _IOC_DIRBITS    3
+
+#define _IOC_NONE       1U
+#define _IOC_READ       2U
+#define _IOC_WRITE      4U
+
+#include <asm-generic/ioctl.h>
+
+#endif  /* _ASM_POWERPC_IOCTL_H */
diff --git a/arch/powerpc/include/asm/ioctls.h b/arch/powerpc/include/asm/ioctls.h
new file mode 100644
index 000000000000..279a6229584b
--- /dev/null
+++ b/arch/powerpc/include/asm/ioctls.h
@@ -0,0 +1,110 @@
+#ifndef _ASM_POWERPC_IOCTLS_H
+#define _ASM_POWERPC_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define FIOCLEX         _IO('f', 1)
+#define FIONCLEX        _IO('f', 2)
+#define FIOASYNC        _IOW('f', 125, int)
+#define FIONBIO         _IOW('f', 126, int)
+#define FIONREAD        _IOR('f', 127, int)
+#define TIOCINQ         FIONREAD
+#define FIOQSIZE        _IOR('f', 128, loff_t)
+
+#define TIOCGETP        _IOR('t', 8, struct sgttyb)
+#define TIOCSETP        _IOW('t', 9, struct sgttyb)
+#define TIOCSETN        _IOW('t', 10, struct sgttyb)    /* TIOCSETP wo flush */
+
+#define TIOCSETC        _IOW('t', 17, struct tchars)
+#define TIOCGETC        _IOR('t', 18, struct tchars)
+#define TCGETS          _IOR('t', 19, struct termios)
+#define TCSETS          _IOW('t', 20, struct termios)
+#define TCSETSW         _IOW('t', 21, struct termios)
+#define TCSETSF         _IOW('t', 22, struct termios)
+
+#define TCGETA          _IOR('t', 23, struct termio)
+#define TCSETA          _IOW('t', 24, struct termio)
+#define TCSETAW         _IOW('t', 25, struct termio)
+#define TCSETAF         _IOW('t', 28, struct termio)
+
+#define TCSBRK          _IO('t', 29)
+#define TCXONC          _IO('t', 30)
+#define TCFLSH          _IO('t', 31)
+
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
+#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
+#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
+#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
+
+#define TIOCGLTC        _IOR('t', 116, struct ltchars)
+#define TIOCSLTC        _IOW('t', 117, struct ltchars)
+#define TIOCSPGRP       _IOW('t', 118, int)
+#define TIOCGPGRP       _IOR('t', 119, int)
+
+#define TIOCEXCL        0x540C
+#define TIOCNXCL        0x540D
+#define TIOCSCTTY       0x540E
+
+#define TIOCSTI         0x5412
+#define TIOCMGET        0x5415
+#define TIOCMBIS        0x5416
+#define TIOCMBIC        0x5417
+#define TIOCMSET        0x5418
+# define TIOCM_LE       0x001
+# define TIOCM_DTR      0x002
+# define TIOCM_RTS      0x004
+# define TIOCM_ST       0x008
+# define TIOCM_SR       0x010
+# define TIOCM_CTS      0x020
+# define TIOCM_CAR      0x040
+# define TIOCM_RNG      0x080
+# define TIOCM_DSR      0x100
+# define TIOCM_CD       TIOCM_CAR
+# define TIOCM_RI       TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+#define TIOCGSOFTCAR    0x5419
+#define TIOCSSOFTCAR    0x541A
+#define TIOCLINUX       0x541C
+#define TIOCCONS        0x541D
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TIOCPKT         0x5420
+# define TIOCPKT_DATA            0
+# define TIOCPKT_FLUSHREAD       1
+# define TIOCPKT_FLUSHWRITE      2
+# define TIOCPKT_STOP            4
+# define TIOCPKT_START           8
+# define TIOCPKT_NOSTOP         16
+# define TIOCPKT_DOSTOP         32
+
+
+#define TIOCNOTTY       0x5422
+#define TIOCSETD        0x5423
+#define TIOCGETD        0x5424
+#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
+#define TIOCSERGETLSR   0x5459 /* Get line status register */
+  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+# define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+
+#endif  /* _ASM_POWERPC_IOCTLS_H */
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
new file mode 100644
index 000000000000..51ecfef8d843
--- /dev/null
+++ b/arch/powerpc/include/asm/iommu.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
+ * Rewrite, cleanup:
+ * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef _ASM_IOMMU_H
+#define _ASM_IOMMU_H
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/bitops.h>
+#include <asm/machdep.h>
+#include <asm/types.h>
+
+#define IOMMU_PAGE_SHIFT      12
+#define IOMMU_PAGE_SIZE       (ASM_CONST(1) << IOMMU_PAGE_SHIFT)
+#define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
+#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
+
+/* Boot time flags */
+extern int iommu_is_off;
+extern int iommu_force_on;
+
+/* Pure 2^n version of get_order */
+static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
+{
+        return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
+}
+
+
+/*
+ * IOMAP_MAX_ORDER defines the largest contiguous block
+ * of dma space we can get.  IOMAP_MAX_ORDER = 13
+ * allows up to 2**12 pages (4096 * 4096) = 16 MB
+ */
+#define IOMAP_MAX_ORDER         13
+
+struct iommu_table {
+        unsigned long  it_busno;     /* Bus number this table belongs to */
+        unsigned long  it_size;      /* Size of iommu table in entries */
+        unsigned long  it_offset;    /* Offset into global table */
+        unsigned long  it_base;      /* mapped address of tce table */
+        unsigned long  it_index;     /* which iommu table this is */
+        unsigned long  it_type;      /* type: PCI or Virtual Bus */
+        unsigned long  it_blocksize; /* Entries in each block (cacheline) */
+        unsigned long  it_hint;      /* Hint for next alloc */
+        unsigned long  it_largehint; /* Hint for large allocs */
+        unsigned long  it_halfpoint; /* Breaking point for small/large allocs */
+        spinlock_t     it_lock;      /* Protects it_map */
+        unsigned long *it_map;       /* A simple allocation bitmap for now */
+};
+
+struct scatterlist;
+
+/* Frees table for an individual device node */
+extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
+
+/* Initializes an iommu_table based in values set in the passed-in
+ * structure
+ */
+extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
+                                            int nid);
+
+extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
+                        struct scatterlist *sglist, int nelems,
+                        unsigned long mask, enum dma_data_direction direction,
+                        struct dma_attrs *attrs);
+extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
+                           int nelems, enum dma_data_direction direction,
+                           struct dma_attrs *attrs);
+
+extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
+                                  size_t size, dma_addr_t *dma_handle,
+                                  unsigned long mask, gfp_t flag, int node);
+extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
+                                void *vaddr, dma_addr_t dma_handle);
+extern dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl,
+                                   void *vaddr, size_t size, unsigned long mask,
+                                   enum dma_data_direction direction,
+                                   struct dma_attrs *attrs);
+extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
+                               size_t size, enum dma_data_direction direction,
+                               struct dma_attrs *attrs);
+
+extern void iommu_init_early_pSeries(void);
+extern void iommu_init_early_iSeries(void);
+extern void iommu_init_early_dart(void);
+extern void iommu_init_early_pasemi(void);
+
+#ifdef CONFIG_PCI
+extern void pci_iommu_init(void);
+extern void pci_direct_iommu_init(void);
+#else
+static inline void pci_iommu_init(void) { }
+#endif
+
+extern void alloc_dart_table(void);
+#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
+static inline void iommu_save(void)
+{
+        if (ppc_md.iommu_save)
+                ppc_md.iommu_save();
+}
+
+static inline void iommu_restore(void)
+{
+        if (ppc_md.iommu_restore)
+                ppc_md.iommu_restore();
+}
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_IOMMU_H */
diff --git a/arch/powerpc/include/asm/ipcbuf.h b/arch/powerpc/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..2c3e1d94db1d
--- /dev/null
+++ b/arch/powerpc/include/asm/ipcbuf.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_POWERPC_IPCBUF_H
+#define _ASM_POWERPC_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for the powerpc is identical to
+ * kern_ipc_perm as we have always had 32-bit UIDs and GIDs in the
+ * kernel.  Note extra padding because this structure is passed back
+ * and forth between kernel and user space.  Pad space is left for:
+ *      - 1 32-bit value to fill up for 8-byte alignment
+ *      - 2 miscellaneous 64-bit values
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/types.h>
+
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+        __kernel_mode_t mode;
+        unsigned int    seq;
+        unsigned int    __pad1;
+        unsigned long long __unused1;
+        unsigned long long __unused2;
+};
+
+#endif /* _ASM_POWERPC_IPCBUF_H */
diff --git a/arch/powerpc/include/asm/ipic.h b/arch/powerpc/include/asm/ipic.h
new file mode 100644
index 000000000000..fb59829983b8
--- /dev/null
+++ b/arch/powerpc/include/asm/ipic.h
@@ -0,0 +1,84 @@
+/*
+ * IPIC external definitions and structure.
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_IPIC_H__
+#define __ASM_IPIC_H__
+
+#include <linux/irq.h>
+
+/* Flags when we init the IPIC */
+#define IPIC_SPREADMODE_GRP_A   0x00000001
+#define IPIC_SPREADMODE_GRP_B   0x00000002
+#define IPIC_SPREADMODE_GRP_C   0x00000004
+#define IPIC_SPREADMODE_GRP_D   0x00000008
+#define IPIC_SPREADMODE_MIX_A   0x00000010
+#define IPIC_SPREADMODE_MIX_B   0x00000020
+#define IPIC_DISABLE_MCP_OUT    0x00000040
+#define IPIC_IRQ0_MCP           0x00000080
+
+/* IPIC registers offsets */
+#define IPIC_SICFR      0x00    /* System Global Interrupt Configuration Register */
+#define IPIC_SIVCR      0x04    /* System Global Interrupt Vector Register */
+#define IPIC_SIPNR_H    0x08    /* System Internal Interrupt Pending Register (HIGH) */
+#define IPIC_SIPNR_L    0x0C    /* System Internal Interrupt Pending Register (LOW) */
+#define IPIC_SIPRR_A    0x10    /* System Internal Interrupt group A Priority Register */
+#define IPIC_SIPRR_B    0x14    /* System Internal Interrupt group B Priority Register */
+#define IPIC_SIPRR_C    0x18    /* System Internal Interrupt group C Priority Register */
+#define IPIC_SIPRR_D    0x1C    /* System Internal Interrupt group D Priority Register */
+#define IPIC_SIMSR_H    0x20    /* System Internal Interrupt Mask Register (HIGH) */
+#define IPIC_SIMSR_L    0x24    /* System Internal Interrupt Mask Register (LOW) */
+#define IPIC_SICNR      0x28    /* System Internal Interrupt Control Register */
+#define IPIC_SEPNR      0x2C    /* System External Interrupt Pending Register */
+#define IPIC_SMPRR_A    0x30    /* System Mixed Interrupt group A Priority Register */
+#define IPIC_SMPRR_B    0x34    /* System Mixed Interrupt group B Priority Register */
+#define IPIC_SEMSR      0x38    /* System External Interrupt Mask Register */
+#define IPIC_SECNR      0x3C    /* System External Interrupt Control Register */
+#define IPIC_SERSR      0x40    /* System Error Status Register */
+#define IPIC_SERMR      0x44    /* System Error Mask Register */
+#define IPIC_SERCR      0x48    /* System Error Control Register */
+#define IPIC_SIFCR_H    0x50    /* System Internal Interrupt Force Register (HIGH) */
+#define IPIC_SIFCR_L    0x54    /* System Internal Interrupt Force Register (LOW) */
+#define IPIC_SEFCR      0x58    /* System External Interrupt Force Register */
+#define IPIC_SERFR      0x5C    /* System Error Force Register */
+#define IPIC_SCVCR      0x60    /* System Critical Interrupt Vector Register */
+#define IPIC_SMVCR      0x64    /* System Management Interrupt Vector Register */
+
+enum ipic_prio_grp {
+        IPIC_INT_GRP_A = IPIC_SIPRR_A,
+        IPIC_INT_GRP_D = IPIC_SIPRR_D,
+        IPIC_MIX_GRP_A = IPIC_SMPRR_A,
+        IPIC_MIX_GRP_B = IPIC_SMPRR_B,
+};
+
+enum ipic_mcp_irq {
+        IPIC_MCP_IRQ0 = 0,
+        IPIC_MCP_WDT  = 1,
+        IPIC_MCP_SBA  = 2,
+        IPIC_MCP_PCI1 = 5,
+        IPIC_MCP_PCI2 = 6,
+        IPIC_MCP_MU   = 7,
+};
+
+extern int ipic_set_priority(unsigned int irq, unsigned int priority);
+extern void ipic_set_highest_priority(unsigned int irq);
+extern void ipic_set_default_priority(void);
+extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
+extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
+extern u32 ipic_get_mcp_status(void);
+extern void ipic_clear_mcp_status(u32 mask);
+
+extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
+extern unsigned int ipic_get_irq(void);
+
+#endif /* __ASM_IPIC_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
new file mode 100644
index 000000000000..a372f76836c2
--- /dev/null
+++ b/arch/powerpc/include/asm/irq.h
@@ -0,0 +1,366 @@
+#ifdef __KERNEL__
+#ifndef _ASM_POWERPC_IRQ_H
+#define _ASM_POWERPC_IRQ_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/threads.h>
+#include <linux/list.h>
+#include <linux/radix-tree.h>
+
+#include <asm/types.h>
+#include <asm/atomic.h>
+
+
+#define get_irq_desc(irq) (&irq_desc[(irq)])
+
+/* Define a way to iterate across irqs. */
+#define for_each_irq(i) \
+        for ((i) = 0; (i) < NR_IRQS; ++(i))
+
+extern atomic_t ppc_n_lost_interrupts;
+
+/* This number is used when no interrupt has been assigned */
+#define NO_IRQ                  (0)
+
+/* This is a special irq number to return from get_irq() to tell that
+ * no interrupt happened _and_ ignore it (don't count it as bad). Some
+ * platforms like iSeries rely on that.
+ */
+#define NO_IRQ_IGNORE           ((unsigned int)-1)
+
+/* Total number of virq in the platform (make it a CONFIG_* option ? */
+#define NR_IRQS         512
+
+/* Number of irqs reserved for the legacy controller */
+#define NUM_ISA_INTERRUPTS      16
+
+/* This type is the placeholder for a hardware interrupt number. It has to
+ * be big enough to enclose whatever representation is used by a given
+ * platform.
+ */
+typedef unsigned long irq_hw_number_t;
+
+/* Interrupt controller "host" data structure. This could be defined as a
+ * irq domain controller. That is, it handles the mapping between hardware
+ * and virtual interrupt numbers for a given interrupt domain. The host
+ * structure is generally created by the PIC code for a given PIC instance
+ * (though a host can cover more than one PIC if they have a flat number
+ * model). It's the host callbacks that are responsible for setting the
+ * irq_chip on a given irq_desc after it's been mapped.
+ *
+ * The host code and data structures are fairly agnostic to the fact that
+ * we use an open firmware device-tree. We do have references to struct
+ * device_node in two places: in irq_find_host() to find the host matching
+ * a given interrupt controller node, and of course as an argument to its
+ * counterpart host->ops->match() callback. However, those are treated as
+ * generic pointers by the core and the fact that it's actually a device-node
+ * pointer is purely a convention between callers and implementation. This
+ * code could thus be used on other architectures by replacing those two
+ * by some sort of arch-specific void * "token" used to identify interrupt
+ * controllers.
+ */
+struct irq_host;
+struct radix_tree_root;
+
+/* Functions below are provided by the host and called whenever a new mapping
+ * is created or an old mapping is disposed. The host can then proceed to
+ * whatever internal data structures management is required. It also needs
+ * to setup the irq_desc when returning from map().
+ */
+struct irq_host_ops {
+        /* Match an interrupt controller device node to a host, returns
+         * 1 on a match
+         */
+        int (*match)(struct irq_host *h, struct device_node *node);
+
+        /* Create or update a mapping between a virtual irq number and a hw
+         * irq number. This is called only once for a given mapping.
+         */
+        int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
+
+        /* Dispose of such a mapping */
+        void (*unmap)(struct irq_host *h, unsigned int virq);
+
+        /* Update of such a mapping  */
+        void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
+
+        /* Translate device-tree interrupt specifier from raw format coming
+         * from the firmware to a irq_hw_number_t (interrupt line number) and
+         * type (sense) that can be passed to set_irq_type(). In the absence
+         * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
+         * will return the hw number in the first cell and IRQ_TYPE_NONE for
+         * the type (which amount to keeping whatever default value the
+         * interrupt controller has for that line)
+         */
+        int (*xlate)(struct irq_host *h, struct device_node *ctrler,
+                     u32 *intspec, unsigned int intsize,
+                     irq_hw_number_t *out_hwirq, unsigned int *out_type);
+};
+
+struct irq_host {
+        struct list_head        link;
+
+        /* type of reverse mapping technique */
+        unsigned int            revmap_type;
+#define IRQ_HOST_MAP_LEGACY     0 /* legacy 8259, gets irqs 1..15 */
+#define IRQ_HOST_MAP_NOMAP      1 /* no fast reverse mapping */
+#define IRQ_HOST_MAP_LINEAR     2 /* linear map of interrupts */
+#define IRQ_HOST_MAP_TREE       3 /* radix tree */
+        union {
+                struct {
+                        unsigned int size;
+                        unsigned int *revmap;
+                } linear;
+                struct radix_tree_root tree;
+        } revmap_data;
+        struct irq_host_ops     *ops;
+        void                    *host_data;
+        irq_hw_number_t         inval_irq;
+
+        /* Optional device node pointer */
+        struct device_node      *of_node;
+};
+
+/* The main irq map itself is an array of NR_IRQ entries containing the
+ * associate host and irq number. An entry with a host of NULL is free.
+ * An entry can be allocated if it's free, the allocator always then sets
+ * hwirq first to the host's invalid irq number and then fills ops.
+ */
+struct irq_map_entry {
+        irq_hw_number_t hwirq;
+        struct irq_host *host;
+};
+
+extern struct irq_map_entry irq_map[NR_IRQS];
+
+extern irq_hw_number_t virq_to_hw(unsigned int virq);
+
+/**
+ * irq_alloc_host - Allocate a new irq_host data structure
+ * @of_node: optional device-tree node of the interrupt controller
+ * @revmap_type: type of reverse mapping to use
+ * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
+ * @ops: map/unmap host callbacks
+ * @inval_irq: provide a hw number in that host space that is always invalid
+ *
+ * Allocates and initialize and irq_host structure. Note that in the case of
+ * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
+ * for all legacy interrupts except 0 (which is always the invalid irq for
+ * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
+ * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
+ * later during boot automatically (the reverse mapping will use the slow path
+ * until that happens).
+ */
+extern struct irq_host *irq_alloc_host(struct device_node *of_node,
+                                       unsigned int revmap_type,
+                                       unsigned int revmap_arg,
+                                       struct irq_host_ops *ops,
+                                       irq_hw_number_t inval_irq);
+
+
+/**
+ * irq_find_host - Locates a host for a given device node
+ * @node: device-tree node of the interrupt controller
+ */
+extern struct irq_host *irq_find_host(struct device_node *node);
+
+
+/**
+ * irq_set_default_host - Set a "default" host
+ * @host: default host pointer
+ *
+ * For convenience, it's possible to set a "default" host that will be used
+ * whenever NULL is passed to irq_create_mapping(). It makes life easier for
+ * platforms that want to manipulate a few hard coded interrupt numbers that
+ * aren't properly represented in the device-tree.
+ */
+extern void irq_set_default_host(struct irq_host *host);
+
+
+/**
+ * irq_set_virq_count - Set the maximum number of virt irqs
+ * @count: number of linux virtual irqs, capped with NR_IRQS
+ *
+ * This is mainly for use by platforms like iSeries who want to program
+ * the virtual irq number in the controller to avoid the reverse mapping
+ */
+extern void irq_set_virq_count(unsigned int count);
+
+
+/**
+ * irq_create_mapping - Map a hardware interrupt into linux virq space
+ * @host: host owning this hardware interrupt or NULL for default host
+ * @hwirq: hardware irq number in that host space
+ *
+ * Only one mapping per hardware interrupt is permitted. Returns a linux
+ * virq number.
+ * If the sense/trigger is to be specified, set_irq_type() should be called
+ * on the number returned from that call.
+ */
+extern unsigned int irq_create_mapping(struct irq_host *host,
+                                       irq_hw_number_t hwirq);
+
+
+/**
+ * irq_dispose_mapping - Unmap an interrupt
+ * @virq: linux virq number of the interrupt to unmap
+ */
+extern void irq_dispose_mapping(unsigned int virq);
+
+/**
+ * irq_find_mapping - Find a linux virq from an hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a slow path, for use by generic code. It's expected that an
+ * irq controller implementation directly calls the appropriate low level
+ * mapping function.
+ */
+extern unsigned int irq_find_mapping(struct irq_host *host,
+                                     irq_hw_number_t hwirq);
+
+/**
+ * irq_create_direct_mapping - Allocate a virq for direct mapping
+ * @host: host to allocate the virq for or NULL for default host
+ *
+ * This routine is used for irq controllers which can choose the hardware
+ * interrupt numbers they generate. In such a case it's simplest to use
+ * the linux virq as the hardware interrupt number.
+ */
+extern unsigned int irq_create_direct_mapping(struct irq_host *host);
+
+/**
+ * irq_radix_revmap - Find a linux virq from a hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a fast path, for use by irq controller code that uses radix tree
+ * revmaps
+ */
+extern unsigned int irq_radix_revmap(struct irq_host *host,
+                                     irq_hw_number_t hwirq);
+
+/**
+ * irq_linear_revmap - Find a linux virq from a hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a fast path, for use by irq controller code that uses linear
+ * revmaps. It does fallback to the slow path if the revmap doesn't exist
+ * yet and will create the revmap entry with appropriate locking
+ */
+
+extern unsigned int irq_linear_revmap(struct irq_host *host,
+                                      irq_hw_number_t hwirq);
+
+
+
+/**
+ * irq_alloc_virt - Allocate virtual irq numbers
+ * @host: host owning these new virtual irqs
+ * @count: number of consecutive numbers to allocate
+ * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
+ *
+ * This is a low level function that is used internally by irq_create_mapping()
+ * and that can be used by some irq controllers implementations for things
+ * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
+ */
+extern unsigned int irq_alloc_virt(struct irq_host *host,
+                                   unsigned int count,
+                                   unsigned int hint);
+
+/**
+ * irq_free_virt - Free virtual irq numbers
+ * @virq: virtual irq number of the first interrupt to free
+ * @count: number of interrupts to free
+ *
+ * This function is the opposite of irq_alloc_virt. It will not clear reverse
+ * maps, this should be done previously by unmap'ing the interrupt. In fact,
+ * all interrupts covered by the range being freed should have been unmapped
+ * prior to calling this.
+ */
+extern void irq_free_virt(unsigned int virq, unsigned int count);
+
+
+/* -- OF helpers -- */
+
+/* irq_create_of_mapping - Map a hardware interrupt into linux virq space
+ * @controller: Device node of the interrupt controller
+ * @inspec: Interrupt specifier from the device-tree
+ * @intsize: Size of the interrupt specifier from the device-tree
+ *
+ * This function is identical to irq_create_mapping except that it takes
+ * as input informations straight from the device-tree (typically the results
+ * of the of_irq_map_*() functions.
+ */
+extern unsigned int irq_create_of_mapping(struct device_node *controller,
+                                          u32 *intspec, unsigned int intsize);
+
+
+/* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
+ * @device: Device node of the device whose interrupt is to be mapped
+ * @index: Index of the interrupt to map
+ *
+ * This function is a wrapper that chains of_irq_map_one() and
+ * irq_create_of_mapping() to make things easier to callers
+ */
+extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
+
+/* -- End OF helpers -- */
+
+/**
+ * irq_early_init - Init irq remapping subsystem
+ */
+extern void irq_early_init(void);
+
+static __inline__ int irq_canonicalize(int irq)
+{
+        return irq;
+}
+
+extern int distribute_irqs;
+
+struct irqaction;
+struct pt_regs;
+
+#define __ARCH_HAS_DO_SOFTIRQ
+
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+/*
+ * Per-cpu stacks for handling critical, debug and machine check
+ * level interrupts.
+ */
+extern struct thread_info *critirq_ctx[NR_CPUS];
+extern struct thread_info *dbgirq_ctx[NR_CPUS];
+extern struct thread_info *mcheckirq_ctx[NR_CPUS];
+extern void exc_lvl_ctx_init(void);
+#else
+#define exc_lvl_ctx_init()
+#endif
+
+#ifdef CONFIG_IRQSTACKS
+/*
+ * Per-cpu stacks for handling hard and soft interrupts.
+ */
+extern struct thread_info *hardirq_ctx[NR_CPUS];
+extern struct thread_info *softirq_ctx[NR_CPUS];
+
+extern void irq_ctx_init(void);
+extern void call_do_softirq(struct thread_info *tp);
+extern int call_handle_irq(int irq, void *p1,
+                           struct thread_info *tp, void *func);
+#else
+#define irq_ctx_init()
+
+#endif /* CONFIG_IRQSTACKS */
+
+extern void do_IRQ(struct pt_regs *regs);
+
+#endif /* _ASM_IRQ_H */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/irq_regs.h b/arch/powerpc/include/asm/irq_regs.h
new file mode 100644
index 000000000000..ba94b51a0a70
--- /dev/null
+++ b/arch/powerpc/include/asm/irq_regs.h
@@ -0,0 +1,2 @@
+#include <asm-generic/irq_regs.h>
+
diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h
new file mode 100644
index 000000000000..17ba3a881bfd
--- /dev/null
+++ b/arch/powerpc/include/asm/irqflags.h
@@ -0,0 +1,42 @@
+/*
+ * IRQ flags handling
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+/*
+ * Get definitions for raw_local_save_flags(x), etc.
+ */
+#include <asm/hw_irq.h>
+
+#else
+#ifdef CONFIG_TRACE_IRQFLAGS
+/*
+ * Most of the CPU's IRQ-state tracing is done from assembly code; we
+ * have to call a C function so call a wrapper that saves all the
+ * C-clobbered registers.
+ */
+#define TRACE_ENABLE_INTS       bl .trace_hardirqs_on
+#define TRACE_DISABLE_INTS      bl .trace_hardirqs_off
+#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)  \
+        cmpdi   en, 0;                          \
+        bne     95f;                            \
+        stb     en,PACASOFTIRQEN(r13);          \
+        bl      .trace_hardirqs_off;            \
+        b       skip;                           \
+95:     bl      .trace_hardirqs_on;             \
+        li      en,1;
+#define TRACE_AND_RESTORE_IRQ(en)               \
+        TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f);  \
+96:     stb     en,PACASOFTIRQEN(r13)
+#else
+#define TRACE_ENABLE_INTS
+#define TRACE_DISABLE_INTS
+#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
+#define TRACE_AND_RESTORE_IRQ(en)               \
+        stb     en,PACASOFTIRQEN(r13)
+#endif
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/iseries/alpaca.h b/arch/powerpc/include/asm/iseries/alpaca.h
new file mode 100644
index 000000000000..c0cce6727a69
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/alpaca.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright © 2008  Stephen Rothwell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_ALPACA_H
+#define _ASM_POWERPC_ISERIES_ALPACA_H
+
+/*
+ * This is the part of the paca that the iSeries hypervisor
+ * needs to be statically initialised. Immediately after boot
+ * we switch to the normal Linux paca.
+ */
+struct alpaca {
+        struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
+        const void *reg_save_ptr;       /* Pointer to LpRegSave for PLIC */
+};
+
+#endif /* _ASM_POWERPC_ISERIES_ALPACA_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call.h b/arch/powerpc/include/asm/iseries/hv_call.h
new file mode 100644
index 000000000000..162d653ad51f
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from the OS.
+ */
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_H
+
+#include <asm/iseries/hv_call_sc.h>
+#include <asm/iseries/hv_types.h>
+#include <asm/paca.h>
+
+/* Type of yield for HvCallBaseYieldProcessor */
+#define HvCall_YieldTimed       0       /* Yield until specified time (tb) */
+#define HvCall_YieldToActive    1       /* Yield until all active procs have run */
+#define HvCall_YieldToProc      2       /* Yield until the specified processor has run */
+
+/* interrupt masks for setEnabledInterrupts */
+#define HvCall_MaskIPI          0x00000001
+#define HvCall_MaskLpEvent      0x00000002
+#define HvCall_MaskLpProd       0x00000004
+#define HvCall_MaskTimeout      0x00000008
+
+/* Log buffer formats */
+#define HvCall_LogBuffer_ASCII          0
+#define HvCall_LogBuffer_EBCDIC         1
+
+#define HvCallBaseAckDeferredInts                       HvCallBase +  0
+#define HvCallBaseCpmPowerOff                           HvCallBase +  1
+#define HvCallBaseGetHwPatch                            HvCallBase +  2
+#define HvCallBaseReIplSpAttn                           HvCallBase +  3
+#define HvCallBaseSetASR                                HvCallBase +  4
+#define HvCallBaseSetASRAndRfi                          HvCallBase +  5
+#define HvCallBaseSetIMR                                HvCallBase +  6
+#define HvCallBaseSendIPI                               HvCallBase +  7
+#define HvCallBaseTerminateMachine                      HvCallBase +  8
+#define HvCallBaseTerminateMachineSrc                   HvCallBase +  9
+#define HvCallBaseProcessPlicInterrupts                 HvCallBase + 10
+#define HvCallBaseIsPrimaryCpmOrMsdIpl                  HvCallBase + 11
+#define HvCallBaseSetVirtualSIT                         HvCallBase + 12
+#define HvCallBaseVaryOffThisProcessor                  HvCallBase + 13
+#define HvCallBaseVaryOffMemoryChunk                    HvCallBase + 14
+#define HvCallBaseVaryOffInteractivePercentage          HvCallBase + 15
+#define HvCallBaseSendLpProd                            HvCallBase + 16
+#define HvCallBaseSetEnabledInterrupts                  HvCallBase + 17
+#define HvCallBaseYieldProcessor                        HvCallBase + 18
+#define HvCallBaseVaryOffSharedProcUnits                HvCallBase + 19
+#define HvCallBaseSetVirtualDecr                        HvCallBase + 20
+#define HvCallBaseClearLogBuffer                        HvCallBase + 21
+#define HvCallBaseGetLogBufferCodePage                  HvCallBase + 22
+#define HvCallBaseGetLogBufferFormat                    HvCallBase + 23
+#define HvCallBaseGetLogBufferLength                    HvCallBase + 24
+#define HvCallBaseReadLogBuffer                         HvCallBase + 25
+#define HvCallBaseSetLogBufferFormatAndCodePage         HvCallBase + 26
+#define HvCallBaseWriteLogBuffer                        HvCallBase + 27
+#define HvCallBaseRouter28                              HvCallBase + 28
+#define HvCallBaseRouter29                              HvCallBase + 29
+#define HvCallBaseRouter30                              HvCallBase + 30
+#define HvCallBaseSetDebugBus                           HvCallBase + 31
+
+#define HvCallCcSetDABR                                 HvCallCc + 7
+
+static inline void HvCall_setVirtualDecr(void)
+{
+        /*
+         * Ignore any error return codes - most likely means that the
+         * target value for the LP has been increased and this vary off
+         * would bring us below the new target.
+         */
+        HvCall0(HvCallBaseSetVirtualDecr);
+}
+
+static inline void HvCall_yieldProcessor(unsigned typeOfYield, u64 yieldParm)
+{
+        HvCall2(HvCallBaseYieldProcessor, typeOfYield, yieldParm);
+}
+
+static inline void HvCall_setEnabledInterrupts(u64 enabledInterrupts)
+{
+        HvCall1(HvCallBaseSetEnabledInterrupts, enabledInterrupts);
+}
+
+static inline void HvCall_setLogBufferFormatAndCodepage(int format,
+                u32 codePage)
+{
+        HvCall2(HvCallBaseSetLogBufferFormatAndCodePage, format, codePage);
+}
+
+extern void HvCall_writeLogBuffer(const void *buffer, u64 bufLen);
+
+static inline void HvCall_sendIPI(struct paca_struct *targetPaca)
+{
+        HvCall1(HvCallBaseSendIPI, targetPaca->paca_index);
+}
+
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_event.h b/arch/powerpc/include/asm/iseries/hv_call_event.h
new file mode 100644
index 000000000000..cc029d388e11
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call_event.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from the OS.
+ */
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
+
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/iseries/hv_call_sc.h>
+#include <asm/iseries/hv_types.h>
+#include <asm/abs_addr.h>
+
+struct HvLpEvent;
+
+typedef u8 HvLpEvent_Type;
+typedef u8 HvLpEvent_AckInd;
+typedef u8 HvLpEvent_AckType;
+
+typedef u8 HvLpDma_Direction;
+typedef u8 HvLpDma_AddressType;
+
+typedef u64 HvLpEvent_Rc;
+typedef u64 HvLpDma_Rc;
+
+#define HvCallEventAckLpEvent                           HvCallEvent +  0
+#define HvCallEventCancelLpEvent                        HvCallEvent +  1
+#define HvCallEventCloseLpEventPath                     HvCallEvent +  2
+#define HvCallEventDmaBufList                           HvCallEvent +  3
+#define HvCallEventDmaSingle                            HvCallEvent +  4
+#define HvCallEventDmaToSp                              HvCallEvent +  5
+#define HvCallEventGetOverflowLpEvents                  HvCallEvent +  6
+#define HvCallEventGetSourceLpInstanceId                HvCallEvent +  7
+#define HvCallEventGetTargetLpInstanceId                HvCallEvent +  8
+#define HvCallEventOpenLpEventPath                      HvCallEvent +  9
+#define HvCallEventSetLpEventStack                      HvCallEvent + 10
+#define HvCallEventSignalLpEvent                        HvCallEvent + 11
+#define HvCallEventSignalLpEventParms                   HvCallEvent + 12
+#define HvCallEventSetInterLpQueueIndex                 HvCallEvent + 13
+#define HvCallEventSetLpEventQueueInterruptProc         HvCallEvent + 14
+#define HvCallEventRouter15                             HvCallEvent + 15
+
+static inline void HvCallEvent_getOverflowLpEvents(u8 queueIndex)
+{
+        HvCall1(HvCallEventGetOverflowLpEvents, queueIndex);
+}
+
+static inline void HvCallEvent_setInterLpQueueIndex(u8 queueIndex)
+{
+        HvCall1(HvCallEventSetInterLpQueueIndex, queueIndex);
+}
+
+static inline void HvCallEvent_setLpEventStack(u8 queueIndex,
+                char *eventStackAddr, u32 eventStackSize)
+{
+        HvCall3(HvCallEventSetLpEventStack, queueIndex,
+                        virt_to_abs(eventStackAddr), eventStackSize);
+}
+
+static inline void HvCallEvent_setLpEventQueueInterruptProc(u8 queueIndex,
+                u16 lpLogicalProcIndex)
+{
+        HvCall2(HvCallEventSetLpEventQueueInterruptProc, queueIndex,
+                        lpLogicalProcIndex);
+}
+
+static inline HvLpEvent_Rc HvCallEvent_signalLpEvent(struct HvLpEvent *event)
+{
+        return HvCall1(HvCallEventSignalLpEvent, virt_to_abs(event));
+}
+
+static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
+                HvLpEvent_Type type, u16 subtype, HvLpEvent_AckInd ackInd,
+                HvLpEvent_AckType ackType, HvLpInstanceId sourceInstanceId,
+                HvLpInstanceId targetInstanceId, u64 correlationToken,
+                u64 eventData1, u64 eventData2, u64 eventData3,
+                u64 eventData4, u64 eventData5)
+{
+        /* Pack the misc bits into a single Dword to pass to PLIC */
+        union {
+                struct {
+                        u8              ack_and_target;
+                        u8              type;
+                        u16             subtype;
+                        HvLpInstanceId  src_inst;
+                        HvLpInstanceId  target_inst;
+                } parms;
+                u64             dword;
+        } packed;
+
+        packed.parms.ack_and_target = (ackType << 7) | (ackInd << 6) | targetLp;
+        packed.parms.type = type;
+        packed.parms.subtype = subtype;
+        packed.parms.src_inst = sourceInstanceId;
+        packed.parms.target_inst = targetInstanceId;
+
+        return HvCall7(HvCallEventSignalLpEventParms, packed.dword,
+                        correlationToken, eventData1, eventData2,
+                        eventData3, eventData4, eventData5);
+}
+
+extern void *iseries_hv_alloc(size_t size, dma_addr_t *dma_handle, gfp_t flag);
+extern void iseries_hv_free(size_t size, void *vaddr, dma_addr_t dma_handle);
+extern dma_addr_t iseries_hv_map(void *vaddr, size_t size,
+                        enum dma_data_direction direction);
+extern void iseries_hv_unmap(dma_addr_t dma_handle, size_t size,
+                        enum dma_data_direction direction);
+
+static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent *event)
+{
+        return HvCall1(HvCallEventAckLpEvent, virt_to_abs(event));
+}
+
+static inline HvLpEvent_Rc HvCallEvent_cancelLpEvent(struct HvLpEvent *event)
+{
+        return HvCall1(HvCallEventCancelLpEvent, virt_to_abs(event));
+}
+
+static inline HvLpInstanceId HvCallEvent_getSourceLpInstanceId(
+                HvLpIndex targetLp, HvLpEvent_Type type)
+{
+        return HvCall2(HvCallEventGetSourceLpInstanceId, targetLp, type);
+}
+
+static inline HvLpInstanceId HvCallEvent_getTargetLpInstanceId(
+                HvLpIndex targetLp, HvLpEvent_Type type)
+{
+        return HvCall2(HvCallEventGetTargetLpInstanceId, targetLp, type);
+}
+
+static inline void HvCallEvent_openLpEventPath(HvLpIndex targetLp,
+                HvLpEvent_Type type)
+{
+        HvCall2(HvCallEventOpenLpEventPath, targetLp, type);
+}
+
+static inline void HvCallEvent_closeLpEventPath(HvLpIndex targetLp,
+                HvLpEvent_Type type)
+{
+        HvCall2(HvCallEventCloseLpEventPath, targetLp, type);
+}
+
+static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type,
+                HvLpIndex remoteLp, HvLpDma_Direction direction,
+                HvLpInstanceId localInstanceId,
+                HvLpInstanceId remoteInstanceId,
+                HvLpDma_AddressType localAddressType,
+                HvLpDma_AddressType remoteAddressType,
+                /* Do these need to be converted to absolute addresses? */
+                u64 localBufList, u64 remoteBufList, u32 transferLength)
+{
+        /* Pack the misc bits into a single Dword to pass to PLIC */
+        union {
+                struct {
+                        u8              flags;
+                        HvLpIndex       remote;
+                        u8              type;
+                        u8              reserved;
+                        HvLpInstanceId  local_inst;
+                        HvLpInstanceId  remote_inst;
+                } parms;
+                u64             dword;
+        } packed;
+
+        packed.parms.flags = (direction << 7) |
+                (localAddressType << 6) | (remoteAddressType << 5);
+        packed.parms.remote = remoteLp;
+        packed.parms.type = type;
+        packed.parms.reserved = 0;
+        packed.parms.local_inst = localInstanceId;
+        packed.parms.remote_inst = remoteInstanceId;
+
+        return HvCall4(HvCallEventDmaBufList, packed.dword, localBufList,
+                        remoteBufList, transferLength);
+}
+
+static inline HvLpDma_Rc HvCallEvent_dmaToSp(void *local, u32 remote,
+                u32 length, HvLpDma_Direction dir)
+{
+        return HvCall4(HvCallEventDmaToSp, virt_to_abs(local), remote,
+                        length, dir);
+}
+
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_sc.h b/arch/powerpc/include/asm/iseries/hv_call_sc.h
new file mode 100644
index 000000000000..f5d210959250
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call_sc.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_SC_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_SC_H
+
+#include <linux/types.h>
+
+#define HvCallBase              0x8000000000000000ul
+#define HvCallCc                0x8001000000000000ul
+#define HvCallCfg               0x8002000000000000ul
+#define HvCallEvent             0x8003000000000000ul
+#define HvCallHpt               0x8004000000000000ul
+#define HvCallPci               0x8005000000000000ul
+#define HvCallSm                0x8007000000000000ul
+#define HvCallXm                0x8009000000000000ul
+
+extern u64 HvCall0(u64);
+extern u64 HvCall1(u64, u64);
+extern u64 HvCall2(u64, u64, u64);
+extern u64 HvCall3(u64, u64, u64, u64);
+extern u64 HvCall4(u64, u64, u64, u64, u64);
+extern u64 HvCall5(u64, u64, u64, u64, u64, u64);
+extern u64 HvCall6(u64, u64, u64, u64, u64, u64, u64);
+extern u64 HvCall7(u64, u64, u64, u64, u64, u64, u64, u64);
+
+extern u64 HvCall0Ret16(u64, void *);
+extern u64 HvCall1Ret16(u64, void *, u64);
+extern u64 HvCall2Ret16(u64, void *, u64, u64);
+extern u64 HvCall3Ret16(u64, void *, u64, u64, u64);
+extern u64 HvCall4Ret16(u64, void *, u64, u64, u64, u64);
+extern u64 HvCall5Ret16(u64, void *, u64, u64, u64, u64, u64);
+extern u64 HvCall6Ret16(u64, void *, u64, u64, u64, u64, u64, u64);
+extern u64 HvCall7Ret16(u64, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64);
+
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_SC_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_xm.h b/arch/powerpc/include/asm/iseries/hv_call_xm.h
new file mode 100644
index 000000000000..392ac3f54df0
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_call_xm.h
@@ -0,0 +1,61 @@
+/*
+ * This file contains the "hypervisor call" interface which is used to
+ * drive the hypervisor from SLIC.
+ */
+#ifndef _ASM_POWERPC_ISERIES_HV_CALL_XM_H
+#define _ASM_POWERPC_ISERIES_HV_CALL_XM_H
+
+#include <asm/iseries/hv_call_sc.h>
+#include <asm/iseries/hv_types.h>
+
+#define HvCallXmGetTceTableParms        HvCallXm +  0
+#define HvCallXmTestBus                 HvCallXm +  1
+#define HvCallXmConnectBusUnit          HvCallXm +  2
+#define HvCallXmLoadTod                 HvCallXm +  8
+#define HvCallXmTestBusUnit             HvCallXm +  9
+#define HvCallXmSetTce                  HvCallXm + 11
+#define HvCallXmSetTces                 HvCallXm + 13
+
+static inline void HvCallXm_getTceTableParms(u64 cb)
+{
+        HvCall1(HvCallXmGetTceTableParms, cb);
+}
+
+static inline u64 HvCallXm_setTce(u64 tceTableToken, u64 tceOffset, u64 tce)
+{
+        return HvCall3(HvCallXmSetTce, tceTableToken, tceOffset, tce);
+}
+
+static inline u64 HvCallXm_setTces(u64 tceTableToken, u64 tceOffset,
+                u64 numTces, u64 tce1, u64 tce2, u64 tce3, u64 tce4)
+{
+        return HvCall7(HvCallXmSetTces, tceTableToken, tceOffset, numTces,
+                             tce1, tce2, tce3, tce4);
+}
+
+static inline u64 HvCallXm_testBus(u16 busNumber)
+{
+        return HvCall1(HvCallXmTestBus, busNumber);
+}
+
+static inline u64 HvCallXm_testBusUnit(u16 busNumber, u8 subBusNumber,
+                u8 deviceId)
+{
+        return HvCall2(HvCallXmTestBusUnit, busNumber,
+                        (subBusNumber << 8) | deviceId);
+}
+
+static inline u64 HvCallXm_connectBusUnit(u16 busNumber, u8 subBusNumber,
+                u8 deviceId, u64 interruptToken)
+{
+        return HvCall5(HvCallXmConnectBusUnit, busNumber,
+                        (subBusNumber << 8) | deviceId, interruptToken, 0,
+                        0 /* HvLpConfig::mapDsaToQueueIndex(HvLpDSA(busNumber, xBoard, xCard)) */);
+}
+
+static inline u64 HvCallXm_loadTod(void)
+{
+        return HvCall0(HvCallXmLoadTod);
+}
+
+#endif /* _ASM_POWERPC_ISERIES_HV_CALL_XM_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_lp_config.h b/arch/powerpc/include/asm/iseries/hv_lp_config.h
new file mode 100644
index 000000000000..a006fd1e4a2c
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_lp_config.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
+#define _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
+
+/*
+ * This file contains the interface to the LPAR configuration data
+ * to determine which resources should be allocated to each partition.
+ */
+
+#include <asm/iseries/hv_call_sc.h>
+#include <asm/iseries/hv_types.h>
+
+enum {
+        HvCallCfg_Cur   = 0,
+        HvCallCfg_Init  = 1,
+        HvCallCfg_Max   = 2,
+        HvCallCfg_Min   = 3
+};
+
+#define HvCallCfgGetSystemPhysicalProcessors            HvCallCfg +  6
+#define HvCallCfgGetPhysicalProcessors                  HvCallCfg +  7
+#define HvCallCfgGetMsChunks                            HvCallCfg +  9
+#define HvCallCfgGetSharedPoolIndex                     HvCallCfg + 20
+#define HvCallCfgGetSharedProcUnits                     HvCallCfg + 21
+#define HvCallCfgGetNumProcsInSharedPool                HvCallCfg + 22
+#define HvCallCfgGetVirtualLanIndexMap                  HvCallCfg + 30
+#define HvCallCfgGetHostingLpIndex                      HvCallCfg + 32
+
+extern HvLpIndex HvLpConfig_getLpIndex_outline(void);
+extern HvLpIndex HvLpConfig_getLpIndex(void);
+extern HvLpIndex HvLpConfig_getPrimaryLpIndex(void);
+
+static inline u64 HvLpConfig_getMsChunks(void)
+{
+        return HvCall2(HvCallCfgGetMsChunks, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Cur);
+}
+
+static inline u64 HvLpConfig_getSystemPhysicalProcessors(void)
+{
+        return HvCall0(HvCallCfgGetSystemPhysicalProcessors);
+}
+
+static inline u64 HvLpConfig_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI)
+{
+        return (u16)HvCall1(HvCallCfgGetNumProcsInSharedPool, sPI);
+}
+
+static inline u64 HvLpConfig_getPhysicalProcessors(void)
+{
+        return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Cur);
+}
+
+static inline HvLpSharedPoolIndex HvLpConfig_getSharedPoolIndex(void)
+{
+        return HvCall1(HvCallCfgGetSharedPoolIndex, HvLpConfig_getLpIndex());
+}
+
+static inline u64 HvLpConfig_getSharedProcUnits(void)
+{
+        return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Cur);
+}
+
+static inline u64 HvLpConfig_getMaxSharedProcUnits(void)
+{
+        return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Max);
+}
+
+static inline u64 HvLpConfig_getMaxPhysicalProcessors(void)
+{
+        return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
+                        HvCallCfg_Max);
+}
+
+static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMapForLp(
+                HvLpIndex lp)
+{
+        /*
+         * This is a new function in V5R1 so calls to this on older
+         * hypervisors will return -1
+         */
+        u64 retVal = HvCall1(HvCallCfgGetVirtualLanIndexMap, lp);
+        if (retVal == -1)
+                retVal = 0;
+        return retVal;
+}
+
+static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMap(void)
+{
+        return HvLpConfig_getVirtualLanIndexMapForLp(
+                        HvLpConfig_getLpIndex_outline());
+}
+
+static inline int HvLpConfig_doLpsCommunicateOnVirtualLan(HvLpIndex lp1,
+                HvLpIndex lp2)
+{
+        HvLpVirtualLanIndexMap virtualLanIndexMap1 =
+                HvLpConfig_getVirtualLanIndexMapForLp(lp1);
+        HvLpVirtualLanIndexMap virtualLanIndexMap2 =
+                HvLpConfig_getVirtualLanIndexMapForLp(lp2);
+        return ((virtualLanIndexMap1 & virtualLanIndexMap2) != 0);
+}
+
+static inline HvLpIndex HvLpConfig_getHostingLpIndex(HvLpIndex lp)
+{
+        return HvCall1(HvCallCfgGetHostingLpIndex, lp);
+}
+
+#endif /* _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_lp_event.h b/arch/powerpc/include/asm/iseries/hv_lp_event.h
new file mode 100644
index 000000000000..8f5da7d77202
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_lp_event.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+/* This file contains the class for HV events in the system. */
+
+#ifndef _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
+#define _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
+
+#include <asm/types.h>
+#include <asm/ptrace.h>
+#include <asm/iseries/hv_types.h>
+#include <asm/iseries/hv_call_event.h>
+
+/*
+ * HvLpEvent is the structure for Lp Event messages passed between
+ * partitions through PLIC.
+ */
+
+struct HvLpEvent {
+        u8      flags;                  /* Event flags                x00-x00 */
+        u8      xType;                  /* Type of message            x01-x01 */
+        u16     xSubtype;               /* Subtype for event          x02-x03 */
+        u8      xSourceLp;              /* Source LP                  x04-x04 */
+        u8      xTargetLp;              /* Target LP                  x05-x05 */
+        u8      xSizeMinus1;            /* Size of Derived class - 1  x06-x06 */
+        u8      xRc;                    /* RC for Ack flows           x07-x07 */
+        u16     xSourceInstanceId;      /* Source sides instance id   x08-x09 */
+        u16     xTargetInstanceId;      /* Target sides instance id   x0A-x0B */
+        union {
+                u32     xSubtypeData;   /* Data usable by the subtype x0C-x0F */
+                u16     xSubtypeDataShort[2];   /* Data as 2 shorts */
+                u8      xSubtypeDataChar[4];    /* Data as 4 chars */
+        } x;
+
+        u64     xCorrelationToken;      /* Unique value for source/type x10-x17 */
+};
+
+typedef void (*LpEventHandler)(struct HvLpEvent *);
+
+/* Register a handler for an event type - returns 0 on success */
+extern int HvLpEvent_registerHandler(HvLpEvent_Type eventType,
+                LpEventHandler hdlr);
+
+/*
+ * Unregister a handler for an event type
+ *
+ * This call will sleep until the handler being removed is guaranteed to
+ * be no longer executing on any CPU. Do not call with locks held.
+ *
+ *  returns 0 on success
+ *  Unregister will fail if there are any paths open for the type
+ */
+extern int HvLpEvent_unregisterHandler(HvLpEvent_Type eventType);
+
+/*
+ * Open an Lp Event Path for an event type
+ * returns 0 on success
+ * openPath will fail if there is no handler registered for the event type.
+ * The lpIndex specified is the partition index for the target partition
+ * (for VirtualIo, VirtualLan and SessionMgr) other types specify zero)
+ */
+extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
+
+/*
+ * Close an Lp Event Path for a type and partition
+ * returns 0 on success
+ */
+extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
+
+#define HvLpEvent_Type_Hypervisor 0
+#define HvLpEvent_Type_MachineFac 1
+#define HvLpEvent_Type_SessionMgr 2
+#define HvLpEvent_Type_SpdIo      3
+#define HvLpEvent_Type_VirtualBus 4
+#define HvLpEvent_Type_PciIo      5
+#define HvLpEvent_Type_RioIo      6
+#define HvLpEvent_Type_VirtualLan 7
+#define HvLpEvent_Type_VirtualIo  8
+#define HvLpEvent_Type_NumTypes   9
+
+#define HvLpEvent_Rc_Good 0
+#define HvLpEvent_Rc_BufferNotAvailable 1
+#define HvLpEvent_Rc_Cancelled 2
+#define HvLpEvent_Rc_GenericError 3
+#define HvLpEvent_Rc_InvalidAddress 4
+#define HvLpEvent_Rc_InvalidPartition 5
+#define HvLpEvent_Rc_InvalidSize 6
+#define HvLpEvent_Rc_InvalidSubtype 7
+#define HvLpEvent_Rc_InvalidSubtypeData 8
+#define HvLpEvent_Rc_InvalidType 9
+#define HvLpEvent_Rc_PartitionDead 10
+#define HvLpEvent_Rc_PathClosed 11
+#define HvLpEvent_Rc_SubtypeError 12
+
+#define HvLpEvent_Function_Ack 0
+#define HvLpEvent_Function_Int 1
+
+#define HvLpEvent_AckInd_NoAck 0
+#define HvLpEvent_AckInd_DoAck 1
+
+#define HvLpEvent_AckType_ImmediateAck 0
+#define HvLpEvent_AckType_DeferredAck 1
+
+#define HV_LP_EVENT_INT                 0x01
+#define HV_LP_EVENT_DO_ACK              0x02
+#define HV_LP_EVENT_DEFERRED_ACK        0x04
+#define HV_LP_EVENT_VALID               0x80
+
+#define HvLpDma_Direction_LocalToRemote 0
+#define HvLpDma_Direction_RemoteToLocal 1
+
+#define HvLpDma_AddressType_TceIndex 0
+#define HvLpDma_AddressType_RealAddress 1
+
+#define HvLpDma_Rc_Good 0
+#define HvLpDma_Rc_Error 1
+#define HvLpDma_Rc_PartitionDead 2
+#define HvLpDma_Rc_PathClosed 3
+#define HvLpDma_Rc_InvalidAddress 4
+#define HvLpDma_Rc_InvalidLength 5
+
+static inline int hvlpevent_is_valid(struct HvLpEvent *h)
+{
+        return h->flags & HV_LP_EVENT_VALID;
+}
+
+static inline void hvlpevent_invalidate(struct HvLpEvent *h)
+{
+        h->flags &= ~ HV_LP_EVENT_VALID;
+}
+
+static inline int hvlpevent_is_int(struct HvLpEvent *h)
+{
+        return h->flags & HV_LP_EVENT_INT;
+}
+
+static inline int hvlpevent_is_ack(struct HvLpEvent *h)
+{
+        return !hvlpevent_is_int(h);
+}
+
+static inline int hvlpevent_need_ack(struct HvLpEvent *h)
+{
+        return h->flags & HV_LP_EVENT_DO_ACK;
+}
+
+#endif /* _ASM_POWERPC_ISERIES_HV_LP_EVENT_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_types.h b/arch/powerpc/include/asm/iseries/hv_types.h
new file mode 100644
index 000000000000..c3e6d2a1d1c3
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/hv_types.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_HV_TYPES_H
+#define _ASM_POWERPC_ISERIES_HV_TYPES_H
+
+/*
+ * General typedefs for the hypervisor.
+ */
+
+#include <asm/types.h>
+
+typedef u8      HvLpIndex;
+typedef u16     HvLpInstanceId;
+typedef u64     HvLpTOD;
+typedef u64     HvLpSystemSerialNum;
+typedef u8      HvLpDeviceSerialNum[12];
+typedef u16     HvLpSanHwSet;
+typedef u16     HvLpBus;
+typedef u16     HvLpBoard;
+typedef u16     HvLpCard;
+typedef u8      HvLpDeviceType[4];
+typedef u8      HvLpDeviceModel[3];
+typedef u64     HvIoToken;
+typedef u8      HvLpName[8];
+typedef u32     HvIoId;
+typedef u64     HvRealMemoryIndex;
+typedef u32     HvLpIndexMap;   /* Must hold HVMAXARCHITECTEDLPS bits!!! */
+typedef u16     HvLpVrmIndex;
+typedef u32     HvXmGenerationId;
+typedef u8      HvLpBusPool;
+typedef u8      HvLpSharedPoolIndex;
+typedef u16     HvLpSharedProcUnitsX100;
+typedef u8      HvLpVirtualLanIndex;
+typedef u16     HvLpVirtualLanIndexMap; /* Must hold HVMAXARCHITECTEDVIRTUALLANS bits!!! */
+typedef u16     HvBusNumber;    /* Hypervisor Bus Number */
+typedef u8      HvSubBusNumber; /* Hypervisor SubBus Number */
+typedef u8      HvAgentId;      /* Hypervisor DevFn */
+
+
+#define HVMAXARCHITECTEDLPS             32
+#define HVMAXARCHITECTEDVIRTUALLANS     16
+#define HVMAXARCHITECTEDVIRTUALDISKS    32
+#define HVMAXARCHITECTEDVIRTUALCDROMS   8
+#define HVMAXARCHITECTEDVIRTUALTAPES    8
+#define HVCHUNKSIZE                     (256 * 1024)
+#define HVPAGESIZE                      (4 * 1024)
+#define HVLPMINMEGSPRIMARY              256
+#define HVLPMINMEGSSECONDARY            64
+#define HVCHUNKSPERMEG                  4
+#define HVPAGESPERMEG                   256
+#define HVPAGESPERCHUNK                 64
+
+#define HvLpIndexInvalid                ((HvLpIndex)0xff)
+
+/*
+ * Enums for the sub-components under PLIC
+ * Used in HvCall  and HvPrimaryCall
+ */
+enum {
+        HvCallCompId = 0,
+        HvCallCpuCtlsCompId = 1,
+        HvCallCfgCompId = 2,
+        HvCallEventCompId = 3,
+        HvCallHptCompId = 4,
+        HvCallPciCompId = 5,
+        HvCallSlmCompId = 6,
+        HvCallSmCompId = 7,
+        HvCallSpdCompId = 8,
+        HvCallXmCompId = 9,
+        HvCallRioCompId = 10,
+        HvCallRsvd3CompId = 11,
+        HvCallRsvd2CompId = 12,
+        HvCallRsvd1CompId = 13,
+        HvCallMaxCompId = 14,
+        HvPrimaryCallCompId = 0,
+        HvPrimaryCallCfgCompId = 1,
+        HvPrimaryCallPciCompId = 2,
+        HvPrimaryCallSmCompId = 3,
+        HvPrimaryCallSpdCompId = 4,
+        HvPrimaryCallXmCompId = 5,
+        HvPrimaryCallRioCompId = 6,
+        HvPrimaryCallRsvd7CompId = 7,
+        HvPrimaryCallRsvd6CompId = 8,
+        HvPrimaryCallRsvd5CompId = 9,
+        HvPrimaryCallRsvd4CompId = 10,
+        HvPrimaryCallRsvd3CompId = 11,
+        HvPrimaryCallRsvd2CompId = 12,
+        HvPrimaryCallRsvd1CompId = 13,
+        HvPrimaryCallMaxCompId = HvCallMaxCompId
+};
+
+struct HvLpBufferList {
+        u64 addr;
+        u64 len;
+};
+
+#endif /* _ASM_POWERPC_ISERIES_HV_TYPES_H */
diff --git a/arch/powerpc/include/asm/iseries/iommu.h b/arch/powerpc/include/asm/iseries/iommu.h
new file mode 100644
index 000000000000..c59ee7e4bed1
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/iommu.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_POWERPC_ISERIES_IOMMU_H
+#define _ASM_POWERPC_ISERIES_IOMMU_H
+
+/*
+ * Copyright (C) 2005  Stephen Rothwell, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the:
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330,
+ * Boston, MA  02111-1307  USA
+ */
+
+struct pci_dev;
+struct vio_dev;
+struct device_node;
+struct iommu_table;
+
+/* Creates table for an individual device node */
+extern void iommu_devnode_init_iSeries(struct pci_dev *pdev,
+                                       struct device_node *dn);
+
+/* Get table parameters from HV */
+extern void iommu_table_getparms_iSeries(unsigned long busno,
+                unsigned char slotno, unsigned char virtbus,
+                struct iommu_table *tbl);
+
+extern struct iommu_table *vio_build_iommu_table_iseries(struct vio_dev *dev);
+extern void iommu_vio_init(void);
+
+#endif /* _ASM_POWERPC_ISERIES_IOMMU_H */
diff --git a/arch/powerpc/include/asm/iseries/it_lp_queue.h b/arch/powerpc/include/asm/iseries/it_lp_queue.h
new file mode 100644
index 000000000000..428278838821
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/it_lp_queue.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
+#define _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
+
+/*
+ *      This control block defines the simple LP queue structure that is
+ *      shared between the hypervisor (PLIC) and the OS in order to send
+ *      events to an LP.
+ */
+
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+#define IT_LP_MAX_QUEUES        8
+
+#define IT_LP_NOT_USED          0       /* Queue will not be used by PLIC */
+#define IT_LP_DEDICATED_IO      1       /* Queue dedicated to IO processor specified */
+#define IT_LP_DEDICATED_LP      2       /* Queue dedicated to LP specified */
+#define IT_LP_SHARED            3       /* Queue shared for both IO and LP */
+
+#define IT_LP_EVENT_STACK_SIZE  4096
+#define IT_LP_EVENT_MAX_SIZE    256
+#define IT_LP_EVENT_ALIGN       64
+
+struct hvlpevent_queue {
+/*
+ * The hq_current_event is the pointer to the next event stack entry
+ * that will become valid.  The OS must peek at this entry to determine
+ * if it is valid.  PLIC will set the valid indicator as the very last
+ * store into that entry.
+ *
+ * When the OS has completed processing of the event then it will mark
+ * the event as invalid so that PLIC knows it can store into that event
+ * location again.
+ *
+ * If the event stack fills and there are overflow events, then PLIC
+ * will set the hq_overflow_pending flag in which case the OS will
+ * have to fetch the additional LP events once they have drained the
+ * event stack.
+ *
+ * The first 16-bytes are known by both the OS and PLIC.  The remainder
+ * of the cache line is for use by the OS.
+ */
+        u8              hq_overflow_pending;    /* 0x00 Overflow events are pending */
+        u8              hq_status;              /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
+        u16             hq_proc_index;          /* 0x02 Logical Proc Index for correlation */
+        u8              hq_reserved1[12];       /* 0x04 */
+        char            *hq_current_event;      /* 0x10 */
+        char            *hq_last_event;         /* 0x18 */
+        char            *hq_event_stack;        /* 0x20 */
+        u8              hq_index;               /* 0x28 unique sequential index. */
+        u8              hq_reserved2[3];        /* 0x29-2b */
+        spinlock_t      hq_lock;
+};
+
+extern struct hvlpevent_queue hvlpevent_queue;
+
+extern int hvlpevent_is_pending(void);
+extern void process_hvlpevents(void);
+extern void setup_hvlpevent_queue(void);
+
+#endif /* _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H */
diff --git a/arch/powerpc/include/asm/iseries/lpar_map.h b/arch/powerpc/include/asm/iseries/lpar_map.h
new file mode 100644
index 000000000000..5e9f3e128ee2
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/lpar_map.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_LPAR_MAP_H
+#define _ASM_POWERPC_ISERIES_LPAR_MAP_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+#endif
+
+/*
+ * The iSeries hypervisor will set up mapping for one or more
+ * ESID/VSID pairs (in SLB/segment registers) and will set up
+ * mappings of one or more ranges of pages to VAs.
+ * We will have the hypervisor set up the ESID->VSID mapping
+ * for the four kernel segments (C-F).  With shared processors,
+ * the hypervisor will clear all segment registers and reload
+ * these four whenever the processor is switched from one
+ * partition to another.
+ */
+
+/* The Vsid and Esid identified below will be used by the hypervisor
+ * to set up a memory mapping for part of the load area before giving
+ * control to the Linux kernel.  The load area is 64 MB, but this must
+ * not attempt to map the whole load area.  The Hashed Page Table may
+ * need to be located within the load area (if the total partition size
+ * is 64 MB), but cannot be mapped.  Typically, this should specify
+ * to map half (32 MB) of the load area.
+ *
+ * The hypervisor will set up page table entries for the number of
+ * pages specified.
+ *
+ * In 32-bit mode, the hypervisor will load all four of the
+ * segment registers (identified by the low-order four bits of the
+ * Esid field.  In 64-bit mode, the hypervisor will load one SLB
+ * entry to map the Esid to the Vsid.
+*/
+
+#define HvEsidsToMap    2
+#define HvRangesToMap   1
+
+/* Hypervisor initially maps 32MB of the load area */
+#define HvPagesToMap    8192
+
+#ifndef __ASSEMBLY__
+struct LparMap {
+        u64     xNumberEsids;   // Number of ESID/VSID pairs
+        u64     xNumberRanges;  // Number of VA ranges to map
+        u64     xSegmentTableOffs; // Page number within load area of seg table
+        u64     xRsvd[5];
+        struct {
+                u64     xKernelEsid;    // Esid used to map kernel load
+                u64     xKernelVsid;    // Vsid used to map kernel load
+        } xEsids[HvEsidsToMap];
+        struct {
+                u64     xPages;         // Number of pages to be mapped
+                u64     xOffset;        // Offset from start of load area
+                u64     xVPN;           // Virtual Page Number
+        } xRanges[HvRangesToMap];
+};
+
+extern const struct LparMap     xLparMap;
+
+#endif /* __ASSEMBLY__ */
+
+/* the fixed address where the LparMap exists */
+#define LPARMAP_PHYS            0x7000
+
+#endif /* _ASM_POWERPC_ISERIES_LPAR_MAP_H */
diff --git a/arch/powerpc/include/asm/iseries/mf.h b/arch/powerpc/include/asm/iseries/mf.h
new file mode 100644
index 000000000000..eb851a9c9e5c
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/mf.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2001  Troy D. Armstrong IBM Corporation
+ * Copyright (C) 2004  Stephen Rothwell IBM Corporation
+ *
+ * This modules exists as an interface between a Linux secondary partition
+ * running on an iSeries and the primary partition's Virtual Service
+ * Processor (VSP) object.  The VSP has final authority over powering on/off
+ * all partitions in the iSeries.  It also provides miscellaneous low-level
+ * machine facility type operations.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_MF_H
+#define _ASM_POWERPC_ISERIES_MF_H
+
+#include <linux/types.h>
+
+#include <asm/iseries/hv_types.h>
+#include <asm/iseries/hv_call_event.h>
+
+struct rtc_time;
+
+typedef void (*MFCompleteHandler)(void *clientToken, int returnCode);
+
+extern void mf_allocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
+                unsigned size, unsigned amount, MFCompleteHandler hdlr,
+                void *userToken);
+extern void mf_deallocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
+                unsigned count, MFCompleteHandler hdlr, void *userToken);
+
+extern void mf_power_off(void);
+extern void mf_reboot(char *cmd);
+
+extern void mf_display_src(u32 word);
+extern void mf_display_progress(u16 value);
+
+extern void mf_init(void);
+
+#endif /* _ASM_POWERPC_ISERIES_MF_H */
diff --git a/arch/powerpc/include/asm/iseries/vio.h b/arch/powerpc/include/asm/iseries/vio.h
new file mode 100644
index 000000000000..f9ac0d00b951
--- /dev/null
+++ b/arch/powerpc/include/asm/iseries/vio.h
@@ -0,0 +1,265 @@
+/* -*- linux-c -*-
+ *
+ *  iSeries Virtual I/O Message Path header
+ *
+ *  Authors: Dave Boutcher <boutcher@us.ibm.com>
+ *           Ryan Arnold <ryanarn@us.ibm.com>
+ *           Colin Devilbiss <devilbis@us.ibm.com>
+ *
+ * (C) Copyright 2000 IBM Corporation
+ *
+ * This header file is used by the iSeries virtual I/O device
+ * drivers.  It defines the interfaces to the common functions
+ * (implemented in drivers/char/viopath.h) as well as defining
+ * common functions and structures.  Currently (at the time I
+ * wrote this comment) the iSeries virtual I/O device drivers
+ * that use this are
+ *   drivers/block/viodasd.c
+ *   drivers/char/viocons.c
+ *   drivers/char/viotape.c
+ *   drivers/cdrom/viocd.c
+ *
+ * The iSeries virtual ethernet support (veth.c) uses a whole
+ * different set of functions.
+ *
+ * This program is free software;  you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) anyu later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef _ASM_POWERPC_ISERIES_VIO_H
+#define _ASM_POWERPC_ISERIES_VIO_H
+
+#include <asm/iseries/hv_types.h>
+#include <asm/iseries/hv_lp_event.h>
+
+/*
+ * iSeries virtual I/O events use the subtype field in
+ * HvLpEvent to figure out what kind of vio event is coming
+ * in.  We use a table to route these, and this defines
+ * the maximum number of distinct subtypes
+ */
+#define VIO_MAX_SUBTYPES 8
+
+#define VIOMAXBLOCKDMA  12
+
+struct open_data {
+        u64     disk_size;
+        u16     max_disk;
+        u16     cylinders;
+        u16     tracks;
+        u16     sectors;
+        u16     bytes_per_sector;
+};
+
+struct rw_data {
+        u64     offset;
+        struct {
+                u32     token;
+                u32     reserved;
+                u64     len;
+        } dma_info[VIOMAXBLOCKDMA];
+};
+
+struct vioblocklpevent {
+        struct HvLpEvent        event;
+        u32                     reserved;
+        u16                     version;
+        u16                     sub_result;
+        u16                     disk;
+        u16                     flags;
+        union {
+                struct open_data        open_data;
+                struct rw_data          rw_data;
+                u64                     changed;
+        } u;
+};
+
+#define vioblockflags_ro   0x0001
+
+enum vioblocksubtype {
+        vioblockopen = 0x0001,
+        vioblockclose = 0x0002,
+        vioblockread = 0x0003,
+        vioblockwrite = 0x0004,
+        vioblockflush = 0x0005,
+        vioblockcheck = 0x0007
+};
+
+struct viocdlpevent {
+        struct HvLpEvent        event;
+        u32                     reserved;
+        u16                     version;
+        u16                     sub_result;
+        u16                     disk;
+        u16                     flags;
+        u32                     token;
+        u64                     offset;         /* On open, max number of disks */
+        u64                     len;            /* On open, size of the disk */
+        u32                     block_size;     /* Only set on open */
+        u32                     media_size;     /* Only set on open */
+};
+
+enum viocdsubtype {
+        viocdopen = 0x0001,
+        viocdclose = 0x0002,
+        viocdread = 0x0003,
+        viocdwrite = 0x0004,
+        viocdlockdoor = 0x0005,
+        viocdgetinfo = 0x0006,
+        viocdcheck = 0x0007
+};
+
+struct viotapelpevent {
+        struct HvLpEvent event;
+        u32 reserved;
+        u16 version;
+        u16 sub_type_result;
+        u16 tape;
+        u16 flags;
+        u32 token;
+        u64 len;
+        union {
+                struct {
+                        u32 tape_op;
+                        u32 count;
+                } op;
+                struct {
+                        u32 type;
+                        u32 resid;
+                        u32 dsreg;
+                        u32 gstat;
+                        u32 erreg;
+                        u32 file_no;
+                        u32 block_no;
+                } get_status;
+                struct {
+                        u32 block_no;
+                } get_pos;
+        } u;
+};
+
+enum viotapesubtype {
+        viotapeopen = 0x0001,
+        viotapeclose = 0x0002,
+        viotaperead = 0x0003,
+        viotapewrite = 0x0004,
+        viotapegetinfo = 0x0005,
+        viotapeop = 0x0006,
+        viotapegetpos = 0x0007,
+        viotapesetpos = 0x0008,
+        viotapegetstatus = 0x0009
+};
+
+/*
+ * Each subtype can register a handler to process their events.
+ * The handler must have this interface.
+ */
+typedef void (vio_event_handler_t) (struct HvLpEvent * event);
+
+extern int viopath_open(HvLpIndex remoteLp, int subtype, int numReq);
+extern int viopath_close(HvLpIndex remoteLp, int subtype, int numReq);
+extern int vio_setHandler(int subtype, vio_event_handler_t * beh);
+extern int vio_clearHandler(int subtype);
+extern int viopath_isactive(HvLpIndex lp);
+extern HvLpInstanceId viopath_sourceinst(HvLpIndex lp);
+extern HvLpInstanceId viopath_targetinst(HvLpIndex lp);
+extern void vio_set_hostlp(void);
+extern void *vio_get_event_buffer(int subtype);
+extern void vio_free_event_buffer(int subtype, void *buffer);
+
+extern struct vio_dev *vio_create_viodasd(u32 unit);
+
+extern HvLpIndex viopath_hostLp;
+extern HvLpIndex viopath_ourLp;
+
+#define VIOCHAR_MAX_DATA        200
+
+#define VIOMAJOR_SUBTYPE_MASK   0xff00
+#define VIOMINOR_SUBTYPE_MASK   0x00ff
+#define VIOMAJOR_SUBTYPE_SHIFT  8
+
+#define VIOVERSION              0x0101
+
+/*
+ * This is the general structure for VIO errors; each module should have
+ * a table of them, and each table should be terminated by an entry of
+ * { 0, 0, NULL }.  Then, to find a specific error message, a module
+ * should pass its local table and the return code.
+ */
+struct vio_error_entry {
+        u16 rc;
+        int errno;
+        const char *msg;
+};
+extern const struct vio_error_entry *vio_lookup_rc(
+                const struct vio_error_entry *local_table, u16 rc);
+
+enum viosubtypes {
+        viomajorsubtype_monitor = 0x0100,
+        viomajorsubtype_blockio = 0x0200,
+        viomajorsubtype_chario = 0x0300,
+        viomajorsubtype_config = 0x0400,
+        viomajorsubtype_cdio = 0x0500,
+        viomajorsubtype_tape = 0x0600,
+        viomajorsubtype_scsi = 0x0700
+};
+
+enum vioconfigsubtype {
+        vioconfigget = 0x0001,
+};
+
+enum viorc {
+        viorc_good = 0x0000,
+        viorc_noConnection = 0x0001,
+        viorc_noReceiver = 0x0002,
+        viorc_noBufferAvailable = 0x0003,
+        viorc_invalidMessageType = 0x0004,
+        viorc_invalidRange = 0x0201,
+        viorc_invalidToken = 0x0202,
+        viorc_DMAError = 0x0203,
+        viorc_useError = 0x0204,
+        viorc_releaseError = 0x0205,
+        viorc_invalidDisk = 0x0206,
+        viorc_openRejected = 0x0301
+};
+
+/*
+ * The structure of the events that flow between us and OS/400 for chario
+ * events.  You can't mess with this unless the OS/400 side changes too.
+ */
+struct viocharlpevent {
+        struct HvLpEvent event;
+        u32 reserved;
+        u16 version;
+        u16 subtype_result_code;
+        u8 virtual_device;
+        u8 len;
+        u8 data[VIOCHAR_MAX_DATA];
+};
+
+#define VIOCHAR_WINDOW          10
+
+enum viocharsubtype {
+        viocharopen = 0x0001,
+        viocharclose = 0x0002,
+        viochardata = 0x0003,
+        viocharack = 0x0004,
+        viocharconfig = 0x0005
+};
+
+enum viochar_rc {
+        viochar_rc_ebusy = 1
+};
+
+#endif /* _ASM_POWERPC_ISERIES_VIO_H */
diff --git a/arch/powerpc/include/asm/kdebug.h b/arch/powerpc/include/asm/kdebug.h
new file mode 100644
index 000000000000..ae6d206728af
--- /dev/null
+++ b/arch/powerpc/include/asm/kdebug.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_POWERPC_KDEBUG_H
+#define _ASM_POWERPC_KDEBUG_H
+#ifdef __KERNEL__
+
+/* Grossly misnamed. */
+enum die_val {
+        DIE_OOPS = 1,
+        DIE_IABR_MATCH,
+        DIE_DABR_MATCH,
+        DIE_BPT,
+        DIE_SSTEP,
+};
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/arch/powerpc/include/asm/kdump.h b/arch/powerpc/include/asm/kdump.h
new file mode 100644
index 000000000000..f6c93c716898
--- /dev/null
+++ b/arch/powerpc/include/asm/kdump.h
@@ -0,0 +1,35 @@
+#ifndef _PPC64_KDUMP_H
+#define _PPC64_KDUMP_H
+
+/* Kdump kernel runs at 32 MB, change at your peril. */
+#define KDUMP_KERNELBASE        0x2000000
+
+/* How many bytes to reserve at zero for kdump. The reserve limit should
+ * be greater or equal to the trampoline's end address.
+ * Reserve to the end of the FWNMI area, see head_64.S */
+#define KDUMP_RESERVE_LIMIT     0x10000 /* 64K */
+
+#ifdef CONFIG_CRASH_DUMP
+
+#define KDUMP_TRAMPOLINE_START  0x0100
+#define KDUMP_TRAMPOLINE_END    0x3000
+
+#define KDUMP_MIN_TCE_ENTRIES   2048
+
+#endif /* CONFIG_CRASH_DUMP */
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_CRASH_DUMP
+
+extern void reserve_kdump_trampoline(void);
+extern void setup_kdump_trampoline(void);
+
+#else /* !CONFIG_CRASH_DUMP */
+
+static inline void reserve_kdump_trampoline(void) { ; }
+static inline void setup_kdump_trampoline(void) { ; }
+
+#endif /* CONFIG_CRASH_DUMP */
+#endif /* __ASSEMBLY__ */
+
+#endif /* __PPC64_KDUMP_H */
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
new file mode 100644
index 000000000000..acdcdc66f1b6
--- /dev/null
+++ b/arch/powerpc/include/asm/kexec.h
@@ -0,0 +1,160 @@
+#ifndef _ASM_POWERPC_KEXEC_H
+#define _ASM_POWERPC_KEXEC_H
+#ifdef __KERNEL__
+
+/*
+ * Maximum page that is mapped directly into kernel memory.
+ * XXX: Since we copy virt we can use any page we allocate
+ */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+
+/*
+ * Maximum address we can reach in physical address mode.
+ * XXX: I want to allow initrd in highmem. Otherwise set to rmo on LPAR.
+ */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+
+/* Maximum address we can use for the control code buffer */
+#ifdef __powerpc64__
+#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
+#else
+/* TASK_SIZE, probably left over from use_mm ?? */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+#endif
+
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#ifdef __powerpc64__
+#define KEXEC_ARCH KEXEC_ARCH_PPC64
+#else
+#define KEXEC_ARCH KEXEC_ARCH_PPC
+#endif
+
+#ifndef __ASSEMBLY__
+#include <linux/cpumask.h>
+
+typedef void (*crash_shutdown_t)(void);
+
+#ifdef CONFIG_KEXEC
+
+#ifdef __powerpc64__
+/*
+ * This function is responsible for capturing register states if coming
+ * via panic or invoking dump using sysrq-trigger.
+ */
+static inline void crash_setup_regs(struct pt_regs *newregs,
+                                        struct pt_regs *oldregs)
+{
+        if (oldregs)
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        else {
+                /* FIXME Merge this with xmon_save_regs ?? */
+                unsigned long tmp1, tmp2;
+                __asm__ __volatile__ (
+                        "std    0,0(%2)\n"
+                        "std    1,8(%2)\n"
+                        "std    2,16(%2)\n"
+                        "std    3,24(%2)\n"
+                        "std    4,32(%2)\n"
+                        "std    5,40(%2)\n"
+                        "std    6,48(%2)\n"
+                        "std    7,56(%2)\n"
+                        "std    8,64(%2)\n"
+                        "std    9,72(%2)\n"
+                        "std    10,80(%2)\n"
+                        "std    11,88(%2)\n"
+                        "std    12,96(%2)\n"
+                        "std    13,104(%2)\n"
+                        "std    14,112(%2)\n"
+                        "std    15,120(%2)\n"
+                        "std    16,128(%2)\n"
+                        "std    17,136(%2)\n"
+                        "std    18,144(%2)\n"
+                        "std    19,152(%2)\n"
+                        "std    20,160(%2)\n"
+                        "std    21,168(%2)\n"
+                        "std    22,176(%2)\n"
+                        "std    23,184(%2)\n"
+                        "std    24,192(%2)\n"
+                        "std    25,200(%2)\n"
+                        "std    26,208(%2)\n"
+                        "std    27,216(%2)\n"
+                        "std    28,224(%2)\n"
+                        "std    29,232(%2)\n"
+                        "std    30,240(%2)\n"
+                        "std    31,248(%2)\n"
+                        "mfmsr  %0\n"
+                        "std    %0, 264(%2)\n"
+                        "mfctr  %0\n"
+                        "std    %0, 280(%2)\n"
+                        "mflr   %0\n"
+                        "std    %0, 288(%2)\n"
+                        "bl     1f\n"
+                "1:     mflr   %1\n"
+                        "std    %1, 256(%2)\n"
+                        "mtlr   %0\n"
+                        "mfxer  %0\n"
+                        "std    %0, 296(%2)\n"
+                        : "=&r" (tmp1), "=&r" (tmp2)
+                        : "b" (newregs)
+                        : "memory");
+        }
+}
+#else
+/*
+ * Provide a dummy definition to avoid build failures. Will remain
+ * empty till crash dump support is enabled.
+ */
+static inline void crash_setup_regs(struct pt_regs *newregs,
+                                        struct pt_regs *oldregs) { }
+#endif /* !__powerpc64 __ */
+
+extern void kexec_smp_wait(void);       /* get and clear naca physid, wait for
+                                          master to copy new code to 0 */
+extern int crashing_cpu;
+extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
+extern cpumask_t cpus_in_sr;
+static inline int kexec_sr_activated(int cpu)
+{
+        return cpu_isset(cpu,cpus_in_sr);
+}
+
+struct kimage;
+struct pt_regs;
+extern void default_machine_kexec(struct kimage *image);
+extern int default_machine_kexec_prepare(struct kimage *image);
+extern void default_machine_crash_shutdown(struct pt_regs *regs);
+extern int crash_shutdown_register(crash_shutdown_t handler);
+extern int crash_shutdown_unregister(crash_shutdown_t handler);
+
+extern void machine_kexec_simple(struct kimage *image);
+extern void crash_kexec_secondary(struct pt_regs *regs);
+extern int overlaps_crashkernel(unsigned long start, unsigned long size);
+extern void reserve_crashkernel(void);
+
+#else /* !CONFIG_KEXEC */
+static inline int kexec_sr_activated(int cpu) { return 0; }
+static inline void crash_kexec_secondary(struct pt_regs *regs) { }
+
+static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
+{
+        return 0;
+}
+
+static inline void reserve_crashkernel(void) { ; }
+
+static inline int crash_shutdown_register(crash_shutdown_t handler)
+{
+        return 0;
+}
+
+static inline int crash_shutdown_unregister(crash_shutdown_t handler)
+{
+        return 0;
+}
+
+#endif /* CONFIG_KEXEC */
+#endif /* ! __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_KEXEC_H */
diff --git a/arch/powerpc/include/asm/keylargo.h b/arch/powerpc/include/asm/keylargo.h
new file mode 100644
index 000000000000..d8520ef121f9
--- /dev/null
+++ b/arch/powerpc/include/asm/keylargo.h
@@ -0,0 +1,261 @@
+#ifndef _ASM_POWERPC_KEYLARGO_H
+#define _ASM_POWERPC_KEYLARGO_H
+#ifdef __KERNEL__
+/*
+ * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
+ *
+ */
+
+/* "Pangea" chipset has keylargo device-id 0x25 while core99
+ * has device-id 0x22. The rev. of the pangea one is 0, so we
+ * fake an artificial rev. in keylargo_rev by oring 0x100
+ */
+#define KL_PANGEA_REV           0x100
+
+/* offset from base for feature control registers */
+#define KEYLARGO_MBCR           0x34    /* KL Only, Media bay control/status */
+#define KEYLARGO_FCR0           0x38
+#define KEYLARGO_FCR1           0x3c
+#define KEYLARGO_FCR2           0x40
+#define KEYLARGO_FCR3           0x44
+#define KEYLARGO_FCR4           0x48
+#define KEYLARGO_FCR5           0x4c    /* Pangea only */
+
+/* K2 aditional FCRs */
+#define K2_FCR6                 0x34
+#define K2_FCR7                 0x30
+#define K2_FCR8                 0x2c
+#define K2_FCR9                 0x28
+#define K2_FCR10                0x24
+
+/* GPIO registers */
+#define KEYLARGO_GPIO_LEVELS0           0x50
+#define KEYLARGO_GPIO_LEVELS1           0x54
+#define KEYLARGO_GPIO_EXTINT_0          0x58
+#define KEYLARGO_GPIO_EXTINT_CNT        18
+#define KEYLARGO_GPIO_0                 0x6A
+#define KEYLARGO_GPIO_CNT               17
+#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE  0x80
+#define KEYLARGO_GPIO_OUTPUT_ENABLE     0x04
+#define KEYLARGO_GPIO_OUTOUT_DATA       0x01
+#define KEYLARGO_GPIO_INPUT_DATA        0x02
+
+/* K2 does only extint GPIOs and does 51 of them */
+#define K2_GPIO_EXTINT_0                0x58
+#define K2_GPIO_EXTINT_CNT              51
+
+/* Specific GPIO regs */
+
+#define KL_GPIO_MODEM_RESET             (KEYLARGO_GPIO_0+0x03)
+#define KL_GPIO_MODEM_POWER             (KEYLARGO_GPIO_0+0x02) /* Pangea */
+
+#define KL_GPIO_SOUND_POWER             (KEYLARGO_GPIO_0+0x05)
+
+/* Hrm... this one is only to be used on Pismo. It seeem to also
+ * control the timebase enable on other machines. Still to be
+ * experimented... --BenH.
+ */
+#define KL_GPIO_FW_CABLE_POWER          (KEYLARGO_GPIO_0+0x09)
+#define KL_GPIO_TB_ENABLE               (KEYLARGO_GPIO_0+0x09)
+
+#define KL_GPIO_ETH_PHY_RESET           (KEYLARGO_GPIO_0+0x10)
+
+#define KL_GPIO_EXTINT_CPU1             (KEYLARGO_GPIO_0+0x0a)
+#define KL_GPIO_EXTINT_CPU1_ASSERT      0x04
+#define KL_GPIO_EXTINT_CPU1_RELEASE     0x38
+
+#define KL_GPIO_RESET_CPU0              (KEYLARGO_GPIO_EXTINT_0+0x03)
+#define KL_GPIO_RESET_CPU1              (KEYLARGO_GPIO_EXTINT_0+0x04)
+#define KL_GPIO_RESET_CPU2              (KEYLARGO_GPIO_EXTINT_0+0x0f)
+#define KL_GPIO_RESET_CPU3              (KEYLARGO_GPIO_EXTINT_0+0x10)
+
+#define KL_GPIO_PMU_MESSAGE_IRQ         (KEYLARGO_GPIO_EXTINT_0+0x09)
+#define KL_GPIO_PMU_MESSAGE_BIT         KEYLARGO_GPIO_INPUT_DATA
+
+#define KL_GPIO_MEDIABAY_IRQ            (KEYLARGO_GPIO_EXTINT_0+0x0e)
+
+#define KL_GPIO_AIRPORT_0               (KEYLARGO_GPIO_EXTINT_0+0x0a)
+#define KL_GPIO_AIRPORT_1               (KEYLARGO_GPIO_EXTINT_0+0x0d)
+#define KL_GPIO_AIRPORT_2               (KEYLARGO_GPIO_0+0x0d)
+#define KL_GPIO_AIRPORT_3               (KEYLARGO_GPIO_0+0x0e)
+#define KL_GPIO_AIRPORT_4               (KEYLARGO_GPIO_0+0x0f)
+
+/*
+ * Bits in feature control register. Those bits different for K2 are
+ * listed separately
+ */
+#define KL_MBCR_MB0_PCI_ENABLE          0x00000800      /* exist ? */
+#define KL_MBCR_MB0_IDE_ENABLE          0x00001000
+#define KL_MBCR_MB0_FLOPPY_ENABLE       0x00002000      /* exist ? */
+#define KL_MBCR_MB0_SOUND_ENABLE        0x00004000      /* hrm... */
+#define KL_MBCR_MB0_DEV_MASK            0x00007800
+#define KL_MBCR_MB0_DEV_POWER           0x00000400
+#define KL_MBCR_MB0_DEV_RESET           0x00000200
+#define KL_MBCR_MB0_ENABLE              0x00000100
+#define KL_MBCR_MB1_PCI_ENABLE          0x08000000      /* exist ? */
+#define KL_MBCR_MB1_IDE_ENABLE          0x10000000
+#define KL_MBCR_MB1_FLOPPY_ENABLE       0x20000000      /* exist ? */
+#define KL_MBCR_MB1_SOUND_ENABLE        0x40000000      /* hrm... */
+#define KL_MBCR_MB1_DEV_MASK            0x78000000
+#define KL_MBCR_MB1_DEV_POWER           0x04000000
+#define KL_MBCR_MB1_DEV_RESET           0x02000000
+#define KL_MBCR_MB1_ENABLE              0x01000000
+
+#define KL0_SCC_B_INTF_ENABLE           0x00000001      /* (KL Only) */
+#define KL0_SCC_A_INTF_ENABLE           0x00000002
+#define KL0_SCC_SLOWPCLK                0x00000004
+#define KL0_SCC_RESET                   0x00000008
+#define KL0_SCCA_ENABLE                 0x00000010
+#define KL0_SCCB_ENABLE                 0x00000020
+#define KL0_SCC_CELL_ENABLE             0x00000040
+#define KL0_IRDA_HIGH_BAND              0x00000100      /* (KL Only) */
+#define KL0_IRDA_SOURCE2_SEL            0x00000200      /* (KL Only) */
+#define KL0_IRDA_SOURCE1_SEL            0x00000400      /* (KL Only) */
+#define KL0_PG_USB0_PMI_ENABLE          0x00000400      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_RESET                  0x00000800      /* (KL Only) */
+#define KL0_PG_USB0_REF_SUSPEND_SEL     0x00000800      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_DEFAULT1               0x00001000      /* (KL Only) */
+#define KL0_PG_USB0_REF_SUSPEND         0x00001000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_DEFAULT0               0x00002000      /* (KL Only) */
+#define KL0_PG_USB0_PAD_SUSPEND         0x00002000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_FAST_CONNECT           0x00004000      /* (KL Only) */
+#define KL0_PG_USB1_PMI_ENABLE          0x00004000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_ENABLE                 0x00008000      /* (KL Only) */
+#define KL0_PG_USB1_REF_SUSPEND_SEL     0x00008000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_CLK32_ENABLE           0x00010000      /* (KL Only) */
+#define KL0_PG_USB1_REF_SUSPEND         0x00010000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_CLK19_ENABLE           0x00020000      /* (KL Only) */
+#define KL0_PG_USB1_PAD_SUSPEND         0x00020000      /* (Pangea/Intrepid Only) */
+#define KL0_USB0_PAD_SUSPEND0           0x00040000
+#define KL0_USB0_PAD_SUSPEND1           0x00080000
+#define KL0_USB0_CELL_ENABLE            0x00100000
+#define KL0_USB1_PAD_SUSPEND0           0x00400000
+#define KL0_USB1_PAD_SUSPEND1           0x00800000
+#define KL0_USB1_CELL_ENABLE            0x01000000
+#define KL0_USB_REF_SUSPEND             0x10000000      /* (KL Only) */
+
+#define KL0_SERIAL_ENABLE               (KL0_SCC_B_INTF_ENABLE | \
+                                        KL0_SCC_SLOWPCLK | \
+                                        KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
+
+#define KL1_USB2_PMI_ENABLE             0x00000001      /* Intrepid only */
+#define KL1_AUDIO_SEL_22MCLK            0x00000002      /* KL/Pangea only */
+#define KL1_USB2_REF_SUSPEND_SEL        0x00000002      /* Intrepid only */
+#define KL1_USB2_REF_SUSPEND            0x00000004      /* Intrepid only */
+#define KL1_AUDIO_CLK_ENABLE_BIT        0x00000008      /* KL/Pangea only */
+#define KL1_USB2_PAD_SUSPEND_SEL        0x00000008      /* Intrepid only */
+#define KL1_USB2_PAD_SUSPEND0           0x00000010      /* Intrepid only */
+#define KL1_AUDIO_CLK_OUT_ENABLE        0x00000020      /* KL/Pangea only */
+#define KL1_USB2_PAD_SUSPEND1           0x00000020      /* Intrepid only */
+#define KL1_AUDIO_CELL_ENABLE           0x00000040      /* KL/Pangea only */
+#define KL1_USB2_CELL_ENABLE            0x00000040      /* Intrepid only */
+#define KL1_AUDIO_CHOOSE                0x00000080      /* KL/Pangea only */
+#define KL1_I2S0_CHOOSE                 0x00000200      /* KL Only */
+#define KL1_I2S0_CELL_ENABLE            0x00000400
+#define KL1_I2S0_CLK_ENABLE_BIT         0x00001000
+#define KL1_I2S0_ENABLE                 0x00002000
+#define KL1_I2S1_CELL_ENABLE            0x00020000
+#define KL1_I2S1_CLK_ENABLE_BIT         0x00080000
+#define KL1_I2S1_ENABLE                 0x00100000
+#define KL1_EIDE0_ENABLE                0x00800000      /* KL/Intrepid Only */
+#define KL1_EIDE0_RESET_N               0x01000000      /* KL/Intrepid Only */
+#define KL1_EIDE1_ENABLE                0x04000000      /* KL Only */
+#define KL1_EIDE1_RESET_N               0x08000000      /* KL Only */
+#define KL1_UIDE_ENABLE                 0x20000000      /* KL/Pangea Only */
+#define KL1_UIDE_RESET_N                0x40000000      /* KL/Pangea Only */
+
+#define KL2_IOBUS_ENABLE                0x00000002
+#define KL2_SLEEP_STATE_BIT             0x00000100      /* KL Only */
+#define KL2_PG_STOP_ALL_CLOCKS          0x00000100      /* Pangea Only */
+#define KL2_MPIC_ENABLE                 0x00020000
+#define KL2_CARDSLOT_RESET              0x00040000      /* Pangea/Intrepid Only */
+#define KL2_ALT_DATA_OUT                0x02000000      /* KL Only ??? */
+#define KL2_MEM_IS_BIG                  0x04000000
+#define KL2_CARDSEL_16                  0x08000000
+
+#define KL3_SHUTDOWN_PLL_TOTAL          0x00000001      /* KL/Pangea only */
+#define KL3_SHUTDOWN_PLLKW6             0x00000002      /* KL/Pangea only */
+#define KL3_IT_SHUTDOWN_PLL3            0x00000002      /* Intrepid only */
+#define KL3_SHUTDOWN_PLLKW4             0x00000004      /* KL/Pangea only */
+#define KL3_IT_SHUTDOWN_PLL2            0x00000004      /* Intrepid only */
+#define KL3_SHUTDOWN_PLLKW35            0x00000008      /* KL/Pangea only */
+#define KL3_IT_SHUTDOWN_PLL1            0x00000008      /* Intrepid only */
+#define KL3_SHUTDOWN_PLLKW12            0x00000010      /* KL Only */
+#define KL3_IT_ENABLE_PLL3_SHUTDOWN     0x00000010      /* Intrepid only */
+#define KL3_PLL_RESET                   0x00000020      /* KL/Pangea only */
+#define KL3_IT_ENABLE_PLL2_SHUTDOWN     0x00000020      /* Intrepid only */
+#define KL3_IT_ENABLE_PLL1_SHUTDOWN     0x00000010      /* Intrepid only */
+#define KL3_SHUTDOWN_PLL2X              0x00000080      /* KL Only */
+#define KL3_CLK66_ENABLE                0x00000100      /* KL Only */
+#define KL3_CLK49_ENABLE                0x00000200
+#define KL3_CLK45_ENABLE                0x00000400
+#define KL3_CLK31_ENABLE                0x00000800      /* KL/Pangea only */
+#define KL3_TIMER_CLK18_ENABLE          0x00001000
+#define KL3_I2S1_CLK18_ENABLE           0x00002000
+#define KL3_I2S0_CLK18_ENABLE           0x00004000
+#define KL3_VIA_CLK16_ENABLE            0x00008000      /* KL/Pangea only */
+#define KL3_IT_VIA_CLK32_ENABLE         0x00008000      /* Intrepid only */
+#define KL3_STOPPING33_ENABLED          0x00080000      /* KL Only */
+#define KL3_PG_PLL_ENABLE_TEST          0x00080000      /* Pangea Only */
+
+/* Intrepid USB bus 2, port 0,1 */
+#define KL3_IT_PORT_WAKEUP_ENABLE(p)            (0x00080000 << ((p)<<3))
+#define KL3_IT_PORT_RESUME_WAKE_EN(p)           (0x00040000 << ((p)<<3))
+#define KL3_IT_PORT_CONNECT_WAKE_EN(p)          (0x00020000 << ((p)<<3))
+#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p)       (0x00010000 << ((p)<<3))
+#define KL3_IT_PORT_RESUME_STAT(p)              (0x00300000 << ((p)<<3))
+#define KL3_IT_PORT_CONNECT_STAT(p)             (0x00200000 << ((p)<<3))
+#define KL3_IT_PORT_DISCONNECT_STAT(p)          (0x00100000 << ((p)<<3))
+
+/* Port 0,1 : bus 0, port 2,3 : bus 1 */
+#define KL4_PORT_WAKEUP_ENABLE(p)       (0x00000008 << ((p)<<3))
+#define KL4_PORT_RESUME_WAKE_EN(p)      (0x00000004 << ((p)<<3))
+#define KL4_PORT_CONNECT_WAKE_EN(p)     (0x00000002 << ((p)<<3))
+#define KL4_PORT_DISCONNECT_WAKE_EN(p)  (0x00000001 << ((p)<<3))
+#define KL4_PORT_RESUME_STAT(p)         (0x00000040 << ((p)<<3))
+#define KL4_PORT_CONNECT_STAT(p)        (0x00000020 << ((p)<<3))
+#define KL4_PORT_DISCONNECT_STAT(p)     (0x00000010 << ((p)<<3))
+
+/* Pangea and Intrepid only */
+#define KL5_VIA_USE_CLK31               0000000001      /* Pangea Only */
+#define KL5_SCC_USE_CLK31               0x00000002      /* Pangea Only */
+#define KL5_PWM_CLK32_EN                0x00000004
+#define KL5_CLK3_68_EN                  0x00000010
+#define KL5_CLK32_EN                    0x00000020
+
+
+/* K2 definitions */
+#define K2_FCR0_USB0_SWRESET            0x00200000
+#define K2_FCR0_USB1_SWRESET            0x02000000
+#define K2_FCR0_RING_PME_DISABLE        0x08000000
+
+#define K2_FCR1_PCI1_BUS_RESET_N        0x00000010
+#define K2_FCR1_PCI1_SLEEP_RESET_EN     0x00000020
+#define K2_FCR1_I2S0_CELL_ENABLE        0x00000400
+#define K2_FCR1_I2S0_RESET              0x00000800
+#define K2_FCR1_I2S0_CLK_ENABLE_BIT     0x00001000
+#define K2_FCR1_I2S0_ENABLE             0x00002000
+#define K2_FCR1_PCI1_CLK_ENABLE         0x00004000
+#define K2_FCR1_FW_CLK_ENABLE           0x00008000
+#define K2_FCR1_FW_RESET_N              0x00010000
+#define K2_FCR1_I2S1_CELL_ENABLE        0x00020000
+#define K2_FCR1_I2S1_CLK_ENABLE_BIT     0x00080000
+#define K2_FCR1_I2S1_ENABLE             0x00100000
+#define K2_FCR1_GMAC_CLK_ENABLE         0x00400000
+#define K2_FCR1_GMAC_POWER_DOWN         0x00800000
+#define K2_FCR1_GMAC_RESET_N            0x01000000
+#define K2_FCR1_SATA_CLK_ENABLE         0x02000000
+#define K2_FCR1_SATA_POWER_DOWN         0x04000000
+#define K2_FCR1_SATA_RESET_N            0x08000000
+#define K2_FCR1_UATA_CLK_ENABLE         0x10000000
+#define K2_FCR1_UATA_RESET_N            0x40000000
+#define K2_FCR1_UATA_CHOOSE_CLK66       0x80000000
+
+/* Shasta definitions */
+#define SH_FCR1_I2S2_CELL_ENABLE        0x00000010
+#define SH_FCR1_I2S2_CLK_ENABLE_BIT     0x00000040
+#define SH_FCR1_I2S2_ENABLE             0x00000080
+#define SH_FCR3_I2S2_CLK18_ENABLE       0x00008000
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_KEYLARGO_H */
diff --git a/arch/powerpc/include/asm/kgdb.h b/arch/powerpc/include/asm/kgdb.h
new file mode 100644
index 000000000000..edd217006d27
--- /dev/null
+++ b/arch/powerpc/include/asm/kgdb.h
@@ -0,0 +1,63 @@
+/*
+ * The PowerPC (32/64) specific defines / externs for KGDB.  Based on
+ * the previous 32bit and 64bit specific files, which had the following
+ * copyrights:
+ *
+ * PPC64 Mods (C) 2005 Frank Rowand (frowand@mvista.com)
+ * PPC Mods (C) 2004 Tom Rini (trini@mvista.com)
+ * PPC Mods (C) 2003 John Whitney (john.whitney@timesys.com)
+ * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
+ *
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Author: Tom Rini <trini@kernel.crashing.org>
+ *
+ * 2006 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifdef __KERNEL__
+#ifndef __POWERPC_KGDB_H__
+#define __POWERPC_KGDB_H__
+
+#ifndef __ASSEMBLY__
+
+#define BREAK_INSTR_SIZE        4
+#define BUFMAX                  ((NUMREGBYTES * 2) + 512)
+#define OUTBUFMAX               ((NUMREGBYTES * 2) + 512)
+static inline void arch_kgdb_breakpoint(void)
+{
+        asm(".long 0x7d821008"); /* twge r2, r2 */
+}
+#define CACHE_FLUSH_IS_SAFE     1
+
+/* The number bytes of registers we have to save depends on a few
+ * things.  For 64bit we default to not including vector registers and
+ * vector state registers. */
+#ifdef CONFIG_PPC64
+/*
+ * 64 bit (8 byte) registers:
+ *   32 gpr, 32 fpr, nip, msr, link, ctr
+ * 32 bit (4 byte) registers:
+ *   ccr, xer, fpscr
+ */
+#define NUMREGBYTES             ((68 * 8) + (3 * 4))
+#define NUMCRITREGBYTES         184
+#else /* CONFIG_PPC32 */
+/* On non-E500 family PPC32 we determine the size by picking the last
+ * register we need, but on E500 we skip sections so we list what we
+ * need to store, and add it up. */
+#ifndef CONFIG_E500
+#define MAXREG                  (PT_FPSCR+1)
+#else
+/* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/
+#define MAXREG                 ((32*2)+6+2+1)
+#endif
+#define NUMREGBYTES             (MAXREG * sizeof(int))
+/* CR/LR, R1, R2, R13-R31 inclusive. */
+#define NUMCRITREGBYTES         (23 * sizeof(int))
+#endif /* 32/64 */
+#endif /* !(__ASSEMBLY__) */
+#endif /* !__POWERPC_KGDB_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/kmap_types.h b/arch/powerpc/include/asm/kmap_types.h
new file mode 100644
index 000000000000..b6bac6f61c16
--- /dev/null
+++ b/arch/powerpc/include/asm/kmap_types.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_POWERPC_KMAP_TYPES_H
+#define _ASM_POWERPC_KMAP_TYPES_H
+
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
+        KM_PPC_SYNC_PAGE,
+        KM_PPC_SYNC_ICACHE,
+        KM_TYPE_NR
+};
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/arch/powerpc/include/asm/kprobes.h b/arch/powerpc/include/asm/kprobes.h
new file mode 100644
index 000000000000..d0e7701fa1f6
--- /dev/null
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -0,0 +1,118 @@
+#ifndef _ASM_POWERPC_KPROBES_H
+#define _ASM_POWERPC_KPROBES_H
+#ifdef __KERNEL__
+/*
+ *  Kernel Probes (KProbes)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2004
+ *
+ * 2002-Oct     Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
+ *              Probes initial implementation ( includes suggestions from
+ *              Rusty Russell).
+ * 2004-Nov     Modified for PPC64 by Ananth N Mavinakayanahalli
+ *              <ananth@in.ibm.com>
+ */
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/percpu.h>
+
+#define  __ARCH_WANT_KPROBES_INSN_SLOT
+
+struct pt_regs;
+struct kprobe;
+
+typedef unsigned int kprobe_opcode_t;
+#define BREAKPOINT_INSTRUCTION  0x7fe00008      /* trap */
+#define MAX_INSN_SIZE 1
+
+#define IS_TW(instr)            (((instr) & 0xfc0007fe) == 0x7c000008)
+#define IS_TD(instr)            (((instr) & 0xfc0007fe) == 0x7c000088)
+#define IS_TDI(instr)           (((instr) & 0xfc000000) == 0x08000000)
+#define IS_TWI(instr)           (((instr) & 0xfc000000) == 0x0c000000)
+
+#ifdef CONFIG_PPC64
+/*
+ * 64bit powerpc uses function descriptors.
+ * Handle cases where:
+ *              - User passes a <.symbol> or <module:.symbol>
+ *              - User passes a <symbol> or <module:symbol>
+ *              - User passes a non-existant symbol, kallsyms_lookup_name
+ *                returns 0. Don't deref the NULL pointer in that case
+ */
+#define kprobe_lookup_name(name, addr)                                  \
+{                                                                       \
+        addr = (kprobe_opcode_t *)kallsyms_lookup_name(name);           \
+        if (addr) {                                                     \
+                char *colon;                                            \
+                if ((colon = strchr(name, ':')) != NULL) {              \
+                        colon++;                                        \
+                        if (*colon != '\0' && *colon != '.')            \
+                                addr = *(kprobe_opcode_t **)addr;       \
+                } else if (name[0] != '.')                              \
+                        addr = *(kprobe_opcode_t **)addr;               \
+        } else {                                                        \
+                char dot_name[KSYM_NAME_LEN];                           \
+                dot_name[0] = '.';                                      \
+                dot_name[1] = '\0';                                     \
+                strncat(dot_name, name, KSYM_NAME_LEN - 2);             \
+                addr = (kprobe_opcode_t *)kallsyms_lookup_name(dot_name); \
+        }                                                               \
+}
+
+#define is_trap(instr)  (IS_TW(instr) || IS_TD(instr) || \
+                        IS_TWI(instr) || IS_TDI(instr))
+#else
+/* Use stock kprobe_lookup_name since ppc32 doesn't use function descriptors */
+#define is_trap(instr)  (IS_TW(instr) || IS_TWI(instr))
+#endif
+
+#define flush_insn_slot(p)      do { } while (0)
+#define kretprobe_blacklist_size 0
+
+void kretprobe_trampoline(void);
+extern void arch_remove_kprobe(struct kprobe *p);
+
+/* Architecture specific copy of original instruction */
+struct arch_specific_insn {
+        /* copy of original instruction */
+        kprobe_opcode_t *insn;
+        /*
+         * Set in kprobes code, initially to 0. If the instruction can be
+         * eumulated, this is set to 1, if not, to -1.
+         */
+        int boostable;
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+        unsigned long saved_msr;
+};
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long kprobe_saved_msr;
+        struct pt_regs jprobe_saved_regs;
+        struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                        unsigned long val, void *data);
+extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_KPROBES_H */
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
new file mode 100644
index 000000000000..f993e4198d5c
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm.h
@@ -0,0 +1,55 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright IBM Corp. 2007
+ *
+ * Authors: Hollis Blanchard <hollisb@us.ibm.com>
+ */
+
+#ifndef __LINUX_KVM_POWERPC_H
+#define __LINUX_KVM_POWERPC_H
+
+#include <asm/types.h>
+
+struct kvm_regs {
+        __u64 pc;
+        __u64 cr;
+        __u64 ctr;
+        __u64 lr;
+        __u64 xer;
+        __u64 msr;
+        __u64 srr0;
+        __u64 srr1;
+        __u64 pid;
+
+        __u64 sprg0;
+        __u64 sprg1;
+        __u64 sprg2;
+        __u64 sprg3;
+        __u64 sprg4;
+        __u64 sprg5;
+        __u64 sprg6;
+        __u64 sprg7;
+
+        __u64 gpr[32];
+};
+
+struct kvm_sregs {
+};
+
+struct kvm_fpu {
+        __u64 fpr[32];
+};
+
+#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
new file mode 100644
index 000000000000..2197764796d9
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -0,0 +1,55 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * Authors: Hollis Blanchard <hollisb@us.ibm.com>
+ */
+
+#ifndef __POWERPC_KVM_ASM_H__
+#define __POWERPC_KVM_ASM_H__
+
+/* IVPR must be 64KiB-aligned. */
+#define VCPU_SIZE_ORDER 4
+#define VCPU_SIZE_LOG   (VCPU_SIZE_ORDER + 12)
+#define VCPU_TLB_PGSZ   PPC44x_TLB_64K
+#define VCPU_SIZE_BYTES (1<<VCPU_SIZE_LOG)
+
+#define BOOKE_INTERRUPT_CRITICAL 0
+#define BOOKE_INTERRUPT_MACHINE_CHECK 1
+#define BOOKE_INTERRUPT_DATA_STORAGE 2
+#define BOOKE_INTERRUPT_INST_STORAGE 3
+#define BOOKE_INTERRUPT_EXTERNAL 4
+#define BOOKE_INTERRUPT_ALIGNMENT 5
+#define BOOKE_INTERRUPT_PROGRAM 6
+#define BOOKE_INTERRUPT_FP_UNAVAIL 7
+#define BOOKE_INTERRUPT_SYSCALL 8
+#define BOOKE_INTERRUPT_AP_UNAVAIL 9
+#define BOOKE_INTERRUPT_DECREMENTER 10
+#define BOOKE_INTERRUPT_FIT 11
+#define BOOKE_INTERRUPT_WATCHDOG 12
+#define BOOKE_INTERRUPT_DTLB_MISS 13
+#define BOOKE_INTERRUPT_ITLB_MISS 14
+#define BOOKE_INTERRUPT_DEBUG 15
+#define BOOKE_MAX_INTERRUPT 15
+
+#define RESUME_FLAG_NV          (1<<0)  /* Reload guest nonvolatile state? */
+#define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
+
+#define RESUME_GUEST            0
+#define RESUME_GUEST_NV         RESUME_FLAG_NV
+#define RESUME_HOST             RESUME_FLAG_HOST
+#define RESUME_HOST_NV          (RESUME_FLAG_HOST|RESUME_FLAG_NV)
+
+#endif /* __POWERPC_KVM_ASM_H__ */
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
new file mode 100644
index 000000000000..2655e2a4831e
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -0,0 +1,155 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright IBM Corp. 2007
+ *
+ * Authors: Hollis Blanchard <hollisb@us.ibm.com>
+ */
+
+#ifndef __POWERPC_KVM_HOST_H__
+#define __POWERPC_KVM_HOST_H__
+
+#include <linux/mutex.h>
+#include <linux/timer.h>
+#include <linux/types.h>
+#include <linux/kvm_types.h>
+#include <asm/kvm_asm.h>
+
+#define KVM_MAX_VCPUS 1
+#define KVM_MEMORY_SLOTS 32
+/* memory slots that does not exposed to userspace */
+#define KVM_PRIVATE_MEM_SLOTS 4
+
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+/* We don't currently support large pages. */
+#define KVM_PAGES_PER_HPAGE (1<<31)
+
+struct kvm;
+struct kvm_run;
+struct kvm_vcpu;
+
+struct kvm_vm_stat {
+        u32 remote_tlb_flush;
+};
+
+struct kvm_vcpu_stat {
+        u32 sum_exits;
+        u32 mmio_exits;
+        u32 dcr_exits;
+        u32 signal_exits;
+        u32 light_exits;
+        /* Account for special types of light exits: */
+        u32 itlb_real_miss_exits;
+        u32 itlb_virt_miss_exits;
+        u32 dtlb_real_miss_exits;
+        u32 dtlb_virt_miss_exits;
+        u32 syscall_exits;
+        u32 isi_exits;
+        u32 dsi_exits;
+        u32 emulated_inst_exits;
+        u32 dec_exits;
+        u32 ext_intr_exits;
+        u32 halt_wakeup;
+};
+
+struct tlbe {
+        u32 tid; /* Only the low 8 bits are used. */
+        u32 word0;
+        u32 word1;
+        u32 word2;
+};
+
+struct kvm_arch {
+};
+
+struct kvm_vcpu_arch {
+        /* Unmodified copy of the guest's TLB. */
+        struct tlbe guest_tlb[PPC44x_TLB_SIZE];
+        /* TLB that's actually used when the guest is running. */
+        struct tlbe shadow_tlb[PPC44x_TLB_SIZE];
+        /* Pages which are referenced in the shadow TLB. */
+        struct page *shadow_pages[PPC44x_TLB_SIZE];
+        /* Copy of the host's TLB. */
+        struct tlbe host_tlb[PPC44x_TLB_SIZE];
+
+        u32 host_stack;
+        u32 host_pid;
+
+        u64 fpr[32];
+        u32 gpr[32];
+
+        u32 pc;
+        u32 cr;
+        u32 ctr;
+        u32 lr;
+        u32 xer;
+
+        u32 msr;
+        u32 mmucr;
+        u32 sprg0;
+        u32 sprg1;
+        u32 sprg2;
+        u32 sprg3;
+        u32 sprg4;
+        u32 sprg5;
+        u32 sprg6;
+        u32 sprg7;
+        u32 srr0;
+        u32 srr1;
+        u32 csrr0;
+        u32 csrr1;
+        u32 dsrr0;
+        u32 dsrr1;
+        u32 dear;
+        u32 esr;
+        u32 dec;
+        u32 decar;
+        u32 tbl;
+        u32 tbu;
+        u32 tcr;
+        u32 tsr;
+        u32 ivor[16];
+        u32 ivpr;
+        u32 pir;
+        u32 pid;
+        u32 pvr;
+        u32 ccr0;
+        u32 ccr1;
+        u32 dbcr0;
+        u32 dbcr1;
+
+        u32 last_inst;
+        u32 fault_dear;
+        u32 fault_esr;
+        gpa_t paddr_accessed;
+
+        u8 io_gpr; /* GPR used as IO source/target */
+        u8 mmio_is_bigendian;
+        u8 dcr_needed;
+        u8 dcr_is_write;
+
+        u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
+
+        struct timer_list dec_timer;
+        unsigned long pending_exceptions;
+};
+
+struct kvm_guest_debug {
+        int enabled;
+        unsigned long bp[4];
+        int singlestep;
+};
+
+#endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_para.h b/arch/powerpc/include/asm/kvm_para.h
new file mode 100644
index 000000000000..2d48f6a63d0b
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_para.h
@@ -0,0 +1,37 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * Authors: Hollis Blanchard <hollisb@us.ibm.com>
+ */
+
+#ifndef __POWERPC_KVM_PARA_H__
+#define __POWERPC_KVM_PARA_H__
+
+#ifdef __KERNEL__
+
+static inline int kvm_para_available(void)
+{
+        return 0;
+}
+
+static inline unsigned int kvm_arch_para_features(void)
+{
+        return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* __POWERPC_KVM_PARA_H__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
new file mode 100644
index 000000000000..a8b068792260
--- /dev/null
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -0,0 +1,95 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * Authors: Hollis Blanchard <hollisb@us.ibm.com>
+ */
+
+#ifndef __POWERPC_KVM_PPC_H__
+#define __POWERPC_KVM_PPC_H__
+
+/* This file exists just so we can dereference kvm_vcpu, avoiding nested header
+ * dependencies. */
+
+#include <linux/mutex.h>
+#include <linux/timer.h>
+#include <linux/types.h>
+#include <linux/kvm_types.h>
+#include <linux/kvm_host.h>
+
+struct kvm_tlb {
+        struct tlbe guest_tlb[PPC44x_TLB_SIZE];
+        struct tlbe shadow_tlb[PPC44x_TLB_SIZE];
+};
+
+enum emulation_result {
+        EMULATE_DONE,         /* no further processing */
+        EMULATE_DO_MMIO,      /* kvm_run filled with MMIO request */
+        EMULATE_DO_DCR,       /* kvm_run filled with DCR request */
+        EMULATE_FAIL,         /* can't emulate this instruction */
+};
+
+extern const unsigned char exception_priority[];
+extern const unsigned char priority_exception[];
+
+extern int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
+extern char kvmppc_handlers_start[];
+extern unsigned long kvmppc_handler_len;
+
+extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu);
+extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
+                              unsigned int rt, unsigned int bytes,
+                              int is_bigendian);
+extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
+                               u32 val, unsigned int bytes, int is_bigendian);
+
+extern int kvmppc_emulate_instruction(struct kvm_run *run,
+                                      struct kvm_vcpu *vcpu);
+extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
+
+extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn,
+                           u64 asid, u32 flags);
+extern void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
+                                  gva_t eend, u32 asid);
+extern void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode);
+
+extern void kvmppc_check_and_deliver_interrupts(struct kvm_vcpu *vcpu);
+
+static inline void kvmppc_queue_exception(struct kvm_vcpu *vcpu, int exception)
+{
+        unsigned int priority = exception_priority[exception];
+        set_bit(priority, &vcpu->arch.pending_exceptions);
+}
+
+static inline void kvmppc_clear_exception(struct kvm_vcpu *vcpu, int exception)
+{
+        unsigned int priority = exception_priority[exception];
+        clear_bit(priority, &vcpu->arch.pending_exceptions);
+}
+
+/* Helper function for "full" MSR writes. No need to call this if only EE is
+ * changing. */
+static inline void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
+{
+        if ((new_msr & MSR_PR) != (vcpu->arch.msr & MSR_PR))
+                kvmppc_mmu_priv_switch(vcpu, new_msr & MSR_PR);
+
+        vcpu->arch.msr = new_msr;
+
+        if (vcpu->arch.msr & MSR_WE)
+                kvm_vcpu_block(vcpu);
+}
+
+#endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/arch/powerpc/include/asm/libata-portmap.h b/arch/powerpc/include/asm/libata-portmap.h
new file mode 100644
index 000000000000..4d8518049f4d
--- /dev/null
+++ b/arch/powerpc/include/asm/libata-portmap.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_POWERPC_LIBATA_PORTMAP_H
+#define __ASM_POWERPC_LIBATA_PORTMAP_H
+
+#define ATA_PRIMARY_CMD 0x1F0
+#define ATA_PRIMARY_CTL 0x3F6
+#define ATA_PRIMARY_IRQ(dev)    pci_get_legacy_ide_irq(dev, 0)
+
+#define ATA_SECONDARY_CMD       0x170
+#define ATA_SECONDARY_CTL       0x376
+#define ATA_SECONDARY_IRQ(dev)  pci_get_legacy_ide_irq(dev, 1)
+
+#endif
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
new file mode 100644
index 000000000000..e1c4ac1cc4ba
--- /dev/null
+++ b/arch/powerpc/include/asm/linkage.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_POWERPC_LINKAGE_H
+#define _ASM_POWERPC_LINKAGE_H
+
+/* Nothing to see here... */
+
+#endif  /* _ASM_POWERPC_LINKAGE_H */
diff --git a/arch/powerpc/include/asm/lmb.h b/arch/powerpc/include/asm/lmb.h
new file mode 100644
index 000000000000..6f5fdf0a19ae
--- /dev/null
+++ b/arch/powerpc/include/asm/lmb.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_POWERPC_LMB_H
+#define _ASM_POWERPC_LMB_H
+
+#include <asm/udbg.h>
+
+#define LMB_DBG(fmt...) udbg_printf(fmt)
+
+#ifdef CONFIG_PPC32
+extern phys_addr_t lowmem_end_addr;
+#define LMB_REAL_LIMIT  lowmem_end_addr
+#else
+#define LMB_REAL_LIMIT  0
+#endif
+
+#endif /* _ASM_POWERPC_LMB_H */
diff --git a/arch/powerpc/include/asm/local.h b/arch/powerpc/include/asm/local.h
new file mode 100644
index 000000000000..612d83276653
--- /dev/null
+++ b/arch/powerpc/include/asm/local.h
@@ -0,0 +1,200 @@
+#ifndef _ARCH_POWERPC_LOCAL_H
+#define _ARCH_POWERPC_LOCAL_H
+
+#include <linux/percpu.h>
+#include <asm/atomic.h>
+
+typedef struct
+{
+        atomic_long_t a;
+} local_t;
+
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
+
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l,i)  atomic_long_set(&(l)->a, (i))
+
+#define local_add(i,l)  atomic_long_add((i),(&(l)->a))
+#define local_sub(i,l)  atomic_long_sub((i),(&(l)->a))
+#define local_inc(l)    atomic_long_inc(&(l)->a)
+#define local_dec(l)    atomic_long_dec(&(l)->a)
+
+static __inline__ long local_add_return(long a, local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%2                # local_add_return\n\
+        add     %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+        PPC_STLCX       "%0,0,%2 \n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (a), "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+#define local_add_negative(a, l)        (local_add_return((a), (l)) < 0)
+
+static __inline__ long local_sub_return(long a, local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%2                # local_sub_return\n\
+        subf    %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+        PPC_STLCX       "%0,0,%2 \n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (a), "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+static __inline__ long local_inc_return(local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%1                # local_inc_return\n\
+        addic   %0,%0,1\n"
+        PPC405_ERR77(0,%1)
+        PPC_STLCX       "%0,0,%1 \n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+/*
+ * local_inc_and_test - increment and test
+ * @l: pointer of type local_t
+ *
+ * Atomically increments @l by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_inc_and_test(l) (local_inc_return(l) == 0)
+
+static __inline__ long local_dec_return(local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%1                # local_dec_return\n\
+        addic   %0,%0,-1\n"
+        PPC405_ERR77(0,%1)
+        PPC_STLCX       "%0,0,%1\n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+#define local_cmpxchg(l, o, n) \
+        (cmpxchg_local(&((l)->a.counter), (o), (n)))
+#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+
+/**
+ * local_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+static __inline__ int local_add_unless(local_t *l, long a, long u)
+{
+        long t;
+
+        __asm__ __volatile__ (
+"1:"    PPC_LLARX       "%0,0,%1                # local_add_unless\n\
+        cmpw    0,%0,%3 \n\
+        beq-    2f \n\
+        add     %0,%2,%0 \n"
+        PPC405_ERR77(0,%2)
+        PPC_STLCX       "%0,0,%1 \n\
+        bne-    1b \n"
+"       subf    %0,%2,%0 \n\
+2:"
+        : "=&r" (t)
+        : "r" (&(l->a.counter)), "r" (a), "r" (u)
+        : "cc", "memory");
+
+        return t != u;
+}
+
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
+#define local_sub_and_test(a, l)        (local_sub_return((a), (l)) == 0)
+#define local_dec_and_test(l)           (local_dec_return((l)) == 0)
+
+/*
+ * Atomically test *l and decrement if it is greater than 0.
+ * The function returns the old value of *l minus 1.
+ */
+static __inline__ long local_dec_if_positive(local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%1                # local_dec_if_positive\n\
+        cmpwi   %0,1\n\
+        addi    %0,%0,-1\n\
+        blt-    2f\n"
+        PPC405_ERR77(0,%1)
+        PPC_STLCX       "%0,0,%1\n\
+        bne-    1b"
+        "\n\
+2:"     : "=&b" (t)
+        : "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+/* Use these for per-cpu local_t variables: on some archs they are
+ * much more efficient than these naive implementations.  Note they take
+ * a variable, not an address.
+ */
+
+#define __local_inc(l)          ((l)->a.counter++)
+#define __local_dec(l)          ((l)->a.counter++)
+#define __local_add(i,l)        ((l)->a.counter+=(i))
+#define __local_sub(i,l)        ((l)->a.counter-=(i))
+
+/* Need to disable preemption for the cpu local counters otherwise we could
+   still access a variable of a previous CPU in a non atomic way. */
+#define cpu_local_wrap_v(l)             \
+        ({ local_t res__;               \
+           preempt_disable();           \
+           res__ = (l);                 \
+           preempt_enable();            \
+           res__; })
+#define cpu_local_wrap(l)               \
+        ({ preempt_disable();           \
+           l;                           \
+           preempt_enable(); })         \
+
+#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
+#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
+#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var(l)))
+#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var(l)))
+#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
+#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
+
+#define __cpu_local_inc(l)      cpu_local_inc(l)
+#define __cpu_local_dec(l)      cpu_local_dec(l)
+#define __cpu_local_add(i, l)   cpu_local_add((i), (l))
+#define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
+
+#endif /* _ARCH_POWERPC_LOCAL_H */
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
new file mode 100644
index 000000000000..2fe268b10333
--- /dev/null
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -0,0 +1,159 @@
+/*
+ * lppaca.h
+ * Copyright (C) 2001  Mike Corrigan IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_LPPACA_H
+#define _ASM_POWERPC_LPPACA_H
+#ifdef __KERNEL__
+
+//=============================================================================
+//
+//      This control block contains the data that is shared between the
+//      hypervisor (PLIC) and the OS.
+//
+//
+//----------------------------------------------------------------------------
+#include <linux/cache.h>
+#include <asm/types.h>
+#include <asm/mmu.h>
+
+/* The Hypervisor barfs if the lppaca crosses a page boundary.  A 1k
+ * alignment is sufficient to prevent this */
+struct lppaca {
+//=============================================================================
+// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
+// NOTE: The xDynXyz fields are fields that will be dynamically changed by
+// PLIC when preparing to bring a processor online or when dispatching a
+// virtual processor!
+//=============================================================================
+        u32     desc;                   // Eye catcher 0xD397D781       x00-x03
+        u16     size;                   // Size of this struct          x04-x05
+        u16     reserved1;              // Reserved                     x06-x07
+        u16     reserved2:14;           // Reserved                     x08-x09
+        u8      shared_proc:1;          // Shared processor indicator   ...
+        u8      secondary_thread:1;     // Secondary thread indicator   ...
+        volatile u8 dyn_proc_status:8;  // Dynamic Status of this proc  x0A-x0A
+        u8      secondary_thread_count; // Secondary thread count       x0B-x0B
+        volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
+        volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
+        u32     decr_val;               // Value for Decr programming   x10-x13
+        u32     pmc_val;                // Value for PMC regs           x14-x17
+        volatile u32 dyn_hw_node_id;    // Dynamic Hardware Node id     x18-x1B
+        volatile u32 dyn_hw_proc_id;    // Dynamic Hardware Proc Id     x1C-x1F
+        volatile u32 dyn_pir;           // Dynamic ProcIdReg value      x20-x23
+        u32     dsei_data;              // DSEI data                    x24-x27
+        u64     sprg3;                  // SPRG3 value                  x28-x2F
+        u8      reserved3[80];          // Reserved                     x30-x7F
+
+//=============================================================================
+// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
+//=============================================================================
+        // This Dword contains a byte for each type of interrupt that can occur.
+        // The IPI is a count while the others are just a binary 1 or 0.
+        union {
+                u64     any_int;
+                struct {
+                        u16     reserved;       // Reserved - cleared by #mpasmbl
+                        u8      xirr_int;       // Indicates xXirrValue is valid or Immed IO
+                        u8      ipi_cnt;        // IPI Count
+                        u8      decr_int;       // DECR interrupt occurred
+                        u8      pdc_int;        // PDC interrupt occurred
+                        u8      quantum_int;    // Interrupt quantum reached
+                        u8      old_plic_deferred_ext_int;      // Old PLIC has a deferred XIRR pending
+                } fields;
+        } int_dword;
+
+        // Whenever any fields in this Dword are set then PLIC will defer the
+        // processing of external interrupts.  Note that PLIC will store the
+        // XIRR directly into the xXirrValue field so that another XIRR will
+        // not be presented until this one clears.  The layout of the low
+        // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
+        // entire Dword is zero or not.  A non-zero value in the low order
+        // 2-bytes will result in SLIC being granted the highest thread
+        // priority upon return.  A 0 will return to SLIC as medium priority.
+        u64     plic_defer_ints_area;   // Entire Dword
+
+        // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
+        // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
+        u64     saved_srr0;             // Saved SRR0                   x10-x17
+        u64     saved_srr1;             // Saved SRR1                   x18-x1F
+
+        // Used to pass parms from the OS to PLIC for SetAsrAndRfid
+        u64     saved_gpr3;             // Saved GPR3                   x20-x27
+        u64     saved_gpr4;             // Saved GPR4                   x28-x2F
+        u64     saved_gpr5;             // Saved GPR5                   x30-x37
+
+        u8      reserved4;              // Reserved                     x38-x38
+        u8      donate_dedicated_cpu;   // Donate dedicated CPU cycles  x39-x39
+        u8      fpregs_in_use;          // FP regs in use               x3A-x3A
+        u8      pmcregs_in_use;         // PMC regs in use              x3B-x3B
+        volatile u32 saved_decr;        // Saved Decr Value             x3C-x3F
+        volatile u64 emulated_time_base;// Emulated TB for this thread  x40-x47
+        volatile u64 cur_plic_latency;  // Unaccounted PLIC latency     x48-x4F
+        u64     tot_plic_latency;       // Accumulated PLIC latency     x50-x57
+        u64     wait_state_cycles;      // Wait cycles for this proc    x58-x5F
+        u64     end_of_quantum;         // TB at end of quantum         x60-x67
+        u64     pdc_saved_sprg1;        // Saved SPRG1 for PMC int      x68-x6F
+        u64     pdc_saved_srr0;         // Saved SRR0 for PMC int       x70-x77
+        volatile u32 virtual_decr;      // Virtual DECR for shared procsx78-x7B
+        u16     slb_count;              // # of SLBs to maintain        x7C-x7D
+        u8      idle;                   // Indicate OS is idle          x7E
+        u8      vmxregs_in_use;         // VMX registers in use         x7F
+
+
+//=============================================================================
+// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
+//=============================================================================
+        // This is the yield_count.  An "odd" value (low bit on) means that
+        // the processor is yielded (either because of an OS yield or a PLIC
+        // preempt).  An even value implies that the processor is currently
+        // executing.
+        // NOTE: This value will ALWAYS be zero for dedicated processors and
+        // will NEVER be zero for shared processors (ie, initialized to a 1).
+        volatile u32 yield_count;       // PLIC increments each dispatchx00-x03
+        u32 reserved6;
+        volatile u64 cmo_faults;        // CMO page fault count         x08-x0F
+        volatile u64 cmo_fault_time;    // CMO page fault time          x10-x17
+        u8      reserved7[104];         // Reserved                     x18-x7F
+
+//=============================================================================
+// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
+//=============================================================================
+        u8      pmc_save_area[256];     // PMC interrupt Area           x00-xFF
+} __attribute__((__aligned__(0x400)));
+
+extern struct lppaca lppaca[];
+
+/*
+ * SLB shadow buffer structure as defined in the PAPR.  The save_area
+ * contains adjacent ESID and VSID pairs for each shadowed SLB.  The
+ * ESID is stored in the lower 64bits, then the VSID.
+ */
+struct slb_shadow {
+        u32     persistent;             // Number of persistent SLBs    x00-x03
+        u32     buffer_length;          // Total shadow buffer length   x04-x07
+        u64     reserved;               // Alignment                    x08-x0f
+        struct  {
+                u64     esid;
+                u64     vsid;
+        } save_area[SLB_NUM_BOLTED];    //                              x10-x40
+} ____cacheline_aligned;
+
+extern struct slb_shadow slb_shadow[];
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/arch/powerpc/include/asm/lv1call.h b/arch/powerpc/include/asm/lv1call.h
new file mode 100644
index 000000000000..81713acf7529
--- /dev/null
+++ b/arch/powerpc/include/asm/lv1call.h
@@ -0,0 +1,348 @@
+/*
+ *  PS3 hvcall interface.
+ *
+ *  Copyright (C) 2006 Sony Computer Entertainment Inc.
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2003, 2004 (c) MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#if !defined(_ASM_POWERPC_LV1CALL_H)
+#define _ASM_POWERPC_LV1CALL_H
+
+#if !defined(__ASSEMBLY__)
+
+#include <linux/types.h>
+
+/* lv1 call declaration macros */
+
+#define LV1_1_IN_ARG_DECL u64 in_1
+#define LV1_2_IN_ARG_DECL LV1_1_IN_ARG_DECL, u64 in_2
+#define LV1_3_IN_ARG_DECL LV1_2_IN_ARG_DECL, u64 in_3
+#define LV1_4_IN_ARG_DECL LV1_3_IN_ARG_DECL, u64 in_4
+#define LV1_5_IN_ARG_DECL LV1_4_IN_ARG_DECL, u64 in_5
+#define LV1_6_IN_ARG_DECL LV1_5_IN_ARG_DECL, u64 in_6
+#define LV1_7_IN_ARG_DECL LV1_6_IN_ARG_DECL, u64 in_7
+#define LV1_8_IN_ARG_DECL LV1_7_IN_ARG_DECL, u64 in_8
+#define LV1_1_OUT_ARG_DECL u64 *out_1
+#define LV1_2_OUT_ARG_DECL LV1_1_OUT_ARG_DECL, u64 *out_2
+#define LV1_3_OUT_ARG_DECL LV1_2_OUT_ARG_DECL, u64 *out_3
+#define LV1_4_OUT_ARG_DECL LV1_3_OUT_ARG_DECL, u64 *out_4
+#define LV1_5_OUT_ARG_DECL LV1_4_OUT_ARG_DECL, u64 *out_5
+#define LV1_6_OUT_ARG_DECL LV1_5_OUT_ARG_DECL, u64 *out_6
+#define LV1_7_OUT_ARG_DECL LV1_6_OUT_ARG_DECL, u64 *out_7
+
+#define LV1_0_IN_0_OUT_ARG_DECL void
+#define LV1_1_IN_0_OUT_ARG_DECL LV1_1_IN_ARG_DECL
+#define LV1_2_IN_0_OUT_ARG_DECL LV1_2_IN_ARG_DECL
+#define LV1_3_IN_0_OUT_ARG_DECL LV1_3_IN_ARG_DECL
+#define LV1_4_IN_0_OUT_ARG_DECL LV1_4_IN_ARG_DECL
+#define LV1_5_IN_0_OUT_ARG_DECL LV1_5_IN_ARG_DECL
+#define LV1_6_IN_0_OUT_ARG_DECL LV1_6_IN_ARG_DECL
+#define LV1_7_IN_0_OUT_ARG_DECL LV1_7_IN_ARG_DECL
+
+#define LV1_0_IN_1_OUT_ARG_DECL                    LV1_1_OUT_ARG_DECL
+#define LV1_1_IN_1_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_2_IN_1_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_3_IN_1_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_4_IN_1_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_5_IN_1_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_6_IN_1_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_7_IN_1_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+#define LV1_8_IN_1_OUT_ARG_DECL LV1_8_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
+
+#define LV1_0_IN_2_OUT_ARG_DECL                    LV1_2_OUT_ARG_DECL
+#define LV1_1_IN_2_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_2_IN_2_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_3_IN_2_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_4_IN_2_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_5_IN_2_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_6_IN_2_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+#define LV1_7_IN_2_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
+
+#define LV1_0_IN_3_OUT_ARG_DECL                    LV1_3_OUT_ARG_DECL
+#define LV1_1_IN_3_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_2_IN_3_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_3_IN_3_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_4_IN_3_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_5_IN_3_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_6_IN_3_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+#define LV1_7_IN_3_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
+
+#define LV1_0_IN_4_OUT_ARG_DECL                    LV1_4_OUT_ARG_DECL
+#define LV1_1_IN_4_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_2_IN_4_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_3_IN_4_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_4_IN_4_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_5_IN_4_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_6_IN_4_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+#define LV1_7_IN_4_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
+
+#define LV1_0_IN_5_OUT_ARG_DECL                    LV1_5_OUT_ARG_DECL
+#define LV1_1_IN_5_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_2_IN_5_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_3_IN_5_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_4_IN_5_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_5_IN_5_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_6_IN_5_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+#define LV1_7_IN_5_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
+
+#define LV1_0_IN_6_OUT_ARG_DECL                    LV1_6_OUT_ARG_DECL
+#define LV1_1_IN_6_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_2_IN_6_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_3_IN_6_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_4_IN_6_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_5_IN_6_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_6_IN_6_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+#define LV1_7_IN_6_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
+
+#define LV1_0_IN_7_OUT_ARG_DECL                    LV1_7_OUT_ARG_DECL
+#define LV1_1_IN_7_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_2_IN_7_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_3_IN_7_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_4_IN_7_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_5_IN_7_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_6_IN_7_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+#define LV1_7_IN_7_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
+
+#define LV1_1_IN_ARGS in_1
+#define LV1_2_IN_ARGS LV1_1_IN_ARGS, in_2
+#define LV1_3_IN_ARGS LV1_2_IN_ARGS, in_3
+#define LV1_4_IN_ARGS LV1_3_IN_ARGS, in_4
+#define LV1_5_IN_ARGS LV1_4_IN_ARGS, in_5
+#define LV1_6_IN_ARGS LV1_5_IN_ARGS, in_6
+#define LV1_7_IN_ARGS LV1_6_IN_ARGS, in_7
+#define LV1_8_IN_ARGS LV1_7_IN_ARGS, in_8
+
+#define LV1_1_OUT_ARGS out_1
+#define LV1_2_OUT_ARGS LV1_1_OUT_ARGS, out_2
+#define LV1_3_OUT_ARGS LV1_2_OUT_ARGS, out_3
+#define LV1_4_OUT_ARGS LV1_3_OUT_ARGS, out_4
+#define LV1_5_OUT_ARGS LV1_4_OUT_ARGS, out_5
+#define LV1_6_OUT_ARGS LV1_5_OUT_ARGS, out_6
+#define LV1_7_OUT_ARGS LV1_6_OUT_ARGS, out_7
+
+#define LV1_0_IN_0_OUT_ARGS
+#define LV1_1_IN_0_OUT_ARGS LV1_1_IN_ARGS
+#define LV1_2_IN_0_OUT_ARGS LV1_2_IN_ARGS
+#define LV1_3_IN_0_OUT_ARGS LV1_3_IN_ARGS
+#define LV1_4_IN_0_OUT_ARGS LV1_4_IN_ARGS
+#define LV1_5_IN_0_OUT_ARGS LV1_5_IN_ARGS
+#define LV1_6_IN_0_OUT_ARGS LV1_6_IN_ARGS
+#define LV1_7_IN_0_OUT_ARGS LV1_7_IN_ARGS
+
+#define LV1_0_IN_1_OUT_ARGS                LV1_1_OUT_ARGS
+#define LV1_1_IN_1_OUT_ARGS LV1_1_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_2_IN_1_OUT_ARGS LV1_2_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_3_IN_1_OUT_ARGS LV1_3_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_4_IN_1_OUT_ARGS LV1_4_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_5_IN_1_OUT_ARGS LV1_5_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_6_IN_1_OUT_ARGS LV1_6_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_7_IN_1_OUT_ARGS LV1_7_IN_ARGS, LV1_1_OUT_ARGS
+#define LV1_8_IN_1_OUT_ARGS LV1_8_IN_ARGS, LV1_1_OUT_ARGS
+
+#define LV1_0_IN_2_OUT_ARGS                LV1_2_OUT_ARGS
+#define LV1_1_IN_2_OUT_ARGS LV1_1_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_2_IN_2_OUT_ARGS LV1_2_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_3_IN_2_OUT_ARGS LV1_3_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_4_IN_2_OUT_ARGS LV1_4_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_5_IN_2_OUT_ARGS LV1_5_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_6_IN_2_OUT_ARGS LV1_6_IN_ARGS, LV1_2_OUT_ARGS
+#define LV1_7_IN_2_OUT_ARGS LV1_7_IN_ARGS, LV1_2_OUT_ARGS
+
+#define LV1_0_IN_3_OUT_ARGS                LV1_3_OUT_ARGS
+#define LV1_1_IN_3_OUT_ARGS LV1_1_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_2_IN_3_OUT_ARGS LV1_2_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_3_IN_3_OUT_ARGS LV1_3_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_4_IN_3_OUT_ARGS LV1_4_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_5_IN_3_OUT_ARGS LV1_5_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_6_IN_3_OUT_ARGS LV1_6_IN_ARGS, LV1_3_OUT_ARGS
+#define LV1_7_IN_3_OUT_ARGS LV1_7_IN_ARGS, LV1_3_OUT_ARGS
+
+#define LV1_0_IN_4_OUT_ARGS                LV1_4_OUT_ARGS
+#define LV1_1_IN_4_OUT_ARGS LV1_1_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_2_IN_4_OUT_ARGS LV1_2_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_3_IN_4_OUT_ARGS LV1_3_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_4_IN_4_OUT_ARGS LV1_4_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_5_IN_4_OUT_ARGS LV1_5_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_6_IN_4_OUT_ARGS LV1_6_IN_ARGS, LV1_4_OUT_ARGS
+#define LV1_7_IN_4_OUT_ARGS LV1_7_IN_ARGS, LV1_4_OUT_ARGS
+
+#define LV1_0_IN_5_OUT_ARGS                LV1_5_OUT_ARGS
+#define LV1_1_IN_5_OUT_ARGS LV1_1_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_2_IN_5_OUT_ARGS LV1_2_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_3_IN_5_OUT_ARGS LV1_3_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_4_IN_5_OUT_ARGS LV1_4_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_5_IN_5_OUT_ARGS LV1_5_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_6_IN_5_OUT_ARGS LV1_6_IN_ARGS, LV1_5_OUT_ARGS
+#define LV1_7_IN_5_OUT_ARGS LV1_7_IN_ARGS, LV1_5_OUT_ARGS
+
+#define LV1_0_IN_6_OUT_ARGS                LV1_6_OUT_ARGS
+#define LV1_1_IN_6_OUT_ARGS LV1_1_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_2_IN_6_OUT_ARGS LV1_2_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_3_IN_6_OUT_ARGS LV1_3_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_4_IN_6_OUT_ARGS LV1_4_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_5_IN_6_OUT_ARGS LV1_5_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_6_IN_6_OUT_ARGS LV1_6_IN_ARGS, LV1_6_OUT_ARGS
+#define LV1_7_IN_6_OUT_ARGS LV1_7_IN_ARGS, LV1_6_OUT_ARGS
+
+#define LV1_0_IN_7_OUT_ARGS                LV1_7_OUT_ARGS
+#define LV1_1_IN_7_OUT_ARGS LV1_1_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_2_IN_7_OUT_ARGS LV1_2_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_3_IN_7_OUT_ARGS LV1_3_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_4_IN_7_OUT_ARGS LV1_4_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_5_IN_7_OUT_ARGS LV1_5_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_6_IN_7_OUT_ARGS LV1_6_IN_ARGS, LV1_7_OUT_ARGS
+#define LV1_7_IN_7_OUT_ARGS LV1_7_IN_ARGS, LV1_7_OUT_ARGS
+
+/*
+ * This LV1_CALL() macro is for use by callers.  It expands into an
+ * inline call wrapper and an underscored HV call declaration.  The
+ * wrapper can be used to instrument the lv1 call interface.  The
+ * file lv1call.S defines its own LV1_CALL() macro to expand into
+ * the actual underscored call definition.
+ */
+
+#if !defined(LV1_CALL)
+#define LV1_CALL(name, in, out, num)                               \
+  extern s64 _lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL);      \
+  static inline int lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL) \
+    {return _lv1_##name(LV1_##in##_IN_##out##_OUT_ARGS);}
+#endif
+
+#endif /* !defined(__ASSEMBLY__) */
+
+/* lv1 call table */
+
+LV1_CALL(allocate_memory,                               4, 2,   0 )
+LV1_CALL(write_htab_entry,                              4, 0,   1 )
+LV1_CALL(construct_virtual_address_space,               3, 2,   2 )
+LV1_CALL(invalidate_htab_entries,                       5, 0,   3 )
+LV1_CALL(get_virtual_address_space_id_of_ppe,           1, 1,   4 )
+LV1_CALL(query_logical_partition_address_region_info,   1, 5,   6 )
+LV1_CALL(select_virtual_address_space,                  1, 0,   7 )
+LV1_CALL(pause,                                         1, 0,   9 )
+LV1_CALL(destruct_virtual_address_space,                1, 0,  10 )
+LV1_CALL(configure_irq_state_bitmap,                    3, 0,  11 )
+LV1_CALL(connect_irq_plug_ext,                          5, 0,  12 )
+LV1_CALL(release_memory,                                1, 0,  13 )
+LV1_CALL(put_iopte,                                     5, 0,  15 )
+LV1_CALL(disconnect_irq_plug_ext,                       3, 0,  17 )
+LV1_CALL(construct_event_receive_port,                  0, 1,  18 )
+LV1_CALL(destruct_event_receive_port,                   1, 0,  19 )
+LV1_CALL(send_event_locally,                            1, 0,  24 )
+LV1_CALL(end_of_interrupt,                              1, 0,  27 )
+LV1_CALL(connect_irq_plug,                              2, 0,  28 )
+LV1_CALL(disconnect_irq_plug,                           1, 0,  29 )
+LV1_CALL(end_of_interrupt_ext,                          3, 0,  30 )
+LV1_CALL(did_update_interrupt_mask,                     2, 0,  31 )
+LV1_CALL(shutdown_logical_partition,                    1, 0,  44 )
+LV1_CALL(destruct_logical_spe,                          1, 0,  54 )
+LV1_CALL(construct_logical_spe,                         7, 6,  57 )
+LV1_CALL(set_spe_interrupt_mask,                        3, 0,  61 )
+LV1_CALL(set_spe_transition_notifier,                   3, 0,  64 )
+LV1_CALL(disable_logical_spe,                           2, 0,  65 )
+LV1_CALL(clear_spe_interrupt_status,                    4, 0,  66 )
+LV1_CALL(get_spe_interrupt_status,                      2, 1,  67 )
+LV1_CALL(get_logical_ppe_id,                            0, 1,  69 )
+LV1_CALL(set_interrupt_mask,                            5, 0,  73 )
+LV1_CALL(get_logical_partition_id,                      0, 1,  74 )
+LV1_CALL(configure_execution_time_variable,             1, 0,  77 )
+LV1_CALL(get_spe_irq_outlet,                            2, 1,  78 )
+LV1_CALL(set_spe_privilege_state_area_1_register,       3, 0,  79 )
+LV1_CALL(create_repository_node,                        6, 0,  90 )
+LV1_CALL(get_repository_node_value,                     5, 2,  91 )
+LV1_CALL(modify_repository_node_value,                  6, 0,  92 )
+LV1_CALL(remove_repository_node,                        4, 0,  93 )
+LV1_CALL(read_htab_entries,                             2, 5,  95 )
+LV1_CALL(set_dabr,                                      2, 0,  96 )
+LV1_CALL(get_total_execution_time,                      2, 1, 103 )
+LV1_CALL(allocate_io_segment,                           3, 1, 116 )
+LV1_CALL(release_io_segment,                            2, 0, 117 )
+LV1_CALL(construct_io_irq_outlet,                       1, 1, 120 )
+LV1_CALL(destruct_io_irq_outlet,                        1, 0, 121 )
+LV1_CALL(map_htab,                                      1, 1, 122 )
+LV1_CALL(unmap_htab,                                    1, 0, 123 )
+LV1_CALL(get_version_info,                              0, 1, 127 )
+LV1_CALL(insert_htab_entry,                             6, 3, 158 )
+LV1_CALL(read_virtual_uart,                             3, 1, 162 )
+LV1_CALL(write_virtual_uart,                            3, 1, 163 )
+LV1_CALL(set_virtual_uart_param,                        3, 0, 164 )
+LV1_CALL(get_virtual_uart_param,                        2, 1, 165 )
+LV1_CALL(configure_virtual_uart_irq,                    1, 1, 166 )
+LV1_CALL(open_device,                                   3, 0, 170 )
+LV1_CALL(close_device,                                  2, 0, 171 )
+LV1_CALL(map_device_mmio_region,                        5, 1, 172 )
+LV1_CALL(unmap_device_mmio_region,                      3, 0, 173 )
+LV1_CALL(allocate_device_dma_region,                    5, 1, 174 )
+LV1_CALL(free_device_dma_region,                        3, 0, 175 )
+LV1_CALL(map_device_dma_region,                         6, 0, 176 )
+LV1_CALL(unmap_device_dma_region,                       4, 0, 177 )
+LV1_CALL(net_add_multicast_address,                     4, 0, 185 )
+LV1_CALL(net_remove_multicast_address,                  4, 0, 186 )
+LV1_CALL(net_start_tx_dma,                              4, 0, 187 )
+LV1_CALL(net_stop_tx_dma,                               3, 0, 188 )
+LV1_CALL(net_start_rx_dma,                              4, 0, 189 )
+LV1_CALL(net_stop_rx_dma,                               3, 0, 190 )
+LV1_CALL(net_set_interrupt_status_indicator,            4, 0, 191 )
+LV1_CALL(net_set_interrupt_mask,                        4, 0, 193 )
+LV1_CALL(net_control,                                   6, 2, 194 )
+LV1_CALL(connect_interrupt_event_receive_port,          4, 0, 197 )
+LV1_CALL(disconnect_interrupt_event_receive_port,       4, 0, 198 )
+LV1_CALL(get_spe_all_interrupt_statuses,                1, 1, 199 )
+LV1_CALL(deconfigure_virtual_uart_irq,                  0, 0, 202 )
+LV1_CALL(enable_logical_spe,                            2, 0, 207 )
+LV1_CALL(gpu_open,                                      1, 0, 210 )
+LV1_CALL(gpu_close,                                     0, 0, 211 )
+LV1_CALL(gpu_device_map,                                1, 2, 212 )
+LV1_CALL(gpu_device_unmap,                              1, 0, 213 )
+LV1_CALL(gpu_memory_allocate,                           5, 2, 214 )
+LV1_CALL(gpu_memory_free,                               1, 0, 216 )
+LV1_CALL(gpu_context_allocate,                          2, 5, 217 )
+LV1_CALL(gpu_context_free,                              1, 0, 218 )
+LV1_CALL(gpu_context_iomap,                             5, 0, 221 )
+LV1_CALL(gpu_context_attribute,                         6, 0, 225 )
+LV1_CALL(gpu_context_intr,                              1, 1, 227 )
+LV1_CALL(gpu_attribute,                                 5, 0, 228 )
+LV1_CALL(get_rtc,                                       0, 2, 232 )
+LV1_CALL(set_ppe_periodic_tracer_frequency,             1, 0, 240 )
+LV1_CALL(start_ppe_periodic_tracer,                     5, 0, 241 )
+LV1_CALL(stop_ppe_periodic_tracer,                      1, 1, 242 )
+LV1_CALL(storage_read,                                  6, 1, 245 )
+LV1_CALL(storage_write,                                 6, 1, 246 )
+LV1_CALL(storage_send_device_command,                   6, 1, 248 )
+LV1_CALL(storage_get_async_status,                      1, 2, 249 )
+LV1_CALL(storage_check_async_status,                    2, 1, 254 )
+LV1_CALL(panic,                                         1, 0, 255 )
+LV1_CALL(construct_lpm,                                 6, 3, 140 )
+LV1_CALL(destruct_lpm,                                  1, 0, 141 )
+LV1_CALL(start_lpm,                                     1, 0, 142 )
+LV1_CALL(stop_lpm,                                      1, 1, 143 )
+LV1_CALL(copy_lpm_trace_buffer,                         3, 1, 144 )
+LV1_CALL(add_lpm_event_bookmark,                        5, 0, 145 )
+LV1_CALL(delete_lpm_event_bookmark,                     3, 0, 146 )
+LV1_CALL(set_lpm_interrupt_mask,                        3, 1, 147 )
+LV1_CALL(get_lpm_interrupt_status,                      1, 1, 148 )
+LV1_CALL(set_lpm_general_control,                       5, 2, 149 )
+LV1_CALL(set_lpm_interval,                              3, 1, 150 )
+LV1_CALL(set_lpm_trigger_control,                       3, 1, 151 )
+LV1_CALL(set_lpm_counter_control,                       4, 1, 152 )
+LV1_CALL(set_lpm_group_control,                         3, 1, 153 )
+LV1_CALL(set_lpm_debug_bus_control,                     3, 1, 154 )
+LV1_CALL(set_lpm_counter,                               5, 2, 155 )
+LV1_CALL(set_lpm_signal,                                7, 0, 156 )
+LV1_CALL(set_lpm_spr_trigger,                           2, 0, 157 )
+
+#endif
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
new file mode 100644
index 000000000000..893aafd87fde
--- /dev/null
+++ b/arch/powerpc/include/asm/machdep.h
@@ -0,0 +1,365 @@
+#ifndef _ASM_POWERPC_MACHDEP_H
+#define _ASM_POWERPC_MACHDEP_H
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/seq_file.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/setup.h>
+
+/* We export this macro for external modules like Alsa to know if
+ * ppc_md.feature_call is implemented or not
+ */
+#define CONFIG_PPC_HAS_FEATURE_CALLS
+
+struct pt_regs;
+struct pci_bus; 
+struct device_node;
+struct iommu_table;
+struct rtc_time;
+struct file;
+struct pci_controller;
+#ifdef CONFIG_KEXEC
+struct kimage;
+#endif
+
+#ifdef CONFIG_SMP
+struct smp_ops_t {
+        void  (*message_pass)(int target, int msg);
+        int   (*probe)(void);
+        void  (*kick_cpu)(int nr);
+        void  (*setup_cpu)(int nr);
+        void  (*take_timebase)(void);
+        void  (*give_timebase)(void);
+        int   (*cpu_enable)(unsigned int nr);
+        int   (*cpu_disable)(void);
+        void  (*cpu_die)(unsigned int nr);
+        int   (*cpu_bootable)(unsigned int nr);
+};
+#endif
+
+struct machdep_calls {
+        char            *name;
+#ifdef CONFIG_PPC64
+        void            (*hpte_invalidate)(unsigned long slot,
+                                           unsigned long va,
+                                           int psize, int ssize,
+                                           int local);
+        long            (*hpte_updatepp)(unsigned long slot, 
+                                         unsigned long newpp, 
+                                         unsigned long va,
+                                         int psize, int ssize,
+                                         int local);
+        void            (*hpte_updateboltedpp)(unsigned long newpp, 
+                                               unsigned long ea,
+                                               int psize, int ssize);
+        long            (*hpte_insert)(unsigned long hpte_group,
+                                       unsigned long va,
+                                       unsigned long prpn,
+                                       unsigned long rflags,
+                                       unsigned long vflags,
+                                       int psize, int ssize);
+        long            (*hpte_remove)(unsigned long hpte_group);
+        void            (*hpte_removebolted)(unsigned long ea,
+                                             int psize, int ssize);
+        void            (*flush_hash_range)(unsigned long number, int local);
+
+        /* special for kexec, to be called in real mode, linar mapping is
+         * destroyed as well */
+        void            (*hpte_clear_all)(void);
+
+        int             (*tce_build)(struct iommu_table *tbl,
+                                     long index,
+                                     long npages,
+                                     unsigned long uaddr,
+                                     enum dma_data_direction direction,
+                                     struct dma_attrs *attrs);
+        void            (*tce_free)(struct iommu_table *tbl,
+                                    long index,
+                                    long npages);
+        unsigned long   (*tce_get)(struct iommu_table *tbl,
+                                    long index);
+        void            (*tce_flush)(struct iommu_table *tbl);
+        void            (*pci_dma_dev_setup)(struct pci_dev *dev);
+        void            (*pci_dma_bus_setup)(struct pci_bus *bus);
+
+        void __iomem *  (*ioremap)(phys_addr_t addr, unsigned long size,
+                                   unsigned long flags);
+        void            (*iounmap)(volatile void __iomem *token);
+
+#ifdef CONFIG_PM
+        void            (*iommu_save)(void);
+        void            (*iommu_restore)(void);
+#endif
+#endif /* CONFIG_PPC64 */
+
+        int             (*probe)(void);
+        void            (*setup_arch)(void); /* Optional, may be NULL */
+        void            (*init_early)(void);
+        /* Optional, may be NULL. */
+        void            (*show_cpuinfo)(struct seq_file *m);
+        void            (*show_percpuinfo)(struct seq_file *m, int i);
+
+        void            (*init_IRQ)(void);
+        unsigned int    (*get_irq)(void);
+#ifdef CONFIG_KEXEC
+        void            (*kexec_cpu_down)(int crash_shutdown, int secondary);
+#endif
+
+        /* PCI stuff */
+        /* Called after scanning the bus, before allocating resources */
+        void            (*pcibios_fixup)(void);
+        int             (*pci_probe_mode)(struct pci_bus *);
+        void            (*pci_irq_fixup)(struct pci_dev *dev);
+
+        /* To setup PHBs when using automatic OF platform driver for PCI */
+        int             (*pci_setup_phb)(struct pci_controller *host);
+
+#ifdef CONFIG_PCI_MSI
+        int             (*msi_check_device)(struct pci_dev* dev,
+                                            int nvec, int type);
+        int             (*setup_msi_irqs)(struct pci_dev *dev,
+                                          int nvec, int type);
+        void            (*teardown_msi_irqs)(struct pci_dev *dev);
+#endif
+
+        void            (*restart)(char *cmd);
+        void            (*power_off)(void);
+        void            (*halt)(void);
+        void            (*panic)(char *str);
+        void            (*cpu_die)(void);
+
+        long            (*time_init)(void); /* Optional, may be NULL */
+
+        int             (*set_rtc_time)(struct rtc_time *);
+        void            (*get_rtc_time)(struct rtc_time *);
+        unsigned long   (*get_boot_time)(void);
+        unsigned char   (*rtc_read_val)(int addr);
+        void            (*rtc_write_val)(int addr, unsigned char val);
+
+        void            (*calibrate_decr)(void);
+
+        void            (*progress)(char *, unsigned short);
+
+        /* Interface for platform error logging */
+        void            (*log_error)(char *buf, unsigned int err_type, int fatal);
+
+        unsigned char   (*nvram_read_val)(int addr);
+        void            (*nvram_write_val)(int addr, unsigned char val);
+        ssize_t         (*nvram_write)(char *buf, size_t count, loff_t *index);
+        ssize_t         (*nvram_read)(char *buf, size_t count, loff_t *index);  
+        ssize_t         (*nvram_size)(void);            
+        void            (*nvram_sync)(void);
+
+        /* Exception handlers */
+        int             (*system_reset_exception)(struct pt_regs *regs);
+        int             (*machine_check_exception)(struct pt_regs *regs);
+
+        /* Motherboard/chipset features. This is a kind of general purpose
+         * hook used to control some machine specific features (like reset
+         * lines, chip power control, etc...).
+         */
+        long            (*feature_call)(unsigned int feature, ...);
+
+        /* Get legacy PCI/IDE interrupt mapping */ 
+        int             (*pci_get_legacy_ide_irq)(struct pci_dev *dev, int channel);
+        
+        /* Get access protection for /dev/mem */
+        pgprot_t        (*phys_mem_access_prot)(struct file *file,
+                                                unsigned long pfn,
+                                                unsigned long size,
+                                                pgprot_t vma_prot);
+
+        /* Idle loop for this platform, leave empty for default idle loop */
+        void            (*idle_loop)(void);
+
+        /*
+         * Function for waiting for work with reduced power in idle loop;
+         * called with interrupts disabled.
+         */
+        void            (*power_save)(void);
+
+        /* Function to enable performance monitor counters for this
+           platform, called once per cpu. */
+        void            (*enable_pmcs)(void);
+
+        /* Set DABR for this platform, leave empty for default implemenation */
+        int             (*set_dabr)(unsigned long dabr);
+
+#ifdef CONFIG_PPC32     /* XXX for now */
+        /* A general init function, called by ppc_init in init/main.c.
+           May be NULL. */
+        void            (*init)(void);
+
+        void            (*kgdb_map_scc)(void);
+
+        /*
+         * optional PCI "hooks"
+         */
+        /* Called in indirect_* to avoid touching devices */
+        int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
+
+        /* Called at then very end of pcibios_init() */
+        void (*pcibios_after_init)(void);
+
+#endif /* CONFIG_PPC32 */
+
+        /* Called after PPC generic resource fixup to perform
+           machine specific fixups */
+        void (*pcibios_fixup_resources)(struct pci_dev *);
+
+        /* Called for each PCI bus in the system when it's probed */
+        void (*pcibios_fixup_bus)(struct pci_bus *);
+
+        /* Called when pci_enable_device() is called. Returns 0 to
+         * allow assignment/enabling of the device. */
+        int  (*pcibios_enable_device_hook)(struct pci_dev *);
+
+        /* Called to shutdown machine specific hardware not already controlled
+         * by other drivers.
+         */
+        void (*machine_shutdown)(void);
+
+#ifdef CONFIG_KEXEC
+        /* Called to do the minimal shutdown needed to run a kexec'd kernel
+         * to run successfully.
+         * XXX Should we move this one out of kexec scope?
+         */
+        void (*machine_crash_shutdown)(struct pt_regs *regs);
+
+        /* Called to do what every setup is needed on image and the
+         * reboot code buffer. Returns 0 on success.
+         * Provide your own (maybe dummy) implementation if your platform
+         * claims to support kexec.
+         */
+        int (*machine_kexec_prepare)(struct kimage *image);
+
+        /* Called to handle any machine specific cleanup on image */
+        void (*machine_kexec_cleanup)(struct kimage *image);
+
+        /* Called to perform the _real_ kexec.
+         * Do NOT allocate memory or fail here. We are past the point of
+         * no return.
+         */
+        void (*machine_kexec)(struct kimage *image);
+#endif /* CONFIG_KEXEC */
+
+#ifdef CONFIG_SUSPEND
+        /* These are called to disable and enable, respectively, IRQs when
+         * entering a suspend state.  If NULL, then the generic versions
+         * will be called.  The generic versions disable/enable the
+         * decrementer along with interrupts.
+         */
+        void (*suspend_disable_irqs)(void);
+        void (*suspend_enable_irqs)(void);
+#endif
+};
+
+extern void e500_idle(void);
+extern void power4_idle(void);
+extern void power4_cpu_offline_powersave(void);
+extern void ppc6xx_idle(void);
+
+/*
+ * ppc_md contains a copy of the machine description structure for the
+ * current platform. machine_id contains the initial address where the
+ * description was found during boot.
+ */
+extern struct machdep_calls ppc_md;
+extern struct machdep_calls *machine_id;
+
+#define __machine_desc __attribute__ ((__section__ (".machine.desc")))
+
+#define define_machine(name)                                    \
+        extern struct machdep_calls mach_##name;                \
+        EXPORT_SYMBOL(mach_##name);                             \
+        struct machdep_calls mach_##name __machine_desc =
+
+#define machine_is(name) \
+        ({ \
+                extern struct machdep_calls mach_##name \
+                        __attribute__((weak));           \
+                machine_id == &mach_##name; \
+        })
+
+extern void probe_machine(void);
+
+extern char cmd_line[COMMAND_LINE_SIZE];
+
+#ifdef CONFIG_PPC_PMAC
+/*
+ * Power macintoshes have either a CUDA, PMU or SMU controlling
+ * system reset, power, NVRAM, RTC.
+ */
+typedef enum sys_ctrler_kind {
+        SYS_CTRLER_UNKNOWN = 0,
+        SYS_CTRLER_CUDA = 1,
+        SYS_CTRLER_PMU = 2,
+        SYS_CTRLER_SMU = 3,
+} sys_ctrler_t;
+extern sys_ctrler_t sys_ctrler;
+
+#endif /* CONFIG_PPC_PMAC */
+
+extern void setup_pci_ptrs(void);
+
+#ifdef CONFIG_SMP
+/* Poor default implementations */
+extern void __devinit smp_generic_give_timebase(void);
+extern void __devinit smp_generic_take_timebase(void);
+#endif /* CONFIG_SMP */
+
+
+/* Functions to produce codes on the leds.
+ * The SRC code should be unique for the message category and should
+ * be limited to the lower 24 bits (the upper 8 are set by these funcs),
+ * and (for boot & dump) should be sorted numerically in the order
+ * the events occur.
+ */
+/* Print a boot progress message. */
+void ppc64_boot_msg(unsigned int src, const char *msg);
+/* Print a termination message (print only -- does not stop the kernel) */
+void ppc64_terminate_msg(unsigned int src, const char *msg);
+
+static inline void log_error(char *buf, unsigned int err_type, int fatal)
+{
+        if (ppc_md.log_error)
+                ppc_md.log_error(buf, err_type, fatal);
+}
+
+#define __define_machine_initcall(mach,level,fn,id) \
+        static int __init __machine_initcall_##mach##_##fn(void) { \
+                if (machine_is(mach)) return fn(); \
+                return 0; \
+        } \
+        __define_initcall(level,__machine_initcall_##mach##_##fn,id);
+
+#define machine_core_initcall(mach,fn)          __define_machine_initcall(mach,"1",fn,1)
+#define machine_core_initcall_sync(mach,fn)     __define_machine_initcall(mach,"1s",fn,1s)
+#define machine_postcore_initcall(mach,fn)      __define_machine_initcall(mach,"2",fn,2)
+#define machine_postcore_initcall_sync(mach,fn) __define_machine_initcall(mach,"2s",fn,2s)
+#define machine_arch_initcall(mach,fn)          __define_machine_initcall(mach,"3",fn,3)
+#define machine_arch_initcall_sync(mach,fn)     __define_machine_initcall(mach,"3s",fn,3s)
+#define machine_subsys_initcall(mach,fn)        __define_machine_initcall(mach,"4",fn,4)
+#define machine_subsys_initcall_sync(mach,fn)   __define_machine_initcall(mach,"4s",fn,4s)
+#define machine_fs_initcall(mach,fn)            __define_machine_initcall(mach,"5",fn,5)
+#define machine_fs_initcall_sync(mach,fn)       __define_machine_initcall(mach,"5s",fn,5s)
+#define machine_rootfs_initcall(mach,fn)        __define_machine_initcall(mach,"rootfs",fn,rootfs)
+#define machine_device_initcall(mach,fn)        __define_machine_initcall(mach,"6",fn,6)
+#define machine_device_initcall_sync(mach,fn)   __define_machine_initcall(mach,"6s",fn,6s)
+#define machine_late_initcall(mach,fn)          __define_machine_initcall(mach,"7",fn,7)
+#define machine_late_initcall_sync(mach,fn)     __define_machine_initcall(mach,"7s",fn,7s)
+
+void generic_suspend_disable_irqs(void);
+void generic_suspend_enable_irqs(void);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/arch/powerpc/include/asm/macio.h b/arch/powerpc/include/asm/macio.h
new file mode 100644
index 000000000000..079c06eae446
--- /dev/null
+++ b/arch/powerpc/include/asm/macio.h
@@ -0,0 +1,142 @@
+#ifndef __MACIO_ASIC_H__
+#define __MACIO_ASIC_H__
+#ifdef __KERNEL__
+
+#include <linux/of_device.h>
+
+extern struct bus_type macio_bus_type;
+
+/* MacIO device driver is defined later */
+struct macio_driver;
+struct macio_chip;
+
+#define MACIO_DEV_COUNT_RESOURCES       8
+#define MACIO_DEV_COUNT_IRQS            8
+
+/*
+ * the macio_bus structure is used to describe a "virtual" bus
+ * within a MacIO ASIC. It's typically provided by a macio_pci_asic
+ * PCI device, but could be provided differently as well (nubus
+ * machines using a fake OF tree).
+ *
+ * The pdev field can be NULL on non-PCI machines
+ */
+struct macio_bus
+{
+        struct macio_chip       *chip;          /* macio_chip (private use) */
+        int                     index;          /* macio chip index in system */
+#ifdef CONFIG_PCI
+        struct pci_dev          *pdev;          /* PCI device hosting this bus */
+#endif
+};
+
+/*
+ * the macio_dev structure is used to describe a device
+ * within an Apple MacIO ASIC.
+ */
+struct macio_dev
+{
+        struct macio_bus        *bus;           /* macio bus this device is on */
+        struct macio_dev        *media_bay;     /* Device is part of a media bay */
+        struct of_device        ofdev;
+        int                     n_resources;
+        struct resource         resource[MACIO_DEV_COUNT_RESOURCES];
+        int                     n_interrupts;
+        struct resource         interrupt[MACIO_DEV_COUNT_IRQS];
+};
+#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
+#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
+
+extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
+extern void macio_dev_put(struct macio_dev *dev);
+
+/*
+ * Accessors to resources & interrupts and other device
+ * fields
+ */
+
+static inline int macio_resource_count(struct macio_dev *dev)
+{
+        return dev->n_resources;
+}
+
+static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
+{
+        return dev->resource[resource_no].start;
+}
+
+static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
+{
+        return dev->resource[resource_no].end;
+}
+
+static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
+{
+        struct resource *res = &dev->resource[resource_no];
+        if (res->start == 0 || res->end == 0 || res->end < res->start)
+                return 0;
+        return res->end - res->start + 1;
+}
+
+extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
+extern void macio_release_resource(struct macio_dev *dev, int resource_no);
+extern int macio_request_resources(struct macio_dev *dev, const char *name);
+extern void macio_release_resources(struct macio_dev *dev);
+
+static inline int macio_irq_count(struct macio_dev *dev)
+{
+        return dev->n_interrupts;
+}
+
+static inline int macio_irq(struct macio_dev *dev, int irq_no)
+{
+        return dev->interrupt[irq_no].start;
+}
+
+static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
+{
+        dev_set_drvdata(&dev->ofdev.dev, data);
+}
+
+static inline void* macio_get_drvdata(struct macio_dev *dev)
+{
+        return dev_get_drvdata(&dev->ofdev.dev);
+}
+
+static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
+{
+        return mdev->ofdev.node;
+}
+
+#ifdef CONFIG_PCI
+static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
+{
+        return mdev->bus->pdev;
+}
+#endif
+
+/*
+ * A driver for a mac-io chip based device
+ */
+struct macio_driver
+{
+        char                    *name;
+        struct of_device_id     *match_table;
+        struct module           *owner;
+
+        int     (*probe)(struct macio_dev* dev, const struct of_device_id *match);
+        int     (*remove)(struct macio_dev* dev);
+
+        int     (*suspend)(struct macio_dev* dev, pm_message_t state);
+        int     (*resume)(struct macio_dev* dev);
+        int     (*shutdown)(struct macio_dev* dev);
+
+        struct device_driver    driver;
+};
+#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
+
+extern int macio_register_driver(struct macio_driver *);
+extern void macio_unregister_driver(struct macio_driver *);
+
+#endif /* __KERNEL__ */
+#endif /* __MACIO_ASIC_H__ */
diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..f2741c8b59a1
--- /dev/null
+++ b/arch/powerpc/include/asm/mc146818rtc.h
@@ -0,0 +1,36 @@
+#ifndef _ASM_POWERPC_MC146818RTC_H
+#define _ASM_POWERPC_MC146818RTC_H
+
+/*
+ * Machine dependent access functions for RTC registers.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_ALWAYS_BCD  1       /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_MC146818RTC_H */
diff --git a/arch/powerpc/include/asm/mediabay.h b/arch/powerpc/include/asm/mediabay.h
new file mode 100644
index 000000000000..b2efb3325808
--- /dev/null
+++ b/arch/powerpc/include/asm/mediabay.h
@@ -0,0 +1,43 @@
+/*
+ * mediabay.h: definitions for using the media bay
+ * on PowerBook 3400 and similar computers.
+ *
+ * Copyright (C) 1997 Paul Mackerras.
+ */
+#ifndef _PPC_MEDIABAY_H
+#define _PPC_MEDIABAY_H
+
+#ifdef __KERNEL__
+
+#define MB_FD           0       /* media bay contains floppy drive (automatic eject ?) */
+#define MB_FD1          1       /* media bay contains floppy drive (manual eject ?) */
+#define MB_SOUND        2       /* sound device ? */
+#define MB_CD           3       /* media bay contains ATA drive such as CD or ZIP */
+#define MB_PCI          5       /* media bay contains a PCI device */
+#define MB_POWER        6       /* media bay contains a Power device (???) */
+#define MB_NO           7       /* media bay contains nothing */
+
+/* Number of bays in the machine or 0 */
+extern int media_bay_count;
+
+#ifdef CONFIG_BLK_DEV_IDE_PMAC
+#include <linux/ide.h>
+
+int check_media_bay_by_base(unsigned long base, int what);
+/* called by IDE PMAC host driver to register IDE controller for media bay */
+int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base,
+                            int irq, ide_hwif_t *hwif);
+
+int check_media_bay(struct device_node *which_bay, int what);
+
+#else
+
+static inline int check_media_bay(struct device_node *which_bay, int what)
+{
+        return -ENODEV;
+}
+
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _PPC_MEDIABAY_H */
diff --git a/arch/powerpc/include/asm/mman.h b/arch/powerpc/include/asm/mman.h
new file mode 100644
index 000000000000..9209f755763e
--- /dev/null
+++ b/arch/powerpc/include/asm/mman.h
@@ -0,0 +1,63 @@
+#ifndef _ASM_POWERPC_MMAN_H
+#define _ASM_POWERPC_MMAN_H
+
+#include <asm-generic/mman.h>
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define PROT_SAO        0x10            /* Strong Access Ordering */
+
+#define MAP_RENAME      MAP_ANONYMOUS   /* In SunOS terminology */
+#define MAP_NORESERVE   0x40            /* don't reserve swap pages */
+#define MAP_LOCKED      0x80
+
+#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
+#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
+
+#define MCL_CURRENT     0x2000          /* lock all currently mapped pages */
+#define MCL_FUTURE      0x4000          /* lock all additions to address space */
+
+#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#ifdef __KERNEL__
+#ifdef CONFIG_PPC64
+
+#include <asm/cputable.h>
+#include <linux/mm.h>
+
+/*
+ * This file is included by linux/mman.h, so we can't use cacl_vm_prot_bits()
+ * here.  How important is the optimization?
+ */
+static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot)
+{
+        return (prot & PROT_SAO) ? VM_SAO : 0;
+}
+#define arch_calc_vm_prot_bits(prot) arch_calc_vm_prot_bits(prot)
+
+static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)
+{
+        return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : 0;
+}
+#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)
+
+static inline int arch_validate_prot(unsigned long prot)
+{
+        if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))
+                return 0;
+        if ((prot & PROT_SAO) && !cpu_has_feature(CPU_FTR_SAO))
+                return 0;
+        return 1;
+}
+#define arch_validate_prot(prot) arch_validate_prot(prot)
+
+#endif /* CONFIG_PPC64 */
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_MMAN_H */
diff --git a/arch/powerpc/include/asm/mmu-40x.h b/arch/powerpc/include/asm/mmu-40x.h
new file mode 100644
index 000000000000..3d108676584c
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-40x.h
@@ -0,0 +1,63 @@
+#ifndef _ASM_POWERPC_MMU_40X_H_
+#define _ASM_POWERPC_MMU_40X_H_
+
+/*
+ * PPC40x support
+ */
+
+#define PPC40X_TLB_SIZE 64
+
+/*
+ * TLB entries are defined by a "high" tag portion and a "low" data
+ * portion.  On all architectures, the data portion is 32-bits.
+ *
+ * TLB entries are managed entirely under software control by reading,
+ * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
+ * instructions.
+ */
+
+#define TLB_LO          1
+#define TLB_HI          0
+
+#define TLB_DATA        TLB_LO
+#define TLB_TAG         TLB_HI
+
+/* Tag portion */
+
+#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
+#define TLB_PAGESZ_MASK 0x00000380
+#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
+#define   PAGESZ_1K             0
+#define   PAGESZ_4K             1
+#define   PAGESZ_16K            2
+#define   PAGESZ_64K            3
+#define   PAGESZ_256K           4
+#define   PAGESZ_1M             5
+#define   PAGESZ_4M             6
+#define   PAGESZ_16M            7
+#define TLB_VALID       0x00000040      /* Entry is valid */
+
+/* Data portion */
+
+#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
+#define TLB_PERM_MASK   0x00000300
+#define TLB_EX          0x00000200      /* Instruction execution allowed */
+#define TLB_WR          0x00000100      /* Writes permitted */
+#define TLB_ZSEL_MASK   0x000000F0
+#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
+#define TLB_ATTR_MASK   0x0000000F
+#define TLB_W           0x00000008      /* Caching is write-through */
+#define TLB_I           0x00000004      /* Caching is inhibited */
+#define TLB_M           0x00000002      /* Memory is coherent */
+#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned long id;
+        unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MMU_40X_H_ */
diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/mmu-44x.h
new file mode 100644
index 000000000000..a825524c981a
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -0,0 +1,76 @@
+#ifndef _ASM_POWERPC_MMU_44X_H_
+#define _ASM_POWERPC_MMU_44X_H_
+/*
+ * PPC440 support
+ */
+
+#define PPC44x_MMUCR_TID        0x000000ff
+#define PPC44x_MMUCR_STS        0x00010000
+
+#define PPC44x_TLB_PAGEID       0
+#define PPC44x_TLB_XLAT         1
+#define PPC44x_TLB_ATTRIB       2
+
+/* Page identification fields */
+#define PPC44x_TLB_EPN_MASK     0xfffffc00      /* Effective Page Number */
+#define PPC44x_TLB_VALID        0x00000200      /* Valid flag */
+#define PPC44x_TLB_TS           0x00000100      /* Translation address space */
+#define PPC44x_TLB_1K           0x00000000      /* Page sizes */
+#define PPC44x_TLB_4K           0x00000010
+#define PPC44x_TLB_16K          0x00000020
+#define PPC44x_TLB_64K          0x00000030
+#define PPC44x_TLB_256K         0x00000040
+#define PPC44x_TLB_1M           0x00000050
+#define PPC44x_TLB_16M          0x00000070
+#define PPC44x_TLB_256M         0x00000090
+
+/* Translation fields */
+#define PPC44x_TLB_RPN_MASK     0xfffffc00      /* Real Page Number */
+#define PPC44x_TLB_ERPN_MASK    0x0000000f
+
+/* Storage attribute and access control fields */
+#define PPC44x_TLB_ATTR_MASK    0x0000ff80
+#define PPC44x_TLB_U0           0x00008000      /* User 0 */
+#define PPC44x_TLB_U1           0x00004000      /* User 1 */
+#define PPC44x_TLB_U2           0x00002000      /* User 2 */
+#define PPC44x_TLB_U3           0x00001000      /* User 3 */
+#define PPC44x_TLB_W            0x00000800      /* Caching is write-through */
+#define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
+#define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
+#define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
+#define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
+
+#define PPC44x_TLB_PERM_MASK    0x0000003f
+#define PPC44x_TLB_UX           0x00000020      /* User execution */
+#define PPC44x_TLB_UW           0x00000010      /* User write */
+#define PPC44x_TLB_UR           0x00000008      /* User read */
+#define PPC44x_TLB_SX           0x00000004      /* Super execution */
+#define PPC44x_TLB_SW           0x00000002      /* Super write */
+#define PPC44x_TLB_SR           0x00000001      /* Super read */
+
+/* Number of TLB entries */
+#define PPC44x_TLB_SIZE         64
+
+#ifndef __ASSEMBLY__
+
+extern unsigned int tlb_44x_hwater;
+
+typedef struct {
+        unsigned long id;
+        unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#ifndef CONFIG_PPC_EARLY_DEBUG_44x
+#define PPC44x_EARLY_TLBS       1
+#else
+#define PPC44x_EARLY_TLBS       2
+#define PPC44x_EARLY_DEBUG_VIRTADDR     (ASM_CONST(0xf0000000) \
+        | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
+#endif
+
+/* Size of the TLBs used for pinning in lowmem */
+#define PPC_PIN_SIZE    (1 << 28)       /* 256M */
+
+#endif /* _ASM_POWERPC_MMU_44X_H_ */
diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
new file mode 100644
index 000000000000..9db877eb88db
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -0,0 +1,145 @@
+#ifndef _ASM_POWERPC_MMU_8XX_H_
+#define _ASM_POWERPC_MMU_8XX_H_
+/*
+ * PPC8xx support
+ */
+
+/* Control/status registers for the MPC8xx.
+ * A write operation to these registers causes serialized access.
+ * During software tablewalk, the registers used perform mask/shift-add
+ * operations when written/read.  A TLB entry is created when the Mx_RPN
+ * is written, and the contents of several registers are used to
+ * create the entry.
+ */
+#define SPRN_MI_CTR     784     /* Instruction TLB control register */
+#define MI_GPM          0x80000000      /* Set domain manager mode */
+#define MI_PPM          0x40000000      /* Set subpage protection */
+#define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
+#define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
+#define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
+#define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
+#define MI_RESETVAL     0x00000000      /* Value of register at reset */
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define SPRN_MI_AP      786
+#define MI_Ks           0x80000000      /* Should not be set */
+#define MI_Kp           0x40000000      /* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MI_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define SPRN_MI_EPN     787
+#define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
+#define MI_EVALID       0x00000200      /* Entry is valid */
+#define MI_ASIDMASK     0x0000000f      /* ASID match value */
+                                        /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the instruction TLB, it contains bits that get loaded into the
+ * TLB entry when the MI_RPN is written.
+ */
+#define SPRN_MI_TWC     789
+#define MI_APG          0x000001e0      /* Access protection group (0) */
+#define MI_GUARDED      0x00000010      /* Guarded storage */
+#define MI_PSMASK       0x0000000c      /* Mask of page size bits */
+#define MI_PS8MEG       0x0000000c      /* 8M page size */
+#define MI_PS512K       0x00000004      /* 512K page size */
+#define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
+#define MI_SVALID       0x00000001      /* Segment entry is valid */
+                                        /* Reset value is undefined */
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the instruction TLB, using
+ * additional information from the MI_EPN, and MI_TWC registers.
+ */
+#define SPRN_MI_RPN     790
+
+/* Define an RPN value for mapping kernel memory to large virtual
+ * pages for boot initialization.  This has real page number of 0,
+ * large page size, shared page, cache enabled, and valid.
+ * Also mark all subpages valid and write access.
+ */
+#define MI_BOOTINIT     0x000001fd
+
+#define SPRN_MD_CTR     792     /* Data TLB control register */
+#define MD_GPM          0x80000000      /* Set domain manager mode */
+#define MD_PPM          0x40000000      /* Set subpage protection */
+#define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
+#define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
+#define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
+#define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
+#define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
+#define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
+#define MD_RESETVAL     0x04000000      /* Value of register at reset */
+
+#define SPRN_M_CASID    793     /* Address space ID (context) to match */
+#define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
+
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define SPRN_MD_AP      794
+#define MD_Ks           0x80000000      /* Should not be set */
+#define MD_Kp           0x40000000      /* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MD_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define SPRN_MD_EPN     795
+#define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
+#define MD_EVALID       0x00000200      /* Entry is valid */
+#define MD_ASIDMASK     0x0000000f      /* ASID match value */
+                                        /* Reset value is undefined */
+
+/* The pointer to the base address of the first level page table.
+ * During a software tablewalk, reading this register provides the address
+ * of the entry associated with MD_EPN.
+ */
+#define SPRN_M_TWB      796
+#define M_L1TB          0xfffff000      /* Level 1 table base address */
+#define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
+                                        /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the data TLB, it contains bits that get loaded into the TLB entry
+ * when the MD_RPN is written.  It is also provides the hardware assist
+ * for finding the PTE address during software tablewalk.
+ */
+#define SPRN_MD_TWC     797
+#define MD_L2TB         0xfffff000      /* Level 2 table base address */
+#define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
+#define MD_APG          0x000001e0      /* Access protection group (0) */
+#define MD_GUARDED      0x00000010      /* Guarded storage */
+#define MD_PSMASK       0x0000000c      /* Mask of page size bits */
+#define MD_PS8MEG       0x0000000c      /* 8M page size */
+#define MD_PS512K       0x00000004      /* 512K page size */
+#define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
+#define MD_WT           0x00000002      /* Use writethrough page attribute */
+#define MD_SVALID       0x00000001      /* Segment entry is valid */
+                                        /* Reset value is undefined */
+
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the data TLB, using
+ * additional information from the MD_EPN, and MD_TWC registers.
+ */
+#define SPRN_MD_RPN     798
+
+/* This is a temporary storage register that could be used to save
+ * a processor working register during a tablewalk.
+ */
+#define SPRN_M_TW       799
+
+#ifndef __ASSEMBLY__
+typedef struct {
+        unsigned long id;
+        unsigned long vdso_base;
+} mm_context_t;
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/arch/powerpc/include/asm/mmu-fsl-booke.h b/arch/powerpc/include/asm/mmu-fsl-booke.h
new file mode 100644
index 000000000000..925d93cf64d8
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-fsl-booke.h
@@ -0,0 +1,82 @@
+#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
+#define _ASM_POWERPC_MMU_FSL_BOOKE_H_
+/*
+ * Freescale Book-E MMU support
+ */
+
+/* Book-E defined page sizes */
+#define BOOKE_PAGESZ_1K         0
+#define BOOKE_PAGESZ_4K         1
+#define BOOKE_PAGESZ_16K        2
+#define BOOKE_PAGESZ_64K        3
+#define BOOKE_PAGESZ_256K       4
+#define BOOKE_PAGESZ_1M         5
+#define BOOKE_PAGESZ_4M         6
+#define BOOKE_PAGESZ_16M        7
+#define BOOKE_PAGESZ_64M        8
+#define BOOKE_PAGESZ_256M       9
+#define BOOKE_PAGESZ_1GB        10
+#define BOOKE_PAGESZ_4GB        11
+#define BOOKE_PAGESZ_16GB       12
+#define BOOKE_PAGESZ_64GB       13
+#define BOOKE_PAGESZ_256GB      14
+#define BOOKE_PAGESZ_1TB        15
+
+#define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
+#define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
+#define MAS0_NV(x)      ((x) & 0x00000FFF)
+
+#define MAS1_VALID      0x80000000
+#define MAS1_IPROT      0x40000000
+#define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
+#define MAS1_TS         0x00001000
+#define MAS1_TSIZE(x)   ((x << 8) & 0x00000F00)
+
+#define MAS2_EPN        0xFFFFF000
+#define MAS2_X0         0x00000040
+#define MAS2_X1         0x00000020
+#define MAS2_W          0x00000010
+#define MAS2_I          0x00000008
+#define MAS2_M          0x00000004
+#define MAS2_G          0x00000002
+#define MAS2_E          0x00000001
+
+#define MAS3_RPN        0xFFFFF000
+#define MAS3_U0         0x00000200
+#define MAS3_U1         0x00000100
+#define MAS3_U2         0x00000080
+#define MAS3_U3         0x00000040
+#define MAS3_UX         0x00000020
+#define MAS3_SX         0x00000010
+#define MAS3_UW         0x00000008
+#define MAS3_SW         0x00000004
+#define MAS3_UR         0x00000002
+#define MAS3_SR         0x00000001
+
+#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
+#define MAS4_TIDDSEL    0x000F0000
+#define MAS4_TSIZED(x)  MAS1_TSIZE(x)
+#define MAS4_X0D        0x00000040
+#define MAS4_X1D        0x00000020
+#define MAS4_WD         0x00000010
+#define MAS4_ID         0x00000008
+#define MAS4_MD         0x00000004
+#define MAS4_GD         0x00000002
+#define MAS4_ED         0x00000001
+
+#define MAS6_SPID0      0x3FFF0000
+#define MAS6_SPID1      0x00007FFE
+#define MAS6_SAS        0x00000001
+#define MAS6_SPID       MAS6_SPID0
+
+#define MAS7_RPN        0xFFFFFFFF
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned long id;
+        unsigned long vdso_base;
+} mm_context_t;
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash32.h b/arch/powerpc/include/asm/mmu-hash32.h
new file mode 100644
index 000000000000..16b1a1e77e64
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-hash32.h
@@ -0,0 +1,83 @@
+#ifndef _ASM_POWERPC_MMU_HASH32_H_
+#define _ASM_POWERPC_MMU_HASH32_H_
+/*
+ * 32-bit hash table MMU support
+ */
+
+/*
+ * BATs
+ */
+
+/* Block size masks */
+#define BL_128K 0x000
+#define BL_256K 0x001
+#define BL_512K 0x003
+#define BL_1M   0x007
+#define BL_2M   0x00F
+#define BL_4M   0x01F
+#define BL_8M   0x03F
+#define BL_16M  0x07F
+#define BL_32M  0x0FF
+#define BL_64M  0x1FF
+#define BL_128M 0x3FF
+#define BL_256M 0x7FF
+
+/* BAT Access Protection */
+#define BPP_XX  0x00            /* No access */
+#define BPP_RX  0x01            /* Read only */
+#define BPP_RW  0x02            /* Read/write */
+
+#ifndef __ASSEMBLY__
+/* Contort a phys_addr_t into the right format/bits for a BAT */
+#ifdef CONFIG_PHYS_64BIT
+#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
+                                ((x & 0x0000000e00000000ULL) >> 24) | \
+                                ((x & 0x0000000100000000ULL) >> 30)))
+#else
+#define BAT_PHYS_ADDR(x) (x)
+#endif
+
+struct ppc_bat {
+        u32 batu;
+        u32 batl;
+};
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Hash table
+ */
+
+/* Values for PP (assumes Ks=0, Kp=1) */
+#define PP_RWXX 0       /* Supervisor read/write, User none */
+#define PP_RWRX 1       /* Supervisor read/write, User read */
+#define PP_RWRW 2       /* Supervisor read/write, User read/write */
+#define PP_RXRX 3       /* Supervisor read,       User read */
+
+#ifndef __ASSEMBLY__
+
+/* Hardware Page Table Entry */
+struct hash_pte {
+        unsigned long v:1;      /* Entry is valid */
+        unsigned long vsid:24;  /* Virtual segment identifier */
+        unsigned long h:1;      /* Hash algorithm indicator */
+        unsigned long api:6;    /* Abbreviated page index */
+        unsigned long rpn:20;   /* Real (physical) page number */
+        unsigned long    :3;    /* Unused */
+        unsigned long r:1;      /* Referenced */
+        unsigned long c:1;      /* Changed */
+        unsigned long w:1;      /* Write-thru cache mode */
+        unsigned long i:1;      /* Cache inhibited */
+        unsigned long m:1;      /* Memory coherence */
+        unsigned long g:1;      /* Guarded */
+        unsigned long  :1;      /* Unused */
+        unsigned long pp:2;     /* Page protection */
+};
+
+typedef struct {
+        unsigned long id;
+        unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
new file mode 100644
index 000000000000..19c7a9403490
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -0,0 +1,478 @@
+#ifndef _ASM_POWERPC_MMU_HASH64_H_
+#define _ASM_POWERPC_MMU_HASH64_H_
+/*
+ * PowerPC64 memory management structures
+ *
+ * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
+ *   PPC64 rework.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/asm-compat.h>
+#include <asm/page.h>
+
+/*
+ * Segment table
+ */
+
+#define STE_ESID_V      0x80
+#define STE_ESID_KS     0x20
+#define STE_ESID_KP     0x10
+#define STE_ESID_N      0x08
+
+#define STE_VSID_SHIFT  12
+
+/* Location of cpu0's segment table */
+#define STAB0_PAGE      0x6
+#define STAB0_OFFSET    (STAB0_PAGE << 12)
+#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
+
+#ifndef __ASSEMBLY__
+extern char initial_stab[];
+#endif /* ! __ASSEMBLY */
+
+/*
+ * SLB
+ */
+
+#define SLB_NUM_BOLTED          3
+#define SLB_CACHE_ENTRIES       8
+
+/* Bits in the SLB ESID word */
+#define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
+
+/* Bits in the SLB VSID word */
+#define SLB_VSID_SHIFT          12
+#define SLB_VSID_SHIFT_1T       24
+#define SLB_VSID_SSIZE_SHIFT    62
+#define SLB_VSID_B              ASM_CONST(0xc000000000000000)
+#define SLB_VSID_B_256M         ASM_CONST(0x0000000000000000)
+#define SLB_VSID_B_1T           ASM_CONST(0x4000000000000000)
+#define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
+#define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
+#define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
+#define SLB_VSID_L              ASM_CONST(0x0000000000000100)
+#define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
+#define SLB_VSID_LP             ASM_CONST(0x0000000000000030)
+#define SLB_VSID_LP_00          ASM_CONST(0x0000000000000000)
+#define SLB_VSID_LP_01          ASM_CONST(0x0000000000000010)
+#define SLB_VSID_LP_10          ASM_CONST(0x0000000000000020)
+#define SLB_VSID_LP_11          ASM_CONST(0x0000000000000030)
+#define SLB_VSID_LLP            (SLB_VSID_L|SLB_VSID_LP)
+
+#define SLB_VSID_KERNEL         (SLB_VSID_KP)
+#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
+
+#define SLBIE_C                 (0x08000000)
+#define SLBIE_SSIZE_SHIFT       25
+
+/*
+ * Hash table
+ */
+
+#define HPTES_PER_GROUP 8
+
+#define HPTE_V_SSIZE_SHIFT      62
+#define HPTE_V_AVPN_SHIFT       7
+#define HPTE_V_AVPN             ASM_CONST(0x3fffffffffffff80)
+#define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
+#define HPTE_V_COMPARE(x,y)     (!(((x) ^ (y)) & 0xffffffffffffff80UL))
+#define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
+#define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
+#define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
+#define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
+#define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
+
+#define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
+#define HPTE_R_TS               ASM_CONST(0x4000000000000000)
+#define HPTE_R_RPN_SHIFT        12
+#define HPTE_R_RPN              ASM_CONST(0x3ffffffffffff000)
+#define HPTE_R_FLAGS            ASM_CONST(0x00000000000003ff)
+#define HPTE_R_PP               ASM_CONST(0x0000000000000003)
+#define HPTE_R_N                ASM_CONST(0x0000000000000004)
+#define HPTE_R_C                ASM_CONST(0x0000000000000080)
+#define HPTE_R_R                ASM_CONST(0x0000000000000100)
+
+#define HPTE_V_1TB_SEG          ASM_CONST(0x4000000000000000)
+#define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
+
+/* Values for PP (assumes Ks=0, Kp=1) */
+/* pp0 will always be 0 for linux     */
+#define PP_RWXX 0       /* Supervisor read/write, User none */
+#define PP_RWRX 1       /* Supervisor read/write, User read */
+#define PP_RWRW 2       /* Supervisor read/write, User read/write */
+#define PP_RXRX 3       /* Supervisor read,       User read */
+
+#ifndef __ASSEMBLY__
+
+struct hash_pte {
+        unsigned long v;
+        unsigned long r;
+};
+
+extern struct hash_pte *htab_address;
+extern unsigned long htab_size_bytes;
+extern unsigned long htab_hash_mask;
+
+/*
+ * Page size definition
+ *
+ *    shift : is the "PAGE_SHIFT" value for that page size
+ *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
+ *            directly to a slbmte "vsid" value
+ *    penc  : is the HPTE encoding mask for the "LP" field:
+ *
+ */
+struct mmu_psize_def
+{
+        unsigned int    shift;  /* number of bits */
+        unsigned int    penc;   /* HPTE encoding */
+        unsigned int    tlbiel; /* tlbiel supported for that page size */
+        unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
+        unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The kernel use the constants below to index in the page sizes array.
+ * The use of fixed constants for this purpose is better for performances
+ * of the low level hash refill handlers.
+ *
+ * A non supported page size has a "shift" field set to 0
+ *
+ * Any new page size being implemented can get a new entry in here. Whether
+ * the kernel will use it or not is a different matter though. The actual page
+ * size used by hugetlbfs is not defined here and may be made variable
+ */
+
+#define MMU_PAGE_4K             0       /* 4K */
+#define MMU_PAGE_64K            1       /* 64K */
+#define MMU_PAGE_64K_AP         2       /* 64K Admixed (in a 4K segment) */
+#define MMU_PAGE_1M             3       /* 1M */
+#define MMU_PAGE_16M            4       /* 16M */
+#define MMU_PAGE_16G            5       /* 16G */
+#define MMU_PAGE_COUNT          6
+
+/*
+ * Segment sizes.
+ * These are the values used by hardware in the B field of
+ * SLB entries and the first dword of MMU hashtable entries.
+ * The B field is 2 bits; the values 2 and 3 are unused and reserved.
+ */
+#define MMU_SEGSIZE_256M        0
+#define MMU_SEGSIZE_1T          1
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * The current system page and segment sizes
+ */
+extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
+extern int mmu_linear_psize;
+extern int mmu_virtual_psize;
+extern int mmu_vmalloc_psize;
+extern int mmu_vmemmap_psize;
+extern int mmu_io_psize;
+extern int mmu_kernel_ssize;
+extern int mmu_highuser_ssize;
+extern u16 mmu_slb_size;
+extern unsigned long tce_alloc_start, tce_alloc_end;
+
+/*
+ * If the processor supports 64k normal pages but not 64k cache
+ * inhibited pages, we have to be prepared to switch processes
+ * to use 4k pages when they create cache-inhibited mappings.
+ * If this is the case, mmu_ci_restrictions will be set to 1.
+ */
+extern int mmu_ci_restrictions;
+
+#ifdef CONFIG_HUGETLB_PAGE
+/*
+ * The page size indexes of the huge pages for use by hugetlbfs
+ */
+extern unsigned int mmu_huge_psizes[MMU_PAGE_COUNT];
+
+#endif /* CONFIG_HUGETLB_PAGE */
+
+/*
+ * This function sets the AVPN and L fields of the HPTE  appropriately
+ * for the page size
+ */
+static inline unsigned long hpte_encode_v(unsigned long va, int psize,
+                                          int ssize)
+{
+        unsigned long v;
+        v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
+        v <<= HPTE_V_AVPN_SHIFT;
+        if (psize != MMU_PAGE_4K)
+                v |= HPTE_V_LARGE;
+        v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
+        return v;
+}
+
+/*
+ * This function sets the ARPN, and LP fields of the HPTE appropriately
+ * for the page size. We assume the pa is already "clean" that is properly
+ * aligned for the requested page size
+ */
+static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
+{
+        unsigned long r;
+
+        /* A 4K page needs no special encoding */
+        if (psize == MMU_PAGE_4K)
+                return pa & HPTE_R_RPN;
+        else {
+                unsigned int penc = mmu_psize_defs[psize].penc;
+                unsigned int shift = mmu_psize_defs[psize].shift;
+                return (pa & ~((1ul << shift) - 1)) | (penc << 12);
+        }
+        return r;
+}
+
+/*
+ * Build a VA given VSID, EA and segment size
+ */
+static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
+                                   int ssize)
+{
+        if (ssize == MMU_SEGSIZE_256M)
+                return (vsid << 28) | (ea & 0xfffffffUL);
+        return (vsid << 40) | (ea & 0xffffffffffUL);
+}
+
+/*
+ * This hashes a virtual address
+ */
+
+static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
+                                     int ssize)
+{
+        unsigned long hash, vsid;
+
+        if (ssize == MMU_SEGSIZE_256M) {
+                hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
+        } else {
+                vsid = va >> 40;
+                hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
+        }
+        return hash & 0x7fffffffffUL;
+}
+
+extern int __hash_page_4K(unsigned long ea, unsigned long access,
+                          unsigned long vsid, pte_t *ptep, unsigned long trap,
+                          unsigned int local, int ssize, int subpage_prot);
+extern int __hash_page_64K(unsigned long ea, unsigned long access,
+                           unsigned long vsid, pte_t *ptep, unsigned long trap,
+                           unsigned int local, int ssize);
+struct mm_struct;
+extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
+extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
+                          unsigned long ea, unsigned long vsid, int local,
+                          unsigned long trap);
+
+extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
+                             unsigned long pstart, unsigned long mode,
+                             int psize, int ssize);
+extern void set_huge_psize(int psize);
+extern void add_gpage(unsigned long addr, unsigned long page_size,
+                          unsigned long number_of_pages);
+extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
+
+extern void htab_initialize(void);
+extern void htab_initialize_secondary(void);
+extern void hpte_init_native(void);
+extern void hpte_init_lpar(void);
+extern void hpte_init_iSeries(void);
+extern void hpte_init_beat(void);
+extern void hpte_init_beat_v3(void);
+
+extern void stabs_alloc(void);
+extern void slb_initialize(void);
+extern void slb_flush_and_rebolt(void);
+extern void stab_initialize(unsigned long stab);
+
+extern void slb_vmalloc_update(void);
+#endif /* __ASSEMBLY__ */
+
+/*
+ * VSID allocation
+ *
+ * We first generate a 36-bit "proto-VSID".  For kernel addresses this
+ * is equal to the ESID, for user addresses it is:
+ *      (context << 15) | (esid & 0x7fff)
+ *
+ * The two forms are distinguishable because the top bit is 0 for user
+ * addresses, whereas the top two bits are 1 for kernel addresses.
+ * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
+ * now.
+ *
+ * The proto-VSIDs are then scrambled into real VSIDs with the
+ * multiplicative hash:
+ *
+ *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
+ *      where   VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
+ *              VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
+ *
+ * This scramble is only well defined for proto-VSIDs below
+ * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
+ * reserved.  VSID_MULTIPLIER is prime, so in particular it is
+ * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
+ * Because the modulus is 2^n-1 we can compute it efficiently without
+ * a divide or extra multiply (see below).
+ *
+ * This scheme has several advantages over older methods:
+ *
+ *      - We have VSIDs allocated for every kernel address
+ * (i.e. everything above 0xC000000000000000), except the very top
+ * segment, which simplifies several things.
+ *
+ *      - We allow for 15 significant bits of ESID and 20 bits of
+ * context for user addresses.  i.e. 8T (43 bits) of address space for
+ * up to 1M contexts (although the page table structure and context
+ * allocation will need changes to take advantage of this).
+ *
+ *      - The scramble function gives robust scattering in the hash
+ * table (at least based on some initial results).  The previous
+ * method was more susceptible to pathological cases giving excessive
+ * hash collisions.
+ */
+/*
+ * WARNING - If you change these you must make sure the asm
+ * implementations in slb_allocate (slb_low.S), do_stab_bolted
+ * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
+ *
+ * You'll also need to change the precomputed VSID values in head.S
+ * which are used by the iSeries firmware.
+ */
+
+#define VSID_MULTIPLIER_256M    ASM_CONST(200730139)    /* 28-bit prime */
+#define VSID_BITS_256M          36
+#define VSID_MODULUS_256M       ((1UL<<VSID_BITS_256M)-1)
+
+#define VSID_MULTIPLIER_1T      ASM_CONST(12538073)     /* 24-bit prime */
+#define VSID_BITS_1T            24
+#define VSID_MODULUS_1T         ((1UL<<VSID_BITS_1T)-1)
+
+#define CONTEXT_BITS            19
+#define USER_ESID_BITS          16
+#define USER_ESID_BITS_1T       4
+
+#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
+
+/*
+ * This macro generates asm code to compute the VSID scramble
+ * function.  Used in slb_allocate() and do_stab_bolted.  The function
+ * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
+ *
+ *      rt = register continaing the proto-VSID and into which the
+ *              VSID will be stored
+ *      rx = scratch register (clobbered)
+ *
+ *      - rt and rx must be different registers
+ *      - The answer will end up in the low VSID_BITS bits of rt.  The higher
+ *        bits may contain other garbage, so you may need to mask the
+ *        result.
+ */
+#define ASM_VSID_SCRAMBLE(rt, rx, size)                                 \
+        lis     rx,VSID_MULTIPLIER_##size@h;                            \
+        ori     rx,rx,VSID_MULTIPLIER_##size@l;                         \
+        mulld   rt,rt,rx;               /* rt = rt * MULTIPLIER */      \
+                                                                        \
+        srdi    rx,rt,VSID_BITS_##size;                                 \
+        clrldi  rt,rt,(64-VSID_BITS_##size);                            \
+        add     rt,rt,rx;               /* add high and low bits */     \
+        /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and         \
+         * 2^36-1+2^28-1.  That in particular means that if r3 >=       \
+         * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has     \
+         * the bit clear, r3 already has the answer we want, if it      \
+         * doesn't, the answer is the low 36 bits of r3+1.  So in all   \
+         * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
+        addi    rx,rt,1;                                                \
+        srdi    rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */   \
+        add     rt,rt,rx
+
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+        mm_context_id_t id;
+        u16 user_psize;         /* page size index */
+
+#ifdef CONFIG_PPC_MM_SLICES
+        u64 low_slices_psize;   /* SLB page size encodings */
+        u64 high_slices_psize;  /* 4 bits per slice for now */
+#else
+        u16 sllp;               /* SLB page size encoding */
+#endif
+        unsigned long vdso_base;
+} mm_context_t;
+
+
+#if 0
+/*
+ * The code below is equivalent to this function for arguments
+ * < 2^VSID_BITS, which is all this should ever be called
+ * with.  However gcc is not clever enough to compute the
+ * modulus (2^n-1) without a second multiply.
+ */
+#define vsid_scrample(protovsid, size) \
+        ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
+
+#else /* 1 */
+#define vsid_scramble(protovsid, size) \
+        ({                                                               \
+                unsigned long x;                                         \
+                x = (protovsid) * VSID_MULTIPLIER_##size;                \
+                x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
+                (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
+        })
+#endif /* 1 */
+
+/* This is only valid for addresses >= KERNELBASE */
+static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
+{
+        if (ssize == MMU_SEGSIZE_256M)
+                return vsid_scramble(ea >> SID_SHIFT, 256M);
+        return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
+}
+
+/* Returns the segment size indicator for a user address */
+static inline int user_segment_size(unsigned long addr)
+{
+        /* Use 1T segments if possible for addresses >= 1T */
+        if (addr >= (1UL << SID_SHIFT_1T))
+                return mmu_highuser_ssize;
+        return MMU_SEGSIZE_256M;
+}
+
+/* This is only valid for user addresses (which are below 2^44) */
+static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
+                                     int ssize)
+{
+        if (ssize == MMU_SEGSIZE_256M)
+                return vsid_scramble((context << USER_ESID_BITS)
+                                     | (ea >> SID_SHIFT), 256M);
+        return vsid_scramble((context << USER_ESID_BITS_1T)
+                             | (ea >> SID_SHIFT_1T), 1T);
+}
+
+/*
+ * This is only used on legacy iSeries in lparmap.c,
+ * hence the 256MB segment assumption.
+ */
+#define VSID_SCRAMBLE(pvsid)    (((pvsid) * VSID_MULTIPLIER_256M) %     \
+                                 VSID_MODULUS_256M)
+#define KERNEL_VSID(ea)         VSID_SCRAMBLE(GET_ESID(ea))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
new file mode 100644
index 000000000000..4c0e1b4f975c
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_POWERPC_MMU_H_
+#define _ASM_POWERPC_MMU_H_
+#ifdef __KERNEL__
+
+#ifdef CONFIG_PPC64
+/* 64-bit classic hash table MMU */
+#  include <asm/mmu-hash64.h>
+#elif defined(CONFIG_PPC_STD_MMU)
+/* 32-bit classic hash table MMU */
+#  include <asm/mmu-hash32.h>
+#elif defined(CONFIG_40x)
+/* 40x-style software loaded TLB */
+#  include <asm/mmu-40x.h>
+#elif defined(CONFIG_44x)
+/* 44x-style software loaded TLB */
+#  include <asm/mmu-44x.h>
+#elif defined(CONFIG_FSL_BOOKE)
+/* Freescale Book-E software loaded TLB */
+#  include <asm/mmu-fsl-booke.h>
+#elif defined (CONFIG_PPC_8xx)
+/* Motorola/Freescale 8xx software loaded TLB */
+#  include <asm/mmu-8xx.h>
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
new file mode 100644
index 000000000000..9102b8bf0ead
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -0,0 +1,280 @@
+#ifndef __ASM_POWERPC_MMU_CONTEXT_H
+#define __ASM_POWERPC_MMU_CONTEXT_H
+#ifdef __KERNEL__
+
+#include <asm/mmu.h>    
+#include <asm/cputable.h>
+#include <asm-generic/mm_hooks.h>
+
+#ifndef CONFIG_PPC64
+#include <asm/atomic.h>
+#include <linux/bitops.h>
+
+/*
+ * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
+ * (virtual segment identifiers) for each context.  Although the
+ * hardware supports 24-bit VSIDs, and thus >1 million contexts,
+ * we only use 32,768 of them.  That is ample, since there can be
+ * at most around 30,000 tasks in the system anyway, and it means
+ * that we can use a bitmap to indicate which contexts are in use.
+ * Using a bitmap means that we entirely avoid all of the problems
+ * that we used to have when the context number overflowed,
+ * particularly on SMP systems.
+ *  -- paulus.
+ */
+
+/*
+ * This function defines the mapping from contexts to VSIDs (virtual
+ * segment IDs).  We use a skew on both the context and the high 4 bits
+ * of the 32-bit virtual address (the "effective segment ID") in order
+ * to spread out the entries in the MMU hash table.  Note, if this
+ * function is changed then arch/ppc/mm/hashtable.S will have to be
+ * changed to correspond.
+ */
+#define CTX_TO_VSID(ctx, va)    (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
+                                 & 0xffffff)
+
+/*
+   The MPC8xx has only 16 contexts.  We rotate through them on each
+   task switch.  A better way would be to keep track of tasks that
+   own contexts, and implement an LRU usage.  That way very active
+   tasks don't always have to pay the TLB reload overhead.  The
+   kernel pages are mapped shared, so the kernel can run on behalf
+   of any task that makes a kernel entry.  Shared does not mean they
+   are not protected, just that the ASID comparison is not performed.
+        -- Dan
+
+   The IBM4xx has 256 contexts, so we can just rotate through these
+   as a way of "switching" contexts.  If the TID of the TLB is zero,
+   the PID/TID comparison is disabled, so we can use a TID of zero
+   to represent all kernel pages as shared among all contexts.
+        -- Dan
+ */
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+#ifdef CONFIG_8xx
+#define NO_CONTEXT              16
+#define LAST_CONTEXT            15
+#define FIRST_CONTEXT           0
+
+#elif defined(CONFIG_4xx)
+#define NO_CONTEXT              256
+#define LAST_CONTEXT            255
+#define FIRST_CONTEXT           1
+
+#elif defined(CONFIG_E200) || defined(CONFIG_E500)
+#define NO_CONTEXT              256
+#define LAST_CONTEXT            255
+#define FIRST_CONTEXT           1
+
+#else
+
+/* PPC 6xx, 7xx CPUs */
+#define NO_CONTEXT              ((unsigned long) -1)
+#define LAST_CONTEXT            32767
+#define FIRST_CONTEXT           1
+#endif
+
+/*
+ * Set the current MMU context.
+ * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
+ * loading up the segment registers for the user part of the address space.
+ *
+ * Since the PGD is immediately available, it is much faster to simply
+ * pass this along as a second parameter, which is required for 8xx and
+ * can be used for debugging on all processors (if you happen to have
+ * an Abatron).
+ */
+extern void set_context(unsigned long contextid, pgd_t *pgd);
+
+/*
+ * Bitmap of contexts in use.
+ * The size of this bitmap is LAST_CONTEXT + 1 bits.
+ */
+extern unsigned long context_map[];
+
+/*
+ * This caches the next context number that we expect to be free.
+ * Its use is an optimization only, we can't rely on this context
+ * number to be free, but it usually will be.
+ */
+extern unsigned long next_mmu_context;
+
+/*
+ * If we don't have sufficient contexts to give one to every task
+ * that could be in the system, we need to be able to steal contexts.
+ * These variables support that.
+ */
+#if LAST_CONTEXT < 30000
+#define FEW_CONTEXTS    1
+extern atomic_t nr_free_contexts;
+extern struct mm_struct *context_mm[LAST_CONTEXT+1];
+extern void steal_context(void);
+#endif
+
+/*
+ * Get a new mmu context for the address space described by `mm'.
+ */
+static inline void get_mmu_context(struct mm_struct *mm)
+{
+        unsigned long ctx;
+
+        if (mm->context.id != NO_CONTEXT)
+                return;
+#ifdef FEW_CONTEXTS
+        while (atomic_dec_if_positive(&nr_free_contexts) < 0)
+                steal_context();
+#endif
+        ctx = next_mmu_context;
+        while (test_and_set_bit(ctx, context_map)) {
+                ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
+                if (ctx > LAST_CONTEXT)
+                        ctx = 0;
+        }
+        next_mmu_context = (ctx + 1) & LAST_CONTEXT;
+        mm->context.id = ctx;
+#ifdef FEW_CONTEXTS
+        context_mm[ctx] = mm;
+#endif
+}
+
+/*
+ * Set up the context for a new address space.
+ */
+static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
+{
+        mm->context.id = NO_CONTEXT;
+        mm->context.vdso_base = 0;
+        return 0;
+}
+
+/*
+ * We're finished using the context for an address space.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        preempt_disable();
+        if (mm->context.id != NO_CONTEXT) {
+                clear_bit(mm->context.id, context_map);
+                mm->context.id = NO_CONTEXT;
+#ifdef FEW_CONTEXTS
+                atomic_inc(&nr_free_contexts);
+#endif
+        }
+        preempt_enable();
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+#ifdef CONFIG_ALTIVEC
+        if (cpu_has_feature(CPU_FTR_ALTIVEC))
+        asm volatile ("dssall;\n"
+#ifndef CONFIG_POWER4
+         "sync;\n" /* G4 needs a sync here, G5 apparently not */
+#endif
+         : : );
+#endif /* CONFIG_ALTIVEC */
+
+        tsk->thread.pgdir = next->pgd;
+
+        /* No need to flush userspace segments if the mm doesnt change */
+        if (prev == next)
+                return;
+
+        /* Setup new userspace context */
+        get_mmu_context(next);
+        set_context(next->context.id, next->pgd);
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+#define activate_mm(active_mm, mm)   switch_mm(active_mm, mm, current)
+
+extern void mmu_context_init(void);
+
+
+#else
+
+#include <linux/kernel.h>       
+#include <linux/mm.h>   
+#include <linux/sched.h>
+
+/*
+ * Copyright (C) 2001 PPC 64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+static inline void enter_lazy_tlb(struct mm_struct *mm,
+                                  struct task_struct *tsk)
+{
+}
+
+/*
+ * The proto-VSID space has 2^35 - 1 segments available for user mappings.
+ * Each segment contains 2^28 bytes.  Each context maps 2^44 bytes,
+ * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
+ */
+#define NO_CONTEXT      0
+#define MAX_CONTEXT     ((1UL << 19) - 1)
+
+extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
+extern void destroy_context(struct mm_struct *mm);
+
+extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
+extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
+
+/*
+ * switch_mm is the entry point called from the architecture independent
+ * code in kernel/sched.c
+ */
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask))
+                cpu_set(smp_processor_id(), next->cpu_vm_mask);
+
+        /* No need to flush userspace segments if the mm doesnt change */
+        if (prev == next)
+                return;
+
+#ifdef CONFIG_ALTIVEC
+        if (cpu_has_feature(CPU_FTR_ALTIVEC))
+                asm volatile ("dssall");
+#endif /* CONFIG_ALTIVEC */
+
+        if (cpu_has_feature(CPU_FTR_SLB))
+                switch_slb(tsk, next);
+        else
+                switch_stab(tsk, next);
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        switch_mm(prev, next, current);
+        local_irq_restore(flags);
+}
+
+#endif /* CONFIG_PPC64 */
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_MMU_CONTEXT_H */
diff --git a/arch/powerpc/include/asm/mmzone.h b/arch/powerpc/include/asm/mmzone.h
new file mode 100644
index 000000000000..19f299b7e256
--- /dev/null
+++ b/arch/powerpc/include/asm/mmzone.h
@@ -0,0 +1,47 @@
+/*
+ * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
+ *
+ * PowerPC64 port:
+ * Copyright (C) 2002 Anton Blanchard, IBM Corp.
+ */
+#ifndef _ASM_MMZONE_H_
+#define _ASM_MMZONE_H_
+#ifdef __KERNEL__
+
+
+/*
+ * generic non-linear memory support:
+ *
+ * 1) we will not split memory into more chunks than will fit into the
+ *    flags field of the struct page
+ */
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+
+extern struct pglist_data *node_data[];
+/*
+ * Return a pointer to the node data for node n.
+ */
+#define NODE_DATA(nid)          (node_data[nid])
+
+/*
+ * Following are specific to this numa platform.
+ */
+
+extern int numa_cpu_lookup_table[];
+extern cpumask_t numa_cpumask_lookup_table[];
+#ifdef CONFIG_MEMORY_HOTPLUG
+extern unsigned long max_pfn;
+#endif
+
+/*
+ * Following are macros that each numa implmentation must define.
+ */
+
+#define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
+#define node_end_pfn(nid)       (NODE_DATA(nid)->node_end_pfn)
+
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_MMZONE_H_ */
diff --git a/arch/powerpc/include/asm/module.h b/arch/powerpc/include/asm/module.h
new file mode 100644
index 000000000000..e5f14b13ccf0
--- /dev/null
+++ b/arch/powerpc/include/asm/module.h
@@ -0,0 +1,77 @@
+#ifndef _ASM_POWERPC_MODULE_H
+#define _ASM_POWERPC_MODULE_H
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/list.h>
+#include <asm/bug.h>
+
+
+#ifndef __powerpc64__
+/*
+ * Thanks to Paul M for explaining this.
+ *
+ * PPC can only do rel jumps += 32MB, and often the kernel and other
+ * modules are furthur away than this.  So, we jump to a table of
+ * trampolines attached to the module (the Procedure Linkage Table)
+ * whenever that happens.
+ */
+
+struct ppc_plt_entry {
+        /* 16 byte jump instruction sequence (4 instructions) */
+        unsigned int jump[4];
+};
+#endif  /* __powerpc64__ */
+
+
+struct mod_arch_specific {
+#ifdef __powerpc64__
+        unsigned int stubs_section;     /* Index of stubs section in module */
+        unsigned int toc_section;       /* What section is the TOC? */
+#else
+        /* Indices of PLT sections within module. */
+        unsigned int core_plt_section;
+        unsigned int init_plt_section;
+#endif
+
+        /* List of BUG addresses, source line numbers and filenames */
+        struct list_head bug_list;
+        struct bug_entry *bug_table;
+        unsigned int num_bugs;
+};
+
+/*
+ * Select ELF headers.
+ * Make empty section for module_frob_arch_sections to expand.
+ */
+
+#ifdef __powerpc64__
+#    define Elf_Shdr    Elf64_Shdr
+#    define Elf_Sym     Elf64_Sym
+#    define Elf_Ehdr    Elf64_Ehdr
+#    ifdef MODULE
+        asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
+#    endif
+#else
+#    define Elf_Shdr    Elf32_Shdr
+#    define Elf_Sym     Elf32_Sym
+#    define Elf_Ehdr    Elf32_Ehdr
+#    ifdef MODULE
+        asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
+        asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
+#    endif      /* MODULE */
+#endif
+
+
+struct exception_table_entry;
+void sort_ex_table(struct exception_table_entry *start,
+                   struct exception_table_entry *finish);
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_MODULE_H */
diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
new file mode 100644
index 000000000000..c48a1658eeac
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc512x.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
+ *
+ * Description:
+ * MPC5121 Prototypes and definitions
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_MPC512x_H__
+#define __ASM_POWERPC_MPC512x_H__
+
+extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
+
+#endif /* __ASM_POWERPC_MPC512x_H__ */
+
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h
new file mode 100644
index 000000000000..81ef10b6b672
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -0,0 +1,295 @@
+/*
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+#endif /* __ASSEMBLY__ */
+
+#include <linux/suspend.h>
+
+/* Variants of the 5200(B) */
+#define MPC5200_SVR             0x80110010
+#define MPC5200_SVR_MASK        0xfffffff0
+#define MPC5200B_SVR            0x80110020
+#define MPC5200B_SVR_MASK       0xfffffff0
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set                             */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+        u32 mbar;               /* MMAP_CTRL + 0x00 */
+
+        u32 cs0_start;          /* MMAP_CTRL + 0x04 */
+        u32 cs0_stop;           /* MMAP_CTRL + 0x08 */
+        u32 cs1_start;          /* MMAP_CTRL + 0x0c */
+        u32 cs1_stop;           /* MMAP_CTRL + 0x10 */
+        u32 cs2_start;          /* MMAP_CTRL + 0x14 */
+        u32 cs2_stop;           /* MMAP_CTRL + 0x18 */
+        u32 cs3_start;          /* MMAP_CTRL + 0x1c */
+        u32 cs3_stop;           /* MMAP_CTRL + 0x20 */
+        u32 cs4_start;          /* MMAP_CTRL + 0x24 */
+        u32 cs4_stop;           /* MMAP_CTRL + 0x28 */
+        u32 cs5_start;          /* MMAP_CTRL + 0x2c */
+        u32 cs5_stop;           /* MMAP_CTRL + 0x30 */
+
+        u32 sdram0;             /* MMAP_CTRL + 0x34 */
+        u32 sdram1;             /* MMAP_CTRL + 0X38 */
+
+        u32 reserved[4];        /* MMAP_CTRL + 0x3c .. 0x48 */
+
+        u32 boot_start;         /* MMAP_CTRL + 0x4c */
+        u32 boot_stop;          /* MMAP_CTRL + 0x50 */
+
+        u32 ipbi_ws_ctrl;       /* MMAP_CTRL + 0x54 */
+
+        u32 cs6_start;          /* MMAP_CTRL + 0x58 */
+        u32 cs6_stop;           /* MMAP_CTRL + 0x5c */
+        u32 cs7_start;          /* MMAP_CTRL + 0x60 */
+        u32 cs7_stop;           /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+        u32 mode;               /* SDRAM + 0x00 */
+        u32 ctrl;               /* SDRAM + 0x04 */
+        u32 config1;            /* SDRAM + 0x08 */
+        u32 config2;            /* SDRAM + 0x0c */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+        u32 taskBar;            /* SDMA + 0x00 */
+        u32 currentPointer;     /* SDMA + 0x04 */
+        u32 endPointer;         /* SDMA + 0x08 */
+        u32 variablePointer;    /* SDMA + 0x0c */
+
+        u8 IntVect1;            /* SDMA + 0x10 */
+        u8 IntVect2;            /* SDMA + 0x11 */
+        u16 PtdCntrl;           /* SDMA + 0x12 */
+
+        u32 IntPend;            /* SDMA + 0x14 */
+        u32 IntMask;            /* SDMA + 0x18 */
+
+        u16 tcr[16];            /* SDMA + 0x1c .. 0x3a */
+
+        u8 ipr[32];             /* SDMA + 0x3c .. 0x5b */
+
+        u32 cReqSelect;         /* SDMA + 0x5c */
+        u32 task_size0;         /* SDMA + 0x60 */
+        u32 task_size1;         /* SDMA + 0x64 */
+        u32 MDEDebug;           /* SDMA + 0x68 */
+        u32 ADSDebug;           /* SDMA + 0x6c */
+        u32 Value1;             /* SDMA + 0x70 */
+        u32 Value2;             /* SDMA + 0x74 */
+        u32 Control;            /* SDMA + 0x78 */
+        u32 Status;             /* SDMA + 0x7c */
+        u32 PTDDebug;           /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+        u32 mode;               /* GPTx + 0x00 */
+        u32 count;              /* GPTx + 0x04 */
+        u32 pwm;                /* GPTx + 0x08 */
+        u32 status;             /* GPTx + 0X0c */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+        u32 port_config;        /* GPIO + 0x00 */
+        u32 simple_gpioe;       /* GPIO + 0x04 */
+        u32 simple_ode;         /* GPIO + 0x08 */
+        u32 simple_ddr;         /* GPIO + 0x0c */
+        u32 simple_dvo;         /* GPIO + 0x10 */
+        u32 simple_ival;        /* GPIO + 0x14 */
+        u8 outo_gpioe;          /* GPIO + 0x18 */
+        u8 reserved1[3];        /* GPIO + 0x19 */
+        u8 outo_dvo;            /* GPIO + 0x1c */
+        u8 reserved2[3];        /* GPIO + 0x1d */
+        u8 sint_gpioe;          /* GPIO + 0x20 */
+        u8 reserved3[3];        /* GPIO + 0x21 */
+        u8 sint_ode;            /* GPIO + 0x24 */
+        u8 reserved4[3];        /* GPIO + 0x25 */
+        u8 sint_ddr;            /* GPIO + 0x28 */
+        u8 reserved5[3];        /* GPIO + 0x29 */
+        u8 sint_dvo;            /* GPIO + 0x2c */
+        u8 reserved6[3];        /* GPIO + 0x2d */
+        u8 sint_inten;          /* GPIO + 0x30 */
+        u8 reserved7[3];        /* GPIO + 0x31 */
+        u16 sint_itype;         /* GPIO + 0x34 */
+        u16 reserved8;          /* GPIO + 0x36 */
+        u8 gpio_control;        /* GPIO + 0x38 */
+        u8 reserved9[3];        /* GPIO + 0x39 */
+        u8 sint_istat;          /* GPIO + 0x3c */
+        u8 sint_ival;           /* GPIO + 0x3d */
+        u8 bus_errs;            /* GPIO + 0x3e */
+        u8 reserved10;          /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
+#define MPC52xx_GPIO_PCI_DIS                    (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+        u8 wkup_gpioe;          /* GPIO_WKUP + 0x00 */
+        u8 reserved1[3];        /* GPIO_WKUP + 0x03 */
+        u8 wkup_ode;            /* GPIO_WKUP + 0x04 */
+        u8 reserved2[3];        /* GPIO_WKUP + 0x05 */
+        u8 wkup_ddr;            /* GPIO_WKUP + 0x08 */
+        u8 reserved3[3];        /* GPIO_WKUP + 0x09 */
+        u8 wkup_dvo;            /* GPIO_WKUP + 0x0C */
+        u8 reserved4[3];        /* GPIO_WKUP + 0x0D */
+        u8 wkup_inten;          /* GPIO_WKUP + 0x10 */
+        u8 reserved5[3];        /* GPIO_WKUP + 0x11 */
+        u8 wkup_iinten;         /* GPIO_WKUP + 0x14 */
+        u8 reserved6[3];        /* GPIO_WKUP + 0x15 */
+        u16 wkup_itype;         /* GPIO_WKUP + 0x18 */
+        u8 reserved7[2];        /* GPIO_WKUP + 0x1A */
+        u8 wkup_maste;          /* GPIO_WKUP + 0x1C */
+        u8 reserved8[3];        /* GPIO_WKUP + 0x1D */
+        u8 wkup_ival;           /* GPIO_WKUP + 0x20 */
+        u8 reserved9[3];        /* GPIO_WKUP + 0x21 */
+        u8 wkup_istat;          /* GPIO_WKUP + 0x24 */
+        u8 reserved10[3];       /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+        u8 reserved[0x40];
+        u32 config;             /* XLB + 0x40 */
+        u32 version;            /* XLB + 0x44 */
+        u32 status;             /* XLB + 0x48 */
+        u32 int_enable;         /* XLB + 0x4c */
+        u32 addr_capture;       /* XLB + 0x50 */
+        u32 bus_sig_capture;    /* XLB + 0x54 */
+        u32 addr_timeout;       /* XLB + 0x58 */
+        u32 data_timeout;       /* XLB + 0x5c */
+        u32 bus_act_timeout;    /* XLB + 0x60 */
+        u32 master_pri_enable;  /* XLB + 0x64 */
+        u32 master_priority;    /* XLB + 0x68 */
+        u32 base_address;       /* XLB + 0x6c */
+        u32 snoop_window;       /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS           (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP           (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+        u32 jtag_id;            /* CDM + 0x00  reg0 read only */
+        u32 rstcfg;             /* CDM + 0x04  reg1 read only */
+        u32 breadcrumb;         /* CDM + 0x08  reg2 */
+
+        u8 mem_clk_sel;         /* CDM + 0x0c  reg3 byte0 */
+        u8 xlb_clk_sel;         /* CDM + 0x0d  reg3 byte1 read only */
+        u8 ipb_clk_sel;         /* CDM + 0x0e  reg3 byte2 */
+        u8 pci_clk_sel;         /* CDM + 0x0f  reg3 byte3 */
+
+        u8 ext_48mhz_en;        /* CDM + 0x10  reg4 byte0 */
+        u8 fd_enable;           /* CDM + 0x11  reg4 byte1 */
+        u16 fd_counters;        /* CDM + 0x12  reg4 byte2,3 */
+
+        u32 clk_enables;        /* CDM + 0x14  reg5 */
+
+        u8 osc_disable;         /* CDM + 0x18  reg6 byte0 */
+        u8 reserved0[3];        /* CDM + 0x19  reg6 byte1,2,3 */
+
+        u8 ccs_sleep_enable;    /* CDM + 0x1c  reg7 byte0 */
+        u8 osc_sleep_enable;    /* CDM + 0x1d  reg7 byte1 */
+        u8 reserved1;           /* CDM + 0x1e  reg7 byte2 */
+        u8 ccs_qreq_test;       /* CDM + 0x1f  reg7 byte3 */
+
+        u8 soft_reset;          /* CDM + 0x20  u8 byte0 */
+        u8 no_ckstp;            /* CDM + 0x21  u8 byte0 */
+        u8 reserved2[2];        /* CDM + 0x22  u8 byte1,2,3 */
+
+        u8 pll_lock;            /* CDM + 0x24  reg9 byte0 */
+        u8 pll_looselock;       /* CDM + 0x25  reg9 byte1 */
+        u8 pll_sm_lockwin;      /* CDM + 0x26  reg9 byte2 */
+        u8 reserved3;           /* CDM + 0x27  reg9 byte3 */
+
+        u16 reserved4;          /* CDM + 0x28  reg10 byte0,1 */
+        u16 mclken_div_psc1;    /* CDM + 0x2a  reg10 byte2,3 */
+
+        u16 reserved5;          /* CDM + 0x2c  reg11 byte0,1 */
+        u16 mclken_div_psc2;    /* CDM + 0x2e  reg11 byte2,3 */
+
+        u16 reserved6;          /* CDM + 0x30  reg12 byte0,1 */
+        u16 mclken_div_psc3;    /* CDM + 0x32  reg12 byte2,3 */
+
+        u16 reserved7;          /* CDM + 0x34  reg13 byte0,1 */
+        u16 mclken_div_psc6;    /* CDM + 0x36  reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx sysdev                                             */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+/* mpc52xx_common.c */
+extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
+extern void mpc5200_setup_xlb_arbiter(void);
+extern void mpc52xx_declare_of_platform_devices(void);
+extern void mpc52xx_map_common_devices(void);
+extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
+extern void mpc52xx_restart(char *cmd);
+
+/* mpc52xx_pic.c */
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+/* mpc52xx_pci.c */
+#ifdef CONFIG_PCI
+extern int __init mpc52xx_add_bridge(struct device_node *node);
+extern void __init mpc52xx_setup_pci(void);
+#else
+static inline void mpc52xx_setup_pci(void) { }
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PM
+struct mpc52xx_suspend {
+        void (*board_suspend_prepare)(void __iomem *mbar);
+        void (*board_resume_finish)(void __iomem *mbar);
+};
+
+extern struct mpc52xx_suspend mpc52xx_suspend;
+extern int __init mpc52xx_pm_init(void);
+extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
+
+#ifdef CONFIG_PPC_LITE5200
+extern int __init lite5200_pm_init(void);
+
+/* lite5200 calls mpc5200 suspend functions, so here they are */
+extern int mpc52xx_pm_prepare(void);
+extern int mpc52xx_pm_enter(suspend_state_t);
+extern void mpc52xx_pm_finish(void);
+extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
+#endif
+#endif /* CONFIG_PM */
+
+#endif /* __ASM_POWERPC_MPC52xx_H__ */
+
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
new file mode 100644
index 000000000000..8917ed630565
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -0,0 +1,276 @@
+/*
+ * include/asm-ppc/mpc52xx_psc.h
+ *
+ * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
+ * PSCs. Theses are shared between multiple drivers since a PSC can be
+ * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based/Extracted from some header of the 2.4 originally written by
+ * Dale Farnsworth <dfarnsworth@mvista.com>
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_MPC52xx_PSC_H__
+#define __ASM_MPC52xx_PSC_H__
+
+#include <asm/types.h>
+
+/* Max number of PSCs */
+#define MPC52xx_PSC_MAXNUM      6
+
+/* Programmable Serial Controller (PSC) status register bits */
+#define MPC52xx_PSC_SR_CDE      0x0080
+#define MPC52xx_PSC_SR_RXRDY    0x0100
+#define MPC52xx_PSC_SR_RXFULL   0x0200
+#define MPC52xx_PSC_SR_TXRDY    0x0400
+#define MPC52xx_PSC_SR_TXEMP    0x0800
+#define MPC52xx_PSC_SR_OE       0x1000
+#define MPC52xx_PSC_SR_PE       0x2000
+#define MPC52xx_PSC_SR_FE       0x4000
+#define MPC52xx_PSC_SR_RB       0x8000
+
+/* PSC Command values */
+#define MPC52xx_PSC_RX_ENABLE           0x0001
+#define MPC52xx_PSC_RX_DISABLE          0x0002
+#define MPC52xx_PSC_TX_ENABLE           0x0004
+#define MPC52xx_PSC_TX_DISABLE          0x0008
+#define MPC52xx_PSC_SEL_MODE_REG_1      0x0010
+#define MPC52xx_PSC_RST_RX              0x0020
+#define MPC52xx_PSC_RST_TX              0x0030
+#define MPC52xx_PSC_RST_ERR_STAT        0x0040
+#define MPC52xx_PSC_RST_BRK_CHG_INT     0x0050
+#define MPC52xx_PSC_START_BRK           0x0060
+#define MPC52xx_PSC_STOP_BRK            0x0070
+
+/* PSC TxRx FIFO status bits */
+#define MPC52xx_PSC_RXTX_FIFO_ERR       0x0040
+#define MPC52xx_PSC_RXTX_FIFO_UF        0x0020
+#define MPC52xx_PSC_RXTX_FIFO_OF        0x0010
+#define MPC52xx_PSC_RXTX_FIFO_FR        0x0008
+#define MPC52xx_PSC_RXTX_FIFO_FULL      0x0004
+#define MPC52xx_PSC_RXTX_FIFO_ALARM     0x0002
+#define MPC52xx_PSC_RXTX_FIFO_EMPTY     0x0001
+
+/* PSC interrupt status/mask bits */
+#define MPC52xx_PSC_IMR_TXRDY           0x0100
+#define MPC52xx_PSC_IMR_RXRDY           0x0200
+#define MPC52xx_PSC_IMR_DB              0x0400
+#define MPC52xx_PSC_IMR_TXEMP           0x0800
+#define MPC52xx_PSC_IMR_ORERR           0x1000
+#define MPC52xx_PSC_IMR_IPC             0x8000
+
+/* PSC input port change bit */
+#define MPC52xx_PSC_CTS                 0x01
+#define MPC52xx_PSC_DCD                 0x02
+#define MPC52xx_PSC_D_CTS               0x10
+#define MPC52xx_PSC_D_DCD               0x20
+
+/* PSC mode fields */
+#define MPC52xx_PSC_MODE_5_BITS                 0x00
+#define MPC52xx_PSC_MODE_6_BITS                 0x01
+#define MPC52xx_PSC_MODE_7_BITS                 0x02
+#define MPC52xx_PSC_MODE_8_BITS                 0x03
+#define MPC52xx_PSC_MODE_BITS_MASK              0x03
+#define MPC52xx_PSC_MODE_PAREVEN                0x00
+#define MPC52xx_PSC_MODE_PARODD                 0x04
+#define MPC52xx_PSC_MODE_PARFORCE               0x08
+#define MPC52xx_PSC_MODE_PARNONE                0x10
+#define MPC52xx_PSC_MODE_ERR                    0x20
+#define MPC52xx_PSC_MODE_FFULL                  0x40
+#define MPC52xx_PSC_MODE_RXRTS                  0x80
+
+#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS        0x00
+#define MPC52xx_PSC_MODE_ONE_STOP               0x07
+#define MPC52xx_PSC_MODE_TWO_STOP               0x0f
+
+#define MPC52xx_PSC_RFNUM_MASK  0x01ff
+
+#define MPC52xx_PSC_SICR_DTS1                   (1 << 29)
+#define MPC52xx_PSC_SICR_SHDR                   (1 << 28)
+#define MPC52xx_PSC_SICR_SIM_MASK               (0xf << 24)
+#define MPC52xx_PSC_SICR_SIM_UART               (0x0 << 24)
+#define MPC52xx_PSC_SICR_SIM_UART_DCD           (0x8 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_8            (0x1 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_16           (0x2 << 24)
+#define MPC52xx_PSC_SICR_SIM_AC97               (0x3 << 24)
+#define MPC52xx_PSC_SICR_SIM_SIR                (0x8 << 24)
+#define MPC52xx_PSC_SICR_SIM_SIR_DCD            (0xc << 24)
+#define MPC52xx_PSC_SICR_SIM_MIR                (0x5 << 24)
+#define MPC52xx_PSC_SICR_SIM_FIR                (0x6 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_24           (0x7 << 24)
+#define MPC52xx_PSC_SICR_SIM_CODEC_32           (0xf << 24)
+#define MPC52xx_PSC_SICR_GENCLK                 (1 << 23)
+#define MPC52xx_PSC_SICR_I2S                    (1 << 22)
+#define MPC52xx_PSC_SICR_CLKPOL                 (1 << 21)
+#define MPC52xx_PSC_SICR_SYNCPOL                (1 << 20)
+#define MPC52xx_PSC_SICR_CELLSLAVE              (1 << 19)
+#define MPC52xx_PSC_SICR_CELL2XCLK              (1 << 18)
+#define MPC52xx_PSC_SICR_ESAI                   (1 << 17)
+#define MPC52xx_PSC_SICR_ENAC97                 (1 << 16)
+#define MPC52xx_PSC_SICR_SPI                    (1 << 15)
+#define MPC52xx_PSC_SICR_MSTR                   (1 << 14)
+#define MPC52xx_PSC_SICR_CPOL                   (1 << 13)
+#define MPC52xx_PSC_SICR_CPHA                   (1 << 12)
+#define MPC52xx_PSC_SICR_USEEOF                 (1 << 11)
+#define MPC52xx_PSC_SICR_DISABLEEOF             (1 << 10)
+
+/* Structure of the hardware registers */
+struct mpc52xx_psc {
+        u8              mode;           /* PSC + 0x00 */
+        u8              reserved0[3];
+        union {                         /* PSC + 0x04 */
+                u16     status;
+                u16     clock_select;
+        } sr_csr;
+#define mpc52xx_psc_status      sr_csr.status
+#define mpc52xx_psc_clock_select sr_csr.clock_select
+        u16             reserved1;
+        u8              command;        /* PSC + 0x08 */
+        u8              reserved2[3];
+        union {                         /* PSC + 0x0c */
+                u8      buffer_8;
+                u16     buffer_16;
+                u32     buffer_32;
+        } buffer;
+#define mpc52xx_psc_buffer_8    buffer.buffer_8
+#define mpc52xx_psc_buffer_16   buffer.buffer_16
+#define mpc52xx_psc_buffer_32   buffer.buffer_32
+        union {                         /* PSC + 0x10 */
+                u8      ipcr;
+                u8      acr;
+        } ipcr_acr;
+#define mpc52xx_psc_ipcr        ipcr_acr.ipcr
+#define mpc52xx_psc_acr         ipcr_acr.acr
+        u8              reserved3[3];
+        union {                         /* PSC + 0x14 */
+                u16     isr;
+                u16     imr;
+        } isr_imr;
+#define mpc52xx_psc_isr         isr_imr.isr
+#define mpc52xx_psc_imr         isr_imr.imr
+        u16             reserved4;
+        u8              ctur;           /* PSC + 0x18 */
+        u8              reserved5[3];
+        u8              ctlr;           /* PSC + 0x1c */
+        u8              reserved6[3];
+        /* BitClkDiv field of CCR is byte swapped in
+         * the hardware for mpc5200/b compatibility */
+        u32             ccr;            /* PSC + 0x20 */
+        u32             ac97_slots;     /* PSC + 0x24 */
+        u32             ac97_cmd;       /* PSC + 0x28 */
+        u32             ac97_data;      /* PSC + 0x2c */
+        u8              ivr;            /* PSC + 0x30 */
+        u8              reserved8[3];
+        u8              ip;             /* PSC + 0x34 */
+        u8              reserved9[3];
+        u8              op1;            /* PSC + 0x38 */
+        u8              reserved10[3];
+        u8              op0;            /* PSC + 0x3c */
+        u8              reserved11[3];
+        u32             sicr;           /* PSC + 0x40 */
+        u8              ircr1;          /* PSC + 0x44 */
+        u8              reserved13[3];
+        u8              ircr2;          /* PSC + 0x44 */
+        u8              reserved14[3];
+        u8              irsdr;          /* PSC + 0x4c */
+        u8              reserved15[3];
+        u8              irmdr;          /* PSC + 0x50 */
+        u8              reserved16[3];
+        u8              irfdr;          /* PSC + 0x54 */
+        u8              reserved17[3];
+};
+
+struct mpc52xx_psc_fifo {
+        u16             rfnum;          /* PSC + 0x58 */
+        u16             reserved18;
+        u16             tfnum;          /* PSC + 0x5c */
+        u16             reserved19;
+        u32             rfdata;         /* PSC + 0x60 */
+        u16             rfstat;         /* PSC + 0x64 */
+        u16             reserved20;
+        u8              rfcntl;         /* PSC + 0x68 */
+        u8              reserved21[5];
+        u16             rfalarm;        /* PSC + 0x6e */
+        u16             reserved22;
+        u16             rfrptr;         /* PSC + 0x72 */
+        u16             reserved23;
+        u16             rfwptr;         /* PSC + 0x76 */
+        u16             reserved24;
+        u16             rflrfptr;       /* PSC + 0x7a */
+        u16             reserved25;
+        u16             rflwfptr;       /* PSC + 0x7e */
+        u32             tfdata;         /* PSC + 0x80 */
+        u16             tfstat;         /* PSC + 0x84 */
+        u16             reserved26;
+        u8              tfcntl;         /* PSC + 0x88 */
+        u8              reserved27[5];
+        u16             tfalarm;        /* PSC + 0x8e */
+        u16             reserved28;
+        u16             tfrptr;         /* PSC + 0x92 */
+        u16             reserved29;
+        u16             tfwptr;         /* PSC + 0x96 */
+        u16             reserved30;
+        u16             tflrfptr;       /* PSC + 0x9a */
+        u16             reserved31;
+        u16             tflwfptr;       /* PSC + 0x9e */
+};
+
+#define MPC512x_PSC_FIFO_RESET_SLICE    0x80
+#define MPC512x_PSC_FIFO_ENABLE_SLICE   0x01
+#define MPC512x_PSC_FIFO_ENABLE_DMA     0x04
+
+#define MPC512x_PSC_FIFO_EMPTY          0x1
+#define MPC512x_PSC_FIFO_FULL           0x2
+#define MPC512x_PSC_FIFO_ALARM          0x4
+#define MPC512x_PSC_FIFO_URERR          0x8
+#define MPC512x_PSC_FIFO_ORERR          0x01
+#define MPC512x_PSC_FIFO_MEMERROR       0x02
+
+struct mpc512x_psc_fifo {
+        u32             reserved1[10];
+        u32             txcmd;          /* PSC + 0x80 */
+        u32             txalarm;        /* PSC + 0x84 */
+        u32             txsr;           /* PSC + 0x88 */
+        u32             txisr;          /* PSC + 0x8c */
+        u32             tximr;          /* PSC + 0x90 */
+        u32             txcnt;          /* PSC + 0x94 */
+        u32             txptr;          /* PSC + 0x98 */
+        u32             txsz;           /* PSC + 0x9c */
+        u32             reserved2[7];
+        union {
+                u8      txdata_8;
+                u16     txdata_16;
+                u32     txdata_32;
+        } txdata;                       /* PSC + 0xbc */
+#define txdata_8 txdata.txdata_8
+#define txdata_16 txdata.txdata_16
+#define txdata_32 txdata.txdata_32
+        u32             rxcmd;          /* PSC + 0xc0 */
+        u32             rxalarm;        /* PSC + 0xc4 */
+        u32             rxsr;           /* PSC + 0xc8 */
+        u32             rxisr;          /* PSC + 0xcc */
+        u32             rximr;          /* PSC + 0xd0 */
+        u32             rxcnt;          /* PSC + 0xd4 */
+        u32             rxptr;          /* PSC + 0xd8 */
+        u32             rxsz;           /* PSC + 0xdc */
+        u32             reserved3[7];
+        union {
+                u8      rxdata_8;
+                u16     rxdata_16;
+                u32     rxdata_32;
+        } rxdata;                       /* PSC + 0xfc */
+#define rxdata_8 rxdata.rxdata_8
+#define rxdata_16 rxdata.rxdata_16
+#define rxdata_32 rxdata.rxdata_32
+};
+
+#endif  /* __ASM_MPC52xx_PSC_H__ */
diff --git a/arch/powerpc/include/asm/mpc6xx.h b/arch/powerpc/include/asm/mpc6xx.h
new file mode 100644
index 000000000000..effc2291beb2
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc6xx.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_POWERPC_MPC6xx_H
+#define __ASM_POWERPC_MPC6xx_H
+
+void mpc6xx_enter_standby(void);
+
+#endif
diff --git a/arch/powerpc/include/asm/mpc8260.h b/arch/powerpc/include/asm/mpc8260.h
new file mode 100644
index 000000000000..03317e1e6185
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8260.h
@@ -0,0 +1,25 @@
+/*
+ * Since there are many different boards and no standard configuration,
+ * we have a unique include file for each.  Rather than change every
+ * file that has to include MPC8260 configuration, they all include
+ * this one and the configuration switching is done here.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_MPC8260_H__
+#define __ASM_POWERPC_MPC8260_H__
+
+#define MPC82XX_BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
+
+#ifdef CONFIG_8260
+
+#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
+#include <platforms/82xx/pq2ads.h>
+#endif
+
+#ifdef CONFIG_PCI_8260
+#include <platforms/82xx/m82xx_pci.h>
+#endif
+
+#endif /* CONFIG_8260 */
+#endif /* !__ASM_POWERPC_MPC8260_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/mpc86xx.h b/arch/powerpc/include/asm/mpc86xx.h
new file mode 100644
index 000000000000..15f650f987e7
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc86xx.h
@@ -0,0 +1,33 @@
+/*
+ * MPC86xx definitions
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_MPC86xx_H__
+#define __ASM_POWERPC_MPC86xx_H__
+
+#include <asm/mmu.h>
+
+#ifdef CONFIG_PPC_86xx
+
+#define CPU0_BOOT_RELEASE 0x01000000
+#define CPU1_BOOT_RELEASE 0x02000000
+#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
+#define MCM_PORT_CONFIG_OFFSET 0x1010
+
+/* Offset from CCSRBAR */
+#define MPC86xx_MCM_OFFSET      (0x00000)
+#define MPC86xx_MCM_SIZE        (0x02000)
+
+#endif /* CONFIG_PPC_86xx */
+#endif /* __ASM_POWERPC_MPC86xx_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/mpc8xx.h b/arch/powerpc/include/asm/mpc8xx.h
new file mode 100644
index 000000000000..98f3c4f17328
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8xx.h
@@ -0,0 +1,12 @@
+/* This is the single file included by all MPC8xx build options.
+ * Since there are many different boards and no standard configuration,
+ * we have a unique include file for each.  Rather than change every
+ * file that has to include MPC8xx configuration, they all include
+ * this one and the configuration switching is done here.
+ */
+#ifndef __CONFIG_8xx_DEFS
+#define __CONFIG_8xx_DEFS
+
+extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
+
+#endif /* __CONFIG_8xx_DEFS */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
new file mode 100644
index 000000000000..fe566a348a86
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic.h
@@ -0,0 +1,481 @@
+#ifndef _ASM_POWERPC_MPIC_H
+#define _ASM_POWERPC_MPIC_H
+#ifdef __KERNEL__
+
+#include <linux/irq.h>
+#include <linux/sysdev.h>
+#include <asm/dcr.h>
+
+/*
+ * Global registers
+ */
+
+#define MPIC_GREG_BASE                  0x01000
+
+#define MPIC_GREG_FEATURE_0             0x00000
+#define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
+#define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
+#define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
+#define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
+#define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
+#define MPIC_GREG_FEATURE_1             0x00010
+#define MPIC_GREG_GLOBAL_CONF_0         0x00020
+#define         MPIC_GREG_GCONF_RESET                   0x80000000
+#define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
+#define         MPIC_GREG_GCONF_NO_BIAS                 0x10000000
+#define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
+#define         MPIC_GREG_GCONF_MCK                     0x08000000
+#define MPIC_GREG_GLOBAL_CONF_1         0x00030
+#define         MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
+#define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
+#define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)    \
+                        (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
+#define MPIC_GREG_VENDOR_0              0x00040
+#define MPIC_GREG_VENDOR_1              0x00050
+#define MPIC_GREG_VENDOR_2              0x00060
+#define MPIC_GREG_VENDOR_3              0x00070
+#define MPIC_GREG_VENDOR_ID             0x00080
+#define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
+#define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
+#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
+#define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
+#define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
+#define MPIC_GREG_PROCESSOR_INIT        0x00090
+#define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
+#define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
+#define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
+#define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
+#define MPIC_GREG_IPI_STRIDE            0x10
+#define MPIC_GREG_SPURIOUS              0x000e0
+#define MPIC_GREG_TIMER_FREQ            0x000f0
+
+/*
+ *
+ * Timer registers
+ */
+#define MPIC_TIMER_BASE                 0x01100
+#define MPIC_TIMER_STRIDE               0x40
+
+#define MPIC_TIMER_CURRENT_CNT          0x00000
+#define MPIC_TIMER_BASE_CNT             0x00010
+#define MPIC_TIMER_VECTOR_PRI           0x00020
+#define MPIC_TIMER_DESTINATION          0x00030
+
+/*
+ * Per-Processor registers
+ */
+
+#define MPIC_CPU_THISBASE               0x00000
+#define MPIC_CPU_BASE                   0x20000
+#define MPIC_CPU_STRIDE                 0x01000
+
+#define MPIC_CPU_IPI_DISPATCH_0         0x00040
+#define MPIC_CPU_IPI_DISPATCH_1         0x00050
+#define MPIC_CPU_IPI_DISPATCH_2         0x00060
+#define MPIC_CPU_IPI_DISPATCH_3         0x00070
+#define MPIC_CPU_IPI_DISPATCH_STRIDE    0x00010
+#define MPIC_CPU_CURRENT_TASK_PRI       0x00080
+#define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
+#define MPIC_CPU_WHOAMI                 0x00090
+#define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
+#define MPIC_CPU_INTACK                 0x000a0
+#define MPIC_CPU_EOI                    0x000b0
+#define MPIC_CPU_MCACK                  0x000c0
+
+/*
+ * Per-source registers
+ */
+
+#define MPIC_IRQ_BASE                   0x10000
+#define MPIC_IRQ_STRIDE                 0x00020
+#define MPIC_IRQ_VECTOR_PRI             0x00000
+#define         MPIC_VECPRI_MASK                        0x80000000
+#define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
+#define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
+#define         MPIC_VECPRI_PRIORITY_SHIFT              16
+#define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
+#define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
+#define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
+#define         MPIC_VECPRI_POLARITY_MASK               0x00800000
+#define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
+#define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
+#define         MPIC_VECPRI_SENSE_MASK                  0x00400000
+#define MPIC_IRQ_DESTINATION            0x00010
+
+#define MPIC_MAX_IRQ_SOURCES    2048
+#define MPIC_MAX_CPUS           32
+#define MPIC_MAX_ISU            32
+
+/*
+ * Tsi108 implementation of MPIC has many differences from the original one
+ */
+
+/*
+ * Global registers
+ */
+
+#define TSI108_GREG_BASE                0x00000
+#define TSI108_GREG_FEATURE_0           0x00000
+#define TSI108_GREG_GLOBAL_CONF_0       0x00004
+#define TSI108_GREG_VENDOR_ID           0x0000c
+#define TSI108_GREG_IPI_VECTOR_PRI_0    0x00204         /* Doorbell 0 */
+#define TSI108_GREG_IPI_STRIDE          0x0c
+#define TSI108_GREG_SPURIOUS            0x00010
+#define TSI108_GREG_TIMER_FREQ          0x00014
+
+/*
+ * Timer registers
+ */
+#define TSI108_TIMER_BASE               0x0030
+#define TSI108_TIMER_STRIDE             0x10
+#define TSI108_TIMER_CURRENT_CNT        0x00000
+#define TSI108_TIMER_BASE_CNT           0x00004
+#define TSI108_TIMER_VECTOR_PRI         0x00008
+#define TSI108_TIMER_DESTINATION        0x0000c
+
+/*
+ * Per-Processor registers
+ */
+#define TSI108_CPU_BASE                 0x00300
+#define TSI108_CPU_STRIDE               0x00040
+#define TSI108_CPU_IPI_DISPATCH_0       0x00200
+#define TSI108_CPU_IPI_DISPATCH_STRIDE  0x00000
+#define TSI108_CPU_CURRENT_TASK_PRI     0x00000
+#define TSI108_CPU_WHOAMI               0xffffffff
+#define TSI108_CPU_INTACK               0x00004
+#define TSI108_CPU_EOI                  0x00008
+#define TSI108_CPU_MCACK                0x00004 /* Doesn't really exist here */
+
+/*
+ * Per-source registers
+ */
+#define TSI108_IRQ_BASE                 0x00100
+#define TSI108_IRQ_STRIDE               0x00008
+#define TSI108_IRQ_VECTOR_PRI           0x00000
+#define TSI108_VECPRI_VECTOR_MASK       0x000000ff
+#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
+#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
+#define TSI108_VECPRI_SENSE_LEVEL       0x02000000
+#define TSI108_VECPRI_SENSE_EDGE        0x00000000
+#define TSI108_VECPRI_POLARITY_MASK     0x01000000
+#define TSI108_VECPRI_SENSE_MASK        0x02000000
+#define TSI108_IRQ_DESTINATION          0x00004
+
+/* weird mpic register indices and mask bits in the HW info array */
+enum {
+        MPIC_IDX_GREG_BASE = 0,
+        MPIC_IDX_GREG_FEATURE_0,
+        MPIC_IDX_GREG_GLOBAL_CONF_0,
+        MPIC_IDX_GREG_VENDOR_ID,
+        MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
+        MPIC_IDX_GREG_IPI_STRIDE,
+        MPIC_IDX_GREG_SPURIOUS,
+        MPIC_IDX_GREG_TIMER_FREQ,
+
+        MPIC_IDX_TIMER_BASE,
+        MPIC_IDX_TIMER_STRIDE,
+        MPIC_IDX_TIMER_CURRENT_CNT,
+        MPIC_IDX_TIMER_BASE_CNT,
+        MPIC_IDX_TIMER_VECTOR_PRI,
+        MPIC_IDX_TIMER_DESTINATION,
+
+        MPIC_IDX_CPU_BASE,
+        MPIC_IDX_CPU_STRIDE,
+        MPIC_IDX_CPU_IPI_DISPATCH_0,
+        MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
+        MPIC_IDX_CPU_CURRENT_TASK_PRI,
+        MPIC_IDX_CPU_WHOAMI,
+        MPIC_IDX_CPU_INTACK,
+        MPIC_IDX_CPU_EOI,
+        MPIC_IDX_CPU_MCACK,
+
+        MPIC_IDX_IRQ_BASE,
+        MPIC_IDX_IRQ_STRIDE,
+        MPIC_IDX_IRQ_VECTOR_PRI,
+
+        MPIC_IDX_VECPRI_VECTOR_MASK,
+        MPIC_IDX_VECPRI_POLARITY_POSITIVE,
+        MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
+        MPIC_IDX_VECPRI_SENSE_LEVEL,
+        MPIC_IDX_VECPRI_SENSE_EDGE,
+        MPIC_IDX_VECPRI_POLARITY_MASK,
+        MPIC_IDX_VECPRI_SENSE_MASK,
+        MPIC_IDX_IRQ_DESTINATION,
+        MPIC_IDX_END
+};
+
+
+#ifdef CONFIG_MPIC_U3_HT_IRQS
+/* Fixup table entry */
+struct mpic_irq_fixup
+{
+        u8 __iomem      *base;
+        u8 __iomem      *applebase;
+        u32             data;
+        unsigned int    index;
+};
+#endif /* CONFIG_MPIC_U3_HT_IRQS */
+
+
+enum mpic_reg_type {
+        mpic_access_mmio_le,
+        mpic_access_mmio_be,
+#ifdef CONFIG_PPC_DCR
+        mpic_access_dcr
+#endif
+};
+
+struct mpic_reg_bank {
+        u32 __iomem     *base;
+#ifdef CONFIG_PPC_DCR
+        dcr_host_t      dhost;
+#endif /* CONFIG_PPC_DCR */
+};
+
+struct mpic_irq_save {
+        u32             vecprio,
+                        dest;
+#ifdef CONFIG_MPIC_U3_HT_IRQS
+        u32             fixup_data;
+#endif
+};
+
+/* The instance data of a given MPIC */
+struct mpic
+{
+        /* The remapper for this MPIC */
+        struct irq_host         *irqhost;
+
+        /* The "linux" controller struct */
+        struct irq_chip         hc_irq;
+#ifdef CONFIG_MPIC_U3_HT_IRQS
+        struct irq_chip         hc_ht_irq;
+#endif
+#ifdef CONFIG_SMP
+        struct irq_chip         hc_ipi;
+#endif
+        const char              *name;
+        /* Flags */
+        unsigned int            flags;
+        /* How many irq sources in a given ISU */
+        unsigned int            isu_size;
+        unsigned int            isu_shift;
+        unsigned int            isu_mask;
+        unsigned int            irq_count;
+        /* Number of sources */
+        unsigned int            num_sources;
+        /* Number of CPUs */
+        unsigned int            num_cpus;
+        /* default senses array */
+        unsigned char           *senses;
+        unsigned int            senses_count;
+
+        /* vector numbers used for internal sources (ipi/timers) */
+        unsigned int            ipi_vecs[4];
+        unsigned int            timer_vecs[4];
+
+        /* Spurious vector to program into unused sources */
+        unsigned int            spurious_vec;
+
+#ifdef CONFIG_MPIC_U3_HT_IRQS
+        /* The fixup table */
+        struct mpic_irq_fixup   *fixups;
+        spinlock_t              fixup_lock;
+#endif
+
+        /* Register access method */
+        enum mpic_reg_type      reg_type;
+
+        /* The various ioremap'ed bases */
+        struct mpic_reg_bank    gregs;
+        struct mpic_reg_bank    tmregs;
+        struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
+        struct mpic_reg_bank    isus[MPIC_MAX_ISU];
+
+        /* Protected sources */
+        unsigned long           *protected;
+
+#ifdef CONFIG_MPIC_WEIRD
+        /* Pointer to HW info array */
+        u32                     *hw_set;
+#endif
+
+#ifdef CONFIG_PCI_MSI
+        spinlock_t              bitmap_lock;
+        unsigned long           *hwirq_bitmap;
+#endif
+
+#ifdef CONFIG_MPIC_BROKEN_REGREAD
+        u32                     isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
+#endif
+
+        /* link */
+        struct mpic             *next;
+
+        struct sys_device       sysdev;
+
+#ifdef CONFIG_PM
+        struct mpic_irq_save    *save_data;
+#endif
+};
+
+/*
+ * MPIC flags (passed to mpic_alloc)
+ *
+ * The top 4 bits contain an MPIC bhw id that is used to index the
+ * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
+ * Note setting any ID (leaving those bits to 0) means standard MPIC
+ */
+
+/* This is the primary controller, only that one has IPIs and
+ * has afinity control. A non-primary MPIC always uses CPU0
+ * registers only
+ */
+#define MPIC_PRIMARY                    0x00000001
+
+/* Set this for a big-endian MPIC */
+#define MPIC_BIG_ENDIAN                 0x00000002
+/* Broken U3 MPIC */
+#define MPIC_U3_HT_IRQS                 0x00000004
+/* Broken IPI registers (autodetected) */
+#define MPIC_BROKEN_IPI                 0x00000008
+/* MPIC wants a reset */
+#define MPIC_WANTS_RESET                0x00000010
+/* Spurious vector requires EOI */
+#define MPIC_SPV_EOI                    0x00000020
+/* No passthrough disable */
+#define MPIC_NO_PTHROU_DIS              0x00000040
+/* DCR based MPIC */
+#define MPIC_USES_DCR                   0x00000080
+/* MPIC has 11-bit vector fields (or larger) */
+#define MPIC_LARGE_VECTORS              0x00000100
+/* Enable delivery of prio 15 interrupts as MCK instead of EE */
+#define MPIC_ENABLE_MCK                 0x00000200
+/* Disable bias among target selection, spread interrupts evenly */
+#define MPIC_NO_BIAS                    0x00000400
+/* Ignore NIRQS as reported by FRR */
+#define MPIC_BROKEN_FRR_NIRQS           0x00000800
+
+/* MPIC HW modification ID */
+#define MPIC_REGSET_MASK                0xf0000000
+#define MPIC_REGSET(val)                (((val) & 0xf ) << 28)
+#define MPIC_GET_REGSET(flags)          (((flags) >> 28) & 0xf)
+
+#define MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
+#define MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
+
+/* Allocate the controller structure and setup the linux irq descs
+ * for the range if interrupts passed in. No HW initialization is
+ * actually performed.
+ * 
+ * @phys_addr:  physial base address of the MPIC
+ * @flags:      flags, see constants above
+ * @isu_size:   number of interrupts in an ISU. Use 0 to use a
+ *              standard ISU-less setup (aka powermac)
+ * @irq_offset: first irq number to assign to this mpic
+ * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
+ *              to match the number of sources
+ * @ipi_offset: first irq number to assign to this mpic IPI sources,
+ *              used only on primary mpic
+ * @senses:     array of sense values
+ * @senses_num: number of entries in the array
+ *
+ * Note about the sense array. If none is passed, all interrupts are
+ * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
+ * case they are edge positive (and the array is ignored anyway).
+ * The values in the array start at the first source of the MPIC,
+ * that is senses[0] correspond to linux irq "irq_offset".
+ */
+extern struct mpic *mpic_alloc(struct device_node *node,
+                               phys_addr_t phys_addr,
+                               unsigned int flags,
+                               unsigned int isu_size,
+                               unsigned int irq_count,
+                               const char *name);
+
+/* Assign ISUs, to call before mpic_init()
+ *
+ * @mpic:       controller structure as returned by mpic_alloc()
+ * @isu_num:    ISU number
+ * @phys_addr:  physical address of the ISU
+ */
+extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
+                            phys_addr_t phys_addr);
+
+/* Set default sense codes
+ *
+ * @mpic:       controller
+ * @senses:     array of sense codes
+ * @count:      size of above array
+ *
+ * Optionally provide an array (indexed on hardware interrupt numbers
+ * for this MPIC) of default sense codes for the chip. Those are linux
+ * sense codes IRQ_TYPE_*
+ *
+ * The driver gets ownership of the pointer, don't dispose of it or
+ * anything like that. __init only.
+ */
+extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
+
+
+/* Initialize the controller. After this has been called, none of the above
+ * should be called again for this mpic
+ */
+extern void mpic_init(struct mpic *mpic);
+
+/*
+ * All of the following functions must only be used after the
+ * ISUs have been assigned and the controller fully initialized
+ * with mpic_init()
+ */
+
+
+/* Change the priority of an interrupt. Default is 8 for irqs and
+ * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
+ * IPI number is then the offset'ed (linux irq number mapped to the IPI)
+ */
+extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
+
+/* Setup a non-boot CPU */
+extern void mpic_setup_this_cpu(void);
+
+/* Clean up for kexec (or cpu offline or ...) */
+extern void mpic_teardown_this_cpu(int secondary);
+
+/* Get the current cpu priority for this cpu (0..15) */
+extern int mpic_cpu_get_priority(void);
+
+/* Set the current cpu priority for this cpu */
+extern void mpic_cpu_set_priority(int prio);
+
+/* Request IPIs on primary mpic */
+extern void mpic_request_ipis(void);
+
+/* Send an IPI (non offseted number 0..3) */
+extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
+
+/* Send a message (IPI) to a given target (cpu number or MSG_*) */
+void smp_mpic_message_pass(int target, int msg);
+
+/* Unmask a specific virq */
+extern void mpic_unmask_irq(unsigned int irq);
+/* Mask a specific virq */
+extern void mpic_mask_irq(unsigned int irq);
+/* EOI a specific virq */
+extern void mpic_end_irq(unsigned int irq);
+
+/* Fetch interrupt from a given mpic */
+extern unsigned int mpic_get_one_irq(struct mpic *mpic);
+/* This one gets from the primary mpic */
+extern unsigned int mpic_get_irq(void);
+/* Fetch Machine Check interrupt from primary mpic */
+extern unsigned int mpic_get_mcirq(void);
+
+/* Set the EPIC clock ratio */
+void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
+
+/* Enable/Disable EPIC serial interrupt mode */
+void mpic_set_serial_int(struct mpic *mpic, int enable);
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_MPIC_H */
diff --git a/arch/powerpc/include/asm/msgbuf.h b/arch/powerpc/include/asm/msgbuf.h
new file mode 100644
index 000000000000..dd76743c7537
--- /dev/null
+++ b/arch/powerpc/include/asm/msgbuf.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_POWERPC_MSGBUF_H
+#define _ASM_POWERPC_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for the PowerPC architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+#ifndef __powerpc64__
+        unsigned int    __unused1;
+#endif
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+#ifndef __powerpc64__
+        unsigned int    __unused2;
+#endif
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+#ifndef __powerpc64__
+        unsigned int    __unused3;
+#endif
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif  /* _ASM_POWERPC_MSGBUF_H */
diff --git a/arch/powerpc/include/asm/mutex.h b/arch/powerpc/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/powerpc/include/asm/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
new file mode 100644
index 000000000000..efde5ac82f7b
--- /dev/null
+++ b/arch/powerpc/include/asm/nvram.h
@@ -0,0 +1,139 @@
+/*
+ * NVRAM definitions and access functions.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_POWERPC_NVRAM_H
+#define _ASM_POWERPC_NVRAM_H
+
+#include <linux/errno.h>
+
+#define NVRW_CNT 0x20
+#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
+#define NVRAM_BLOCK_LEN 16
+#define NVRAM_MAX_REQ (2080/NVRAM_BLOCK_LEN)
+#define NVRAM_MIN_REQ (1056/NVRAM_BLOCK_LEN)
+
+#define NVRAM_AS0  0x74
+#define NVRAM_AS1  0x75
+#define NVRAM_DATA 0x77
+
+
+/* RTC Offsets */
+
+#define MOTO_RTC_SECONDS        0x1FF9
+#define MOTO_RTC_MINUTES        0x1FFA
+#define MOTO_RTC_HOURS          0x1FFB
+#define MOTO_RTC_DAY_OF_WEEK    0x1FFC
+#define MOTO_RTC_DAY_OF_MONTH   0x1FFD
+#define MOTO_RTC_MONTH          0x1FFE
+#define MOTO_RTC_YEAR           0x1FFF
+#define MOTO_RTC_CONTROLA       0x1FF8
+#define MOTO_RTC_CONTROLB       0x1FF9
+
+#define NVRAM_SIG_SP    0x02    /* support processor */
+#define NVRAM_SIG_OF    0x50    /* open firmware config */
+#define NVRAM_SIG_FW    0x51    /* general firmware */
+#define NVRAM_SIG_HW    0x52    /* hardware (VPD) */
+#define NVRAM_SIG_FLIP  0x5a    /* Apple flip/flop header */
+#define NVRAM_SIG_APPL  0x5f    /* Apple "system" (???) */
+#define NVRAM_SIG_SYS   0x70    /* system env vars */
+#define NVRAM_SIG_CFG   0x71    /* config data */
+#define NVRAM_SIG_ELOG  0x72    /* error log */
+#define NVRAM_SIG_VEND  0x7e    /* vendor defined */
+#define NVRAM_SIG_FREE  0x7f    /* Free space */
+#define NVRAM_SIG_OS    0xa0    /* OS defined */
+#define NVRAM_SIG_PANIC 0xa1    /* Apple OSX "panic" */
+
+/* If change this size, then change the size of NVNAME_LEN */
+struct nvram_header {
+        unsigned char signature;
+        unsigned char checksum;
+        unsigned short length;
+        char name[12];
+};
+
+#ifdef __KERNEL__
+
+#include <linux/list.h>
+
+struct nvram_partition {
+        struct list_head partition;
+        struct nvram_header header;
+        unsigned int index;
+};
+
+
+extern int nvram_write_error_log(char * buff, int length,
+                                         unsigned int err_type, unsigned int err_seq);
+extern int nvram_read_error_log(char * buff, int length,
+                                         unsigned int * err_type, unsigned int *err_seq);
+extern int nvram_clear_error_log(void);
+extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
+
+extern int pSeries_nvram_init(void);
+
+#ifdef CONFIG_MMIO_NVRAM
+extern int mmio_nvram_init(void);
+#else
+static inline int mmio_nvram_init(void)
+{
+        return -ENODEV;
+}
+#endif
+
+#endif /* __KERNEL__ */
+
+/* PowerMac specific nvram stuffs */
+
+enum {
+        pmac_nvram_OF,          /* Open Firmware partition */
+        pmac_nvram_XPRAM,       /* MacOS XPRAM partition */
+        pmac_nvram_NR           /* MacOS Name Registry partition */
+};
+
+#ifdef __KERNEL__
+/* Return partition offset in nvram */
+extern int      pmac_get_partition(int partition);
+
+/* Direct access to XPRAM on PowerMacs */
+extern u8       pmac_xpram_read(int xpaddr);
+extern void     pmac_xpram_write(int xpaddr, u8 data);
+
+/* Synchronize NVRAM */
+extern void     nvram_sync(void);
+
+/* Normal access to NVRAM */
+extern unsigned char nvram_read_byte(int i);
+extern void nvram_write_byte(unsigned char c, int i);
+#endif
+
+/* Some offsets in XPRAM */
+#define PMAC_XPRAM_MACHINE_LOC  0xe4
+#define PMAC_XPRAM_SOUND_VOLUME 0x08
+
+/* Machine location structure in PowerMac XPRAM */
+struct pmac_machine_location {
+        unsigned int    latitude;       /* 2+30 bit Fractional number */
+        unsigned int    longitude;      /* 2+30 bit Fractional number */
+        unsigned int    delta;          /* mix of GMT delta and DLS */
+};
+
+/*
+ * /dev/nvram ioctls
+ *
+ * Note that PMAC_NVRAM_GET_OFFSET is still supported, but is
+ * definitely obsolete. Do not use it if you can avoid it
+ */
+
+#define OBSOLETE_PMAC_NVRAM_GET_OFFSET \
+                                _IOWR('p', 0x40, int)
+
+#define IOC_NVRAM_GET_OFFSET    _IOWR('p', 0x42, int)   /* Get NVRAM partition offset */
+#define IOC_NVRAM_SYNC          _IO('p', 0x43)          /* Sync NVRAM image */
+
+#endif /* _ASM_POWERPC_NVRAM_H */
diff --git a/arch/powerpc/include/asm/of_device.h b/arch/powerpc/include/asm/of_device.h
new file mode 100644
index 000000000000..3c123990ca2e
--- /dev/null
+++ b/arch/powerpc/include/asm/of_device.h
@@ -0,0 +1,31 @@
+#ifndef _ASM_POWERPC_OF_DEVICE_H
+#define _ASM_POWERPC_OF_DEVICE_H
+#ifdef __KERNEL__
+
+#include <linux/device.h>
+#include <linux/of.h>
+
+/*
+ * The of_device is a kind of "base class" that is a superset of
+ * struct device for use by devices attached to an OF node and
+ * probed using OF properties.
+ */
+struct of_device
+{
+        struct device_node      *node;          /* to be obsoleted */
+        u64                     dma_mask;       /* DMA mask */
+        struct device           dev;            /* Generic device interface */
+};
+
+extern struct of_device *of_device_alloc(struct device_node *np,
+                                         const char *bus_id,
+                                         struct device *parent);
+
+extern int of_device_uevent(struct device *dev,
+                            struct kobj_uevent_env *env);
+
+/* This is just here during the transition */
+#include <linux/of_device.h>
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_OF_DEVICE_H */
diff --git a/arch/powerpc/include/asm/of_platform.h b/arch/powerpc/include/asm/of_platform.h
new file mode 100644
index 000000000000..18659ef72139
--- /dev/null
+++ b/arch/powerpc/include/asm/of_platform.h
@@ -0,0 +1,42 @@
+#ifndef _ASM_POWERPC_OF_PLATFORM_H
+#define _ASM_POWERPC_OF_PLATFORM_H
+/*
+ *    Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                       <benh@kernel.crashing.org>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+
+/* This is just here during the transition */
+#include <linux/of_platform.h>
+
+/* Platform drivers register/unregister */
+static inline int of_register_platform_driver(struct of_platform_driver *drv)
+{
+        return of_register_driver(drv, &of_platform_bus_type);
+}
+static inline void of_unregister_platform_driver(struct of_platform_driver *drv)
+{
+        of_unregister_driver(drv);
+}
+
+/* Platform devices and busses creation */
+extern struct of_device *of_platform_device_create(struct device_node *np,
+                                                   const char *bus_id,
+                                                   struct device *parent);
+/* pseudo "matches" value to not do deep probe */
+#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
+
+extern int of_platform_bus_probe(struct device_node *root,
+                                 const struct of_device_id *matches,
+                                 struct device *parent);
+
+extern struct of_device *of_find_device_by_phandle(phandle ph);
+
+extern void of_instantiate_rtc(void);
+
+#endif  /* _ASM_POWERPC_OF_PLATFORM_H */
diff --git a/arch/powerpc/include/asm/ohare.h b/arch/powerpc/include/asm/ohare.h
new file mode 100644
index 000000000000..0d030f9dea24
--- /dev/null
+++ b/arch/powerpc/include/asm/ohare.h
@@ -0,0 +1,54 @@
+#ifndef _ASM_POWERPC_OHARE_H
+#define _ASM_POWERPC_OHARE_H
+#ifdef __KERNEL__
+/*
+ * ohare.h: definitions for using the "O'Hare" I/O controller chip.
+ *
+ * Copyright (C) 1997 Paul Mackerras.
+ *
+ * BenH: Changed to match those of heathrow (but not all of them). Please
+ *       check if I didn't break anything (especially the media bay).
+ */
+
+/* offset from ohare base for feature control register */
+#define OHARE_MBCR      0x34
+#define OHARE_FCR       0x38
+
+/*
+ * Bits in feature control register.
+ * These were mostly derived by experiment on a powerbook 3400
+ * and may differ for other machines.
+ */
+#define OH_SCC_RESET            1
+#define OH_BAY_POWER_N          2       /* a guess */
+#define OH_BAY_PCI_ENABLE       4       /* a guess */
+#define OH_BAY_IDE_ENABLE       8
+#define OH_BAY_FLOPPY_ENABLE    0x10
+#define OH_IDE0_ENABLE          0x20
+#define OH_IDE0_RESET_N         0x40    /* a guess */
+#define OH_BAY_DEV_MASK         0x1c
+#define OH_BAY_RESET_N          0x80
+#define OH_IOBUS_ENABLE         0x100   /* IOBUS seems to be IDE */
+#define OH_SCC_ENABLE           0x200
+#define OH_MESH_ENABLE          0x400
+#define OH_FLOPPY_ENABLE        0x800
+#define OH_SCCA_IO              0x4000
+#define OH_SCCB_IO              0x8000
+#define OH_VIA_ENABLE           0x10000 /* Is apparently wrong, to be verified */
+#define OH_IDE1_RESET_N         0x800000
+
+/*
+ * Bits to set in the feature control register on PowerBooks.
+ */
+#define PBOOK_FEATURES          (OH_IDE_ENABLE | OH_SCC_ENABLE | \
+                                 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
+
+/*
+ * A magic value to put into the feature control register of the
+ * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
+ * Contributed by Harry Eaton.
+ */
+#define STARMAX_FEATURES        0xbeff7a
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_OHARE_H */
diff --git a/arch/powerpc/include/asm/oprofile_impl.h b/arch/powerpc/include/asm/oprofile_impl.h
new file mode 100644
index 000000000000..95035c602ba6
--- /dev/null
+++ b/arch/powerpc/include/asm/oprofile_impl.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
+ *
+ * Based on alpha version.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
+#define _ASM_POWERPC_OPROFILE_IMPL_H
+#ifdef __KERNEL__
+
+#define OP_MAX_COUNTER 8
+
+/* Per-counter configuration as set via oprofilefs.  */
+struct op_counter_config {
+        unsigned long enabled;
+        unsigned long event;
+        unsigned long count;
+        /* Classic doesn't support per-counter user/kernel selection */
+        unsigned long kernel;
+        unsigned long user;
+        unsigned long unit_mask;
+};
+
+/* System-wide configuration as set via oprofilefs.  */
+struct op_system_config {
+#ifdef CONFIG_PPC64
+        unsigned long mmcr0;
+        unsigned long mmcr1;
+        unsigned long mmcra;
+#endif
+        unsigned long enable_kernel;
+        unsigned long enable_user;
+};
+
+/* Per-arch configuration */
+struct op_powerpc_model {
+        int (*reg_setup) (struct op_counter_config *,
+                           struct op_system_config *,
+                           int num_counters);
+        int  (*cpu_setup) (struct op_counter_config *);
+        int  (*start) (struct op_counter_config *);
+        int  (*global_start) (struct op_counter_config *);
+        void (*stop) (void);
+        void (*global_stop) (void);
+        int (*sync_start)(void);
+        int (*sync_stop)(void);
+        void (*handle_interrupt) (struct pt_regs *,
+                                  struct op_counter_config *);
+        int num_counters;
+};
+
+extern struct op_powerpc_model op_model_fsl_emb;
+extern struct op_powerpc_model op_model_rs64;
+extern struct op_powerpc_model op_model_power4;
+extern struct op_powerpc_model op_model_7450;
+extern struct op_powerpc_model op_model_cell;
+extern struct op_powerpc_model op_model_pa6t;
+
+
+/* All the classic PPC parts use these */
+static inline unsigned int classic_ctr_read(unsigned int i)
+{
+        switch(i) {
+        case 0:
+                return mfspr(SPRN_PMC1);
+        case 1:
+                return mfspr(SPRN_PMC2);
+        case 2:
+                return mfspr(SPRN_PMC3);
+        case 3:
+                return mfspr(SPRN_PMC4);
+        case 4:
+                return mfspr(SPRN_PMC5);
+        case 5:
+                return mfspr(SPRN_PMC6);
+
+/* No PPC32 chip has more than 6 so far */
+#ifdef CONFIG_PPC64
+        case 6:
+                return mfspr(SPRN_PMC7);
+        case 7:
+                return mfspr(SPRN_PMC8);
+#endif
+        default:
+                return 0;
+        }
+}
+
+static inline void classic_ctr_write(unsigned int i, unsigned int val)
+{
+        switch(i) {
+        case 0:
+                mtspr(SPRN_PMC1, val);
+                break;
+        case 1:
+                mtspr(SPRN_PMC2, val);
+                break;
+        case 2:
+                mtspr(SPRN_PMC3, val);
+                break;
+        case 3:
+                mtspr(SPRN_PMC4, val);
+                break;
+        case 4:
+                mtspr(SPRN_PMC5, val);
+                break;
+        case 5:
+                mtspr(SPRN_PMC6, val);
+                break;
+
+/* No PPC32 chip has more than 6, yet */
+#ifdef CONFIG_PPC64
+        case 6:
+                mtspr(SPRN_PMC7, val);
+                break;
+        case 7:
+                mtspr(SPRN_PMC8, val);
+                break;
+#endif
+        default:
+                break;
+        }
+}
+
+
+extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h
new file mode 100644
index 000000000000..e482e5352e69
--- /dev/null
+++ b/arch/powerpc/include/asm/pSeries_reconfig.h
@@ -0,0 +1,29 @@
+#ifndef _PPC64_PSERIES_RECONFIG_H
+#define _PPC64_PSERIES_RECONFIG_H
+#ifdef __KERNEL__
+
+#include <linux/notifier.h>
+
+/*
+ * Use this API if your code needs to know about OF device nodes being
+ * added or removed on pSeries systems.
+ */
+
+#define PSERIES_RECONFIG_ADD            0x0001
+#define PSERIES_RECONFIG_REMOVE         0x0002
+#define PSERIES_DRCONF_MEM_ADD          0x0003
+#define PSERIES_DRCONF_MEM_REMOVE       0x0004
+
+#ifdef CONFIG_PPC_PSERIES
+extern int pSeries_reconfig_notifier_register(struct notifier_block *);
+extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
+#else /* !CONFIG_PPC_PSERIES */
+static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
+{
+        return 0;
+}
+static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
+#endif /* CONFIG_PPC_PSERIES */
+
+#endif /* __KERNEL__ */
+#endif /* _PPC64_PSERIES_RECONFIG_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
new file mode 100644
index 000000000000..6493a395508b
--- /dev/null
+++ b/arch/powerpc/include/asm/paca.h
@@ -0,0 +1,112 @@
+/*
+ * This control block defines the PACA which defines the processor
+ * specific data for each logical processor on the system.
+ * There are some pointers defined that are utilized by PLIC.
+ *
+ * C 2001 PPC 64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_PACA_H
+#define _ASM_POWERPC_PACA_H
+#ifdef __KERNEL__
+
+#include        <asm/types.h>
+#include        <asm/lppaca.h>
+#include        <asm/mmu.h>
+
+register struct paca_struct *local_paca asm("r13");
+
+#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
+extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
+/*
+ * Add standard checks that preemption cannot occur when using get_paca():
+ * otherwise the paca_struct it points to may be the wrong one just after.
+ */
+#define get_paca()      ((void) debug_smp_processor_id(), local_paca)
+#else
+#define get_paca()      local_paca
+#endif
+
+#define get_lppaca()    (get_paca()->lppaca_ptr)
+#define get_slb_shadow()        (get_paca()->slb_shadow_ptr)
+
+struct task_struct;
+
+/*
+ * Defines the layout of the paca.
+ *
+ * This structure is not directly accessed by firmware or the service
+ * processor.
+ */
+struct paca_struct {
+        /*
+         * Because hw_cpu_id, unlike other paca fields, is accessed
+         * routinely from other CPUs (from the IRQ code), we stick to
+         * read-only (after boot) fields in the first cacheline to
+         * avoid cacheline bouncing.
+         */
+
+        struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
+
+        /*
+         * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 
+         * load lock_token and paca_index with a single lwz
+         * instruction.  They must travel together and be properly
+         * aligned.
+         */
+        u16 lock_token;                 /* Constant 0x8000, used in locks */
+        u16 paca_index;                 /* Logical processor number */
+
+        u64 kernel_toc;                 /* Kernel TOC address */
+        u64 stab_real;                  /* Absolute address of segment table */
+        u64 stab_addr;                  /* Virtual address of segment table */
+        void *emergency_sp;             /* pointer to emergency stack */
+        u64 data_offset;                /* per cpu data offset */
+        s16 hw_cpu_id;                  /* Physical processor number */
+        u8 cpu_start;                   /* At startup, processor spins until */
+                                        /* this becomes non-zero. */
+        struct slb_shadow *slb_shadow_ptr;
+
+        /*
+         * Now, starting in cacheline 2, the exception save areas
+         */
+        /* used for most interrupts/exceptions */
+        u64 exgen[10] __attribute__((aligned(0x80)));
+        u64 exmc[10];           /* used for machine checks */
+        u64 exslb[10];          /* used for SLB/segment table misses
+                                 * on the linear mapping */
+
+        mm_context_t context;
+        u16 vmalloc_sllp;
+        u16 slb_cache_ptr;
+        u16 slb_cache[SLB_CACHE_ENTRIES];
+
+        /*
+         * then miscellaneous read-write fields
+         */
+        struct task_struct *__current;  /* Pointer to current */
+        u64 kstack;                     /* Saved Kernel stack addr */
+        u64 stab_rr;                    /* stab/slb round-robin counter */
+        u64 saved_r1;                   /* r1 save for RTAS calls */
+        u64 saved_msr;                  /* MSR saved here by enter_rtas */
+        u16 trap_save;                  /* Used when bad stack is encountered */
+        u8 soft_enabled;                /* irq soft-enable flag */
+        u8 hard_enabled;                /* set if irqs are enabled in MSR */
+        u8 io_sync;                     /* writel() needs spin_unlock sync */
+
+        /* Stuff for accurate time accounting */
+        u64 user_time;                  /* accumulated usermode TB ticks */
+        u64 system_time;                /* accumulated system TB ticks */
+        u64 startpurr;                  /* PURR/TB value snapshot */
+        u64 startspurr;                 /* SPURR value snapshot */
+};
+
+extern struct paca_struct paca[];
+extern void initialise_pacas(void);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_PACA_H */
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
new file mode 100644
index 000000000000..e088545cb3f5
--- /dev/null
+++ b/arch/powerpc/include/asm/page.h
@@ -0,0 +1,225 @@
+#ifndef _ASM_POWERPC_PAGE_H
+#define _ASM_POWERPC_PAGE_H
+
+/*
+ * Copyright (C) 2001,2005 IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/asm-compat.h>
+#include <asm/kdump.h>
+#include <asm/types.h>
+
+/*
+ * On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software
+ * page size. When using 64K pages however, whether we are really supporting
+ * 64K pages in HW or not is irrelevant to those definitions.
+ */
+#ifdef CONFIG_PPC_64K_PAGES
+#define PAGE_SHIFT              16
+#else
+#define PAGE_SHIFT              12
+#endif
+
+#define PAGE_SIZE               (ASM_CONST(1) << PAGE_SHIFT)
+
+/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
+#define __HAVE_ARCH_GATE_AREA           1
+
+/*
+ * Subtle: (1 << PAGE_SHIFT) is an int, not an unsigned long. So if we
+ * assign PAGE_MASK to a larger type it gets extended the way we want
+ * (i.e. with 1s in the high bits)
+ */
+#define PAGE_MASK      (~((1 << PAGE_SHIFT) - 1))
+
+/*
+ * KERNELBASE is the virtual address of the start of the kernel, it's often
+ * the same as PAGE_OFFSET, but _might not be_.
+ *
+ * The kdump dump kernel is one example where KERNELBASE != PAGE_OFFSET.
+ *
+ * PAGE_OFFSET is the virtual address of the start of lowmem.
+ *
+ * PHYSICAL_START is the physical address of the start of the kernel.
+ *
+ * MEMORY_START is the physical address of the start of lowmem.
+ *
+ * KERNELBASE, PAGE_OFFSET, and PHYSICAL_START are all configurable on
+ * ppc32 and based on how they are set we determine MEMORY_START.
+ *
+ * For the linear mapping the following equation should be true:
+ * KERNELBASE - PAGE_OFFSET = PHYSICAL_START - MEMORY_START
+ *
+ * Also, KERNELBASE >= PAGE_OFFSET and PHYSICAL_START >= MEMORY_START
+ *
+ * There are two was to determine a physical address from a virtual one:
+ * va = pa + PAGE_OFFSET - MEMORY_START
+ * va = pa + KERNELBASE - PHYSICAL_START
+ *
+ * If you want to know something's offset from the start of the kernel you
+ * should subtract KERNELBASE.
+ *
+ * If you want to test if something's a kernel address, use is_kernel_addr().
+ */
+
+#define KERNELBASE      ASM_CONST(CONFIG_KERNEL_START)
+#define PAGE_OFFSET     ASM_CONST(CONFIG_PAGE_OFFSET)
+#define LOAD_OFFSET     ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
+
+#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_FLATMEM)
+#ifndef __ASSEMBLY__
+extern phys_addr_t memstart_addr;
+extern phys_addr_t kernstart_addr;
+#endif
+#define PHYSICAL_START  kernstart_addr
+#define MEMORY_START    memstart_addr
+#else
+#define PHYSICAL_START  ASM_CONST(CONFIG_PHYSICAL_START)
+#define MEMORY_START    (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
+#endif
+
+#ifdef CONFIG_FLATMEM
+#define ARCH_PFN_OFFSET         (MEMORY_START >> PAGE_SHIFT)
+#define pfn_valid(pfn)          ((pfn) >= ARCH_PFN_OFFSET && (pfn) < (ARCH_PFN_OFFSET + max_mapnr))
+#endif
+
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define __va(x) ((void *)((unsigned long)(x) - PHYSICAL_START + KERNELBASE))
+#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE)
+
+/*
+ * Unfortunately the PLT is in the BSS in the PPC32 ELF ABI,
+ * and needs to be executable.  This means the whole heap ends
+ * up being executable.
+ */
+#define VM_DATA_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#define VM_DATA_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#ifdef __powerpc64__
+#include <asm/page_64.h>
+#else
+#include <asm/page_32.h>
+#endif
+
+/* align addr on a size boundary - adjust address up/down if needed */
+#define _ALIGN_UP(addr,size)    (((addr)+((size)-1))&(~((size)-1)))
+#define _ALIGN_DOWN(addr,size)  ((addr)&(~((size)-1)))
+
+/* align addr on a size boundary - adjust address up if needed */
+#define _ALIGN(addr,size)     _ALIGN_UP(addr,size)
+
+/*
+ * Don't compare things with KERNELBASE or PAGE_OFFSET to test for
+ * "kernelness", use is_kernel_addr() - it should do what you want.
+ */
+#define is_kernel_addr(x)       ((x) >= PAGE_OFFSET)
+
+#ifndef __ASSEMBLY__
+
+#undef STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+/* These are used to make use of C type-checking. */
+
+/* PTE level */
+typedef struct { pte_basic_t pte; } pte_t;
+#define pte_val(x)      ((x).pte)
+#define __pte(x)        ((pte_t) { (x) })
+
+/* 64k pages additionally define a bigger "real PTE" type that gathers
+ * the "second half" part of the PTE for pseudo 64k pages
+ */
+#ifdef CONFIG_PPC_64K_PAGES
+typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
+#else
+typedef struct { pte_t pte; } real_pte_t;
+#endif
+
+/* PMD level */
+#ifdef CONFIG_PPC64
+typedef struct { unsigned long pmd; } pmd_t;
+#define pmd_val(x)      ((x).pmd)
+#define __pmd(x)        ((pmd_t) { (x) })
+
+/* PUD level exusts only on 4k pages */
+#ifndef CONFIG_PPC_64K_PAGES
+typedef struct { unsigned long pud; } pud_t;
+#define pud_val(x)      ((x).pud)
+#define __pud(x)        ((pud_t) { (x) })
+#endif /* !CONFIG_PPC_64K_PAGES */
+#endif /* CONFIG_PPC64 */
+
+/* PGD level */
+typedef struct { unsigned long pgd; } pgd_t;
+#define pgd_val(x)      ((x).pgd)
+#define __pgd(x)        ((pgd_t) { (x) })
+
+/* Page protection bits */
+typedef struct { unsigned long pgprot; } pgprot_t;
+#define pgprot_val(x)   ((x).pgprot)
+#define __pgprot(x)     ((pgprot_t) { (x) })
+
+#else
+
+/*
+ * .. while these make it easier on the compiler
+ */
+
+typedef pte_basic_t pte_t;
+#define pte_val(x)      (x)
+#define __pte(x)        (x)
+
+#ifdef CONFIG_PPC_64K_PAGES
+typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
+#else
+typedef unsigned long real_pte_t;
+#endif
+
+
+#ifdef CONFIG_PPC64
+typedef unsigned long pmd_t;
+#define pmd_val(x)      (x)
+#define __pmd(x)        (x)
+
+#ifndef CONFIG_PPC_64K_PAGES
+typedef unsigned long pud_t;
+#define pud_val(x)      (x)
+#define __pud(x)        (x)
+#endif /* !CONFIG_PPC_64K_PAGES */
+#endif /* CONFIG_PPC64 */
+
+typedef unsigned long pgd_t;
+#define pgd_val(x)      (x)
+#define pgprot_val(x)   (x)
+
+typedef unsigned long pgprot_t;
+#define __pgd(x)        (x)
+#define __pgprot(x)     (x)
+
+#endif
+
+struct page;
+extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
+extern void copy_user_page(void *to, void *from, unsigned long vaddr,
+                struct page *p);
+extern int page_is_ram(unsigned long pfn);
+
+struct vm_area_struct;
+
+typedef struct page *pgtable_t;
+
+#include <asm-generic/memory_model.h>
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PAGE_H */
diff --git a/arch/powerpc/include/asm/page_32.h b/arch/powerpc/include/asm/page_32.h
new file mode 100644
index 000000000000..ebfae530a379
--- /dev/null
+++ b/arch/powerpc/include/asm/page_32.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_POWERPC_PAGE_32_H
+#define _ASM_POWERPC_PAGE_32_H
+
+#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
+#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
+#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
+#endif
+#endif
+
+#define VM_DATA_DEFAULT_FLAGS   VM_DATA_DEFAULT_FLAGS32
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+#endif
+
+#ifndef __ASSEMBLY__
+/*
+ * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
+ * physical addressing.  For now this just the IBM PPC440.
+ */
+#ifdef CONFIG_PTE_64BIT
+typedef unsigned long long pte_basic_t;
+#define PTE_SHIFT       (PAGE_SHIFT - 3)        /* 512 ptes per page */
+#else
+typedef unsigned long pte_basic_t;
+#define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
+#endif
+
+struct page;
+extern void clear_pages(void *page, int order);
+static inline void clear_page(void *page) { clear_pages(page, 0); }
+extern void copy_page(void *to, void *from);
+
+#include <asm-generic/page.h>
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PAGE_32_H */
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
new file mode 100644
index 000000000000..043bfdfe4f73
--- /dev/null
+++ b/arch/powerpc/include/asm/page_64.h
@@ -0,0 +1,185 @@
+#ifndef _ASM_POWERPC_PAGE_64_H
+#define _ASM_POWERPC_PAGE_64_H
+
+/*
+ * Copyright (C) 2001 PPC64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
+ * specific, every notion of page number shared with the firmware, TCEs,
+ * iommu, etc... still uses a page size of 4K.
+ */
+#define HW_PAGE_SHIFT           12
+#define HW_PAGE_SIZE            (ASM_CONST(1) << HW_PAGE_SHIFT)
+#define HW_PAGE_MASK            (~(HW_PAGE_SIZE-1))
+
+/*
+ * PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
+ * HW_PAGE_SHIFT, that is 4K pages.
+ */
+#define PAGE_FACTOR             (PAGE_SHIFT - HW_PAGE_SHIFT)
+
+/* Segment size; normal 256M segments */
+#define SID_SHIFT               28
+#define SID_MASK                ASM_CONST(0xfffffffff)
+#define ESID_MASK               0xfffffffff0000000UL
+#define GET_ESID(x)             (((x) >> SID_SHIFT) & SID_MASK)
+
+/* 1T segments */
+#define SID_SHIFT_1T            40
+#define SID_MASK_1T             0xffffffUL
+#define ESID_MASK_1T            0xffffff0000000000UL
+#define GET_ESID_1T(x)          (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
+
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+
+typedef unsigned long pte_basic_t;
+
+static __inline__ void clear_page(void *addr)
+{
+        unsigned long lines, line_size;
+
+        line_size = ppc64_caches.dline_size;
+        lines = ppc64_caches.dlines_per_page;
+
+        __asm__ __volatile__(
+        "mtctr  %1      # clear_page\n\
+1:      dcbz    0,%0\n\
+        add     %0,%0,%3\n\
+        bdnz+   1b"
+        : "=r" (addr)
+        : "r" (lines), "0" (addr), "r" (line_size)
+        : "ctr", "memory");
+}
+
+extern void copy_4K_page(void *to, void *from);
+
+#ifdef CONFIG_PPC_64K_PAGES
+static inline void copy_page(void *to, void *from)
+{
+        unsigned int i;
+        for (i=0; i < (1 << (PAGE_SHIFT - 12)); i++) {
+                copy_4K_page(to, from);
+                to += 4096;
+                from += 4096;
+        }
+}
+#else /* CONFIG_PPC_64K_PAGES */
+static inline void copy_page(void *to, void *from)
+{
+        copy_4K_page(to, from);
+}
+#endif /* CONFIG_PPC_64K_PAGES */
+
+/* Log 2 of page table size */
+extern u64 ppc64_pft_size;
+
+/* Large pages size */
+#ifdef CONFIG_HUGETLB_PAGE
+extern unsigned int HPAGE_SHIFT;
+#else
+#define HPAGE_SHIFT PAGE_SHIFT
+#endif
+#define HPAGE_SIZE              ((1UL) << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+#define HUGE_MAX_HSTATE         3
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PPC_MM_SLICES
+
+#define SLICE_LOW_SHIFT         28
+#define SLICE_HIGH_SHIFT        40
+
+#define SLICE_LOW_TOP           (0x100000000ul)
+#define SLICE_NUM_LOW           (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
+#define SLICE_NUM_HIGH          (PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
+
+#define GET_LOW_SLICE_INDEX(addr)       ((addr) >> SLICE_LOW_SHIFT)
+#define GET_HIGH_SLICE_INDEX(addr)      ((addr) >> SLICE_HIGH_SHIFT)
+
+#ifndef __ASSEMBLY__
+
+struct slice_mask {
+        u16 low_slices;
+        u16 high_slices;
+};
+
+struct mm_struct;
+
+extern unsigned long slice_get_unmapped_area(unsigned long addr,
+                                             unsigned long len,
+                                             unsigned long flags,
+                                             unsigned int psize,
+                                             int topdown,
+                                             int use_cache);
+
+extern unsigned int get_slice_psize(struct mm_struct *mm,
+                                    unsigned long addr);
+
+extern void slice_init_context(struct mm_struct *mm, unsigned int psize);
+extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
+extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
+                                  unsigned long len, unsigned int psize);
+
+#define slice_mm_new_context(mm)        ((mm)->context.id == 0)
+
+#endif /* __ASSEMBLY__ */
+#else
+#define slice_init()
+#define get_slice_psize(mm, addr)       ((mm)->context.user_psize)
+#define slice_set_user_psize(mm, psize)         \
+do {                                            \
+        (mm)->context.user_psize = (psize);     \
+        (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
+} while (0)
+#define slice_set_range_psize(mm, start, len, psize)    \
+        slice_set_user_psize((mm), (psize))
+#define slice_mm_new_context(mm)        1
+#endif /* CONFIG_PPC_MM_SLICES */
+
+#ifdef CONFIG_HUGETLB_PAGE
+
+#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+
+#endif /* !CONFIG_HUGETLB_PAGE */
+
+#ifdef MODULE
+#define __page_aligned __attribute__((__aligned__(PAGE_SIZE)))
+#else
+#define __page_aligned \
+        __attribute__((__aligned__(PAGE_SIZE), \
+                __section__(".data.page_aligned")))
+#endif
+
+#define VM_DATA_DEFAULT_FLAGS \
+        (test_thread_flag(TIF_32BIT) ? \
+         VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
+
+/*
+ * This is the default if a program doesn't have a PT_GNU_STACK
+ * program header entry. The PPC64 ELF ABI has a non executable stack
+ * stack by default, so in the absense of a PT_GNU_STACK program header
+ * we turn execute permission off.
+ */
+#define VM_STACK_DEFAULT_FLAGS32        (VM_READ | VM_WRITE | VM_EXEC | \
+                                         VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#define VM_STACK_DEFAULT_FLAGS64        (VM_READ | VM_WRITE | \
+                                         VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#define VM_STACK_DEFAULT_FLAGS \
+        (test_thread_flag(TIF_32BIT) ? \
+         VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
+
+#include <asm-generic/page.h>
+
+#endif /* _ASM_POWERPC_PAGE_64_H */
diff --git a/arch/powerpc/include/asm/param.h b/arch/powerpc/include/asm/param.h
new file mode 100644
index 000000000000..094f63d4d5ca
--- /dev/null
+++ b/arch/powerpc/include/asm/param.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_POWERPC_PARAM_H
+#define _ASM_POWERPC_PARAM_H
+
+#ifdef __KERNEL__
+#define HZ              CONFIG_HZ       /* internal kernel timer frequency */
+#define USER_HZ         100             /* for user interfaces in "ticks" */
+#define CLOCKS_PER_SEC  (USER_HZ)       /* frequency at which times() counts */
+#endif /* __KERNEL__ */
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   4096
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif  /* _ASM_POWERPC_PARAM_H */
diff --git a/arch/powerpc/include/asm/parport.h b/arch/powerpc/include/asm/parport.h
new file mode 100644
index 000000000000..414c50e2e881
--- /dev/null
+++ b/arch/powerpc/include/asm/parport.h
@@ -0,0 +1,39 @@
+/*
+ * parport.h: platform-specific PC-style parport initialisation
+ *
+ * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+
+#ifndef _ASM_POWERPC_PARPORT_H
+#define _ASM_POWERPC_PARPORT_H
+#ifdef __KERNEL__
+
+#include <asm/prom.h>
+
+static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
+{
+        struct device_node *np;
+        const u32 *prop;
+        u32 io1, io2;
+        int propsize;
+        int count = 0;
+        for (np = NULL; (np = of_find_compatible_node(np,
+                                                      "parallel",
+                                                      "pnpPNP,400")) != NULL;) {
+                prop = of_get_property(np, "reg", &propsize);
+                if (!prop || propsize > 6*sizeof(u32))
+                        continue;
+                io1 = prop[1]; io2 = prop[2];
+                prop = of_get_property(np, "interrupts", NULL);
+                if (!prop)
+                        continue;
+                if (parport_pc_probe_port(io1, io2, prop[0], autodma, NULL) != NULL)
+                        count++;
+        }
+        return count;
+}
+
+#endif /* __KERNEL__ */
+#endif /* !(_ASM_POWERPC_PARPORT_H) */
diff --git a/arch/powerpc/include/asm/pasemi_dma.h b/arch/powerpc/include/asm/pasemi_dma.h
new file mode 100644
index 000000000000..19fd7933e2d9
--- /dev/null
+++ b/arch/powerpc/include/asm/pasemi_dma.h
@@ -0,0 +1,538 @@
+/*
+ * Copyright (C) 2006-2008 PA Semi, Inc
+ *
+ * Hardware register layout and descriptor formats for the on-board
+ * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
+ * drivers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef ASM_PASEMI_DMA_H
+#define ASM_PASEMI_DMA_H
+
+/* status register layout in IOB region, at 0xfb800000 */
+struct pasdma_status {
+        u64 rx_sta[64];         /* RX channel status */
+        u64 tx_sta[20];         /* TX channel status */
+};
+
+
+/* All these registers live in the PCI configuration space for the DMA PCI
+ * device. Use the normal PCI config access functions for them.
+ */
+enum {
+        PAS_DMA_CAP_TXCH  = 0x44,       /* Transmit Channel Info      */
+        PAS_DMA_CAP_RXCH  = 0x48,       /* Transmit Channel Info      */
+        PAS_DMA_CAP_IFI   = 0x4c,       /* Interface Info             */
+        PAS_DMA_COM_TXCMD = 0x100,      /* Transmit Command Register  */
+        PAS_DMA_COM_TXSTA = 0x104,      /* Transmit Status Register   */
+        PAS_DMA_COM_RXCMD = 0x108,      /* Receive Command Register   */
+        PAS_DMA_COM_RXSTA = 0x10c,      /* Receive Status Register    */
+        PAS_DMA_COM_CFG   = 0x114,      /* Common config reg          */
+        PAS_DMA_TXF_SFLG0 = 0x140,      /* Set flags                  */
+        PAS_DMA_TXF_SFLG1 = 0x144,      /* Set flags                  */
+        PAS_DMA_TXF_CFLG0 = 0x148,      /* Set flags                  */
+        PAS_DMA_TXF_CFLG1 = 0x14c,      /* Set flags                  */
+};
+
+
+#define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */
+#define PAS_DMA_CAP_TXCH_TCHN_S 16
+
+#define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */
+#define PAS_DMA_CAP_RXCH_RCHN_S 16
+
+#define PAS_DMA_CAP_IFI_IOFF_M  0xff000000 /* Cfg reg for intf pointers */
+#define PAS_DMA_CAP_IFI_IOFF_S  24
+#define PAS_DMA_CAP_IFI_NIN_M   0x00ff0000 /* # of interfaces */
+#define PAS_DMA_CAP_IFI_NIN_S   16
+
+#define PAS_DMA_COM_TXCMD_EN    0x00000001 /* enable */
+#define PAS_DMA_COM_TXSTA_ACT   0x00000001 /* active */
+#define PAS_DMA_COM_RXCMD_EN    0x00000001 /* enable */
+#define PAS_DMA_COM_RXSTA_ACT   0x00000001 /* active */
+
+
+/* Per-interface and per-channel registers */
+#define _PAS_DMA_RXINT_STRIDE           0x20
+#define PAS_DMA_RXINT_RCMDSTA(i)        (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
+#define    PAS_DMA_RXINT_RCMDSTA_EN     0x00000001
+#define    PAS_DMA_RXINT_RCMDSTA_ST     0x00000002
+#define    PAS_DMA_RXINT_RCMDSTA_MBT    0x00000008
+#define    PAS_DMA_RXINT_RCMDSTA_MDR    0x00000010
+#define    PAS_DMA_RXINT_RCMDSTA_MOO    0x00000020
+#define    PAS_DMA_RXINT_RCMDSTA_MBP    0x00000040
+#define    PAS_DMA_RXINT_RCMDSTA_BT     0x00000800
+#define    PAS_DMA_RXINT_RCMDSTA_DR     0x00001000
+#define    PAS_DMA_RXINT_RCMDSTA_OO     0x00002000
+#define    PAS_DMA_RXINT_RCMDSTA_BP     0x00004000
+#define    PAS_DMA_RXINT_RCMDSTA_TB     0x00008000
+#define    PAS_DMA_RXINT_RCMDSTA_ACT    0x00010000
+#define    PAS_DMA_RXINT_RCMDSTA_DROPS_M        0xfffe0000
+#define    PAS_DMA_RXINT_RCMDSTA_DROPS_S        17
+#define PAS_DMA_RXINT_CFG(i)            (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
+#define    PAS_DMA_RXINT_CFG_RBP        0x80000000
+#define    PAS_DMA_RXINT_CFG_ITRR       0x40000000
+#define    PAS_DMA_RXINT_CFG_DHL_M      0x07000000
+#define    PAS_DMA_RXINT_CFG_DHL_S      24
+#define    PAS_DMA_RXINT_CFG_DHL(x)     (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
+                                         PAS_DMA_RXINT_CFG_DHL_M)
+#define    PAS_DMA_RXINT_CFG_ITR        0x00400000
+#define    PAS_DMA_RXINT_CFG_LW         0x00200000
+#define    PAS_DMA_RXINT_CFG_L2         0x00100000
+#define    PAS_DMA_RXINT_CFG_HEN        0x00080000
+#define    PAS_DMA_RXINT_CFG_WIF        0x00000002
+#define    PAS_DMA_RXINT_CFG_WIL        0x00000001
+
+#define PAS_DMA_RXINT_INCR(i)           (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
+#define    PAS_DMA_RXINT_INCR_INCR_M    0x0000ffff
+#define    PAS_DMA_RXINT_INCR_INCR_S    0
+#define    PAS_DMA_RXINT_INCR_INCR(x)   ((x) & 0x0000ffff)
+#define PAS_DMA_RXINT_BASEL(i)          (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
+#define    PAS_DMA_RXINT_BASEL_BRBL(x)  ((x) & ~0x3f)
+#define PAS_DMA_RXINT_BASEU(i)          (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
+#define    PAS_DMA_RXINT_BASEU_BRBH(x)  ((x) & 0xfff)
+#define    PAS_DMA_RXINT_BASEU_SIZ_M    0x3fff0000      /* # of cache lines worth of buffer ring */
+#define    PAS_DMA_RXINT_BASEU_SIZ_S    16              /* 0 = 16K */
+#define    PAS_DMA_RXINT_BASEU_SIZ(x)   (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
+                                         PAS_DMA_RXINT_BASEU_SIZ_M)
+
+
+#define _PAS_DMA_TXCHAN_STRIDE  0x20    /* Size per channel             */
+#define _PAS_DMA_TXCHAN_TCMDSTA 0x300   /* Command / Status             */
+#define _PAS_DMA_TXCHAN_CFG     0x304   /* Configuration                */
+#define _PAS_DMA_TXCHAN_DSCRBU  0x308   /* Descriptor BU Allocation     */
+#define _PAS_DMA_TXCHAN_INCR    0x310   /* Descriptor increment         */
+#define _PAS_DMA_TXCHAN_CNT     0x314   /* Descriptor count/offset      */
+#define _PAS_DMA_TXCHAN_BASEL   0x318   /* Descriptor ring base (low)   */
+#define _PAS_DMA_TXCHAN_BASEU   0x31c   /*                      (high)  */
+#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
+#define    PAS_DMA_TXCHAN_TCMDSTA_EN    0x00000001      /* Enabled */
+#define    PAS_DMA_TXCHAN_TCMDSTA_ST    0x00000002      /* Stop interface */
+#define    PAS_DMA_TXCHAN_TCMDSTA_ACT   0x00010000      /* Active */
+#define    PAS_DMA_TXCHAN_TCMDSTA_SZ    0x00000800
+#define    PAS_DMA_TXCHAN_TCMDSTA_DB    0x00000400
+#define    PAS_DMA_TXCHAN_TCMDSTA_DE    0x00000200
+#define    PAS_DMA_TXCHAN_TCMDSTA_DA    0x00000100
+#define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
+#define    PAS_DMA_TXCHAN_CFG_TY_IFACE  0x00000000      /* Type = interface */
+#define    PAS_DMA_TXCHAN_CFG_TY_COPY   0x00000001      /* Type = copy only */
+#define    PAS_DMA_TXCHAN_CFG_TY_FUNC   0x00000002      /* Type = function */
+#define    PAS_DMA_TXCHAN_CFG_TY_XOR    0x00000003      /* Type = xor only */
+#define    PAS_DMA_TXCHAN_CFG_TATTR_M   0x0000003c
+#define    PAS_DMA_TXCHAN_CFG_TATTR_S   2
+#define    PAS_DMA_TXCHAN_CFG_TATTR(x)  (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
+                                         PAS_DMA_TXCHAN_CFG_TATTR_M)
+#define    PAS_DMA_TXCHAN_CFG_LPDQ      0x00000800
+#define    PAS_DMA_TXCHAN_CFG_LPSQ      0x00000400
+#define    PAS_DMA_TXCHAN_CFG_WT_M      0x000003c0
+#define    PAS_DMA_TXCHAN_CFG_WT_S      6
+#define    PAS_DMA_TXCHAN_CFG_WT(x)     (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
+                                         PAS_DMA_TXCHAN_CFG_WT_M)
+#define    PAS_DMA_TXCHAN_CFG_TRD       0x00010000      /* translate data */
+#define    PAS_DMA_TXCHAN_CFG_TRR       0x00008000      /* translate rings */
+#define    PAS_DMA_TXCHAN_CFG_UP        0x00004000      /* update tx descr when sent */
+#define    PAS_DMA_TXCHAN_CFG_CL        0x00002000      /* Clean last line */
+#define    PAS_DMA_TXCHAN_CFG_CF        0x00001000      /* Clean first line */
+#define PAS_DMA_TXCHAN_INCR(c)    (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
+#define PAS_DMA_TXCHAN_BASEL(c)   (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
+#define    PAS_DMA_TXCHAN_BASEL_BRBL_M  0xffffffc0
+#define    PAS_DMA_TXCHAN_BASEL_BRBL_S  0
+#define    PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
+                                         PAS_DMA_TXCHAN_BASEL_BRBL_M)
+#define PAS_DMA_TXCHAN_BASEU(c)   (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
+#define    PAS_DMA_TXCHAN_BASEU_BRBH_M  0x00000fff
+#define    PAS_DMA_TXCHAN_BASEU_BRBH_S  0
+#define    PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
+                                         PAS_DMA_TXCHAN_BASEU_BRBH_M)
+/* # of cache lines worth of buffer ring */
+#define    PAS_DMA_TXCHAN_BASEU_SIZ_M   0x3fff0000
+#define    PAS_DMA_TXCHAN_BASEU_SIZ_S   16              /* 0 = 16K */
+#define    PAS_DMA_TXCHAN_BASEU_SIZ(x)  (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
+                                         PAS_DMA_TXCHAN_BASEU_SIZ_M)
+
+#define _PAS_DMA_RXCHAN_STRIDE  0x20    /* Size per channel             */
+#define _PAS_DMA_RXCHAN_CCMDSTA 0x800   /* Command / Status             */
+#define _PAS_DMA_RXCHAN_CFG     0x804   /* Configuration                */
+#define _PAS_DMA_RXCHAN_INCR    0x810   /* Descriptor increment         */
+#define _PAS_DMA_RXCHAN_CNT     0x814   /* Descriptor count/offset      */
+#define _PAS_DMA_RXCHAN_BASEL   0x818   /* Descriptor ring base (low)   */
+#define _PAS_DMA_RXCHAN_BASEU   0x81c   /*                      (high)  */
+#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
+#define    PAS_DMA_RXCHAN_CCMDSTA_EN    0x00000001      /* Enabled */
+#define    PAS_DMA_RXCHAN_CCMDSTA_ST    0x00000002      /* Stop interface */
+#define    PAS_DMA_RXCHAN_CCMDSTA_ACT   0x00010000      /* Active */
+#define    PAS_DMA_RXCHAN_CCMDSTA_DU    0x00020000
+#define    PAS_DMA_RXCHAN_CCMDSTA_OD    0x00002000
+#define    PAS_DMA_RXCHAN_CCMDSTA_FD    0x00001000
+#define    PAS_DMA_RXCHAN_CCMDSTA_DT    0x00000800
+#define PAS_DMA_RXCHAN_CFG(c)     (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
+#define    PAS_DMA_RXCHAN_CFG_CTR       0x00000400
+#define    PAS_DMA_RXCHAN_CFG_HBU_M     0x00000380
+#define    PAS_DMA_RXCHAN_CFG_HBU_S     7
+#define    PAS_DMA_RXCHAN_CFG_HBU(x)    (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
+                                         PAS_DMA_RXCHAN_CFG_HBU_M)
+#define PAS_DMA_RXCHAN_INCR(c)    (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
+#define PAS_DMA_RXCHAN_BASEL(c)   (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
+#define    PAS_DMA_RXCHAN_BASEL_BRBL_M  0xffffffc0
+#define    PAS_DMA_RXCHAN_BASEL_BRBL_S  0
+#define    PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
+                                         PAS_DMA_RXCHAN_BASEL_BRBL_M)
+#define PAS_DMA_RXCHAN_BASEU(c)   (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
+#define    PAS_DMA_RXCHAN_BASEU_BRBH_M  0x00000fff
+#define    PAS_DMA_RXCHAN_BASEU_BRBH_S  0
+#define    PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
+                                         PAS_DMA_RXCHAN_BASEU_BRBH_M)
+/* # of cache lines worth of buffer ring */
+#define    PAS_DMA_RXCHAN_BASEU_SIZ_M   0x3fff0000
+#define    PAS_DMA_RXCHAN_BASEU_SIZ_S   16              /* 0 = 16K */
+#define    PAS_DMA_RXCHAN_BASEU_SIZ(x)  (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
+                                         PAS_DMA_RXCHAN_BASEU_SIZ_M)
+
+#define    PAS_STATUS_PCNT_M            0x000000000000ffffull
+#define    PAS_STATUS_PCNT_S            0
+#define    PAS_STATUS_DCNT_M            0x00000000ffff0000ull
+#define    PAS_STATUS_DCNT_S            16
+#define    PAS_STATUS_BPCNT_M           0x0000ffff00000000ull
+#define    PAS_STATUS_BPCNT_S           32
+#define    PAS_STATUS_CAUSE_M           0xf000000000000000ull
+#define    PAS_STATUS_TIMER             0x1000000000000000ull
+#define    PAS_STATUS_ERROR             0x2000000000000000ull
+#define    PAS_STATUS_SOFT              0x4000000000000000ull
+#define    PAS_STATUS_INT               0x8000000000000000ull
+
+#define PAS_IOB_COM_PKTHDRCNT           0x120
+#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M      0x0fff0000
+#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S      16
+#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M      0x00000fff
+#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S      0
+
+#define PAS_IOB_DMA_RXCH_CFG(i)         (0x1100 + (i)*4)
+#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_M         0x00000fff
+#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_S         0
+#define    PAS_IOB_DMA_RXCH_CFG_CNTTH(x)        (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
+                                                 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
+#define PAS_IOB_DMA_TXCH_CFG(i)         (0x1200 + (i)*4)
+#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_M         0x00000fff
+#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_S         0
+#define    PAS_IOB_DMA_TXCH_CFG_CNTTH(x)        (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
+                                                 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
+#define PAS_IOB_DMA_RXCH_STAT(i)        (0x1300 + (i)*4)
+#define    PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
+#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_M       0x00000fff
+#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_S       0
+#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL(x)      (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
+                                                 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
+#define PAS_IOB_DMA_TXCH_STAT(i)        (0x1400 + (i)*4)
+#define    PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
+#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_M       0x00000fff
+#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_S       0
+#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL(x)      (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
+                                                 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
+#define PAS_IOB_DMA_RXCH_RESET(i)       (0x1500 + (i)*4)
+#define    PAS_IOB_DMA_RXCH_RESET_PCNT_M        0xffff0000
+#define    PAS_IOB_DMA_RXCH_RESET_PCNT_S        16
+#define    PAS_IOB_DMA_RXCH_RESET_PCNT(x)       (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
+                                                 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
+#define    PAS_IOB_DMA_RXCH_RESET_PCNTRST       0x00000020
+#define    PAS_IOB_DMA_RXCH_RESET_DCNTRST       0x00000010
+#define    PAS_IOB_DMA_RXCH_RESET_TINTC         0x00000008
+#define    PAS_IOB_DMA_RXCH_RESET_DINTC         0x00000004
+#define    PAS_IOB_DMA_RXCH_RESET_SINTC         0x00000002
+#define    PAS_IOB_DMA_RXCH_RESET_PINTC         0x00000001
+#define PAS_IOB_DMA_TXCH_RESET(i)       (0x1600 + (i)*4)
+#define    PAS_IOB_DMA_TXCH_RESET_PCNT_M        0xffff0000
+#define    PAS_IOB_DMA_TXCH_RESET_PCNT_S        16
+#define    PAS_IOB_DMA_TXCH_RESET_PCNT(x)       (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
+                                                 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
+#define    PAS_IOB_DMA_TXCH_RESET_PCNTRST       0x00000020
+#define    PAS_IOB_DMA_TXCH_RESET_DCNTRST       0x00000010
+#define    PAS_IOB_DMA_TXCH_RESET_TINTC         0x00000008
+#define    PAS_IOB_DMA_TXCH_RESET_DINTC         0x00000004
+#define    PAS_IOB_DMA_TXCH_RESET_SINTC         0x00000002
+#define    PAS_IOB_DMA_TXCH_RESET_PINTC         0x00000001
+
+#define PAS_IOB_DMA_COM_TIMEOUTCFG              0x1700
+#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M    0x00ffffff
+#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S    0
+#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x)   (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
+                                                 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
+
+/* Transmit descriptor fields */
+#define XCT_MACTX_T             0x8000000000000000ull
+#define XCT_MACTX_ST            0x4000000000000000ull
+#define XCT_MACTX_NORES         0x0000000000000000ull
+#define XCT_MACTX_8BRES         0x1000000000000000ull
+#define XCT_MACTX_24BRES        0x2000000000000000ull
+#define XCT_MACTX_40BRES        0x3000000000000000ull
+#define XCT_MACTX_I             0x0800000000000000ull
+#define XCT_MACTX_O             0x0400000000000000ull
+#define XCT_MACTX_E             0x0200000000000000ull
+#define XCT_MACTX_VLAN_M        0x0180000000000000ull
+#define XCT_MACTX_VLAN_NOP      0x0000000000000000ull
+#define XCT_MACTX_VLAN_REMOVE   0x0080000000000000ull
+#define XCT_MACTX_VLAN_INSERT   0x0100000000000000ull
+#define XCT_MACTX_VLAN_REPLACE  0x0180000000000000ull
+#define XCT_MACTX_CRC_M         0x0060000000000000ull
+#define XCT_MACTX_CRC_NOP       0x0000000000000000ull
+#define XCT_MACTX_CRC_INSERT    0x0020000000000000ull
+#define XCT_MACTX_CRC_PAD       0x0040000000000000ull
+#define XCT_MACTX_CRC_REPLACE   0x0060000000000000ull
+#define XCT_MACTX_SS            0x0010000000000000ull
+#define XCT_MACTX_LLEN_M        0x00007fff00000000ull
+#define XCT_MACTX_LLEN_S        32ull
+#define XCT_MACTX_LLEN(x)       ((((long)(x)) << XCT_MACTX_LLEN_S) & \
+                                 XCT_MACTX_LLEN_M)
+#define XCT_MACTX_IPH_M         0x00000000f8000000ull
+#define XCT_MACTX_IPH_S         27ull
+#define XCT_MACTX_IPH(x)        ((((long)(x)) << XCT_MACTX_IPH_S) & \
+                                 XCT_MACTX_IPH_M)
+#define XCT_MACTX_IPO_M         0x0000000007c00000ull
+#define XCT_MACTX_IPO_S         22ull
+#define XCT_MACTX_IPO(x)        ((((long)(x)) << XCT_MACTX_IPO_S) & \
+                                 XCT_MACTX_IPO_M)
+#define XCT_MACTX_CSUM_M        0x0000000000000060ull
+#define XCT_MACTX_CSUM_NOP      0x0000000000000000ull
+#define XCT_MACTX_CSUM_TCP      0x0000000000000040ull
+#define XCT_MACTX_CSUM_UDP      0x0000000000000060ull
+#define XCT_MACTX_V6            0x0000000000000010ull
+#define XCT_MACTX_C             0x0000000000000004ull
+#define XCT_MACTX_AL2           0x0000000000000002ull
+
+/* Receive descriptor fields */
+#define XCT_MACRX_T             0x8000000000000000ull
+#define XCT_MACRX_ST            0x4000000000000000ull
+#define XCT_MACRX_RR_M          0x3000000000000000ull
+#define XCT_MACRX_RR_NORES      0x0000000000000000ull
+#define XCT_MACRX_RR_8BRES      0x1000000000000000ull
+#define XCT_MACRX_O             0x0400000000000000ull
+#define XCT_MACRX_E             0x0200000000000000ull
+#define XCT_MACRX_FF            0x0100000000000000ull
+#define XCT_MACRX_PF            0x0080000000000000ull
+#define XCT_MACRX_OB            0x0040000000000000ull
+#define XCT_MACRX_OD            0x0020000000000000ull
+#define XCT_MACRX_FS            0x0010000000000000ull
+#define XCT_MACRX_NB_M          0x000fc00000000000ull
+#define XCT_MACRX_NB_S          46ULL
+#define XCT_MACRX_NB(x)         ((((long)(x)) << XCT_MACRX_NB_S) & \
+                                 XCT_MACRX_NB_M)
+#define XCT_MACRX_LLEN_M        0x00003fff00000000ull
+#define XCT_MACRX_LLEN_S        32ULL
+#define XCT_MACRX_LLEN(x)       ((((long)(x)) << XCT_MACRX_LLEN_S) & \
+                                 XCT_MACRX_LLEN_M)
+#define XCT_MACRX_CRC           0x0000000080000000ull
+#define XCT_MACRX_LEN_M         0x0000000060000000ull
+#define XCT_MACRX_LEN_TOOSHORT  0x0000000020000000ull
+#define XCT_MACRX_LEN_BELOWMIN  0x0000000040000000ull
+#define XCT_MACRX_LEN_TRUNC     0x0000000060000000ull
+#define XCT_MACRX_CAST_M        0x0000000018000000ull
+#define XCT_MACRX_CAST_UNI      0x0000000000000000ull
+#define XCT_MACRX_CAST_MULTI    0x0000000008000000ull
+#define XCT_MACRX_CAST_BROAD    0x0000000010000000ull
+#define XCT_MACRX_CAST_PAUSE    0x0000000018000000ull
+#define XCT_MACRX_VLC_M         0x0000000006000000ull
+#define XCT_MACRX_FM            0x0000000001000000ull
+#define XCT_MACRX_HTY_M         0x0000000000c00000ull
+#define XCT_MACRX_HTY_IPV4_OK   0x0000000000000000ull
+#define XCT_MACRX_HTY_IPV6      0x0000000000400000ull
+#define XCT_MACRX_HTY_IPV4_BAD  0x0000000000800000ull
+#define XCT_MACRX_HTY_NONIP     0x0000000000c00000ull
+#define XCT_MACRX_IPP_M         0x00000000003f0000ull
+#define XCT_MACRX_IPP_S         16
+#define XCT_MACRX_CSUM_M        0x000000000000ffffull
+#define XCT_MACRX_CSUM_S        0
+
+#define XCT_PTR_T               0x8000000000000000ull
+#define XCT_PTR_LEN_M           0x7ffff00000000000ull
+#define XCT_PTR_LEN_S           44
+#define XCT_PTR_LEN(x)          ((((long)(x)) << XCT_PTR_LEN_S) & \
+                                 XCT_PTR_LEN_M)
+#define XCT_PTR_ADDR_M          0x00000fffffffffffull
+#define XCT_PTR_ADDR_S          0
+#define XCT_PTR_ADDR(x)         ((((long)(x)) << XCT_PTR_ADDR_S) & \
+                                 XCT_PTR_ADDR_M)
+
+/* Receive interface 8byte result fields */
+#define XCT_RXRES_8B_L4O_M      0xff00000000000000ull
+#define XCT_RXRES_8B_L4O_S      56
+#define XCT_RXRES_8B_RULE_M     0x00ffff0000000000ull
+#define XCT_RXRES_8B_RULE_S     40
+#define XCT_RXRES_8B_EVAL_M     0x000000ffff000000ull
+#define XCT_RXRES_8B_EVAL_S     24
+#define XCT_RXRES_8B_HTYPE_M    0x0000000000f00000ull
+#define XCT_RXRES_8B_HASH_M     0x00000000000fffffull
+#define XCT_RXRES_8B_HASH_S     0
+
+/* Receive interface buffer fields */
+#define XCT_RXB_LEN_M           0x0ffff00000000000ull
+#define XCT_RXB_LEN_S           44
+#define XCT_RXB_LEN(x)          ((((long)(x)) << XCT_RXB_LEN_S) & \
+                                 XCT_RXB_LEN_M)
+#define XCT_RXB_ADDR_M          0x00000fffffffffffull
+#define XCT_RXB_ADDR_S          0
+#define XCT_RXB_ADDR(x)         ((((long)(x)) << XCT_RXB_ADDR_S) & \
+                                 XCT_RXB_ADDR_M)
+
+/* Copy descriptor fields */
+#define XCT_COPY_T              0x8000000000000000ull
+#define XCT_COPY_ST             0x4000000000000000ull
+#define XCT_COPY_RR_M           0x3000000000000000ull
+#define XCT_COPY_RR_NORES       0x0000000000000000ull
+#define XCT_COPY_RR_8BRES       0x1000000000000000ull
+#define XCT_COPY_RR_24BRES      0x2000000000000000ull
+#define XCT_COPY_RR_40BRES      0x3000000000000000ull
+#define XCT_COPY_I              0x0800000000000000ull
+#define XCT_COPY_O              0x0400000000000000ull
+#define XCT_COPY_E              0x0200000000000000ull
+#define XCT_COPY_STY_ZERO       0x01c0000000000000ull
+#define XCT_COPY_DTY_PREF       0x0038000000000000ull
+#define XCT_COPY_LLEN_M         0x0007ffff00000000ull
+#define XCT_COPY_LLEN_S         32
+#define XCT_COPY_LLEN(x)        ((((long)(x)) << XCT_COPY_LLEN_S) & \
+                                 XCT_COPY_LLEN_M)
+#define XCT_COPY_SE             0x0000000000000001ull
+
+/* Function descriptor fields */
+#define XCT_FUN_T               0x8000000000000000ull
+#define XCT_FUN_ST              0x4000000000000000ull
+#define XCT_FUN_RR_M            0x3000000000000000ull
+#define XCT_FUN_RR_NORES        0x0000000000000000ull
+#define XCT_FUN_RR_8BRES        0x1000000000000000ull
+#define XCT_FUN_RR_24BRES       0x2000000000000000ull
+#define XCT_FUN_RR_40BRES       0x3000000000000000ull
+#define XCT_FUN_I               0x0800000000000000ull
+#define XCT_FUN_O               0x0400000000000000ull
+#define XCT_FUN_E               0x0200000000000000ull
+#define XCT_FUN_FUN_M           0x01c0000000000000ull
+#define XCT_FUN_FUN_S           54
+#define XCT_FUN_FUN(x)          ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
+#define XCT_FUN_CRM_M           0x0038000000000000ull
+#define XCT_FUN_CRM_NOP         0x0000000000000000ull
+#define XCT_FUN_CRM_SIG         0x0008000000000000ull
+#define XCT_FUN_LLEN_M          0x0007ffff00000000ull
+#define XCT_FUN_LLEN_S          32
+#define XCT_FUN_LLEN(x)         ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
+#define XCT_FUN_SHL_M           0x00000000f8000000ull
+#define XCT_FUN_SHL_S           27
+#define XCT_FUN_SHL(x)          ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
+#define XCT_FUN_CHL_M           0x0000000007c00000ull
+#define XCT_FUN_HSZ_M           0x00000000003c0000ull
+#define XCT_FUN_ALG_M           0x0000000000038000ull
+#define XCT_FUN_HP              0x0000000000004000ull
+#define XCT_FUN_BCM_M           0x0000000000003800ull
+#define XCT_FUN_BCP_M           0x0000000000000600ull
+#define XCT_FUN_SIG_M           0x00000000000001f0ull
+#define XCT_FUN_SIG_TCP4        0x0000000000000140ull
+#define XCT_FUN_SIG_TCP6        0x0000000000000150ull
+#define XCT_FUN_SIG_UDP4        0x0000000000000160ull
+#define XCT_FUN_SIG_UDP6        0x0000000000000170ull
+#define XCT_FUN_A               0x0000000000000008ull
+#define XCT_FUN_C               0x0000000000000004ull
+#define XCT_FUN_AL2             0x0000000000000002ull
+#define XCT_FUN_SE              0x0000000000000001ull
+
+/* Function descriptor 8byte result fields */
+#define XCT_FUNRES_8B_CS_M      0x0000ffff00000000ull
+#define XCT_FUNRES_8B_CS_S      32
+#define XCT_FUNRES_8B_CRC_M     0x00000000ffffffffull
+#define XCT_FUNRES_8B_CRC_S     0
+
+/* Control descriptor fields */
+#define CTRL_CMD_T              0x8000000000000000ull
+#define CTRL_CMD_META_EVT       0x2000000000000000ull
+#define CTRL_CMD_O              0x0400000000000000ull
+#define CTRL_CMD_ETYPE_M        0x0038000000000000ull
+#define CTRL_CMD_ETYPE_EXT      0x0000000000000000ull
+#define CTRL_CMD_ETYPE_WSET     0x0020000000000000ull
+#define CTRL_CMD_ETYPE_WCLR     0x0028000000000000ull
+#define CTRL_CMD_ETYPE_SET      0x0030000000000000ull
+#define CTRL_CMD_ETYPE_CLR      0x0038000000000000ull
+#define CTRL_CMD_REG_M          0x000000000000007full
+#define CTRL_CMD_REG_S          0
+#define CTRL_CMD_REG(x)         ((((long)(x)) << CTRL_CMD_REG_S) & \
+                                 CTRL_CMD_REG_M)
+
+
+
+/* Prototypes for the shared DMA functions in the platform code. */
+
+/* DMA TX Channel type. Right now only limitations used are event types 0/1,
+ * for event-triggered DMA transactions.
+ */
+
+enum pasemi_dmachan_type {
+        RXCHAN = 0,             /* Any RX chan */
+        TXCHAN = 1,             /* Any TX chan */
+        TXCHAN_EVT0 = 0x1001,   /* TX chan in event class 0 (chan 0-9) */
+        TXCHAN_EVT1 = 0x2001,   /* TX chan in event class 1 (chan 10-19) */
+};
+
+struct pasemi_dmachan {
+        int              chno;          /* Channel number */
+        enum pasemi_dmachan_type chan_type;     /* TX / RX */
+        u64             *status;        /* Ptr to cacheable status */
+        int              irq;           /* IRQ used by channel */
+        unsigned int     ring_size;     /* size of allocated ring */
+        dma_addr_t       ring_dma;      /* DMA address for ring */
+        u64             *ring_virt;     /* Virt address for ring */
+        void            *priv;          /* Ptr to start of client struct */
+};
+
+/* Read/write the different registers in the I/O Bridge, Ethernet
+ * and DMA Controller
+ */
+extern unsigned int pasemi_read_iob_reg(unsigned int reg);
+extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);
+
+extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
+extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);
+
+extern unsigned int pasemi_read_dma_reg(unsigned int reg);
+extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);
+
+/* Channel management routines */
+
+extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
+                                   int total_size, int offset);
+extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);
+
+extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
+                                  const u32 cmdsta);
+extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);
+
+/* Common routines to allocate rings and buffers */
+
+extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
+extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);
+
+extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
+                                  dma_addr_t *handle);
+extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
+                                dma_addr_t *handle);
+
+/* Routines to allocate flags (events) for channel syncronization */
+extern int  pasemi_dma_alloc_flag(void);
+extern void pasemi_dma_free_flag(int flag);
+extern void pasemi_dma_set_flag(int flag);
+extern void pasemi_dma_clear_flag(int flag);
+
+/* Routines to allocate function engines */
+extern int  pasemi_dma_alloc_fun(void);
+extern void pasemi_dma_free_fun(int fun);
+
+/* Initialize the library, must be called before any other functions */
+extern int pasemi_dma_init(void);
+
+#endif /* ASM_PASEMI_DMA_H */
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
new file mode 100644
index 000000000000..ae2ea803a0f2
--- /dev/null
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -0,0 +1,302 @@
+#ifndef _ASM_POWERPC_PCI_BRIDGE_H
+#define _ASM_POWERPC_PCI_BRIDGE_H
+#ifdef __KERNEL__
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/pci.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+
+struct device_node;
+
+extern unsigned int ppc_pci_flags;
+enum {
+        /* Force re-assigning all resources (ignore firmware
+         * setup completely)
+         */
+        PPC_PCI_REASSIGN_ALL_RSRC       = 0x00000001,
+
+        /* Re-assign all bus numbers */
+        PPC_PCI_REASSIGN_ALL_BUS        = 0x00000002,
+
+        /* Do not try to assign, just use existing setup */
+        PPC_PCI_PROBE_ONLY              = 0x00000004,
+
+        /* Don't bother with ISA alignment unless the bridge has
+         * ISA forwarding enabled
+         */
+        PPC_PCI_CAN_SKIP_ISA_ALIGN      = 0x00000008,
+
+        /* Enable domain numbers in /proc */
+        PPC_PCI_ENABLE_PROC_DOMAINS     = 0x00000010,
+        /* ... except for domain 0 */
+        PPC_PCI_COMPAT_DOMAIN_0         = 0x00000020,
+};
+
+
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+struct pci_controller {
+        struct pci_bus *bus;
+        char is_dynamic;
+#ifdef CONFIG_PPC64
+        int node;
+#endif
+        struct device_node *dn;
+        struct list_head list_node;
+        struct device *parent;
+
+        int first_busno;
+        int last_busno;
+#ifndef CONFIG_PPC64
+        int self_busno;
+#endif
+
+        void __iomem *io_base_virt;
+#ifdef CONFIG_PPC64
+        void *io_base_alloc;
+#endif
+        resource_size_t io_base_phys;
+#ifndef CONFIG_PPC64
+        resource_size_t pci_io_size;
+#endif
+
+        /* Some machines (PReP) have a non 1:1 mapping of
+         * the PCI memory space in the CPU bus space
+         */
+        resource_size_t pci_mem_offset;
+#ifdef CONFIG_PPC64
+        unsigned long pci_io_size;
+#endif
+
+        struct pci_ops *ops;
+        unsigned int __iomem *cfg_addr;
+        void __iomem *cfg_data;
+
+#ifndef CONFIG_PPC64
+        /*
+         * Used for variants of PCI indirect handling and possible quirks:
+         *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
+         *  EXT_REG - provides access to PCI-e extended registers
+         *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
+         *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
+         *   to determine which bus number to match on when generating type0
+         *   config cycles
+         *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
+         *   hanging if we don't have link and try to do config cycles to
+         *   anything but the PHB.  Only allow talking to the PHB if this is
+         *   set.
+         *  BIG_ENDIAN - cfg_addr is a big endian register
+         *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
+         *   the PLB4.  Effectively disable MRM commands by setting this.
+         */
+#define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
+#define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
+#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
+#define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
+#define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
+#define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
+        u32 indirect_type;
+#endif  /* !CONFIG_PPC64 */
+        /* Currently, we limit ourselves to 1 IO range and 3 mem
+         * ranges since the common pci_bus structure can't handle more
+         */
+        struct resource io_resource;
+        struct resource mem_resources[3];
+        int global_number;              /* PCI domain number */
+#ifdef CONFIG_PPC64
+        unsigned long buid;
+        unsigned long dma_window_base_cur;
+        unsigned long dma_window_size;
+
+        void *private_data;
+#endif  /* CONFIG_PPC64 */
+};
+
+#ifndef CONFIG_PPC64
+
+static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
+{
+        return bus->sysdata;
+}
+
+static inline int isa_vaddr_is_ioport(void __iomem *address)
+{
+        /* No specific ISA handling on ppc32 at this stage, it
+         * all goes through PCI
+         */
+        return 0;
+}
+
+/* These are used for config access before all the PCI probing
+   has been done. */
+extern int early_read_config_byte(struct pci_controller *hose, int bus,
+                        int dev_fn, int where, u8 *val);
+extern int early_read_config_word(struct pci_controller *hose, int bus,
+                        int dev_fn, int where, u16 *val);
+extern int early_read_config_dword(struct pci_controller *hose, int bus,
+                        int dev_fn, int where, u32 *val);
+extern int early_write_config_byte(struct pci_controller *hose, int bus,
+                        int dev_fn, int where, u8 val);
+extern int early_write_config_word(struct pci_controller *hose, int bus,
+                        int dev_fn, int where, u16 val);
+extern int early_write_config_dword(struct pci_controller *hose, int bus,
+                        int dev_fn, int where, u32 val);
+
+extern int early_find_capability(struct pci_controller *hose, int bus,
+                                 int dev_fn, int cap);
+
+extern void setup_indirect_pci(struct pci_controller* hose,
+                               resource_size_t cfg_addr,
+                               resource_size_t cfg_data, u32 flags);
+extern void setup_grackle(struct pci_controller *hose);
+#else   /* CONFIG_PPC64 */
+
+/*
+ * PCI stuff, for nodes representing PCI devices, pointed to
+ * by device_node->data.
+ */
+struct iommu_table;
+
+struct pci_dn {
+        int     busno;                  /* pci bus number */
+        int     devfn;                  /* pci device and function number */
+
+        struct  pci_controller *phb;    /* for pci devices */
+        struct  iommu_table *iommu_table;       /* for phb's or bridges */
+        struct  device_node *node;      /* back-pointer to the device_node */
+
+        int     pci_ext_config_space;   /* for pci devices */
+
+#ifdef CONFIG_EEH
+        struct  pci_dev *pcidev;        /* back-pointer to the pci device */
+        int     class_code;             /* pci device class */
+        int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
+        int     eeh_config_addr;
+        int     eeh_pe_config_addr; /* new-style partition endpoint address */
+        int     eeh_check_count;        /* # times driver ignored error */
+        int     eeh_freeze_count;       /* # times this device froze up. */
+        int     eeh_false_positives;    /* # times this device reported #ff's */
+        u32     config_space[16];       /* saved PCI config space */
+#endif
+};
+
+/* Get the pointer to a device_node's pci_dn */
+#define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
+
+extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
+
+/* Get a device_node from a pci_dev.  This code must be fast except
+ * in the case where the sysdata is incorrect and needs to be fixed
+ * up (this will only happen once).
+ * In this case the sysdata will have been inherited from a PCI host
+ * bridge or a PCI-PCI bridge further up the tree, so it will point
+ * to a valid struct pci_dn, just not the one we want.
+ */
+static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
+{
+        struct device_node *dn = dev->sysdata;
+        struct pci_dn *pdn = dn->data;
+
+        if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
+                return dn;      /* fast path.  sysdata is good */
+        return fetch_dev_dn(dev);
+}
+
+static inline int pci_device_from_OF_node(struct device_node *np,
+                                          u8 *bus, u8 *devfn)
+{
+        if (!PCI_DN(np))
+                return -ENODEV;
+        *bus = PCI_DN(np)->busno;
+        *devfn = PCI_DN(np)->devfn;
+        return 0;
+}
+
+static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
+{
+        if (bus->self)
+                return pci_device_to_OF_node(bus->self);
+        else
+                return bus->sysdata; /* Must be root bus (PHB) */
+}
+
+/** Find the bus corresponding to the indicated device node */
+extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
+
+/** Remove all of the PCI devices under this bus */
+extern void pcibios_remove_pci_devices(struct pci_bus *bus);
+
+/** Discover new pci devices under this bus, and add them */
+extern void pcibios_add_pci_devices(struct pci_bus *bus);
+extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
+
+extern int pcibios_remove_root_bus(struct pci_controller *phb);
+
+static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
+{
+        struct device_node *busdn = bus->sysdata;
+
+        BUG_ON(busdn == NULL);
+        return PCI_DN(busdn)->phb;
+}
+
+
+extern void isa_bridge_find_early(struct pci_controller *hose);
+
+static inline int isa_vaddr_is_ioport(void __iomem *address)
+{
+        /* Check if address hits the reserved legacy IO range */
+        unsigned long ea = (unsigned long)address;
+        return ea >= ISA_IO_BASE && ea < ISA_IO_END;
+}
+
+extern int pcibios_unmap_io_space(struct pci_bus *bus);
+extern int pcibios_map_io_space(struct pci_bus *bus);
+
+/* Return values for ppc_md.pci_probe_mode function */
+#define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
+#define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
+#define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
+
+#ifdef CONFIG_NUMA
+#define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
+#else
+#define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
+#endif
+
+#endif  /* CONFIG_PPC64 */
+
+/* Get the PCI host controller for an OF device */
+extern struct pci_controller *pci_find_hose_for_OF_device(
+                        struct device_node* node);
+
+/* Fill up host controller resources from the OF node */
+extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
+                        struct device_node *dev, int primary);
+
+/* Allocate & free a PCI host bridge structure */
+extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
+extern void pcibios_free_controller(struct pci_controller *phb);
+
+#ifdef CONFIG_PCI
+extern unsigned long pci_address_to_pio(phys_addr_t address);
+extern int pcibios_vaddr_is_ioport(void __iomem *address);
+#else
+static inline unsigned long pci_address_to_pio(phys_addr_t address)
+{
+        return (unsigned long)-1;
+}
+static inline int pcibios_vaddr_is_ioport(void __iomem *address)
+{
+        return 0;
+}
+#endif  /* CONFIG_PCI */
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_PCI_BRIDGE_H */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
new file mode 100644
index 000000000000..a05a942b1c25
--- /dev/null
+++ b/arch/powerpc/include/asm/pci.h
@@ -0,0 +1,228 @@
+#ifndef __ASM_POWERPC_PCI_H
+#define __ASM_POWERPC_PCI_H
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/machdep.h>
+#include <asm/scatterlist.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+
+#include <asm-generic/pci-dma-compat.h>
+
+#define PCIBIOS_MIN_IO          0x1000
+#define PCIBIOS_MIN_MEM         0x10000000
+
+struct pci_dev;
+
+/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
+#define IOBASE_BRIDGE_NUMBER    0
+#define IOBASE_MEMORY           1
+#define IOBASE_IO               2
+#define IOBASE_ISA_IO           3
+#define IOBASE_ISA_MEM          4
+
+/*
+ * Set this to 1 if you want the kernel to re-assign all PCI
+ * bus numbers (don't do that on ppc64 yet !)
+ */
+#define pcibios_assign_all_busses()     (ppc_pci_flags & \
+                                         PPC_PCI_REASSIGN_ALL_BUS)
+#define pcibios_scan_all_fns(a, b)      0
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        if (ppc_md.pci_get_legacy_ide_irq)
+                return ppc_md.pci_get_legacy_ide_irq(dev, channel);
+        return channel ? 15 : 14;
+}
+
+#ifdef CONFIG_PPC64
+
+/*
+ * We want to avoid touching the cacheline size or MWI bit.
+ * pSeries firmware sets the cacheline size (which is not the cpu cacheline
+ * size in all cases) and hardware treats MWI the same as memory write.
+ */
+#define PCI_DISABLE_MWI
+
+#ifdef CONFIG_PCI
+extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
+extern struct dma_mapping_ops *get_pci_dma_ops(void);
+
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_MULTIPLE;
+        *strategy_parameter = cacheline_size;
+}
+#else   /* CONFIG_PCI */
+#define set_pci_dma_ops(d)
+#define get_pci_dma_ops()       NULL
+#endif
+
+#else /* 32-bit */
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+#endif /* CONFIG_PPC64 */
+
+extern int pci_domain_nr(struct pci_bus *bus);
+
+/* Decide whether to display the domain number in /proc */
+extern int pci_proc_domain(struct pci_bus *bus);
+
+
+struct vm_area_struct;
+/* Map a range of PCI memory or I/O space for a device into user space */
+int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
+                        enum pci_mmap_state mmap_state, int write_combine);
+
+/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
+#define HAVE_PCI_MMAP   1
+
+#if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
+/*
+ * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
+ * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
+ * so on are not nops.
+ * and thus...
+ */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+
+#else /* 32-bit && coherent */
+
+/* pci_unmap_{page,single} is a nop so... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+
+#endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */
+
+#ifdef CONFIG_PPC64
+
+/* The PCI address space does not equal the physical memory address
+ * space (we have an IOMMU).  The IDE and SCSI device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (0)
+
+#else /* 32-bit */
+
+/* The PCI address space does equal the physical memory
+ * address space (no IOMMU).  The IDE and SCSI device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (1)
+
+#endif /* CONFIG_PPC64 */
+
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+                        struct pci_bus_region *region,
+                        struct resource *res);
+
+extern void pcibios_bus_to_resource(struct pci_dev *dev,
+                        struct resource *res,
+                        struct pci_bus_region *region);
+
+static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
+                        struct resource *res)
+{
+        struct resource *root = NULL;
+
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
+
+extern void pcibios_setup_new_device(struct pci_dev *dev);
+
+extern void pcibios_claim_one_bus(struct pci_bus *b);
+
+extern void pcibios_resource_survey(void);
+
+extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
+
+extern struct pci_dev *of_create_pci_dev(struct device_node *node,
+                                        struct pci_bus *bus, int devfn);
+
+extern void of_scan_pci_bridge(struct device_node *node,
+                                struct pci_dev *dev);
+
+extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
+
+extern int pci_read_irq_line(struct pci_dev *dev);
+
+struct file;
+extern pgprot_t pci_phys_mem_access_prot(struct file *file,
+                                         unsigned long pfn,
+                                         unsigned long size,
+                                         pgprot_t prot);
+
+#define HAVE_ARCH_PCI_RESOURCE_TO_USER
+extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
+                                 const struct resource *rsrc,
+                                 resource_size_t *start, resource_size_t *end);
+
+extern void pcibios_do_bus_setup(struct pci_bus *bus);
+extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
+
+#endif  /* __KERNEL__ */
+#endif /* __ASM_POWERPC_PCI_H */
diff --git a/arch/powerpc/include/asm/percpu.h b/arch/powerpc/include/asm/percpu.h
new file mode 100644
index 000000000000..f879252b7ea6
--- /dev/null
+++ b/arch/powerpc/include/asm/percpu.h
@@ -0,0 +1,24 @@
+#ifndef _ASM_POWERPC_PERCPU_H_
+#define _ASM_POWERPC_PERCPU_H_
+#ifdef __powerpc64__
+#include <linux/compiler.h>
+
+/*
+ * Same as asm-generic/percpu.h, except that we store the per cpu offset
+ * in the paca. Based on the x86-64 implementation.
+ */
+
+#ifdef CONFIG_SMP
+
+#include <asm/paca.h>
+
+#define __per_cpu_offset(cpu) (paca[cpu].data_offset)
+#define __my_cpu_offset local_paca->data_offset
+#define per_cpu_offset(x) (__per_cpu_offset(x))
+
+#endif /* CONFIG_SMP */
+#endif /* __powerpc64__ */
+
+#include <asm-generic/percpu.h>
+
+#endif /* _ASM_POWERPC_PERCPU_H_ */
diff --git a/arch/powerpc/include/asm/pgalloc-32.h b/arch/powerpc/include/asm/pgalloc-32.h
new file mode 100644
index 000000000000..58c07147b3ea
--- /dev/null
+++ b/arch/powerpc/include/asm/pgalloc-32.h
@@ -0,0 +1,43 @@
+#ifndef _ASM_POWERPC_PGALLOC_32_H
+#define _ASM_POWERPC_PGALLOC_32_H
+
+#include <linux/threads.h>
+
+extern void __bad_pte(pmd_t *pmd);
+
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
+
+/*
+ * We don't have any real pmd's, and this code never triggers because
+ * the pgd will always be present..
+ */
+/* #define pmd_alloc_one(mm,address)       ({ BUG(); ((pmd_t *)2); }) */
+#define pmd_free(mm, x)                 do { } while (0)
+#define __pmd_free_tlb(tlb,x)           do { } while (0)
+/* #define pgd_populate(mm, pmd, pte)      BUG() */
+
+#ifndef CONFIG_BOOKE
+#define pmd_populate_kernel(mm, pmd, pte)       \
+                (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte)      \
+                (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
+#define pmd_pgtable(pmd) pmd_page(pmd)
+#else
+#define pmd_populate_kernel(mm, pmd, pte)       \
+                (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte)      \
+                (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
+#define pmd_pgtable(pmd) pmd_page(pmd)
+#endif
+
+extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
+extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte);
+extern void pte_free(struct mm_struct *mm, pgtable_t pte);
+
+#define __pte_free_tlb(tlb, pte)        pte_free((tlb)->mm, (pte))
+
+#define check_pgt_cache()       do { } while (0)
+
+#endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
new file mode 100644
index 000000000000..812a1d8f35cb
--- /dev/null
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -0,0 +1,166 @@
+#ifndef _ASM_POWERPC_PGALLOC_64_H
+#define _ASM_POWERPC_PGALLOC_64_H
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/cpumask.h>
+#include <linux/percpu.h>
+
+#ifndef CONFIG_PPC_SUBPAGE_PROT
+static inline void subpage_prot_free(pgd_t *pgd) {}
+#endif
+
+extern struct kmem_cache *pgtable_cache[];
+
+#define PGD_CACHE_NUM           0
+#define PUD_CACHE_NUM           1
+#define PMD_CACHE_NUM           1
+#define HUGEPTE_CACHE_NUM       2
+#define PTE_NONCACHE_NUM        7  /* from GFP rather than kmem_cache */
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
+}
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        subpage_prot_free(pgd);
+        kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
+}
+
+#ifndef CONFIG_PPC_64K_PAGES
+
+#define pgd_populate(MM, PGD, PUD)      pgd_set(PGD, PUD)
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pud_free(struct mm_struct *mm, pud_t *pud)
+{
+        kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
+}
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        pud_set(pud, (unsigned long)pmd);
+}
+
+#define pmd_populate(mm, pmd, pte_page) \
+        pmd_populate_kernel(mm, pmd, page_address(pte_page))
+#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+
+#else /* CONFIG_PPC_64K_PAGES */
+
+#define pud_populate(mm, pud, pmd)      pud_set(pud, (unsigned long)pmd)
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+                                       pte_t *pte)
+{
+        pmd_set(pmd, (unsigned long)pte);
+}
+
+#define pmd_populate(mm, pmd, pte_page) \
+        pmd_populate_kernel(mm, pmd, page_address(pte_page))
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+#endif /* CONFIG_PPC_64K_PAGES */
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+        kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long address)
+{
+        return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+                                        unsigned long address)
+{
+        struct page *page;
+        pte_t *pte;
+
+        pte = pte_alloc_one_kernel(mm, address);
+        if (!pte)
+                return NULL;
+        page = virt_to_page(pte);
+        pgtable_page_ctor(page);
+        return page;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        free_page((unsigned long)pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+        pgtable_page_dtor(ptepage);
+        __free_page(ptepage);
+}
+
+#define PGF_CACHENUM_MASK       0x7
+
+typedef struct pgtable_free {
+        unsigned long val;
+} pgtable_free_t;
+
+static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
+                                                unsigned long mask)
+{
+        BUG_ON(cachenum > PGF_CACHENUM_MASK);
+
+        return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
+}
+
+static inline void pgtable_free(pgtable_free_t pgf)
+{
+        void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
+        int cachenum = pgf.val & PGF_CACHENUM_MASK;
+
+        if (cachenum == PTE_NONCACHE_NUM)
+                free_page((unsigned long)p);
+        else
+                kmem_cache_free(pgtable_cache[cachenum], p);
+}
+
+extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
+
+#define __pte_free_tlb(tlb,ptepage)     \
+do { \
+        pgtable_page_dtor(ptepage); \
+        pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
+                PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \
+} while (0)
+#define __pmd_free_tlb(tlb, pmd)        \
+        pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
+                PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
+#ifndef CONFIG_PPC_64K_PAGES
+#define __pud_free_tlb(tlb, pud)        \
+        pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
+                PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
+#endif /* CONFIG_PPC_64K_PAGES */
+
+#define check_pgt_cache()       do { } while (0)
+
+#endif /* _ASM_POWERPC_PGALLOC_64_H */
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
new file mode 100644
index 000000000000..b4505ed0f0f2
--- /dev/null
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_POWERPC_PGALLOC_H
+#define _ASM_POWERPC_PGALLOC_H
+#ifdef __KERNEL__
+
+#ifdef CONFIG_PPC64
+#include <asm/pgalloc-64.h>
+#else
+#include <asm/pgalloc-32.h>
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/pgtable-4k.h b/arch/powerpc/include/asm/pgtable-4k.h
new file mode 100644
index 000000000000..6b18ba9d2d85
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-4k.h
@@ -0,0 +1,117 @@
+#ifndef _ASM_POWERPC_PGTABLE_4K_H
+#define _ASM_POWERPC_PGTABLE_4K_H
+/*
+ * Entries per page directory level.  The PTE level must use a 64b record
+ * for each page table entry.  The PMD and PGD level use a 32b record for
+ * each entry by assuming that each entry is page aligned.
+ */
+#define PTE_INDEX_SIZE  9
+#define PMD_INDEX_SIZE  7
+#define PUD_INDEX_SIZE  7
+#define PGD_INDEX_SIZE  9
+
+#ifndef __ASSEMBLY__
+#define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_INDEX_SIZE)
+#define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
+#define PUD_TABLE_SIZE  (sizeof(pud_t) << PUD_INDEX_SIZE)
+#define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
+#endif  /* __ASSEMBLY__ */
+
+#define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
+#define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
+#define PTRS_PER_PUD    (1 << PMD_INDEX_SIZE)
+#define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
+
+/* PMD_SHIFT determines what a second-level page table entry can map */
+#define PMD_SHIFT       (PAGE_SHIFT + PTE_INDEX_SIZE)
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+/* With 4k base page size, hugepage PTEs go at the PMD level */
+#define MIN_HUGEPTE_SHIFT       PMD_SHIFT
+
+/* PUD_SHIFT determines what a third-level page table entry can map */
+#define PUD_SHIFT       (PMD_SHIFT + PMD_INDEX_SIZE)
+#define PUD_SIZE        (1UL << PUD_SHIFT)
+#define PUD_MASK        (~(PUD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
+#define PGDIR_SHIFT     (PUD_SHIFT + PUD_INDEX_SIZE)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/* PTE bits */
+#define _PAGE_HASHPTE   0x0400 /* software: pte has an associated HPTE */
+#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
+#define _PAGE_GROUP_IX  0x7000 /* software: HPTE index within group */
+#define _PAGE_F_SECOND  _PAGE_SECONDARY
+#define _PAGE_F_GIX     _PAGE_GROUP_IX
+#define _PAGE_SPECIAL   0x10000 /* software: special page */
+#define __HAVE_ARCH_PTE_SPECIAL
+
+/* PTE flags to conserve for HPTE identification */
+#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
+                         _PAGE_SECONDARY | _PAGE_GROUP_IX)
+
+/* There is no 4K PFN hack on 4K pages */
+#define _PAGE_4K_PFN    0
+
+/* PAGE_MASK gives the right answer below, but only by accident */
+/* It should be preserving the high 48 bits and then specifically */
+/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
+                         _PAGE_HPTEFLAGS)
+
+/* Bits to mask out from a PMD to get to the PTE page */
+#define PMD_MASKED_BITS         0
+/* Bits to mask out from a PUD to get to the PMD page */
+#define PUD_MASKED_BITS         0
+/* Bits to mask out from a PGD to get to the PUD page */
+#define PGD_MASKED_BITS         0
+
+/* shift to put page number into pte */
+#define PTE_RPN_SHIFT   (17)
+
+#ifdef STRICT_MM_TYPECHECKS
+#define __real_pte(e,p)         ((real_pte_t){(e)})
+#define __rpte_to_pte(r)        ((r).pte)
+#else
+#define __real_pte(e,p)         (e)
+#define __rpte_to_pte(r)        (__pte(r))
+#endif
+#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
+
+#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)       \
+        do {                                                             \
+                index = 0;                                               \
+                shift = mmu_psize_defs[psize].shift;                     \
+
+#define pte_iterate_hashed_end() } while(0)
+
+#ifdef CONFIG_PPC_HAS_HASH_64K
+#define pte_pagesize_index(mm, addr, pte)       get_slice_psize(mm, addr)
+#else
+#define pte_pagesize_index(mm, addr, pte)       MMU_PAGE_4K
+#endif
+
+/*
+ * 4-level page tables related bits
+ */
+
+#define pgd_none(pgd)           (!pgd_val(pgd))
+#define pgd_bad(pgd)            (pgd_val(pgd) == 0)
+#define pgd_present(pgd)        (pgd_val(pgd) != 0)
+#define pgd_clear(pgdp)         (pgd_val(*(pgdp)) = 0)
+#define pgd_page_vaddr(pgd)     (pgd_val(pgd) & ~PGD_MASKED_BITS)
+#define pgd_page(pgd)           virt_to_page(pgd_page_vaddr(pgd))
+
+#define pud_offset(pgdp, addr)  \
+  (((pud_t *) pgd_page_vaddr(*(pgdp))) + \
+    (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
+
+#define pud_ERROR(e) \
+        printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
+
+#define remap_4k_pfn(vma, addr, pfn, prot)      \
+        remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
+#endif /* _ASM_POWERPC_PGTABLE_4K_H */
diff --git a/arch/powerpc/include/asm/pgtable-64k.h b/arch/powerpc/include/asm/pgtable-64k.h
new file mode 100644
index 000000000000..07b0d8f09cb6
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-64k.h
@@ -0,0 +1,155 @@
+#ifndef _ASM_POWERPC_PGTABLE_64K_H
+#define _ASM_POWERPC_PGTABLE_64K_H
+
+#include <asm-generic/pgtable-nopud.h>
+
+
+#define PTE_INDEX_SIZE  12
+#define PMD_INDEX_SIZE  12
+#define PUD_INDEX_SIZE  0
+#define PGD_INDEX_SIZE  4
+
+#ifndef __ASSEMBLY__
+#define PTE_TABLE_SIZE  (sizeof(real_pte_t) << PTE_INDEX_SIZE)
+#define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
+#define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
+
+#define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
+#define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
+#define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
+
+#ifdef CONFIG_PPC_SUBPAGE_PROT
+/*
+ * For the sub-page protection option, we extend the PGD with one of
+ * these.  Basically we have a 3-level tree, with the top level being
+ * the protptrs array.  To optimize speed and memory consumption when
+ * only addresses < 4GB are being protected, pointers to the first
+ * four pages of sub-page protection words are stored in the low_prot
+ * array.
+ * Each page of sub-page protection words protects 1GB (4 bytes
+ * protects 64k).  For the 3-level tree, each page of pointers then
+ * protects 8TB.
+ */
+struct subpage_prot_table {
+        unsigned long maxaddr;  /* only addresses < this are protected */
+        unsigned int **protptrs[2];
+        unsigned int *low_prot[4];
+};
+
+#undef PGD_TABLE_SIZE
+#define PGD_TABLE_SIZE          ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \
+                                 sizeof(struct subpage_prot_table))
+
+#define SBP_L1_BITS             (PAGE_SHIFT - 2)
+#define SBP_L2_BITS             (PAGE_SHIFT - 3)
+#define SBP_L1_COUNT            (1 << SBP_L1_BITS)
+#define SBP_L2_COUNT            (1 << SBP_L2_BITS)
+#define SBP_L2_SHIFT            (PAGE_SHIFT + SBP_L1_BITS)
+#define SBP_L3_SHIFT            (SBP_L2_SHIFT + SBP_L2_BITS)
+
+extern void subpage_prot_free(pgd_t *pgd);
+
+static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
+{
+        return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD);
+}
+#endif /* CONFIG_PPC_SUBPAGE_PROT */
+#endif  /* __ASSEMBLY__ */
+
+/* With 4k base page size, hugepage PTEs go at the PMD level */
+#define MIN_HUGEPTE_SHIFT       PAGE_SHIFT
+
+/* PMD_SHIFT determines what a second-level page table entry can map */
+#define PMD_SHIFT       (PAGE_SHIFT + PTE_INDEX_SIZE)
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT     (PMD_SHIFT + PMD_INDEX_SIZE)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/* Additional PTE bits (don't change without checking asm in hash_low.S) */
+#define __HAVE_ARCH_PTE_SPECIAL
+#define _PAGE_SPECIAL   0x00000400 /* software: special page */
+#define _PAGE_HPTE_SUB  0x0ffff000 /* combo only: sub pages HPTE bits */
+#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
+#define _PAGE_COMBO     0x10000000 /* this is a combo 4k page */
+#define _PAGE_4K_PFN    0x20000000 /* PFN is for a single 4k page */
+
+/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
+ * we set that to be the whole sub-bits mask. The C code will only
+ * test this, so a multi-bit mask will work. For combo pages, this
+ * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
+ * all the sub bits. For real 64k pages, we now have the assembly set
+ * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
+ * that mask. This is fine as long as the HIDX bits are never set on
+ * a PTE that isn't hashed, which is the case today.
+ *
+ * A little nit is for the huge page C code, which does the hashing
+ * in C, we need to provide which bit to use.
+ */
+#define _PAGE_HASHPTE   _PAGE_HPTE_SUB
+
+/* Note the full page bits must be in the same location as for normal
+ * 4k pages as the same asssembly will be used to insert 64K pages
+ * wether the kernel has CONFIG_PPC_64K_PAGES or not
+ */
+#define _PAGE_F_SECOND  0x00008000 /* full page: hidx bits */
+#define _PAGE_F_GIX     0x00007000 /* full page: hidx bits */
+
+/* PTE flags to conserve for HPTE identification */
+#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
+
+/* Shift to put page number into pte.
+ *
+ * That gives us a max RPN of 34 bits, which means a max of 50 bits
+ * of addressable physical space, or 46 bits for the special 4k PFNs.
+ */
+#define PTE_RPN_SHIFT   (30)
+#define PTE_RPN_MAX     (1UL << (64 - PTE_RPN_SHIFT))
+#define PTE_RPN_MASK    (~((1UL<<PTE_RPN_SHIFT)-1))
+
+/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
+ * pgprot changes
+ */
+#define _PAGE_CHG_MASK  (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
+                         _PAGE_ACCESSED)
+
+/* Bits to mask out from a PMD to get to the PTE page */
+#define PMD_MASKED_BITS         0x1ff
+/* Bits to mask out from a PGD/PUD to get to the PMD page */
+#define PUD_MASKED_BITS         0x1ff
+
+/* Manipulate "rpte" values */
+#define __real_pte(e,p)         ((real_pte_t) { \
+        (e), pte_val(*((p) + PTRS_PER_PTE)) })
+#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
+        (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
+#define __rpte_to_pte(r)        ((r).pte)
+#define __rpte_sub_valid(rpte, index) \
+        (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
+
+
+/* Trick: we set __end to va + 64k, which happens works for
+ * a 16M page as well as we want only one iteration
+ */
+#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)          \
+        do {                                                                \
+                unsigned long __end = va + PAGE_SIZE;                       \
+                unsigned __split = (psize == MMU_PAGE_4K ||                 \
+                                    psize == MMU_PAGE_64K_AP);              \
+                shift = mmu_psize_defs[psize].shift;                        \
+                for (index = 0; va < __end; index++, va += (1L << shift)) { \
+                        if (!__split || __rpte_sub_valid(rpte, index)) do { \
+
+#define pte_iterate_hashed_end() } while(0); } } while(0)
+
+#define pte_pagesize_index(mm, addr, pte)       \
+        (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
+
+#define remap_4k_pfn(vma, addr, pfn, prot)                              \
+        remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,                \
+                        __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
+
+#endif /* _ASM_POWERPC_PGTABLE_64K_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
new file mode 100644
index 000000000000..6fe39e327047
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -0,0 +1,802 @@
+#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
+#define _ASM_POWERPC_PGTABLE_PPC32_H
+
+#include <asm-generic/pgtable-nopmd.h>
+
+#ifndef __ASSEMBLY__
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
+
+extern unsigned long va_to_phys(unsigned long address);
+extern pte_t *va_to_pte(unsigned long address);
+extern unsigned long ioremap_bot, ioremap_base;
+
+#ifdef CONFIG_44x
+extern int icache_44x_need_flush;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The PowerPC MMU uses a hash table containing PTEs, together with
+ * a set of 16 segment registers (on 32-bit implementations), to define
+ * the virtual to physical address mapping.
+ *
+ * We use the hash table as an extended TLB, i.e. a cache of currently
+ * active mappings.  We maintain a two-level page table tree, much
+ * like that used by the i386, for the sake of the Linux memory
+ * management code.  Low-level assembler code in hashtable.S
+ * (procedure hash_page) is responsible for extracting ptes from the
+ * tree and putting them into the hash table when necessary, and
+ * updating the accessed and modified bits in the page table tree.
+ */
+
+/*
+ * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
+ * We also use the two level tables, but we can put the real bits in them
+ * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
+ * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
+ * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
+ * based upon user/super access.  The TLB does not have accessed nor write
+ * protect.  We assume that if the TLB get loaded with an entry it is
+ * accessed, and overload the changed bit for write protect.  We use
+ * two bits in the software pte that are supposed to be set to zero in
+ * the TLB entry (24 and 25) for these indicators.  Although the level 1
+ * descriptor contains the guarded and writethrough/copyback bits, we can
+ * set these at the page level since they get copied from the Mx_TWC
+ * register when the TLB entry is loaded.  We will use bit 27 for guard, since
+ * that is where it exists in the MD_TWC, and bit 26 for writethrough.
+ * These will get masked from the level 2 descriptor at TLB load time, and
+ * copied to the MD_TWC before it gets loaded.
+ * Large page sizes added.  We currently support two sizes, 4K and 8M.
+ * This also allows a TLB hander optimization because we can directly
+ * load the PMD into MD_TWC.  The 8M pages are only used for kernel
+ * mapping of well known areas.  The PMD (PGD) entries contain control
+ * flags in addition to the address, so care must be taken that the
+ * software no longer assumes these are only pointers.
+ */
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully-associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively (see "mmu.h" for definitions).
+ */
+
+/*
+ * The normal case is that PTEs are 32-bits and we have a 1-page
+ * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
+ *
+ * For any >32-bit physical address platform, we can use the following
+ * two level page table layout where the pgdir is 8KB and the MS 13 bits
+ * are an index to the second level table.  The combined pgdir/pmd first
+ * level has 2048 entries and the second level has 512 64-bit PTE entries.
+ * -Matt
+ */
+/* PGDIR_SHIFT determines what a top-level page table entry can map */
+#define PGDIR_SHIFT     (PAGE_SHIFT + PTE_SHIFT)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * entries per page directory level: our page-table tree is two-level, so
+ * we don't really have any PMD directory.
+ */
+#ifndef __ASSEMBLY__
+#define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_SHIFT)
+#define PGD_TABLE_SIZE  (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
+#endif  /* __ASSEMBLY__ */
+
+#define PTRS_PER_PTE    (1 << PTE_SHIFT)
+#define PTRS_PER_PMD    1
+#define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
+
+#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
+#define FIRST_USER_ADDRESS      0
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
+                (unsigned long long)pte_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 64MB value just means that there will be a 64MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ *
+ * We no longer map larger than phys RAM with the BATs so we don't have
+ * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
+ * about clashes between our early calls to ioremap() that start growing down
+ * from ioremap_base being run into the VM area allocations (growing upwards
+ * from VMALLOC_START).  For this reason we have ioremap_bot to check when
+ * we actually run into our mappings setup in the early boot with the VM
+ * system.  This really does become a problem for machines with good amounts
+ * of RAM.  -- Cort
+ */
+#define VMALLOC_OFFSET (0x1000000) /* 16M */
+#ifdef PPC_PIN_SIZE
+#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#else
+#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#endif
+#define VMALLOC_END     ioremap_bot
+
+/*
+ * Bits in a linux-style PTE.  These match the bits in the
+ * (hardware-defined) PowerPC PTE as closely as possible.
+ */
+
+#if defined(CONFIG_40x)
+
+/* There are several potential gotchas here.  The 40x hardware TLBLO
+   field looks like this:
+
+   0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+   RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
+
+   Where possible we make the Linux PTE bits match up with this
+
+   - bits 20 and 21 must be cleared, because we use 4k pages (40x can
+     support down to 1k pages), this is done in the TLBMiss exception
+     handler.
+   - We use only zones 0 (for kernel pages) and 1 (for user pages)
+     of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
+     miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
+     zone.
+   - PRESENT *must* be in the bottom two bits because swap cache
+     entries use the top 30 bits.  Because 40x doesn't support SMP
+     anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
+     is cleared in the TLB miss handler before the TLB entry is loaded.
+   - All other bits of the PTE are loaded into TLBLO without
+     modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
+     software PTE bits.  We actually use use bits 21, 24, 25, and
+     30 respectively for the software bits: ACCESSED, DIRTY, RW, and
+     PRESENT.
+*/
+
+/* Definitions for 40x embedded chips. */
+#define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
+#define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
+#define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
+#define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
+#define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
+#define _PAGE_USER      0x010   /* matches one of the zone permission bits */
+#define _PAGE_RW        0x040   /* software: Writes permitted */
+#define _PAGE_DIRTY     0x080   /* software: dirty page */
+#define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
+#define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
+#define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
+
+#define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
+#define _PMD_BAD        0x802
+#define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
+#define _PMD_SIZE_4M    0x0c0
+#define _PMD_SIZE_16M   0x0e0
+#define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
+
+/* Until my rework is finished, 40x still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES      1
+
+#elif defined(CONFIG_44x)
+/*
+ * Definitions for PPC440
+ *
+ * Because of the 3 word TLB entries to support 36-bit addressing,
+ * the attribute are difficult to map in such a fashion that they
+ * are easily loaded during exception processing.  I decided to
+ * organize the entry so the ERPN is the only portion in the
+ * upper word of the PTE and the attribute bits below are packed
+ * in as sensibly as they can be in the area below a 4KB page size
+ * oriented RPN.  This at least makes it easy to load the RPN and
+ * ERPN fields in the TLB. -Matt
+ *
+ * Note that these bits preclude future use of a page size
+ * less than 4KB.
+ *
+ *
+ * PPC 440 core has following TLB attribute fields;
+ *
+ *   TLB1:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   RPN.................................  -  -  -  -  -  - ERPN.......
+ *
+ *   TLB2:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
+ *
+ * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
+ * TLB2 storage attibute fields. Those are:
+ *
+ *   TLB2:
+ *   0...10    11   12   13   14   15   16...31
+ *   no change WL1  IL1I IL1D IL2I IL2D no change
+ *
+ * There are some constrains and options, to decide mapping software bits
+ * into TLB entry.
+ *
+ *   - PRESENT *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - FILE *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
+ *     doesn't support SMP. So we can use this as software bit, like
+ *     DIRTY.
+ *
+ * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
+ * for memory protection related functions (see PTE structure in
+ * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
+ * above bits.  Note that the bit values are CPU specific, not architecture
+ * specific.
+ *
+ * The kernel PTE entry holds an arch-dependent swp_entry structure under
+ * certain situations. In other words, in such situations some portion of
+ * the PTE bits are used as a swp_entry. In the PPC implementation, the
+ * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
+ * hold protection values. That means the three protection bits are
+ * reserved for both PTE and SWAP entry at the most significant three
+ * LSBs.
+ *
+ * There are three protection bits available for SWAP entry:
+ *      _PAGE_PRESENT
+ *      _PAGE_FILE
+ *      _PAGE_HASHPTE (if HW has)
+ *
+ * So those three bits have to be inside of 0-2nd LSB of PTE.
+ *
+ */
+
+#define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
+#define _PAGE_RW        0x00000002              /* S: Write permission */
+#define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
+#define _PAGE_HWEXEC    0x00000004              /* H: Execute permission */
+#define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
+#define _PAGE_DIRTY     0x00000010              /* S: Page dirty */
+#define _PAGE_USER      0x00000040              /* S: User page */
+#define _PAGE_ENDIAN    0x00000080              /* H: E bit */
+#define _PAGE_GUARDED   0x00000100              /* H: G bit */
+#define _PAGE_COHERENT  0x00000200              /* H: M bit */
+#define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
+#define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
+
+/* TODO: Add large page lowmem mapping support */
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK  0xffffffff00000000ULL
+
+
+#elif defined(CONFIG_FSL_BOOKE)
+/*
+   MMU Assist Register 3:
+
+   32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
+   RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
+
+   - PRESENT *must* be in the bottom three bits because swap cache
+     entries use the top 29 bits.
+
+   - FILE *must* be in the bottom three bits because swap cache
+     entries use the top 29 bits.
+*/
+
+/* Definitions for FSL Book-E Cores */
+#define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
+#define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
+#define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
+#define _PAGE_RW        0x00004 /* S: Write permission (SW) */
+#define _PAGE_DIRTY     0x00008 /* S: Page dirty */
+#define _PAGE_HWEXEC    0x00010 /* H: SX permission */
+#define _PAGE_ACCESSED  0x00020 /* S: Page referenced */
+
+#define _PAGE_ENDIAN    0x00040 /* H: E bit */
+#define _PAGE_GUARDED   0x00080 /* H: G bit */
+#define _PAGE_COHERENT  0x00100 /* H: M bit */
+#define _PAGE_NO_CACHE  0x00200 /* H: I bit */
+#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
+
+#ifdef CONFIG_PTE_64BIT
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK  0xffffffffffff0000ULL
+#endif
+
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+
+#elif defined(CONFIG_8xx)
+/* Definitions for 8xx embedded chips. */
+#define _PAGE_PRESENT   0x0001  /* Page is valid */
+#define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
+#define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
+#define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
+
+/* These five software bits must be masked out when the entry is loaded
+ * into the TLB.
+ */
+#define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
+#define _PAGE_GUARDED   0x0010  /* software: guarded access */
+#define _PAGE_DIRTY     0x0020  /* software: page changed */
+#define _PAGE_RW        0x0040  /* software: user write access allowed */
+#define _PAGE_ACCESSED  0x0080  /* software: page referenced */
+
+/* Setting any bits in the nibble with the follow two controls will
+ * require a TLB exception handler change.  It is assumed unused bits
+ * are always zero.
+ */
+#define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
+#define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
+
+#define _PMD_PRESENT    0x0001
+#define _PMD_BAD        0x0ff0
+#define _PMD_PAGE_MASK  0x000c
+#define _PMD_PAGE_8M    0x000c
+
+#define _PTE_NONE_MASK _PAGE_ACCESSED
+
+/* Until my rework is finished, 8xx still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES      1
+
+#else /* CONFIG_6xx */
+/* Definitions for 60x, 740/750, etc. */
+#define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
+#define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
+#define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
+#define _PAGE_USER      0x004   /* usermode access allowed */
+#define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
+#define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
+#define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
+#define _PAGE_DIRTY     0x080   /* C: page changed */
+#define _PAGE_ACCESSED  0x100   /* R: page referenced */
+#define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
+#define _PAGE_RW        0x400   /* software: user write access allowed */
+
+#define _PTE_NONE_MASK  _PAGE_HASHPTE
+
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+
+/* Hash table based platforms need atomic updates of the linux PTE */
+#define PTE_ATOMIC_UPDATES      1
+
+#endif
+
+/*
+ * Some bits are only used on some cpu families...
+ */
+#ifndef _PAGE_HASHPTE
+#define _PAGE_HASHPTE   0
+#endif
+#ifndef _PTE_NONE_MASK
+#define _PTE_NONE_MASK 0
+#endif
+#ifndef _PAGE_SHARED
+#define _PAGE_SHARED    0
+#endif
+#ifndef _PAGE_HWWRITE
+#define _PAGE_HWWRITE   0
+#endif
+#ifndef _PAGE_HWEXEC
+#define _PAGE_HWEXEC    0
+#endif
+#ifndef _PAGE_EXEC
+#define _PAGE_EXEC      0
+#endif
+#ifndef _PAGE_ENDIAN
+#define _PAGE_ENDIAN    0
+#endif
+#ifndef _PAGE_COHERENT
+#define _PAGE_COHERENT  0
+#endif
+#ifndef _PAGE_WRITETHRU
+#define _PAGE_WRITETHRU 0
+#endif
+#ifndef _PMD_PRESENT_MASK
+#define _PMD_PRESENT_MASK       _PMD_PRESENT
+#endif
+#ifndef _PMD_SIZE
+#define _PMD_SIZE       0
+#define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
+#endif
+
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+
+
+#define PAGE_PROT_BITS  __pgprot(_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
+                                 _PAGE_WRITETHRU | _PAGE_ENDIAN | \
+                                 _PAGE_USER | _PAGE_ACCESSED | \
+                                 _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
+                                 _PAGE_EXEC | _PAGE_HWEXEC)
+/*
+ * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
+ * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
+ * to have it in the Linux PTE, and in fact the bit could be reused for
+ * another purpose.  -- paulus.
+ */
+
+#ifdef CONFIG_44x
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
+#else
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
+#endif
+#define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
+#define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
+
+#ifdef CONFIG_PPC_STD_MMU
+/* On standard PPC MMU, no user access implies kernel read/write access,
+ * so to write-protect kernel memory we must turn on user access */
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
+#else
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
+#endif
+
+#define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
+
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
+        defined(CONFIG_KPROBES)
+/* We want the debuggers to be able to set breakpoints anywhere, so
+ * don't write protect the kernel text */
+#define _PAGE_RAM_TEXT  _PAGE_RAM
+#else
+#define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
+#endif
+
+#define PAGE_NONE       __pgprot(_PAGE_BASE)
+#define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
+#define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
+#define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+
+#define PAGE_KERNEL             __pgprot(_PAGE_RAM)
+#define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
+
+/*
+ * The PowerPC can only do execute protection on a segment (256MB) basis,
+ * not on a page basis.  So we consider execute permission the same as read.
+ * Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY_X
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY_X
+#define __P100  PAGE_READONLY
+#define __P101  PAGE_READONLY_X
+#define __P110  PAGE_COPY
+#define __P111  PAGE_COPY_X
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY_X
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED_X
+#define __S100  PAGE_READONLY
+#define __S101  PAGE_READONLY_X
+#define __S110  PAGE_SHARED
+#define __S111  PAGE_SHARED_X
+
+#ifndef __ASSEMBLY__
+/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
+ * kernel without large page PMD support */
+extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
+
+/*
+ * Conversions between PTE values and page frame numbers.
+ */
+
+/* in some case we want to additionaly adjust where the pfn is in the pte to
+ * allow room for more flags */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
+#define PFN_SHIFT_OFFSET        (PAGE_SHIFT + 8)
+#else
+#define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
+#endif
+
+#define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
+                                        pgprot_val(prot))
+#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
+#endif /* __ASSEMBLY__ */
+
+#define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
+
+#define pmd_none(pmd)           (!pmd_val(pmd))
+#define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
+#define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
+#define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
+
+#ifndef __ASSEMBLY__
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
+static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
+static inline int pte_special(pte_t pte)        { return 0; }
+
+static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
+static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
+
+static inline pte_t pte_wrprotect(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_mkclean(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_mkold(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+
+static inline pte_t pte_mkwrite(pte_t pte) {
+        pte_val(pte) |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) {
+        pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) {
+        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkspecial(pte_t pte) {
+        return pte; }
+static inline unsigned long pte_pgprot(pte_t pte)
+{
+        return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
+}
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+        return pte;
+}
+
+/*
+ * When flushing the tlb entry for a page, we also need to flush the hash
+ * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
+ */
+extern int flush_hash_pages(unsigned context, unsigned long va,
+                            unsigned long pmdval, int count);
+
+/* Add an HPTE to the hash table */
+extern void add_hash_page(unsigned context, unsigned long va,
+                          unsigned long pmdval);
+
+/*
+ * Atomic PTE updates.
+ *
+ * pte_update clears and sets bit atomically, and returns
+ * the old pte value.  In the 64-bit PTE case we lock around the
+ * low PTE word since we expect ALL flag bits to be there
+ */
+#ifndef CONFIG_PTE_64BIT
+static inline unsigned long pte_update(pte_t *p,
+                                       unsigned long clr,
+                                       unsigned long set)
+{
+#ifdef PTE_ATOMIC_UPDATES
+        unsigned long old, tmp;
+
+        __asm__ __volatile__("\
+1:      lwarx   %0,0,%3\n\
+        andc    %1,%0,%4\n\
+        or      %1,%1,%5\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %1,0,%3\n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*p)
+        : "r" (p), "r" (clr), "r" (set), "m" (*p)
+        : "cc" );
+#else /* PTE_ATOMIC_UPDATES */
+        unsigned long old = pte_val(*p);
+        *p = __pte((old & ~clr) | set);
+#endif /* !PTE_ATOMIC_UPDATES */
+
+#ifdef CONFIG_44x
+        if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
+                icache_44x_need_flush = 1;
+#endif
+        return old;
+}
+#else /* CONFIG_PTE_64BIT */
+/* TODO: Change that to only modify the low word and move set_pte_at()
+ * out of line
+ */
+static inline unsigned long long pte_update(pte_t *p,
+                                            unsigned long clr,
+                                            unsigned long set)
+{
+#ifdef PTE_ATOMIC_UPDATES
+        unsigned long long old;
+        unsigned long tmp;
+
+        __asm__ __volatile__("\
+1:      lwarx   %L0,0,%4\n\
+        lwzx    %0,0,%3\n\
+        andc    %1,%L0,%5\n\
+        or      %1,%1,%6\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %1,0,%4\n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*p)
+        : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
+        : "cc" );
+#else /* PTE_ATOMIC_UPDATES */
+        unsigned long long old = pte_val(*p);
+        *p = __pte((old & ~(unsigned long long)clr) | set);
+#endif /* !PTE_ATOMIC_UPDATES */
+
+#ifdef CONFIG_44x
+        if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
+                icache_44x_need_flush = 1;
+#endif
+        return old;
+}
+#endif /* CONFIG_PTE_64BIT */
+
+/*
+ * set_pte stores a linux PTE into the linux page table.
+ * On machines which use an MMU hash table we avoid changing the
+ * _PAGE_HASHPTE bit.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pte)
+{
+#if _PAGE_HASHPTE != 0
+        pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
+#else
+        *ptep = pte;
+#endif
+}
+
+/*
+ * 2.6 calls this without flushing the TLB entry; this is wrong
+ * for our hash-based implementation, we fix that up here.
+ */
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
+{
+        unsigned long old;
+        old = pte_update(ptep, _PAGE_ACCESSED, 0);
+#if _PAGE_HASHPTE != 0
+        if (old & _PAGE_HASHPTE) {
+                unsigned long ptephys = __pa(ptep) & PAGE_MASK;
+                flush_hash_pages(context, addr, ptephys, 1);
+        }
+#endif
+        return (old & _PAGE_ACCESSED) != 0;
+}
+#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
+        __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+                                       pte_t *ptep)
+{
+        return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
+}
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+                                      pte_t *ptep)
+{
+        pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
+}
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
+{
+        unsigned long bits = pte_val(entry) &
+                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
+        pte_update(ptep, 0, bits);
+}
+
+#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+({                                                                         \
+        int __changed = !pte_same(*(__ptep), __entry);                     \
+        if (__changed) {                                                   \
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        }                                                                  \
+        __changed;                                                         \
+})
+
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
+
+/*
+ * Note that on Book E processors, the pmd contains the kernel virtual
+ * (lowmem) address of the pte page.  The physical address is less useful
+ * because everything runs with translation enabled (even the TLB miss
+ * handler).  On everything else the pmd contains the physical address
+ * of the pte page.  -- paulus
+ */
+#ifndef CONFIG_BOOKE
+#define pmd_page_vaddr(pmd)     \
+        ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd)           \
+        (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
+#else
+#define pmd_page_vaddr(pmd)     \
+        ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd)           \
+        pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+#endif
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(address)       ((address) >> PGDIR_SHIFT)
+#define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(address)              \
+        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, addr)    \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
+#define pte_offset_map(dir, addr)               \
+        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
+#define pte_offset_map_nested(dir, addr)        \
+        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
+
+#define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
+#define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
+
+/*
+ * Encode and decode a swap entry.
+ * Note that the bits we use in a PTE for representing a swap entry
+ * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
+ *_PAGE_HASHPTE bit (if used).  -- paulus
+ */
+#define __swp_type(entry)               ((entry).val & 0x1f)
+#define __swp_offset(entry)             ((entry).val >> 5)
+#define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
+
+/* Encode and decode a nonlinear file mapping entry */
+#define PTE_FILE_MAX_BITS       29
+#define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
+#define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
+                      pmd_t **pmdp);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
new file mode 100644
index 000000000000..db0b8f3b8807
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -0,0 +1,468 @@
+#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
+#define _ASM_POWERPC_PGTABLE_PPC64_H_
+/*
+ * This file contains the functions and defines necessary to modify and use
+ * the ppc64 hashed page table.
+ */
+
+#ifndef __ASSEMBLY__
+#include <linux/stddef.h>
+#include <asm/tlbflush.h>
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PPC_64K_PAGES
+#include <asm/pgtable-64k.h>
+#else
+#include <asm/pgtable-4k.h>
+#endif
+
+#define FIRST_USER_ADDRESS      0
+
+/*
+ * Size of EA range mapped by our pagetables.
+ */
+#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
+                            PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
+#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
+
+#if TASK_SIZE_USER64 > PGTABLE_RANGE
+#error TASK_SIZE_USER64 exceeds pagetable range
+#endif
+
+#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
+#error TASK_SIZE_USER64 exceeds user VSID range
+#endif
+
+
+/*
+ * Define the address range of the vmalloc VM area.
+ */
+#define VMALLOC_START ASM_CONST(0xD000000000000000)
+#define VMALLOC_SIZE  (PGTABLE_RANGE >> 1)
+#define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
+
+/*
+ * Define the address ranges for MMIO and IO space :
+ *
+ *  ISA_IO_BASE = VMALLOC_END, 64K reserved area
+ *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
+ * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
+ */
+#define FULL_IO_SIZE    0x80000000ul
+#define  ISA_IO_BASE    (VMALLOC_END)
+#define  ISA_IO_END     (VMALLOC_END + 0x10000ul)
+#define  PHB_IO_BASE    (ISA_IO_END)
+#define  PHB_IO_END     (VMALLOC_END + FULL_IO_SIZE)
+#define IOREMAP_BASE    (PHB_IO_END)
+#define IOREMAP_END     (VMALLOC_START + PGTABLE_RANGE)
+
+/*
+ * Region IDs
+ */
+#define REGION_SHIFT            60UL
+#define REGION_MASK             (0xfUL << REGION_SHIFT)
+#define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
+
+#define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
+#define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
+#define VMEMMAP_REGION_ID       (0xfUL)
+#define USER_REGION_ID          (0UL)
+
+/*
+ * Defines the address of the vmemap area, in its own region
+ */
+#define VMEMMAP_BASE            (VMEMMAP_REGION_ID << REGION_SHIFT)
+#define vmemmap                 ((struct page *)VMEMMAP_BASE)
+
+
+/*
+ * Common bits in a linux-style PTE.  These match the bits in the
+ * (hardware-defined) PowerPC PTE as closely as possible. Additional
+ * bits may be defined in pgtable-*.h
+ */
+#define _PAGE_PRESENT   0x0001 /* software: pte contains a translation */
+#define _PAGE_USER      0x0002 /* matches one of the PP bits */
+#define _PAGE_FILE      0x0002 /* (!present only) software: pte holds file offset */
+#define _PAGE_EXEC      0x0004 /* No execute on POWER4 and newer (we invert) */
+#define _PAGE_GUARDED   0x0008
+#define _PAGE_COHERENT  0x0010 /* M: enforce memory coherence (SMP systems) */
+#define _PAGE_NO_CACHE  0x0020 /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
+#define _PAGE_DIRTY     0x0080 /* C: page changed */
+#define _PAGE_ACCESSED  0x0100 /* R: page referenced */
+#define _PAGE_RW        0x0200 /* software: user write access allowed */
+#define _PAGE_BUSY      0x0800 /* software: PTE & hash are busy */
+
+/* Strong Access Ordering */
+#define _PAGE_SAO       (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
+
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
+
+#define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY)
+
+/* __pgprot defined in arch/powerpc/incliude/asm/page.h */
+#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
+
+#define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
+#define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_KERNEL     __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
+#define PAGE_KERNEL_CI  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                               _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
+
+#define PAGE_AGP        __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
+#define HAVE_PAGE_AGP
+
+#define PAGE_PROT_BITS  __pgprot(_PAGE_GUARDED | _PAGE_COHERENT | \
+                                 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \
+                                 _PAGE_4K_PFN | _PAGE_RW | _PAGE_USER | \
+                                 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
+/* PTEIDX nibble */
+#define _PTEIDX_SECONDARY       0x8
+#define _PTEIDX_GROUP_IX        0x7
+
+
+/*
+ * POWER4 and newer have per page execute protection, older chips can only
+ * do this on a segment (256MB) basis.
+ *
+ * Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ *
+ * Note due to the way vm flags are laid out, the bits are XWR
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_READONLY_X
+#define __P101  PAGE_READONLY_X
+#define __P110  PAGE_COPY_X
+#define __P111  PAGE_COPY_X
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_READONLY_X
+#define __S101  PAGE_READONLY_X
+#define __S110  PAGE_SHARED_X
+#define __S111  PAGE_SHARED_X
+
+#ifdef CONFIG_HUGETLB_PAGE
+
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ *
+ * mk_pte takes a (struct page *) as input
+ */
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
+{
+        pte_t pte;
+
+
+        pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
+        return pte;
+}
+
+#define pte_modify(_pte, newprot) \
+  (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
+
+#define pte_none(pte)           ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+
+/* pte_clear moved to later in this file */
+
+#define pte_pfn(x)              ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#define PMD_BAD_BITS            (PTE_TABLE_SIZE-1)
+#define PUD_BAD_BITS            (PMD_TABLE_SIZE-1)
+
+#define pmd_set(pmdp, pmdval)   (pmd_val(*(pmdp)) = (pmdval))
+#define pmd_none(pmd)           (!pmd_val(pmd))
+#define pmd_bad(pmd)            (!is_kernel_addr(pmd_val(pmd)) \
+                                 || (pmd_val(pmd) & PMD_BAD_BITS))
+#define pmd_present(pmd)        (pmd_val(pmd) != 0)
+#define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
+#define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
+#define pmd_page(pmd)           virt_to_page(pmd_page_vaddr(pmd))
+
+#define pud_set(pudp, pudval)   (pud_val(*(pudp)) = (pudval))
+#define pud_none(pud)           (!pud_val(pud))
+#define pud_bad(pud)            (!is_kernel_addr(pud_val(pud)) \
+                                 || (pud_val(pud) & PUD_BAD_BITS))
+#define pud_present(pud)        (pud_val(pud) != 0)
+#define pud_clear(pudp)         (pud_val(*(pudp)) = 0)
+#define pud_page_vaddr(pud)     (pud_val(pud) & ~PUD_MASKED_BITS)
+#define pud_page(pud)           virt_to_page(pud_page_vaddr(pud))
+
+#define pgd_set(pgdp, pudp)     ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
+
+/*
+ * Find an entry in a page-table-directory.  We combine the address region
+ * (the high order N bits) and the pgd portion of the address.
+ */
+/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
+#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
+
+#define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
+
+#define pmd_offset(pudp,addr) \
+  (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
+
+#define pte_offset_kernel(dir,addr) \
+  (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+
+#define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
+#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
+#define pte_unmap(pte)                  do { } while(0)
+#define pte_unmap_nested(pte)           do { } while(0)
+
+/* to find an entry in a kernel page-table-directory */
+/* This now only contains the vmalloc pages */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
+static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
+static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
+
+static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
+static inline void pte_cache(pte_t pte)   { pte_val(pte) &= ~_PAGE_NO_CACHE; }
+
+static inline pte_t pte_wrprotect(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_RW); return pte; }
+static inline pte_t pte_mkclean(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
+static inline pte_t pte_mkold(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) {
+        pte_val(pte) |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) {
+        pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) {
+        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkhuge(pte_t pte) {
+        return pte; }
+static inline pte_t pte_mkspecial(pte_t pte) {
+        pte_val(pte) |= _PAGE_SPECIAL; return pte; }
+static inline unsigned long pte_pgprot(pte_t pte)
+{
+        return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
+}
+
+/* Atomic PTE updates */
+static inline unsigned long pte_update(struct mm_struct *mm,
+                                       unsigned long addr,
+                                       pte_t *ptep, unsigned long clr,
+                                       int huge)
+{
+        unsigned long old, tmp;
+
+        __asm__ __volatile__(
+        "1:     ldarx   %0,0,%3         # pte_update\n\
+        andi.   %1,%0,%6\n\
+        bne-    1b \n\
+        andc    %1,%0,%4 \n\
+        stdcx.  %1,0,%3 \n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
+        : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
+        : "cc" );
+
+        if (old & _PAGE_HASHPTE)
+                hpte_need_flush(mm, addr, ptep, old, huge);
+        return old;
+}
+
+static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
+                                              unsigned long addr, pte_t *ptep)
+{
+        unsigned long old;
+
+        if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
+                return 0;
+        old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
+        return (old & _PAGE_ACCESSED) != 0;
+}
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
+({                                                                         \
+        int __r;                                                           \
+        __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
+        __r;                                                               \
+})
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+                                      pte_t *ptep)
+{
+        unsigned long old;
+
+        if ((pte_val(*ptep) & _PAGE_RW) == 0)
+                return;
+        old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        unsigned long old;
+
+        if ((pte_val(*ptep) & _PAGE_RW) == 0)
+                return;
+        old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
+}
+
+/*
+ * We currently remove entries from the hashtable regardless of whether
+ * the entry was young or dirty. The generic routines only flush if the
+ * entry was young or dirty which is not good enough.
+ *
+ * We should be more intelligent about this but for the moment we override
+ * these functions and force a tlb flush unconditionally
+ */
+#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
+#define ptep_clear_flush_young(__vma, __address, __ptep)                \
+({                                                                      \
+        int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
+                                                  __ptep);              \
+        __young;                                                        \
+})
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
+                                       unsigned long addr, pte_t *ptep)
+{
+        unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
+        return __pte(old);
+}
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
+                             pte_t * ptep)
+{
+        pte_update(mm, addr, ptep, ~0UL, 0);
+}
+
+/*
+ * set_pte stores a linux PTE into the linux page table.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pte)
+{
+        if (pte_present(*ptep))
+                pte_clear(mm, addr, ptep);
+        pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
+        *ptep = pte;
+}
+
+/* Set the dirty and/or accessed bits atomically in a linux PTE, this
+ * function doesn't need to flush the hash entry
+ */
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
+{
+        unsigned long bits = pte_val(entry) &
+                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
+        unsigned long old, tmp;
+
+        __asm__ __volatile__(
+        "1:     ldarx   %0,0,%4\n\
+                andi.   %1,%0,%6\n\
+                bne-    1b \n\
+                or      %0,%3,%0\n\
+                stdcx.  %0,0,%4\n\
+                bne-    1b"
+        :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
+        :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
+        :"cc");
+}
+#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+({                                                                         \
+        int __changed = !pte_same(*(__ptep), __entry);                     \
+        if (__changed) {                                                   \
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        }                                                                  \
+        __changed;                                                         \
+})
+
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/* Encode and de-code a swap entry */
+#define __swp_type(entry)       (((entry).val >> 1) & 0x3f)
+#define __swp_offset(entry)     ((entry).val >> 8)
+#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
+#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val << PTE_RPN_SHIFT })
+#define pte_to_pgoff(pte)       (pte_val(pte) >> PTE_RPN_SHIFT)
+#define pgoff_to_pte(off)       ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
+#define PTE_FILE_MAX_BITS       (BITS_PER_LONG - PTE_RPN_SHIFT)
+
+void pgtable_cache_init(void);
+
+/*
+ * find_linux_pte returns the address of a linux pte for a given
+ * effective address and directory.  If not found, it returns zero.
+ */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
+{
+        pgd_t *pg;
+        pud_t *pu;
+        pmd_t *pm;
+        pte_t *pt = NULL;
+
+        pg = pgdir + pgd_index(ea);
+        if (!pgd_none(*pg)) {
+                pu = pud_offset(pg, ea);
+                if (!pud_none(*pu)) {
+                        pm = pmd_offset(pu, ea);
+                        if (pmd_present(*pm))
+                                pt = pte_offset_kernel(pm, ea);
+                }
+        }
+        return pt;
+}
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long address);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
new file mode 100644
index 000000000000..dbb8ca172e44
--- /dev/null
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -0,0 +1,57 @@
+#ifndef _ASM_POWERPC_PGTABLE_H
+#define _ASM_POWERPC_PGTABLE_H
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>              /* For TASK_SIZE */
+#include <asm/mmu.h>
+#include <asm/page.h>
+struct mm_struct;
+#endif /* !__ASSEMBLY__ */
+
+#if defined(CONFIG_PPC64)
+#  include <asm/pgtable-ppc64.h>
+#else
+#  include <asm/pgtable-ppc32.h>
+#endif
+
+#ifndef __ASSEMBLY__
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+extern pgd_t swapper_pg_dir[];
+
+extern void paging_init(void);
+
+/*
+ * kern_addr_valid is intended to indicate whether an address is a valid
+ * kernel address.  Most 32-bit archs define it as always true (like this)
+ * but most 64-bit archs actually perform a test.  What should we do here?
+ */
+#define kern_addr_valid(addr)   (1)
+
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+
+#include <asm-generic/pgtable.h>
+
+
+/*
+ * This gets called at the end of handling a page fault, when
+ * the kernel has put a new PTE into the page table for the process.
+ * We use it to ensure coherency between the i-cache and d-cache
+ * for the page which has just been mapped in.
+ * On machines which use an MMU hash table, we use this to put a
+ * corresponding HPTE into the hash table ahead of time, instead of
+ * waiting for the inevitable extra hash-table miss exception.
+ */
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_PGTABLE_H */
diff --git a/arch/powerpc/include/asm/phyp_dump.h b/arch/powerpc/include/asm/phyp_dump.h
new file mode 100644
index 000000000000..fa74c6c3e106
--- /dev/null
+++ b/arch/powerpc/include/asm/phyp_dump.h
@@ -0,0 +1,47 @@
+/*
+ * Hypervisor-assisted dump
+ *
+ * Linas Vepstas, Manish Ahuja 2008
+ * Copyright 2008 IBM Corp.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _PPC64_PHYP_DUMP_H
+#define _PPC64_PHYP_DUMP_H
+
+#ifdef CONFIG_PHYP_DUMP
+
+/* The RMR region will be saved for later dumping
+ * whenever the kernel crashes. Set this to 256MB. */
+#define PHYP_DUMP_RMR_START 0x0
+#define PHYP_DUMP_RMR_END   (1UL<<28)
+
+struct phyp_dump {
+        /* Memory that is reserved during very early boot. */
+        unsigned long init_reserve_start;
+        unsigned long init_reserve_size;
+        /* cmd line options during boot */
+        unsigned long reserve_bootvar;
+        unsigned long phyp_dump_at_boot;
+        /* Check status during boot if dump supported, active & present*/
+        unsigned long phyp_dump_configured;
+        unsigned long phyp_dump_is_active;
+        /* store cpu & hpte size */
+        unsigned long cpu_state_size;
+        unsigned long hpte_region_size;
+        /* previous scratch area values */
+        unsigned long reserved_scratch_addr;
+        unsigned long reserved_scratch_size;
+};
+
+extern struct phyp_dump *phyp_dump_info;
+
+int early_init_dt_scan_phyp_dump(unsigned long node,
+                const char *uname, int depth, void *data);
+
+#endif /* CONFIG_PHYP_DUMP */
+#endif /* _PPC64_PHYP_DUMP_H */
diff --git a/arch/powerpc/include/asm/pmac_feature.h b/arch/powerpc/include/asm/pmac_feature.h
new file mode 100644
index 000000000000..877c35a4356e
--- /dev/null
+++ b/arch/powerpc/include/asm/pmac_feature.h
@@ -0,0 +1,405 @@
+/*
+ * Definition of platform feature hooks for PowerMacs
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Paul Mackerras &
+ *                    Ben. Herrenschmidt.
+ *
+ *
+ * Note: I removed media-bay details from the feature stuff, I believe it's
+ *       not worth it, the media-bay driver can directly use the mac-io
+ *       ASIC registers.
+ *
+ * Implementation note: Currently, none of these functions will block.
+ * However, they may internally protect themselves with a spinlock
+ * for way too long. Be prepared for at least some of these to block
+ * in the future.
+ *
+ * Unless specifically defined, the result code is assumed to be an
+ * error when negative, 0 is the default success result. Some functions
+ * may return additional positive result values.
+ *
+ * To keep implementation simple, all feature calls are assumed to have
+ * the prototype parameters (struct device_node* node, int value).
+ * When either is not used, pass 0.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_PMAC_FEATURE_H
+#define __ASM_POWERPC_PMAC_FEATURE_H
+
+#include <asm/macio.h>
+#include <asm/machdep.h>
+
+/*
+ * Known Mac motherboard models
+ *
+ * Please, report any error here to benh@kernel.crashing.org, thanks !
+ *
+ * Note that I don't fully maintain this list for Core99 & MacRISC2
+ * and I'm considering removing all NewWorld entries from it and
+ * entirely rely on the model string.
+ */
+
+/* PowerSurge are the first generation of PCI Pmacs. This include
+ * all of the Grand-Central based machines. We currently don't
+ * differenciate most of them.
+ */
+#define PMAC_TYPE_PSURGE                0x10    /* PowerSurge */
+#define PMAC_TYPE_ANS                   0x11    /* Apple Network Server */
+
+/* Here is the infamous serie of OHare based machines
+ */
+#define PMAC_TYPE_COMET                 0x20    /* Beleived to be PowerBook 2400 */
+#define PMAC_TYPE_HOOPER                0x21    /* Beleived to be PowerBook 3400 */
+#define PMAC_TYPE_KANGA                 0x22    /* PowerBook 3500 (first G3) */
+#define PMAC_TYPE_ALCHEMY               0x23    /* Alchemy motherboard base */
+#define PMAC_TYPE_GAZELLE               0x24    /* Spartacus, some 5xxx/6xxx */
+#define PMAC_TYPE_UNKNOWN_OHARE         0x2f    /* Unknown, but OHare based */
+
+/* Here are the Heathrow based machines
+ * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
+ */
+#define PMAC_TYPE_GOSSAMER              0x30    /* Gossamer motherboard */
+#define PMAC_TYPE_SILK                  0x31    /* Desktop PowerMac G3 */
+#define PMAC_TYPE_WALLSTREET            0x32    /* Wallstreet/Mainstreet PowerBook*/
+#define PMAC_TYPE_UNKNOWN_HEATHROW      0x3f    /* Unknown but heathrow based */
+
+/* Here are newworld machines based on Paddington (heathrow derivative)
+ */
+#define PMAC_TYPE_101_PBOOK             0x40    /* 101 PowerBook (aka Lombard) */
+#define PMAC_TYPE_ORIG_IMAC             0x41    /* First generation iMac */
+#define PMAC_TYPE_YOSEMITE              0x42    /* B&W G3 */
+#define PMAC_TYPE_YIKES                 0x43    /* Yikes G4 (PCI graphics) */
+#define PMAC_TYPE_UNKNOWN_PADDINGTON    0x4f    /* Unknown but paddington based */
+
+/* Core99 machines based on UniNorth 1.0 and 1.5
+ *
+ * Note: A single entry here may cover several actual models according
+ * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
+ * FireWire based iMacs, etc...). Those machines are too similar to be
+ * distinguished here, when they need to be differencied, use the
+ * device-tree "model" or "compatible" property.
+ */
+#define PMAC_TYPE_ORIG_IBOOK            0x40    /* First iBook model (no firewire) */
+#define PMAC_TYPE_SAWTOOTH              0x41    /* Desktop G4s */
+#define PMAC_TYPE_FW_IMAC               0x42    /* FireWire iMacs (except Pangea based) */
+#define PMAC_TYPE_FW_IBOOK              0x43    /* FireWire iBooks (except iBook2) */
+#define PMAC_TYPE_CUBE                  0x44    /* Cube PowerMac */
+#define PMAC_TYPE_QUICKSILVER           0x45    /* QuickSilver G4s */
+#define PMAC_TYPE_PISMO                 0x46    /* Pismo PowerBook */
+#define PMAC_TYPE_TITANIUM              0x47    /* Titanium PowerBook */
+#define PMAC_TYPE_TITANIUM2             0x48    /* Titanium II PowerBook (no L3, M6) */
+#define PMAC_TYPE_TITANIUM3             0x49    /* Titanium III PowerBook (with L3 & M7) */
+#define PMAC_TYPE_TITANIUM4             0x50    /* Titanium IV PowerBook (with L3 & M9) */
+#define PMAC_TYPE_EMAC                  0x50    /* eMac */
+#define PMAC_TYPE_UNKNOWN_CORE99        0x5f
+
+/* MacRisc2 with UniNorth 2.0 */
+#define PMAC_TYPE_RACKMAC               0x80    /* XServe */
+#define PMAC_TYPE_WINDTUNNEL            0x81
+
+/* MacRISC2 machines based on the Pangea chipset
+ */
+#define PMAC_TYPE_PANGEA_IMAC           0x100   /* Flower Power iMac */
+#define PMAC_TYPE_IBOOK2                0x101   /* iBook2 (polycarbonate) */
+#define PMAC_TYPE_FLAT_PANEL_IMAC       0x102   /* Flat panel iMac */
+#define PMAC_TYPE_UNKNOWN_PANGEA        0x10f
+
+/* MacRISC2 machines based on the Intrepid chipset
+ */
+#define PMAC_TYPE_UNKNOWN_INTREPID      0x11f   /* Generic */
+
+/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
+ * but rather machine families
+ */
+#define PMAC_TYPE_POWERMAC_G5           0x150   /* U3 & U3H based */
+#define PMAC_TYPE_POWERMAC_G5_U3L       0x151   /* U3L based desktop */
+#define PMAC_TYPE_IMAC_G5               0x152   /* iMac G5 */
+#define PMAC_TYPE_XSERVE_G5             0x153   /* Xserve G5 */
+#define PMAC_TYPE_UNKNOWN_K2            0x19f   /* Any other K2 based */
+#define PMAC_TYPE_UNKNOWN_SHASTA        0x19e   /* Any other Shasta based */
+
+/*
+ * Motherboard flags
+ */
+
+#define PMAC_MB_CAN_SLEEP               0x00000001
+#define PMAC_MB_HAS_FW_POWER            0x00000002
+#define PMAC_MB_OLD_CORE99              0x00000004
+#define PMAC_MB_MOBILE                  0x00000008
+#define PMAC_MB_MAY_SLEEP               0x00000010
+
+/*
+ * Feature calls supported on pmac
+ *
+ */
+
+/*
+ * Use this inline wrapper
+ */
+struct device_node;
+
+static inline long pmac_call_feature(int selector, struct device_node* node,
+                                        long param, long value)
+{
+        if (!ppc_md.feature_call || !machine_is(powermac))
+                return -ENODEV;
+        return ppc_md.feature_call(selector, node, param, value);
+}
+
+/* PMAC_FTR_SERIAL_ENABLE       (struct device_node* node, int param, int value)
+ * enable/disable an SCC side. Pass the node corresponding to the
+ * channel side as a parameter.
+ * param is the type of port
+ * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
+ * for use by xmon.
+ */
+#define PMAC_FTR_SCC_ENABLE             PMAC_FTR_DEF(0)
+        #define PMAC_SCC_ASYNC          0
+        #define PMAC_SCC_IRDA           1
+        #define PMAC_SCC_I2S1           2
+        #define PMAC_SCC_FLAG_XMON      0x00001000
+
+/* PMAC_FTR_MODEM_ENABLE        (struct device_node* node, 0, int value)
+ * enable/disable the internal modem.
+ */
+#define PMAC_FTR_MODEM_ENABLE           PMAC_FTR_DEF(1)
+
+/* PMAC_FTR_SWIM3_ENABLE        (struct device_node* node, 0,int value)
+ * enable/disable the swim3 (floppy) cell of a mac-io ASIC
+ */
+#define PMAC_FTR_SWIM3_ENABLE           PMAC_FTR_DEF(2)
+
+/* PMAC_FTR_MESH_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the mesh (scsi) cell of a mac-io ASIC
+ */
+#define PMAC_FTR_MESH_ENABLE            PMAC_FTR_DEF(3)
+
+/* PMAC_FTR_IDE_ENABLE          (struct device_node* node, int busID, int value)
+ * enable/disable an IDE port of a mac-io ASIC
+ * pass the busID parameter
+ */
+#define PMAC_FTR_IDE_ENABLE             PMAC_FTR_DEF(4)
+
+/* PMAC_FTR_IDE_RESET           (struct device_node* node, int busID, int value)
+ * assert(1)/release(0) an IDE reset line (mac-io IDE only)
+ */
+#define PMAC_FTR_IDE_RESET              PMAC_FTR_DEF(5)
+
+/* PMAC_FTR_BMAC_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
+ * it's reset line
+ */
+#define PMAC_FTR_BMAC_ENABLE            PMAC_FTR_DEF(6)
+
+/* PMAC_FTR_GMAC_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
+ * control the cell's clock.
+ */
+#define PMAC_FTR_GMAC_ENABLE            PMAC_FTR_DEF(7)
+
+/* PMAC_FTR_GMAC_PHY_RESET      (struct device_node* node, 0, 0)
+ * Perform a HW reset of the PHY connected to a gmac controller.
+ * Pass the gmac device node, not the PHY node.
+ */
+#define PMAC_FTR_GMAC_PHY_RESET         PMAC_FTR_DEF(8)
+
+/* PMAC_FTR_SOUND_CHIP_ENABLE   (struct device_node* node, 0, int value)
+ * enable/disable the sound chip, whatever it is and provided it can
+ * acually be controlled
+ */
+#define PMAC_FTR_SOUND_CHIP_ENABLE      PMAC_FTR_DEF(9)
+
+/* -- add various tweaks related to sound routing -- */
+
+/* PMAC_FTR_AIRPORT_ENABLE      (struct device_node* node, 0, int value)
+ * enable/disable the airport card
+ */
+#define PMAC_FTR_AIRPORT_ENABLE         PMAC_FTR_DEF(10)
+
+/* PMAC_FTR_RESET_CPU           (NULL, int cpu_nr, 0)
+ * toggle the reset line of a CPU on an uninorth-based SMP machine
+ */
+#define PMAC_FTR_RESET_CPU              PMAC_FTR_DEF(11)
+
+/* PMAC_FTR_USB_ENABLE          (struct device_node* node, 0, int value)
+ * enable/disable an USB cell, along with the power of the USB "pad"
+ * on keylargo based machines
+ */
+#define PMAC_FTR_USB_ENABLE             PMAC_FTR_DEF(12)
+
+/* PMAC_FTR_1394_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the firewire cell of an uninorth ASIC.
+ */
+#define PMAC_FTR_1394_ENABLE            PMAC_FTR_DEF(13)
+
+/* PMAC_FTR_1394_CABLE_POWER    (struct device_node* node, 0, int value)
+ * enable/disable the firewire cable power supply of the uninorth
+ * firewire cell
+ */
+#define PMAC_FTR_1394_CABLE_POWER       PMAC_FTR_DEF(14)
+
+/* PMAC_FTR_SLEEP_STATE         (struct device_node* node, 0, int value)
+ * set the sleep state of the motherboard.
+ *
+ * Pass -1 as value to query for sleep capability
+ * Pass 1 to set IOs to sleep
+ * Pass 0 to set IOs to wake
+ */
+#define PMAC_FTR_SLEEP_STATE            PMAC_FTR_DEF(15)
+
+/* PMAC_FTR_GET_MB_INFO         (NULL, selector, 0)
+ *
+ * returns some motherboard infos.
+ * selector: 0  - model id
+ *           1  - model flags (capabilities)
+ *           2  - model name (cast to const char *)
+ */
+#define PMAC_FTR_GET_MB_INFO            PMAC_FTR_DEF(16)
+#define   PMAC_MB_INFO_MODEL    0
+#define   PMAC_MB_INFO_FLAGS    1
+#define   PMAC_MB_INFO_NAME     2
+
+/* PMAC_FTR_READ_GPIO           (NULL, int index, 0)
+ *
+ * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
+ * the value returned is a byte (positive), or a negative error code
+ */
+#define PMAC_FTR_READ_GPIO              PMAC_FTR_DEF(17)
+
+/* PMAC_FTR_WRITE_GPIO          (NULL, int index, int value)
+ *
+ * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
+ */
+#define PMAC_FTR_WRITE_GPIO             PMAC_FTR_DEF(18)
+
+/* PMAC_FTR_ENABLE_MPIC
+ *
+ * Enable the MPIC cell
+ */
+#define PMAC_FTR_ENABLE_MPIC            PMAC_FTR_DEF(19)
+
+/* PMAC_FTR_AACK_DELAY_ENABLE   (NULL, int enable, 0)
+ *
+ * Enable/disable the AACK delay on the northbridge for systems using DFS
+ */
+#define PMAC_FTR_AACK_DELAY_ENABLE      PMAC_FTR_DEF(20)
+
+/* PMAC_FTR_DEVICE_CAN_WAKE
+ *
+ * Used by video drivers to inform system that they can actually perform
+ * wakeup from sleep
+ */
+#define PMAC_FTR_DEVICE_CAN_WAKE        PMAC_FTR_DEF(22)
+
+
+/* Don't use those directly, they are for the sake of pmac_setup.c */
+extern long pmac_do_feature_call(unsigned int selector, ...);
+extern void pmac_feature_init(void);
+
+/* Video suspend tweak */
+extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
+extern void pmac_call_early_video_resume(void);
+
+#define PMAC_FTR_DEF(x) ((0x6660000) | (x))
+
+/* The AGP driver registers itself here */
+extern void pmac_register_agp_pm(struct pci_dev *bridge,
+                                 int (*suspend)(struct pci_dev *bridge),
+                                 int (*resume)(struct pci_dev *bridge));
+
+/* Those are meant to be used by video drivers to deal with AGP
+ * suspend resume properly
+ */
+extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
+extern void pmac_resume_agp_for_card(struct pci_dev *dev);
+
+/*
+ * The part below is for use by macio_asic.c only, do not rely
+ * on the data structures or constants below in a normal driver
+ *
+ */
+
+#define MAX_MACIO_CHIPS         2
+
+enum {
+        macio_unknown = 0,
+        macio_grand_central,
+        macio_ohare,
+        macio_ohareII,
+        macio_heathrow,
+        macio_gatwick,
+        macio_paddington,
+        macio_keylargo,
+        macio_pangea,
+        macio_intrepid,
+        macio_keylargo2,
+        macio_shasta,
+};
+
+struct macio_chip
+{
+        struct device_node      *of_node;
+        int                     type;
+        const char              *name;
+        int                     rev;
+        volatile u32            __iomem *base;
+        unsigned long           flags;
+
+        /* For use by macio_asic PCI driver */
+        struct macio_bus        lbus;
+};
+
+extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
+
+#define MACIO_FLAG_SCCA_ON      0x00000001
+#define MACIO_FLAG_SCCB_ON      0x00000002
+#define MACIO_FLAG_SCC_LOCKED   0x00000004
+#define MACIO_FLAG_AIRPORT_ON   0x00000010
+#define MACIO_FLAG_FW_SUPPORTED 0x00000020
+
+extern struct macio_chip* macio_find(struct device_node* child, int type);
+
+#define MACIO_FCR32(macio, r)   ((macio)->base + ((r) >> 2))
+#define MACIO_FCR8(macio, r)    (((volatile u8 __iomem *)((macio)->base)) + (r))
+
+#define MACIO_IN32(r)           (in_le32(MACIO_FCR32(macio,r)))
+#define MACIO_OUT32(r,v)        (out_le32(MACIO_FCR32(macio,r), (v)))
+#define MACIO_BIS(r,v)          (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
+#define MACIO_BIC(r,v)          (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
+#define MACIO_IN8(r)            (in_8(MACIO_FCR8(macio,r)))
+#define MACIO_OUT8(r,v)         (out_8(MACIO_FCR8(macio,r), (v)))
+
+/*
+ * Those are exported by pmac feature for internal use by arch code
+ * only like the platform function callbacks, do not use directly in drivers
+ */
+extern spinlock_t feature_lock;
+extern struct device_node *uninorth_node;
+extern u32 __iomem *uninorth_base;
+
+/*
+ * Uninorth reg. access. Note that Uni-N regs are big endian
+ */
+
+#define UN_REG(r)       (uninorth_base + ((r) >> 2))
+#define UN_IN(r)        (in_be32(UN_REG(r)))
+#define UN_OUT(r,v)     (out_be32(UN_REG(r), (v)))
+#define UN_BIS(r,v)     (UN_OUT((r), UN_IN(r) | (v)))
+#define UN_BIC(r,v)     (UN_OUT((r), UN_IN(r) & ~(v)))
+
+/* Uninorth variant:
+ *
+ * 0 = not uninorth
+ * 1 = U1.x or U2.x
+ * 3 = U3
+ * 4 = U4
+ */
+extern int pmac_get_uninorth_variant(void);
+
+#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/pmac_low_i2c.h b/arch/powerpc/include/asm/pmac_low_i2c.h
new file mode 100644
index 000000000000..131011bd7e76
--- /dev/null
+++ b/arch/powerpc/include/asm/pmac_low_i2c.h
@@ -0,0 +1,107 @@
+/* 
+ *  include/asm-ppc/pmac_low_i2c.h
+ *
+ *  Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+#ifndef __PMAC_LOW_I2C_H__
+#define __PMAC_LOW_I2C_H__
+#ifdef __KERNEL__
+
+/* i2c mode (based on the platform functions format) */
+enum {
+        pmac_i2c_mode_dumb      = 1,
+        pmac_i2c_mode_std       = 2,
+        pmac_i2c_mode_stdsub    = 3,
+        pmac_i2c_mode_combined  = 4,
+};
+
+/* RW bit in address */
+enum {
+        pmac_i2c_read           = 0x01,
+        pmac_i2c_write          = 0x00
+};
+
+/* i2c bus type */
+enum {
+        pmac_i2c_bus_keywest    = 0,
+        pmac_i2c_bus_pmu        = 1,
+        pmac_i2c_bus_smu        = 2,
+};
+
+/* i2c bus features */
+enum {
+        /* can_largesub : supports >1 byte subaddresses (SMU only) */
+        pmac_i2c_can_largesub   = 0x00000001u,
+
+        /* multibus : device node holds multiple busses, bus number is
+         * encoded in bits 0xff00 of "reg" of a given device
+         */
+        pmac_i2c_multibus       = 0x00000002u,
+};
+
+/* i2c busses in the system */
+struct pmac_i2c_bus;
+struct i2c_adapter;
+
+/* Init, called early during boot */
+extern int pmac_i2c_init(void);
+
+/* Lookup an i2c bus for a device-node. The node can be either the bus
+ * node itself or a device below it. In the case of a multibus, the bus
+ * node itself is the controller node, else, it's a child of the controller
+ * node
+ */
+extern struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node);
+
+/* Get the address for an i2c device. This strips the bus number if
+ * necessary. The 7 bits address is returned 1 bit right shifted so that the
+ * direction can be directly ored in
+ */
+extern u8 pmac_i2c_get_dev_addr(struct device_node *device);
+
+/* Get infos about a bus */
+extern struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus);
+extern struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus);
+extern int pmac_i2c_get_type(struct pmac_i2c_bus *bus);
+extern int pmac_i2c_get_flags(struct pmac_i2c_bus *bus);
+extern int pmac_i2c_get_channel(struct pmac_i2c_bus *bus);
+
+/* i2c layer adapter attach/detach */
+extern void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
+                                    struct i2c_adapter *adapter);
+extern void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
+                                    struct i2c_adapter *adapter);
+extern struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus);
+extern struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter);
+
+/* March a device or bus with an i2c adapter structure, to be used by drivers
+ * to match device-tree nodes with i2c adapters during adapter discovery
+ * callbacks
+ */
+extern int pmac_i2c_match_adapter(struct device_node *dev,
+                                  struct i2c_adapter *adapter);
+
+
+/* (legacy) Locking functions exposed to i2c-keywest */
+extern int pmac_low_i2c_lock(struct device_node *np);
+extern int pmac_low_i2c_unlock(struct device_node *np);
+
+/* Access functions for platform code */
+extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled);
+extern void pmac_i2c_close(struct pmac_i2c_bus *bus);
+extern int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode);
+extern int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
+                         u32 subaddr, u8 *data,  int len);
+
+/* Suspend/resume code called by via-pmu directly for now */
+extern void pmac_pfunc_i2c_suspend(void);
+extern void pmac_pfunc_i2c_resume(void);
+
+#endif /* __KERNEL__ */
+#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/arch/powerpc/include/asm/pmac_pfunc.h b/arch/powerpc/include/asm/pmac_pfunc.h
new file mode 100644
index 000000000000..1330d6a58c57
--- /dev/null
+++ b/arch/powerpc/include/asm/pmac_pfunc.h
@@ -0,0 +1,252 @@
+#ifndef __PMAC_PFUNC_H__
+#define __PMAC_PFUNC_H__
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+/* Flags in command lists */
+#define PMF_FLAGS_ON_INIT               0x80000000u
+#define PMF_FLGAS_ON_TERM               0x40000000u
+#define PMF_FLAGS_ON_SLEEP              0x20000000u
+#define PMF_FLAGS_ON_WAKE               0x10000000u
+#define PMF_FLAGS_ON_DEMAND             0x08000000u
+#define PMF_FLAGS_INT_GEN               0x04000000u
+#define PMF_FLAGS_HIGH_SPEED            0x02000000u
+#define PMF_FLAGS_LOW_SPEED             0x01000000u
+#define PMF_FLAGS_SIDE_EFFECTS          0x00800000u
+
+/*
+ * Arguments to a platform function call.
+ *
+ * NOTE: By convention, pointer arguments point to an u32
+ */
+struct pmf_args {
+        union {
+                u32 v;
+                u32 *p;
+        } u[4];
+        unsigned int count;
+};
+
+/*
+ * A driver capable of interpreting commands provides a handlers
+ * structure filled with whatever handlers are implemented by this
+ * driver. Non implemented handlers are left NULL.
+ *
+ * PMF_STD_ARGS are the same arguments that are passed to the parser
+ * and that gets passed back to the various handlers.
+ *
+ * Interpreting a given function always start with a begin() call which
+ * returns an instance data to be passed around subsequent calls, and
+ * ends with an end() call. This allows the low level driver to implement
+ * locking policy or per-function instance data.
+ *
+ * For interrupt capable functions, irq_enable() is called when a client
+ * registers, and irq_disable() is called when the last client unregisters
+ * Note that irq_enable & irq_disable are called within a semaphore held
+ * by the core, thus you should not try to register yourself to some other
+ * pmf interrupt during those calls.
+ */
+
+#define PMF_STD_ARGS    struct pmf_function *func, void *instdata, \
+                        struct pmf_args *args
+
+struct pmf_function;
+
+struct pmf_handlers {
+        void * (*begin)(struct pmf_function *func, struct pmf_args *args);
+        void (*end)(struct pmf_function *func, void *instdata);
+
+        int (*irq_enable)(struct pmf_function *func);
+        int (*irq_disable)(struct pmf_function *func);
+
+        int (*write_gpio)(PMF_STD_ARGS, u8 value, u8 mask);
+        int (*read_gpio)(PMF_STD_ARGS, u8 mask, int rshift, u8 xor);
+
+        int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
+        int (*read_reg32)(PMF_STD_ARGS, u32 offset);
+        int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
+        int (*read_reg16)(PMF_STD_ARGS, u32 offset);
+        int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
+        int (*read_reg8)(PMF_STD_ARGS, u32 offset);
+
+        int (*delay)(PMF_STD_ARGS, u32 duration);
+
+        int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
+        int (*wait_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
+        int (*wait_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
+
+        int (*read_i2c)(PMF_STD_ARGS, u32 len);
+        int (*write_i2c)(PMF_STD_ARGS, u32 len, const u8 *data);
+        int (*rmw_i2c)(PMF_STD_ARGS, u32 masklen, u32 valuelen, u32 totallen,
+                       const u8 *maskdata, const u8 *valuedata);
+
+        int (*read_cfg)(PMF_STD_ARGS, u32 offset, u32 len);
+        int (*write_cfg)(PMF_STD_ARGS, u32 offset, u32 len, const u8 *data);
+        int (*rmw_cfg)(PMF_STD_ARGS, u32 offset, u32 masklen, u32 valuelen,
+                       u32 totallen, const u8 *maskdata, const u8 *valuedata);
+
+        int (*read_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len);
+        int (*write_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len, const u8 *data);
+        int (*set_i2c_mode)(PMF_STD_ARGS, int mode);
+        int (*rmw_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 masklen, u32 valuelen,
+                           u32 totallen, const u8 *maskdata,
+                           const u8 *valuedata);
+
+        int (*read_reg32_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
+                               u32 xor);
+        int (*read_reg16_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
+                               u32 xor);
+        int (*read_reg8_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
+                              u32 xor);
+
+        int (*write_reg32_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
+        int (*write_reg16_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
+        int (*write_reg8_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
+
+        int (*mask_and_compare)(PMF_STD_ARGS, u32 len, const u8 *maskdata,
+                                const u8 *valuedata);
+
+        struct module *owner;
+};
+
+
+/*
+ * Drivers who expose platform functions register at init time, this
+ * causes the platform functions for that device node to be parsed in
+ * advance and associated with the device. The data structures are
+ * partially public so a driver can walk the list of platform functions
+ * and eventually inspect the flags
+ */
+struct pmf_device;
+
+struct pmf_function {
+        /* All functions for a given driver are linked */
+        struct list_head        link;
+
+        /* Function node & driver data */
+        struct device_node      *node;
+        void                    *driver_data;
+
+        /* For internal use by core */
+        struct pmf_device       *dev;
+
+        /* The name is the "xxx" in "platform-do-xxx", this is how
+         * platform functions are identified by this code. Some functions
+         * only operate for a given target, in which case the phandle is
+         * here (or 0 if the filter doesn't apply)
+         */
+        const char              *name;
+        u32                     phandle;
+
+        /* The flags for that function. You can have several functions
+         * with the same name and different flag
+         */
+        u32                     flags;
+
+        /* The actual tokenized function blob */
+        const void              *data;
+        unsigned int            length;
+
+        /* Interrupt clients */
+        struct list_head        irq_clients;
+
+        /* Refcounting */
+        struct kref             ref;
+};
+
+/*
+ * For platform functions that are interrupts, one can register
+ * irq_client structures. You canNOT use the same structure twice
+ * as it contains a link member. Also, the callback is called with
+ * a spinlock held, you must not call back into any of the pmf_* functions
+ * from within that callback
+ */
+struct pmf_irq_client {
+        void                    (*handler)(void *data);
+        void                    *data;
+        struct module           *owner;
+        struct list_head        link;
+        struct pmf_function     *func;
+};
+
+
+/*
+ * Register/Unregister a function-capable driver and its handlers
+ */
+extern int pmf_register_driver(struct device_node *np,
+                              struct pmf_handlers *handlers,
+                              void *driverdata);
+
+extern void pmf_unregister_driver(struct device_node *np);
+
+
+/*
+ * Register/Unregister interrupt clients
+ */
+extern int pmf_register_irq_client(struct device_node *np,
+                                   const char *name,
+                                   struct pmf_irq_client *client);
+
+extern void pmf_unregister_irq_client(struct pmf_irq_client *client);
+
+/*
+ * Called by the handlers when an irq happens
+ */
+extern void pmf_do_irq(struct pmf_function *func);
+
+
+/*
+ * Low level call to platform functions.
+ *
+ * The phandle can filter on the target object for functions that have
+ * multiple targets, the flags allow you to restrict the call to a given
+ * combination of flags.
+ *
+ * The args array contains as many arguments as is required by the function,
+ * this is dependent on the function you are calling, unfortunately Apple
+ * mechanism provides no way to encode that so you have to get it right at
+ * the call site. Some functions require no args, in which case, you can
+ * pass NULL.
+ *
+ * You can also pass NULL to the name. This will match any function that has
+ * the appropriate combination of flags & phandle or you can pass 0 to the
+ * phandle to match any
+ */
+extern int pmf_do_functions(struct device_node *np, const char *name,
+                            u32 phandle, u32 flags, struct pmf_args *args);
+
+
+
+/*
+ * High level call to a platform function.
+ *
+ * This one looks for the platform-xxx first so you should call it to the
+ * actual target if any. It will fallback to platform-do-xxx if it can't
+ * find one. It will also exclusively target functions that have
+ * the "OnDemand" flag.
+ */
+
+extern int pmf_call_function(struct device_node *target, const char *name,
+                             struct pmf_args *args);
+
+
+/*
+ * For low latency interrupt usage, you can lookup for on-demand functions
+ * using the functions below
+ */
+
+extern struct pmf_function *pmf_find_function(struct device_node *target,
+                                              const char *name);
+
+extern struct pmf_function * pmf_get_function(struct pmf_function *func);
+extern void pmf_put_function(struct pmf_function *func);
+
+extern int pmf_call_one(struct pmf_function *func, struct pmf_args *args);
+
+
+/* Suspend/resume code called by via-pmu directly for now */
+extern void pmac_pfunc_base_suspend(void);
+extern void pmac_pfunc_base_resume(void);
+
+#endif /* __PMAC_PFUNC_H__ */
diff --git a/arch/powerpc/include/asm/pmc.h b/arch/powerpc/include/asm/pmc.h
new file mode 100644
index 000000000000..d6a616a1b3ea
--- /dev/null
+++ b/arch/powerpc/include/asm/pmc.h
@@ -0,0 +1,37 @@
+/*
+ * pmc.h
+ * Copyright (C) 2004  David Gibson, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _POWERPC_PMC_H
+#define _POWERPC_PMC_H
+#ifdef __KERNEL__
+
+#include <asm/ptrace.h>
+
+typedef void (*perf_irq_t)(struct pt_regs *);
+extern perf_irq_t perf_irq;
+
+int reserve_pmc_hardware(perf_irq_t new_perf_irq);
+void release_pmc_hardware(void);
+
+#ifdef CONFIG_PPC64
+void power4_enable_pmcs(void);
+void pasemi_enable_pmcs(void);
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _POWERPC_PMC_H */
diff --git a/arch/powerpc/include/asm/pmi.h b/arch/powerpc/include/asm/pmi.h
new file mode 100644
index 000000000000..b4e91fbf5081
--- /dev/null
+++ b/arch/powerpc/include/asm/pmi.h
@@ -0,0 +1,66 @@
+#ifndef _POWERPC_PMI_H
+#define _POWERPC_PMI_H
+
+/*
+ * Definitions for talking with PMI device on PowerPC
+ *
+ * PMI (Platform Management Interrupt) is a way to communicate
+ * with the BMC (Baseboard Management Controller) via interrupts.
+ * Unlike IPMI it is bidirectional and has a low latency.
+ *
+ * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
+ *
+ * Author: Christian Krafft <krafft@de.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifdef __KERNEL__
+
+#define PMI_TYPE_FREQ_CHANGE    0x01
+#define PMI_TYPE_POWER_BUTTON   0x02
+#define PMI_READ_TYPE           0
+#define PMI_READ_DATA0          1
+#define PMI_READ_DATA1          2
+#define PMI_READ_DATA2          3
+#define PMI_WRITE_TYPE          4
+#define PMI_WRITE_DATA0         5
+#define PMI_WRITE_DATA1         6
+#define PMI_WRITE_DATA2         7
+
+#define PMI_ACK                 0x80
+
+#define PMI_TIMEOUT             100
+
+typedef struct {
+        u8      type;
+        u8      data0;
+        u8      data1;
+        u8      data2;
+} pmi_message_t;
+
+struct pmi_handler {
+        struct list_head node;
+        u8 type;
+        void (*handle_pmi_message) (pmi_message_t);
+};
+
+int pmi_register_handler(struct pmi_handler *);
+void pmi_unregister_handler(struct pmi_handler *);
+
+int pmi_send_message(pmi_message_t);
+
+#endif /* __KERNEL__ */
+#endif /* _POWERPC_PMI_H */
diff --git a/arch/powerpc/include/asm/poll.h b/arch/powerpc/include/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/powerpc/include/asm/poll.h
@@ -0,0 +1 @@
+#include <asm-generic/poll.h>
diff --git a/arch/powerpc/include/asm/posix_types.h b/arch/powerpc/include/asm/posix_types.h
new file mode 100644
index 000000000000..c4e396b540df
--- /dev/null
+++ b/arch/powerpc/include/asm/posix_types.h
@@ -0,0 +1,128 @@
+#ifndef _ASM_POWERPC_POSIX_TYPES_H
+#define _ASM_POWERPC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+typedef long            __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef long            __kernel_suseconds_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+typedef unsigned int    __kernel_old_uid_t;
+typedef unsigned int    __kernel_old_gid_t;
+
+#ifdef __powerpc64__
+typedef unsigned long   __kernel_nlink_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
+typedef unsigned long   __kernel_old_dev_t;
+#else
+typedef unsigned short  __kernel_nlink_t;
+typedef short           __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef unsigned int    __kernel_old_dev_t;
+#endif
+
+#ifdef __powerpc64__
+typedef long long       __kernel_loff_t;
+#else
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+#endif
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define __FD_ISSET(d, set)      (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
+#define __FD_ZERO(set)  \
+  ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{ 
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+        unsigned long *tmp = (unsigned long *)p->fds_bits;
+        int i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                      case 16:
+                        tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                        tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+
+                      case 8:
+                        tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+
+                      case 4:
+                        tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                        return;
+                }
+        }
+        i = __FDSET_LONGS;
+        while (i) {
+                i--;
+                *tmp = 0;
+                tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) */
+#endif /* __GNUC__ */
+#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
new file mode 100644
index 000000000000..854ab713f56c
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -0,0 +1,149 @@
+/*
+ * c 2001 PPC 64 Team, IBM Corp
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_PPC_PCI_H
+#define _ASM_POWERPC_PPC_PCI_H
+#ifdef __KERNEL__
+
+#ifdef CONFIG_PCI
+
+#include <linux/pci.h>
+#include <asm/pci-bridge.h>
+
+extern unsigned long isa_io_base;
+
+extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
+extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
+
+
+extern struct list_head hose_list;
+
+extern void find_and_init_phbs(void);
+
+extern struct pci_dev *isa_bridge_pcidev;       /* may be NULL if no ISA bus */
+
+/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
+#define BUID_HI(buid) ((buid) >> 32)
+#define BUID_LO(buid) ((buid) & 0xffffffff)
+
+/* PCI device_node operations */
+struct device_node;
+typedef void *(*traverse_func)(struct device_node *me, void *data);
+void *traverse_pci_devices(struct device_node *start, traverse_func pre,
+                void *data);
+
+extern void pci_devs_phb_init(void);
+extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
+extern void scan_phb(struct pci_controller *hose);
+
+/* From rtas_pci.h */
+extern void init_pci_config_tokens (void);
+extern unsigned long get_phb_buid (struct device_node *);
+extern int rtas_setup_phb(struct pci_controller *phb);
+
+extern unsigned long pci_probe_only;
+
+/* ---- EEH internal-use-only related routines ---- */
+#ifdef CONFIG_EEH
+
+void pci_addr_cache_insert_device(struct pci_dev *dev);
+void pci_addr_cache_remove_device(struct pci_dev *dev);
+void pci_addr_cache_build(void);
+struct pci_dev *pci_get_device_by_addr(unsigned long addr);
+
+/**
+ * eeh_slot_error_detail -- record and EEH error condition to the log
+ * @pdn:      pci device node
+ * @severity: EEH_LOG_TEMP_FAILURE or EEH_LOG_PERM_FAILURE
+ *
+ * Obtains the EEH error details from the RTAS subsystem,
+ * and then logs these details with the RTAS error log system.
+ */
+#define EEH_LOG_TEMP_FAILURE 1
+#define EEH_LOG_PERM_FAILURE 2
+void eeh_slot_error_detail (struct pci_dn *pdn, int severity);
+
+/**
+ * rtas_pci_enable - enable IO transfers for this slot
+ * @pdn:       pci device node
+ * @function:  either EEH_THAW_MMIO or EEH_THAW_DMA 
+ *
+ * Enable I/O transfers to this slot 
+ */
+#define EEH_THAW_MMIO 2
+#define EEH_THAW_DMA  3
+int rtas_pci_enable(struct pci_dn *pdn, int function);
+
+/**
+ * rtas_set_slot_reset -- unfreeze a frozen slot
+ * @pdn:       pci device node
+ *
+ * Clear the EEH-frozen condition on a slot.  This routine
+ * does this by asserting the PCI #RST line for 1/8th of
+ * a second; this routine will sleep while the adapter is
+ * being reset.
+ *
+ * Returns a non-zero value if the reset failed.
+ */
+int rtas_set_slot_reset (struct pci_dn *);
+int eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs);
+
+/** 
+ * eeh_restore_bars - Restore device configuration info.
+ * @pdn:       pci device node
+ *
+ * A reset of a PCI device will clear out its config space.
+ * This routines will restore the config space for this
+ * device, and is children, to values previously obtained
+ * from the firmware.
+ */
+void eeh_restore_bars(struct pci_dn *);
+
+/**
+ * rtas_configure_bridge -- firmware initialization of pci bridge
+ * @pdn:       pci device node
+ *
+ * Ask the firmware to configure all PCI bridges devices
+ * located behind the indicated node. Required after a
+ * pci device reset. Does essentially the same hing as
+ * eeh_restore_bars, but for brdges, and lets firmware 
+ * do the work.
+ */
+void rtas_configure_bridge(struct pci_dn *);
+
+int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
+int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
+
+/**
+ * eeh_mark_slot -- set mode flags for pertition endpoint
+ * @pdn:       pci device node
+ *
+ * mark and clear slots: find "partition endpoint" PE and set or 
+ * clear the flags for each subnode of the PE.
+ */
+void eeh_mark_slot (struct device_node *dn, int mode_flag);
+void eeh_clear_slot (struct device_node *dn, int mode_flag);
+
+/**
+ * find_device_pe -- Find the associated "Partiationable Endpoint" PE
+ * @pdn:       pci device node
+ */
+struct device_node * find_device_pe(struct device_node *dn);
+
+void eeh_sysfs_add_device(struct pci_dev *pdev);
+void eeh_sysfs_remove_device(struct pci_dev *pdev);
+
+#endif /* CONFIG_EEH */
+
+#else /* CONFIG_PCI */
+static inline void find_and_init_phbs(void) { }
+static inline void init_pci_config_tokens(void) { }
+#endif /* !CONFIG_PCI */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h
new file mode 100644
index 000000000000..033039a80c42
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc4xx.h
@@ -0,0 +1,18 @@
+/*
+ * PPC4xx Prototypes and definitions
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_PPC4xx_H__
+#define __ASM_POWERPC_PPC4xx_H__
+
+extern void ppc4xx_reset_system(char *cmd);
+
+#endif /* __ASM_POWERPC_PPC4xx_H__ */
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
new file mode 100644
index 000000000000..0966899d974b
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -0,0 +1,689 @@
+/*
+ * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
+ */
+#ifndef _ASM_POWERPC_PPC_ASM_H
+#define _ASM_POWERPC_PPC_ASM_H
+
+#include <linux/stringify.h>
+#include <asm/asm-compat.h>
+#include <asm/processor.h>
+
+#ifndef __ASSEMBLY__
+#error __FILE__ should only be used in assembler files
+#else
+
+#define SZL                     (BITS_PER_LONG/8)
+
+/*
+ * Stuff for accurate CPU time accounting.
+ * These macros handle transitions between user and system state
+ * in exception entry and exit and accumulate time to the
+ * user_time and system_time fields in the paca.
+ */
+
+#ifndef CONFIG_VIRT_CPU_ACCOUNTING
+#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
+#define ACCOUNT_CPU_USER_EXIT(ra, rb)
+#else
+#define ACCOUNT_CPU_USER_ENTRY(ra, rb)                                  \
+        beq     2f;                     /* if from kernel mode */       \
+BEGIN_FTR_SECTION;                                                      \
+        mfspr   ra,SPRN_PURR;           /* get processor util. reg */   \
+END_FTR_SECTION_IFSET(CPU_FTR_PURR);                                    \
+BEGIN_FTR_SECTION;                                                      \
+        MFTB(ra);                       /* or get TB if no PURR */      \
+END_FTR_SECTION_IFCLR(CPU_FTR_PURR);                                    \
+        ld      rb,PACA_STARTPURR(r13);                                 \
+        std     ra,PACA_STARTPURR(r13);                                 \
+        subf    rb,rb,ra;               /* subtract start value */      \
+        ld      ra,PACA_USER_TIME(r13);                                 \
+        add     ra,ra,rb;               /* add on to user time */       \
+        std     ra,PACA_USER_TIME(r13);                                 \
+2:
+
+#define ACCOUNT_CPU_USER_EXIT(ra, rb)                                   \
+BEGIN_FTR_SECTION;                                                      \
+        mfspr   ra,SPRN_PURR;           /* get processor util. reg */   \
+END_FTR_SECTION_IFSET(CPU_FTR_PURR);                                    \
+BEGIN_FTR_SECTION;                                                      \
+        MFTB(ra);                       /* or get TB if no PURR */      \
+END_FTR_SECTION_IFCLR(CPU_FTR_PURR);                                    \
+        ld      rb,PACA_STARTPURR(r13);                                 \
+        std     ra,PACA_STARTPURR(r13);                                 \
+        subf    rb,rb,ra;               /* subtract start value */      \
+        ld      ra,PACA_SYSTEM_TIME(r13);                               \
+        add     ra,ra,rb;               /* add on to user time */       \
+        std     ra,PACA_SYSTEM_TIME(r13);
+#endif
+
+/*
+ * Macros for storing registers into and loading registers from
+ * exception frames.
+ */
+#ifdef __powerpc64__
+#define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
+#define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
+#define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
+#else
+#define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
+#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
+#define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
+                                SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
+                                REST_10GPRS(22, base)
+#endif
+
+/*
+ * Define what the VSX XX1 form instructions will look like, then add
+ * the 128 bit load store instructions based on that.
+ */
+#define VSX_XX1(xs, ra, rb)     (((xs) & 0x1f) << 21 | ((ra) << 16) |  \
+                                 ((rb) << 11) | (((xs) >> 5)))
+
+#define STXVD2X(xs, ra, rb)     .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
+#define LXVD2X(xs, ra, rb)      .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
+
+#define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+#define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
+#define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
+#define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
+#define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
+#define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
+#define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
+#define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
+#define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
+#define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
+#define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
+#define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
+#define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
+
+#define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
+#define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
+#define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
+#define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
+#define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
+#define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
+#define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
+#define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
+#define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
+#define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
+#define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
+#define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
+
+/* Save the lower 32 VSRs in the thread VSR region */
+#define SAVE_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n));  STXVD2X(n,b,base)
+#define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
+#define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
+#define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
+#define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
+#define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
+#define REST_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
+#define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
+#define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
+#define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
+#define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
+#define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
+/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
+#define SAVE_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,b,base)
+#define SAVE_2VSRSU(n,b,base)   SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
+#define SAVE_4VSRSU(n,b,base)   SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
+#define SAVE_8VSRSU(n,b,base)   SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
+#define SAVE_16VSRSU(n,b,base)  SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
+#define SAVE_32VSRSU(n,b,base)  SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
+#define REST_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
+#define REST_2VSRSU(n,b,base)   REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
+#define REST_4VSRSU(n,b,base)   REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
+#define REST_8VSRSU(n,b,base)   REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
+#define REST_16VSRSU(n,b,base)  REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
+#define REST_32VSRSU(n,b,base)  REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
+
+#define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
+#define SAVE_2EVRS(n,s,base)    SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
+#define SAVE_4EVRS(n,s,base)    SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
+#define SAVE_8EVRS(n,s,base)    SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
+#define SAVE_16EVRS(n,s,base)   SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
+#define SAVE_32EVRS(n,s,base)   SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
+#define REST_EVR(n,s,base)      lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
+#define REST_2EVRS(n,s,base)    REST_EVR(n,s,base); REST_EVR(n+1,s,base)
+#define REST_4EVRS(n,s,base)    REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
+#define REST_8EVRS(n,s,base)    REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
+#define REST_16EVRS(n,s,base)   REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
+#define REST_32EVRS(n,s,base)   REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
+
+/* Macros to adjust thread priority for hardware multithreading */
+#define HMT_VERY_LOW    or      31,31,31        # very low priority
+#define HMT_LOW         or      1,1,1
+#define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
+#define HMT_MEDIUM      or      2,2,2
+#define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
+#define HMT_HIGH        or      3,3,3
+
+/* handle instructions that older assemblers may not know */
+#define RFCI            .long 0x4c000066        /* rfci instruction */
+#define RFDI            .long 0x4c00004e        /* rfdi instruction */
+#define RFMCI           .long 0x4c00004c        /* rfmci instruction */
+
+#ifdef __KERNEL__
+#ifdef CONFIG_PPC64
+
+#define XGLUE(a,b) a##b
+#define GLUE(a,b) XGLUE(a,b)
+
+#define _GLOBAL(name) \
+        .section ".text"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _INIT_GLOBAL(name) \
+        .section ".text.init.refok"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _KPROBE(name) \
+        .section ".kprobes.text","a"; \
+        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _STATIC(name) \
+        .section ".text"; \
+        .align 2 ; \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _INIT_STATIC(name) \
+        .section ".text.init.refok"; \
+        .align 2 ; \
+        .section ".opd","aw"; \
+name: \
+        .quad GLUE(.,name); \
+        .quad .TOC.@tocbase; \
+        .quad 0; \
+        .previous; \
+        .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#else /* 32-bit */
+
+#define _ENTRY(n)       \
+        .globl n;       \
+n:
+
+#define _GLOBAL(n)      \
+        .text;          \
+        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
+        .globl n;       \
+n:
+
+#define _KPROBE(n)      \
+        .section ".kprobes.text","a";   \
+        .globl  n;      \
+n:
+
+#endif
+
+/* 
+ * LOAD_REG_IMMEDIATE(rn, expr)
+ *   Loads the value of the constant expression 'expr' into register 'rn'
+ *   using immediate instructions only.  Use this when it's important not
+ *   to reference other data (i.e. on ppc64 when the TOC pointer is not
+ *   valid).
+ *
+ * LOAD_REG_ADDR(rn, name)
+ *   Loads the address of label 'name' into register 'rn'.  Use this when
+ *   you don't particularly need immediate instructions only, but you need
+ *   the whole address in one register (e.g. it's a structure address and
+ *   you want to access various offsets within it).  On ppc32 this is
+ *   identical to LOAD_REG_IMMEDIATE.
+ *
+ * LOAD_REG_ADDRBASE(rn, name)
+ * ADDROFF(name)
+ *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
+ *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
+ *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
+ *   in size, so is suitable for use directly as an offset in load and store
+ *   instructions.  Use this when loading/storing a single word or less as:
+ *      LOAD_REG_ADDRBASE(rX, name)
+ *      ld      rY,ADDROFF(name)(rX)
+ */
+#ifdef __powerpc64__
+#define LOAD_REG_IMMEDIATE(reg,expr)            \
+        lis     (reg),(expr)@highest;           \
+        ori     (reg),(reg),(expr)@higher;      \
+        rldicr  (reg),(reg),32,31;              \
+        oris    (reg),(reg),(expr)@h;           \
+        ori     (reg),(reg),(expr)@l;
+
+#define LOAD_REG_ADDR(reg,name)                 \
+        ld      (reg),name@got(r2)
+
+#define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
+#define ADDROFF(name)                   0
+
+/* offsets for stack frame layout */
+#define LRSAVE  16
+
+#else /* 32-bit */
+
+#define LOAD_REG_IMMEDIATE(reg,expr)            \
+        lis     (reg),(expr)@ha;                \
+        addi    (reg),(reg),(expr)@l;
+
+#define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE(reg, name)
+
+#define LOAD_REG_ADDRBASE(reg, name)    lis     (reg),name@ha
+#define ADDROFF(name)                   name@l
+
+/* offsets for stack frame layout */
+#define LRSAVE  4
+
+#endif
+
+/* various errata or part fixups */
+#ifdef CONFIG_PPC601_SYNC_FIX
+#define SYNC                            \
+BEGIN_FTR_SECTION                       \
+        sync;                           \
+        isync;                          \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#define SYNC_601                        \
+BEGIN_FTR_SECTION                       \
+        sync;                           \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#define ISYNC_601                       \
+BEGIN_FTR_SECTION                       \
+        isync;                          \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#else
+#define SYNC
+#define SYNC_601
+#define ISYNC_601
+#endif
+
+#ifdef CONFIG_PPC_CELL
+#define MFTB(dest)                      \
+90:     mftb  dest;                     \
+BEGIN_FTR_SECTION_NESTED(96);           \
+        cmpwi dest,0;                   \
+        beq-  90b;                      \
+END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
+#else
+#define MFTB(dest)                      mftb dest
+#endif
+
+#ifndef CONFIG_SMP
+#define TLBSYNC
+#else /* CONFIG_SMP */
+/* tlbsync is not implemented on 601 */
+#define TLBSYNC                         \
+BEGIN_FTR_SECTION                       \
+        tlbsync;                        \
+        sync;                           \
+END_FTR_SECTION_IFCLR(CPU_FTR_601)
+#endif
+
+        
+/*
+ * This instruction is not implemented on the PPC 603 or 601; however, on
+ * the 403GCX and 405GP tlbia IS defined and tlbie is not.
+ * All of these instructions exist in the 8xx, they have magical powers,
+ * and they must be used.
+ */
+
+#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
+#define tlbia                                   \
+        li      r4,1024;                        \
+        mtctr   r4;                             \
+        lis     r4,KERNELBASE@h;                \
+0:      tlbie   r4;                             \
+        addi    r4,r4,0x1000;                   \
+        bdnz    0b
+#endif
+
+
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
+
+#if defined(CONFIG_BOOKE)
+#define toreal(rd)
+#define fromreal(rd)
+
+/*
+ * We use addis to ensure compatibility with the "classic" ppc versions of
+ * these macros, which use rs = 0 to get the tophys offset in rd, rather than
+ * converting the address in r0, and so this version has to do that too
+ * (i.e. set register rd to 0 when rs == 0).
+ */
+#define tophys(rd,rs)                           \
+        addis   rd,rs,0
+
+#define tovirt(rd,rs)                           \
+        addis   rd,rs,0
+
+#elif defined(CONFIG_PPC64)
+#define toreal(rd)              /* we can access c000... in real mode */
+#define fromreal(rd)
+
+#define tophys(rd,rs)                           \
+        clrldi  rd,rs,2
+
+#define tovirt(rd,rs)                           \
+        rotldi  rd,rs,16;                       \
+        ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
+        rotldi  rd,rd,48
+#else
+/*
+ * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
+ * physical base address of RAM at compile time.
+ */
+#define toreal(rd)      tophys(rd,rd)
+#define fromreal(rd)    tovirt(rd,rd)
+
+#define tophys(rd,rs)                           \
+0:      addis   rd,rs,-KERNELBASE@h;            \
+        .section ".vtop_fixup","aw";            \
+        .align  1;                              \
+        .long   0b;                             \
+        .previous
+
+#define tovirt(rd,rs)                           \
+0:      addis   rd,rs,KERNELBASE@h;             \
+        .section ".ptov_fixup","aw";            \
+        .align  1;                              \
+        .long   0b;                             \
+        .previous
+#endif
+
+#ifdef CONFIG_PPC64
+#define RFI             rfid
+#define MTMSRD(r)       mtmsrd  r
+
+#else
+#define FIX_SRR1(ra, rb)
+#ifndef CONFIG_40x
+#define RFI             rfi
+#else
+#define RFI             rfi; b .        /* Prevent prefetch past rfi */
+#endif
+#define MTMSRD(r)       mtmsr   r
+#define CLR_TOP32(r)
+#endif
+
+#endif /* __KERNEL__ */
+
+/* The boring bits... */
+
+/* Condition Register Bit Fields */
+
+#define cr0     0
+#define cr1     1
+#define cr2     2
+#define cr3     3
+#define cr4     4
+#define cr5     5
+#define cr6     6
+#define cr7     7
+
+
+/* General Purpose Registers (GPRs) */
+
+#define r0      0
+#define r1      1
+#define r2      2
+#define r3      3
+#define r4      4
+#define r5      5
+#define r6      6
+#define r7      7
+#define r8      8
+#define r9      9
+#define r10     10
+#define r11     11
+#define r12     12
+#define r13     13
+#define r14     14
+#define r15     15
+#define r16     16
+#define r17     17
+#define r18     18
+#define r19     19
+#define r20     20
+#define r21     21
+#define r22     22
+#define r23     23
+#define r24     24
+#define r25     25
+#define r26     26
+#define r27     27
+#define r28     28
+#define r29     29
+#define r30     30
+#define r31     31
+
+
+/* Floating Point Registers (FPRs) */
+
+#define fr0     0
+#define fr1     1
+#define fr2     2
+#define fr3     3
+#define fr4     4
+#define fr5     5
+#define fr6     6
+#define fr7     7
+#define fr8     8
+#define fr9     9
+#define fr10    10
+#define fr11    11
+#define fr12    12
+#define fr13    13
+#define fr14    14
+#define fr15    15
+#define fr16    16
+#define fr17    17
+#define fr18    18
+#define fr19    19
+#define fr20    20
+#define fr21    21
+#define fr22    22
+#define fr23    23
+#define fr24    24
+#define fr25    25
+#define fr26    26
+#define fr27    27
+#define fr28    28
+#define fr29    29
+#define fr30    30
+#define fr31    31
+
+/* AltiVec Registers (VPRs) */
+
+#define vr0     0
+#define vr1     1
+#define vr2     2
+#define vr3     3
+#define vr4     4
+#define vr5     5
+#define vr6     6
+#define vr7     7
+#define vr8     8
+#define vr9     9
+#define vr10    10
+#define vr11    11
+#define vr12    12
+#define vr13    13
+#define vr14    14
+#define vr15    15
+#define vr16    16
+#define vr17    17
+#define vr18    18
+#define vr19    19
+#define vr20    20
+#define vr21    21
+#define vr22    22
+#define vr23    23
+#define vr24    24
+#define vr25    25
+#define vr26    26
+#define vr27    27
+#define vr28    28
+#define vr29    29
+#define vr30    30
+#define vr31    31
+
+/* VSX Registers (VSRs) */
+
+#define vsr0    0
+#define vsr1    1
+#define vsr2    2
+#define vsr3    3
+#define vsr4    4
+#define vsr5    5
+#define vsr6    6
+#define vsr7    7
+#define vsr8    8
+#define vsr9    9
+#define vsr10   10
+#define vsr11   11
+#define vsr12   12
+#define vsr13   13
+#define vsr14   14
+#define vsr15   15
+#define vsr16   16
+#define vsr17   17
+#define vsr18   18
+#define vsr19   19
+#define vsr20   20
+#define vsr21   21
+#define vsr22   22
+#define vsr23   23
+#define vsr24   24
+#define vsr25   25
+#define vsr26   26
+#define vsr27   27
+#define vsr28   28
+#define vsr29   29
+#define vsr30   30
+#define vsr31   31
+#define vsr32   32
+#define vsr33   33
+#define vsr34   34
+#define vsr35   35
+#define vsr36   36
+#define vsr37   37
+#define vsr38   38
+#define vsr39   39
+#define vsr40   40
+#define vsr41   41
+#define vsr42   42
+#define vsr43   43
+#define vsr44   44
+#define vsr45   45
+#define vsr46   46
+#define vsr47   47
+#define vsr48   48
+#define vsr49   49
+#define vsr50   50
+#define vsr51   51
+#define vsr52   52
+#define vsr53   53
+#define vsr54   54
+#define vsr55   55
+#define vsr56   56
+#define vsr57   57
+#define vsr58   58
+#define vsr59   59
+#define vsr60   60
+#define vsr61   61
+#define vsr62   62
+#define vsr63   63
+
+/* SPE Registers (EVPRs) */
+
+#define evr0    0
+#define evr1    1
+#define evr2    2
+#define evr3    3
+#define evr4    4
+#define evr5    5
+#define evr6    6
+#define evr7    7
+#define evr8    8
+#define evr9    9
+#define evr10   10
+#define evr11   11
+#define evr12   12
+#define evr13   13
+#define evr14   14
+#define evr15   15
+#define evr16   16
+#define evr17   17
+#define evr18   18
+#define evr19   19
+#define evr20   20
+#define evr21   21
+#define evr22   22
+#define evr23   23
+#define evr24   24
+#define evr25   25
+#define evr26   26
+#define evr27   27
+#define evr28   28
+#define evr29   29
+#define evr30   30
+#define evr31   31
+
+/* some stab codes */
+#define N_FUN   36
+#define N_RSYM  64
+#define N_SLINE 68
+#define N_SO    100
+
+#endif /*  __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
new file mode 100644
index 000000000000..101ed87f7d84
--- /dev/null
+++ b/arch/powerpc/include/asm/processor.h
@@ -0,0 +1,314 @@
+#ifndef _ASM_POWERPC_PROCESSOR_H
+#define _ASM_POWERPC_PROCESSOR_H
+
+/*
+ * Copyright (C) 2001 PPC 64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/reg.h>
+
+#ifdef CONFIG_VSX
+#define TS_FPRWIDTH 2
+#else
+#define TS_FPRWIDTH 1
+#endif
+
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+/* We do _not_ want to define new machine types at all, those must die
+ * in favor of using the device-tree
+ * -- BenH.
+ */
+
+/* PREP sub-platform types see residual.h for these */
+#define _PREP_Motorola  0x01    /* motorola prep */
+#define _PREP_Firm      0x02    /* firmworks prep */
+#define _PREP_IBM       0x00    /* ibm prep */
+#define _PREP_Bull      0x03    /* bull prep */
+
+/* CHRP sub-platform types. These are arbitrary */
+#define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
+#define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
+#define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
+#define _CHRP_briq      0x07    /* TotalImpact's briQ */
+
+#if defined(__KERNEL__) && defined(CONFIG_PPC32)
+
+extern int _chrp_type;
+
+#ifdef CONFIG_PPC_PREP
+
+/* what kind of prep workstation we are */
+extern int _prep_type;
+
+#endif /* CONFIG_PPC_PREP */
+
+#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+/* Macros for adjusting thread priority (hardware multi-threading) */
+#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
+#define HMT_low()        asm volatile("or 1,1,1      # low priority")
+#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
+#define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
+#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
+#define HMT_high()       asm volatile("or 3,3,3      # high priority")
+
+#ifdef __KERNEL__
+
+extern int have_of;
+
+struct task_struct;
+void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
+void release_thread(struct task_struct *);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+extern void prepare_to_copy(struct task_struct *tsk);
+
+/* Create a new kernel thread. */
+extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/* Lazy FPU handling on uni-processor */
+extern struct task_struct *last_task_used_math;
+extern struct task_struct *last_task_used_altivec;
+extern struct task_struct *last_task_used_vsx;
+extern struct task_struct *last_task_used_spe;
+
+#ifdef CONFIG_PPC32
+
+#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
+#error User TASK_SIZE overlaps with KERNEL_START address
+#endif
+#define TASK_SIZE       (CONFIG_TASK_SIZE)
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
+#endif
+
+#ifdef CONFIG_PPC64
+/* 64-bit user address space is 44-bits (16TB user VM) */
+#define TASK_SIZE_USER64 (0x0000100000000000UL)
+
+/* 
+ * 32-bit user address space is 4GB - 1 page 
+ * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
+ */
+#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
+
+#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
+                TASK_SIZE_USER32 : TASK_SIZE_USER64)
+#define TASK_SIZE         TASK_SIZE_OF(current)
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
+#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
+
+#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \
+                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
+#endif
+
+#ifdef __KERNEL__
+#ifdef __powerpc64__
+
+#define STACK_TOP_USER64 TASK_SIZE_USER64
+#define STACK_TOP_USER32 TASK_SIZE_USER32
+
+#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
+                   STACK_TOP_USER32 : STACK_TOP_USER64)
+
+#define STACK_TOP_MAX STACK_TOP_USER64
+
+#else /* __powerpc64__ */
+
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX   STACK_TOP
+
+#endif /* __powerpc64__ */
+#endif /* __KERNEL__ */
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+#define TS_FPROFFSET 0
+#define TS_VSRLOWOFFSET 1
+#define TS_FPR(i) fpr[i][TS_FPROFFSET]
+
+struct thread_struct {
+        unsigned long   ksp;            /* Kernel stack pointer */
+        unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
+
+#ifdef CONFIG_PPC64
+        unsigned long   ksp_vsid;
+#endif
+        struct pt_regs  *regs;          /* Pointer to saved register state */
+        mm_segment_t    fs;             /* for get_fs() validation */
+#ifdef CONFIG_PPC32
+        void            *pgdir;         /* root of page-table tree */
+#endif
+#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
+        unsigned long   dbcr0;          /* debug control register values */
+        unsigned long   dbcr1;
+#endif
+        /* FP and VSX 0-31 register set */
+        double          fpr[32][TS_FPRWIDTH];
+        struct {
+
+                unsigned int pad;
+                unsigned int val;       /* Floating point status */
+        } fpscr;
+        int             fpexc_mode;     /* floating-point exception mode */
+        unsigned int    align_ctl;      /* alignment handling control */
+#ifdef CONFIG_PPC64
+        unsigned long   start_tb;       /* Start purr when proc switched in */
+        unsigned long   accum_tb;       /* Total accumilated purr for process */
+#endif
+        unsigned long   dabr;           /* Data address breakpoint register */
+#ifdef CONFIG_ALTIVEC
+        /* Complete AltiVec register set */
+        vector128       vr[32] __attribute__((aligned(16)));
+        /* AltiVec status */
+        vector128       vscr __attribute__((aligned(16)));
+        unsigned long   vrsave;
+        int             used_vr;        /* set if process has used altivec */
+#endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_VSX
+        /* VSR status */
+        int             used_vsr;       /* set if process has used altivec */
+#endif /* CONFIG_VSX */
+#ifdef CONFIG_SPE
+        unsigned long   evr[32];        /* upper 32-bits of SPE regs */
+        u64             acc;            /* Accumulator */
+        unsigned long   spefscr;        /* SPE & eFP status */
+        int             used_spe;       /* set if process has used spe */
+#endif /* CONFIG_SPE */
+};
+
+#define ARCH_MIN_TASKALIGN 16
+
+#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
+#define INIT_SP_LIMIT \
+        (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
+
+
+#ifdef CONFIG_PPC32
+#define INIT_THREAD { \
+        .ksp = INIT_SP, \
+        .ksp_limit = INIT_SP_LIMIT, \
+        .fs = KERNEL_DS, \
+        .pgdir = swapper_pg_dir, \
+        .fpexc_mode = MSR_FE0 | MSR_FE1, \
+}
+#else
+#define INIT_THREAD  { \
+        .ksp = INIT_SP, \
+        .ksp_limit = INIT_SP_LIMIT, \
+        .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
+        .fs = KERNEL_DS, \
+        .fpr = {{0}}, \
+        .fpscr = { .val = 0, }, \
+        .fpexc_mode = 0, \
+}
+#endif
+
+/*
+ * Return saved PC of a blocked thread. For now, this is the "user" PC
+ */
+#define thread_saved_pc(tsk)    \
+        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+
+#define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.regs)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
+
+/* Get/set floating-point exception mode */
+#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
+#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
+
+extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
+extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
+
+#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
+#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
+
+extern int get_endian(struct task_struct *tsk, unsigned long adr);
+extern int set_endian(struct task_struct *tsk, unsigned int val);
+
+#define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
+#define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
+
+extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
+extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
+
+static inline unsigned int __unpack_fe01(unsigned long msr_bits)
+{
+        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
+}
+
+static inline unsigned long __pack_fe01(unsigned int fpmode)
+{
+        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
+}
+
+#ifdef CONFIG_PPC64
+#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
+#else
+#define cpu_relax()     barrier()
+#endif
+
+/* Check that a certain kernel stack pointer is valid in task_struct p */
+int validate_sp(unsigned long sp, struct task_struct *p,
+                       unsigned long nbytes);
+
+/*
+ * Prefetch macros.
+ */
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+#define ARCH_HAS_SPINLOCK_PREFETCH
+
+static inline void prefetch(const void *x)
+{
+        if (unlikely(!x))
+                return;
+
+        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
+}
+
+static inline void prefetchw(const void *x)
+{
+        if (unlikely(!x))
+                return;
+
+        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
+}
+
+#define spin_lock_prefetch(x)   prefetchw(x)
+
+#ifdef CONFIG_PPC64
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
new file mode 100644
index 000000000000..eb3bd2e1c7f6
--- /dev/null
+++ b/arch/powerpc/include/asm/prom.h
@@ -0,0 +1,356 @@
+#ifndef _POWERPC_PROM_H
+#define _POWERPC_PROM_H
+#ifdef __KERNEL__
+
+/*
+ * Definitions for talking to the Open Firmware PROM on
+ * Power Macintosh computers.
+ *
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <linux/platform_device.h>
+#include <asm/irq.h>
+#include <asm/atomic.h>
+
+#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1
+#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
+
+#define of_compat_cmp(s1, s2, l)        strcasecmp((s1), (s2))
+#define of_prop_cmp(s1, s2)             strcmp((s1), (s2))
+#define of_node_cmp(s1, s2)             strcasecmp((s1), (s2))
+
+/* Definitions used by the flattened device tree */
+#define OF_DT_HEADER            0xd00dfeed      /* marker */
+#define OF_DT_BEGIN_NODE        0x1             /* Start of node, full name */
+#define OF_DT_END_NODE          0x2             /* End node */
+#define OF_DT_PROP              0x3             /* Property: name off, size,
+                                                 * content */
+#define OF_DT_NOP               0x4             /* nop */
+#define OF_DT_END               0x9
+
+#define OF_DT_VERSION           0x10
+
+/*
+ * This is what gets passed to the kernel by prom_init or kexec
+ *
+ * The dt struct contains the device tree structure, full pathes and
+ * property contents. The dt strings contain a separate block with just
+ * the strings for the property names, and is fully page aligned and
+ * self contained in a page, so that it can be kept around by the kernel,
+ * each property name appears only once in this page (cheap compression)
+ *
+ * the mem_rsvmap contains a map of reserved ranges of physical memory,
+ * passing it here instead of in the device-tree itself greatly simplifies
+ * the job of everybody. It's just a list of u64 pairs (base/size) that
+ * ends when size is 0
+ */
+struct boot_param_header
+{
+        u32     magic;                  /* magic word OF_DT_HEADER */
+        u32     totalsize;              /* total size of DT block */
+        u32     off_dt_struct;          /* offset to structure */
+        u32     off_dt_strings;         /* offset to strings */
+        u32     off_mem_rsvmap;         /* offset to memory reserve map */
+        u32     version;                /* format version */
+        u32     last_comp_version;      /* last compatible version */
+        /* version 2 fields below */
+        u32     boot_cpuid_phys;        /* Physical CPU id we're booting on */
+        /* version 3 fields below */
+        u32     dt_strings_size;        /* size of the DT strings block */
+        /* version 17 fields below */
+        u32     dt_struct_size;         /* size of the DT structure block */
+};
+
+
+
+typedef u32 phandle;
+typedef u32 ihandle;
+
+struct property {
+        char    *name;
+        int     length;
+        void    *value;
+        struct property *next;
+};
+
+struct device_node {
+        const char *name;
+        const char *type;
+        phandle node;
+        phandle linux_phandle;
+        char    *full_name;
+
+        struct  property *properties;
+        struct  property *deadprops; /* removed properties */
+        struct  device_node *parent;
+        struct  device_node *child;
+        struct  device_node *sibling;
+        struct  device_node *next;      /* next device of same type */
+        struct  device_node *allnext;   /* next in list of all nodes */
+        struct  proc_dir_entry *pde;    /* this node's proc directory */
+        struct  kref kref;
+        unsigned long _flags;
+        void    *data;
+};
+
+extern struct device_node *of_chosen;
+
+static inline int of_node_check_flag(struct device_node *n, unsigned long flag)
+{
+        return test_bit(flag, &n->_flags);
+}
+
+static inline void of_node_set_flag(struct device_node *n, unsigned long flag)
+{
+        set_bit(flag, &n->_flags);
+}
+
+
+#define HAVE_ARCH_DEVTREE_FIXUPS
+
+static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de)
+{
+        dn->pde = de;
+}
+
+
+extern struct device_node *of_find_all_nodes(struct device_node *prev);
+extern struct device_node *of_node_get(struct device_node *node);
+extern void of_node_put(struct device_node *node);
+
+/* For scanning the flat device-tree at boot time */
+extern int __init of_scan_flat_dt(int (*it)(unsigned long node,
+                                            const char *uname, int depth,
+                                            void *data),
+                                  void *data);
+extern void* __init of_get_flat_dt_prop(unsigned long node, const char *name,
+                                        unsigned long *size);
+extern int __init of_flat_dt_is_compatible(unsigned long node, const char *name);
+extern unsigned long __init of_get_flat_dt_root(void);
+
+/* For updating the device tree at runtime */
+extern void of_attach_node(struct device_node *);
+extern void of_detach_node(struct device_node *);
+
+/* Other Prototypes */
+extern void finish_device_tree(void);
+extern void unflatten_device_tree(void);
+extern void early_init_devtree(void *);
+extern int machine_is_compatible(const char *compat);
+extern void print_properties(struct device_node *node);
+extern int prom_n_intr_cells(struct device_node* np);
+extern void prom_get_irq_senses(unsigned char *senses, int off, int max);
+extern int prom_add_property(struct device_node* np, struct property* prop);
+extern int prom_remove_property(struct device_node *np, struct property *prop);
+extern int prom_update_property(struct device_node *np,
+                                struct property *newprop,
+                                struct property *oldprop);
+
+#ifdef CONFIG_PPC32
+/*
+ * PCI <-> OF matching functions
+ * (XXX should these be here?)
+ */
+struct pci_bus;
+struct pci_dev;
+extern int pci_device_from_OF_node(struct device_node *node,
+                                   u8* bus, u8* devfn);
+extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
+extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
+extern void pci_create_OF_bus_map(void);
+#endif
+
+extern struct resource *request_OF_resource(struct device_node* node,
+                                int index, const char* name_postfix);
+extern int release_OF_resource(struct device_node* node, int index);
+
+
+/*
+ * OF address retreival & translation
+ */
+
+
+/* Helper to read a big number; size is in cells (not bytes) */
+static inline u64 of_read_number(const u32 *cell, int size)
+{
+        u64 r = 0;
+        while (size--)
+                r = (r << 32) | *(cell++);
+        return r;
+}
+
+/* Like of_read_number, but we want an unsigned long result */
+#ifdef CONFIG_PPC32
+static inline unsigned long of_read_ulong(const u32 *cell, int size)
+{
+        return cell[size-1];
+}
+#else
+#define of_read_ulong(cell, size)       of_read_number(cell, size)
+#endif
+
+/* Translate an OF address block into a CPU physical address
+ */
+extern u64 of_translate_address(struct device_node *np, const u32 *addr);
+
+/* Translate a DMA address from device space to CPU space */
+extern u64 of_translate_dma_address(struct device_node *dev,
+                                    const u32 *in_addr);
+
+/* Extract an address from a device, returns the region size and
+ * the address space flags too. The PCI version uses a BAR number
+ * instead of an absolute index
+ */
+extern const u32 *of_get_address(struct device_node *dev, int index,
+                           u64 *size, unsigned int *flags);
+#ifdef CONFIG_PCI
+extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no,
+                               u64 *size, unsigned int *flags);
+#else
+static inline const u32 *of_get_pci_address(struct device_node *dev,
+                int bar_no, u64 *size, unsigned int *flags)
+{
+        return NULL;
+}
+#endif /* CONFIG_PCI */
+
+/* Get an address as a resource. Note that if your address is
+ * a PIO address, the conversion will fail if the physical address
+ * can't be internally converted to an IO token with
+ * pci_address_to_pio(), that is because it's either called to early
+ * or it can't be matched to any host bridge IO space
+ */
+extern int of_address_to_resource(struct device_node *dev, int index,
+                                  struct resource *r);
+#ifdef CONFIG_PCI
+extern int of_pci_address_to_resource(struct device_node *dev, int bar,
+                                      struct resource *r);
+#else
+static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
+                struct resource *r)
+{
+        return -ENOSYS;
+}
+#endif /* CONFIG_PCI */
+
+/* Parse the ibm,dma-window property of an OF node into the busno, phys and
+ * size parameters.
+ */
+void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
+                unsigned long *busno, unsigned long *phys, unsigned long *size);
+
+extern void kdump_move_device_tree(void);
+
+/* CPU OF node matching */
+struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
+
+/* Get the MAC address */
+extern const void *of_get_mac_address(struct device_node *np);
+
+/*
+ * OF interrupt mapping
+ */
+
+/* This structure is returned when an interrupt is mapped. The controller
+ * field needs to be put() after use
+ */
+
+#define OF_MAX_IRQ_SPEC          4 /* We handle specifiers of at most 4 cells */
+
+struct of_irq {
+        struct device_node *controller; /* Interrupt controller node */
+        u32 size;                       /* Specifier size */
+        u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
+};
+
+/**
+ * of_irq_map_init - Initialize the irq remapper
+ * @flags:      flags defining workarounds to enable
+ *
+ * Some machines have bugs in the device-tree which require certain workarounds
+ * to be applied. Call this before any interrupt mapping attempts to enable
+ * those workarounds.
+ */
+#define OF_IMAP_OLDWORLD_MAC    0x00000001
+#define OF_IMAP_NO_PHANDLE      0x00000002
+
+extern void of_irq_map_init(unsigned int flags);
+
+/**
+ * of_irq_map_raw - Low level interrupt tree parsing
+ * @parent:     the device interrupt parent
+ * @intspec:    interrupt specifier ("interrupts" property of the device)
+ * @ointsize:   size of the passed in interrupt specifier
+ * @addr:       address specifier (start of "reg" property of the device)
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * Returns 0 on success and a negative number on error
+ *
+ * This function is a low-level interrupt tree walking function. It
+ * can be used to do a partial walk with synthetized reg and interrupts
+ * properties, for example when resolving PCI interrupts when no device
+ * node exist for the parent.
+ *
+ */
+
+extern int of_irq_map_raw(struct device_node *parent, const u32 *intspec,
+                          u32 ointsize, const u32 *addr,
+                          struct of_irq *out_irq);
+
+
+/**
+ * of_irq_map_one - Resolve an interrupt for a device
+ * @device:     the device whose interrupt is to be resolved
+ * @index:      index of the interrupt to resolve
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * This function resolves an interrupt, walking the tree, for a given
+ * device-tree node. It's the high level pendant to of_irq_map_raw().
+ * It also implements the workarounds for OldWolrd Macs.
+ */
+extern int of_irq_map_one(struct device_node *device, int index,
+                          struct of_irq *out_irq);
+
+/**
+ * of_irq_map_pci - Resolve the interrupt for a PCI device
+ * @pdev:       the device whose interrupt is to be resolved
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * This function resolves the PCI interrupt for a given PCI device. If a
+ * device-node exists for a given pci_dev, it will use normal OF tree
+ * walking. If not, it will implement standard swizzling and walk up the
+ * PCI tree until an device-node is found, at which point it will finish
+ * resolving using the OF tree walking.
+ */
+struct pci_dev;
+extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
+
+extern int of_irq_to_resource(struct device_node *dev, int index,
+                        struct resource *r);
+
+/**
+ * of_iomap - Maps the memory mapped IO for a given device_node
+ * @device:     the device whose io range will be mapped
+ * @index:      index of the io range
+ *
+ * Returns a pointer to the mapped memory
+ */
+extern void __iomem *of_iomap(struct device_node *device, int index);
+
+/*
+ * NB:  This is here while we transition from using asm/prom.h
+ * to linux/of.h
+ */
+#include <linux/of.h>
+
+#endif /* __KERNEL__ */
+#endif /* _POWERPC_PROM_H */
diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h
new file mode 100644
index 000000000000..f9e34c493cbb
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3.h
@@ -0,0 +1,519 @@
+/*
+ *  PS3 platform declarations.
+ *
+ *  Copyright (C) 2006 Sony Computer Entertainment Inc.
+ *  Copyright 2006 Sony Corp.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#if !defined(_ASM_POWERPC_PS3_H)
+#define _ASM_POWERPC_PS3_H
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/device.h>
+#include "cell-pmu.h"
+
+union ps3_firmware_version {
+        u64 raw;
+        struct {
+                u16 pad;
+                u16 major;
+                u16 minor;
+                u16 rev;
+        };
+};
+
+void ps3_get_firmware_version(union ps3_firmware_version *v);
+int ps3_compare_firmware_version(u16 major, u16 minor, u16 rev);
+
+/* 'Other OS' area */
+
+enum ps3_param_av_multi_out {
+        PS3_PARAM_AV_MULTI_OUT_NTSC = 0,
+        PS3_PARAM_AV_MULTI_OUT_PAL_RGB = 1,
+        PS3_PARAM_AV_MULTI_OUT_PAL_YCBCR = 2,
+        PS3_PARAM_AV_MULTI_OUT_SECAM = 3,
+};
+
+enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void);
+
+/* dma routines */
+
+enum ps3_dma_page_size {
+        PS3_DMA_4K = 12U,
+        PS3_DMA_64K = 16U,
+        PS3_DMA_1M = 20U,
+        PS3_DMA_16M = 24U,
+};
+
+enum ps3_dma_region_type {
+        PS3_DMA_OTHER = 0,
+        PS3_DMA_INTERNAL = 2,
+};
+
+struct ps3_dma_region_ops;
+
+/**
+ * struct ps3_dma_region - A per device dma state variables structure
+ * @did: The HV device id.
+ * @page_size: The ioc pagesize.
+ * @region_type: The HV region type.
+ * @bus_addr: The 'translated' bus address of the region.
+ * @len: The length in bytes of the region.
+ * @offset: The offset from the start of memory of the region.
+ * @ioid: The IOID of the device who owns this region
+ * @chunk_list: Opaque variable used by the ioc page manager.
+ * @region_ops: struct ps3_dma_region_ops - dma region operations
+ */
+
+struct ps3_dma_region {
+        struct ps3_system_bus_device *dev;
+        /* device variables */
+        const struct ps3_dma_region_ops *region_ops;
+        unsigned char ioid;
+        enum ps3_dma_page_size page_size;
+        enum ps3_dma_region_type region_type;
+        unsigned long len;
+        unsigned long offset;
+
+        /* driver variables  (set by ps3_dma_region_create) */
+        unsigned long bus_addr;
+        struct {
+                spinlock_t lock;
+                struct list_head head;
+        } chunk_list;
+};
+
+struct ps3_dma_region_ops {
+        int (*create)(struct ps3_dma_region *);
+        int (*free)(struct ps3_dma_region *);
+        int (*map)(struct ps3_dma_region *,
+                   unsigned long virt_addr,
+                   unsigned long len,
+                   unsigned long *bus_addr,
+                   u64 iopte_pp);
+        int (*unmap)(struct ps3_dma_region *,
+                     unsigned long bus_addr,
+                     unsigned long len);
+};
+/**
+ * struct ps3_dma_region_init - Helper to initialize structure variables
+ *
+ * Helper to properly initialize variables prior to calling
+ * ps3_system_bus_device_register.
+ */
+
+struct ps3_system_bus_device;
+
+int ps3_dma_region_init(struct ps3_system_bus_device *dev,
+        struct ps3_dma_region *r, enum ps3_dma_page_size page_size,
+        enum ps3_dma_region_type region_type, void *addr, unsigned long len);
+int ps3_dma_region_create(struct ps3_dma_region *r);
+int ps3_dma_region_free(struct ps3_dma_region *r);
+int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr,
+        unsigned long len, unsigned long *bus_addr,
+        u64 iopte_pp);
+int ps3_dma_unmap(struct ps3_dma_region *r, unsigned long bus_addr,
+        unsigned long len);
+
+/* mmio routines */
+
+enum ps3_mmio_page_size {
+        PS3_MMIO_4K = 12U,
+        PS3_MMIO_64K = 16U
+};
+
+struct ps3_mmio_region_ops;
+/**
+ * struct ps3_mmio_region - a per device mmio state variables structure
+ *
+ * Current systems can be supported with a single region per device.
+ */
+
+struct ps3_mmio_region {
+        struct ps3_system_bus_device *dev;
+        const struct ps3_mmio_region_ops *mmio_ops;
+        unsigned long bus_addr;
+        unsigned long len;
+        enum ps3_mmio_page_size page_size;
+        unsigned long lpar_addr;
+};
+
+struct ps3_mmio_region_ops {
+        int (*create)(struct ps3_mmio_region *);
+        int (*free)(struct ps3_mmio_region *);
+};
+/**
+ * struct ps3_mmio_region_init - Helper to initialize structure variables
+ *
+ * Helper to properly initialize variables prior to calling
+ * ps3_system_bus_device_register.
+ */
+
+int ps3_mmio_region_init(struct ps3_system_bus_device *dev,
+        struct ps3_mmio_region *r, unsigned long bus_addr, unsigned long len,
+        enum ps3_mmio_page_size page_size);
+int ps3_mmio_region_create(struct ps3_mmio_region *r);
+int ps3_free_mmio_region(struct ps3_mmio_region *r);
+unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr);
+
+/* inrerrupt routines */
+
+enum ps3_cpu_binding {
+        PS3_BINDING_CPU_ANY = -1,
+        PS3_BINDING_CPU_0 = 0,
+        PS3_BINDING_CPU_1 = 1,
+};
+
+int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
+        unsigned int *virq);
+int ps3_irq_plug_destroy(unsigned int virq);
+int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq);
+int ps3_event_receive_port_destroy(unsigned int virq);
+int ps3_send_event_locally(unsigned int virq);
+
+int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
+        unsigned int *virq);
+int ps3_io_irq_destroy(unsigned int virq);
+int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
+        unsigned int *virq);
+int ps3_vuart_irq_destroy(unsigned int virq);
+int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
+        unsigned int class, unsigned int *virq);
+int ps3_spe_irq_destroy(unsigned int virq);
+
+int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
+        enum ps3_cpu_binding cpu, unsigned int *virq);
+int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
+        unsigned int virq);
+
+/* lv1 result codes */
+
+enum lv1_result {
+        LV1_SUCCESS                     = 0,
+        /* not used                       -1 */
+        LV1_RESOURCE_SHORTAGE           = -2,
+        LV1_NO_PRIVILEGE                = -3,
+        LV1_DENIED_BY_POLICY            = -4,
+        LV1_ACCESS_VIOLATION            = -5,
+        LV1_NO_ENTRY                    = -6,
+        LV1_DUPLICATE_ENTRY             = -7,
+        LV1_TYPE_MISMATCH               = -8,
+        LV1_BUSY                        = -9,
+        LV1_EMPTY                       = -10,
+        LV1_WRONG_STATE                 = -11,
+        /* not used                       -12 */
+        LV1_NO_MATCH                    = -13,
+        LV1_ALREADY_CONNECTED           = -14,
+        LV1_UNSUPPORTED_PARAMETER_VALUE = -15,
+        LV1_CONDITION_NOT_SATISFIED     = -16,
+        LV1_ILLEGAL_PARAMETER_VALUE     = -17,
+        LV1_BAD_OPTION                  = -18,
+        LV1_IMPLEMENTATION_LIMITATION   = -19,
+        LV1_NOT_IMPLEMENTED             = -20,
+        LV1_INVALID_CLASS_ID            = -21,
+        LV1_CONSTRAINT_NOT_SATISFIED    = -22,
+        LV1_ALIGNMENT_ERROR             = -23,
+        LV1_HARDWARE_ERROR              = -24,
+        LV1_INVALID_DATA_FORMAT         = -25,
+        LV1_INVALID_OPERATION           = -26,
+        LV1_INTERNAL_ERROR              = -32768,
+};
+
+static inline const char* ps3_result(int result)
+{
+#if defined(DEBUG)
+        switch (result) {
+        case LV1_SUCCESS:
+                return "LV1_SUCCESS (0)";
+        case -1:
+                return "** unknown result ** (-1)";
+        case LV1_RESOURCE_SHORTAGE:
+                return "LV1_RESOURCE_SHORTAGE (-2)";
+        case LV1_NO_PRIVILEGE:
+                return "LV1_NO_PRIVILEGE (-3)";
+        case LV1_DENIED_BY_POLICY:
+                return "LV1_DENIED_BY_POLICY (-4)";
+        case LV1_ACCESS_VIOLATION:
+                return "LV1_ACCESS_VIOLATION (-5)";
+        case LV1_NO_ENTRY:
+                return "LV1_NO_ENTRY (-6)";
+        case LV1_DUPLICATE_ENTRY:
+                return "LV1_DUPLICATE_ENTRY (-7)";
+        case LV1_TYPE_MISMATCH:
+                return "LV1_TYPE_MISMATCH (-8)";
+        case LV1_BUSY:
+                return "LV1_BUSY (-9)";
+        case LV1_EMPTY:
+                return "LV1_EMPTY (-10)";
+        case LV1_WRONG_STATE:
+                return "LV1_WRONG_STATE (-11)";
+        case -12:
+                return "** unknown result ** (-12)";
+        case LV1_NO_MATCH:
+                return "LV1_NO_MATCH (-13)";
+        case LV1_ALREADY_CONNECTED:
+                return "LV1_ALREADY_CONNECTED (-14)";
+        case LV1_UNSUPPORTED_PARAMETER_VALUE:
+                return "LV1_UNSUPPORTED_PARAMETER_VALUE (-15)";
+        case LV1_CONDITION_NOT_SATISFIED:
+                return "LV1_CONDITION_NOT_SATISFIED (-16)";
+        case LV1_ILLEGAL_PARAMETER_VALUE:
+                return "LV1_ILLEGAL_PARAMETER_VALUE (-17)";
+        case LV1_BAD_OPTION:
+                return "LV1_BAD_OPTION (-18)";
+        case LV1_IMPLEMENTATION_LIMITATION:
+                return "LV1_IMPLEMENTATION_LIMITATION (-19)";
+        case LV1_NOT_IMPLEMENTED:
+                return "LV1_NOT_IMPLEMENTED (-20)";
+        case LV1_INVALID_CLASS_ID:
+                return "LV1_INVALID_CLASS_ID (-21)";
+        case LV1_CONSTRAINT_NOT_SATISFIED:
+                return "LV1_CONSTRAINT_NOT_SATISFIED (-22)";
+        case LV1_ALIGNMENT_ERROR:
+                return "LV1_ALIGNMENT_ERROR (-23)";
+        case LV1_HARDWARE_ERROR:
+                return "LV1_HARDWARE_ERROR (-24)";
+        case LV1_INVALID_DATA_FORMAT:
+                return "LV1_INVALID_DATA_FORMAT (-25)";
+        case LV1_INVALID_OPERATION:
+                return "LV1_INVALID_OPERATION (-26)";
+        case LV1_INTERNAL_ERROR:
+                return "LV1_INTERNAL_ERROR (-32768)";
+        default:
+                BUG();
+                return "** unknown result **";
+        };
+#else
+        return "";
+#endif
+}
+
+/* system bus routines */
+
+enum ps3_match_id {
+        PS3_MATCH_ID_EHCI           = 1,
+        PS3_MATCH_ID_OHCI           = 2,
+        PS3_MATCH_ID_GELIC          = 3,
+        PS3_MATCH_ID_AV_SETTINGS    = 4,
+        PS3_MATCH_ID_SYSTEM_MANAGER = 5,
+        PS3_MATCH_ID_STOR_DISK      = 6,
+        PS3_MATCH_ID_STOR_ROM       = 7,
+        PS3_MATCH_ID_STOR_FLASH     = 8,
+        PS3_MATCH_ID_SOUND          = 9,
+        PS3_MATCH_ID_GRAPHICS       = 10,
+        PS3_MATCH_ID_LPM            = 11,
+};
+
+#define PS3_MODULE_ALIAS_EHCI           "ps3:1"
+#define PS3_MODULE_ALIAS_OHCI           "ps3:2"
+#define PS3_MODULE_ALIAS_GELIC          "ps3:3"
+#define PS3_MODULE_ALIAS_AV_SETTINGS    "ps3:4"
+#define PS3_MODULE_ALIAS_SYSTEM_MANAGER "ps3:5"
+#define PS3_MODULE_ALIAS_STOR_DISK      "ps3:6"
+#define PS3_MODULE_ALIAS_STOR_ROM       "ps3:7"
+#define PS3_MODULE_ALIAS_STOR_FLASH     "ps3:8"
+#define PS3_MODULE_ALIAS_SOUND          "ps3:9"
+#define PS3_MODULE_ALIAS_GRAPHICS       "ps3:10"
+#define PS3_MODULE_ALIAS_LPM            "ps3:11"
+
+enum ps3_system_bus_device_type {
+        PS3_DEVICE_TYPE_IOC0 = 1,
+        PS3_DEVICE_TYPE_SB,
+        PS3_DEVICE_TYPE_VUART,
+        PS3_DEVICE_TYPE_LPM,
+};
+
+enum ps3_match_sub_id {
+        /* for PS3_MATCH_ID_GRAPHICS */
+        PS3_MATCH_SUB_ID_FB             = 1,
+};
+
+/**
+ * struct ps3_system_bus_device - a device on the system bus
+ */
+
+struct ps3_system_bus_device {
+        enum ps3_match_id match_id;
+        enum ps3_match_sub_id match_sub_id;
+        enum ps3_system_bus_device_type dev_type;
+
+        u64 bus_id;                       /* SB */
+        u64 dev_id;                       /* SB */
+        unsigned int interrupt_id;        /* SB */
+        struct ps3_dma_region *d_region;  /* SB, IOC0 */
+        struct ps3_mmio_region *m_region; /* SB, IOC0*/
+        unsigned int port_number;         /* VUART */
+        struct {                          /* LPM */
+                u64 node_id;
+                u64 pu_id;
+                u64 rights;
+        } lpm;
+
+/*      struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
+        struct device core;
+        void *driver_priv; /* private driver variables */
+};
+
+int ps3_open_hv_device(struct ps3_system_bus_device *dev);
+int ps3_close_hv_device(struct ps3_system_bus_device *dev);
+
+/**
+ * struct ps3_system_bus_driver - a driver for a device on the system bus
+ */
+
+struct ps3_system_bus_driver {
+        enum ps3_match_id match_id;
+        enum ps3_match_sub_id match_sub_id;
+        struct device_driver core;
+        int (*probe)(struct ps3_system_bus_device *);
+        int (*remove)(struct ps3_system_bus_device *);
+        int (*shutdown)(struct ps3_system_bus_device *);
+/*      int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */
+/*      int (*resume)(struct ps3_system_bus_device *); */
+};
+
+int ps3_system_bus_device_register(struct ps3_system_bus_device *dev);
+int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv);
+void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv);
+
+static inline struct ps3_system_bus_driver *ps3_drv_to_system_bus_drv(
+        struct device_driver *_drv)
+{
+        return container_of(_drv, struct ps3_system_bus_driver, core);
+}
+static inline struct ps3_system_bus_device *ps3_dev_to_system_bus_dev(
+        struct device *_dev)
+{
+        return container_of(_dev, struct ps3_system_bus_device, core);
+}
+static inline struct ps3_system_bus_driver *
+        ps3_system_bus_dev_to_system_bus_drv(struct ps3_system_bus_device *_dev)
+{
+        BUG_ON(!_dev);
+        BUG_ON(!_dev->core.driver);
+        return ps3_drv_to_system_bus_drv(_dev->core.driver);
+}
+
+/**
+ * ps3_system_bus_set_drvdata -
+ * @dev: device structure
+ * @data: Data to set
+ */
+
+static inline void ps3_system_bus_set_driver_data(
+        struct ps3_system_bus_device *dev, void *data)
+{
+        dev->core.driver_data = data;
+}
+static inline void *ps3_system_bus_get_driver_data(
+        struct ps3_system_bus_device *dev)
+{
+        return dev->core.driver_data;
+}
+
+/* These two need global scope for get_dma_ops(). */
+
+extern struct bus_type ps3_system_bus_type;
+
+/* system manager */
+
+struct ps3_sys_manager_ops {
+        struct ps3_system_bus_device *dev;
+        void (*power_off)(struct ps3_system_bus_device *dev);
+        void (*restart)(struct ps3_system_bus_device *dev);
+};
+
+void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
+void __noreturn ps3_sys_manager_power_off(void);
+void __noreturn ps3_sys_manager_restart(void);
+void __noreturn ps3_sys_manager_halt(void);
+int ps3_sys_manager_get_wol(void);
+void ps3_sys_manager_set_wol(int state);
+
+struct ps3_prealloc {
+    const char *name;
+    void *address;
+    unsigned long size;
+    unsigned long align;
+};
+
+extern struct ps3_prealloc ps3fb_videomemory;
+extern struct ps3_prealloc ps3flash_bounce_buffer;
+
+/* logical performance monitor */
+
+/**
+ * enum ps3_lpm_rights - Rigths granted by the system policy module.
+ *
+ * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm.
+ * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer.
+ */
+
+enum ps3_lpm_rights {
+        PS3_LPM_RIGHTS_USE_LPM = 0x001,
+        PS3_LPM_RIGHTS_USE_TB = 0x100,
+};
+
+/**
+ * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use.
+ *
+ * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer.
+ * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer.  Must have
+ *  rights @PS3_LPM_RIGHTS_USE_TB.
+ */
+
+enum ps3_lpm_tb_type {
+        PS3_LPM_TB_TYPE_NONE = 0,
+        PS3_LPM_TB_TYPE_INTERNAL = 1,
+};
+
+int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
+        u64 tb_cache_size);
+int ps3_lpm_close(void);
+int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
+        unsigned long *bytes_copied);
+int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
+        unsigned long count, unsigned long *bytes_copied);
+void ps3_set_bookmark(u64 bookmark);
+void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
+int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit,
+        u8 bus_word);
+
+u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
+void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
+u32 ps3_read_ctr(u32 cpu, u32 ctr);
+void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
+
+u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
+void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
+u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
+void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
+
+u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
+void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
+
+void ps3_enable_pm(u32 cpu);
+void ps3_disable_pm(u32 cpu);
+void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
+void ps3_disable_pm_interrupts(u32 cpu);
+
+u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
+void ps3_sync_irq(int node);
+u32 ps3_get_hw_thread_id(int cpu);
+u64 ps3_get_spe_id(void *arg);
+
+#endif
diff --git a/arch/powerpc/include/asm/ps3av.h b/arch/powerpc/include/asm/ps3av.h
new file mode 100644
index 000000000000..fda98715cd35
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3av.h
@@ -0,0 +1,744 @@
+/*
+ *  PS3 AV backend support.
+ *
+ *  Copyright (C) 2007 Sony Computer Entertainment Inc.
+ *  Copyright 2007 Sony Corp.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _ASM_POWERPC_PS3AV_H_
+#define _ASM_POWERPC_PS3AV_H_
+
+/** command for ioctl() **/
+#define PS3AV_VERSION 0x205     /* version of ps3av command */
+
+#define PS3AV_CID_AV_INIT              0x00000001
+#define PS3AV_CID_AV_FIN               0x00000002
+#define PS3AV_CID_AV_GET_HW_CONF       0x00000003
+#define PS3AV_CID_AV_GET_MONITOR_INFO  0x00000004
+#define PS3AV_CID_AV_ENABLE_EVENT      0x00000006
+#define PS3AV_CID_AV_DISABLE_EVENT     0x00000007
+#define PS3AV_CID_AV_TV_MUTE           0x0000000a
+
+#define PS3AV_CID_AV_VIDEO_CS          0x00010001
+#define PS3AV_CID_AV_VIDEO_MUTE        0x00010002
+#define PS3AV_CID_AV_VIDEO_DISABLE_SIG 0x00010003
+#define PS3AV_CID_AV_AUDIO_PARAM       0x00020001
+#define PS3AV_CID_AV_AUDIO_MUTE        0x00020002
+#define PS3AV_CID_AV_HDMI_MODE         0x00040001
+
+#define PS3AV_CID_VIDEO_INIT           0x01000001
+#define PS3AV_CID_VIDEO_MODE           0x01000002
+#define PS3AV_CID_VIDEO_FORMAT         0x01000004
+#define PS3AV_CID_VIDEO_PITCH          0x01000005
+
+#define PS3AV_CID_AUDIO_INIT           0x02000001
+#define PS3AV_CID_AUDIO_MODE           0x02000002
+#define PS3AV_CID_AUDIO_MUTE           0x02000003
+#define PS3AV_CID_AUDIO_ACTIVE         0x02000004
+#define PS3AV_CID_AUDIO_INACTIVE       0x02000005
+#define PS3AV_CID_AUDIO_SPDIF_BIT      0x02000006
+#define PS3AV_CID_AUDIO_CTRL           0x02000007
+
+#define PS3AV_CID_EVENT_UNPLUGGED      0x10000001
+#define PS3AV_CID_EVENT_PLUGGED        0x10000002
+#define PS3AV_CID_EVENT_HDCP_DONE      0x10000003
+#define PS3AV_CID_EVENT_HDCP_FAIL      0x10000004
+#define PS3AV_CID_EVENT_HDCP_AUTH      0x10000005
+#define PS3AV_CID_EVENT_HDCP_ERROR     0x10000006
+
+#define PS3AV_CID_AVB_PARAM            0x04000001
+
+/* max backend ports */
+#define PS3AV_HDMI_MAX                 2        /* HDMI_0 HDMI_1 */
+#define PS3AV_AVMULTI_MAX              1        /* AVMULTI_0 */
+#define PS3AV_AV_PORT_MAX              (PS3AV_HDMI_MAX + PS3AV_AVMULTI_MAX)
+#define PS3AV_OPT_PORT_MAX             1        /* SPDIF0 */
+#define PS3AV_HEAD_MAX                 2        /* HEAD_A HEAD_B */
+
+/* num of pkt for PS3AV_CID_AVB_PARAM */
+#define PS3AV_AVB_NUM_VIDEO            PS3AV_HEAD_MAX
+#define PS3AV_AVB_NUM_AUDIO            0        /* not supported */
+#define PS3AV_AVB_NUM_AV_VIDEO         PS3AV_AV_PORT_MAX
+#define PS3AV_AVB_NUM_AV_AUDIO         PS3AV_HDMI_MAX
+
+#define PS3AV_MUTE_PORT_MAX            1        /* num of ports in mute pkt */
+
+/* event_bit */
+#define PS3AV_CMD_EVENT_BIT_UNPLUGGED                   (1 << 0)
+#define PS3AV_CMD_EVENT_BIT_PLUGGED                     (1 << 1)
+#define PS3AV_CMD_EVENT_BIT_HDCP_DONE                   (1 << 2)
+#define PS3AV_CMD_EVENT_BIT_HDCP_FAIL                   (1 << 3)
+#define PS3AV_CMD_EVENT_BIT_HDCP_REAUTH                 (1 << 4)
+#define PS3AV_CMD_EVENT_BIT_HDCP_TOPOLOGY               (1 << 5)
+
+/* common params */
+/* mute */
+#define PS3AV_CMD_MUTE_OFF                              0x0000
+#define PS3AV_CMD_MUTE_ON                               0x0001
+/* avport */
+#define PS3AV_CMD_AVPORT_HDMI_0                         0x0000
+#define PS3AV_CMD_AVPORT_HDMI_1                         0x0001
+#define PS3AV_CMD_AVPORT_AVMULTI_0                      0x0010
+#define PS3AV_CMD_AVPORT_SPDIF_0                        0x0020
+#define PS3AV_CMD_AVPORT_SPDIF_1                        0x0021
+
+/* for av backend */
+/* av_mclk */
+#define PS3AV_CMD_AV_MCLK_128                           0x0000
+#define PS3AV_CMD_AV_MCLK_256                           0x0001
+#define PS3AV_CMD_AV_MCLK_512                           0x0003
+/* av_inputlen */
+#define PS3AV_CMD_AV_INPUTLEN_16                        0x02
+#define PS3AV_CMD_AV_INPUTLEN_20                        0x0a
+#define PS3AV_CMD_AV_INPUTLEN_24                        0x0b
+/* alayout */
+#define PS3AV_CMD_AV_LAYOUT_32                          (1 << 0)
+#define PS3AV_CMD_AV_LAYOUT_44                          (1 << 1)
+#define PS3AV_CMD_AV_LAYOUT_48                          (1 << 2)
+#define PS3AV_CMD_AV_LAYOUT_88                          (1 << 3)
+#define PS3AV_CMD_AV_LAYOUT_96                          (1 << 4)
+#define PS3AV_CMD_AV_LAYOUT_176                         (1 << 5)
+#define PS3AV_CMD_AV_LAYOUT_192                         (1 << 6)
+/* hdmi_mode */
+#define PS3AV_CMD_AV_HDMI_MODE_NORMAL                   0xff
+#define PS3AV_CMD_AV_HDMI_HDCP_OFF                      0x01
+#define PS3AV_CMD_AV_HDMI_EDID_PASS                     0x80
+#define PS3AV_CMD_AV_HDMI_DVI                           0x40
+
+/* for video module */
+/* video_head */
+#define PS3AV_CMD_VIDEO_HEAD_A                          0x0000
+#define PS3AV_CMD_VIDEO_HEAD_B                          0x0001
+/* video_cs_out video_cs_in */
+#define PS3AV_CMD_VIDEO_CS_NONE                         0x0000
+#define PS3AV_CMD_VIDEO_CS_RGB_8                        0x0001
+#define PS3AV_CMD_VIDEO_CS_YUV444_8                     0x0002
+#define PS3AV_CMD_VIDEO_CS_YUV422_8                     0x0003
+#define PS3AV_CMD_VIDEO_CS_XVYCC_8                      0x0004
+#define PS3AV_CMD_VIDEO_CS_RGB_10                       0x0005
+#define PS3AV_CMD_VIDEO_CS_YUV444_10                    0x0006
+#define PS3AV_CMD_VIDEO_CS_YUV422_10                    0x0007
+#define PS3AV_CMD_VIDEO_CS_XVYCC_10                     0x0008
+#define PS3AV_CMD_VIDEO_CS_RGB_12                       0x0009
+#define PS3AV_CMD_VIDEO_CS_YUV444_12                    0x000a
+#define PS3AV_CMD_VIDEO_CS_YUV422_12                    0x000b
+#define PS3AV_CMD_VIDEO_CS_XVYCC_12                     0x000c
+/* video_vid */
+#define PS3AV_CMD_VIDEO_VID_NONE                        0x0000
+#define PS3AV_CMD_VIDEO_VID_480I                        0x0001
+#define PS3AV_CMD_VIDEO_VID_576I                        0x0003
+#define PS3AV_CMD_VIDEO_VID_480P                        0x0005
+#define PS3AV_CMD_VIDEO_VID_576P                        0x0006
+#define PS3AV_CMD_VIDEO_VID_1080I_60HZ                  0x0007
+#define PS3AV_CMD_VIDEO_VID_1080I_50HZ                  0x0008
+#define PS3AV_CMD_VIDEO_VID_720P_60HZ                   0x0009
+#define PS3AV_CMD_VIDEO_VID_720P_50HZ                   0x000a
+#define PS3AV_CMD_VIDEO_VID_1080P_60HZ                  0x000b
+#define PS3AV_CMD_VIDEO_VID_1080P_50HZ                  0x000c
+#define PS3AV_CMD_VIDEO_VID_WXGA                        0x000d
+#define PS3AV_CMD_VIDEO_VID_SXGA                        0x000e
+#define PS3AV_CMD_VIDEO_VID_WUXGA                       0x000f
+#define PS3AV_CMD_VIDEO_VID_480I_A                      0x0010
+/* video_format */
+#define PS3AV_CMD_VIDEO_FORMAT_BLACK                    0x0000
+#define PS3AV_CMD_VIDEO_FORMAT_ARGB_8BIT                0x0007
+/* video_order */
+#define PS3AV_CMD_VIDEO_ORDER_RGB                       0x0000
+#define PS3AV_CMD_VIDEO_ORDER_BGR                       0x0001
+/* video_fmt */
+#define PS3AV_CMD_VIDEO_FMT_X8R8G8B8                    0x0000
+/* video_out_format */
+#define PS3AV_CMD_VIDEO_OUT_FORMAT_RGB_12BIT            0x0000
+/* video_cl_cnv */
+#define PS3AV_CMD_VIDEO_CL_CNV_ENABLE_LUT               0x0000
+#define PS3AV_CMD_VIDEO_CL_CNV_DISABLE_LUT              0x0010
+/* video_sync */
+#define PS3AV_CMD_VIDEO_SYNC_VSYNC                      0x0001
+#define PS3AV_CMD_VIDEO_SYNC_CSYNC                      0x0004
+#define PS3AV_CMD_VIDEO_SYNC_HSYNC                      0x0010
+
+/* for audio module */
+/* num_of_ch */
+#define PS3AV_CMD_AUDIO_NUM_OF_CH_2                     0x0000
+#define PS3AV_CMD_AUDIO_NUM_OF_CH_3                     0x0001
+#define PS3AV_CMD_AUDIO_NUM_OF_CH_4                     0x0002
+#define PS3AV_CMD_AUDIO_NUM_OF_CH_5                     0x0003
+#define PS3AV_CMD_AUDIO_NUM_OF_CH_6                     0x0004
+#define PS3AV_CMD_AUDIO_NUM_OF_CH_7                     0x0005
+#define PS3AV_CMD_AUDIO_NUM_OF_CH_8                     0x0006
+/* audio_fs */
+#define PS3AV_CMD_AUDIO_FS_32K                          0x0001
+#define PS3AV_CMD_AUDIO_FS_44K                          0x0002
+#define PS3AV_CMD_AUDIO_FS_48K                          0x0003
+#define PS3AV_CMD_AUDIO_FS_88K                          0x0004
+#define PS3AV_CMD_AUDIO_FS_96K                          0x0005
+#define PS3AV_CMD_AUDIO_FS_176K                         0x0006
+#define PS3AV_CMD_AUDIO_FS_192K                         0x0007
+/* audio_word_bits */
+#define PS3AV_CMD_AUDIO_WORD_BITS_16                    0x0001
+#define PS3AV_CMD_AUDIO_WORD_BITS_20                    0x0002
+#define PS3AV_CMD_AUDIO_WORD_BITS_24                    0x0003
+/* audio_format */
+#define PS3AV_CMD_AUDIO_FORMAT_PCM                      0x0001
+#define PS3AV_CMD_AUDIO_FORMAT_BITSTREAM                0x00ff
+/* audio_source */
+#define PS3AV_CMD_AUDIO_SOURCE_SERIAL                   0x0000
+#define PS3AV_CMD_AUDIO_SOURCE_SPDIF                    0x0001
+/* audio_swap */
+#define PS3AV_CMD_AUDIO_SWAP_0                          0x0000
+#define PS3AV_CMD_AUDIO_SWAP_1                          0x0000
+/* audio_map */
+#define PS3AV_CMD_AUDIO_MAP_OUTPUT_0                    0x0000
+#define PS3AV_CMD_AUDIO_MAP_OUTPUT_1                    0x0001
+#define PS3AV_CMD_AUDIO_MAP_OUTPUT_2                    0x0002
+#define PS3AV_CMD_AUDIO_MAP_OUTPUT_3                    0x0003
+/* audio_layout */
+#define PS3AV_CMD_AUDIO_LAYOUT_2CH                      0x0000
+#define PS3AV_CMD_AUDIO_LAYOUT_6CH                      0x000b  /* LREClr */
+#define PS3AV_CMD_AUDIO_LAYOUT_8CH                      0x001f  /* LREClrXY */
+/* audio_downmix */
+#define PS3AV_CMD_AUDIO_DOWNMIX_PERMITTED               0x0000
+#define PS3AV_CMD_AUDIO_DOWNMIX_PROHIBITED              0x0001
+
+/* audio_port */
+#define PS3AV_CMD_AUDIO_PORT_HDMI_0                     ( 1 << 0 )
+#define PS3AV_CMD_AUDIO_PORT_HDMI_1                     ( 1 << 1 )
+#define PS3AV_CMD_AUDIO_PORT_AVMULTI_0                  ( 1 << 10 )
+#define PS3AV_CMD_AUDIO_PORT_SPDIF_0                    ( 1 << 20 )
+#define PS3AV_CMD_AUDIO_PORT_SPDIF_1                    ( 1 << 21 )
+
+/* audio_ctrl_id */
+#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_RESET               0x0000
+#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_DE_EMPHASIS         0x0001
+#define PS3AV_CMD_AUDIO_CTRL_ID_AVCLK                   0x0002
+/* audio_ctrl_data[0] reset */
+#define PS3AV_CMD_AUDIO_CTRL_RESET_NEGATE               0x0000
+#define PS3AV_CMD_AUDIO_CTRL_RESET_ASSERT               0x0001
+/* audio_ctrl_data[0] de-emphasis */
+#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_OFF            0x0000
+#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_ON             0x0001
+/* audio_ctrl_data[0] avclk */
+#define PS3AV_CMD_AUDIO_CTRL_AVCLK_22                   0x0000
+#define PS3AV_CMD_AUDIO_CTRL_AVCLK_18                   0x0001
+
+/* av_vid */
+/* do not use these params directly, use vid_video2av */
+#define PS3AV_CMD_AV_VID_480I                           0x0000
+#define PS3AV_CMD_AV_VID_480P                           0x0001
+#define PS3AV_CMD_AV_VID_720P_60HZ                      0x0002
+#define PS3AV_CMD_AV_VID_1080I_60HZ                     0x0003
+#define PS3AV_CMD_AV_VID_1080P_60HZ                     0x0004
+#define PS3AV_CMD_AV_VID_576I                           0x0005
+#define PS3AV_CMD_AV_VID_576P                           0x0006
+#define PS3AV_CMD_AV_VID_720P_50HZ                      0x0007
+#define PS3AV_CMD_AV_VID_1080I_50HZ                     0x0008
+#define PS3AV_CMD_AV_VID_1080P_50HZ                     0x0009
+#define PS3AV_CMD_AV_VID_WXGA                           0x000a
+#define PS3AV_CMD_AV_VID_SXGA                           0x000b
+#define PS3AV_CMD_AV_VID_WUXGA                          0x000c
+/* av_cs_out av_cs_in */
+/* use cs_video2av() */
+#define PS3AV_CMD_AV_CS_RGB_8                           0x0000
+#define PS3AV_CMD_AV_CS_YUV444_8                        0x0001
+#define PS3AV_CMD_AV_CS_YUV422_8                        0x0002
+#define PS3AV_CMD_AV_CS_XVYCC_8                         0x0003
+#define PS3AV_CMD_AV_CS_RGB_10                          0x0004
+#define PS3AV_CMD_AV_CS_YUV444_10                       0x0005
+#define PS3AV_CMD_AV_CS_YUV422_10                       0x0006
+#define PS3AV_CMD_AV_CS_XVYCC_10                        0x0007
+#define PS3AV_CMD_AV_CS_RGB_12                          0x0008
+#define PS3AV_CMD_AV_CS_YUV444_12                       0x0009
+#define PS3AV_CMD_AV_CS_YUV422_12                       0x000a
+#define PS3AV_CMD_AV_CS_XVYCC_12                        0x000b
+#define PS3AV_CMD_AV_CS_8                               0x0000
+#define PS3AV_CMD_AV_CS_10                              0x0001
+#define PS3AV_CMD_AV_CS_12                              0x0002
+/* dither */
+#define PS3AV_CMD_AV_DITHER_OFF                         0x0000
+#define PS3AV_CMD_AV_DITHER_ON                          0x0001
+#define PS3AV_CMD_AV_DITHER_8BIT                        0x0000
+#define PS3AV_CMD_AV_DITHER_10BIT                       0x0002
+#define PS3AV_CMD_AV_DITHER_12BIT                       0x0004
+/* super_white */
+#define PS3AV_CMD_AV_SUPER_WHITE_OFF                    0x0000
+#define PS3AV_CMD_AV_SUPER_WHITE_ON                     0x0001
+/* aspect */
+#define PS3AV_CMD_AV_ASPECT_16_9                        0x0000
+#define PS3AV_CMD_AV_ASPECT_4_3                         0x0001
+/* video_cs_cnv() */
+#define PS3AV_CMD_VIDEO_CS_RGB                          0x0001
+#define PS3AV_CMD_VIDEO_CS_YUV422                       0x0002
+#define PS3AV_CMD_VIDEO_CS_YUV444                       0x0003
+
+/* for broadcast automode */
+#define PS3AV_RESBIT_720x480P                   0x0003  /* 0x0001 | 0x0002 */
+#define PS3AV_RESBIT_720x576P                   0x0003  /* 0x0001 | 0x0002 */
+#define PS3AV_RESBIT_1280x720P                  0x0004
+#define PS3AV_RESBIT_1920x1080I                 0x0008
+#define PS3AV_RESBIT_1920x1080P                 0x4000
+#define PS3AV_RES_MASK_60                       (PS3AV_RESBIT_720x480P \
+                                                | PS3AV_RESBIT_1280x720P \
+                                                | PS3AV_RESBIT_1920x1080I \
+                                                | PS3AV_RESBIT_1920x1080P)
+#define PS3AV_RES_MASK_50                       (PS3AV_RESBIT_720x576P \
+                                                | PS3AV_RESBIT_1280x720P \
+                                                | PS3AV_RESBIT_1920x1080I \
+                                                | PS3AV_RESBIT_1920x1080P)
+
+/* for VESA automode */
+#define PS3AV_RESBIT_VGA                        0x0001
+#define PS3AV_RESBIT_WXGA                       0x0002
+#define PS3AV_RESBIT_SXGA                       0x0004
+#define PS3AV_RESBIT_WUXGA                      0x0008
+#define PS3AV_RES_MASK_VESA                     (PS3AV_RESBIT_WXGA |\
+                                                 PS3AV_RESBIT_SXGA |\
+                                                 PS3AV_RESBIT_WUXGA)
+
+#define PS3AV_MONITOR_TYPE_HDMI                 1       /* HDMI */
+#define PS3AV_MONITOR_TYPE_DVI                  2       /* DVI */
+
+
+/* for video mode */
+enum ps3av_mode_num {
+        PS3AV_MODE_AUTO                         = 0,
+        PS3AV_MODE_480I                         = 1,
+        PS3AV_MODE_480P                         = 2,
+        PS3AV_MODE_720P60                       = 3,
+        PS3AV_MODE_1080I60                      = 4,
+        PS3AV_MODE_1080P60                      = 5,
+        PS3AV_MODE_576I                         = 6,
+        PS3AV_MODE_576P                         = 7,
+        PS3AV_MODE_720P50                       = 8,
+        PS3AV_MODE_1080I50                      = 9,
+        PS3AV_MODE_1080P50                      = 10,
+        PS3AV_MODE_WXGA                         = 11,
+        PS3AV_MODE_SXGA                         = 12,
+        PS3AV_MODE_WUXGA                        = 13,
+};
+
+#define PS3AV_MODE_MASK                         0x000F
+#define PS3AV_MODE_HDCP_OFF                     0x1000  /* Retail PS3 product doesn't support this */
+#define PS3AV_MODE_DITHER                       0x0800
+#define PS3AV_MODE_COLOR                        0x0400
+#define PS3AV_MODE_WHITE                        0x0200
+#define PS3AV_MODE_FULL                         0x0080
+#define PS3AV_MODE_DVI                          0x0040
+#define PS3AV_MODE_RGB                          0x0020
+
+
+#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_60       PS3AV_MODE_480P
+#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_60    PS3AV_MODE_480I
+#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_50       PS3AV_MODE_576P
+#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_50    PS3AV_MODE_576I
+
+#define PS3AV_REGION_60                         0x01
+#define PS3AV_REGION_50                         0x02
+#define PS3AV_REGION_RGB                        0x10
+
+#define get_status(buf)                         (((__u32 *)buf)[2])
+#define PS3AV_HDR_SIZE                          4       /* version + size */
+
+
+/** command packet structure **/
+struct ps3av_send_hdr {
+        u16 version;
+        u16 size;               /* size of command packet */
+        u32 cid;                /* command id */
+};
+
+struct ps3av_reply_hdr {
+        u16 version;
+        u16 size;
+        u32 cid;
+        u32 status;
+};
+
+/* backend: initialization */
+struct ps3av_pkt_av_init {
+        struct ps3av_send_hdr send_hdr;
+        u32 event_bit;
+};
+
+/* backend: finalize */
+struct ps3av_pkt_av_fin {
+        struct ps3av_send_hdr send_hdr;
+        /* recv */
+        u32 reserved;
+};
+
+/* backend: get port */
+struct ps3av_pkt_av_get_hw_conf {
+        struct ps3av_send_hdr send_hdr;
+        /* recv */
+        u32 status;
+        u16 num_of_hdmi;        /* out: number of hdmi */
+        u16 num_of_avmulti;     /* out: number of avmulti */
+        u16 num_of_spdif;       /* out: number of hdmi */
+        u16 reserved;
+};
+
+/* backend: get monitor info */
+struct ps3av_info_resolution {
+        u32 res_bits;
+        u32 native;
+};
+
+struct ps3av_info_cs {
+        u8 rgb;
+        u8 yuv444;
+        u8 yuv422;
+        u8 reserved;
+};
+
+struct ps3av_info_color {
+        u16 red_x;
+        u16 red_y;
+        u16 green_x;
+        u16 green_y;
+        u16 blue_x;
+        u16 blue_y;
+        u16 white_x;
+        u16 white_y;
+        u32 gamma;
+};
+
+struct ps3av_info_audio {
+        u8 type;
+        u8 max_num_of_ch;
+        u8 fs;
+        u8 sbit;
+};
+
+struct ps3av_info_monitor {
+        u8 avport;
+        u8 monitor_id[10];
+        u8 monitor_type;
+        u8 monitor_name[16];
+        struct ps3av_info_resolution res_60;
+        struct ps3av_info_resolution res_50;
+        struct ps3av_info_resolution res_other;
+        struct ps3av_info_resolution res_vesa;
+        struct ps3av_info_cs cs;
+        struct ps3av_info_color color;
+        u8 supported_ai;
+        u8 speaker_info;
+        u8 num_of_audio_block;
+        struct ps3av_info_audio audio[0];       /* 0 or more audio blocks */
+        u8 reserved[169];
+} __attribute__ ((packed));
+
+struct ps3av_pkt_av_get_monitor_info {
+        struct ps3av_send_hdr send_hdr;
+        u16 avport;             /* in: avport */
+        u16 reserved;
+        /* recv */
+        struct ps3av_info_monitor info; /* out: monitor info */
+};
+
+/* backend: enable/disable event */
+struct ps3av_pkt_av_event {
+        struct ps3av_send_hdr send_hdr;
+        u32 event_bit;          /* in */
+};
+
+/* backend: video cs param */
+struct ps3av_pkt_av_video_cs {
+        struct ps3av_send_hdr send_hdr;
+        u16 avport;             /* in: avport */
+        u16 av_vid;             /* in: video resolution */
+        u16 av_cs_out;          /* in: output color space */
+        u16 av_cs_in;           /* in: input color space */
+        u8 dither;              /* in: dither bit length */
+        u8 bitlen_out;          /* in: bit length */
+        u8 super_white;         /* in: super white */
+        u8 aspect;              /* in: aspect ratio */
+};
+
+/* backend: video mute */
+struct ps3av_av_mute {
+        u16 avport;             /* in: avport */
+        u16 mute;               /* in: mute on/off */
+};
+
+struct ps3av_pkt_av_video_mute {
+        struct ps3av_send_hdr send_hdr;
+        struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
+};
+
+/* backend: video disable signal */
+struct ps3av_pkt_av_video_disable_sig {
+        struct ps3av_send_hdr send_hdr;
+        u16 avport;             /* in: avport */
+        u16 reserved;
+};
+
+/* backend: audio param */
+struct ps3av_audio_info_frame {
+        struct pb1_bit {
+                u8 ct:4;
+                u8 rsv:1;
+                u8 cc:3;
+        } pb1;
+        struct pb2_bit {
+                u8 rsv:3;
+                u8 sf:3;
+                u8 ss:2;
+        } pb2;
+        u8 pb3;
+        u8 pb4;
+        struct pb5_bit {
+                u8 dm:1;
+                u8 lsv:4;
+                u8 rsv:3;
+        } pb5;
+};
+
+struct ps3av_pkt_av_audio_param {
+        struct ps3av_send_hdr send_hdr;
+        u16 avport;             /* in: avport */
+        u16 reserved;
+        u8 mclk;                /* in: audio mclk */
+        u8 ns[3];               /* in: audio ns val */
+        u8 enable;              /* in: audio enable */
+        u8 swaplr;              /* in: audio swap */
+        u8 fifomap;             /* in: audio fifomap */
+        u8 inputctrl;           /* in: audio input ctrl */
+        u8 inputlen;            /* in: sample bit size */
+        u8 layout;              /* in: speaker layout param */
+        struct ps3av_audio_info_frame info;     /* in: info */
+        u8 chstat[5];           /* in: ch stat */
+};
+
+/* backend: audio_mute */
+struct ps3av_pkt_av_audio_mute {
+        struct ps3av_send_hdr send_hdr;
+        struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
+};
+
+/* backend: hdmi_mode */
+struct ps3av_pkt_av_hdmi_mode {
+        struct ps3av_send_hdr send_hdr;
+        u8 mode;                /* in: hdmi_mode */
+        u8 reserved0;
+        u8 reserved1;
+        u8 reserved2;
+};
+
+/* backend: tv_mute */
+struct ps3av_pkt_av_tv_mute {
+        struct ps3av_send_hdr send_hdr;
+        u16 avport;             /* in: avport HDMI only */
+        u16 mute;               /* in: mute */
+};
+
+/* video: initialize */
+struct ps3av_pkt_video_init {
+        struct ps3av_send_hdr send_hdr;
+        /* recv */
+        u32 reserved;
+};
+
+/* video: mode setting */
+struct ps3av_pkt_video_mode {
+        struct ps3av_send_hdr send_hdr;
+        u32 video_head;         /* in: head */
+        u32 reserved;
+        u32 video_vid;          /* in: video resolution */
+        u16 reserved1;
+        u16 width;              /* in: width in pixel */
+        u16 reserved2;
+        u16 height;             /* in: height in pixel */
+        u32 pitch;              /* in: line size in byte */
+        u32 video_out_format;   /* in: out format */
+        u32 video_format;       /* in: input frame buffer format */
+        u8 reserved3;
+        u8 video_cl_cnv;        /* in: color conversion */
+        u16 video_order;        /* in: input RGB order */
+        u32 reserved4;
+};
+
+/* video: format */
+struct ps3av_pkt_video_format {
+        struct ps3av_send_hdr send_hdr;
+        u32 video_head;         /* in: head */
+        u32 video_format;       /* in: frame buffer format */
+        u8 reserved;
+        u8 video_cl_cnv;        /* in: color conversion */
+        u16 video_order;        /* in: input RGB order */
+};
+
+/* video: pitch */
+struct ps3av_pkt_video_pitch {
+        u16 version;
+        u16 size;               /* size of command packet */
+        u32 cid;                /* command id */
+        u32 video_head;         /* in: head */
+        u32 pitch;              /* in: line size in byte */
+};
+
+/* audio: initialize */
+struct ps3av_pkt_audio_init {
+        struct ps3av_send_hdr send_hdr;
+        /* recv */
+        u32 reserved;
+};
+
+/* audio: mode setting */
+struct ps3av_pkt_audio_mode {
+        struct ps3av_send_hdr send_hdr;
+        u8 avport;              /* in: avport */
+        u8 reserved0[3];
+        u32 mask;               /* in: mask */
+        u32 audio_num_of_ch;    /* in: number of ch */
+        u32 audio_fs;           /* in: sampling freq */
+        u32 audio_word_bits;    /* in: sample bit size */
+        u32 audio_format;       /* in: audio output format */
+        u32 audio_source;       /* in: audio source */
+        u8 audio_enable[4];     /* in: audio enable */
+        u8 audio_swap[4];       /* in: audio swap */
+        u8 audio_map[4];        /* in: audio map */
+        u32 audio_layout;       /* in: speaker layout */
+        u32 audio_downmix;      /* in: audio downmix permission */
+        u32 audio_downmix_level;
+        u8 audio_cs_info[8];    /* in: IEC channel status */
+};
+
+/* audio: mute */
+struct ps3av_audio_mute {
+        u8 avport;              /* in: opt_port optical */
+        u8 reserved[3];
+        u32 mute;               /* in: mute */
+};
+
+struct ps3av_pkt_audio_mute {
+        struct ps3av_send_hdr send_hdr;
+        struct ps3av_audio_mute mute[PS3AV_OPT_PORT_MAX];
+};
+
+/* audio: active/inactive */
+struct ps3av_pkt_audio_active {
+        struct ps3av_send_hdr send_hdr;
+        u32 audio_port;         /* in: audio active/inactive port */
+};
+
+/* audio: SPDIF user bit */
+struct ps3av_pkt_audio_spdif_bit {
+        u16 version;
+        u16 size;               /* size of command packet */
+        u32 cid;                /* command id */
+        u8 avport;              /* in: avport SPDIF only */
+        u8 reserved[3];
+        u32 audio_port;         /* in: SPDIF only */
+        u32 spdif_bit_data[12]; /* in: user bit data */
+};
+
+/* audio: audio control */
+struct ps3av_pkt_audio_ctrl {
+        u16 version;
+        u16 size;               /* size of command packet */
+        u32 cid;                /* command id */
+        u32 audio_ctrl_id;      /* in: control id */
+        u32 audio_ctrl_data[4]; /* in: control data */
+};
+
+/* avb:param */
+#define PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE        \
+        (PS3AV_AVB_NUM_VIDEO*sizeof(struct ps3av_pkt_video_mode) + \
+         PS3AV_AVB_NUM_AUDIO*sizeof(struct ps3av_pkt_audio_mode) + \
+         PS3AV_AVB_NUM_AV_VIDEO*sizeof(struct ps3av_pkt_av_video_cs) + \
+         PS3AV_AVB_NUM_AV_AUDIO*sizeof(struct ps3av_pkt_av_audio_param))
+
+struct ps3av_pkt_avb_param {
+        struct ps3av_send_hdr send_hdr;
+        u16 num_of_video_pkt;
+        u16 num_of_audio_pkt;
+        u16 num_of_av_video_pkt;
+        u16 num_of_av_audio_pkt;
+        /*
+         * The actual buffer layout depends on the fields above:
+         *
+         * struct ps3av_pkt_video_mode video[num_of_video_pkt];
+         * struct ps3av_pkt_audio_mode audio[num_of_audio_pkt];
+         * struct ps3av_pkt_av_video_cs av_video[num_of_av_video_pkt];
+         * struct ps3av_pkt_av_audio_param av_audio[num_of_av_audio_pkt];
+         */
+        u8 buf[PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE];
+};
+
+
+/** command status **/
+#define PS3AV_STATUS_SUCCESS                    0x0000  /* success */
+#define PS3AV_STATUS_RECEIVE_VUART_ERROR        0x0001  /* receive vuart error */
+#define PS3AV_STATUS_SYSCON_COMMUNICATE_FAIL    0x0002  /* syscon communication error */
+#define PS3AV_STATUS_INVALID_COMMAND            0x0003  /* obsolete invalid CID */
+#define PS3AV_STATUS_INVALID_PORT               0x0004  /* invalid port number */
+#define PS3AV_STATUS_INVALID_VID                0x0005  /* invalid video format */
+#define PS3AV_STATUS_INVALID_COLOR_SPACE        0x0006  /* invalid video colose space */
+#define PS3AV_STATUS_INVALID_FS                 0x0007  /* invalid audio sampling freq */
+#define PS3AV_STATUS_INVALID_AUDIO_CH           0x0008  /* invalid audio channel number */
+#define PS3AV_STATUS_UNSUPPORTED_VERSION        0x0009  /* version mismatch  */
+#define PS3AV_STATUS_INVALID_SAMPLE_SIZE        0x000a  /* invalid audio sample bit size */
+#define PS3AV_STATUS_FAILURE                    0x000b  /* other failures */
+#define PS3AV_STATUS_UNSUPPORTED_COMMAND        0x000c  /* unsupported cid */
+#define PS3AV_STATUS_BUFFER_OVERFLOW            0x000d  /* write buffer overflow */
+#define PS3AV_STATUS_INVALID_VIDEO_PARAM        0x000e  /* invalid video param */
+#define PS3AV_STATUS_NO_SEL                     0x000f  /* not exist selector */
+#define PS3AV_STATUS_INVALID_AV_PARAM           0x0010  /* invalid backend param */
+#define PS3AV_STATUS_INVALID_AUDIO_PARAM        0x0011  /* invalid audio param */
+#define PS3AV_STATUS_UNSUPPORTED_HDMI_MODE      0x0012  /* unsupported hdmi mode */
+#define PS3AV_STATUS_NO_SYNC_HEAD               0x0013  /* sync head failed */
+
+extern void ps3av_set_hdr(u32, u16, struct ps3av_send_hdr *);
+extern int ps3av_do_pkt(u32, u16, size_t, struct ps3av_send_hdr *);
+
+extern int ps3av_cmd_init(void);
+extern int ps3av_cmd_fin(void);
+extern int ps3av_cmd_av_video_mute(int, u32 *, u32);
+extern int ps3av_cmd_av_video_disable_sig(u32);
+extern int ps3av_cmd_av_tv_mute(u32, u32);
+extern int ps3av_cmd_enable_event(void);
+extern int ps3av_cmd_av_hdmi_mode(u8);
+extern u32 ps3av_cmd_set_av_video_cs(void *, u32, int, int, int, u32);
+extern u32 ps3av_cmd_set_video_mode(void *, u32, int, int, u32);
+extern int ps3av_cmd_video_format_black(u32, u32, u32);
+extern int ps3av_cmd_av_audio_mute(int, u32 *, u32);
+extern u32 ps3av_cmd_set_av_audio_param(void *, u32,
+                                        const struct ps3av_pkt_audio_mode *,
+                                        u32);
+extern void ps3av_cmd_set_audio_mode(struct ps3av_pkt_audio_mode *, u32, u32,
+                                     u32, u32, u32, u32);
+extern int ps3av_cmd_audio_mode(struct ps3av_pkt_audio_mode *);
+extern int ps3av_cmd_audio_mute(int, u32 *, u32);
+extern int ps3av_cmd_audio_active(int, u32);
+extern int ps3av_cmd_avb_param(struct ps3av_pkt_avb_param *, u32);
+extern int ps3av_cmd_av_get_hw_conf(struct ps3av_pkt_av_get_hw_conf *);
+extern int ps3av_cmd_video_get_monitor_info(struct ps3av_pkt_av_get_monitor_info *,
+                                            u32);
+
+extern int ps3av_set_video_mode(u32);
+extern int ps3av_set_audio_mode(u32, u32, u32, u32, u32);
+extern int ps3av_get_auto_mode(void);
+extern int ps3av_get_mode(void);
+extern int ps3av_video_mode2res(u32, u32 *, u32 *);
+extern int ps3av_video_mute(int);
+extern int ps3av_audio_mute(int);
+extern int ps3av_dev_open(void);
+extern int ps3av_dev_close(void);
+extern void ps3av_register_flip_ctl(void (*flip_ctl)(int on, void *data),
+                                    void *flip_data);
+extern void ps3av_flip_ctl(int on);
+
+#endif  /* _ASM_POWERPC_PS3AV_H_ */
diff --git a/arch/powerpc/include/asm/ps3fb.h b/arch/powerpc/include/asm/ps3fb.h
new file mode 100644
index 000000000000..3f121fe4010d
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3fb.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2006 Sony Computer Entertainment Inc.
+ * Copyright 2006, 2007 Sony Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _ASM_POWERPC_PS3FB_H_
+#define _ASM_POWERPC_PS3FB_H_
+
+#include <linux/ioctl.h>
+
+/* ioctl */
+#define PS3FB_IOCTL_SETMODE       _IOW('r',  1, int) /* set video mode */
+#define PS3FB_IOCTL_GETMODE       _IOR('r',  2, int) /* get video mode */
+#define PS3FB_IOCTL_SCREENINFO    _IOR('r',  3, int) /* get screen info */
+#define PS3FB_IOCTL_ON            _IO('r', 4)        /* use IOCTL_FSEL */
+#define PS3FB_IOCTL_OFF           _IO('r', 5)        /* return to normal-flip */
+#define PS3FB_IOCTL_FSEL          _IOW('r', 6, int)  /* blit and flip request */
+
+#ifndef FBIO_WAITFORVSYNC
+#define FBIO_WAITFORVSYNC         _IOW('F', 0x20, __u32) /* wait for vsync */
+#endif
+
+struct ps3fb_ioctl_res {
+        __u32 xres; /* frame buffer x_size */
+        __u32 yres; /* frame buffer y_size */
+        __u32 xoff; /* margine x  */
+        __u32 yoff; /* margine y */
+        __u32 num_frames; /* num of frame buffers */
+};
+
+#endif /* _ASM_POWERPC_PS3FB_H_ */
diff --git a/arch/powerpc/include/asm/ps3stor.h b/arch/powerpc/include/asm/ps3stor.h
new file mode 100644
index 000000000000..6fcaf714fa50
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3stor.h
@@ -0,0 +1,71 @@
+/*
+ * PS3 Storage Devices
+ *
+ * Copyright (C) 2007 Sony Computer Entertainment Inc.
+ * Copyright 2007 Sony Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _ASM_POWERPC_PS3STOR_H_
+#define _ASM_POWERPC_PS3STOR_H_
+
+#include <linux/interrupt.h>
+
+#include <asm/ps3.h>
+
+
+struct ps3_storage_region {
+        unsigned int id;
+        u64 start;
+        u64 size;
+};
+
+struct ps3_storage_device {
+        struct ps3_system_bus_device sbd;
+
+        struct ps3_dma_region dma_region;
+        unsigned int irq;
+        u64 blk_size;
+
+        u64 tag;
+        u64 lv1_status;
+        struct completion done;
+
+        unsigned long bounce_size;
+        void *bounce_buf;
+        u64 bounce_lpar;
+        dma_addr_t bounce_dma;
+
+        unsigned int num_regions;
+        unsigned long accessible_regions;
+        unsigned int region_idx;                /* first accessible region */
+        struct ps3_storage_region regions[0];   /* Must be last */
+};
+
+static inline struct ps3_storage_device *to_ps3_storage_device(struct device *dev)
+{
+        return container_of(dev, struct ps3_storage_device, sbd.core);
+}
+
+extern int ps3stor_setup(struct ps3_storage_device *dev,
+                         irq_handler_t handler);
+extern void ps3stor_teardown(struct ps3_storage_device *dev);
+extern u64 ps3stor_read_write_sectors(struct ps3_storage_device *dev, u64 lpar,
+                                      u64 start_sector, u64 sectors,
+                                      int write);
+extern u64 ps3stor_send_command(struct ps3_storage_device *dev, u64 cmd,
+                                u64 arg1, u64 arg2, u64 arg3, u64 arg4);
+
+#endif /* _ASM_POWERPC_PS3STOR_H_ */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
new file mode 100644
index 000000000000..734e0754fb9b
--- /dev/null
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -0,0 +1,293 @@
+#ifndef _ASM_POWERPC_PTRACE_H
+#define _ASM_POWERPC_PTRACE_H
+
+/*
+ * Copyright (C) 2001 PPC64 Team, IBM Corp
+ *
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ *
+ * this should only contain volatile regs
+ * since we can keep non-volatile in the thread_struct
+ * should set this up when only volatiles are saved
+ * by intr code.
+ *
+ * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
+ * that the overall structure is a multiple of 16 bytes in length.
+ *
+ * Note that the offsets of the fields in this struct correspond with
+ * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+        unsigned long gpr[32];
+        unsigned long nip;
+        unsigned long msr;
+        unsigned long orig_gpr3;        /* Used for restarting system calls */
+        unsigned long ctr;
+        unsigned long link;
+        unsigned long xer;
+        unsigned long ccr;
+#ifdef __powerpc64__
+        unsigned long softe;            /* Soft enabled/disabled */
+#else
+        unsigned long mq;               /* 601 only (not used at present) */
+                                        /* Used on APUS to hold IPL value. */
+#endif
+        unsigned long trap;             /* Reason for being here */
+        /* N.B. for critical exceptions on 4xx, the dar and dsisr
+           fields are overloaded to hold srr0 and srr1. */
+        unsigned long dar;              /* Fault registers */
+        unsigned long dsisr;            /* on 4xx/Book-E used for ESR */
+        unsigned long result;           /* Result of a system call */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+
+#ifdef __powerpc64__
+
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+
+#define STACK_FRAME_OVERHEAD    112     /* size of minimum stack frame */
+#define STACK_FRAME_LR_SAVE     2       /* Location of LR in stack frame */
+#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
+#define STACK_INT_FRAME_SIZE    (sizeof(struct pt_regs) + \
+                                        STACK_FRAME_OVERHEAD + 288)
+#define STACK_FRAME_MARKER      12
+
+/* Size of dummy stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE      128
+#define __SIGNAL_FRAMESIZE32    64
+
+#else /* __powerpc64__ */
+
+#define STACK_FRAME_OVERHEAD    16      /* size of minimum stack frame */
+#define STACK_FRAME_LR_SAVE     1       /* Location of LR in stack frame */
+#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
+#define STACK_INT_FRAME_SIZE    (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
+#define STACK_FRAME_MARKER      2
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE      64
+
+#endif /* __powerpc64__ */
+
+#ifndef __ASSEMBLY__
+
+#define instruction_pointer(regs) ((regs)->nip)
+#define user_stack_pointer(regs) ((regs)->gpr[1])
+#define regs_return_value(regs) ((regs)->gpr[3])
+
+#ifdef CONFIG_SMP
+extern unsigned long profile_pc(struct pt_regs *regs);
+#else
+#define profile_pc(regs) instruction_pointer(regs)
+#endif
+
+#ifdef __powerpc64__
+#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
+#else
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+#endif
+
+#define force_successful_syscall_return()   \
+        do { \
+                set_thread_flag(TIF_NOERROR); \
+        } while(0)
+
+struct task_struct;
+extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
+extern int ptrace_put_reg(struct task_struct *task, int regno,
+                          unsigned long data);
+
+/*
+ * We use the least-significant bit of the trap field to indicate
+ * whether we have saved the full set of registers, or only a
+ * partial set.  A 1 there means the partial set.
+ * On 4xx we use the next bit to indicate whether the exception
+ * is a critical exception (1 means it is).
+ */
+#define FULL_REGS(regs)         (((regs)->trap & 1) == 0)
+#ifndef __powerpc64__
+#define IS_CRITICAL_EXC(regs)   (((regs)->trap & 2) != 0)
+#define IS_MCHECK_EXC(regs)     (((regs)->trap & 4) != 0)
+#define IS_DEBUG_EXC(regs)      (((regs)->trap & 8) != 0)
+#endif /* ! __powerpc64__ */
+#define TRAP(regs)              ((regs)->trap & ~0xF)
+#ifdef __powerpc64__
+#define CHECK_FULL_REGS(regs)   BUG_ON(regs->trap & 1)
+#else
+#define CHECK_FULL_REGS(regs)                                                 \
+do {                                                                          \
+        if ((regs)->trap & 1)                                                 \
+                printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
+} while (0)
+#endif /* __powerpc64__ */
+
+/*
+ * These are defined as per linux/ptrace.h, which see.
+ */
+#define arch_has_single_step()  (1)
+extern void user_enable_single_step(struct task_struct *);
+extern void user_disable_single_step(struct task_struct *);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0   0
+#define PT_R1   1
+#define PT_R2   2
+#define PT_R3   3
+#define PT_R4   4
+#define PT_R5   5
+#define PT_R6   6
+#define PT_R7   7
+#define PT_R8   8
+#define PT_R9   9
+#define PT_R10  10
+#define PT_R11  11
+#define PT_R12  12
+#define PT_R13  13
+#define PT_R14  14
+#define PT_R15  15
+#define PT_R16  16
+#define PT_R17  17
+#define PT_R18  18
+#define PT_R19  19
+#define PT_R20  20
+#define PT_R21  21
+#define PT_R22  22
+#define PT_R23  23
+#define PT_R24  24
+#define PT_R25  25
+#define PT_R26  26
+#define PT_R27  27
+#define PT_R28  28
+#define PT_R29  29
+#define PT_R30  30
+#define PT_R31  31
+
+#define PT_NIP  32
+#define PT_MSR  33
+#define PT_ORIG_R3 34
+#define PT_CTR  35
+#define PT_LNK  36
+#define PT_XER  37
+#define PT_CCR  38
+#ifndef __powerpc64__
+#define PT_MQ   39
+#else
+#define PT_SOFTE 39
+#endif
+#define PT_TRAP 40
+#define PT_DAR  41
+#define PT_DSISR 42
+#define PT_RESULT 43
+#define PT_REGS_COUNT 44
+
+#define PT_FPR0 48      /* each FP reg occupies 2 slots in this space */
+
+#ifndef __powerpc64__
+
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#else /* __powerpc64__ */
+
+#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
+
+#ifdef __KERNEL__
+#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
+#endif
+
+#define PT_VR0 82       /* each Vector reg occupies 2 slots in 64-bit */
+#define PT_VSCR (PT_VR0 + 32*2 + 1)
+#define PT_VRSAVE (PT_VR0 + 33*2)
+
+#ifdef __KERNEL__
+#define PT_VR0_32 164   /* each Vector reg occupies 4 slots in 32-bit */
+#define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
+#define PT_VRSAVE_32 (PT_VR0 + 33*4)
+#endif
+
+/*
+ * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
+ */
+#define PT_VSR0 150     /* each VSR reg occupies 2 slots in 64-bit */
+#define PT_VSR31 (PT_VSR0 + 2*31)
+#ifdef __KERNEL__
+#define PT_VSR0_32 300  /* each VSR reg occupies 4 slots in 32-bit */
+#endif
+#endif /* __powerpc64__ */
+
+/*
+ * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
+ * The transfer totals 34 quadword.  Quadwords 0-31 contain the
+ * corresponding vector registers.  Quadword 32 contains the vscr as the
+ * last word (offset 12) within that quadword.  Quadword 33 contains the
+ * vrsave as the first word (offset 0) within the quadword.
+ *
+ * This definition of the VMX state is compatible with the current PPC32
+ * ptrace interface.  This allows signal handling and ptrace to use the same
+ * structures.  This also simplifies the implementation of a bi-arch
+ * (combined (32- and 64-bit) gdb.
+ */
+#define PTRACE_GETVRREGS        18
+#define PTRACE_SETVRREGS        19
+
+/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
+ * spefscr, in one go */
+#define PTRACE_GETEVRREGS       20
+#define PTRACE_SETEVRREGS       21
+
+/* Get the first 32 128bit VSX registers */
+#define PTRACE_GETVSRREGS       27
+#define PTRACE_SETVSRREGS       28
+
+/*
+ * Get or set a debug register. The first 16 are DABR registers and the
+ * second 16 are IABR registers.
+ */
+#define PTRACE_GET_DEBUGREG     25
+#define PTRACE_SET_DEBUGREG     26
+
+/* (new) PTRACE requests using the same numbers as x86 and the same
+ * argument ordering. Additionally, they support more registers too
+ */
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13
+#define PTRACE_GETFPREGS          14
+#define PTRACE_SETFPREGS          15
+#define PTRACE_GETREGS64          22
+#define PTRACE_SETREGS64          23
+
+/* (old) PTRACE requests with inverted arguments */
+#define PPC_PTRACE_GETREGS      0x99    /* Get GPRs 0 - 31 */
+#define PPC_PTRACE_SETREGS      0x98    /* Set GPRs 0 - 31 */
+#define PPC_PTRACE_GETFPREGS    0x97    /* Get FPRs 0 - 31 */
+#define PPC_PTRACE_SETFPREGS    0x96    /* Set FPRs 0 - 31 */
+
+/* Calls to trace a 64bit program from a 32bit program */
+#define PPC_PTRACE_PEEKTEXT_3264 0x95
+#define PPC_PTRACE_PEEKDATA_3264 0x94
+#define PPC_PTRACE_POKETEXT_3264 0x93
+#define PPC_PTRACE_POKEDATA_3264 0x92
+#define PPC_PTRACE_PEEKUSR_3264  0x91
+#define PPC_PTRACE_POKEUSR_3264  0x90
+
+#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
new file mode 100644
index 000000000000..edee15d269ea
--- /dev/null
+++ b/arch/powerpc/include/asm/qe.h
@@ -0,0 +1,642 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:     Shlomi Gridish <gridish@freescale.com>
+ *              Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * QUICC Engine (QE) external definitions and structure.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_POWERPC_QE_H
+#define _ASM_POWERPC_QE_H
+#ifdef __KERNEL__
+
+#include <linux/spinlock.h>
+#include <asm/cpm.h>
+#include <asm/immap_qe.h>
+
+#define QE_NUM_OF_SNUM  28
+#define QE_NUM_OF_BRGS  16
+#define QE_NUM_OF_PORTS 1024
+
+/* Memory partitions
+*/
+#define MEM_PART_SYSTEM         0
+#define MEM_PART_SECONDARY      1
+#define MEM_PART_MURAM          2
+
+/* Clocks and BRGs */
+enum qe_clock {
+        QE_CLK_NONE = 0,
+        QE_BRG1,                /* Baud Rate Generator 1 */
+        QE_BRG2,                /* Baud Rate Generator 2 */
+        QE_BRG3,                /* Baud Rate Generator 3 */
+        QE_BRG4,                /* Baud Rate Generator 4 */
+        QE_BRG5,                /* Baud Rate Generator 5 */
+        QE_BRG6,                /* Baud Rate Generator 6 */
+        QE_BRG7,                /* Baud Rate Generator 7 */
+        QE_BRG8,                /* Baud Rate Generator 8 */
+        QE_BRG9,                /* Baud Rate Generator 9 */
+        QE_BRG10,               /* Baud Rate Generator 10 */
+        QE_BRG11,               /* Baud Rate Generator 11 */
+        QE_BRG12,               /* Baud Rate Generator 12 */
+        QE_BRG13,               /* Baud Rate Generator 13 */
+        QE_BRG14,               /* Baud Rate Generator 14 */
+        QE_BRG15,               /* Baud Rate Generator 15 */
+        QE_BRG16,               /* Baud Rate Generator 16 */
+        QE_CLK1,                /* Clock 1 */
+        QE_CLK2,                /* Clock 2 */
+        QE_CLK3,                /* Clock 3 */
+        QE_CLK4,                /* Clock 4 */
+        QE_CLK5,                /* Clock 5 */
+        QE_CLK6,                /* Clock 6 */
+        QE_CLK7,                /* Clock 7 */
+        QE_CLK8,                /* Clock 8 */
+        QE_CLK9,                /* Clock 9 */
+        QE_CLK10,               /* Clock 10 */
+        QE_CLK11,               /* Clock 11 */
+        QE_CLK12,               /* Clock 12 */
+        QE_CLK13,               /* Clock 13 */
+        QE_CLK14,               /* Clock 14 */
+        QE_CLK15,               /* Clock 15 */
+        QE_CLK16,               /* Clock 16 */
+        QE_CLK17,               /* Clock 17 */
+        QE_CLK18,               /* Clock 18 */
+        QE_CLK19,               /* Clock 19 */
+        QE_CLK20,               /* Clock 20 */
+        QE_CLK21,               /* Clock 21 */
+        QE_CLK22,               /* Clock 22 */
+        QE_CLK23,               /* Clock 23 */
+        QE_CLK24,               /* Clock 24 */
+        QE_CLK_DUMMY
+};
+
+static inline bool qe_clock_is_brg(enum qe_clock clk)
+{
+        return clk >= QE_BRG1 && clk <= QE_BRG16;
+}
+
+extern spinlock_t cmxgcr_lock;
+
+/* Export QE common operations */
+extern void __init qe_reset(void);
+
+/* QE PIO */
+#define QE_PIO_PINS 32
+
+struct qe_pio_regs {
+        __be32  cpodr;          /* Open drain register */
+        __be32  cpdata;         /* Data register */
+        __be32  cpdir1;         /* Direction register */
+        __be32  cpdir2;         /* Direction register */
+        __be32  cppar1;         /* Pin assignment register */
+        __be32  cppar2;         /* Pin assignment register */
+#ifdef CONFIG_PPC_85xx
+        u8      pad[8];
+#endif
+};
+
+extern int par_io_init(struct device_node *np);
+extern int par_io_of_config(struct device_node *np);
+#define QE_PIO_DIR_IN   2
+#define QE_PIO_DIR_OUT  1
+extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
+                                int dir, int open_drain, int assignment,
+                                int has_irq);
+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
+                             int assignment, int has_irq);
+extern int par_io_data_set(u8 port, u8 pin, u8 val);
+
+/* QE internal API */
+int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
+enum qe_clock qe_clock_source(const char *source);
+unsigned int qe_get_brg_clk(void);
+int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
+int qe_get_snum(void);
+void qe_put_snum(u8 snum);
+/* we actually use cpm_muram implementation, define this for convenience */
+#define qe_muram_init cpm_muram_init
+#define qe_muram_alloc cpm_muram_alloc
+#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
+#define qe_muram_free cpm_muram_free
+#define qe_muram_addr cpm_muram_addr
+#define qe_muram_offset cpm_muram_offset
+
+/* Structure that defines QE firmware binary files.
+ *
+ * See Documentation/powerpc/qe-firmware.txt for a description of these
+ * fields.
+ */
+struct qe_firmware {
+        struct qe_header {
+                __be32 length;  /* Length of the entire structure, in bytes */
+                u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
+                u8 version;     /* Version of this layout. First ver is '1' */
+        } header;
+        u8 id[62];      /* Null-terminated identifier string */
+        u8 split;       /* 0 = shared I-RAM, 1 = split I-RAM */
+        u8 count;       /* Number of microcode[] structures */
+        struct {
+                __be16 model;           /* The SOC model  */
+                u8 major;               /* The SOC revision major */
+                u8 minor;               /* The SOC revision minor */
+        } __attribute__ ((packed)) soc;
+        u8 padding[4];                  /* Reserved, for alignment */
+        __be64 extended_modes;          /* Extended modes */
+        __be32 vtraps[8];               /* Virtual trap addresses */
+        u8 reserved[4];                 /* Reserved, for future expansion */
+        struct qe_microcode {
+                u8 id[32];              /* Null-terminated identifier */
+                __be32 traps[16];       /* Trap addresses, 0 == ignore */
+                __be32 eccr;            /* The value for the ECCR register */
+                __be32 iram_offset;     /* Offset into I-RAM for the code */
+                __be32 count;           /* Number of 32-bit words of the code */
+                __be32 code_offset;     /* Offset of the actual microcode */
+                u8 major;               /* The microcode version major */
+                u8 minor;               /* The microcode version minor */
+                u8 revision;            /* The microcode version revision */
+                u8 padding;             /* Reserved, for alignment */
+                u8 reserved[4];         /* Reserved, for future expansion */
+        } __attribute__ ((packed)) microcode[1];
+        /* All microcode binaries should be located here */
+        /* CRC32 should be located here, after the microcode binaries */
+} __attribute__ ((packed));
+
+struct qe_firmware_info {
+        char id[64];            /* Firmware name */
+        u32 vtraps[8];          /* Virtual trap addresses */
+        u64 extended_modes;     /* Extended modes */
+};
+
+/* Upload a firmware to the QE */
+int qe_upload_firmware(const struct qe_firmware *firmware);
+
+/* Obtain information on the uploaded firmware */
+struct qe_firmware_info *qe_get_firmware_info(void);
+
+/* QE USB */
+int qe_usb_clock_set(enum qe_clock clk, int rate);
+
+/* Buffer descriptors */
+struct qe_bd {
+        __be16 status;
+        __be16 length;
+        __be32 buf;
+} __attribute__ ((packed));
+
+#define BD_STATUS_MASK  0xffff0000
+#define BD_LENGTH_MASK  0x0000ffff
+
+/* Alignment */
+#define QE_INTR_TABLE_ALIGN     16      /* ??? */
+#define QE_ALIGNMENT_OF_BD      8
+#define QE_ALIGNMENT_OF_PRAM    64
+
+/* RISC allocation */
+enum qe_risc_allocation {
+        QE_RISC_ALLOCATION_RISC1 = 1,   /* RISC 1 */
+        QE_RISC_ALLOCATION_RISC2 = 2,   /* RISC 2 */
+        QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3  /* Dynamically choose
+                                                   RISC 1 or RISC 2 */
+};
+
+/* QE extended filtering Table Lookup Key Size */
+enum qe_fltr_tbl_lookup_key_size {
+        QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
+                = 0x3f,         /* LookupKey parsed by the Generate LookupKey
+                                   CMD is truncated to 8 bytes */
+        QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
+                = 0x5f,         /* LookupKey parsed by the Generate LookupKey
+                                   CMD is truncated to 16 bytes */
+};
+
+/* QE FLTR extended filtering Largest External Table Lookup Key Size */
+enum qe_fltr_largest_external_tbl_lookup_key_size {
+        QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
+                = 0x0,/* not used */
+        QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
+                = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,        /* 8 bytes */
+        QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
+                = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,       /* 16 bytes */
+};
+
+/* structure representing QE parameter RAM */
+struct qe_timer_tables {
+        u16 tm_base;            /* QE timer table base adr */
+        u16 tm_ptr;             /* QE timer table pointer */
+        u16 r_tmr;              /* QE timer mode register */
+        u16 r_tmv;              /* QE timer valid register */
+        u32 tm_cmd;             /* QE timer cmd register */
+        u32 tm_cnt;             /* QE timer internal cnt */
+} __attribute__ ((packed));
+
+#define QE_FLTR_TAD_SIZE        8
+
+/* QE extended filtering Termination Action Descriptor (TAD) */
+struct qe_fltr_tad {
+        u8 serialized[QE_FLTR_TAD_SIZE];
+} __attribute__ ((packed));
+
+/* Communication Direction */
+enum comm_dir {
+        COMM_DIR_NONE = 0,
+        COMM_DIR_RX = 1,
+        COMM_DIR_TX = 2,
+        COMM_DIR_RX_AND_TX = 3
+};
+
+/* QE CMXUCR Registers.
+ * There are two UCCs represented in each of the four CMXUCR registers.
+ * These values are for the UCC in the LSBs
+ */
+#define QE_CMXUCR_MII_ENET_MNG          0x00007000
+#define QE_CMXUCR_MII_ENET_MNG_SHIFT    12
+#define QE_CMXUCR_GRANT                 0x00008000
+#define QE_CMXUCR_TSA                   0x00004000
+#define QE_CMXUCR_BKPT                  0x00000100
+#define QE_CMXUCR_TX_CLK_SRC_MASK       0x0000000F
+
+/* QE CMXGCR Registers.
+*/
+#define QE_CMXGCR_MII_ENET_MNG          0x00007000
+#define QE_CMXGCR_MII_ENET_MNG_SHIFT    12
+#define QE_CMXGCR_USBCS                 0x0000000f
+#define QE_CMXGCR_USBCS_CLK3            0x1
+#define QE_CMXGCR_USBCS_CLK5            0x2
+#define QE_CMXGCR_USBCS_CLK7            0x3
+#define QE_CMXGCR_USBCS_CLK9            0x4
+#define QE_CMXGCR_USBCS_CLK13           0x5
+#define QE_CMXGCR_USBCS_CLK17           0x6
+#define QE_CMXGCR_USBCS_CLK19           0x7
+#define QE_CMXGCR_USBCS_CLK21           0x8
+#define QE_CMXGCR_USBCS_BRG9            0x9
+#define QE_CMXGCR_USBCS_BRG10           0xa
+
+/* QE CECR Commands.
+*/
+#define QE_CR_FLG                       0x00010000
+#define QE_RESET                        0x80000000
+#define QE_INIT_TX_RX                   0x00000000
+#define QE_INIT_RX                      0x00000001
+#define QE_INIT_TX                      0x00000002
+#define QE_ENTER_HUNT_MODE              0x00000003
+#define QE_STOP_TX                      0x00000004
+#define QE_GRACEFUL_STOP_TX             0x00000005
+#define QE_RESTART_TX                   0x00000006
+#define QE_CLOSE_RX_BD                  0x00000007
+#define QE_SWITCH_COMMAND               0x00000007
+#define QE_SET_GROUP_ADDRESS            0x00000008
+#define QE_START_IDMA                   0x00000009
+#define QE_MCC_STOP_RX                  0x00000009
+#define QE_ATM_TRANSMIT                 0x0000000a
+#define QE_HPAC_CLEAR_ALL               0x0000000b
+#define QE_GRACEFUL_STOP_RX             0x0000001a
+#define QE_RESTART_RX                   0x0000001b
+#define QE_HPAC_SET_PRIORITY            0x0000010b
+#define QE_HPAC_STOP_TX                 0x0000020b
+#define QE_HPAC_STOP_RX                 0x0000030b
+#define QE_HPAC_GRACEFUL_STOP_TX        0x0000040b
+#define QE_HPAC_GRACEFUL_STOP_RX        0x0000050b
+#define QE_HPAC_START_TX                0x0000060b
+#define QE_HPAC_START_RX                0x0000070b
+#define QE_USB_STOP_TX                  0x0000000a
+#define QE_USB_RESTART_TX               0x0000000c
+#define QE_QMC_STOP_TX                  0x0000000c
+#define QE_QMC_STOP_RX                  0x0000000d
+#define QE_SS7_SU_FIL_RESET             0x0000000e
+/* jonathbr added from here down for 83xx */
+#define QE_RESET_BCS                    0x0000000a
+#define QE_MCC_INIT_TX_RX_16            0x00000003
+#define QE_MCC_STOP_TX                  0x00000004
+#define QE_MCC_INIT_TX_1                0x00000005
+#define QE_MCC_INIT_RX_1                0x00000006
+#define QE_MCC_RESET                    0x00000007
+#define QE_SET_TIMER                    0x00000008
+#define QE_RANDOM_NUMBER                0x0000000c
+#define QE_ATM_MULTI_THREAD_INIT        0x00000011
+#define QE_ASSIGN_PAGE                  0x00000012
+#define QE_ADD_REMOVE_HASH_ENTRY        0x00000013
+#define QE_START_FLOW_CONTROL           0x00000014
+#define QE_STOP_FLOW_CONTROL            0x00000015
+#define QE_ASSIGN_PAGE_TO_DEVICE        0x00000016
+
+#define QE_ASSIGN_RISC                  0x00000010
+#define QE_CR_MCN_NORMAL_SHIFT          6
+#define QE_CR_MCN_USB_SHIFT             4
+#define QE_CR_MCN_RISC_ASSIGN_SHIFT     8
+#define QE_CR_SNUM_SHIFT                17
+
+/* QE CECR Sub Block - sub block of QE command.
+*/
+#define QE_CR_SUBBLOCK_INVALID          0x00000000
+#define QE_CR_SUBBLOCK_USB              0x03200000
+#define QE_CR_SUBBLOCK_UCCFAST1         0x02000000
+#define QE_CR_SUBBLOCK_UCCFAST2         0x02200000
+#define QE_CR_SUBBLOCK_UCCFAST3         0x02400000
+#define QE_CR_SUBBLOCK_UCCFAST4         0x02600000
+#define QE_CR_SUBBLOCK_UCCFAST5         0x02800000
+#define QE_CR_SUBBLOCK_UCCFAST6         0x02a00000
+#define QE_CR_SUBBLOCK_UCCFAST7         0x02c00000
+#define QE_CR_SUBBLOCK_UCCFAST8         0x02e00000
+#define QE_CR_SUBBLOCK_UCCSLOW1         0x00000000
+#define QE_CR_SUBBLOCK_UCCSLOW2         0x00200000
+#define QE_CR_SUBBLOCK_UCCSLOW3         0x00400000
+#define QE_CR_SUBBLOCK_UCCSLOW4         0x00600000
+#define QE_CR_SUBBLOCK_UCCSLOW5         0x00800000
+#define QE_CR_SUBBLOCK_UCCSLOW6         0x00a00000
+#define QE_CR_SUBBLOCK_UCCSLOW7         0x00c00000
+#define QE_CR_SUBBLOCK_UCCSLOW8         0x00e00000
+#define QE_CR_SUBBLOCK_MCC1             0x03800000
+#define QE_CR_SUBBLOCK_MCC2             0x03a00000
+#define QE_CR_SUBBLOCK_MCC3             0x03000000
+#define QE_CR_SUBBLOCK_IDMA1            0x02800000
+#define QE_CR_SUBBLOCK_IDMA2            0x02a00000
+#define QE_CR_SUBBLOCK_IDMA3            0x02c00000
+#define QE_CR_SUBBLOCK_IDMA4            0x02e00000
+#define QE_CR_SUBBLOCK_HPAC             0x01e00000
+#define QE_CR_SUBBLOCK_SPI1             0x01400000
+#define QE_CR_SUBBLOCK_SPI2             0x01600000
+#define QE_CR_SUBBLOCK_RAND             0x01c00000
+#define QE_CR_SUBBLOCK_TIMER            0x01e00000
+#define QE_CR_SUBBLOCK_GENERAL          0x03c00000
+
+/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
+#define QE_CR_PROTOCOL_UNSPECIFIED      0x00    /* For all other protocols */
+#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
+#define QE_CR_PROTOCOL_QMC              0x02
+#define QE_CR_PROTOCOL_UART             0x04
+#define QE_CR_PROTOCOL_ATM_POS          0x0A
+#define QE_CR_PROTOCOL_ETHERNET         0x0C
+#define QE_CR_PROTOCOL_L2_SWITCH        0x0D
+
+/* BRG configuration register */
+#define QE_BRGC_ENABLE          0x00010000
+#define QE_BRGC_DIVISOR_SHIFT   1
+#define QE_BRGC_DIVISOR_MAX     0xFFF
+#define QE_BRGC_DIV16           1
+
+/* QE Timers registers */
+#define QE_GTCFR1_PCAS  0x80
+#define QE_GTCFR1_STP2  0x20
+#define QE_GTCFR1_RST2  0x10
+#define QE_GTCFR1_GM2   0x08
+#define QE_GTCFR1_GM1   0x04
+#define QE_GTCFR1_STP1  0x02
+#define QE_GTCFR1_RST1  0x01
+
+/* SDMA registers */
+#define QE_SDSR_BER1    0x02000000
+#define QE_SDSR_BER2    0x01000000
+
+#define QE_SDMR_GLB_1_MSK       0x80000000
+#define QE_SDMR_ADR_SEL         0x20000000
+#define QE_SDMR_BER1_MSK        0x02000000
+#define QE_SDMR_BER2_MSK        0x01000000
+#define QE_SDMR_EB1_MSK         0x00800000
+#define QE_SDMR_ER1_MSK         0x00080000
+#define QE_SDMR_ER2_MSK         0x00040000
+#define QE_SDMR_CEN_MASK        0x0000E000
+#define QE_SDMR_SBER_1          0x00000200
+#define QE_SDMR_SBER_2          0x00000200
+#define QE_SDMR_EB1_PR_MASK     0x000000C0
+#define QE_SDMR_ER1_PR          0x00000008
+
+#define QE_SDMR_CEN_SHIFT       13
+#define QE_SDMR_EB1_PR_SHIFT    6
+
+#define QE_SDTM_MSNUM_SHIFT     24
+
+#define QE_SDEBCR_BA_MASK       0x01FFFFFF
+
+/* Communication Processor */
+#define QE_CP_CERCR_MEE         0x8000  /* Multi-user RAM ECC enable */
+#define QE_CP_CERCR_IEE         0x4000  /* Instruction RAM ECC enable */
+#define QE_CP_CERCR_CIR         0x0800  /* Common instruction RAM */
+
+/* I-RAM */
+#define QE_IRAM_IADD_AIE        0x80000000      /* Auto Increment Enable */
+#define QE_IRAM_IADD_BADDR      0x00080000      /* Base Address */
+
+/* UPC */
+#define UPGCR_PROTOCOL  0x80000000      /* protocol ul2 or pl2 */
+#define UPGCR_TMS       0x40000000      /* Transmit master/slave mode */
+#define UPGCR_RMS       0x20000000      /* Receive master/slave mode */
+#define UPGCR_ADDR      0x10000000      /* Master MPHY Addr multiplexing */
+#define UPGCR_DIAG      0x01000000      /* Diagnostic mode */
+
+/* UCC GUEMR register */
+#define UCC_GUEMR_MODE_MASK_RX  0x02
+#define UCC_GUEMR_MODE_FAST_RX  0x02
+#define UCC_GUEMR_MODE_SLOW_RX  0x00
+#define UCC_GUEMR_MODE_MASK_TX  0x01
+#define UCC_GUEMR_MODE_FAST_TX  0x01
+#define UCC_GUEMR_MODE_SLOW_TX  0x00
+#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
+#define UCC_GUEMR_SET_RESERVED3 0x10    /* Bit 3 in the guemr is reserved but
+                                           must be set 1 */
+
+/* structure representing UCC SLOW parameter RAM */
+struct ucc_slow_pram {
+        __be16 rbase;           /* RX BD base address */
+        __be16 tbase;           /* TX BD base address */
+        u8 rbmr;                /* RX bus mode register (same as CPM's RFCR) */
+        u8 tbmr;                /* TX bus mode register (same as CPM's TFCR) */
+        __be16 mrblr;           /* Rx buffer length */
+        __be32 rstate;          /* Rx internal state */
+        __be32 rptr;            /* Rx internal data pointer */
+        __be16 rbptr;           /* rb BD Pointer */
+        __be16 rcount;          /* Rx internal byte count */
+        __be32 rtemp;           /* Rx temp */
+        __be32 tstate;          /* Tx internal state */
+        __be32 tptr;            /* Tx internal data pointer */
+        __be16 tbptr;           /* Tx BD pointer */
+        __be16 tcount;          /* Tx byte count */
+        __be32 ttemp;           /* Tx temp */
+        __be32 rcrc;            /* temp receive CRC */
+        __be32 tcrc;            /* temp transmit CRC */
+} __attribute__ ((packed));
+
+/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
+#define UCC_SLOW_GUMR_H_SAM_QMC         0x00000000
+#define UCC_SLOW_GUMR_H_SAM_SATM        0x00008000
+#define UCC_SLOW_GUMR_H_REVD            0x00002000
+#define UCC_SLOW_GUMR_H_TRX             0x00001000
+#define UCC_SLOW_GUMR_H_TTX             0x00000800
+#define UCC_SLOW_GUMR_H_CDP             0x00000400
+#define UCC_SLOW_GUMR_H_CTSP            0x00000200
+#define UCC_SLOW_GUMR_H_CDS             0x00000100
+#define UCC_SLOW_GUMR_H_CTSS            0x00000080
+#define UCC_SLOW_GUMR_H_TFL             0x00000040
+#define UCC_SLOW_GUMR_H_RFW             0x00000020
+#define UCC_SLOW_GUMR_H_TXSY            0x00000010
+#define UCC_SLOW_GUMR_H_4SYNC           0x00000004
+#define UCC_SLOW_GUMR_H_8SYNC           0x00000008
+#define UCC_SLOW_GUMR_H_16SYNC          0x0000000c
+#define UCC_SLOW_GUMR_H_RTSM            0x00000002
+#define UCC_SLOW_GUMR_H_RSYN            0x00000001
+
+#define UCC_SLOW_GUMR_L_TCI             0x10000000
+#define UCC_SLOW_GUMR_L_RINV            0x02000000
+#define UCC_SLOW_GUMR_L_TINV            0x01000000
+#define UCC_SLOW_GUMR_L_TEND            0x00040000
+#define UCC_SLOW_GUMR_L_TDCR_MASK       0x00030000
+#define UCC_SLOW_GUMR_L_TDCR_32         0x00030000
+#define UCC_SLOW_GUMR_L_TDCR_16         0x00020000
+#define UCC_SLOW_GUMR_L_TDCR_8          0x00010000
+#define UCC_SLOW_GUMR_L_TDCR_1          0x00000000
+#define UCC_SLOW_GUMR_L_RDCR_MASK       0x0000c000
+#define UCC_SLOW_GUMR_L_RDCR_32         0x0000c000
+#define UCC_SLOW_GUMR_L_RDCR_16         0x00008000
+#define UCC_SLOW_GUMR_L_RDCR_8          0x00004000
+#define UCC_SLOW_GUMR_L_RDCR_1          0x00000000
+#define UCC_SLOW_GUMR_L_RENC_NRZI       0x00000800
+#define UCC_SLOW_GUMR_L_RENC_NRZ        0x00000000
+#define UCC_SLOW_GUMR_L_TENC_NRZI       0x00000100
+#define UCC_SLOW_GUMR_L_TENC_NRZ        0x00000000
+#define UCC_SLOW_GUMR_L_DIAG_MASK       0x000000c0
+#define UCC_SLOW_GUMR_L_DIAG_LE         0x000000c0
+#define UCC_SLOW_GUMR_L_DIAG_ECHO       0x00000080
+#define UCC_SLOW_GUMR_L_DIAG_LOOP       0x00000040
+#define UCC_SLOW_GUMR_L_DIAG_NORM       0x00000000
+#define UCC_SLOW_GUMR_L_ENR             0x00000020
+#define UCC_SLOW_GUMR_L_ENT             0x00000010
+#define UCC_SLOW_GUMR_L_MODE_MASK       0x0000000F
+#define UCC_SLOW_GUMR_L_MODE_BISYNC     0x00000008
+#define UCC_SLOW_GUMR_L_MODE_AHDLC      0x00000006
+#define UCC_SLOW_GUMR_L_MODE_UART       0x00000004
+#define UCC_SLOW_GUMR_L_MODE_QMC        0x00000002
+
+/* General UCC FAST Mode Register */
+#define UCC_FAST_GUMR_TCI       0x20000000
+#define UCC_FAST_GUMR_TRX       0x10000000
+#define UCC_FAST_GUMR_TTX       0x08000000
+#define UCC_FAST_GUMR_CDP       0x04000000
+#define UCC_FAST_GUMR_CTSP      0x02000000
+#define UCC_FAST_GUMR_CDS       0x01000000
+#define UCC_FAST_GUMR_CTSS      0x00800000
+#define UCC_FAST_GUMR_TXSY      0x00020000
+#define UCC_FAST_GUMR_RSYN      0x00010000
+#define UCC_FAST_GUMR_RTSM      0x00002000
+#define UCC_FAST_GUMR_REVD      0x00000400
+#define UCC_FAST_GUMR_ENR       0x00000020
+#define UCC_FAST_GUMR_ENT       0x00000010
+
+/* UART Slow UCC Event Register (UCCE) */
+#define UCC_UART_UCCE_AB        0x0200
+#define UCC_UART_UCCE_IDLE      0x0100
+#define UCC_UART_UCCE_GRA       0x0080
+#define UCC_UART_UCCE_BRKE      0x0040
+#define UCC_UART_UCCE_BRKS      0x0020
+#define UCC_UART_UCCE_CCR       0x0008
+#define UCC_UART_UCCE_BSY       0x0004
+#define UCC_UART_UCCE_TX        0x0002
+#define UCC_UART_UCCE_RX        0x0001
+
+/* HDLC Slow UCC Event Register (UCCE) */
+#define UCC_HDLC_UCCE_GLR       0x1000
+#define UCC_HDLC_UCCE_GLT       0x0800
+#define UCC_HDLC_UCCE_IDLE      0x0100
+#define UCC_HDLC_UCCE_BRKE      0x0040
+#define UCC_HDLC_UCCE_BRKS      0x0020
+#define UCC_HDLC_UCCE_TXE       0x0010
+#define UCC_HDLC_UCCE_RXF       0x0008
+#define UCC_HDLC_UCCE_BSY       0x0004
+#define UCC_HDLC_UCCE_TXB       0x0002
+#define UCC_HDLC_UCCE_RXB       0x0001
+
+/* BISYNC Slow UCC Event Register (UCCE) */
+#define UCC_BISYNC_UCCE_GRA     0x0080
+#define UCC_BISYNC_UCCE_TXE     0x0010
+#define UCC_BISYNC_UCCE_RCH     0x0008
+#define UCC_BISYNC_UCCE_BSY     0x0004
+#define UCC_BISYNC_UCCE_TXB     0x0002
+#define UCC_BISYNC_UCCE_RXB     0x0001
+
+/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
+#define UCC_GETH_UCCE_MPD       0x80000000
+#define UCC_GETH_UCCE_SCAR      0x40000000
+#define UCC_GETH_UCCE_GRA       0x20000000
+#define UCC_GETH_UCCE_CBPR      0x10000000
+#define UCC_GETH_UCCE_BSY       0x08000000
+#define UCC_GETH_UCCE_RXC       0x04000000
+#define UCC_GETH_UCCE_TXC       0x02000000
+#define UCC_GETH_UCCE_TXE       0x01000000
+#define UCC_GETH_UCCE_TXB7      0x00800000
+#define UCC_GETH_UCCE_TXB6      0x00400000
+#define UCC_GETH_UCCE_TXB5      0x00200000
+#define UCC_GETH_UCCE_TXB4      0x00100000
+#define UCC_GETH_UCCE_TXB3      0x00080000
+#define UCC_GETH_UCCE_TXB2      0x00040000
+#define UCC_GETH_UCCE_TXB1      0x00020000
+#define UCC_GETH_UCCE_TXB0      0x00010000
+#define UCC_GETH_UCCE_RXB7      0x00008000
+#define UCC_GETH_UCCE_RXB6      0x00004000
+#define UCC_GETH_UCCE_RXB5      0x00002000
+#define UCC_GETH_UCCE_RXB4      0x00001000
+#define UCC_GETH_UCCE_RXB3      0x00000800
+#define UCC_GETH_UCCE_RXB2      0x00000400
+#define UCC_GETH_UCCE_RXB1      0x00000200
+#define UCC_GETH_UCCE_RXB0      0x00000100
+#define UCC_GETH_UCCE_RXF7      0x00000080
+#define UCC_GETH_UCCE_RXF6      0x00000040
+#define UCC_GETH_UCCE_RXF5      0x00000020
+#define UCC_GETH_UCCE_RXF4      0x00000010
+#define UCC_GETH_UCCE_RXF3      0x00000008
+#define UCC_GETH_UCCE_RXF2      0x00000004
+#define UCC_GETH_UCCE_RXF1      0x00000002
+#define UCC_GETH_UCCE_RXF0      0x00000001
+
+/* UPSMR, when used as a UART */
+#define UCC_UART_UPSMR_FLC              0x8000
+#define UCC_UART_UPSMR_SL               0x4000
+#define UCC_UART_UPSMR_CL_MASK          0x3000
+#define UCC_UART_UPSMR_CL_8             0x3000
+#define UCC_UART_UPSMR_CL_7             0x2000
+#define UCC_UART_UPSMR_CL_6             0x1000
+#define UCC_UART_UPSMR_CL_5             0x0000
+#define UCC_UART_UPSMR_UM_MASK          0x0c00
+#define UCC_UART_UPSMR_UM_NORMAL        0x0000
+#define UCC_UART_UPSMR_UM_MAN_MULTI     0x0400
+#define UCC_UART_UPSMR_UM_AUTO_MULTI    0x0c00
+#define UCC_UART_UPSMR_FRZ              0x0200
+#define UCC_UART_UPSMR_RZS              0x0100
+#define UCC_UART_UPSMR_SYN              0x0080
+#define UCC_UART_UPSMR_DRT              0x0040
+#define UCC_UART_UPSMR_PEN              0x0010
+#define UCC_UART_UPSMR_RPM_MASK         0x000c
+#define UCC_UART_UPSMR_RPM_ODD          0x0000
+#define UCC_UART_UPSMR_RPM_LOW          0x0004
+#define UCC_UART_UPSMR_RPM_EVEN         0x0008
+#define UCC_UART_UPSMR_RPM_HIGH         0x000C
+#define UCC_UART_UPSMR_TPM_MASK         0x0003
+#define UCC_UART_UPSMR_TPM_ODD          0x0000
+#define UCC_UART_UPSMR_TPM_LOW          0x0001
+#define UCC_UART_UPSMR_TPM_EVEN         0x0002
+#define UCC_UART_UPSMR_TPM_HIGH         0x0003
+
+/* UCC Transmit On Demand Register (UTODR) */
+#define UCC_SLOW_TOD    0x8000
+#define UCC_FAST_TOD    0x8000
+
+/* UCC Bus Mode Register masks */
+/* Not to be confused with the Bundle Mode Register */
+#define UCC_BMR_GBL             0x20
+#define UCC_BMR_BO_BE           0x10
+#define UCC_BMR_CETM            0x04
+#define UCC_BMR_DTB             0x02
+#define UCC_BMR_BDB             0x01
+
+/* Function code masks */
+#define FC_GBL                          0x20
+#define FC_DTB_LCL                      0x02
+#define UCC_FAST_FUNCTION_CODE_GBL      0x20
+#define UCC_FAST_FUNCTION_CODE_DTB_LCL  0x02
+#define UCC_FAST_FUNCTION_CODE_BDB_LCL  0x01
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_QE_H */
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h
new file mode 100644
index 000000000000..56a7745ca343
--- /dev/null
+++ b/arch/powerpc/include/asm/qe_ic.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:     Shlomi Gridish <gridish@freescale.com>
+ *              Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * QE IC external definitions and structure.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_POWERPC_QE_IC_H
+#define _ASM_POWERPC_QE_IC_H
+
+#include <linux/irq.h>
+
+#define NUM_OF_QE_IC_GROUPS     6
+
+/* Flags when we init the QE IC */
+#define QE_IC_SPREADMODE_GRP_W                  0x00000001
+#define QE_IC_SPREADMODE_GRP_X                  0x00000002
+#define QE_IC_SPREADMODE_GRP_Y                  0x00000004
+#define QE_IC_SPREADMODE_GRP_Z                  0x00000008
+#define QE_IC_SPREADMODE_GRP_RISCA              0x00000010
+#define QE_IC_SPREADMODE_GRP_RISCB              0x00000020
+
+#define QE_IC_LOW_SIGNAL                        0x00000100
+#define QE_IC_HIGH_SIGNAL                       0x00000200
+
+#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH       0x00001000
+#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH       0x00002000
+#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH       0x00004000
+#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH       0x00008000
+#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH       0x00010000
+#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH       0x00020000
+#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH       0x00040000
+#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH       0x00080000
+#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH   0x00100000
+#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH   0x00200000
+#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH   0x00400000
+#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH   0x00800000
+#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT           (12)
+
+/* QE interrupt sources groups */
+enum qe_ic_grp_id {
+        QE_IC_GRP_W = 0,        /* QE interrupt controller group W */
+        QE_IC_GRP_X,            /* QE interrupt controller group X */
+        QE_IC_GRP_Y,            /* QE interrupt controller group Y */
+        QE_IC_GRP_Z,            /* QE interrupt controller group Z */
+        QE_IC_GRP_RISCA,        /* QE interrupt controller RISC group A */
+        QE_IC_GRP_RISCB         /* QE interrupt controller RISC group B */
+};
+
+void qe_ic_init(struct device_node *node, unsigned int flags,
+                void (*low_handler)(unsigned int irq, struct irq_desc *desc),
+                void (*high_handler)(unsigned int irq, struct irq_desc *desc));
+void qe_ic_set_highest_priority(unsigned int virq, int high);
+int qe_ic_set_priority(unsigned int virq, unsigned int priority);
+int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
+
+struct qe_ic;
+unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
+unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
+
+static inline void qe_ic_cascade_low_ipic(unsigned int irq,
+                                          struct irq_desc *desc)
+{
+        struct qe_ic *qe_ic = desc->handler_data;
+        unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+        if (cascade_irq != NO_IRQ)
+                generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_high_ipic(unsigned int irq,
+                                           struct irq_desc *desc)
+{
+        struct qe_ic *qe_ic = desc->handler_data;
+        unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+        if (cascade_irq != NO_IRQ)
+                generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_low_mpic(unsigned int irq,
+                                          struct irq_desc *desc)
+{
+        struct qe_ic *qe_ic = desc->handler_data;
+        unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+        if (cascade_irq != NO_IRQ)
+                generic_handle_irq(cascade_irq);
+
+        desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_high_mpic(unsigned int irq,
+                                           struct irq_desc *desc)
+{
+        struct qe_ic *qe_ic = desc->handler_data;
+        unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+        if (cascade_irq != NO_IRQ)
+                generic_handle_irq(cascade_irq);
+
+        desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
+                                            struct irq_desc *desc)
+{
+        struct qe_ic *qe_ic = desc->handler_data;
+        unsigned int cascade_irq;
+
+        cascade_irq = qe_ic_get_high_irq(qe_ic);
+        if (cascade_irq == NO_IRQ)
+                cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+        if (cascade_irq != NO_IRQ)
+                generic_handle_irq(cascade_irq);
+
+        desc->chip->eoi(irq);
+}
+
+#endif /* _ASM_POWERPC_QE_IC_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
new file mode 100644
index 000000000000..c6d1ab650778
--- /dev/null
+++ b/arch/powerpc/include/asm/reg.h
@@ -0,0 +1,788 @@
+/*
+ * Contains the definition of registers common to all PowerPC variants.
+ * If a register definition has been changed in a different PowerPC
+ * variant, we will case it in #ifndef XXX ... #endif, and have the
+ * number used in the Programming Environments Manual For 32-Bit
+ * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
+ */
+
+#ifndef _ASM_POWERPC_REG_H
+#define _ASM_POWERPC_REG_H
+#ifdef __KERNEL__
+
+#include <linux/stringify.h>
+#include <asm/cputable.h>
+
+/* Pickup Book E specific registers. */
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+#include <asm/reg_booke.h>
+#endif /* CONFIG_BOOKE || CONFIG_40x */
+
+#ifdef CONFIG_FSL_EMB_PERFMON
+#include <asm/reg_fsl_emb.h>
+#endif
+
+#ifdef CONFIG_8xx
+#include <asm/reg_8xx.h>
+#endif /* CONFIG_8xx */
+
+#define MSR_SF_LG       63              /* Enable 64 bit mode */
+#define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
+#define MSR_HV_LG       60              /* Hypervisor state */
+#define MSR_VEC_LG      25              /* Enable AltiVec */
+#define MSR_VSX_LG      23              /* Enable VSX */
+#define MSR_POW_LG      18              /* Enable Power Management */
+#define MSR_WE_LG       18              /* Wait State Enable */
+#define MSR_TGPR_LG     17              /* TLB Update registers in use */
+#define MSR_CE_LG       17              /* Critical Interrupt Enable */
+#define MSR_ILE_LG      16              /* Interrupt Little Endian */
+#define MSR_EE_LG       15              /* External Interrupt Enable */
+#define MSR_PR_LG       14              /* Problem State / Privilege Level */
+#define MSR_FP_LG       13              /* Floating Point enable */
+#define MSR_ME_LG       12              /* Machine Check Enable */
+#define MSR_FE0_LG      11              /* Floating Exception mode 0 */
+#define MSR_SE_LG       10              /* Single Step */
+#define MSR_BE_LG       9               /* Branch Trace */
+#define MSR_DE_LG       9               /* Debug Exception Enable */
+#define MSR_FE1_LG      8               /* Floating Exception mode 1 */
+#define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
+#define MSR_IR_LG       5               /* Instruction Relocate */
+#define MSR_DR_LG       4               /* Data Relocate */
+#define MSR_PE_LG       3               /* Protection Enable */
+#define MSR_PX_LG       2               /* Protection Exclusive Mode */
+#define MSR_PMM_LG      2               /* Performance monitor */
+#define MSR_RI_LG       1               /* Recoverable Exception */
+#define MSR_LE_LG       0               /* Little Endian */
+
+#ifdef __ASSEMBLY__
+#define __MASK(X)       (1<<(X))
+#else
+#define __MASK(X)       (1UL<<(X))
+#endif
+
+#ifdef CONFIG_PPC64
+#define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
+#define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
+#define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
+#else
+/* so tests for these bits fail on 32-bit */
+#define MSR_SF          0
+#define MSR_ISF         0
+#define MSR_HV          0
+#endif
+
+#define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
+#define MSR_VSX         __MASK(MSR_VSX_LG)      /* Enable VSX */
+#define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
+#define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
+#define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
+#define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
+#define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
+#define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
+#define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
+#define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
+#define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
+#define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
+#define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
+#define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
+#define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
+#define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
+#define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
+#define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
+#define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
+#define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
+#define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
+#ifndef MSR_PMM
+#define MSR_PMM         __MASK(MSR_PMM_LG)      /* Performance monitor */
+#endif
+#define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
+#define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
+
+#ifdef CONFIG_PPC64
+#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
+#define MSR_KERNEL      MSR_ | MSR_SF
+
+#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
+#define MSR_USER64      MSR_USER32 | MSR_SF
+
+#else /* 32-bit */
+/* Default MSR for kernel mode. */
+#ifndef MSR_KERNEL      /* reg_booke.h also defines this */
+#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
+#endif
+
+#define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
+#endif
+
+/* Floating Point Status and Control Register (FPSCR) Fields */
+#define FPSCR_FX        0x80000000      /* FPU exception summary */
+#define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
+#define FPSCR_VX        0x20000000      /* Invalid operation summary */
+#define FPSCR_OX        0x10000000      /* Overflow exception summary */
+#define FPSCR_UX        0x08000000      /* Underflow exception summary */
+#define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
+#define FPSCR_XX        0x02000000      /* Inexact exception summary */
+#define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
+#define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
+#define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
+#define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
+#define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
+#define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
+#define FPSCR_FR        0x00040000      /* Fraction rounded */
+#define FPSCR_FI        0x00020000      /* Fraction inexact */
+#define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
+#define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
+#define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
+#define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
+#define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
+#define FPSCR_VE        0x00000080      /* Invalid op exception enable */
+#define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
+#define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
+#define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
+#define FPSCR_XE        0x00000008      /* FP inexact exception enable */
+#define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
+#define FPSCR_RN        0x00000003      /* FPU rounding control */
+
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_CTR        0x009   /* Count Register */
+#define SPRN_DSCR       0x11
+#define SPRN_CTRLF      0x088
+#define SPRN_CTRLT      0x098
+#define   CTRL_CT       0xc0000000      /* current thread */
+#define   CTRL_CT0      0x80000000      /* thread 0 */
+#define   CTRL_CT1      0x40000000      /* thread 1 */
+#define   CTRL_TE       0x00c00000      /* thread enable */
+#define   CTRL_RUNLATCH 0x1
+#define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
+#define   DABR_TRANSLATION      (1UL << 2)
+#define SPRN_DABR2      0x13D   /* e300 */
+#define SPRN_DABRX      0x3F7   /* Data Address Breakpoint Register Extension */
+#define   DABRX_USER    (1UL << 0)
+#define   DABRX_KERNEL  (1UL << 1)
+#define SPRN_DAR        0x013   /* Data Address Register */
+#define SPRN_DBCR       0x136   /* e300 Data Breakpoint Control Reg */
+#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
+#define   DSISR_NOHPTE          0x40000000      /* no translation found */
+#define   DSISR_PROTFAULT       0x08000000      /* protection fault */
+#define   DSISR_ISSTORE         0x02000000      /* access was a store */
+#define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
+#define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
+#define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
+#define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
+#define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
+#define SPRN_TBWU       0x11D   /* Time Base Upper Register (super, R/W) */
+#define SPRN_SPURR      0x134   /* Scaled PURR */
+#define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
+#define SPRN_LPCR       0x13E   /* LPAR Control Register */
+#define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
+#define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
+#define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
+#define SPRN_DBAT1U     0x21A   /* Data BAT 1 Upper Register */
+#define SPRN_DBAT2L     0x21D   /* Data BAT 2 Lower Register */
+#define SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
+#define SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
+#define SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
+#define SPRN_DBAT4L     0x239   /* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U     0x238   /* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L     0x23B   /* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U     0x23A   /* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L     0x23D   /* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U     0x23C   /* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L     0x23F   /* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U     0x23E   /* Data BAT 7 Upper Register */
+
+#define SPRN_DEC        0x016           /* Decrement Register */
+#define SPRN_DER        0x095           /* Debug Enable Regsiter */
+#define DER_RSTE        0x40000000      /* Reset Interrupt */
+#define DER_CHSTPE      0x20000000      /* Check Stop */
+#define DER_MCIE        0x10000000      /* Machine Check Interrupt */
+#define DER_EXTIE       0x02000000      /* External Interrupt */
+#define DER_ALIE        0x01000000      /* Alignment Interrupt */
+#define DER_PRIE        0x00800000      /* Program Interrupt */
+#define DER_FPUVIE      0x00400000      /* FP Unavailable Interrupt */
+#define DER_DECIE       0x00200000      /* Decrementer Interrupt */
+#define DER_SYSIE       0x00040000      /* System Call Interrupt */
+#define DER_TRE         0x00020000      /* Trace Interrupt */
+#define DER_SEIE        0x00004000      /* FP SW Emulation Interrupt */
+#define DER_ITLBMSE     0x00002000      /* Imp. Spec. Instruction TLB Miss */
+#define DER_ITLBERE     0x00001000      /* Imp. Spec. Instruction TLB Error */
+#define DER_DTLBMSE     0x00000800      /* Imp. Spec. Data TLB Miss */
+#define DER_DTLBERE     0x00000400      /* Imp. Spec. Data TLB Error */
+#define DER_LBRKE       0x00000008      /* Load/Store Breakpoint Interrupt */
+#define DER_IBRKE       0x00000004      /* Instruction Breakpoint Interrupt */
+#define DER_EBRKE       0x00000002      /* External Breakpoint Interrupt */
+#define DER_DPIE        0x00000001      /* Dev. Port Nonmaskable Request */
+#define SPRN_DMISS      0x3D0           /* Data TLB Miss Register */
+#define SPRN_EAR        0x11A           /* External Address Register */
+#define SPRN_HASH1      0x3D2           /* Primary Hash Address Register */
+#define SPRN_HASH2      0x3D3           /* Secondary Hash Address Resgister */
+#define SPRN_HID0       0x3F0           /* Hardware Implementation Register 0 */
+#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
+#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
+#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
+#define HID0_SBCLK      (1<<27)
+#define HID0_EICE       (1<<26)
+#define HID0_TBEN       (1<<26)         /* Timebase enable - 745x */
+#define HID0_ECLK       (1<<25)
+#define HID0_PAR        (1<<24)
+#define HID0_STEN       (1<<24)         /* Software table search enable - 745x */
+#define HID0_HIGH_BAT   (1<<23)         /* Enable high BATs - 7455 */
+#define HID0_DOZE       (1<<23)
+#define HID0_NAP        (1<<22)
+#define HID0_SLEEP      (1<<21)
+#define HID0_DPM        (1<<20)
+#define HID0_BHTCLR     (1<<18)         /* Clear branch history table - 7450 */
+#define HID0_XAEN       (1<<17)         /* Extended addressing enable - 7450 */
+#define HID0_NHR        (1<<16)         /* Not hard reset (software bit-7450)*/
+#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
+#define HID0_DCE        (1<<14)         /* Data Cache Enable */
+#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
+#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
+#define HID0_ICFI       (1<<11)         /* Instr. Cache Flash Invalidate */
+#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
+#define HID0_SPD        (1<<9)          /* Speculative disable */
+#define HID0_DAPUEN     (1<<8)          /* Debug APU enable */
+#define HID0_SGE        (1<<7)          /* Store Gathering Enable */
+#define HID0_SIED       (1<<7)          /* Serial Instr. Execution [Disable] */
+#define HID0_DCFA       (1<<6)          /* Data Cache Flush Assist */
+#define HID0_LRSTK      (1<<4)          /* Link register stack - 745x */
+#define HID0_BTIC       (1<<5)          /* Branch Target Instr Cache Enable */
+#define HID0_ABE        (1<<3)          /* Address Broadcast Enable */
+#define HID0_FOLD       (1<<3)          /* Branch Folding enable - 745x */
+#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
+#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
+#define HID0_NOPDST     (1<<1)          /* No-op dst, dstt, etc. instr. */
+#define HID0_NOPTI      (1<<0)          /* No-op dcbt and dcbst instr. */
+
+#define SPRN_HID1       0x3F1           /* Hardware Implementation Register 1 */
+#define HID1_EMCP       (1<<31)         /* 7450 Machine Check Pin Enable */
+#define HID1_DFS        (1<<22)         /* 7447A Dynamic Frequency Scaling */
+#define HID1_PC0        (1<<16)         /* 7450 PLL_CFG[0] */
+#define HID1_PC1        (1<<15)         /* 7450 PLL_CFG[1] */
+#define HID1_PC2        (1<<14)         /* 7450 PLL_CFG[2] */
+#define HID1_PC3        (1<<13)         /* 7450 PLL_CFG[3] */
+#define HID1_SYNCBE     (1<<11)         /* 7450 ABE for sync, eieio */
+#define HID1_ABE        (1<<10)         /* 7450 Address Broadcast Enable */
+#define HID1_PS         (1<<16)         /* 750FX PLL selection */
+#define SPRN_HID2       0x3F8           /* Hardware Implementation Register 2 */
+#define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
+#define SPRN_IABR2      0x3FA           /* 83xx */
+#define SPRN_IBCR       0x135           /* 83xx Insn Breakpoint Control Reg */
+#define SPRN_HID4       0x3F4           /* 970 HID4 */
+#define SPRN_HID5       0x3F6           /* 970 HID5 */
+#define SPRN_HID6       0x3F9   /* BE HID 6 */
+#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
+#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
+#define SPRN_TSC_CELL   0x399   /* Thread switch control on Cell */
+#define   TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
+#define   TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
+#define   TSC_CELL_EE_ENABLE    0x100000 /* External Interrupt */
+#define   TSC_CELL_EE_BOOST     0x080000 /* External Interrupt Boost */
+#define SPRN_TSC        0x3FD   /* Thread switch control on others */
+#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
+#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
+#define SPRN_IAC1       0x3F4           /* Instruction Address Compare 1 */
+#define SPRN_IAC2       0x3F5           /* Instruction Address Compare 2 */
+#endif
+#define SPRN_IBAT0L     0x211           /* Instruction BAT 0 Lower Register */
+#define SPRN_IBAT0U     0x210           /* Instruction BAT 0 Upper Register */
+#define SPRN_IBAT1L     0x213           /* Instruction BAT 1 Lower Register */
+#define SPRN_IBAT1U     0x212           /* Instruction BAT 1 Upper Register */
+#define SPRN_IBAT2L     0x215           /* Instruction BAT 2 Lower Register */
+#define SPRN_IBAT2U     0x214           /* Instruction BAT 2 Upper Register */
+#define SPRN_IBAT3L     0x217           /* Instruction BAT 3 Lower Register */
+#define SPRN_IBAT3U     0x216           /* Instruction BAT 3 Upper Register */
+#define SPRN_IBAT4L     0x231           /* Instruction BAT 4 Lower Register */
+#define SPRN_IBAT4U     0x230           /* Instruction BAT 4 Upper Register */
+#define SPRN_IBAT5L     0x233           /* Instruction BAT 5 Lower Register */
+#define SPRN_IBAT5U     0x232           /* Instruction BAT 5 Upper Register */
+#define SPRN_IBAT6L     0x235           /* Instruction BAT 6 Lower Register */
+#define SPRN_IBAT6U     0x234           /* Instruction BAT 6 Upper Register */
+#define SPRN_IBAT7L     0x237           /* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT7U     0x236           /* Instruction BAT 7 Upper Register */
+#define SPRN_ICMP       0x3D5           /* Instruction TLB Compare Register */
+#define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
+#define SPRN_ICTRL      0x3F3   /* 1011 7450 icache and interrupt ctrl */
+#define ICTRL_EICE      0x08000000      /* enable icache parity errs */
+#define ICTRL_EDC       0x04000000      /* enable dcache parity errs */
+#define ICTRL_EICP      0x00000100      /* enable icache par. check */
+#define SPRN_IMISS      0x3D4           /* Instruction TLB Miss Register */
+#define SPRN_IMMR       0x27E           /* Internal Memory Map Register */
+#define SPRN_L2CR       0x3F9           /* Level 2 Cache Control Regsiter */
+#define SPRN_L2CR2      0x3f8
+#define L2CR_L2E                0x80000000      /* L2 enable */
+#define L2CR_L2PE               0x40000000      /* L2 parity enable */
+#define L2CR_L2SIZ_MASK         0x30000000      /* L2 size mask */
+#define L2CR_L2SIZ_256KB        0x10000000      /* L2 size 256KB */
+#define L2CR_L2SIZ_512KB        0x20000000      /* L2 size 512KB */
+#define L2CR_L2SIZ_1MB          0x30000000      /* L2 size 1MB */
+#define L2CR_L2CLK_MASK         0x0e000000      /* L2 clock mask */
+#define L2CR_L2CLK_DISABLED     0x00000000      /* L2 clock disabled */
+#define L2CR_L2CLK_DIV1         0x02000000      /* L2 clock / 1 */
+#define L2CR_L2CLK_DIV1_5       0x04000000      /* L2 clock / 1.5 */
+#define L2CR_L2CLK_DIV2         0x08000000      /* L2 clock / 2 */
+#define L2CR_L2CLK_DIV2_5       0x0a000000      /* L2 clock / 2.5 */
+#define L2CR_L2CLK_DIV3         0x0c000000      /* L2 clock / 3 */
+#define L2CR_L2RAM_MASK         0x01800000      /* L2 RAM type mask */
+#define L2CR_L2RAM_FLOW         0x00000000      /* L2 RAM flow through */
+#define L2CR_L2RAM_PIPE         0x01000000      /* L2 RAM pipelined */
+#define L2CR_L2RAM_PIPE_LW      0x01800000      /* L2 RAM pipelined latewr */
+#define L2CR_L2DO               0x00400000      /* L2 data only */
+#define L2CR_L2I                0x00200000      /* L2 global invalidate */
+#define L2CR_L2CTL              0x00100000      /* L2 RAM control */
+#define L2CR_L2WT               0x00080000      /* L2 write-through */
+#define L2CR_L2TS               0x00040000      /* L2 test support */
+#define L2CR_L2OH_MASK          0x00030000      /* L2 output hold mask */
+#define L2CR_L2OH_0_5           0x00000000      /* L2 output hold 0.5 ns */
+#define L2CR_L2OH_1_0           0x00010000      /* L2 output hold 1.0 ns */
+#define L2CR_L2SL               0x00008000      /* L2 DLL slow */
+#define L2CR_L2DF               0x00004000      /* L2 differential clock */
+#define L2CR_L2BYP              0x00002000      /* L2 DLL bypass */
+#define L2CR_L2IP               0x00000001      /* L2 GI in progress */
+#define L2CR_L2IO_745x          0x00100000      /* L2 instr. only (745x) */
+#define L2CR_L2DO_745x          0x00010000      /* L2 data only (745x) */
+#define L2CR_L2REP_745x         0x00001000      /* L2 repl. algorithm (745x) */
+#define L2CR_L2HWF_745x         0x00000800      /* L2 hardware flush (745x) */
+#define SPRN_L3CR               0x3FA   /* Level 3 Cache Control Regsiter */
+#define L3CR_L3E                0x80000000      /* L3 enable */
+#define L3CR_L3PE               0x40000000      /* L3 data parity enable */
+#define L3CR_L3APE              0x20000000      /* L3 addr parity enable */
+#define L3CR_L3SIZ              0x10000000      /* L3 size */
+#define L3CR_L3CLKEN            0x08000000      /* L3 clock enable */
+#define L3CR_L3RES              0x04000000      /* L3 special reserved bit */
+#define L3CR_L3CLKDIV           0x03800000      /* L3 clock divisor */
+#define L3CR_L3IO               0x00400000      /* L3 instruction only */
+#define L3CR_L3SPO              0x00040000      /* L3 sample point override */
+#define L3CR_L3CKSP             0x00030000      /* L3 clock sample point */
+#define L3CR_L3PSP              0x0000e000      /* L3 P-clock sample point */
+#define L3CR_L3REP              0x00001000      /* L3 replacement algorithm */
+#define L3CR_L3HWF              0x00000800      /* L3 hardware flush */
+#define L3CR_L3I                0x00000400      /* L3 global invalidate */
+#define L3CR_L3RT               0x00000300      /* L3 SRAM type */
+#define L3CR_L3NIRCA            0x00000080      /* L3 non-integer ratio clock adj. */
+#define L3CR_L3DO               0x00000040      /* L3 data only mode */
+#define L3CR_PMEN               0x00000004      /* L3 private memory enable */
+#define L3CR_PMSIZ              0x00000001      /* L3 private memory size */
+
+#define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
+#define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
+#define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
+#define SPRN_LDSTDB     0x3f4   /* */
+#define SPRN_LR         0x008   /* Link Register */
+#ifndef SPRN_PIR
+#define SPRN_PIR        0x3FF   /* Processor Identification Register */
+#endif
+#define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
+#define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
+#define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
+#define SPRN_PVR        0x11F   /* Processor Version Register */
+#define SPRN_RPA        0x3D6   /* Required Physical Address Register */
+#define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
+#define SPRN_SDR1       0x019   /* MMU Hash Base Register */
+#define SPRN_ASR        0x118   /* Address Space Register */
+#define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
+#define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
+#define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
+#define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
+#define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
+#define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 */
+#define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 */
+#define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 */
+#define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
+#define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
+#define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
+#define   SRR1_WAKEMASK         0x00380000 /* reason for wakeup */
+#define   SRR1_WAKERESET        0x00380000 /* System reset */
+#define   SRR1_WAKESYSERR       0x00300000 /* System error */
+#define   SRR1_WAKEEE           0x00200000 /* External interrupt */
+#define   SRR1_WAKEMT           0x00280000 /* mtctrl */
+#define   SRR1_WAKEDEC          0x00180000 /* Decrementer interrupt */
+#define   SRR1_WAKETHERM        0x00100000 /* Thermal management interrupt */
+#define SPRN_HSRR0      0x13A   /* Save/Restore Register 0 */
+#define SPRN_HSRR1      0x13B   /* Save/Restore Register 1 */
+
+#define SPRN_TBCTL      0x35f   /* PA6T Timebase control register */
+#define   TBCTL_FREEZE          0x0000000000000000ull /* Freeze all tbs */
+#define   TBCTL_RESTART         0x0000000100000000ull /* Restart all tbs */
+#define   TBCTL_UPDATE_UPPER    0x0000000200000000ull /* Set upper 32 bits */
+#define   TBCTL_UPDATE_LOWER    0x0000000300000000ull /* Set lower 32 bits */
+
+#ifndef SPRN_SVR
+#define SPRN_SVR        0x11E   /* System Version Register */
+#endif
+#define SPRN_THRM1      0x3FC           /* Thermal Management Register 1 */
+/* these bits were defined in inverted endian sense originally, ugh, confusing */
+#define THRM1_TIN       (1 << 31)
+#define THRM1_TIV       (1 << 30)
+#define THRM1_THRES(x)  ((x&0x7f)<<23)
+#define THRM3_SITV(x)   ((x&0x3fff)<<1)
+#define THRM1_TID       (1<<2)
+#define THRM1_TIE       (1<<1)
+#define THRM1_V         (1<<0)
+#define SPRN_THRM2      0x3FD           /* Thermal Management Register 2 */
+#define SPRN_THRM3      0x3FE           /* Thermal Management Register 3 */
+#define THRM3_E         (1<<0)
+#define SPRN_TLBMISS    0x3D4           /* 980 7450 TLB Miss Register */
+#define SPRN_UMMCR0     0x3A8   /* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1     0x3AC   /* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1      0x3A9   /* User Performance Counter Register 1 */
+#define SPRN_UPMC2      0x3AA   /* User Performance Counter Register 2 */
+#define SPRN_UPMC3      0x3AD   /* User Performance Counter Register 3 */
+#define SPRN_UPMC4      0x3AE   /* User Performance Counter Register 4 */
+#define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
+#define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
+#define SPRN_XER        0x001   /* Fixed Point Exception Register */
+
+#define SPRN_SCOMC      0x114   /* SCOM Access Control */
+#define SPRN_SCOMD      0x115   /* SCOM Access DATA */
+
+/* Performance monitor SPRs */
+#ifdef CONFIG_PPC64
+#define SPRN_MMCR0      795
+#define   MMCR0_FC      0x80000000UL /* freeze counters */
+#define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
+#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
+#define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
+#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
+#define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
+#define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
+#define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
+#define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
+#define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
+#define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
+#define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
+#define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+#define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
+#define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
+#define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
+#define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
+#define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
+#define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
+#define SPRN_MMCR1      798
+#define SPRN_MMCRA      0x312
+#define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
+#define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
+#define   MMCRA_SLOT    0x07000000UL /* SLOT bits (37-39) */
+#define   MMCRA_SLOT_SHIFT      24
+#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
+#define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
+#define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
+#define   POWER6_MMCRA_THRM     0x00000020UL
+#define   POWER6_MMCRA_OTHER    0x0000000EUL
+#define SPRN_PMC1       787
+#define SPRN_PMC2       788
+#define SPRN_PMC3       789
+#define SPRN_PMC4       790
+#define SPRN_PMC5       791
+#define SPRN_PMC6       792
+#define SPRN_PMC7       793
+#define SPRN_PMC8       794
+#define SPRN_SIAR       780
+#define SPRN_SDAR       781
+
+#define SPRN_PA6T_MMCR0 795
+#define   PA6T_MMCR0_EN0        0x0000000000000001UL
+#define   PA6T_MMCR0_EN1        0x0000000000000002UL
+#define   PA6T_MMCR0_EN2        0x0000000000000004UL
+#define   PA6T_MMCR0_EN3        0x0000000000000008UL
+#define   PA6T_MMCR0_EN4        0x0000000000000010UL
+#define   PA6T_MMCR0_EN5        0x0000000000000020UL
+#define   PA6T_MMCR0_SUPEN      0x0000000000000040UL
+#define   PA6T_MMCR0_PREN       0x0000000000000080UL
+#define   PA6T_MMCR0_HYPEN      0x0000000000000100UL
+#define   PA6T_MMCR0_FCM0       0x0000000000000200UL
+#define   PA6T_MMCR0_FCM1       0x0000000000000400UL
+#define   PA6T_MMCR0_INTGEN     0x0000000000000800UL
+#define   PA6T_MMCR0_INTEN0     0x0000000000001000UL
+#define   PA6T_MMCR0_INTEN1     0x0000000000002000UL
+#define   PA6T_MMCR0_INTEN2     0x0000000000004000UL
+#define   PA6T_MMCR0_INTEN3     0x0000000000008000UL
+#define   PA6T_MMCR0_INTEN4     0x0000000000010000UL
+#define   PA6T_MMCR0_INTEN5     0x0000000000020000UL
+#define   PA6T_MMCR0_DISCNT     0x0000000000040000UL
+#define   PA6T_MMCR0_UOP        0x0000000000080000UL
+#define   PA6T_MMCR0_TRG        0x0000000000100000UL
+#define   PA6T_MMCR0_TRGEN      0x0000000000200000UL
+#define   PA6T_MMCR0_TRGREG     0x0000000001600000UL
+#define   PA6T_MMCR0_SIARLOG    0x0000000002000000UL
+#define   PA6T_MMCR0_SDARLOG    0x0000000004000000UL
+#define   PA6T_MMCR0_PROEN      0x0000000008000000UL
+#define   PA6T_MMCR0_PROLOG     0x0000000010000000UL
+#define   PA6T_MMCR0_DAMEN2     0x0000000020000000UL
+#define   PA6T_MMCR0_DAMEN3     0x0000000040000000UL
+#define   PA6T_MMCR0_DAMEN4     0x0000000080000000UL
+#define   PA6T_MMCR0_DAMEN5     0x0000000100000000UL
+#define   PA6T_MMCR0_DAMSEL2    0x0000000200000000UL
+#define   PA6T_MMCR0_DAMSEL3    0x0000000400000000UL
+#define   PA6T_MMCR0_DAMSEL4    0x0000000800000000UL
+#define   PA6T_MMCR0_DAMSEL5    0x0000001000000000UL
+#define   PA6T_MMCR0_HANDDIS    0x0000002000000000UL
+#define   PA6T_MMCR0_PCTEN      0x0000004000000000UL
+#define   PA6T_MMCR0_SOCEN      0x0000008000000000UL
+#define   PA6T_MMCR0_SOCMOD     0x0000010000000000UL
+
+#define SPRN_PA6T_MMCR1 798
+#define   PA6T_MMCR1_ES2        0x00000000000000ffUL
+#define   PA6T_MMCR1_ES3        0x000000000000ff00UL
+#define   PA6T_MMCR1_ES4        0x0000000000ff0000UL
+#define   PA6T_MMCR1_ES5        0x00000000ff000000UL
+
+#define SPRN_PA6T_UPMC0 771     /* User PerfMon Counter 0 */
+#define SPRN_PA6T_UPMC1 772     /* ... */
+#define SPRN_PA6T_UPMC2 773
+#define SPRN_PA6T_UPMC3 774
+#define SPRN_PA6T_UPMC4 775
+#define SPRN_PA6T_UPMC5 776
+#define SPRN_PA6T_UMMCR0 779    /* User Monitor Mode Control Register 0 */
+#define SPRN_PA6T_SIAR  780     /* Sampled Instruction Address */
+#define SPRN_PA6T_UMMCR1 782    /* User Monitor Mode Control Register 1 */
+#define SPRN_PA6T_SIER  785     /* Sampled Instruction Event Register */
+#define SPRN_PA6T_PMC0  787
+#define SPRN_PA6T_PMC1  788
+#define SPRN_PA6T_PMC2  789
+#define SPRN_PA6T_PMC3  790
+#define SPRN_PA6T_PMC4  791
+#define SPRN_PA6T_PMC5  792
+#define SPRN_PA6T_TSR0  793     /* Timestamp Register 0 */
+#define SPRN_PA6T_TSR1  794     /* Timestamp Register 1 */
+#define SPRN_PA6T_TSR2  799     /* Timestamp Register 2 */
+#define SPRN_PA6T_TSR3  784     /* Timestamp Register 3 */
+
+#define SPRN_PA6T_IER   981     /* Icache Error Register */
+#define SPRN_PA6T_DER   982     /* Dcache Error Register */
+#define SPRN_PA6T_BER   862     /* BIU Error Address Register */
+#define SPRN_PA6T_MER   849     /* MMU Error Register */
+
+#define SPRN_PA6T_IMA0  880     /* Instruction Match Array 0 */
+#define SPRN_PA6T_IMA1  881     /* ... */
+#define SPRN_PA6T_IMA2  882
+#define SPRN_PA6T_IMA3  883
+#define SPRN_PA6T_IMA4  884
+#define SPRN_PA6T_IMA5  885
+#define SPRN_PA6T_IMA6  886
+#define SPRN_PA6T_IMA7  887
+#define SPRN_PA6T_IMA8  888
+#define SPRN_PA6T_IMA9  889
+#define SPRN_PA6T_BTCR  978     /* Breakpoint and Tagging Control Register */
+#define SPRN_PA6T_IMAAT 979     /* Instruction Match Array Action Table */
+#define SPRN_PA6T_PCCR  1019    /* Power Counter Control Register */
+#define SPRN_BKMK       1020    /* Cell Bookmark Register */
+#define SPRN_PA6T_RPCCR 1021    /* Retire PC Trace Control Register */
+
+
+#else /* 32-bit */
+#define SPRN_MMCR0      952     /* Monitor Mode Control Register 0 */
+#define   MMCR0_FC      0x80000000UL /* freeze counters */
+#define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
+#define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
+#define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
+#define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
+#define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
+#define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
+#define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
+#define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
+#define   MMCR0_PMCnCE  0x00004000UL /* count enable for all but PMC 1*/
+#define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+#define   MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
+#define   MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
+
+#define SPRN_MMCR1      956
+#define   MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
+#define   MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
+#define   MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
+#define   MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
+#define SPRN_MMCR2      944
+#define SPRN_PMC1       953     /* Performance Counter Register 1 */
+#define SPRN_PMC2       954     /* Performance Counter Register 2 */
+#define SPRN_PMC3       957     /* Performance Counter Register 3 */
+#define SPRN_PMC4       958     /* Performance Counter Register 4 */
+#define SPRN_PMC5       945     /* Performance Counter Register 5 */
+#define SPRN_PMC6       946     /* Performance Counter Register 6 */
+
+#define SPRN_SIAR       955     /* Sampled Instruction Address Register */
+
+/* Bit definitions for MMCR0 and PMC1 / PMC2. */
+#define MMCR0_PMC1_CYCLES       (1 << 7)
+#define MMCR0_PMC1_ICACHEMISS   (5 << 7)
+#define MMCR0_PMC1_DTLB         (6 << 7)
+#define MMCR0_PMC2_DCACHEMISS   0x6
+#define MMCR0_PMC2_CYCLES       0x1
+#define MMCR0_PMC2_ITLB         0x7
+#define MMCR0_PMC2_LOADMISSTIME 0x5
+#endif
+
+/*
+ * An mtfsf instruction with the L bit set. On CPUs that support this a
+ * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
+ *
+ * Until binutils gets the new form of mtfsf, hardwire the instruction.
+ */
+#ifdef CONFIG_PPC64
+#define MTFSF_L(REG) \
+        .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
+#else
+#define MTFSF_L(REG)    mtfsf   0xff, (REG)
+#endif
+
+/* Processor Version Register (PVR) field extraction */
+
+#define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
+#define PVR_REV(pvr)    (((pvr) >>   0) & 0xFFFF)       /* Revison field */
+
+#define __is_processor(pv)      (PVR_VER(mfspr(SPRN_PVR)) == (pv))
+
+/*
+ * IBM has further subdivided the standard PowerPC 16-bit version and
+ * revision subfields of the PVR for the PowerPC 403s into the following:
+ */
+
+#define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
+#define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
+#define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
+#define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
+#define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
+#define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
+
+/* Processor Version Numbers */
+
+#define PVR_403GA       0x00200000
+#define PVR_403GB       0x00200100
+#define PVR_403GC       0x00200200
+#define PVR_403GCX      0x00201400
+#define PVR_405GP       0x40110000
+#define PVR_STB03XXX    0x40310000
+#define PVR_NP405H      0x41410000
+#define PVR_NP405L      0x41610000
+#define PVR_601         0x00010000
+#define PVR_602         0x00050000
+#define PVR_603         0x00030000
+#define PVR_603e        0x00060000
+#define PVR_603ev       0x00070000
+#define PVR_603r        0x00071000
+#define PVR_604         0x00040000
+#define PVR_604e        0x00090000
+#define PVR_604r        0x000A0000
+#define PVR_620         0x00140000
+#define PVR_740         0x00080000
+#define PVR_750         PVR_740
+#define PVR_740P        0x10080000
+#define PVR_750P        PVR_740P
+#define PVR_7400        0x000C0000
+#define PVR_7410        0x800C0000
+#define PVR_7450        0x80000000
+#define PVR_8540        0x80200000
+#define PVR_8560        0x80200000
+/*
+ * For the 8xx processors, all of them report the same PVR family for
+ * the PowerPC core. The various versions of these processors must be
+ * differentiated by the version number in the Communication Processor
+ * Module (CPM).
+ */
+#define PVR_821         0x00500000
+#define PVR_823         PVR_821
+#define PVR_850         PVR_821
+#define PVR_860         PVR_821
+#define PVR_8240        0x00810100
+#define PVR_8245        0x80811014
+#define PVR_8260        PVR_8240
+
+/* 64-bit processors */
+/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
+#define PV_NORTHSTAR    0x0033
+#define PV_PULSAR       0x0034
+#define PV_POWER4       0x0035
+#define PV_ICESTAR      0x0036
+#define PV_SSTAR        0x0037
+#define PV_POWER4p      0x0038
+#define PV_970          0x0039
+#define PV_POWER5       0x003A
+#define PV_POWER5p      0x003B
+#define PV_970FX        0x003C
+#define PV_630          0x0040
+#define PV_630p 0x0041
+#define PV_970MP        0x0044
+#define PV_970GX        0x0045
+#define PV_BE           0x0070
+#define PV_PA6T         0x0090
+
+/* Macros for setting and retrieving special purpose registers */
+#ifndef __ASSEMBLY__
+#define mfmsr()         ({unsigned long rval; \
+                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#ifdef CONFIG_PPC64
+#define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
+                                     : : "r" (v))
+#define mtmsrd(v)       __mtmsrd((v), 0)
+#define mtmsr(v)        mtmsrd(v)
+#else
+#define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
+#endif
+
+#define mfspr(rn)       ({unsigned long rval; \
+                        asm volatile("mfspr %0," __stringify(rn) \
+                                : "=r" (rval)); rval;})
+#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
+
+#ifdef __powerpc64__
+#ifdef CONFIG_PPC_CELL
+#define mftb()          ({unsigned long rval;                           \
+                        asm volatile(                                   \
+                                "90:    mftb %0;\n"                     \
+                                "97:    cmpwi %0,0;\n"                  \
+                                "       beq- 90b;\n"                    \
+                                "99:\n"                                 \
+                                ".section __ftr_fixup,\"a\"\n"          \
+                                ".align 3\n"                            \
+                                "98:\n"                                 \
+                                "       .llong %1\n"                    \
+                                "       .llong %1\n"                    \
+                                "       .llong 97b-98b\n"               \
+                                "       .llong 99b-98b\n"               \
+                                "       .llong 0\n"                     \
+                                "       .llong 0\n"                     \
+                                ".previous"                             \
+                        : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
+#else
+#define mftb()          ({unsigned long rval;   \
+                        asm volatile("mftb %0" : "=r" (rval)); rval;})
+#endif /* !CONFIG_PPC_CELL */
+
+#else /* __powerpc64__ */
+
+#define mftbl()         ({unsigned long rval;   \
+                        asm volatile("mftbl %0" : "=r" (rval)); rval;})
+#define mftbu()         ({unsigned long rval;   \
+                        asm volatile("mftbu %0" : "=r" (rval)); rval;})
+#endif /* !__powerpc64__ */
+
+#define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
+#define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
+
+#ifdef CONFIG_PPC32
+#define mfsrin(v)       ({unsigned int rval; \
+                        asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
+                                        rval;})
+#endif
+
+#define proc_trap()     asm volatile("trap")
+
+#ifdef CONFIG_PPC64
+
+extern void ppc64_runlatch_on(void);
+extern void ppc64_runlatch_off(void);
+
+extern unsigned long scom970_read(unsigned int address);
+extern void scom970_write(unsigned int address, unsigned long value);
+
+#else
+#define ppc64_runlatch_on()
+#define ppc64_runlatch_off()
+
+#endif /* CONFIG_PPC64 */
+
+#define __get_SP()      ({unsigned long sp; \
+                        asm volatile("mr %0,1": "=r" (sp)); sp;})
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_REG_H */
diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h
new file mode 100644
index 000000000000..e8ea346b21d3
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_8xx.h
@@ -0,0 +1,42 @@
+/*
+ * Contains register definitions common to PowerPC 8xx CPUs.  Notice
+ */
+#ifndef _ASM_POWERPC_REG_8xx_H
+#define _ASM_POWERPC_REG_8xx_H
+
+/* Cache control on the MPC8xx is provided through some additional
+ * special purpose registers.
+ */
+#define SPRN_IC_CST     560     /* Instruction cache control/status */
+#define SPRN_IC_ADR     561     /* Address needed for some commands */
+#define SPRN_IC_DAT     562     /* Read-only data register */
+#define SPRN_DC_CST     568     /* Data cache control/status */
+#define SPRN_DC_ADR     569     /* Address needed for some commands */
+#define SPRN_DC_DAT     570     /* Read-only data register */
+
+/* Commands.  Only the first few are available to the instruction cache.
+*/
+#define IDC_ENABLE      0x02000000      /* Cache enable */
+#define IDC_DISABLE     0x04000000      /* Cache disable */
+#define IDC_LDLCK       0x06000000      /* Load and lock */
+#define IDC_UNLINE      0x08000000      /* Unlock line */
+#define IDC_UNALL       0x0a000000      /* Unlock all */
+#define IDC_INVALL      0x0c000000      /* Invalidate all */
+
+#define DC_FLINE        0x0e000000      /* Flush data cache line */
+#define DC_SFWT         0x01000000      /* Set forced writethrough mode */
+#define DC_CFWT         0x03000000      /* Clear forced writethrough mode */
+#define DC_SLES         0x05000000      /* Set little endian swap mode */
+#define DC_CLES         0x07000000      /* Clear little endian swap mode */
+
+/* Status.
+*/
+#define IDC_ENABLED     0x80000000      /* Cache is enabled */
+#define IDC_CERR1       0x00200000      /* Cache error 1 */
+#define IDC_CERR2       0x00100000      /* Cache error 2 */
+#define IDC_CERR3       0x00080000      /* Cache error 3 */
+
+#define DC_DFWT         0x40000000      /* Data cache is forced write through */
+#define DC_LES          0x20000000      /* Caches are little endian mode */
+
+#endif /* _ASM_POWERPC_REG_8xx_H */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
new file mode 100644
index 000000000000..be980f4ee495
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -0,0 +1,501 @@
+/*
+ * Contains register definitions common to the Book E PowerPC
+ * specification.  Notice that while the IBM-40x series of CPUs
+ * are not true Book E PowerPCs, they borrowed a number of features
+ * before Book E was finalized, and are included here as well.  Unfortunatly,
+ * they sometimes used different locations than true Book E CPUs did.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_REG_BOOKE_H__
+#define __ASM_POWERPC_REG_BOOKE_H__
+
+/* Machine State Register (MSR) Fields */
+#define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
+#define MSR_SPE         (1<<25) /* Enable SPE */
+#define MSR_DWE         (1<<10) /* Debug Wait Enable */
+#define MSR_UBLE        (1<<10) /* BTB lock enable (e500) */
+#define MSR_IS          MSR_IR  /* Instruction Space */
+#define MSR_DS          MSR_DR  /* Data Space */
+#define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
+
+/* Default MSR for kernel mode. */
+#if defined (CONFIG_40x)
+#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
+#elif defined(CONFIG_BOOKE)
+#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_CE)
+#endif
+
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_DECAR      0x036   /* Decrementer Auto Reload Register */
+#define SPRN_IVPR       0x03F   /* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0     0x100   /* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R     0x104   /* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R     0x105   /* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R     0x106   /* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R     0x107   /* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W     0x114   /* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W     0x115   /* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W     0x116   /* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W     0x117   /* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2      0x136   /* Debug Control Register 2 */
+#define SPRN_IAC3       0x13A   /* Instruction Address Compare 3 */
+#define SPRN_IAC4       0x13B   /* Instruction Address Compare 4 */
+#define SPRN_DVC1       0x13E   /* Data Value Compare Register 1 */
+#define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
+#define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1      0x191   /* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2      0x192   /* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3      0x193   /* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4      0x194   /* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5      0x195   /* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6      0x196   /* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7      0x197   /* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8      0x198   /* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9      0x199   /* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10     0x19A   /* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11     0x19B   /* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12     0x19C   /* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13     0x19D   /* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14     0x19E   /* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15     0x19F   /* Interrupt Vector Offset Register 15 */
+#define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
+#define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
+#define SPRN_L1CFG0     0x203   /* L1 Cache Configure Register 0 */
+#define SPRN_L1CFG1     0x204   /* L1 Cache Configure Register 1 */
+#define SPRN_ATB        0x20E   /* Alternate Time Base */
+#define SPRN_ATBL       0x20E   /* Alternate Time Base Lower */
+#define SPRN_ATBU       0x20F   /* Alternate Time Base Upper */
+#define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34     0x212   /* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35     0x213   /* Interrupt Vector Offset Register 35 */
+#define SPRN_IVOR36     0x214   /* Interrupt Vector Offset Register 36 */
+#define SPRN_IVOR37     0x215   /* Interrupt Vector Offset Register 37 */
+#define SPRN_MCSRR0     0x23A   /* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1     0x23B   /* Machine Check Save and Restore Register 1 */
+#define SPRN_MCSR       0x23C   /* Machine Check Status Register */
+#define SPRN_MCAR       0x23D   /* Machine Check Address Register */
+#define SPRN_DSRR0      0x23E   /* Debug Save and Restore Register 0 */
+#define SPRN_DSRR1      0x23F   /* Debug Save and Restore Register 1 */
+#define SPRN_SPRG8      0x25C   /* Special Purpose Register General 8 */
+#define SPRN_SPRG9      0x25D   /* Special Purpose Register General 9 */
+#define SPRN_L1CSR2     0x25E   /* L1 Cache Control and Status Register 2 */
+#define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
+#define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
+#define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
+#define SPRN_MAS3       0x273   /* MMU Assist Register 3 */
+#define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
+#define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
+#define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
+#define SPRN_PID1       0x279   /* Process ID Register 1 */
+#define SPRN_PID2       0x27A   /* Process ID Register 2 */
+#define SPRN_TLB0CFG    0x2B0   /* TLB 0 Config Register */
+#define SPRN_TLB1CFG    0x2B1   /* TLB 1 Config Register */
+#define SPRN_EPR        0x2BE   /* External Proxy Register */
+#define SPRN_CCR1       0x378   /* Core Configuration Register 1 */
+#define SPRN_ZPR        0x3B0   /* Zone Protection Register (40x) */
+#define SPRN_MAS7       0x3B0   /* MMU Assist Register 7 */
+#define SPRN_MMUCR      0x3B2   /* MMU Control Register */
+#define SPRN_CCR0       0x3B3   /* Core Configuration Register 0 */
+#define SPRN_EPLC       0x3B3   /* External Process ID Load Context */
+#define SPRN_EPSC       0x3B4   /* External Process ID Store Context */
+#define SPRN_SGR        0x3B9   /* Storage Guarded Register */
+#define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
+#define SPRN_SLER       0x3BB   /* Little-endian real mode */
+#define SPRN_SU0R       0x3BC   /* "User 0" real mode (40x) */
+#define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
+#define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
+#define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
+#define SPRN_L1CSR0     0x3F2   /* L1 Cache Control and Status Register 0 */
+#define SPRN_L1CSR1     0x3F3   /* L1 Cache Control and Status Register 1 */
+#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
+#define SPRN_BUCSR      0x3F5   /* Branch Unit Control and Status */
+#define SPRN_L2CSR0     0x3F9   /* L2 Data Cache Control and Status Register 0 */
+#define SPRN_L2CSR1     0x3FA   /* L2 Data Cache Control and Status Register 1 */
+#define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
+#define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_SVR        0x3FF   /* System Version Register */
+
+/*
+ * SPRs which have conflicting definitions on true Book E versus classic,
+ * or IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define SPRN_PID        0x030   /* Process ID */
+#define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
+#define SPRN_CSRR0      0x03A   /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1      0x03B   /* Critical Save and Restore Register 1 */
+#define SPRN_DEAR       0x03D   /* Data Error Address Register */
+#define SPRN_ESR        0x03E   /* Exception Syndrome Register */
+#define SPRN_PIR        0x11E   /* Processor Identification Register */
+#define SPRN_DBSR       0x130   /* Debug Status Register */
+#define SPRN_DBCR0      0x134   /* Debug Control Register 0 */
+#define SPRN_DBCR1      0x135   /* Debug Control Register 1 */
+#define SPRN_IAC1       0x138   /* Instruction Address Compare 1 */
+#define SPRN_IAC2       0x139   /* Instruction Address Compare 2 */
+#define SPRN_DAC1       0x13C   /* Data Address Compare 1 */
+#define SPRN_DAC2       0x13D   /* Data Address Compare 2 */
+#define SPRN_TSR        0x150   /* Timer Status Register */
+#define SPRN_TCR        0x154   /* Timer Control Register */
+#endif /* Book E */
+#ifdef CONFIG_40x
+#define SPRN_PID        0x3B1   /* Process ID */
+#define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */          
+#define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
+#define SPRN_DEAR       0x3D5   /* Data Error Address Register */
+#define SPRN_TSR        0x3D8   /* Timer Status Register */
+#define SPRN_TCR        0x3DA   /* Timer Control Register */
+#define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
+#define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
+#define SPRN_DBSR       0x3F0   /* Debug Status Register */             
+#define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
+#define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
+#define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
+#define SPRN_CSRR0      SPRN_SRR2 /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1      SPRN_SRR3 /* Critical Save and Restore Register 1 */
+#endif
+
+/* Bit definitions for CCR1. */
+#define CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
+#define CCR1_TCS        0x00000080 /* Timer Clock Select */
+
+/* Bit definitions for the MCSR. */
+#define MCSR_MCS        0x80000000 /* Machine Check Summary */
+#define MCSR_IB         0x40000000 /* Instruction PLB Error */
+#define MCSR_DRB        0x20000000 /* Data Read PLB Error */
+#define MCSR_DWB        0x10000000 /* Data Write PLB Error */
+#define MCSR_TLBP       0x08000000 /* TLB Parity Error */
+#define MCSR_ICP        0x04000000 /* I-Cache Parity Error */
+#define MCSR_DCSP       0x02000000 /* D-Cache Search Parity Error */
+#define MCSR_DCFP       0x01000000 /* D-Cache Flush Parity Error */
+#define MCSR_IMPE       0x00800000 /* Imprecise Machine Check Exception */
+
+#ifdef CONFIG_E500
+#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
+#define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
+#define MCSR_DCP_PERR   0x20000000UL /* D-Cache Push Parity Error */
+#define MCSR_DCPERR     0x10000000UL /* D-Cache Parity Error */
+#define MCSR_BUS_IAERR  0x00000080UL /* Instruction Address Error */
+#define MCSR_BUS_RAERR  0x00000040UL /* Read Address Error */
+#define MCSR_BUS_WAERR  0x00000020UL /* Write Address Error */
+#define MCSR_BUS_IBERR  0x00000010UL /* Instruction Data Error */
+#define MCSR_BUS_RBERR  0x00000008UL /* Read Data Bus Error */
+#define MCSR_BUS_WBERR  0x00000004UL /* Write Data Bus Error */
+#define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
+#define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
+
+/* e500 parts may set unused bits in MCSR; mask these off */
+#define MCSR_MASK       (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
+                        MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
+                        MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
+                        MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
+#endif
+#ifdef CONFIG_E200
+#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
+#define MCSR_CP_PERR    0x20000000UL /* Cache Push Parity Error */
+#define MCSR_CPERR      0x10000000UL /* Cache Parity Error */
+#define MCSR_EXCP_ERR   0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
+                                        fetch for an exception handler */
+#define MCSR_BUS_IRERR  0x00000010UL /* Read Bus Error on instruction fetch*/
+#define MCSR_BUS_DRERR  0x00000008UL /* Read Bus Error on data load */
+#define MCSR_BUS_WRERR  0x00000004UL /* Write Bus Error on buffered
+                                        store or cache line push */
+
+/* e200 parts may set unused bits in MCSR; mask these off */
+#define MCSR_MASK       (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
+                        MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
+                        MCSR_BUS_WRERR)
+#endif
+
+/* Bit definitions for the DBSR. */
+/*
+ * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define DBSR_IC         0x08000000      /* Instruction Completion */
+#define DBSR_BT         0x04000000      /* Branch Taken */
+#define DBSR_IRPT       0x02000000      /* Exception Debug Event */
+#define DBSR_TIE        0x01000000      /* Trap Instruction Event */
+#define DBSR_IAC1       0x00800000      /* Instr Address Compare 1 Event */
+#define DBSR_IAC2       0x00400000      /* Instr Address Compare 2 Event */
+#define DBSR_IAC3       0x00200000      /* Instr Address Compare 3 Event */
+#define DBSR_IAC4       0x00100000      /* Instr Address Compare 4 Event */
+#define DBSR_DAC1R      0x00080000      /* Data Addr Compare 1 Read Event */
+#define DBSR_DAC1W      0x00040000      /* Data Addr Compare 1 Write Event */
+#define DBSR_DAC2R      0x00020000      /* Data Addr Compare 2 Read Event */
+#define DBSR_DAC2W      0x00010000      /* Data Addr Compare 2 Write Event */
+#define DBSR_RET        0x00008000      /* Return Debug Event */
+#define DBSR_CIRPT      0x00000040      /* Critical Interrupt Taken Event */
+#define DBSR_CRET       0x00000020      /* Critical Return Debug Event */
+#endif
+#ifdef CONFIG_40x
+#define DBSR_IC         0x80000000      /* Instruction Completion */
+#define DBSR_BT         0x40000000      /* Branch taken */
+#define DBSR_IRPT       0x20000000      /* Exception Debug Event */
+#define DBSR_TIE        0x10000000      /* Trap Instruction debug Event */
+#define DBSR_IAC1       0x04000000      /* Instruction Address Compare 1 Event */
+#define DBSR_IAC2       0x02000000      /* Instruction Address Compare 2 Event */
+#define DBSR_IAC3       0x00080000      /* Instruction Address Compare 3 Event */
+#define DBSR_IAC4       0x00040000      /* Instruction Address Compare 4 Event */
+#define DBSR_DAC1R      0x01000000      /* Data Address Compare 1 Read Event */
+#define DBSR_DAC1W      0x00800000      /* Data Address Compare 1 Write Event */
+#define DBSR_DAC2R      0x00400000      /* Data Address Compare 2 Read Event */
+#define DBSR_DAC2W      0x00200000      /* Data Address Compare 2 Write Event */
+#endif
+
+/* Bit definitions related to the ESR. */
+#define ESR_MCI         0x80000000      /* Machine Check - Instruction */
+#define ESR_IMCP        0x80000000      /* Instr. Machine Check - Protection */
+#define ESR_IMCN        0x40000000      /* Instr. Machine Check - Non-config */
+#define ESR_IMCB        0x20000000      /* Instr. Machine Check - Bus error */
+#define ESR_IMCT        0x10000000      /* Instr. Machine Check - Timeout */
+#define ESR_PIL         0x08000000      /* Program Exception - Illegal */
+#define ESR_PPR         0x04000000      /* Program Exception - Privileged */
+#define ESR_PTR         0x02000000      /* Program Exception - Trap */
+#define ESR_FP          0x01000000      /* Floating Point Operation */
+#define ESR_DST         0x00800000      /* Storage Exception - Data miss */
+#define ESR_DIZ         0x00400000      /* Storage Exception - Zone fault */
+#define ESR_ST          0x00800000      /* Store Operation */
+#define ESR_DLK         0x00200000      /* Data Cache Locking */
+#define ESR_ILK         0x00100000      /* Instr. Cache Locking */
+#define ESR_PUO         0x00040000      /* Unimplemented Operation exception */
+#define ESR_BO          0x00020000      /* Byte Ordering */
+
+/* Bit definitions related to the DBCR0. */
+#if defined(CONFIG_40x)
+#define DBCR0_EDM       0x80000000      /* External Debug Mode */
+#define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
+#define DBCR0_RST       0x30000000      /* all the bits in the RST field */
+#define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
+#define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
+#define DBCR0_RST_CORE  0x10000000      /* Core Reset */
+#define DBCR0_RST_NONE  0x00000000      /* No Reset */
+#define DBCR0_IC        0x08000000      /* Instruction Completion */
+#define DBCR0_ICMP      DBCR0_IC
+#define DBCR0_BT        0x04000000      /* Branch Taken */
+#define DBCR0_BRT       DBCR0_BT
+#define DBCR0_EDE       0x02000000      /* Exception Debug Event */
+#define DBCR0_IRPT      DBCR0_EDE
+#define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
+#define DBCR0_IA1       0x00800000      /* Instr Addr compare 1 enable */
+#define DBCR0_IAC1      DBCR0_IA1
+#define DBCR0_IA2       0x00400000      /* Instr Addr compare 2 enable */
+#define DBCR0_IAC2      DBCR0_IA2
+#define DBCR0_IA12      0x00200000      /* Instr Addr 1-2 range enable */
+#define DBCR0_IA12X     0x00100000      /* Instr Addr 1-2 range eXclusive */
+#define DBCR0_IA3       0x00080000      /* Instr Addr compare 3 enable */
+#define DBCR0_IAC3      DBCR0_IA3
+#define DBCR0_IA4       0x00040000      /* Instr Addr compare 4 enable */
+#define DBCR0_IAC4      DBCR0_IA4
+#define DBCR0_IA34      0x00020000      /* Instr Addr 3-4 range Enable */
+#define DBCR0_IA34X     0x00010000      /* Instr Addr 3-4 range eXclusive */
+#define DBCR0_IA12T     0x00008000      /* Instr Addr 1-2 range Toggle */
+#define DBCR0_IA34T     0x00004000      /* Instr Addr 3-4 range Toggle */
+#define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
+#elif defined(CONFIG_BOOKE)
+#define DBCR0_EDM       0x80000000      /* External Debug Mode */
+#define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
+#define DBCR0_RST       0x30000000      /* all the bits in the RST field */
+/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
+#define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
+#define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
+#define DBCR0_RST_CORE  0x10000000      /* Core Reset */
+#define DBCR0_RST_NONE  0x00000000      /* No Reset */
+#define DBCR0_ICMP      0x08000000      /* Instruction Completion */
+#define DBCR0_IC        DBCR0_ICMP
+#define DBCR0_BRT       0x04000000      /* Branch Taken */
+#define DBCR0_BT        DBCR0_BRT
+#define DBCR0_IRPT      0x02000000      /* Exception Debug Event */
+#define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
+#define DBCR0_TIE       DBCR0_TDE
+#define DBCR0_IAC1      0x00800000      /* Instr Addr compare 1 enable */
+#define DBCR0_IAC2      0x00400000      /* Instr Addr compare 2 enable */
+#define DBCR0_IAC3      0x00200000      /* Instr Addr compare 3 enable */
+#define DBCR0_IAC4      0x00100000      /* Instr Addr compare 4 enable */
+#define DBCR0_DAC1R     0x00080000      /* DAC 1 Read enable */
+#define DBCR0_DAC1W     0x00040000      /* DAC 1 Write enable */
+#define DBCR0_DAC2R     0x00020000      /* DAC 2 Read enable */
+#define DBCR0_DAC2W     0x00010000      /* DAC 2 Write enable */
+#define DBCR0_RET       0x00008000      /* Return Debug Event */
+#define DBCR0_CIRPT     0x00000040      /* Critical Interrupt Taken Event */
+#define DBCR0_CRET      0x00000020      /* Critical Return Debug Event */
+#define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
+
+/* Bit definitions related to the DBCR1. */
+#define DBCR1_IAC12M    0x00800000      /* Instr Addr 1-2 range enable */
+#define DBCR1_IAC12MX   0x00C00000      /* Instr Addr 1-2 range eXclusive */
+#define DBCR1_IAC12AT   0x00010000      /* Instr Addr 1-2 range Toggle */
+#define DBCR1_IAC34M    0x00000080      /* Instr Addr 3-4 range enable */
+#define DBCR1_IAC34MX   0x000000C0      /* Instr Addr 3-4 range eXclusive */
+#define DBCR1_IAC34AT   0x00000001      /* Instr Addr 3-4 range Toggle */
+
+/* Bit definitions related to the DBCR2. */
+#define DBCR2_DAC12M    0x00800000      /* DAC 1-2 range enable */
+#define DBCR2_DAC12MX   0x00C00000      /* DAC 1-2 range eXclusive */
+#define DBCR2_DAC12A    0x00200000      /* DAC 1-2 Asynchronous */
+#endif
+
+/* Bit definitions related to the TCR. */
+#define TCR_WP(x)       (((x)&0x3)<<30) /* WDT Period */
+#define TCR_WP_MASK     TCR_WP(3)
+#define WP_2_17         0               /* 2^17 clocks */
+#define WP_2_21         1               /* 2^21 clocks */
+#define WP_2_25         2               /* 2^25 clocks */
+#define WP_2_29         3               /* 2^29 clocks */
+#define TCR_WRC(x)      (((x)&0x3)<<28) /* WDT Reset Control */
+#define TCR_WRC_MASK    TCR_WRC(3)
+#define WRC_NONE        0               /* No reset will occur */
+#define WRC_CORE        1               /* Core reset will occur */
+#define WRC_CHIP        2               /* Chip reset will occur */
+#define WRC_SYSTEM      3               /* System reset will occur */
+#define TCR_WIE         0x08000000      /* WDT Interrupt Enable */
+#define TCR_PIE         0x04000000      /* PIT Interrupt Enable */
+#define TCR_DIE         TCR_PIE         /* DEC Interrupt Enable */
+#define TCR_FP(x)       (((x)&0x3)<<24) /* FIT Period */
+#define TCR_FP_MASK     TCR_FP(3)
+#define FP_2_9          0               /* 2^9 clocks */
+#define FP_2_13         1               /* 2^13 clocks */
+#define FP_2_17         2               /* 2^17 clocks */
+#define FP_2_21         3               /* 2^21 clocks */
+#define TCR_FIE         0x00800000      /* FIT Interrupt Enable */
+#define TCR_ARE         0x00400000      /* Auto Reload Enable */
+
+/* Bit definitions for the TSR. */
+#define TSR_ENW         0x80000000      /* Enable Next Watchdog */
+#define TSR_WIS         0x40000000      /* WDT Interrupt Status */
+#define TSR_WRS(x)      (((x)&0x3)<<28) /* WDT Reset Status */
+#define WRS_NONE        0               /* No WDT reset occurred */
+#define WRS_CORE        1               /* WDT forced core reset */
+#define WRS_CHIP        2               /* WDT forced chip reset */
+#define WRS_SYSTEM      3               /* WDT forced system reset */
+#define TSR_PIS         0x08000000      /* PIT Interrupt Status */
+#define TSR_DIS         TSR_PIS         /* DEC Interrupt Status */
+#define TSR_FIS         0x04000000      /* FIT Interrupt Status */
+
+/* Bit definitions for the DCCR. */
+#define DCCR_NOCACHE    0               /* Noncacheable */
+#define DCCR_CACHE      1               /* Cacheable */
+
+/* Bit definitions for DCWR. */
+#define DCWR_COPY       0               /* Copy-back */
+#define DCWR_WRITE      1               /* Write-through */
+
+/* Bit definitions for ICCR. */
+#define ICCR_NOCACHE    0               /* Noncacheable */
+#define ICCR_CACHE      1               /* Cacheable */
+
+/* Bit definitions for L1CSR0. */
+#define L1CSR0_CLFC     0x00000100      /* Cache Lock Bits Flash Clear */
+#define L1CSR0_DCFI     0x00000002      /* Data Cache Flash Invalidate */
+#define L1CSR0_CFI      0x00000002      /* Cache Flash Invalidate */
+#define L1CSR0_DCE      0x00000001      /* Data Cache Enable */
+
+/* Bit definitions for L1CSR1. */
+#define L1CSR1_ICLFR    0x00000100      /* Instr Cache Lock Bits Flash Reset */
+#define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
+#define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
+
+/* Bit definitions for L2CSR0. */
+#define L2CSR0_L2E      0x80000000      /* L2 Cache Enable */
+#define L2CSR0_L2PE     0x40000000      /* L2 Cache Parity/ECC Enable */
+#define L2CSR0_L2WP     0x1c000000      /* L2 I/D Way Partioning */
+#define L2CSR0_L2CM     0x03000000      /* L2 Cache Coherency Mode */
+#define L2CSR0_L2FI     0x00200000      /* L2 Cache Flash Invalidate */
+#define L2CSR0_L2IO     0x00100000      /* L2 Cache Instruction Only */
+#define L2CSR0_L2DO     0x00010000      /* L2 Cache Data Only */
+#define L2CSR0_L2REP    0x00003000      /* L2 Line Replacement Algo */
+#define L2CSR0_L2FL     0x00000800      /* L2 Cache Flush */
+#define L2CSR0_L2LFC    0x00000400      /* L2 Cache Lock Flash Clear */
+#define L2CSR0_L2LOA    0x00000080      /* L2 Cache Lock Overflow Allocate */
+#define L2CSR0_L2LO     0x00000020      /* L2 Cache Lock Overflow */
+
+/* Bit definitions for SGR. */
+#define SGR_NORMAL      0               /* Speculative fetching allowed. */
+#define SGR_GUARDED     1               /* Speculative fetching disallowed. */
+
+/* Bit definitions for SPEFSCR. */
+#define SPEFSCR_SOVH    0x80000000      /* Summary integer overflow high */
+#define SPEFSCR_OVH     0x40000000      /* Integer overflow high */
+#define SPEFSCR_FGH     0x20000000      /* Embedded FP guard bit high */
+#define SPEFSCR_FXH     0x10000000      /* Embedded FP sticky bit high */
+#define SPEFSCR_FINVH   0x08000000      /* Embedded FP invalid operation high */
+#define SPEFSCR_FDBZH   0x04000000      /* Embedded FP div by zero high */
+#define SPEFSCR_FUNFH   0x02000000      /* Embedded FP underflow high */
+#define SPEFSCR_FOVFH   0x01000000      /* Embedded FP overflow high */
+#define SPEFSCR_FINXS   0x00200000      /* Embedded FP inexact sticky */
+#define SPEFSCR_FINVS   0x00100000      /* Embedded FP invalid op. sticky */
+#define SPEFSCR_FDBZS   0x00080000      /* Embedded FP div by zero sticky */
+#define SPEFSCR_FUNFS   0x00040000      /* Embedded FP underflow sticky */
+#define SPEFSCR_FOVFS   0x00020000      /* Embedded FP overflow sticky */
+#define SPEFSCR_MODE    0x00010000      /* Embedded FP mode */
+#define SPEFSCR_SOV     0x00008000      /* Integer summary overflow */
+#define SPEFSCR_OV      0x00004000      /* Integer overflow */
+#define SPEFSCR_FG      0x00002000      /* Embedded FP guard bit */
+#define SPEFSCR_FX      0x00001000      /* Embedded FP sticky bit */
+#define SPEFSCR_FINV    0x00000800      /* Embedded FP invalid operation */
+#define SPEFSCR_FDBZ    0x00000400      /* Embedded FP div by zero */
+#define SPEFSCR_FUNF    0x00000200      /* Embedded FP underflow */
+#define SPEFSCR_FOVF    0x00000100      /* Embedded FP overflow */
+#define SPEFSCR_FINXE   0x00000040      /* Embedded FP inexact enable */
+#define SPEFSCR_FINVE   0x00000020      /* Embedded FP invalid op. enable */
+#define SPEFSCR_FDBZE   0x00000010      /* Embedded FP div by zero enable */
+#define SPEFSCR_FUNFE   0x00000008      /* Embedded FP underflow enable */
+#define SPEFSCR_FOVFE   0x00000004      /* Embedded FP overflow enable */
+#define SPEFSCR_FRMC    0x00000003      /* Embedded FP rounding mode control */
+
+/*
+ * The IBM-403 is an even more odd special case, as it is much
+ * older than the IBM-405 series.  We put these down here incase someone
+ * wishes to support these machines again.
+ */
+#ifdef CONFIG_403GCX
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_TBHU       0x3CC   /* Time Base High User-mode */
+#define SPRN_TBLU       0x3CD   /* Time Base Low User-mode */
+#define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
+#define SPRN_TBHI       0x3DC   /* Time Base High */
+#define SPRN_TBLO       0x3DD   /* Time Base Low */
+#define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
+#define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
+#define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
+#define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
+#define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
+
+
+/* Bit definitions for the DBCR. */
+#define DBCR_EDM        DBCR0_EDM
+#define DBCR_IDM        DBCR0_IDM
+#define DBCR_RST(x)     (((x) & 0x3) << 28)
+#define DBCR_RST_NONE   0
+#define DBCR_RST_CORE   1
+#define DBCR_RST_CHIP   2
+#define DBCR_RST_SYSTEM 3
+#define DBCR_IC         DBCR0_IC        /* Instruction Completion Debug Evnt */
+#define DBCR_BT         DBCR0_BT        /* Branch Taken Debug Event */
+#define DBCR_EDE        DBCR0_EDE       /* Exception Debug Event */
+#define DBCR_TDE        DBCR0_TDE       /* TRAP Debug Event */
+#define DBCR_FER        0x00F80000      /* First Events Remaining Mask */
+#define DBCR_FT         0x00040000      /* Freeze Timers on Debug Event */
+#define DBCR_IA1        0x00020000      /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2        0x00010000      /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R        0x00008000      /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W        0x00004000      /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x)     (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
+#define DAC_BYTE        0
+#define DAC_HALF        1
+#define DAC_WORD        2
+#define DAC_QUAD        3
+#define DBCR_D2R        0x00000800      /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W        0x00000400      /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x)     (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
+#define DBCR_SBT        0x00000040      /* Second Branch Taken Debug Event */
+#define DBCR_SED        0x00000020      /* Second Exception Debug Event */
+#define DBCR_STD        0x00000010      /* Second Trap Debug Event */
+#define DBCR_SIA        0x00000008      /* Second IAC Enable */
+#define DBCR_SDA        0x00000004      /* Second DAC Enable */
+#define DBCR_JOI        0x00000002      /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII        0x00000001      /* JTAG Serial Inbound Int. Enable */
+#endif /* 403GCX */
+#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h b/arch/powerpc/include/asm/reg_fsl_emb.h
new file mode 100644
index 000000000000..1e180a594589
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_fsl_emb.h
@@ -0,0 +1,72 @@
+/*
+ * Contains register definitions for the Freescale Embedded Performance
+ * Monitor.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
+#define __ASM_POWERPC_REG_FSL_EMB_H__
+
+#ifndef __ASSEMBLY__
+/* Performance Monitor Registers */
+#define mfpmr(rn)       ({unsigned int rval; \
+                        asm volatile("mfpmr %0," __stringify(rn) \
+                                     : "=r" (rval)); rval;})
+#define mtpmr(rn, v)    asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
+#endif /* __ASSEMBLY__ */
+
+/* Freescale Book E Performance Monitor APU Registers */
+#define PMRN_PMC0       0x010   /* Performance Monitor Counter 0 */
+#define PMRN_PMC1       0x011   /* Performance Monitor Counter 1 */
+#define PMRN_PMC2       0x012   /* Performance Monitor Counter 1 */
+#define PMRN_PMC3       0x013   /* Performance Monitor Counter 1 */
+#define PMRN_PMLCA0     0x090   /* PM Local Control A0 */
+#define PMRN_PMLCA1     0x091   /* PM Local Control A1 */
+#define PMRN_PMLCA2     0x092   /* PM Local Control A2 */
+#define PMRN_PMLCA3     0x093   /* PM Local Control A3 */
+
+#define PMLCA_FC        0x80000000      /* Freeze Counter */
+#define PMLCA_FCS       0x40000000      /* Freeze in Supervisor */
+#define PMLCA_FCU       0x20000000      /* Freeze in User */
+#define PMLCA_FCM1      0x10000000      /* Freeze when PMM==1 */
+#define PMLCA_FCM0      0x08000000      /* Freeze when PMM==0 */
+#define PMLCA_CE        0x04000000      /* Condition Enable */
+
+#define PMLCA_EVENT_MASK 0x007f0000     /* Event field */
+#define PMLCA_EVENT_SHIFT       16
+
+#define PMRN_PMLCB0     0x110   /* PM Local Control B0 */
+#define PMRN_PMLCB1     0x111   /* PM Local Control B1 */
+#define PMRN_PMLCB2     0x112   /* PM Local Control B2 */
+#define PMRN_PMLCB3     0x113   /* PM Local Control B3 */
+
+#define PMLCB_THRESHMUL_MASK    0x0700  /* Threshhold Multiple Field */
+#define PMLCB_THRESHMUL_SHIFT   8
+
+#define PMLCB_THRESHOLD_MASK    0x003f  /* Threshold Field */
+#define PMLCB_THRESHOLD_SHIFT   0
+
+#define PMRN_PMGC0      0x190   /* PM Global Control 0 */
+
+#define PMGC0_FAC       0x80000000      /* Freeze all Counters */
+#define PMGC0_PMIE      0x40000000      /* Interrupt Enable */
+#define PMGC0_FCECE     0x20000000      /* Freeze countes on
+                                           Enabled Condition or
+                                           Event */
+
+#define PMRN_UPMC0      0x000   /* User Performance Monitor Counter 0 */
+#define PMRN_UPMC1      0x001   /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC2      0x002   /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC3      0x003   /* User Performance Monitor Counter 1 */
+#define PMRN_UPMLCA0    0x080   /* User PM Local Control A0 */
+#define PMRN_UPMLCA1    0x081   /* User PM Local Control A1 */
+#define PMRN_UPMLCA2    0x082   /* User PM Local Control A2 */
+#define PMRN_UPMLCA3    0x083   /* User PM Local Control A3 */
+#define PMRN_UPMLCB0    0x100   /* User PM Local Control B0 */
+#define PMRN_UPMLCB1    0x101   /* User PM Local Control B1 */
+#define PMRN_UPMLCB2    0x102   /* User PM Local Control B2 */
+#define PMRN_UPMLCB3    0x103   /* User PM Local Control B3 */
+#define PMRN_UPMGC0     0x180   /* User PM Global Control 0 */
+
+
+#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/resource.h b/arch/powerpc/include/asm/resource.h
new file mode 100644
index 000000000000..04bc4db8921b
--- /dev/null
+++ b/arch/powerpc/include/asm/resource.h
@@ -0,0 +1 @@
+#include <asm-generic/resource.h>
diff --git a/arch/powerpc/include/asm/rheap.h b/arch/powerpc/include/asm/rheap.h
new file mode 100644
index 000000000000..172381769cfc
--- /dev/null
+++ b/arch/powerpc/include/asm/rheap.h
@@ -0,0 +1,89 @@
+/*
+ * include/asm-ppc/rheap.h
+ *
+ * Header file for the implementation of a remote heap.
+ *
+ * Author: Pantelis Antoniou <panto@intracom.gr>
+ *
+ * 2004 (c) INTRACOM S.A. Greece. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASM_PPC_RHEAP_H__
+#define __ASM_PPC_RHEAP_H__
+
+#include <linux/list.h>
+
+typedef struct _rh_block {
+        struct list_head list;
+        unsigned long start;
+        int size;
+        const char *owner;
+} rh_block_t;
+
+typedef struct _rh_info {
+        unsigned int alignment;
+        int max_blocks;
+        int empty_slots;
+        rh_block_t *block;
+        struct list_head empty_list;
+        struct list_head free_list;
+        struct list_head taken_list;
+        unsigned int flags;
+} rh_info_t;
+
+#define RHIF_STATIC_INFO        0x1
+#define RHIF_STATIC_BLOCK       0x2
+
+typedef struct _rh_stats {
+        unsigned long start;
+        int size;
+        const char *owner;
+} rh_stats_t;
+
+#define RHGS_FREE       0
+#define RHGS_TAKEN      1
+
+/* Create a remote heap dynamically */
+extern rh_info_t *rh_create(unsigned int alignment);
+
+/* Destroy a remote heap, created by rh_create() */
+extern void rh_destroy(rh_info_t * info);
+
+/* Initialize in place a remote info block */
+extern void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks,
+                    rh_block_t * block);
+
+/* Attach a free region to manage */
+extern int rh_attach_region(rh_info_t * info, unsigned long start, int size);
+
+/* Detach a free region */
+extern unsigned long rh_detach_region(rh_info_t * info, unsigned long start, int size);
+
+/* Allocate the given size from the remote heap (with alignment) */
+extern unsigned long rh_alloc_align(rh_info_t * info, int size, int alignment,
+                const char *owner);
+
+/* Allocate the given size from the remote heap */
+extern unsigned long rh_alloc(rh_info_t * info, int size, const char *owner);
+
+/* Allocate the given size from the given address */
+extern unsigned long rh_alloc_fixed(rh_info_t * info, unsigned long start, int size,
+                            const char *owner);
+
+/* Free the allocated area */
+extern int rh_free(rh_info_t * info, unsigned long start);
+
+/* Get stats for debugging purposes */
+extern int rh_get_stats(rh_info_t * info, int what, int max_stats,
+                        rh_stats_t * stats);
+
+/* Simple dump of remote heap info */
+extern void rh_dump(rh_info_t * info);
+
+/* Set owner of taken block */
+extern int rh_set_owner(rh_info_t * info, unsigned long start, const char *owner);
+
+#endif                          /* __ASM_PPC_RHEAP_H__ */
diff --git a/arch/powerpc/include/asm/rio.h b/arch/powerpc/include/asm/rio.h
new file mode 100644
index 000000000000..0018bf80cb25
--- /dev/null
+++ b/arch/powerpc/include/asm/rio.h
@@ -0,0 +1,18 @@
+/*
+ * RapidIO architecture support
+ *
+ * Copyright 2005 MontaVista Software, Inc.
+ * Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef ASM_PPC_RIO_H
+#define ASM_PPC_RIO_H
+
+extern void platform_rio_init(void);
+
+#endif                          /* ASM_PPC_RIO_H */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
new file mode 100644
index 000000000000..8eaa7b28d9d0
--- /dev/null
+++ b/arch/powerpc/include/asm/rtas.h
@@ -0,0 +1,247 @@
+#ifndef _POWERPC_RTAS_H
+#define _POWERPC_RTAS_H
+#ifdef __KERNEL__
+
+#include <linux/spinlock.h>
+#include <asm/page.h>
+
+/*
+ * Definitions for talking to the RTAS on CHRP machines.
+ *
+ * Copyright (C) 2001 Peter Bergner
+ * Copyright (C) 2001 PPC 64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define RTAS_UNKNOWN_SERVICE (-1)
+#define RTAS_INSTANTIATE_MAX (1UL<<30) /* Don't instantiate rtas at/above this value */
+
+/* Buffer size for ppc_rtas system call. */
+#define RTAS_RMOBUF_MAX (64 * 1024)
+
+/* RTAS return status codes */
+#define RTAS_NOT_SUSPENDABLE    -9004
+#define RTAS_BUSY               -2    /* RTAS Busy */
+#define RTAS_EXTENDED_DELAY_MIN 9900
+#define RTAS_EXTENDED_DELAY_MAX 9905
+
+/*
+ * In general to call RTAS use rtas_token("string") to lookup
+ * an RTAS token for the given string (e.g. "event-scan").
+ * To actually perform the call use
+ *    ret = rtas_call(token, n_in, n_out, ...)
+ * Where n_in is the number of input parameters and
+ *       n_out is the number of output parameters
+ *
+ * If the "string" is invalid on this system, RTAS_UNKNOWN_SERVICE
+ * will be returned as a token.  rtas_call() does look for this
+ * token and error out gracefully so rtas_call(rtas_token("str"), ...)
+ * may be safely used for one-shot calls to RTAS.
+ *
+ */
+
+typedef u32 rtas_arg_t;
+
+struct rtas_args {
+        u32 token;
+        u32 nargs;
+        u32 nret; 
+        rtas_arg_t args[16];
+        rtas_arg_t *rets;     /* Pointer to return values in args[]. */
+};  
+
+struct rtas_t {
+        unsigned long entry;            /* physical address pointer */
+        unsigned long base;             /* physical address pointer */
+        unsigned long size;
+        spinlock_t lock;
+        struct rtas_args args;
+        struct device_node *dev;        /* virtual address pointer */
+};
+
+/* RTAS event classes */
+#define RTAS_INTERNAL_ERROR             0x80000000 /* set bit 0 */
+#define RTAS_EPOW_WARNING               0x40000000 /* set bit 1 */
+#define RTAS_POWERMGM_EVENTS            0x20000000 /* set bit 2 */
+#define RTAS_HOTPLUG_EVENTS             0x10000000 /* set bit 3 */
+#define RTAS_EVENT_SCAN_ALL_EVENTS      0xf0000000
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_FATAL             0x5
+#define RTAS_SEVERITY_ERROR             0x4
+#define RTAS_SEVERITY_ERROR_SYNC        0x3
+#define RTAS_SEVERITY_WARNING           0x2
+#define RTAS_SEVERITY_EVENT             0x1
+#define RTAS_SEVERITY_NO_ERROR          0x0
+
+/* RTAS event disposition */
+#define RTAS_DISP_FULLY_RECOVERED       0x0
+#define RTAS_DISP_LIMITED_RECOVERY      0x1
+#define RTAS_DISP_NOT_RECOVERED         0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_UNKNOWN          0x0
+#define RTAS_INITIATOR_CPU              0x1
+#define RTAS_INITIATOR_PCI              0x2
+#define RTAS_INITIATOR_ISA              0x3
+#define RTAS_INITIATOR_MEMORY           0x4
+#define RTAS_INITIATOR_POWERMGM         0x5
+
+/* RTAS event target */
+#define RTAS_TARGET_UNKNOWN             0x0
+#define RTAS_TARGET_CPU                 0x1
+#define RTAS_TARGET_PCI                 0x2
+#define RTAS_TARGET_ISA                 0x3
+#define RTAS_TARGET_MEMORY              0x4
+#define RTAS_TARGET_POWERMGM            0x5
+
+/* RTAS event type */
+#define RTAS_TYPE_RETRY                 0x01
+#define RTAS_TYPE_TCE_ERR               0x02
+#define RTAS_TYPE_INTERN_DEV_FAIL       0x03
+#define RTAS_TYPE_TIMEOUT               0x04
+#define RTAS_TYPE_DATA_PARITY           0x05
+#define RTAS_TYPE_ADDR_PARITY           0x06
+#define RTAS_TYPE_CACHE_PARITY          0x07
+#define RTAS_TYPE_ADDR_INVALID          0x08
+#define RTAS_TYPE_ECC_UNCORR            0x09
+#define RTAS_TYPE_ECC_CORR              0x0a
+#define RTAS_TYPE_EPOW                  0x40
+#define RTAS_TYPE_PLATFORM              0xE0
+#define RTAS_TYPE_IO                    0xE1
+#define RTAS_TYPE_INFO                  0xE2
+#define RTAS_TYPE_DEALLOC               0xE3
+#define RTAS_TYPE_DUMP                  0xE4
+/* I don't add PowerMGM events right now, this is a different topic */ 
+#define RTAS_TYPE_PMGM_POWER_SW_ON      0x60
+#define RTAS_TYPE_PMGM_POWER_SW_OFF     0x61
+#define RTAS_TYPE_PMGM_LID_OPEN         0x62
+#define RTAS_TYPE_PMGM_LID_CLOSE        0x63
+#define RTAS_TYPE_PMGM_SLEEP_BTN        0x64
+#define RTAS_TYPE_PMGM_WAKE_BTN         0x65
+#define RTAS_TYPE_PMGM_BATTERY_WARN     0x66
+#define RTAS_TYPE_PMGM_BATTERY_CRIT     0x67
+#define RTAS_TYPE_PMGM_SWITCH_TO_BAT    0x68
+#define RTAS_TYPE_PMGM_SWITCH_TO_AC     0x69
+#define RTAS_TYPE_PMGM_KBD_OR_MOUSE     0x6a
+#define RTAS_TYPE_PMGM_ENCLOS_OPEN      0x6b
+#define RTAS_TYPE_PMGM_ENCLOS_CLOSED    0x6c
+#define RTAS_TYPE_PMGM_RING_INDICATE    0x6d
+#define RTAS_TYPE_PMGM_LAN_ATTENTION    0x6e
+#define RTAS_TYPE_PMGM_TIME_ALARM       0x6f
+#define RTAS_TYPE_PMGM_CONFIG_CHANGE    0x70
+#define RTAS_TYPE_PMGM_SERVICE_PROC     0x71
+
+struct rtas_error_log {
+        unsigned long version:8;                /* Architectural version */
+        unsigned long severity:3;               /* Severity level of error */
+        unsigned long disposition:2;            /* Degree of recovery */
+        unsigned long extended:1;               /* extended log present? */
+        unsigned long /* reserved */ :2;        /* Reserved for future use */
+        unsigned long initiator:4;              /* Initiator of event */
+        unsigned long target:4;                 /* Target of failed operation */
+        unsigned long type:8;                   /* General event or error*/
+        unsigned long extended_log_length:32;   /* length in bytes */
+        unsigned char buffer[1];
+};
+
+/*
+ * This can be set by the rtas_flash module so that it can get called
+ * as the absolutely last thing before the kernel terminates.
+ */
+extern void (*rtas_flash_term_hook)(int);
+
+extern struct rtas_t rtas;
+
+extern void enter_rtas(unsigned long);
+extern int rtas_token(const char *service);
+extern int rtas_service_present(const char *service);
+extern int rtas_call(int token, int, int, int *, ...);
+extern void rtas_restart(char *cmd);
+extern void rtas_power_off(void);
+extern void rtas_halt(void);
+extern void rtas_os_term(char *str);
+extern int rtas_get_sensor(int sensor, int index, int *state);
+extern int rtas_get_power_level(int powerdomain, int *level);
+extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
+extern int rtas_set_indicator(int indicator, int index, int new_value);
+extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
+extern void rtas_progress(char *s, unsigned short hex);
+extern void rtas_initialize(void);
+
+struct rtc_time;
+extern unsigned long rtas_get_boot_time(void);
+extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
+extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
+
+extern unsigned int rtas_busy_delay_time(int status);
+extern unsigned int rtas_busy_delay(int status);
+
+extern int early_init_dt_scan_rtas(unsigned long node,
+                const char *uname, int depth, void *data);
+
+extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
+
+/* Error types logged.  */
+#define ERR_FLAG_ALREADY_LOGGED 0x0
+#define ERR_FLAG_BOOT           0x1     /* log was pulled from NVRAM on boot */
+#define ERR_TYPE_RTAS_LOG       0x2     /* from rtas event-scan */
+#define ERR_TYPE_KERNEL_PANIC   0x4     /* from panic() */
+
+/* All the types and not flags */
+#define ERR_TYPE_MASK   (ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC)
+
+#define RTAS_DEBUG KERN_DEBUG "RTAS: "
+ 
+#define RTAS_ERROR_LOG_MAX 2048
+
+/*
+ * Return the firmware-specified size of the error log buffer
+ *  for all rtas calls that require an error buffer argument.
+ *  This includes 'check-exception' and 'rtas-last-error'.
+ */
+extern int rtas_get_error_log_max(void);
+
+/* Event Scan Parameters */
+#define EVENT_SCAN_ALL_EVENTS   0xf0000000
+#define SURVEILLANCE_TOKEN      9000
+#define LOG_NUMBER              64              /* must be a power of two */
+#define LOG_NUMBER_MASK         (LOG_NUMBER-1)
+
+/* Some RTAS ops require a data buffer and that buffer must be < 4G.
+ * Rather than having a memory allocator, just use this buffer
+ * (get the lock first), make the RTAS call.  Copy the data instead
+ * of holding the buffer for long.
+ */
+
+#define RTAS_DATA_BUF_SIZE 4096
+extern spinlock_t rtas_data_buf_lock;
+extern char rtas_data_buf[RTAS_DATA_BUF_SIZE];
+
+/* RMO buffer reserved for user-space RTAS use */
+extern unsigned long rtas_rmo_buf;
+
+#define GLOBAL_INTERRUPT_QUEUE 9005
+
+/**
+ * rtas_config_addr - Format a busno, devfn and reg for RTAS.
+ * @busno: The bus number.
+ * @devfn: The device and function number as encoded by PCI_DEVFN().
+ * @reg: The register number.
+ *
+ * This function encodes the given busno, devfn and register number as
+ * required for RTAS calls that take a "config_addr" parameter.
+ * See PAPR requirement 7.3.4-1 for more info.
+ */
+static inline u32 rtas_config_addr(int busno, int devfn, int reg)
+{
+        return ((reg & 0xf00) << 20) | ((busno & 0xff) << 16) |
+                        (devfn << 8) | (reg & 0xff);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/include/asm/rtc.h b/arch/powerpc/include/asm/rtc.h
new file mode 100644
index 000000000000..f5802926b6c0
--- /dev/null
+++ b/arch/powerpc/include/asm/rtc.h
@@ -0,0 +1,78 @@
+/*
+ * Real-time clock definitions and interfaces
+ *
+ * Author: Tom Rini <trini@mvista.com>
+ *
+ * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Based on:
+ * include/asm-m68k/rtc.h
+ *
+ * Copyright Richard Zidlicky
+ * implementation details for genrtc/q40rtc driver
+ *
+ * And the old drivers/macintosh/rtc.c which was heavily based on:
+ * Linux/SPARC Real Time Clock Driver
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ *
+ * With additional work by Paul Mackerras and Franz Sirl.
+ */
+
+#ifndef __ASM_POWERPC_RTC_H__
+#define __ASM_POWERPC_RTC_H__
+
+#ifdef __KERNEL__
+
+#include <linux/rtc.h>
+
+#include <asm/machdep.h>
+#include <asm/time.h>
+
+#define RTC_PIE 0x40            /* periodic interrupt enable */
+#define RTC_AIE 0x20            /* alarm interrupt enable */
+#define RTC_UIE 0x10            /* update-finished interrupt enable */
+
+/* some dummy definitions */
+#define RTC_BATT_BAD 0x100      /* battery bad */
+#define RTC_SQWE 0x08           /* enable square-wave output */
+#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
+#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
+
+static inline unsigned int get_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.get_rtc_time)
+                ppc_md.get_rtc_time(time);
+        return RTC_24H;
+}
+
+/* Set the current date and time in the real time clock. */
+static inline int set_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.set_rtc_time)
+                return ppc_md.set_rtc_time(time);
+        return -EINVAL;
+}
+
+static inline unsigned int get_rtc_ss(void)
+{
+        struct rtc_time h;
+
+        get_rtc_time(&h);
+        return h.tm_sec;
+}
+
+static inline int get_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+static inline int set_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_RTC_H__ */
diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h
new file mode 100644
index 000000000000..24cd9281ec37
--- /dev/null
+++ b/arch/powerpc/include/asm/rwsem.h
@@ -0,0 +1,173 @@
+#ifndef _ASM_POWERPC_RWSEM_H
+#define _ASM_POWERPC_RWSEM_H
+
+#ifndef _LINUX_RWSEM_H
+#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
+#endif
+
+#ifdef __KERNEL__
+
+/*
+ * R/W semaphores for PPC using the stuff in lib/rwsem.c.
+ * Adapted largely from include/asm-i386/rwsem.h
+ * by Paul Mackerras <paulus@samba.org>.
+ */
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+
+/*
+ * the semaphore definition
+ */
+struct rw_semaphore {
+        /* XXX this should be able to be an atomic_t  -- paulus */
+        signed int              count;
+#define RWSEM_UNLOCKED_VALUE            0x00000000
+#define RWSEM_ACTIVE_BIAS               0x00000001
+#define RWSEM_ACTIVE_MASK               0x0000ffff
+#define RWSEM_WAITING_BIAS              (-0x00010000)
+#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+        { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
+          LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
+
+#define DECLARE_RWSEM(name)             \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                                 \
+        do {                                            \
+                static struct lock_class_key __key;     \
+                                                        \
+                __init_rwsem((sem), #sem, &__key);      \
+        } while (0)
+
+/*
+ * lock for reading
+ */
+static inline void __down_read(struct rw_semaphore *sem)
+{
+        if (unlikely(atomic_inc_return((atomic_t *)(&sem->count)) <= 0))
+                rwsem_down_read_failed(sem);
+}
+
+static inline int __down_read_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        while ((tmp = sem->count) >= 0) {
+                if (tmp == cmpxchg(&sem->count, tmp,
+                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/*
+ * lock for writing
+ */
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        int tmp;
+
+        tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
+                                (atomic_t *)(&sem->count));
+        if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
+                rwsem_down_write_failed(sem);
+}
+
+static inline void __down_write(struct rw_semaphore *sem)
+{
+        __down_write_nested(sem, 0);
+}
+
+static inline int __down_write_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
+                      RWSEM_ACTIVE_WRITE_BIAS);
+        return tmp == RWSEM_UNLOCKED_VALUE;
+}
+
+/*
+ * unlock after reading
+ */
+static inline void __up_read(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = atomic_dec_return((atomic_t *)(&sem->count));
+        if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
+                rwsem_wake(sem);
+}
+
+/*
+ * unlock after writing
+ */
+static inline void __up_write(struct rw_semaphore *sem)
+{
+        if (unlikely(atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
+                              (atomic_t *)(&sem->count)) < 0))
+                rwsem_wake(sem);
+}
+
+/*
+ * implement atomic add functionality
+ */
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+{
+        atomic_add(delta, (atomic_t *)(&sem->count));
+}
+
+/*
+ * downgrade write lock to read lock
+ */
+static inline void __downgrade_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
+        if (tmp < 0)
+                rwsem_downgrade_wake(sem);
+}
+
+/*
+ * implement exchange and add functionality
+ */
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+{
+        return atomic_add_return(delta, (atomic_t *)(&sem->count));
+}
+
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_RWSEM_H */
diff --git a/arch/powerpc/include/asm/scatterlist.h b/arch/powerpc/include/asm/scatterlist.h
new file mode 100644
index 000000000000..fcf7d55afe45
--- /dev/null
+++ b/arch/powerpc/include/asm/scatterlist.h
@@ -0,0 +1,50 @@
+#ifndef _ASM_POWERPC_SCATTERLIST_H
+#define _ASM_POWERPC_SCATTERLIST_H
+/*
+ * Copyright (C) 2001 PPC64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#include <asm/dma.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+        unsigned long sg_magic;
+#endif
+        unsigned long page_link;
+        unsigned int offset;
+        unsigned int length;
+
+        /* For TCE support */
+        dma_addr_t dma_address;
+        u32 dma_length;
+};
+
+/*
+ * These macros should be used after a dma_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#ifdef __powerpc64__
+#define sg_dma_len(sg)          ((sg)->dma_length)
+#else
+#define sg_dma_len(sg)          ((sg)->length)
+#endif
+
+#ifdef __powerpc64__
+#define ISA_DMA_THRESHOLD       (~0UL)
+#endif
+
+#define ARCH_HAS_SG_CHAIN
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SCATTERLIST_H */
diff --git a/arch/powerpc/include/asm/seccomp.h b/arch/powerpc/include/asm/seccomp.h
new file mode 100644
index 000000000000..853765eb1f65
--- /dev/null
+++ b/arch/powerpc/include/asm/seccomp.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_POWERPC_SECCOMP_H
+#define _ASM_POWERPC_SECCOMP_H
+
+#ifdef __KERNEL__
+#include <linux/thread_info.h>
+#endif
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#define __NR_seccomp_read_32 __NR_read
+#define __NR_seccomp_write_32 __NR_write
+#define __NR_seccomp_exit_32 __NR_exit
+#define __NR_seccomp_sigreturn_32 __NR_sigreturn
+
+#endif  /* _ASM_POWERPC_SECCOMP_H */
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
new file mode 100644
index 000000000000..916018e425c4
--- /dev/null
+++ b/arch/powerpc/include/asm/sections.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_POWERPC_SECTIONS_H
+#define _ASM_POWERPC_SECTIONS_H
+#ifdef __KERNEL__
+
+#include <asm-generic/sections.h>
+
+#ifdef __powerpc64__
+
+extern char _end[];
+
+static inline int in_kernel_text(unsigned long addr)
+{
+        if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end)
+                return 1;
+
+        return 0;
+}
+
+#endif
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_SECTIONS_H */
diff --git a/arch/powerpc/include/asm/sembuf.h b/arch/powerpc/include/asm/sembuf.h
new file mode 100644
index 000000000000..99a41938ae3d
--- /dev/null
+++ b/arch/powerpc/include/asm/sembuf.h
@@ -0,0 +1,36 @@
+#ifndef _ASM_POWERPC_SEMBUF_H
+#define _ASM_POWERPC_SEMBUF_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * The semid64_ds structure for PPC architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;     /* permissions .. see ipc.h */
+#ifndef __powerpc64__
+        unsigned long   __unused1;
+#endif
+        __kernel_time_t sem_otime;      /* last semop time */
+#ifndef __powerpc64__
+        unsigned long   __unused2;
+#endif
+        __kernel_time_t sem_ctime;      /* last change time */
+        unsigned long   sem_nsems;      /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif  /* _ASM_POWERPC_SEMBUF_H */
diff --git a/arch/powerpc/include/asm/serial.h b/arch/powerpc/include/asm/serial.h
new file mode 100644
index 000000000000..3e8589b43cb2
--- /dev/null
+++ b/arch/powerpc/include/asm/serial.h
@@ -0,0 +1,24 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_SERIAL_H
+#define _ASM_POWERPC_SERIAL_H
+
+/*
+ * Serial ports are not listed here, because they are discovered
+ * through the device tree.
+ */
+
+/* Default baud base if not found in device-tree */
+#define BASE_BAUD ( 1843200 / 16 )
+
+#ifdef CONFIG_PPC_UDBG_16550
+extern void find_legacy_serial_ports(void);
+#else
+#define find_legacy_serial_ports()      do { } while (0)
+#endif
+
+#endif /* _PPC64_SERIAL_H */
diff --git a/arch/powerpc/include/asm/setjmp.h b/arch/powerpc/include/asm/setjmp.h
new file mode 100644
index 000000000000..279d03a1eec6
--- /dev/null
+++ b/arch/powerpc/include/asm/setjmp.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright © 2008 Michael Neuling IBM Corporation
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ */
+#ifndef _ASM_POWERPC_SETJMP_H
+#define _ASM_POWERPC_SETJMP_H
+
+#define JMP_BUF_LEN    23
+
+extern long setjmp(long *);
+extern void longjmp(long *, long);
+
+#endif /* _ASM_POWERPC_SETJMP_H */
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
new file mode 100644
index 000000000000..817fac0a0714
--- /dev/null
+++ b/arch/powerpc/include/asm/setup.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_POWERPC_SETUP_H
+#define _ASM_POWERPC_SETUP_H
+
+#define COMMAND_LINE_SIZE       512
+
+#endif  /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/include/asm/shmbuf.h b/arch/powerpc/include/asm/shmbuf.h
new file mode 100644
index 000000000000..8efa39698b6c
--- /dev/null
+++ b/arch/powerpc/include/asm/shmbuf.h
@@ -0,0 +1,59 @@
+#ifndef _ASM_POWERPC_SHMBUF_H
+#define _ASM_POWERPC_SHMBUF_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * The shmid64_ds structure for PPC architecture.
+ *
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+#ifndef __powerpc64__
+        unsigned long           __unused1;
+#endif
+        __kernel_time_t         shm_atime;      /* last attach time */
+#ifndef __powerpc64__
+        unsigned long           __unused2;
+#endif
+        __kernel_time_t         shm_dtime;      /* last detach time */
+#ifndef __powerpc64__
+        unsigned long           __unused3;
+#endif
+        __kernel_time_t         shm_ctime;      /* last change time */
+#ifndef __powerpc64__
+        unsigned long           __unused4;
+#endif
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused5;
+        unsigned long           __unused6;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif  /* _ASM_POWERPC_SHMBUF_H */
diff --git a/arch/powerpc/include/asm/shmparam.h b/arch/powerpc/include/asm/shmparam.h
new file mode 100644
index 000000000000..5cda42a6d39e
--- /dev/null
+++ b/arch/powerpc/include/asm/shmparam.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_POWERPC_SHMPARAM_H
+#define _ASM_POWERPC_SHMPARAM_H
+
+#define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
+
+#endif  /* _ASM_POWERPC_SHMPARAM_H */
diff --git a/arch/powerpc/include/asm/sigcontext.h b/arch/powerpc/include/asm/sigcontext.h
new file mode 100644
index 000000000000..9c1f24fd5d11
--- /dev/null
+++ b/arch/powerpc/include/asm/sigcontext.h
@@ -0,0 +1,87 @@
+#ifndef _ASM_POWERPC_SIGCONTEXT_H
+#define _ASM_POWERPC_SIGCONTEXT_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/compiler.h>
+#include <asm/ptrace.h>
+#ifdef __powerpc64__
+#include <asm/elf.h>
+#endif
+
+struct sigcontext {
+        unsigned long   _unused[4];
+        int             signal;
+#ifdef __powerpc64__
+        int             _pad0;
+#endif
+        unsigned long   handler;
+        unsigned long   oldmask;
+        struct pt_regs  __user *regs;
+#ifdef __powerpc64__
+        elf_gregset_t   gp_regs;
+        elf_fpregset_t  fp_regs;
+/*
+ * To maintain compatibility with current implementations the sigcontext is
+ * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
+ * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This
+ * allows the array of vector registers to be quadword aligned independent of
+ * the alignment of the containing sigcontext or ucontext. It is the
+ * responsibility of the code setting the sigcontext to set this pointer to
+ * either NULL (if this processor does not support the VMX feature) or the
+ * address of the first quadword within the allocated (vmx_reserve) area.
+ *
+ * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
+ * an array of 34 quadword entries (elf_vrregset_t).  The entries with
+ * indexes 0-31 contain the corresponding vector registers.  The entry with
+ * index 32 contains the vscr as the last word (offset 12) within the
+ * quadword.  This allows the vscr to be stored as either a quadword (since
+ * it must be copied via a vector register to/from storage) or as a word.
+ * The entry with index 33 contains the vrsave as the first word (offset 0)
+ * within the quadword.
+ *
+ * Part of the VSX data is stored here also by extending vmx_restore
+ * by an additional 32 double words.  Architecturally the layout of
+ * the VSR registers and how they overlap on top of the legacy FPR and
+ * VR registers is shown below:
+ *
+ *                    VSR doubleword 0               VSR doubleword 1
+ *           ----------------------------------------------------------------
+ *   VSR[0]  |             FPR[0]            |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[1]  |             FPR[1]            |                              |
+ *           ----------------------------------------------------------------
+ *           |              ...              |                              |
+ *           |              ...              |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[30] |             FPR[30]           |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[31] |             FPR[31]           |                              |
+ *           ----------------------------------------------------------------
+ *   VSR[32] |                             VR[0]                            |
+ *           ----------------------------------------------------------------
+ *   VSR[33] |                             VR[1]                            |
+ *           ----------------------------------------------------------------
+ *           |                              ...                             |
+ *           |                              ...                             |
+ *           ----------------------------------------------------------------
+ *   VSR[62] |                             VR[30]                           |
+ *           ----------------------------------------------------------------
+ *   VSR[63] |                             VR[31]                           |
+ *           ----------------------------------------------------------------
+ *
+ * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
+ * is stored at the start of vmx_reserve.  vmx_reserve is extended for
+ * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
+ * registers and vscr/vrsave.
+ */
+        elf_vrreg_t     __user *v_regs;
+        long            vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];
+#endif
+};
+
+#endif /* _ASM_POWERPC_SIGCONTEXT_H */
diff --git a/arch/powerpc/include/asm/siginfo.h b/arch/powerpc/include/asm/siginfo.h
new file mode 100644
index 000000000000..12f1bce037be
--- /dev/null
+++ b/arch/powerpc/include/asm/siginfo.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_POWERPC_SIGINFO_H
+#define _ASM_POWERPC_SIGINFO_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifdef __powerpc64__
+#    define __ARCH_SI_PREAMBLE_SIZE     (4 * sizeof(int))
+#    define SI_PAD_SIZE32               ((SI_MAX_SIZE/sizeof(int)) - 3)
+#endif
+
+#include <asm-generic/siginfo.h>
+
+/*
+ * SIGTRAP si_codes
+ */
+#define TRAP_BRANCH     (__SI_FAULT|3)  /* process taken branch trap */
+#define TRAP_HWBKPT     (__SI_FAULT|4)  /* hardware breakpoint or watchpoint */
+#undef NSIGTRAP
+#define NSIGTRAP        4
+
+#endif  /* _ASM_POWERPC_SIGINFO_H */
diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h
new file mode 100644
index 000000000000..a7360cdd99eb
--- /dev/null
+++ b/arch/powerpc/include/asm/signal.h
@@ -0,0 +1,150 @@
+#ifndef _ASM_POWERPC_SIGNAL_H
+#define _ASM_POWERPC_SIGNAL_H
+
+#include <linux/types.h>
+
+#define _NSIG           64
+#ifdef __powerpc64__
+#define _NSIG_BPW       64
+#else
+#define _NSIG_BPW       32
+#endif
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001U
+#define SA_NOCLDWAIT    0x00000002U
+#define SA_SIGINFO      0x00000004U
+#define SA_ONSTACK      0x08000000U
+#define SA_RESTART      0x10000000U
+#define SA_NODEFER      0x40000000U
+#define SA_RESETHAND    0x80000000U
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000U
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#include <asm-generic/signal.h>
+
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        __sigrestore_t sa_restorer;
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        __sigrestore_t sa_restorer;
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+struct pt_regs;
+extern void do_signal(struct pt_regs *regs, unsigned long thread_info_flags);
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+#endif /* __KERNEL__ */
+
+#ifndef __powerpc64__
+/*
+ * These are parameters to dbg_sigreturn syscall.  They enable or
+ * disable certain debugging things that can be done from signal
+ * handlers.  The dbg_sigreturn syscall *must* be called from a
+ * SA_SIGINFO signal so the ucontext can be passed to it.  It takes an
+ * array of struct sig_dbg_op, which has the debug operations to
+ * perform before returning from the signal.
+ */
+struct sig_dbg_op {
+        int dbg_type;
+        unsigned long dbg_value;
+};
+
+/* Enable or disable single-stepping.  The value sets the state. */
+#define SIG_DBG_SINGLE_STEPPING         1
+
+/* Enable or disable branch tracing.  The value sets the state. */
+#define SIG_DBG_BRANCH_TRACING          2
+#endif /* ! __powerpc64__ */
+
+#endif /* _ASM_POWERPC_SIGNAL_H */
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
new file mode 100644
index 000000000000..4d28e1e4521b
--- /dev/null
+++ b/arch/powerpc/include/asm/smp.h
@@ -0,0 +1,127 @@
+/* 
+ * smp.h: PowerPC-specific SMP code.
+ *
+ * Original was a copy of sparc smp.h.  Now heavily modified
+ * for PPC.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_POWERPC_SMP_H
+#define _ASM_POWERPC_SMP_H
+#ifdef __KERNEL__
+
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/kernel.h>
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+#endif
+#include <asm/percpu.h>
+
+extern int boot_cpuid;
+
+extern void cpu_die(void);
+
+#ifdef CONFIG_SMP
+
+extern void smp_send_debugger_break(int cpu);
+extern void smp_message_recv(int);
+
+DECLARE_PER_CPU(unsigned int, pvr);
+
+#ifdef CONFIG_HOTPLUG_CPU
+extern void fixup_irqs(cpumask_t map);
+int generic_cpu_disable(void);
+int generic_cpu_enable(unsigned int cpu);
+void generic_cpu_die(unsigned int cpu);
+void generic_mach_cpu_die(void);
+#endif
+
+#ifdef CONFIG_PPC64
+#define raw_smp_processor_id()  (local_paca->paca_index)
+#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
+#else
+/* 32-bit */
+extern int smp_hw_index[];
+
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
+#define hard_smp_processor_id()         (smp_hw_index[smp_processor_id()])
+#define get_hard_smp_processor_id(cpu)  (smp_hw_index[(cpu)])
+#define set_hard_smp_processor_id(cpu, phys)\
+                                        (smp_hw_index[(cpu)] = (phys))
+#endif
+
+DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
+DECLARE_PER_CPU(cpumask_t, cpu_core_map);
+extern int cpu_to_core_id(int cpu);
+
+/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
+ *
+ * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
+ * in /proc/interrupts will be wrong!!! --Troy */
+#define PPC_MSG_CALL_FUNCTION   0
+#define PPC_MSG_RESCHEDULE      1
+#define PPC_MSG_CALL_FUNC_SINGLE        2
+#define PPC_MSG_DEBUGGER_BREAK  3
+
+void smp_init_iSeries(void);
+void smp_init_pSeries(void);
+void smp_init_cell(void);
+void smp_init_celleb(void);
+void smp_setup_cpu_maps(void);
+void smp_setup_cpu_sibling_map(void);
+
+extern int __cpu_disable(void);
+extern void __cpu_die(unsigned int cpu);
+
+#else
+/* for UP */
+#define hard_smp_processor_id()         0
+#define smp_setup_cpu_maps()
+
+#endif /* CONFIG_SMP */
+
+#ifdef CONFIG_PPC64
+#define get_hard_smp_processor_id(CPU) (paca[(CPU)].hw_cpu_id)
+#define set_hard_smp_processor_id(CPU, VAL) \
+        do { (paca[(CPU)].hw_cpu_id = (VAL)); } while (0)
+
+extern void smp_release_cpus(void);
+
+#else
+/* 32-bit */
+#ifndef CONFIG_SMP
+extern int boot_cpuid_phys;
+#define get_hard_smp_processor_id(cpu)  boot_cpuid_phys
+#define set_hard_smp_processor_id(cpu, phys)
+#endif
+#endif
+
+extern int smt_enabled_at_boot;
+
+extern int smp_mpic_probe(void);
+extern void smp_mpic_setup_cpu(int cpu);
+extern void smp_generic_kick_cpu(int nr);
+
+extern void smp_generic_give_timebase(void);
+extern void smp_generic_take_timebase(void);
+
+extern struct smp_ops_t *smp_ops;
+
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SMP_H) */
diff --git a/arch/powerpc/include/asm/smu.h b/arch/powerpc/include/asm/smu.h
new file mode 100644
index 000000000000..7ae2753da565
--- /dev/null
+++ b/arch/powerpc/include/asm/smu.h
@@ -0,0 +1,700 @@
+#ifndef _SMU_H
+#define _SMU_H
+
+/*
+ * Definitions for talking to the SMU chip in newer G5 PowerMacs
+ */
+#ifdef __KERNEL__
+#include <linux/list.h>
+#endif
+#include <linux/types.h>
+
+/*
+ * Known SMU commands
+ *
+ * Most of what is below comes from looking at the Open Firmware driver,
+ * though this is still incomplete and could use better documentation here
+ * or there...
+ */
+
+
+/*
+ * Partition info commands
+ *
+ * These commands are used to retrieve the sdb-partition-XX datas from
+ * the SMU. The length is always 2. First byte is the subcommand code
+ * and second byte is the partition ID.
+ *
+ * The reply is 6 bytes:
+ *
+ *  - 0..1 : partition address
+ *  - 2    : a byte containing the partition ID
+ *  - 3    : length (maybe other bits are rest of header ?)
+ *
+ * The data must then be obtained with calls to another command:
+ * SMU_CMD_MISC_ee_GET_DATABLOCK_REC (described below).
+ */
+#define SMU_CMD_PARTITION_COMMAND               0x3e
+#define   SMU_CMD_PARTITION_LATEST              0x01
+#define   SMU_CMD_PARTITION_BASE                0x02
+#define   SMU_CMD_PARTITION_UPDATE              0x03
+
+
+/*
+ * Fan control
+ *
+ * This is a "mux" for fan control commands. The command seem to
+ * act differently based on the number of arguments. With 1 byte
+ * of argument, this seem to be queries for fans status, setpoint,
+ * etc..., while with 0xe arguments, we will set the fans speeds.
+ *
+ * Queries (1 byte arg):
+ * ---------------------
+ *
+ * arg=0x01: read RPM fans status
+ * arg=0x02: read RPM fans setpoint
+ * arg=0x11: read PWM fans status
+ * arg=0x12: read PWM fans setpoint
+ *
+ * the "status" queries return the current speed while the "setpoint" ones
+ * return the programmed/target speed. It _seems_ that the result is a bit
+ * mask in the first byte of active/available fans, followed by 6 words (16
+ * bits) containing the requested speed.
+ *
+ * Setpoint (14 bytes arg):
+ * ------------------------
+ *
+ * first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the
+ * mask of fans affected by the command. Followed by 6 words containing the
+ * setpoint value for selected fans in the mask (or 0 if mask value is 0)
+ */
+#define SMU_CMD_FAN_COMMAND                     0x4a
+
+
+/*
+ * Battery access
+ *
+ * Same command number as the PMU, could it be same syntax ?
+ */
+#define SMU_CMD_BATTERY_COMMAND                 0x6f
+#define   SMU_CMD_GET_BATTERY_INFO              0x00
+
+/*
+ * Real time clock control
+ *
+ * This is a "mux", first data byte contains the "sub" command.
+ * The "RTC" part of the SMU controls the date, time, powerup
+ * timer, but also a PRAM
+ *
+ * Dates are in BCD format on 7 bytes:
+ * [sec] [min] [hour] [weekday] [month day] [month] [year]
+ * with month being 1 based and year minus 100
+ */
+#define SMU_CMD_RTC_COMMAND                     0x8e
+#define   SMU_CMD_RTC_SET_PWRUP_TIMER           0x00 /* i: 7 bytes date */
+#define   SMU_CMD_RTC_GET_PWRUP_TIMER           0x01 /* o: 7 bytes date */
+#define   SMU_CMD_RTC_STOP_PWRUP_TIMER          0x02
+#define   SMU_CMD_RTC_SET_PRAM_BYTE_ACC         0x20 /* i: 1 byte (address?) */
+#define   SMU_CMD_RTC_SET_PRAM_AUTOINC          0x21 /* i: 1 byte (data?) */
+#define   SMU_CMD_RTC_SET_PRAM_LO_BYTES         0x22 /* i: 10 bytes */
+#define   SMU_CMD_RTC_SET_PRAM_HI_BYTES         0x23 /* i: 10 bytes */
+#define   SMU_CMD_RTC_GET_PRAM_BYTE             0x28 /* i: 1 bytes (address?) */
+#define   SMU_CMD_RTC_GET_PRAM_LO_BYTES         0x29 /* o: 10 bytes */
+#define   SMU_CMD_RTC_GET_PRAM_HI_BYTES         0x2a /* o: 10 bytes */
+#define   SMU_CMD_RTC_SET_DATETIME              0x80 /* i: 7 bytes date */
+#define   SMU_CMD_RTC_GET_DATETIME              0x81 /* o: 7 bytes date */
+
+ /*
+  * i2c commands
+  *
+  * To issue an i2c command, first is to send a parameter block to the
+  * the SMU. This is a command of type 0x9a with 9 bytes of header
+  * eventually followed by data for a write:
+  *
+  * 0: bus number (from device-tree usually, SMU has lots of busses !)
+  * 1: transfer type/format (see below)
+  * 2: device address. For combined and combined4 type transfers, this
+  *    is the "write" version of the address (bit 0x01 cleared)
+  * 3: subaddress length (0..3)
+  * 4: subaddress byte 0 (or only byte for subaddress length 1)
+  * 5: subaddress byte 1
+  * 6: subaddress byte 2
+  * 7: combined address (device address for combined mode data phase)
+  * 8: data length
+  *
+  * The transfer types are the same good old Apple ones it seems,
+  * that is:
+  *   - 0x00: Simple transfer
+  *   - 0x01: Subaddress transfer (addr write + data tx, no restart)
+  *   - 0x02: Combined transfer (addr write + restart + data tx)
+  *
+  * This is then followed by actual data for a write.
+  *
+  * At this point, the OF driver seems to have a limitation on transfer
+  * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
+  * wether this is just an OF limit due to some temporary buffer size
+  * or if this is an SMU imposed limit. This driver has the same limitation
+  * for now as I use a 0x10 bytes temporary buffer as well
+  *
+  * Once that is completed, a response is expected from the SMU. This is
+  * obtained via a command of type 0x9a with a length of 1 byte containing
+  * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
+  * though I can't tell yet if this is actually necessary. Once this command
+  * is complete, at this point, all I can tell is what OF does. OF tests
+  * byte 0 of the reply:
+  *   - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
+  *   - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
+  *   - on write, < 0 -> failure (immediate exit)
+  *   - else, OF just exists (without error, weird)
+  *
+  * So on read, there is this wait-for-busy thing when getting a 0xfc or
+  * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
+  * doing the above again until either the retries expire or the result
+  * is no longer 0xfe or 0xfc
+  *
+  * The Darwin I2C driver is less subtle though. On any non-success status
+  * from the response command, it waits 5ms and tries again up to 20 times,
+  * it doesn't differenciate between fatal errors or "busy" status.
+  *
+  * This driver provides an asynchronous paramblock based i2c command
+  * interface to be used either directly by low level code or by a higher
+  * level driver interfacing to the linux i2c layer. The current
+  * implementation of this relies on working timers & timer interrupts
+  * though, so be careful of calling context for now. This may be "fixed"
+  * in the future by adding a polling facility.
+  */
+#define SMU_CMD_I2C_COMMAND                     0x9a
+          /* transfer types */
+#define   SMU_I2C_TRANSFER_SIMPLE       0x00
+#define   SMU_I2C_TRANSFER_STDSUB       0x01
+#define   SMU_I2C_TRANSFER_COMBINED     0x02
+
+/*
+ * Power supply control
+ *
+ * The "sub" command is an ASCII string in the data, the
+ * data length is that of the string.
+ *
+ * The VSLEW command can be used to get or set the voltage slewing.
+ *  - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
+ *    reply at data offset 6, 7 and 8.
+ *  - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
+ *    used to set the voltage slewing point. The SMU replies with "DONE"
+ * I yet have to figure out their exact meaning of those 3 bytes in
+ * both cases. They seem to be:
+ *  x = processor mask
+ *  y = op. point index
+ *  z = processor freq. step index
+ * I haven't yet decyphered result codes
+ *
+ */
+#define SMU_CMD_POWER_COMMAND                   0xaa
+#define   SMU_CMD_POWER_RESTART                 "RESTART"
+#define   SMU_CMD_POWER_SHUTDOWN                "SHUTDOWN"
+#define   SMU_CMD_POWER_VOLTAGE_SLEW            "VSLEW"
+
+/*
+ * Read ADC sensors
+ *
+ * This command takes one byte of parameter: the sensor ID (or "reg"
+ * value in the device-tree) and returns a 16 bits value
+ */
+#define SMU_CMD_READ_ADC                        0xd8
+
+
+/* Misc commands
+ *
+ * This command seem to be a grab bag of various things
+ *
+ * Parameters:
+ *   1: subcommand
+ */
+#define SMU_CMD_MISC_df_COMMAND                 0xdf
+
+/*
+ * Sets "system ready" status
+ *
+ * I did not yet understand how it exactly works or what it does.
+ *
+ * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
+ * the same codebase for all OF versions. On PowerBooks, this command would
+ * enable the backlight. For the G5s, it only activates the front LED. However,
+ * don't take this for granted.
+ *
+ * Parameters:
+ *   2: status [0x00, 0x01 or 0x02]
+ */
+#define   SMU_CMD_MISC_df_SET_DISPLAY_LIT       0x02
+
+/*
+ * Sets mode of power switch.
+ *
+ * What this actually does is not yet known. Maybe it enables some interrupt.
+ *
+ * Parameters:
+ *   2: enable power switch? [0x00 or 0x01]
+ *   3 (optional): enable nmi? [0x00 or 0x01]
+ *
+ * Returns:
+ *   If parameter 2 is 0x00 and parameter 3 is not specified, returns wether
+ *   NMI is enabled. Otherwise unknown.
+ */
+#define   SMU_CMD_MISC_df_NMI_OPTION            0x04
+
+/* Sets LED dimm offset.
+ *
+ * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
+ * frequency) depends on current time. Therefore, the SMU needs to know the
+ * timezone.
+ *
+ * Parameters:
+ *   2-8: unknown (BCD coding)
+ */
+#define   SMU_CMD_MISC_df_DIMM_OFFSET           0x99
+
+
+/*
+ * Version info commands
+ *
+ * Parameters:
+ *   1 (optional): Specifies version part to retrieve
+ *
+ * Returns:
+ *   Version value
+ */
+#define SMU_CMD_VERSION_COMMAND                 0xea
+#define   SMU_VERSION_RUNNING                   0x00
+#define   SMU_VERSION_BASE                      0x01
+#define   SMU_VERSION_UPDATE                    0x02
+
+
+/*
+ * Switches
+ *
+ * These are switches whose status seems to be known to the SMU.
+ *
+ * Parameters:
+ *   none
+ *
+ * Result:
+ *   Switch bits (ORed, see below)
+ */
+#define SMU_CMD_SWITCHES                        0xdc
+
+/* Switches bits */
+#define SMU_SWITCH_CASE_CLOSED                  0x01
+#define SMU_SWITCH_AC_POWER                     0x04
+#define SMU_SWITCH_POWER_SWITCH                 0x08
+
+
+/*
+ * Misc commands
+ *
+ * This command seem to be a grab bag of various things
+ *
+ * SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to
+ * transfer blocks of data from the SMU. So far, I've decrypted it's
+ * usage to retrieve partition data. In order to do that, you have to
+ * break your transfer in "chunks" since that command cannot transfer
+ * more than a chunk at a time. The chunk size used by OF is 0xe bytes,
+ * but it seems that the darwin driver will let you do 0x1e bytes if
+ * your "PMU" version is >= 0x30. You can get the "PMU" version apparently
+ * either in the last 16 bits of property "smu-version-pmu" or as the 16
+ * bytes at offset 1 of "smu-version-info"
+ *
+ * For each chunk, the command takes 7 bytes of arguments:
+ *  byte 0: subcommand code (0x02)
+ *  byte 1: 0x04 (always, I don't know what it means, maybe the address
+ *                space to use or some other nicety. It's hard coded in OF)
+ *  byte 2..5: SMU address of the chunk (big endian 32 bits)
+ *  byte 6: size to transfer (up to max chunk size)
+ *
+ * The data is returned directly
+ */
+#define SMU_CMD_MISC_ee_COMMAND                 0xee
+#define   SMU_CMD_MISC_ee_GET_DATABLOCK_REC     0x02
+
+/* Retrieves currently used watts.
+ *
+ * Parameters:
+ *   1: 0x03 (Meaning unknown)
+ */
+#define   SMU_CMD_MISC_ee_GET_WATTS             0x03
+
+#define   SMU_CMD_MISC_ee_LEDS_CTRL             0x04 /* i: 00 (00,01) [00] */
+#define   SMU_CMD_MISC_ee_GET_DATA              0x05 /* i: 00 , o: ?? */
+
+
+/*
+ * Power related commands
+ *
+ * Parameters:
+ *   1: subcommand
+ */
+#define SMU_CMD_POWER_EVENTS_COMMAND            0x8f
+
+/* SMU_POWER_EVENTS subcommands */
+enum {
+        SMU_PWR_GET_POWERUP_EVENTS      = 0x00,
+        SMU_PWR_SET_POWERUP_EVENTS      = 0x01,
+        SMU_PWR_CLR_POWERUP_EVENTS      = 0x02,
+        SMU_PWR_GET_WAKEUP_EVENTS       = 0x03,
+        SMU_PWR_SET_WAKEUP_EVENTS       = 0x04,
+        SMU_PWR_CLR_WAKEUP_EVENTS       = 0x05,
+
+        /*
+         * Get last shutdown cause
+         *
+         * Returns:
+         *   1 byte (signed char): Last shutdown cause. Exact meaning unknown.
+         */
+        SMU_PWR_LAST_SHUTDOWN_CAUSE     = 0x07,
+
+        /*
+         * Sets or gets server ID. Meaning or use is unknown.
+         *
+         * Parameters:
+         *   2 (optional): Set server ID (1 byte)
+         *
+         * Returns:
+         *   1 byte (server ID?)
+         */
+        SMU_PWR_SERVER_ID               = 0x08,
+};
+
+/* Power events wakeup bits */
+enum {
+        SMU_PWR_WAKEUP_KEY              = 0x01, /* Wake on key press */
+        SMU_PWR_WAKEUP_AC_INSERT        = 0x02, /* Wake on AC adapter plug */
+        SMU_PWR_WAKEUP_AC_CHANGE        = 0x04,
+        SMU_PWR_WAKEUP_LID_OPEN         = 0x08,
+        SMU_PWR_WAKEUP_RING             = 0x10,
+};
+
+
+/*
+ * - Kernel side interface -
+ */
+
+#ifdef __KERNEL__
+
+/*
+ * Asynchronous SMU commands
+ *
+ * Fill up this structure and submit it via smu_queue_command(),
+ * and get notified by the optional done() callback, or because
+ * status becomes != 1
+ */
+
+struct smu_cmd;
+
+struct smu_cmd
+{
+        /* public */
+        u8                      cmd;            /* command */
+        int                     data_len;       /* data len */
+        int                     reply_len;      /* reply len */
+        void                    *data_buf;      /* data buffer */
+        void                    *reply_buf;     /* reply buffer */
+        int                     status;         /* command status */
+        void                    (*done)(struct smu_cmd *cmd, void *misc);
+        void                    *misc;
+
+        /* private */
+        struct list_head        link;
+};
+
+/*
+ * Queues an SMU command, all fields have to be initialized
+ */
+extern int smu_queue_cmd(struct smu_cmd *cmd);
+
+/*
+ * Simple command wrapper. This structure embeds a small buffer
+ * to ease sending simple SMU commands from the stack
+ */
+struct smu_simple_cmd
+{
+        struct smu_cmd  cmd;
+        u8              buffer[16];
+};
+
+/*
+ * Queues a simple command. All fields will be initialized by that
+ * function
+ */
+extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
+                            unsigned int data_len,
+                            void (*done)(struct smu_cmd *cmd, void *misc),
+                            void *misc,
+                            ...);
+
+/*
+ * Completion helper. Pass it to smu_queue_simple or as 'done'
+ * member to smu_queue_cmd, it will call complete() on the struct
+ * completion passed in the "misc" argument
+ */
+extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
+
+/*
+ * Synchronous helpers. Will spin-wait for completion of a command
+ */
+extern void smu_spinwait_cmd(struct smu_cmd *cmd);
+
+static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
+{
+        smu_spinwait_cmd(&scmd->cmd);
+}
+
+/*
+ * Poll routine to call if blocked with irqs off
+ */
+extern void smu_poll(void);
+
+
+/*
+ * Init routine, presence check....
+ */
+extern int smu_init(void);
+extern int smu_present(void);
+struct of_device;
+extern struct of_device *smu_get_ofdev(void);
+
+
+/*
+ * Common command wrappers
+ */
+extern void smu_shutdown(void);
+extern void smu_restart(void);
+struct rtc_time;
+extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
+extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
+
+/*
+ * SMU command buffer absolute address, exported by pmac_setup,
+ * this is allocated very early during boot.
+ */
+extern unsigned long smu_cmdbuf_abs;
+
+
+/*
+ * Kenrel asynchronous i2c interface
+ */
+
+#define SMU_I2C_READ_MAX        0x1d
+#define SMU_I2C_WRITE_MAX       0x15
+
+/* SMU i2c header, exactly matches i2c header on wire */
+struct smu_i2c_param
+{
+        u8      bus;            /* SMU bus ID (from device tree) */
+        u8      type;           /* i2c transfer type */
+        u8      devaddr;        /* device address (includes direction) */
+        u8      sublen;         /* subaddress length */
+        u8      subaddr[3];     /* subaddress */
+        u8      caddr;          /* combined address, filled by SMU driver */
+        u8      datalen;        /* length of transfer */
+        u8      data[SMU_I2C_READ_MAX]; /* data */
+};
+
+struct smu_i2c_cmd
+{
+        /* public */
+        struct smu_i2c_param    info;
+        void                    (*done)(struct smu_i2c_cmd *cmd, void *misc);
+        void                    *misc;
+        int                     status; /* 1 = pending, 0 = ok, <0 = fail */
+
+        /* private */
+        struct smu_cmd          scmd;
+        int                     read;
+        int                     stage;
+        int                     retries;
+        u8                      pdata[32];
+        struct list_head        link;
+};
+
+/*
+ * Call this to queue an i2c command to the SMU. You must fill info,
+ * including info.data for a write, done and misc.
+ * For now, no polling interface is provided so you have to use completion
+ * callback.
+ */
+extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
+
+
+#endif /* __KERNEL__ */
+
+
+/*
+ * - SMU "sdb" partitions informations -
+ */
+
+
+/*
+ * Partition header format
+ */
+struct smu_sdbp_header {
+        __u8    id;
+        __u8    len;
+        __u8    version;
+        __u8    flags;
+};
+
+
+ /*
+ * demangle 16 and 32 bits integer in some SMU partitions
+ * (currently, afaik, this concerns only the FVT partition
+ * (0x12)
+ */
+#define SMU_U16_MIX(x)  le16_to_cpu(x);
+#define SMU_U32_MIX(x)  ((((x) & 0xff00ff00u) >> 8)|(((x) & 0x00ff00ffu) << 8))
+
+
+/* This is the definition of the SMU sdb-partition-0x12 table (called
+ * CPU F/V/T operating points in Darwin). The definition for all those
+ * SMU tables should be moved to some separate file
+ */
+#define SMU_SDB_FVT_ID                  0x12
+
+struct smu_sdbp_fvt {
+        __u32   sysclk;                 /* Base SysClk frequency in Hz for
+                                         * this operating point. Value need to
+                                         * be unmixed with SMU_U32_MIX()
+                                         */
+        __u8    pad;
+        __u8    maxtemp;                /* Max temp. supported by this
+                                         * operating point
+                                         */
+
+        __u16   volts[3];               /* CPU core voltage for the 3
+                                         * PowerTune modes, a mode with
+                                         * 0V = not supported. Value need
+                                         * to be unmixed with SMU_U16_MIX()
+                                         */
+};
+
+/* This partition contains voltage & current sensor calibration
+ * informations
+ */
+#define SMU_SDB_CPUVCP_ID               0x21
+
+struct smu_sdbp_cpuvcp {
+        __u16   volt_scale;             /* u4.12 fixed point */
+        __s16   volt_offset;            /* s4.12 fixed point */
+        __u16   curr_scale;             /* u4.12 fixed point */
+        __s16   curr_offset;            /* s4.12 fixed point */
+        __s32   power_quads[3];         /* s4.28 fixed point */
+};
+
+/* This partition contains CPU thermal diode calibration
+ */
+#define SMU_SDB_CPUDIODE_ID             0x18
+
+struct smu_sdbp_cpudiode {
+        __u16   m_value;                /* u1.15 fixed point */
+        __s16   b_value;                /* s10.6 fixed point */
+
+};
+
+/* This partition contains Slots power calibration
+ */
+#define SMU_SDB_SLOTSPOW_ID             0x78
+
+struct smu_sdbp_slotspow {
+        __u16   pow_scale;              /* u4.12 fixed point */
+        __s16   pow_offset;             /* s4.12 fixed point */
+};
+
+/* This partition contains machine specific version information about
+ * the sensor/control layout
+ */
+#define SMU_SDB_SENSORTREE_ID           0x25
+
+struct smu_sdbp_sensortree {
+        __u8    model_id;
+        __u8    unknown[3];
+};
+
+/* This partition contains CPU thermal control PID informations. So far
+ * only single CPU machines have been seen with an SMU, so we assume this
+ * carries only informations for those
+ */
+#define SMU_SDB_CPUPIDDATA_ID           0x17
+
+struct smu_sdbp_cpupiddata {
+        __u8    unknown1;
+        __u8    target_temp_delta;
+        __u8    unknown2;
+        __u8    history_len;
+        __s16   power_adj;
+        __u16   max_power;
+        __s32   gp,gr,gd;
+};
+
+
+/* Other partitions without known structures */
+#define SMU_SDB_DEBUG_SWITCHES_ID       0x05
+
+#ifdef __KERNEL__
+/*
+ * This returns the pointer to an SMU "sdb" partition data or NULL
+ * if not found. The data format is described below
+ */
+extern const struct smu_sdbp_header *smu_get_sdb_partition(int id,
+                                        unsigned int *size);
+
+/* Get "sdb" partition data from an SMU satellite */
+extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id,
+                                        int id, unsigned int *size);
+
+
+#endif /* __KERNEL__ */
+
+
+/*
+ * - Userland interface -
+ */
+
+/*
+ * A given instance of the device can be configured for 2 different
+ * things at the moment:
+ *
+ *  - sending SMU commands (default at open() time)
+ *  - receiving SMU events (not yet implemented)
+ *
+ * Commands are written with write() of a command block. They can be
+ * "driver" commands (for example to switch to event reception mode)
+ * or real SMU commands. They are made of a header followed by command
+ * data if any.
+ *
+ * For SMU commands (not for driver commands), you can then read() back
+ * a reply. The reader will be blocked or not depending on how the device
+ * file is opened. poll() isn't implemented yet. The reply will consist
+ * of a header as well, followed by the reply data if any. You should
+ * always provide a buffer large enough for the maximum reply data, I
+ * recommand one page.
+ *
+ * It is illegal to send SMU commands through a file descriptor configured
+ * for events reception
+ *
+ */
+struct smu_user_cmd_hdr
+{
+        __u32           cmdtype;
+#define SMU_CMDTYPE_SMU                 0       /* SMU command */
+#define SMU_CMDTYPE_WANTS_EVENTS        1       /* switch fd to events mode */
+#define SMU_CMDTYPE_GET_PARTITION       2       /* retrieve an sdb partition */
+
+        __u8            cmd;                    /* SMU command byte */
+        __u8            pad[3];                 /* padding */
+        __u32           data_len;               /* Length of data following */
+};
+
+struct smu_user_reply_hdr
+{
+        __u32           status;                 /* Command status */
+        __u32           reply_len;              /* Length of data follwing */
+};
+
+#endif /*  _SMU_H */
diff --git a/arch/powerpc/include/asm/socket.h b/arch/powerpc/include/asm/socket.h
new file mode 100644
index 000000000000..f5a4e168e498
--- /dev/null
+++ b/arch/powerpc/include/asm/socket.h
@@ -0,0 +1,64 @@
+#ifndef _ASM_POWERPC_SOCKET_H
+#define _ASM_POWERPC_SOCKET_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_RCVLOWAT     16
+#define SO_SNDLOWAT     17
+#define SO_RCVTIMEO     18
+#define SO_SNDTIMEO     19
+#define SO_PASSCRED     20
+#define SO_PEERCRED     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC              31
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#endif  /* _ASM_POWERPC_SOCKET_H */
diff --git a/arch/powerpc/include/asm/sockios.h b/arch/powerpc/include/asm/sockios.h
new file mode 100644
index 000000000000..55cef7675a31
--- /dev/null
+++ b/arch/powerpc/include/asm/sockios.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_POWERPC_SOCKIOS_H
+#define _ASM_POWERPC_SOCKIOS_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif  /* _ASM_POWERPC_SOCKIOS_H */
diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
new file mode 100644
index 000000000000..54a47ea2c3aa
--- /dev/null
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -0,0 +1,32 @@
+#ifndef _ASM_POWERPC_SPARSEMEM_H
+#define _ASM_POWERPC_SPARSEMEM_H 1
+#ifdef __KERNEL__
+
+#ifdef CONFIG_SPARSEMEM
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSADDR_BITS            2^N: how much physical address space we have
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#define SECTION_SIZE_BITS       24
+
+#define MAX_PHYSADDR_BITS       44
+#define MAX_PHYSMEM_BITS        44
+
+#endif /* CONFIG_SPARSEMEM */
+
+#ifdef CONFIG_MEMORY_HOTPLUG
+extern void create_section_mapping(unsigned long start, unsigned long end);
+extern int remove_section_mapping(unsigned long start, unsigned long end);
+#ifdef CONFIG_NUMA
+extern int hot_add_scn_to_nid(unsigned long scn_addr);
+#else
+static inline int hot_add_scn_to_nid(unsigned long scn_addr)
+{
+        return 0;
+}
+#endif /* CONFIG_NUMA */
+#endif /* CONFIG_MEMORY_HOTPLUG */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SPARSEMEM_H */
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
new file mode 100644
index 000000000000..f56a843f4705
--- /dev/null
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -0,0 +1,295 @@
+#ifndef __ASM_SPINLOCK_H
+#define __ASM_SPINLOCK_H
+#ifdef __KERNEL__
+
+/*
+ * Simple spin lock operations.  
+ *
+ * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
+ * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
+ * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
+ *      Rework to support virtual processors
+ *
+ * Type of int is used as a full 64b word is not necessary.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * (the type definitions are in asm/spinlock_types.h)
+ */
+#include <linux/irqflags.h>
+#ifdef CONFIG_PPC64
+#include <asm/paca.h>
+#include <asm/hvcall.h>
+#include <asm/iseries/hv_call.h>
+#endif
+#include <asm/asm-compat.h>
+#include <asm/synch.h>
+
+#define __raw_spin_is_locked(x)         ((x)->slock != 0)
+
+#ifdef CONFIG_PPC64
+/* use 0x800000yy when locked, where yy == CPU number */
+#define LOCK_TOKEN      (*(u32 *)(&get_paca()->lock_token))
+#else
+#define LOCK_TOKEN      1
+#endif
+
+#if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
+#define CLEAR_IO_SYNC   (get_paca()->io_sync = 0)
+#define SYNC_IO         do {                                            \
+                                if (unlikely(get_paca()->io_sync)) {    \
+                                        mb();                           \
+                                        get_paca()->io_sync = 0;        \
+                                }                                       \
+                        } while (0)
+#else
+#define CLEAR_IO_SYNC
+#define SYNC_IO
+#endif
+
+/*
+ * This returns the old value in the lock, so we succeeded
+ * in getting the lock if the return value is 0.
+ */
+static inline unsigned long __spin_trylock(raw_spinlock_t *lock)
+{
+        unsigned long tmp, token;
+
+        token = LOCK_TOKEN;
+        __asm__ __volatile__(
+"1:     lwarx           %0,0,%2\n\
+        cmpwi           0,%0,0\n\
+        bne-            2f\n\
+        stwcx.          %1,0,%2\n\
+        bne-            1b\n\
+        isync\n\
+2:"     : "=&r" (tmp)
+        : "r" (token), "r" (&lock->slock)
+        : "cr0", "memory");
+
+        return tmp;
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+        CLEAR_IO_SYNC;
+        return __spin_trylock(lock) == 0;
+}
+
+/*
+ * On a system with shared processors (that is, where a physical
+ * processor is multiplexed between several virtual processors),
+ * there is no point spinning on a lock if the holder of the lock
+ * isn't currently scheduled on a physical processor.  Instead
+ * we detect this situation and ask the hypervisor to give the
+ * rest of our timeslice to the lock holder.
+ *
+ * So that we can tell which virtual processor is holding a lock,
+ * we put 0x80000000 | smp_processor_id() in the lock when it is
+ * held.  Conveniently, we have a word in the paca that holds this
+ * value.
+ */
+
+#if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
+/* We only yield to the hypervisor if we are in shared processor mode */
+#define SHARED_PROCESSOR (get_lppaca()->shared_proc)
+extern void __spin_yield(raw_spinlock_t *lock);
+extern void __rw_yield(raw_rwlock_t *lock);
+#else /* SPLPAR || ISERIES */
+#define __spin_yield(x) barrier()
+#define __rw_yield(x)   barrier()
+#define SHARED_PROCESSOR        0
+#endif
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+        CLEAR_IO_SYNC;
+        while (1) {
+                if (likely(__spin_trylock(lock) == 0))
+                        break;
+                do {
+                        HMT_low();
+                        if (SHARED_PROCESSOR)
+                                __spin_yield(lock);
+                } while (unlikely(lock->slock != 0));
+                HMT_medium();
+        }
+}
+
+static inline
+void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+{
+        unsigned long flags_dis;
+
+        CLEAR_IO_SYNC;
+        while (1) {
+                if (likely(__spin_trylock(lock) == 0))
+                        break;
+                local_save_flags(flags_dis);
+                local_irq_restore(flags);
+                do {
+                        HMT_low();
+                        if (SHARED_PROCESSOR)
+                                __spin_yield(lock);
+                } while (unlikely(lock->slock != 0));
+                HMT_medium();
+                local_irq_restore(flags_dis);
+        }
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+        SYNC_IO;
+        __asm__ __volatile__("# __raw_spin_unlock\n\t"
+                                LWSYNC_ON_SMP: : :"memory");
+        lock->slock = 0;
+}
+
+#ifdef CONFIG_PPC64
+extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
+#else
+#define __raw_spin_unlock_wait(lock) \
+        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+#endif
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+
+#define __raw_read_can_lock(rw)         ((rw)->lock >= 0)
+#define __raw_write_can_lock(rw)        (!(rw)->lock)
+
+#ifdef CONFIG_PPC64
+#define __DO_SIGN_EXTEND        "extsw  %0,%0\n"
+#define WRLOCK_TOKEN            LOCK_TOKEN      /* it's negative */
+#else
+#define __DO_SIGN_EXTEND
+#define WRLOCK_TOKEN            (-1)
+#endif
+
+/*
+ * This returns the old value in the lock + 1,
+ * so we got a read lock if the return value is > 0.
+ */
+static inline long __read_trylock(raw_rwlock_t *rw)
+{
+        long tmp;
+
+        __asm__ __volatile__(
+"1:     lwarx           %0,0,%1\n"
+        __DO_SIGN_EXTEND
+"       addic.          %0,%0,1\n\
+        ble-            2f\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.          %0,0,%1\n\
+        bne-            1b\n\
+        isync\n\
+2:"     : "=&r" (tmp)
+        : "r" (&rw->lock)
+        : "cr0", "xer", "memory");
+
+        return tmp;
+}
+
+/*
+ * This returns the old value in the lock,
+ * so we got the write lock if the return value is 0.
+ */
+static inline long __write_trylock(raw_rwlock_t *rw)
+{
+        long tmp, token;
+
+        token = WRLOCK_TOKEN;
+        __asm__ __volatile__(
+"1:     lwarx           %0,0,%2\n\
+        cmpwi           0,%0,0\n\
+        bne-            2f\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.          %1,0,%2\n\
+        bne-            1b\n\
+        isync\n\
+2:"     : "=&r" (tmp)
+        : "r" (token), "r" (&rw->lock)
+        : "cr0", "memory");
+
+        return tmp;
+}
+
+static inline void __raw_read_lock(raw_rwlock_t *rw)
+{
+        while (1) {
+                if (likely(__read_trylock(rw) > 0))
+                        break;
+                do {
+                        HMT_low();
+                        if (SHARED_PROCESSOR)
+                                __rw_yield(rw);
+                } while (unlikely(rw->lock < 0));
+                HMT_medium();
+        }
+}
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+        while (1) {
+                if (likely(__write_trylock(rw) == 0))
+                        break;
+                do {
+                        HMT_low();
+                        if (SHARED_PROCESSOR)
+                                __rw_yield(rw);
+                } while (unlikely(rw->lock != 0));
+                HMT_medium();
+        }
+}
+
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+        return __read_trylock(rw) > 0;
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+        return __write_trylock(rw) == 0;
+}
+
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
+{
+        long tmp;
+
+        __asm__ __volatile__(
+        "# read_unlock\n\t"
+        LWSYNC_ON_SMP
+"1:     lwarx           %0,0,%1\n\
+        addic           %0,%0,-1\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.          %0,0,%1\n\
+        bne-            1b"
+        : "=&r"(tmp)
+        : "r"(&rw->lock)
+        : "cr0", "memory");
+}
+
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+        __asm__ __volatile__("# write_unlock\n\t"
+                                LWSYNC_ON_SMP: : :"memory");
+        rw->lock = 0;
+}
+
+#define _raw_spin_relax(lock)   __spin_yield(lock)
+#define _raw_read_relax(lock)   __rw_yield(lock)
+#define _raw_write_relax(lock)  __rw_yield(lock)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SPINLOCK_H */
diff --git a/arch/powerpc/include/asm/spinlock_types.h b/arch/powerpc/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..74236c9f05b1
--- /dev/null
+++ b/arch/powerpc/include/asm/spinlock_types.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_POWERPC_SPINLOCK_TYPES_H
+#define _ASM_POWERPC_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        volatile unsigned int slock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+
+typedef struct {
+        volatile signed int lock;
+} raw_rwlock_t;
+
+#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+
+#endif
diff --git a/arch/powerpc/include/asm/spu.h b/arch/powerpc/include/asm/spu.h
new file mode 100644
index 000000000000..8b2eb044270a
--- /dev/null
+++ b/arch/powerpc/include/asm/spu.h
@@ -0,0 +1,732 @@
+/*
+ * SPU core / file system interface and HW structures
+ *
+ * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
+ *
+ * Author: Arnd Bergmann <arndb@de.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _SPU_H
+#define _SPU_H
+#ifdef __KERNEL__
+
+#include <linux/workqueue.h>
+#include <linux/sysdev.h>
+
+#define LS_SIZE (256 * 1024)
+#define LS_ADDR_MASK (LS_SIZE - 1)
+
+#define MFC_PUT_CMD             0x20
+#define MFC_PUTS_CMD            0x28
+#define MFC_PUTR_CMD            0x30
+#define MFC_PUTF_CMD            0x22
+#define MFC_PUTB_CMD            0x21
+#define MFC_PUTFS_CMD           0x2A
+#define MFC_PUTBS_CMD           0x29
+#define MFC_PUTRF_CMD           0x32
+#define MFC_PUTRB_CMD           0x31
+#define MFC_PUTL_CMD            0x24
+#define MFC_PUTRL_CMD           0x34
+#define MFC_PUTLF_CMD           0x26
+#define MFC_PUTLB_CMD           0x25
+#define MFC_PUTRLF_CMD          0x36
+#define MFC_PUTRLB_CMD          0x35
+
+#define MFC_GET_CMD             0x40
+#define MFC_GETS_CMD            0x48
+#define MFC_GETF_CMD            0x42
+#define MFC_GETB_CMD            0x41
+#define MFC_GETFS_CMD           0x4A
+#define MFC_GETBS_CMD           0x49
+#define MFC_GETL_CMD            0x44
+#define MFC_GETLF_CMD           0x46
+#define MFC_GETLB_CMD           0x45
+
+#define MFC_SDCRT_CMD           0x80
+#define MFC_SDCRTST_CMD         0x81
+#define MFC_SDCRZ_CMD           0x89
+#define MFC_SDCRS_CMD           0x8D
+#define MFC_SDCRF_CMD           0x8F
+
+#define MFC_GETLLAR_CMD         0xD0
+#define MFC_PUTLLC_CMD          0xB4
+#define MFC_PUTLLUC_CMD         0xB0
+#define MFC_PUTQLLUC_CMD        0xB8
+#define MFC_SNDSIG_CMD          0xA0
+#define MFC_SNDSIGB_CMD         0xA1
+#define MFC_SNDSIGF_CMD         0xA2
+#define MFC_BARRIER_CMD         0xC0
+#define MFC_EIEIO_CMD           0xC8
+#define MFC_SYNC_CMD            0xCC
+
+#define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
+#define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
+#define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
+#define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
+#define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
+#define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
+#define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
+#define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
+
+#define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
+
+/* Events for Channels 0-2 */
+#define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
+#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
+#define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
+#define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
+#define MFC_DECREMENTER_EVENT               0x00000020
+#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
+#define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
+#define MFC_SIGNAL_2_EVENT                  0x00000100
+#define MFC_SIGNAL_1_EVENT                  0x00000200
+#define MFC_LLR_LOST_EVENT                  0x00000400
+#define MFC_PRIV_ATTN_EVENT                 0x00000800
+#define MFC_MULTI_SRC_EVENT                 0x00001000
+
+/* Flag indicating progress during context switch. */
+#define SPU_CONTEXT_SWITCH_PENDING      0UL
+#define SPU_CONTEXT_FAULT_PENDING       1UL
+
+struct spu_context;
+struct spu_runqueue;
+struct spu_lscsa;
+struct device_node;
+
+enum spu_utilization_state {
+        SPU_UTIL_USER,
+        SPU_UTIL_SYSTEM,
+        SPU_UTIL_IOWAIT,
+        SPU_UTIL_IDLE_LOADED,
+        SPU_UTIL_MAX
+};
+
+struct spu {
+        const char *name;
+        unsigned long local_store_phys;
+        u8 *local_store;
+        unsigned long problem_phys;
+        struct spu_problem __iomem *problem;
+        struct spu_priv2 __iomem *priv2;
+        struct list_head cbe_list;
+        struct list_head full_list;
+        enum { SPU_FREE, SPU_USED } alloc_state;
+        int number;
+        unsigned int irqs[3];
+        u32 node;
+        u64 flags;
+        u64 class_0_pending;
+        u64 class_0_dar;
+        u64 class_1_dar;
+        u64 class_1_dsisr;
+        size_t ls_size;
+        unsigned int slb_replace;
+        struct mm_struct *mm;
+        struct spu_context *ctx;
+        struct spu_runqueue *rq;
+        unsigned long long timestamp;
+        pid_t pid;
+        pid_t tgid;
+        spinlock_t register_lock;
+
+        void (* wbox_callback)(struct spu *spu);
+        void (* ibox_callback)(struct spu *spu);
+        void (* stop_callback)(struct spu *spu, int irq);
+        void (* mfc_callback)(struct spu *spu);
+
+        char irq_c0[8];
+        char irq_c1[8];
+        char irq_c2[8];
+
+        u64 spe_id;
+
+        void* pdata; /* platform private data */
+
+        /* of based platforms only */
+        struct device_node *devnode;
+
+        /* native only */
+        struct spu_priv1 __iomem *priv1;
+
+        /* beat only */
+        u64 shadow_int_mask_RW[3];
+
+        struct sys_device sysdev;
+
+        int has_mem_affinity;
+        struct list_head aff_list;
+
+        struct {
+                /* protected by interrupt reentrancy */
+                enum spu_utilization_state util_state;
+                unsigned long long tstamp;
+                unsigned long long times[SPU_UTIL_MAX];
+                unsigned long long vol_ctx_switch;
+                unsigned long long invol_ctx_switch;
+                unsigned long long min_flt;
+                unsigned long long maj_flt;
+                unsigned long long hash_flt;
+                unsigned long long slb_flt;
+                unsigned long long class2_intr;
+                unsigned long long libassist;
+        } stats;
+};
+
+struct cbe_spu_info {
+        struct mutex list_mutex;
+        struct list_head spus;
+        int n_spus;
+        int nr_active;
+        atomic_t busy_spus;
+        atomic_t reserved_spus;
+};
+
+extern struct cbe_spu_info cbe_spu_info[];
+
+void spu_init_channels(struct spu *spu);
+void spu_irq_setaffinity(struct spu *spu, int cpu);
+
+void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
+                void *code, int code_size);
+
+#ifdef CONFIG_KEXEC
+void crash_register_spus(struct list_head *list);
+#else
+static inline void crash_register_spus(struct list_head *list)
+{
+}
+#endif
+
+extern void spu_invalidate_slbs(struct spu *spu);
+extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
+int spu_64k_pages_available(void);
+
+/* Calls from the memory management to the SPU */
+struct mm_struct;
+extern void spu_flush_all_slbs(struct mm_struct *mm);
+
+/* This interface allows a profiler (e.g., OProfile) to store a ref
+ * to spu context information that it creates.  This caching technique
+ * avoids the need to recreate this information after a save/restore operation.
+ *
+ * Assumes the caller has already incremented the ref count to
+ * profile_info; then spu_context_destroy must call kref_put
+ * on prof_info_kref.
+ */
+void spu_set_profile_private_kref(struct spu_context *ctx,
+                                  struct kref *prof_info_kref,
+                                  void ( * prof_info_release) (struct kref *kref));
+
+void *spu_get_profile_private_kref(struct spu_context *ctx);
+
+/* system callbacks from the SPU */
+struct spu_syscall_block {
+        u64 nr_ret;
+        u64 parm[6];
+};
+extern long spu_sys_callback(struct spu_syscall_block *s);
+
+/* syscalls implemented in spufs */
+struct file;
+struct spufs_calls {
+        long (*create_thread)(const char __user *name,
+                                        unsigned int flags, mode_t mode,
+                                        struct file *neighbor);
+        long (*spu_run)(struct file *filp, __u32 __user *unpc,
+                                                __u32 __user *ustatus);
+        int (*coredump_extra_notes_size)(void);
+        int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
+        void (*notify_spus_active)(void);
+        struct module *owner;
+};
+
+/* return status from spu_run, same as in libspe */
+#define SPE_EVENT_DMA_ALIGNMENT         0x0008  /*A DMA alignment error */
+#define SPE_EVENT_SPE_ERROR             0x0010  /*An illegal instruction error*/
+#define SPE_EVENT_SPE_DATA_SEGMENT      0x0020  /*A DMA segmentation error    */
+#define SPE_EVENT_SPE_DATA_STORAGE      0x0040  /*A DMA storage error */
+#define SPE_EVENT_INVALID_DMA           0x0800  /* Invalid MFC DMA */
+
+/*
+ * Flags for sys_spu_create.
+ */
+#define SPU_CREATE_EVENTS_ENABLED       0x0001
+#define SPU_CREATE_GANG                 0x0002
+#define SPU_CREATE_NOSCHED              0x0004
+#define SPU_CREATE_ISOLATE              0x0008
+#define SPU_CREATE_AFFINITY_SPU         0x0010
+#define SPU_CREATE_AFFINITY_MEM         0x0020
+
+#define SPU_CREATE_FLAG_ALL             0x003f /* mask of all valid flags */
+
+
+int register_spu_syscalls(struct spufs_calls *calls);
+void unregister_spu_syscalls(struct spufs_calls *calls);
+
+int spu_add_sysdev_attr(struct sysdev_attribute *attr);
+void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
+
+int spu_add_sysdev_attr_group(struct attribute_group *attrs);
+void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
+
+int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
+                unsigned long dsisr, unsigned *flt);
+
+/*
+ * Notifier blocks:
+ *
+ * oprofile can get notified when a context switch is performed
+ * on an spe. The notifer function that gets called is passed
+ * a pointer to the SPU structure as well as the object-id that
+ * identifies the binary running on that SPU now.
+ *
+ * For a context save, the object-id that is passed is zero,
+ * identifying that the kernel will run from that moment on.
+ *
+ * For a context restore, the object-id is the value written
+ * to object-id spufs file from user space and the notifer
+ * function can assume that spu->ctx is valid.
+ */
+struct notifier_block;
+int spu_switch_event_register(struct notifier_block * n);
+int spu_switch_event_unregister(struct notifier_block * n);
+
+extern void notify_spus_active(void);
+extern void do_notify_spus_active(void);
+
+/*
+ * This defines the Local Store, Problem Area and Privilege Area of an SPU.
+ */
+
+union mfc_tag_size_class_cmd {
+        struct {
+                u16 mfc_size;
+                u16 mfc_tag;
+                u8  pad;
+                u8  mfc_rclassid;
+                u16 mfc_cmd;
+        } u;
+        struct {
+                u32 mfc_size_tag32;
+                u32 mfc_class_cmd32;
+        } by32;
+        u64 all64;
+};
+
+struct mfc_cq_sr {
+        u64 mfc_cq_data0_RW;
+        u64 mfc_cq_data1_RW;
+        u64 mfc_cq_data2_RW;
+        u64 mfc_cq_data3_RW;
+};
+
+struct spu_problem {
+#define MS_SYNC_PENDING         1L
+        u64 spc_mssync_RW;                                      /* 0x0000 */
+        u8  pad_0x0008_0x3000[0x3000 - 0x0008];
+
+        /* DMA Area */
+        u8  pad_0x3000_0x3004[0x4];                             /* 0x3000 */
+        u32 mfc_lsa_W;                                          /* 0x3004 */
+        u64 mfc_ea_W;                                           /* 0x3008 */
+        union mfc_tag_size_class_cmd mfc_union_W;                       /* 0x3010 */
+        u8  pad_0x3018_0x3104[0xec];                            /* 0x3018 */
+        u32 dma_qstatus_R;                                      /* 0x3104 */
+        u8  pad_0x3108_0x3204[0xfc];                            /* 0x3108 */
+        u32 dma_querytype_RW;                                   /* 0x3204 */
+        u8  pad_0x3208_0x321c[0x14];                            /* 0x3208 */
+        u32 dma_querymask_RW;                                   /* 0x321c */
+        u8  pad_0x3220_0x322c[0xc];                             /* 0x3220 */
+        u32 dma_tagstatus_R;                                    /* 0x322c */
+#define DMA_TAGSTATUS_INTR_ANY  1u
+#define DMA_TAGSTATUS_INTR_ALL  2u
+        u8  pad_0x3230_0x4000[0x4000 - 0x3230];                 /* 0x3230 */
+
+        /* SPU Control Area */
+        u8  pad_0x4000_0x4004[0x4];                             /* 0x4000 */
+        u32 pu_mb_R;                                            /* 0x4004 */
+        u8  pad_0x4008_0x400c[0x4];                             /* 0x4008 */
+        u32 spu_mb_W;                                           /* 0x400c */
+        u8  pad_0x4010_0x4014[0x4];                             /* 0x4010 */
+        u32 mb_stat_R;                                          /* 0x4014 */
+        u8  pad_0x4018_0x401c[0x4];                             /* 0x4018 */
+        u32 spu_runcntl_RW;                                     /* 0x401c */
+#define SPU_RUNCNTL_STOP        0L
+#define SPU_RUNCNTL_RUNNABLE    1L
+#define SPU_RUNCNTL_ISOLATE     2L
+        u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
+        u32 spu_status_R;                                       /* 0x4024 */
+#define SPU_STOP_STATUS_SHIFT           16
+#define SPU_STATUS_STOPPED              0x0
+#define SPU_STATUS_RUNNING              0x1
+#define SPU_STATUS_STOPPED_BY_STOP      0x2
+#define SPU_STATUS_STOPPED_BY_HALT      0x4
+#define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
+#define SPU_STATUS_SINGLE_STEP          0x10
+#define SPU_STATUS_INVALID_INSTR        0x20
+#define SPU_STATUS_INVALID_CH           0x40
+#define SPU_STATUS_ISOLATED_STATE       0x80
+#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
+#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
+        u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
+        u32 spu_spe_R;                                          /* 0x402c */
+        u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
+        u32 spu_npc_RW;                                         /* 0x4034 */
+        u8  pad_0x4038_0x14000[0x14000 - 0x4038];               /* 0x4038 */
+
+        /* Signal Notification Area */
+        u8  pad_0x14000_0x1400c[0xc];                           /* 0x14000 */
+        u32 signal_notify1;                                     /* 0x1400c */
+        u8  pad_0x14010_0x1c00c[0x7ffc];                        /* 0x14010 */
+        u32 signal_notify2;                                     /* 0x1c00c */
+} __attribute__ ((aligned(0x20000)));
+
+/* SPU Privilege 2 State Area */
+struct spu_priv2 {
+        /* MFC Registers */
+        u8  pad_0x0000_0x1100[0x1100 - 0x0000];                 /* 0x0000 */
+
+        /* SLB Management Registers */
+        u8  pad_0x1100_0x1108[0x8];                             /* 0x1100 */
+        u64 slb_index_W;                                        /* 0x1108 */
+#define SLB_INDEX_MASK                          0x7L
+        u64 slb_esid_RW;                                        /* 0x1110 */
+        u64 slb_vsid_RW;                                        /* 0x1118 */
+#define SLB_VSID_SUPERVISOR_STATE       (0x1ull << 11)
+#define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
+#define SLB_VSID_PROBLEM_STATE          (0x1ull << 10)
+#define SLB_VSID_PROBLEM_STATE_MASK     (0x1ull << 10)
+#define SLB_VSID_EXECUTE_SEGMENT        (0x1ull << 9)
+#define SLB_VSID_NO_EXECUTE_SEGMENT     (0x1ull << 9)
+#define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
+#define SLB_VSID_4K_PAGE                (0x0 << 8)
+#define SLB_VSID_LARGE_PAGE             (0x1ull << 8)
+#define SLB_VSID_PAGE_SIZE_MASK         (0x1ull << 8)
+#define SLB_VSID_CLASS_MASK             (0x1ull << 7)
+#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
+        u64 slb_invalidate_entry_W;                             /* 0x1120 */
+        u64 slb_invalidate_all_W;                               /* 0x1128 */
+        u8  pad_0x1130_0x2000[0x2000 - 0x1130];                 /* 0x1130 */
+
+        /* Context Save / Restore Area */
+        struct mfc_cq_sr spuq[16];                              /* 0x2000 */
+        struct mfc_cq_sr puq[8];                                /* 0x2200 */
+        u8  pad_0x2300_0x3000[0x3000 - 0x2300];                 /* 0x2300 */
+
+        /* MFC Control */
+        u64 mfc_control_RW;                                     /* 0x3000 */
+#define MFC_CNTL_RESUME_DMA_QUEUE               (0ull << 0)
+#define MFC_CNTL_SUSPEND_DMA_QUEUE              (1ull << 0)
+#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK         (1ull << 0)
+#define MFC_CNTL_SUSPEND_MASK                   (1ull << 4)
+#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION     (0ull << 8)
+#define MFC_CNTL_SUSPEND_IN_PROGRESS            (1ull << 8)
+#define MFC_CNTL_SUSPEND_COMPLETE               (3ull << 8)
+#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK        (3ull << 8)
+#define MFC_CNTL_DMA_QUEUES_EMPTY               (1ull << 14)
+#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK          (1ull << 14)
+#define MFC_CNTL_PURGE_DMA_REQUEST              (1ull << 15)
+#define MFC_CNTL_PURGE_DMA_IN_PROGRESS          (1ull << 24)
+#define MFC_CNTL_PURGE_DMA_COMPLETE             (3ull << 24)
+#define MFC_CNTL_PURGE_DMA_STATUS_MASK          (3ull << 24)
+#define MFC_CNTL_RESTART_DMA_COMMAND            (1ull << 32)
+#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
+#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
+#define MFC_CNTL_MFC_PRIVILEGE_STATE            (2ull << 33)
+#define MFC_CNTL_MFC_PROBLEM_STATE              (3ull << 33)
+#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
+#define MFC_CNTL_DECREMENTER_HALTED             (1ull << 35)
+#define MFC_CNTL_DECREMENTER_RUNNING            (1ull << 40)
+#define MFC_CNTL_DECREMENTER_STATUS_MASK        (1ull << 40)
+        u8  pad_0x3008_0x4000[0x4000 - 0x3008];                 /* 0x3008 */
+
+        /* Interrupt Mailbox */
+        u64 puint_mb_R;                                         /* 0x4000 */
+        u8  pad_0x4008_0x4040[0x4040 - 0x4008];                 /* 0x4008 */
+
+        /* SPU Control */
+        u64 spu_privcntl_RW;                                    /* 0x4040 */
+#define SPU_PRIVCNTL_MODE_NORMAL                (0x0ull << 0)
+#define SPU_PRIVCNTL_MODE_SINGLE_STEP           (0x1ull << 0)
+#define SPU_PRIVCNTL_MODE_MASK                  (0x1ull << 0)
+#define SPU_PRIVCNTL_NO_ATTENTION_EVENT         (0x0ull << 1)
+#define SPU_PRIVCNTL_ATTENTION_EVENT            (0x1ull << 1)
+#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK       (0x1ull << 1)
+#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL         (0x0ull << 2)
+#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
+        u8  pad_0x4048_0x4058[0x10];                            /* 0x4048 */
+        u64 spu_lslr_RW;                                        /* 0x4058 */
+        u64 spu_chnlcntptr_RW;                                  /* 0x4060 */
+        u64 spu_chnlcnt_RW;                                     /* 0x4068 */
+        u64 spu_chnldata_RW;                                    /* 0x4070 */
+        u64 spu_cfg_RW;                                         /* 0x4078 */
+        u8  pad_0x4080_0x5000[0x5000 - 0x4080];                 /* 0x4080 */
+
+        /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
+        u64 spu_pm_trace_tag_status_RW;                         /* 0x5000 */
+        u64 spu_tag_status_query_RW;                            /* 0x5008 */
+#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
+#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
+        u64 spu_cmd_buf1_RW;                                    /* 0x5010 */
+#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
+#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
+        u64 spu_cmd_buf2_RW;                                    /* 0x5018 */
+#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
+#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
+#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
+        u64 spu_atomic_status_RW;                               /* 0x5020 */
+} __attribute__ ((aligned(0x20000)));
+
+/* SPU Privilege 1 State Area */
+struct spu_priv1 {
+        /* Control and Configuration Area */
+        u64 mfc_sr1_RW;                                         /* 0x000 */
+#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
+#define MFC_STATE1_BUS_TLBIE_MASK               0x02ull
+#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
+#define MFC_STATE1_PROBLEM_STATE_MASK           0x08ull
+#define MFC_STATE1_RELOCATE_MASK                0x10ull
+#define MFC_STATE1_MASTER_RUN_CONTROL_MASK      0x20ull
+#define MFC_STATE1_TABLE_SEARCH_MASK            0x40ull
+        u64 mfc_lpid_RW;                                        /* 0x008 */
+        u64 spu_idr_RW;                                         /* 0x010 */
+        u64 mfc_vr_RO;                                          /* 0x018 */
+#define MFC_VERSION_BITS                (0xffff << 16)
+#define MFC_REVISION_BITS               (0xffff)
+#define MFC_GET_VERSION_BITS(vr)        (((vr) & MFC_VERSION_BITS) >> 16)
+#define MFC_GET_REVISION_BITS(vr)       ((vr) & MFC_REVISION_BITS)
+        u64 spu_vr_RO;                                          /* 0x020 */
+#define SPU_VERSION_BITS                (0xffff << 16)
+#define SPU_REVISION_BITS               (0xffff)
+#define SPU_GET_VERSION_BITS(vr)        (vr & SPU_VERSION_BITS) >> 16
+#define SPU_GET_REVISION_BITS(vr)       (vr & SPU_REVISION_BITS)
+        u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
+
+        /* Interrupt Area */
+        u64 int_mask_RW[3];                                     /* 0x100 */
+#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR                0x1L
+#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR          0x2L
+#define CLASS0_ENABLE_SPU_ERROR_INTR                    0x4L
+#define CLASS0_ENABLE_MFC_FIR_INTR                      0x8L
+#define CLASS1_ENABLE_SEGMENT_FAULT_INTR                0x1L
+#define CLASS1_ENABLE_STORAGE_FAULT_INTR                0x2L
+#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
+#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
+#define CLASS2_ENABLE_MAILBOX_INTR                      0x1L
+#define CLASS2_ENABLE_SPU_STOP_INTR                     0x2L
+#define CLASS2_ENABLE_SPU_HALT_INTR                     0x4L
+#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
+#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR            0x10L
+        u8  pad_0x118_0x140[0x28];                              /* 0x118 */
+        u64 int_stat_RW[3];                                     /* 0x140 */
+#define CLASS0_DMA_ALIGNMENT_INTR                       0x1L
+#define CLASS0_INVALID_DMA_COMMAND_INTR                 0x2L
+#define CLASS0_SPU_ERROR_INTR                           0x4L
+#define CLASS0_INTR_MASK                                0x7L
+#define CLASS1_SEGMENT_FAULT_INTR                       0x1L
+#define CLASS1_STORAGE_FAULT_INTR                       0x2L
+#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR           0x4L
+#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR           0x8L
+#define CLASS1_INTR_MASK                                0xfL
+#define CLASS2_MAILBOX_INTR                             0x1L
+#define CLASS2_SPU_STOP_INTR                            0x2L
+#define CLASS2_SPU_HALT_INTR                            0x4L
+#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR          0x8L
+#define CLASS2_MAILBOX_THRESHOLD_INTR                   0x10L
+#define CLASS2_INTR_MASK                                0x1fL
+        u8  pad_0x158_0x180[0x28];                              /* 0x158 */
+        u64 int_route_RW;                                       /* 0x180 */
+
+        /* Interrupt Routing */
+        u8  pad_0x188_0x200[0x200 - 0x188];                     /* 0x188 */
+
+        /* Atomic Unit Control Area */
+        u64 mfc_atomic_flush_RW;                                /* 0x200 */
+#define mfc_atomic_flush_enable                 0x1L
+        u8  pad_0x208_0x280[0x78];                              /* 0x208 */
+        u64 resource_allocation_groupID_RW;                     /* 0x280 */
+        u64 resource_allocation_enable_RW;                      /* 0x288 */
+        u8  pad_0x290_0x3c8[0x3c8 - 0x290];                     /* 0x290 */
+
+        /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
+
+        u64 smf_sbi_signal_sel;                                 /* 0x3c8 */
+#define smf_sbi_mask_lsb        56
+#define smf_sbi_shift           (63 - smf_sbi_mask_lsb)
+#define smf_sbi_mask            (0x301LL << smf_sbi_shift)
+#define smf_sbi_bus0_bits       (0x001LL << smf_sbi_shift)
+#define smf_sbi_bus2_bits       (0x100LL << smf_sbi_shift)
+#define smf_sbi2_bus0_bits      (0x201LL << smf_sbi_shift)
+#define smf_sbi2_bus2_bits      (0x300LL << smf_sbi_shift)
+        u64 smf_ato_signal_sel;                                 /* 0x3d0 */
+#define smf_ato_mask_lsb        35
+#define smf_ato_shift           (63 - smf_ato_mask_lsb)
+#define smf_ato_mask            (0x3LL << smf_ato_shift)
+#define smf_ato_bus0_bits       (0x2LL << smf_ato_shift)
+#define smf_ato_bus2_bits       (0x1LL << smf_ato_shift)
+        u8  pad_0x3d8_0x400[0x400 - 0x3d8];                     /* 0x3d8 */
+
+        /* TLB Management Registers */
+        u64 mfc_sdr_RW;                                         /* 0x400 */
+        u8  pad_0x408_0x500[0xf8];                              /* 0x408 */
+        u64 tlb_index_hint_RO;                                  /* 0x500 */
+        u64 tlb_index_W;                                        /* 0x508 */
+        u64 tlb_vpn_RW;                                         /* 0x510 */
+        u64 tlb_rpn_RW;                                         /* 0x518 */
+        u8  pad_0x520_0x540[0x20];                              /* 0x520 */
+        u64 tlb_invalidate_entry_W;                             /* 0x540 */
+        u64 tlb_invalidate_all_W;                               /* 0x548 */
+        u8  pad_0x550_0x580[0x580 - 0x550];                     /* 0x550 */
+
+        /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
+        u64 smm_hid;                                            /* 0x580 */
+#define PAGE_SIZE_MASK          0xf000000000000000ull
+#define PAGE_SIZE_16MB_64KB     0x2000000000000000ull
+        u8  pad_0x588_0x600[0x600 - 0x588];                     /* 0x588 */
+
+        /* MFC Status/Control Area */
+        u64 mfc_accr_RW;                                        /* 0x600 */
+#define MFC_ACCR_EA_ACCESS_GET          (1 << 0)
+#define MFC_ACCR_EA_ACCESS_PUT          (1 << 1)
+#define MFC_ACCR_LS_ACCESS_GET          (1 << 3)
+#define MFC_ACCR_LS_ACCESS_PUT          (1 << 4)
+        u8  pad_0x608_0x610[0x8];                               /* 0x608 */
+        u64 mfc_dsisr_RW;                                       /* 0x610 */
+#define MFC_DSISR_PTE_NOT_FOUND         (1 << 30)
+#define MFC_DSISR_ACCESS_DENIED         (1 << 27)
+#define MFC_DSISR_ATOMIC                (1 << 26)
+#define MFC_DSISR_ACCESS_PUT            (1 << 25)
+#define MFC_DSISR_ADDR_MATCH            (1 << 22)
+#define MFC_DSISR_LS                    (1 << 17)
+#define MFC_DSISR_L                     (1 << 16)
+#define MFC_DSISR_ADDRESS_OVERFLOW      (1 << 0)
+        u8  pad_0x618_0x620[0x8];                               /* 0x618 */
+        u64 mfc_dar_RW;                                         /* 0x620 */
+        u8  pad_0x628_0x700[0x700 - 0x628];                     /* 0x628 */
+
+        /* Replacement Management Table (RMT) Area */
+        u64 rmt_index_RW;                                       /* 0x700 */
+        u8  pad_0x708_0x710[0x8];                               /* 0x708 */
+        u64 rmt_data1_RW;                                       /* 0x710 */
+        u8  pad_0x718_0x800[0x800 - 0x718];                     /* 0x718 */
+
+        /* Control/Configuration Registers */
+        u64 mfc_dsir_R;                                         /* 0x800 */
+#define MFC_DSIR_Q                      (1 << 31)
+#define MFC_DSIR_SPU_QUEUE              MFC_DSIR_Q
+        u64 mfc_lsacr_RW;                                       /* 0x808 */
+#define MFC_LSACR_COMPARE_MASK          ((~0ull) << 32)
+#define MFC_LSACR_COMPARE_ADDR          ((~0ull) >> 32)
+        u64 mfc_lscrr_R;                                        /* 0x810 */
+#define MFC_LSCRR_Q                     (1 << 31)
+#define MFC_LSCRR_SPU_QUEUE             MFC_LSCRR_Q
+#define MFC_LSCRR_QI_SHIFT              32
+#define MFC_LSCRR_QI_MASK               ((~0ull) << MFC_LSCRR_QI_SHIFT)
+        u8  pad_0x818_0x820[0x8];                               /* 0x818 */
+        u64 mfc_tclass_id_RW;                                   /* 0x820 */
+#define MFC_TCLASS_ID_ENABLE            (1L << 0L)
+#define MFC_TCLASS_SLOT2_ENABLE         (1L << 5L)
+#define MFC_TCLASS_SLOT1_ENABLE         (1L << 6L)
+#define MFC_TCLASS_SLOT0_ENABLE         (1L << 7L)
+#define MFC_TCLASS_QUOTA_2_SHIFT        8L
+#define MFC_TCLASS_QUOTA_1_SHIFT        16L
+#define MFC_TCLASS_QUOTA_0_SHIFT        24L
+#define MFC_TCLASS_QUOTA_2_MASK         (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
+#define MFC_TCLASS_QUOTA_1_MASK         (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
+#define MFC_TCLASS_QUOTA_0_MASK         (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
+        u8  pad_0x828_0x900[0x900 - 0x828];                     /* 0x828 */
+
+        /* Real Mode Support Registers */
+        u64 mfc_rm_boundary;                                    /* 0x900 */
+        u8  pad_0x908_0x938[0x30];                              /* 0x908 */
+        u64 smf_dma_signal_sel;                                 /* 0x938 */
+#define mfc_dma1_mask_lsb       41
+#define mfc_dma1_shift          (63 - mfc_dma1_mask_lsb)
+#define mfc_dma1_mask           (0x3LL << mfc_dma1_shift)
+#define mfc_dma1_bits           (0x1LL << mfc_dma1_shift)
+#define mfc_dma2_mask_lsb       43
+#define mfc_dma2_shift          (63 - mfc_dma2_mask_lsb)
+#define mfc_dma2_mask           (0x3LL << mfc_dma2_shift)
+#define mfc_dma2_bits           (0x1LL << mfc_dma2_shift)
+        u8  pad_0x940_0xa38[0xf8];                              /* 0x940 */
+        u64 smm_signal_sel;                                     /* 0xa38 */
+#define smm_sig_mask_lsb        12
+#define smm_sig_shift           (63 - smm_sig_mask_lsb)
+#define smm_sig_mask            (0x3LL << smm_sig_shift)
+#define smm_sig_bus0_bits       (0x2LL << smm_sig_shift)
+#define smm_sig_bus2_bits       (0x1LL << smm_sig_shift)
+        u8  pad_0xa40_0xc00[0xc00 - 0xa40];                     /* 0xa40 */
+
+        /* DMA Command Error Area */
+        u64 mfc_cer_R;                                          /* 0xc00 */
+#define MFC_CER_Q               (1 << 31)
+#define MFC_CER_SPU_QUEUE       MFC_CER_Q
+        u8  pad_0xc08_0x1000[0x1000 - 0xc08];                   /* 0xc08 */
+
+        /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
+        /* DMA Command Error Area */
+        u64 spu_ecc_cntl_RW;                                    /* 0x1000 */
+#define SPU_ECC_CNTL_E                  (1ull << 0ull)
+#define SPU_ECC_CNTL_ENABLE             SPU_ECC_CNTL_E
+#define SPU_ECC_CNTL_DISABLE            (~SPU_ECC_CNTL_E & 1L)
+#define SPU_ECC_CNTL_S                  (1ull << 1ull)
+#define SPU_ECC_STOP_AFTER_ERROR        SPU_ECC_CNTL_S
+#define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
+#define SPU_ECC_CNTL_B                  (1ull << 2ull)
+#define SPU_ECC_BACKGROUND_ENABLE       SPU_ECC_CNTL_B
+#define SPU_ECC_BACKGROUND_DISABLE      (~SPU_ECC_CNTL_B & 4L)
+#define SPU_ECC_CNTL_I_SHIFT            3ull
+#define SPU_ECC_CNTL_I_MASK             (3ull << SPU_ECC_CNTL_I_SHIFT)
+#define SPU_ECC_WRITE_ALWAYS            (~SPU_ECC_CNTL_I & 12L)
+#define SPU_ECC_WRITE_CORRECTABLE       (1ull << SPU_ECC_CNTL_I_SHIFT)
+#define SPU_ECC_WRITE_UNCORRECTABLE     (3ull << SPU_ECC_CNTL_I_SHIFT)
+#define SPU_ECC_CNTL_D                  (1ull << 5ull)
+#define SPU_ECC_DETECTION_ENABLE        SPU_ECC_CNTL_D
+#define SPU_ECC_DETECTION_DISABLE       (~SPU_ECC_CNTL_D & 32L)
+        u64 spu_ecc_stat_RW;                                    /* 0x1008 */
+#define SPU_ECC_CORRECTED_ERROR         (1ull << 0ul)
+#define SPU_ECC_UNCORRECTED_ERROR       (1ull << 1ul)
+#define SPU_ECC_SCRUB_COMPLETE          (1ull << 2ul)
+#define SPU_ECC_SCRUB_IN_PROGRESS       (1ull << 3ul)
+#define SPU_ECC_INSTRUCTION_ERROR       (1ull << 4ul)
+#define SPU_ECC_DATA_ERROR              (1ull << 5ul)
+#define SPU_ECC_DMA_ERROR               (1ull << 6ul)
+#define SPU_ECC_STATUS_CNT_MASK         (256ull << 8)
+        u64 spu_ecc_addr_RW;                                    /* 0x1010 */
+        u64 spu_err_mask_RW;                                    /* 0x1018 */
+#define SPU_ERR_ILLEGAL_INSTR           (1ull << 0ul)
+#define SPU_ERR_ILLEGAL_CHANNEL         (1ull << 1ul)
+        u8  pad_0x1020_0x1028[0x1028 - 0x1020];                 /* 0x1020 */
+
+        /* SPU Debug-Trace Bus (DTB) Selection Registers */
+        u64 spu_trig0_sel;                                      /* 0x1028 */
+        u64 spu_trig1_sel;                                      /* 0x1030 */
+        u64 spu_trig2_sel;                                      /* 0x1038 */
+        u64 spu_trig3_sel;                                      /* 0x1040 */
+        u64 spu_trace_sel;                                      /* 0x1048 */
+#define spu_trace_sel_mask              0x1f1fLL
+#define spu_trace_sel_bus0_bits         0x1000LL
+#define spu_trace_sel_bus2_bits         0x0010LL
+        u64 spu_event0_sel;                                     /* 0x1050 */
+        u64 spu_event1_sel;                                     /* 0x1058 */
+        u64 spu_event2_sel;                                     /* 0x1060 */
+        u64 spu_event3_sel;                                     /* 0x1068 */
+        u64 spu_trace_cntl;                                     /* 0x1070 */
+} __attribute__ ((aligned(0x2000)));
+
+#endif /* __KERNEL__ */
+#endif
diff --git a/arch/powerpc/include/asm/spu_csa.h b/arch/powerpc/include/asm/spu_csa.h
new file mode 100644
index 000000000000..a40fd491250c
--- /dev/null
+++ b/arch/powerpc/include/asm/spu_csa.h
@@ -0,0 +1,266 @@
+/*
+ * spu_csa.h: Definitions for SPU context save area (CSA).
+ *
+ * (C) Copyright IBM 2005
+ *
+ * Author: Mark Nutter <mnutter@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _SPU_CSA_H_
+#define _SPU_CSA_H_
+#ifdef __KERNEL__
+
+/*
+ * Total number of 128-bit registers.
+ */
+#define NR_SPU_GPRS             128
+#define NR_SPU_SPRS             9
+#define NR_SPU_REGS_PAD         7
+#define NR_SPU_SPILL_REGS       144     /* GPRS + SPRS + PAD */
+#define SIZEOF_SPU_SPILL_REGS   NR_SPU_SPILL_REGS * 16
+
+#define SPU_SAVE_COMPLETE       0x3FFB
+#define SPU_RESTORE_COMPLETE    0x3FFC
+
+/*
+ * Definitions for various 'stopped' status conditions,
+ * to be recreated during context restore.
+ */
+#define SPU_STOPPED_STATUS_P    1
+#define SPU_STOPPED_STATUS_I    2
+#define SPU_STOPPED_STATUS_H    3
+#define SPU_STOPPED_STATUS_S    4
+#define SPU_STOPPED_STATUS_S_I  5
+#define SPU_STOPPED_STATUS_S_P  6
+#define SPU_STOPPED_STATUS_P_H  7
+#define SPU_STOPPED_STATUS_P_I  8
+#define SPU_STOPPED_STATUS_R    9
+
+/*
+ * Definitions for software decrementer status flag.
+ */
+#define SPU_DECR_STATUS_RUNNING 0x1
+#define SPU_DECR_STATUS_WRAPPED 0x2
+
+#ifndef  __ASSEMBLY__
+/**
+ * spu_reg128 - generic 128-bit register definition.
+ */
+struct spu_reg128 {
+        u32 slot[4];
+};
+
+/**
+ * struct spu_lscsa - Local Store Context Save Area.
+ * @gprs: Array of saved registers.
+ * @fpcr: Saved floating point status control register.
+ * @decr: Saved decrementer value.
+ * @decr_status: Indicates software decrementer status flags.
+ * @ppu_mb: Saved PPU mailbox data.
+ * @ppuint_mb: Saved PPU interrupting mailbox data.
+ * @tag_mask: Saved tag group mask.
+ * @event_mask: Saved event mask.
+ * @srr0: Saved SRR0.
+ * @stopped_status: Conditions to be recreated by restore.
+ * @ls: Saved contents of Local Storage Area.
+ *
+ * The LSCSA represents state that is primarily saved and
+ * restored by SPU-side code.
+ */
+struct spu_lscsa {
+        struct spu_reg128 gprs[128];
+        struct spu_reg128 fpcr;
+        struct spu_reg128 decr;
+        struct spu_reg128 decr_status;
+        struct spu_reg128 ppu_mb;
+        struct spu_reg128 ppuint_mb;
+        struct spu_reg128 tag_mask;
+        struct spu_reg128 event_mask;
+        struct spu_reg128 srr0;
+        struct spu_reg128 stopped_status;
+
+        /*
+         * 'ls' must be page-aligned on all configurations.
+         * Since we don't want to rely on having the spu-gcc
+         * installed to build the kernel and this structure
+         * is used in the SPU-side code, make it 64k-page
+         * aligned for now.
+         */
+        unsigned char ls[LS_SIZE] __attribute__((aligned(65536)));
+};
+
+#ifndef __SPU__
+/*
+ * struct spu_problem_collapsed - condensed problem state area, w/o pads.
+ */
+struct spu_problem_collapsed {
+        u64 spc_mssync_RW;
+        u32 mfc_lsa_W;
+        u32 unused_pad0;
+        u64 mfc_ea_W;
+        union mfc_tag_size_class_cmd mfc_union_W;
+        u32 dma_qstatus_R;
+        u32 dma_querytype_RW;
+        u32 dma_querymask_RW;
+        u32 dma_tagstatus_R;
+        u32 pu_mb_R;
+        u32 spu_mb_W;
+        u32 mb_stat_R;
+        u32 spu_runcntl_RW;
+        u32 spu_status_R;
+        u32 spu_spc_R;
+        u32 spu_npc_RW;
+        u32 signal_notify1;
+        u32 signal_notify2;
+        u32 unused_pad1;
+};
+
+/*
+ * struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
+ */
+struct spu_priv1_collapsed {
+        u64 mfc_sr1_RW;
+        u64 mfc_lpid_RW;
+        u64 spu_idr_RW;
+        u64 mfc_vr_RO;
+        u64 spu_vr_RO;
+        u64 int_mask_class0_RW;
+        u64 int_mask_class1_RW;
+        u64 int_mask_class2_RW;
+        u64 int_stat_class0_RW;
+        u64 int_stat_class1_RW;
+        u64 int_stat_class2_RW;
+        u64 int_route_RW;
+        u64 mfc_atomic_flush_RW;
+        u64 resource_allocation_groupID_RW;
+        u64 resource_allocation_enable_RW;
+        u64 mfc_fir_R;
+        u64 mfc_fir_status_or_W;
+        u64 mfc_fir_status_and_W;
+        u64 mfc_fir_mask_R;
+        u64 mfc_fir_mask_or_W;
+        u64 mfc_fir_mask_and_W;
+        u64 mfc_fir_chkstp_enable_RW;
+        u64 smf_sbi_signal_sel;
+        u64 smf_ato_signal_sel;
+        u64 tlb_index_hint_RO;
+        u64 tlb_index_W;
+        u64 tlb_vpn_RW;
+        u64 tlb_rpn_RW;
+        u64 tlb_invalidate_entry_W;
+        u64 tlb_invalidate_all_W;
+        u64 smm_hid;
+        u64 mfc_accr_RW;
+        u64 mfc_dsisr_RW;
+        u64 mfc_dar_RW;
+        u64 rmt_index_RW;
+        u64 rmt_data1_RW;
+        u64 mfc_dsir_R;
+        u64 mfc_lsacr_RW;
+        u64 mfc_lscrr_R;
+        u64 mfc_tclass_id_RW;
+        u64 mfc_rm_boundary;
+        u64 smf_dma_signal_sel;
+        u64 smm_signal_sel;
+        u64 mfc_cer_R;
+        u64 pu_ecc_cntl_RW;
+        u64 pu_ecc_stat_RW;
+        u64 spu_ecc_addr_RW;
+        u64 spu_err_mask_RW;
+        u64 spu_trig0_sel;
+        u64 spu_trig1_sel;
+        u64 spu_trig2_sel;
+        u64 spu_trig3_sel;
+        u64 spu_trace_sel;
+        u64 spu_event0_sel;
+        u64 spu_event1_sel;
+        u64 spu_event2_sel;
+        u64 spu_event3_sel;
+        u64 spu_trace_cntl;
+};
+
+/*
+ * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads.
+ */
+struct spu_priv2_collapsed {
+        u64 slb_index_W;
+        u64 slb_esid_RW;
+        u64 slb_vsid_RW;
+        u64 slb_invalidate_entry_W;
+        u64 slb_invalidate_all_W;
+        struct mfc_cq_sr spuq[16];
+        struct mfc_cq_sr puq[8];
+        u64 mfc_control_RW;
+        u64 puint_mb_R;
+        u64 spu_privcntl_RW;
+        u64 spu_lslr_RW;
+        u64 spu_chnlcntptr_RW;
+        u64 spu_chnlcnt_RW;
+        u64 spu_chnldata_RW;
+        u64 spu_cfg_RW;
+        u64 spu_tag_status_query_RW;
+        u64 spu_cmd_buf1_RW;
+        u64 spu_cmd_buf2_RW;
+        u64 spu_atomic_status_RW;
+};
+
+/**
+ * struct spu_state
+ * @lscsa: Local Store Context Save Area.
+ * @prob: Collapsed Problem State Area, w/o pads.
+ * @priv1: Collapsed Privileged 1 Area, w/o pads.
+ * @priv2: Collapsed Privileged 2 Area, w/o pads.
+ * @spu_chnlcnt_RW: Array of saved channel counts.
+ * @spu_chnldata_RW: Array of saved channel data.
+ * @suspend_time: Time stamp when decrementer disabled.
+ *
+ * Structure representing the whole of the SPU
+ * context save area (CSA).  This struct contains
+ * all of the state necessary to suspend and then
+ * later optionally resume execution of an SPU
+ * context.
+ *
+ * The @lscsa region is by far the largest, and is
+ * allocated separately so that it may either be
+ * pinned or mapped to/from application memory, as
+ * appropriate for the OS environment.
+ */
+struct spu_state {
+        struct spu_lscsa *lscsa;
+#ifdef CONFIG_SPU_FS_64K_LS
+        int             use_big_pages;
+        /* One struct page per 64k page */
+#define SPU_LSCSA_NUM_BIG_PAGES (sizeof(struct spu_lscsa) / 0x10000)
+        struct page     *lscsa_pages[SPU_LSCSA_NUM_BIG_PAGES];
+#endif
+        struct spu_problem_collapsed prob;
+        struct spu_priv1_collapsed priv1;
+        struct spu_priv2_collapsed priv2;
+        u64 spu_chnlcnt_RW[32];
+        u64 spu_chnldata_RW[32];
+        u32 spu_mailbox_data[4];
+        u32 pu_mailbox_data[1];
+        u64 class_0_dar, class_0_pending;
+        u64 class_1_dar, class_1_dsisr;
+        unsigned long suspend_time;
+        spinlock_t register_lock;
+};
+
+#endif /* !__SPU__ */
+#endif /* __KERNEL__ */
+#endif /* !__ASSEMBLY__ */
+#endif /* _SPU_CSA_H_ */
diff --git a/arch/powerpc/include/asm/spu_info.h b/arch/powerpc/include/asm/spu_info.h
new file mode 100644
index 000000000000..3545efbf9891
--- /dev/null
+++ b/arch/powerpc/include/asm/spu_info.h
@@ -0,0 +1,54 @@
+/*
+ * SPU info structures
+ *
+ * (C) Copyright 2006 IBM Corp.
+ *
+ * Author: Dwayne Grant McConnell <decimal@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _SPU_INFO_H
+#define _SPU_INFO_H
+
+#ifdef __KERNEL__
+#include <asm/spu.h>
+#include <linux/types.h>
+#else
+struct mfc_cq_sr {
+        __u64 mfc_cq_data0_RW;
+        __u64 mfc_cq_data1_RW;
+        __u64 mfc_cq_data2_RW;
+        __u64 mfc_cq_data3_RW;
+};
+#endif /* __KERNEL__ */
+
+struct spu_dma_info {
+        __u64 dma_info_type;
+        __u64 dma_info_mask;
+        __u64 dma_info_status;
+        __u64 dma_info_stall_and_notify;
+        __u64 dma_info_atomic_command_status;
+        struct mfc_cq_sr dma_info_command_data[16];
+};
+
+struct spu_proxydma_info {
+        __u64 proxydma_info_type;
+        __u64 proxydma_info_mask;
+        __u64 proxydma_info_status;
+        struct mfc_cq_sr proxydma_info_command_data[8];
+};
+
+#endif
diff --git a/arch/powerpc/include/asm/spu_priv1.h b/arch/powerpc/include/asm/spu_priv1.h
new file mode 100644
index 000000000000..25020a34ce7f
--- /dev/null
+++ b/arch/powerpc/include/asm/spu_priv1.h
@@ -0,0 +1,236 @@
+/*
+ * Defines an spu hypervisor abstraction layer.
+ *
+ *  Copyright 2006 Sony Corp.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#if !defined(_SPU_PRIV1_H)
+#define _SPU_PRIV1_H
+#if defined(__KERNEL__)
+
+#include <linux/types.h>
+
+struct spu;
+struct spu_context;
+
+/* access to priv1 registers */
+
+struct spu_priv1_ops {
+        void (*int_mask_and) (struct spu *spu, int class, u64 mask);
+        void (*int_mask_or) (struct spu *spu, int class, u64 mask);
+        void (*int_mask_set) (struct spu *spu, int class, u64 mask);
+        u64 (*int_mask_get) (struct spu *spu, int class);
+        void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
+        u64 (*int_stat_get) (struct spu *spu, int class);
+        void (*cpu_affinity_set) (struct spu *spu, int cpu);
+        u64 (*mfc_dar_get) (struct spu *spu);
+        u64 (*mfc_dsisr_get) (struct spu *spu);
+        void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
+        void (*mfc_sdr_setup) (struct spu *spu);
+        void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
+        u64 (*mfc_sr1_get) (struct spu *spu);
+        void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
+        u64 (*mfc_tclass_id_get) (struct spu *spu);
+        void (*tlb_invalidate) (struct spu *spu);
+        void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
+        u64 (*resource_allocation_groupID_get) (struct spu *spu);
+        void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
+        u64 (*resource_allocation_enable_get) (struct spu *spu);
+};
+
+extern const struct spu_priv1_ops* spu_priv1_ops;
+
+static inline void
+spu_int_mask_and (struct spu *spu, int class, u64 mask)
+{
+        spu_priv1_ops->int_mask_and(spu, class, mask);
+}
+
+static inline void
+spu_int_mask_or (struct spu *spu, int class, u64 mask)
+{
+        spu_priv1_ops->int_mask_or(spu, class, mask);
+}
+
+static inline void
+spu_int_mask_set (struct spu *spu, int class, u64 mask)
+{
+        spu_priv1_ops->int_mask_set(spu, class, mask);
+}
+
+static inline u64
+spu_int_mask_get (struct spu *spu, int class)
+{
+        return spu_priv1_ops->int_mask_get(spu, class);
+}
+
+static inline void
+spu_int_stat_clear (struct spu *spu, int class, u64 stat)
+{
+        spu_priv1_ops->int_stat_clear(spu, class, stat);
+}
+
+static inline u64
+spu_int_stat_get (struct spu *spu, int class)
+{
+        return spu_priv1_ops->int_stat_get (spu, class);
+}
+
+static inline void
+spu_cpu_affinity_set (struct spu *spu, int cpu)
+{
+        spu_priv1_ops->cpu_affinity_set(spu, cpu);
+}
+
+static inline u64
+spu_mfc_dar_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_dar_get(spu);
+}
+
+static inline u64
+spu_mfc_dsisr_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_dsisr_get(spu);
+}
+
+static inline void
+spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
+{
+        spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
+}
+
+static inline void
+spu_mfc_sdr_setup (struct spu *spu)
+{
+        spu_priv1_ops->mfc_sdr_setup(spu);
+}
+
+static inline void
+spu_mfc_sr1_set (struct spu *spu, u64 sr1)
+{
+        spu_priv1_ops->mfc_sr1_set(spu, sr1);
+}
+
+static inline u64
+spu_mfc_sr1_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_sr1_get(spu);
+}
+
+static inline void
+spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
+{
+        spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
+}
+
+static inline u64
+spu_mfc_tclass_id_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_tclass_id_get(spu);
+}
+
+static inline void
+spu_tlb_invalidate (struct spu *spu)
+{
+        spu_priv1_ops->tlb_invalidate(spu);
+}
+
+static inline void
+spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
+{
+        spu_priv1_ops->resource_allocation_groupID_set(spu, id);
+}
+
+static inline u64
+spu_resource_allocation_groupID_get (struct spu *spu)
+{
+        return spu_priv1_ops->resource_allocation_groupID_get(spu);
+}
+
+static inline void
+spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
+{
+        spu_priv1_ops->resource_allocation_enable_set(spu, enable);
+}
+
+static inline u64
+spu_resource_allocation_enable_get (struct spu *spu)
+{
+        return spu_priv1_ops->resource_allocation_enable_get(spu);
+}
+
+/* spu management abstraction */
+
+struct spu_management_ops {
+        int (*enumerate_spus)(int (*fn)(void *data));
+        int (*create_spu)(struct spu *spu, void *data);
+        int (*destroy_spu)(struct spu *spu);
+        void (*enable_spu)(struct spu_context *ctx);
+        void (*disable_spu)(struct spu_context *ctx);
+        int (*init_affinity)(void);
+};
+
+extern const struct spu_management_ops* spu_management_ops;
+
+static inline int
+spu_enumerate_spus (int (*fn)(void *data))
+{
+        return spu_management_ops->enumerate_spus(fn);
+}
+
+static inline int
+spu_create_spu (struct spu *spu, void *data)
+{
+        return spu_management_ops->create_spu(spu, data);
+}
+
+static inline int
+spu_destroy_spu (struct spu *spu)
+{
+        return spu_management_ops->destroy_spu(spu);
+}
+
+static inline int
+spu_init_affinity (void)
+{
+        return spu_management_ops->init_affinity();
+}
+
+static inline void
+spu_enable_spu (struct spu_context *ctx)
+{
+        spu_management_ops->enable_spu(ctx);
+}
+
+static inline void
+spu_disable_spu (struct spu_context *ctx)
+{
+        spu_management_ops->disable_spu(ctx);
+}
+
+/*
+ * The declarations folowing are put here for convenience
+ * and only intended to be used by the platform setup code.
+ */
+
+extern const struct spu_priv1_ops spu_priv1_mmio_ops;
+extern const struct spu_priv1_ops spu_priv1_beat_ops;
+
+extern const struct spu_management_ops spu_management_of_ops;
+
+#endif /* __KERNEL__ */
+#endif
diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h
new file mode 100644
index 000000000000..f593b0f9b627
--- /dev/null
+++ b/arch/powerpc/include/asm/sstep.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+struct pt_regs;
+
+/*
+ * We don't allow single-stepping an mtmsrd that would clear
+ * MSR_RI, since that would make the exception unrecoverable.
+ * Since we need to single-step to proceed from a breakpoint,
+ * we don't allow putting a breakpoint on an mtmsrd instruction.
+ * Similarly we don't allow breakpoints on rfid instructions.
+ * These macros tell us if an instruction is a mtmsrd or rfid.
+ * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
+ * and an mtmsrd (64-bit).
+ */
+#define IS_MTMSRD(instr)        (((instr) & 0xfc0007be) == 0x7c000124)
+#define IS_RFID(instr)          (((instr) & 0xfc0007fe) == 0x4c000024)
+#define IS_RFI(instr)           (((instr) & 0xfc0007fe) == 0x4c000064)
+
+/* Emulate instructions that cause a transfer of control. */
+extern int emulate_step(struct pt_regs *regs, unsigned int instr);
diff --git a/arch/powerpc/include/asm/stat.h b/arch/powerpc/include/asm/stat.h
new file mode 100644
index 000000000000..e4edc510b530
--- /dev/null
+++ b/arch/powerpc/include/asm/stat.h
@@ -0,0 +1,81 @@
+#ifndef _ASM_POWERPC_STAT_H
+#define _ASM_POWERPC_STAT_H
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/types.h>
+
+#define STAT_HAVE_NSEC 1
+
+#ifndef __powerpc64__
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+#endif /* !__powerpc64__ */
+
+struct stat {
+        unsigned long   st_dev;
+        ino_t           st_ino;
+#ifdef __powerpc64__
+        nlink_t         st_nlink;
+        mode_t          st_mode;
+#else
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+#endif
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned long   st_rdev;
+        off_t           st_size;
+        unsigned long   st_blksize;
+        unsigned long   st_blocks;
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+        unsigned long   __unused4;
+        unsigned long   __unused5;
+#ifdef __powerpc64__
+        unsigned long   __unused6;
+#endif
+};
+
+/* This matches struct stat64 in glibc2.1. Only used for 32 bit. */
+struct stat64 {
+        unsigned long long st_dev;              /* Device.  */
+        unsigned long long st_ino;              /* File serial number.  */
+        unsigned int    st_mode;        /* File mode.  */
+        unsigned int    st_nlink;       /* Link count.  */
+        unsigned int    st_uid;         /* User ID of the file's owner.  */
+        unsigned int    st_gid;         /* Group ID of the file's group. */
+        unsigned long long st_rdev;     /* Device number, if device.  */
+        unsigned short  __pad2;
+        long long       st_size;        /* Size of file, in bytes.  */
+        int             st_blksize;     /* Optimal block size for I/O.  */
+        long long       st_blocks;      /* Number 512-byte blocks allocated. */
+        int             st_atime;       /* Time of last access.  */
+        unsigned int    st_atime_nsec;
+        int             st_mtime;       /* Time of last modification.  */
+        unsigned int    st_mtime_nsec;
+        int             st_ctime;       /* Time of last status change.  */
+        unsigned int    st_ctime_nsec;
+        unsigned int    __unused4;
+        unsigned int    __unused5;
+};
+
+#endif /* _ASM_POWERPC_STAT_H */
diff --git a/arch/powerpc/include/asm/statfs.h b/arch/powerpc/include/asm/statfs.h
new file mode 100644
index 000000000000..67024026c10d
--- /dev/null
+++ b/arch/powerpc/include/asm/statfs.h
@@ -0,0 +1,60 @@
+#ifndef _ASM_POWERPC_STATFS_H
+#define _ASM_POWERPC_STATFS_H
+
+/* For ppc32 we just use the generic definitions, not so simple on ppc64 */
+
+#ifndef __powerpc64__
+#include <asm-generic/statfs.h>
+#else
+
+#ifndef __KERNEL_STRICT_NAMES
+#include <linux/types.h>
+typedef __kernel_fsid_t fsid_t;
+#endif
+
+/*
+ * We're already 64-bit, so duplicate the definition
+ */
+struct statfs {
+        long f_type;
+        long f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        long f_namelen;
+        long f_frsize;
+        long f_spare[5];
+};
+
+struct statfs64 {
+        long f_type;
+        long f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        long f_namelen;
+        long f_frsize;
+        long f_spare[5];
+};
+
+struct compat_statfs64 {
+        __u32 f_type;
+        __u32 f_bsize;
+        __u64 f_blocks;
+        __u64 f_bfree;
+        __u64 f_bavail;
+        __u64 f_files;
+        __u64 f_ffree;
+        __kernel_fsid_t f_fsid;
+        __u32 f_namelen;
+        __u32 f_frsize;
+        __u32 f_spare[5];
+};
+#endif /* ! __powerpc64__ */
+#endif
diff --git a/arch/powerpc/include/asm/string.h b/arch/powerpc/include/asm/string.h
new file mode 100644
index 000000000000..e40010abcaf1
--- /dev/null
+++ b/arch/powerpc/include/asm/string.h
@@ -0,0 +1,32 @@
+#ifndef _ASM_POWERPC_STRING_H
+#define _ASM_POWERPC_STRING_H
+
+#ifdef __KERNEL__
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRLEN
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRNCMP
+#define __HAVE_ARCH_STRCAT
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMCHR
+
+extern char * strcpy(char *,const char *);
+extern char * strncpy(char *,const char *, __kernel_size_t);
+extern __kernel_size_t strlen(const char *);
+extern int strcmp(const char *,const char *);
+extern int strncmp(const char *, const char *, __kernel_size_t);
+extern char * strcat(char *, const char *);
+extern void * memset(void *,int,__kernel_size_t);
+extern void * memcpy(void *,const void *,__kernel_size_t);
+extern void * memmove(void *,const void *,__kernel_size_t);
+extern int memcmp(const void *,const void *,__kernel_size_t);
+extern void * memchr(const void *,int,__kernel_size_t);
+
+#endif /* __KERNEL__ */
+
+#endif  /* _ASM_POWERPC_STRING_H */
diff --git a/arch/powerpc/include/asm/suspend.h b/arch/powerpc/include/asm/suspend.h
new file mode 100644
index 000000000000..cbf2c9404c37
--- /dev/null
+++ b/arch/powerpc/include/asm/suspend.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_POWERPC_SUSPEND_H
+#define __ASM_POWERPC_SUSPEND_H
+
+static inline int arch_prepare_suspend(void) { return 0; }
+
+void save_processor_state(void);
+void restore_processor_state(void);
+
+#endif /* __ASM_POWERPC_SUSPEND_H */
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
new file mode 100644
index 000000000000..45963e80f557
--- /dev/null
+++ b/arch/powerpc/include/asm/synch.h
@@ -0,0 +1,44 @@
+#ifndef _ASM_POWERPC_SYNCH_H 
+#define _ASM_POWERPC_SYNCH_H 
+#ifdef __KERNEL__
+
+#include <linux/stringify.h>
+#include <asm/feature-fixups.h>
+
+#ifndef __ASSEMBLY__
+extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
+extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
+                             void *fixup_end);
+
+static inline void eieio(void)
+{
+        __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void isync(void)
+{
+        __asm__ __volatile__ ("isync" : : : "memory");
+}
+#endif /* __ASSEMBLY__ */
+
+#if defined(__powerpc64__)
+#    define LWSYNC      lwsync
+#elif defined(CONFIG_E500)
+#    define LWSYNC                                      \
+        START_LWSYNC_SECTION(96);                       \
+        sync;                                           \
+        MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
+#else
+#    define LWSYNC      sync
+#endif
+
+#ifdef CONFIG_SMP
+#define ISYNC_ON_SMP    "\n\tisync\n"
+#define LWSYNC_ON_SMP   stringify_in_c(LWSYNC) "\n"
+#else
+#define ISYNC_ON_SMP
+#define LWSYNC_ON_SMP
+#endif
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_SYNCH_H */
diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/syscall.h
new file mode 100644
index 000000000000..efa7f0b879f3
--- /dev/null
+++ b/arch/powerpc/include/asm/syscall.h
@@ -0,0 +1,84 @@
+/*
+ * Access to user system call parameters and results
+ *
+ * Copyright (C) 2008 Red Hat, Inc.  All rights reserved.
+ *
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the GNU General Public License v.2.
+ *
+ * See asm-generic/syscall.h for descriptions of what we must do here.
+ */
+
+#ifndef _ASM_SYSCALL_H
+#define _ASM_SYSCALL_H  1
+
+#include <linux/sched.h>
+
+static inline long syscall_get_nr(struct task_struct *task,
+                                  struct pt_regs *regs)
+{
+        return TRAP(regs) == 0xc00 ? regs->gpr[0] : -1L;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        regs->gpr[3] = regs->orig_gpr3;
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        return (regs->ccr & 0x1000) ? -regs->gpr[3] : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->gpr[3];
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        if (error) {
+                regs->ccr |= 0x1000L;
+                regs->gpr[3] = -error;
+        } else {
+                regs->ccr &= ~0x1000L;
+                regs->gpr[3] = val;
+        }
+}
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+#ifdef CONFIG_PPC64
+        if (test_tsk_thread_flag(task, TIF_32BIT)) {
+                /*
+                 * Zero-extend 32-bit argument values.  The high bits are
+                 * garbage ignored by the actual syscall dispatch.
+                 */
+                while (n-- > 0)
+                        args[n] = (u32) regs->gpr[3 + i + n];
+                return;
+        }
+#endif
+        memcpy(args, &regs->gpr[3 + i], n * sizeof(args[0]));
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+        memcpy(&regs->gpr[3 + i], args, n * sizeof(args[0]));
+}
+
+#endif  /* _ASM_SYSCALL_H */
diff --git a/arch/powerpc/include/asm/syscalls.h b/arch/powerpc/include/asm/syscalls.h
new file mode 100644
index 000000000000..eb8eb400c664
--- /dev/null
+++ b/arch/powerpc/include/asm/syscalls.h
@@ -0,0 +1,52 @@
+#ifndef __ASM_POWERPC_SYSCALLS_H
+#define __ASM_POWERPC_SYSCALLS_H
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <asm/signal.h>
+
+struct new_utsname;
+struct pt_regs;
+struct rtas_args;
+struct sigaction;
+
+asmlinkage unsigned long sys_mmap(unsigned long addr, size_t len,
+                unsigned long prot, unsigned long flags,
+                unsigned long fd, off_t offset);
+asmlinkage unsigned long sys_mmap2(unsigned long addr, size_t len,
+                unsigned long prot, unsigned long flags,
+                unsigned long fd, unsigned long pgoff);
+asmlinkage int sys_execve(unsigned long a0, unsigned long a1,
+                unsigned long a2, unsigned long a3, unsigned long a4,
+                unsigned long a5, struct pt_regs *regs);
+asmlinkage int sys_clone(unsigned long clone_flags, unsigned long usp,
+                int __user *parent_tidp, void __user *child_threadptr,
+                int __user *child_tidp, int p6, struct pt_regs *regs);
+asmlinkage int sys_fork(unsigned long p1, unsigned long p2,
+                unsigned long p3, unsigned long p4, unsigned long p5,
+                unsigned long p6, struct pt_regs *regs);
+asmlinkage int sys_vfork(unsigned long p1, unsigned long p2,
+                unsigned long p3, unsigned long p4, unsigned long p5,
+                unsigned long p6, struct pt_regs *regs);
+asmlinkage long sys_pipe(int __user *fildes);
+asmlinkage long sys_pipe2(int __user *fildes, int flags);
+asmlinkage long sys_rt_sigaction(int sig,
+                const struct sigaction __user *act,
+                struct sigaction __user *oact, size_t sigsetsize);
+asmlinkage int sys_ipc(uint call, int first, unsigned long second,
+                long third, void __user *ptr, long fifth);
+asmlinkage long ppc64_personality(unsigned long personality);
+asmlinkage int ppc_rtas(struct rtas_args __user *uargs);
+asmlinkage time_t sys64_time(time_t __user * tloc);
+asmlinkage long ppc_newuname(struct new_utsname __user * name);
+
+asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset,
+                size_t sigsetsize);
+asmlinkage long sys_sigaltstack(const stack_t __user *uss,
+                stack_t __user *uoss, unsigned long r5, unsigned long r6,
+                unsigned long r7, unsigned long r8, struct pt_regs *regs);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_SYSCALLS_H */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
new file mode 100644
index 000000000000..e084272ed1c2
--- /dev/null
+++ b/arch/powerpc/include/asm/systbl.h
@@ -0,0 +1,324 @@
+/*
+ * List of powerpc syscalls. For the meaning of the _SPU suffix see
+ * arch/powerpc/platforms/cell/spu_callbacks.c
+ */
+
+SYSCALL(restart_syscall)
+SYSCALL(exit)
+PPC_SYS(fork)
+SYSCALL_SPU(read)
+SYSCALL_SPU(write)
+COMPAT_SYS_SPU(open)
+SYSCALL_SPU(close)
+COMPAT_SYS_SPU(waitpid)
+COMPAT_SYS_SPU(creat)
+SYSCALL_SPU(link)
+SYSCALL_SPU(unlink)
+COMPAT_SYS(execve)
+SYSCALL_SPU(chdir)
+COMPAT_SYS_SPU(time)
+SYSCALL_SPU(mknod)
+SYSCALL_SPU(chmod)
+SYSCALL_SPU(lchown)
+SYSCALL(ni_syscall)
+OLDSYS(stat)
+SYSX_SPU(sys_lseek,ppc32_lseek,sys_lseek)
+SYSCALL_SPU(getpid)
+COMPAT_SYS(mount)
+SYSX(sys_ni_syscall,sys_oldumount,sys_oldumount)
+SYSCALL_SPU(setuid)
+SYSCALL_SPU(getuid)
+COMPAT_SYS_SPU(stime)
+COMPAT_SYS(ptrace)
+SYSCALL_SPU(alarm)
+OLDSYS(fstat)
+COMPAT_SYS(pause)
+COMPAT_SYS(utime)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(access)
+COMPAT_SYS_SPU(nice)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(sync)
+COMPAT_SYS_SPU(kill)
+SYSCALL_SPU(rename)
+COMPAT_SYS_SPU(mkdir)
+SYSCALL_SPU(rmdir)
+SYSCALL_SPU(dup)
+SYSCALL_SPU(pipe)
+COMPAT_SYS_SPU(times)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(brk)
+SYSCALL_SPU(setgid)
+SYSCALL_SPU(getgid)
+SYSCALL(signal)
+SYSCALL_SPU(geteuid)
+SYSCALL_SPU(getegid)
+SYSCALL(acct)
+SYSCALL(umount)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(ioctl)
+COMPAT_SYS_SPU(fcntl)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(setpgid)
+SYSCALL(ni_syscall)
+SYSX(sys_ni_syscall,sys_olduname, sys_olduname)
+COMPAT_SYS_SPU(umask)
+SYSCALL_SPU(chroot)
+SYSCALL(ustat)
+SYSCALL_SPU(dup2)
+SYSCALL_SPU(getppid)
+SYSCALL_SPU(getpgrp)
+SYSCALL_SPU(setsid)
+SYS32ONLY(sigaction)
+SYSCALL_SPU(sgetmask)
+COMPAT_SYS_SPU(ssetmask)
+SYSCALL_SPU(setreuid)
+SYSCALL_SPU(setregid)
+SYS32ONLY(sigsuspend)
+COMPAT_SYS(sigpending)
+COMPAT_SYS_SPU(sethostname)
+COMPAT_SYS_SPU(setrlimit)
+COMPAT_SYS(old_getrlimit)
+COMPAT_SYS_SPU(getrusage)
+COMPAT_SYS_SPU(gettimeofday)
+COMPAT_SYS_SPU(settimeofday)
+COMPAT_SYS_SPU(getgroups)
+COMPAT_SYS_SPU(setgroups)
+SYSX(sys_ni_syscall,sys_ni_syscall,ppc_select)
+SYSCALL_SPU(symlink)
+OLDSYS(lstat)
+COMPAT_SYS_SPU(readlink)
+SYSCALL(uselib)
+SYSCALL(swapon)
+SYSCALL(reboot)
+SYSX(sys_ni_syscall,old32_readdir,old_readdir)
+SYSCALL_SPU(mmap)
+SYSCALL_SPU(munmap)
+SYSCALL_SPU(truncate)
+SYSCALL_SPU(ftruncate)
+SYSCALL_SPU(fchmod)
+SYSCALL_SPU(fchown)
+COMPAT_SYS_SPU(getpriority)
+COMPAT_SYS_SPU(setpriority)
+SYSCALL(ni_syscall)
+COMPAT_SYS(statfs)
+COMPAT_SYS(fstatfs)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(socketcall)
+COMPAT_SYS_SPU(syslog)
+COMPAT_SYS_SPU(setitimer)
+COMPAT_SYS_SPU(getitimer)
+COMPAT_SYS_SPU(newstat)
+COMPAT_SYS_SPU(newlstat)
+COMPAT_SYS_SPU(newfstat)
+SYSX(sys_ni_syscall,sys_uname,sys_uname)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(vhangup)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(wait4)
+SYSCALL(swapoff)
+COMPAT_SYS_SPU(sysinfo)
+COMPAT_SYS(ipc)
+SYSCALL_SPU(fsync)
+SYS32ONLY(sigreturn)
+PPC_SYS(clone)
+COMPAT_SYS_SPU(setdomainname)
+PPC_SYS_SPU(newuname)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(adjtimex)
+SYSCALL_SPU(mprotect)
+SYSX(sys_ni_syscall,compat_sys_sigprocmask,sys_sigprocmask)
+SYSCALL(ni_syscall)
+SYSCALL(init_module)
+SYSCALL(delete_module)
+SYSCALL(ni_syscall)
+SYSCALL(quotactl)
+COMPAT_SYS_SPU(getpgid)
+SYSCALL_SPU(fchdir)
+SYSCALL_SPU(bdflush)
+COMPAT_SYS(sysfs)
+SYSX_SPU(ppc64_personality,ppc64_personality,sys_personality)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(setfsuid)
+SYSCALL_SPU(setfsgid)
+SYSCALL_SPU(llseek)
+COMPAT_SYS_SPU(getdents)
+SYSX_SPU(sys_select,ppc32_select,ppc_select)
+SYSCALL_SPU(flock)
+SYSCALL_SPU(msync)
+COMPAT_SYS_SPU(readv)
+COMPAT_SYS_SPU(writev)
+COMPAT_SYS_SPU(getsid)
+SYSCALL_SPU(fdatasync)
+COMPAT_SYS(sysctl)
+SYSCALL_SPU(mlock)
+SYSCALL_SPU(munlock)
+SYSCALL_SPU(mlockall)
+SYSCALL_SPU(munlockall)
+COMPAT_SYS_SPU(sched_setparam)
+COMPAT_SYS_SPU(sched_getparam)
+COMPAT_SYS_SPU(sched_setscheduler)
+COMPAT_SYS_SPU(sched_getscheduler)
+SYSCALL_SPU(sched_yield)
+COMPAT_SYS_SPU(sched_get_priority_max)
+COMPAT_SYS_SPU(sched_get_priority_min)
+COMPAT_SYS_SPU(sched_rr_get_interval)
+COMPAT_SYS_SPU(nanosleep)
+SYSCALL_SPU(mremap)
+SYSCALL_SPU(setresuid)
+SYSCALL_SPU(getresuid)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(poll)
+COMPAT_SYS(nfsservctl)
+SYSCALL_SPU(setresgid)
+SYSCALL_SPU(getresgid)
+COMPAT_SYS_SPU(prctl)
+COMPAT_SYS(rt_sigreturn)
+COMPAT_SYS(rt_sigaction)
+COMPAT_SYS(rt_sigprocmask)
+COMPAT_SYS(rt_sigpending)
+COMPAT_SYS(rt_sigtimedwait)
+COMPAT_SYS(rt_sigqueueinfo)
+COMPAT_SYS(rt_sigsuspend)
+COMPAT_SYS_SPU(pread64)
+COMPAT_SYS_SPU(pwrite64)
+SYSCALL_SPU(chown)
+SYSCALL_SPU(getcwd)
+SYSCALL_SPU(capget)
+SYSCALL_SPU(capset)
+COMPAT_SYS(sigaltstack)
+SYSX_SPU(sys_sendfile64,compat_sys_sendfile,sys_sendfile)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+PPC_SYS(vfork)
+COMPAT_SYS_SPU(getrlimit)
+COMPAT_SYS_SPU(readahead)
+SYS32ONLY(mmap2)
+SYS32ONLY(truncate64)
+SYS32ONLY(ftruncate64)
+SYSX(sys_ni_syscall,sys_stat64,sys_stat64)
+SYSX(sys_ni_syscall,sys_lstat64,sys_lstat64)
+SYSX(sys_ni_syscall,sys_fstat64,sys_fstat64)
+SYSCALL(pciconfig_read)
+SYSCALL(pciconfig_write)
+SYSCALL(pciconfig_iobase)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(getdents64)
+SYSCALL_SPU(pivot_root)
+SYSX(sys_ni_syscall,compat_sys_fcntl64,sys_fcntl64)
+SYSCALL_SPU(madvise)
+SYSCALL_SPU(mincore)
+SYSCALL_SPU(gettid)
+SYSCALL_SPU(tkill)
+SYSCALL_SPU(setxattr)
+SYSCALL_SPU(lsetxattr)
+SYSCALL_SPU(fsetxattr)
+SYSCALL_SPU(getxattr)
+SYSCALL_SPU(lgetxattr)
+SYSCALL_SPU(fgetxattr)
+SYSCALL_SPU(listxattr)
+SYSCALL_SPU(llistxattr)
+SYSCALL_SPU(flistxattr)
+SYSCALL_SPU(removexattr)
+SYSCALL_SPU(lremovexattr)
+SYSCALL_SPU(fremovexattr)
+COMPAT_SYS_SPU(futex)
+COMPAT_SYS_SPU(sched_setaffinity)
+COMPAT_SYS_SPU(sched_getaffinity)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+SYS32ONLY(sendfile64)
+COMPAT_SYS_SPU(io_setup)
+SYSCALL_SPU(io_destroy)
+COMPAT_SYS_SPU(io_getevents)
+COMPAT_SYS_SPU(io_submit)
+SYSCALL_SPU(io_cancel)
+SYSCALL(set_tid_address)
+SYSX_SPU(sys_fadvise64,ppc32_fadvise64,sys_fadvise64)
+SYSCALL(exit_group)
+SYSX(sys_lookup_dcookie,ppc32_lookup_dcookie,sys_lookup_dcookie)
+SYSCALL_SPU(epoll_create)
+SYSCALL_SPU(epoll_ctl)
+SYSCALL_SPU(epoll_wait)
+SYSCALL_SPU(remap_file_pages)
+SYSX_SPU(sys_timer_create,compat_sys_timer_create,sys_timer_create)
+COMPAT_SYS_SPU(timer_settime)
+COMPAT_SYS_SPU(timer_gettime)
+SYSCALL_SPU(timer_getoverrun)
+SYSCALL_SPU(timer_delete)
+COMPAT_SYS_SPU(clock_settime)
+COMPAT_SYS_SPU(clock_gettime)
+COMPAT_SYS_SPU(clock_getres)
+COMPAT_SYS_SPU(clock_nanosleep)
+SYSX(ppc64_swapcontext,ppc32_swapcontext,ppc_swapcontext)
+COMPAT_SYS_SPU(tgkill)
+COMPAT_SYS_SPU(utimes)
+COMPAT_SYS_SPU(statfs64)
+COMPAT_SYS_SPU(fstatfs64)
+SYSX(sys_ni_syscall, ppc_fadvise64_64, ppc_fadvise64_64)
+PPC_SYS_SPU(rtas)
+OLDSYS(debug_setcontext)
+SYSCALL(ni_syscall)
+COMPAT_SYS(migrate_pages)
+COMPAT_SYS(mbind)
+COMPAT_SYS(get_mempolicy)
+COMPAT_SYS(set_mempolicy)
+COMPAT_SYS(mq_open)
+SYSCALL(mq_unlink)
+COMPAT_SYS(mq_timedsend)
+COMPAT_SYS(mq_timedreceive)
+COMPAT_SYS(mq_notify)
+COMPAT_SYS(mq_getsetattr)
+COMPAT_SYS(kexec_load)
+COMPAT_SYS(add_key)
+COMPAT_SYS(request_key)
+COMPAT_SYS(keyctl)
+COMPAT_SYS(waitid)
+COMPAT_SYS(ioprio_set)
+COMPAT_SYS(ioprio_get)
+SYSCALL(inotify_init)
+SYSCALL(inotify_add_watch)
+SYSCALL(inotify_rm_watch)
+SYSCALL(spu_run)
+SYSCALL(spu_create)
+COMPAT_SYS(pselect6)
+COMPAT_SYS(ppoll)
+SYSCALL_SPU(unshare)
+SYSCALL_SPU(splice)
+SYSCALL_SPU(tee)
+COMPAT_SYS_SPU(vmsplice)
+COMPAT_SYS_SPU(openat)
+SYSCALL_SPU(mkdirat)
+SYSCALL_SPU(mknodat)
+SYSCALL_SPU(fchownat)
+COMPAT_SYS_SPU(futimesat)
+SYSX_SPU(sys_newfstatat, sys_fstatat64, sys_fstatat64)
+SYSCALL_SPU(unlinkat)
+SYSCALL_SPU(renameat)
+SYSCALL_SPU(linkat)
+SYSCALL_SPU(symlinkat)
+SYSCALL_SPU(readlinkat)
+SYSCALL_SPU(fchmodat)
+SYSCALL_SPU(faccessat)
+COMPAT_SYS_SPU(get_robust_list)
+COMPAT_SYS_SPU(set_robust_list)
+COMPAT_SYS_SPU(move_pages)
+SYSCALL_SPU(getcpu)
+COMPAT_SYS(epoll_pwait)
+COMPAT_SYS_SPU(utimensat)
+COMPAT_SYS_SPU(signalfd)
+SYSCALL_SPU(timerfd_create)
+SYSCALL_SPU(eventfd)
+COMPAT_SYS_SPU(sync_file_range2)
+COMPAT_SYS(fallocate)
+SYSCALL(subpage_prot)
+COMPAT_SYS_SPU(timerfd_settime)
+COMPAT_SYS_SPU(timerfd_gettime)
+COMPAT_SYS_SPU(signalfd4)
+SYSCALL_SPU(eventfd2)
+SYSCALL_SPU(epoll_create1)
+SYSCALL_SPU(dup3)
+SYSCALL_SPU(pipe2)
+SYSCALL(inotify_init1)
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
new file mode 100644
index 000000000000..d6648c143322
--- /dev/null
+++ b/arch/powerpc/include/asm/system.h
@@ -0,0 +1,548 @@
+/*
+ * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
+ */
+#ifndef _ASM_POWERPC_SYSTEM_H
+#define _ASM_POWERPC_SYSTEM_H
+
+#include <linux/kernel.h>
+#include <linux/irqflags.h>
+
+#include <asm/hw_irq.h>
+
+/*
+ * Memory barrier.
+ * The sync instruction guarantees that all memory accesses initiated
+ * by this processor have been performed (with respect to all other
+ * mechanisms that access memory).  The eieio instruction is a barrier
+ * providing an ordering (separately) for (a) cacheable stores and (b)
+ * loads and stores to non-cacheable memory (e.g. I/O devices).
+ *
+ * mb() prevents loads and stores being reordered across this point.
+ * rmb() prevents loads being reordered across this point.
+ * wmb() prevents stores being reordered across this point.
+ * read_barrier_depends() prevents data-dependent loads being reordered
+ *      across this point (nop on PPC).
+ *
+ * We have to use the sync instructions for mb(), since lwsync doesn't
+ * order loads with respect to previous stores.  Lwsync is fine for
+ * rmb(), though. Note that rmb() actually uses a sync on 32-bit
+ * architectures.
+ *
+ * For wmb(), we use sync since wmb is used in drivers to order
+ * stores to system memory with respect to writes to the device.
+ * However, smp_wmb() can be a lighter-weight lwsync or eieio barrier
+ * on SMP since it is only used to order updates to system memory.
+ */
+#define mb()   __asm__ __volatile__ ("sync" : : : "memory")
+#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
+#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
+#define read_barrier_depends()  do { } while(0)
+
+#define set_mb(var, value)      do { var = value; mb(); } while (0)
+
+#ifdef __KERNEL__
+#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
+#ifdef CONFIG_SMP
+
+#ifdef __SUBARCH_HAS_LWSYNC
+#    define SMPWMB      lwsync
+#else
+#    define SMPWMB      eieio
+#endif
+
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory")
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif /* CONFIG_SMP */
+
+/*
+ * This is a barrier which prevents following instructions from being
+ * started until the value of the argument x is known.  For example, if
+ * x is a variable loaded from memory, this prevents following
+ * instructions from being executed until the load has been performed.
+ */
+#define data_barrier(x) \
+        asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
+
+struct task_struct;
+struct pt_regs;
+
+#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
+
+extern int (*__debugger)(struct pt_regs *regs);
+extern int (*__debugger_ipi)(struct pt_regs *regs);
+extern int (*__debugger_bpt)(struct pt_regs *regs);
+extern int (*__debugger_sstep)(struct pt_regs *regs);
+extern int (*__debugger_iabr_match)(struct pt_regs *regs);
+extern int (*__debugger_dabr_match)(struct pt_regs *regs);
+extern int (*__debugger_fault_handler)(struct pt_regs *regs);
+
+#define DEBUGGER_BOILERPLATE(__NAME) \
+static inline int __NAME(struct pt_regs *regs) \
+{ \
+        if (unlikely(__ ## __NAME)) \
+                return __ ## __NAME(regs); \
+        return 0; \
+}
+
+DEBUGGER_BOILERPLATE(debugger)
+DEBUGGER_BOILERPLATE(debugger_ipi)
+DEBUGGER_BOILERPLATE(debugger_bpt)
+DEBUGGER_BOILERPLATE(debugger_sstep)
+DEBUGGER_BOILERPLATE(debugger_iabr_match)
+DEBUGGER_BOILERPLATE(debugger_dabr_match)
+DEBUGGER_BOILERPLATE(debugger_fault_handler)
+
+#else
+static inline int debugger(struct pt_regs *regs) { return 0; }
+static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
+static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
+static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
+static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
+static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
+static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
+#endif
+
+extern int set_dabr(unsigned long dabr);
+extern void do_dabr(struct pt_regs *regs, unsigned long address,
+                    unsigned long error_code);
+extern void print_backtrace(unsigned long *);
+extern void show_regs(struct pt_regs * regs);
+extern void flush_instruction_cache(void);
+extern void hard_reset_now(void);
+extern void poweroff_now(void);
+
+#ifdef CONFIG_6xx
+extern long _get_L2CR(void);
+extern long _get_L3CR(void);
+extern void _set_L2CR(unsigned long);
+extern void _set_L3CR(unsigned long);
+#else
+#define _get_L2CR()     0L
+#define _get_L3CR()     0L
+#define _set_L2CR(val)  do { } while(0)
+#define _set_L3CR(val)  do { } while(0)
+#endif
+
+extern void via_cuda_init(void);
+extern void read_rtc_time(void);
+extern void pmac_find_display(void);
+extern void giveup_fpu(struct task_struct *);
+extern void disable_kernel_fp(void);
+extern void enable_kernel_fp(void);
+extern void flush_fp_to_thread(struct task_struct *);
+extern void enable_kernel_altivec(void);
+extern void giveup_altivec(struct task_struct *);
+extern void load_up_altivec(struct task_struct *);
+extern int emulate_altivec(struct pt_regs *);
+extern void __giveup_vsx(struct task_struct *);
+extern void giveup_vsx(struct task_struct *);
+extern void enable_kernel_spe(void);
+extern void giveup_spe(struct task_struct *);
+extern void load_up_spe(struct task_struct *);
+extern int fix_alignment(struct pt_regs *);
+extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
+extern void cvt_df(double *from, float *to, struct thread_struct *thread);
+
+#ifndef CONFIG_SMP
+extern void discard_lazy_cpu_state(void);
+#else
+static inline void discard_lazy_cpu_state(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ALTIVEC
+extern void flush_altivec_to_thread(struct task_struct *);
+#else
+static inline void flush_altivec_to_thread(struct task_struct *t)
+{
+}
+#endif
+
+#ifdef CONFIG_VSX
+extern void flush_vsx_to_thread(struct task_struct *);
+#else
+static inline void flush_vsx_to_thread(struct task_struct *t)
+{
+}
+#endif
+
+#ifdef CONFIG_SPE
+extern void flush_spe_to_thread(struct task_struct *);
+#else
+static inline void flush_spe_to_thread(struct task_struct *t)
+{
+}
+#endif
+
+extern int call_rtas(const char *, int, int, unsigned long *, ...);
+extern void cacheable_memzero(void *p, unsigned int nb);
+extern void *cacheable_memcpy(void *, const void *, unsigned int);
+extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
+extern void bad_page_fault(struct pt_regs *, unsigned long, int);
+extern int die(const char *, struct pt_regs *, long);
+extern void _exception(int, struct pt_regs *, int, unsigned long);
+extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
+
+#ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+#endif /* CONFIG_BOOKE_WDT */
+
+struct device_node;
+extern void note_scsi_host(struct device_node *, void *);
+
+extern struct task_struct *__switch_to(struct task_struct *,
+        struct task_struct *);
+#define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
+
+struct thread_struct;
+extern struct task_struct *_switch(struct thread_struct *prev,
+                                   struct thread_struct *next);
+
+extern unsigned int rtas_data;
+extern int mem_init_done;       /* set on boot once kmalloc can be called */
+extern int init_bootmem_done;   /* set on !NUMA once bootmem is available */
+extern unsigned long memory_limit;
+extern unsigned long klimit;
+
+extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
+extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
+
+extern int powersave_nap;       /* set if nap mode can be used in idle loop */
+
+/*
+ * Atomic exchange
+ *
+ * Changes the memory location '*ptr' to be val and returns
+ * the previous value stored there.
+ */
+static __always_inline unsigned long
+__xchg_u32(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %3,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
+        : "r" (p), "r" (val)
+        : "cc", "memory");
+
+        return prev;
+}
+
+/*
+ * Atomic exchange
+ *
+ * Changes the memory location '*ptr' to be val and returns
+ * the previous value stored there.
+ */
+static __always_inline unsigned long
+__xchg_u32_local(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %3,0,%2 \n\
+        bne-    1b"
+        : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
+        : "r" (p), "r" (val)
+        : "cc", "memory");
+
+        return prev;
+}
+
+#ifdef CONFIG_PPC64
+static __always_inline unsigned long
+__xchg_u64(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stdcx.  %3,0,%2 \n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
+        : "r" (p), "r" (val)
+        : "cc", "memory");
+
+        return prev;
+}
+
+static __always_inline unsigned long
+__xchg_u64_local(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+"1:     ldarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stdcx.  %3,0,%2 \n\
+        bne-    1b"
+        : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
+        : "r" (p), "r" (val)
+        : "cc", "memory");
+
+        return prev;
+}
+#endif
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid xchg().
+ */
+extern void __xchg_called_with_bad_pointer(void);
+
+static __always_inline unsigned long
+__xchg(volatile void *ptr, unsigned long x, unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __xchg_u32(ptr, x);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __xchg_u64(ptr, x);
+#endif
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+static __always_inline unsigned long
+__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __xchg_u32_local(ptr, x);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __xchg_u64_local(ptr, x);
+#endif
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+#define xchg(ptr,x)                                                          \
+  ({                                                                         \
+     __typeof__(*(ptr)) _x_ = (x);                                           \
+     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
+  })
+
+#define xchg_local(ptr,x)                                                    \
+  ({                                                                         \
+     __typeof__(*(ptr)) _x_ = (x);                                           \
+     (__typeof__(*(ptr))) __xchg_local((ptr),                                \
+                (unsigned long)_x_, sizeof(*(ptr)));                         \
+  })
+
+/*
+ * Compare and exchange - if *p == old, set it to new,
+ * and return the old value of *p.
+ */
+#define __HAVE_ARCH_CMPXCHG     1
+
+static __always_inline unsigned long
+__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
+{
+        unsigned int prev;
+
+        __asm__ __volatile__ (
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
+        cmpw    0,%0,%3\n\
+        bne-    2f\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %4,0,%2\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
+        : "cc", "memory");
+
+        return prev;
+}
+
+static __always_inline unsigned long
+__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
+                        unsigned long new)
+{
+        unsigned int prev;
+
+        __asm__ __volatile__ (
+"1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
+        cmpw    0,%0,%3\n\
+        bne-    2f\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %4,0,%2\n\
+        bne-    1b"
+        "\n\
+2:"
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
+        : "cc", "memory");
+
+        return prev;
+}
+
+#ifdef CONFIG_PPC64
+static __always_inline unsigned long
+__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__ (
+        LWSYNC_ON_SMP
+"1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
+        cmpd    0,%0,%3\n\
+        bne-    2f\n\
+        stdcx.  %4,0,%2\n\
+        bne-    1b"
+        ISYNC_ON_SMP
+        "\n\
+2:"
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
+        : "cc", "memory");
+
+        return prev;
+}
+
+static __always_inline unsigned long
+__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
+                        unsigned long new)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__ (
+"1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
+        cmpd    0,%0,%3\n\
+        bne-    2f\n\
+        stdcx.  %4,0,%2\n\
+        bne-    1b"
+        "\n\
+2:"
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
+        : "cc", "memory");
+
+        return prev;
+}
+#endif
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid cmpxchg().  */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static __always_inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
+          unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32(ptr, old, new);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __cmpxchg_u64(ptr, old, new);
+#endif
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+static __always_inline unsigned long
+__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
+          unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32_local(ptr, old, new);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __cmpxchg_u64_local(ptr, old, new);
+#endif
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr, o, n)                                               \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+
+#define cmpxchg_local(ptr, o, n)                                         \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+#ifdef CONFIG_PPC64
+/*
+ * We handle most unaligned accesses in hardware. On the other hand 
+ * unaligned DMA can be very expensive on some ppc64 IO chips (it does
+ * powers of 2 writes until it reaches sufficient alignment).
+ *
+ * Based on this we disable the IP header alignment in network drivers.
+ * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
+ * cacheline alignment of buffers.
+ */
+#define NET_IP_ALIGN    0
+#define NET_SKB_PAD     L1_CACHE_BYTES
+
+#define cmpxchg64(ptr, o, n)                                            \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg((ptr), (o), (n));                                       \
+  })
+#define cmpxchg64_local(ptr, o, n)                                      \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg_local((ptr), (o), (n));                                 \
+  })
+#else
+#include <asm-generic/cmpxchg-local.h>
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+#endif
+
+#define arch_align_stack(x) (x)
+
+/* Used in very early kernel initialization. */
+extern unsigned long reloc_offset(void);
+extern unsigned long add_reloc_offset(unsigned long);
+extern void reloc_got2(unsigned long);
+
+#define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
+
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+extern void account_system_vtime(struct task_struct *);
+#endif
+
+extern struct dentry *powerpc_debugfs_root;
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
new file mode 100644
index 000000000000..f663634cccc9
--- /dev/null
+++ b/arch/powerpc/include/asm/tce.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
+ * Rewrite, cleanup:
+ * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_TCE_H
+#define _ASM_POWERPC_TCE_H
+#ifdef __KERNEL__
+
+#include <asm/iommu.h>
+
+/*
+ * Tces come in two formats, one for the virtual bus and a different
+ * format for PCI
+ */
+#define TCE_VB  0
+#define TCE_PCI 1
+
+/* TCE page size is 4096 bytes (1 << 12) */
+
+#define TCE_SHIFT       12
+#define TCE_PAGE_SIZE   (1 << TCE_SHIFT)
+
+#define TCE_ENTRY_SIZE          8               /* each TCE is 64 bits */
+
+#define TCE_RPN_MASK            0xfffffffffful  /* 40-bit RPN (4K pages) */
+#define TCE_RPN_SHIFT           12
+#define TCE_VALID               0x800           /* TCE valid */
+#define TCE_ALLIO               0x400           /* TCE valid for all lpars */
+#define TCE_PCI_WRITE           0x2             /* write from PCI allowed */
+#define TCE_PCI_READ            0x1             /* read from PCI allowed */
+#define TCE_VB_WRITE            0x1             /* write from VB allowed */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_TCE_H */
diff --git a/arch/powerpc/include/asm/termbits.h b/arch/powerpc/include/asm/termbits.h
new file mode 100644
index 000000000000..6698188ca550
--- /dev/null
+++ b/arch/powerpc/include/asm/termbits.h
@@ -0,0 +1,209 @@
+#ifndef _ASM_POWERPC_TERMBITS_H
+#define _ASM_POWERPC_TERMBITS_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+/*
+ * termios type and macro definitions.  Be careful about adding stuff
+ * to this file since it's used in GNU libc and there are strict rules
+ * concerning namespace pollution.
+ */
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t c_line;                    /* line discipline (== c_cc[19]) */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* For PowerPC the termios and ktermios are the same */
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t c_line;                    /* line discipline (== c_cc[19]) */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR            0
+#define VQUIT            1
+#define VERASE           2
+#define VKILL            3
+#define VEOF             4
+#define VMIN             5
+#define VEOL             6
+#define VTIME            7
+#define VEOL2            8
+#define VSWTC            9
+#define VWERASE         10
+#define VREPRINT        11
+#define VSUSP           12
+#define VSTART          13
+#define VSTOP           14
+#define VLNEXT          15
+#define VDISCARD        16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IXON    0001000
+#define IXOFF   0002000
+#define IXANY   0004000
+#define IUCLC   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define ONLCR   0000002
+#define OLCUC   0000004
+
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+
+#define OFILL   00000100
+#define OFDEL   00000200
+#define NLDLY   00001400
+#define   NL0   00000000
+#define   NL1   00000400
+#define   NL2   00001000
+#define   NL3   00001400
+#define TABDLY  00006000
+#define   TAB0  00000000
+#define   TAB1  00002000
+#define   TAB2  00004000
+#define   TAB3  00006000
+#define   XTABS 00006000        /* required by POSIX to == TAB3 */
+#define CRDLY   00030000
+#define   CR0   00000000
+#define   CR1   00010000
+#define   CR2   00020000
+#define   CR3   00030000
+#define FFDLY   00040000
+#define   FF0   00000000
+#define   FF1   00040000
+#define BSDLY   00100000
+#define   BS0   00000000
+#define   BS1   00100000
+#define VTDLY   00200000
+#define   VT0   00000000
+#define   VT1   00200000
+
+/* c_cflag bit meaning */
+#define CBAUD   0000377
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define  EXTA   B19200
+#define  EXTB   B38400
+#define  CBAUDEX 0000000
+#define  B57600   00020
+#define  B115200  00021
+#define  B230400  00022
+#define  B460800  00023
+#define  B500000  00024
+#define  B576000  00025
+#define  B921600  00026
+#define B1000000  00027
+#define B1152000  00030
+#define B1500000  00031
+#define B2000000  00032
+#define B2500000  00033
+#define B3000000  00034
+#define B3500000  00035
+#define B4000000  00036
+#define   BOTHER  00037
+
+#define CIBAUD  077600000
+#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
+
+#define CSIZE   00001400
+#define   CS5   00000000
+#define   CS6   00000400
+#define   CS7   00001000
+#define   CS8   00001400
+
+#define CSTOPB  00002000
+#define CREAD   00004000
+#define PARENB  00010000
+#define PARODD  00020000
+#define HUPCL   00040000
+
+#define CLOCAL  00100000
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+/* c_lflag bits */
+#define ISIG    0x00000080
+#define ICANON  0x00000100
+#define XCASE   0x00004000
+#define ECHO    0x00000008
+#define ECHOE   0x00000002
+#define ECHOK   0x00000004
+#define ECHONL  0x00000010
+#define NOFLSH  0x80000000
+#define TOSTOP  0x00400000
+#define ECHOCTL 0x00000040
+#define ECHOPRT 0x00000020
+#define ECHOKE  0x00000001
+#define FLUSHO  0x00800000
+#define PENDIN  0x20000000
+#define IEXTEN  0x00000400
+
+/* Values for the ACTION argument to `tcflow'.  */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* Values for the QUEUE_SELECTOR argument to `tcflush'.  */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'.  */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif  /* _ASM_POWERPC_TERMBITS_H */
diff --git a/arch/powerpc/include/asm/termios.h b/arch/powerpc/include/asm/termios.h
new file mode 100644
index 000000000000..2c14fea07c8a
--- /dev/null
+++ b/arch/powerpc/include/asm/termios.h
@@ -0,0 +1,85 @@
+#ifndef _ASM_POWERPC_TERMIOS_H
+#define _ASM_POWERPC_TERMIOS_H
+
+/*
+ * Liberally adapted from alpha/termios.h.  In particular, the c_cc[]
+ * fields have been reordered so that termio & termios share the
+ * common subset in the same order (for brain dead programs that don't
+ * know or care about the differences).
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/ioctls.h>
+#include <asm/termbits.h>
+
+struct sgttyb {
+        char    sg_ispeed;
+        char    sg_ospeed;
+        char    sg_erase;
+        char    sg_kill;
+        short   sg_flags;
+};
+
+struct tchars {
+        char    t_intrc;
+        char    t_quitc;
+        char    t_startc;
+        char    t_stopc;
+        char    t_eofc;
+        char    t_brkc;
+};
+
+struct ltchars {
+        char    t_suspc;
+        char    t_dsuspc;
+        char    t_rprntc;
+        char    t_flushc;
+        char    t_werasc;
+        char    t_lnextc;
+};
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 10
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* c_cc characters */
+#define _VINTR  0
+#define _VQUIT  1
+#define _VERASE 2
+#define _VKILL  3
+#define _VEOF   4
+#define _VMIN   5
+#define _VEOL   6
+#define _VTIME  7
+#define _VEOL2  8
+#define _VSWTC  9
+
+#ifdef __KERNEL__
+/*                   ^C  ^\ del  ^U  ^D   1   0   0   0   0  ^W  ^R  ^Z  ^Q  ^S  ^V  ^U  */
+#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025" 
+#endif
+
+#ifdef __KERNEL__
+
+#include <asm-generic/termios.h>
+
+#endif  /* __KERNEL__ */
+
+#endif  /* _ASM_POWERPC_TERMIOS_H */
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
new file mode 100644
index 000000000000..9665a26a253a
--- /dev/null
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -0,0 +1,161 @@
+/* thread_info.h: PowerPC low-level thread information
+ * adapted from the i386 version by Paul Mackerras
+ *
+ * Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_POWERPC_THREAD_INFO_H
+#define _ASM_POWERPC_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+/* We have 8k stacks on ppc32 and 16k on ppc64 */
+
+#ifdef CONFIG_PPC64
+#define THREAD_SHIFT            14
+#else
+#define THREAD_SHIFT            13
+#endif
+
+#define THREAD_SIZE             (1 << THREAD_SHIFT)
+
+#ifndef __ASSEMBLY__
+#include <linux/cache.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <linux/stringify.h>
+
+/*
+ * low level task data.
+ */
+struct thread_info {
+        struct task_struct *task;               /* main task structure */
+        struct exec_domain *exec_domain;        /* execution domain */
+        int             cpu;                    /* cpu we're on */
+        int             preempt_count;          /* 0 => preemptable,
+                                                   <0 => BUG */
+        struct restart_block restart_block;
+        unsigned long   local_flags;            /* private flags for thread */
+
+        /* low level flags - has atomic operations done on it */
+        unsigned long   flags ____cacheline_aligned_in_smp;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task =         &tsk,                   \
+        .exec_domain =  &default_exec_domain,   \
+        .cpu =          0,                      \
+        .preempt_count = 1,                     \
+        .restart_block = {                      \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+        .flags =        0,                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* thread information allocation */
+
+#if THREAD_SHIFT >= PAGE_SHIFT
+
+#define THREAD_SIZE_ORDER       (THREAD_SHIFT - PAGE_SHIFT)
+
+#else /* THREAD_SHIFT < PAGE_SHIFT */
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
+extern void free_thread_info(struct thread_info *ti);
+
+#endif /* THREAD_SHIFT < PAGE_SHIFT */
+
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+        register unsigned long sp asm("r1");
+
+        /* gcc4, at least, is smart enough to turn this into a single
+         * rlwinm for ppc32 and clrrdi for ppc64 */
+        return (struct thread_info *)(sp & ~(THREAD_SIZE-1));
+}
+
+#endif /* __ASSEMBLY__ */
+
+#define PREEMPT_ACTIVE          0x10000000
+
+/*
+ * thread information flag bit numbers
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_SIGPENDING          1       /* signal pending */
+#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
+#define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
+                                           TIF_NEED_RESCHED */
+#define TIF_32BIT               4       /* 32 bit binary */
+#define TIF_PERFMON_WORK        5       /* work for pfm_handle_work() */
+#define TIF_PERFMON_CTXSW       6       /* perfmon needs ctxsw calls */
+#define TIF_SYSCALL_AUDIT       7       /* syscall auditing active */
+#define TIF_SINGLESTEP          8       /* singlestepping active */
+#define TIF_MEMDIE              9
+#define TIF_SECCOMP             10      /* secure computing */
+#define TIF_RESTOREALL          11      /* Restore all regs (implies NOERROR) */
+#define TIF_NOERROR             12      /* Force successful syscall return */
+#define TIF_NOTIFY_RESUME       13      /* callback before returning to user */
+#define TIF_FREEZE              14      /* Freezing for suspend */
+#define TIF_RUNLATCH            15      /* Is the runlatch enabled? */
+#define TIF_ABI_PENDING         16      /* 32/64 bit switch needed */
+
+/* as above, but as bit values */
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_32BIT              (1<<TIF_32BIT)
+#define _TIF_PERFMON_WORK       (1<<TIF_PERFMON_WORK)
+#define _TIF_PERFMON_CTXSW      (1<<TIF_PERFMON_CTXSW)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
+#define _TIF_RESTOREALL         (1<<TIF_RESTOREALL)
+#define _TIF_NOERROR            (1<<TIF_NOERROR)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
+#define _TIF_RUNLATCH           (1<<TIF_RUNLATCH)
+#define _TIF_ABI_PENDING        (1<<TIF_ABI_PENDING)
+#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
+
+#define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
+                                 _TIF_NOTIFY_RESUME)
+#define _TIF_PERSYSCALL_MASK    (_TIF_RESTOREALL|_TIF_NOERROR)
+
+/* Bits in local_flags */
+/* Don't move TLF_NAPPING without adjusting the code in entry_32.S */
+#define TLF_NAPPING             0       /* idle thread enabled NAP mode */
+#define TLF_SLEEPING            1       /* suspend code enabled SLEEP mode */
+#define TLF_RESTORE_SIGMASK     2       /* Restore signal mask in do_signal */
+
+#define _TLF_NAPPING            (1 << TLF_NAPPING)
+#define _TLF_SLEEPING           (1 << TLF_SLEEPING)
+#define _TLF_RESTORE_SIGMASK    (1 << TLF_RESTORE_SIGMASK)
+
+#ifndef __ASSEMBLY__
+#define HAVE_SET_RESTORE_SIGMASK        1
+static inline void set_restore_sigmask(void)
+{
+        struct thread_info *ti = current_thread_info();
+        ti->local_flags |= _TLF_RESTORE_SIGMASK;
+        set_bit(TIF_SIGPENDING, &ti->flags);
+}
+#endif  /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_THREAD_INFO_H */
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
new file mode 100644
index 000000000000..febd581ec9b0
--- /dev/null
+++ b/arch/powerpc/include/asm/time.h
@@ -0,0 +1,255 @@
+/*
+ * Common time prototypes and such for all ppc machines.
+ *
+ * Written by Cort Dougan (cort@cs.nmt.edu) to merge
+ * Paul Mackerras' version and mine for PReP and Pmac.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __POWERPC_TIME_H
+#define __POWERPC_TIME_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#include <linux/percpu.h>
+
+#include <asm/processor.h>
+#ifdef CONFIG_PPC_ISERIES
+#include <asm/paca.h>
+#include <asm/firmware.h>
+#include <asm/iseries/hv_call.h>
+#endif
+
+/* time.c */
+extern unsigned long tb_ticks_per_jiffy;
+extern unsigned long tb_ticks_per_usec;
+extern unsigned long tb_ticks_per_sec;
+extern u64 tb_to_xs;
+extern unsigned      tb_to_us;
+
+struct rtc_time;
+extern void to_tm(int tim, struct rtc_time * tm);
+extern void GregorianDay(struct rtc_time *tm);
+extern time_t last_rtc_update;
+
+extern void generic_calibrate_decr(void);
+extern void wakeup_decrementer(void);
+extern void snapshot_timebase(void);
+
+extern void set_dec_cpu6(unsigned int val);
+
+/* Some sane defaults: 125 MHz timebase, 1GHz processor */
+extern unsigned long ppc_proc_freq;
+#define DEFAULT_PROC_FREQ       (DEFAULT_TB_FREQ * 8)
+extern unsigned long ppc_tb_freq;
+#define DEFAULT_TB_FREQ         125000000UL
+
+/*
+ * By putting all of this stuff into a single struct we 
+ * reduce the number of cache lines touched by do_gettimeofday.
+ * Both by collecting all of the data in one cache line and
+ * by touching only one TOC entry on ppc64.
+ */
+struct gettimeofday_vars {
+        u64 tb_to_xs;
+        u64 stamp_xsec;
+        u64 tb_orig_stamp;
+};
+
+struct gettimeofday_struct {
+        unsigned long tb_ticks_per_sec;
+        struct gettimeofday_vars vars[2];
+        struct gettimeofday_vars * volatile varp;
+        unsigned      var_idx;
+        unsigned      tb_to_us;
+};
+
+struct div_result {
+        u64 result_high;
+        u64 result_low;
+};
+
+/* Accessor functions for the timebase (RTC on 601) registers. */
+/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
+#ifdef CONFIG_6xx
+#define __USE_RTC()     (!cpu_has_feature(CPU_FTR_USE_TB))
+#else
+#define __USE_RTC()     0
+#endif
+
+#ifdef CONFIG_PPC64
+
+/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
+#define get_tbl         get_tb
+
+#else
+
+static inline unsigned long get_tbl(void)
+{
+#if defined(CONFIG_403GCX)
+        unsigned long tbl;
+        asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
+        return tbl;
+#else
+        return mftbl();
+#endif
+}
+
+static inline unsigned int get_tbu(void)
+{
+#ifdef CONFIG_403GCX
+        unsigned int tbu;
+        asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
+        return tbu;
+#else
+        return mftbu();
+#endif
+}
+#endif /* !CONFIG_PPC64 */
+
+static inline unsigned int get_rtcl(void)
+{
+        unsigned int rtcl;
+
+        asm volatile("mfrtcl %0" : "=r" (rtcl));
+        return rtcl;
+}
+
+static inline u64 get_rtc(void)
+{
+        unsigned int hi, lo, hi2;
+
+        do {
+                asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2"
+                             : "=r" (hi), "=r" (lo), "=r" (hi2));
+        } while (hi2 != hi);
+        return (u64)hi * 1000000000 + lo;
+}
+
+#ifdef CONFIG_PPC64
+static inline u64 get_tb(void)
+{
+        return mftb();
+}
+#else /* CONFIG_PPC64 */
+static inline u64 get_tb(void)
+{
+        unsigned int tbhi, tblo, tbhi2;
+
+        do {
+                tbhi = get_tbu();
+                tblo = get_tbl();
+                tbhi2 = get_tbu();
+        } while (tbhi != tbhi2);
+
+        return ((u64)tbhi << 32) | tblo;
+}
+#endif /* !CONFIG_PPC64 */
+
+static inline u64 get_tb_or_rtc(void)
+{
+        return __USE_RTC() ? get_rtc() : get_tb();
+}
+
+static inline void set_tb(unsigned int upper, unsigned int lower)
+{
+        mtspr(SPRN_TBWL, 0);
+        mtspr(SPRN_TBWU, upper);
+        mtspr(SPRN_TBWL, lower);
+}
+
+/* Accessor functions for the decrementer register.
+ * The 4xx doesn't even have a decrementer.  I tried to use the
+ * generic timer interrupt code, which seems OK, with the 4xx PIT
+ * in auto-reload mode.  The problem is PIT stops counting when it
+ * hits zero.  If it would wrap, we could use it just like a decrementer.
+ */
+static inline unsigned int get_dec(void)
+{
+#if defined(CONFIG_40x)
+        return (mfspr(SPRN_PIT));
+#else
+        return (mfspr(SPRN_DEC));
+#endif
+}
+
+/*
+ * Note: Book E and 4xx processors differ from other PowerPC processors
+ * in when the decrementer generates its interrupt: on the 1 to 0
+ * transition for Book E/4xx, but on the 0 to -1 transition for others.
+ */
+static inline void set_dec(int val)
+{
+#if defined(CONFIG_40x)
+        mtspr(SPRN_PIT, val);
+#elif defined(CONFIG_8xx_CPU6)
+        set_dec_cpu6(val - 1);
+#else
+#ifndef CONFIG_BOOKE
+        --val;
+#endif
+#ifdef CONFIG_PPC_ISERIES
+        if (firmware_has_feature(FW_FEATURE_ISERIES) &&
+                        get_lppaca()->shared_proc) {
+                get_lppaca()->virtual_decr = val;
+                if (get_dec() > val)
+                        HvCall_setVirtualDecr();
+                return;
+        }
+#endif
+        mtspr(SPRN_DEC, val);
+#endif /* not 40x or 8xx_CPU6 */
+}
+
+static inline unsigned long tb_ticks_since(unsigned long tstamp)
+{
+        if (__USE_RTC()) {
+                int delta = get_rtcl() - (unsigned int) tstamp;
+                return delta < 0 ? delta + 1000000000 : delta;
+        }
+        return get_tbl() - tstamp;
+}
+
+#define mulhwu(x,y) \
+({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
+
+#ifdef CONFIG_PPC64
+#define mulhdu(x,y) \
+({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
+#else
+extern u64 mulhdu(u64, u64);
+#endif
+
+extern void smp_space_timers(unsigned int);
+
+extern unsigned mulhwu_scale_factor(unsigned, unsigned);
+extern void div128_by_32(u64 dividend_high, u64 dividend_low,
+                         unsigned divisor, struct div_result *dr);
+
+/* Used to store Processor Utilization register (purr) values */
+
+struct cpu_usage {
+        u64 current_tb;  /* Holds the current purr register values */
+};
+
+DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
+
+#if defined(CONFIG_VIRT_CPU_ACCOUNTING)
+extern void calculate_steal_time(void);
+extern void snapshot_timebases(void);
+#define account_process_vtime(tsk)              account_process_tick(tsk, 0)
+#else
+#define calculate_steal_time()                  do { } while (0)
+#define snapshot_timebases()                    do { } while (0)
+#define account_process_vtime(tsk)              do { } while (0)
+#endif
+
+extern void secondary_cpu_time_init(void);
+extern void iSeries_time_init_early(void);
+
+#endif /* __KERNEL__ */
+#endif /* __POWERPC_TIME_H */
diff --git a/arch/powerpc/include/asm/timex.h b/arch/powerpc/include/asm/timex.h
new file mode 100644
index 000000000000..c55e14f7ef44
--- /dev/null
+++ b/arch/powerpc/include/asm/timex.h
@@ -0,0 +1,50 @@
+#ifndef _ASM_POWERPC_TIMEX_H
+#define _ASM_POWERPC_TIMEX_H
+
+#ifdef __KERNEL__
+
+/*
+ * PowerPC architecture timex specifications
+ */
+
+#include <asm/cputable.h>
+#include <asm/reg.h>
+
+#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
+
+typedef unsigned long cycles_t;
+
+static inline cycles_t get_cycles(void)
+{
+#ifdef __powerpc64__
+        return mftb();
+#else
+        cycles_t ret;
+
+        /*
+         * For the "cycle" counter we use the timebase lower half.
+         * Currently only used on SMP.
+         */
+
+        ret = 0;
+
+        __asm__ __volatile__(
+                "97:    mftb %0\n"
+                "99:\n"
+                ".section __ftr_fixup,\"a\"\n"
+                ".align 2\n"
+                "98:\n"
+                "       .long %1\n"
+                "       .long 0\n"
+                "       .long 97b-98b\n"
+                "       .long 99b-98b\n"
+                "       .long 0\n"
+                "       .long 0\n"
+                ".previous"
+                : "=r" (ret) : "i" (CPU_FTR_601));
+        return ret;
+#endif
+}
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_TIMEX_H */
diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h
new file mode 100644
index 000000000000..e20ff7541f36
--- /dev/null
+++ b/arch/powerpc/include/asm/tlb.h
@@ -0,0 +1,81 @@
+/*
+ *      TLB shootdown specifics for powerpc
+ *
+ * Copyright (C) 2002 Anton Blanchard, IBM Corp.
+ * Copyright (C) 2002 Paul Mackerras, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_TLB_H
+#define _ASM_POWERPC_TLB_H
+#ifdef __KERNEL__
+
+#ifndef __powerpc64__
+#include <asm/pgtable.h>
+#endif
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+#ifndef __powerpc64__
+#include <asm/page.h>
+#include <asm/mmu.h>
+#endif
+
+#include <linux/pagemap.h>
+
+struct mmu_gather;
+
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma)   do { } while (0)
+
+#if !defined(CONFIG_PPC_STD_MMU)
+
+#define tlb_flush(tlb)                  flush_tlb_mm((tlb)->mm)
+
+#elif defined(__powerpc64__)
+
+extern void pte_free_finish(void);
+
+static inline void tlb_flush(struct mmu_gather *tlb)
+{
+        struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
+
+        /* If there's a TLB batch pending, then we must flush it because the
+         * pages are going to be freed and we really don't want to have a CPU
+         * access a freed page because it has a stale TLB
+         */
+        if (tlbbatch->index)
+                __flush_tlb_pending(tlbbatch);
+
+        pte_free_finish();
+}
+
+#else
+
+extern void tlb_flush(struct mmu_gather *tlb);
+
+#endif
+
+/* Get the generic bits... */
+#include <asm-generic/tlb.h>
+
+#if !defined(CONFIG_PPC_STD_MMU) || defined(__powerpc64__)
+
+#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
+
+#else
+extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
+                             unsigned long address);
+
+static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
+                                        unsigned long address)
+{
+        if (pte_val(*ptep) & _PAGE_HASHPTE)
+                flush_hash_entry(tlb->mm, ptep, address);
+}
+
+#endif
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_TLB_H */
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
new file mode 100644
index 000000000000..361cd5c7a32b
--- /dev/null
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -0,0 +1,166 @@
+#ifndef _ASM_POWERPC_TLBFLUSH_H
+#define _ASM_POWERPC_TLBFLUSH_H
+
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifdef __KERNEL__
+
+#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
+/*
+ * TLB flushing for software loaded TLB chips
+ *
+ * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
+ * flush_tlb_kernel_range are best implemented as tlbia vs
+ * specific tlbie's
+ */
+
+#include <linux/mm.h>
+
+extern void _tlbie(unsigned long address, unsigned int pid);
+
+#if defined(CONFIG_40x) || defined(CONFIG_8xx)
+#define _tlbia()        asm volatile ("tlbia; sync" : : : "memory")
+#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
+extern void _tlbia(void);
+#endif
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+        _tlbia();
+}
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                  unsigned long vmaddr)
+{
+        _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
+}
+
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+                                         unsigned long vmaddr)
+{
+        _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
+}
+
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                                   unsigned long start, unsigned long end)
+{
+        _tlbia();
+}
+
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+        _tlbia();
+}
+
+#elif defined(CONFIG_PPC32)
+/*
+ * TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx
+ */
+extern void _tlbie(unsigned long address);
+extern void _tlbia(void);
+
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
+extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+                            unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+
+#else
+/*
+ * TLB flushing for 64-bit has-MMU CPUs
+ */
+
+#include <linux/percpu.h>
+#include <asm/page.h>
+
+#define PPC64_TLB_BATCH_NR 192
+
+struct ppc64_tlb_batch {
+        int                     active;
+        unsigned long           index;
+        struct mm_struct        *mm;
+        real_pte_t              pte[PPC64_TLB_BATCH_NR];
+        unsigned long           vaddr[PPC64_TLB_BATCH_NR];
+        unsigned int            psize;
+        int                     ssize;
+};
+DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
+
+extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
+
+extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
+                            pte_t *ptep, unsigned long pte, int huge);
+
+#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
+
+static inline void arch_enter_lazy_mmu_mode(void)
+{
+        struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
+
+        batch->active = 1;
+}
+
+static inline void arch_leave_lazy_mmu_mode(void)
+{
+        struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
+
+        if (batch->index)
+                __flush_tlb_pending(batch);
+        batch->active = 0;
+}
+
+#define arch_flush_lazy_mmu_mode()      do {} while (0)
+
+
+extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
+                            int ssize, int local);
+extern void flush_hash_range(unsigned long number, int local);
+
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+}
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                  unsigned long vmaddr)
+{
+}
+
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+                                         unsigned long vmaddr)
+{
+}
+
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                                   unsigned long start, unsigned long end)
+{
+}
+
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+}
+
+/* Private function for use by PCI IO mapping code */
+extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
+                                     unsigned long end);
+
+
+#endif
+
+#endif /*__KERNEL__ */
+#endif /* _ASM_POWERPC_TLBFLUSH_H */
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
new file mode 100644
index 000000000000..c32da6f97999
--- /dev/null
+++ b/arch/powerpc/include/asm/topology.h
@@ -0,0 +1,117 @@
+#ifndef _ASM_POWERPC_TOPOLOGY_H
+#define _ASM_POWERPC_TOPOLOGY_H
+#ifdef __KERNEL__
+
+
+struct sys_device;
+struct device_node;
+
+#ifdef CONFIG_NUMA
+
+#include <asm/mmzone.h>
+
+static inline int cpu_to_node(int cpu)
+{
+        return numa_cpu_lookup_table[cpu];
+}
+
+#define parent_node(node)       (node)
+
+static inline cpumask_t node_to_cpumask(int node)
+{
+        return numa_cpumask_lookup_table[node];
+}
+
+static inline int node_to_first_cpu(int node)
+{
+        cpumask_t tmp;
+        tmp = node_to_cpumask(node);
+        return first_cpu(tmp);
+}
+
+int of_node_to_nid(struct device_node *device);
+
+struct pci_bus;
+#ifdef CONFIG_PCI
+extern int pcibus_to_node(struct pci_bus *bus);
+#else
+static inline int pcibus_to_node(struct pci_bus *bus)
+{
+        return -1;
+}
+#endif
+
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
+
+/* sched_domains SD_NODE_INIT for PPC64 machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .child                  = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 8,                    \
+        .max_interval           = 32,                   \
+        .busy_factor            = 32,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 1,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 1,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_EXEC       \
+                                | SD_BALANCE_NEWIDLE    \
+                                | SD_WAKE_IDLE          \
+                                | SD_SERIALIZE          \
+                                | SD_WAKE_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+        .nr_balance_failed      = 0,                    \
+}
+
+extern void __init dump_numa_cpu_topology(void);
+
+extern int sysfs_add_device_to_node(struct sys_device *dev, int nid);
+extern void sysfs_remove_device_from_node(struct sys_device *dev, int nid);
+
+#else
+
+static inline int of_node_to_nid(struct device_node *device)
+{
+        return 0;
+}
+
+static inline void dump_numa_cpu_topology(void) {}
+
+static inline int sysfs_add_device_to_node(struct sys_device *dev, int nid)
+{
+        return 0;
+}
+
+static inline void sysfs_remove_device_from_node(struct sys_device *dev,
+                                                int nid)
+{
+}
+
+#endif /* CONFIG_NUMA */
+
+#include <asm-generic/topology.h>
+
+#ifdef CONFIG_SMP
+#include <asm/cputable.h>
+#define smt_capable()           (cpu_has_feature(CPU_FTR_SMT))
+
+#ifdef CONFIG_PPC64
+#include <asm/smp.h>
+
+#define topology_thread_siblings(cpu)   (per_cpu(cpu_sibling_map, cpu))
+#define topology_core_siblings(cpu)     (per_cpu(cpu_core_map, cpu))
+#define topology_core_id(cpu)           (cpu_to_core_id(cpu))
+#endif
+#endif
+
+#endif /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_TOPOLOGY_H */
diff --git a/arch/powerpc/include/asm/tsi108.h b/arch/powerpc/include/asm/tsi108.h
new file mode 100644
index 000000000000..f8b60793b7a9
--- /dev/null
+++ b/arch/powerpc/include/asm/tsi108.h
@@ -0,0 +1,121 @@
+/*
+ * common routine and memory layout for Tundra TSI108(Grendel) host bridge
+ * memory controller.
+ *
+ * Author: Jacob Pan (jacob.pan@freescale.com)
+ *         Alex Bounine (alexandreb@tundra.com)
+ *
+ * Copyright 2004-2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __PPC_KERNEL_TSI108_H
+#define __PPC_KERNEL_TSI108_H
+
+#include <asm/pci-bridge.h>
+
+/* Size of entire register space */
+#define TSI108_REG_SIZE         (0x10000)
+
+/* Sizes of register spaces for individual blocks */
+#define TSI108_HLP_SIZE         0x1000
+#define TSI108_PCI_SIZE         0x1000
+#define TSI108_CLK_SIZE         0x1000
+#define TSI108_PB_SIZE          0x1000
+#define TSI108_SD_SIZE          0x1000
+#define TSI108_DMA_SIZE         0x1000
+#define TSI108_ETH_SIZE         0x1000
+#define TSI108_I2C_SIZE         0x400
+#define TSI108_MPIC_SIZE        0x400
+#define TSI108_UART0_SIZE       0x200
+#define TSI108_GPIO_SIZE        0x200
+#define TSI108_UART1_SIZE       0x200
+
+/* Offsets within Tsi108(A) CSR space for individual blocks */
+#define TSI108_HLP_OFFSET       0x0000
+#define TSI108_PCI_OFFSET       0x1000
+#define TSI108_CLK_OFFSET       0x2000
+#define TSI108_PB_OFFSET        0x3000
+#define TSI108_SD_OFFSET        0x4000
+#define TSI108_DMA_OFFSET       0x5000
+#define TSI108_ETH_OFFSET       0x6000
+#define TSI108_I2C_OFFSET       0x7000
+#define TSI108_MPIC_OFFSET      0x7400
+#define TSI108_UART0_OFFSET     0x7800
+#define TSI108_GPIO_OFFSET      0x7A00
+#define TSI108_UART1_OFFSET     0x7C00
+
+/* Tsi108 registers used by common code components */
+#define TSI108_PCI_CSR          (0x004)
+#define TSI108_PCI_IRP_CFG_CTL  (0x180)
+#define TSI108_PCI_IRP_STAT     (0x184)
+#define TSI108_PCI_IRP_ENABLE   (0x188)
+#define TSI108_PCI_IRP_INTAD    (0x18C)
+
+#define TSI108_PCI_IRP_STAT_P_INT       (0x00400000)
+#define TSI108_PCI_IRP_ENABLE_P_INT     (0x00400000)
+
+#define TSI108_CG_PWRUP_STATUS  (0x234)
+
+#define TSI108_PB_ISR           (0x00C)
+#define TSI108_PB_ERRCS         (0x404)
+#define TSI108_PB_AERR          (0x408)
+
+#define TSI108_PB_ERRCS_ES              (1 << 1)
+#define TSI108_PB_ISR_PBS_RD_ERR        (1 << 8)
+
+#define TSI108_PCI_CFG_SIZE             (0x01000000)
+
+/*
+ * PHY Configuration Options
+ *
+ * Specify "bcm54xx" in the compatible property of your device tree phy
+ * nodes if your board uses the Broadcom PHYs
+ */
+#define TSI108_PHY_MV88E        0       /* Marvel 88Exxxx PHY */
+#define TSI108_PHY_BCM54XX      1       /* Broardcom BCM54xx PHY */
+
+/* Global variables */
+
+extern u32 tsi108_pci_cfg_base;
+/* Exported functions */
+
+extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
+extern unsigned long tsi108_get_mem_size(void);
+extern unsigned long tsi108_get_cpu_clk(void);
+extern unsigned long tsi108_get_sdc_clk(void);
+extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
+                                      int offset, int len, u32 val);
+extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
+                                     int offset, int len, u32 * val);
+extern void tsi108_clear_pci_error(u32 pci_cfg_base);
+
+extern phys_addr_t get_csrbase(void);
+
+typedef struct {
+        u32 regs;               /* hw registers base address */
+        u32 phyregs;            /* phy registers base address */
+        u16 phy;                /* phy address */
+        u16 irq_num;            /* irq number */
+        u8 mac_addr[6];         /* phy mac address */
+        u16 phy_type;   /* type of phy on board */
+} hw_info;
+
+extern u32 get_vir_csrbase(void);
+extern u32 tsi108_csr_vir_base;
+
+static inline u32 tsi108_read_reg(u32 reg_offset)
+{
+        return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
+}
+
+static inline void tsi108_write_reg(u32 reg_offset, u32 val)
+{
+        out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
+}
+
+#endif                          /* __PPC_KERNEL_TSI108_H */
diff --git a/arch/powerpc/include/asm/tsi108_irq.h b/arch/powerpc/include/asm/tsi108_irq.h
new file mode 100644
index 000000000000..6ed93979fbe4
--- /dev/null
+++ b/arch/powerpc/include/asm/tsi108_irq.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2005 Tundra Semiconductor Corp.
+ * Alex Bounine, <alexandreb at tundra.com).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * definitions for interrupt controller initialization and external interrupt
+ * demultiplexing on TSI108EMU/SVB boards.
+ */
+
+#ifndef _ASM_POWERPC_TSI108_IRQ_H
+#define _ASM_POWERPC_TSI108_IRQ_H
+
+/*
+ * Tsi108 interrupts
+ */
+#ifndef TSI108_IRQ_REG_BASE
+#define TSI108_IRQ_REG_BASE             0
+#endif
+
+#define TSI108_IRQ(x)           (TSI108_IRQ_REG_BASE + (x))
+
+#define TSI108_MAX_VECTORS      (36 + 4)        /* 36 sources + PCI INT demux */
+#define MAX_TASK_PRIO   0xF
+
+#define TSI108_IRQ_SPURIOUS     (TSI108_MAX_VECTORS)
+
+#define DEFAULT_PRIO_LVL        10      /* initial priority level */
+
+/* Interrupt vectors assignment to external and internal
+ * sources of requests. */
+
+/* EXTERNAL INTERRUPT SOURCES */
+
+#define IRQ_TSI108_EXT_INT0     TSI108_IRQ(0)   /* External Source at INT[0] */
+#define IRQ_TSI108_EXT_INT1     TSI108_IRQ(1)   /* External Source at INT[1] */
+#define IRQ_TSI108_EXT_INT2     TSI108_IRQ(2)   /* External Source at INT[2] */
+#define IRQ_TSI108_EXT_INT3     TSI108_IRQ(3)   /* External Source at INT[3] */
+
+/* INTERNAL INTERRUPT SOURCES */
+
+#define IRQ_TSI108_RESERVED0    TSI108_IRQ(4)   /* Reserved IRQ */
+#define IRQ_TSI108_RESERVED1    TSI108_IRQ(5)   /* Reserved IRQ */
+#define IRQ_TSI108_RESERVED2    TSI108_IRQ(6)   /* Reserved IRQ */
+#define IRQ_TSI108_RESERVED3    TSI108_IRQ(7)   /* Reserved IRQ */
+#define IRQ_TSI108_DMA0         TSI108_IRQ(8)   /* DMA0 */
+#define IRQ_TSI108_DMA1         TSI108_IRQ(9)   /* DMA1 */
+#define IRQ_TSI108_DMA2         TSI108_IRQ(10)  /* DMA2 */
+#define IRQ_TSI108_DMA3         TSI108_IRQ(11)  /* DMA3 */
+#define IRQ_TSI108_UART0        TSI108_IRQ(12)  /* UART0 */
+#define IRQ_TSI108_UART1        TSI108_IRQ(13)  /* UART1 */
+#define IRQ_TSI108_I2C          TSI108_IRQ(14)  /* I2C */
+#define IRQ_TSI108_GPIO         TSI108_IRQ(15)  /* GPIO */
+#define IRQ_TSI108_GIGE0        TSI108_IRQ(16)  /* GIGE0 */
+#define IRQ_TSI108_GIGE1        TSI108_IRQ(17)  /* GIGE1 */
+#define IRQ_TSI108_RESERVED4    TSI108_IRQ(18)  /* Reserved IRQ */
+#define IRQ_TSI108_HLP          TSI108_IRQ(19)  /* HLP */
+#define IRQ_TSI108_SDRAM        TSI108_IRQ(20)  /* SDC */
+#define IRQ_TSI108_PROC_IF      TSI108_IRQ(21)  /* Processor IF */
+#define IRQ_TSI108_RESERVED5    TSI108_IRQ(22)  /* Reserved IRQ */
+#define IRQ_TSI108_PCI          TSI108_IRQ(23)  /* PCI/X block */
+
+#define IRQ_TSI108_MBOX0        TSI108_IRQ(24)  /* Mailbox 0 register */
+#define IRQ_TSI108_MBOX1        TSI108_IRQ(25)  /* Mailbox 1 register */
+#define IRQ_TSI108_MBOX2        TSI108_IRQ(26)  /* Mailbox 2 register */
+#define IRQ_TSI108_MBOX3        TSI108_IRQ(27)  /* Mailbox 3 register */
+
+#define IRQ_TSI108_DBELL0       TSI108_IRQ(28)  /* Doorbell 0 */
+#define IRQ_TSI108_DBELL1       TSI108_IRQ(29)  /* Doorbell 1 */
+#define IRQ_TSI108_DBELL2       TSI108_IRQ(30)  /* Doorbell 2 */
+#define IRQ_TSI108_DBELL3       TSI108_IRQ(31)  /* Doorbell 3 */
+
+#define IRQ_TSI108_TIMER0       TSI108_IRQ(32)  /* Global Timer 0 */
+#define IRQ_TSI108_TIMER1       TSI108_IRQ(33)  /* Global Timer 1 */
+#define IRQ_TSI108_TIMER2       TSI108_IRQ(34)  /* Global Timer 2 */
+#define IRQ_TSI108_TIMER3       TSI108_IRQ(35)  /* Global Timer 3 */
+
+/*
+ * PCI bus INTA# - INTD# lines demultiplexor
+ */
+#define IRQ_PCI_INTAD_BASE      TSI108_IRQ(36)
+#define IRQ_PCI_INTA            (IRQ_PCI_INTAD_BASE + 0)
+#define IRQ_PCI_INTB            (IRQ_PCI_INTAD_BASE + 1)
+#define IRQ_PCI_INTC            (IRQ_PCI_INTAD_BASE + 2)
+#define IRQ_PCI_INTD            (IRQ_PCI_INTAD_BASE + 3)
+#define NUM_PCI_IRQS            (4)
+
+/* number of entries in vector dispatch table */
+#define IRQ_TSI108_TAB_SIZE     (TSI108_MAX_VECTORS + 1)
+
+/* Mapping of MPIC outputs to processors' interrupt pins */
+
+#define IDIR_INT_OUT0           0x1
+#define IDIR_INT_OUT1           0x2
+#define IDIR_INT_OUT2           0x4
+#define IDIR_INT_OUT3           0x8
+
+/*---------------------------------------------------------------
+ * IRQ line configuration parameters */
+
+/* Interrupt delivery modes */
+typedef enum {
+        TSI108_IRQ_DIRECTED,
+        TSI108_IRQ_DISTRIBUTED,
+} TSI108_IRQ_MODE;
+#endif                          /*  _ASM_POWERPC_TSI108_IRQ_H */
diff --git a/arch/powerpc/include/asm/tsi108_pci.h b/arch/powerpc/include/asm/tsi108_pci.h
new file mode 100644
index 000000000000..5653d7cc3e24
--- /dev/null
+++ b/arch/powerpc/include/asm/tsi108_pci.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2007 IBM Corp
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_TSI108_PCI_H
+#define _ASM_POWERPC_TSI108_PCI_H
+
+#include <asm/tsi108.h>
+
+/* Register definitions */
+#define TSI108_PCI_P2O_BAR0 (TSI108_PCI_OFFSET + 0x10)
+#define TSI108_PCI_P2O_BAR0_UPPER (TSI108_PCI_OFFSET + 0x14)
+#define TSI108_PCI_P2O_BAR2 (TSI108_PCI_OFFSET + 0x18)
+#define TSI108_PCI_P2O_BAR2_UPPER (TSI108_PCI_OFFSET + 0x1c)
+#define TSI108_PCI_P2O_PAGE_SIZES (TSI108_PCI_OFFSET + 0x4c)
+#define TSI108_PCI_PFAB_BAR0 (TSI108_PCI_OFFSET + 0x204)
+#define TSI108_PCI_PFAB_BAR0_UPPER (TSI108_PCI_OFFSET + 0x208)
+#define TSI108_PCI_PFAB_IO (TSI108_PCI_OFFSET + 0x20c)
+#define TSI108_PCI_PFAB_IO_UPPER (TSI108_PCI_OFFSET + 0x210)
+#define TSI108_PCI_PFAB_MEM32 (TSI108_PCI_OFFSET + 0x214)
+#define TSI108_PCI_PFAB_PFM3 (TSI108_PCI_OFFSET + 0x220)
+#define TSI108_PCI_PFAB_PFM4 (TSI108_PCI_OFFSET + 0x230)
+
+extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
+extern void tsi108_pci_int_init(struct device_node *node);
+extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
+extern void tsi108_clear_pci_cfg_error(void);
+
+#endif                          /*  _ASM_POWERPC_TSI108_PCI_H */
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
new file mode 100644
index 000000000000..d3374bc865ba
--- /dev/null
+++ b/arch/powerpc/include/asm/types.h
@@ -0,0 +1,75 @@
+#ifndef _ASM_POWERPC_TYPES_H
+#define _ASM_POWERPC_TYPES_H
+
+#ifdef __powerpc64__
+# include <asm-generic/int-l64.h>
+#else
+# include <asm-generic/int-ll64.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifdef __powerpc64__
+typedef unsigned int umode_t;
+#else
+typedef unsigned short umode_t;
+#endif
+
+typedef struct {
+        __u32 u[4];
+} __attribute__((aligned(16))) __vector128;
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __powerpc64__
+#define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef __vector128 vector128;
+
+/* Physical address used by some IO functions */
+#if defined(CONFIG_PPC64) || defined(CONFIG_PHYS_64BIT)
+typedef u64 phys_addr_t;
+#else
+typedef u32 phys_addr_t;
+#endif
+
+#ifdef __powerpc64__
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+typedef u64 dma64_addr_t;
+
+typedef struct {
+        unsigned long entry;
+        unsigned long toc;
+        unsigned long env;
+} func_descr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_TYPES_H */
diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h
new file mode 100644
index 000000000000..bd0fb8495154
--- /dev/null
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -0,0 +1,496 @@
+#ifndef _ARCH_POWERPC_UACCESS_H
+#define _ARCH_POWERPC_UACCESS_H
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <asm/asm-compat.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ *
+ * The fs/ds values are now the highest legal address in the "segment".
+ * This simplifies the checking in the routines below.
+ */
+
+#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
+
+#define KERNEL_DS       MAKE_MM_SEG(~0UL)
+#ifdef __powerpc64__
+/* We use TASK_SIZE_USER64 as TASK_SIZE is not constant */
+#define USER_DS         MAKE_MM_SEG(TASK_SIZE_USER64 - 1)
+#else
+#define USER_DS         MAKE_MM_SEG(TASK_SIZE - 1)
+#endif
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current->thread.fs)
+#define set_fs(val)     (current->thread.fs = (val))
+
+#define segment_eq(a, b)        ((a).seg == (b).seg)
+
+#ifdef __powerpc64__
+/*
+ * This check is sufficient because there is a large enough
+ * gap between user addresses and the kernel addresses
+ */
+#define __access_ok(addr, size, segment)        \
+        (((addr) <= (segment).seg) && ((size) <= (segment).seg))
+
+#else
+
+#define __access_ok(addr, size, segment)        \
+        (((addr) <= (segment).seg) &&           \
+         (((size) == 0) || (((size) - 1) <= ((segment).seg - (addr)))))
+
+#endif
+
+#define access_ok(type, addr, size)             \
+        (__chk_user_ptr(addr),                  \
+         __access_ok((__force unsigned long)(addr), (size), get_fs()))
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+        unsigned long insn;
+        unsigned long fixup;
+};
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on the
+ * PowerPC, we can just do these as direct assignments.  (Of course, the
+ * exception handling means that it's no longer "just"...)
+ *
+ * The "user64" versions of the user access functions are versions that
+ * allow access of 64-bit data. The "get_user" functions do not
+ * properly handle 64-bit data because the value gets down cast to a long.
+ * The "put_user" functions already handle 64-bit data properly but we add
+ * "user64" versions for completeness
+ */
+#define get_user(x, ptr) \
+        __get_user_check((x), (ptr), sizeof(*(ptr)))
+#define put_user(x, ptr) \
+        __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x, ptr) \
+        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+#define __put_user(x, ptr) \
+        __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
+
+#ifndef __powerpc64__
+#define __get_user64(x, ptr) \
+        __get_user64_nocheck((x), (ptr), sizeof(*(ptr)))
+#define __put_user64(x, ptr) __put_user(x, ptr)
+#endif
+
+#define __get_user_inatomic(x, ptr) \
+        __get_user_nosleep((x), (ptr), sizeof(*(ptr)))
+#define __put_user_inatomic(x, ptr) \
+        __put_user_nosleep((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
+
+#define __get_user_unaligned __get_user
+#define __put_user_unaligned __put_user
+
+extern long __put_user_bad(void);
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about, so there
+ * are no aliasing issues.
+ */
+#define __put_user_asm(x, addr, err, op)                        \
+        __asm__ __volatile__(                                   \
+                "1:     " op " %1,0(%2) # put_user\n"           \
+                "2:\n"                                          \
+                ".section .fixup,\"ax\"\n"                      \
+                "3:     li %0,%3\n"                             \
+                "       b 2b\n"                                 \
+                ".previous\n"                                   \
+                ".section __ex_table,\"a\"\n"                   \
+                        PPC_LONG_ALIGN "\n"                     \
+                        PPC_LONG "1b,3b\n"                      \
+                ".previous"                                     \
+                : "=r" (err)                                    \
+                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
+
+#ifdef __powerpc64__
+#define __put_user_asm2(x, ptr, retval)                         \
+          __put_user_asm(x, ptr, retval, "std")
+#else /* __powerpc64__ */
+#define __put_user_asm2(x, addr, err)                           \
+        __asm__ __volatile__(                                   \
+                "1:     stw %1,0(%2)\n"                         \
+                "2:     stw %1+1,4(%2)\n"                       \
+                "3:\n"                                          \
+                ".section .fixup,\"ax\"\n"                      \
+                "4:     li %0,%3\n"                             \
+                "       b 3b\n"                                 \
+                ".previous\n"                                   \
+                ".section __ex_table,\"a\"\n"                   \
+                        PPC_LONG_ALIGN "\n"                     \
+                        PPC_LONG "1b,4b\n"                      \
+                        PPC_LONG "2b,4b\n"                      \
+                ".previous"                                     \
+                : "=r" (err)                                    \
+                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
+#endif /* __powerpc64__ */
+
+#define __put_user_size(x, ptr, size, retval)                   \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+          case 1: __put_user_asm(x, ptr, retval, "stb"); break; \
+          case 2: __put_user_asm(x, ptr, retval, "sth"); break; \
+          case 4: __put_user_asm(x, ptr, retval, "stw"); break; \
+          case 8: __put_user_asm2(x, ptr, retval); break;       \
+          default: __put_user_bad();                            \
+        }                                                       \
+} while (0)
+
+#define __put_user_nocheck(x, ptr, size)                        \
+({                                                              \
+        long __pu_err;                                          \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
+        if (!is_kernel_addr((unsigned long)__pu_addr))          \
+                might_sleep();                                  \
+        __chk_user_ptr(ptr);                                    \
+        __put_user_size((x), __pu_addr, (size), __pu_err);      \
+        __pu_err;                                               \
+})
+
+#define __put_user_check(x, ptr, size)                                  \
+({                                                                      \
+        long __pu_err = -EFAULT;                                        \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
+        might_sleep();                                                  \
+        if (access_ok(VERIFY_WRITE, __pu_addr, size))                   \
+                __put_user_size((x), __pu_addr, (size), __pu_err);      \
+        __pu_err;                                                       \
+})
+
+#define __put_user_nosleep(x, ptr, size)                        \
+({                                                              \
+        long __pu_err;                                          \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
+        __chk_user_ptr(ptr);                                    \
+        __put_user_size((x), __pu_addr, (size), __pu_err);      \
+        __pu_err;                                               \
+})
+
+
+extern long __get_user_bad(void);
+
+#define __get_user_asm(x, addr, err, op)                \
+        __asm__ __volatile__(                           \
+                "1:     "op" %1,0(%2)   # get_user\n"   \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li %0,%3\n"                     \
+                "       li %1,0\n"                      \
+                "       b 2b\n"                         \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
+                ".previous"                             \
+                : "=r" (err), "=r" (x)                  \
+                : "b" (addr), "i" (-EFAULT), "0" (err))
+
+#ifdef __powerpc64__
+#define __get_user_asm2(x, addr, err)                   \
+        __get_user_asm(x, addr, err, "ld")
+#else /* __powerpc64__ */
+#define __get_user_asm2(x, addr, err)                   \
+        __asm__ __volatile__(                           \
+                "1:     lwz %1,0(%2)\n"                 \
+                "2:     lwz %1+1,4(%2)\n"               \
+                "3:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "4:     li %0,%3\n"                     \
+                "       li %1,0\n"                      \
+                "       li %1+1,0\n"                    \
+                "       b 3b\n"                         \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,4b\n"              \
+                        PPC_LONG "2b,4b\n"              \
+                ".previous"                             \
+                : "=r" (err), "=&r" (x)                 \
+                : "b" (addr), "i" (-EFAULT), "0" (err))
+#endif /* __powerpc64__ */
+
+#define __get_user_size(x, ptr, size, retval)                   \
+do {                                                            \
+        retval = 0;                                             \
+        __chk_user_ptr(ptr);                                    \
+        if (size > sizeof(x))                                   \
+                (x) = __get_user_bad();                         \
+        switch (size) {                                         \
+        case 1: __get_user_asm(x, ptr, retval, "lbz"); break;   \
+        case 2: __get_user_asm(x, ptr, retval, "lhz"); break;   \
+        case 4: __get_user_asm(x, ptr, retval, "lwz"); break;   \
+        case 8: __get_user_asm2(x, ptr, retval);  break;        \
+        default: (x) = __get_user_bad();                        \
+        }                                                       \
+} while (0)
+
+#define __get_user_nocheck(x, ptr, size)                        \
+({                                                              \
+        long __gu_err;                                          \
+        unsigned long __gu_val;                                 \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);     \
+        __chk_user_ptr(ptr);                                    \
+        if (!is_kernel_addr((unsigned long)__gu_addr))          \
+                might_sleep();                                  \
+        __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+
+#ifndef __powerpc64__
+#define __get_user64_nocheck(x, ptr, size)                      \
+({                                                              \
+        long __gu_err;                                          \
+        long long __gu_val;                                     \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);     \
+        __chk_user_ptr(ptr);                                    \
+        if (!is_kernel_addr((unsigned long)__gu_addr))          \
+                might_sleep();                                  \
+        __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+#endif /* __powerpc64__ */
+
+#define __get_user_check(x, ptr, size)                                  \
+({                                                                      \
+        long __gu_err = -EFAULT;                                        \
+        unsigned long  __gu_val = 0;                                    \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
+        might_sleep();                                                  \
+        if (access_ok(VERIFY_READ, __gu_addr, (size)))                  \
+                __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                             \
+        __gu_err;                                                       \
+})
+
+#define __get_user_nosleep(x, ptr, size)                        \
+({                                                              \
+        long __gu_err;                                          \
+        unsigned long __gu_val;                                 \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);     \
+        __chk_user_ptr(ptr);                                    \
+        __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+
+
+/* more complex routines */
+
+extern unsigned long __copy_tofrom_user(void __user *to,
+                const void __user *from, unsigned long size);
+
+#ifndef __powerpc64__
+
+static inline unsigned long copy_from_user(void *to,
+                const void __user *from, unsigned long n)
+{
+        unsigned long over;
+
+        if (access_ok(VERIFY_READ, from, n))
+                return __copy_tofrom_user((__force void __user *)to, from, n);
+        if ((unsigned long)from < TASK_SIZE) {
+                over = (unsigned long)from + n - TASK_SIZE;
+                return __copy_tofrom_user((__force void __user *)to, from,
+                                n - over) + over;
+        }
+        return n;
+}
+
+static inline unsigned long copy_to_user(void __user *to,
+                const void *from, unsigned long n)
+{
+        unsigned long over;
+
+        if (access_ok(VERIFY_WRITE, to, n))
+                return __copy_tofrom_user(to, (__force void __user *)from, n);
+        if ((unsigned long)to < TASK_SIZE) {
+                over = (unsigned long)to + n - TASK_SIZE;
+                return __copy_tofrom_user(to, (__force void __user *)from,
+                                n - over) + over;
+        }
+        return n;
+}
+
+#else /* __powerpc64__ */
+
+#define __copy_in_user(to, from, size) \
+        __copy_tofrom_user((to), (from), (size))
+
+extern unsigned long copy_from_user(void *to, const void __user *from,
+                                    unsigned long n);
+extern unsigned long copy_to_user(void __user *to, const void *from,
+                                  unsigned long n);
+extern unsigned long copy_in_user(void __user *to, const void __user *from,
+                                  unsigned long n);
+
+#endif /* __powerpc64__ */
+
+static inline unsigned long __copy_from_user_inatomic(void *to,
+                const void __user *from, unsigned long n)
+{
+        if (__builtin_constant_p(n) && (n <= 8)) {
+                unsigned long ret = 1;
+
+                switch (n) {
+                case 1:
+                        __get_user_size(*(u8 *)to, from, 1, ret);
+                        break;
+                case 2:
+                        __get_user_size(*(u16 *)to, from, 2, ret);
+                        break;
+                case 4:
+                        __get_user_size(*(u32 *)to, from, 4, ret);
+                        break;
+                case 8:
+                        __get_user_size(*(u64 *)to, from, 8, ret);
+                        break;
+                }
+                if (ret == 0)
+                        return 0;
+        }
+        return __copy_tofrom_user((__force void __user *)to, from, n);
+}
+
+static inline unsigned long __copy_to_user_inatomic(void __user *to,
+                const void *from, unsigned long n)
+{
+        if (__builtin_constant_p(n) && (n <= 8)) {
+                unsigned long ret = 1;
+
+                switch (n) {
+                case 1:
+                        __put_user_size(*(u8 *)from, (u8 __user *)to, 1, ret);
+                        break;
+                case 2:
+                        __put_user_size(*(u16 *)from, (u16 __user *)to, 2, ret);
+                        break;
+                case 4:
+                        __put_user_size(*(u32 *)from, (u32 __user *)to, 4, ret);
+                        break;
+                case 8:
+                        __put_user_size(*(u64 *)from, (u64 __user *)to, 8, ret);
+                        break;
+                }
+                if (ret == 0)
+                        return 0;
+        }
+        return __copy_tofrom_user(to, (__force const void __user *)from, n);
+}
+
+static inline unsigned long __copy_from_user(void *to,
+                const void __user *from, unsigned long size)
+{
+        might_sleep();
+        return __copy_from_user_inatomic(to, from, size);
+}
+
+static inline unsigned long __copy_to_user(void __user *to,
+                const void *from, unsigned long size)
+{
+        might_sleep();
+        return __copy_to_user_inatomic(to, from, size);
+}
+
+extern unsigned long __clear_user(void __user *addr, unsigned long size);
+
+static inline unsigned long clear_user(void __user *addr, unsigned long size)
+{
+        might_sleep();
+        if (likely(access_ok(VERIFY_WRITE, addr, size)))
+                return __clear_user(addr, size);
+        if ((unsigned long)addr < TASK_SIZE) {
+                unsigned long over = (unsigned long)addr + size - TASK_SIZE;
+                return __clear_user(addr, size - over) + over;
+        }
+        return size;
+}
+
+extern int __strncpy_from_user(char *dst, const char __user *src, long count);
+
+static inline long strncpy_from_user(char *dst, const char __user *src,
+                long count)
+{
+        might_sleep();
+        if (likely(access_ok(VERIFY_READ, src, 1)))
+                return __strncpy_from_user(dst, src, count);
+        return -EFAULT;
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 for error
+ */
+extern int __strnlen_user(const char __user *str, long len, unsigned long top);
+
+/*
+ * Returns the length of the string at str (including the null byte),
+ * or 0 if we hit a page we can't access,
+ * or something > len if we didn't find a null byte.
+ *
+ * The `top' parameter to __strnlen_user is to make sure that
+ * we can never overflow from the user area into kernel space.
+ */
+static inline int strnlen_user(const char __user *str, long len)
+{
+        unsigned long top = current->thread.fs.seg;
+
+        if ((unsigned long)str > top)
+                return 0;
+        return __strnlen_user(str, len, top);
+}
+
+#define strlen_user(str)        strnlen_user((str), 0x7ffffffe)
+
+#endif  /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+
+#endif  /* _ARCH_POWERPC_UACCESS_H */
diff --git a/arch/powerpc/include/asm/ucc.h b/arch/powerpc/include/asm/ucc.h
new file mode 100644
index 000000000000..46b09ba6bead
--- /dev/null
+++ b/arch/powerpc/include/asm/ucc.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:     Shlomi Gridish <gridish@freescale.com>
+ *              Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC unit routines.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_H__
+#define __UCC_H__
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#define STATISTICS
+
+#define UCC_MAX_NUM     8
+
+/* Slow or fast type for UCCs.
+*/
+enum ucc_speed_type {
+        UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
+        UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
+};
+
+/* ucc_set_type
+ * Sets UCC to slow or fast mode.
+ *
+ * ucc_num - (In) number of UCC (0-7).
+ * speed   - (In) slow or fast mode for UCC.
+ */
+int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
+
+int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
+
+int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
+        enum comm_dir mode);
+
+int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
+
+/* QE MUX clock routing for UCC
+*/
+static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
+{
+        return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
+}
+
+static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
+{
+        return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
+}
+
+static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
+{
+        return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
+}
+
+#endif                          /* __UCC_H__ */
diff --git a/arch/powerpc/include/asm/ucc_fast.h b/arch/powerpc/include/asm/ucc_fast.h
new file mode 100644
index 000000000000..839aab8bf37d
--- /dev/null
+++ b/arch/powerpc/include/asm/ucc_fast.h
@@ -0,0 +1,244 @@
+/*
+ * Internal header file for UCC FAST unit routines.
+ *
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:     Shlomi Gridish <gridish@freescale.com>
+ *              Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_FAST_H__
+#define __UCC_FAST_H__
+
+#include <linux/kernel.h>
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include "ucc.h"
+
+/* Receive BD's status */
+#define R_E     0x80000000      /* buffer empty */
+#define R_W     0x20000000      /* wrap bit */
+#define R_I     0x10000000      /* interrupt on reception */
+#define R_L     0x08000000      /* last */
+#define R_F     0x04000000      /* first */
+
+/* transmit BD's status */
+#define T_R     0x80000000      /* ready bit */
+#define T_W     0x20000000      /* wrap bit */
+#define T_I     0x10000000      /* interrupt on completion */
+#define T_L     0x08000000      /* last */
+
+/* Rx Data buffer must be 4 bytes aligned in most cases */
+#define UCC_FAST_RX_ALIGN                       4
+#define UCC_FAST_MRBLR_ALIGNMENT                4
+#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT       8
+
+/* Sizes */
+#define UCC_FAST_URFS_MIN_VAL                           0x88
+#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
+
+/* ucc_fast_channel_protocol_mode - UCC FAST mode */
+enum ucc_fast_channel_protocol_mode {
+        UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
+        UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
+        UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
+        UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
+        UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
+        UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
+        UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
+        UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
+        UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
+        UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
+        UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
+        UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
+        UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
+        UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
+        UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
+        UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
+};
+
+/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
+enum ucc_fast_transparent_txrx {
+        UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
+        UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
+};
+
+/* UCC fast diagnostic mode */
+enum ucc_fast_diag_mode {
+        UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
+        UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
+        UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
+        UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
+};
+
+/* UCC fast Sync length (transparent mode only) */
+enum ucc_fast_sync_len {
+        UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
+        UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
+        UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
+        UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
+};
+
+/* UCC fast RTS mode */
+enum ucc_fast_ready_to_send {
+        UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
+        UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
+};
+
+/* UCC fast receiver decoding mode */
+enum ucc_fast_rx_decoding_method {
+        UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
+        UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
+        UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
+        UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
+};
+
+/* UCC fast transmitter encoding mode */
+enum ucc_fast_tx_encoding_method {
+        UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
+        UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
+        UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
+        UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
+};
+
+/* UCC fast CRC length */
+enum ucc_fast_transparent_tcrc {
+        UCC_FAST_16_BIT_CRC = 0x00000000,
+        UCC_FAST_CRC_RESERVED0 = 0x00000040,
+        UCC_FAST_32_BIT_CRC = 0x00000080,
+        UCC_FAST_CRC_RESERVED1 = 0x000000C0
+};
+
+/* Fast UCC initialization structure */
+struct ucc_fast_info {
+        int ucc_num;
+        enum qe_clock rx_clock;
+        enum qe_clock tx_clock;
+        u32 regs;
+        int irq;
+        u32 uccm_mask;
+        int bd_mem_part;
+        int brkpt_support;
+        int grant_support;
+        int tsa;
+        int cdp;
+        int cds;
+        int ctsp;
+        int ctss;
+        int tci;
+        int txsy;
+        int rtsm;
+        int revd;
+        int rsyn;
+        u16 max_rx_buf_length;
+        u16 urfs;
+        u16 urfet;
+        u16 urfset;
+        u16 utfs;
+        u16 utfet;
+        u16 utftt;
+        u16 ufpt;
+        enum ucc_fast_channel_protocol_mode mode;
+        enum ucc_fast_transparent_txrx ttx_trx;
+        enum ucc_fast_tx_encoding_method tenc;
+        enum ucc_fast_rx_decoding_method renc;
+        enum ucc_fast_transparent_tcrc tcrc;
+        enum ucc_fast_sync_len synl;
+};
+
+struct ucc_fast_private {
+        struct ucc_fast_info *uf_info;
+        struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
+        u32 __iomem *p_ucce;    /* a pointer to the event register in memory. */
+        u32 __iomem *p_uccm;    /* a pointer to the mask register in memory. */
+#ifdef CONFIG_UGETH_TX_ON_DEMAND
+        u16 __iomem *p_utodr;   /* pointer to the transmit on demand register */
+#endif
+        int enabled_tx;         /* Whether channel is enabled for Tx (ENT) */
+        int enabled_rx;         /* Whether channel is enabled for Rx (ENR) */
+        int stopped_tx;         /* Whether channel has been stopped for Tx
+                                   (STOP_TX, etc.) */
+        int stopped_rx;         /* Whether channel has been stopped for Rx */
+        u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
+                                                    virtual fifo */
+        u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
+                                                    virtual fifo */
+#ifdef STATISTICS
+        u32 tx_frames;          /* Transmitted frames counter. */
+        u32 rx_frames;          /* Received frames counter (only frames
+                                   passed to application). */
+        u32 tx_discarded;       /* Discarded tx frames counter (frames that
+                                   were discarded by the driver due to errors).
+                                   */
+        u32 rx_discarded;       /* Discarded rx frames counter (frames that
+                                   were discarded by the driver due to errors).
+                                   */
+#endif                          /* STATISTICS */
+        u16 mrblr;              /* maximum receive buffer length */
+};
+
+/* ucc_fast_init
+ * Initializes Fast UCC according to user provided parameters.
+ *
+ * uf_info  - (In) pointer to the fast UCC info structure.
+ * uccf_ret - (Out) pointer to the fast UCC structure.
+ */
+int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
+
+/* ucc_fast_free
+ * Frees all resources for fast UCC.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_free(struct ucc_fast_private * uccf);
+
+/* ucc_fast_enable
+ * Enables a fast UCC port.
+ * This routine enables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
+
+/* ucc_fast_disable
+ * Disables a fast UCC port.
+ * This routine disables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
+
+/* ucc_fast_irq
+ * Handles interrupts on fast UCC.
+ * Called from the general interrupt routine to handle interrupts on fast UCC.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_irq(struct ucc_fast_private * uccf);
+
+/* ucc_fast_transmit_on_demand
+ * Immediately forces a poll of the transmitter for data to be sent.
+ * Typically, the hardware performs a periodic poll for data that the
+ * transmit routine has set up to be transmitted. In cases where
+ * this polling cycle is not soon enough, this optional routine can
+ * be invoked to force a poll right away, instead. Proper use for
+ * each transmission for which this functionality is desired is to
+ * call the transmit routine and then this routine right after.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
+
+u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
+
+void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
+
+#endif                          /* __UCC_FAST_H__ */
diff --git a/arch/powerpc/include/asm/ucc_slow.h b/arch/powerpc/include/asm/ucc_slow.h
new file mode 100644
index 000000000000..0980e6ad335b
--- /dev/null
+++ b/arch/powerpc/include/asm/ucc_slow.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:     Shlomi Gridish <gridish@freescale.com>
+ *              Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC SLOW unit routines.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_SLOW_H__
+#define __UCC_SLOW_H__
+
+#include <linux/kernel.h>
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include "ucc.h"
+
+/* transmit BD's status */
+#define T_R     0x80000000      /* ready bit */
+#define T_PAD   0x40000000      /* add pads to short frames */
+#define T_W     0x20000000      /* wrap bit */
+#define T_I     0x10000000      /* interrupt on completion */
+#define T_L     0x08000000      /* last */
+
+#define T_A     0x04000000      /* Address - the data transmitted as address
+                                   chars */
+#define T_TC    0x04000000      /* transmit CRC */
+#define T_CM    0x02000000      /* continuous mode */
+#define T_DEF   0x02000000      /* collision on previous attempt to transmit */
+#define T_P     0x01000000      /* Preamble - send Preamble sequence before
+                                   data */
+#define T_HB    0x01000000      /* heartbeat */
+#define T_NS    0x00800000      /* No Stop */
+#define T_LC    0x00800000      /* late collision */
+#define T_RL    0x00400000      /* retransmission limit */
+#define T_UN    0x00020000      /* underrun */
+#define T_CT    0x00010000      /* CTS lost */
+#define T_CSL   0x00010000      /* carrier sense lost */
+#define T_RC    0x003c0000      /* retry count */
+
+/* Receive BD's status */
+#define R_E     0x80000000      /* buffer empty */
+#define R_W     0x20000000      /* wrap bit */
+#define R_I     0x10000000      /* interrupt on reception */
+#define R_L     0x08000000      /* last */
+#define R_C     0x08000000      /* the last byte in this buffer is a cntl
+                                   char */
+#define R_F     0x04000000      /* first */
+#define R_A     0x04000000      /* the first byte in this buffer is address
+                                   byte */
+#define R_CM    0x02000000      /* continuous mode */
+#define R_ID    0x01000000      /* buffer close on reception of idles */
+#define R_M     0x01000000      /* Frame received because of promiscuous
+                                   mode */
+#define R_AM    0x00800000      /* Address match */
+#define R_DE    0x00800000      /* Address match */
+#define R_LG    0x00200000      /* Break received */
+#define R_BR    0x00200000      /* Frame length violation */
+#define R_NO    0x00100000      /* Rx Non Octet Aligned Packet */
+#define R_FR    0x00100000      /* Framing Error (no stop bit) character
+                                   received */
+#define R_PR    0x00080000      /* Parity Error character received */
+#define R_AB    0x00080000      /* Frame Aborted */
+#define R_SH    0x00080000      /* frame is too short */
+#define R_CR    0x00040000      /* CRC Error */
+#define R_OV    0x00020000      /* Overrun */
+#define R_CD    0x00010000      /* CD lost */
+#define R_CL    0x00010000      /* this frame is closed because of a
+                                   collision */
+
+/* Rx Data buffer must be 4 bytes aligned in most cases.*/
+#define UCC_SLOW_RX_ALIGN               4
+#define UCC_SLOW_MRBLR_ALIGNMENT        4
+#define UCC_SLOW_PRAM_SIZE              0x100
+#define ALIGNMENT_OF_UCC_SLOW_PRAM      64
+
+/* UCC Slow Channel Protocol Mode */
+enum ucc_slow_channel_protocol_mode {
+        UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
+        UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
+        UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
+};
+
+/* UCC Slow Transparent Transmit CRC (TCRC) */
+enum ucc_slow_transparent_tcrc {
+        /* 16-bit CCITT CRC (HDLC).  (X16 + X12 + X5 + 1) */
+        UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
+        /* CRC16 (BISYNC).  (X16 + X15 + X2 + 1) */
+        UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
+        /* 32-bit CCITT CRC (Ethernet and HDLC) */
+        UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
+};
+
+/* UCC Slow oversampling rate for transmitter (TDCR) */
+enum ucc_slow_tx_oversampling_rate {
+        /* 1x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
+        /* 8x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
+        /* 16x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
+        /* 32x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
+};
+
+/* UCC Slow Oversampling rate for receiver (RDCR)
+*/
+enum ucc_slow_rx_oversampling_rate {
+        /* 1x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
+        /* 8x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
+        /* 16x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
+        /* 32x clock mode */
+        UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
+};
+
+/* UCC Slow Transmitter encoding method (TENC)
+*/
+enum ucc_slow_tx_encoding_method {
+        UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
+        UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
+};
+
+/* UCC Slow Receiver decoding method (RENC)
+*/
+enum ucc_slow_rx_decoding_method {
+        UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
+        UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
+};
+
+/* UCC Slow Diagnostic mode (DIAG)
+*/
+enum ucc_slow_diag_mode {
+        UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
+        UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
+        UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
+        UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
+};
+
+struct ucc_slow_info {
+        int ucc_num;
+        int protocol;                   /* QE_CR_PROTOCOL_xxx */
+        enum qe_clock rx_clock;
+        enum qe_clock tx_clock;
+        phys_addr_t regs;
+        int irq;
+        u16 uccm_mask;
+        int data_mem_part;
+        int init_tx;
+        int init_rx;
+        u32 tx_bd_ring_len;
+        u32 rx_bd_ring_len;
+        int rx_interrupts;
+        int brkpt_support;
+        int grant_support;
+        int tsa;
+        int cdp;
+        int cds;
+        int ctsp;
+        int ctss;
+        int rinv;
+        int tinv;
+        int rtsm;
+        int rfw;
+        int tci;
+        int tend;
+        int tfl;
+        int txsy;
+        u16 max_rx_buf_length;
+        enum ucc_slow_transparent_tcrc tcrc;
+        enum ucc_slow_channel_protocol_mode mode;
+        enum ucc_slow_diag_mode diag;
+        enum ucc_slow_tx_oversampling_rate tdcr;
+        enum ucc_slow_rx_oversampling_rate rdcr;
+        enum ucc_slow_tx_encoding_method tenc;
+        enum ucc_slow_rx_decoding_method renc;
+};
+
+struct ucc_slow_private {
+        struct ucc_slow_info *us_info;
+        struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
+        struct ucc_slow_pram *us_pram;  /* a pointer to the parameter RAM */
+        u32 us_pram_offset;
+        int enabled_tx;         /* Whether channel is enabled for Tx (ENT) */
+        int enabled_rx;         /* Whether channel is enabled for Rx (ENR) */
+        int stopped_tx;         /* Whether channel has been stopped for Tx
+                                   (STOP_TX, etc.) */
+        int stopped_rx;         /* Whether channel has been stopped for Rx */
+        struct list_head confQ; /* frames passed to chip waiting for tx */
+        u32 first_tx_bd_mask;   /* mask is used in Tx routine to save status
+                                   and length for first BD in a frame */
+        u32 tx_base_offset;     /* first BD in Tx BD table offset (In MURAM) */
+        u32 rx_base_offset;     /* first BD in Rx BD table offset (In MURAM) */
+        struct qe_bd *confBd;   /* next BD for confirm after Tx */
+        struct qe_bd *tx_bd;    /* next BD for new Tx request */
+        struct qe_bd *rx_bd;    /* next BD to collect after Rx */
+        void *p_rx_frame;       /* accumulating receive frame */
+        u16 *p_ucce;            /* a pointer to the event register in memory.
+                                 */
+        u16 *p_uccm;            /* a pointer to the mask register in memory */
+        u16 saved_uccm;         /* a saved mask for the RX Interrupt bits */
+#ifdef STATISTICS
+        u32 tx_frames;          /* Transmitted frames counters */
+        u32 rx_frames;          /* Received frames counters (only frames
+                                   passed to application) */
+        u32 rx_discarded;       /* Discarded frames counters (frames that
+                                   were discarded by the driver due to
+                                   errors) */
+#endif                          /* STATISTICS */
+};
+
+/* ucc_slow_init
+ * Initializes Slow UCC according to provided parameters.
+ *
+ * us_info  - (In) pointer to the slow UCC info structure.
+ * uccs_ret - (Out) pointer to the slow UCC structure.
+ */
+int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
+
+/* ucc_slow_free
+ * Frees all resources for slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_free(struct ucc_slow_private * uccs);
+
+/* ucc_slow_enable
+ * Enables a fast UCC port.
+ * This routine enables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
+
+/* ucc_slow_disable
+ * Disables a fast UCC port.
+ * This routine disables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
+
+/* ucc_slow_poll_transmitter_now
+ * Immediately forces a poll of the transmitter for data to be sent.
+ * Typically, the hardware performs a periodic poll for data that the
+ * transmit routine has set up to be transmitted. In cases where
+ * this polling cycle is not soon enough, this optional routine can
+ * be invoked to force a poll right away, instead. Proper use for
+ * each transmission for which this functionality is desired is to
+ * call the transmit routine and then this routine right after.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
+
+/* ucc_slow_graceful_stop_tx
+ * Smoothly stops transmission on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
+
+/* ucc_slow_stop_tx
+ * Stops transmission on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
+
+/* ucc_slow_restart_tx
+ * Restarts transmitting on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
+
+u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
+
+#endif                          /* __UCC_SLOW_H__ */
diff --git a/arch/powerpc/include/asm/ucontext.h b/arch/powerpc/include/asm/ucontext.h
new file mode 100644
index 000000000000..d9a4ddf0cc86
--- /dev/null
+++ b/arch/powerpc/include/asm/ucontext.h
@@ -0,0 +1,40 @@
+#ifndef _ASM_POWERPC_UCONTEXT_H
+#define _ASM_POWERPC_UCONTEXT_H
+
+#ifdef __powerpc64__
+#include <asm/sigcontext.h>
+#else
+#include <asm/elf.h>
+#endif
+#include <asm/signal.h>
+
+#ifndef __powerpc64__
+struct mcontext {
+        elf_gregset_t   mc_gregs;
+        elf_fpregset_t  mc_fregs;
+        unsigned long   mc_pad[2];
+        elf_vrregset_t  mc_vregs __attribute__((__aligned__(16)));
+};
+#endif
+
+struct ucontext {
+        unsigned long   uc_flags;
+        struct ucontext __user *uc_link;
+        stack_t         uc_stack;
+#ifndef __powerpc64__
+        int             uc_pad[7];
+        struct mcontext __user *uc_regs;/* points to uc_mcontext field */
+#endif
+        sigset_t        uc_sigmask;
+        /* glibc has 1024-bit signal masks, ours are 64-bit */
+#ifdef __powerpc64__
+        sigset_t        __unused[15];   /* Allow for uc_sigmask growth */
+        struct sigcontext uc_mcontext;  /* last for extensibility */
+#else
+        int             uc_maskext[30];
+        int             uc_pad2[3];
+        struct mcontext uc_mcontext;
+#endif
+};
+
+#endif /* _ASM_POWERPC_UCONTEXT_H */
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
new file mode 100644
index 000000000000..6418ceea44b7
--- /dev/null
+++ b/arch/powerpc/include/asm/udbg.h
@@ -0,0 +1,55 @@
+/*
+ * (c) 2001, 2006 IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_POWERPC_UDBG_H
+#define _ASM_POWERPC_UDBG_H
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <linux/init.h>
+
+extern void (*udbg_putc)(char c);
+extern int (*udbg_getc)(void);
+extern int (*udbg_getc_poll)(void);
+
+extern void udbg_puts(const char *s);
+extern int udbg_write(const char *s, int n);
+extern int udbg_read(char *buf, int buflen);
+
+extern void register_early_udbg_console(void);
+extern void udbg_printf(const char *fmt, ...)
+        __attribute__ ((format (printf, 1, 2)));
+extern void udbg_progress(char *s, unsigned short hex);
+
+extern void udbg_init_uart(void __iomem *comport, unsigned int speed,
+                           unsigned int clock);
+extern unsigned int udbg_probe_uart_speed(void __iomem *comport,
+                                          unsigned int clock);
+
+struct device_node;
+extern void udbg_scc_init(int force_scc);
+extern int udbg_adb_init(int force_btext);
+extern void udbg_adb_init_early(void);
+
+extern void __init udbg_early_init(void);
+extern void __init udbg_init_debug_lpar(void);
+extern void __init udbg_init_pmac_realmode(void);
+extern void __init udbg_init_maple_realmode(void);
+extern void __init udbg_init_pas_realmode(void);
+extern void __init udbg_init_iseries(void);
+extern void __init udbg_init_rtas_panel(void);
+extern void __init udbg_init_rtas_console(void);
+extern void __init udbg_init_debug_beat(void);
+extern void __init udbg_init_btext(void);
+extern void __init udbg_init_44x_as1(void);
+extern void __init udbg_init_40x_realmode(void);
+extern void __init udbg_init_cpm(void);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_UDBG_H */
diff --git a/arch/powerpc/include/asm/uic.h b/arch/powerpc/include/asm/uic.h
new file mode 100644
index 000000000000..597edfcae3d6
--- /dev/null
+++ b/arch/powerpc/include/asm/uic.h
@@ -0,0 +1,21 @@
+/*
+ * IBM PPC4xx UIC external definitions and structure.
+ *
+ * Maintainer: David Gibson <dwg@au1.ibm.com>
+ * Copyright 2007 IBM Corporation.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_POWERPC_UIC_H
+#define _ASM_POWERPC_UIC_H
+
+#ifdef __KERNEL__
+
+extern void __init uic_init_tree(void);
+extern unsigned int uic_get_irq(void);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_UIC_H */
diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h
new file mode 100644
index 000000000000..5f1b1e3c2137
--- /dev/null
+++ b/arch/powerpc/include/asm/unaligned.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_POWERPC_UNALIGNED_H
+#define _ASM_POWERPC_UNALIGNED_H
+
+#ifdef __KERNEL__
+
+/*
+ * The PowerPC can do unaligned accesses itself in big endian mode.
+ */
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned   __get_unaligned_be
+#define put_unaligned   __put_unaligned_be
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_UNALIGNED_H */
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
new file mode 100644
index 000000000000..f737732c3861
--- /dev/null
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -0,0 +1,229 @@
+/*
+ * uninorth.h: definitions for using the "UniNorth" host bridge chip
+ *             from Apple. This chip is used on "Core99" machines
+ *             This also includes U2 used on more recent MacRISC2/3
+ *             machines and U3 (G5) 
+ *
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_UNINORTH_H__
+#define __ASM_UNINORTH_H__
+
+/*
+ * Uni-N and U3 config space reg. definitions
+ *
+ * (Little endian)
+ */
+
+/* Address ranges selection. This one should work with Bandit too */
+/* Not U3 */
+#define UNI_N_ADDR_SELECT               0x48
+#define UNI_N_ADDR_COARSE_MASK          0xffff0000      /* 256Mb regions at *0000000 */
+#define UNI_N_ADDR_FINE_MASK            0x0000ffff      /*  16Mb regions at f*000000 */
+
+/* AGP registers */
+/* Not U3 */
+#define UNI_N_CFG_GART_BASE             0x8c
+#define UNI_N_CFG_AGP_BASE              0x90
+#define UNI_N_CFG_GART_CTRL             0x94
+#define UNI_N_CFG_INTERNAL_STATUS       0x98
+#define UNI_N_CFG_GART_DUMMY_PAGE       0xa4
+
+/* UNI_N_CFG_GART_CTRL bits definitions */
+#define UNI_N_CFG_GART_INVAL            0x00000001
+#define UNI_N_CFG_GART_ENABLE           0x00000100
+#define UNI_N_CFG_GART_2xRESET          0x00010000
+#define UNI_N_CFG_GART_DISSBADET        0x00020000
+/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
+#define U3_N_CFG_GART_SYNCMODE          0x00040000
+#define U3_N_CFG_GART_PERFRD            0x00080000
+#define U3_N_CFG_GART_B2BGNT            0x00200000
+#define U3_N_CFG_GART_FASTDDR           0x00400000
+
+/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
+ * revision 1.5 (x4 AGP) may need further changes.
+ *
+ * AGP_BASE register contains the base address of the AGP aperture on
+ * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
+ * even if decoding of this address range is enabled in the address select
+ * register. Apparently, the only supported bases are 256Mb multiples
+ * (high 4 bits of that register).
+ *
+ * GART_BASE register appear to contain the physical address of the GART
+ * in system memory in the high address bits (page aligned), and the
+ * GART size in the low order bits (number of GART pages)
+ *
+ * The GART format itself is one 32bits word per physical memory page.
+ * This word contains, in little-endian format (!!!), the physical address
+ * of the page in the high bits, and what appears to be an "enable" bit
+ * in the LSB bit (0) that must be set to 1 when the entry is valid.
+ *
+ * Obviously, the GART is not cache coherent and so any change to it
+ * must be flushed to memory (or maybe just make the GART space non
+ * cachable). AGP memory itself doens't seem to be cache coherent neither.
+ *
+ * In order to invalidate the GART (which is probably necessary to inval
+ * the bridge internal TLBs), the following sequence has to be written,
+ * in order, to the GART_CTRL register:
+ *
+ *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
+ *   UNI_N_CFG_GART_ENABLE
+ *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
+ *   UNI_N_CFG_GART_ENABLE
+ *
+ * As far as AGP "features" are concerned, it looks like fast write may
+ * not be supported but this has to be confirmed.
+ *
+ * Turning on AGP seem to require a double invalidate operation, one before
+ * setting the AGP command register, on after.
+ *
+ * Turning off AGP seems to require the following sequence: first wait
+ * for the AGP to be idle by reading the internal status register, then
+ * write in that order to the GART_CTRL register:
+ *
+ *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
+ *   0
+ *   UNI_N_CFG_GART_2xRESET
+ *   0
+ */
+
+/*
+ * Uni-N memory mapped reg. definitions
+ *
+ * Those registers are Big-Endian !!
+ *
+ * Their meaning come from either Darwin and/or from experiments I made with
+ * the bootrom, I'm not sure about their exact meaning yet
+ *
+ */
+
+/* Version of the UniNorth chip */
+#define UNI_N_VERSION                   0x0000          /* Known versions: 3,7 and 8 */
+
+#define UNI_N_VERSION_107               0x0003          /* 1.0.7 */
+#define UNI_N_VERSION_10A               0x0007          /* 1.0.10 */
+#define UNI_N_VERSION_150               0x0011          /* 1.5 */
+#define UNI_N_VERSION_200               0x0024          /* 2.0 */
+#define UNI_N_VERSION_PANGEA            0x00C0          /* Integrated U1 + K */
+#define UNI_N_VERSION_INTREPID          0x00D2          /* Integrated U2 + K */
+#define UNI_N_VERSION_300               0x0030          /* 3.0 (U3 on G5) */
+
+/* This register is used to enable/disable various clocks */
+#define UNI_N_CLOCK_CNTL                0x0020
+#define UNI_N_CLOCK_CNTL_PCI            0x00000001      /* PCI2 clock control */
+#define UNI_N_CLOCK_CNTL_GMAC           0x00000002      /* GMAC clock control */
+#define UNI_N_CLOCK_CNTL_FW             0x00000004      /* FireWire clock control */
+#define UNI_N_CLOCK_CNTL_ATA100         0x00000010      /* ATA-100 clock control (U2) */
+
+/* Power Management control */
+#define UNI_N_POWER_MGT                 0x0030
+#define UNI_N_POWER_MGT_NORMAL          0x00
+#define UNI_N_POWER_MGT_IDLE2           0x01
+#define UNI_N_POWER_MGT_SLEEP           0x02
+
+/* This register is configured by Darwin depending on the UniN
+ * revision
+ */
+#define UNI_N_ARB_CTRL                  0x0040
+#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
+#define UNI_N_ARB_CTRL_QACK_DELAY_MASK  0x0e1f8000
+#define UNI_N_ARB_CTRL_QACK_DELAY       0x30
+#define UNI_N_ARB_CTRL_QACK_DELAY105    0x00
+
+/* This one _might_ return the CPU number of the CPU reading it;
+ * the bootROM decides whether to boot or to sleep/spinloop depending
+ * on this register beeing 0 or not
+ */
+#define UNI_N_CPU_NUMBER                0x0050
+
+/* This register appear to be read by the bootROM to decide what
+ *  to do on a non-recoverable reset (powerup or wakeup)
+ */
+#define UNI_N_HWINIT_STATE              0x0070
+#define UNI_N_HWINIT_STATE_SLEEPING     0x01
+#define UNI_N_HWINIT_STATE_RUNNING      0x02
+/* This last bit appear to be used by the bootROM to know the second
+ * CPU has started and will enter it's sleep loop with IP=0
+ */
+#define UNI_N_HWINIT_STATE_CPU1_FLAG    0x10000000
+
+/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
+ * is in low speed mode.
+ */
+#define UNI_N_AACK_DELAY                0x0100
+#define UNI_N_AACK_DELAY_ENABLE         0x00000001
+
+/* Clock status for Intrepid */
+#define UNI_N_CLOCK_STOP_STATUS0        0x0150
+#define UNI_N_CLOCK_STOPPED_EXTAGP      0x00200000
+#define UNI_N_CLOCK_STOPPED_AGPDEL      0x00100000
+#define UNI_N_CLOCK_STOPPED_I2S0_45_49  0x00080000
+#define UNI_N_CLOCK_STOPPED_I2S0_18     0x00040000
+#define UNI_N_CLOCK_STOPPED_I2S1_45_49  0x00020000
+#define UNI_N_CLOCK_STOPPED_I2S1_18     0x00010000
+#define UNI_N_CLOCK_STOPPED_TIMER       0x00008000
+#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
+#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
+#define UNI_N_CLOCK_STOPPED_SCC_VIA32   0x00001000
+#define UNI_N_CLOCK_STOPPED_SCC_SLOT0   0x00000800
+#define UNI_N_CLOCK_STOPPED_SCC_SLOT1   0x00000400
+#define UNI_N_CLOCK_STOPPED_SCC_SLOT2   0x00000200
+#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO  0x00000100
+#define UNI_N_CLOCK_STOPPED_VEO0        0x00000080
+#define UNI_N_CLOCK_STOPPED_VEO1        0x00000040
+#define UNI_N_CLOCK_STOPPED_USB0        0x00000020
+#define UNI_N_CLOCK_STOPPED_USB1        0x00000010
+#define UNI_N_CLOCK_STOPPED_USB2        0x00000008
+#define UNI_N_CLOCK_STOPPED_32          0x00000004
+#define UNI_N_CLOCK_STOPPED_45          0x00000002
+#define UNI_N_CLOCK_STOPPED_49          0x00000001
+
+#define UNI_N_CLOCK_STOP_STATUS1        0x0160
+#define UNI_N_CLOCK_STOPPED_PLL4REF     0x00080000
+#define UNI_N_CLOCK_STOPPED_CPUDEL      0x00040000
+#define UNI_N_CLOCK_STOPPED_CPU         0x00020000
+#define UNI_N_CLOCK_STOPPED_BUF_REFCKO  0x00010000
+#define UNI_N_CLOCK_STOPPED_PCI2        0x00008000
+#define UNI_N_CLOCK_STOPPED_FW          0x00004000
+#define UNI_N_CLOCK_STOPPED_GB          0x00002000
+#define UNI_N_CLOCK_STOPPED_ATA66       0x00001000
+#define UNI_N_CLOCK_STOPPED_ATA100      0x00000800
+#define UNI_N_CLOCK_STOPPED_MAX         0x00000400
+#define UNI_N_CLOCK_STOPPED_PCI1        0x00000200
+#define UNI_N_CLOCK_STOPPED_KLPCI       0x00000100
+#define UNI_N_CLOCK_STOPPED_USB0PCI     0x00000080
+#define UNI_N_CLOCK_STOPPED_USB1PCI     0x00000040
+#define UNI_N_CLOCK_STOPPED_USB2PCI     0x00000020
+#define UNI_N_CLOCK_STOPPED_7PCI1       0x00000008
+#define UNI_N_CLOCK_STOPPED_AGP         0x00000004
+#define UNI_N_CLOCK_STOPPED_PCI0        0x00000002
+#define UNI_N_CLOCK_STOPPED_18          0x00000001
+
+/* Intrepid registe to OF do-platform-clockspreading */
+#define UNI_N_CLOCK_SPREADING           0x190
+
+/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
+
+
+/*
+ * U3 specific registers
+ */
+
+
+/* U3 Toggle */
+#define U3_TOGGLE_REG                   0x00e0
+#define U3_PMC_START_STOP               0x0001
+#define U3_MPIC_RESET                   0x0002
+#define U3_MPIC_OUTPUT_ENABLE           0x0004
+
+/* U3 API PHY Config 1 */
+#define U3_API_PHY_CONFIG_1             0x23030
+
+/* U3 HyperTransport registers */
+#define U3_HT_CONFIG_BASE               0x70000
+#define U3_HT_LINK_COMMAND              0x100
+#define U3_HT_LINK_CONFIG               0x110
+#define U3_HT_LINK_FREQ                 0x120
+
+#endif /* __ASM_UNINORTH_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
new file mode 100644
index 000000000000..e07d0c76ed77
--- /dev/null
+++ b/arch/powerpc/include/asm/unistd.h
@@ -0,0 +1,398 @@
+#ifndef _ASM_POWERPC_UNISTD_H_
+#define _ASM_POWERPC_UNISTD_H_
+
+/*
+ * This file contains the system call numbers.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define __NR_restart_syscall      0
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_waitpid              7
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_time                13
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lchown              16
+#define __NR_break               17
+#define __NR_oldstat             18
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_umount              22
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_ptrace              26
+#define __NR_alarm               27
+#define __NR_oldfstat            28
+#define __NR_pause               29
+#define __NR_utime               30
+#define __NR_stty                31
+#define __NR_gtty                32
+#define __NR_access              33
+#define __NR_nice                34
+#define __NR_ftime               35
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_prof                44
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_signal              48
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_umount2             52
+#define __NR_lock                53
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_mpx                 56
+#define __NR_setpgid             57
+#define __NR_ulimit              58
+#define __NR_oldolduname         59
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_sgetmask            68
+#define __NR_ssetmask            69
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrlimit           76
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_select              82
+#define __NR_symlink             83
+#define __NR_oldlstat            84
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_readdir             89
+#define __NR_mmap                90
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_profil              98
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_ioperm             101
+#define __NR_socketcall         102
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_olduname           109
+#define __NR_iopl               110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_vm86               113
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_ipc                117
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_modify_ldt         123
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_sigprocmask        126
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_get_kernel_syms    130
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+#define __NR__newselect         142
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+#define __NR_mlock              150
+#define __NR_munlock            151
+#define __NR_mlockall           152
+#define __NR_munlockall         153
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+#define __NR_mremap             163
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+#define __NR_query_module       166
+#define __NR_poll               167
+#define __NR_nfsservctl         168
+#define __NR_setresgid          169
+#define __NR_getresgid          170
+#define __NR_prctl              171
+#define __NR_rt_sigreturn       172
+#define __NR_rt_sigaction       173
+#define __NR_rt_sigprocmask     174
+#define __NR_rt_sigpending      175
+#define __NR_rt_sigtimedwait    176
+#define __NR_rt_sigqueueinfo    177
+#define __NR_rt_sigsuspend      178
+#define __NR_pread64            179
+#define __NR_pwrite64           180
+#define __NR_chown              181
+#define __NR_getcwd             182
+#define __NR_capget             183
+#define __NR_capset             184
+#define __NR_sigaltstack        185
+#define __NR_sendfile           186
+#define __NR_getpmsg            187     /* some people actually want streams */
+#define __NR_putpmsg            188     /* some people actually want streams */
+#define __NR_vfork              189
+#define __NR_ugetrlimit         190     /* SuS compliant getrlimit */
+#define __NR_readahead          191
+#ifndef __powerpc64__                   /* these are 32-bit only */
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#endif
+#define __NR_pciconfig_read     198
+#define __NR_pciconfig_write    199
+#define __NR_pciconfig_iobase   200
+#define __NR_multiplexer        201
+#define __NR_getdents64         202
+#define __NR_pivot_root         203
+#ifndef __powerpc64__
+#define __NR_fcntl64            204
+#endif
+#define __NR_madvise            205
+#define __NR_mincore            206
+#define __NR_gettid             207
+#define __NR_tkill              208
+#define __NR_setxattr           209
+#define __NR_lsetxattr          210
+#define __NR_fsetxattr          211
+#define __NR_getxattr           212
+#define __NR_lgetxattr          213
+#define __NR_fgetxattr          214
+#define __NR_listxattr          215
+#define __NR_llistxattr         216
+#define __NR_flistxattr         217
+#define __NR_removexattr        218
+#define __NR_lremovexattr       219
+#define __NR_fremovexattr       220
+#define __NR_futex              221
+#define __NR_sched_setaffinity  222
+#define __NR_sched_getaffinity  223
+/* 224 currently unused */
+#define __NR_tuxcall            225
+#ifndef __powerpc64__
+#define __NR_sendfile64         226
+#endif
+#define __NR_io_setup           227
+#define __NR_io_destroy         228
+#define __NR_io_getevents       229
+#define __NR_io_submit          230
+#define __NR_io_cancel          231
+#define __NR_set_tid_address    232
+#define __NR_fadvise64          233
+#define __NR_exit_group         234
+#define __NR_lookup_dcookie     235
+#define __NR_epoll_create       236
+#define __NR_epoll_ctl          237
+#define __NR_epoll_wait         238
+#define __NR_remap_file_pages   239
+#define __NR_timer_create       240
+#define __NR_timer_settime      241
+#define __NR_timer_gettime      242
+#define __NR_timer_getoverrun   243
+#define __NR_timer_delete       244
+#define __NR_clock_settime      245
+#define __NR_clock_gettime      246
+#define __NR_clock_getres       247
+#define __NR_clock_nanosleep    248
+#define __NR_swapcontext        249
+#define __NR_tgkill             250
+#define __NR_utimes             251
+#define __NR_statfs64           252
+#define __NR_fstatfs64          253
+#ifndef __powerpc64__
+#define __NR_fadvise64_64       254
+#endif
+#define __NR_rtas               255
+#define __NR_sys_debug_setcontext 256
+/* Number 257 is reserved for vserver */
+#define __NR_migrate_pages      258
+#define __NR_mbind              259
+#define __NR_get_mempolicy      260
+#define __NR_set_mempolicy      261
+#define __NR_mq_open            262
+#define __NR_mq_unlink          263
+#define __NR_mq_timedsend       264
+#define __NR_mq_timedreceive    265
+#define __NR_mq_notify          266
+#define __NR_mq_getsetattr      267
+#define __NR_kexec_load         268
+#define __NR_add_key            269
+#define __NR_request_key        270
+#define __NR_keyctl             271
+#define __NR_waitid             272
+#define __NR_ioprio_set         273
+#define __NR_ioprio_get         274
+#define __NR_inotify_init       275
+#define __NR_inotify_add_watch  276
+#define __NR_inotify_rm_watch   277
+#define __NR_spu_run            278
+#define __NR_spu_create         279
+#define __NR_pselect6           280
+#define __NR_ppoll              281
+#define __NR_unshare            282
+#define __NR_splice             283
+#define __NR_tee                284
+#define __NR_vmsplice           285
+#define __NR_openat             286
+#define __NR_mkdirat            287
+#define __NR_mknodat            288
+#define __NR_fchownat           289
+#define __NR_futimesat          290
+#ifdef __powerpc64__
+#define __NR_newfstatat         291
+#else
+#define __NR_fstatat64          291
+#endif
+#define __NR_unlinkat           292
+#define __NR_renameat           293
+#define __NR_linkat             294
+#define __NR_symlinkat          295
+#define __NR_readlinkat         296
+#define __NR_fchmodat           297
+#define __NR_faccessat          298
+#define __NR_get_robust_list    299
+#define __NR_set_robust_list    300
+#define __NR_move_pages         301
+#define __NR_getcpu             302
+#define __NR_epoll_pwait        303
+#define __NR_utimensat          304
+#define __NR_signalfd           305
+#define __NR_timerfd_create     306
+#define __NR_eventfd            307
+#define __NR_sync_file_range2   308
+#define __NR_fallocate          309
+#define __NR_subpage_prot       310
+#define __NR_timerfd_settime    311
+#define __NR_timerfd_gettime    312
+#define __NR_signalfd4          313
+#define __NR_eventfd2           314
+#define __NR_epoll_create1      315
+#define __NR_dup3               316
+#define __NR_pipe2              317
+#define __NR_inotify_init1      318
+
+#ifdef __KERNEL__
+
+#define __NR_syscalls           319
+
+#define __NR__exit __NR_exit
+#define NR_syscalls     __NR_syscalls
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+#ifdef CONFIG_PPC32
+#define __ARCH_WANT_OLD_STAT
+#endif
+#ifdef CONFIG_PPC64
+#define __ARCH_WANT_COMPAT_SYS_TIME
+#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
+#define __ARCH_WANT_SYS_NEWFSTATAT
+#endif
+
+/*
+ * "Conditional" syscalls
+ */
+#define cond_syscall(x) \
+        asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
+
+#endif          /* __ASSEMBLY__ */
+#endif          /* __KERNEL__ */
+
+#endif /* _ASM_POWERPC_UNISTD_H_ */
diff --git a/arch/powerpc/include/asm/user.h b/arch/powerpc/include/asm/user.h
new file mode 100644
index 000000000000..3fd4545dd74e
--- /dev/null
+++ b/arch/powerpc/include/asm/user.h
@@ -0,0 +1,51 @@
+#ifndef _ASM_POWERPC_USER_H
+#define _ASM_POWERPC_USER_H
+
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/*
+ * Adapted from <asm-alpha/user.h>
+ *
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd, NOT the osf-core).  The file contents
+ * are as follows:
+ *
+ *  upage: 1 page consisting of a user struct that tells gdb
+ *      what is present in the file.  Directly after this is a
+ *      copy of the task_struct, which is currently not used by gdb,
+ *      but it may come in handy at some point.  All of the registers
+ *      are stored as part of the upage.  The upage should always be
+ *      only one page long.
+ *  data: The data segment follows next.  We use current->end_text to
+ *      current->brk to pick up all of the user variables, plus any memory
+ *      that may have been sbrk'ed.  No attempt is made to determine if a
+ *      page is demand-zero or if a page is totally unused, we just cover
+ *      the entire range.  All of the addresses are rounded in such a way
+ *      that an integral number of pages is written.
+ *  stack: We need the stack information in order to get a meaningful
+ *      backtrace.  We need to write the data from usp to
+ *      current->start_stack, so we round each of these in order to be able
+ *      to write an integer number of pages.
+ */
+struct user {
+        struct pt_regs  regs;                   /* entire machine state */
+        size_t          u_tsize;                /* text size (pages) */
+        size_t          u_dsize;                /* data size (pages) */
+        size_t          u_ssize;                /* stack size (pages) */
+        unsigned long   start_code;             /* text starting address */
+        unsigned long   start_data;             /* data starting address */
+        unsigned long   start_stack;            /* stack starting address */
+        long int        signal;                 /* signal causing core dump */
+        unsigned long   u_ar0;                  /* help gdb find registers */
+        unsigned long   magic;                  /* identifies a core file */
+        char            u_comm[32];             /* user command name */
+};
+
+#define NBPG                    PAGE_SIZE
+#define UPAGES                  1
+#define HOST_TEXT_START_ADDR    (u.start_code)
+#define HOST_DATA_START_ADDR    (u.start_data)
+#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+#endif  /* _ASM_POWERPC_USER_H */
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
new file mode 100644
index 000000000000..26fc449bd989
--- /dev/null
+++ b/arch/powerpc/include/asm/vdso.h
@@ -0,0 +1,78 @@
+#ifndef __PPC64_VDSO_H__
+#define __PPC64_VDSO_H__
+
+#ifdef __KERNEL__
+
+/* Default link addresses for the vDSOs */
+#define VDSO32_LBASE    0x100000
+#define VDSO64_LBASE    0x100000
+
+/* Default map addresses */
+#define VDSO32_MBASE    VDSO32_LBASE
+#define VDSO64_MBASE    VDSO64_LBASE
+
+#define VDSO_VERSION_STRING     LINUX_2.6.15
+
+/* Define if 64 bits VDSO has procedure descriptors */
+#undef VDS64_HAS_DESCRIPTORS
+
+#ifndef __ASSEMBLY__
+
+/* Offsets relative to thread->vdso_base */
+extern unsigned long vdso64_rt_sigtramp;
+extern unsigned long vdso32_sigtramp;
+extern unsigned long vdso32_rt_sigtramp;
+
+#else /* __ASSEMBLY__ */
+
+#ifdef __VDSO64__
+#ifdef VDS64_HAS_DESCRIPTORS
+#define V_FUNCTION_BEGIN(name)          \
+        .globl name;                    \
+        .section ".opd","a";            \
+        .align 3;                       \
+        name:                           \
+        .quad .name,.TOC.@tocbase,0;    \
+        .previous;                      \
+        .globl .name;                   \
+        .type .name,@function;          \
+        .name:                          \
+
+#define V_FUNCTION_END(name)            \
+        .size .name,.-.name;
+
+#define V_LOCAL_FUNC(name) (.name)
+
+#else /* VDS64_HAS_DESCRIPTORS */
+
+#define V_FUNCTION_BEGIN(name)          \
+        .globl name;                    \
+        name:                           \
+
+#define V_FUNCTION_END(name)            \
+        .size name,.-name;
+
+#define V_LOCAL_FUNC(name) (name)
+
+#endif /* VDS64_HAS_DESCRIPTORS */
+#endif /* __VDSO64__ */
+
+#ifdef __VDSO32__
+
+#define V_FUNCTION_BEGIN(name)          \
+        .globl name;                    \
+        .type name,@function;           \
+        name:                           \
+
+#define V_FUNCTION_END(name)            \
+        .size name,.-name;
+
+#define V_LOCAL_FUNC(name) (name)
+
+#endif /* __VDSO32__ */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __PPC64_VDSO_H__ */
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
new file mode 100644
index 000000000000..f01393224b52
--- /dev/null
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -0,0 +1,121 @@
+#ifndef _VDSO_DATAPAGE_H
+#define _VDSO_DATAPAGE_H
+#ifdef __KERNEL__
+
+/*
+ * Copyright (C) 2002 Peter Bergner <bergner@vnet.ibm.com>, IBM
+ * Copyright (C) 2005 Benjamin Herrenschmidy <benh@kernel.crashing.org>,
+ *                    IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+
+/*
+ * Note about this structure:
+ *
+ * This structure was historically called systemcfg and exposed to
+ * userland via /proc/ppc64/systemcfg. Unfortunately, this became an
+ * ABI issue as some proprietary software started relying on being able
+ * to mmap() it, thus we have to keep the base layout at least for a
+ * few kernel versions.
+ *
+ * However, since ppc32 doesn't suffer from this backward handicap,
+ * a simpler version of the data structure is used there with only the
+ * fields actually used by the vDSO.
+ *
+ */
+
+/*
+ * If the major version changes we are incompatible.
+ * Minor version changes are a hint.
+ */
+#define SYSTEMCFG_MAJOR 1
+#define SYSTEMCFG_MINOR 1
+
+#ifndef __ASSEMBLY__
+
+#include <linux/unistd.h>
+
+#define SYSCALL_MAP_SIZE      ((__NR_syscalls + 31) / 32)
+
+/*
+ * So here is the ppc64 backward compatible version
+ */
+
+#ifdef CONFIG_PPC64
+
+struct vdso_data {
+        __u8  eye_catcher[16];          /* Eyecatcher: SYSTEMCFG:PPC64  0x00 */
+        struct {                        /* Systemcfg version numbers         */
+                __u32 major;            /* Major number                 0x10 */
+                __u32 minor;            /* Minor number                 0x14 */
+        } version;
+
+        /* Note about the platform flags: it now only contains the lpar
+         * bit. The actual platform number is dead and burried
+         */
+        __u32 platform;                 /* Platform flags               0x18 */
+        __u32 processor;                /* Processor type               0x1C */
+        __u64 processorCount;           /* # of physical processors     0x20 */
+        __u64 physicalMemorySize;       /* Size of real memory(B)       0x28 */
+        __u64 tb_orig_stamp;            /* Timebase at boot             0x30 */
+        __u64 tb_ticks_per_sec;         /* Timebase tics / sec          0x38 */
+        __u64 tb_to_xs;                 /* Inverse of TB to 2^20        0x40 */
+        __u64 stamp_xsec;               /*                              0x48 */
+        __u64 tb_update_count;          /* Timebase atomicity ctr       0x50 */
+        __u32 tz_minuteswest;           /* Minutes west of Greenwich    0x58 */
+        __u32 tz_dsttime;               /* Type of dst correction       0x5C */
+        __u32 dcache_size;              /* L1 d-cache size              0x60 */
+        __u32 dcache_line_size;         /* L1 d-cache line size         0x64 */
+        __u32 icache_size;              /* L1 i-cache size              0x68 */
+        __u32 icache_line_size;         /* L1 i-cache line size         0x6C */
+
+        /* those additional ones don't have to be located anywhere
+         * special as they were not part of the original systemcfg
+         */
+        __u32 dcache_block_size;                /* L1 d-cache block size     */
+        __u32 icache_block_size;                /* L1 i-cache block size     */
+        __u32 dcache_log_block_size;            /* L1 d-cache log block size */
+        __u32 icache_log_block_size;            /* L1 i-cache log block size */
+        __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
+        __s32 wtom_clock_nsec;
+        __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls  */
+        __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
+};
+
+#else /* CONFIG_PPC64 */
+
+/*
+ * And here is the simpler 32 bits version
+ */
+struct vdso_data {
+        __u64 tb_orig_stamp;            /* Timebase at boot             0x30 */
+        __u64 tb_ticks_per_sec;         /* Timebase tics / sec          0x38 */
+        __u64 tb_to_xs;                 /* Inverse of TB to 2^20        0x40 */
+        __u64 stamp_xsec;               /*                              0x48 */
+        __u32 tb_update_count;          /* Timebase atomicity ctr       0x50 */
+        __u32 tz_minuteswest;           /* Minutes west of Greenwich    0x58 */
+        __u32 tz_dsttime;               /* Type of dst correction       0x5C */
+        __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
+        __s32 wtom_clock_nsec;
+        __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
+        __u32 dcache_block_size;        /* L1 d-cache block size     */
+        __u32 icache_block_size;        /* L1 i-cache block size     */
+        __u32 dcache_log_block_size;    /* L1 d-cache log block size */
+        __u32 icache_log_block_size;    /* L1 i-cache log block size */
+};
+
+#endif /* CONFIG_PPC64 */
+
+#ifdef __KERNEL__
+extern struct vdso_data *vdso_data;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* _SYSTEMCFG_H */
diff --git a/arch/powerpc/include/asm/vga.h b/arch/powerpc/include/asm/vga.h
new file mode 100644
index 000000000000..a2eac409c1ec
--- /dev/null
+++ b/arch/powerpc/include/asm/vga.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_POWERPC_VGA_H_
+#define _ASM_POWERPC_VGA_H_
+
+#ifdef __KERNEL__
+
+/*
+ *      Access to VGA videoram
+ *
+ *      (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+
+
+#include <asm/io.h>
+
+
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
+
+#define VT_BUF_HAVE_RW
+/*
+ *  These are only needed for supporting VGA or MDA text mode, which use little
+ *  endian byte ordering.
+ *  In other cases, we can optimize by using native byte ordering and
+ *  <linux/vt_buffer.h> has already done the right job for us.
+ */
+
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+    st_le16(addr, val);
+}
+
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+    return ld_le16(addr);
+}
+
+#define VT_BUF_HAVE_MEMCPYW
+#define scr_memcpyw     memcpy
+
+#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
+
+extern unsigned long vgacon_remap_base;
+
+#ifdef __powerpc64__
+#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap((x), s))
+#else
+#define VGA_MAP_MEM(x,s) (x + vgacon_remap_base)
+#endif
+
+#define vga_readb(x) (*(x))
+#define vga_writeb(x,y) (*(y) = (x))
+
+#endif  /* __KERNEL__ */
+#endif  /* _ASM_POWERPC_VGA_H_ */
diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h
new file mode 100644
index 000000000000..0a290a195946
--- /dev/null
+++ b/arch/powerpc/include/asm/vio.h
@@ -0,0 +1,118 @@
+/*
+ * IBM PowerPC Virtual I/O Infrastructure Support.
+ *
+ * Copyright (c) 2003 IBM Corp.
+ *  Dave Engebretsen engebret@us.ibm.com
+ *  Santiago Leon santil@us.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_POWERPC_VIO_H
+#define _ASM_POWERPC_VIO_H
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mod_devicetable.h>
+
+#include <asm/hvcall.h>
+#include <asm/scatterlist.h>
+
+/*
+ * Architecture-specific constants for drivers to
+ * extract attributes of the device using vio_get_attribute()
+ */
+#define VETH_MAC_ADDR "local-mac-address"
+#define VETH_MCAST_FILTER_SIZE "ibm,mac-address-filters"
+
+/* End architecture-specific constants */
+
+#define h_vio_signal(ua, mode) \
+  plpar_hcall_norets(H_VIO_SIGNAL, ua, mode)
+
+#define VIO_IRQ_DISABLE         0UL
+#define VIO_IRQ_ENABLE          1UL
+
+/*
+ * VIO CMO minimum entitlement for all devices and spare entitlement
+ */
+#define VIO_CMO_MIN_ENT 1562624
+
+struct iommu_table;
+
+/**
+ * vio_dev - This structure is used to describe virtual I/O devices.
+ *
+ * @desired: set from return of driver's get_desired_dma() function
+ * @entitled: bytes of IO data that has been reserved for this device.
+ * @allocated: bytes of IO data currently in use by the device.
+ * @allocs_failed: number of DMA failures due to insufficient entitlement.
+ */
+struct vio_dev {
+        const char *name;
+        const char *type;
+        uint32_t unit_address;
+        unsigned int irq;
+        struct {
+                size_t desired;
+                size_t entitled;
+                size_t allocated;
+                atomic_t allocs_failed;
+        } cmo;
+        struct device dev;
+};
+
+struct vio_driver {
+        const struct vio_device_id *id_table;
+        int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
+        int (*remove)(struct vio_dev *dev);
+        /* A driver must have a get_desired_dma() function to
+         * be loaded in a CMO environment if it uses DMA.
+         */
+        unsigned long (*get_desired_dma)(struct vio_dev *dev);
+        struct device_driver driver;
+};
+
+extern int vio_register_driver(struct vio_driver *drv);
+extern void vio_unregister_driver(struct vio_driver *drv);
+
+extern int vio_cmo_entitlement_update(size_t);
+extern void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired);
+
+extern void __devinit vio_unregister_device(struct vio_dev *dev);
+
+struct device_node;
+
+extern struct vio_dev *vio_register_device_node(
+                struct device_node *node_vdev);
+extern const void *vio_get_attribute(struct vio_dev *vdev, char *which,
+                int *length);
+#ifdef CONFIG_PPC_PSERIES
+extern struct vio_dev *vio_find_node(struct device_node *vnode);
+extern int vio_enable_interrupts(struct vio_dev *dev);
+extern int vio_disable_interrupts(struct vio_dev *dev);
+#else
+static inline int vio_enable_interrupts(struct vio_dev *dev)
+{
+        return 0;
+}
+#endif
+
+static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
+{
+        return container_of(drv, struct vio_driver, driver);
+}
+
+static inline struct vio_dev *to_vio_dev(struct device *dev)
+{
+        return container_of(dev, struct vio_dev, dev);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_VIO_H */
diff --git a/arch/powerpc/include/asm/xilinx_intc.h b/arch/powerpc/include/asm/xilinx_intc.h
new file mode 100644
index 000000000000..343612f8fece
--- /dev/null
+++ b/arch/powerpc/include/asm/xilinx_intc.h
@@ -0,0 +1,20 @@
+/*
+ * Xilinx intc external definitions
+ *
+ * Copyright 2007 Secret Lab Technologies Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_POWERPC_XILINX_INTC_H
+#define _ASM_POWERPC_XILINX_INTC_H
+
+#ifdef __KERNEL__
+
+extern void __init xilinx_intc_init_tree(void);
+extern unsigned int xilinx_intc_get_irq(void);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/include/asm/xmon.h b/arch/powerpc/include/asm/xmon.h
new file mode 100644
index 000000000000..5eb8e599e5cc
--- /dev/null
+++ b/arch/powerpc/include/asm/xmon.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_POWERPC_XMON_H
+#define __ASM_POWERPC_XMON_H
+
+/*
+ * Copyrignt (C) 2006 IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/irqreturn.h>
+
+#ifdef CONFIG_XMON
+extern void xmon_setup(void);
+extern void xmon_register_spus(struct list_head *list);
+struct pt_regs;
+extern int xmon(struct pt_regs *excp);
+extern irqreturn_t xmon_irq(int, void *);
+#else
+static inline void xmon_setup(void) { };
+static inline void xmon_register_spus(struct list_head *list) { };
+#endif
+
+#if defined(CONFIG_XMON) && defined(CONFIG_SMP)
+extern int cpus_are_in_xmon(void);
+#endif
+
+#endif /* __KERNEL __ */
+#endif /* __ASM_POWERPC_XMON_H */
diff --git a/arch/powerpc/include/asm/xor.h b/arch/powerpc/include/asm/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/arch/powerpc/include/asm/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 1a4094704b1f..64f5948ebc9d 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -59,8 +59,6 @@ obj64-$(CONFIG_HIBERNATION)	+= swsusp_asm64.o
 obj-$(CONFIG_MODULES)           += module.o module_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_44x)               += cpu_setup_44x.o
 
-ifeq ($(CONFIG_PPC_MERGE),y)
-
 extra-$(CONFIG_PPC_STD_MMU)     := head_32.o
 extra-$(CONFIG_PPC64)           := head_64.o
 extra-$(CONFIG_40x)             := head_40x.o
@@ -100,12 +98,6 @@ ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
 obj-y                           += iomap.o
 endif
 
-else
-# stuff used from here for ARCH=ppc
-smpobj-$(CONFIG_SMP)            += smp.o
-
-endif
-
 obj-$(CONFIG_PPC64)             += $(obj64-y)
 
 extra-$(CONFIG_PPC_FPU)         += fpu.o
@@ -121,9 +113,6 @@ PHONY += systbl_chk
 systbl_chk: $(src)/systbl_chk.sh $(obj)/systbl_chk.i
         $(call cmd,systbl_chk)
 
-
-ifeq ($(CONFIG_PPC_MERGE),y)
-
 $(obj)/built-in.o:              prom_init_check
 
 quiet_cmd_prom_init_check = CALL    $<
@@ -133,7 +122,4 @@ PHONY += prom_init_check
 prom_init_check: $(src)/prom_init_check.sh $(obj)/prom_init.o
         $(call cmd,prom_init_check)
 
-endif
-
-
 clean-files := vmlinux.lds
diff --git a/arch/powerpc/kernel/cpu_setup_44x.S b/arch/powerpc/kernel/cpu_setup_44x.S
index 5465e8de0e61..80cac984d85d 100644
--- a/arch/powerpc/kernel/cpu_setup_44x.S
+++ b/arch/powerpc/kernel/cpu_setup_44x.S
@@ -39,12 +39,6 @@ _GLOBAL(__setup_cpu_440gx)
 _GLOBAL(__setup_cpu_440spe)
         b       __fixup_440A_mcheck
 
- /* Temporary fixup for arch/ppc until we kill the whole thing */
-#ifndef CONFIG_PPC_MERGE
-_GLOBAL(__fixup_440A_mcheck)
-        blr
-#endif
-
 /* enable APU between CPU and FPU */
 _GLOBAL(__init_fpu_44x)
         mfspr   r3,SPRN_CCR0
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 81c8324a4a3c..1cbbf7033641 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -148,7 +148,7 @@ transfer_to_handler:
         /* Check to see if the dbcr0 register is set up to debug.  Use the
            internal debug mode bit to do this. */
         lwz     r12,THREAD_DBCR0(r12)
-        andis.  r12,r12,(DBCR0_IDM  | DBSR_DAC1R | DBSR_DAC1W)@h
+        andis.  r12,r12,DBCR0_IDM@h
         beq+    3f
         /* From user and task is ptraced - load up global dbcr0 */
         li      r12,-1                  /* clear all pending debug events */
@@ -292,7 +292,7 @@ syscall_exit_cont:
         /* If the process has its own DBCR0 value, load it up.  The internal
            debug mode bit tells us that dbcr0 should be loaded. */
         lwz     r0,THREAD+THREAD_DBCR0(r2)
-        andis.  r10,r0,(DBCR0_IDM  | DBSR_DAC1R | DBSR_DAC1W)@h
+        andis.  r10,r0,DBCR0_IDM@h
         bnel-   load_dbcr0
 #endif
 #ifdef CONFIG_44x
@@ -343,7 +343,12 @@ syscall_dotrace:
         stw     r0,_TRAP(r1)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      do_syscall_trace_enter
-        lwz     r0,GPR0(r1)     /* Restore original registers */
+        /*
+         * Restore argument registers possibly just changed.
+         * We use the return value of do_syscall_trace_enter
+         * for call number to look up in the table (r0).
+         */
+        mr      r0,r3
         lwz     r3,GPR3(r1)
         lwz     r4,GPR4(r1)
         lwz     r5,GPR5(r1)
@@ -720,7 +725,7 @@ restore_user:
         /* Check whether this process has its own DBCR0 value.  The internal
            debug mode bit tells us that dbcr0 should be loaded. */
         lwz     r0,THREAD+THREAD_DBCR0(r2)
-        andis.  r10,r0,(DBCR0_IDM  | DBSR_DAC1R | DBSR_DAC1W)@h
+        andis.  r10,r0,DBCR0_IDM@h
         bnel-   load_dbcr0
 #endif
 
@@ -1055,8 +1060,8 @@ do_user_signal:			/* r10 contains MSR_KERNEL here */
         SAVE_NVGPRS(r1)
         rlwinm  r3,r3,0,0,30
         stw     r3,_TRAP(r1)
-2:      li      r3,0
-        addi    r4,r1,STACK_FRAME_OVERHEAD
+2:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        mr      r4,r9
         bl      do_signal
         REST_NVGPRS(r1)
         b       recheck
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index d7369243ae44..2d802e97097c 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -214,7 +214,12 @@ syscall_dotrace:
         bl      .save_nvgprs
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .do_syscall_trace_enter
-        ld      r0,GPR0(r1)     /* Restore original registers */
+        /*
+         * Restore argument registers possibly just changed.
+         * We use the return value of do_syscall_trace_enter
+         * for the call number to look up in the table (r0).
+         */
+        mr      r0,r3
         ld      r3,GPR3(r1)
         ld      r4,GPR4(r1)
         ld      r5,GPR5(r1)
@@ -638,8 +643,7 @@ user_work:
         b       .ret_from_except_lite
 
 1:      bl      .save_nvgprs
-        li      r3,0
-        addi    r4,r1,STACK_FRAME_OVERHEAD
+        addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .do_signal
         b       .ret_from_except
 
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 6ac8612da3c3..d972decf0324 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -77,22 +77,12 @@ static int ppc_spurious_interrupts;
 EXPORT_SYMBOL(__irq_offset_value);
 atomic_t ppc_n_lost_interrupts;
 
-#ifndef CONFIG_PPC_MERGE
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
-#endif
-
 #ifdef CONFIG_TAU_INT
 extern int tau_initialized;
 extern int tau_interrupts(int);
 #endif
 #endif /* CONFIG_PPC32 */
 
-#if defined(CONFIG_SMP) && !defined(CONFIG_PPC_MERGE)
-extern atomic_t ipi_recv;
-extern atomic_t ipi_sent;
-#endif
-
 #ifdef CONFIG_PPC64
 EXPORT_SYMBOL(irq_desc);
 
@@ -216,21 +206,14 @@ int show_interrupts(struct seq_file *p, void *v)
 skip:
                 spin_unlock_irqrestore(&desc->lock, flags);
         } else if (i == NR_IRQS) {
-#ifdef CONFIG_PPC32
-#ifdef CONFIG_TAU_INT
+#if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
                 if (tau_initialized){
                         seq_puts(p, "TAU: ");
                         for_each_online_cpu(j)
                                 seq_printf(p, "%10u ", tau_interrupts(j));
                         seq_puts(p, "  PowerPC             Thermal Assist (cpu temp)\n");
                 }
-#endif
-#if defined(CONFIG_SMP) && !defined(CONFIG_PPC_MERGE)
-                /* should this be per processor send/receive? */
-                seq_printf(p, "IPI (recv/sent): %10u/%u\n",
-                                atomic_read(&ipi_recv), atomic_read(&ipi_sent));
-#endif
-#endif /* CONFIG_PPC32 */
+#endif /* CONFIG_PPC32 && CONFIG_TAU_INT*/
                 seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts);
         }
         return 0;
@@ -454,8 +437,6 @@ void do_softirq(void)
  * IRQ controller and virtual interrupts
  */
 
-#ifdef CONFIG_PPC_MERGE
-
 static LIST_HEAD(irq_hosts);
 static DEFINE_SPINLOCK(irq_big_lock);
 static DEFINE_PER_CPU(unsigned int, irq_radix_reader);
@@ -1114,8 +1095,6 @@ static int __init irq_debugfs_init(void)
 __initcall(irq_debugfs_init);
 #endif /* CONFIG_VIRQ_DEBUG */
 
-#endif /* CONFIG_PPC_MERGE */
-
 #ifdef CONFIG_PPC64
 static int __init setup_noirqdistrib(char *str)
 {
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index 4d96e1db55ee..9ddfaef1a184 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -493,18 +493,18 @@ static int __init serial_dev_init(void)
 device_initcall(serial_dev_init);
 
 
+#ifdef CONFIG_SERIAL_8250_CONSOLE
 /*
  * This is called very early, as part of console_init() (typically just after
  * time_init()). This function is respondible for trying to find a good
  * default console on serial ports. It tries to match the open firmware
- * default output with one of the available serial console drivers, either
- * one of the platform serial ports that have been probed earlier by
- * find_legacy_serial_ports() or some more platform specific ones.
+ * default output with one of the available serial console drivers that have
+ * been probed earlier by find_legacy_serial_ports()
  */
 static int __init check_legacy_serial_console(void)
 {
         struct device_node *prom_stdout = NULL;
-        int speed = 0, offset = 0;
+        int i, speed = 0, offset = 0;
         const char *name;
         const u32 *spd;
 
@@ -548,31 +548,20 @@ static int __init check_legacy_serial_console(void)
         if (spd)
                 speed = *spd;
 
-        if (0)
-                ;
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        else if (strcmp(name, "serial") == 0) {
-                int i;
-                /* Look for it in probed array */
-                for (i = 0; i < legacy_serial_count; i++) {
-                        if (prom_stdout != legacy_serial_infos[i].np)
-                                continue;
-                        offset = i;
-                        speed = legacy_serial_infos[i].speed;
-                        break;
-                }
-                if (i >= legacy_serial_count)
-                        goto not_found;
+        if (strcmp(name, "serial") != 0)
+                goto not_found;
+
+        /* Look for it in probed array */
+        for (i = 0; i < legacy_serial_count; i++) {
+                if (prom_stdout != legacy_serial_infos[i].np)
+                        continue;
+                offset = i;
+                speed = legacy_serial_infos[i].speed;
+                break;
         }
-#endif /* CONFIG_SERIAL_8250_CONSOLE */
-#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
-        else if (strcmp(name, "ch-a") == 0)
-                offset = 0;
-        else if (strcmp(name, "ch-b") == 0)
-                offset = 1;
-#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
-        else
+        if (i >= legacy_serial_count)
                 goto not_found;
+
         of_node_put(prom_stdout);
 
         DBG("Found serial console at ttyS%d\n", offset);
@@ -591,3 +580,4 @@ static int __init check_legacy_serial_console(void)
 }
 console_initcall(check_legacy_serial_console);
 
+#endif /* CONFIG_SERIAL_8250_CONSOLE */
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index 9f856a0c3e38..1a09719c7628 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -636,10 +636,6 @@ static ssize_t lparcfg_write(struct file *file, const char __user * buf,
                 retval = -EIO;
         } else if (retval == H_PARAMETER) {
                 retval = -EINVAL;
-        } else {
-                printk(KERN_WARNING "%s: received unknown hv return code %ld",
-                       __func__, retval);
-                retval = -EIO;
         }
 
         return retval;
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index db2497ccc111..957bded0020d 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -254,7 +254,7 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
                 return;
 
         /* Clear the DAC and struct entries.  One shot trigger */
-#if (defined(CONFIG_44x) || defined(CONFIG_BOOKE))
+#if defined(CONFIG_BOOKE)
         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R | DBSR_DAC1W
                                                         | DBCR0_IDM));
 #endif
@@ -276,17 +276,15 @@ int set_dabr(unsigned long dabr)
 {
         __get_cpu_var(current_dabr) = dabr;
 
-#ifdef CONFIG_PPC_MERGE         /* XXX for now */
         if (ppc_md.set_dabr)
                 return ppc_md.set_dabr(dabr);
-#endif
 
         /* XXX should we have a CPU_FTR_HAS_DABR ? */
 #if defined(CONFIG_PPC64) || defined(CONFIG_6xx)
         mtspr(SPRN_DABR, dabr);
 #endif
 
-#if defined(CONFIG_44x) || defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE)
         mtspr(SPRN_DAC1, dabr);
 #endif
 
@@ -373,7 +371,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
         if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
                 set_dabr(new->thread.dabr);
 
-#if defined(CONFIG_44x) || defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE)
         /* If new thread DAC (HW breakpoint) is the same then leave it */
         if (new->thread.dabr)
                 set_dabr(new->thread.dabr);
@@ -568,7 +566,7 @@ void flush_thread(void)
                 current->thread.dabr = 0;
                 set_dabr(0);
 
-#if defined(CONFIG_44x) || defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE)
                 current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W);
 #endif
         }
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index c4ab2195b9cb..b72849ac7db3 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -205,8 +205,6 @@ static int __initdata mem_reserve_cnt;
 static cell_t __initdata regbuf[1024];
 
 
-#define MAX_CPU_THREADS 2
-
 /*
  * Error results ... some OF calls will return "-1" on error, some
  * will return 0, some will return either. To simplify, here are
@@ -1339,10 +1337,6 @@ static void __init prom_hold_cpus(void)
         unsigned int reg;
         phandle node;
         char type[64];
-        int cpuid = 0;
-        unsigned int interrupt_server[MAX_CPU_THREADS];
-        unsigned int cpu_threads, hw_cpu_num;
-        int propsize;
         struct prom_t *_prom = &RELOC(prom);
         unsigned long *spinloop
                 = (void *) LOW_ADDR(__secondary_hold_spinloop);
@@ -1386,7 +1380,6 @@ static void __init prom_hold_cpus(void)
                 reg = -1;
                 prom_getprop(node, "reg", &reg, sizeof(reg));
 
-                prom_debug("\ncpuid        = 0x%x\n", cpuid);
                 prom_debug("cpu hw idx   = 0x%x\n", reg);
 
                 /* Init the acknowledge var which will be reset by
@@ -1395,28 +1388,9 @@ static void __init prom_hold_cpus(void)
                  */
                 *acknowledge = (unsigned long)-1;
 
-                propsize = prom_getprop(node, "ibm,ppc-interrupt-server#s",
-                                        &interrupt_server,
-                                        sizeof(interrupt_server));
-                if (propsize < 0) {
-                        /* no property.  old hardware has no SMT */
-                        cpu_threads = 1;
-                        interrupt_server[0] = reg; /* fake it with phys id */
-                } else {
-                        /* We have a threaded processor */
-                        cpu_threads = propsize / sizeof(u32);
-                        if (cpu_threads > MAX_CPU_THREADS) {
-                                prom_printf("SMT: too many threads!\n"
-                                            "SMT: found %x, max is %x\n",
-                                            cpu_threads, MAX_CPU_THREADS);
-                                cpu_threads = 1; /* ToDo: panic? */
-                        }
-                }
-
-                hw_cpu_num = interrupt_server[0];
-                if (hw_cpu_num != _prom->cpu) {
+                if (reg != _prom->cpu) {
                         /* Primary Thread of non-boot cpu */
-                        prom_printf("%x : starting cpu hw idx %x... ", cpuid, reg);
+                        prom_printf("starting cpu hw idx %x... ", reg);
                         call_prom("start-cpu", 3, 0, node,
                                   secondary_hold, reg);
 
@@ -1431,17 +1405,10 @@ static void __init prom_hold_cpus(void)
                 }
 #ifdef CONFIG_SMP
                 else
-                        prom_printf("%x : boot cpu     %x\n", cpuid, reg);
+                        prom_printf("boot cpu hw idx %x\n", reg);
 #endif /* CONFIG_SMP */
-
-                /* Reserve cpu #s for secondary threads.   They start later. */
-                cpuid += cpu_threads;
         }
 
-        if (cpuid > NR_CPUS)
-                prom_printf("WARNING: maximum CPUs (" __stringify(NR_CPUS)
-                            ") exceeded: ignoring extras\n");
-
         prom_debug("prom_hold_cpus: end...\n");
 }
 
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index a5d0e78779c8..3635be61f899 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/ptrace.h>
 #include <linux/regset.h>
+#include <linux/tracehook.h>
 #include <linux/elf.h>
 #include <linux/user.h>
 #include <linux/security.h>
@@ -374,7 +375,7 @@ static int vsr_get(struct task_struct *target, const struct user_regset *regset,
         flush_vsx_to_thread(target);
 
         for (i = 0; i < 32 ; i++)
-                buf[i] = current->thread.fpr[i][TS_VSRLOWOFFSET];
+                buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
                                   buf, 0, 32 * sizeof(double));
 
@@ -393,7 +394,7 @@ static int vsr_set(struct task_struct *target, const struct user_regset *regset,
         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
                                  buf, 0, 32 * sizeof(double));
         for (i = 0; i < 32 ; i++)
-                current->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
+                target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
 
 
         return ret;
@@ -717,7 +718,7 @@ void user_disable_single_step(struct task_struct *task)
         struct pt_regs *regs = task->thread.regs;
 
 
-#if defined(CONFIG_44x) || defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE)
         /* If DAC then do not single step, skip */
         if (task->thread.dabr)
                 return;
@@ -744,10 +745,11 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
         if (addr > 0)
                 return -EINVAL;
 
+        /* The bottom 3 bits in dabr are flags */
         if ((data & ~0x7UL) >= TASK_SIZE)
                 return -EIO;
 
-#ifdef CONFIG_PPC64
+#ifndef CONFIG_BOOKE
 
         /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
          *  It was assumed, on previous implementations, that 3 bits were
@@ -769,7 +771,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
         task->thread.dabr = data;
 
 #endif
-#if defined(CONFIG_44x) || defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE)
 
         /* As described above, it was assumed 3 bits were passed with the data
          *  address, but we will assume only the mode bits will be passed
@@ -973,15 +975,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         case PTRACE_GETVSRREGS:
                 return copy_regset_to_user(child, &user_ppc_native_view,
                                            REGSET_VSX,
-                                           0, (32 * sizeof(vector128) +
-                                               sizeof(u32)),
+                                           0, 32 * sizeof(double),
                                            (void __user *) data);
 
         case PTRACE_SETVSRREGS:
                 return copy_regset_from_user(child, &user_ppc_native_view,
                                              REGSET_VSX,
-                                             0, (32 * sizeof(vector128) +
-                                                 sizeof(u32)),
+                                             0, 32 * sizeof(double),
                                              (const void __user *) data);
 #endif
 #ifdef CONFIG_SPE
@@ -1013,31 +1013,24 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         return ret;
 }
 
-static void do_syscall_trace(void)
+/*
+ * We must return the syscall number to actually look up in the table.
+ * This can be -1L to skip running any syscall at all.
+ */
+long do_syscall_trace_enter(struct pt_regs *regs)
 {
-        /* the 0x80 provides a way for the tracing parent to distinguish
-           between a syscall stop and SIGTRAP delivery */
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                 ? 0x80 : 0));
-
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
-        }
-}
+        long ret = 0;
 
-void do_syscall_trace_enter(struct pt_regs *regs)
-{
         secure_computing(regs->gpr[0]);
 
-        if (test_thread_flag(TIF_SYSCALL_TRACE)
-            && (current->ptrace & PT_PTRACED))
-                do_syscall_trace();
+        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
+            tracehook_report_syscall_entry(regs))
+                /*
+                 * Tracing decided this syscall should not happen.
+                 * We'll return a bogus call number to get an ENOSYS
+                 * error, but leave the original number in regs->gpr[0].
+                 */
+                ret = -1L;
 
         if (unlikely(current->audit_context)) {
 #ifdef CONFIG_PPC64
@@ -1055,16 +1048,19 @@ void do_syscall_trace_enter(struct pt_regs *regs)
                                             regs->gpr[5] & 0xffffffff,
                                             regs->gpr[6] & 0xffffffff);
         }
+
+        return ret ?: regs->gpr[0];
 }
 
 void do_syscall_trace_leave(struct pt_regs *regs)
 {
+        int step;
+
         if (unlikely(current->audit_context))
                 audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
                                    regs->result);
 
-        if ((test_thread_flag(TIF_SYSCALL_TRACE)
-             || test_thread_flag(TIF_SINGLESTEP))
-            && (current->ptrace & PT_PTRACED))
-                do_syscall_trace();
+        step = test_thread_flag(TIF_SINGLESTEP);
+        if (step || test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, step);
 }
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c
index 67bf1a1e7e14..197d49c790ad 100644
--- a/arch/powerpc/kernel/ptrace32.c
+++ b/arch/powerpc/kernel/ptrace32.c
@@ -294,6 +294,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
         case PTRACE_SETFPREGS:
         case PTRACE_GETVRREGS:
         case PTRACE_SETVRREGS:
+        case PTRACE_GETVSRREGS:
+        case PTRACE_SETVSRREGS:
         case PTRACE_GETREGS64:
         case PTRACE_SETREGS64:
         case PPC_PTRACE_GETFPREGS:
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 61a3f4132087..9cc5a52711e5 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -367,7 +367,6 @@ static void __init cpu_init_thread_core_maps(int tpc)
  * setup_cpu_maps - initialize the following cpu maps:
  *                  cpu_possible_map
  *                  cpu_present_map
- *                  cpu_sibling_map
  *
  * Having the possible map set up early allows us to restrict allocations
  * of things like irqstacks to num_possible_cpus() rather than NR_CPUS.
@@ -475,29 +474,6 @@ void __init smp_setup_cpu_maps(void)
          */
         cpu_init_thread_core_maps(nthreads);
 }
-
-/*
- * Being that cpu_sibling_map is now a per_cpu array, then it cannot
- * be initialized until the per_cpu areas have been created.  This
- * function is now called from setup_per_cpu_areas().
- */
-void __init smp_setup_cpu_sibling_map(void)
-{
-#ifdef CONFIG_PPC64
-        int i, cpu, base;
-
-        for_each_possible_cpu(cpu) {
-                DBG("Sibling map for CPU %d:", cpu);
-                base = cpu_first_thread_in_core(cpu);
-                for (i = 0; i < threads_per_core; i++) {
-                        cpu_set(base + i, per_cpu(cpu_sibling_map, cpu));
-                        DBG(" %d", base + i);
-                }
-                DBG("\n");
-        }
-
-#endif /* CONFIG_PPC64 */
-}
 #endif /* CONFIG_SMP */
 
 #ifdef CONFIG_PCSPKR_PLATFORM
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 04d8de9f0fc6..8b25f51f03bf 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -611,9 +611,6 @@ void __init setup_per_cpu_areas(void)
                 paca[i].data_offset = ptr - __per_cpu_start;
                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
         }
-
-        /* Now that per_cpu is setup, initialize cpu_sibling_map */
-        smp_setup_cpu_sibling_map();
 }
 #endif
 
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 7aada783ec6a..a54405ebd7b0 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -9,7 +9,7 @@
  * this archive for more details.
  */
 
-#include <linux/ptrace.h>
+#include <linux/tracehook.h>
 #include <linux/signal.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
@@ -112,7 +112,7 @@ static void check_syscall_restart(struct pt_regs *regs, struct k_sigaction *ka,
         }
 }
 
-int do_signal(sigset_t *oldset, struct pt_regs *regs)
+static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
 {
         siginfo_t info;
         int signr;
@@ -147,7 +147,7 @@ int do_signal(sigset_t *oldset, struct pt_regs *regs)
          */
         if (current->thread.dabr) {
                 set_dabr(current->thread.dabr);
-#if defined(CONFIG_44x) || defined(CONFIG_BOOKE)
+#if defined(CONFIG_BOOKE)
                 mtspr(SPRN_DBCR0, current->thread.dbcr0);
 #endif
         }
@@ -177,11 +177,28 @@ int do_signal(sigset_t *oldset, struct pt_regs *regs)
                  * its frame, and we can clear the TLF_RESTORE_SIGMASK flag.
                  */
                 current_thread_info()->local_flags &= ~_TLF_RESTORE_SIGMASK;
+
+                /*
+                 * Let tracing know that we've done the handler setup.
+                 */
+                tracehook_signal_handler(signr, &info, &ka, regs,
+                                         test_thread_flag(TIF_SINGLESTEP));
         }
 
         return ret;
 }
 
+void do_signal(struct pt_regs *regs, unsigned long thread_info_flags)
+{
+        if (thread_info_flags & _TIF_SIGPENDING)
+                do_signal_pending(NULL, regs);
+
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+        }
+}
+
 long sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
                 unsigned long r5, unsigned long r6, unsigned long r7,
                 unsigned long r8, struct pt_regs *regs)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index f5ae9fa222ea..5337ca7bb649 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -41,6 +41,7 @@
 #include <asm/smp.h>
 #include <asm/time.h>
 #include <asm/machdep.h>
+#include <asm/cputhreads.h>
 #include <asm/cputable.h>
 #include <asm/system.h>
 #include <asm/mpic.h>
@@ -62,10 +63,12 @@ struct thread_info *secondary_ti;
 cpumask_t cpu_possible_map = CPU_MASK_NONE;
 cpumask_t cpu_online_map = CPU_MASK_NONE;
 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
+DEFINE_PER_CPU(cpumask_t, cpu_core_map) = CPU_MASK_NONE;
 
 EXPORT_SYMBOL(cpu_online_map);
 EXPORT_SYMBOL(cpu_possible_map);
 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
+EXPORT_PER_CPU_SYMBOL(cpu_core_map);
 
 /* SMP operations for this machine */
 struct smp_ops_t *smp_ops;
@@ -228,6 +231,8 @@ void __devinit smp_prepare_boot_cpu(void)
         BUG_ON(smp_processor_id() != boot_cpuid);
 
         cpu_set(boot_cpuid, cpu_online_map);
+        cpu_set(boot_cpuid, per_cpu(cpu_sibling_map, boot_cpuid));
+        cpu_set(boot_cpuid, per_cpu(cpu_core_map, boot_cpuid));
 #ifdef CONFIG_PPC64
         paca[boot_cpuid].__current = current;
 #endif
@@ -375,11 +380,60 @@ int __cpuinit __cpu_up(unsigned int cpu)
         return 0;
 }
 
+/* Return the value of the reg property corresponding to the given
+ * logical cpu.
+ */
+int cpu_to_core_id(int cpu)
+{
+        struct device_node *np;
+        const int *reg;
+        int id = -1;
+
+        np = of_get_cpu_node(cpu, NULL);
+        if (!np)
+                goto out;
+
+        reg = of_get_property(np, "reg", NULL);
+        if (!reg)
+                goto out;
+
+        id = *reg;
+out:
+        of_node_put(np);
+        return id;
+}
+
+/* Must be called when no change can occur to cpu_present_map,
+ * i.e. during cpu online or offline.
+ */
+static struct device_node *cpu_to_l2cache(int cpu)
+{
+        struct device_node *np;
+        const phandle *php;
+        phandle ph;
+
+        if (!cpu_present(cpu))
+                return NULL;
+
+        np = of_get_cpu_node(cpu, NULL);
+        if (np == NULL)
+                return NULL;
+
+        php = of_get_property(np, "l2-cache", NULL);
+        if (php == NULL)
+                return NULL;
+        ph = *php;
+        of_node_put(np);
+
+        return of_find_node_by_phandle(ph);
+}
 
 /* Activate a secondary processor. */
 int __devinit start_secondary(void *unused)
 {
         unsigned int cpu = smp_processor_id();
+        struct device_node *l2_cache;
+        int i, base;
 
         atomic_inc(&init_mm.mm_count);
         current->active_mm = &init_mm;
@@ -400,6 +454,33 @@ int __devinit start_secondary(void *unused)
 
         ipi_call_lock();
         cpu_set(cpu, cpu_online_map);
+        /* Update sibling maps */
+        base = cpu_first_thread_in_core(cpu);
+        for (i = 0; i < threads_per_core; i++) {
+                if (cpu_is_offline(base + i))
+                        continue;
+                cpu_set(cpu, per_cpu(cpu_sibling_map, base + i));
+                cpu_set(base + i, per_cpu(cpu_sibling_map, cpu));
+
+                /* cpu_core_map should be a superset of
+                 * cpu_sibling_map even if we don't have cache
+                 * information, so update the former here, too.
+                 */
+                cpu_set(cpu, per_cpu(cpu_core_map, base +i));
+                cpu_set(base + i, per_cpu(cpu_core_map, cpu));
+        }
+        l2_cache = cpu_to_l2cache(cpu);
+        for_each_online_cpu(i) {
+                struct device_node *np = cpu_to_l2cache(i);
+                if (!np)
+                        continue;
+                if (np == l2_cache) {
+                        cpu_set(cpu, per_cpu(cpu_core_map, i));
+                        cpu_set(i, per_cpu(cpu_core_map, cpu));
+                }
+                of_node_put(np);
+        }
+        of_node_put(l2_cache);
         ipi_call_unlock();
 
         local_irq_enable();
@@ -437,10 +518,42 @@ void __init smp_cpus_done(unsigned int max_cpus)
 #ifdef CONFIG_HOTPLUG_CPU
 int __cpu_disable(void)
 {
-        if (smp_ops->cpu_disable)
-                return smp_ops->cpu_disable();
+        struct device_node *l2_cache;
+        int cpu = smp_processor_id();
+        int base, i;
+        int err;
 
-        return -ENOSYS;
+        if (!smp_ops->cpu_disable)
+                return -ENOSYS;
+
+        err = smp_ops->cpu_disable();
+        if (err)
+                return err;
+
+        /* Update sibling maps */
+        base = cpu_first_thread_in_core(cpu);
+        for (i = 0; i < threads_per_core; i++) {
+                cpu_clear(cpu, per_cpu(cpu_sibling_map, base + i));
+                cpu_clear(base + i, per_cpu(cpu_sibling_map, cpu));
+                cpu_clear(cpu, per_cpu(cpu_core_map, base +i));
+                cpu_clear(base + i, per_cpu(cpu_core_map, cpu));
+        }
+
+        l2_cache = cpu_to_l2cache(cpu);
+        for_each_present_cpu(i) {
+                struct device_node *np = cpu_to_l2cache(i);
+                if (!np)
+                        continue;
+                if (np == l2_cache) {
+                        cpu_clear(cpu, per_cpu(cpu_core_map, i));
+                        cpu_clear(i, per_cpu(cpu_core_map, cpu));
+                }
+                of_node_put(np);
+        }
+        of_node_put(l2_cache);
+
+
+        return 0;
 }
 
 void __cpu_die(unsigned int cpu)
diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
index f2589645870a..b0dbb1daa4df 100644
--- a/arch/powerpc/kernel/stacktrace.c
+++ b/arch/powerpc/kernel/stacktrace.c
@@ -13,7 +13,6 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/stacktrace.h>
-#include <linux/module.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 800e5e9a087b..56d172d16e56 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -22,6 +22,8 @@
 
 static DEFINE_PER_CPU(struct cpu, cpu_devices);
 
+static DEFINE_PER_CPU(struct kobject *, cache_toplevel);
+
 /* SMT stuff */
 
 #ifdef CONFIG_PPC_MULTIPLATFORM
@@ -297,8 +299,289 @@ static struct sysdev_attribute pa6t_attrs[] = {
 #endif /* CONFIG_DEBUG_KERNEL */
 };
 
+struct cache_desc {
+        struct kobject kobj;
+        struct cache_desc *next;
+        const char *type;       /* Instruction, Data, or Unified */
+        u32 size;               /* total cache size in KB */
+        u32 line_size;          /* in bytes */
+        u32 nr_sets;            /* number of sets */
+        u32 level;              /* e.g. 1, 2, 3... */
+        u32 associativity;      /* e.g. 8-way... 0 is fully associative */
+};
+
+DEFINE_PER_CPU(struct cache_desc *, cache_desc);
+
+static struct cache_desc *kobj_to_cache_desc(struct kobject *k)
+{
+        return container_of(k, struct cache_desc, kobj);
+}
+
+static void cache_desc_release(struct kobject *k)
+{
+        struct cache_desc *desc = kobj_to_cache_desc(k);
+
+        pr_debug("%s: releasing %s\n", __func__, kobject_name(k));
+
+        if (desc->next)
+                kobject_put(&desc->next->kobj);
+
+        kfree(kobj_to_cache_desc(k));
+}
+
+static ssize_t cache_desc_show(struct kobject *k, struct attribute *attr, char *buf)
+{
+        struct kobj_attribute *kobj_attr;
+
+        kobj_attr = container_of(attr, struct kobj_attribute, attr);
+
+        return kobj_attr->show(k, kobj_attr, buf);
+}
+
+static struct sysfs_ops cache_desc_sysfs_ops = {
+        .show = cache_desc_show,
+};
+
+static struct kobj_type cache_desc_type = {
+        .release = cache_desc_release,
+        .sysfs_ops = &cache_desc_sysfs_ops,
+};
+
+static ssize_t cache_size_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
+{
+        struct cache_desc *cache = kobj_to_cache_desc(k);
+
+        return sprintf(buf, "%uK\n", cache->size);
+}
+
+static struct kobj_attribute cache_size_attr =
+        __ATTR(size, 0444, cache_size_show, NULL);
+
+static ssize_t cache_line_size_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
+{
+        struct cache_desc *cache = kobj_to_cache_desc(k);
+
+        return sprintf(buf, "%u\n", cache->line_size);
+}
+
+static struct kobj_attribute cache_line_size_attr =
+        __ATTR(coherency_line_size, 0444, cache_line_size_show, NULL);
+
+static ssize_t cache_nr_sets_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
+{
+        struct cache_desc *cache = kobj_to_cache_desc(k);
+
+        return sprintf(buf, "%u\n", cache->nr_sets);
+}
+
+static struct kobj_attribute cache_nr_sets_attr =
+        __ATTR(number_of_sets, 0444, cache_nr_sets_show, NULL);
+
+static ssize_t cache_type_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
+{
+        struct cache_desc *cache = kobj_to_cache_desc(k);
+
+        return sprintf(buf, "%s\n", cache->type);
+}
+
+static struct kobj_attribute cache_type_attr =
+        __ATTR(type, 0444, cache_type_show, NULL);
+
+static ssize_t cache_level_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
+{
+        struct cache_desc *cache = kobj_to_cache_desc(k);
+
+        return sprintf(buf, "%u\n", cache->level);
+}
+
+static struct kobj_attribute cache_level_attr =
+        __ATTR(level, 0444, cache_level_show, NULL);
+
+static ssize_t cache_assoc_show(struct kobject *k, struct kobj_attribute *attr, char *buf)
+{
+        struct cache_desc *cache = kobj_to_cache_desc(k);
+
+        return sprintf(buf, "%u\n", cache->associativity);
+}
+
+static struct kobj_attribute cache_assoc_attr =
+        __ATTR(ways_of_associativity, 0444, cache_assoc_show, NULL);
+
+struct cache_desc_info {
+        const char *type;
+        const char *size_prop;
+        const char *line_size_prop;
+        const char *nr_sets_prop;
+};
+
+/* PowerPC Processor binding says the [di]-cache-* must be equal on
+ * unified caches, so just use d-cache properties. */
+static struct cache_desc_info ucache_info = {
+        .type = "Unified",
+        .size_prop = "d-cache-size",
+        .line_size_prop = "d-cache-line-size",
+        .nr_sets_prop = "d-cache-sets",
+};
 
-static void register_cpu_online(unsigned int cpu)
+static struct cache_desc_info dcache_info = {
+        .type = "Data",
+        .size_prop = "d-cache-size",
+        .line_size_prop = "d-cache-line-size",
+        .nr_sets_prop = "d-cache-sets",
+};
+
+static struct cache_desc_info icache_info = {
+        .type = "Instruction",
+        .size_prop = "i-cache-size",
+        .line_size_prop = "i-cache-line-size",
+        .nr_sets_prop = "i-cache-sets",
+};
+
+static struct cache_desc * __cpuinit create_cache_desc(struct device_node *np, struct kobject *parent, int index, int level, struct cache_desc_info *info)
+{
+        const u32 *cache_line_size;
+        struct cache_desc *new;
+        const u32 *cache_size;
+        const u32 *nr_sets;
+        int rc;
+
+        new = kzalloc(sizeof(*new), GFP_KERNEL);
+        if (!new)
+                return NULL;
+
+        rc = kobject_init_and_add(&new->kobj, &cache_desc_type, parent,
+                                  "index%d", index);
+        if (rc)
+                goto err;
+
+        /* type */
+        new->type = info->type;
+        rc = sysfs_create_file(&new->kobj, &cache_type_attr.attr);
+        WARN_ON(rc);
+
+        /* level */
+        new->level = level;
+        rc = sysfs_create_file(&new->kobj, &cache_level_attr.attr);
+        WARN_ON(rc);
+
+        /* size */
+        cache_size = of_get_property(np, info->size_prop, NULL);
+        if (cache_size) {
+                new->size = *cache_size / 1024;
+                rc = sysfs_create_file(&new->kobj,
+                                       &cache_size_attr.attr);
+                WARN_ON(rc);
+        }
+
+        /* coherency_line_size */
+        cache_line_size = of_get_property(np, info->line_size_prop, NULL);
+        if (cache_line_size) {
+                new->line_size = *cache_line_size;
+                rc = sysfs_create_file(&new->kobj,
+                                       &cache_line_size_attr.attr);
+                WARN_ON(rc);
+        }
+
+        /* number_of_sets */
+        nr_sets = of_get_property(np, info->nr_sets_prop, NULL);
+        if (nr_sets) {
+                new->nr_sets = *nr_sets;
+                rc = sysfs_create_file(&new->kobj,
+                                       &cache_nr_sets_attr.attr);
+                WARN_ON(rc);
+        }
+
+        /* ways_of_associativity */
+        if (new->nr_sets == 1) {
+                /* fully associative */
+                new->associativity = 0;
+                goto create_assoc;
+        }
+
+        if (new->nr_sets && new->size && new->line_size) {
+                /* If we have values for all of these we can derive
+                 * the associativity. */
+                new->associativity =
+                        ((new->size * 1024) / new->nr_sets) / new->line_size;
+create_assoc:
+                rc = sysfs_create_file(&new->kobj,
+                                       &cache_assoc_attr.attr);
+                WARN_ON(rc);
+        }
+
+        return new;
+err:
+        kfree(new);
+        return NULL;
+}
+
+static bool cache_is_unified(struct device_node *np)
+{
+        return of_get_property(np, "cache-unified", NULL);
+}
+
+static struct cache_desc * __cpuinit create_cache_index_info(struct device_node *np, struct kobject *parent, int index, int level)
+{
+        const phandle *next_cache_phandle;
+        struct device_node *next_cache;
+        struct cache_desc *new, **end;
+
+        pr_debug("%s(node = %s, index = %d)\n", __func__, np->full_name, index);
+
+        if (cache_is_unified(np)) {
+                new = create_cache_desc(np, parent, index, level,
+                                        &ucache_info);
+        } else {
+                new = create_cache_desc(np, parent, index, level,
+                                        &dcache_info);
+                if (new) {
+                        index++;
+                        new->next = create_cache_desc(np, parent, index, level,
+                                                      &icache_info);
+                }
+        }
+        if (!new)
+                return NULL;
+
+        end = &new->next;
+        while (*end)
+                end = &(*end)->next;
+
+        next_cache_phandle = of_get_property(np, "l2-cache", NULL);
+        if (!next_cache_phandle)
+                goto out;
+
+        next_cache = of_find_node_by_phandle(*next_cache_phandle);
+        if (!next_cache)
+                goto out;
+
+        *end = create_cache_index_info(next_cache, parent, ++index, ++level);
+
+        of_node_put(next_cache);
+out:
+        return new;
+}
+
+static void __cpuinit create_cache_info(struct sys_device *sysdev)
+{
+        struct kobject *cache_toplevel;
+        struct device_node *np = NULL;
+        int cpu = sysdev->id;
+
+        cache_toplevel = kobject_create_and_add("cache", &sysdev->kobj);
+        if (!cache_toplevel)
+                return;
+        per_cpu(cache_toplevel, cpu) = cache_toplevel;
+        np = of_get_cpu_node(cpu, NULL);
+        if (np != NULL) {
+                per_cpu(cache_desc, cpu) =
+                        create_cache_index_info(np, cache_toplevel, 0, 1);
+                of_node_put(np);
+        }
+        return;
+}
+
+static void __cpuinit register_cpu_online(unsigned int cpu)
 {
         struct cpu *c = &per_cpu(cpu_devices, cpu);
         struct sys_device *s = &c->sysdev;
@@ -346,9 +629,33 @@ static void register_cpu_online(unsigned int cpu)
 
         if (cpu_has_feature(CPU_FTR_DSCR))
                 sysdev_create_file(s, &attr_dscr);
+
+        create_cache_info(s);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
+static void remove_cache_info(struct sys_device *sysdev)
+{
+        struct kobject *cache_toplevel;
+        struct cache_desc *cache_desc;
+        int cpu = sysdev->id;
+
+        cache_desc = per_cpu(cache_desc, cpu);
+        if (cache_desc != NULL) {
+                sysfs_remove_file(&cache_desc->kobj, &cache_size_attr.attr);
+                sysfs_remove_file(&cache_desc->kobj, &cache_line_size_attr.attr);
+                sysfs_remove_file(&cache_desc->kobj, &cache_type_attr.attr);
+                sysfs_remove_file(&cache_desc->kobj, &cache_level_attr.attr);
+                sysfs_remove_file(&cache_desc->kobj, &cache_nr_sets_attr.attr);
+                sysfs_remove_file(&cache_desc->kobj, &cache_assoc_attr.attr);
+
+                kobject_put(&cache_desc->kobj);
+        }
+        cache_toplevel = per_cpu(cache_toplevel, cpu);
+        if (cache_toplevel != NULL)
+                kobject_put(cache_toplevel);
+}
+
 static void unregister_cpu_online(unsigned int cpu)
 {
         struct cpu *c = &per_cpu(cpu_devices, cpu);
@@ -399,6 +706,8 @@ static void unregister_cpu_online(unsigned int cpu)
 
         if (cpu_has_feature(CPU_FTR_DSCR))
                 sysdev_remove_file(s, &attr_dscr);
+
+        remove_cache_info(s);
 }
 #endif /* CONFIG_HOTPLUG_CPU */
 
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index f177c60ea766..65639a43e644 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -788,9 +788,7 @@ static int __init vdso_init(void)
 
         return 0;
 }
-#ifdef CONFIG_PPC_MERGE
 arch_initcall(vdso_init);
-#endif
 
 int in_gate_area_no_task(unsigned long addr)
 {
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index ade8aeaa2e70..22a3c33fd751 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -530,7 +530,7 @@ static dma_addr_t vio_dma_iommu_map_single(struct device *dev, void *vaddr,
         }
 
         ret = dma_iommu_ops.map_single(dev, vaddr, size, direction, attrs);
-        if (unlikely(dma_mapping_error(ret))) {
+        if (unlikely(dma_mapping_error(dev, ret))) {
                 vio_cmo_dealloc(viodev, roundup(size, IOMMU_PAGE_SIZE));
                 atomic_inc(&viodev->cmo.allocs_failed);
         }
@@ -1031,8 +1031,8 @@ void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired) {}
 static int vio_cmo_bus_probe(struct vio_dev *viodev) { return 0; }
 static void vio_cmo_bus_remove(struct vio_dev *viodev) {}
 static void vio_cmo_set_dma_ops(struct vio_dev *viodev) {}
-static void vio_cmo_bus_init() {}
-static void vio_cmo_sysfs_init() { }
+static void vio_cmo_bus_init(void) {}
+static void vio_cmo_sysfs_init(void) { }
 #endif /* CONFIG_PPC_SMLPAR */
 EXPORT_SYMBOL(vio_cmo_entitlement_update);
 EXPORT_SYMBOL(vio_cmo_set_dev_desired);
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 2a88e8b9a3c6..d69912c07ce7 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -6,12 +6,10 @@ ifeq ($(CONFIG_PPC64),y)
 EXTRA_CFLAGS            += -mno-minimal-toc
 endif
 
-ifeq ($(CONFIG_PPC_MERGE),y)
 obj-y                   := string.o alloc.o \
                            checksum_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_PPC32)     += div64.o copy_32.o crtsavres.o
 obj-$(CONFIG_HAS_IOMEM) += devres.o
-endif
 
 obj-$(CONFIG_PPC64)     += copypage_64.o copyuser_64.o \
                            memcpy_64.o usercopy_64.o mem_64.o string.o
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 1c00e0196f6c..e7392b45a5ef 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -12,7 +12,8 @@ obj-y				:= fault.o mem.o \
                                    mmu_context_$(CONFIG_WORD_SIZE).o
 hash-$(CONFIG_PPC_NATIVE)       := hash_native_64.o
 obj-$(CONFIG_PPC64)             += hash_utils_64.o \
-                                   slb_low.o slb.o stab.o mmap.o $(hash-y)
+                                   slb_low.o slb.o stab.o \
+                                   gup.o mmap.o $(hash-y)
 obj-$(CONFIG_PPC_STD_MMU_32)    += ppc_mmu_32.o
 obj-$(CONFIG_PPC_STD_MMU)       += hash_low_$(CONFIG_WORD_SIZE).o \
                                    tlb_$(CONFIG_WORD_SIZE).o
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
new file mode 100644
index 000000000000..9fdf4d6335e4
--- /dev/null
+++ b/arch/powerpc/mm/gup.c
@@ -0,0 +1,280 @@
+/*
+ * Lockless get_user_pages_fast for powerpc
+ *
+ * Copyright (C) 2008 Nick Piggin
+ * Copyright (C) 2008 Novell Inc.
+ */
+#undef DEBUG
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/vmstat.h>
+#include <linux/pagemap.h>
+#include <linux/rwsem.h>
+#include <asm/pgtable.h>
+
+/*
+ * The performance critical leaf functions are made noinline otherwise gcc
+ * inlines everything into a single function which results in too much
+ * register pressure.
+ */
+static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
+                unsigned long end, int write, struct page **pages, int *nr)
+{
+        unsigned long mask, result;
+        pte_t *ptep;
+
+        result = _PAGE_PRESENT|_PAGE_USER;
+        if (write)
+                result |= _PAGE_RW;
+        mask = result | _PAGE_SPECIAL;
+
+        ptep = pte_offset_kernel(&pmd, addr);
+        do {
+                pte_t pte = *ptep;
+                struct page *page;
+
+                if ((pte_val(pte) & mask) != result)
+                        return 0;
+                VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+                page = pte_page(pte);
+                if (!page_cache_get_speculative(page))
+                        return 0;
+                if (unlikely(pte != *ptep)) {
+                        put_page(page);
+                        return 0;
+                }
+                pages[*nr] = page;
+                (*nr)++;
+
+        } while (ptep++, addr += PAGE_SIZE, addr != end);
+
+        return 1;
+}
+
+#ifdef CONFIG_HUGETLB_PAGE
+static noinline int gup_huge_pte(pte_t *ptep, struct hstate *hstate,
+                                 unsigned long *addr, unsigned long end,
+                                 int write, struct page **pages, int *nr)
+{
+        unsigned long mask;
+        unsigned long pte_end;
+        struct page *head, *page;
+        pte_t pte;
+        int refs;
+
+        pte_end = (*addr + huge_page_size(hstate)) & huge_page_mask(hstate);
+        if (pte_end < end)
+                end = pte_end;
+
+        pte = *ptep;
+        mask = _PAGE_PRESENT|_PAGE_USER;
+        if (write)
+                mask |= _PAGE_RW;
+        if ((pte_val(pte) & mask) != mask)
+                return 0;
+        /* hugepages are never "special" */
+        VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+
+        refs = 0;
+        head = pte_page(pte);
+        page = head + ((*addr & ~huge_page_mask(hstate)) >> PAGE_SHIFT);
+        do {
+                VM_BUG_ON(compound_head(page) != head);
+                pages[*nr] = page;
+                (*nr)++;
+                page++;
+                refs++;
+        } while (*addr += PAGE_SIZE, *addr != end);
+
+        if (!page_cache_add_speculative(head, refs)) {
+                *nr -= refs;
+                return 0;
+        }
+        if (unlikely(pte != *ptep)) {
+                /* Could be optimized better */
+                while (*nr) {
+                        put_page(page);
+                        (*nr)--;
+                }
+        }
+
+        return 1;
+}
+#endif /* CONFIG_HUGETLB_PAGE */
+
+static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
+                int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pmd_t *pmdp;
+
+        pmdp = pmd_offset(&pud, addr);
+        do {
+                pmd_t pmd = *pmdp;
+
+                next = pmd_addr_end(addr, end);
+                if (pmd_none(pmd))
+                        return 0;
+                if (!gup_pte_range(pmd, addr, next, write, pages, nr))
+                        return 0;
+        } while (pmdp++, addr = next, addr != end);
+
+        return 1;
+}
+
+static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
+                int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pud_t *pudp;
+
+        pudp = pud_offset(&pgd, addr);
+        do {
+                pud_t pud = *pudp;
+
+                next = pud_addr_end(addr, end);
+                if (pud_none(pud))
+                        return 0;
+                if (!gup_pmd_range(pud, addr, next, write, pages, nr))
+                        return 0;
+        } while (pudp++, addr = next, addr != end);
+
+        return 1;
+}
+
+int get_user_pages_fast(unsigned long start, int nr_pages, int write,
+                        struct page **pages)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr, len, end;
+        unsigned long next;
+        pgd_t *pgdp;
+        int psize, nr = 0;
+        unsigned int shift;
+
+        pr_debug("%s(%lx,%x,%s)\n", __func__, start, nr_pages, write ? "write" : "read");
+
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+        end = start + len;
+
+        if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
+                                        start, len)))
+                goto slow_irqon;
+
+        pr_debug("  aligned: %lx .. %lx\n", start, end);
+
+#ifdef CONFIG_HUGETLB_PAGE
+        /* We bail out on slice boundary crossing when hugetlb is
+         * enabled in order to not have to deal with two different
+         * page table formats
+         */
+        if (addr < SLICE_LOW_TOP) {
+                if (end > SLICE_LOW_TOP)
+                        goto slow_irqon;
+
+                if (unlikely(GET_LOW_SLICE_INDEX(addr) !=
+                             GET_LOW_SLICE_INDEX(end - 1)))
+                        goto slow_irqon;
+        } else {
+                if (unlikely(GET_HIGH_SLICE_INDEX(addr) !=
+                             GET_HIGH_SLICE_INDEX(end - 1)))
+                        goto slow_irqon;
+        }
+#endif /* CONFIG_HUGETLB_PAGE */
+
+        /*
+         * XXX: batch / limit 'nr', to avoid large irq off latency
+         * needs some instrumenting to determine the common sizes used by
+         * important workloads (eg. DB2), and whether limiting the batch size
+         * will decrease performance.
+         *
+         * It seems like we're in the clear for the moment. Direct-IO is
+         * the main guy that batches up lots of get_user_pages, and even
+         * they are limited to 64-at-a-time which is not so many.
+         */
+        /*
+         * This doesn't prevent pagetable teardown, but does prevent
+         * the pagetables from being freed on powerpc.
+         *
+         * So long as we atomically load page table pointers versus teardown,
+         * we can follow the address down to the the page and take a ref on it.
+         */
+        local_irq_disable();
+
+        psize = get_slice_psize(mm, addr);
+        shift = mmu_psize_defs[psize].shift;
+
+#ifdef CONFIG_HUGETLB_PAGE
+        if (unlikely(mmu_huge_psizes[psize])) {
+                pte_t *ptep;
+                unsigned long a = addr;
+                unsigned long sz = ((1UL) << shift);
+                struct hstate *hstate = size_to_hstate(sz);
+
+                BUG_ON(!hstate);
+                /*
+                 * XXX: could be optimized to avoid hstate
+                 * lookup entirely (just use shift)
+                 */
+
+                do {
+                        VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, a)].shift);
+                        ptep = huge_pte_offset(mm, a);
+                        pr_debug(" %016lx: huge ptep %p\n", a, ptep);
+                        if (!ptep || !gup_huge_pte(ptep, hstate, &a, end, write, pages,
+                                                   &nr))
+                                goto slow;
+                } while (a != end);
+        } else
+#endif /* CONFIG_HUGETLB_PAGE */
+        {
+                pgdp = pgd_offset(mm, addr);
+                do {
+                        pgd_t pgd = *pgdp;
+
+                        VM_BUG_ON(shift != mmu_psize_defs[get_slice_psize(mm, addr)].shift);
+                        pr_debug("  %016lx: normal pgd %p\n", addr, (void *)pgd);
+                        next = pgd_addr_end(addr, end);
+                        if (pgd_none(pgd))
+                                goto slow;
+                        if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                                goto slow;
+                } while (pgdp++, addr = next, addr != end);
+        }
+        local_irq_enable();
+
+        VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT);
+        return nr;
+
+        {
+                int ret;
+
+slow:
+                local_irq_enable();
+slow_irqon:
+                pr_debug("  slow path ! nr = %d\n", nr);
+
+                /* Try to get the remaining pages with get_user_pages */
+                start += nr << PAGE_SHIFT;
+                pages += nr;
+
+                down_read(&mm->mmap_sem);
+                ret = get_user_pages(current, mm, start,
+                        (end - start) >> PAGE_SHIFT, write, 0, pages, NULL);
+                up_read(&mm->mmap_sem);
+
+                /* Have to be a bit careful with return values */
+                if (nr > 0) {
+                        if (ret < 0)
+                                ret = nr;
+                        else
+                                ret += nr;
+                }
+
+                return ret;
+        }
+}
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index ed0aab0208a6..f1c2d55b4377 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -736,14 +736,21 @@ static int __init hugetlbpage_init(void)
 
         if (!cpu_has_feature(CPU_FTR_16M_PAGE))
                 return -ENODEV;
+
         /* Add supported huge page sizes.  Need to change HUGE_MAX_HSTATE
          * and adjust PTE_NONCACHE_NUM if the number of supported huge page
          * sizes changes.
          */
         set_huge_psize(MMU_PAGE_16M);
-        set_huge_psize(MMU_PAGE_64K);
         set_huge_psize(MMU_PAGE_16G);
 
+        /* Temporarily disable support for 64K huge pages when 64K SPU local
+         * store support is enabled as the current implementation conflicts.
+         */
+#ifndef CONFIG_SPU_FS_64K_LS
+        set_huge_psize(MMU_PAGE_64K);
+#endif
+
         for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
                 if (mmu_huge_psizes[psize]) {
                         huge_pgtable_cache(psize) = kmem_cache_create(
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 702691cb9e82..1c93c255873b 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -311,7 +311,7 @@ void __init paging_init(void)
 #endif /* CONFIG_HIGHMEM */
 
         printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%lx\n",
-               (u64)top_of_ram, total_ram);
+               (unsigned long long)top_of_ram, total_ram);
         printk(KERN_DEBUG "Memory hole size: %ldMB\n",
                (long int)((top_of_ram - total_ram) >> 20));
         memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index c53145f61942..6aa120813775 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -236,8 +236,8 @@ void __init MMU_init_hw(void)
 
         Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
 
-        printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n",
-               total_memory >> 20, Hash_size >> 10, Hash);
+        printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
+               (unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
 
 
         /*
diff --git a/arch/powerpc/mm/tlb_64.c b/arch/powerpc/mm/tlb_64.c
index 409fcc7b63ce..be7dd422c0fa 100644
--- a/arch/powerpc/mm/tlb_64.c
+++ b/arch/powerpc/mm/tlb_64.c
@@ -34,7 +34,7 @@
 DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 
 /* This is declared as we are using the more or less generic
- * include/asm-powerpc/tlb.h file -- tgall
+ * arch/powerpc/include/asm/tlb.h file -- tgall
  */
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile
index daf0e1568d6d..b8a52062738a 100644
--- a/arch/powerpc/platforms/52xx/Makefile
+++ b/arch/powerpc/platforms/52xx/Makefile
@@ -1,10 +1,8 @@
 #
 # Makefile for 52xx based boards
 #
-ifeq ($(CONFIG_PPC_MERGE),y)
 obj-y                           += mpc52xx_pic.o mpc52xx_common.o
 obj-$(CONFIG_PCI)               += mpc52xx_pci.o
-endif
 
 obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o
 obj-$(CONFIG_PPC_EFIKA)         += efika.o
@@ -15,4 +13,4 @@ ifeq ($(CONFIG_PPC_LITE5200),y)
         obj-$(CONFIG_PM)        += lite5200_sleep.o lite5200_pm.o
 endif
 
-obj-$(CONFIG_PPC_MPC5200_GPIO)  += mpc52xx_gpio.o
\ No newline at end of file
+obj-$(CONFIG_PPC_MPC5200_GPIO)  += mpc52xx_gpio.o
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index dd4be4aee314..ec43477caa63 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -105,6 +105,7 @@ static void __init mpc832x_sys_setup_arch(void)
 static struct of_device_id mpc832x_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         { .type = "qe", },
         { .compatible = "fsl,qe", },
         {},
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index f049d692d4c8..0300268ce5b8 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -115,6 +115,7 @@ static void __init mpc832x_rdb_setup_arch(void)
 static struct of_device_id mpc832x_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         { .type = "qe", },
         { .compatible = "fsl,qe", },
         {},
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index 7301d77a08ee..76092d37c7d9 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -41,6 +41,7 @@
 
 static struct of_device_id __initdata mpc834x_itx_ids[] = {
         { .compatible = "fsl,pq2pro-localbus", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/83xx/mpc834x_mds.c b/arch/powerpc/platforms/83xx/mpc834x_mds.c
index 30d509aa9f08..fc3f2ed1f3e9 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_mds.c
@@ -111,6 +111,7 @@ static void __init mpc834x_mds_init_IRQ(void)
 static struct of_device_id mpc834x_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 75b80e836576..9d46e5bdd101 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -136,6 +136,7 @@ static void __init mpc836x_mds_setup_arch(void)
 static struct of_device_id mpc836x_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         { .type = "qe", },
         { .compatible = "fsl,qe", },
         {},
diff --git a/arch/powerpc/platforms/83xx/sbc834x.c b/arch/powerpc/platforms/83xx/sbc834x.c
index fc21f5c15bab..156c4e218009 100644
--- a/arch/powerpc/platforms/83xx/sbc834x.c
+++ b/arch/powerpc/platforms/83xx/sbc834x.c
@@ -83,6 +83,7 @@ static void __init sbc834x_init_IRQ(void)
 static struct __initdata of_device_id sbc834x_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
index 2145adeb220c..8a3b117b6ce2 100644
--- a/arch/powerpc/platforms/85xx/ksi8560.c
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -222,6 +222,7 @@ static void ksi8560_show_cpuinfo(struct seq_file *m)
 
 static struct of_device_id __initdata of_bus_ids[] = {
         { .type = "soc", },
+        { .type = "simple-bus", },
         { .name = "cpm", },
         { .name = "localbus", },
         {},
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 6b846aa1ced9..1bf5aefdfeb1 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -91,6 +91,7 @@ static void __init mpc8536_ds_setup_arch(void)
 static struct of_device_id __initdata mpc8536_ds_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index ba498d6f2d02..d17807a6b89a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -230,6 +230,7 @@ static struct of_device_id __initdata of_bus_ids[] = {
         { .type = "soc", },
         { .name = "cpm", },
         { .name = "localbus", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 00c535806647..483b65cbabae 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -186,6 +186,7 @@ static int __init mpc8544_ds_probe(void)
 static struct of_device_id __initdata mpc85xxds_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 43a459f63e31..2494c5155919 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -260,6 +260,7 @@ machine_arch_initcall(mpc85xx_mds, board_fixups);
 static struct of_device_id mpc85xx_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
+        { .compatible = "simple-bus", },
         { .type = "qe", },
         { .compatible = "fsl,qe", },
         {},
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index 2c580cd24e4f..6509ade71668 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -217,6 +217,7 @@ static struct of_device_id __initdata of_bus_ids[] = {
         { .type = "soc", },
         { .name = "cpm", },
         { .name = "localbus", },
+        { .compatible = "simple-bus", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
index 835f2dc24dc9..014e26cda08d 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
@@ -19,7 +19,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/pci-bridge.h>
-#include <asm-powerpc/mpic.h>
+#include <asm/mpic.h>
 #include <asm/mpc86xx.h>
 #include <asm/cacheflush.h>
 
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 6fc849e51e48..71d7562e190b 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -105,6 +105,16 @@ config 8xx_COPYBACK
 
           If in doubt, say Y here.
 
+config 8xx_GPIO
+        bool "GPIO API Support"
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Saying Y here will cause the ports on an MPC8xx processor to be used
+          with the GPIO API.  If you say N here, the kernel needs less memory.
+
+          If in doubt, say Y here.
+
 config 8xx_CPU6
         bool "CPU6 Silicon Errata (860 Pre Rev. C)"
         help
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 1d0968775c0a..4c900efa164e 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -254,6 +254,8 @@ config CPM2
         select CPM
         select PPC_LIB_RHEAP
         select PPC_PCI_CHOICE
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_GPIO
         help
           The CPM2 (Communications Processor Module) is a coprocessor on
           embedded CPUs made by Freescale.  Selecting this option means that
@@ -281,6 +283,7 @@ config FSL_ULI1575
 
 config CPM
         bool
+        select PPC_CLOCK
 
 config OF_RTC
         bool
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index 423a0234dc31..8079e0b4fd69 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -1,13 +1,7 @@
 
 obj-$(CONFIG_FSL_ULI1575)       += fsl_uli1575.o
 
-ifeq ($(CONFIG_PPC_MERGE),y)
 obj-$(CONFIG_PPC_PMAC)          += powermac/
-else
-ifeq ($(CONFIG_PPC64),y)
-obj-$(CONFIG_PPC_PMAC)          += powermac/
-endif
-endif
 obj-$(CONFIG_PPC_CHRP)          += chrp/
 obj-$(CONFIG_40x)               += 40x/
 obj-$(CONFIG_44x)               += 44x/
diff --git a/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c b/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c
index 69288f653144..3233fe84d158 100644
--- a/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c
+++ b/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c
@@ -96,6 +96,12 @@ static int pmi_notifier(struct notifier_block *nb,
         struct cpufreq_frequency_table *cbe_freqs;
         u8 node;
 
+        /* Should this really be called for CPUFREQ_ADJUST, CPUFREQ_INCOMPATIBLE
+         * and CPUFREQ_NOTIFY policy events?)
+         */
+        if (event == CPUFREQ_START)
+                return 0;
+
         cbe_freqs = cpufreq_frequency_get_table(policy->cpu);
         node = cbe_cpu_to_node(policy->cpu);
 
diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile
index 89774177b209..58ecdd72630f 100644
--- a/arch/powerpc/platforms/powermac/Makefile
+++ b/arch/powerpc/platforms/powermac/Makefile
@@ -7,7 +7,7 @@ endif
 
 obj-y                           += pic.o setup.o time.o feature.o pci.o \
                                    sleep.o low_i2c.o cache.o pfunc_core.o \
-                                   pfunc_base.o
+                                   pfunc_base.o udbg_scc.o udbg_adb.o
 obj-$(CONFIG_PMAC_BACKLIGHT)    += backlight.o
 obj-$(CONFIG_CPU_FREQ_PMAC)     += cpufreq_32.o
 obj-$(CONFIG_CPU_FREQ_PMAC64)   += cpufreq_64.o
@@ -19,4 +19,3 @@ obj-$(CONFIG_NVRAM:m=y)		+= nvram.o
 obj-$(CONFIG_PPC64)             += nvram.o
 obj-$(CONFIG_PPC32)             += bootx_init.o
 obj-$(CONFIG_SMP)               += smp.o
-obj-$(CONFIG_PPC_MERGE)         += udbg_scc.o udbg_adb.o
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 31635446901a..88ccf3a08a9c 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -541,6 +541,78 @@ static int __init pmac_declare_of_platform_devices(void)
 }
 machine_device_initcall(powermac, pmac_declare_of_platform_devices);
 
+#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
+/*
+ * This is called very early, as part of console_init() (typically just after
+ * time_init()). This function is respondible for trying to find a good
+ * default console on serial ports. It tries to match the open firmware
+ * default output with one of the available serial console drivers.
+ */
+static int __init check_pmac_serial_console(void)
+{
+        struct device_node *prom_stdout = NULL;
+        int offset = 0;
+        const char *name;
+#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
+        char *devname = "ttyS";
+#else
+        char *devname = "ttyPZ";
+#endif
+
+        pr_debug(" -> check_pmac_serial_console()\n");
+
+        /* The user has requested a console so this is already set up. */
+        if (strstr(boot_command_line, "console=")) {
+                pr_debug(" console was specified !\n");
+                return -EBUSY;
+        }
+
+        if (!of_chosen) {
+                pr_debug(" of_chosen is NULL !\n");
+                return -ENODEV;
+        }
+
+        /* We are getting a weird phandle from OF ... */
+        /* ... So use the full path instead */
+        name = of_get_property(of_chosen, "linux,stdout-path", NULL);
+        if (name == NULL) {
+                pr_debug(" no linux,stdout-path !\n");
+                return -ENODEV;
+        }
+        prom_stdout = of_find_node_by_path(name);
+        if (!prom_stdout) {
+                pr_debug(" can't find stdout package %s !\n", name);
+                return -ENODEV;
+        }
+        pr_debug("stdout is %s\n", prom_stdout->full_name);
+
+        name = of_get_property(prom_stdout, "name", NULL);
+        if (!name) {
+                pr_debug(" stdout package has no name !\n");
+                goto not_found;
+        }
+
+        if (strcmp(name, "ch-a") == 0)
+                offset = 0;
+        else if (strcmp(name, "ch-b") == 0)
+                offset = 1;
+        else
+                goto not_found;
+        of_node_put(prom_stdout);
+
+        pr_debug("Found serial console at %s%d\n", devname, offset);
+
+        return add_preferred_console(devname, offset, NULL);
+
+ not_found:
+        pr_debug("No preferred console found !\n");
+        of_node_put(prom_stdout);
+        return -ENODEV;
+}
+console_initcall(check_pmac_serial_console);
+
+#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
+
 /*
  * Called very early, MMU is off, device-tree isn't unflattened
  */
diff --git a/arch/powerpc/platforms/powermac/udbg_scc.c b/arch/powerpc/platforms/powermac/udbg_scc.c
index 47de4d3fc167..572771fd8463 100644
--- a/arch/powerpc/platforms/powermac/udbg_scc.c
+++ b/arch/powerpc/platforms/powermac/udbg_scc.c
@@ -125,13 +125,23 @@ void udbg_scc_init(int force_scc)
         out_8(sccc, 0xc0);
 
         /* If SCC was the OF output port, read the BRG value, else
-         * Setup for 57600 8N1
+         * Setup for 38400 or 57600 8N1 depending on the machine
          */
         if (ch_def != NULL) {
                 out_8(sccc, 13);
                 scc_inittab[1] = in_8(sccc);
                 out_8(sccc, 12);
                 scc_inittab[3] = in_8(sccc);
+        } else if (machine_is_compatible("RackMac1,1")
+                   || machine_is_compatible("RackMac1,2")
+                   || machine_is_compatible("MacRISC4")) {
+                /* Xserves and G5s default to 57600 */
+                scc_inittab[1] = 0;
+                scc_inittab[3] = 0;
+        } else {
+                /* Others default to 38400 */
+                scc_inittab[1] = 0;
+                scc_inittab[3] = 1;
         }
 
         for (i = 0; i < sizeof(scc_inittab); ++i)
diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c
index c6b3be03168b..38fe32a7cc70 100644
--- a/arch/powerpc/platforms/pseries/cmm.c
+++ b/arch/powerpc/platforms/pseries/cmm.c
@@ -289,7 +289,9 @@ static int cmm_thread(void *dummy)
 }
 
 #define CMM_SHOW(name, format, args...)                 \
-        static ssize_t show_##name(struct sys_device *dev, char *buf)   \
+        static ssize_t show_##name(struct sys_device *dev,      \
+                                   struct sysdev_attribute *attr,       \
+                                   char *buf)                   \
         {                                                       \
                 return sprintf(buf, format, ##args);            \
         }                                                       \
@@ -298,12 +300,14 @@ static int cmm_thread(void *dummy)
 CMM_SHOW(loaned_kb, "%lu\n", PAGES2KB(loaned_pages));
 CMM_SHOW(loaned_target_kb, "%lu\n", PAGES2KB(loaned_pages_target));
 
-static ssize_t show_oom_pages(struct sys_device *dev, char *buf)
+static ssize_t show_oom_pages(struct sys_device *dev,
+                              struct sysdev_attribute *attr, char *buf)
 {
         return sprintf(buf, "%lu\n", PAGES2KB(oom_freed_pages));
 }
 
 static ssize_t store_oom_pages(struct sys_device *dev,
+                               struct sysdev_attribute *attr,
                                const char *buf, size_t count)
 {
         unsigned long val = simple_strtoul (buf, NULL, 10);
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 16a0ed28eb00..a90054b56d5c 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_MV64X60)		+= $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
 obj-$(CONFIG_RTC_DRV_CMOS)      += rtc_cmos_setup.o
 obj-$(CONFIG_AXON_RAM)          += axonram.o
 
-ifeq ($(CONFIG_PPC_MERGE),y)
 obj-$(CONFIG_PPC_INDIRECT_PCI)  += indirect_pci.o
 obj-$(CONFIG_PPC_I8259)         += i8259.o
 obj-$(CONFIG_IPIC)              += ipic.o
@@ -36,7 +35,6 @@ obj-$(CONFIG_OF_RTC)		+= of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)               += ppc4xx_pci.o
 endif
-endif
 
 # Temporary hack until we have migrated to asm-powerpc
 ifeq ($(ARCH),powerpc)
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 661df42830b9..4a04823e8423 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -30,6 +30,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/module.h>
+#include <linux/spinlock.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/8xx_immap.h>
@@ -42,6 +43,10 @@
 
 #include <asm/fs_pd.h>
 
+#ifdef CONFIG_8xx_GPIO
+#include <linux/of_gpio.h>
+#endif
+
 #define CPM_MAP_SIZE    (0x4000)
 
 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
@@ -290,20 +295,24 @@ struct cpm_ioport16 {
         __be16 res[3];
 };
 
-struct cpm_ioport32 {
-        __be32 dir, par, sor;
+struct cpm_ioport32b {
+        __be32 dir, par, odr, dat;
+};
+
+struct cpm_ioport32e {
+        __be32 dir, par, sor, odr, dat;
 };
 
 static void cpm1_set_pin32(int port, int pin, int flags)
 {
-        struct cpm_ioport32 __iomem *iop;
+        struct cpm_ioport32e __iomem *iop;
         pin = 1 << (31 - pin);
 
         if (port == CPM_PORTB)
-                iop = (struct cpm_ioport32 __iomem *)
+                iop = (struct cpm_ioport32e __iomem *)
                       &mpc8xx_immr->im_cpm.cp_pbdir;
         else
-                iop = (struct cpm_ioport32 __iomem *)
+                iop = (struct cpm_ioport32e __iomem *)
                       &mpc8xx_immr->im_cpm.cp_pedir;
 
         if (flags & CPM_PIN_OUTPUT)
@@ -498,3 +507,251 @@ int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 
         return 0;
 }
+
+/*
+ * GPIO LIB API implementation
+ */
+#ifdef CONFIG_8xx_GPIO
+
+struct cpm1_gpio16_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u16 cpdata;
+};
+
+static inline struct cpm1_gpio16_chip *
+to_cpm1_gpio16_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
+}
+
+static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+
+        cpm1_gc->cpdata = in_be16(&iop->dat);
+}
+
+static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        u16 pin_mask;
+
+        pin_mask = 1 << (15 - gpio);
+
+        return !!(in_be16(&iop->dat) & pin_mask);
+}
+
+static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        unsigned long flags;
+        u16 pin_mask = 1 << (15 - gpio);
+
+        spin_lock_irqsave(&cpm1_gc->lock, flags);
+
+        if (value)
+                cpm1_gc->cpdata |= pin_mask;
+        else
+                cpm1_gc->cpdata &= ~pin_mask;
+
+        out_be16(&iop->dat, cpm1_gc->cpdata);
+
+        spin_unlock_irqrestore(&cpm1_gc->lock, flags);
+}
+
+static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        u16 pin_mask;
+
+        pin_mask = 1 << (15 - gpio);
+
+        setbits16(&iop->dir, pin_mask);
+
+        cpm1_gpio16_set(gc, gpio, val);
+
+        return 0;
+}
+
+static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport16 __iomem *iop = mm_gc->regs;
+        u16 pin_mask;
+
+        pin_mask = 1 << (15 - gpio);
+
+        clrbits16(&iop->dir, pin_mask);
+
+        return 0;
+}
+
+int cpm1_gpiochip_add16(struct device_node *np)
+{
+        struct cpm1_gpio16_chip *cpm1_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct of_gpio_chip *of_gc;
+        struct gpio_chip *gc;
+
+        cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
+        if (!cpm1_gc)
+                return -ENOMEM;
+
+        spin_lock_init(&cpm1_gc->lock);
+
+        mm_gc = &cpm1_gc->mm_gc;
+        of_gc = &mm_gc->of_gc;
+        gc = &of_gc->gc;
+
+        mm_gc->save_regs = cpm1_gpio16_save_regs;
+        of_gc->gpio_cells = 2;
+        gc->ngpio = 16;
+        gc->direction_input = cpm1_gpio16_dir_in;
+        gc->direction_output = cpm1_gpio16_dir_out;
+        gc->get = cpm1_gpio16_get;
+        gc->set = cpm1_gpio16_set;
+
+        return of_mm_gpiochip_add(np, mm_gc);
+}
+
+struct cpm1_gpio32_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u32 cpdata;
+};
+
+static inline struct cpm1_gpio32_chip *
+to_cpm1_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
+}
+
+static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+
+        cpm1_gc->cpdata = in_be32(&iop->dat);
+}
+
+static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        return !!(in_be32(&iop->dat) & pin_mask);
+}
+
+static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        unsigned long flags;
+        u32 pin_mask = 1 << (31 - gpio);
+
+        spin_lock_irqsave(&cpm1_gc->lock, flags);
+
+        if (value)
+                cpm1_gc->cpdata |= pin_mask;
+        else
+                cpm1_gc->cpdata &= ~pin_mask;
+
+        out_be32(&iop->dat, cpm1_gc->cpdata);
+
+        spin_unlock_irqrestore(&cpm1_gc->lock, flags);
+}
+
+static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        setbits32(&iop->dir, pin_mask);
+
+        cpm1_gpio32_set(gc, gpio, val);
+
+        return 0;
+}
+
+static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm_ioport32b __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        clrbits32(&iop->dir, pin_mask);
+
+        return 0;
+}
+
+int cpm1_gpiochip_add32(struct device_node *np)
+{
+        struct cpm1_gpio32_chip *cpm1_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct of_gpio_chip *of_gc;
+        struct gpio_chip *gc;
+
+        cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
+        if (!cpm1_gc)
+                return -ENOMEM;
+
+        spin_lock_init(&cpm1_gc->lock);
+
+        mm_gc = &cpm1_gc->mm_gc;
+        of_gc = &mm_gc->of_gc;
+        gc = &of_gc->gc;
+
+        mm_gc->save_regs = cpm1_gpio32_save_regs;
+        of_gc->gpio_cells = 2;
+        gc->ngpio = 32;
+        gc->direction_input = cpm1_gpio32_dir_in;
+        gc->direction_output = cpm1_gpio32_dir_out;
+        gc->get = cpm1_gpio32_get;
+        gc->set = cpm1_gpio32_set;
+
+        return of_mm_gpiochip_add(np, mm_gc);
+}
+
+static int cpm_init_par_io(void)
+{
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a")
+                cpm1_gpiochip_add16(np);
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b")
+                cpm1_gpiochip_add32(np);
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c")
+                cpm1_gpiochip_add16(np);
+
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d")
+                cpm1_gpiochip_add16(np);
+
+        /* Port E uses CPM2 layout */
+        for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e")
+                cpm2_gpiochip_add32(np);
+        return 0;
+}
+arch_initcall(cpm_init_par_io);
+
+#endif /* CONFIG_8xx_GPIO */
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 5a6c5dfc53ef..f1c3395633b9 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -115,16 +115,10 @@ EXPORT_SYMBOL(cpm_command);
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK     (get_brgfreq())
-#define BRG_UART_CLK    (BRG_INT_CLK/16)
-
-/* This function is used by UARTS, or anything else that uses a 16x
- * oversampled clock.
- */
-void
-cpm_setbrg(uint brg, uint rate)
+void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
 {
         u32 __iomem *bp;
+        u32 val;
 
         /* This is good enough to get SMCs running.....
         */
@@ -135,34 +129,14 @@ cpm_setbrg(uint brg, uint rate)
                 brg -= 4;
         }
         bp += brg;
-        out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
-
-        cpm2_unmap(bp);
-}
-
-/* This function is used to set high speed synchronous baud rate
- * clocks.
- */
-void
-cpm2_fastbrg(uint brg, uint rate, int div16)
-{
-        u32 __iomem *bp;
-        u32 val;
-
-        if (brg < 4) {
-                bp = cpm2_map_size(im_brgc1, 16);
-        } else {
-                bp = cpm2_map_size(im_brgc5, 16);
-                brg -= 4;
-        }
-        bp += brg;
-        val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
+        val = (((clk / rate) - 1) << 1) | CPM_BRG_EN | src;
         if (div16)
                 val |= CPM_BRG_DIV16;
 
         out_be32(bp, val);
         cpm2_unmap(bp);
 }
+EXPORT_SYMBOL(__cpm2_setbrg);
 
 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
 {
@@ -377,3 +351,14 @@ void cpm2_set_pin(int port, int pin, int flags)
         else
                 clrbits32(&iop[port].odr, pin);
 }
+
+static int cpm_init_par_io(void)
+{
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
+                cpm2_gpiochip_add32(np);
+        return 0;
+}
+arch_initcall(cpm_init_par_io);
+
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index e4b7296acb2c..53da8a079f96 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -19,6 +19,8 @@
 
 #include <linux/init.h>
 #include <linux/of_device.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
 
 #include <asm/udbg.h>
 #include <asm/io.h>
@@ -28,6 +30,10 @@
 
 #include <mm/mmu_decl.h>
 
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+#include <linux/of_gpio.h>
+#endif
+
 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
 static u32 __iomem *cpm_udbg_txdesc =
         (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
@@ -207,3 +213,120 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
         return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
 }
 EXPORT_SYMBOL(cpm_muram_dma);
+
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+        u32 dir, par, sor, odr, dat;
+        u32 res[3];
+};
+
+struct cpm2_gpio32_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u32 cpdata;
+};
+
+static inline struct cpm2_gpio32_chip *
+to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
+}
+
+static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+
+        cpm2_gc->cpdata = in_be32(&iop->dat);
+}
+
+static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        return !!(in_be32(&iop->dat) & pin_mask);
+}
+
+static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        unsigned long flags;
+        u32 pin_mask = 1 << (31 - gpio);
+
+        spin_lock_irqsave(&cpm2_gc->lock, flags);
+
+        if (value)
+                cpm2_gc->cpdata |= pin_mask;
+        else
+                cpm2_gc->cpdata &= ~pin_mask;
+
+        out_be32(&iop->dat, cpm2_gc->cpdata);
+
+        spin_unlock_irqrestore(&cpm2_gc->lock, flags);
+}
+
+static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        setbits32(&iop->dir, pin_mask);
+
+        cpm2_gpio32_set(gc, gpio, val);
+
+        return 0;
+}
+
+static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct cpm2_ioports __iomem *iop = mm_gc->regs;
+        u32 pin_mask;
+
+        pin_mask = 1 << (31 - gpio);
+
+        clrbits32(&iop->dir, pin_mask);
+
+        return 0;
+}
+
+int cpm2_gpiochip_add32(struct device_node *np)
+{
+        struct cpm2_gpio32_chip *cpm2_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct of_gpio_chip *of_gc;
+        struct gpio_chip *gc;
+
+        cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
+        if (!cpm2_gc)
+                return -ENOMEM;
+
+        spin_lock_init(&cpm2_gc->lock);
+
+        mm_gc = &cpm2_gc->mm_gc;
+        of_gc = &mm_gc->of_gc;
+        gc = &of_gc->gc;
+
+        mm_gc->save_regs = cpm2_gpio32_save_regs;
+        of_gc->gpio_cells = 2;
+        gc->ngpio = 32;
+        gc->direction_input = cpm2_gpio32_dir_in;
+        gc->direction_output = cpm2_gpio32_dir_out;
+        gc->get = cpm2_gpio32_get;
+        gc->set = cpm2_gpio32_set;
+
+        return of_mm_gpiochip_add(np, mm_gc);
+}
+#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
diff --git a/arch/powerpc/sysdev/rtc_cmos_setup.c b/arch/powerpc/sysdev/rtc_cmos_setup.c
index c09ddc0dbeb3..c1879ebfd4f4 100644
--- a/arch/powerpc/sysdev/rtc_cmos_setup.c
+++ b/arch/powerpc/sysdev/rtc_cmos_setup.c
@@ -21,6 +21,7 @@ static int  __init add_rtc(void)
         struct device_node *np;
         struct platform_device *pd;
         struct resource res[2];
+        unsigned int num_res = 1;
         int ret;
 
         memset(&res, 0, sizeof(res));
@@ -41,14 +42,24 @@ static int  __init add_rtc(void)
         if (res[0].start != RTC_PORT(0))
                 return -EINVAL;
 
-        /* Use a fixed interrupt value of 8 since on PPC if we are using this
-         * its off an i8259 which we ensure has interrupt numbers 0..15. */
-        res[1].start = 8;
-        res[1].end = 8;
-        res[1].flags = IORESOURCE_IRQ;
+        np = of_find_compatible_node(NULL, NULL, "chrp,iic");
+        if (!np)
+                np = of_find_compatible_node(NULL, NULL, "pnpPNP,000");
+        if (np) {
+                of_node_put(np);
+                /*
+                 * Use a fixed interrupt value of 8 since on PPC if we are
+                 * using this its off an i8259 which we ensure has interrupt
+                 * numbers 0..15.
+                 */
+                res[1].start = 8;
+                res[1].end = 8;
+                res[1].flags = IORESOURCE_IRQ;
+                num_res++;
+        }
 
         pd = platform_device_register_simple("rtc_cmos", -1,
-                                             &res[0], 2);
+                                             &res[0], num_res);
 
         if (IS_ERR(pd))
                 return PTR_ERR(pd);
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 2ed88122be93..8d41908e2513 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -317,6 +317,9 @@ config ARCH_ENABLE_MEMORY_HOTPLUG
         def_bool y
         depends on SPARSEMEM
 
+config ARCH_ENABLE_MEMORY_HOTREMOVE
+        def_bool y
+
 source "mm/Kconfig"
 
 comment "I/O subsystem configuration"
diff --git a/arch/s390/include/asm/Kbuild b/arch/s390/include/asm/Kbuild
new file mode 100644
index 000000000000..63a23415fba6
--- /dev/null
+++ b/arch/s390/include/asm/Kbuild
@@ -0,0 +1,15 @@
+include include/asm-generic/Kbuild.asm
+
+header-y += dasd.h
+header-y += monwriter.h
+header-y += qeth.h
+header-y += tape390.h
+header-y += ucontext.h
+header-y += vtoc.h
+header-y += zcrypt.h
+header-y += chsc.h
+
+unifdef-y += cmb.h
+unifdef-y += debug.h
+unifdef-y += chpid.h
+unifdef-y += schid.h
diff --git a/arch/s390/include/asm/airq.h b/arch/s390/include/asm/airq.h
new file mode 100644
index 000000000000..1ac80d6b0588
--- /dev/null
+++ b/arch/s390/include/asm/airq.h
@@ -0,0 +1,19 @@
+/*
+ *  include/asm-s390/airq.h
+ *
+ *    Copyright IBM Corp. 2002,2007
+ *    Author(s): Ingo Adlung <adlung@de.ibm.com>
+ *               Cornelia Huck <cornelia.huck@de.ibm.com>
+ *               Arnd Bergmann <arndb@de.ibm.com>
+ *               Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_AIRQ_H
+#define _ASM_S390_AIRQ_H
+
+typedef void (*adapter_int_handler_t)(void *, void *);
+
+void *s390_register_adapter_interrupt(adapter_int_handler_t, void *, u8);
+void s390_unregister_adapter_interrupt(void *, u8);
+
+#endif /* _ASM_S390_AIRQ_H */
diff --git a/arch/s390/include/asm/appldata.h b/arch/s390/include/asm/appldata.h
new file mode 100644
index 000000000000..79283dac8281
--- /dev/null
+++ b/arch/s390/include/asm/appldata.h
@@ -0,0 +1,90 @@
+/*
+ * include/asm-s390/appldata.h
+ *
+ * Copyright (C) IBM Corp. 2006
+ *
+ * Author(s): Melissa Howland <melissah@us.ibm.com>
+ */
+
+#ifndef _ASM_S390_APPLDATA_H
+#define _ASM_S390_APPLDATA_H
+
+#include <asm/io.h>
+
+#ifndef CONFIG_64BIT
+
+#define APPLDATA_START_INTERVAL_REC     0x00    /* Function codes for */
+#define APPLDATA_STOP_REC               0x01    /* DIAG 0xDC          */
+#define APPLDATA_GEN_EVENT_REC          0x02
+#define APPLDATA_START_CONFIG_REC       0x03
+
+/*
+ * Parameter list for DIAGNOSE X'DC'
+ */
+struct appldata_parameter_list {
+        u16 diag;               /* The DIAGNOSE code X'00DC'          */
+        u8  function;           /* The function code for the DIAGNOSE */
+        u8  parlist_length;     /* Length of the parameter list       */
+        u32 product_id_addr;    /* Address of the 16-byte product ID  */
+        u16 reserved;
+        u16 buffer_length;      /* Length of the application data buffer  */
+        u32 buffer_addr;        /* Address of the application data buffer */
+} __attribute__ ((packed));
+
+#else /* CONFIG_64BIT */
+
+#define APPLDATA_START_INTERVAL_REC     0x80
+#define APPLDATA_STOP_REC               0x81
+#define APPLDATA_GEN_EVENT_REC          0x82
+#define APPLDATA_START_CONFIG_REC       0x83
+
+/*
+ * Parameter list for DIAGNOSE X'DC'
+ */
+struct appldata_parameter_list {
+        u16 diag;
+        u8  function;
+        u8  parlist_length;
+        u32 unused01;
+        u16 reserved;
+        u16 buffer_length;
+        u32 unused02;
+        u64 product_id_addr;
+        u64 buffer_addr;
+} __attribute__ ((packed));
+
+#endif /* CONFIG_64BIT */
+
+struct appldata_product_id {
+        char prod_nr[7];        /* product number */
+        u16  prod_fn;           /* product function */
+        u8   record_nr;         /* record number */
+        u16  version_nr;        /* version */
+        u16  release_nr;        /* release */
+        u16  mod_lvl;           /* modification level */
+} __attribute__ ((packed));
+
+static inline int appldata_asm(struct appldata_product_id *id,
+                               unsigned short fn, void *buffer,
+                               unsigned short length)
+{
+        struct appldata_parameter_list parm_list;
+        int ry;
+
+        if (!MACHINE_IS_VM)
+                return -ENOSYS;
+        parm_list.diag = 0xdc;
+        parm_list.function = fn;
+        parm_list.parlist_length = sizeof(parm_list);
+        parm_list.buffer_length = length;
+        parm_list.product_id_addr = (unsigned long) id;
+        parm_list.buffer_addr = virt_to_phys(buffer);
+        asm volatile(
+                "       diag    %1,%0,0xdc"
+                : "=d" (ry)
+                : "d" (&parm_list), "m" (parm_list), "m" (*id)
+                : "cc");
+        return ry;
+}
+
+#endif /* _ASM_S390_APPLDATA_H */
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h
new file mode 100644
index 000000000000..2d184655bc5d
--- /dev/null
+++ b/arch/s390/include/asm/atomic.h
@@ -0,0 +1,285 @@
+#ifndef __ARCH_S390_ATOMIC__
+#define __ARCH_S390_ATOMIC__
+
+#include <linux/compiler.h>
+
+/*
+ *  include/asm-s390/atomic.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999-2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *               Denis Joseph Barrow,
+ *               Arnd Bergmann (arndb@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/bitops.h"
+ *    Copyright (C) 1992, Linus Torvalds
+ *
+ */
+
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ * S390 uses 'Compare And Swap' for atomicity in SMP enviroment
+ */
+
+typedef struct {
+        int counter;
+} __attribute__ ((aligned (4))) atomic_t;
+#define ATOMIC_INIT(i)  { (i) }
+
+#ifdef __KERNEL__
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+
+#define __CS_LOOP(ptr, op_val, op_string) ({                            \
+        typeof(ptr->counter) old_val, new_val;                          \
+        asm volatile(                                                   \
+                "       l       %0,%2\n"                                \
+                "0:     lr      %1,%0\n"                                \
+                op_string "     %1,%3\n"                                \
+                "       cs      %0,%1,%2\n"                             \
+                "       jl      0b"                                     \
+                : "=&d" (old_val), "=&d" (new_val),                     \
+                  "=Q" (((atomic_t *)(ptr))->counter)                   \
+                : "d" (op_val),  "Q" (((atomic_t *)(ptr))->counter)     \
+                : "cc", "memory");                                      \
+        new_val;                                                        \
+})
+
+#else /* __GNUC__ */
+
+#define __CS_LOOP(ptr, op_val, op_string) ({                            \
+        typeof(ptr->counter) old_val, new_val;                          \
+        asm volatile(                                                   \
+                "       l       %0,0(%3)\n"                             \
+                "0:     lr      %1,%0\n"                                \
+                op_string "     %1,%4\n"                                \
+                "       cs      %0,%1,0(%3)\n"                          \
+                "       jl      0b"                                     \
+                : "=&d" (old_val), "=&d" (new_val),                     \
+                  "=m" (((atomic_t *)(ptr))->counter)                   \
+                : "a" (ptr), "d" (op_val),                              \
+                  "m" (((atomic_t *)(ptr))->counter)                    \
+                : "cc", "memory");                                      \
+        new_val;                                                        \
+})
+
+#endif /* __GNUC__ */
+
+static inline int atomic_read(const atomic_t *v)
+{
+        barrier();
+        return v->counter;
+}
+
+static inline void atomic_set(atomic_t *v, int i)
+{
+        v->counter = i;
+        barrier();
+}
+
+static __inline__ int atomic_add_return(int i, atomic_t * v)
+{
+        return __CS_LOOP(v, i, "ar");
+}
+#define atomic_add(_i, _v)              atomic_add_return(_i, _v)
+#define atomic_add_negative(_i, _v)     (atomic_add_return(_i, _v) < 0)
+#define atomic_inc(_v)                  atomic_add_return(1, _v)
+#define atomic_inc_return(_v)           atomic_add_return(1, _v)
+#define atomic_inc_and_test(_v)         (atomic_add_return(1, _v) == 0)
+
+static __inline__ int atomic_sub_return(int i, atomic_t * v)
+{
+        return __CS_LOOP(v, i, "sr");
+}
+#define atomic_sub(_i, _v)              atomic_sub_return(_i, _v)
+#define atomic_sub_and_test(_i, _v)     (atomic_sub_return(_i, _v) == 0)
+#define atomic_dec(_v)                  atomic_sub_return(1, _v)
+#define atomic_dec_return(_v)           atomic_sub_return(1, _v)
+#define atomic_dec_and_test(_v)         (atomic_sub_return(1, _v) == 0)
+
+static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t * v)
+{
+               __CS_LOOP(v, ~mask, "nr");
+}
+
+static __inline__ void atomic_set_mask(unsigned long mask, atomic_t * v)
+{
+               __CS_LOOP(v, mask, "or");
+}
+
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+static __inline__ int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+        asm volatile(
+                "       cs      %0,%2,%1"
+                : "+d" (old), "=Q" (v->counter)
+                : "d" (new), "Q" (v->counter)
+                : "cc", "memory");
+#else /* __GNUC__ */
+        asm volatile(
+                "       cs      %0,%3,0(%2)"
+                : "+d" (old), "=m" (v->counter)
+                : "a" (v), "d" (new), "m" (v->counter)
+                : "cc", "memory");
+#endif /* __GNUC__ */
+        return old;
+}
+
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == u))
+                        break;
+                old = atomic_cmpxchg(v, c, c + a);
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != u;
+}
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+#undef __CS_LOOP
+
+#ifdef __s390x__
+typedef struct {
+        long long counter;
+} __attribute__ ((aligned (8))) atomic64_t;
+#define ATOMIC64_INIT(i)  { (i) }
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+
+#define __CSG_LOOP(ptr, op_val, op_string) ({                           \
+        typeof(ptr->counter) old_val, new_val;                          \
+        asm volatile(                                                   \
+                "       lg      %0,%2\n"                                \
+                "0:     lgr     %1,%0\n"                                \
+                op_string "     %1,%3\n"                                \
+                "       csg     %0,%1,%2\n"                             \
+                "       jl      0b"                                     \
+                : "=&d" (old_val), "=&d" (new_val),                     \
+                  "=Q" (((atomic_t *)(ptr))->counter)                   \
+                : "d" (op_val), "Q" (((atomic_t *)(ptr))->counter)      \
+                : "cc", "memory" );                                     \
+        new_val;                                                        \
+})
+
+#else /* __GNUC__ */
+
+#define __CSG_LOOP(ptr, op_val, op_string) ({                           \
+        typeof(ptr->counter) old_val, new_val;                          \
+        asm volatile(                                                   \
+                "       lg      %0,0(%3)\n"                             \
+                "0:     lgr     %1,%0\n"                                \
+                op_string "     %1,%4\n"                                \
+                "       csg     %0,%1,0(%3)\n"                          \
+                "       jl      0b"                                     \
+                : "=&d" (old_val), "=&d" (new_val),                     \
+                  "=m" (((atomic_t *)(ptr))->counter)                   \
+                : "a" (ptr), "d" (op_val),                              \
+                  "m" (((atomic_t *)(ptr))->counter)                    \
+                : "cc", "memory" );                                     \
+        new_val;                                                        \
+})
+
+#endif /* __GNUC__ */
+
+static inline long long atomic64_read(const atomic64_t *v)
+{
+        barrier();
+        return v->counter;
+}
+
+static inline void atomic64_set(atomic64_t *v, long long i)
+{
+        v->counter = i;
+        barrier();
+}
+
+static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
+{
+        return __CSG_LOOP(v, i, "agr");
+}
+#define atomic64_add(_i, _v)            atomic64_add_return(_i, _v)
+#define atomic64_add_negative(_i, _v)   (atomic64_add_return(_i, _v) < 0)
+#define atomic64_inc(_v)                atomic64_add_return(1, _v)
+#define atomic64_inc_return(_v)         atomic64_add_return(1, _v)
+#define atomic64_inc_and_test(_v)       (atomic64_add_return(1, _v) == 0)
+
+static __inline__ long long atomic64_sub_return(long long i, atomic64_t * v)
+{
+        return __CSG_LOOP(v, i, "sgr");
+}
+#define atomic64_sub(_i, _v)            atomic64_sub_return(_i, _v)
+#define atomic64_sub_and_test(_i, _v)   (atomic64_sub_return(_i, _v) == 0)
+#define atomic64_dec(_v)                atomic64_sub_return(1, _v)
+#define atomic64_dec_return(_v)         atomic64_sub_return(1, _v)
+#define atomic64_dec_and_test(_v)       (atomic64_sub_return(1, _v) == 0)
+
+static __inline__ void atomic64_clear_mask(unsigned long mask, atomic64_t * v)
+{
+               __CSG_LOOP(v, ~mask, "ngr");
+}
+
+static __inline__ void atomic64_set_mask(unsigned long mask, atomic64_t * v)
+{
+               __CSG_LOOP(v, mask, "ogr");
+}
+
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+static __inline__ long long atomic64_cmpxchg(atomic64_t *v,
+                                             long long old, long long new)
+{
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+        asm volatile(
+                "       csg     %0,%2,%1"
+                : "+d" (old), "=Q" (v->counter)
+                : "d" (new), "Q" (v->counter)
+                : "cc", "memory");
+#else /* __GNUC__ */
+        asm volatile(
+                "       csg     %0,%3,0(%2)"
+                : "+d" (old), "=m" (v->counter)
+                : "a" (v), "d" (new), "m" (v->counter)
+                : "cc", "memory");
+#endif /* __GNUC__ */
+        return old;
+}
+
+static __inline__ int atomic64_add_unless(atomic64_t *v,
+                                          long long a, long long u)
+{
+        long long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == u))
+                        break;
+                old = atomic64_cmpxchg(v, c, c + a);
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != u;
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+#undef __CSG_LOOP
+#endif
+
+#define smp_mb__before_atomic_dec()     smp_mb()
+#define smp_mb__after_atomic_dec()      smp_mb()
+#define smp_mb__before_atomic_inc()     smp_mb()
+#define smp_mb__after_atomic_inc()      smp_mb()
+
+#include <asm-generic/atomic.h>
+#endif /* __KERNEL__ */
+#endif /* __ARCH_S390_ATOMIC__  */
diff --git a/arch/s390/include/asm/auxvec.h b/arch/s390/include/asm/auxvec.h
new file mode 100644
index 000000000000..0d340720fd99
--- /dev/null
+++ b/arch/s390/include/asm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMS390_AUXVEC_H
+#define __ASMS390_AUXVEC_H
+
+#endif
diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h
new file mode 100644
index 000000000000..b4eb24ab5af9
--- /dev/null
+++ b/arch/s390/include/asm/bitops.h
@@ -0,0 +1,884 @@
+#ifndef _S390_BITOPS_H
+#define _S390_BITOPS_H
+
+/*
+ *  include/asm-s390/bitops.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/bitops.h"
+ *    Copyright (C) 1992, Linus Torvalds
+ *
+ */
+
+#ifdef __KERNEL__
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+
+/*
+ * 32 bit bitops format:
+ * bit 0 is the LSB of *addr; bit 31 is the MSB of *addr;
+ * bit 32 is the LSB of *(addr+4). That combined with the
+ * big endian byte order on S390 give the following bit
+ * order in memory:
+ *    1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 \
+ *    0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
+ * after that follows the next long with bit numbers
+ *    3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
+ *    2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
+ * The reason for this bit ordering is the fact that
+ * in the architecture independent code bits operations
+ * of the form "flags |= (1 << bitnr)" are used INTERMIXED
+ * with operation of the form "set_bit(bitnr, flags)".
+ *
+ * 64 bit bitops format:
+ * bit 0 is the LSB of *addr; bit 63 is the MSB of *addr;
+ * bit 64 is the LSB of *(addr+8). That combined with the
+ * big endian byte order on S390 give the following bit
+ * order in memory:
+ *    3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
+ *    2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
+ *    1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10
+ *    0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
+ * after that follows the next long with bit numbers
+ *    7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70
+ *    6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60
+ *    5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50
+ *    4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40
+ * The reason for this bit ordering is the fact that
+ * in the architecture independent code bits operations
+ * of the form "flags |= (1 << bitnr)" are used INTERMIXED
+ * with operation of the form "set_bit(bitnr, flags)".
+ */
+
+/* bitmap tables from arch/S390/kernel/bitmap.S */
+extern const char _oi_bitmap[];
+extern const char _ni_bitmap[];
+extern const char _zb_findmap[];
+extern const char _sb_findmap[];
+
+#ifndef __s390x__
+
+#define __BITOPS_ALIGN          3
+#define __BITOPS_WORDSIZE       32
+#define __BITOPS_OR             "or"
+#define __BITOPS_AND            "nr"
+#define __BITOPS_XOR            "xr"
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
+        asm volatile(                                           \
+                "       l       %0,%2\n"                        \
+                "0:     lr      %1,%0\n"                        \
+                __op_string "   %1,%3\n"                        \
+                "       cs      %0,%1,%2\n"                     \
+                "       jl      0b"                             \
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=Q" (*(unsigned long *) __addr)              \
+                : "d" (__val), "Q" (*(unsigned long *) __addr)  \
+                : "cc");
+
+#else /* __GNUC__ */
+
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
+        asm volatile(                                           \
+                "       l       %0,0(%4)\n"                     \
+                "0:     lr      %1,%0\n"                        \
+                __op_string "   %1,%3\n"                        \
+                "       cs      %0,%1,0(%4)\n"                  \
+                "       jl      0b"                             \
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=m" (*(unsigned long *) __addr)              \
+                : "d" (__val), "a" (__addr),                    \
+                  "m" (*(unsigned long *) __addr) : "cc");
+
+#endif /* __GNUC__ */
+
+#else /* __s390x__ */
+
+#define __BITOPS_ALIGN          7
+#define __BITOPS_WORDSIZE       64
+#define __BITOPS_OR             "ogr"
+#define __BITOPS_AND            "ngr"
+#define __BITOPS_XOR            "xgr"
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
+        asm volatile(                                           \
+                "       lg      %0,%2\n"                        \
+                "0:     lgr     %1,%0\n"                        \
+                __op_string "   %1,%3\n"                        \
+                "       csg     %0,%1,%2\n"                     \
+                "       jl      0b"                             \
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=Q" (*(unsigned long *) __addr)              \
+                : "d" (__val), "Q" (*(unsigned long *) __addr)  \
+                : "cc");
+
+#else /* __GNUC__ */
+
+#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
+        asm volatile(                                           \
+                "       lg      %0,0(%4)\n"                     \
+                "0:     lgr     %1,%0\n"                        \
+                __op_string "   %1,%3\n"                        \
+                "       csg     %0,%1,0(%4)\n"                  \
+                "       jl      0b"                             \
+                : "=&d" (__old), "=&d" (__new),                 \
+                  "=m" (*(unsigned long *) __addr)              \
+                : "d" (__val), "a" (__addr),                    \
+                  "m" (*(unsigned long *) __addr) : "cc");
+
+
+#endif /* __GNUC__ */
+
+#endif /* __s390x__ */
+
+#define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
+#define __BITOPS_BARRIER() asm volatile("" : : : "memory")
+
+#ifdef CONFIG_SMP
+/*
+ * SMP safe set_bit routine based on compare and swap (CS)
+ */
+static inline void set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr, old, new, mask;
+
+        addr = (unsigned long) ptr;
+        /* calculate address for CS */
+        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        /* make OR mask */
+        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        /* Do the atomic update. */
+        __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
+}
+
+/*
+ * SMP safe clear_bit routine based on compare and swap (CS)
+ */
+static inline void clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr, old, new, mask;
+
+        addr = (unsigned long) ptr;
+        /* calculate address for CS */
+        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        /* make AND mask */
+        mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
+        /* Do the atomic update. */
+        __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
+}
+
+/*
+ * SMP safe change_bit routine based on compare and swap (CS)
+ */
+static inline void change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr, old, new, mask;
+
+        addr = (unsigned long) ptr;
+        /* calculate address for CS */
+        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        /* make XOR mask */
+        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        /* Do the atomic update. */
+        __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
+}
+
+/*
+ * SMP safe test_and_set_bit routine based on compare and swap (CS)
+ */
+static inline int
+test_and_set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr, old, new, mask;
+
+        addr = (unsigned long) ptr;
+        /* calculate address for CS */
+        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        /* make OR/test mask */
+        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        /* Do the atomic update. */
+        __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
+        __BITOPS_BARRIER();
+        return (old & mask) != 0;
+}
+
+/*
+ * SMP safe test_and_clear_bit routine based on compare and swap (CS)
+ */
+static inline int
+test_and_clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr, old, new, mask;
+
+        addr = (unsigned long) ptr;
+        /* calculate address for CS */
+        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        /* make AND/test mask */
+        mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
+        /* Do the atomic update. */
+        __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
+        __BITOPS_BARRIER();
+        return (old ^ new) != 0;
+}
+
+/*
+ * SMP safe test_and_change_bit routine based on compare and swap (CS) 
+ */
+static inline int
+test_and_change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr, old, new, mask;
+
+        addr = (unsigned long) ptr;
+        /* calculate address for CS */
+        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        /* make XOR/test mask */
+        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        /* Do the atomic update. */
+        __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
+        __BITOPS_BARRIER();
+        return (old & mask) != 0;
+}
+#endif /* CONFIG_SMP */
+
+/*
+ * fast, non-SMP set_bit routine
+ */
+static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+
+        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        asm volatile(
+                "       oc      0(1,%1),0(%2)"
+                : "=m" (*(char *) addr) : "a" (addr),
+                  "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
+}
+
+static inline void 
+__constant_set_bit(const unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+
+        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        *(unsigned char *) addr |= 1 << (nr & 7);
+}
+
+#define set_bit_simple(nr,addr) \
+(__builtin_constant_p((nr)) ? \
+ __constant_set_bit((nr),(addr)) : \
+ __set_bit((nr),(addr)) )
+
+/*
+ * fast, non-SMP clear_bit routine
+ */
+static inline void 
+__clear_bit(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+
+        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        asm volatile(
+                "       nc      0(1,%1),0(%2)"
+                : "=m" (*(char *) addr) : "a" (addr),
+                  "a" (_ni_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc");
+}
+
+static inline void 
+__constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+
+        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        *(unsigned char *) addr &= ~(1 << (nr & 7));
+}
+
+#define clear_bit_simple(nr,addr) \
+(__builtin_constant_p((nr)) ? \
+ __constant_clear_bit((nr),(addr)) : \
+ __clear_bit((nr),(addr)) )
+
+/* 
+ * fast, non-SMP change_bit routine 
+ */
+static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+
+        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        asm volatile(
+                "       xc      0(1,%1),0(%2)"
+                :  "=m" (*(char *) addr) : "a" (addr),
+                   "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
+}
+
+static inline void 
+__constant_change_bit(const unsigned long nr, volatile unsigned long *ptr) 
+{
+        unsigned long addr;
+
+        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        *(unsigned char *) addr ^= 1 << (nr & 7);
+}
+
+#define change_bit_simple(nr,addr) \
+(__builtin_constant_p((nr)) ? \
+ __constant_change_bit((nr),(addr)) : \
+ __change_bit((nr),(addr)) )
+
+/*
+ * fast, non-SMP test_and_set_bit routine
+ */
+static inline int
+test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+        unsigned char ch;
+
+        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        ch = *(unsigned char *) addr;
+        asm volatile(
+                "       oc      0(1,%1),0(%2)"
+                : "=m" (*(char *) addr)
+                : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                  "m" (*(char *) addr) : "cc", "memory");
+        return (ch >> (nr & 7)) & 1;
+}
+#define __test_and_set_bit(X,Y)         test_and_set_bit_simple(X,Y)
+
+/*
+ * fast, non-SMP test_and_clear_bit routine
+ */
+static inline int
+test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+        unsigned char ch;
+
+        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        ch = *(unsigned char *) addr;
+        asm volatile(
+                "       nc      0(1,%1),0(%2)"
+                : "=m" (*(char *) addr)
+                : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
+                  "m" (*(char *) addr) : "cc", "memory");
+        return (ch >> (nr & 7)) & 1;
+}
+#define __test_and_clear_bit(X,Y)       test_and_clear_bit_simple(X,Y)
+
+/*
+ * fast, non-SMP test_and_change_bit routine
+ */
+static inline int
+test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr)
+{
+        unsigned long addr;
+        unsigned char ch;
+
+        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        ch = *(unsigned char *) addr;
+        asm volatile(
+                "       xc      0(1,%1),0(%2)"
+                : "=m" (*(char *) addr)
+                : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
+                  "m" (*(char *) addr) : "cc", "memory");
+        return (ch >> (nr & 7)) & 1;
+}
+#define __test_and_change_bit(X,Y)      test_and_change_bit_simple(X,Y)
+
+#ifdef CONFIG_SMP
+#define set_bit             set_bit_cs
+#define clear_bit           clear_bit_cs
+#define change_bit          change_bit_cs
+#define test_and_set_bit    test_and_set_bit_cs
+#define test_and_clear_bit  test_and_clear_bit_cs
+#define test_and_change_bit test_and_change_bit_cs
+#else
+#define set_bit             set_bit_simple
+#define clear_bit           clear_bit_simple
+#define change_bit          change_bit_simple
+#define test_and_set_bit    test_and_set_bit_simple
+#define test_and_clear_bit  test_and_clear_bit_simple
+#define test_and_change_bit test_and_change_bit_simple
+#endif
+
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+
+static inline int __test_bit(unsigned long nr, const volatile unsigned long *ptr)
+{
+        unsigned long addr;
+        unsigned char ch;
+
+        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        ch = *(volatile unsigned char *) addr;
+        return (ch >> (nr & 7)) & 1;
+}
+
+static inline int 
+__constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
+    return (((volatile char *) addr)
+            [(nr^(__BITOPS_WORDSIZE-8))>>3] & (1<<(nr&7))) != 0;
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p((nr)) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)) )
+
+/*
+ * Optimized find bit helper functions.
+ */
+
+/**
+ * __ffz_word_loop - find byte offset of first long != -1UL
+ * @addr: pointer to array of unsigned long
+ * @size: size of the array in bits
+ */
+static inline unsigned long __ffz_word_loop(const unsigned long *addr,
+                                            unsigned long size)
+{
+        typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
+        unsigned long bytes = 0;
+
+        asm volatile(
+#ifndef __s390x__
+                "       ahi     %1,-1\n"
+                "       sra     %1,5\n"
+                "       jz      1f\n"
+                "0:     c       %2,0(%0,%3)\n"
+                "       jne     1f\n"
+                "       la      %0,4(%0)\n"
+                "       brct    %1,0b\n"
+                "1:\n"
+#else
+                "       aghi    %1,-1\n"
+                "       srag    %1,%1,6\n"
+                "       jz      1f\n"
+                "0:     cg      %2,0(%0,%3)\n"
+                "       jne     1f\n"
+                "       la      %0,8(%0)\n"
+                "       brct    %1,0b\n"
+                "1:\n"
+#endif
+                : "+&a" (bytes), "+&d" (size)
+                : "d" (-1UL), "a" (addr), "m" (*(addrtype *) addr)
+                : "cc" );
+        return bytes;
+}
+
+/**
+ * __ffs_word_loop - find byte offset of first long != 0UL
+ * @addr: pointer to array of unsigned long
+ * @size: size of the array in bits
+ */
+static inline unsigned long __ffs_word_loop(const unsigned long *addr,
+                                            unsigned long size)
+{
+        typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
+        unsigned long bytes = 0;
+
+        asm volatile(
+#ifndef __s390x__
+                "       ahi     %1,-1\n"
+                "       sra     %1,5\n"
+                "       jz      1f\n"
+                "0:     c       %2,0(%0,%3)\n"
+                "       jne     1f\n"
+                "       la      %0,4(%0)\n"
+                "       brct    %1,0b\n"
+                "1:\n"
+#else
+                "       aghi    %1,-1\n"
+                "       srag    %1,%1,6\n"
+                "       jz      1f\n"
+                "0:     cg      %2,0(%0,%3)\n"
+                "       jne     1f\n"
+                "       la      %0,8(%0)\n"
+                "       brct    %1,0b\n"
+                "1:\n"
+#endif
+                : "+&a" (bytes), "+&a" (size)
+                : "d" (0UL), "a" (addr), "m" (*(addrtype *) addr)
+                : "cc" );
+        return bytes;
+}
+
+/**
+ * __ffz_word - add number of the first unset bit
+ * @nr: base value the bit number is added to
+ * @word: the word that is searched for unset bits
+ */
+static inline unsigned long __ffz_word(unsigned long nr, unsigned long word)
+{
+#ifdef __s390x__
+        if (likely((word & 0xffffffff) == 0xffffffff)) {
+                word >>= 32;
+                nr += 32;
+        }
+#endif
+        if (likely((word & 0xffff) == 0xffff)) {
+                word >>= 16;
+                nr += 16;
+        }
+        if (likely((word & 0xff) == 0xff)) {
+                word >>= 8;
+                nr += 8;
+        }
+        return nr + _zb_findmap[(unsigned char) word];
+}
+
+/**
+ * __ffs_word - add number of the first set bit
+ * @nr: base value the bit number is added to
+ * @word: the word that is searched for set bits
+ */
+static inline unsigned long __ffs_word(unsigned long nr, unsigned long word)
+{
+#ifdef __s390x__
+        if (likely((word & 0xffffffff) == 0)) {
+                word >>= 32;
+                nr += 32;
+        }
+#endif
+        if (likely((word & 0xffff) == 0)) {
+                word >>= 16;
+                nr += 16;
+        }
+        if (likely((word & 0xff) == 0)) {
+                word >>= 8;
+                nr += 8;
+        }
+        return nr + _sb_findmap[(unsigned char) word];
+}
+
+
+/**
+ * __load_ulong_be - load big endian unsigned long
+ * @p: pointer to array of unsigned long
+ * @offset: byte offset of source value in the array
+ */
+static inline unsigned long __load_ulong_be(const unsigned long *p,
+                                            unsigned long offset)
+{
+        p = (unsigned long *)((unsigned long) p + offset);
+        return *p;
+}
+
+/**
+ * __load_ulong_le - load little endian unsigned long
+ * @p: pointer to array of unsigned long
+ * @offset: byte offset of source value in the array
+ */
+static inline unsigned long __load_ulong_le(const unsigned long *p,
+                                            unsigned long offset)
+{
+        unsigned long word;
+
+        p = (unsigned long *)((unsigned long) p + offset);
+#ifndef __s390x__
+        asm volatile(
+                "       ic      %0,0(%1)\n"
+                "       icm     %0,2,1(%1)\n"
+                "       icm     %0,4,2(%1)\n"
+                "       icm     %0,8,3(%1)"
+                : "=&d" (word) : "a" (p), "m" (*p) : "cc");
+#else
+        asm volatile(
+                "       lrvg    %0,%1"
+                : "=d" (word) : "m" (*p) );
+#endif
+        return word;
+}
+
+/*
+ * The various find bit functions.
+ */
+
+/*
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+        return __ffz_word(0, word);
+}
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs (unsigned long word)
+{
+        return __ffs_word(0, word);
+}
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int x)
+{
+        if (!x)
+                return 0;
+        return __ffs_word(1, x);
+}
+
+/**
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+static inline unsigned long find_first_zero_bit(const unsigned long *addr,
+                                                unsigned long size)
+{
+        unsigned long bytes, bits;
+
+        if (!size)
+                return 0;
+        bytes = __ffz_word_loop(addr, size);
+        bits = __ffz_word(bytes*8, __load_ulong_be(addr, bytes));
+        return (bits < size) ? bits : size;
+}
+
+/**
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first set bit, not the number of the byte
+ * containing a bit.
+ */
+static inline unsigned long find_first_bit(const unsigned long * addr,
+                                           unsigned long size)
+{
+        unsigned long bytes, bits;
+
+        if (!size)
+                return 0;
+        bytes = __ffs_word_loop(addr, size);
+        bits = __ffs_word(bytes*8, __load_ulong_be(addr, bytes));
+        return (bits < size) ? bits : size;
+}
+
+/**
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static inline int find_next_zero_bit (const unsigned long * addr,
+                                      unsigned long size,
+                                      unsigned long offset)
+{
+        const unsigned long *p;
+        unsigned long bit, set;
+
+        if (offset >= size)
+                return size;
+        bit = offset & (__BITOPS_WORDSIZE - 1);
+        offset -= bit;
+        size -= offset;
+        p = addr + offset / __BITOPS_WORDSIZE;
+        if (bit) {
+                /*
+                 * __ffz_word returns __BITOPS_WORDSIZE
+                 * if no zero bit is present in the word.
+                 */
+                set = __ffz_word(0, *p >> bit) + bit;
+                if (set >= size)
+                        return size + offset;
+                if (set < __BITOPS_WORDSIZE)
+                        return set + offset;
+                offset += __BITOPS_WORDSIZE;
+                size -= __BITOPS_WORDSIZE;
+                p++;
+        }
+        return offset + find_first_zero_bit(p, size);
+}
+
+/**
+ * find_next_bit - find the first set bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static inline int find_next_bit (const unsigned long * addr,
+                                 unsigned long size,
+                                 unsigned long offset)
+{
+        const unsigned long *p;
+        unsigned long bit, set;
+
+        if (offset >= size)
+                return size;
+        bit = offset & (__BITOPS_WORDSIZE - 1);
+        offset -= bit;
+        size -= offset;
+        p = addr + offset / __BITOPS_WORDSIZE;
+        if (bit) {
+                /*
+                 * __ffs_word returns __BITOPS_WORDSIZE
+                 * if no one bit is present in the word.
+                 */
+                set = __ffs_word(0, *p & (~0UL << bit));
+                if (set >= size)
+                        return size + offset;
+                if (set < __BITOPS_WORDSIZE)
+                        return set + offset;
+                offset += __BITOPS_WORDSIZE;
+                size -= __BITOPS_WORDSIZE;
+                p++;
+        }
+        return offset + find_first_bit(p, size);
+}
+
+/*
+ * Every architecture must define this function. It's the fastest
+ * way of searching a 140-bit bitmap where the first 100 bits are
+ * unlikely to be set. It's guaranteed that at least one of the 140
+ * bits is cleared.
+ */
+static inline int sched_find_first_bit(unsigned long *b)
+{
+        return find_first_bit(b, 140);
+}
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+
+/*
+ * ATTENTION: intel byte ordering convention for ext2 and minix !!
+ * bit 0 is the LSB of addr; bit 31 is the MSB of addr;
+ * bit 32 is the LSB of (addr+4).
+ * That combined with the little endian byte order of Intel gives the
+ * following bit order in memory:
+ *    07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 \
+ *    23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
+ */
+
+#define ext2_set_bit(nr, addr)       \
+        __test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
+#define ext2_set_bit_atomic(lock, nr, addr)       \
+        test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
+#define ext2_clear_bit(nr, addr)     \
+        __test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
+#define ext2_clear_bit_atomic(lock, nr, addr)     \
+        test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
+#define ext2_test_bit(nr, addr)      \
+        test_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
+
+static inline int ext2_find_first_zero_bit(void *vaddr, unsigned int size)
+{
+        unsigned long bytes, bits;
+
+        if (!size)
+                return 0;
+        bytes = __ffz_word_loop(vaddr, size);
+        bits = __ffz_word(bytes*8, __load_ulong_le(vaddr, bytes));
+        return (bits < size) ? bits : size;
+}
+
+static inline int ext2_find_next_zero_bit(void *vaddr, unsigned long size,
+                                          unsigned long offset)
+{
+        unsigned long *addr = vaddr, *p;
+        unsigned long bit, set;
+
+        if (offset >= size)
+                return size;
+        bit = offset & (__BITOPS_WORDSIZE - 1);
+        offset -= bit;
+        size -= offset;
+        p = addr + offset / __BITOPS_WORDSIZE;
+        if (bit) {
+                /*
+                 * s390 version of ffz returns __BITOPS_WORDSIZE
+                 * if no zero bit is present in the word.
+                 */
+                set = ffz(__load_ulong_le(p, 0) >> bit) + bit;
+                if (set >= size)
+                        return size + offset;
+                if (set < __BITOPS_WORDSIZE)
+                        return set + offset;
+                offset += __BITOPS_WORDSIZE;
+                size -= __BITOPS_WORDSIZE;
+                p++;
+        }
+        return offset + ext2_find_first_zero_bit(p, size);
+}
+
+static inline unsigned long ext2_find_first_bit(void *vaddr,
+                                                unsigned long size)
+{
+        unsigned long bytes, bits;
+
+        if (!size)
+                return 0;
+        bytes = __ffs_word_loop(vaddr, size);
+        bits = __ffs_word(bytes*8, __load_ulong_le(vaddr, bytes));
+        return (bits < size) ? bits : size;
+}
+
+static inline int ext2_find_next_bit(void *vaddr, unsigned long size,
+                                     unsigned long offset)
+{
+        unsigned long *addr = vaddr, *p;
+        unsigned long bit, set;
+
+        if (offset >= size)
+                return size;
+        bit = offset & (__BITOPS_WORDSIZE - 1);
+        offset -= bit;
+        size -= offset;
+        p = addr + offset / __BITOPS_WORDSIZE;
+        if (bit) {
+                /*
+                 * s390 version of ffz returns __BITOPS_WORDSIZE
+                 * if no zero bit is present in the word.
+                 */
+                set = ffs(__load_ulong_le(p, 0) >> bit) + bit;
+                if (set >= size)
+                        return size + offset;
+                if (set < __BITOPS_WORDSIZE)
+                        return set + offset;
+                offset += __BITOPS_WORDSIZE;
+                size -= __BITOPS_WORDSIZE;
+                p++;
+        }
+        return offset + ext2_find_first_bit(p, size);
+}
+
+#include <asm-generic/bitops/minix.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* _S390_BITOPS_H */
diff --git a/arch/s390/include/asm/bug.h b/arch/s390/include/asm/bug.h
new file mode 100644
index 000000000000..384e3621e341
--- /dev/null
+++ b/arch/s390/include/asm/bug.h
@@ -0,0 +1,70 @@
+#ifndef _ASM_S390_BUG_H
+#define _ASM_S390_BUG_H
+
+#include <linux/kernel.h>
+
+#ifdef CONFIG_BUG
+
+#ifdef CONFIG_64BIT
+#define S390_LONG ".quad"
+#else
+#define S390_LONG ".long"
+#endif
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+
+#define __EMIT_BUG(x) do {                                      \
+        asm volatile(                                           \
+                "0:     j       0b+2\n"                         \
+                "1:\n"                                          \
+                ".section .rodata.str,\"aMS\",@progbits,1\n"    \
+                "2:     .asciz  \""__FILE__"\"\n"               \
+                ".previous\n"                                   \
+                ".section __bug_table,\"a\"\n"                  \
+                "3:\t"  S390_LONG "\t1b,2b\n"                   \
+                "       .short  %0,%1\n"                        \
+                "       .org    3b+%2\n"                        \
+                ".previous\n"                                   \
+                : : "i" (__LINE__),                             \
+                    "i" (x),                                    \
+                    "i" (sizeof(struct bug_entry)));            \
+} while (0)
+
+#else /* CONFIG_DEBUG_BUGVERBOSE */
+
+#define __EMIT_BUG(x) do {                              \
+        asm volatile(                                   \
+                "0:     j       0b+2\n"                 \
+                "1:\n"                                  \
+                ".section __bug_table,\"a\"\n"          \
+                "2:\t"  S390_LONG "\t1b\n"              \
+                "       .short  %0\n"                   \
+                "       .org    2b+%1\n"                \
+                ".previous\n"                           \
+                : : "i" (x),                            \
+                    "i" (sizeof(struct bug_entry)));    \
+} while (0)
+
+#endif /* CONFIG_DEBUG_BUGVERBOSE */
+
+#define BUG()   __EMIT_BUG(0)
+
+#define WARN_ON(x) ({                                   \
+        int __ret_warn_on = !!(x);                      \
+        if (__builtin_constant_p(__ret_warn_on)) {      \
+                if (__ret_warn_on)                      \
+                        __EMIT_BUG(BUGFLAG_WARNING);    \
+        } else {                                        \
+                if (unlikely(__ret_warn_on))            \
+                        __EMIT_BUG(BUGFLAG_WARNING);    \
+        }                                               \
+        unlikely(__ret_warn_on);                        \
+})
+
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_WARN_ON
+#endif /* CONFIG_BUG */
+
+#include <asm-generic/bug.h>
+
+#endif /* _ASM_S390_BUG_H */
diff --git a/arch/s390/include/asm/bugs.h b/arch/s390/include/asm/bugs.h
new file mode 100644
index 000000000000..011f1e6a2a6c
--- /dev/null
+++ b/arch/s390/include/asm/bugs.h
@@ -0,0 +1,22 @@
+/*
+ *  include/asm-s390/bugs.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/bugs.h"
+ *    Copyright (C) 1994  Linus Torvalds
+ */
+
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ *      void check_bugs(void);
+ */
+
+static inline void check_bugs(void)
+{
+  /* s390 has no bugs ... */
+}
diff --git a/arch/s390/include/asm/byteorder.h b/arch/s390/include/asm/byteorder.h
new file mode 100644
index 000000000000..1fe2492baa8d
--- /dev/null
+++ b/arch/s390/include/asm/byteorder.h
@@ -0,0 +1,125 @@
+#ifndef _S390_BYTEORDER_H
+#define _S390_BYTEORDER_H
+
+/*
+ *  include/asm-s390/byteorder.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ */
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+#ifdef __s390x__
+static inline __u64 ___arch__swab64p(const __u64 *x)
+{
+        __u64 result;
+
+        asm volatile("lrvg %0,%1" : "=d" (result) : "m" (*x));
+        return result;
+}
+
+static inline __u64 ___arch__swab64(__u64 x)
+{
+        __u64 result;
+
+        asm volatile("lrvgr %0,%1" : "=d" (result) : "d" (x));
+        return result;
+}
+
+static inline void ___arch__swab64s(__u64 *x)
+{
+        *x = ___arch__swab64p(x);
+}
+#endif /* __s390x__ */
+
+static inline __u32 ___arch__swab32p(const __u32 *x)
+{
+        __u32 result;
+        
+        asm volatile(
+#ifndef __s390x__
+                "       icm     %0,8,3(%1)\n"
+                "       icm     %0,4,2(%1)\n"
+                "       icm     %0,2,1(%1)\n"
+                "       ic      %0,0(%1)"
+                : "=&d" (result) : "a" (x), "m" (*x) : "cc");
+#else /* __s390x__ */
+                "       lrv     %0,%1"
+                : "=d" (result) : "m" (*x));
+#endif /* __s390x__ */
+        return result;
+}
+
+static inline __u32 ___arch__swab32(__u32 x)
+{
+#ifndef __s390x__
+        return ___arch__swab32p(&x);
+#else /* __s390x__ */
+        __u32 result;
+        
+        asm volatile("lrvr  %0,%1" : "=d" (result) : "d" (x));
+        return result;
+#endif /* __s390x__ */
+}
+
+static __inline__ void ___arch__swab32s(__u32 *x)
+{
+        *x = ___arch__swab32p(x);
+}
+
+static __inline__ __u16 ___arch__swab16p(const __u16 *x)
+{
+        __u16 result;
+        
+        asm volatile(
+#ifndef __s390x__
+                "       icm     %0,2,1(%1)\n"
+                "       ic      %0,0(%1)\n"
+                : "=&d" (result) : "a" (x), "m" (*x) : "cc");
+#else /* __s390x__ */
+                "       lrvh    %0,%1"
+                : "=d" (result) : "m" (*x));
+#endif /* __s390x__ */
+        return result;
+}
+
+static __inline__ __u16 ___arch__swab16(__u16 x)
+{
+        return ___arch__swab16p(&x);
+}
+
+static __inline__ void ___arch__swab16s(__u16 *x)
+{
+        *x = ___arch__swab16p(x);
+}
+
+#ifdef __s390x__
+#define __arch__swab64(x) ___arch__swab64(x)
+#define __arch__swab64p(x) ___arch__swab64p(x)
+#define __arch__swab64s(x) ___arch__swab64s(x)
+#endif /* __s390x__ */
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#define __arch__swab32p(x) ___arch__swab32p(x)
+#define __arch__swab16p(x) ___arch__swab16p(x)
+#define __arch__swab32s(x) ___arch__swab32s(x)
+#define __arch__swab16s(x) ___arch__swab16s(x)
+
+#ifndef __s390x__
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+#else /* __s390x__ */
+#define __BYTEORDER_HAS_U64__
+#endif /* __s390x__ */
+
+#endif /* __GNUC__ */
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _S390_BYTEORDER_H */
diff --git a/arch/s390/include/asm/cache.h b/arch/s390/include/asm/cache.h
new file mode 100644
index 000000000000..9b866816863c
--- /dev/null
+++ b/arch/s390/include/asm/cache.h
@@ -0,0 +1,19 @@
+/*
+ *  include/asm-s390/cache.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *
+ *  Derived from "include/asm-i386/cache.h"
+ *    Copyright (C) 1992, Linus Torvalds
+ */
+
+#ifndef __ARCH_S390_CACHE_H
+#define __ARCH_S390_CACHE_H
+
+#define L1_CACHE_BYTES     256
+#define L1_CACHE_SHIFT     8
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+#endif
diff --git a/arch/s390/include/asm/cacheflush.h b/arch/s390/include/asm/cacheflush.h
new file mode 100644
index 000000000000..49d5af916d01
--- /dev/null
+++ b/arch/s390/include/asm/cacheflush.h
@@ -0,0 +1,31 @@
+#ifndef _S390_CACHEFLUSH_H
+#define _S390_CACHEFLUSH_H
+
+/* Keep includes the same across arches.  */
+#include <linux/mm.h>
+
+/* Caches aren't brain-dead on the s390. */
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_dcache_page(page)                 do { } while (0)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+#define flush_icache_range(start, end)          do { } while (0)
+#define flush_icache_page(vma,pg)               do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_vmap(start, end)            do { } while (0)
+#define flush_cache_vunmap(start, end)          do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+
+#ifdef CONFIG_DEBUG_PAGEALLOC
+void kernel_map_pages(struct page *page, int numpages, int enable);
+#endif
+
+#endif /* _S390_CACHEFLUSH_H */
diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h
new file mode 100644
index 000000000000..ba007d8df941
--- /dev/null
+++ b/arch/s390/include/asm/ccwdev.h
@@ -0,0 +1,192 @@
+/*
+ *  include/asm-s390/ccwdev.h
+ *  include/asm-s390x/ccwdev.h
+ *
+ *    Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Arnd Bergmann <arndb@de.ibm.com>
+ *
+ *  Interface for CCW device drivers
+ */
+#ifndef _S390_CCWDEV_H_
+#define _S390_CCWDEV_H_
+
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+#include <asm/fcx.h>
+
+/* structs from asm/cio.h */
+struct irb;
+struct ccw1;
+struct ccw_dev_id;
+
+/* simplified initializers for struct ccw_device:
+ * CCW_DEVICE and CCW_DEVICE_DEVTYPE initialize one
+ * entry in your MODULE_DEVICE_TABLE and set the match_flag correctly */
+#define CCW_DEVICE(cu, cum)                                             \
+        .cu_type=(cu), .cu_model=(cum),                                 \
+        .match_flags=(CCW_DEVICE_ID_MATCH_CU_TYPE                       \
+                   | (cum ? CCW_DEVICE_ID_MATCH_CU_MODEL : 0))
+
+#define CCW_DEVICE_DEVTYPE(cu, cum, dev, devm)                          \
+        .cu_type=(cu), .cu_model=(cum), .dev_type=(dev), .dev_model=(devm),\
+        .match_flags=CCW_DEVICE_ID_MATCH_CU_TYPE                        \
+                   | ((cum) ? CCW_DEVICE_ID_MATCH_CU_MODEL : 0)         \
+                   | CCW_DEVICE_ID_MATCH_DEVICE_TYPE                    \
+                   | ((devm) ? CCW_DEVICE_ID_MATCH_DEVICE_MODEL : 0)
+
+/* scan through an array of device ids and return the first
+ * entry that matches the device.
+ *
+ * the array must end with an entry containing zero match_flags
+ */
+static inline const struct ccw_device_id *
+ccw_device_id_match(const struct ccw_device_id *array,
+                        const struct ccw_device_id *match)
+{
+        const struct ccw_device_id *id = array;
+
+        for (id = array; id->match_flags; id++) {
+                if ((id->match_flags & CCW_DEVICE_ID_MATCH_CU_TYPE)
+                    && (id->cu_type != match->cu_type))
+                        continue;
+
+                if ((id->match_flags & CCW_DEVICE_ID_MATCH_CU_MODEL)
+                    && (id->cu_model != match->cu_model))
+                        continue;
+
+                if ((id->match_flags & CCW_DEVICE_ID_MATCH_DEVICE_TYPE)
+                    && (id->dev_type != match->dev_type))
+                        continue;
+
+                if ((id->match_flags & CCW_DEVICE_ID_MATCH_DEVICE_MODEL)
+                    && (id->dev_model != match->dev_model))
+                        continue;
+
+                return id;
+        }
+
+        return NULL;
+}
+
+/**
+ * struct ccw_device - channel attached device
+ * @ccwlock: pointer to device lock
+ * @id: id of this device
+ * @drv: ccw driver for this device
+ * @dev: embedded device structure
+ * @online: online status of device
+ * @handler: interrupt handler
+ *
+ * @handler is a member of the device rather than the driver since a driver
+ * can have different interrupt handlers for different ccw devices
+ * (multi-subchannel drivers).
+ */
+struct ccw_device {
+        spinlock_t *ccwlock;
+/* private: */
+        struct ccw_device_private *private;     /* cio private information */
+/* public: */
+        struct ccw_device_id id;
+        struct ccw_driver *drv;
+        struct device dev;
+        int online;
+        void (*handler) (struct ccw_device *, unsigned long, struct irb *);
+};
+
+
+/**
+ * struct ccw driver - device driver for channel attached devices
+ * @owner: owning module
+ * @ids: ids supported by this driver
+ * @probe: function called on probe
+ * @remove: function called on remove
+ * @set_online: called when setting device online
+ * @set_offline: called when setting device offline
+ * @notify: notify driver of device state changes
+ * @shutdown: called at device shutdown
+ * @driver: embedded device driver structure
+ * @name: device driver name
+ */
+struct ccw_driver {
+        struct module *owner;
+        struct ccw_device_id *ids;
+        int (*probe) (struct ccw_device *);
+        void (*remove) (struct ccw_device *);
+        int (*set_online) (struct ccw_device *);
+        int (*set_offline) (struct ccw_device *);
+        int (*notify) (struct ccw_device *, int);
+        void (*shutdown) (struct ccw_device *);
+        struct device_driver driver;
+        char *name;
+};
+
+extern struct ccw_device *get_ccwdev_by_busid(struct ccw_driver *cdrv,
+                                              const char *bus_id);
+
+/* devices drivers call these during module load and unload.
+ * When a driver is registered, its probe method is called
+ * when new devices for its type pop up */
+extern int  ccw_driver_register   (struct ccw_driver *driver);
+extern void ccw_driver_unregister (struct ccw_driver *driver);
+
+struct ccw1;
+
+extern int ccw_device_set_options_mask(struct ccw_device *, unsigned long);
+extern int ccw_device_set_options(struct ccw_device *, unsigned long);
+extern void ccw_device_clear_options(struct ccw_device *, unsigned long);
+
+/* Allow for i/o completion notification after primary interrupt status. */
+#define CCWDEV_EARLY_NOTIFICATION       0x0001
+/* Report all interrupt conditions. */
+#define CCWDEV_REPORT_ALL               0x0002
+/* Try to perform path grouping. */
+#define CCWDEV_DO_PATHGROUP             0x0004
+/* Allow forced onlining of boxed devices. */
+#define CCWDEV_ALLOW_FORCE              0x0008
+
+extern int ccw_device_start(struct ccw_device *, struct ccw1 *,
+                            unsigned long, __u8, unsigned long);
+extern int ccw_device_start_timeout(struct ccw_device *, struct ccw1 *,
+                                    unsigned long, __u8, unsigned long, int);
+extern int ccw_device_start_key(struct ccw_device *, struct ccw1 *,
+                                unsigned long, __u8, __u8, unsigned long);
+extern int ccw_device_start_timeout_key(struct ccw_device *, struct ccw1 *,
+                                        unsigned long, __u8, __u8,
+                                        unsigned long, int);
+
+
+extern int ccw_device_resume(struct ccw_device *);
+extern int ccw_device_halt(struct ccw_device *, unsigned long);
+extern int ccw_device_clear(struct ccw_device *, unsigned long);
+int ccw_device_tm_start_key(struct ccw_device *cdev, struct tcw *tcw,
+                            unsigned long intparm, u8 lpm, u8 key);
+int ccw_device_tm_start_key(struct ccw_device *, struct tcw *,
+                            unsigned long, u8, u8);
+int ccw_device_tm_start_timeout_key(struct ccw_device *, struct tcw *,
+                            unsigned long, u8, u8, int);
+int ccw_device_tm_start(struct ccw_device *, struct tcw *,
+                            unsigned long, u8);
+int ccw_device_tm_start_timeout(struct ccw_device *, struct tcw *,
+                            unsigned long, u8, int);
+int ccw_device_tm_intrg(struct ccw_device *cdev);
+
+extern int ccw_device_set_online(struct ccw_device *cdev);
+extern int ccw_device_set_offline(struct ccw_device *cdev);
+
+
+extern struct ciw *ccw_device_get_ciw(struct ccw_device *, __u32 cmd);
+extern __u8 ccw_device_get_path_mask(struct ccw_device *);
+extern void ccw_device_get_id(struct ccw_device *, struct ccw_dev_id *);
+
+#define get_ccwdev_lock(x) (x)->ccwlock
+
+#define to_ccwdev(n) container_of(n, struct ccw_device, dev)
+#define to_ccwdrv(n) container_of(n, struct ccw_driver, driver)
+
+extern struct ccw_device *ccw_device_probe_console(void);
+
+// FIXME: these have to go
+extern int _ccw_device_get_subchannel_number(struct ccw_device *);
+
+extern void *ccw_device_get_chp_desc(struct ccw_device *, int);
+#endif /* _S390_CCWDEV_H_ */
diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h
new file mode 100644
index 000000000000..a27f68985a79
--- /dev/null
+++ b/arch/s390/include/asm/ccwgroup.h
@@ -0,0 +1,69 @@
+#ifndef S390_CCWGROUP_H
+#define S390_CCWGROUP_H
+
+struct ccw_device;
+struct ccw_driver;
+
+/**
+ * struct ccwgroup_device - ccw group device
+ * @creator_id: unique number of the driver
+ * @state: online/offline state
+ * @count: number of attached slave devices
+ * @dev: embedded device structure
+ * @cdev: variable number of slave devices, allocated as needed
+ */
+struct ccwgroup_device {
+        unsigned long creator_id;
+        enum {
+                CCWGROUP_OFFLINE,
+                CCWGROUP_ONLINE,
+        } state;
+/* private: */
+        atomic_t onoff;
+        struct mutex reg_mutex;
+/* public: */
+        unsigned int count;
+        struct device   dev;
+        struct ccw_device *cdev[0];
+};
+
+/**
+ * struct ccwgroup_driver - driver for ccw group devices
+ * @owner: driver owner
+ * @name: driver name
+ * @max_slaves: maximum number of slave devices
+ * @driver_id: unique id
+ * @probe: function called on probe
+ * @remove: function called on remove
+ * @set_online: function called when device is set online
+ * @set_offline: function called when device is set offline
+ * @shutdown: function called when device is shut down
+ * @driver: embedded driver structure
+ */
+struct ccwgroup_driver {
+        struct module *owner;
+        char *name;
+        int max_slaves;
+        unsigned long driver_id;
+
+        int (*probe) (struct ccwgroup_device *);
+        void (*remove) (struct ccwgroup_device *);
+        int (*set_online) (struct ccwgroup_device *);
+        int (*set_offline) (struct ccwgroup_device *);
+        void (*shutdown)(struct ccwgroup_device *);
+
+        struct device_driver driver;
+};
+
+extern int  ccwgroup_driver_register   (struct ccwgroup_driver *cdriver);
+extern void ccwgroup_driver_unregister (struct ccwgroup_driver *cdriver);
+int ccwgroup_create_from_string(struct device *root, unsigned int creator_id,
+                                struct ccw_driver *cdrv, int num_devices,
+                                const char *buf);
+
+extern int ccwgroup_probe_ccwdev(struct ccw_device *cdev);
+extern void ccwgroup_remove_ccwdev(struct ccw_device *cdev);
+
+#define to_ccwgroupdev(x) container_of((x), struct ccwgroup_device, dev)
+#define to_ccwgroupdrv(x) container_of((x), struct ccwgroup_driver, driver)
+#endif
diff --git a/arch/s390/include/asm/checksum.h b/arch/s390/include/asm/checksum.h
new file mode 100644
index 000000000000..d5a8e7c1477c
--- /dev/null
+++ b/arch/s390/include/asm/checksum.h
@@ -0,0 +1,166 @@
+#ifndef _S390_CHECKSUM_H
+#define _S390_CHECKSUM_H
+
+/*
+ *  include/asm-s390/checksum.h
+ *    S390 fast network checksum routines
+ *    see also arch/S390/lib/checksum.c
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Ulrich Hild        (first version)
+ *               Martin Schwidefsky (heavily optimized CKSM version)
+ *               D.J. Barrow        (third attempt) 
+ */
+
+#include <asm/uaccess.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+static inline __wsum
+csum_partial(const void *buff, int len, __wsum sum)
+{
+        register unsigned long reg2 asm("2") = (unsigned long) buff;
+        register unsigned long reg3 asm("3") = (unsigned long) len;
+
+        asm volatile(
+                "0:     cksm    %0,%1\n"        /* do checksum on longs */
+                "       jo      0b\n"
+                : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
+        return sum;
+}
+
+/*
+ * the same as csum_partial_copy, but copies from user space.
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ *
+ * Copy from userspace and compute checksum.  If we catch an exception
+ * then zero the rest of the buffer.
+ */
+static inline __wsum
+csum_partial_copy_from_user(const void __user *src, void *dst,
+                                          int len, __wsum sum,
+                                          int *err_ptr)
+{
+        int missing;
+
+        missing = copy_from_user(dst, src, len);
+        if (missing) {
+                memset(dst + len - missing, 0, missing);
+                *err_ptr = -EFAULT;
+        }
+                
+        return csum_partial(dst, len, sum);
+}
+
+
+static inline __wsum
+csum_partial_copy_nocheck (const void *src, void *dst, int len, __wsum sum)
+{
+        memcpy(dst,src,len);
+        return csum_partial(dst, len, sum);
+}
+
+/*
+ *      Fold a partial checksum without adding pseudo headers
+ */
+static inline __sum16 csum_fold(__wsum sum)
+{
+#ifndef __s390x__
+        register_pair rp;
+
+        asm volatile(
+                "       slr     %N1,%N1\n"      /* %0 = H L */
+                "       lr      %1,%0\n"        /* %0 = H L, %1 = H L 0 0 */
+                "       srdl    %1,16\n"        /* %0 = H L, %1 = 0 H L 0 */
+                "       alr     %1,%N1\n"       /* %0 = H L, %1 = L H L 0 */
+                "       alr     %0,%1\n"        /* %0 = H+L+C L+H */
+                "       srl     %0,16\n"        /* %0 = H+L+C */
+                : "+&d" (sum), "=d" (rp) : : "cc");
+#else /* __s390x__ */
+        asm volatile(
+                "       sr      3,3\n"          /* %0 = H*65536 + L */
+                "       lr      2,%0\n"         /* %0 = H L, 2/3 = H L / 0 0 */
+                "       srdl    2,16\n"         /* %0 = H L, 2/3 = 0 H / L 0 */
+                "       alr     2,3\n"          /* %0 = H L, 2/3 = L H / L 0 */
+                "       alr     %0,2\n"         /* %0 = H+L+C L+H */
+                "       srl     %0,16\n"        /* %0 = H+L+C */
+                : "+&d" (sum) : : "cc", "2", "3");
+#endif /* __s390x__ */
+        return (__force __sum16) ~sum;
+}
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ *
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+        return csum_fold(csum_partial(iph, ihl*4, 0));
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 32-bit checksum
+ */
+static inline __wsum
+csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                   unsigned short len, unsigned short proto,
+                   __wsum sum)
+{
+        __u32 csum = (__force __u32)sum;
+
+        csum += (__force __u32)saddr;
+        if (csum < (__force __u32)saddr)
+                csum++;
+
+        csum += (__force __u32)daddr;
+        if (csum < (__force __u32)daddr)
+                csum++;
+
+        csum += len + proto;
+        if (csum < len + proto)
+                csum++;
+
+        return (__force __wsum)csum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+
+static inline __sum16
+csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                  unsigned short len, unsigned short proto,
+                  __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#endif /* _S390_CHECKSUM_H */
+
+
diff --git a/arch/s390/include/asm/chpid.h b/arch/s390/include/asm/chpid.h
new file mode 100644
index 000000000000..dfe3c7f3439a
--- /dev/null
+++ b/arch/s390/include/asm/chpid.h
@@ -0,0 +1,56 @@
+/*
+ *  drivers/s390/cio/chpid.h
+ *
+ *    Copyright IBM Corp. 2007
+ *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_CHPID_H
+#define _ASM_S390_CHPID_H _ASM_S390_CHPID_H
+
+#include <linux/string.h>
+#include <asm/types.h>
+
+#define __MAX_CHPID 255
+
+struct chp_id {
+        u8 reserved1;
+        u8 cssid;
+        u8 reserved2;
+        u8 id;
+} __attribute__((packed));
+
+#ifdef __KERNEL__
+#include <asm/cio.h>
+
+static inline void chp_id_init(struct chp_id *chpid)
+{
+        memset(chpid, 0, sizeof(struct chp_id));
+}
+
+static inline int chp_id_is_equal(struct chp_id *a, struct chp_id *b)
+{
+        return (a->id == b->id) && (a->cssid == b->cssid);
+}
+
+static inline void chp_id_next(struct chp_id *chpid)
+{
+        if (chpid->id < __MAX_CHPID)
+                chpid->id++;
+        else {
+                chpid->id = 0;
+                chpid->cssid++;
+        }
+}
+
+static inline int chp_id_is_valid(struct chp_id *chpid)
+{
+        return (chpid->cssid <= __MAX_CSSID);
+}
+
+
+#define chp_id_for_each(c) \
+        for (chp_id_init(c); chp_id_is_valid(c); chp_id_next(c))
+#endif /* __KERNEL */
+
+#endif /* _ASM_S390_CHPID_H */
diff --git a/arch/s390/include/asm/chsc.h b/arch/s390/include/asm/chsc.h
new file mode 100644
index 000000000000..d38d0cf62d4b
--- /dev/null
+++ b/arch/s390/include/asm/chsc.h
@@ -0,0 +1,127 @@
+/*
+ * ioctl interface for /dev/chsc
+ *
+ * Copyright 2008 IBM Corp.
+ * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
+ */
+
+#ifndef _ASM_CHSC_H
+#define _ASM_CHSC_H
+
+#include <asm/chpid.h>
+#include <asm/schid.h>
+
+struct chsc_async_header {
+        __u16 length;
+        __u16 code;
+        __u32 cmd_dependend;
+        __u32 key : 4;
+        __u32 : 28;
+        struct subchannel_id sid;
+} __attribute__ ((packed));
+
+struct chsc_async_area {
+        struct chsc_async_header header;
+        __u8 data[PAGE_SIZE - 16 /* size of chsc_async_header */];
+} __attribute__ ((packed));
+
+
+struct chsc_response_struct {
+        __u16 length;
+        __u16 code;
+        __u32 parms;
+        __u8 data[PAGE_SIZE - 8];
+} __attribute__ ((packed));
+
+struct chsc_chp_cd {
+        struct chp_id chpid;
+        int m;
+        int fmt;
+        struct chsc_response_struct cpcb;
+};
+
+struct chsc_cu_cd {
+        __u16 cun;
+        __u8 cssid;
+        int m;
+        int fmt;
+        struct chsc_response_struct cucb;
+};
+
+struct chsc_sch_cud {
+        struct subchannel_id schid;
+        int fmt;
+        struct chsc_response_struct scub;
+};
+
+struct conf_id {
+        int m;
+        __u8 cssid;
+        __u8 ssid;
+};
+
+struct chsc_conf_info {
+        struct conf_id id;
+        int fmt;
+        struct chsc_response_struct scid;
+};
+
+struct ccl_parm_chpid {
+        int m;
+        struct chp_id chp;
+};
+
+struct ccl_parm_cssids {
+        __u8 f_cssid;
+        __u8 l_cssid;
+};
+
+struct chsc_comp_list {
+        struct {
+                enum {
+                        CCL_CU_ON_CHP = 1,
+                        CCL_CHP_TYPE_CAP = 2,
+                        CCL_CSS_IMG = 4,
+                        CCL_CSS_IMG_CONF_CHAR = 5,
+                        CCL_IOP_CHP = 6,
+                } ctype;
+                int fmt;
+                struct ccl_parm_chpid chpid;
+                struct ccl_parm_cssids cssids;
+        } req;
+        struct chsc_response_struct sccl;
+};
+
+struct chsc_dcal {
+        struct {
+                enum {
+                        DCAL_CSS_IID_PN = 4,
+                } atype;
+                __u32 list_parm[2];
+                int fmt;
+        } req;
+        struct chsc_response_struct sdcal;
+};
+
+struct chsc_cpd_info {
+        struct chp_id chpid;
+        int m;
+        int fmt;
+        int rfmt;
+        int c;
+        struct chsc_response_struct chpdb;
+};
+
+#define CHSC_IOCTL_MAGIC 'c'
+
+#define CHSC_START _IOWR(CHSC_IOCTL_MAGIC, 0x81, struct chsc_async_area)
+#define CHSC_INFO_CHANNEL_PATH _IOWR(CHSC_IOCTL_MAGIC, 0x82, \
+                                    struct chsc_chp_cd)
+#define CHSC_INFO_CU _IOWR(CHSC_IOCTL_MAGIC, 0x83, struct chsc_cu_cd)
+#define CHSC_INFO_SCH_CU _IOWR(CHSC_IOCTL_MAGIC, 0x84, struct chsc_sch_cud)
+#define CHSC_INFO_CI _IOWR(CHSC_IOCTL_MAGIC, 0x85, struct chsc_conf_info)
+#define CHSC_INFO_CCL _IOWR(CHSC_IOCTL_MAGIC, 0x86, struct chsc_comp_list)
+#define CHSC_INFO_CPD _IOWR(CHSC_IOCTL_MAGIC, 0x87, struct chsc_cpd_info)
+#define CHSC_INFO_DCAL _IOWR(CHSC_IOCTL_MAGIC, 0x88, struct chsc_dcal)
+
+#endif
diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h
new file mode 100644
index 000000000000..6dccb071aec3
--- /dev/null
+++ b/arch/s390/include/asm/cio.h
@@ -0,0 +1,514 @@
+/*
+ *  include/asm-s390/cio.h
+ *  include/asm-s390x/cio.h
+ *
+ * Common interface for I/O on S/390
+ */
+#ifndef _ASM_S390_CIO_H_
+#define _ASM_S390_CIO_H_
+
+#include <linux/spinlock.h>
+#include <asm/types.h>
+
+#ifdef __KERNEL__
+
+#define LPM_ANYPATH 0xff
+#define __MAX_CSSID 0
+
+/**
+ * struct cmd_scsw - command-mode subchannel status word
+ * @key: subchannel key
+ * @sctl: suspend control
+ * @eswf: esw format
+ * @cc: deferred condition code
+ * @fmt: format
+ * @pfch: prefetch
+ * @isic: initial-status interruption control
+ * @alcc: address-limit checking control
+ * @ssi: suppress-suspended interruption
+ * @zcc: zero condition code
+ * @ectl: extended control
+ * @pno: path not operational
+ * @res: reserved
+ * @fctl: function control
+ * @actl: activity control
+ * @stctl: status control
+ * @cpa: channel program address
+ * @dstat: device status
+ * @cstat: subchannel status
+ * @count: residual count
+ */
+struct cmd_scsw {
+        __u32 key  : 4;
+        __u32 sctl : 1;
+        __u32 eswf : 1;
+        __u32 cc   : 2;
+        __u32 fmt  : 1;
+        __u32 pfch : 1;
+        __u32 isic : 1;
+        __u32 alcc : 1;
+        __u32 ssi  : 1;
+        __u32 zcc  : 1;
+        __u32 ectl : 1;
+        __u32 pno  : 1;
+        __u32 res  : 1;
+        __u32 fctl : 3;
+        __u32 actl : 7;
+        __u32 stctl : 5;
+        __u32 cpa;
+        __u32 dstat : 8;
+        __u32 cstat : 8;
+        __u32 count : 16;
+} __attribute__ ((packed));
+
+/**
+ * struct tm_scsw - transport-mode subchannel status word
+ * @key: subchannel key
+ * @eswf: esw format
+ * @cc: deferred condition code
+ * @fmt: format
+ * @x: IRB-format control
+ * @q: interrogate-complete
+ * @ectl: extended control
+ * @pno: path not operational
+ * @fctl: function control
+ * @actl: activity control
+ * @stctl: status control
+ * @tcw: TCW address
+ * @dstat: device status
+ * @cstat: subchannel status
+ * @fcxs: FCX status
+ * @schxs: subchannel-extended status
+ */
+struct tm_scsw {
+        u32 key:4;
+        u32 :1;
+        u32 eswf:1;
+        u32 cc:2;
+        u32 fmt:3;
+        u32 x:1;
+        u32 q:1;
+        u32 :1;
+        u32 ectl:1;
+        u32 pno:1;
+        u32 :1;
+        u32 fctl:3;
+        u32 actl:7;
+        u32 stctl:5;
+        u32 tcw;
+        u32 dstat:8;
+        u32 cstat:8;
+        u32 fcxs:8;
+        u32 schxs:8;
+} __attribute__ ((packed));
+
+/**
+ * union scsw - subchannel status word
+ * @cmd: command-mode SCSW
+ * @tm: transport-mode SCSW
+ */
+union scsw {
+        struct cmd_scsw cmd;
+        struct tm_scsw tm;
+} __attribute__ ((packed));
+
+int scsw_is_tm(union scsw *scsw);
+u32 scsw_key(union scsw *scsw);
+u32 scsw_eswf(union scsw *scsw);
+u32 scsw_cc(union scsw *scsw);
+u32 scsw_ectl(union scsw *scsw);
+u32 scsw_pno(union scsw *scsw);
+u32 scsw_fctl(union scsw *scsw);
+u32 scsw_actl(union scsw *scsw);
+u32 scsw_stctl(union scsw *scsw);
+u32 scsw_dstat(union scsw *scsw);
+u32 scsw_cstat(union scsw *scsw);
+int scsw_is_solicited(union scsw *scsw);
+int scsw_is_valid_key(union scsw *scsw);
+int scsw_is_valid_eswf(union scsw *scsw);
+int scsw_is_valid_cc(union scsw *scsw);
+int scsw_is_valid_ectl(union scsw *scsw);
+int scsw_is_valid_pno(union scsw *scsw);
+int scsw_is_valid_fctl(union scsw *scsw);
+int scsw_is_valid_actl(union scsw *scsw);
+int scsw_is_valid_stctl(union scsw *scsw);
+int scsw_is_valid_dstat(union scsw *scsw);
+int scsw_is_valid_cstat(union scsw *scsw);
+int scsw_cmd_is_valid_key(union scsw *scsw);
+int scsw_cmd_is_valid_sctl(union scsw *scsw);
+int scsw_cmd_is_valid_eswf(union scsw *scsw);
+int scsw_cmd_is_valid_cc(union scsw *scsw);
+int scsw_cmd_is_valid_fmt(union scsw *scsw);
+int scsw_cmd_is_valid_pfch(union scsw *scsw);
+int scsw_cmd_is_valid_isic(union scsw *scsw);
+int scsw_cmd_is_valid_alcc(union scsw *scsw);
+int scsw_cmd_is_valid_ssi(union scsw *scsw);
+int scsw_cmd_is_valid_zcc(union scsw *scsw);
+int scsw_cmd_is_valid_ectl(union scsw *scsw);
+int scsw_cmd_is_valid_pno(union scsw *scsw);
+int scsw_cmd_is_valid_fctl(union scsw *scsw);
+int scsw_cmd_is_valid_actl(union scsw *scsw);
+int scsw_cmd_is_valid_stctl(union scsw *scsw);
+int scsw_cmd_is_valid_dstat(union scsw *scsw);
+int scsw_cmd_is_valid_cstat(union scsw *scsw);
+int scsw_cmd_is_solicited(union scsw *scsw);
+int scsw_tm_is_valid_key(union scsw *scsw);
+int scsw_tm_is_valid_eswf(union scsw *scsw);
+int scsw_tm_is_valid_cc(union scsw *scsw);
+int scsw_tm_is_valid_fmt(union scsw *scsw);
+int scsw_tm_is_valid_x(union scsw *scsw);
+int scsw_tm_is_valid_q(union scsw *scsw);
+int scsw_tm_is_valid_ectl(union scsw *scsw);
+int scsw_tm_is_valid_pno(union scsw *scsw);
+int scsw_tm_is_valid_fctl(union scsw *scsw);
+int scsw_tm_is_valid_actl(union scsw *scsw);
+int scsw_tm_is_valid_stctl(union scsw *scsw);
+int scsw_tm_is_valid_dstat(union scsw *scsw);
+int scsw_tm_is_valid_cstat(union scsw *scsw);
+int scsw_tm_is_valid_fcxs(union scsw *scsw);
+int scsw_tm_is_valid_schxs(union scsw *scsw);
+int scsw_tm_is_solicited(union scsw *scsw);
+
+#define SCSW_FCTL_CLEAR_FUNC     0x1
+#define SCSW_FCTL_HALT_FUNC      0x2
+#define SCSW_FCTL_START_FUNC     0x4
+
+#define SCSW_ACTL_SUSPENDED      0x1
+#define SCSW_ACTL_DEVACT         0x2
+#define SCSW_ACTL_SCHACT         0x4
+#define SCSW_ACTL_CLEAR_PEND     0x8
+#define SCSW_ACTL_HALT_PEND      0x10
+#define SCSW_ACTL_START_PEND     0x20
+#define SCSW_ACTL_RESUME_PEND    0x40
+
+#define SCSW_STCTL_STATUS_PEND   0x1
+#define SCSW_STCTL_SEC_STATUS    0x2
+#define SCSW_STCTL_PRIM_STATUS   0x4
+#define SCSW_STCTL_INTER_STATUS  0x8
+#define SCSW_STCTL_ALERT_STATUS  0x10
+
+#define DEV_STAT_ATTENTION       0x80
+#define DEV_STAT_STAT_MOD        0x40
+#define DEV_STAT_CU_END          0x20
+#define DEV_STAT_BUSY            0x10
+#define DEV_STAT_CHN_END         0x08
+#define DEV_STAT_DEV_END         0x04
+#define DEV_STAT_UNIT_CHECK      0x02
+#define DEV_STAT_UNIT_EXCEP      0x01
+
+#define SCHN_STAT_PCI            0x80
+#define SCHN_STAT_INCORR_LEN     0x40
+#define SCHN_STAT_PROG_CHECK     0x20
+#define SCHN_STAT_PROT_CHECK     0x10
+#define SCHN_STAT_CHN_DATA_CHK   0x08
+#define SCHN_STAT_CHN_CTRL_CHK   0x04
+#define SCHN_STAT_INTF_CTRL_CHK  0x02
+#define SCHN_STAT_CHAIN_CHECK    0x01
+
+/*
+ * architectured values for first sense byte
+ */
+#define SNS0_CMD_REJECT         0x80
+#define SNS_CMD_REJECT          SNS0_CMD_REJEC
+#define SNS0_INTERVENTION_REQ   0x40
+#define SNS0_BUS_OUT_CHECK      0x20
+#define SNS0_EQUIPMENT_CHECK    0x10
+#define SNS0_DATA_CHECK         0x08
+#define SNS0_OVERRUN            0x04
+#define SNS0_INCOMPL_DOMAIN     0x01
+
+/*
+ * architectured values for second sense byte
+ */
+#define SNS1_PERM_ERR           0x80
+#define SNS1_INV_TRACK_FORMAT   0x40
+#define SNS1_EOC                0x20
+#define SNS1_MESSAGE_TO_OPER    0x10
+#define SNS1_NO_REC_FOUND       0x08
+#define SNS1_FILE_PROTECTED     0x04
+#define SNS1_WRITE_INHIBITED    0x02
+#define SNS1_INPRECISE_END      0x01
+
+/*
+ * architectured values for third sense byte
+ */
+#define SNS2_REQ_INH_WRITE      0x80
+#define SNS2_CORRECTABLE        0x40
+#define SNS2_FIRST_LOG_ERR      0x20
+#define SNS2_ENV_DATA_PRESENT   0x10
+#define SNS2_INPRECISE_END      0x04
+
+/**
+ * struct ccw1 - channel command word
+ * @cmd_code: command code
+ * @flags: flags, like IDA adressing, etc.
+ * @count: byte count
+ * @cda: data address
+ *
+ * The ccw is the basic structure to build channel programs that perform
+ * operations with the device or the control unit. Only Format-1 channel
+ * command words are supported.
+ */
+struct ccw1 {
+        __u8  cmd_code;
+        __u8  flags;
+        __u16 count;
+        __u32 cda;
+} __attribute__ ((packed,aligned(8)));
+
+#define CCW_FLAG_DC             0x80
+#define CCW_FLAG_CC             0x40
+#define CCW_FLAG_SLI            0x20
+#define CCW_FLAG_SKIP           0x10
+#define CCW_FLAG_PCI            0x08
+#define CCW_FLAG_IDA            0x04
+#define CCW_FLAG_SUSPEND        0x02
+
+#define CCW_CMD_READ_IPL        0x02
+#define CCW_CMD_NOOP            0x03
+#define CCW_CMD_BASIC_SENSE     0x04
+#define CCW_CMD_TIC             0x08
+#define CCW_CMD_STLCK           0x14
+#define CCW_CMD_SENSE_PGID      0x34
+#define CCW_CMD_SUSPEND_RECONN  0x5B
+#define CCW_CMD_RDC             0x64
+#define CCW_CMD_RELEASE         0x94
+#define CCW_CMD_SET_PGID        0xAF
+#define CCW_CMD_SENSE_ID        0xE4
+#define CCW_CMD_DCTL            0xF3
+
+#define SENSE_MAX_COUNT         0x20
+
+/**
+ * struct erw - extended report word
+ * @res0: reserved
+ * @auth: authorization check
+ * @pvrf: path-verification-required flag
+ * @cpt: channel-path timeout
+ * @fsavf: failing storage address validity flag
+ * @cons: concurrent sense
+ * @scavf: secondary ccw address validity flag
+ * @fsaf: failing storage address format
+ * @scnt: sense count, if @cons == %1
+ * @res16: reserved
+ */
+struct erw {
+        __u32 res0  : 3;
+        __u32 auth  : 1;
+        __u32 pvrf  : 1;
+        __u32 cpt   : 1;
+        __u32 fsavf : 1;
+        __u32 cons  : 1;
+        __u32 scavf : 1;
+        __u32 fsaf  : 1;
+        __u32 scnt  : 6;
+        __u32 res16 : 16;
+} __attribute__ ((packed));
+
+/**
+ * struct sublog - subchannel logout area
+ * @res0: reserved
+ * @esf: extended status flags
+ * @lpum: last path used mask
+ * @arep: ancillary report
+ * @fvf: field-validity flags
+ * @sacc: storage access code
+ * @termc: termination code
+ * @devsc: device-status check
+ * @serr: secondary error
+ * @ioerr: i/o-error alert
+ * @seqc: sequence code
+ */
+struct sublog {
+        __u32 res0  : 1;
+        __u32 esf   : 7;
+        __u32 lpum  : 8;
+        __u32 arep  : 1;
+        __u32 fvf   : 5;
+        __u32 sacc  : 2;
+        __u32 termc : 2;
+        __u32 devsc : 1;
+        __u32 serr  : 1;
+        __u32 ioerr : 1;
+        __u32 seqc  : 3;
+} __attribute__ ((packed));
+
+/**
+ * struct esw0 - Format 0 Extended Status Word (ESW)
+ * @sublog: subchannel logout
+ * @erw: extended report word
+ * @faddr: failing storage address
+ * @saddr: secondary ccw address
+ */
+struct esw0 {
+        struct sublog sublog;
+        struct erw erw;
+        __u32  faddr[2];
+        __u32  saddr;
+} __attribute__ ((packed));
+
+/**
+ * struct esw1 - Format 1 Extended Status Word (ESW)
+ * @zero0: reserved zeros
+ * @lpum: last path used mask
+ * @zero16: reserved zeros
+ * @erw: extended report word
+ * @zeros: three fullwords of zeros
+ */
+struct esw1 {
+        __u8  zero0;
+        __u8  lpum;
+        __u16 zero16;
+        struct erw erw;
+        __u32 zeros[3];
+} __attribute__ ((packed));
+
+/**
+ * struct esw2 - Format 2 Extended Status Word (ESW)
+ * @zero0: reserved zeros
+ * @lpum: last path used mask
+ * @dcti: device-connect-time interval
+ * @erw: extended report word
+ * @zeros: three fullwords of zeros
+ */
+struct esw2 {
+        __u8  zero0;
+        __u8  lpum;
+        __u16 dcti;
+        struct erw erw;
+        __u32 zeros[3];
+} __attribute__ ((packed));
+
+/**
+ * struct esw3 - Format 3 Extended Status Word (ESW)
+ * @zero0: reserved zeros
+ * @lpum: last path used mask
+ * @res: reserved
+ * @erw: extended report word
+ * @zeros: three fullwords of zeros
+ */
+struct esw3 {
+        __u8  zero0;
+        __u8  lpum;
+        __u16 res;
+        struct erw erw;
+        __u32 zeros[3];
+} __attribute__ ((packed));
+
+/**
+ * struct irb - interruption response block
+ * @scsw: subchannel status word
+ * @esw: extened status word, 4 formats
+ * @ecw: extended control word
+ *
+ * The irb that is handed to the device driver when an interrupt occurs. For
+ * solicited interrupts, the common I/O layer already performs checks whether
+ * a field is valid; a field not being valid is always passed as %0.
+ * If a unit check occured, @ecw may contain sense data; this is retrieved
+ * by the common I/O layer itself if the device doesn't support concurrent
+ * sense (so that the device driver never needs to perform basic sene itself).
+ * For unsolicited interrupts, the irb is passed as-is (expect for sense data,
+ * if applicable).
+ */
+struct irb {
+        union scsw scsw;
+        union {
+                struct esw0 esw0;
+                struct esw1 esw1;
+                struct esw2 esw2;
+                struct esw3 esw3;
+        } esw;
+        __u8   ecw[32];
+} __attribute__ ((packed,aligned(4)));
+
+/**
+ * struct ciw - command information word  (CIW) layout
+ * @et: entry type
+ * @reserved: reserved bits
+ * @ct: command type
+ * @cmd: command code
+ * @count: command count
+ */
+struct ciw {
+        __u32 et       :  2;
+        __u32 reserved :  2;
+        __u32 ct       :  4;
+        __u32 cmd      :  8;
+        __u32 count    : 16;
+} __attribute__ ((packed));
+
+#define CIW_TYPE_RCD    0x0     /* read configuration data */
+#define CIW_TYPE_SII    0x1     /* set interface identifier */
+#define CIW_TYPE_RNI    0x2     /* read node identifier */
+
+/*
+ * Flags used as input parameters for do_IO()
+ */
+#define DOIO_ALLOW_SUSPEND       0x0001 /* allow for channel prog. suspend */
+#define DOIO_DENY_PREFETCH       0x0002 /* don't allow for CCW prefetch */
+#define DOIO_SUPPRESS_INTER      0x0004 /* suppress intermediate inter. */
+                                        /* ... for suspended CCWs */
+/* Device or subchannel gone. */
+#define CIO_GONE       0x0001
+/* No path to device. */
+#define CIO_NO_PATH    0x0002
+/* Device has appeared. */
+#define CIO_OPER       0x0004
+/* Sick revalidation of device. */
+#define CIO_REVALIDATE 0x0008
+
+/**
+ * struct ccw_dev_id - unique identifier for ccw devices
+ * @ssid: subchannel set id
+ * @devno: device number
+ *
+ * This structure is not directly based on any hardware structure. The
+ * hardware identifies a device by its device number and its subchannel,
+ * which is in turn identified by its id. In order to get a unique identifier
+ * for ccw devices across subchannel sets, @struct ccw_dev_id has been
+ * introduced.
+ */
+struct ccw_dev_id {
+        u8 ssid;
+        u16 devno;
+};
+
+/**
+ * ccw_device_id_is_equal() - compare two ccw_dev_ids
+ * @dev_id1: a ccw_dev_id
+ * @dev_id2: another ccw_dev_id
+ * Returns:
+ *  %1 if the two structures are equal field-by-field,
+ *  %0 if not.
+ * Context:
+ *  any
+ */
+static inline int ccw_dev_id_is_equal(struct ccw_dev_id *dev_id1,
+                                      struct ccw_dev_id *dev_id2)
+{
+        if ((dev_id1->ssid == dev_id2->ssid) &&
+            (dev_id1->devno == dev_id2->devno))
+                return 1;
+        return 0;
+}
+
+extern void wait_cons_dev(void);
+
+extern void css_schedule_reprobe(void);
+
+extern void reipl_ccw_dev(struct ccw_dev_id *id);
+
+struct cio_iplinfo {
+        u16 devno;
+        int is_qdio;
+};
+
+extern int cio_get_iplinfo(struct cio_iplinfo *iplinfo);
+
+/* Function from drivers/s390/cio/chsc.c */
+int chsc_sstpc(void *page, unsigned int op, u16 ctrl);
+int chsc_sstpi(void *page, void *result, size_t size);
+
+#endif
+
+#endif
diff --git a/arch/s390/include/asm/cmb.h b/arch/s390/include/asm/cmb.h
new file mode 100644
index 000000000000..50196857d27a
--- /dev/null
+++ b/arch/s390/include/asm/cmb.h
@@ -0,0 +1,58 @@
+#ifndef S390_CMB_H
+#define S390_CMB_H
+/**
+ * struct cmbdata - channel measurement block data for user space
+ * @size: size of the stored data
+ * @elapsed_time: time since last sampling
+ * @ssch_rsch_count: number of ssch and rsch
+ * @sample_count: number of samples
+ * @device_connect_time: time of device connect
+ * @function_pending_time: time of function pending
+ * @device_disconnect_time: time of device disconnect
+ * @control_unit_queuing_time: time of control unit queuing
+ * @device_active_only_time: time of device active only
+ * @device_busy_time: time of device busy (ext. format)
+ * @initial_command_response_time: initial command response time (ext. format)
+ *
+ * All values are stored as 64 bit for simplicity, especially
+ * in 32 bit emulation mode. All time values are normalized to
+ * nanoseconds.
+ * Currently, two formats are known, which differ by the size of
+ * this structure, i.e. the last two members are only set when
+ * the extended channel measurement facility (first shipped in
+ * z990 machines) is activated.
+ * Potentially, more fields could be added, which would result in a
+ * new ioctl number.
+ */
+struct cmbdata {
+        __u64 size;
+        __u64 elapsed_time;
+ /* basic and exended format: */
+        __u64 ssch_rsch_count;
+        __u64 sample_count;
+        __u64 device_connect_time;
+        __u64 function_pending_time;
+        __u64 device_disconnect_time;
+        __u64 control_unit_queuing_time;
+        __u64 device_active_only_time;
+ /* extended format only: */
+        __u64 device_busy_time;
+        __u64 initial_command_response_time;
+};
+
+/* enable channel measurement */
+#define BIODASDCMFENABLE        _IO(DASD_IOCTL_LETTER, 32)
+/* enable channel measurement */
+#define BIODASDCMFDISABLE       _IO(DASD_IOCTL_LETTER, 33)
+/* read channel measurement data */
+#define BIODASDREADALLCMB       _IOWR(DASD_IOCTL_LETTER, 33, struct cmbdata)
+
+#ifdef __KERNEL__
+struct ccw_device;
+extern int enable_cmf(struct ccw_device *cdev);
+extern int disable_cmf(struct ccw_device *cdev);
+extern u64 cmf_read(struct ccw_device *cdev, int index);
+extern int cmf_readall(struct ccw_device *cdev, struct cmbdata *data);
+
+#endif /* __KERNEL__ */
+#endif /* S390_CMB_H */
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
new file mode 100644
index 000000000000..de065b32381a
--- /dev/null
+++ b/arch/s390/include/asm/compat.h
@@ -0,0 +1,233 @@
+#ifndef _ASM_S390X_COMPAT_H
+#define _ASM_S390X_COMPAT_H
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+#include <linux/sched.h>
+
+#define PSW32_MASK_PER          0x40000000UL
+#define PSW32_MASK_DAT          0x04000000UL
+#define PSW32_MASK_IO           0x02000000UL
+#define PSW32_MASK_EXT          0x01000000UL
+#define PSW32_MASK_KEY          0x00F00000UL
+#define PSW32_MASK_MCHECK       0x00040000UL
+#define PSW32_MASK_WAIT         0x00020000UL
+#define PSW32_MASK_PSTATE       0x00010000UL
+#define PSW32_MASK_ASC          0x0000C000UL
+#define PSW32_MASK_CC           0x00003000UL
+#define PSW32_MASK_PM           0x00000f00UL
+
+#define PSW32_ADDR_AMODE31      0x80000000UL
+#define PSW32_ADDR_INSN         0x7FFFFFFFUL
+
+#define PSW32_BASE_BITS         0x00080000UL
+
+#define PSW32_ASC_PRIMARY       0x00000000UL
+#define PSW32_ASC_ACCREG        0x00004000UL
+#define PSW32_ASC_SECONDARY     0x00008000UL
+#define PSW32_ASC_HOME          0x0000C000UL
+
+#define PSW32_MASK_MERGE(CURRENT,NEW) \
+        (((CURRENT) & ~(PSW32_MASK_CC|PSW32_MASK_PM)) | \
+         ((NEW) & (PSW32_MASK_CC|PSW32_MASK_PM)))
+
+extern long psw32_user_bits;
+
+#define COMPAT_USER_HZ  100
+
+typedef u32             compat_size_t;
+typedef s32             compat_ssize_t;
+typedef s32             compat_time_t;
+typedef s32             compat_clock_t;
+typedef s32             compat_pid_t;
+typedef u16             __compat_uid_t;
+typedef u16             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
+typedef u16             compat_mode_t;
+typedef u32             compat_ino_t;
+typedef u16             compat_dev_t;
+typedef s32             compat_off_t;
+typedef s64             compat_loff_t;
+typedef u16             compat_nlink_t;
+typedef u16             compat_ipc_pid_t;
+typedef s32             compat_daddr_t;
+typedef u32             compat_caddr_t;
+typedef __kernel_fsid_t compat_fsid_t;
+typedef s32             compat_key_t;
+typedef s32             compat_timer_t;
+
+typedef s32             compat_int_t;
+typedef s32             compat_long_t;
+typedef s64             compat_s64;
+typedef u32             compat_uint_t;
+typedef u32             compat_ulong_t;
+typedef u64             compat_u64;
+
+struct compat_timespec {
+        compat_time_t   tv_sec;
+        s32             tv_nsec;
+};
+
+struct compat_timeval {
+        compat_time_t   tv_sec;
+        s32             tv_usec;
+};
+
+struct compat_stat {
+        compat_dev_t    st_dev;
+        u16             __pad1;
+        compat_ino_t    st_ino;
+        compat_mode_t   st_mode;
+        compat_nlink_t  st_nlink;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
+        compat_dev_t    st_rdev;
+        u16             __pad2;
+        u32             st_size;
+        u32             st_blksize;
+        u32             st_blocks;
+        u32             st_atime;
+        u32             st_atime_nsec;
+        u32             st_mtime;
+        u32             st_mtime_nsec;
+        u32             st_ctime;
+        u32             st_ctime_nsec;
+        u32             __unused4;
+        u32             __unused5;
+};
+
+struct compat_flock {
+        short           l_type;
+        short           l_whence;
+        compat_off_t    l_start;
+        compat_off_t    l_len;
+        compat_pid_t    l_pid;
+};
+
+#define F_GETLK64       12
+#define F_SETLK64       13
+#define F_SETLKW64      14    
+
+struct compat_flock64 {
+        short           l_type;
+        short           l_whence;
+        compat_loff_t   l_start;
+        compat_loff_t   l_len;
+        compat_pid_t    l_pid;
+};
+
+struct compat_statfs {
+        s32             f_type;
+        s32             f_bsize;
+        s32             f_blocks;
+        s32             f_bfree;
+        s32             f_bavail;
+        s32             f_files;
+        s32             f_ffree;
+        compat_fsid_t   f_fsid;
+        s32             f_namelen;
+        s32             f_frsize;
+        s32             f_spare[6];
+};
+
+#define COMPAT_RLIM_OLD_INFINITY        0x7fffffff
+#define COMPAT_RLIM_INFINITY            0xffffffff
+
+typedef u32             compat_old_sigset_t;    /* at least 32 bits */
+
+#define _COMPAT_NSIG            64
+#define _COMPAT_NSIG_BPW        32
+
+typedef u32             compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX        0x7fffffff
+#define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
+
+/*
+ * A pointer passed in from user mode. This should not
+ * be used for syscall parameters, just declare them
+ * as pointers because the syscall entry code will have
+ * appropriately converted them already.
+ */
+typedef u32             compat_uptr_t;
+
+static inline void __user *compat_ptr(compat_uptr_t uptr)
+{
+        return (void __user *)(unsigned long)(uptr & 0x7fffffffUL);
+}
+
+static inline compat_uptr_t ptr_to_compat(void __user *uptr)
+{
+        return (u32)(unsigned long)uptr;
+}
+
+static inline void __user *compat_alloc_user_space(long len)
+{
+        unsigned long stack;
+
+        stack = KSTK_ESP(current);
+        if (test_thread_flag(TIF_31BIT))
+                stack &= 0x7fffffffUL;
+        return (void __user *) (stack - len);
+}
+
+struct compat_ipc64_perm {
+        compat_key_t key;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
+        compat_mode_t mode;
+        unsigned short __pad1;
+        unsigned short seq;
+        unsigned short __pad2;
+        unsigned int __unused1;
+        unsigned int __unused2;
+};
+
+struct compat_semid64_ds {
+        struct compat_ipc64_perm sem_perm;
+        compat_time_t  sem_otime;
+        compat_ulong_t __pad1;
+        compat_time_t  sem_ctime;
+        compat_ulong_t __pad2;
+        compat_ulong_t sem_nsems;
+        compat_ulong_t __unused1;
+        compat_ulong_t __unused2;
+};
+
+struct compat_msqid64_ds {
+        struct compat_ipc64_perm msg_perm;
+        compat_time_t   msg_stime;
+        compat_ulong_t __pad1;
+        compat_time_t   msg_rtime;
+        compat_ulong_t __pad2;
+        compat_time_t   msg_ctime;
+        compat_ulong_t __pad3;
+        compat_ulong_t msg_cbytes;
+        compat_ulong_t msg_qnum;
+        compat_ulong_t msg_qbytes;
+        compat_pid_t   msg_lspid;
+        compat_pid_t   msg_lrpid;
+        compat_ulong_t __unused1;
+        compat_ulong_t __unused2;
+};
+
+struct compat_shmid64_ds {
+        struct compat_ipc64_perm shm_perm;
+        compat_size_t  shm_segsz;
+        compat_time_t  shm_atime;
+        compat_ulong_t __pad1;
+        compat_time_t  shm_dtime;
+        compat_ulong_t __pad2;
+        compat_time_t  shm_ctime;
+        compat_ulong_t __pad3;
+        compat_pid_t   shm_cpid;
+        compat_pid_t   shm_lpid;
+        compat_ulong_t shm_nattch;
+        compat_ulong_t __unused1;
+        compat_ulong_t __unused2;
+};
+#endif /* _ASM_S390X_COMPAT_H */
diff --git a/arch/s390/include/asm/cpcmd.h b/arch/s390/include/asm/cpcmd.h
new file mode 100644
index 000000000000..48a9eab16429
--- /dev/null
+++ b/arch/s390/include/asm/cpcmd.h
@@ -0,0 +1,34 @@
+/*
+ *  arch/s390/kernel/cpcmd.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *               Christian Borntraeger (cborntra@de.ibm.com),
+ */
+
+#ifndef _ASM_S390_CPCMD_H
+#define _ASM_S390_CPCMD_H
+
+/*
+ * the lowlevel function for cpcmd
+ * the caller of __cpcmd has to ensure that the response buffer is below 2 GB
+ */
+extern int __cpcmd(const char *cmd, char *response, int rlen, int *response_code);
+
+/*
+ * cpcmd is the in-kernel interface for issuing CP commands
+ *
+ * cmd:         null-terminated command string, max 240 characters
+ * response:    response buffer for VM's textual response
+ * rlen:        size of the response buffer, cpcmd will not exceed this size
+ *              but will cap the output, if its too large. Everything that
+ *              did not fit into the buffer will be silently dropped
+ * response_code: return pointer for VM's error code
+ * return value: the size of the response. The caller can check if the buffer
+ *              was large enough by comparing the return value and rlen
+ * NOTE: If the response buffer is not below 2 GB, cpcmd can sleep
+ */
+extern int cpcmd(const char *cmd, char *response, int rlen, int *response_code);
+
+#endif /* _ASM_S390_CPCMD_H */
diff --git a/arch/s390/include/asm/cpu.h b/arch/s390/include/asm/cpu.h
new file mode 100644
index 000000000000..e5a6a9ba3adf
--- /dev/null
+++ b/arch/s390/include/asm/cpu.h
@@ -0,0 +1,33 @@
+/*
+ *  include/asm-s390/cpu.h
+ *
+ *    Copyright IBM Corp. 2007
+ *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_CPU_H_
+#define _ASM_S390_CPU_H_
+
+#include <linux/types.h>
+#include <linux/percpu.h>
+#include <linux/spinlock.h>
+
+struct s390_idle_data {
+        spinlock_t lock;
+        unsigned int in_idle;
+        unsigned long long idle_count;
+        unsigned long long idle_enter;
+        unsigned long long idle_time;
+};
+
+DECLARE_PER_CPU(struct s390_idle_data, s390_idle);
+
+void s390_idle_leave(void);
+
+static inline void s390_idle_check(void)
+{
+        if ((&__get_cpu_var(s390_idle))->in_idle)
+                s390_idle_leave();
+}
+
+#endif /* _ASM_S390_CPU_H_ */
diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h
new file mode 100644
index 000000000000..133ce054fc89
--- /dev/null
+++ b/arch/s390/include/asm/cputime.h
@@ -0,0 +1,177 @@
+/*
+ *  include/asm-s390/cputime.h
+ *
+ *  (C) Copyright IBM Corp. 2004
+ *
+ *  Author: Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#ifndef _S390_CPUTIME_H
+#define _S390_CPUTIME_H
+
+#include <asm/div64.h>
+
+/* We want to use micro-second resolution. */
+
+typedef unsigned long long cputime_t;
+typedef unsigned long long cputime64_t;
+
+#ifndef __s390x__
+
+static inline unsigned int
+__div(unsigned long long n, unsigned int base)
+{
+        register_pair rp;
+
+        rp.pair = n >> 1;
+        asm ("dr %0,%1" : "+d" (rp) : "d" (base >> 1));
+        return rp.subreg.odd;
+}
+
+#else /* __s390x__ */
+
+static inline unsigned int
+__div(unsigned long long n, unsigned int base)
+{
+        return n / base;
+}
+
+#endif /* __s390x__ */
+
+#define cputime_zero                    (0ULL)
+#define cputime_max                     ((~0UL >> 1) - 1)
+#define cputime_add(__a, __b)           ((__a) +  (__b))
+#define cputime_sub(__a, __b)           ((__a) -  (__b))
+#define cputime_div(__a, __n) ({                \
+        unsigned long long __div = (__a);       \
+        do_div(__div,__n);                      \
+        __div;                                  \
+})
+#define cputime_halve(__a)              ((__a) >> 1)
+#define cputime_eq(__a, __b)            ((__a) == (__b))
+#define cputime_gt(__a, __b)            ((__a) >  (__b))
+#define cputime_ge(__a, __b)            ((__a) >= (__b))
+#define cputime_lt(__a, __b)            ((__a) <  (__b))
+#define cputime_le(__a, __b)            ((__a) <= (__b))
+#define cputime_to_jiffies(__ct)        (__div((__ct), 1000000 / HZ))
+#define cputime_to_scaled(__ct)         (__ct)
+#define jiffies_to_cputime(__hz)        ((cputime_t)(__hz) * (1000000 / HZ))
+
+#define cputime64_zero                  (0ULL)
+#define cputime64_add(__a, __b)         ((__a) + (__b))
+#define cputime_to_cputime64(__ct)      (__ct)
+
+static inline u64
+cputime64_to_jiffies64(cputime64_t cputime)
+{
+        do_div(cputime, 1000000 / HZ);
+        return cputime;
+}
+
+/*
+ * Convert cputime to milliseconds and back.
+ */
+static inline unsigned int
+cputime_to_msecs(const cputime_t cputime)
+{
+        return __div(cputime, 1000);
+}
+
+static inline cputime_t
+msecs_to_cputime(const unsigned int m)
+{
+        return (cputime_t) m * 1000;
+}
+
+/*
+ * Convert cputime to milliseconds and back.
+ */
+static inline unsigned int
+cputime_to_secs(const cputime_t cputime)
+{
+        return __div(cputime, 1000000);
+}
+
+static inline cputime_t
+secs_to_cputime(const unsigned int s)
+{
+        return (cputime_t) s * 1000000;
+}
+
+/*
+ * Convert cputime to timespec and back.
+ */
+static inline cputime_t
+timespec_to_cputime(const struct timespec *value)
+{
+        return value->tv_nsec / 1000 + (u64) value->tv_sec * 1000000;
+}
+
+static inline void
+cputime_to_timespec(const cputime_t cputime, struct timespec *value)
+{
+#ifndef __s390x__
+        register_pair rp;
+
+        rp.pair = cputime >> 1;
+        asm ("dr %0,%1" : "+d" (rp) : "d" (1000000 >> 1));
+        value->tv_nsec = rp.subreg.even * 1000;
+        value->tv_sec = rp.subreg.odd;
+#else
+        value->tv_nsec = (cputime % 1000000) * 1000;
+        value->tv_sec = cputime / 1000000;
+#endif
+}
+
+/*
+ * Convert cputime to timeval and back.
+ * Since cputime and timeval have the same resolution (microseconds)
+ * this is easy.
+ */
+static inline cputime_t
+timeval_to_cputime(const struct timeval *value)
+{
+        return value->tv_usec + (u64) value->tv_sec * 1000000;
+}
+
+static inline void
+cputime_to_timeval(const cputime_t cputime, struct timeval *value)
+{
+#ifndef __s390x__
+        register_pair rp;
+
+        rp.pair = cputime >> 1;
+        asm ("dr %0,%1" : "+d" (rp) : "d" (1000000 >> 1));
+        value->tv_usec = rp.subreg.even;
+        value->tv_sec = rp.subreg.odd;
+#else
+        value->tv_usec = cputime % 1000000;
+        value->tv_sec = cputime / 1000000;
+#endif
+}
+
+/*
+ * Convert cputime to clock and back.
+ */
+static inline clock_t
+cputime_to_clock_t(cputime_t cputime)
+{
+        return __div(cputime, 1000000 / USER_HZ);
+}
+
+static inline cputime_t
+clock_t_to_cputime(unsigned long x)
+{
+        return (cputime_t) x * (1000000 / USER_HZ);
+}
+
+/*
+ * Convert cputime64 to clock.
+ */
+static inline clock_t
+cputime64_to_clock_t(cputime64_t cputime)
+{
+       return __div(cputime, 1000000 / USER_HZ);
+}
+
+#endif /* _S390_CPUTIME_H */
diff --git a/arch/s390/include/asm/current.h b/arch/s390/include/asm/current.h
new file mode 100644
index 000000000000..83cf36cde2da
--- /dev/null
+++ b/arch/s390/include/asm/current.h
@@ -0,0 +1,23 @@
+/*
+ *  include/asm-s390/current.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/current.h"
+ */
+
+#ifndef _S390_CURRENT_H
+#define _S390_CURRENT_H
+
+#ifdef __KERNEL__
+#include <asm/lowcore.h>
+
+struct task_struct;
+
+#define current ((struct task_struct *const)S390_lowcore.current_task)
+
+#endif
+
+#endif /* !(_S390_CURRENT_H) */
diff --git a/arch/s390/include/asm/dasd.h b/arch/s390/include/asm/dasd.h
new file mode 100644
index 000000000000..3f002e13d024
--- /dev/null
+++ b/arch/s390/include/asm/dasd.h
@@ -0,0 +1,270 @@
+/* 
+ * File...........: linux/drivers/s390/block/dasd.c
+ * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
+ * Bugreports.to..: <Linux390@de.ibm.com>
+ * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000
+ *
+ * This file is the interface of the DASD device driver, which is exported to user space
+ * any future changes wrt the API will result in a change of the APIVERSION reported
+ * to userspace by the DASDAPIVER-ioctl
+ *
+ */
+
+#ifndef DASD_H
+#define DASD_H
+#include <linux/ioctl.h>
+
+#define DASD_IOCTL_LETTER 'D'
+
+#define DASD_API_VERSION 6
+
+/* 
+ * struct dasd_information2_t
+ * represents any data about the device, which is visible to userspace.
+ *  including foramt and featueres.
+ */
+typedef struct dasd_information2_t {
+        unsigned int devno;         /* S/390 devno */
+        unsigned int real_devno;    /* for aliases */
+        unsigned int schid;         /* S/390 subchannel identifier */
+        unsigned int cu_type  : 16; /* from SenseID */
+        unsigned int cu_model :  8; /* from SenseID */
+        unsigned int dev_type : 16; /* from SenseID */
+        unsigned int dev_model : 8; /* from SenseID */
+        unsigned int open_count; 
+        unsigned int req_queue_len; 
+        unsigned int chanq_len;     /* length of chanq */
+        char type[4];               /* from discipline.name, 'none' for unknown */
+        unsigned int status;        /* current device level */
+        unsigned int label_block;   /* where to find the VOLSER */
+        unsigned int FBA_layout;    /* fixed block size (like AIXVOL) */
+        unsigned int characteristics_size;
+        unsigned int confdata_size;
+        char characteristics[64];   /* from read_device_characteristics */
+        char configuration_data[256]; /* from read_configuration_data */
+        unsigned int format;          /* format info like formatted/cdl/ldl/... */
+        unsigned int features;        /* dasd features like 'ro',...            */
+        unsigned int reserved0;       /* reserved for further use ,...          */
+        unsigned int reserved1;       /* reserved for further use ,...          */
+        unsigned int reserved2;       /* reserved for further use ,...          */
+        unsigned int reserved3;       /* reserved for further use ,...          */
+        unsigned int reserved4;       /* reserved for further use ,...          */
+        unsigned int reserved5;       /* reserved for further use ,...          */
+        unsigned int reserved6;       /* reserved for further use ,...          */
+        unsigned int reserved7;       /* reserved for further use ,...          */
+} dasd_information2_t;
+
+/*
+ * values to be used for dasd_information_t.format
+ * 0x00: NOT formatted
+ * 0x01: Linux disc layout
+ * 0x02: Common disc layout
+ */
+#define DASD_FORMAT_NONE 0
+#define DASD_FORMAT_LDL  1
+#define DASD_FORMAT_CDL  2
+/*
+ * values to be used for dasd_information_t.features
+ * 0x00: default features
+ * 0x01: readonly (ro)
+ * 0x02: use diag discipline (diag)
+ * 0x04: set the device initially online (internal use only)
+ * 0x08: enable ERP related logging
+ */
+#define DASD_FEATURE_DEFAULT         0x00
+#define DASD_FEATURE_READONLY        0x01
+#define DASD_FEATURE_USEDIAG         0x02
+#define DASD_FEATURE_INITIAL_ONLINE  0x04
+#define DASD_FEATURE_ERPLOG          0x08
+
+#define DASD_PARTN_BITS 2
+
+/* 
+ * struct dasd_information_t
+ * represents any data about the data, which is visible to userspace
+ */
+typedef struct dasd_information_t {
+        unsigned int devno;         /* S/390 devno */
+        unsigned int real_devno;    /* for aliases */
+        unsigned int schid;         /* S/390 subchannel identifier */
+        unsigned int cu_type  : 16; /* from SenseID */
+        unsigned int cu_model :  8; /* from SenseID */
+        unsigned int dev_type : 16; /* from SenseID */
+        unsigned int dev_model : 8; /* from SenseID */
+        unsigned int open_count; 
+        unsigned int req_queue_len; 
+        unsigned int chanq_len;     /* length of chanq */
+        char type[4];               /* from discipline.name, 'none' for unknown */
+        unsigned int status;        /* current device level */
+        unsigned int label_block;   /* where to find the VOLSER */
+        unsigned int FBA_layout;    /* fixed block size (like AIXVOL) */
+        unsigned int characteristics_size;
+        unsigned int confdata_size;
+        char characteristics[64];   /* from read_device_characteristics */
+        char configuration_data[256]; /* from read_configuration_data */
+} dasd_information_t;
+
+/*
+ * Read Subsystem Data - Performance Statistics
+ */ 
+typedef struct dasd_rssd_perf_stats_t {
+        unsigned char  invalid:1;
+        unsigned char  format:3;
+        unsigned char  data_format:4;
+        unsigned char  unit_address;
+        unsigned short device_status;
+        unsigned int   nr_read_normal;
+        unsigned int   nr_read_normal_hits;
+        unsigned int   nr_write_normal;
+        unsigned int   nr_write_fast_normal_hits;
+        unsigned int   nr_read_seq;
+        unsigned int   nr_read_seq_hits;
+        unsigned int   nr_write_seq;
+        unsigned int   nr_write_fast_seq_hits;
+        unsigned int   nr_read_cache;
+        unsigned int   nr_read_cache_hits;
+        unsigned int   nr_write_cache;
+        unsigned int   nr_write_fast_cache_hits;
+        unsigned int   nr_inhibit_cache;
+        unsigned int   nr_bybass_cache;
+        unsigned int   nr_seq_dasd_to_cache;
+        unsigned int   nr_dasd_to_cache;
+        unsigned int   nr_cache_to_dasd;
+        unsigned int   nr_delayed_fast_write;
+        unsigned int   nr_normal_fast_write;
+        unsigned int   nr_seq_fast_write;
+        unsigned int   nr_cache_miss;
+        unsigned char  status2;
+        unsigned int   nr_quick_write_promotes;
+        unsigned char  reserved;
+        unsigned short ssid;
+        unsigned char  reseved2[96];
+} __attribute__((packed)) dasd_rssd_perf_stats_t;
+
+/* 
+ * struct profile_info_t
+ * holds the profinling information 
+ */
+typedef struct dasd_profile_info_t {
+        unsigned int dasd_io_reqs;       /* number of requests processed at all */
+        unsigned int dasd_io_sects;      /* number of sectors processed at all */
+        unsigned int dasd_io_secs[32];   /* histogram of request's sizes */
+        unsigned int dasd_io_times[32];  /* histogram of requests's times */
+        unsigned int dasd_io_timps[32];  /* histogram of requests's times per sector */
+        unsigned int dasd_io_time1[32];  /* histogram of time from build to start */
+        unsigned int dasd_io_time2[32];  /* histogram of time from start to irq */
+        unsigned int dasd_io_time2ps[32]; /* histogram of time from start to irq */
+        unsigned int dasd_io_time3[32];  /* histogram of time from irq to end */
+        unsigned int dasd_io_nr_req[32]; /* histogram of # of requests in chanq */
+} dasd_profile_info_t;
+
+/* 
+ * struct format_data_t
+ * represents all data necessary to format a dasd
+ */
+typedef struct format_data_t {
+        int start_unit; /* from track */
+        int stop_unit;  /* to track */
+        int blksize;    /* sectorsize */
+        int intensity;  
+} format_data_t;
+
+/*
+ * values to be used for format_data_t.intensity
+ * 0/8: normal format
+ * 1/9: also write record zero
+ * 3/11: also write home address
+ * 4/12: invalidate track
+ */
+#define DASD_FMT_INT_FMT_R0 1 /* write record zero */
+#define DASD_FMT_INT_FMT_HA 2 /* write home address, also set FMT_R0 ! */
+#define DASD_FMT_INT_INVAL  4 /* invalidate tracks */
+#define DASD_FMT_INT_COMPAT 8 /* use OS/390 compatible disk layout */
+
+
+/* 
+ * struct attrib_data_t
+ * represents the operation (cache) bits for the device.
+ * Used in DE to influence caching of the DASD.
+ */
+typedef struct attrib_data_t {
+        unsigned char operation:3;     /* cache operation mode */
+        unsigned char reserved:5;      /* cache operation mode */
+        __u16         nr_cyl;          /* no of cyliners for read ahaed */
+        __u8          reserved2[29];   /* for future use */
+} __attribute__ ((packed)) attrib_data_t;
+
+/* definition of operation (cache) bits within attributes of DE */
+#define DASD_NORMAL_CACHE  0x0
+#define DASD_BYPASS_CACHE  0x1
+#define DASD_INHIBIT_LOAD  0x2
+#define DASD_SEQ_ACCESS    0x3
+#define DASD_SEQ_PRESTAGE  0x4
+#define DASD_REC_ACCESS    0x5
+
+
+/********************************************************************************
+ * SECTION: Definition of IOCTLs
+ *
+ * Here ist how the ioctl-nr should be used:
+ *    0 -   31   DASD driver itself
+ *   32 -  239   still open
+ *  240 -  255   reserved for EMC 
+ *******************************************************************************/
+
+/* Disable the volume (for Linux) */
+#define BIODASDDISABLE _IO(DASD_IOCTL_LETTER,0) 
+/* Enable the volume (for Linux) */
+#define BIODASDENABLE  _IO(DASD_IOCTL_LETTER,1)  
+/* Issue a reserve/release command, rsp. */
+#define BIODASDRSRV    _IO(DASD_IOCTL_LETTER,2) /* reserve */
+#define BIODASDRLSE    _IO(DASD_IOCTL_LETTER,3) /* release */
+#define BIODASDSLCK    _IO(DASD_IOCTL_LETTER,4) /* steal lock */
+/* reset profiling information of a device */
+#define BIODASDPRRST   _IO(DASD_IOCTL_LETTER,5)
+/* Quiesce IO on device */
+#define BIODASDQUIESCE _IO(DASD_IOCTL_LETTER,6) 
+/* Resume IO on device */
+#define BIODASDRESUME  _IO(DASD_IOCTL_LETTER,7) 
+
+
+/* retrieve API version number */
+#define DASDAPIVER     _IOR(DASD_IOCTL_LETTER,0,int)
+/* Get information on a dasd device */
+#define BIODASDINFO    _IOR(DASD_IOCTL_LETTER,1,dasd_information_t)
+/* retrieve profiling information of a device */
+#define BIODASDPRRD    _IOR(DASD_IOCTL_LETTER,2,dasd_profile_info_t)
+/* Get information on a dasd device (enhanced) */
+#define BIODASDINFO2   _IOR(DASD_IOCTL_LETTER,3,dasd_information2_t)
+/* Performance Statistics Read */
+#define BIODASDPSRD    _IOR(DASD_IOCTL_LETTER,4,dasd_rssd_perf_stats_t)
+/* Get Attributes (cache operations) */
+#define BIODASDGATTR   _IOR(DASD_IOCTL_LETTER,5,attrib_data_t) 
+
+
+/* #define BIODASDFORMAT  _IOW(IOCTL_LETTER,0,format_data_t) , deprecated */
+#define BIODASDFMT     _IOW(DASD_IOCTL_LETTER,1,format_data_t) 
+/* Set Attributes (cache operations) */
+#define BIODASDSATTR   _IOW(DASD_IOCTL_LETTER,2,attrib_data_t) 
+
+
+#endif                          /* DASD_H */
+
+/*
+ * Overrides for Emacs so that we follow Linus's tabbing style.
+ * Emacs will notice this stuff at the end of the file and automatically
+ * adjust the settings for this buffer only.  This must remain at the end
+ * of the file.
+ * ---------------------------------------------------------------------------
+ * Local variables:
+ * c-indent-level: 4 
+ * c-brace-imaginary-offset: 0
+ * c-brace-offset: -4
+ * c-argdecl-indent: 4
+ * c-label-offset: -4
+ * c-continued-statement-offset: 4
+ * c-continued-brace-offset: 0
+ * indent-tabs-mode: nil
+ * tab-width: 8
+ * End:
+ */
diff --git a/arch/s390/include/asm/debug.h b/arch/s390/include/asm/debug.h
new file mode 100644
index 000000000000..9450ce6e32de
--- /dev/null
+++ b/arch/s390/include/asm/debug.h
@@ -0,0 +1,261 @@
+/*
+ *  include/asm-s390/debug.h
+ *   S/390 debug facility
+ *
+ *    Copyright (C) 1999, 2000 IBM Deutschland Entwicklung GmbH,
+ *                             IBM Corporation
+ */
+
+#ifndef DEBUG_H
+#define DEBUG_H
+
+#include <linux/fs.h>
+
+/* Note:
+ * struct __debug_entry must be defined outside of #ifdef __KERNEL__ 
+ * in order to allow a user program to analyze the 'raw'-view.
+ */
+
+struct __debug_entry{
+        union {
+                struct {
+                        unsigned long long clock:52;
+                        unsigned long long exception:1;
+                        unsigned long long level:3;
+                        unsigned long long cpuid:8;
+                } fields;
+
+                unsigned long long stck;
+        } id;
+        void* caller;
+} __attribute__((packed));
+
+
+#define __DEBUG_FEATURE_VERSION      2  /* version of debug feature */
+
+#ifdef __KERNEL__
+#include <linux/string.h>
+#include <linux/spinlock.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+
+#define DEBUG_MAX_LEVEL            6  /* debug levels range from 0 to 6 */
+#define DEBUG_OFF_LEVEL            -1 /* level where debug is switched off */
+#define DEBUG_FLUSH_ALL            -1 /* parameter to flush all areas */
+#define DEBUG_MAX_VIEWS            10 /* max number of views in proc fs */
+#define DEBUG_MAX_NAME_LEN         64 /* max length for a debugfs file name */
+#define DEBUG_DEFAULT_LEVEL        3  /* initial debug level */
+
+#define DEBUG_DIR_ROOT "s390dbf" /* name of debug root directory in proc fs */
+
+#define DEBUG_DATA(entry) (char*)(entry + 1) /* data is stored behind */
+                                             /* the entry information */
+
+typedef struct __debug_entry debug_entry_t;
+
+struct debug_view;
+
+typedef struct debug_info {     
+        struct debug_info* next;
+        struct debug_info* prev;
+        atomic_t ref_count;
+        spinlock_t lock;                        
+        int level;
+        int nr_areas;
+        int pages_per_area;
+        int buf_size;
+        int entry_size; 
+        debug_entry_t*** areas;
+        int active_area;
+        int *active_pages;
+        int *active_entries;
+        struct dentry* debugfs_root_entry;
+        struct dentry* debugfs_entries[DEBUG_MAX_VIEWS];
+        struct debug_view* views[DEBUG_MAX_VIEWS];      
+        char name[DEBUG_MAX_NAME_LEN];
+        mode_t mode;
+} debug_info_t;
+
+typedef int (debug_header_proc_t) (debug_info_t* id,
+                                   struct debug_view* view,
+                                   int area,
+                                   debug_entry_t* entry,
+                                   char* out_buf);
+
+typedef int (debug_format_proc_t) (debug_info_t* id,
+                                   struct debug_view* view, char* out_buf,
+                                   const char* in_buf);
+typedef int (debug_prolog_proc_t) (debug_info_t* id,
+                                   struct debug_view* view,
+                                   char* out_buf);
+typedef int (debug_input_proc_t) (debug_info_t* id,
+                                  struct debug_view* view,
+                                  struct file* file,
+                                  const char __user *user_buf,
+                                  size_t in_buf_size, loff_t* offset);
+
+int debug_dflt_header_fn(debug_info_t* id, struct debug_view* view,
+                         int area, debug_entry_t* entry, char* out_buf);                                                
+                                
+struct debug_view {
+        char name[DEBUG_MAX_NAME_LEN];
+        debug_prolog_proc_t* prolog_proc;
+        debug_header_proc_t* header_proc;
+        debug_format_proc_t* format_proc;
+        debug_input_proc_t*  input_proc;
+        void*                private_data;
+};
+
+extern struct debug_view debug_hex_ascii_view;
+extern struct debug_view debug_raw_view;
+extern struct debug_view debug_sprintf_view;
+
+/* do NOT use the _common functions */
+
+debug_entry_t* debug_event_common(debug_info_t* id, int level, 
+                                  const void* data, int length);
+
+debug_entry_t* debug_exception_common(debug_info_t* id, int level, 
+                                      const void* data, int length);
+
+/* Debug Feature API: */
+
+debug_info_t *debug_register(const char *name, int pages, int nr_areas,
+                             int buf_size);
+
+debug_info_t *debug_register_mode(const char *name, int pages, int nr_areas,
+                                  int buf_size, mode_t mode, uid_t uid,
+                                  gid_t gid);
+
+void debug_unregister(debug_info_t* id);
+
+void debug_set_level(debug_info_t* id, int new_level);
+
+void debug_stop_all(void);
+
+static inline debug_entry_t*
+debug_event(debug_info_t* id, int level, void* data, int length)
+{
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_event_common(id,level,data,length);
+}
+
+static inline debug_entry_t*
+debug_int_event(debug_info_t* id, int level, unsigned int tag)
+{
+        unsigned int t=tag;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_event_common(id,level,&t,sizeof(unsigned int));
+}
+
+static inline debug_entry_t *
+debug_long_event (debug_info_t* id, int level, unsigned long tag)
+{
+        unsigned long t=tag;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_event_common(id,level,&t,sizeof(unsigned long));
+}
+
+static inline debug_entry_t*
+debug_text_event(debug_info_t* id, int level, const char* txt)
+{
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_event_common(id,level,txt,strlen(txt));
+}
+
+extern debug_entry_t *
+debug_sprintf_event(debug_info_t* id,int level,char *string,...)
+        __attribute__ ((format(printf, 3, 4)));
+
+
+static inline debug_entry_t*
+debug_exception(debug_info_t* id, int level, void* data, int length)
+{
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_exception_common(id,level,data,length);
+}
+
+static inline debug_entry_t*
+debug_int_exception(debug_info_t* id, int level, unsigned int tag)
+{
+        unsigned int t=tag;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_exception_common(id,level,&t,sizeof(unsigned int));
+}
+
+static inline debug_entry_t *
+debug_long_exception (debug_info_t* id, int level, unsigned long tag)
+{
+        unsigned long t=tag;
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_exception_common(id,level,&t,sizeof(unsigned long));
+}
+
+static inline debug_entry_t*
+debug_text_exception(debug_info_t* id, int level, const char* txt)
+{
+        if ((!id) || (level > id->level) || (id->pages_per_area == 0))
+                return NULL;
+        return debug_exception_common(id,level,txt,strlen(txt));
+}
+
+
+extern debug_entry_t *
+debug_sprintf_exception(debug_info_t* id,int level,char *string,...)
+        __attribute__ ((format(printf, 3, 4)));
+
+int debug_register_view(debug_info_t* id, struct debug_view* view);
+int debug_unregister_view(debug_info_t* id, struct debug_view* view);
+
+/*
+   define the debug levels:
+   - 0 No debugging output to console or syslog
+   - 1 Log internal errors to syslog, ignore check conditions 
+   - 2 Log internal errors and check conditions to syslog
+   - 3 Log internal errors to console, log check conditions to syslog
+   - 4 Log internal errors and check conditions to console
+   - 5 panic on internal errors, log check conditions to console
+   - 6 panic on both, internal errors and check conditions
+ */
+
+#ifndef DEBUG_LEVEL
+#define DEBUG_LEVEL 4
+#endif
+
+#define INTERNAL_ERRMSG(x,y...) "E" __FILE__ "%d: " x, __LINE__, y
+#define INTERNAL_WRNMSG(x,y...) "W" __FILE__ "%d: " x, __LINE__, y
+#define INTERNAL_INFMSG(x,y...) "I" __FILE__ "%d: " x, __LINE__, y
+#define INTERNAL_DEBMSG(x,y...) "D" __FILE__ "%d: " x, __LINE__, y
+
+#if DEBUG_LEVEL > 0
+#define PRINT_DEBUG(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
+#define PRINT_INFO(x...) printk ( KERN_INFO PRINTK_HEADER x )
+#define PRINT_WARN(x...) printk ( KERN_WARNING PRINTK_HEADER x )
+#define PRINT_ERR(x...) printk ( KERN_ERR PRINTK_HEADER x )
+#define PRINT_FATAL(x...) panic ( PRINTK_HEADER x )
+#else
+#define PRINT_DEBUG(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
+#define PRINT_INFO(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
+#define PRINT_WARN(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
+#define PRINT_ERR(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
+#define PRINT_FATAL(x...) printk ( KERN_DEBUG PRINTK_HEADER x )
+#endif                          /* DASD_DEBUG */
+
+#undef DEBUG_MALLOC
+#ifdef DEBUG_MALLOC
+void *b;
+#define kmalloc(x...) (PRINT_INFO(" kmalloc %p\n",b=kmalloc(x)),b)
+#define kfree(x) PRINT_INFO(" kfree %p\n",x);kfree(x)
+#define get_zeroed_page(x...) (PRINT_INFO(" gfp %p\n",b=get_zeroed_page(x)),b)
+#define __get_free_pages(x...) (PRINT_INFO(" gfps %p\n",b=__get_free_pages(x)),b)
+#endif                          /* DEBUG_MALLOC */
+
+#endif                          /* __KERNEL__ */
+#endif                          /* DEBUG_H */
diff --git a/arch/s390/include/asm/delay.h b/arch/s390/include/asm/delay.h
new file mode 100644
index 000000000000..78357314c450
--- /dev/null
+++ b/arch/s390/include/asm/delay.h
@@ -0,0 +1,22 @@
+/*
+ *  include/asm-s390/delay.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/delay.h"
+ *    Copyright (C) 1993 Linus Torvalds
+ *
+ *  Delay routines calling functions in arch/s390/lib/delay.c
+ */
+ 
+#ifndef _S390_DELAY_H
+#define _S390_DELAY_H
+
+extern void __udelay(unsigned long usecs);
+extern void __delay(unsigned long loops);
+
+#define udelay(n) __udelay(n)
+
+#endif /* defined(_S390_DELAY_H) */
diff --git a/arch/s390/include/asm/device.h b/arch/s390/include/asm/device.h
new file mode 100644
index 000000000000..d8f9872b0e2d
--- /dev/null
+++ b/arch/s390/include/asm/device.h
@@ -0,0 +1,7 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#include <asm-generic/device.h>
+
diff --git a/arch/s390/include/asm/diag.h b/arch/s390/include/asm/diag.h
new file mode 100644
index 000000000000..72b2e2f2d32d
--- /dev/null
+++ b/arch/s390/include/asm/diag.h
@@ -0,0 +1,39 @@
+/*
+ * s390 diagnose functions
+ *
+ * Copyright IBM Corp. 2007
+ * Author(s): Michael Holzheu <holzheu@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_DIAG_H
+#define _ASM_S390_DIAG_H
+
+/*
+ * Diagnose 10: Release pages
+ */
+extern void diag10(unsigned long addr);
+
+/*
+ * Diagnose 14: Input spool file manipulation
+ */
+extern int diag14(unsigned long rx, unsigned long ry1, unsigned long subcode);
+
+/*
+ * Diagnose 210: Get information about a virtual device
+ */
+struct diag210 {
+        u16 vrdcdvno;   /* device number (input) */
+        u16 vrdclen;    /* data block length (input) */
+        u8 vrdcvcla;    /* virtual device class (output) */
+        u8 vrdcvtyp;    /* virtual device type (output) */
+        u8 vrdcvsta;    /* virtual device status (output) */
+        u8 vrdcvfla;    /* virtual device flags (output) */
+        u8 vrdcrccl;    /* real device class (output) */
+        u8 vrdccrty;    /* real device type (output) */
+        u8 vrdccrmd;    /* real device model (output) */
+        u8 vrdccrft;    /* real device feature (output) */
+} __attribute__((packed, aligned(4)));
+
+extern int diag210(struct diag210 *addr);
+
+#endif /* _ASM_S390_DIAG_H */
diff --git a/arch/s390/include/asm/div64.h b/arch/s390/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/s390/include/asm/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/arch/s390/include/asm/dma.h b/arch/s390/include/asm/dma.h
new file mode 100644
index 000000000000..7425c6af6cd4
--- /dev/null
+++ b/arch/s390/include/asm/dma.h
@@ -0,0 +1,16 @@
+/*
+ *  include/asm-s390/dma.h
+ *
+ *  S390 version
+ */
+
+#ifndef _ASM_DMA_H
+#define _ASM_DMA_H
+
+#include <asm/io.h>             /* need byte IO */
+
+#define MAX_DMA_ADDRESS         0x80000000
+
+#define free_dma(x)     do { } while (0)
+
+#endif /* _ASM_DMA_H */
diff --git a/arch/s390/include/asm/ebcdic.h b/arch/s390/include/asm/ebcdic.h
new file mode 100644
index 000000000000..7f6f641d32f4
--- /dev/null
+++ b/arch/s390/include/asm/ebcdic.h
@@ -0,0 +1,49 @@
+/*
+ *  include/asm-s390/ebcdic.h
+ *    EBCDIC -> ASCII, ASCII -> EBCDIC conversion routines.
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#ifndef _EBCDIC_H
+#define _EBCDIC_H
+
+#ifndef _S390_TYPES_H
+#include <types.h>
+#endif
+
+extern __u8 _ascebc_500[256];   /* ASCII -> EBCDIC 500 conversion table */
+extern __u8 _ebcasc_500[256];   /* EBCDIC 500 -> ASCII conversion table */
+extern __u8 _ascebc[256];   /* ASCII -> EBCDIC conversion table */
+extern __u8 _ebcasc[256];   /* EBCDIC -> ASCII conversion table */
+extern __u8 _ebc_tolower[256]; /* EBCDIC -> lowercase */
+extern __u8 _ebc_toupper[256]; /* EBCDIC -> uppercase */
+
+static inline void
+codepage_convert(const __u8 *codepage, volatile __u8 * addr, unsigned long nr)
+{
+        if (nr-- <= 0)
+                return;
+        asm volatile(
+                "       bras    1,1f\n"
+                "       tr      0(1,%0),0(%2)\n"
+                "0:     tr      0(256,%0),0(%2)\n"
+                "       la      %0,256(%0)\n"
+                "1:     ahi     %1,-256\n"
+                "       jnm     0b\n"
+                "       ex      %1,0(1)"
+                : "+&a" (addr), "+&a" (nr)
+                : "a" (codepage) : "cc", "memory", "1");
+}
+
+#define ASCEBC(addr,nr) codepage_convert(_ascebc, addr, nr)
+#define EBCASC(addr,nr) codepage_convert(_ebcasc, addr, nr)
+#define ASCEBC_500(addr,nr) codepage_convert(_ascebc_500, addr, nr)
+#define EBCASC_500(addr,nr) codepage_convert(_ebcasc_500, addr, nr)
+#define EBC_TOLOWER(addr,nr) codepage_convert(_ebc_tolower, addr, nr)
+#define EBC_TOUPPER(addr,nr) codepage_convert(_ebc_toupper, addr, nr)
+
+#endif
+
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h
new file mode 100644
index 000000000000..3cad56923815
--- /dev/null
+++ b/arch/s390/include/asm/elf.h
@@ -0,0 +1,196 @@
+/*
+ *  include/asm-s390/elf.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/elf.h"
+ */
+
+#ifndef __ASMS390_ELF_H
+#define __ASMS390_ELF_H
+
+/* s390 relocations defined by the ABIs */
+#define R_390_NONE              0       /* No reloc.  */
+#define R_390_8                 1       /* Direct 8 bit.  */
+#define R_390_12                2       /* Direct 12 bit.  */
+#define R_390_16                3       /* Direct 16 bit.  */
+#define R_390_32                4       /* Direct 32 bit.  */
+#define R_390_PC32              5       /* PC relative 32 bit.  */
+#define R_390_GOT12             6       /* 12 bit GOT offset.  */
+#define R_390_GOT32             7       /* 32 bit GOT offset.  */
+#define R_390_PLT32             8       /* 32 bit PC relative PLT address.  */
+#define R_390_COPY              9       /* Copy symbol at runtime.  */
+#define R_390_GLOB_DAT          10      /* Create GOT entry.  */
+#define R_390_JMP_SLOT          11      /* Create PLT entry.  */
+#define R_390_RELATIVE          12      /* Adjust by program base.  */
+#define R_390_GOTOFF32          13      /* 32 bit offset to GOT.         */
+#define R_390_GOTPC             14      /* 32 bit PC rel. offset to GOT.  */
+#define R_390_GOT16             15      /* 16 bit GOT offset.  */
+#define R_390_PC16              16      /* PC relative 16 bit.  */
+#define R_390_PC16DBL           17      /* PC relative 16 bit shifted by 1.  */
+#define R_390_PLT16DBL          18      /* 16 bit PC rel. PLT shifted by 1.  */
+#define R_390_PC32DBL           19      /* PC relative 32 bit shifted by 1.  */
+#define R_390_PLT32DBL          20      /* 32 bit PC rel. PLT shifted by 1.  */
+#define R_390_GOTPCDBL          21      /* 32 bit PC rel. GOT shifted by 1.  */
+#define R_390_64                22      /* Direct 64 bit.  */
+#define R_390_PC64              23      /* PC relative 64 bit.  */
+#define R_390_GOT64             24      /* 64 bit GOT offset.  */
+#define R_390_PLT64             25      /* 64 bit PC relative PLT address.  */
+#define R_390_GOTENT            26      /* 32 bit PC rel. to GOT entry >> 1. */
+#define R_390_GOTOFF16          27      /* 16 bit offset to GOT. */
+#define R_390_GOTOFF64          28      /* 64 bit offset to GOT. */
+#define R_390_GOTPLT12          29      /* 12 bit offset to jump slot.  */
+#define R_390_GOTPLT16          30      /* 16 bit offset to jump slot.  */
+#define R_390_GOTPLT32          31      /* 32 bit offset to jump slot.  */
+#define R_390_GOTPLT64          32      /* 64 bit offset to jump slot.  */
+#define R_390_GOTPLTENT         33      /* 32 bit rel. offset to jump slot.  */
+#define R_390_PLTOFF16          34      /* 16 bit offset from GOT to PLT. */
+#define R_390_PLTOFF32          35      /* 32 bit offset from GOT to PLT. */
+#define R_390_PLTOFF64          36      /* 16 bit offset from GOT to PLT. */
+#define R_390_TLS_LOAD          37      /* Tag for load insn in TLS code. */
+#define R_390_TLS_GDCALL        38      /* Tag for function call in general
+                                           dynamic TLS code.  */
+#define R_390_TLS_LDCALL        39      /* Tag for function call in local
+                                           dynamic TLS code.  */
+#define R_390_TLS_GD32          40      /* Direct 32 bit for general dynamic
+                                           thread local data.  */
+#define R_390_TLS_GD64          41      /* Direct 64 bit for general dynamic
+                                           thread local data.  */
+#define R_390_TLS_GOTIE12       42      /* 12 bit GOT offset for static TLS
+                                           block offset.  */
+#define R_390_TLS_GOTIE32       43      /* 32 bit GOT offset for static TLS
+                                           block offset.  */
+#define R_390_TLS_GOTIE64       44      /* 64 bit GOT offset for static TLS
+                                           block offset.  */
+#define R_390_TLS_LDM32         45      /* Direct 32 bit for local dynamic
+                                           thread local data in LD code.  */
+#define R_390_TLS_LDM64         46      /* Direct 64 bit for local dynamic
+                                           thread local data in LD code.  */
+#define R_390_TLS_IE32          47      /* 32 bit address of GOT entry for
+                                           negated static TLS block offset.  */
+#define R_390_TLS_IE64          48      /* 64 bit address of GOT entry for
+                                           negated static TLS block offset.  */
+#define R_390_TLS_IEENT         49      /* 32 bit rel. offset to GOT entry for
+                                           negated static TLS block offset.  */
+#define R_390_TLS_LE32          50      /* 32 bit negated offset relative to
+                                           static TLS block.  */
+#define R_390_TLS_LE64          51      /* 64 bit negated offset relative to
+                                           static TLS block.  */
+#define R_390_TLS_LDO32         52      /* 32 bit offset relative to TLS
+                                           block.  */
+#define R_390_TLS_LDO64         53      /* 64 bit offset relative to TLS
+                                           block.  */
+#define R_390_TLS_DTPMOD        54      /* ID of module containing symbol.  */
+#define R_390_TLS_DTPOFF        55      /* Offset in TLS block.  */
+#define R_390_TLS_TPOFF         56      /* Negate offset in static TLS
+                                           block.  */
+#define R_390_20                57      /* Direct 20 bit.  */
+#define R_390_GOT20             58      /* 20 bit GOT offset.  */
+#define R_390_GOTPLT20          59      /* 20 bit offset to jump slot.  */
+#define R_390_TLS_GOTIE20       60      /* 20 bit GOT offset for static TLS
+                                           block offset.  */
+/* Keep this the last entry.  */
+#define R_390_NUM       61
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#ifndef __s390x__
+#define ELF_CLASS       ELFCLASS32
+#else /* __s390x__ */
+#define ELF_CLASS       ELFCLASS64
+#endif /* __s390x__ */
+#define ELF_DATA        ELFDATA2MSB
+#define ELF_ARCH        EM_S390
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+typedef s390_fp_regs elf_fpregset_t;
+typedef s390_regs elf_gregset_t;
+
+typedef s390_fp_regs compat_elf_fpregset_t;
+typedef s390_compat_regs compat_elf_gregset_t;
+
+#include <linux/sched.h>        /* for task_struct */
+#include <asm/system.h>         /* for save_access_regs */
+#include <asm/mmu_context.h>
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) \
+        (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
+         && (x)->e_ident[EI_CLASS] == ELF_CLASS) 
+#define compat_elf_check_arch(x) \
+        (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
+         && (x)->e_ident[EI_CLASS] == ELF_CLASS)
+#define compat_start_thread     start_thread31
+
+/* For SVR4/S390 the function pointer to be registered with `atexit` is
+   passed in R14. */
+#define ELF_PLAT_INIT(_r, load_addr) \
+        do { \
+                _r->gprs[14] = 0; \
+        } while (0)
+
+#define CORE_DUMP_USE_REGSET
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       4096
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+#define ELF_ET_DYN_BASE         (STACK_TOP / 3 * 2)
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this CPU supports. */
+
+extern unsigned long elf_hwcap;
+#define ELF_HWCAP (elf_hwcap)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.
+
+   For the moment, we have only optimizations for the Intel generations,
+   but that could change... */
+
+#define ELF_PLATFORM_SIZE 8
+extern char elf_platform[];
+#define ELF_PLATFORM (elf_platform)
+
+#ifndef __s390x__
+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#else /* __s390x__ */
+#define SET_PERSONALITY(ex, ibcs2)                      \
+do {                                                    \
+        if (ibcs2)                                      \
+                set_personality(PER_SVR4);              \
+        else if (current->personality != PER_LINUX32)   \
+                set_personality(PER_LINUX);             \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)       \
+                set_thread_flag(TIF_31BIT);             \
+        else                                            \
+                clear_thread_flag(TIF_31BIT);           \
+} while (0)
+#endif /* __s390x__ */
+
+/*
+ * An executable for which elf_read_implies_exec() returns TRUE will
+ * have the READ_IMPLIES_EXEC personality flag set automatically.
+ */
+#define elf_read_implies_exec(ex, executable_stack)     \
+({                                                      \
+        if (current->mm->context.noexec &&              \
+            executable_stack != EXSTACK_DISABLE_X)      \
+                disable_noexec(current->mm, current);   \
+        current->mm->context.noexec == 0;               \
+})
+
+#endif
diff --git a/arch/s390/include/asm/emergency-restart.h b/arch/s390/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/s390/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/s390/include/asm/errno.h b/arch/s390/include/asm/errno.h
new file mode 100644
index 000000000000..e41d5b37c4d6
--- /dev/null
+++ b/arch/s390/include/asm/errno.h
@@ -0,0 +1,13 @@
+/*
+ *  include/asm-s390/errno.h
+ *
+ *  S390 version
+ *
+ */
+
+#ifndef _S390_ERRNO_H
+#define _S390_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#endif
diff --git a/arch/s390/include/asm/etr.h b/arch/s390/include/asm/etr.h
new file mode 100644
index 000000000000..80ef58c61970
--- /dev/null
+++ b/arch/s390/include/asm/etr.h
@@ -0,0 +1,258 @@
+/*
+ *  include/asm-s390/etr.h
+ *
+ *  Copyright IBM Corp. 2006
+ *  Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ */
+#ifndef __S390_ETR_H
+#define __S390_ETR_H
+
+/* ETR attachment control register */
+struct etr_eacr {
+        unsigned int e0         : 1;    /* port 0 stepping control */
+        unsigned int e1         : 1;    /* port 1 stepping control */
+        unsigned int _pad0      : 5;    /* must be 00100 */
+        unsigned int dp         : 1;    /* data port control */
+        unsigned int p0         : 1;    /* port 0 change recognition control */
+        unsigned int p1         : 1;    /* port 1 change recognition control */
+        unsigned int _pad1      : 3;    /* must be 000 */
+        unsigned int ea         : 1;    /* ETR alert control */
+        unsigned int es         : 1;    /* ETR sync check control */
+        unsigned int sl         : 1;    /* switch to local control */
+} __attribute__ ((packed));
+
+/* Port state returned by steai */
+enum etr_psc {
+        etr_psc_operational = 0,
+        etr_psc_semi_operational = 1,
+        etr_psc_protocol_error =  4,
+        etr_psc_no_symbols = 8,
+        etr_psc_no_signal = 12,
+        etr_psc_pps_mode = 13
+};
+
+/* Logical port state returned by stetr */
+enum etr_lpsc {
+        etr_lpsc_operational_step = 0,
+        etr_lpsc_operational_alt = 1,
+        etr_lpsc_semi_operational = 2,
+        etr_lpsc_protocol_error =  4,
+        etr_lpsc_no_symbol_sync = 8,
+        etr_lpsc_no_signal = 12,
+        etr_lpsc_pps_mode = 13
+};
+
+/* ETR status words */
+struct etr_esw {
+        struct etr_eacr eacr;           /* attachment control register */
+        unsigned int y          : 1;    /* stepping mode */
+        unsigned int _pad0      : 5;    /* must be 00000 */
+        unsigned int p          : 1;    /* stepping port number */
+        unsigned int q          : 1;    /* data port number */
+        unsigned int psc0       : 4;    /* port 0 state code */
+        unsigned int psc1       : 4;    /* port 1 state code */
+} __attribute__ ((packed));
+
+/* Second level data register status word */
+struct etr_slsw {
+        unsigned int vv1        : 1;    /* copy of validity bit data frame 1 */
+        unsigned int vv2        : 1;    /* copy of validity bit data frame 2 */
+        unsigned int vv3        : 1;    /* copy of validity bit data frame 3 */
+        unsigned int vv4        : 1;    /* copy of validity bit data frame 4 */
+        unsigned int _pad0      : 19;   /* must by all zeroes */
+        unsigned int n          : 1;    /* EAF port number */
+        unsigned int v1         : 1;    /* validity bit ETR data frame 1 */
+        unsigned int v2         : 1;    /* validity bit ETR data frame 2 */
+        unsigned int v3         : 1;    /* validity bit ETR data frame 3 */
+        unsigned int v4         : 1;    /* validity bit ETR data frame 4 */
+        unsigned int _pad1      : 4;    /* must be 0000 */
+} __attribute__ ((packed));
+
+/* ETR data frames */
+struct etr_edf1 {
+        unsigned int u          : 1;    /* untuned bit */
+        unsigned int _pad0      : 1;    /* must be 0 */
+        unsigned int r          : 1;    /* service request bit */
+        unsigned int _pad1      : 4;    /* must be 0000 */
+        unsigned int a          : 1;    /* time adjustment bit */
+        unsigned int net_id     : 8;    /* ETR network id */
+        unsigned int etr_id     : 8;    /* id of ETR which sends data frames */
+        unsigned int etr_pn     : 8;    /* port number of ETR output port */
+} __attribute__ ((packed));
+
+struct etr_edf2 {
+        unsigned int etv        : 32;   /* Upper 32 bits of TOD. */
+} __attribute__ ((packed));
+
+struct etr_edf3 {
+        unsigned int rc         : 8;    /* failure reason code */
+        unsigned int _pad0      : 3;    /* must be 000 */
+        unsigned int c          : 1;    /* ETR coupled bit */
+        unsigned int tc         : 4;    /* ETR type code */
+        unsigned int blto       : 8;    /* biased local time offset */
+                                        /* (blto - 128) * 15 = minutes */
+        unsigned int buo        : 8;    /* biased utc offset */
+                                        /* (buo - 128) = leap seconds */
+} __attribute__ ((packed));
+
+struct etr_edf4 {
+        unsigned int ed         : 8;    /* ETS device dependent data */
+        unsigned int _pad0      : 1;    /* must be 0 */
+        unsigned int buc        : 5;    /* biased ut1 correction */
+                                        /* (buc - 16) * 0.1 seconds */
+        unsigned int em         : 6;    /* ETS error magnitude */
+        unsigned int dc         : 6;    /* ETS drift code */
+        unsigned int sc         : 6;    /* ETS steering code */
+} __attribute__ ((packed));
+
+/*
+ * ETR attachment information block, two formats
+ * format 1 has 4 reserved words with a size of 64 bytes
+ * format 2 has 16 reserved words with a size of 96 bytes
+ */
+struct etr_aib {
+        struct etr_esw esw;
+        struct etr_slsw slsw;
+        unsigned long long tsp;
+        struct etr_edf1 edf1;
+        struct etr_edf2 edf2;
+        struct etr_edf3 edf3;
+        struct etr_edf4 edf4;
+        unsigned int reserved[16];
+} __attribute__ ((packed,aligned(8)));
+
+/* ETR interruption parameter */
+struct etr_irq_parm {
+        unsigned int _pad0      : 8;
+        unsigned int pc0        : 1;    /* port 0 state change */
+        unsigned int pc1        : 1;    /* port 1 state change */
+        unsigned int _pad1      : 3;
+        unsigned int eai        : 1;    /* ETR alert indication */
+        unsigned int _pad2      : 18;
+} __attribute__ ((packed));
+
+/* Query TOD offset result */
+struct etr_ptff_qto {
+        unsigned long long physical_clock;
+        unsigned long long tod_offset;
+        unsigned long long logical_tod_offset;
+        unsigned long long tod_epoch_difference;
+} __attribute__ ((packed));
+
+/* Inline assembly helper functions */
+static inline int etr_setr(struct etr_eacr *ctrl)
+{
+        int rc = -ENOSYS;
+
+        asm volatile(
+                "       .insn   s,0xb2160000,0(%2)\n"
+                "0:     la      %0,0\n"
+                "1:\n"
+                EX_TABLE(0b,1b)
+                : "+d" (rc) : "m" (*ctrl), "a" (ctrl));
+        return rc;
+}
+
+/* Stores a format 1 aib with 64 bytes */
+static inline int etr_stetr(struct etr_aib *aib)
+{
+        int rc = -ENOSYS;
+
+        asm volatile(
+                "       .insn   s,0xb2170000,0(%2)\n"
+                "0:     la      %0,0\n"
+                "1:\n"
+                EX_TABLE(0b,1b)
+                : "+d" (rc) : "m" (*aib), "a" (aib));
+        return rc;
+}
+
+/* Stores a format 2 aib with 96 bytes for specified port */
+static inline int etr_steai(struct etr_aib *aib, unsigned int func)
+{
+        register unsigned int reg0 asm("0") = func;
+        int rc = -ENOSYS;
+
+        asm volatile(
+                "       .insn   s,0xb2b30000,0(%2)\n"
+                "0:     la      %0,0\n"
+                "1:\n"
+                EX_TABLE(0b,1b)
+                : "+d" (rc) : "m" (*aib), "a" (aib), "d" (reg0));
+        return rc;
+}
+
+/* Function codes for the steai instruction. */
+#define ETR_STEAI_STEPPING_PORT         0x10
+#define ETR_STEAI_ALTERNATE_PORT        0x11
+#define ETR_STEAI_PORT_0                0x12
+#define ETR_STEAI_PORT_1                0x13
+
+static inline int etr_ptff(void *ptff_block, unsigned int func)
+{
+        register unsigned int reg0 asm("0") = func;
+        register unsigned long reg1 asm("1") = (unsigned long) ptff_block;
+        int rc = -ENOSYS;
+
+        asm volatile(
+                "       .word   0x0104\n"
+                "       ipm     %0\n"
+                "       srl     %0,28\n"
+                : "=d" (rc), "=m" (ptff_block)
+                : "d" (reg0), "d" (reg1), "m" (ptff_block) : "cc");
+        return rc;
+}
+
+/* Function codes for the ptff instruction. */
+#define ETR_PTFF_QAF    0x00    /* query available functions */
+#define ETR_PTFF_QTO    0x01    /* query tod offset */
+#define ETR_PTFF_QSI    0x02    /* query steering information */
+#define ETR_PTFF_ATO    0x40    /* adjust tod offset */
+#define ETR_PTFF_STO    0x41    /* set tod offset */
+#define ETR_PTFF_SFS    0x42    /* set fine steering rate */
+#define ETR_PTFF_SGS    0x43    /* set gross steering rate */
+
+/* Functions needed by the machine check handler */
+void etr_switch_to_local(void);
+void etr_sync_check(void);
+
+/* STP interruption parameter */
+struct stp_irq_parm {
+        unsigned int _pad0      : 14;
+        unsigned int tsc        : 1;    /* Timing status change */
+        unsigned int lac        : 1;    /* Link availability change */
+        unsigned int tcpc       : 1;    /* Time control parameter change */
+        unsigned int _pad2      : 15;
+} __attribute__ ((packed));
+
+#define STP_OP_SYNC     1
+#define STP_OP_CTRL     3
+
+struct stp_sstpi {
+        unsigned int rsvd0;
+        unsigned int rsvd1 : 8;
+        unsigned int stratum : 8;
+        unsigned int vbits : 16;
+        unsigned int leaps : 16;
+        unsigned int tmd : 4;
+        unsigned int ctn : 4;
+        unsigned int rsvd2 : 3;
+        unsigned int c : 1;
+        unsigned int tst : 4;
+        unsigned int tzo : 16;
+        unsigned int dsto : 16;
+        unsigned int ctrl : 16;
+        unsigned int rsvd3 : 16;
+        unsigned int tto;
+        unsigned int rsvd4;
+        unsigned int ctnid[3];
+        unsigned int rsvd5;
+        unsigned int todoff[4];
+        unsigned int rsvd6[48];
+} __attribute__ ((packed));
+
+/* Functions needed by the machine check handler */
+void stp_sync_check(void);
+void stp_island_check(void);
+
+#endif /* __S390_ETR_H */
diff --git a/arch/s390/include/asm/extmem.h b/arch/s390/include/asm/extmem.h
new file mode 100644
index 000000000000..33837d756184
--- /dev/null
+++ b/arch/s390/include/asm/extmem.h
@@ -0,0 +1,33 @@
+/*
+ *  include/asm-s390x/extmem.h
+ *
+ *  definitions for external memory segment support
+ *  Copyright (C) 2003 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ */
+
+#ifndef _ASM_S390X_DCSS_H
+#define _ASM_S390X_DCSS_H
+#ifndef __ASSEMBLY__
+
+/* possible values for segment type as returned by segment_info */
+#define SEG_TYPE_SW 0
+#define SEG_TYPE_EW 1
+#define SEG_TYPE_SR 2
+#define SEG_TYPE_ER 3
+#define SEG_TYPE_SN 4
+#define SEG_TYPE_EN 5
+#define SEG_TYPE_SC 6
+#define SEG_TYPE_EWEN 7
+
+#define SEGMENT_SHARED 0
+#define SEGMENT_EXCLUSIVE 1
+
+int segment_load (char *name, int segtype, unsigned long *addr, unsigned long *length);
+void segment_unload(char *name);
+void segment_save(char *name);
+int segment_type (char* name);
+int segment_modify_shared (char *name, int do_nonshared);
+void segment_warning(int rc, char *seg_name);
+
+#endif
+#endif
diff --git a/arch/s390/include/asm/fb.h b/arch/s390/include/asm/fb.h
new file mode 100644
index 000000000000..c7df38030992
--- /dev/null
+++ b/arch/s390/include/asm/fb.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+#include <linux/fb.h>
+
+#define fb_pgprotect(...) do {} while (0)
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/s390/include/asm/fcntl.h b/arch/s390/include/asm/fcntl.h
new file mode 100644
index 000000000000..46ab12db5739
--- /dev/null
+++ b/arch/s390/include/asm/fcntl.h
@@ -0,0 +1 @@
+#include <asm-generic/fcntl.h>
diff --git a/arch/s390/include/asm/fcx.h b/arch/s390/include/asm/fcx.h
new file mode 100644
index 000000000000..8be1f3a58042
--- /dev/null
+++ b/arch/s390/include/asm/fcx.h
@@ -0,0 +1,311 @@
+/*
+ *  Functions for assembling fcx enabled I/O control blocks.
+ *
+ *    Copyright IBM Corp. 2008
+ *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_FCX_H
+#define _ASM_S390_FCX_H _ASM_S390_FCX_H
+
+#include <linux/types.h>
+
+#define TCW_FORMAT_DEFAULT              0
+#define TCW_TIDAW_FORMAT_DEFAULT        0
+#define TCW_FLAGS_INPUT_TIDA            1 << (23 - 5)
+#define TCW_FLAGS_TCCB_TIDA             1 << (23 - 6)
+#define TCW_FLAGS_OUTPUT_TIDA           1 << (23 - 7)
+#define TCW_FLAGS_TIDAW_FORMAT(x)       ((x) & 3) << (23 - 9)
+#define TCW_FLAGS_GET_TIDAW_FORMAT(x)   (((x) >> (23 - 9)) & 3)
+
+/**
+ * struct tcw - Transport Control Word (TCW)
+ * @format: TCW format
+ * @flags: TCW flags
+ * @tccbl: Transport-Command-Control-Block Length
+ * @r: Read Operations
+ * @w: Write Operations
+ * @output: Output-Data Address
+ * @input: Input-Data Address
+ * @tsb: Transport-Status-Block Address
+ * @tccb: Transport-Command-Control-Block Address
+ * @output_count: Output Count
+ * @input_count: Input Count
+ * @intrg: Interrogate TCW Address
+ */
+struct tcw {
+        u32 format:2;
+        u32 :6;
+        u32 flags:24;
+        u32 :8;
+        u32 tccbl:6;
+        u32 r:1;
+        u32 w:1;
+        u32 :16;
+        u64 output;
+        u64 input;
+        u64 tsb;
+        u64 tccb;
+        u32 output_count;
+        u32 input_count;
+        u32 :32;
+        u32 :32;
+        u32 :32;
+        u32 intrg;
+} __attribute__ ((packed, aligned(64)));
+
+#define TIDAW_FLAGS_LAST                1 << (7 - 0)
+#define TIDAW_FLAGS_SKIP                1 << (7 - 1)
+#define TIDAW_FLAGS_DATA_INT            1 << (7 - 2)
+#define TIDAW_FLAGS_TTIC                1 << (7 - 3)
+#define TIDAW_FLAGS_INSERT_CBC          1 << (7 - 4)
+
+/**
+ * struct tidaw - Transport-Indirect-Addressing Word (TIDAW)
+ * @flags: TIDAW flags. Can be an arithmetic OR of the following constants:
+ * %TIDAW_FLAGS_LAST, %TIDAW_FLAGS_SKIP, %TIDAW_FLAGS_DATA_INT,
+ * %TIDAW_FLAGS_TTIC, %TIDAW_FLAGS_INSERT_CBC
+ * @count: Count
+ * @addr: Address
+ */
+struct tidaw {
+        u32 flags:8;
+        u32 :24;
+        u32 count;
+        u64 addr;
+} __attribute__ ((packed, aligned(16)));
+
+/**
+ * struct tsa_iostat - I/O-Status Transport-Status Area (IO-Stat TSA)
+ * @dev_time: Device Time
+ * @def_time: Defer Time
+ * @queue_time: Queue Time
+ * @dev_busy_time: Device-Busy Time
+ * @dev_act_time: Device-Active-Only Time
+ * @sense: Sense Data (if present)
+ */
+struct tsa_iostat {
+        u32 dev_time;
+        u32 def_time;
+        u32 queue_time;
+        u32 dev_busy_time;
+        u32 dev_act_time;
+        u8 sense[32];
+} __attribute__ ((packed));
+
+/**
+ * struct tsa_ddpcs - Device-Detected-Program-Check Transport-Status Area (DDPC TSA)
+ * @rc: Reason Code
+ * @rcq: Reason Code Qualifier
+ * @sense: Sense Data (if present)
+ */
+struct tsa_ddpc {
+        u32 :24;
+        u32 rc:8;
+        u8 rcq[16];
+        u8 sense[32];
+} __attribute__ ((packed));
+
+#define TSA_INTRG_FLAGS_CU_STATE_VALID          1 << (7 - 0)
+#define TSA_INTRG_FLAGS_DEV_STATE_VALID         1 << (7 - 1)
+#define TSA_INTRG_FLAGS_OP_STATE_VALID          1 << (7 - 2)
+
+/**
+ * struct tsa_intrg - Interrogate Transport-Status Area (Intrg. TSA)
+ * @format: Format
+ * @flags: Flags. Can be an arithmetic OR of the following constants:
+ * %TSA_INTRG_FLAGS_CU_STATE_VALID, %TSA_INTRG_FLAGS_DEV_STATE_VALID,
+ * %TSA_INTRG_FLAGS_OP_STATE_VALID
+ * @cu_state: Controle-Unit State
+ * @dev_state: Device State
+ * @op_state: Operation State
+ * @sd_info: State-Dependent Information
+ * @dl_id: Device-Level Identifier
+ * @dd_data: Device-Dependent Data
+ */
+struct tsa_intrg {
+        u32 format:8;
+        u32 flags:8;
+        u32 cu_state:8;
+        u32 dev_state:8;
+        u32 op_state:8;
+        u32 :24;
+        u8 sd_info[12];
+        u32 dl_id;
+        u8 dd_data[28];
+} __attribute__ ((packed));
+
+#define TSB_FORMAT_NONE         0
+#define TSB_FORMAT_IOSTAT       1
+#define TSB_FORMAT_DDPC         2
+#define TSB_FORMAT_INTRG        3
+
+#define TSB_FLAGS_DCW_OFFSET_VALID      1 << (7 - 0)
+#define TSB_FLAGS_COUNT_VALID           1 << (7 - 1)
+#define TSB_FLAGS_CACHE_MISS            1 << (7 - 2)
+#define TSB_FLAGS_TIME_VALID            1 << (7 - 3)
+#define TSB_FLAGS_FORMAT(x)             ((x) & 7)
+#define TSB_FORMAT(t)                   ((t)->flags & 7)
+
+/**
+ * struct tsb - Transport-Status Block (TSB)
+ * @length: Length
+ * @flags: Flags. Can be an arithmetic OR of the following constants:
+ * %TSB_FLAGS_DCW_OFFSET_VALID, %TSB_FLAGS_COUNT_VALID, %TSB_FLAGS_CACHE_MISS,
+ * %TSB_FLAGS_TIME_VALID
+ * @dcw_offset: DCW Offset
+ * @count: Count
+ * @tsa: Transport-Status-Area
+ */
+struct tsb {
+        u32 length:8;
+        u32 flags:8;
+        u32 dcw_offset:16;
+        u32 count;
+        u32 :32;
+        union {
+                struct tsa_iostat iostat;
+                struct tsa_ddpc ddpc;
+                struct tsa_intrg intrg;
+        } __attribute__ ((packed)) tsa;
+} __attribute__ ((packed, aligned(8)));
+
+#define DCW_INTRG_FORMAT_DEFAULT        0
+
+#define DCW_INTRG_RC_UNSPECIFIED        0
+#define DCW_INTRG_RC_TIMEOUT            1
+
+#define DCW_INTRG_RCQ_UNSPECIFIED       0
+#define DCW_INTRG_RCQ_PRIMARY           1
+#define DCW_INTRG_RCQ_SECONDARY         2
+
+#define DCW_INTRG_FLAGS_MPM             1 < (7 - 0)
+#define DCW_INTRG_FLAGS_PPR             1 < (7 - 1)
+#define DCW_INTRG_FLAGS_CRIT            1 < (7 - 2)
+
+/**
+ * struct dcw_intrg_data - Interrogate DCW data
+ * @format: Format. Should be %DCW_INTRG_FORMAT_DEFAULT
+ * @rc: Reason Code. Can be one of %DCW_INTRG_RC_UNSPECIFIED,
+ * %DCW_INTRG_RC_TIMEOUT
+ * @rcq: Reason Code Qualifier: Can be one of %DCW_INTRG_RCQ_UNSPECIFIED,
+ * %DCW_INTRG_RCQ_PRIMARY, %DCW_INTRG_RCQ_SECONDARY
+ * @lpm: Logical-Path Mask
+ * @pam: Path-Available Mask
+ * @pim: Path-Installed Mask
+ * @timeout: Timeout
+ * @flags: Flags. Can be an arithmetic OR of %DCW_INTRG_FLAGS_MPM,
+ * %DCW_INTRG_FLAGS_PPR, %DCW_INTRG_FLAGS_CRIT
+ * @time: Time
+ * @prog_id: Program Identifier
+ * @prog_data: Program-Dependent Data
+ */
+struct dcw_intrg_data {
+        u32 format:8;
+        u32 rc:8;
+        u32 rcq:8;
+        u32 lpm:8;
+        u32 pam:8;
+        u32 pim:8;
+        u32 timeout:16;
+        u32 flags:8;
+        u32 :24;
+        u32 :32;
+        u64 time;
+        u64 prog_id;
+        u8  prog_data[0];
+} __attribute__ ((packed));
+
+#define DCW_FLAGS_CC            1 << (7 - 1)
+
+#define DCW_CMD_WRITE           0x01
+#define DCW_CMD_READ            0x02
+#define DCW_CMD_CONTROL         0x03
+#define DCW_CMD_SENSE           0x04
+#define DCW_CMD_SENSE_ID        0xe4
+#define DCW_CMD_INTRG           0x40
+
+/**
+ * struct dcw - Device-Command Word (DCW)
+ * @cmd: Command Code. Can be one of %DCW_CMD_WRITE, %DCW_CMD_READ,
+ * %DCW_CMD_CONTROL, %DCW_CMD_SENSE, %DCW_CMD_SENSE_ID, %DCW_CMD_INTRG
+ * @flags: Flags. Can be an arithmetic OR of %DCW_FLAGS_CC
+ * @cd_count: Control-Data Count
+ * @count: Count
+ * @cd: Control Data
+ */
+struct dcw {
+        u32 cmd:8;
+        u32 flags:8;
+        u32 :8;
+        u32 cd_count:8;
+        u32 count;
+        u8 cd[0];
+} __attribute__ ((packed));
+
+#define TCCB_FORMAT_DEFAULT     0x7f
+#define TCCB_MAX_DCW            30
+#define TCCB_MAX_SIZE           (sizeof(struct tccb_tcah) + \
+                                 TCCB_MAX_DCW * sizeof(struct dcw) + \
+                                 sizeof(struct tccb_tcat))
+#define TCCB_SAC_DEFAULT        0xf901
+#define TCCB_SAC_INTRG          0xf902
+
+/**
+ * struct tccb_tcah - Transport-Command-Area Header (TCAH)
+ * @format: Format. Should be %TCCB_FORMAT_DEFAULT
+ * @tcal: Transport-Command-Area Length
+ * @sac: Service-Action Code. Can be one of %TCCB_SAC_DEFAULT, %TCCB_SAC_INTRG
+ * @prio: Priority
+ */
+struct tccb_tcah {
+        u32 format:8;
+        u32 :24;
+        u32 :24;
+        u32 tcal:8;
+        u32 sac:16;
+        u32 :8;
+        u32 prio:8;
+        u32 :32;
+} __attribute__ ((packed));
+
+/**
+ * struct tccb_tcat - Transport-Command-Area Trailer (TCAT)
+ * @count: Transport Count
+ */
+struct tccb_tcat {
+        u32 :32;
+        u32 count;
+} __attribute__ ((packed));
+
+/**
+ * struct tccb - (partial) Transport-Command-Control Block (TCCB)
+ * @tcah: TCAH
+ * @tca: Transport-Command Area
+ */
+struct tccb {
+        struct tccb_tcah tcah;
+        u8 tca[0];
+} __attribute__ ((packed, aligned(8)));
+
+struct tcw *tcw_get_intrg(struct tcw *tcw);
+void *tcw_get_data(struct tcw *tcw);
+struct tccb *tcw_get_tccb(struct tcw *tcw);
+struct tsb *tcw_get_tsb(struct tcw *tcw);
+
+void tcw_init(struct tcw *tcw, int r, int w);
+void tcw_finalize(struct tcw *tcw, int num_tidaws);
+
+void tcw_set_intrg(struct tcw *tcw, struct tcw *intrg_tcw);
+void tcw_set_data(struct tcw *tcw, void *data, int use_tidal);
+void tcw_set_tccb(struct tcw *tcw, struct tccb *tccb);
+void tcw_set_tsb(struct tcw *tcw, struct tsb *tsb);
+
+void tccb_init(struct tccb *tccb, size_t tccb_size, u32 sac);
+void tsb_init(struct tsb *tsb);
+struct dcw *tccb_add_dcw(struct tccb *tccb, size_t tccb_size, u8 cmd, u8 flags,
+                         void *cd, u8 cd_count, u32 count);
+struct tidaw *tcw_add_tidaw(struct tcw *tcw, int num_tidaws, u8 flags,
+                            void *addr, u32 count);
+
+#endif /* _ASM_S390_FCX_H */
diff --git a/arch/s390/include/asm/futex.h b/arch/s390/include/asm/futex.h
new file mode 100644
index 000000000000..5c5d02de49e9
--- /dev/null
+++ b/arch/s390/include/asm/futex.h
@@ -0,0 +1,52 @@
+#ifndef _ASM_S390_FUTEX_H
+#define _ASM_S390_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval, ret;
+
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();
+        ret = uaccess.futex_atomic_op(op, uaddr, oparg, &oldval);
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr,
+                                                int oldval, int newval)
+{
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        return uaccess.futex_atomic_cmpxchg(uaddr, oldval, newval);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_S390_FUTEX_H */
diff --git a/arch/s390/include/asm/hardirq.h b/arch/s390/include/asm/hardirq.h
new file mode 100644
index 000000000000..89ec7056da28
--- /dev/null
+++ b/arch/s390/include/asm/hardirq.h
@@ -0,0 +1,51 @@
+/*
+ *  include/asm-s390/hardirq.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
+ *
+ *  Derived from "include/asm-i386/hardirq.h"
+ */
+
+#ifndef __ASM_HARDIRQ_H
+#define __ASM_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/sched.h>
+#include <linux/cache.h>
+#include <linux/interrupt.h>
+#include <asm/lowcore.h>
+
+/* irq_cpustat_t is unused currently, but could be converted
+ * into a percpu variable instead of storing softirq_pending
+ * on the lowcore */
+typedef struct {
+        unsigned int __softirq_pending;
+} irq_cpustat_t;
+
+#define local_softirq_pending() (S390_lowcore.softirq_pending)
+
+#define __ARCH_IRQ_STAT
+#define __ARCH_HAS_DO_SOFTIRQ
+
+#define HARDIRQ_BITS    8
+
+void clock_comparator_work(void);
+
+static inline unsigned long long local_tick_disable(void)
+{
+        unsigned long long old;
+
+        old = S390_lowcore.clock_comparator;
+        S390_lowcore.clock_comparator = -1ULL;
+        return old;
+}
+
+static inline void local_tick_enable(unsigned long long comp)
+{
+        S390_lowcore.clock_comparator = comp;
+}
+
+#endif /* __ASM_HARDIRQ_H */
diff --git a/arch/s390/include/asm/hugetlb.h b/arch/s390/include/asm/hugetlb.h
new file mode 100644
index 000000000000..670a1d1745d2
--- /dev/null
+++ b/arch/s390/include/asm/hugetlb.h
@@ -0,0 +1,184 @@
+/*
+ *  IBM System z Huge TLB Page Support for Kernel.
+ *
+ *    Copyright IBM Corp. 2008
+ *    Author(s): Gerald Schaefer <gerald.schaefer@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_HUGETLB_H
+#define _ASM_S390_HUGETLB_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+
+#define is_hugepage_only_range(mm, addr, len)   0
+#define hugetlb_free_pgd_range                  free_pgd_range
+
+void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                     pte_t *ptep, pte_t pte);
+
+/*
+ * If the arch doesn't supply something else, assume that hugepage
+ * size aligned regions are ok without further preparation.
+ */
+static inline int prepare_hugepage_range(struct file *file,
+                        unsigned long addr, unsigned long len)
+{
+        if (len & ~HPAGE_MASK)
+                return -EINVAL;
+        if (addr & ~HPAGE_MASK)
+                return -EINVAL;
+        return 0;
+}
+
+#define hugetlb_prefault_arch_hook(mm)          do { } while (0)
+
+int arch_prepare_hugepage(struct page *page);
+void arch_release_hugepage(struct page *page);
+
+static inline pte_t pte_mkhuge(pte_t pte)
+{
+        /*
+         * PROT_NONE needs to be remapped from the pte type to the ste type.
+         * The HW invalid bit is also different for pte and ste. The pte
+         * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
+         * bit, so we don't have to clear it.
+         */
+        if (pte_val(pte) & _PAGE_INVALID) {
+                if (pte_val(pte) & _PAGE_SWT)
+                        pte_val(pte) |= _HPAGE_TYPE_NONE;
+                pte_val(pte) |= _SEGMENT_ENTRY_INV;
+        }
+        /*
+         * Clear SW pte bits SWT and SWX, there are no SW bits in a segment
+         * table entry.
+         */
+        pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX);
+        /*
+         * Also set the change-override bit because we don't need dirty bit
+         * tracking for hugetlbfs pages.
+         */
+        pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
+        return pte;
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_RO;
+        return pte;
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return (pte_val(pte) & _SEGMENT_ENTRY_INV) &&
+                !(pte_val(pte) & _SEGMENT_ENTRY_RO);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        pte_t pte = *ptep;
+        unsigned long mask;
+
+        if (!MACHINE_HAS_HPAGE) {
+                ptep = (pte_t *) (pte_val(pte) & _SEGMENT_ENTRY_ORIGIN);
+                if (ptep) {
+                        mask = pte_val(pte) &
+                                (_SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO);
+                        pte = pte_mkhuge(*ptep);
+                        pte_val(pte) |= mask;
+                }
+        }
+        return pte;
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        pte_t pte = huge_ptep_get(ptep);
+
+        pmd_clear((pmd_t *) ptep);
+        return pte;
+}
+
+static inline void __pmd_csp(pmd_t *pmdp)
+{
+        register unsigned long reg2 asm("2") = pmd_val(*pmdp);
+        register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
+                                               _SEGMENT_ENTRY_INV;
+        register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
+
+        asm volatile(
+                "       csp %1,%3"
+                : "=m" (*pmdp)
+                : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
+        pmd_val(*pmdp) = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY;
+}
+
+static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
+{
+        unsigned long sto = (unsigned long) pmdp -
+                                pmd_index(address) * sizeof(pmd_t);
+
+        if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) {
+                asm volatile(
+                        "       .insn   rrf,0xb98e0000,%2,%3,0,0"
+                        : "=m" (*pmdp)
+                        : "m" (*pmdp), "a" (sto),
+                          "a" ((address & HPAGE_MASK))
+                );
+        }
+        pmd_val(*pmdp) = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY;
+}
+
+static inline void huge_ptep_invalidate(struct mm_struct *mm,
+                                        unsigned long address, pte_t *ptep)
+{
+        pmd_t *pmdp = (pmd_t *) ptep;
+
+        if (!MACHINE_HAS_IDTE) {
+                __pmd_csp(pmdp);
+                if (mm->context.noexec) {
+                        pmdp = get_shadow_table(pmdp);
+                        __pmd_csp(pmdp);
+                }
+                return;
+        }
+
+        __pmd_idte(address, pmdp);
+        if (mm->context.noexec) {
+                pmdp = get_shadow_table(pmdp);
+                __pmd_idte(address, pmdp);
+        }
+        return;
+}
+
+#define huge_ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \
+({                                                                          \
+        int __changed = !pte_same(huge_ptep_get(__ptep), __entry);          \
+        if (__changed) {                                                    \
+                huge_ptep_invalidate((__vma)->vm_mm, __addr, __ptep);       \
+                set_huge_pte_at((__vma)->vm_mm, __addr, __ptep, __entry);   \
+        }                                                                   \
+        __changed;                                                          \
+})
+
+#define huge_ptep_set_wrprotect(__mm, __addr, __ptep)                   \
+({                                                                      \
+        pte_t __pte = huge_ptep_get(__ptep);                            \
+        if (pte_write(__pte)) {                                         \
+                if (atomic_read(&(__mm)->mm_users) > 1 ||               \
+                    (__mm) != current->active_mm)                       \
+                        huge_ptep_invalidate(__mm, __addr, __ptep);     \
+                set_huge_pte_at(__mm, __addr, __ptep,                   \
+                                huge_pte_wrprotect(__pte));             \
+        }                                                               \
+})
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long address, pte_t *ptep)
+{
+        huge_ptep_invalidate(vma->vm_mm, address, ptep);
+}
+
+#endif /* _ASM_S390_HUGETLB_H */
diff --git a/arch/s390/include/asm/idals.h b/arch/s390/include/asm/idals.h
new file mode 100644
index 000000000000..e82c10efe65a
--- /dev/null
+++ b/arch/s390/include/asm/idals.h
@@ -0,0 +1,256 @@
+/* 
+ * File...........: linux/include/asm-s390x/idals.h
+ * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
+ *                  Martin Schwidefsky <schwidefsky@de.ibm.com>
+ * Bugreports.to..: <Linux390@de.ibm.com>
+ * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 2000a
+ 
+ * History of changes
+ * 07/24/00 new file
+ * 05/04/02 code restructuring.
+ */
+
+#ifndef _S390_IDALS_H
+#define _S390_IDALS_H
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/cio.h>
+#include <asm/uaccess.h>
+
+#ifdef __s390x__
+#define IDA_SIZE_LOG 12 /* 11 for 2k , 12 for 4k */
+#else
+#define IDA_SIZE_LOG 11 /* 11 for 2k , 12 for 4k */
+#endif
+#define IDA_BLOCK_SIZE (1L<<IDA_SIZE_LOG)
+
+/*
+ * Test if an address/length pair needs an idal list.
+ */
+static inline int
+idal_is_needed(void *vaddr, unsigned int length)
+{
+#ifdef __s390x__
+        return ((__pa(vaddr) + length - 1) >> 31) != 0;
+#else
+        return 0;
+#endif
+}
+
+
+/*
+ * Return the number of idal words needed for an address/length pair.
+ */
+static inline unsigned int
+idal_nr_words(void *vaddr, unsigned int length)
+{
+#ifdef __s390x__
+        if (idal_is_needed(vaddr, length))
+                return ((__pa(vaddr) & (IDA_BLOCK_SIZE-1)) + length + 
+                        (IDA_BLOCK_SIZE-1)) >> IDA_SIZE_LOG;
+#endif
+        return 0;
+}
+
+/*
+ * Create the list of idal words for an address/length pair.
+ */
+static inline unsigned long *
+idal_create_words(unsigned long *idaws, void *vaddr, unsigned int length)
+{
+#ifdef __s390x__
+        unsigned long paddr;
+        unsigned int cidaw;
+
+        paddr = __pa(vaddr);
+        cidaw = ((paddr & (IDA_BLOCK_SIZE-1)) + length + 
+                 (IDA_BLOCK_SIZE-1)) >> IDA_SIZE_LOG;
+        *idaws++ = paddr;
+        paddr &= -IDA_BLOCK_SIZE;
+        while (--cidaw > 0) {
+                paddr += IDA_BLOCK_SIZE;
+                *idaws++ = paddr;
+        }
+#endif
+        return idaws;
+}
+
+/*
+ * Sets the address of the data in CCW.
+ * If necessary it allocates an IDAL and sets the appropriate flags.
+ */
+static inline int
+set_normalized_cda(struct ccw1 * ccw, void *vaddr)
+{
+#ifdef __s390x__
+        unsigned int nridaws;
+        unsigned long *idal;
+
+        if (ccw->flags & CCW_FLAG_IDA)
+                return -EINVAL;
+        nridaws = idal_nr_words(vaddr, ccw->count);
+        if (nridaws > 0) {
+                idal = kmalloc(nridaws * sizeof(unsigned long),
+                               GFP_ATOMIC | GFP_DMA );
+                if (idal == NULL)
+                        return -ENOMEM;
+                idal_create_words(idal, vaddr, ccw->count);
+                ccw->flags |= CCW_FLAG_IDA;
+                vaddr = idal;
+        }
+#endif
+        ccw->cda = (__u32)(unsigned long) vaddr;
+        return 0;
+}
+
+/*
+ * Releases any allocated IDAL related to the CCW.
+ */
+static inline void
+clear_normalized_cda(struct ccw1 * ccw)
+{
+#ifdef __s390x__
+        if (ccw->flags & CCW_FLAG_IDA) {
+                kfree((void *)(unsigned long) ccw->cda);
+                ccw->flags &= ~CCW_FLAG_IDA;
+        }
+#endif
+        ccw->cda = 0;
+}
+
+/*
+ * Idal buffer extension
+ */
+struct idal_buffer {
+        size_t size;
+        size_t page_order;
+        void *data[0];
+};
+
+/*
+ * Allocate an idal buffer
+ */
+static inline struct idal_buffer *
+idal_buffer_alloc(size_t size, int page_order)
+{
+        struct idal_buffer *ib;
+        int nr_chunks, nr_ptrs, i;
+
+        nr_ptrs = (size + IDA_BLOCK_SIZE - 1) >> IDA_SIZE_LOG;
+        nr_chunks = (4096 << page_order) >> IDA_SIZE_LOG;
+        ib = kmalloc(sizeof(struct idal_buffer) + nr_ptrs*sizeof(void *),
+                     GFP_DMA | GFP_KERNEL);
+        if (ib == NULL)
+                return ERR_PTR(-ENOMEM);
+        ib->size = size;
+        ib->page_order = page_order;
+        for (i = 0; i < nr_ptrs; i++) {
+                if ((i & (nr_chunks - 1)) != 0) {
+                        ib->data[i] = ib->data[i-1] + IDA_BLOCK_SIZE;
+                        continue;
+                }
+                ib->data[i] = (void *)
+                        __get_free_pages(GFP_KERNEL, page_order);
+                if (ib->data[i] != NULL)
+                        continue;
+                // Not enough memory
+                while (i >= nr_chunks) {
+                        i -= nr_chunks;
+                        free_pages((unsigned long) ib->data[i],
+                                   ib->page_order);
+                }
+                kfree(ib);
+                return ERR_PTR(-ENOMEM);
+        }
+        return ib;
+}
+
+/*
+ * Free an idal buffer.
+ */
+static inline void
+idal_buffer_free(struct idal_buffer *ib)
+{
+        int nr_chunks, nr_ptrs, i;
+
+        nr_ptrs = (ib->size + IDA_BLOCK_SIZE - 1) >> IDA_SIZE_LOG;
+        nr_chunks = (4096 << ib->page_order) >> IDA_SIZE_LOG;
+        for (i = 0; i < nr_ptrs; i += nr_chunks)
+                free_pages((unsigned long) ib->data[i], ib->page_order);
+        kfree(ib);
+}
+
+/*
+ * Test if a idal list is really needed.
+ */
+static inline int
+__idal_buffer_is_needed(struct idal_buffer *ib)
+{
+#ifdef __s390x__
+        return ib->size > (4096ul << ib->page_order) ||
+                idal_is_needed(ib->data[0], ib->size);
+#else
+        return ib->size > (4096ul << ib->page_order);
+#endif
+}
+
+/*
+ * Set channel data address to idal buffer.
+ */
+static inline void
+idal_buffer_set_cda(struct idal_buffer *ib, struct ccw1 *ccw)
+{
+        if (__idal_buffer_is_needed(ib)) {
+                // setup idals;
+                ccw->cda = (u32)(addr_t) ib->data;
+                ccw->flags |= CCW_FLAG_IDA;
+        } else
+                // we do not need idals - use direct addressing
+                ccw->cda = (u32)(addr_t) ib->data[0];
+        ccw->count = ib->size;
+}
+
+/*
+ * Copy count bytes from an idal buffer to user memory
+ */
+static inline size_t
+idal_buffer_to_user(struct idal_buffer *ib, void __user *to, size_t count)
+{
+        size_t left;
+        int i;
+
+        BUG_ON(count > ib->size);
+        for (i = 0; count > IDA_BLOCK_SIZE; i++) {
+                left = copy_to_user(to, ib->data[i], IDA_BLOCK_SIZE);
+                if (left)
+                        return left + count - IDA_BLOCK_SIZE;
+                to = (void __user *) to + IDA_BLOCK_SIZE;
+                count -= IDA_BLOCK_SIZE;
+        }
+        return copy_to_user(to, ib->data[i], count);
+}
+
+/*
+ * Copy count bytes from user memory to an idal buffer
+ */
+static inline size_t
+idal_buffer_from_user(struct idal_buffer *ib, const void __user *from, size_t count)
+{
+        size_t left;
+        int i;
+
+        BUG_ON(count > ib->size);
+        for (i = 0; count > IDA_BLOCK_SIZE; i++) {
+                left = copy_from_user(ib->data[i], from, IDA_BLOCK_SIZE);
+                if (left)
+                        return left + count - IDA_BLOCK_SIZE;
+                from = (void __user *) from + IDA_BLOCK_SIZE;
+                count -= IDA_BLOCK_SIZE;
+        }
+        return copy_from_user(ib->data[i], from, count);
+}
+
+#endif
diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h
new file mode 100644
index 000000000000..b7ff6afc3caa
--- /dev/null
+++ b/arch/s390/include/asm/io.h
@@ -0,0 +1,54 @@
+/*
+ *  include/asm-s390/io.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/io.h"
+ */
+
+#ifndef _S390_IO_H
+#define _S390_IO_H
+
+#ifdef __KERNEL__
+
+#include <asm/page.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * Change virtual addresses to physical addresses and vv.
+ * These are pretty trivial
+ */
+static inline unsigned long virt_to_phys(volatile void * address)
+{
+        unsigned long real_address;
+        asm volatile(
+                 "      lra     %0,0(%1)\n"
+                 "      jz      0f\n"
+                 "      la      %0,0\n"
+                 "0:"
+                 : "=a" (real_address) : "a" (address) : "cc");
+        return real_address;
+}
+
+static inline void * phys_to_virt(unsigned long address)
+{
+        return (void *) address;
+}
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/s390/include/asm/ioctl.h b/arch/s390/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/s390/include/asm/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/arch/s390/include/asm/ioctls.h b/arch/s390/include/asm/ioctls.h
new file mode 100644
index 000000000000..40e481b1b461
--- /dev/null
+++ b/arch/s390/include/asm/ioctls.h
@@ -0,0 +1,92 @@
+/*
+ *  include/asm-s390/ioctls.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/ioctls.h"
+ */
+
+#ifndef __ARCH_S390_IOCTLS_H__
+#define __ARCH_S390_IOCTLS_H__
+
+#include <asm/ioctl.h>
+
+/* 0x54 is just a magic number to make these relatively unique ('T') */
+
+#define TCGETS          0x5401
+#define TCSETS          0x5402
+#define TCSETSW         0x5403
+#define TCSETSF         0x5404
+#define TCGETA          0x5405
+#define TCSETA          0x5406
+#define TCSETAW         0x5407
+#define TCSETAF         0x5408
+#define TCSBRK          0x5409
+#define TCXONC          0x540A
+#define TCFLSH          0x540B
+#define TIOCEXCL        0x540C
+#define TIOCNXCL        0x540D
+#define TIOCSCTTY       0x540E
+#define TIOCGPGRP       0x540F
+#define TIOCSPGRP       0x5410
+#define TIOCOUTQ        0x5411
+#define TIOCSTI         0x5412
+#define TIOCGWINSZ      0x5413
+#define TIOCSWINSZ      0x5414
+#define TIOCMGET        0x5415
+#define TIOCMBIS        0x5416
+#define TIOCMBIC        0x5417
+#define TIOCMSET        0x5418
+#define TIOCGSOFTCAR    0x5419
+#define TIOCSSOFTCAR    0x541A
+#define FIONREAD        0x541B
+#define TIOCINQ         FIONREAD
+#define TIOCLINUX       0x541C
+#define TIOCCONS        0x541D
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TIOCPKT         0x5420
+#define FIONBIO         0x5421
+#define TIOCNOTTY       0x5422
+#define TIOCSETD        0x5423
+#define TIOCGETD        0x5424
+#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T',0x2A, struct termios2)
+#define TCSETS2         _IOW('T',0x2B, struct termios2)
+#define TCSETSW2        _IOW('T',0x2C, struct termios2)
+#define TCSETSF2        _IOW('T',0x2D, struct termios2)
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
+#define FIOCLEX         0x5451
+#define FIOASYNC        0x5452
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
+#define TIOCSERGETLSR   0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+#define FIOQSIZE        0x545E
+
+/* Used for packet mode */
+#define TIOCPKT_DATA             0
+#define TIOCPKT_FLUSHREAD        1
+#define TIOCPKT_FLUSHWRITE       2
+#define TIOCPKT_STOP             4
+#define TIOCPKT_START            8
+#define TIOCPKT_NOSTOP          16
+#define TIOCPKT_DOSTOP          32
+
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+#endif
diff --git a/arch/s390/include/asm/ipcbuf.h b/arch/s390/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..37f293d12c8f
--- /dev/null
+++ b/arch/s390/include/asm/ipcbuf.h
@@ -0,0 +1,31 @@
+#ifndef __S390_IPCBUF_H__
+#define __S390_IPCBUF_H__
+
+/*
+ * The user_ipc_perm structure for S/390 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid32_t        uid;
+        __kernel_gid32_t        gid;
+        __kernel_uid32_t        cuid;
+        __kernel_gid32_t        cgid;
+        __kernel_mode_t         mode;
+        unsigned short          __pad1;
+        unsigned short          seq;
+#ifndef __s390x__
+        unsigned short          __pad2;
+#endif /* ! __s390x__ */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+#endif /* __S390_IPCBUF_H__ */
diff --git a/arch/s390/include/asm/ipl.h b/arch/s390/include/asm/ipl.h
new file mode 100644
index 000000000000..1171e6d144a3
--- /dev/null
+++ b/arch/s390/include/asm/ipl.h
@@ -0,0 +1,168 @@
+/*
+ * s390 (re)ipl support
+ *
+ * Copyright IBM Corp. 2007
+ */
+
+#ifndef _ASM_S390_IPL_H
+#define _ASM_S390_IPL_H
+
+#include <asm/types.h>
+#include <asm/cio.h>
+#include <asm/setup.h>
+
+#define IPL_PARMBLOCK_ORIGIN    0x2000
+
+#define IPL_PARM_BLK_FCP_LEN (sizeof(struct ipl_list_hdr) + \
+                              sizeof(struct ipl_block_fcp))
+
+#define IPL_PARM_BLK0_FCP_LEN (sizeof(struct ipl_block_fcp) + 8)
+
+#define IPL_PARM_BLK_CCW_LEN (sizeof(struct ipl_list_hdr) + \
+                              sizeof(struct ipl_block_ccw))
+
+#define IPL_PARM_BLK0_CCW_LEN (sizeof(struct ipl_block_ccw) + 8)
+
+#define IPL_MAX_SUPPORTED_VERSION (0)
+
+#define IPL_PARMBLOCK_START     ((struct ipl_parameter_block *) \
+                                 IPL_PARMBLOCK_ORIGIN)
+#define IPL_PARMBLOCK_SIZE      (IPL_PARMBLOCK_START->hdr.len)
+
+struct ipl_list_hdr {
+        u32 len;
+        u8  reserved1[3];
+        u8  version;
+        u32 blk0_len;
+        u8  pbt;
+        u8  flags;
+        u16 reserved2;
+} __attribute__((packed));
+
+struct ipl_block_fcp {
+        u8  reserved1[313-1];
+        u8  opt;
+        u8  reserved2[3];
+        u16 reserved3;
+        u16 devno;
+        u8  reserved4[4];
+        u64 wwpn;
+        u64 lun;
+        u32 bootprog;
+        u8  reserved5[12];
+        u64 br_lba;
+        u32 scp_data_len;
+        u8  reserved6[260];
+        u8  scp_data[];
+} __attribute__((packed));
+
+#define DIAG308_VMPARM_SIZE     64
+
+struct ipl_block_ccw {
+        u8  load_parm[8];
+        u8  reserved1[84];
+        u8  reserved2[2];
+        u16 devno;
+        u8  vm_flags;
+        u8  reserved3[3];
+        u32 vm_parm_len;
+        u8  nss_name[8];
+        u8  vm_parm[DIAG308_VMPARM_SIZE];
+        u8  reserved4[8];
+} __attribute__((packed));
+
+struct ipl_parameter_block {
+        struct ipl_list_hdr hdr;
+        union {
+                struct ipl_block_fcp fcp;
+                struct ipl_block_ccw ccw;
+        } ipl_info;
+} __attribute__((packed,aligned(4096)));
+
+/*
+ * IPL validity flags
+ */
+extern u32 ipl_flags;
+extern u32 dump_prefix_page;
+extern unsigned int zfcpdump_prefix_array[];
+
+extern void do_reipl(void);
+extern void do_halt(void);
+extern void do_poff(void);
+extern void ipl_save_parameters(void);
+extern void ipl_update_parameters(void);
+extern void get_ipl_vmparm(char *);
+
+enum {
+        IPL_DEVNO_VALID         = 1,
+        IPL_PARMBLOCK_VALID     = 2,
+        IPL_NSS_VALID           = 4,
+};
+
+enum ipl_type {
+        IPL_TYPE_UNKNOWN        = 1,
+        IPL_TYPE_CCW            = 2,
+        IPL_TYPE_FCP            = 4,
+        IPL_TYPE_FCP_DUMP       = 8,
+        IPL_TYPE_NSS            = 16,
+};
+
+struct ipl_info
+{
+        enum ipl_type type;
+        union {
+                struct {
+                        struct ccw_dev_id dev_id;
+                } ccw;
+                struct {
+                        struct ccw_dev_id dev_id;
+                        u64 wwpn;
+                        u64 lun;
+                } fcp;
+                struct {
+                        char name[NSS_NAME_SIZE + 1];
+                } nss;
+        } data;
+};
+
+extern struct ipl_info ipl_info;
+extern void setup_ipl(void);
+
+/*
+ * DIAG 308 support
+ */
+enum diag308_subcode  {
+        DIAG308_REL_HSA = 2,
+        DIAG308_IPL     = 3,
+        DIAG308_DUMP    = 4,
+        DIAG308_SET     = 5,
+        DIAG308_STORE   = 6,
+};
+
+enum diag308_ipl_type {
+        DIAG308_IPL_TYPE_FCP    = 0,
+        DIAG308_IPL_TYPE_CCW    = 2,
+};
+
+enum diag308_opt {
+        DIAG308_IPL_OPT_IPL     = 0x10,
+        DIAG308_IPL_OPT_DUMP    = 0x20,
+};
+
+enum diag308_flags {
+        DIAG308_FLAGS_LP_VALID  = 0x80,
+};
+
+enum diag308_vm_flags {
+        DIAG308_VM_FLAGS_NSS_VALID      = 0x80,
+        DIAG308_VM_FLAGS_VP_VALID       = 0x40,
+};
+
+enum diag308_rc {
+        DIAG308_RC_OK           = 0x0001,
+        DIAG308_RC_NOCONFIG     = 0x0102,
+};
+
+extern int diag308(unsigned long subcode, void *addr);
+
+#endif /* _ASM_S390_IPL_H */
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
new file mode 100644
index 000000000000..7da991a858f8
--- /dev/null
+++ b/arch/s390/include/asm/irq.h
@@ -0,0 +1,23 @@
+#ifndef _ASM_IRQ_H
+#define _ASM_IRQ_H
+
+#ifdef __KERNEL__
+#include <linux/hardirq.h>
+
+/*
+ * the definition of irqs has changed in 2.5.46:
+ * NR_IRQS is no longer the number of i/o
+ * interrupts (65536), but rather the number
+ * of interrupt classes (2).
+ * Only external and i/o interrupts make much sense here (CH).
+ */
+
+enum interruption_class {
+        EXTERNAL_INTERRUPT,
+        IO_INTERRUPT,
+
+        NR_IRQS,
+};
+
+#endif /* __KERNEL__ */
+#endif
diff --git a/arch/s390/include/asm/irq_regs.h b/arch/s390/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/s390/include/asm/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/arch/s390/include/asm/irqflags.h b/arch/s390/include/asm/irqflags.h
new file mode 100644
index 000000000000..3f26131120b7
--- /dev/null
+++ b/arch/s390/include/asm/irqflags.h
@@ -0,0 +1,106 @@
+/*
+ *  include/asm-s390/irqflags.h
+ *
+ *    Copyright (C) IBM Corp. 2006
+ *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ */
+
+#ifndef __ASM_IRQFLAGS_H
+#define __ASM_IRQFLAGS_H
+
+#ifdef __KERNEL__
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+
+/* store then or system mask. */
+#define __raw_local_irq_stosm(__or)                                     \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stosm   %0,%1"                                  \
+                : "=Q" (__mask) : "i" (__or) : "memory");               \
+        __mask;                                                         \
+})
+
+/* store then and system mask. */
+#define __raw_local_irq_stnsm(__and)                                    \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stnsm   %0,%1"                                  \
+                : "=Q" (__mask) : "i" (__and) : "memory");              \
+        __mask;                                                         \
+})
+
+/* set system mask. */
+#define __raw_local_irq_ssm(__mask)                                     \
+({                                                                      \
+        asm volatile("ssm   %0" : : "Q" (__mask) : "memory");           \
+})
+
+#else /* __GNUC__ */
+
+/* store then or system mask. */
+#define __raw_local_irq_stosm(__or)                                     \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stosm   0(%1),%2"                               \
+                : "=m" (__mask)                                         \
+                : "a" (&__mask), "i" (__or) : "memory");                \
+        __mask;                                                         \
+})
+
+/* store then and system mask. */
+#define __raw_local_irq_stnsm(__and)                                    \
+({                                                                      \
+        unsigned long __mask;                                           \
+        asm volatile(                                                   \
+                "       stnsm   0(%1),%2"                               \
+                : "=m" (__mask)                                         \
+                : "a" (&__mask), "i" (__and) : "memory");               \
+        __mask;                                                         \
+})
+
+/* set system mask. */
+#define __raw_local_irq_ssm(__mask)                                     \
+({                                                                      \
+        asm volatile(                                                   \
+                "       ssm     0(%0)"                                  \
+                : : "a" (&__mask), "m" (__mask) : "memory");            \
+})
+
+#endif /* __GNUC__ */
+
+/* interrupt control.. */
+static inline unsigned long raw_local_irq_enable(void)
+{
+        return __raw_local_irq_stosm(0x03);
+}
+
+static inline unsigned long raw_local_irq_disable(void)
+{
+        return __raw_local_irq_stnsm(0xfc);
+}
+
+#define raw_local_save_flags(x)                                         \
+do {                                                                    \
+        typecheck(unsigned long, x);                                    \
+        (x) = __raw_local_irq_stosm(0x00);                              \
+} while (0)
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        __raw_local_irq_ssm(flags);
+}
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return !(flags & (3UL << (BITS_PER_LONG - 8)));
+}
+
+/* For spinlocks etc */
+#define raw_local_irq_save(x)   ((x) = raw_local_irq_disable())
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_IRQFLAGS_H */
diff --git a/arch/s390/include/asm/isc.h b/arch/s390/include/asm/isc.h
new file mode 100644
index 000000000000..34bb8916db4f
--- /dev/null
+++ b/arch/s390/include/asm/isc.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_S390_ISC_H
+#define _ASM_S390_ISC_H
+
+#include <linux/types.h>
+
+/*
+ * I/O interruption subclasses used by drivers.
+ * Please add all used iscs here so that it is possible to distribute
+ * isc usage between drivers.
+ * Reminder: 0 is highest priority, 7 lowest.
+ */
+#define MAX_ISC 7
+
+/* Regular I/O interrupts. */
+#define IO_SCH_ISC 3                    /* regular I/O subchannels */
+#define CONSOLE_ISC 1                   /* console I/O subchannel */
+#define CHSC_SCH_ISC 7                  /* CHSC subchannels */
+/* Adapter interrupts. */
+#define QDIO_AIRQ_ISC IO_SCH_ISC        /* I/O subchannel in qdio mode */
+
+/* Functions for registration of I/O interruption subclasses */
+void isc_register(unsigned int isc);
+void isc_unregister(unsigned int isc);
+
+#endif /* _ASM_S390_ISC_H */
diff --git a/arch/s390/include/asm/itcw.h b/arch/s390/include/asm/itcw.h
new file mode 100644
index 000000000000..a9bc5c36b32a
--- /dev/null
+++ b/arch/s390/include/asm/itcw.h
@@ -0,0 +1,30 @@
+/*
+ *  Functions for incremental construction of fcx enabled I/O control blocks.
+ *
+ *    Copyright IBM Corp. 2008
+ *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_ITCW_H
+#define _ASM_S390_ITCW_H _ASM_S390_ITCW_H
+
+#include <linux/types.h>
+#include <asm/fcx.h>
+
+#define ITCW_OP_READ    0
+#define ITCW_OP_WRITE   1
+
+struct itcw;
+
+struct tcw *itcw_get_tcw(struct itcw *itcw);
+size_t itcw_calc_size(int intrg, int max_tidaws, int intrg_max_tidaws);
+struct itcw *itcw_init(void *buffer, size_t size, int op, int intrg,
+                       int max_tidaws, int intrg_max_tidaws);
+struct dcw *itcw_add_dcw(struct itcw *itcw, u8 cmd, u8 flags, void *cd,
+                         u8 cd_count, u32 count);
+struct tidaw *itcw_add_tidaw(struct itcw *itcw, u8 flags, void *addr,
+                             u32 count);
+void itcw_set_data(struct itcw *itcw, void *addr, int use_tidal);
+void itcw_finalize(struct itcw *itcw);
+
+#endif /* _ASM_S390_ITCW_H */
diff --git a/arch/s390/include/asm/kdebug.h b/arch/s390/include/asm/kdebug.h
new file mode 100644
index 000000000000..40db27cd6e60
--- /dev/null
+++ b/arch/s390/include/asm/kdebug.h
@@ -0,0 +1,27 @@
+#ifndef _S390_KDEBUG_H
+#define _S390_KDEBUG_H
+
+/*
+ * Feb 2006 Ported to s390 <grundym@us.ibm.com>
+ */
+
+struct pt_regs;
+
+enum die_val {
+        DIE_OOPS = 1,
+        DIE_BPT,
+        DIE_SSTEP,
+        DIE_PANIC,
+        DIE_NMI,
+        DIE_DIE,
+        DIE_NMIWATCHDOG,
+        DIE_KERNELDEBUG,
+        DIE_TRAP,
+        DIE_GPF,
+        DIE_CALL,
+        DIE_NMI_IPI,
+};
+
+extern void die(const char *, struct pt_regs *, long);
+
+#endif
diff --git a/arch/s390/include/asm/kexec.h b/arch/s390/include/asm/kexec.h
new file mode 100644
index 000000000000..f219c6411e0b
--- /dev/null
+++ b/arch/s390/include/asm/kexec.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-s390/kexec.h
+ *
+ * (C) Copyright IBM Corp. 2005
+ *
+ * Author(s): Rolf Adelsberger <adelsberger@de.ibm.com>
+ *
+ */
+
+#ifndef _S390_KEXEC_H
+#define _S390_KEXEC_H
+
+#ifdef __KERNEL__
+#include <asm/page.h>
+#endif
+#include <asm/processor.h>
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+
+/* Maximum address we can use for the control pages */
+/* Not more than 2GB */
+#define KEXEC_CONTROL_MEMORY_LIMIT (1UL<<31)
+
+/* Allocate one page for the pdp and the second for the code */
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_S390
+
+/* Provide a dummy definition to avoid build failures. */
+static inline void crash_setup_regs(struct pt_regs *newregs,
+                                        struct pt_regs *oldregs) { }
+
+#endif /*_S390_KEXEC_H */
diff --git a/arch/s390/include/asm/kmap_types.h b/arch/s390/include/asm/kmap_types.h
new file mode 100644
index 000000000000..fd1574648223
--- /dev/null
+++ b/arch/s390/include/asm/kmap_types.h
@@ -0,0 +1,23 @@
+#ifdef __KERNEL__
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,    
+        KM_TYPE_NR
+};
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/arch/s390/include/asm/kprobes.h b/arch/s390/include/asm/kprobes.h
new file mode 100644
index 000000000000..330f68caffe4
--- /dev/null
+++ b/arch/s390/include/asm/kprobes.h
@@ -0,0 +1,103 @@
+#ifndef _ASM_S390_KPROBES_H
+#define _ASM_S390_KPROBES_H
+/*
+ *  Kernel Probes (KProbes)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2002, 2006
+ *
+ * 2002-Oct     Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
+ *              Probes initial implementation ( includes suggestions from
+ *              Rusty Russell).
+ * 2004-Nov     Modified for PPC64 by Ananth N Mavinakayanahalli
+ *              <ananth@in.ibm.com>
+ * 2005-Dec     Used as a template for s390 by Mike Grundy
+ *              <grundym@us.ibm.com>
+ */
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/percpu.h>
+
+#define  __ARCH_WANT_KPROBES_INSN_SLOT
+struct pt_regs;
+struct kprobe;
+
+typedef u16 kprobe_opcode_t;
+#define BREAKPOINT_INSTRUCTION  0x0002
+
+/* Maximum instruction size is 3 (16bit) halfwords: */
+#define MAX_INSN_SIZE           0x0003
+#define MAX_STACK_SIZE          64
+#define MIN_STACK_SIZE(ADDR) (((MAX_STACK_SIZE) < \
+        (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) \
+        ? (MAX_STACK_SIZE) \
+        : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
+
+#define kretprobe_blacklist_size 0
+
+#define KPROBE_SWAP_INST        0x10
+
+#define FIXUP_PSW_NORMAL        0x08
+#define FIXUP_BRANCH_NOT_TAKEN  0x04
+#define FIXUP_RETURN_REGISTER   0x02
+#define FIXUP_NOT_REQUIRED      0x01
+
+/* Architecture specific copy of original instruction */
+struct arch_specific_insn {
+        /* copy of original instruction */
+        kprobe_opcode_t *insn;
+        int fixup;
+        int ilen;
+        int reg;
+};
+
+struct ins_replace_args {
+        kprobe_opcode_t *ptr;
+        kprobe_opcode_t old;
+        kprobe_opcode_t new;
+};
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+        unsigned long saved_psw;
+        unsigned long kprobe_saved_imask;
+        unsigned long kprobe_saved_ctl[3];
+};
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long kprobe_saved_imask;
+        unsigned long kprobe_saved_ctl[3];
+        struct pt_regs jprobe_saved_regs;
+        unsigned long jprobe_saved_r14;
+        unsigned long jprobe_saved_r15;
+        struct prev_kprobe prev_kprobe;
+        kprobe_opcode_t jprobes_stack[MAX_STACK_SIZE];
+};
+
+void arch_remove_kprobe(struct kprobe *p);
+void kretprobe_trampoline(void);
+int  is_prohibited_opcode(kprobe_opcode_t *instruction);
+void get_instruction_type(struct arch_specific_insn *ainsn);
+
+int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
+int kprobe_exceptions_notify(struct notifier_block *self,
+        unsigned long val, void *data);
+
+#define flush_insn_slot(p)      do { } while (0)
+
+#endif  /* _ASM_S390_KPROBES_H */
diff --git a/arch/s390/include/asm/kvm.h b/arch/s390/include/asm/kvm.h
new file mode 100644
index 000000000000..d74002f95794
--- /dev/null
+++ b/arch/s390/include/asm/kvm.h
@@ -0,0 +1,45 @@
+#ifndef __LINUX_KVM_S390_H
+#define __LINUX_KVM_S390_H
+
+/*
+ * asm-s390/kvm.h - KVM s390 specific structures and definitions
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ *    Author(s): Carsten Otte <cotte@de.ibm.com>
+ *               Christian Borntraeger <borntraeger@de.ibm.com>
+ */
+#include <asm/types.h>
+
+/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
+struct kvm_pic_state {
+        /* no PIC for s390 */
+};
+
+struct kvm_ioapic_state {
+        /* no IOAPIC for s390 */
+};
+
+/* for KVM_GET_REGS and KVM_SET_REGS */
+struct kvm_regs {
+        /* general purpose regs for s390 */
+        __u64 gprs[16];
+};
+
+/* for KVM_GET_SREGS and KVM_SET_SREGS */
+struct kvm_sregs {
+        __u32 acrs[16];
+        __u64 crs[16];
+};
+
+/* for KVM_GET_FPU and KVM_SET_FPU */
+struct kvm_fpu {
+        __u32 fpc;
+        __u64 fprs[16];
+};
+
+#endif
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
new file mode 100644
index 000000000000..3c55e4107dcc
--- /dev/null
+++ b/arch/s390/include/asm/kvm_host.h
@@ -0,0 +1,235 @@
+/*
+ * asm-s390/kvm_host.h - definition for kernel virtual machines on s390
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ *    Author(s): Carsten Otte <cotte@de.ibm.com>
+ */
+
+
+#ifndef ASM_KVM_HOST_H
+#define ASM_KVM_HOST_H
+#include <linux/kvm_host.h>
+#include <asm/debug.h>
+
+#define KVM_MAX_VCPUS 64
+#define KVM_MEMORY_SLOTS 32
+/* memory slots that does not exposed to userspace */
+#define KVM_PRIVATE_MEM_SLOTS 4
+
+struct kvm_guest_debug {
+};
+
+struct sca_entry {
+        atomic_t scn;
+        __u64   reserved;
+        __u64   sda;
+        __u64   reserved2[2];
+} __attribute__((packed));
+
+
+struct sca_block {
+        __u64   ipte_control;
+        __u64   reserved[5];
+        __u64   mcn;
+        __u64   reserved2;
+        struct sca_entry cpu[64];
+} __attribute__((packed));
+
+#define KVM_PAGES_PER_HPAGE 256
+
+#define CPUSTAT_HOST       0x80000000
+#define CPUSTAT_WAIT       0x10000000
+#define CPUSTAT_ECALL_PEND 0x08000000
+#define CPUSTAT_STOP_INT   0x04000000
+#define CPUSTAT_IO_INT     0x02000000
+#define CPUSTAT_EXT_INT    0x01000000
+#define CPUSTAT_RUNNING    0x00800000
+#define CPUSTAT_RETAINED   0x00400000
+#define CPUSTAT_TIMING_SUB 0x00020000
+#define CPUSTAT_SIE_SUB    0x00010000
+#define CPUSTAT_RRF        0x00008000
+#define CPUSTAT_SLSV       0x00004000
+#define CPUSTAT_SLSR       0x00002000
+#define CPUSTAT_ZARCH      0x00000800
+#define CPUSTAT_MCDS       0x00000100
+#define CPUSTAT_SM         0x00000080
+#define CPUSTAT_G          0x00000008
+#define CPUSTAT_J          0x00000002
+#define CPUSTAT_P          0x00000001
+
+struct kvm_s390_sie_block {
+        atomic_t cpuflags;              /* 0x0000 */
+        __u32   prefix;                 /* 0x0004 */
+        __u8    reserved8[32];          /* 0x0008 */
+        __u64   cputm;                  /* 0x0028 */
+        __u64   ckc;                    /* 0x0030 */
+        __u64   epoch;                  /* 0x0038 */
+        __u8    reserved40[4];          /* 0x0040 */
+#define LCTL_CR0        0x8000
+        __u16   lctl;                   /* 0x0044 */
+        __s16   icpua;                  /* 0x0046 */
+        __u32   ictl;                   /* 0x0048 */
+        __u32   eca;                    /* 0x004c */
+        __u8    icptcode;               /* 0x0050 */
+        __u8    reserved51;             /* 0x0051 */
+        __u16   ihcpu;                  /* 0x0052 */
+        __u8    reserved54[2];          /* 0x0054 */
+        __u16   ipa;                    /* 0x0056 */
+        __u32   ipb;                    /* 0x0058 */
+        __u32   scaoh;                  /* 0x005c */
+        __u8    reserved60;             /* 0x0060 */
+        __u8    ecb;                    /* 0x0061 */
+        __u8    reserved62[2];          /* 0x0062 */
+        __u32   scaol;                  /* 0x0064 */
+        __u8    reserved68[4];          /* 0x0068 */
+        __u32   todpr;                  /* 0x006c */
+        __u8    reserved70[16];         /* 0x0070 */
+        __u64   gmsor;                  /* 0x0080 */
+        __u64   gmslm;                  /* 0x0088 */
+        psw_t   gpsw;                   /* 0x0090 */
+        __u64   gg14;                   /* 0x00a0 */
+        __u64   gg15;                   /* 0x00a8 */
+        __u8    reservedb0[30];         /* 0x00b0 */
+        __u16   iprcc;                  /* 0x00ce */
+        __u8    reservedd0[48];         /* 0x00d0 */
+        __u64   gcr[16];                /* 0x0100 */
+        __u64   gbea;                   /* 0x0180 */
+        __u8    reserved188[120];       /* 0x0188 */
+} __attribute__((packed));
+
+struct kvm_vcpu_stat {
+        u32 exit_userspace;
+        u32 exit_null;
+        u32 exit_external_request;
+        u32 exit_external_interrupt;
+        u32 exit_stop_request;
+        u32 exit_validity;
+        u32 exit_instruction;
+        u32 instruction_lctl;
+        u32 instruction_lctlg;
+        u32 exit_program_interruption;
+        u32 exit_instr_and_program;
+        u32 deliver_emergency_signal;
+        u32 deliver_service_signal;
+        u32 deliver_virtio_interrupt;
+        u32 deliver_stop_signal;
+        u32 deliver_prefix_signal;
+        u32 deliver_restart_signal;
+        u32 deliver_program_int;
+        u32 exit_wait_state;
+        u32 instruction_stidp;
+        u32 instruction_spx;
+        u32 instruction_stpx;
+        u32 instruction_stap;
+        u32 instruction_storage_key;
+        u32 instruction_stsch;
+        u32 instruction_chsc;
+        u32 instruction_stsi;
+        u32 instruction_stfl;
+        u32 instruction_sigp_sense;
+        u32 instruction_sigp_emergency;
+        u32 instruction_sigp_stop;
+        u32 instruction_sigp_arch;
+        u32 instruction_sigp_prefix;
+        u32 instruction_sigp_restart;
+        u32 diagnose_44;
+};
+
+struct kvm_s390_io_info {
+        __u16        subchannel_id;            /* 0x0b8 */
+        __u16        subchannel_nr;            /* 0x0ba */
+        __u32        io_int_parm;              /* 0x0bc */
+        __u32        io_int_word;              /* 0x0c0 */
+};
+
+struct kvm_s390_ext_info {
+        __u32 ext_params;
+        __u64 ext_params2;
+};
+
+#define PGM_OPERATION            0x01
+#define PGM_PRIVILEGED_OPERATION 0x02
+#define PGM_EXECUTE              0x03
+#define PGM_PROTECTION           0x04
+#define PGM_ADDRESSING           0x05
+#define PGM_SPECIFICATION        0x06
+#define PGM_DATA                 0x07
+
+struct kvm_s390_pgm_info {
+        __u16 code;
+};
+
+struct kvm_s390_prefix_info {
+        __u32 address;
+};
+
+struct kvm_s390_interrupt_info {
+        struct list_head list;
+        u64     type;
+        union {
+                struct kvm_s390_io_info io;
+                struct kvm_s390_ext_info ext;
+                struct kvm_s390_pgm_info pgm;
+                struct kvm_s390_prefix_info prefix;
+        };
+};
+
+/* for local_interrupt.action_flags */
+#define ACTION_STORE_ON_STOP 1
+#define ACTION_STOP_ON_STOP  2
+
+struct kvm_s390_local_interrupt {
+        spinlock_t lock;
+        struct list_head list;
+        atomic_t active;
+        struct kvm_s390_float_interrupt *float_int;
+        int timer_due; /* event indicator for waitqueue below */
+        wait_queue_head_t wq;
+        atomic_t *cpuflags;
+        unsigned int action_bits;
+};
+
+struct kvm_s390_float_interrupt {
+        spinlock_t lock;
+        struct list_head list;
+        atomic_t active;
+        int next_rr_cpu;
+        unsigned long idle_mask [(64 + sizeof(long) - 1) / sizeof(long)];
+        struct kvm_s390_local_interrupt *local_int[64];
+};
+
+
+struct kvm_vcpu_arch {
+        struct kvm_s390_sie_block *sie_block;
+        unsigned long     guest_gprs[16];
+        s390_fp_regs      host_fpregs;
+        unsigned int      host_acrs[NUM_ACRS];
+        s390_fp_regs      guest_fpregs;
+        unsigned int      guest_acrs[NUM_ACRS];
+        struct kvm_s390_local_interrupt local_int;
+        struct timer_list ckc_timer;
+        union  {
+                cpuid_t   cpu_id;
+                u64       stidp_data;
+        };
+};
+
+struct kvm_vm_stat {
+        u32 remote_tlb_flush;
+};
+
+struct kvm_arch{
+        unsigned long guest_origin;
+        unsigned long guest_memsize;
+        struct sca_block *sca;
+        debug_info_t *dbf;
+        struct kvm_s390_float_interrupt float_int;
+};
+
+extern int sie64a(struct kvm_s390_sie_block *, unsigned long *);
+#endif
diff --git a/arch/s390/include/asm/kvm_para.h b/arch/s390/include/asm/kvm_para.h
new file mode 100644
index 000000000000..2c503796b619
--- /dev/null
+++ b/arch/s390/include/asm/kvm_para.h
@@ -0,0 +1,150 @@
+/*
+ * asm-s390/kvm_para.h - definition for paravirtual devices on s390
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ *    Author(s): Christian Borntraeger <borntraeger@de.ibm.com>
+ */
+
+#ifndef __S390_KVM_PARA_H
+#define __S390_KVM_PARA_H
+
+/*
+ * Hypercalls for KVM on s390. The calling convention is similar to the
+ * s390 ABI, so we use R2-R6 for parameters 1-5. In addition we use R1
+ * as hypercall number and R7 as parameter 6. The return value is
+ * written to R2. We use the diagnose instruction as hypercall. To avoid
+ * conflicts with existing diagnoses for LPAR and z/VM, we do not use
+ * the instruction encoded number, but specify the number in R1 and
+ * use 0x500 as KVM hypercall
+ *
+ * Copyright IBM Corp. 2007,2008
+ * Author(s): Christian Borntraeger <borntraeger@de.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.
+ */
+
+static inline long kvm_hypercall0(unsigned long nr)
+{
+        register unsigned long __nr asm("1") = nr;
+        register long __rc asm("2");
+
+        asm volatile ("diag 2,4,0x500\n"
+                      : "=d" (__rc) : "d" (__nr): "memory", "cc");
+        return __rc;
+}
+
+static inline long kvm_hypercall1(unsigned long nr, unsigned long p1)
+{
+        register unsigned long __nr asm("1") = nr;
+        register unsigned long __p1 asm("2") = p1;
+        register long __rc asm("2");
+
+        asm volatile ("diag 2,4,0x500\n"
+                      : "=d" (__rc) : "d" (__nr), "0" (__p1) : "memory", "cc");
+        return __rc;
+}
+
+static inline long kvm_hypercall2(unsigned long nr, unsigned long p1,
+                               unsigned long p2)
+{
+        register unsigned long __nr asm("1") = nr;
+        register unsigned long __p1 asm("2") = p1;
+        register unsigned long __p2 asm("3") = p2;
+        register long __rc asm("2");
+
+        asm volatile ("diag 2,4,0x500\n"
+                      : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2)
+                      : "memory", "cc");
+        return __rc;
+}
+
+static inline long kvm_hypercall3(unsigned long nr, unsigned long p1,
+                               unsigned long p2, unsigned long p3)
+{
+        register unsigned long __nr asm("1") = nr;
+        register unsigned long __p1 asm("2") = p1;
+        register unsigned long __p2 asm("3") = p2;
+        register unsigned long __p3 asm("4") = p3;
+        register long __rc asm("2");
+
+        asm volatile ("diag 2,4,0x500\n"
+                      : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
+                        "d" (__p3) : "memory", "cc");
+        return __rc;
+}
+
+
+static inline long kvm_hypercall4(unsigned long nr, unsigned long p1,
+                               unsigned long p2, unsigned long p3,
+                               unsigned long p4)
+{
+        register unsigned long __nr asm("1") = nr;
+        register unsigned long __p1 asm("2") = p1;
+        register unsigned long __p2 asm("3") = p2;
+        register unsigned long __p3 asm("4") = p3;
+        register unsigned long __p4 asm("5") = p4;
+        register long __rc asm("2");
+
+        asm volatile ("diag 2,4,0x500\n"
+                      : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
+                        "d" (__p3), "d" (__p4) : "memory", "cc");
+        return __rc;
+}
+
+static inline long kvm_hypercall5(unsigned long nr, unsigned long p1,
+                               unsigned long p2, unsigned long p3,
+                               unsigned long p4, unsigned long p5)
+{
+        register unsigned long __nr asm("1") = nr;
+        register unsigned long __p1 asm("2") = p1;
+        register unsigned long __p2 asm("3") = p2;
+        register unsigned long __p3 asm("4") = p3;
+        register unsigned long __p4 asm("5") = p4;
+        register unsigned long __p5 asm("6") = p5;
+        register long __rc asm("2");
+
+        asm volatile ("diag 2,4,0x500\n"
+                      : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
+                        "d" (__p3), "d" (__p4), "d" (__p5)  : "memory", "cc");
+        return __rc;
+}
+
+static inline long kvm_hypercall6(unsigned long nr, unsigned long p1,
+                               unsigned long p2, unsigned long p3,
+                               unsigned long p4, unsigned long p5,
+                               unsigned long p6)
+{
+        register unsigned long __nr asm("1") = nr;
+        register unsigned long __p1 asm("2") = p1;
+        register unsigned long __p2 asm("3") = p2;
+        register unsigned long __p3 asm("4") = p3;
+        register unsigned long __p4 asm("5") = p4;
+        register unsigned long __p5 asm("6") = p5;
+        register unsigned long __p6 asm("7") = p6;
+        register long __rc asm("2");
+
+        asm volatile ("diag 2,4,0x500\n"
+                      : "=d" (__rc) : "d" (__nr), "0" (__p1), "d" (__p2),
+                        "d" (__p3), "d" (__p4), "d" (__p5), "d" (__p6)
+                      : "memory", "cc");
+        return __rc;
+}
+
+/* kvm on s390 is always paravirtualization enabled */
+static inline int kvm_para_available(void)
+{
+        return 1;
+}
+
+/* No feature bits are currently assigned for kvm on s390 */
+static inline unsigned int kvm_arch_para_features(void)
+{
+        return 0;
+}
+
+#endif /* __S390_KVM_PARA_H */
diff --git a/arch/s390/include/asm/kvm_virtio.h b/arch/s390/include/asm/kvm_virtio.h
new file mode 100644
index 000000000000..146100224def
--- /dev/null
+++ b/arch/s390/include/asm/kvm_virtio.h
@@ -0,0 +1,63 @@
+/*
+ * kvm_virtio.h - definition for virtio for kvm on s390
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ *    Author(s): Christian Borntraeger <borntraeger@de.ibm.com>
+ */
+
+#ifndef __KVM_S390_VIRTIO_H
+#define __KVM_S390_VIRTIO_H
+
+#include <linux/types.h>
+
+struct kvm_device_desc {
+        /* The device type: console, network, disk etc.  Type 0 terminates. */
+        __u8 type;
+        /* The number of virtqueues (first in config array) */
+        __u8 num_vq;
+        /*
+         * The number of bytes of feature bits.  Multiply by 2: one for host
+         * features and one for guest acknowledgements.
+         */
+        __u8 feature_len;
+        /* The number of bytes of the config array after virtqueues. */
+        __u8 config_len;
+        /* A status byte, written by the Guest. */
+        __u8 status;
+        __u8 config[0];
+};
+
+/*
+ * This is how we expect the device configuration field for a virtqueue
+ * to be laid out in config space.
+ */
+struct kvm_vqconfig {
+        /* The token returned with an interrupt. Set by the guest */
+        __u64 token;
+        /* The address of the virtio ring */
+        __u64 address;
+        /* The number of entries in the virtio_ring */
+        __u16 num;
+
+};
+
+#define KVM_S390_VIRTIO_NOTIFY          0
+#define KVM_S390_VIRTIO_RESET           1
+#define KVM_S390_VIRTIO_SET_STATUS      2
+
+#ifdef __KERNEL__
+/* early virtio console setup */
+#ifdef CONFIG_VIRTIO_CONSOLE
+extern void s390_virtio_console_init(void);
+#else
+static inline void s390_virtio_console_init(void)
+{
+}
+#endif /* CONFIG_VIRTIO_CONSOLE */
+#endif /* __KERNEL__ */
+#endif
diff --git a/arch/s390/include/asm/linkage.h b/arch/s390/include/asm/linkage.h
new file mode 100644
index 000000000000..291c2d01c44f
--- /dev/null
+++ b/arch/s390/include/asm/linkage.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* Nothing to see here... */
+
+#endif
diff --git a/arch/s390/include/asm/local.h b/arch/s390/include/asm/local.h
new file mode 100644
index 000000000000..c11c530f74d0
--- /dev/null
+++ b/arch/s390/include/asm/local.h
@@ -0,0 +1 @@
+#include <asm-generic/local.h>
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
new file mode 100644
index 000000000000..0bc51d52a899
--- /dev/null
+++ b/arch/s390/include/asm/lowcore.h
@@ -0,0 +1,433 @@
+/*
+ *  include/asm-s390/lowcore.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Hartmut Penner (hp@de.ibm.com),
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
+ */
+
+#ifndef _ASM_S390_LOWCORE_H
+#define _ASM_S390_LOWCORE_H
+
+#ifndef __s390x__
+#define __LC_EXT_OLD_PSW                0x018
+#define __LC_SVC_OLD_PSW                0x020
+#define __LC_PGM_OLD_PSW                0x028
+#define __LC_MCK_OLD_PSW                0x030
+#define __LC_IO_OLD_PSW                 0x038
+#define __LC_EXT_NEW_PSW                0x058
+#define __LC_SVC_NEW_PSW                0x060
+#define __LC_PGM_NEW_PSW                0x068
+#define __LC_MCK_NEW_PSW                0x070
+#define __LC_IO_NEW_PSW                 0x078
+#else /* !__s390x__ */
+#define __LC_EXT_OLD_PSW                0x0130
+#define __LC_SVC_OLD_PSW                0x0140
+#define __LC_PGM_OLD_PSW                0x0150
+#define __LC_MCK_OLD_PSW                0x0160
+#define __LC_IO_OLD_PSW                 0x0170
+#define __LC_EXT_NEW_PSW                0x01b0
+#define __LC_SVC_NEW_PSW                0x01c0
+#define __LC_PGM_NEW_PSW                0x01d0
+#define __LC_MCK_NEW_PSW                0x01e0
+#define __LC_IO_NEW_PSW                 0x01f0
+#endif /* !__s390x__ */
+
+#define __LC_IPL_PARMBLOCK_PTR          0x014
+#define __LC_EXT_PARAMS                 0x080
+#define __LC_CPU_ADDRESS                0x084
+#define __LC_EXT_INT_CODE               0x086
+
+#define __LC_SVC_ILC                    0x088
+#define __LC_SVC_INT_CODE               0x08A
+#define __LC_PGM_ILC                    0x08C
+#define __LC_PGM_INT_CODE               0x08E
+
+#define __LC_PER_ATMID                  0x096
+#define __LC_PER_ADDRESS                0x098
+#define __LC_PER_ACCESS_ID              0x0A1
+#define __LC_AR_MODE_ID                 0x0A3
+
+#define __LC_SUBCHANNEL_ID              0x0B8
+#define __LC_SUBCHANNEL_NR              0x0BA
+#define __LC_IO_INT_PARM                0x0BC
+#define __LC_IO_INT_WORD                0x0C0
+#define __LC_MCCK_CODE                  0x0E8
+
+#define __LC_LAST_BREAK                 0x110
+
+#define __LC_RETURN_PSW                 0x200
+
+#define __LC_SAVE_AREA                  0xC00
+
+#ifndef __s390x__
+#define __LC_IRB                        0x208
+#define __LC_SYNC_ENTER_TIMER           0x248
+#define __LC_ASYNC_ENTER_TIMER          0x250
+#define __LC_EXIT_TIMER                 0x258
+#define __LC_LAST_UPDATE_TIMER          0x260
+#define __LC_USER_TIMER                 0x268
+#define __LC_SYSTEM_TIMER               0x270
+#define __LC_LAST_UPDATE_CLOCK          0x278
+#define __LC_STEAL_CLOCK                0x280
+#define __LC_RETURN_MCCK_PSW            0x288
+#define __LC_KERNEL_STACK               0xC40
+#define __LC_THREAD_INFO                0xC44
+#define __LC_ASYNC_STACK                0xC48
+#define __LC_KERNEL_ASCE                0xC4C
+#define __LC_USER_ASCE                  0xC50
+#define __LC_PANIC_STACK                0xC54
+#define __LC_CPUID                      0xC60
+#define __LC_CPUADDR                    0xC68
+#define __LC_IPLDEV                     0xC7C
+#define __LC_CURRENT                    0xC90
+#define __LC_INT_CLOCK                  0xC98
+#else /* __s390x__ */
+#define __LC_IRB                        0x210
+#define __LC_SYNC_ENTER_TIMER           0x250
+#define __LC_ASYNC_ENTER_TIMER          0x258
+#define __LC_EXIT_TIMER                 0x260
+#define __LC_LAST_UPDATE_TIMER          0x268
+#define __LC_USER_TIMER                 0x270
+#define __LC_SYSTEM_TIMER               0x278
+#define __LC_LAST_UPDATE_CLOCK          0x280
+#define __LC_STEAL_CLOCK                0x288
+#define __LC_RETURN_MCCK_PSW            0x290
+#define __LC_KERNEL_STACK               0xD40
+#define __LC_THREAD_INFO                0xD48
+#define __LC_ASYNC_STACK                0xD50
+#define __LC_KERNEL_ASCE                0xD58
+#define __LC_USER_ASCE                  0xD60
+#define __LC_PANIC_STACK                0xD68
+#define __LC_CPUID                      0xD80
+#define __LC_CPUADDR                    0xD88
+#define __LC_IPLDEV                     0xDB8
+#define __LC_CURRENT                    0xDD8
+#define __LC_INT_CLOCK                  0xDE8
+#endif /* __s390x__ */
+
+
+#define __LC_PANIC_MAGIC                0xE00
+#ifndef __s390x__
+#define __LC_PFAULT_INTPARM             0x080
+#define __LC_CPU_TIMER_SAVE_AREA        0x0D8
+#define __LC_CLOCK_COMP_SAVE_AREA       0x0E0
+#define __LC_PSW_SAVE_AREA              0x100
+#define __LC_PREFIX_SAVE_AREA           0x108
+#define __LC_AREGS_SAVE_AREA            0x120
+#define __LC_FPREGS_SAVE_AREA           0x160
+#define __LC_GPREGS_SAVE_AREA           0x180
+#define __LC_CREGS_SAVE_AREA            0x1C0
+#else /* __s390x__ */
+#define __LC_PFAULT_INTPARM             0x11B8
+#define __LC_FPREGS_SAVE_AREA           0x1200
+#define __LC_GPREGS_SAVE_AREA           0x1280
+#define __LC_PSW_SAVE_AREA              0x1300
+#define __LC_PREFIX_SAVE_AREA           0x1318
+#define __LC_FP_CREG_SAVE_AREA          0x131C
+#define __LC_TODREG_SAVE_AREA           0x1324
+#define __LC_CPU_TIMER_SAVE_AREA        0x1328
+#define __LC_CLOCK_COMP_SAVE_AREA       0x1331
+#define __LC_AREGS_SAVE_AREA            0x1340
+#define __LC_CREGS_SAVE_AREA            0x1380
+#endif /* __s390x__ */
+
+#ifndef __ASSEMBLY__
+
+#include <asm/processor.h>
+#include <linux/types.h>
+#include <asm/sigp.h>
+
+void restart_int_handler(void);
+void ext_int_handler(void);
+void system_call(void);
+void pgm_check_handler(void);
+void mcck_int_handler(void);
+void io_int_handler(void);
+
+struct save_area_s390 {
+        u32     ext_save;
+        u64     timer;
+        u64     clk_cmp;
+        u8      pad1[24];
+        u8      psw[8];
+        u32     pref_reg;
+        u8      pad2[20];
+        u32     acc_regs[16];
+        u64     fp_regs[4];
+        u32     gp_regs[16];
+        u32     ctrl_regs[16];
+}  __attribute__((packed));
+
+struct save_area_s390x {
+        u64     fp_regs[16];
+        u64     gp_regs[16];
+        u8      psw[16];
+        u8      pad1[8];
+        u32     pref_reg;
+        u32     fp_ctrl_reg;
+        u8      pad2[4];
+        u32     tod_reg;
+        u64     timer;
+        u64     clk_cmp;
+        u8      pad3[8];
+        u32     acc_regs[16];
+        u64     ctrl_regs[16];
+}  __attribute__((packed));
+
+union save_area {
+        struct save_area_s390   s390;
+        struct save_area_s390x  s390x;
+};
+
+#define SAVE_AREA_BASE_S390     0xd4
+#define SAVE_AREA_BASE_S390X    0x1200
+
+#ifndef __s390x__
+#define SAVE_AREA_SIZE sizeof(struct save_area_s390)
+#define SAVE_AREA_BASE SAVE_AREA_BASE_S390
+#else
+#define SAVE_AREA_SIZE sizeof(struct save_area_s390x)
+#define SAVE_AREA_BASE SAVE_AREA_BASE_S390X
+#endif
+
+struct _lowcore
+{
+#ifndef __s390x__
+        /* prefix area: defined by architecture */
+        psw_t        restart_psw;              /* 0x000 */
+        __u32        ccw2[4];                  /* 0x008 */
+        psw_t        external_old_psw;         /* 0x018 */
+        psw_t        svc_old_psw;              /* 0x020 */
+        psw_t        program_old_psw;          /* 0x028 */
+        psw_t        mcck_old_psw;             /* 0x030 */
+        psw_t        io_old_psw;               /* 0x038 */
+        __u8         pad1[0x58-0x40];          /* 0x040 */
+        psw_t        external_new_psw;         /* 0x058 */
+        psw_t        svc_new_psw;              /* 0x060 */
+        psw_t        program_new_psw;          /* 0x068 */
+        psw_t        mcck_new_psw;             /* 0x070 */
+        psw_t        io_new_psw;               /* 0x078 */
+        __u32        ext_params;               /* 0x080 */
+        __u16        cpu_addr;                 /* 0x084 */
+        __u16        ext_int_code;             /* 0x086 */
+        __u16        svc_ilc;                  /* 0x088 */
+        __u16        svc_code;                 /* 0x08a */
+        __u16        pgm_ilc;                  /* 0x08c */
+        __u16        pgm_code;                 /* 0x08e */
+        __u32        trans_exc_code;           /* 0x090 */
+        __u16        mon_class_num;            /* 0x094 */
+        __u16        per_perc_atmid;           /* 0x096 */
+        __u32        per_address;              /* 0x098 */
+        __u32        monitor_code;             /* 0x09c */
+        __u8         exc_access_id;            /* 0x0a0 */
+        __u8         per_access_id;            /* 0x0a1 */
+        __u8         pad2[0xB8-0xA2];          /* 0x0a2 */
+        __u16        subchannel_id;            /* 0x0b8 */
+        __u16        subchannel_nr;            /* 0x0ba */
+        __u32        io_int_parm;              /* 0x0bc */
+        __u32        io_int_word;              /* 0x0c0 */
+        __u8         pad3[0xc8-0xc4];          /* 0x0c4 */
+        __u32        stfl_fac_list;            /* 0x0c8 */
+        __u8         pad4[0xd4-0xcc];          /* 0x0cc */
+        __u32        extended_save_area_addr;  /* 0x0d4 */
+        __u32        cpu_timer_save_area[2];   /* 0x0d8 */
+        __u32        clock_comp_save_area[2];  /* 0x0e0 */
+        __u32        mcck_interruption_code[2]; /* 0x0e8 */
+        __u8         pad5[0xf4-0xf0];          /* 0x0f0 */
+        __u32        external_damage_code;     /* 0x0f4 */
+        __u32        failing_storage_address;  /* 0x0f8 */
+        __u8         pad6[0x100-0xfc];         /* 0x0fc */
+        __u32        st_status_fixed_logout[4];/* 0x100 */
+        __u8         pad7[0x120-0x110];        /* 0x110 */
+        __u32        access_regs_save_area[16];/* 0x120 */
+        __u32        floating_pt_save_area[8]; /* 0x160 */
+        __u32        gpregs_save_area[16];     /* 0x180 */
+        __u32        cregs_save_area[16];      /* 0x1c0 */      
+
+        psw_t        return_psw;               /* 0x200 */
+        __u8         irb[64];                  /* 0x208 */
+        __u64        sync_enter_timer;         /* 0x248 */
+        __u64        async_enter_timer;        /* 0x250 */
+        __u64        exit_timer;               /* 0x258 */
+        __u64        last_update_timer;        /* 0x260 */
+        __u64        user_timer;               /* 0x268 */
+        __u64        system_timer;             /* 0x270 */
+        __u64        last_update_clock;        /* 0x278 */
+        __u64        steal_clock;              /* 0x280 */
+        psw_t        return_mcck_psw;          /* 0x288 */
+        __u8         pad8[0xc00-0x290];        /* 0x290 */
+
+        /* System info area */
+        __u32        save_area[16];            /* 0xc00 */
+        __u32        kernel_stack;             /* 0xc40 */
+        __u32        thread_info;              /* 0xc44 */
+        __u32        async_stack;              /* 0xc48 */
+        __u32        kernel_asce;              /* 0xc4c */
+        __u32        user_asce;                /* 0xc50 */
+        __u32        panic_stack;              /* 0xc54 */
+        __u32        user_exec_asce;           /* 0xc58 */
+        __u8         pad10[0xc60-0xc5c];       /* 0xc5c */
+        /* entry.S sensitive area start */
+        struct       cpuinfo_S390 cpu_data;    /* 0xc60 */
+        __u32        ipl_device;               /* 0xc7c */
+        /* entry.S sensitive area end */
+
+        /* SMP info area: defined by DJB */
+        __u64        clock_comparator;         /* 0xc80 */
+        __u32        ext_call_fast;            /* 0xc88 */
+        __u32        percpu_offset;            /* 0xc8c */
+        __u32        current_task;             /* 0xc90 */
+        __u32        softirq_pending;          /* 0xc94 */
+        __u64        int_clock;                /* 0xc98 */
+        __u8         pad11[0xe00-0xca0];       /* 0xca0 */
+
+        /* 0xe00 is used as indicator for dump tools */
+        /* whether the kernel died with panic() or not */
+        __u32        panic_magic;              /* 0xe00 */
+
+        /* Align to the top 1k of prefix area */
+        __u8         pad12[0x1000-0xe04];      /* 0xe04 */
+#else /* !__s390x__ */
+        /* prefix area: defined by architecture */
+        __u32        ccw1[2];                  /* 0x000 */
+        __u32        ccw2[4];                  /* 0x008 */
+        __u8         pad1[0x80-0x18];          /* 0x018 */
+        __u32        ext_params;               /* 0x080 */
+        __u16        cpu_addr;                 /* 0x084 */
+        __u16        ext_int_code;             /* 0x086 */
+        __u16        svc_ilc;                  /* 0x088 */
+        __u16        svc_code;                 /* 0x08a */
+        __u16        pgm_ilc;                  /* 0x08c */
+        __u16        pgm_code;                 /* 0x08e */
+        __u32        data_exc_code;            /* 0x090 */
+        __u16        mon_class_num;            /* 0x094 */
+        __u16        per_perc_atmid;           /* 0x096 */
+        addr_t       per_address;              /* 0x098 */
+        __u8         exc_access_id;            /* 0x0a0 */
+        __u8         per_access_id;            /* 0x0a1 */
+        __u8         op_access_id;             /* 0x0a2 */
+        __u8         ar_access_id;             /* 0x0a3 */
+        __u8         pad2[0xA8-0xA4];          /* 0x0a4 */
+        addr_t       trans_exc_code;           /* 0x0A0 */
+        addr_t       monitor_code;             /* 0x09c */
+        __u16        subchannel_id;            /* 0x0b8 */
+        __u16        subchannel_nr;            /* 0x0ba */
+        __u32        io_int_parm;              /* 0x0bc */
+        __u32        io_int_word;              /* 0x0c0 */
+        __u8         pad3[0xc8-0xc4];          /* 0x0c4 */
+        __u32        stfl_fac_list;            /* 0x0c8 */
+        __u8         pad4[0xe8-0xcc];          /* 0x0cc */
+        __u32        mcck_interruption_code[2]; /* 0x0e8 */
+        __u8         pad5[0xf4-0xf0];          /* 0x0f0 */
+        __u32        external_damage_code;     /* 0x0f4 */
+        addr_t       failing_storage_address;  /* 0x0f8 */
+        __u8         pad6[0x120-0x100];        /* 0x100 */
+        psw_t        restart_old_psw;          /* 0x120 */
+        psw_t        external_old_psw;         /* 0x130 */
+        psw_t        svc_old_psw;              /* 0x140 */
+        psw_t        program_old_psw;          /* 0x150 */
+        psw_t        mcck_old_psw;             /* 0x160 */
+        psw_t        io_old_psw;               /* 0x170 */
+        __u8         pad7[0x1a0-0x180];        /* 0x180 */
+        psw_t        restart_psw;              /* 0x1a0 */
+        psw_t        external_new_psw;         /* 0x1b0 */
+        psw_t        svc_new_psw;              /* 0x1c0 */
+        psw_t        program_new_psw;          /* 0x1d0 */
+        psw_t        mcck_new_psw;             /* 0x1e0 */
+        psw_t        io_new_psw;               /* 0x1f0 */
+        psw_t        return_psw;               /* 0x200 */
+        __u8         irb[64];                  /* 0x210 */
+        __u64        sync_enter_timer;         /* 0x250 */
+        __u64        async_enter_timer;        /* 0x258 */
+        __u64        exit_timer;               /* 0x260 */
+        __u64        last_update_timer;        /* 0x268 */
+        __u64        user_timer;               /* 0x270 */
+        __u64        system_timer;             /* 0x278 */
+        __u64        last_update_clock;        /* 0x280 */
+        __u64        steal_clock;              /* 0x288 */
+        psw_t        return_mcck_psw;          /* 0x290 */
+        __u8         pad8[0xc00-0x2a0];        /* 0x2a0 */
+        /* System info area */
+        __u64        save_area[16];            /* 0xc00 */
+        __u8         pad9[0xd40-0xc80];        /* 0xc80 */
+        __u64        kernel_stack;             /* 0xd40 */
+        __u64        thread_info;              /* 0xd48 */
+        __u64        async_stack;              /* 0xd50 */
+        __u64        kernel_asce;              /* 0xd58 */
+        __u64        user_asce;                /* 0xd60 */
+        __u64        panic_stack;              /* 0xd68 */
+        __u64        user_exec_asce;           /* 0xd70 */
+        __u8         pad10[0xd80-0xd78];       /* 0xd78 */
+        /* entry.S sensitive area start */
+        struct       cpuinfo_S390 cpu_data;    /* 0xd80 */
+        __u32        ipl_device;               /* 0xdb8 */
+        __u32        pad11;                    /* 0xdbc */
+        /* entry.S sensitive area end */
+
+        /* SMP info area: defined by DJB */
+        __u64        clock_comparator;         /* 0xdc0 */
+        __u64        ext_call_fast;            /* 0xdc8 */
+        __u64        percpu_offset;            /* 0xdd0 */
+        __u64        current_task;             /* 0xdd8 */
+        __u32        softirq_pending;          /* 0xde0 */
+        __u32        pad_0x0de4;               /* 0xde4 */
+        __u64        int_clock;                /* 0xde8 */
+        __u8         pad12[0xe00-0xdf0];       /* 0xdf0 */
+
+        /* 0xe00 is used as indicator for dump tools */
+        /* whether the kernel died with panic() or not */
+        __u32        panic_magic;              /* 0xe00 */
+
+        __u8         pad13[0x11b8-0xe04];      /* 0xe04 */
+
+        /* 64 bit extparam used for pfault, diag 250 etc  */
+        __u64        ext_params2;               /* 0x11B8 */
+
+        __u8         pad14[0x1200-0x11C0];      /* 0x11C0 */
+
+        /* System info area */ 
+
+        __u64        floating_pt_save_area[16]; /* 0x1200 */
+        __u64        gpregs_save_area[16];      /* 0x1280 */
+        __u32        st_status_fixed_logout[4]; /* 0x1300 */
+        __u8         pad15[0x1318-0x1310];      /* 0x1310 */
+        __u32        prefixreg_save_area;       /* 0x1318 */
+        __u32        fpt_creg_save_area;        /* 0x131c */
+        __u8         pad16[0x1324-0x1320];      /* 0x1320 */
+        __u32        tod_progreg_save_area;     /* 0x1324 */
+        __u32        cpu_timer_save_area[2];    /* 0x1328 */
+        __u32        clock_comp_save_area[2];   /* 0x1330 */
+        __u8         pad17[0x1340-0x1338];      /* 0x1338 */
+        __u32        access_regs_save_area[16]; /* 0x1340 */ 
+        __u64        cregs_save_area[16];       /* 0x1380 */
+
+        /* align to the top of the prefix area */
+
+        __u8         pad18[0x2000-0x1400];      /* 0x1400 */
+#endif /* !__s390x__ */
+} __attribute__((packed)); /* End structure*/
+
+#define S390_lowcore (*((struct _lowcore *) 0))
+extern struct _lowcore *lowcore_ptr[];
+
+static inline void set_prefix(__u32 address)
+{
+        asm volatile("spx %0" : : "m" (address) : "memory");
+}
+
+static inline __u32 store_prefix(void)
+{
+        __u32 address;
+
+        asm volatile("stpx %0" : "=m" (address));
+        return address;
+}
+
+#define __PANIC_MAGIC           0xDEADC0DE
+
+#endif
+
+#endif
diff --git a/arch/s390/include/asm/mathemu.h b/arch/s390/include/asm/mathemu.h
new file mode 100644
index 000000000000..e8dd1ba8edb0
--- /dev/null
+++ b/arch/s390/include/asm/mathemu.h
@@ -0,0 +1,29 @@
+/*
+ *  arch/s390/kernel/mathemu.h
+ *    IEEE floating point emulation.
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ */
+
+#ifndef __MATHEMU__
+#define __MATHEMU__
+
+extern int math_emu_b3(__u8 *, struct pt_regs *);
+extern int math_emu_ed(__u8 *, struct pt_regs *);
+extern int math_emu_ldr(__u8 *);
+extern int math_emu_ler(__u8 *);
+extern int math_emu_std(__u8 *, struct pt_regs *);
+extern int math_emu_ld(__u8 *, struct pt_regs *);
+extern int math_emu_ste(__u8 *, struct pt_regs *);
+extern int math_emu_le(__u8 *, struct pt_regs *);
+extern int math_emu_lfpc(__u8 *, struct pt_regs *);
+extern int math_emu_stfpc(__u8 *, struct pt_regs *);
+extern int math_emu_srnm(__u8 *, struct pt_regs *);
+
+#endif                                 /* __MATHEMU__                      */
+
+
+
+
diff --git a/arch/s390/include/asm/mman.h b/arch/s390/include/asm/mman.h
new file mode 100644
index 000000000000..7839767d837e
--- /dev/null
+++ b/arch/s390/include/asm/mman.h
@@ -0,0 +1,25 @@
+/*
+ *  include/asm-s390/mman.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/mman.h"
+ */
+
+#ifndef __S390_MMAN_H__
+#define __S390_MMAN_H__
+
+#include <asm-generic/mman.h>
+
+#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
+#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
+#define MAP_LOCKED      0x2000          /* pages are locked */
+#define MAP_NORESERVE   0x4000          /* don't check for reservations */
+#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#endif /* __S390_MMAN_H__ */
diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h
new file mode 100644
index 000000000000..5dd5e7b3476f
--- /dev/null
+++ b/arch/s390/include/asm/mmu.h
@@ -0,0 +1,13 @@
+#ifndef __MMU_H
+#define __MMU_H
+
+typedef struct {
+        struct list_head crst_list;
+        struct list_head pgtable_list;
+        unsigned long asce_bits;
+        unsigned long asce_limit;
+        int noexec;
+        int pgstes;
+} mm_context_t;
+
+#endif
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h
new file mode 100644
index 000000000000..4c2fbf48c9c4
--- /dev/null
+++ b/arch/s390/include/asm/mmu_context.h
@@ -0,0 +1,77 @@
+/*
+ *  include/asm-s390/mmu_context.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/mmu_context.h"
+ */
+
+#ifndef __S390_MMU_CONTEXT_H
+#define __S390_MMU_CONTEXT_H
+
+#include <asm/pgalloc.h>
+#include <asm/uaccess.h>
+#include <asm-generic/mm_hooks.h>
+
+static inline int init_new_context(struct task_struct *tsk,
+                                   struct mm_struct *mm)
+{
+        mm->context.asce_bits = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
+#ifdef CONFIG_64BIT
+        mm->context.asce_bits |= _ASCE_TYPE_REGION3;
+#endif
+        if (current->mm->context.pgstes) {
+                mm->context.noexec = 0;
+                mm->context.pgstes = 1;
+        } else {
+                mm->context.noexec = s390_noexec;
+                mm->context.pgstes = 0;
+        }
+        mm->context.asce_limit = STACK_TOP_MAX;
+        crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
+        return 0;
+}
+
+#define destroy_context(mm)             do { } while (0)
+
+#ifndef __s390x__
+#define LCTL_OPCODE "lctl"
+#else
+#define LCTL_OPCODE "lctlg"
+#endif
+
+static inline void update_mm(struct mm_struct *mm, struct task_struct *tsk)
+{
+        pgd_t *pgd = mm->pgd;
+
+        S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
+        if (switch_amode) {
+                /* Load primary space page table origin. */
+                pgd = mm->context.noexec ? get_shadow_table(pgd) : pgd;
+                S390_lowcore.user_exec_asce = mm->context.asce_bits | __pa(pgd);
+                asm volatile(LCTL_OPCODE" 1,1,%0\n"
+                             : : "m" (S390_lowcore.user_exec_asce) );
+        } else
+                /* Load home space page table origin. */
+                asm volatile(LCTL_OPCODE" 13,13,%0"
+                             : : "m" (S390_lowcore.user_asce) );
+        set_fs(current->thread.mm_segment);
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        cpu_set(smp_processor_id(), next->cpu_vm_mask);
+        update_mm(next, tsk);
+}
+
+#define enter_lazy_tlb(mm,tsk)  do { } while (0)
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+static inline void activate_mm(struct mm_struct *prev,
+                               struct mm_struct *next)
+{
+        switch_mm(prev, next, current);
+}
+
+#endif /* __S390_MMU_CONTEXT_H */
diff --git a/arch/s390/include/asm/module.h b/arch/s390/include/asm/module.h
new file mode 100644
index 000000000000..1cc1c5af705a
--- /dev/null
+++ b/arch/s390/include/asm/module.h
@@ -0,0 +1,46 @@
+#ifndef _ASM_S390_MODULE_H
+#define _ASM_S390_MODULE_H
+/*
+ * This file contains the s390 architecture specific module code.
+ */
+
+struct mod_arch_syminfo
+{
+        unsigned long got_offset;
+        unsigned long plt_offset;
+        int got_initialized;
+        int plt_initialized;
+};
+
+struct mod_arch_specific
+{
+        /* Starting offset of got in the module core memory. */
+        unsigned long got_offset;
+        /* Starting offset of plt in the module core memory. */
+        unsigned long plt_offset;
+        /* Size of the got. */
+        unsigned long got_size;
+        /* Size of the plt. */
+        unsigned long plt_size;
+        /* Number of symbols in syminfo. */
+        int nsyms;
+        /* Additional symbol information (got and plt offsets). */
+        struct mod_arch_syminfo *syminfo;
+};
+
+#ifdef __s390x__
+#define ElfW(x) Elf64_ ## x
+#define ELFW(x) ELF64_ ## x
+#else
+#define ElfW(x) Elf32_ ## x
+#define ELFW(x) ELF32_ ## x
+#endif
+
+#define Elf_Addr ElfW(Addr)
+#define Elf_Rela ElfW(Rela)
+#define Elf_Shdr ElfW(Shdr)
+#define Elf_Sym ElfW(Sym)
+#define Elf_Ehdr ElfW(Ehdr)
+#define ELF_R_SYM ELFW(R_SYM)
+#define ELF_R_TYPE ELFW(R_TYPE)
+#endif /* _ASM_S390_MODULE_H */
diff --git a/arch/s390/include/asm/monwriter.h b/arch/s390/include/asm/monwriter.h
new file mode 100644
index 000000000000..f0cbf96c52e6
--- /dev/null
+++ b/arch/s390/include/asm/monwriter.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-s390/monwriter.h
+ *
+ * Copyright (C) IBM Corp. 2006
+ * Character device driver for writing z/VM APPLDATA monitor records
+ * Version 1.0
+ * Author(s): Melissa Howland <melissah@us.ibm.com>
+ *
+ */
+
+#ifndef _ASM_390_MONWRITER_H
+#define _ASM_390_MONWRITER_H
+
+/* mon_function values */
+#define MONWRITE_START_INTERVAL 0x00 /* start interval recording */
+#define MONWRITE_STOP_INTERVAL  0x01 /* stop interval or config recording */
+#define MONWRITE_GEN_EVENT      0x02 /* generate event record */
+#define MONWRITE_START_CONFIG   0x03 /* start configuration recording */
+
+/* the header the app uses in its write() data */
+struct monwrite_hdr {
+        unsigned char mon_function;
+        unsigned short applid;
+        unsigned char record_num;
+        unsigned short version;
+        unsigned short release;
+        unsigned short mod_level;
+        unsigned short datalen;
+        unsigned char hdrlen;
+
+} __attribute__((packed));
+
+#endif /* _ASM_390_MONWRITER_H */
diff --git a/arch/s390/include/asm/msgbuf.h b/arch/s390/include/asm/msgbuf.h
new file mode 100644
index 000000000000..1bbdee927924
--- /dev/null
+++ b/arch/s390/include/asm/msgbuf.h
@@ -0,0 +1,37 @@
+#ifndef _S390_MSGBUF_H
+#define _S390_MSGBUF_H
+
+/* 
+ * The msqid64_ds structure for S/390 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+#ifndef __s390x__
+        unsigned long   __unused1;
+#endif /* ! __s390x__ */
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+#ifndef __s390x__
+        unsigned long   __unused2;
+#endif /* ! __s390x__ */
+        __kernel_time_t msg_ctime;      /* last change time */
+#ifndef __s390x__
+        unsigned long   __unused3;
+#endif /* ! __s390x__ */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* _S390_MSGBUF_H */
diff --git a/arch/s390/include/asm/mutex.h b/arch/s390/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/s390/include/asm/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
new file mode 100644
index 000000000000..991ba939408c
--- /dev/null
+++ b/arch/s390/include/asm/page.h
@@ -0,0 +1,155 @@
+/*
+ *  include/asm-s390/page.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Hartmut Penner (hp@de.ibm.com)
+ */
+
+#ifndef _S390_PAGE_H
+#define _S390_PAGE_H
+
+#include <linux/const.h>
+#include <asm/types.h>
+
+/* PAGE_SHIFT determines the page size */
+#define PAGE_SHIFT      12
+#define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
+#define PAGE_MASK       (~(PAGE_SIZE-1))
+#define PAGE_DEFAULT_ACC        0
+#define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)
+
+#define HPAGE_SHIFT     20
+#define HPAGE_SIZE      (1UL << HPAGE_SHIFT)
+#define HPAGE_MASK      (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+
+#define ARCH_HAS_SETCLEAR_HUGE_PTE
+#define ARCH_HAS_HUGE_PTE_TYPE
+#define ARCH_HAS_PREPARE_HUGEPAGE
+#define ARCH_HAS_HUGEPAGE_CLEAR_FLUSH
+
+#include <asm/setup.h>
+#ifndef __ASSEMBLY__
+
+static inline void clear_page(void *page)
+{
+        if (MACHINE_HAS_PFMF) {
+                asm volatile(
+                        "       .insn   rre,0xb9af0000,%0,%1"
+                        : : "d" (0x10000), "a" (page) : "memory", "cc");
+        } else {
+                register unsigned long reg1 asm ("1") = 0;
+                register void *reg2 asm ("2") = page;
+                register unsigned long reg3 asm ("3") = 4096;
+                asm volatile(
+                        "       mvcl    2,0"
+                        : "+d" (reg2), "+d" (reg3) : "d" (reg1)
+                        : "memory", "cc");
+        }
+}
+
+static inline void copy_page(void *to, void *from)
+{
+        if (MACHINE_HAS_MVPG) {
+                register unsigned long reg0 asm ("0") = 0;
+                asm volatile(
+                        "       mvpg    %0,%1"
+                        : : "a" (to), "a" (from), "d" (reg0)
+                        : "memory", "cc");
+        } else
+                asm volatile(
+                        "       mvc     0(256,%0),0(%1)\n"
+                        "       mvc     256(256,%0),256(%1)\n"
+                        "       mvc     512(256,%0),512(%1)\n"
+                        "       mvc     768(256,%0),768(%1)\n"
+                        "       mvc     1024(256,%0),1024(%1)\n"
+                        "       mvc     1280(256,%0),1280(%1)\n"
+                        "       mvc     1536(256,%0),1536(%1)\n"
+                        "       mvc     1792(256,%0),1792(%1)\n"
+                        "       mvc     2048(256,%0),2048(%1)\n"
+                        "       mvc     2304(256,%0),2304(%1)\n"
+                        "       mvc     2560(256,%0),2560(%1)\n"
+                        "       mvc     2816(256,%0),2816(%1)\n"
+                        "       mvc     3072(256,%0),3072(%1)\n"
+                        "       mvc     3328(256,%0),3328(%1)\n"
+                        "       mvc     3584(256,%0),3584(%1)\n"
+                        "       mvc     3840(256,%0),3840(%1)\n"
+                        : : "a" (to), "a" (from) : "memory");
+}
+
+#define clear_user_page(page, vaddr, pg)        clear_page(page)
+#define copy_user_page(to, from, vaddr, pg)     copy_page(to, from)
+
+#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
+        alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
+#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
+
+/*
+ * These are used to make use of C type-checking..
+ */
+
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long pmd; } pmd_t;
+typedef struct { unsigned long pud; } pud_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef pte_t *pgtable_t;
+
+#define pgprot_val(x)   ((x).pgprot)
+#define pte_val(x)      ((x).pte)
+#define pmd_val(x)      ((x).pmd)
+#define pud_val(x)      ((x).pud)
+#define pgd_val(x)      ((x).pgd)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+/* default storage key used for all pages */
+extern unsigned int default_storage_key;
+
+static inline void
+page_set_storage_key(unsigned long addr, unsigned int skey)
+{
+        asm volatile("sske %0,%1" : : "d" (skey), "a" (addr));
+}
+
+static inline unsigned int
+page_get_storage_key(unsigned long addr)
+{
+        unsigned int skey;
+
+        asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr), "0" (0));
+        return skey;
+}
+
+#ifdef CONFIG_PAGE_STATES
+
+struct page;
+void arch_free_page(struct page *page, int order);
+void arch_alloc_page(struct page *page, int order);
+
+#define HAVE_ARCH_FREE_PAGE
+#define HAVE_ARCH_ALLOC_PAGE
+
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#define __PAGE_OFFSET           0x0UL
+#define PAGE_OFFSET             0x0UL
+#define __pa(x)                 (unsigned long)(x)
+#define __va(x)                 (void *)(unsigned long)(x)
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/page.h>
+
+#endif /* _S390_PAGE_H */
diff --git a/arch/s390/include/asm/param.h b/arch/s390/include/asm/param.h
new file mode 100644
index 000000000000..34aaa4603347
--- /dev/null
+++ b/arch/s390/include/asm/param.h
@@ -0,0 +1,30 @@
+/*
+ *  include/asm-s390/param.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/param.h"
+ */
+
+#ifndef _ASMS390_PARAM_H
+#define _ASMS390_PARAM_H
+
+#ifdef __KERNEL__
+# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
+# define USER_HZ        100             /* .. some user interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   4096
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif
diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h
new file mode 100644
index 000000000000..42a145c9ddd6
--- /dev/null
+++ b/arch/s390/include/asm/pci.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_S390_PCI_H
+#define __ASM_S390_PCI_H
+
+/* S/390 systems don't have a PCI bus. This file is just here because some stupid .c code
+ * includes it even if CONFIG_PCI is not set.
+ */
+#define PCI_DMA_BUS_IS_PHYS (0)
+
+#endif /* __ASM_S390_PCI_H */
+
diff --git a/arch/s390/include/asm/percpu.h b/arch/s390/include/asm/percpu.h
new file mode 100644
index 000000000000..408d60b4f75b
--- /dev/null
+++ b/arch/s390/include/asm/percpu.h
@@ -0,0 +1,37 @@
+#ifndef __ARCH_S390_PERCPU__
+#define __ARCH_S390_PERCPU__
+
+#include <linux/compiler.h>
+#include <asm/lowcore.h>
+
+/*
+ * s390 uses its own implementation for per cpu data, the offset of
+ * the cpu local data area is cached in the cpu's lowcore memory.
+ * For 64 bit module code s390 forces the use of a GOT slot for the
+ * address of the per cpu variable. This is needed because the module
+ * may be more than 4G above the per cpu area.
+ */
+#if defined(__s390x__) && defined(MODULE)
+
+#define SHIFT_PERCPU_PTR(ptr,offset) (({                        \
+        extern int simple_identifier_##var(void);       \
+        unsigned long *__ptr;                           \
+        asm ( "larl %0, %1@GOTENT"              \
+            : "=a" (__ptr) : "X" (ptr) );               \
+        (typeof(ptr))((*__ptr) + (offset));     }))
+
+#else
+
+#define SHIFT_PERCPU_PTR(ptr, offset) (({                               \
+        extern int simple_identifier_##var(void);               \
+        unsigned long __ptr;                                    \
+        asm ( "" : "=a" (__ptr) : "0" (ptr) );                  \
+        (typeof(ptr)) (__ptr + (offset)); }))
+
+#endif
+
+#define __my_cpu_offset S390_lowcore.percpu_offset
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_S390_PERCPU__ */
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
new file mode 100644
index 000000000000..f5b2bf3d7c1d
--- /dev/null
+++ b/arch/s390/include/asm/pgalloc.h
@@ -0,0 +1,174 @@
+/*
+ *  include/asm-s390/pgalloc.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Hartmut Penner (hp@de.ibm.com)
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/pgalloc.h"
+ *    Copyright (C) 1994  Linus Torvalds
+ */
+
+#ifndef _S390_PGALLOC_H
+#define _S390_PGALLOC_H
+
+#include <linux/threads.h>
+#include <linux/gfp.h>
+#include <linux/mm.h>
+
+#define check_pgt_cache()       do {} while (0)
+
+unsigned long *crst_table_alloc(struct mm_struct *, int);
+void crst_table_free(struct mm_struct *, unsigned long *);
+
+unsigned long *page_table_alloc(struct mm_struct *);
+void page_table_free(struct mm_struct *, unsigned long *);
+void disable_noexec(struct mm_struct *, struct task_struct *);
+
+static inline void clear_table(unsigned long *s, unsigned long val, size_t n)
+{
+        *s = val;
+        n = (n / 256) - 1;
+        asm volatile(
+#ifdef CONFIG_64BIT
+                "       mvc     8(248,%0),0(%0)\n"
+#else
+                "       mvc     4(252,%0),0(%0)\n"
+#endif
+                "0:     mvc     256(256,%0),0(%0)\n"
+                "       la      %0,256(%0)\n"
+                "       brct    %1,0b\n"
+                : "+a" (s), "+d" (n));
+}
+
+static inline void crst_table_init(unsigned long *crst, unsigned long entry)
+{
+        clear_table(crst, entry, sizeof(unsigned long)*2048);
+        crst = get_shadow_table(crst);
+        if (crst)
+                clear_table(crst, entry, sizeof(unsigned long)*2048);
+}
+
+#ifndef __s390x__
+
+static inline unsigned long pgd_entry_type(struct mm_struct *mm)
+{
+        return _SEGMENT_ENTRY_EMPTY;
+}
+
+#define pud_alloc_one(mm,address)               ({ BUG(); ((pud_t *)2); })
+#define pud_free(mm, x)                         do { } while (0)
+
+#define pmd_alloc_one(mm,address)               ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(mm, x)                         do { } while (0)
+
+#define pgd_populate(mm, pgd, pud)              BUG()
+#define pgd_populate_kernel(mm, pgd, pud)       BUG()
+
+#define pud_populate(mm, pud, pmd)              BUG()
+#define pud_populate_kernel(mm, pud, pmd)       BUG()
+
+#else /* __s390x__ */
+
+static inline unsigned long pgd_entry_type(struct mm_struct *mm)
+{
+        if (mm->context.asce_limit <= (1UL << 31))
+                return _SEGMENT_ENTRY_EMPTY;
+        if (mm->context.asce_limit <= (1UL << 42))
+                return _REGION3_ENTRY_EMPTY;
+        return _REGION2_ENTRY_EMPTY;
+}
+
+int crst_table_upgrade(struct mm_struct *, unsigned long limit);
+void crst_table_downgrade(struct mm_struct *, unsigned long limit);
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+        unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
+        if (table)
+                crst_table_init(table, _REGION3_ENTRY_EMPTY);
+        return (pud_t *) table;
+}
+#define pud_free(mm, pud) crst_table_free(mm, (unsigned long *) pud)
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long vmaddr)
+{
+        unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
+        if (table)
+                crst_table_init(table, _SEGMENT_ENTRY_EMPTY);
+        return (pmd_t *) table;
+}
+#define pmd_free(mm, pmd) crst_table_free(mm, (unsigned long *) pmd)
+
+static inline void pgd_populate_kernel(struct mm_struct *mm,
+                                       pgd_t *pgd, pud_t *pud)
+{
+        pgd_val(*pgd) = _REGION2_ENTRY | __pa(pud);
+}
+
+static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
+{
+        pgd_populate_kernel(mm, pgd, pud);
+        if (mm->context.noexec) {
+                pgd = get_shadow_table(pgd);
+                pud = get_shadow_table(pud);
+                pgd_populate_kernel(mm, pgd, pud);
+        }
+}
+
+static inline void pud_populate_kernel(struct mm_struct *mm,
+                                       pud_t *pud, pmd_t *pmd)
+{
+        pud_val(*pud) = _REGION3_ENTRY | __pa(pmd);
+}
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        pud_populate_kernel(mm, pud, pmd);
+        if (mm->context.noexec) {
+                pud = get_shadow_table(pud);
+                pmd = get_shadow_table(pmd);
+                pud_populate_kernel(mm, pud, pmd);
+        }
+}
+
+#endif /* __s390x__ */
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        INIT_LIST_HEAD(&mm->context.crst_list);
+        INIT_LIST_HEAD(&mm->context.pgtable_list);
+        return (pgd_t *) crst_table_alloc(mm, s390_noexec);
+}
+#define pgd_free(mm, pgd) crst_table_free(mm, (unsigned long *) pgd)
+
+static inline void pmd_populate_kernel(struct mm_struct *mm,
+                                       pmd_t *pmd, pte_t *pte)
+{
+        pmd_val(*pmd) = _SEGMENT_ENTRY + __pa(pte);
+}
+
+static inline void pmd_populate(struct mm_struct *mm,
+                                pmd_t *pmd, pgtable_t pte)
+{
+        pmd_populate_kernel(mm, pmd, pte);
+        if (mm->context.noexec) {
+                pmd = get_shadow_table(pmd);
+                pmd_populate_kernel(mm, pmd, pte + PTRS_PER_PTE);
+        }
+}
+
+#define pmd_pgtable(pmd) \
+        (pgtable_t)(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)
+
+/*
+ * page table entry allocation/free routines.
+ */
+#define pte_alloc_one_kernel(mm, vmaddr) ((pte_t *) page_table_alloc(mm))
+#define pte_alloc_one(mm, vmaddr) ((pte_t *) page_table_alloc(mm))
+
+#define pte_free_kernel(mm, pte) page_table_free(mm, (unsigned long *) pte)
+#define pte_free(mm, pte) page_table_free(mm, (unsigned long *) pte)
+
+#endif /* _S390_PGALLOC_H */
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
new file mode 100644
index 000000000000..0bdb704ae051
--- /dev/null
+++ b/arch/s390/include/asm/pgtable.h
@@ -0,0 +1,1093 @@
+/*
+ *  include/asm-s390/pgtable.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Hartmut Penner (hp@de.ibm.com)
+ *               Ulrich Weigand (weigand@de.ibm.com)
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/pgtable.h"
+ */
+
+#ifndef _ASM_S390_PGTABLE_H
+#define _ASM_S390_PGTABLE_H
+
+/*
+ * The Linux memory management assumes a three-level page table setup. For
+ * s390 31 bit we "fold" the mid level into the top-level page table, so
+ * that we physically have the same two-level page table as the s390 mmu
+ * expects in 31 bit mode. For s390 64 bit we use three of the five levels
+ * the hardware provides (region first and region second tables are not
+ * used).
+ *
+ * The "pgd_xxx()" functions are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ *
+ * This file contains the functions and defines necessary to modify and use
+ * the S390 page table tree.
+ */
+#ifndef __ASSEMBLY__
+#include <linux/sched.h>
+#include <linux/mm_types.h>
+#include <asm/bitops.h>
+#include <asm/bug.h>
+#include <asm/processor.h>
+
+extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
+extern void paging_init(void);
+extern void vmem_map_init(void);
+
+/*
+ * The S390 doesn't have any external MMU info: the kernel page
+ * tables contain all the necessary information.
+ */
+#define update_mmu_cache(vma, address, pte)     do { } while (0)
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern char empty_zero_page[PAGE_SIZE];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * PMD_SHIFT determines the size of the area a second-level page
+ * table can map
+ * PGDIR_SHIFT determines what a third-level page table entry can map
+ */
+#ifndef __s390x__
+# define PMD_SHIFT      20
+# define PUD_SHIFT      20
+# define PGDIR_SHIFT    20
+#else /* __s390x__ */
+# define PMD_SHIFT      20
+# define PUD_SHIFT      31
+# define PGDIR_SHIFT    42
+#endif /* __s390x__ */
+
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+#define PUD_SIZE        (1UL << PUD_SHIFT)
+#define PUD_MASK        (~(PUD_SIZE-1))
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * entries per page directory level: the S390 is two-level, so
+ * we don't really have any PMD directory physically.
+ * for S390 segment-table entries are combined to one PGD
+ * that leads to 1024 pte per pgd
+ */
+#define PTRS_PER_PTE    256
+#ifndef __s390x__
+#define PTRS_PER_PMD    1
+#define PTRS_PER_PUD    1
+#else /* __s390x__ */
+#define PTRS_PER_PMD    2048
+#define PTRS_PER_PUD    2048
+#endif /* __s390x__ */
+#define PTRS_PER_PGD    2048
+
+#define FIRST_USER_ADDRESS  0
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
+#define pud_ERROR(e) \
+        printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
+
+#ifndef __ASSEMBLY__
+/*
+ * The vmalloc area will always be on the topmost area of the kernel
+ * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc,
+ * which should be enough for any sane case.
+ * By putting vmalloc at the top, we maximise the gap between physical
+ * memory and vmalloc to catch misplaced memory accesses. As a side
+ * effect, this also makes sure that 64 bit module code cannot be used
+ * as system call address.
+ */
+#ifndef __s390x__
+#define VMALLOC_START   0x78000000UL
+#define VMALLOC_END     0x7e000000UL
+#define VMEM_MAP_END    0x80000000UL
+#else /* __s390x__ */
+#define VMALLOC_START   0x3e000000000UL
+#define VMALLOC_END     0x3e040000000UL
+#define VMEM_MAP_END    0x40000000000UL
+#endif /* __s390x__ */
+
+/*
+ * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1
+ * mapping. This needs to be calculated at compile time since the size of the
+ * VMEM_MAP is static but the size of struct page can change.
+ */
+#define VMEM_MAX_PAGES  ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page))
+#define VMEM_MAX_PFN    min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES)
+#define VMEM_MAX_PHYS   ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1))
+#define vmemmap         ((struct page *) VMALLOC_END)
+
+/*
+ * A 31 bit pagetable entry of S390 has following format:
+ *  |   PFRA          |    |  OS  |
+ * 0                   0IP0
+ * 00000000001111111111222222222233
+ * 01234567890123456789012345678901
+ *
+ * I Page-Invalid Bit:    Page is not available for address-translation
+ * P Page-Protection Bit: Store access not possible for page
+ *
+ * A 31 bit segmenttable entry of S390 has following format:
+ *  |   P-table origin      |  |PTL
+ * 0                         IC
+ * 00000000001111111111222222222233
+ * 01234567890123456789012345678901
+ *
+ * I Segment-Invalid Bit:    Segment is not available for address-translation
+ * C Common-Segment Bit:     Segment is not private (PoP 3-30)
+ * PTL Page-Table-Length:    Page-table length (PTL+1*16 entries -> up to 256)
+ *
+ * The 31 bit segmenttable origin of S390 has following format:
+ *
+ *  |S-table origin   |     | STL |
+ * X                   **GPS
+ * 00000000001111111111222222222233
+ * 01234567890123456789012345678901
+ *
+ * X Space-Switch event:
+ * G Segment-Invalid Bit:     *
+ * P Private-Space Bit:       Segment is not private (PoP 3-30)
+ * S Storage-Alteration:
+ * STL Segment-Table-Length:  Segment-table length (STL+1*16 entries -> up to 2048)
+ *
+ * A 64 bit pagetable entry of S390 has following format:
+ * |                     PFRA                         |0IP0|  OS  |
+ * 0000000000111111111122222222223333333333444444444455555555556666
+ * 0123456789012345678901234567890123456789012345678901234567890123
+ *
+ * I Page-Invalid Bit:    Page is not available for address-translation
+ * P Page-Protection Bit: Store access not possible for page
+ *
+ * A 64 bit segmenttable entry of S390 has following format:
+ * |        P-table origin                              |      TT
+ * 0000000000111111111122222222223333333333444444444455555555556666
+ * 0123456789012345678901234567890123456789012345678901234567890123
+ *
+ * I Segment-Invalid Bit:    Segment is not available for address-translation
+ * C Common-Segment Bit:     Segment is not private (PoP 3-30)
+ * P Page-Protection Bit: Store access not possible for page
+ * TT Type 00
+ *
+ * A 64 bit region table entry of S390 has following format:
+ * |        S-table origin                             |   TF  TTTL
+ * 0000000000111111111122222222223333333333444444444455555555556666
+ * 0123456789012345678901234567890123456789012345678901234567890123
+ *
+ * I Segment-Invalid Bit:    Segment is not available for address-translation
+ * TT Type 01
+ * TF
+ * TL Table length
+ *
+ * The 64 bit regiontable origin of S390 has following format:
+ * |      region table origon                          |       DTTL
+ * 0000000000111111111122222222223333333333444444444455555555556666
+ * 0123456789012345678901234567890123456789012345678901234567890123
+ *
+ * X Space-Switch event:
+ * G Segment-Invalid Bit:  
+ * P Private-Space Bit:    
+ * S Storage-Alteration:
+ * R Real space
+ * TL Table-Length:
+ *
+ * A storage key has the following format:
+ * | ACC |F|R|C|0|
+ *  0   3 4 5 6 7
+ * ACC: access key
+ * F  : fetch protection bit
+ * R  : referenced bit
+ * C  : changed bit
+ */
+
+/* Hardware bits in the page table entry */
+#define _PAGE_RO        0x200           /* HW read-only bit  */
+#define _PAGE_INVALID   0x400           /* HW invalid bit    */
+
+/* Software bits in the page table entry */
+#define _PAGE_SWT       0x001           /* SW pte type bit t */
+#define _PAGE_SWX       0x002           /* SW pte type bit x */
+#define _PAGE_SPECIAL   0x004           /* SW associated with special page */
+#define __HAVE_ARCH_PTE_SPECIAL
+
+/* Set of bits not changed in pte_modify */
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_SPECIAL)
+
+/* Six different types of pages. */
+#define _PAGE_TYPE_EMPTY        0x400
+#define _PAGE_TYPE_NONE         0x401
+#define _PAGE_TYPE_SWAP         0x403
+#define _PAGE_TYPE_FILE         0x601   /* bit 0x002 is used for offset !! */
+#define _PAGE_TYPE_RO           0x200
+#define _PAGE_TYPE_RW           0x000
+#define _PAGE_TYPE_EX_RO        0x202
+#define _PAGE_TYPE_EX_RW        0x002
+
+/*
+ * Only four types for huge pages, using the invalid bit and protection bit
+ * of a segment table entry.
+ */
+#define _HPAGE_TYPE_EMPTY       0x020   /* _SEGMENT_ENTRY_INV */
+#define _HPAGE_TYPE_NONE        0x220
+#define _HPAGE_TYPE_RO          0x200   /* _SEGMENT_ENTRY_RO  */
+#define _HPAGE_TYPE_RW          0x000
+
+/*
+ * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
+ * pte_none and pte_file to find out the pte type WITHOUT holding the page
+ * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
+ * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
+ * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
+ * This change is done while holding the lock, but the intermediate step
+ * of a previously valid pte with the hw invalid bit set can be observed by
+ * handle_pte_fault. That makes it necessary that all valid pte types with
+ * the hw invalid bit set must be distinguishable from the four pte types
+ * empty, none, swap and file.
+ *
+ *                      irxt  ipte  irxt
+ * _PAGE_TYPE_EMPTY     1000   ->   1000
+ * _PAGE_TYPE_NONE      1001   ->   1001
+ * _PAGE_TYPE_SWAP      1011   ->   1011
+ * _PAGE_TYPE_FILE      11?1   ->   11?1
+ * _PAGE_TYPE_RO        0100   ->   1100
+ * _PAGE_TYPE_RW        0000   ->   1000
+ * _PAGE_TYPE_EX_RO     0110   ->   1110
+ * _PAGE_TYPE_EX_RW     0010   ->   1010
+ *
+ * pte_none is true for bits combinations 1000, 1010, 1100, 1110
+ * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
+ * pte_file is true for bits combinations 1101, 1111
+ * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
+ */
+
+/* Page status table bits for virtualization */
+#define RCP_PCL_BIT     55
+#define RCP_HR_BIT      54
+#define RCP_HC_BIT      53
+#define RCP_GR_BIT      50
+#define RCP_GC_BIT      49
+
+#ifndef __s390x__
+
+/* Bits in the segment table address-space-control-element */
+#define _ASCE_SPACE_SWITCH      0x80000000UL    /* space switch event       */
+#define _ASCE_ORIGIN_MASK       0x7ffff000UL    /* segment table origin     */
+#define _ASCE_PRIVATE_SPACE     0x100   /* private space control            */
+#define _ASCE_ALT_EVENT         0x80    /* storage alteration event control */
+#define _ASCE_TABLE_LENGTH      0x7f    /* 128 x 64 entries = 8k            */
+
+/* Bits in the segment table entry */
+#define _SEGMENT_ENTRY_ORIGIN   0x7fffffc0UL    /* page table origin        */
+#define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
+#define _SEGMENT_ENTRY_COMMON   0x10    /* common segment bit               */
+#define _SEGMENT_ENTRY_PTL      0x0f    /* page table length                */
+
+#define _SEGMENT_ENTRY          (_SEGMENT_ENTRY_PTL)
+#define _SEGMENT_ENTRY_EMPTY    (_SEGMENT_ENTRY_INV)
+
+#else /* __s390x__ */
+
+/* Bits in the segment/region table address-space-control-element */
+#define _ASCE_ORIGIN            ~0xfffUL/* segment table origin             */
+#define _ASCE_PRIVATE_SPACE     0x100   /* private space control            */
+#define _ASCE_ALT_EVENT         0x80    /* storage alteration event control */
+#define _ASCE_SPACE_SWITCH      0x40    /* space switch event               */
+#define _ASCE_REAL_SPACE        0x20    /* real space control               */
+#define _ASCE_TYPE_MASK         0x0c    /* asce table type mask             */
+#define _ASCE_TYPE_REGION1      0x0c    /* region first table type          */
+#define _ASCE_TYPE_REGION2      0x08    /* region second table type         */
+#define _ASCE_TYPE_REGION3      0x04    /* region third table type          */
+#define _ASCE_TYPE_SEGMENT      0x00    /* segment table type               */
+#define _ASCE_TABLE_LENGTH      0x03    /* region table length              */
+
+/* Bits in the region table entry */
+#define _REGION_ENTRY_ORIGIN    ~0xfffUL/* region/segment table origin      */
+#define _REGION_ENTRY_INV       0x20    /* invalid region table entry       */
+#define _REGION_ENTRY_TYPE_MASK 0x0c    /* region/segment table type mask   */
+#define _REGION_ENTRY_TYPE_R1   0x0c    /* region first table type          */
+#define _REGION_ENTRY_TYPE_R2   0x08    /* region second table type         */
+#define _REGION_ENTRY_TYPE_R3   0x04    /* region third table type          */
+#define _REGION_ENTRY_LENGTH    0x03    /* region third length              */
+
+#define _REGION1_ENTRY          (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
+#define _REGION1_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
+#define _REGION2_ENTRY          (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
+#define _REGION2_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
+#define _REGION3_ENTRY          (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
+#define _REGION3_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
+
+/* Bits in the segment table entry */
+#define _SEGMENT_ENTRY_ORIGIN   ~0x7ffUL/* segment table origin             */
+#define _SEGMENT_ENTRY_RO       0x200   /* page protection bit              */
+#define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
+
+#define _SEGMENT_ENTRY          (0)
+#define _SEGMENT_ENTRY_EMPTY    (_SEGMENT_ENTRY_INV)
+
+#define _SEGMENT_ENTRY_LARGE    0x400   /* STE-format control, large page   */
+#define _SEGMENT_ENTRY_CO       0x100   /* change-recording override   */
+
+#endif /* __s390x__ */
+
+/*
+ * A user page table pointer has the space-switch-event bit, the
+ * private-space-control bit and the storage-alteration-event-control
+ * bit set. A kernel page table pointer doesn't need them.
+ */
+#define _ASCE_USER_BITS         (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
+                                 _ASCE_ALT_EVENT)
+
+/* Bits int the storage key */
+#define _PAGE_CHANGED    0x02          /* HW changed bit                   */
+#define _PAGE_REFERENCED 0x04          /* HW referenced bit                */
+
+/*
+ * Page protection definitions.
+ */
+#define PAGE_NONE       __pgprot(_PAGE_TYPE_NONE)
+#define PAGE_RO         __pgprot(_PAGE_TYPE_RO)
+#define PAGE_RW         __pgprot(_PAGE_TYPE_RW)
+#define PAGE_EX_RO      __pgprot(_PAGE_TYPE_EX_RO)
+#define PAGE_EX_RW      __pgprot(_PAGE_TYPE_EX_RW)
+
+#define PAGE_KERNEL     PAGE_RW
+#define PAGE_COPY       PAGE_RO
+
+/*
+ * Dependent on the EXEC_PROTECT option s390 can do execute protection.
+ * Write permission always implies read permission. In theory with a
+ * primary/secondary page table execute only can be implemented but
+ * it would cost an additional bit in the pte to distinguish all the
+ * different pte types. To avoid that execute permission currently
+ * implies read permission as well.
+ */
+         /*xwr*/
+#define __P000  PAGE_NONE
+#define __P001  PAGE_RO
+#define __P010  PAGE_RO
+#define __P011  PAGE_RO
+#define __P100  PAGE_EX_RO
+#define __P101  PAGE_EX_RO
+#define __P110  PAGE_EX_RO
+#define __P111  PAGE_EX_RO
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_RO
+#define __S010  PAGE_RW
+#define __S011  PAGE_RW
+#define __S100  PAGE_EX_RO
+#define __S101  PAGE_EX_RO
+#define __S110  PAGE_EX_RW
+#define __S111  PAGE_EX_RW
+
+#ifndef __s390x__
+# define PxD_SHADOW_SHIFT       1
+#else /* __s390x__ */
+# define PxD_SHADOW_SHIFT       2
+#endif /* __s390x__ */
+
+static inline void *get_shadow_table(void *table)
+{
+        unsigned long addr, offset;
+        struct page *page;
+
+        addr = (unsigned long) table;
+        offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1);
+        page = virt_to_page((void *)(addr ^ offset));
+        return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL);
+}
+
+/*
+ * Certain architectures need to do special things when PTEs
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t entry)
+{
+        *ptep = entry;
+        if (mm->context.noexec) {
+                if (!(pte_val(entry) & _PAGE_INVALID) &&
+                    (pte_val(entry) & _PAGE_SWX))
+                        pte_val(entry) |= _PAGE_RO;
+                else
+                        pte_val(entry) = _PAGE_TYPE_EMPTY;
+                ptep[PTRS_PER_PTE] = entry;
+        }
+}
+
+/*
+ * pgd/pmd/pte query functions
+ */
+#ifndef __s390x__
+
+static inline int pgd_present(pgd_t pgd) { return 1; }
+static inline int pgd_none(pgd_t pgd)    { return 0; }
+static inline int pgd_bad(pgd_t pgd)     { return 0; }
+
+static inline int pud_present(pud_t pud) { return 1; }
+static inline int pud_none(pud_t pud)    { return 0; }
+static inline int pud_bad(pud_t pud)     { return 0; }
+
+#else /* __s390x__ */
+
+static inline int pgd_present(pgd_t pgd)
+{
+        if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
+                return 1;
+        return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
+}
+
+static inline int pgd_none(pgd_t pgd)
+{
+        if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
+                return 0;
+        return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
+}
+
+static inline int pgd_bad(pgd_t pgd)
+{
+        /*
+         * With dynamic page table levels the pgd can be a region table
+         * entry or a segment table entry. Check for the bit that are
+         * invalid for either table entry.
+         */
+        unsigned long mask =
+                ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
+                ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
+        return (pgd_val(pgd) & mask) != 0;
+}
+
+static inline int pud_present(pud_t pud)
+{
+        if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
+                return 1;
+        return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
+}
+
+static inline int pud_none(pud_t pud)
+{
+        if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
+                return 0;
+        return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
+}
+
+static inline int pud_bad(pud_t pud)
+{
+        /*
+         * With dynamic page table levels the pud can be a region table
+         * entry or a segment table entry. Check for the bit that are
+         * invalid for either table entry.
+         */
+        unsigned long mask =
+                ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
+                ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
+        return (pud_val(pud) & mask) != 0;
+}
+
+#endif /* __s390x__ */
+
+static inline int pmd_present(pmd_t pmd)
+{
+        return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
+}
+
+static inline int pmd_none(pmd_t pmd)
+{
+        return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
+}
+
+static inline int pmd_bad(pmd_t pmd)
+{
+        unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
+        return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
+}
+
+static inline int pte_none(pte_t pte)
+{
+        return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
+}
+
+static inline int pte_present(pte_t pte)
+{
+        unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
+        return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
+                (!(pte_val(pte) & _PAGE_INVALID) &&
+                 !(pte_val(pte) & _PAGE_SWT));
+}
+
+static inline int pte_file(pte_t pte)
+{
+        unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
+        return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
+}
+
+static inline int pte_special(pte_t pte)
+{
+        return (pte_val(pte) & _PAGE_SPECIAL);
+}
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(a,b)  (pte_val(a) == pte_val(b))
+
+static inline void rcp_lock(pte_t *ptep)
+{
+#ifdef CONFIG_PGSTE
+        unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
+        preempt_disable();
+        while (test_and_set_bit(RCP_PCL_BIT, pgste))
+                ;
+#endif
+}
+
+static inline void rcp_unlock(pte_t *ptep)
+{
+#ifdef CONFIG_PGSTE
+        unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
+        clear_bit(RCP_PCL_BIT, pgste);
+        preempt_enable();
+#endif
+}
+
+/* forward declaration for SetPageUptodate in page-flags.h*/
+static inline void page_clear_dirty(struct page *page);
+#include <linux/page-flags.h>
+
+static inline void ptep_rcp_copy(pte_t *ptep)
+{
+#ifdef CONFIG_PGSTE
+        struct page *page = virt_to_page(pte_val(*ptep));
+        unsigned int skey;
+        unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
+
+        skey = page_get_storage_key(page_to_phys(page));
+        if (skey & _PAGE_CHANGED)
+                set_bit_simple(RCP_GC_BIT, pgste);
+        if (skey & _PAGE_REFERENCED)
+                set_bit_simple(RCP_GR_BIT, pgste);
+        if (test_and_clear_bit_simple(RCP_HC_BIT, pgste))
+                SetPageDirty(page);
+        if (test_and_clear_bit_simple(RCP_HR_BIT, pgste))
+                SetPageReferenced(page);
+#endif
+}
+
+/*
+ * query functions pte_write/pte_dirty/pte_young only work if
+ * pte_present() is true. Undefined behaviour if not..
+ */
+static inline int pte_write(pte_t pte)
+{
+        return (pte_val(pte) & _PAGE_RO) == 0;
+}
+
+static inline int pte_dirty(pte_t pte)
+{
+        /* A pte is neither clean nor dirty on s/390. The dirty bit
+         * is in the storage key. See page_test_and_clear_dirty for
+         * details.
+         */
+        return 0;
+}
+
+static inline int pte_young(pte_t pte)
+{
+        /* A pte is neither young nor old on s/390. The young bit
+         * is in the storage key. See page_test_and_clear_young for
+         * details.
+         */
+        return 0;
+}
+
+/*
+ * pgd/pmd/pte modification functions
+ */
+
+#ifndef __s390x__
+
+#define pgd_clear(pgd)          do { } while (0)
+#define pud_clear(pud)          do { } while (0)
+
+#else /* __s390x__ */
+
+static inline void pgd_clear_kernel(pgd_t * pgd)
+{
+        if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
+                pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
+}
+
+static inline void pgd_clear(pgd_t * pgd)
+{
+        pgd_t *shadow = get_shadow_table(pgd);
+
+        pgd_clear_kernel(pgd);
+        if (shadow)
+                pgd_clear_kernel(shadow);
+}
+
+static inline void pud_clear_kernel(pud_t *pud)
+{
+        if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
+                pud_val(*pud) = _REGION3_ENTRY_EMPTY;
+}
+
+static inline void pud_clear(pud_t *pud)
+{
+        pud_t *shadow = get_shadow_table(pud);
+
+        pud_clear_kernel(pud);
+        if (shadow)
+                pud_clear_kernel(shadow);
+}
+
+#endif /* __s390x__ */
+
+static inline void pmd_clear_kernel(pmd_t * pmdp)
+{
+        pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
+}
+
+static inline void pmd_clear(pmd_t *pmd)
+{
+        pmd_t *shadow = get_shadow_table(pmd);
+
+        pmd_clear_kernel(pmd);
+        if (shadow)
+                pmd_clear_kernel(shadow);
+}
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        if (mm->context.pgstes)
+                ptep_rcp_copy(ptep);
+        pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+        if (mm->context.noexec)
+                pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY;
+}
+
+/*
+ * The following pte modification functions only work if
+ * pte_present() is true. Undefined behaviour if not..
+ */
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte_val(pte) &= _PAGE_CHG_MASK;
+        pte_val(pte) |= pgprot_val(newprot);
+        return pte;
+}
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        /* Do not clobber _PAGE_TYPE_NONE pages!  */
+        if (!(pte_val(pte) & _PAGE_INVALID))
+                pte_val(pte) |= _PAGE_RO;
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte_val(pte) &= ~_PAGE_RO;
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        /* The only user of pte_mkclean is the fork() code.
+           We must *not* clear the *physical* page dirty bit
+           just because fork() wants to clear the dirty bit in
+           *one* of the page's mappings.  So we just do nothing. */
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        /* We do not explicitly set the dirty bit because the
+         * sske instruction is slow. It is faster to let the
+         * next instruction set the dirty bit.
+         */
+        return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        /* S/390 doesn't keep its dirty/referenced bit in the pte.
+         * There is no point in clearing the real referenced bit.
+         */
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        /* S/390 doesn't keep its dirty/referenced bit in the pte.
+         * There is no point in setting the real referenced bit.
+         */
+        return pte;
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_SPECIAL;
+        return pte;
+}
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
+                                            unsigned long addr, pte_t *ptep)
+{
+#ifdef CONFIG_PGSTE
+        unsigned long physpage;
+        int young;
+        unsigned long *pgste;
+
+        if (!vma->vm_mm->context.pgstes)
+                return 0;
+        physpage = pte_val(*ptep) & PAGE_MASK;
+        pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
+
+        young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0);
+        rcp_lock(ptep);
+        if (young)
+                set_bit_simple(RCP_GR_BIT, pgste);
+        young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste);
+        rcp_unlock(ptep);
+        return young;
+#endif
+        return 0;
+}
+
+#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
+static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
+                                         unsigned long address, pte_t *ptep)
+{
+        /* No need to flush TLB
+         * On s390 reference bits are in storage key and never in TLB
+         * With virtualization we handle the reference bit, without we
+         * we can simply return */
+#ifdef CONFIG_PGSTE
+        return ptep_test_and_clear_young(vma, address, ptep);
+#endif
+        return 0;
+}
+
+static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
+{
+        if (!(pte_val(*ptep) & _PAGE_INVALID)) {
+#ifndef __s390x__
+                /* pto must point to the start of the segment table */
+                pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
+#else
+                /* ipte in zarch mode can do the math */
+                pte_t *pto = ptep;
+#endif
+                asm volatile(
+                        "       ipte    %2,%3"
+                        : "=m" (*ptep) : "m" (*ptep),
+                          "a" (pto), "a" (address));
+        }
+}
+
+static inline void ptep_invalidate(struct mm_struct *mm,
+                                   unsigned long address, pte_t *ptep)
+{
+        if (mm->context.pgstes) {
+                rcp_lock(ptep);
+                __ptep_ipte(address, ptep);
+                ptep_rcp_copy(ptep);
+                pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+                rcp_unlock(ptep);
+                return;
+        }
+        __ptep_ipte(address, ptep);
+        pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+        if (mm->context.noexec) {
+                __ptep_ipte(address, ptep + PTRS_PER_PTE);
+                pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY;
+        }
+}
+
+/*
+ * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
+ * both clear the TLB for the unmapped pte. The reason is that
+ * ptep_get_and_clear is used in common code (e.g. change_pte_range)
+ * to modify an active pte. The sequence is
+ *   1) ptep_get_and_clear
+ *   2) set_pte_at
+ *   3) flush_tlb_range
+ * On s390 the tlb needs to get flushed with the modification of the pte
+ * if the pte is active. The only way how this can be implemented is to
+ * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
+ * is a nop.
+ */
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+#define ptep_get_and_clear(__mm, __address, __ptep)                     \
+({                                                                      \
+        pte_t __pte = *(__ptep);                                        \
+        if (atomic_read(&(__mm)->mm_users) > 1 ||                       \
+            (__mm) != current->active_mm)                               \
+                ptep_invalidate(__mm, __address, __ptep);               \
+        else                                                            \
+                pte_clear((__mm), (__address), (__ptep));               \
+        __pte;                                                          \
+})
+
+#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
+static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
+                                     unsigned long address, pte_t *ptep)
+{
+        pte_t pte = *ptep;
+        ptep_invalidate(vma->vm_mm, address, ptep);
+        return pte;
+}
+
+/*
+ * The batched pte unmap code uses ptep_get_and_clear_full to clear the
+ * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
+ * tlbs of an mm if it can guarantee that the ptes of the mm_struct
+ * cannot be accessed while the batched unmap is running. In this case
+ * full==1 and a simple pte_clear is enough. See tlb.h.
+ */
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
+static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
+                                            unsigned long addr,
+                                            pte_t *ptep, int full)
+{
+        pte_t pte = *ptep;
+
+        if (full)
+                pte_clear(mm, addr, ptep);
+        else
+                ptep_invalidate(mm, addr, ptep);
+        return pte;
+}
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+#define ptep_set_wrprotect(__mm, __addr, __ptep)                        \
+({                                                                      \
+        pte_t __pte = *(__ptep);                                        \
+        if (pte_write(__pte)) {                                         \
+                if (atomic_read(&(__mm)->mm_users) > 1 ||               \
+                    (__mm) != current->active_mm)                       \
+                        ptep_invalidate(__mm, __addr, __ptep);          \
+                set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \
+        }                                                               \
+})
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+#define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty)  \
+({                                                                      \
+        int __changed = !pte_same(*(__ptep), __entry);                  \
+        if (__changed) {                                                \
+                ptep_invalidate((__vma)->vm_mm, __addr, __ptep);        \
+                set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry);    \
+        }                                                               \
+        __changed;                                                      \
+})
+
+/*
+ * Test and clear dirty bit in storage key.
+ * We can't clear the changed bit atomically. This is a potential
+ * race against modification of the referenced bit. This function
+ * should therefore only be called if it is not mapped in any
+ * address space.
+ */
+#define __HAVE_ARCH_PAGE_TEST_DIRTY
+static inline int page_test_dirty(struct page *page)
+{
+        return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
+}
+
+#define __HAVE_ARCH_PAGE_CLEAR_DIRTY
+static inline void page_clear_dirty(struct page *page)
+{
+        page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY);
+}
+
+/*
+ * Test and clear referenced bit in storage key.
+ */
+#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
+static inline int page_test_and_clear_young(struct page *page)
+{
+        unsigned long physpage = page_to_phys(page);
+        int ccode;
+
+        asm volatile(
+                "       rrbe    0,%1\n"
+                "       ipm     %0\n"
+                "       srl     %0,28\n"
+                : "=d" (ccode) : "a" (physpage) : "cc" );
+        return ccode & 2;
+}
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
+{
+        pte_t __pte;
+        pte_val(__pte) = physpage + pgprot_val(pgprot);
+        return __pte;
+}
+
+static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
+{
+        unsigned long physpage = page_to_phys(page);
+
+        return mk_pte_phys(physpage, pgprot);
+}
+
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
+#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
+
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+#ifndef __s390x__
+
+#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
+#define pud_deref(pmd) ({ BUG(); 0UL; })
+#define pgd_deref(pmd) ({ BUG(); 0UL; })
+
+#define pud_offset(pgd, address) ((pud_t *) pgd)
+#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
+
+#else /* __s390x__ */
+
+#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
+#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
+#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
+
+static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
+{
+        pud_t *pud = (pud_t *) pgd;
+        if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
+                pud = (pud_t *) pgd_deref(*pgd);
+        return pud  + pud_index(address);
+}
+
+static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
+{
+        pmd_t *pmd = (pmd_t *) pud;
+        if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
+                pmd = (pmd_t *) pud_deref(*pud);
+        return pmd + pmd_index(address);
+}
+
+#endif /* __s390x__ */
+
+#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
+#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
+#define pte_page(x) pfn_to_page(pte_pfn(x))
+
+#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
+
+/* Find an entry in the lowest level page table.. */
+#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
+#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
+#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
+#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
+#define pte_unmap(pte) do { } while (0)
+#define pte_unmap_nested(pte) do { } while (0)
+
+/*
+ * 31 bit swap entry format:
+ * A page-table entry has some bits we have to treat in a special way.
+ * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
+ * exception will occur instead of a page translation exception. The
+ * specifiation exception has the bad habit not to store necessary
+ * information in the lowcore.
+ * Bit 21 and bit 22 are the page invalid bit and the page protection
+ * bit. We set both to indicate a swapped page.
+ * Bit 30 and 31 are used to distinguish the different page types. For
+ * a swapped page these bits need to be zero.
+ * This leaves the bits 1-19 and bits 24-29 to store type and offset.
+ * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
+ * plus 24 for the offset.
+ * 0|     offset        |0110|o|type |00|
+ * 0 0000000001111111111 2222 2 22222 33
+ * 0 1234567890123456789 0123 4 56789 01
+ *
+ * 64 bit swap entry format:
+ * A page-table entry has some bits we have to treat in a special way.
+ * Bits 52 and bit 55 have to be zero, otherwise an specification
+ * exception will occur instead of a page translation exception. The
+ * specifiation exception has the bad habit not to store necessary
+ * information in the lowcore.
+ * Bit 53 and bit 54 are the page invalid bit and the page protection
+ * bit. We set both to indicate a swapped page.
+ * Bit 62 and 63 are used to distinguish the different page types. For
+ * a swapped page these bits need to be zero.
+ * This leaves the bits 0-51 and bits 56-61 to store type and offset.
+ * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
+ * plus 56 for the offset.
+ * |                      offset                        |0110|o|type |00|
+ *  0000000000111111111122222222223333333333444444444455 5555 5 55566 66
+ *  0123456789012345678901234567890123456789012345678901 2345 6 78901 23
+ */
+#ifndef __s390x__
+#define __SWP_OFFSET_MASK (~0UL >> 12)
+#else
+#define __SWP_OFFSET_MASK (~0UL >> 11)
+#endif
+static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
+{
+        pte_t pte;
+        offset &= __SWP_OFFSET_MASK;
+        pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
+                ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
+        return pte;
+}
+
+#define __swp_type(entry)       (((entry).val >> 2) & 0x1f)
+#define __swp_offset(entry)     (((entry).val >> 11) | (((entry).val >> 7) & 1))
+#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
+
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+#ifndef __s390x__
+# define PTE_FILE_MAX_BITS      26
+#else /* __s390x__ */
+# define PTE_FILE_MAX_BITS      59
+#endif /* __s390x__ */
+
+#define pte_to_pgoff(__pte) \
+        ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
+
+#define pgoff_to_pte(__off) \
+        ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
+                   | _PAGE_TYPE_FILE })
+
+#endif /* !__ASSEMBLY__ */
+
+#define kern_addr_valid(addr)   (1)
+
+extern int vmem_add_mapping(unsigned long start, unsigned long size);
+extern int vmem_remove_mapping(unsigned long start, unsigned long size);
+extern int s390_enable_sie(void);
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+#include <asm-generic/pgtable.h>
+
+#endif /* _S390_PAGE_H */
diff --git a/arch/s390/include/asm/poll.h b/arch/s390/include/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/s390/include/asm/poll.h
@@ -0,0 +1 @@
+#include <asm-generic/poll.h>
diff --git a/arch/s390/include/asm/posix_types.h b/arch/s390/include/asm/posix_types.h
new file mode 100644
index 000000000000..397d93fba3a7
--- /dev/null
+++ b/arch/s390/include/asm/posix_types.h
@@ -0,0 +1,111 @@
+/*
+ *  include/asm-s390/posix_types.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/posix_types.h"
+ */
+
+#ifndef __ARCH_S390_POSIX_TYPES_H
+#define __ARCH_S390_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+#ifndef __s390x__
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned short  __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef unsigned short  __kernel_ipc_pid_t;
+typedef unsigned short  __kernel_uid_t;
+typedef unsigned short  __kernel_gid_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+typedef unsigned short  __kernel_old_uid_t;
+typedef unsigned short  __kernel_old_gid_t;
+typedef unsigned short  __kernel_old_dev_t;
+
+#else /* __s390x__ */
+
+typedef unsigned int    __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+typedef unsigned int    __kernel_nlink_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+typedef long            __kernel_ssize_t;
+typedef long            __kernel_ptrdiff_t;
+typedef unsigned long   __kernel_sigset_t;      /* at least 32 bits */
+typedef __kernel_uid_t __kernel_old_uid_t;
+typedef __kernel_gid_t __kernel_old_gid_t;
+typedef __kernel_uid_t __kernel_uid32_t;
+typedef __kernel_gid_t __kernel_gid32_t;
+typedef unsigned short __kernel_old_dev_t;
+
+#endif /* __s390x__ */
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+        int     val[2];
+#else                        /* !defined(__KERNEL__) && !defined(__USE_ALL)*/
+        int     __val[2];
+#endif                       /* !defined(__KERNEL__) && !defined(__USE_ALL)*/
+} __kernel_fsid_t;
+
+
+#ifdef __KERNEL__
+
+#undef __FD_SET
+static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static inline int __FD_ISSET(unsigned long fd, const __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (fdsetp->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+#undef  __FD_ZERO
+#define __FD_ZERO(fdsetp) \
+        ((void) memset ((void *) (fdsetp), 0, sizeof (__kernel_fd_set)))
+
+#endif     /* __KERNEL__ */
+
+#endif
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
new file mode 100644
index 000000000000..4af80af2a88f
--- /dev/null
+++ b/arch/s390/include/asm/processor.h
@@ -0,0 +1,360 @@
+/*
+ *  include/asm-s390/processor.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Hartmut Penner (hp@de.ibm.com),
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/processor.h"
+ *    Copyright (C) 1994, Linus Torvalds
+ */
+
+#ifndef __ASM_S390_PROCESSOR_H
+#define __ASM_S390_PROCESSOR_H
+
+#include <asm/ptrace.h>
+
+#ifdef __KERNEL__
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
+
+/*
+ *  CPU type and hardware bug flags. Kept separately for each CPU.
+ *  Members of this structure are referenced in head.S, so think twice
+ *  before touching them. [mj]
+ */
+
+typedef struct
+{
+        unsigned int version :  8;
+        unsigned int ident   : 24;
+        unsigned int machine : 16;
+        unsigned int unused  : 16;
+} __attribute__ ((packed)) cpuid_t;
+
+static inline void get_cpu_id(cpuid_t *ptr)
+{
+        asm volatile("stidp 0(%1)" : "=m" (*ptr) : "a" (ptr));
+}
+
+struct cpuinfo_S390
+{
+        cpuid_t  cpu_id;
+        __u16    cpu_addr;
+        __u16    cpu_nr;
+        unsigned long loops_per_jiffy;
+        unsigned long *pgd_quick;
+#ifdef __s390x__
+        unsigned long *pmd_quick;
+#endif /* __s390x__ */
+        unsigned long *pte_quick;
+        unsigned long pgtable_cache_sz;
+};
+
+extern void s390_adjust_jiffies(void);
+extern void print_cpu_info(struct cpuinfo_S390 *);
+extern int get_cpu_capability(unsigned int *);
+
+/*
+ * User space process size: 2GB for 31 bit, 4TB for 64 bit.
+ */
+#ifndef __s390x__
+
+#define TASK_SIZE               (1UL << 31)
+#define TASK_UNMAPPED_BASE      (1UL << 30)
+
+#else /* __s390x__ */
+
+#define TASK_SIZE_OF(tsk)       (test_tsk_thread_flag(tsk,TIF_31BIT) ? \
+                                        (1UL << 31) : (1UL << 53))
+#define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
+                                        (1UL << 30) : (1UL << 41))
+#define TASK_SIZE               TASK_SIZE_OF(current)
+
+#endif /* __s390x__ */
+
+#ifdef __KERNEL__
+
+#ifndef __s390x__
+#define STACK_TOP               (1UL << 31)
+#define STACK_TOP_MAX           (1UL << 31)
+#else /* __s390x__ */
+#define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
+#define STACK_TOP_MAX           (1UL << 42)
+#endif /* __s390x__ */
+
+
+#endif
+
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+
+typedef struct {
+        __u32 ar4;
+} mm_segment_t;
+
+/*
+ * Thread structure
+ */
+struct thread_struct {
+        s390_fp_regs fp_regs;
+        unsigned int  acrs[NUM_ACRS];
+        unsigned long ksp;              /* kernel stack pointer             */
+        mm_segment_t mm_segment;
+        unsigned long prot_addr;        /* address of protection-excep.     */
+        unsigned int trap_no;
+        per_struct per_info;
+        /* Used to give failing instruction back to user for ieee exceptions */
+        unsigned long ieee_instruction_pointer; 
+        /* pfault_wait is used to block the process on a pfault event */
+        unsigned long pfault_wait;
+};
+
+typedef struct thread_struct thread_struct;
+
+/*
+ * Stack layout of a C stack frame.
+ */
+#ifndef __PACK_STACK
+struct stack_frame {
+        unsigned long back_chain;
+        unsigned long empty1[5];
+        unsigned long gprs[10];
+        unsigned int  empty2[8];
+};
+#else
+struct stack_frame {
+        unsigned long empty1[5];
+        unsigned int  empty2[8];
+        unsigned long gprs[10];
+        unsigned long back_chain;
+};
+#endif
+
+#define ARCH_MIN_TASKALIGN      8
+
+#define INIT_THREAD {                                                   \
+        .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
+}
+
+/*
+ * Do necessary setup to start up a new thread.
+ */
+#define start_thread(regs, new_psw, new_stackp) do {            \
+        set_fs(USER_DS);                                        \
+        regs->psw.mask  = psw_user_bits;                        \
+        regs->psw.addr  = new_psw | PSW_ADDR_AMODE;             \
+        regs->gprs[15]  = new_stackp;                           \
+} while (0)
+
+#define start_thread31(regs, new_psw, new_stackp) do {          \
+        set_fs(USER_DS);                                        \
+        regs->psw.mask  = psw_user32_bits;                      \
+        regs->psw.addr  = new_psw | PSW_ADDR_AMODE;             \
+        regs->gprs[15]  = new_stackp;                           \
+        crst_table_downgrade(current->mm, 1UL << 31);           \
+} while (0)
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+struct mm_struct;
+struct seq_file;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+extern unsigned long thread_saved_pc(struct task_struct *t);
+
+/*
+ * Print register of task into buffer. Used in fs/proc/array.c.
+ */
+extern void task_show_regs(struct seq_file *m, struct task_struct *task);
+
+extern void show_code(struct pt_regs *regs);
+
+unsigned long get_wchan(struct task_struct *p);
+#define task_pt_regs(tsk) ((struct pt_regs *) \
+        (task_stack_page(tsk) + THREAD_SIZE) - 1)
+#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
+#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
+
+/*
+ * Give up the time slice of the virtual PU.
+ */
+static inline void cpu_relax(void)
+{
+        if (MACHINE_HAS_DIAG44)
+                asm volatile("diag 0,0,68");
+        barrier();
+}
+
+static inline void psw_set_key(unsigned int key)
+{
+        asm volatile("spka 0(%0)" : : "d" (key));
+}
+
+/*
+ * Set PSW to specified value.
+ */
+static inline void __load_psw(psw_t psw)
+{
+#ifndef __s390x__
+        asm volatile("lpsw  0(%0)" : : "a" (&psw), "m" (psw) : "cc");
+#else
+        asm volatile("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc");
+#endif
+}
+
+/*
+ * Set PSW mask to specified value, while leaving the
+ * PSW addr pointing to the next instruction.
+ */
+
+static inline void __load_psw_mask (unsigned long mask)
+{
+        unsigned long addr;
+        psw_t psw;
+
+        psw.mask = mask;
+
+#ifndef __s390x__
+        asm volatile(
+                "       basr    %0,0\n"
+                "0:     ahi     %0,1f-0b\n"
+                "       st      %0,4(%1)\n"
+                "       lpsw    0(%1)\n"
+                "1:"
+                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
+#else /* __s390x__ */
+        asm volatile(
+                "       larl    %0,1f\n"
+                "       stg     %0,8(%1)\n"
+                "       lpswe   0(%1)\n"
+                "1:"
+                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
+#endif /* __s390x__ */
+}
+ 
+/*
+ * Function to stop a processor until an interruption occurred
+ */
+static inline void enabled_wait(void)
+{
+        __load_psw_mask(PSW_BASE_BITS | PSW_MASK_IO | PSW_MASK_EXT |
+                        PSW_MASK_MCHECK | PSW_MASK_WAIT | PSW_DEFAULT_KEY);
+}
+
+/*
+ * Function to drop a processor into disabled wait state
+ */
+
+static inline void disabled_wait(unsigned long code)
+{
+        unsigned long ctl_buf;
+        psw_t dw_psw;
+
+        dw_psw.mask = PSW_BASE_BITS | PSW_MASK_WAIT;
+        dw_psw.addr = code;
+        /* 
+         * Store status and then load disabled wait psw,
+         * the processor is dead afterwards
+         */
+#ifndef __s390x__
+        asm volatile(
+                "       stctl   0,0,0(%2)\n"
+                "       ni      0(%2),0xef\n"   /* switch off protection */
+                "       lctl    0,0,0(%2)\n"
+                "       stpt    0xd8\n"         /* store timer */
+                "       stckc   0xe0\n"         /* store clock comparator */
+                "       stpx    0x108\n"        /* store prefix register */
+                "       stam    0,15,0x120\n"   /* store access registers */
+                "       std     0,0x160\n"      /* store f0 */
+                "       std     2,0x168\n"      /* store f2 */
+                "       std     4,0x170\n"      /* store f4 */
+                "       std     6,0x178\n"      /* store f6 */
+                "       stm     0,15,0x180\n"   /* store general registers */
+                "       stctl   0,15,0x1c0\n"   /* store control registers */
+                "       oi      0x1c0,0x10\n"   /* fake protection bit */
+                "       lpsw    0(%1)"
+                : "=m" (ctl_buf)
+                : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
+#else /* __s390x__ */
+        asm volatile(
+                "       stctg   0,0,0(%2)\n"
+                "       ni      4(%2),0xef\n"   /* switch off protection */
+                "       lctlg   0,0,0(%2)\n"
+                "       lghi    1,0x1000\n"
+                "       stpt    0x328(1)\n"     /* store timer */
+                "       stckc   0x330(1)\n"     /* store clock comparator */
+                "       stpx    0x318(1)\n"     /* store prefix register */
+                "       stam    0,15,0x340(1)\n"/* store access registers */
+                "       stfpc   0x31c(1)\n"     /* store fpu control */
+                "       std     0,0x200(1)\n"   /* store f0 */
+                "       std     1,0x208(1)\n"   /* store f1 */
+                "       std     2,0x210(1)\n"   /* store f2 */
+                "       std     3,0x218(1)\n"   /* store f3 */
+                "       std     4,0x220(1)\n"   /* store f4 */
+                "       std     5,0x228(1)\n"   /* store f5 */
+                "       std     6,0x230(1)\n"   /* store f6 */
+                "       std     7,0x238(1)\n"   /* store f7 */
+                "       std     8,0x240(1)\n"   /* store f8 */
+                "       std     9,0x248(1)\n"   /* store f9 */
+                "       std     10,0x250(1)\n"  /* store f10 */
+                "       std     11,0x258(1)\n"  /* store f11 */
+                "       std     12,0x260(1)\n"  /* store f12 */
+                "       std     13,0x268(1)\n"  /* store f13 */
+                "       std     14,0x270(1)\n"  /* store f14 */
+                "       std     15,0x278(1)\n"  /* store f15 */
+                "       stmg    0,15,0x280(1)\n"/* store general registers */
+                "       stctg   0,15,0x380(1)\n"/* store control registers */
+                "       oi      0x384(1),0x10\n"/* fake protection bit */
+                "       lpswe   0(%1)"
+                : "=m" (ctl_buf)
+                : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0");
+#endif /* __s390x__ */
+}
+
+/*
+ * Basic Machine Check/Program Check Handler.
+ */
+
+extern void s390_base_mcck_handler(void);
+extern void s390_base_pgm_handler(void);
+extern void s390_base_ext_handler(void);
+
+extern void (*s390_base_mcck_handler_fn)(void);
+extern void (*s390_base_pgm_handler_fn)(void);
+extern void (*s390_base_ext_handler_fn)(void);
+
+#define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
+
+#endif
+
+/*
+ * Helper macro for exception table entries
+ */
+#ifndef __s390x__
+#define EX_TABLE(_fault,_target)                        \
+        ".section __ex_table,\"a\"\n"                   \
+        "       .align 4\n"                             \
+        "       .long  " #_fault "," #_target "\n"      \
+        ".previous\n"
+#else
+#define EX_TABLE(_fault,_target)                        \
+        ".section __ex_table,\"a\"\n"                   \
+        "       .align 8\n"                             \
+        "       .quad  " #_fault "," #_target "\n"      \
+        ".previous\n"
+#endif
+
+#endif                                 /* __ASM_S390_PROCESSOR_H           */
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
new file mode 100644
index 000000000000..af2c9ac28a07
--- /dev/null
+++ b/arch/s390/include/asm/ptrace.h
@@ -0,0 +1,499 @@
+/*
+ *  include/asm-s390/ptrace.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
+ */
+
+#ifndef _S390_PTRACE_H
+#define _S390_PTRACE_H
+
+/*
+ * Offsets in the user_regs_struct. They are used for the ptrace
+ * system call and in entry.S
+ */
+#ifndef __s390x__
+
+#define PT_PSWMASK  0x00
+#define PT_PSWADDR  0x04
+#define PT_GPR0     0x08
+#define PT_GPR1     0x0C
+#define PT_GPR2     0x10
+#define PT_GPR3     0x14
+#define PT_GPR4     0x18
+#define PT_GPR5     0x1C
+#define PT_GPR6     0x20
+#define PT_GPR7     0x24
+#define PT_GPR8     0x28
+#define PT_GPR9     0x2C
+#define PT_GPR10    0x30
+#define PT_GPR11    0x34
+#define PT_GPR12    0x38
+#define PT_GPR13    0x3C
+#define PT_GPR14    0x40
+#define PT_GPR15    0x44
+#define PT_ACR0     0x48
+#define PT_ACR1     0x4C
+#define PT_ACR2     0x50
+#define PT_ACR3     0x54
+#define PT_ACR4     0x58
+#define PT_ACR5     0x5C
+#define PT_ACR6     0x60
+#define PT_ACR7     0x64
+#define PT_ACR8     0x68
+#define PT_ACR9     0x6C
+#define PT_ACR10    0x70
+#define PT_ACR11    0x74
+#define PT_ACR12    0x78
+#define PT_ACR13    0x7C
+#define PT_ACR14    0x80
+#define PT_ACR15    0x84
+#define PT_ORIGGPR2 0x88
+#define PT_FPC      0x90
+/*
+ * A nasty fact of life that the ptrace api
+ * only supports passing of longs.
+ */
+#define PT_FPR0_HI  0x98
+#define PT_FPR0_LO  0x9C
+#define PT_FPR1_HI  0xA0
+#define PT_FPR1_LO  0xA4
+#define PT_FPR2_HI  0xA8
+#define PT_FPR2_LO  0xAC
+#define PT_FPR3_HI  0xB0
+#define PT_FPR3_LO  0xB4
+#define PT_FPR4_HI  0xB8
+#define PT_FPR4_LO  0xBC
+#define PT_FPR5_HI  0xC0
+#define PT_FPR5_LO  0xC4
+#define PT_FPR6_HI  0xC8
+#define PT_FPR6_LO  0xCC
+#define PT_FPR7_HI  0xD0
+#define PT_FPR7_LO  0xD4
+#define PT_FPR8_HI  0xD8
+#define PT_FPR8_LO  0XDC
+#define PT_FPR9_HI  0xE0
+#define PT_FPR9_LO  0xE4
+#define PT_FPR10_HI 0xE8
+#define PT_FPR10_LO 0xEC
+#define PT_FPR11_HI 0xF0
+#define PT_FPR11_LO 0xF4
+#define PT_FPR12_HI 0xF8
+#define PT_FPR12_LO 0xFC
+#define PT_FPR13_HI 0x100
+#define PT_FPR13_LO 0x104
+#define PT_FPR14_HI 0x108
+#define PT_FPR14_LO 0x10C
+#define PT_FPR15_HI 0x110
+#define PT_FPR15_LO 0x114
+#define PT_CR_9     0x118
+#define PT_CR_10    0x11C
+#define PT_CR_11    0x120
+#define PT_IEEE_IP  0x13C
+#define PT_LASTOFF  PT_IEEE_IP
+#define PT_ENDREGS  0x140-1
+
+#define GPR_SIZE        4
+#define CR_SIZE         4
+
+#define STACK_FRAME_OVERHEAD    96      /* size of minimum stack frame */
+
+#else /* __s390x__ */
+
+#define PT_PSWMASK  0x00
+#define PT_PSWADDR  0x08
+#define PT_GPR0     0x10
+#define PT_GPR1     0x18
+#define PT_GPR2     0x20
+#define PT_GPR3     0x28
+#define PT_GPR4     0x30
+#define PT_GPR5     0x38
+#define PT_GPR6     0x40
+#define PT_GPR7     0x48
+#define PT_GPR8     0x50
+#define PT_GPR9     0x58
+#define PT_GPR10    0x60
+#define PT_GPR11    0x68
+#define PT_GPR12    0x70
+#define PT_GPR13    0x78
+#define PT_GPR14    0x80
+#define PT_GPR15    0x88
+#define PT_ACR0     0x90
+#define PT_ACR1     0x94
+#define PT_ACR2     0x98
+#define PT_ACR3     0x9C
+#define PT_ACR4     0xA0
+#define PT_ACR5     0xA4
+#define PT_ACR6     0xA8
+#define PT_ACR7     0xAC
+#define PT_ACR8     0xB0
+#define PT_ACR9     0xB4
+#define PT_ACR10    0xB8
+#define PT_ACR11    0xBC
+#define PT_ACR12    0xC0
+#define PT_ACR13    0xC4
+#define PT_ACR14    0xC8
+#define PT_ACR15    0xCC
+#define PT_ORIGGPR2 0xD0
+#define PT_FPC      0xD8
+#define PT_FPR0     0xE0
+#define PT_FPR1     0xE8
+#define PT_FPR2     0xF0
+#define PT_FPR3     0xF8
+#define PT_FPR4     0x100
+#define PT_FPR5     0x108
+#define PT_FPR6     0x110
+#define PT_FPR7     0x118
+#define PT_FPR8     0x120
+#define PT_FPR9     0x128
+#define PT_FPR10    0x130
+#define PT_FPR11    0x138
+#define PT_FPR12    0x140
+#define PT_FPR13    0x148
+#define PT_FPR14    0x150
+#define PT_FPR15    0x158
+#define PT_CR_9     0x160
+#define PT_CR_10    0x168
+#define PT_CR_11    0x170
+#define PT_IEEE_IP  0x1A8
+#define PT_LASTOFF  PT_IEEE_IP
+#define PT_ENDREGS  0x1B0-1
+
+#define GPR_SIZE        8
+#define CR_SIZE         8
+
+#define STACK_FRAME_OVERHEAD    160      /* size of minimum stack frame */
+
+#endif /* __s390x__ */
+
+#define NUM_GPRS        16
+#define NUM_FPRS        16
+#define NUM_CRS         16
+#define NUM_ACRS        16
+
+#define FPR_SIZE        8
+#define FPC_SIZE        4
+#define FPC_PAD_SIZE    4 /* gcc insists on aligning the fpregs */
+#define ACR_SIZE        4
+
+
+#define PTRACE_OLDSETOPTIONS         21
+
+#ifndef __ASSEMBLY__
+#include <linux/stddef.h>
+#include <linux/types.h>
+
+typedef union
+{
+        float   f;
+        double  d;
+        __u64   ui;
+        struct
+        {
+                __u32 hi;
+                __u32 lo;
+        } fp;
+} freg_t;
+
+typedef struct
+{
+        __u32   fpc;
+        freg_t  fprs[NUM_FPRS];              
+} s390_fp_regs;
+
+#define FPC_EXCEPTION_MASK      0xF8000000
+#define FPC_FLAGS_MASK          0x00F80000
+#define FPC_DXC_MASK            0x0000FF00
+#define FPC_RM_MASK             0x00000003
+#define FPC_VALID_MASK          0xF8F8FF03
+
+/* this typedef defines how a Program Status Word looks like */
+typedef struct 
+{
+        unsigned long mask;
+        unsigned long addr;
+} __attribute__ ((aligned(8))) psw_t;
+
+typedef struct
+{
+        __u32   mask;
+        __u32   addr;
+} __attribute__ ((aligned(8))) psw_compat_t;
+
+#ifndef __s390x__
+
+#define PSW_MASK_PER            0x40000000UL
+#define PSW_MASK_DAT            0x04000000UL
+#define PSW_MASK_IO             0x02000000UL
+#define PSW_MASK_EXT            0x01000000UL
+#define PSW_MASK_KEY            0x00F00000UL
+#define PSW_MASK_MCHECK         0x00040000UL
+#define PSW_MASK_WAIT           0x00020000UL
+#define PSW_MASK_PSTATE         0x00010000UL
+#define PSW_MASK_ASC            0x0000C000UL
+#define PSW_MASK_CC             0x00003000UL
+#define PSW_MASK_PM             0x00000F00UL
+
+#define PSW_ADDR_AMODE          0x80000000UL
+#define PSW_ADDR_INSN           0x7FFFFFFFUL
+
+#define PSW_BASE_BITS           0x00080000UL
+#define PSW_DEFAULT_KEY         (((unsigned long) PAGE_DEFAULT_ACC) << 20)
+
+#define PSW_ASC_PRIMARY         0x00000000UL
+#define PSW_ASC_ACCREG          0x00004000UL
+#define PSW_ASC_SECONDARY       0x00008000UL
+#define PSW_ASC_HOME            0x0000C000UL
+
+#else /* __s390x__ */
+
+#define PSW_MASK_PER            0x4000000000000000UL
+#define PSW_MASK_DAT            0x0400000000000000UL
+#define PSW_MASK_IO             0x0200000000000000UL
+#define PSW_MASK_EXT            0x0100000000000000UL
+#define PSW_MASK_KEY            0x00F0000000000000UL
+#define PSW_MASK_MCHECK         0x0004000000000000UL
+#define PSW_MASK_WAIT           0x0002000000000000UL
+#define PSW_MASK_PSTATE         0x0001000000000000UL
+#define PSW_MASK_ASC            0x0000C00000000000UL
+#define PSW_MASK_CC             0x0000300000000000UL
+#define PSW_MASK_PM             0x00000F0000000000UL
+
+#define PSW_ADDR_AMODE          0x0000000000000000UL
+#define PSW_ADDR_INSN           0xFFFFFFFFFFFFFFFFUL
+
+#define PSW_BASE_BITS           0x0000000180000000UL
+#define PSW_BASE32_BITS         0x0000000080000000UL
+#define PSW_DEFAULT_KEY         (((unsigned long) PAGE_DEFAULT_ACC) << 52)
+
+#define PSW_ASC_PRIMARY         0x0000000000000000UL
+#define PSW_ASC_ACCREG          0x0000400000000000UL
+#define PSW_ASC_SECONDARY       0x0000800000000000UL
+#define PSW_ASC_HOME            0x0000C00000000000UL
+
+extern long psw_user32_bits;
+
+#endif /* __s390x__ */
+
+extern long psw_kernel_bits;
+extern long psw_user_bits;
+
+/* This macro merges a NEW PSW mask specified by the user into
+   the currently active PSW mask CURRENT, modifying only those
+   bits in CURRENT that the user may be allowed to change: this
+   is the condition code and the program mask bits.  */
+#define PSW_MASK_MERGE(CURRENT,NEW) \
+        (((CURRENT) & ~(PSW_MASK_CC|PSW_MASK_PM)) | \
+         ((NEW) & (PSW_MASK_CC|PSW_MASK_PM)))
+
+/*
+ * The s390_regs structure is used to define the elf_gregset_t.
+ */
+typedef struct
+{
+        psw_t psw;
+        unsigned long gprs[NUM_GPRS];
+        unsigned int  acrs[NUM_ACRS];
+        unsigned long orig_gpr2;
+} s390_regs;
+
+typedef struct
+{
+        psw_compat_t    psw;
+        __u32           gprs[NUM_GPRS];
+        __u32           acrs[NUM_ACRS];
+        __u32           orig_gpr2;
+} s390_compat_regs;
+
+
+#ifdef __KERNEL__
+#include <asm/setup.h>
+#include <asm/page.h>
+
+/*
+ * The pt_regs struct defines the way the registers are stored on
+ * the stack during a system call.
+ */
+struct pt_regs 
+{
+        unsigned long args[1];
+        psw_t psw;
+        unsigned long gprs[NUM_GPRS];
+        unsigned long orig_gpr2;
+        unsigned short ilc;
+        unsigned short trap;
+};
+#endif
+
+/*
+ * Now for the program event recording (trace) definitions.
+ */
+typedef struct
+{
+        unsigned long cr[3];
+} per_cr_words;
+
+#define PER_EM_MASK 0xE8000000UL
+
+typedef struct
+{
+#ifdef __s390x__
+        unsigned                       : 32;
+#endif /* __s390x__ */
+        unsigned em_branching          : 1;
+        unsigned em_instruction_fetch  : 1;
+        /*
+         * Switching on storage alteration automatically fixes
+         * the storage alteration event bit in the users std.
+         */
+        unsigned em_storage_alteration : 1;
+        unsigned em_gpr_alt_unused     : 1;
+        unsigned em_store_real_address : 1;
+        unsigned                       : 3;
+        unsigned branch_addr_ctl       : 1;
+        unsigned                       : 1;
+        unsigned storage_alt_space_ctl : 1;
+        unsigned                       : 21;
+        unsigned long starting_addr;
+        unsigned long ending_addr;
+} per_cr_bits;
+
+typedef struct
+{
+        unsigned short perc_atmid;
+        unsigned long address;
+        unsigned char access_id;
+} per_lowcore_words;
+
+typedef struct
+{
+        unsigned perc_branching          : 1;
+        unsigned perc_instruction_fetch  : 1;
+        unsigned perc_storage_alteration : 1;
+        unsigned perc_gpr_alt_unused     : 1;
+        unsigned perc_store_real_address : 1;
+        unsigned                         : 3;
+        unsigned atmid_psw_bit_31        : 1;
+        unsigned atmid_validity_bit      : 1;
+        unsigned atmid_psw_bit_32        : 1;
+        unsigned atmid_psw_bit_5         : 1;
+        unsigned atmid_psw_bit_16        : 1;
+        unsigned atmid_psw_bit_17        : 1;
+        unsigned si                      : 2;
+        unsigned long address;
+        unsigned                         : 4;
+        unsigned access_id               : 4;
+} per_lowcore_bits;
+
+typedef struct
+{
+        union {
+                per_cr_words   words;
+                per_cr_bits    bits;
+        } control_regs;
+        /*
+         * Use these flags instead of setting em_instruction_fetch
+         * directly they are used so that single stepping can be
+         * switched on & off while not affecting other tracing
+         */
+        unsigned  single_step       : 1;
+        unsigned  instruction_fetch : 1;
+        unsigned                    : 30;
+        /*
+         * These addresses are copied into cr10 & cr11 if single
+         * stepping is switched off
+         */
+        unsigned long starting_addr;
+        unsigned long ending_addr;
+        union {
+                per_lowcore_words words;
+                per_lowcore_bits  bits;
+        } lowcore; 
+} per_struct;
+
+typedef struct
+{
+        unsigned int  len;
+        unsigned long kernel_addr;
+        unsigned long process_addr;
+} ptrace_area;
+
+/*
+ * S/390 specific non posix ptrace requests. I chose unusual values so
+ * they are unlikely to clash with future ptrace definitions.
+ */
+#define PTRACE_PEEKUSR_AREA           0x5000
+#define PTRACE_POKEUSR_AREA           0x5001
+#define PTRACE_PEEKTEXT_AREA          0x5002
+#define PTRACE_PEEKDATA_AREA          0x5003
+#define PTRACE_POKETEXT_AREA          0x5004
+#define PTRACE_POKEDATA_AREA          0x5005
+
+/*
+ * PT_PROT definition is loosely based on hppa bsd definition in
+ * gdb/hppab-nat.c
+ */
+#define PTRACE_PROT                       21
+
+typedef enum
+{
+        ptprot_set_access_watchpoint,
+        ptprot_set_write_watchpoint,
+        ptprot_disable_watchpoint
+} ptprot_flags;
+
+typedef struct
+{
+        unsigned long lowaddr;
+        unsigned long hiaddr;
+        ptprot_flags prot;
+} ptprot_area;                     
+
+/* Sequence of bytes for breakpoint illegal instruction.  */
+#define S390_BREAKPOINT     {0x0,0x1}
+#define S390_BREAKPOINT_U16 ((__u16)0x0001)
+#define S390_SYSCALL_OPCODE ((__u16)0x0a00)
+#define S390_SYSCALL_SIZE   2
+
+/*
+ * The user_regs_struct defines the way the user registers are
+ * store on the stack for signal handling.
+ */
+struct user_regs_struct
+{
+        psw_t psw;
+        unsigned long gprs[NUM_GPRS];
+        unsigned int  acrs[NUM_ACRS];
+        unsigned long orig_gpr2;
+        s390_fp_regs fp_regs;
+        /*
+         * These per registers are in here so that gdb can modify them
+         * itself as there is no "official" ptrace interface for hardware
+         * watchpoints. This is the way intel does it.
+         */
+        per_struct per_info;
+        unsigned long ieee_instruction_pointer; 
+        /* Used to give failing instruction back to user for ieee exceptions */
+};
+
+#ifdef __KERNEL__
+/*
+ * These are defined as per linux/ptrace.h, which see.
+ */
+#define arch_has_single_step()  (1)
+struct task_struct;
+extern void user_enable_single_step(struct task_struct *);
+extern void user_disable_single_step(struct task_struct *);
+
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+
+#define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
+#define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
+#define regs_return_value(regs)((regs)->gprs[2])
+#define profile_pc(regs) instruction_pointer(regs)
+extern void show_regs(struct pt_regs * regs);
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _S390_PTRACE_H */
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
new file mode 100644
index 000000000000..6813772171f2
--- /dev/null
+++ b/arch/s390/include/asm/qdio.h
@@ -0,0 +1,382 @@
+/*
+ * linux/include/asm-s390/qdio.h
+ *
+ * Copyright 2000,2008 IBM Corp.
+ * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
+ *            Jan Glauber <jang@linux.vnet.ibm.com>
+ *
+ */
+#ifndef __QDIO_H__
+#define __QDIO_H__
+
+#include <linux/interrupt.h>
+#include <asm/cio.h>
+#include <asm/ccwdev.h>
+
+#define QDIO_MAX_QUEUES_PER_IRQ         32
+#define QDIO_MAX_BUFFERS_PER_Q          128
+#define QDIO_MAX_BUFFERS_MASK           (QDIO_MAX_BUFFERS_PER_Q - 1)
+#define QDIO_MAX_ELEMENTS_PER_BUFFER    16
+#define QDIO_SBAL_SIZE                  256
+
+#define QDIO_QETH_QFMT                  0
+#define QDIO_ZFCP_QFMT                  1
+#define QDIO_IQDIO_QFMT                 2
+
+/**
+ * struct qdesfmt0 - queue descriptor, format 0
+ * @sliba: storage list information block address
+ * @sla: storage list address
+ * @slsba: storage list state block address
+ * @akey: access key for DLIB
+ * @bkey: access key for SL
+ * @ckey: access key for SBALs
+ * @dkey: access key for SLSB
+ */
+struct qdesfmt0 {
+        u64 sliba;
+        u64 sla;
+        u64 slsba;
+        u32      : 32;
+        u32 akey : 4;
+        u32 bkey : 4;
+        u32 ckey : 4;
+        u32 dkey : 4;
+        u32      : 16;
+} __attribute__ ((packed));
+
+/**
+ * struct qdr - queue description record (QDR)
+ * @qfmt: queue format
+ * @pfmt: implementation dependent parameter format
+ * @ac: adapter characteristics
+ * @iqdcnt: input queue descriptor count
+ * @oqdcnt: output queue descriptor count
+ * @iqdsz: inpout queue descriptor size
+ * @oqdsz: output queue descriptor size
+ * @qiba: queue information block address
+ * @qkey: queue information block key
+ * @qdf0: queue descriptions
+ */
+struct qdr {
+        u32 qfmt   : 8;
+        u32 pfmt   : 8;
+        u32        : 8;
+        u32 ac     : 8;
+        u32        : 8;
+        u32 iqdcnt : 8;
+        u32        : 8;
+        u32 oqdcnt : 8;
+        u32        : 8;
+        u32 iqdsz  : 8;
+        u32        : 8;
+        u32 oqdsz  : 8;
+        /* private: */
+        u32 res[9];
+        /* public: */
+        u64 qiba;
+        u32        : 32;
+        u32 qkey   : 4;
+        u32        : 28;
+        struct qdesfmt0 qdf0[126];
+} __attribute__ ((packed, aligned(4096)));
+
+#define QIB_AC_OUTBOUND_PCI_SUPPORTED   0x40
+#define QIB_RFLAGS_ENABLE_QEBSM         0x80
+
+/**
+ * struct qib - queue information block (QIB)
+ * @qfmt: queue format
+ * @pfmt: implementation dependent parameter format
+ * @rflags: QEBSM
+ * @ac: adapter characteristics
+ * @isliba: absolute address of first input SLIB
+ * @osliba: absolute address of first output SLIB
+ * @ebcnam: adapter identifier in EBCDIC
+ * @parm: implementation dependent parameters
+ */
+struct qib {
+        u32 qfmt   : 8;
+        u32 pfmt   : 8;
+        u32 rflags : 8;
+        u32 ac     : 8;
+        u32        : 32;
+        u64 isliba;
+        u64 osliba;
+        u32        : 32;
+        u32        : 32;
+        u8 ebcnam[8];
+        /* private: */
+        u8 res[88];
+        /* public: */
+        u8 parm[QDIO_MAX_BUFFERS_PER_Q];
+} __attribute__ ((packed, aligned(256)));
+
+/**
+ * struct slibe - storage list information block element (SLIBE)
+ * @parms: implementation dependent parameters
+ */
+struct slibe {
+        u64 parms;
+};
+
+/**
+ * struct slib - storage list information block (SLIB)
+ * @nsliba: next SLIB address (if any)
+ * @sla: SL address
+ * @slsba: SLSB address
+ * @slibe: SLIB elements
+ */
+struct slib {
+        u64 nsliba;
+        u64 sla;
+        u64 slsba;
+        /* private: */
+        u8 res[1000];
+        /* public: */
+        struct slibe slibe[QDIO_MAX_BUFFERS_PER_Q];
+} __attribute__ ((packed, aligned(2048)));
+
+/**
+ * struct sbal_flags - storage block address list flags
+ * @last: last entry
+ * @cont: contiguous storage
+ * @frag: fragmentation
+ */
+struct sbal_flags {
+        u8      : 1;
+        u8 last : 1;
+        u8 cont : 1;
+        u8      : 1;
+        u8 frag : 2;
+        u8      : 2;
+} __attribute__ ((packed));
+
+#define SBAL_FLAGS_FIRST_FRAG           0x04000000UL
+#define SBAL_FLAGS_MIDDLE_FRAG          0x08000000UL
+#define SBAL_FLAGS_LAST_FRAG            0x0c000000UL
+#define SBAL_FLAGS_LAST_ENTRY           0x40000000UL
+#define SBAL_FLAGS_CONTIGUOUS           0x20000000UL
+
+#define SBAL_FLAGS0_DATA_CONTINUATION   0x20UL
+
+/* Awesome OpenFCP extensions */
+#define SBAL_FLAGS0_TYPE_STATUS         0x00UL
+#define SBAL_FLAGS0_TYPE_WRITE          0x08UL
+#define SBAL_FLAGS0_TYPE_READ           0x10UL
+#define SBAL_FLAGS0_TYPE_WRITE_READ     0x18UL
+#define SBAL_FLAGS0_MORE_SBALS          0x04UL
+#define SBAL_FLAGS0_COMMAND             0x02UL
+#define SBAL_FLAGS0_LAST_SBAL           0x00UL
+#define SBAL_FLAGS0_ONLY_SBAL           SBAL_FLAGS0_COMMAND
+#define SBAL_FLAGS0_MIDDLE_SBAL         SBAL_FLAGS0_MORE_SBALS
+#define SBAL_FLAGS0_FIRST_SBAL SBAL_FLAGS0_MORE_SBALS | SBAL_FLAGS0_COMMAND
+#define SBAL_FLAGS0_PCI                 0x40
+
+/**
+ * struct sbal_sbalf_0 - sbal flags for sbale 0
+ * @pci: PCI indicator
+ * @cont: data continuation
+ * @sbtype: storage-block type (FCP)
+ */
+struct sbal_sbalf_0 {
+        u8        : 1;
+        u8 pci    : 1;
+        u8 cont   : 1;
+        u8 sbtype : 2;
+        u8        : 3;
+} __attribute__ ((packed));
+
+/**
+ * struct sbal_sbalf_1 - sbal flags for sbale 1
+ * @key: storage key
+ */
+struct sbal_sbalf_1 {
+        u8     : 4;
+        u8 key : 4;
+} __attribute__ ((packed));
+
+/**
+ * struct sbal_sbalf_14 - sbal flags for sbale 14
+ * @erridx: error index
+ */
+struct sbal_sbalf_14 {
+        u8        : 4;
+        u8 erridx : 4;
+} __attribute__ ((packed));
+
+/**
+ * struct sbal_sbalf_15 - sbal flags for sbale 15
+ * @reason: reason for error state
+ */
+struct sbal_sbalf_15 {
+        u8 reason;
+} __attribute__ ((packed));
+
+/**
+ * union sbal_sbalf - storage block address list flags
+ * @i0: sbalf0
+ * @i1: sbalf1
+ * @i14: sbalf14
+ * @i15: sblaf15
+ * @value: raw value
+ */
+union sbal_sbalf {
+        struct sbal_sbalf_0  i0;
+        struct sbal_sbalf_1  i1;
+        struct sbal_sbalf_14 i14;
+        struct sbal_sbalf_15 i15;
+        u8 value;
+};
+
+/**
+ * struct qdio_buffer_element - SBAL entry
+ * @flags: flags
+ * @length: length
+ * @addr: address
+*/
+struct qdio_buffer_element {
+        u32 flags;
+        u32 length;
+#ifdef CONFIG_32BIT
+        /* private: */
+        void *reserved;
+        /* public: */
+#endif
+        void *addr;
+} __attribute__ ((packed, aligned(16)));
+
+/**
+ * struct qdio_buffer - storage block address list (SBAL)
+ * @element: SBAL entries
+ */
+struct qdio_buffer {
+        struct qdio_buffer_element element[QDIO_MAX_ELEMENTS_PER_BUFFER];
+} __attribute__ ((packed, aligned(256)));
+
+/**
+ * struct sl_element - storage list entry
+ * @sbal: absolute SBAL address
+ */
+struct sl_element {
+#ifdef CONFIG_32BIT
+        /* private: */
+        unsigned long reserved;
+        /* public: */
+#endif
+        unsigned long sbal;
+} __attribute__ ((packed));
+
+/**
+ * struct sl - storage list (SL)
+ * @element: SL entries
+ */
+struct sl {
+        struct sl_element element[QDIO_MAX_BUFFERS_PER_Q];
+} __attribute__ ((packed, aligned(1024)));
+
+/**
+ * struct slsb - storage list state block (SLSB)
+ * @val: state per buffer
+ */
+struct slsb {
+        u8 val[QDIO_MAX_BUFFERS_PER_Q];
+} __attribute__ ((packed, aligned(256)));
+
+struct qdio_ssqd_desc {
+        u8 flags;
+        u8:8;
+        u16 sch;
+        u8 qfmt;
+        u8 parm;
+        u8 qdioac1;
+        u8 sch_class;
+        u8 pcnt;
+        u8 icnt;
+        u8:8;
+        u8 ocnt;
+        u8:8;
+        u8 mbccnt;
+        u16 qdioac2;
+        u64 sch_token;
+        u64:64;
+} __attribute__ ((packed));
+
+/* params are: ccw_device, qdio_error, queue_number,
+   first element processed, number of elements processed, int_parm */
+typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
+                            int, int, unsigned long);
+
+/* qdio errors reported to the upper-layer program */
+#define QDIO_ERROR_SIGA_ACCESS_EXCEPTION        0x10
+#define QDIO_ERROR_SIGA_BUSY                    0x20
+#define QDIO_ERROR_ACTIVATE_CHECK_CONDITION     0x40
+#define QDIO_ERROR_SLSB_STATE                   0x80
+
+/* for qdio_initialize */
+#define QDIO_INBOUND_0COPY_SBALS                0x01
+#define QDIO_OUTBOUND_0COPY_SBALS               0x02
+#define QDIO_USE_OUTBOUND_PCIS                  0x04
+
+/* for qdio_cleanup */
+#define QDIO_FLAG_CLEANUP_USING_CLEAR           0x01
+#define QDIO_FLAG_CLEANUP_USING_HALT            0x02
+
+/**
+ * struct qdio_initialize - qdio initalization data
+ * @cdev: associated ccw device
+ * @q_format: queue format
+ * @adapter_name: name for the adapter
+ * @qib_param_field_format: format for qib_parm_field
+ * @qib_param_field: pointer to 128 bytes or NULL, if no param field
+ * @input_slib_elements: pointer to no_input_qs * 128 words of data or NULL
+ * @output_slib_elements: pointer to no_output_qs * 128 words of data or NULL
+ * @no_input_qs: number of input queues
+ * @no_output_qs: number of output queues
+ * @input_handler: handler to be called for input queues
+ * @output_handler: handler to be called for output queues
+ * @int_parm: interruption parameter
+ * @flags: initialization flags
+ * @input_sbal_addr_array:  address of no_input_qs * 128 pointers
+ * @output_sbal_addr_array: address of no_output_qs * 128 pointers
+ */
+struct qdio_initialize {
+        struct ccw_device *cdev;
+        unsigned char q_format;
+        unsigned char adapter_name[8];
+        unsigned int qib_param_field_format;
+        unsigned char *qib_param_field;
+        unsigned long *input_slib_elements;
+        unsigned long *output_slib_elements;
+        unsigned int no_input_qs;
+        unsigned int no_output_qs;
+        qdio_handler_t *input_handler;
+        qdio_handler_t *output_handler;
+        unsigned long int_parm;
+        unsigned long flags;
+        void **input_sbal_addr_array;
+        void **output_sbal_addr_array;
+};
+
+#define QDIO_STATE_INACTIVE             0x00000002 /* after qdio_cleanup */
+#define QDIO_STATE_ESTABLISHED          0x00000004 /* after qdio_establish */
+#define QDIO_STATE_ACTIVE               0x00000008 /* after qdio_activate */
+#define QDIO_STATE_STOPPED              0x00000010 /* after queues went down */
+
+#define QDIO_FLAG_SYNC_INPUT            0x01
+#define QDIO_FLAG_SYNC_OUTPUT           0x02
+#define QDIO_FLAG_PCI_OUT               0x10
+
+extern int qdio_initialize(struct qdio_initialize *init_data);
+extern int qdio_allocate(struct qdio_initialize *init_data);
+extern int qdio_establish(struct qdio_initialize *init_data);
+extern int qdio_activate(struct ccw_device *);
+
+extern int do_QDIO(struct ccw_device*, unsigned int flags,
+                   int q_nr, int qidx, int count);
+extern int qdio_cleanup(struct ccw_device*, int how);
+extern int qdio_shutdown(struct ccw_device*, int how);
+extern int qdio_free(struct ccw_device *);
+extern struct qdio_ssqd_desc *qdio_get_ssqd_desc(struct ccw_device *cdev);
+
+#endif /* __QDIO_H__ */
diff --git a/arch/s390/include/asm/qeth.h b/arch/s390/include/asm/qeth.h
new file mode 100644
index 000000000000..930d378ef75a
--- /dev/null
+++ b/arch/s390/include/asm/qeth.h
@@ -0,0 +1,78 @@
+/*
+ * include/asm-s390/qeth.h
+ *
+ * ioctl definitions for qeth driver
+ *
+ * Copyright (C) 2004 IBM Corporation
+ *
+ * Author(s):   Thomas Spatzier <tspat@de.ibm.com>
+ *
+ */
+#ifndef __ASM_S390_QETH_IOCTL_H__
+#define __ASM_S390_QETH_IOCTL_H__
+#include <linux/ioctl.h>
+
+#define SIOC_QETH_ARP_SET_NO_ENTRIES    (SIOCDEVPRIVATE)
+#define SIOC_QETH_ARP_QUERY_INFO        (SIOCDEVPRIVATE + 1)
+#define SIOC_QETH_ARP_ADD_ENTRY         (SIOCDEVPRIVATE + 2)
+#define SIOC_QETH_ARP_REMOVE_ENTRY      (SIOCDEVPRIVATE + 3)
+#define SIOC_QETH_ARP_FLUSH_CACHE       (SIOCDEVPRIVATE + 4)
+#define SIOC_QETH_ADP_SET_SNMP_CONTROL  (SIOCDEVPRIVATE + 5)
+#define SIOC_QETH_GET_CARD_TYPE         (SIOCDEVPRIVATE + 6)
+
+struct qeth_arp_cache_entry {
+        __u8  macaddr[6];
+        __u8  reserved1[2];
+        __u8  ipaddr[16]; /* for both  IPv4 and IPv6 */
+        __u8  reserved2[32];
+} __attribute__ ((packed));
+
+struct qeth_arp_qi_entry7 {
+        __u8 media_specific[32];
+        __u8 macaddr_type;
+        __u8 ipaddr_type;
+        __u8 macaddr[6];
+        __u8 ipaddr[4];
+} __attribute__((packed));
+
+struct qeth_arp_qi_entry7_short {
+        __u8 macaddr_type;
+        __u8 ipaddr_type;
+        __u8 macaddr[6];
+        __u8 ipaddr[4];
+} __attribute__((packed));
+
+struct qeth_arp_qi_entry5 {
+        __u8 media_specific[32];
+        __u8 macaddr_type;
+        __u8 ipaddr_type;
+        __u8 ipaddr[4];
+} __attribute__((packed));
+
+struct qeth_arp_qi_entry5_short {
+        __u8 macaddr_type;
+        __u8 ipaddr_type;
+        __u8 ipaddr[4];
+} __attribute__((packed));
+
+/*
+ * can be set by user if no "media specific information" is wanted
+ * -> saves a lot of space in user space buffer
+ */
+#define QETH_QARP_STRIP_ENTRIES  0x8000
+#define QETH_QARP_REQUEST_MASK   0x00ff
+
+/* data sent to user space as result of query arp ioctl */
+#define QETH_QARP_USER_DATA_SIZE 20000
+#define QETH_QARP_MASK_OFFSET    4
+#define QETH_QARP_ENTRIES_OFFSET 6
+struct qeth_arp_query_user_data {
+        union {
+                __u32 data_len;         /* set by user space program */
+                __u32 no_entries;       /* set by kernel */
+        } u;
+        __u16 mask_bits;
+        char *entries;
+} __attribute__((packed));
+
+#endif /* __ASM_S390_QETH_IOCTL_H__ */
diff --git a/arch/s390/include/asm/reset.h b/arch/s390/include/asm/reset.h
new file mode 100644
index 000000000000..f584f4a52581
--- /dev/null
+++ b/arch/s390/include/asm/reset.h
@@ -0,0 +1,21 @@
+/*
+ *  include/asm-s390/reset.h
+ *
+ *    Copyright IBM Corp. 2006
+ *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_RESET_H
+#define _ASM_S390_RESET_H
+
+#include <linux/list.h>
+
+struct reset_call {
+        struct list_head list;
+        void (*fn)(void);
+};
+
+extern void register_reset_call(struct reset_call *reset);
+extern void unregister_reset_call(struct reset_call *reset);
+extern void s390_reset_system(void);
+#endif /* _ASM_S390_RESET_H */
diff --git a/arch/s390/include/asm/resource.h b/arch/s390/include/asm/resource.h
new file mode 100644
index 000000000000..366c01de04f2
--- /dev/null
+++ b/arch/s390/include/asm/resource.h
@@ -0,0 +1,15 @@
+/*
+ *  include/asm-s390/resource.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/resources.h"
+ */
+
+#ifndef _S390_RESOURCE_H
+#define _S390_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif
+
diff --git a/arch/s390/include/asm/rwsem.h b/arch/s390/include/asm/rwsem.h
new file mode 100644
index 000000000000..9d2a17971805
--- /dev/null
+++ b/arch/s390/include/asm/rwsem.h
@@ -0,0 +1,387 @@
+#ifndef _S390_RWSEM_H
+#define _S390_RWSEM_H
+
+/*
+ *  include/asm-s390/rwsem.h
+ *
+ *  S390 version
+ *    Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Based on asm-alpha/semaphore.h and asm-i386/rwsem.h
+ */
+
+/*
+ *
+ * The MSW of the count is the negated number of active writers and waiting
+ * lockers, and the LSW is the total number of active locks
+ *
+ * The lock count is initialized to 0 (no active and no waiting lockers).
+ *
+ * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an
+ * uncontended lock. This can be determined because XADD returns the old value.
+ * Readers increment by 1 and see a positive value when uncontended, negative
+ * if there are writers (and maybe) readers waiting (in which case it goes to
+ * sleep).
+ *
+ * The value of WAITING_BIAS supports up to 32766 waiting processes. This can
+ * be extended to 65534 by manually checking the whole MSW rather than relying
+ * on the S flag.
+ *
+ * The value of ACTIVE_BIAS supports up to 65535 active processes.
+ *
+ * This should be totally fair - if anything is waiting, a process that wants a
+ * lock will go to the back of the queue. When the currently active lock is
+ * released, if there's a writer at the front of the queue, then that and only
+ * that will be woken up; if there's a bunch of consequtive readers at the
+ * front, then they'll all be woken up, but no other readers will be.
+ */
+
+#ifndef _LINUX_RWSEM_H
+#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
+#endif
+
+#ifdef __KERNEL__
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+
+struct rwsem_waiter;
+
+extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *);
+extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *);
+extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *);
+extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *);
+extern struct rw_semaphore *rwsem_downgrade_write(struct rw_semaphore *);
+
+/*
+ * the semaphore definition
+ */
+struct rw_semaphore {
+        signed long             count;
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
+};
+
+#ifndef __s390x__
+#define RWSEM_UNLOCKED_VALUE    0x00000000
+#define RWSEM_ACTIVE_BIAS       0x00000001
+#define RWSEM_ACTIVE_MASK       0x0000ffff
+#define RWSEM_WAITING_BIAS      (-0x00010000)
+#else /* __s390x__ */
+#define RWSEM_UNLOCKED_VALUE    0x0000000000000000L
+#define RWSEM_ACTIVE_BIAS       0x0000000000000001L
+#define RWSEM_ACTIVE_MASK       0x00000000ffffffffL
+#define RWSEM_WAITING_BIAS      (-0x0000000100000000L)
+#endif /* __s390x__ */
+#define RWSEM_ACTIVE_READ_BIAS  RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+
+/*
+ * initialisation
+ */
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+ { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait.lock), \
+   LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
+
+#define DECLARE_RWSEM(name) \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+static inline void init_rwsem(struct rw_semaphore *sem)
+{
+        sem->count = RWSEM_UNLOCKED_VALUE;
+        spin_lock_init(&sem->wait_lock);
+        INIT_LIST_HEAD(&sem->wait_list);
+}
+
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                         \
+do {                                            \
+        static struct lock_class_key __key;     \
+                                                \
+        __init_rwsem((sem), #sem, &__key);      \
+} while (0)
+
+
+/*
+ * lock for reading
+ */
+static inline void __down_read(struct rw_semaphore *sem)
+{
+        signed long old, new;
+
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     lr      %1,%0\n"
+                "       ahi     %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     lgr     %1,%0\n"
+                "       aghi    %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count),
+                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
+        if (old < 0)
+                rwsem_down_read_failed(sem);
+}
+
+/*
+ * trylock for reading -- returns 1 if successful, 0 if contention
+ */
+static inline int __down_read_trylock(struct rw_semaphore *sem)
+{
+        signed long old, new;
+
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     ltr     %1,%0\n"
+                "       jm      1f\n"
+                "       ahi     %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b\n"
+                "1:"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     ltgr    %1,%0\n"
+                "       jm      1f\n"
+                "       aghi    %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b\n"
+                "1:"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count),
+                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
+        return old >= 0 ? 1 : 0;
+}
+
+/*
+ * lock for writing
+ */
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        signed long old, new, tmp;
+
+        tmp = RWSEM_ACTIVE_WRITE_BIAS;
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     lr      %1,%0\n"
+                "       a       %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     lgr     %1,%0\n"
+                "       ag      %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
+                : "cc", "memory");
+        if (old != 0)
+                rwsem_down_write_failed(sem);
+}
+
+static inline void __down_write(struct rw_semaphore *sem)
+{
+        __down_write_nested(sem, 0);
+}
+
+/*
+ * trylock for writing -- returns 1 if successful, 0 if contention
+ */
+static inline int __down_write_trylock(struct rw_semaphore *sem)
+{
+        signed long old;
+
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%2)\n"
+                "0:     ltr     %0,%0\n"
+                "       jnz     1f\n"
+                "       cs      %0,%4,0(%2)\n"
+                "       jl      0b\n"
+#else /* __s390x__ */
+                "       lg      %0,0(%2)\n"
+                "0:     ltgr    %0,%0\n"
+                "       jnz     1f\n"
+                "       csg     %0,%4,0(%2)\n"
+                "       jl      0b\n"
+#endif /* __s390x__ */
+                "1:"
+                : "=&d" (old), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count),
+                  "d" (RWSEM_ACTIVE_WRITE_BIAS) : "cc", "memory");
+        return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0;
+}
+
+/*
+ * unlock after reading
+ */
+static inline void __up_read(struct rw_semaphore *sem)
+{
+        signed long old, new;
+
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     lr      %1,%0\n"
+                "       ahi     %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     lgr     %1,%0\n"
+                "       aghi    %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count),
+                  "i" (-RWSEM_ACTIVE_READ_BIAS)
+                : "cc", "memory");
+        if (new < 0)
+                if ((new & RWSEM_ACTIVE_MASK) == 0)
+                        rwsem_wake(sem);
+}
+
+/*
+ * unlock after writing
+ */
+static inline void __up_write(struct rw_semaphore *sem)
+{
+        signed long old, new, tmp;
+
+        tmp = -RWSEM_ACTIVE_WRITE_BIAS;
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     lr      %1,%0\n"
+                "       a       %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     lgr     %1,%0\n"
+                "       ag      %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
+                : "cc", "memory");
+        if (new < 0)
+                if ((new & RWSEM_ACTIVE_MASK) == 0)
+                        rwsem_wake(sem);
+}
+
+/*
+ * downgrade write lock to read lock
+ */
+static inline void __downgrade_write(struct rw_semaphore *sem)
+{
+        signed long old, new, tmp;
+
+        tmp = -RWSEM_WAITING_BIAS;
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     lr      %1,%0\n"
+                "       a       %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     lgr     %1,%0\n"
+                "       ag      %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
+                : "cc", "memory");
+        if (new > 1)
+                rwsem_downgrade_wake(sem);
+}
+
+/*
+ * implement atomic add functionality
+ */
+static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
+{
+        signed long old, new;
+
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     lr      %1,%0\n"
+                "       ar      %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     lgr     %1,%0\n"
+                "       agr     %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count), "d" (delta)
+                : "cc", "memory");
+}
+
+/*
+ * implement exchange and add functionality
+ */
+static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
+{
+        signed long old, new;
+
+        asm volatile(
+#ifndef __s390x__
+                "       l       %0,0(%3)\n"
+                "0:     lr      %1,%0\n"
+                "       ar      %1,%5\n"
+                "       cs      %0,%1,0(%3)\n"
+                "       jl      0b"
+#else /* __s390x__ */
+                "       lg      %0,0(%3)\n"
+                "0:     lgr     %1,%0\n"
+                "       agr     %1,%5\n"
+                "       csg     %0,%1,0(%3)\n"
+                "       jl      0b"
+#endif /* __s390x__ */
+                : "=&d" (old), "=&d" (new), "=m" (sem->count)
+                : "a" (&sem->count), "m" (sem->count), "d" (delta)
+                : "cc", "memory");
+        return new;
+}
+
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _S390_RWSEM_H */
diff --git a/arch/s390/include/asm/s390_ext.h b/arch/s390/include/asm/s390_ext.h
new file mode 100644
index 000000000000..2afc060266a2
--- /dev/null
+++ b/arch/s390/include/asm/s390_ext.h
@@ -0,0 +1,32 @@
+#ifndef _S390_EXTINT_H
+#define _S390_EXTINT_H
+
+/*
+ *  include/asm-s390/s390_ext.h
+ *
+ *  S390 version
+ *    Copyright IBM Corp. 1999,2007
+ *    Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com),
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ */
+
+#include <linux/types.h>
+
+typedef void (*ext_int_handler_t)(__u16 code);
+
+typedef struct ext_int_info_t {
+        struct ext_int_info_t *next;
+        ext_int_handler_t handler;
+        __u16 code;
+} ext_int_info_t;
+
+extern ext_int_info_t *ext_int_hash[];
+
+int register_external_interrupt(__u16 code, ext_int_handler_t handler);
+int register_early_external_interrupt(__u16 code, ext_int_handler_t handler,
+                                      ext_int_info_t *info);
+int unregister_external_interrupt(__u16 code, ext_int_handler_t handler);
+int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler,
+                                        ext_int_info_t *info);
+
+#endif
diff --git a/arch/s390/include/asm/s390_rdev.h b/arch/s390/include/asm/s390_rdev.h
new file mode 100644
index 000000000000..6fa20442a48c
--- /dev/null
+++ b/arch/s390/include/asm/s390_rdev.h
@@ -0,0 +1,15 @@
+/*
+ *  include/asm-s390/ccwdev.h
+ *
+ *    Copyright (C) 2002,2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
+ *               Carsten Otte  <cotte@de.ibm.com>
+ *
+ *  Interface for s390 root device
+ */
+
+#ifndef _S390_RDEV_H_
+#define _S390_RDEV_H_
+extern struct device *s390_root_dev_register(const char *);
+extern void s390_root_dev_unregister(struct device *);
+#endif /* _S390_RDEV_H_ */
diff --git a/arch/s390/include/asm/scatterlist.h b/arch/s390/include/asm/scatterlist.h
new file mode 100644
index 000000000000..29ec8e28c8df
--- /dev/null
+++ b/arch/s390/include/asm/scatterlist.h
@@ -0,0 +1,19 @@
+#ifndef _ASMS390_SCATTERLIST_H
+#define _ASMS390_SCATTERLIST_H
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+    unsigned long sg_magic;
+#endif
+    unsigned long page_link;
+    unsigned int offset;
+    unsigned int length;
+};
+
+#ifdef __s390x__
+#define ISA_DMA_THRESHOLD (0xffffffffffffffffUL)
+#else
+#define ISA_DMA_THRESHOLD (0xffffffffUL)
+#endif
+
+#endif /* _ASMS390X_SCATTERLIST_H */
diff --git a/arch/s390/include/asm/schid.h b/arch/s390/include/asm/schid.h
new file mode 100644
index 000000000000..825503cf3dc2
--- /dev/null
+++ b/arch/s390/include/asm/schid.h
@@ -0,0 +1,32 @@
+#ifndef ASM_SCHID_H
+#define ASM_SCHID_H
+
+struct subchannel_id {
+        __u32 cssid : 8;
+        __u32 : 4;
+        __u32 m : 1;
+        __u32 ssid : 2;
+        __u32 one : 1;
+        __u32 sch_no : 16;
+} __attribute__ ((packed, aligned(4)));
+
+#ifdef __KERNEL__
+#include <linux/string.h>
+
+/* Helper function for sane state of pre-allocated subchannel_id. */
+static inline void
+init_subchannel_id(struct subchannel_id *schid)
+{
+        memset(schid, 0, sizeof(struct subchannel_id));
+        schid->one = 1;
+}
+
+static inline int
+schid_equal(struct subchannel_id *schid1, struct subchannel_id *schid2)
+{
+        return !memcmp(schid1, schid2, sizeof(struct subchannel_id));
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* ASM_SCHID_H */
diff --git a/arch/s390/include/asm/sclp.h b/arch/s390/include/asm/sclp.h
new file mode 100644
index 000000000000..fed7bee650a0
--- /dev/null
+++ b/arch/s390/include/asm/sclp.h
@@ -0,0 +1,58 @@
+/*
+ *  include/asm-s390/sclp.h
+ *
+ *    Copyright IBM Corp. 2007
+ *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_SCLP_H
+#define _ASM_S390_SCLP_H
+
+#include <linux/types.h>
+#include <asm/chpid.h>
+
+#define SCLP_CHP_INFO_MASK_SIZE         32
+
+struct sclp_chp_info {
+        u8 recognized[SCLP_CHP_INFO_MASK_SIZE];
+        u8 standby[SCLP_CHP_INFO_MASK_SIZE];
+        u8 configured[SCLP_CHP_INFO_MASK_SIZE];
+};
+
+#define LOADPARM_LEN 8
+
+struct sclp_ipl_info {
+        int is_valid;
+        int has_dump;
+        char loadparm[LOADPARM_LEN];
+};
+
+struct sclp_cpu_entry {
+        u8 address;
+        u8 reserved0[13];
+        u8 type;
+        u8 reserved1;
+} __attribute__((packed));
+
+struct sclp_cpu_info {
+        unsigned int configured;
+        unsigned int standby;
+        unsigned int combined;
+        int has_cpu_type;
+        struct sclp_cpu_entry cpu[255];
+};
+
+int sclp_get_cpu_info(struct sclp_cpu_info *info);
+int sclp_cpu_configure(u8 cpu);
+int sclp_cpu_deconfigure(u8 cpu);
+void sclp_facilities_detect(void);
+unsigned long long sclp_get_rnmax(void);
+unsigned long long sclp_get_rzm(void);
+int sclp_sdias_blk_count(void);
+int sclp_sdias_copy(void *dest, int blk_num, int nr_blks);
+int sclp_chp_configure(struct chp_id chpid);
+int sclp_chp_deconfigure(struct chp_id chpid);
+int sclp_chp_read_info(struct sclp_chp_info *info);
+void sclp_get_ipl_info(struct sclp_ipl_info *info);
+
+#endif /* _ASM_S390_SCLP_H */
diff --git a/arch/s390/include/asm/sections.h b/arch/s390/include/asm/sections.h
new file mode 100644
index 000000000000..fbd9116eb17b
--- /dev/null
+++ b/arch/s390/include/asm/sections.h
@@ -0,0 +1,8 @@
+#ifndef _S390_SECTIONS_H
+#define _S390_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern char _eshared[], _ehead[];
+
+#endif
diff --git a/arch/s390/include/asm/segment.h b/arch/s390/include/asm/segment.h
new file mode 100644
index 000000000000..8bfce3475b1c
--- /dev/null
+++ b/arch/s390/include/asm/segment.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_SEGMENT_H
+#define _ASM_SEGMENT_H
+
+#endif
diff --git a/arch/s390/include/asm/sembuf.h b/arch/s390/include/asm/sembuf.h
new file mode 100644
index 000000000000..32626b0cac4b
--- /dev/null
+++ b/arch/s390/include/asm/sembuf.h
@@ -0,0 +1,29 @@
+#ifndef _S390_SEMBUF_H
+#define _S390_SEMBUF_H
+
+/* 
+ * The semid64_ds structure for S/390 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem (for !__s390x__)
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+#ifndef __s390x__
+        unsigned long   __unused1;
+#endif /* ! __s390x__ */
+        __kernel_time_t sem_ctime;              /* last change time */
+#ifndef __s390x__
+        unsigned long   __unused2;
+#endif /* ! __s390x__ */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _S390_SEMBUF_H */
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
new file mode 100644
index 000000000000..2bd9faeb3919
--- /dev/null
+++ b/arch/s390/include/asm/setup.h
@@ -0,0 +1,140 @@
+/*
+ *  include/asm-s390/setup.h
+ *
+ *  S390 version
+ *    Copyright IBM Corp. 1999,2006
+ */
+
+#ifndef _ASM_S390_SETUP_H
+#define _ASM_S390_SETUP_H
+
+#define COMMAND_LINE_SIZE       1024
+
+#define ARCH_COMMAND_LINE_SIZE  896
+
+#ifdef __KERNEL__
+
+#include <asm/types.h>
+
+#define PARMAREA                0x10400
+#define MEMORY_CHUNKS           256
+
+#ifndef __ASSEMBLY__
+
+#ifndef __s390x__
+#define IPL_DEVICE        (*(unsigned long *)  (0x10404))
+#define INITRD_START      (*(unsigned long *)  (0x1040C))
+#define INITRD_SIZE       (*(unsigned long *)  (0x10414))
+#else /* __s390x__ */
+#define IPL_DEVICE        (*(unsigned long *)  (0x10400))
+#define INITRD_START      (*(unsigned long *)  (0x10408))
+#define INITRD_SIZE       (*(unsigned long *)  (0x10410))
+#endif /* __s390x__ */
+#define COMMAND_LINE      ((char *)            (0x10480))
+
+#define CHUNK_READ_WRITE 0
+#define CHUNK_READ_ONLY  1
+
+struct mem_chunk {
+        unsigned long addr;
+        unsigned long size;
+        int type;
+};
+
+extern struct mem_chunk memory_chunk[];
+extern unsigned long real_memory_size;
+
+void detect_memory_layout(struct mem_chunk chunk[]);
+
+#ifdef CONFIG_S390_SWITCH_AMODE
+extern unsigned int switch_amode;
+#else
+#define switch_amode    (0)
+#endif
+
+#ifdef CONFIG_S390_EXEC_PROTECT
+extern unsigned int s390_noexec;
+#else
+#define s390_noexec     (0)
+#endif
+
+/*
+ * Machine features detected in head.S
+ */
+extern unsigned long machine_flags;
+
+#define MACHINE_FLAG_VM         (1UL << 0)
+#define MACHINE_FLAG_IEEE       (1UL << 1)
+#define MACHINE_FLAG_CSP        (1UL << 3)
+#define MACHINE_FLAG_MVPG       (1UL << 4)
+#define MACHINE_FLAG_DIAG44     (1UL << 5)
+#define MACHINE_FLAG_IDTE       (1UL << 6)
+#define MACHINE_FLAG_DIAG9C     (1UL << 7)
+#define MACHINE_FLAG_MVCOS      (1UL << 8)
+#define MACHINE_FLAG_KVM        (1UL << 9)
+#define MACHINE_FLAG_HPAGE      (1UL << 10)
+#define MACHINE_FLAG_PFMF       (1UL << 11)
+
+#define MACHINE_IS_VM           (machine_flags & MACHINE_FLAG_VM)
+#define MACHINE_IS_KVM          (machine_flags & MACHINE_FLAG_KVM)
+#define MACHINE_HAS_DIAG9C      (machine_flags & MACHINE_FLAG_DIAG9C)
+
+#ifndef __s390x__
+#define MACHINE_HAS_IEEE        (machine_flags & MACHINE_FLAG_IEEE)
+#define MACHINE_HAS_CSP         (machine_flags & MACHINE_FLAG_CSP)
+#define MACHINE_HAS_IDTE        (0)
+#define MACHINE_HAS_DIAG44      (1)
+#define MACHINE_HAS_MVPG        (machine_flags & MACHINE_FLAG_MVPG)
+#define MACHINE_HAS_MVCOS       (0)
+#define MACHINE_HAS_HPAGE       (0)
+#define MACHINE_HAS_PFMF        (0)
+#else /* __s390x__ */
+#define MACHINE_HAS_IEEE        (1)
+#define MACHINE_HAS_CSP         (1)
+#define MACHINE_HAS_IDTE        (machine_flags & MACHINE_FLAG_IDTE)
+#define MACHINE_HAS_DIAG44      (machine_flags & MACHINE_FLAG_DIAG44)
+#define MACHINE_HAS_MVPG        (1)
+#define MACHINE_HAS_MVCOS       (machine_flags & MACHINE_FLAG_MVCOS)
+#define MACHINE_HAS_HPAGE       (machine_flags & MACHINE_FLAG_HPAGE)
+#define MACHINE_HAS_PFMF        (machine_flags & MACHINE_FLAG_PFMF)
+#endif /* __s390x__ */
+
+#define ZFCPDUMP_HSA_SIZE       (32UL<<20)
+
+/*
+ * Console mode. Override with conmode=
+ */
+extern unsigned int console_mode;
+extern unsigned int console_devno;
+extern unsigned int console_irq;
+
+extern char vmhalt_cmd[];
+extern char vmpoff_cmd[];
+
+#define CONSOLE_IS_UNDEFINED    (console_mode == 0)
+#define CONSOLE_IS_SCLP         (console_mode == 1)
+#define CONSOLE_IS_3215         (console_mode == 2)
+#define CONSOLE_IS_3270         (console_mode == 3)
+#define SET_CONSOLE_SCLP        do { console_mode = 1; } while (0)
+#define SET_CONSOLE_3215        do { console_mode = 2; } while (0)
+#define SET_CONSOLE_3270        do { console_mode = 3; } while (0)
+
+#define NSS_NAME_SIZE   8
+extern char kernel_nss_name[];
+
+#else /* __ASSEMBLY__ */
+
+#ifndef __s390x__
+#define IPL_DEVICE        0x10404
+#define INITRD_START      0x1040C
+#define INITRD_SIZE       0x10414
+#else /* __s390x__ */
+#define IPL_DEVICE        0x10400
+#define INITRD_START      0x10408
+#define INITRD_SIZE       0x10410
+#endif /* __s390x__ */
+#define COMMAND_LINE      0x10480
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_S390_SETUP_H */
diff --git a/arch/s390/include/asm/sfp-machine.h b/arch/s390/include/asm/sfp-machine.h
new file mode 100644
index 000000000000..4e16aede4b06
--- /dev/null
+++ b/arch/s390/include/asm/sfp-machine.h
@@ -0,0 +1,142 @@
+/* Machine-dependent software floating-point definitions.
+   S/390 kernel version.
+   Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Richard Henderson (rth@cygnus.com),
+                  Jakub Jelinek (jj@ultra.linux.cz),
+                  David S. Miller (davem@redhat.com) and
+                  Peter Maydell (pmaydell@chiark.greenend.org.uk).
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If
+   not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _SFP_MACHINE_H
+#define _SFP_MACHINE_H
+   
+
+#define _FP_W_TYPE_SIZE         32
+#define _FP_W_TYPE              unsigned int
+#define _FP_WS_TYPE             signed int
+#define _FP_I_TYPE              int
+
+#define _FP_MUL_MEAT_S(R,X,Y)                                   \
+  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y)                                   \
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y)                                   \
+  _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_udiv(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S           ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D           ((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q           ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S           0
+#define _FP_NANSIGN_D           0
+#define _FP_NANSIGN_Q           0
+
+#define _FP_KEEPNANFRACP 1
+
+/*
+ * If one NaN is signaling and the other is not,
+ * we choose that one, otherwise we choose X.
+ */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
+  do {                                                          \
+    if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)          \
+        && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs))     \
+      {                                                         \
+        R##_s = Y##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,Y);                                \
+      }                                                         \
+    else                                                        \
+      {                                                         \
+        R##_s = X##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,X);                                \
+      }                                                         \
+    R##_c = FP_CLS_NAN;                                         \
+  } while (0)
+
+/* Some assembly to speed things up. */
+#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({          \
+        unsigned int __r2 = (x2) + (y2);                        \
+        unsigned int __r1 = (x1);                               \
+        unsigned int __r0 = (x0);                               \
+        asm volatile(                                           \
+                "       alr     %2,%3\n"                        \
+                "       brc     12,0f\n"                        \
+                "       lhi     0,1\n"                          \
+                "       alr     %1,0\n"                         \
+                "       brc     12,0f\n"                        \
+                "       alr     %0,0\n"                         \
+                "0:"                                            \
+                : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0)      \
+                : "d" (y0), "i" (1) : "cc", "0" );              \
+        asm volatile(                                           \
+                "       alr     %1,%2\n"                        \
+                "       brc     12,0f\n"                        \
+                "       ahi     %0,1\n"                         \
+                "0:"                                            \
+                : "+&d" (__r2), "+&d" (__r1)                    \
+                : "d" (y1) : "cc");                             \
+        (r2) = __r2;                                            \
+        (r1) = __r1;                                            \
+        (r0) = __r0;                                            \
+})
+
+#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) ({          \
+        unsigned int __r2 = (x2) - (y2);                        \
+        unsigned int __r1 = (x1);                               \
+        unsigned int __r0 = (x0);                               \
+        asm volatile(                                           \
+                "       slr   %2,%3\n"                          \
+                "       brc     3,0f\n"                         \
+                "       lhi     0,1\n"                          \
+                "       slr     %1,0\n"                         \
+                "       brc     3,0f\n"                         \
+                "       slr     %0,0\n"                         \
+                "0:"                                            \
+                : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0)      \
+                : "d" (y0) : "cc", "0");                        \
+        asm volatile(                                           \
+                "       slr     %1,%2\n"                        \
+                "       brc     3,0f\n"                         \
+                "       ahi     %0,-1\n"                        \
+                "0:"                                            \
+                : "+&d" (__r2), "+&d" (__r1)                    \
+                : "d" (y1) : "cc");                             \
+        (r2) = __r2;                                            \
+        (r1) = __r1;                                            \
+        (r0) = __r0;                                            \
+})
+
+#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
+
+/* Obtain the current rounding mode. */
+#define FP_ROUNDMODE    mode
+
+/* Exception flags. */
+#define FP_EX_INVALID           0x800000
+#define FP_EX_DIVZERO           0x400000
+#define FP_EX_OVERFLOW          0x200000
+#define FP_EX_UNDERFLOW         0x100000
+#define FP_EX_INEXACT           0x080000
+
+/* We write the results always */
+#define FP_INHIBIT_RESULTS 0
+
+#endif
diff --git a/arch/s390/include/asm/sfp-util.h b/arch/s390/include/asm/sfp-util.h
new file mode 100644
index 000000000000..0addc6466d95
--- /dev/null
+++ b/arch/s390/include/asm/sfp-util.h
@@ -0,0 +1,77 @@
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) ({           \
+        unsigned int __sh = (ah);                       \
+        unsigned int __sl = (al);                       \
+        asm volatile(                                   \
+                "       alr     %1,%3\n"                \
+                "       brc     12,0f\n"                \
+                "       ahi     %0,1\n"                 \
+                "0:     alr  %0,%2"                     \
+                : "+&d" (__sh), "+d" (__sl)             \
+                : "d" (bh), "d" (bl) : "cc");           \
+        (sh) = __sh;                                    \
+        (sl) = __sl;                                    \
+})
+
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) ({           \
+        unsigned int __sh = (ah);                       \
+        unsigned int __sl = (al);                       \
+        asm volatile(                                   \
+                "       slr     %1,%3\n"                \
+                "       brc     3,0f\n"                 \
+                "       ahi     %0,-1\n"                \
+                "0:     slr     %0,%2"                  \
+                : "+&d" (__sh), "+d" (__sl)             \
+                : "d" (bh), "d" (bl) : "cc");           \
+        (sh) = __sh;                                    \
+        (sl) = __sl;                                    \
+})
+
+/* a umul b = a mul b + (a>=2<<31) ? b<<32:0 + (b>=2<<31) ? a<<32:0 */
+#define umul_ppmm(wh, wl, u, v) ({                      \
+        unsigned int __wh = u;                          \
+        unsigned int __wl = v;                          \
+        asm volatile(                                   \
+                "       ltr     1,%0\n"                 \
+                "       mr      0,%1\n"                 \
+                "       jnm     0f\n"                           \
+                "       alr     0,%1\n"                 \
+                "0:     ltr     %1,%1\n"                        \
+                "       jnm     1f\n"                           \
+                "       alr     0,%0\n"                 \
+                "1:     lr      %0,0\n"                 \
+                "       lr      %1,1\n"                 \
+                : "+d" (__wh), "+d" (__wl)              \
+                : : "0", "1", "cc");                    \
+        wh = __wh;                                      \
+        wl = __wl;                                      \
+})
+
+#ifdef __s390x__
+#define udiv_qrnnd(q, r, n1, n0, d)                     \
+  do { unsigned long __n;                               \
+       unsigned int __r, __d;                           \
+    __n = ((unsigned long)(n1) << 32) + n0;             \
+    __d = (d);                                          \
+    (q) = __n / __d;                                    \
+    (r) = __n % __d;                                    \
+  } while (0)
+#else
+#define udiv_qrnnd(q, r, n1, n0, d)                     \
+  do { unsigned int __r;                                \
+    (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));         \
+    (r) = __r;                                          \
+  } while (0)
+extern unsigned long __udiv_qrnnd (unsigned int *, unsigned int,
+                                   unsigned int , unsigned int);
+#endif
+
+#define UDIV_NEEDS_NORMALIZATION 0
+
+#define abort() return 0
+
+#define __BYTE_ORDER __BIG_ENDIAN
diff --git a/arch/s390/include/asm/shmbuf.h b/arch/s390/include/asm/shmbuf.h
new file mode 100644
index 000000000000..eed2e280ce37
--- /dev/null
+++ b/arch/s390/include/asm/shmbuf.h
@@ -0,0 +1,48 @@
+#ifndef _S390_SHMBUF_H
+#define _S390_SHMBUF_H
+
+/* 
+ * The shmid64_ds structure for S/390 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem (for !__s390x__)
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+#ifndef __s390x__
+        unsigned long           __unused1;
+#endif /* ! __s390x__ */
+        __kernel_time_t         shm_dtime;      /* last detach time */
+#ifndef __s390x__
+        unsigned long           __unused2;
+#endif /* ! __s390x__ */
+        __kernel_time_t         shm_ctime;      /* last change time */
+#ifndef __s390x__
+        unsigned long           __unused3;
+#endif /* ! __s390x__ */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused4;
+        unsigned long           __unused5;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _S390_SHMBUF_H */
diff --git a/arch/s390/include/asm/shmparam.h b/arch/s390/include/asm/shmparam.h
new file mode 100644
index 000000000000..c2e0c0508e73
--- /dev/null
+++ b/arch/s390/include/asm/shmparam.h
@@ -0,0 +1,13 @@
+/*
+ *  include/asm-s390/shmparam.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/shmparam.h"
+ */
+#ifndef _ASM_S390_SHMPARAM_H
+#define _ASM_S390_SHMPARAM_H
+
+#define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
+
+#endif /* _ASM_S390_SHMPARAM_H */
diff --git a/arch/s390/include/asm/sigcontext.h b/arch/s390/include/asm/sigcontext.h
new file mode 100644
index 000000000000..aeb6e0b13329
--- /dev/null
+++ b/arch/s390/include/asm/sigcontext.h
@@ -0,0 +1,71 @@
+/*
+ *  include/asm-s390/sigcontext.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ */
+
+#ifndef _ASM_S390_SIGCONTEXT_H
+#define _ASM_S390_SIGCONTEXT_H
+
+#include <linux/compiler.h>
+
+#define __NUM_GPRS 16
+#define __NUM_FPRS 16
+#define __NUM_ACRS 16
+
+#ifndef __s390x__
+
+/* Has to be at least _NSIG_WORDS from asm/signal.h */
+#define _SIGCONTEXT_NSIG        64
+#define _SIGCONTEXT_NSIG_BPW    32
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE      96
+
+#else /* __s390x__ */
+
+/* Has to be at least _NSIG_WORDS from asm/signal.h */
+#define _SIGCONTEXT_NSIG        64
+#define _SIGCONTEXT_NSIG_BPW    64 
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE      160
+
+#endif /* __s390x__ */
+
+#define _SIGCONTEXT_NSIG_WORDS  (_SIGCONTEXT_NSIG / _SIGCONTEXT_NSIG_BPW)
+#define _SIGMASK_COPY_SIZE      (sizeof(unsigned long)*_SIGCONTEXT_NSIG_WORDS)
+
+typedef struct 
+{
+        unsigned long mask;
+        unsigned long addr;
+} __attribute__ ((aligned(8))) _psw_t;
+
+typedef struct
+{
+        _psw_t psw;
+        unsigned long gprs[__NUM_GPRS];
+        unsigned int  acrs[__NUM_ACRS];
+} _s390_regs_common;
+
+typedef struct
+{
+        unsigned int fpc;
+        double   fprs[__NUM_FPRS];
+} _s390_fp_regs;
+
+typedef struct
+{
+        _s390_regs_common regs;
+        _s390_fp_regs     fpregs;
+} _sigregs;
+
+struct sigcontext
+{
+        unsigned long   oldmask[_SIGCONTEXT_NSIG_WORDS];
+        _sigregs        __user *sregs;
+};
+
+
+#endif
+
diff --git a/arch/s390/include/asm/siginfo.h b/arch/s390/include/asm/siginfo.h
new file mode 100644
index 000000000000..e0ff1ab054be
--- /dev/null
+++ b/arch/s390/include/asm/siginfo.h
@@ -0,0 +1,18 @@
+/*
+ *  include/asm-s390/siginfo.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/siginfo.h"
+ */
+
+#ifndef _S390_SIGINFO_H
+#define _S390_SIGINFO_H
+
+#ifdef __s390x__
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#endif
+
+#include <asm-generic/siginfo.h>
+
+#endif
diff --git a/arch/s390/include/asm/signal.h b/arch/s390/include/asm/signal.h
new file mode 100644
index 000000000000..f6cfddb278cb
--- /dev/null
+++ b/arch/s390/include/asm/signal.h
@@ -0,0 +1,172 @@
+/*
+ *  include/asm-s390/signal.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/signal.h"
+ */
+
+#ifndef _ASMS390_SIGNAL_H
+#define _ASMS390_SIGNAL_H
+
+#include <linux/types.h>
+#include <linux/time.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+struct pt_regs;
+
+#ifdef __KERNEL__
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+#include <asm/sigcontext.h>
+#define _NSIG           _SIGCONTEXT_NSIG
+#define _NSIG_BPW       _SIGCONTEXT_NSIG_BPW
+#define _NSIG_WORDS     _SIGCONTEXT_NSIG_WORDS
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+#define NSIG            32
+typedef unsigned long sigset_t;
+
+#endif /* __KERNEL__ */
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002
+#define SA_SIGINFO      0x00000004
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#include <asm-generic/signal.h>
+
+#ifdef __KERNEL__
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+struct sigaction {
+        union {
+          __sighandler_t _sa_handler;
+          void (*_sa_sigaction)(int, struct siginfo *, void *);
+        } _u;
+#ifndef __s390x__ /* lovely */
+        sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+#else  /* __s390x__ */
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+        sigset_t sa_mask;
+#endif /* __s390x__ */
+};
+
+#define sa_handler      _u._sa_handler
+#define sa_sigaction    _u._sa_sigaction
+
+#endif /* __KERNEL__ */
+
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+
+#endif
diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h
new file mode 100644
index 000000000000..e16d56f8dfe1
--- /dev/null
+++ b/arch/s390/include/asm/sigp.h
@@ -0,0 +1,126 @@
+/*
+ *  include/asm-s390/sigp.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *               Heiko Carstens (heiko.carstens@de.ibm.com)
+ *
+ *  sigp.h by D.J. Barrow (c) IBM 1999
+ *  contains routines / structures for signalling other S/390 processors in an
+ *  SMP configuration.
+ */
+
+#ifndef __SIGP__
+#define __SIGP__
+
+#include <asm/ptrace.h>
+#include <asm/atomic.h>
+
+/* get real cpu address from logical cpu number */
+extern volatile int __cpu_logical_map[];
+
+typedef enum
+{
+        sigp_unassigned=0x0,
+        sigp_sense,
+        sigp_external_call,
+        sigp_emergency_signal,
+        sigp_start,
+        sigp_stop,
+        sigp_restart,
+        sigp_unassigned1,
+        sigp_unassigned2,
+        sigp_stop_and_store_status,
+        sigp_unassigned3,
+        sigp_initial_cpu_reset,
+        sigp_cpu_reset,
+        sigp_set_prefix,
+        sigp_store_status_at_address,
+        sigp_store_extended_status_at_address
+} sigp_order_code;
+
+typedef __u32 sigp_status_word;
+
+typedef enum
+{
+        sigp_order_code_accepted=0,
+        sigp_status_stored,
+        sigp_busy,
+        sigp_not_operational
+} sigp_ccode;
+
+
+/*
+ * Definitions for the external call
+ */
+
+/* 'Bit' signals, asynchronous */
+typedef enum
+{
+        ec_schedule=0,
+        ec_call_function,
+        ec_bit_last
+} ec_bit_sig;
+
+/*
+ * Signal processor
+ */
+static inline sigp_ccode
+signal_processor(__u16 cpu_addr, sigp_order_code order_code)
+{
+        register unsigned long reg1 asm ("1") = 0;
+        sigp_ccode ccode;
+
+        asm volatile(
+                "       sigp    %1,%2,0(%3)\n"
+                "       ipm     %0\n"
+                "       srl     %0,28\n"
+                :       "=d"    (ccode)
+                : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
+                  "a" (order_code) : "cc" , "memory");
+        return ccode;
+}
+
+/*
+ * Signal processor with parameter
+ */
+static inline sigp_ccode
+signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code)
+{
+        register unsigned int reg1 asm ("1") = parameter;
+        sigp_ccode ccode;
+
+        asm volatile(
+                "       sigp    %1,%2,0(%3)\n"
+                "       ipm     %0\n"
+                "       srl     %0,28\n"
+                : "=d" (ccode)
+                : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]),
+                  "a" (order_code) : "cc" , "memory");
+        return ccode;
+}
+
+/*
+ * Signal processor with parameter and return status
+ */
+static inline sigp_ccode
+signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr,
+                    sigp_order_code order_code)
+{
+        register unsigned int reg1 asm ("1") = parameter;
+        sigp_ccode ccode;
+
+        asm volatile(
+                "       sigp    %1,%2,0(%3)\n"
+                "       ipm     %0\n"
+                "       srl     %0,28\n"
+                : "=d" (ccode), "+d" (reg1)
+                : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code)
+                : "cc" , "memory");
+        *statusptr = reg1;
+        return ccode;
+}
+
+#endif /* __SIGP__ */
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
new file mode 100644
index 000000000000..ae89cf2478fc
--- /dev/null
+++ b/arch/s390/include/asm/smp.h
@@ -0,0 +1,116 @@
+/*
+ *  include/asm-s390/smp.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *               Heiko Carstens (heiko.carstens@de.ibm.com)
+ */
+#ifndef __ASM_SMP_H
+#define __ASM_SMP_H
+
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/bitops.h>
+
+#if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
+
+#include <asm/lowcore.h>
+#include <asm/sigp.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+
+/*
+  s390 specific smp.c headers
+ */
+typedef struct
+{
+        int        intresting;
+        sigp_ccode ccode; 
+        __u32      status;
+        __u16      cpu;
+} sigp_info;
+
+extern void machine_restart_smp(char *);
+extern void machine_halt_smp(void);
+extern void machine_power_off_smp(void);
+
+#define NO_PROC_ID              0xFF            /* No processor magic marker */
+
+/*
+ *      This magic constant controls our willingness to transfer
+ *      a process across CPUs. Such a transfer incurs misses on the L1
+ *      cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
+ *      gut feeling is this will vary by board in value. For a board
+ *      with separate L2 cache it probably depends also on the RSS, and
+ *      for a board with shared L2 cache it ought to decay fast as other
+ *      processes are run.
+ */
+ 
+#define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
+
+#define raw_smp_processor_id()  (S390_lowcore.cpu_data.cpu_nr)
+
+static inline __u16 hard_smp_processor_id(void)
+{
+        return stap();
+}
+
+/*
+ * returns 1 if cpu is in stopped/check stopped state or not operational
+ * returns 0 otherwise
+ */
+static inline int
+smp_cpu_not_running(int cpu)
+{
+        __u32 status;
+
+        switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
+        case sigp_order_code_accepted:
+        case sigp_status_stored:
+                /* Check for stopped and check stop state */
+                if (status & 0x50)
+                        return 1;
+                break;
+        case sigp_not_operational:
+                return 1;
+        default:
+                break;
+        }
+        return 0;
+}
+
+#define cpu_logical_map(cpu) (cpu)
+
+extern int __cpu_disable (void);
+extern void __cpu_die (unsigned int cpu);
+extern void cpu_die (void) __attribute__ ((noreturn));
+extern int __cpu_up (unsigned int cpu);
+
+extern struct mutex smp_cpu_state_mutex;
+extern int smp_cpu_polarization[];
+
+extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
+        void *info, int wait);
+#endif
+
+#ifndef CONFIG_SMP
+static inline void smp_send_stop(void)
+{
+        /* Disable all interrupts/machine checks */
+        __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
+}
+
+#define hard_smp_processor_id()         0
+#define smp_cpu_not_running(cpu)        1
+#endif
+
+#ifdef CONFIG_HOTPLUG_CPU
+extern int smp_rescan_cpus(void);
+#else
+static inline int smp_rescan_cpus(void) { return 0; }
+#endif
+
+extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
+#endif
diff --git a/arch/s390/include/asm/socket.h b/arch/s390/include/asm/socket.h
new file mode 100644
index 000000000000..c786ab623b2d
--- /dev/null
+++ b/arch/s390/include/asm/socket.h
@@ -0,0 +1,65 @@
+/*
+ *  include/asm-s390/socket.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/socket.h"
+ */
+
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC              31
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#endif /* _ASM_SOCKET_H */
diff --git a/arch/s390/include/asm/sockios.h b/arch/s390/include/asm/sockios.h
new file mode 100644
index 000000000000..f4fc16c7da59
--- /dev/null
+++ b/arch/s390/include/asm/sockios.h
@@ -0,0 +1,21 @@
+/*
+ *  include/asm-s390/sockios.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/sockios.h"
+ */
+
+#ifndef __ARCH_S390_SOCKIOS__
+#define __ARCH_S390_SOCKIOS__
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif
diff --git a/arch/s390/include/asm/sparsemem.h b/arch/s390/include/asm/sparsemem.h
new file mode 100644
index 000000000000..545d219e6a2d
--- /dev/null
+++ b/arch/s390/include/asm/sparsemem.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_S390_SPARSEMEM_H
+#define _ASM_S390_SPARSEMEM_H
+
+#ifdef CONFIG_64BIT
+
+#define SECTION_SIZE_BITS       28
+#define MAX_PHYSADDR_BITS       42
+#define MAX_PHYSMEM_BITS        42
+
+#else
+
+#define SECTION_SIZE_BITS       25
+#define MAX_PHYSADDR_BITS       31
+#define MAX_PHYSMEM_BITS        31
+
+#endif /* CONFIG_64BIT */
+
+#endif /* _ASM_S390_SPARSEMEM_H */
diff --git a/arch/s390/include/asm/spinlock.h b/arch/s390/include/asm/spinlock.h
new file mode 100644
index 000000000000..df84ae96915f
--- /dev/null
+++ b/arch/s390/include/asm/spinlock.h
@@ -0,0 +1,178 @@
+/*
+ *  include/asm-s390/spinlock.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/spinlock.h"
+ */
+
+#ifndef __ASM_SPINLOCK_H
+#define __ASM_SPINLOCK_H
+
+#include <linux/smp.h>
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+
+static inline int
+_raw_compare_and_swap(volatile unsigned int *lock,
+                      unsigned int old, unsigned int new)
+{
+        asm volatile(
+                "       cs      %0,%3,%1"
+                : "=d" (old), "=Q" (*lock)
+                : "0" (old), "d" (new), "Q" (*lock)
+                : "cc", "memory" );
+        return old;
+}
+
+#else /* __GNUC__ */
+
+static inline int
+_raw_compare_and_swap(volatile unsigned int *lock,
+                      unsigned int old, unsigned int new)
+{
+        asm volatile(
+                "       cs      %0,%3,0(%4)"
+                : "=d" (old), "=m" (*lock)
+                : "0" (old), "d" (new), "a" (lock), "m" (*lock)
+                : "cc", "memory" );
+        return old;
+}
+
+#endif /* __GNUC__ */
+
+/*
+ * Simple spin lock operations.  There are two variants, one clears IRQ's
+ * on the local processor, one does not.
+ *
+ * We make no fairness assumptions. They have a cost.
+ *
+ * (the type definitions are in asm/spinlock_types.h)
+ */
+
+#define __raw_spin_is_locked(x) ((x)->owner_cpu != 0)
+#define __raw_spin_unlock_wait(lock) \
+        do { while (__raw_spin_is_locked(lock)) \
+                 _raw_spin_relax(lock); } while (0)
+
+extern void _raw_spin_lock_wait(raw_spinlock_t *);
+extern void _raw_spin_lock_wait_flags(raw_spinlock_t *, unsigned long flags);
+extern int _raw_spin_trylock_retry(raw_spinlock_t *);
+extern void _raw_spin_relax(raw_spinlock_t *lock);
+
+static inline void __raw_spin_lock(raw_spinlock_t *lp)
+{
+        int old;
+
+        old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
+        if (likely(old == 0))
+                return;
+        _raw_spin_lock_wait(lp);
+}
+
+static inline void __raw_spin_lock_flags(raw_spinlock_t *lp,
+                                         unsigned long flags)
+{
+        int old;
+
+        old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
+        if (likely(old == 0))
+                return;
+        _raw_spin_lock_wait_flags(lp, flags);
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lp)
+{
+        int old;
+
+        old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
+        if (likely(old == 0))
+                return 1;
+        return _raw_spin_trylock_retry(lp);
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lp)
+{
+        _raw_compare_and_swap(&lp->owner_cpu, lp->owner_cpu, 0);
+}
+                
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_read_can_lock(x) ((int)(x)->lock >= 0)
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_write_can_lock(x) ((x)->lock == 0)
+
+extern void _raw_read_lock_wait(raw_rwlock_t *lp);
+extern int _raw_read_trylock_retry(raw_rwlock_t *lp);
+extern void _raw_write_lock_wait(raw_rwlock_t *lp);
+extern int _raw_write_trylock_retry(raw_rwlock_t *lp);
+
+static inline void __raw_read_lock(raw_rwlock_t *rw)
+{
+        unsigned int old;
+        old = rw->lock & 0x7fffffffU;
+        if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old)
+                _raw_read_lock_wait(rw);
+}
+
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
+{
+        unsigned int old, cmp;
+
+        old = rw->lock;
+        do {
+                cmp = old;
+                old = _raw_compare_and_swap(&rw->lock, old, old - 1);
+        } while (cmp != old);
+}
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+        if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0))
+                _raw_write_lock_wait(rw);
+}
+
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+        _raw_compare_and_swap(&rw->lock, 0x80000000, 0);
+}
+
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+        unsigned int old;
+        old = rw->lock & 0x7fffffffU;
+        if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old))
+                return 1;
+        return _raw_read_trylock_retry(rw);
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+        if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0))
+                return 1;
+        return _raw_write_trylock_retry(rw);
+}
+
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#endif /* __ASM_SPINLOCK_H */
diff --git a/arch/s390/include/asm/spinlock_types.h b/arch/s390/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..654abc40de04
--- /dev/null
+++ b/arch/s390/include/asm/spinlock_types.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_SPINLOCK_TYPES_H
+#define __ASM_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        volatile unsigned int owner_cpu;
+} __attribute__ ((aligned (4))) raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_rwlock_t;
+
+#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+
+#endif
diff --git a/arch/s390/include/asm/stat.h b/arch/s390/include/asm/stat.h
new file mode 100644
index 000000000000..d92959eebb65
--- /dev/null
+++ b/arch/s390/include/asm/stat.h
@@ -0,0 +1,105 @@
+/*
+ *  include/asm-s390/stat.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/stat.h"
+ */
+
+#ifndef _S390_STAT_H
+#define _S390_STAT_H
+
+#ifndef __s390x__
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+struct stat {
+        unsigned short st_dev;
+        unsigned short __pad1;
+        unsigned long  st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned short __pad2;
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+        unsigned long long      st_dev;
+        unsigned int    __pad1;
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long   __st_ino;
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+        unsigned long   st_uid;
+        unsigned long   st_gid;
+        unsigned long long      st_rdev;
+        unsigned int    __pad3;
+        long long       st_size;
+        unsigned long   st_blksize;
+        unsigned char   __pad4[4];
+        unsigned long   __pad5;     /* future possible st_blocks high bits */
+        unsigned long   st_blocks;  /* Number 512-byte blocks allocated. */
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;  /* will be high 32 bits of ctime someday */
+        unsigned long long      st_ino;
+};
+
+#else /* __s390x__ */
+
+struct stat {
+        unsigned long  st_dev;
+        unsigned long  st_ino;
+        unsigned long  st_nlink;
+        unsigned int   st_mode;
+        unsigned int   st_uid;
+        unsigned int   st_gid;
+        unsigned int   __pad1;
+        unsigned long  st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  st_blksize;
+        long           st_blocks;
+        unsigned long  __unused[3];
+};
+
+#endif /* __s390x__ */
+
+#define STAT_HAVE_NSEC 1
+
+#endif
diff --git a/arch/s390/include/asm/statfs.h b/arch/s390/include/asm/statfs.h
new file mode 100644
index 000000000000..099a45579190
--- /dev/null
+++ b/arch/s390/include/asm/statfs.h
@@ -0,0 +1,71 @@
+/*
+ *  include/asm-s390/statfs.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/statfs.h"
+ */
+
+#ifndef _S390_STATFS_H
+#define _S390_STATFS_H
+
+#ifndef __s390x__
+#include <asm-generic/statfs.h>
+#else
+
+#ifndef __KERNEL_STRICT_NAMES
+
+#include <linux/types.h>
+
+typedef __kernel_fsid_t fsid_t;
+
+#endif
+
+/*
+ * This is ugly -- we're already 64-bit clean, so just duplicate the 
+ * definitions.
+ */
+struct statfs {
+        int  f_type;
+        int  f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        int  f_namelen;
+        int  f_frsize;
+        int  f_spare[5];
+};
+
+struct statfs64 {
+        int  f_type;
+        int  f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        int  f_namelen;
+        int  f_frsize;
+        int  f_spare[5];
+};
+
+struct compat_statfs64 {
+        __u32 f_type;
+        __u32 f_bsize;
+        __u64 f_blocks;
+        __u64 f_bfree;
+        __u64 f_bavail;
+        __u64 f_files;
+        __u64 f_ffree;
+        __kernel_fsid_t f_fsid;
+        __u32 f_namelen;
+        __u32 f_frsize;
+        __u32 f_spare[5];
+};
+
+#endif /* __s390x__ */
+#endif
diff --git a/arch/s390/include/asm/string.h b/arch/s390/include/asm/string.h
new file mode 100644
index 000000000000..d074673a6d9b
--- /dev/null
+++ b/arch/s390/include/asm/string.h
@@ -0,0 +1,143 @@
+/*
+ *  include/asm-s390/string.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ */
+
+#ifndef _S390_STRING_H_
+#define _S390_STRING_H_
+
+#ifdef __KERNEL__
+
+#ifndef _LINUX_TYPES_H
+#include <linux/types.h>
+#endif
+
+#define __HAVE_ARCH_MEMCHR      /* inline & arch function */
+#define __HAVE_ARCH_MEMCMP      /* arch function */
+#define __HAVE_ARCH_MEMCPY      /* gcc builtin & arch function */
+#define __HAVE_ARCH_MEMSCAN     /* inline & arch function */
+#define __HAVE_ARCH_MEMSET      /* gcc builtin & arch function */
+#define __HAVE_ARCH_STRCAT      /* inline & arch function */
+#define __HAVE_ARCH_STRCMP      /* arch function */
+#define __HAVE_ARCH_STRCPY      /* inline & arch function */
+#define __HAVE_ARCH_STRLCAT     /* arch function */
+#define __HAVE_ARCH_STRLCPY     /* arch function */
+#define __HAVE_ARCH_STRLEN      /* inline & arch function */
+#define __HAVE_ARCH_STRNCAT     /* arch function */
+#define __HAVE_ARCH_STRNCPY     /* arch function */
+#define __HAVE_ARCH_STRNLEN     /* inline & arch function */
+#define __HAVE_ARCH_STRRCHR     /* arch function */
+#define __HAVE_ARCH_STRSTR      /* arch function */
+
+/* Prototypes for non-inlined arch strings functions. */
+extern int memcmp(const void *, const void *, size_t);
+extern void *memcpy(void *, const void *, size_t);
+extern void *memset(void *, int, size_t);
+extern int strcmp(const char *,const char *);
+extern size_t strlcat(char *, const char *, size_t);
+extern size_t strlcpy(char *, const char *, size_t);
+extern char *strncat(char *, const char *, size_t);
+extern char *strncpy(char *, const char *, size_t);
+extern char *strrchr(const char *, int);
+extern char *strstr(const char *, const char *);
+
+#undef __HAVE_ARCH_MEMMOVE
+#undef __HAVE_ARCH_STRCHR
+#undef __HAVE_ARCH_STRNCHR
+#undef __HAVE_ARCH_STRNCMP
+#undef __HAVE_ARCH_STRNICMP
+#undef __HAVE_ARCH_STRPBRK
+#undef __HAVE_ARCH_STRSEP
+#undef __HAVE_ARCH_STRSPN
+
+#if !defined(IN_ARCH_STRING_C)
+
+static inline void *memchr(const void * s, int c, size_t n)
+{
+        register int r0 asm("0") = (char) c;
+        const void *ret = s + n;
+
+        asm volatile(
+                "0:     srst    %0,%1\n"
+                "       jo      0b\n"
+                "       jl      1f\n"
+                "       la      %0,0\n"
+                "1:"
+                : "+a" (ret), "+&a" (s) : "d" (r0) : "cc");
+        return (void *) ret;
+}
+
+static inline void *memscan(void *s, int c, size_t n)
+{
+        register int r0 asm("0") = (char) c;
+        const void *ret = s + n;
+
+        asm volatile(
+                "0:     srst    %0,%1\n"
+                "       jo      0b\n"
+                : "+a" (ret), "+&a" (s) : "d" (r0) : "cc");
+        return (void *) ret;
+}
+
+static inline char *strcat(char *dst, const char *src)
+{
+        register int r0 asm("0") = 0;
+        unsigned long dummy;
+        char *ret = dst;
+
+        asm volatile(
+                "0:     srst    %0,%1\n"
+                "       jo      0b\n"
+                "1:     mvst    %0,%2\n"
+                "       jo      1b"
+                : "=&a" (dummy), "+a" (dst), "+a" (src)
+                : "d" (r0), "0" (0) : "cc", "memory" );
+        return ret;
+}
+
+static inline char *strcpy(char *dst, const char *src)
+{
+        register int r0 asm("0") = 0;
+        char *ret = dst;
+
+        asm volatile(
+                "0:     mvst    %0,%1\n"
+                "       jo      0b"
+                : "+&a" (dst), "+&a" (src) : "d" (r0)
+                : "cc", "memory");
+        return ret;
+}
+
+static inline size_t strlen(const char *s)
+{
+        register unsigned long r0 asm("0") = 0;
+        const char *tmp = s;
+
+        asm volatile(
+                "0:     srst    %0,%1\n"
+                "       jo      0b"
+                : "+d" (r0), "+a" (tmp) :  : "cc");
+        return r0 - (unsigned long) s;
+}
+
+static inline size_t strnlen(const char * s, size_t n)
+{
+        register int r0 asm("0") = 0;
+        const char *tmp = s;
+        const char *end = s + n;
+
+        asm volatile(
+                "0:     srst    %0,%1\n"
+                "       jo      0b"
+                : "+a" (end), "+a" (tmp) : "d" (r0)  : "cc");
+        return end - s;
+}
+
+#endif /* !IN_ARCH_STRING_C */
+
+#endif /* __KERNEL__ */
+
+#endif /* __S390_STRING_H_ */
diff --git a/arch/s390/include/asm/suspend.h b/arch/s390/include/asm/suspend.h
new file mode 100644
index 000000000000..1f34580e67a7
--- /dev/null
+++ b/arch/s390/include/asm/suspend.h
@@ -0,0 +1,5 @@
+#ifndef __ASM_S390_SUSPEND_H
+#define __ASM_S390_SUSPEND_H
+
+#endif
+
diff --git a/arch/s390/include/asm/sysinfo.h b/arch/s390/include/asm/sysinfo.h
new file mode 100644
index 000000000000..79d01343f8b0
--- /dev/null
+++ b/arch/s390/include/asm/sysinfo.h
@@ -0,0 +1,121 @@
+/*
+ * definition for store system information stsi
+ *
+ * Copyright IBM Corp. 2001,2008
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ *    Author(s): Ulrich Weigand <weigand@de.ibm.com>
+ *               Christian Borntraeger <borntraeger@de.ibm.com>
+ */
+
+#ifndef __ASM_S390_SYSINFO_H
+#define __ASM_S390_SYSINFO_H
+
+struct sysinfo_1_1_1 {
+        char reserved_0[32];
+        char manufacturer[16];
+        char type[4];
+        char reserved_1[12];
+        char model_capacity[16];
+        char sequence[16];
+        char plant[4];
+        char model[16];
+        char model_perm_cap[16];
+        char model_temp_cap[16];
+        char model_cap_rating[4];
+        char model_perm_cap_rating[4];
+        char model_temp_cap_rating[4];
+};
+
+struct sysinfo_1_2_1 {
+        char reserved_0[80];
+        char sequence[16];
+        char plant[4];
+        char reserved_1[2];
+        unsigned short cpu_address;
+};
+
+struct sysinfo_1_2_2 {
+        char format;
+        char reserved_0[1];
+        unsigned short acc_offset;
+        char reserved_1[24];
+        unsigned int secondary_capability;
+        unsigned int capability;
+        unsigned short cpus_total;
+        unsigned short cpus_configured;
+        unsigned short cpus_standby;
+        unsigned short cpus_reserved;
+        unsigned short adjustment[0];
+};
+
+struct sysinfo_1_2_2_extension {
+        unsigned int alt_capability;
+        unsigned short alt_adjustment[0];
+};
+
+struct sysinfo_2_2_1 {
+        char reserved_0[80];
+        char sequence[16];
+        char plant[4];
+        unsigned short cpu_id;
+        unsigned short cpu_address;
+};
+
+struct sysinfo_2_2_2 {
+        char reserved_0[32];
+        unsigned short lpar_number;
+        char reserved_1;
+        unsigned char characteristics;
+        unsigned short cpus_total;
+        unsigned short cpus_configured;
+        unsigned short cpus_standby;
+        unsigned short cpus_reserved;
+        char name[8];
+        unsigned int caf;
+        char reserved_2[16];
+        unsigned short cpus_dedicated;
+        unsigned short cpus_shared;
+};
+
+#define LPAR_CHAR_DEDICATED     (1 << 7)
+#define LPAR_CHAR_SHARED        (1 << 6)
+#define LPAR_CHAR_LIMITED       (1 << 5)
+
+struct sysinfo_3_2_2 {
+        char reserved_0[31];
+        unsigned char count;
+        struct {
+                char reserved_0[4];
+                unsigned short cpus_total;
+                unsigned short cpus_configured;
+                unsigned short cpus_standby;
+                unsigned short cpus_reserved;
+                char name[8];
+                unsigned int caf;
+                char cpi[16];
+                char reserved_1[24];
+
+        } vm[8];
+};
+
+static inline int stsi(void *sysinfo, int fc, int sel1, int sel2)
+{
+        register int r0 asm("0") = (fc << 28) | sel1;
+        register int r1 asm("1") = sel2;
+
+        asm volatile(
+                "   stsi 0(%2)\n"
+                "0: jz   2f\n"
+                "1: lhi  %0,%3\n"
+                "2:\n"
+                EX_TABLE(0b, 1b)
+                : "+d" (r0) : "d" (r1), "a" (sysinfo), "K" (-ENOSYS)
+                : "cc", "memory");
+        return r0;
+}
+
+#endif /* __ASM_S390_SYSINFO_H */
diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h
new file mode 100644
index 000000000000..819e7d99ca0c
--- /dev/null
+++ b/arch/s390/include/asm/system.h
@@ -0,0 +1,462 @@
+/*
+ *  include/asm-s390/system.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *
+ *  Derived from "include/asm-i386/system.h"
+ */
+
+#ifndef __ASM_SYSTEM_H
+#define __ASM_SYSTEM_H
+
+#include <linux/kernel.h>
+#include <asm/types.h>
+#include <asm/ptrace.h>
+#include <asm/setup.h>
+#include <asm/processor.h>
+#include <asm/lowcore.h>
+
+#ifdef __KERNEL__
+
+struct task_struct;
+
+extern struct task_struct *__switch_to(void *, void *);
+
+static inline void save_fp_regs(s390_fp_regs *fpregs)
+{
+        asm volatile(
+                "       std     0,8(%1)\n"
+                "       std     2,24(%1)\n"
+                "       std     4,40(%1)\n"
+                "       std     6,56(%1)"
+                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
+        if (!MACHINE_HAS_IEEE)
+                return;
+        asm volatile(
+                "       stfpc   0(%1)\n"
+                "       std     1,16(%1)\n"
+                "       std     3,32(%1)\n"
+                "       std     5,48(%1)\n"
+                "       std     7,64(%1)\n"
+                "       std     8,72(%1)\n"
+                "       std     9,80(%1)\n"
+                "       std     10,88(%1)\n"
+                "       std     11,96(%1)\n"
+                "       std     12,104(%1)\n"
+                "       std     13,112(%1)\n"
+                "       std     14,120(%1)\n"
+                "       std     15,128(%1)\n"
+                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
+}
+
+static inline void restore_fp_regs(s390_fp_regs *fpregs)
+{
+        asm volatile(
+                "       ld      0,8(%0)\n"
+                "       ld      2,24(%0)\n"
+                "       ld      4,40(%0)\n"
+                "       ld      6,56(%0)"
+                : : "a" (fpregs), "m" (*fpregs));
+        if (!MACHINE_HAS_IEEE)
+                return;
+        asm volatile(
+                "       lfpc    0(%0)\n"
+                "       ld      1,16(%0)\n"
+                "       ld      3,32(%0)\n"
+                "       ld      5,48(%0)\n"
+                "       ld      7,64(%0)\n"
+                "       ld      8,72(%0)\n"
+                "       ld      9,80(%0)\n"
+                "       ld      10,88(%0)\n"
+                "       ld      11,96(%0)\n"
+                "       ld      12,104(%0)\n"
+                "       ld      13,112(%0)\n"
+                "       ld      14,120(%0)\n"
+                "       ld      15,128(%0)\n"
+                : : "a" (fpregs), "m" (*fpregs));
+}
+
+static inline void save_access_regs(unsigned int *acrs)
+{
+        asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
+}
+
+static inline void restore_access_regs(unsigned int *acrs)
+{
+        asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
+}
+
+#define switch_to(prev,next,last) do {                                       \
+        if (prev == next)                                                    \
+                break;                                                       \
+        save_fp_regs(&prev->thread.fp_regs);                                 \
+        restore_fp_regs(&next->thread.fp_regs);                              \
+        save_access_regs(&prev->thread.acrs[0]);                             \
+        restore_access_regs(&next->thread.acrs[0]);                          \
+        prev = __switch_to(prev,next);                                       \
+} while (0)
+
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+extern void account_vtime(struct task_struct *);
+extern void account_tick_vtime(struct task_struct *);
+extern void account_system_vtime(struct task_struct *);
+#else
+#define account_vtime(x) do { /* empty */ } while (0)
+#endif
+
+#ifdef CONFIG_PFAULT
+extern void pfault_irq_init(void);
+extern int pfault_init(void);
+extern void pfault_fini(void);
+#else /* CONFIG_PFAULT */
+#define pfault_irq_init()       do { } while (0)
+#define pfault_init()           ({-1;})
+#define pfault_fini()           do { } while (0)
+#endif /* CONFIG_PFAULT */
+
+#ifdef CONFIG_PAGE_STATES
+extern void cmma_init(void);
+#else
+static inline void cmma_init(void) { }
+#endif
+
+#define finish_arch_switch(prev) do {                                        \
+        set_fs(current->thread.mm_segment);                                  \
+        account_vtime(prev);                                                 \
+} while (0)
+
+#define nop() asm volatile("nop")
+
+#define xchg(ptr,x)                                                       \
+({                                                                        \
+        __typeof__(*(ptr)) __ret;                                         \
+        __ret = (__typeof__(*(ptr)))                                      \
+                __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
+        __ret;                                                            \
+})
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
+{
+        unsigned long addr, old;
+        int shift;
+
+        switch (size) {
+        case 1:
+                addr = (unsigned long) ptr;
+                shift = (3 ^ (addr & 3)) << 3;
+                addr ^= addr & 3;
+                asm volatile(
+                        "       l       %0,0(%4)\n"
+                        "0:     lr      0,%0\n"
+                        "       nr      0,%3\n"
+                        "       or      0,%2\n"
+                        "       cs      %0,0,0(%4)\n"
+                        "       jl      0b\n"
+                        : "=&d" (old), "=m" (*(int *) addr)
+                        : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
+                          "m" (*(int *) addr) : "memory", "cc", "0");
+                return old >> shift;
+        case 2:
+                addr = (unsigned long) ptr;
+                shift = (2 ^ (addr & 2)) << 3;
+                addr ^= addr & 2;
+                asm volatile(
+                        "       l       %0,0(%4)\n"
+                        "0:     lr      0,%0\n"
+                        "       nr      0,%3\n"
+                        "       or      0,%2\n"
+                        "       cs      %0,0,0(%4)\n"
+                        "       jl      0b\n"
+                        : "=&d" (old), "=m" (*(int *) addr)
+                        : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
+                          "m" (*(int *) addr) : "memory", "cc", "0");
+                return old >> shift;
+        case 4:
+                asm volatile(
+                        "       l       %0,0(%3)\n"
+                        "0:     cs      %0,%2,0(%3)\n"
+                        "       jl      0b\n"
+                        : "=&d" (old), "=m" (*(int *) ptr)
+                        : "d" (x), "a" (ptr), "m" (*(int *) ptr)
+                        : "memory", "cc");
+                return old;
+#ifdef __s390x__
+        case 8:
+                asm volatile(
+                        "       lg      %0,0(%3)\n"
+                        "0:     csg     %0,%2,0(%3)\n"
+                        "       jl      0b\n"
+                        : "=&d" (old), "=m" (*(long *) ptr)
+                        : "d" (x), "a" (ptr), "m" (*(long *) ptr)
+                        : "memory", "cc");
+                return old;
+#endif /* __s390x__ */
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+#define cmpxchg(ptr, o, n)                                              \
+        ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),       \
+                                        (unsigned long)(n), sizeof(*(ptr))))
+
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+{
+        unsigned long addr, prev, tmp;
+        int shift;
+
+        switch (size) {
+        case 1:
+                addr = (unsigned long) ptr;
+                shift = (3 ^ (addr & 3)) << 3;
+                addr ^= addr & 3;
+                asm volatile(
+                        "       l       %0,0(%4)\n"
+                        "0:     nr      %0,%5\n"
+                        "       lr      %1,%0\n"
+                        "       or      %0,%2\n"
+                        "       or      %1,%3\n"
+                        "       cs      %0,%1,0(%4)\n"
+                        "       jnl     1f\n"
+                        "       xr      %1,%0\n"
+                        "       nr      %1,%5\n"
+                        "       jnz     0b\n"
+                        "1:"
+                        : "=&d" (prev), "=&d" (tmp)
+                        : "d" (old << shift), "d" (new << shift), "a" (ptr),
+                          "d" (~(255 << shift))
+                        : "memory", "cc");
+                return prev >> shift;
+        case 2:
+                addr = (unsigned long) ptr;
+                shift = (2 ^ (addr & 2)) << 3;
+                addr ^= addr & 2;
+                asm volatile(
+                        "       l       %0,0(%4)\n"
+                        "0:     nr      %0,%5\n"
+                        "       lr      %1,%0\n"
+                        "       or      %0,%2\n"
+                        "       or      %1,%3\n"
+                        "       cs      %0,%1,0(%4)\n"
+                        "       jnl     1f\n"
+                        "       xr      %1,%0\n"
+                        "       nr      %1,%5\n"
+                        "       jnz     0b\n"
+                        "1:"
+                        : "=&d" (prev), "=&d" (tmp)
+                        : "d" (old << shift), "d" (new << shift), "a" (ptr),
+                          "d" (~(65535 << shift))
+                        : "memory", "cc");
+                return prev >> shift;
+        case 4:
+                asm volatile(
+                        "       cs      %0,%2,0(%3)\n"
+                        : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
+                        : "memory", "cc");
+                return prev;
+#ifdef __s390x__
+        case 8:
+                asm volatile(
+                        "       csg     %0,%2,0(%3)\n"
+                        : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
+                        : "memory", "cc");
+                return prev;
+#endif /* __s390x__ */
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+/*
+ * Force strict CPU ordering.
+ * And yes, this is required on UP too when we're talking
+ * to devices.
+ *
+ * This is very similar to the ppc eieio/sync instruction in that is
+ * does a checkpoint syncronisation & makes sure that 
+ * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
+ */
+
+#define eieio() asm volatile("bcr 15,0" : : : "memory")
+#define SYNC_OTHER_CORES(x)   eieio()
+#define mb()    eieio()
+#define rmb()   eieio()
+#define wmb()   eieio()
+#define read_barrier_depends() do { } while(0)
+#define smp_mb()       mb()
+#define smp_rmb()      rmb()
+#define smp_wmb()      wmb()
+#define smp_read_barrier_depends()    read_barrier_depends()
+#define smp_mb__before_clear_bit()     smp_mb()
+#define smp_mb__after_clear_bit()      smp_mb()
+
+
+#define set_mb(var, value)      do { var = value; mb(); } while (0)
+
+#ifdef __s390x__
+
+#define __ctl_load(array, low, high) ({                         \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
+        asm volatile(                                           \
+                "       lctlg   %1,%2,0(%0)\n"                  \
+                : : "a" (&array), "i" (low), "i" (high),        \
+                    "m" (*(addrtype *)(&array)));               \
+        })
+
+#define __ctl_store(array, low, high) ({                        \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
+        asm volatile(                                           \
+                "       stctg   %2,%3,0(%1)\n"                  \
+                : "=m" (*(addrtype *)(&array))                  \
+                : "a" (&array), "i" (low), "i" (high));         \
+        })
+
+#else /* __s390x__ */
+
+#define __ctl_load(array, low, high) ({                         \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
+        asm volatile(                                           \
+                "       lctl    %1,%2,0(%0)\n"                  \
+                : : "a" (&array), "i" (low), "i" (high),        \
+                    "m" (*(addrtype *)(&array)));               \
+})
+
+#define __ctl_store(array, low, high) ({                        \
+        typedef struct { char _[sizeof(array)]; } addrtype;     \
+        asm volatile(                                           \
+                "       stctl   %2,%3,0(%1)\n"                  \
+                : "=m" (*(addrtype *)(&array))                  \
+                : "a" (&array), "i" (low), "i" (high));         \
+        })
+
+#endif /* __s390x__ */
+
+#define __ctl_set_bit(cr, bit) ({       \
+        unsigned long __dummy;          \
+        __ctl_store(__dummy, cr, cr);   \
+        __dummy |= 1UL << (bit);        \
+        __ctl_load(__dummy, cr, cr);    \
+})
+
+#define __ctl_clear_bit(cr, bit) ({     \
+        unsigned long __dummy;          \
+        __ctl_store(__dummy, cr, cr);   \
+        __dummy &= ~(1UL << (bit));     \
+        __ctl_load(__dummy, cr, cr);    \
+})
+
+#include <linux/irqflags.h>
+
+#include <asm-generic/cmpxchg-local.h>
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+                                      unsigned long old,
+                                      unsigned long new, int size)
+{
+        switch (size) {
+        case 1:
+        case 2:
+        case 4:
+#ifdef __s390x__
+        case 8:
+#endif
+                return __cmpxchg(ptr, old, new, size);
+        default:
+                return __cmpxchg_local_generic(ptr, old, new, size);
+        }
+
+        return old;
+}
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)                                        \
+        ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
+                        (unsigned long)(n), sizeof(*(ptr))))
+#ifdef __s390x__
+#define cmpxchg64_local(ptr, o, n)                                      \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg_local((ptr), (o), (n));                                 \
+  })
+#else
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+#endif
+
+/*
+ * Use to set psw mask except for the first byte which
+ * won't be changed by this function.
+ */
+static inline void
+__set_psw_mask(unsigned long mask)
+{
+        __load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
+}
+
+#define local_mcck_enable()  __set_psw_mask(psw_kernel_bits)
+#define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
+
+int stfle(unsigned long long *list, int doublewords);
+
+#ifdef CONFIG_SMP
+
+extern void smp_ctl_set_bit(int cr, int bit);
+extern void smp_ctl_clear_bit(int cr, int bit);
+#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
+#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
+
+#else
+
+#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
+#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
+
+#endif /* CONFIG_SMP */
+
+static inline unsigned int stfl(void)
+{
+        asm volatile(
+                "       .insn   s,0xb2b10000,0(0)\n" /* stfl */
+                "0:\n"
+                EX_TABLE(0b,0b));
+        return S390_lowcore.stfl_fac_list;
+}
+
+static inline unsigned short stap(void)
+{
+        unsigned short cpu_address;
+
+        asm volatile("stap %0" : "=m" (cpu_address));
+        return cpu_address;
+}
+
+extern void (*_machine_restart)(char *command);
+extern void (*_machine_halt)(void);
+extern void (*_machine_power_off)(void);
+
+#define arch_align_stack(x) (x)
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+extern psw_t sysc_restore_trace_psw;
+extern psw_t io_restore_trace_psw;
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/s390/include/asm/tape390.h b/arch/s390/include/asm/tape390.h
new file mode 100644
index 000000000000..884fba48f1ff
--- /dev/null
+++ b/arch/s390/include/asm/tape390.h
@@ -0,0 +1,103 @@
+/*************************************************************************
+ *
+ * tape390.h
+ *         enables user programs to display messages and control encryption
+ *         on s390 tape devices
+ *
+ *         Copyright IBM Corp. 2001,2006
+ *         Author(s): Michael Holzheu <holzheu@de.ibm.com>
+ *
+ *************************************************************************/
+
+#ifndef _TAPE390_H
+#define _TAPE390_H
+
+#define TAPE390_DISPLAY _IOW('d', 1, struct display_struct)
+
+/*
+ * The TAPE390_DISPLAY ioctl calls the Load Display command
+ * which transfers 17 bytes of data from the channel to the subsystem:
+ *     - 1 format control byte, and
+ *     - two 8-byte messages
+ *
+ * Format control byte:
+ *   0-2: New Message Overlay
+ *     3: Alternate Messages
+ *     4: Blink Message
+ *     5: Display Low/High Message
+ *     6: Reserved
+ *     7: Automatic Load Request
+ *
+ */
+
+typedef struct display_struct {
+        char cntrl;
+        char message1[8];
+        char message2[8];
+} display_struct;
+
+/*
+ * Tape encryption support
+ */
+
+struct tape390_crypt_info {
+        char capability;
+        char status;
+        char medium_status;
+} __attribute__ ((packed));
+
+
+/* Macros for "capable" field */
+#define TAPE390_CRYPT_SUPPORTED_MASK 0x01
+#define TAPE390_CRYPT_SUPPORTED(x) \
+        ((x.capability & TAPE390_CRYPT_SUPPORTED_MASK))
+
+/* Macros for "status" field */
+#define TAPE390_CRYPT_ON_MASK 0x01
+#define TAPE390_CRYPT_ON(x) (((x.status) & TAPE390_CRYPT_ON_MASK))
+
+/* Macros for "medium status" field */
+#define TAPE390_MEDIUM_LOADED_MASK 0x01
+#define TAPE390_MEDIUM_ENCRYPTED_MASK 0x02
+#define TAPE390_MEDIUM_ENCRYPTED(x) \
+        (((x.medium_status) & TAPE390_MEDIUM_ENCRYPTED_MASK))
+#define TAPE390_MEDIUM_LOADED(x) \
+        (((x.medium_status) & TAPE390_MEDIUM_LOADED_MASK))
+
+/*
+ * The TAPE390_CRYPT_SET ioctl is used to switch on/off encryption.
+ * The "encryption_capable" and "tape_status" fields are ignored for this ioctl!
+ */
+#define TAPE390_CRYPT_SET _IOW('d', 2, struct tape390_crypt_info)
+
+/*
+ * The TAPE390_CRYPT_QUERY ioctl is used to query the encryption state.
+ */
+#define TAPE390_CRYPT_QUERY _IOR('d', 3, struct tape390_crypt_info)
+
+/* Values for "kekl1/2_type" and "kekl1/2_type_on_tape" fields */
+#define TAPE390_KEKL_TYPE_NONE 0
+#define TAPE390_KEKL_TYPE_LABEL 1
+#define TAPE390_KEKL_TYPE_HASH 2
+
+struct tape390_kekl {
+        unsigned char type;
+        unsigned char type_on_tape;
+        char label[65];
+} __attribute__ ((packed));
+
+struct tape390_kekl_pair {
+        struct tape390_kekl kekl[2];
+} __attribute__ ((packed));
+
+/*
+ * The TAPE390_KEKL_SET ioctl is used to set Key Encrypting Key labels.
+ */
+#define TAPE390_KEKL_SET _IOW('d', 4, struct tape390_kekl_pair)
+
+/*
+ * The TAPE390_KEKL_QUERY ioctl is used to query Key Encrypting Key labels.
+ */
+#define TAPE390_KEKL_QUERY _IOR('d', 5, struct tape390_kekl_pair)
+
+#endif 
diff --git a/arch/s390/include/asm/termbits.h b/arch/s390/include/asm/termbits.h
new file mode 100644
index 000000000000..58731853d529
--- /dev/null
+++ b/arch/s390/include/asm/termbits.h
@@ -0,0 +1,206 @@
+/*
+ *  include/asm-s390/termbits.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/termbits.h"
+ */
+
+#ifndef __ARCH_S390_TERMBITS_H__
+#define __ARCH_S390_TERMBITS_H__
+
+#include <linux/posix_types.h>
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define  BOTHER  0010000
+#define  B57600  0010001
+#define  B115200 0010002
+#define  B230400 0010003
+#define  B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate */
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+#define IBSHIFT   16            /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif
diff --git a/arch/s390/include/asm/termios.h b/arch/s390/include/asm/termios.h
new file mode 100644
index 000000000000..67f66278f533
--- /dev/null
+++ b/arch/s390/include/asm/termios.h
@@ -0,0 +1,67 @@
+/*
+ *  include/asm-s390/termios.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/termios.h"
+ */
+
+#ifndef _S390_TERMIOS_H
+#define _S390_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+#ifdef __KERNEL__
+
+/*      intr=^C         quit=^\         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+
+#include <asm-generic/termios.h>
+
+#endif  /* __KERNEL__ */
+
+#endif  /* _S390_TERMIOS_H */
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
new file mode 100644
index 000000000000..91a8f93ad355
--- /dev/null
+++ b/arch/s390/include/asm/thread_info.h
@@ -0,0 +1,118 @@
+/*
+ *  include/asm-s390/thread_info.h
+ *
+ *  S390 version
+ *    Copyright (C) IBM Corp. 2002,2006
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+/*
+ * Size of kernel stack for each process
+ */
+#ifndef __s390x__
+#ifndef __SMALL_STACK
+#define THREAD_ORDER 1
+#define ASYNC_ORDER  1
+#else
+#define THREAD_ORDER 0
+#define ASYNC_ORDER  0
+#endif
+#else /* __s390x__ */
+#ifndef __SMALL_STACK
+#define THREAD_ORDER 2
+#define ASYNC_ORDER  2
+#else
+#define THREAD_ORDER 1
+#define ASYNC_ORDER  1
+#endif
+#endif /* __s390x__ */
+
+#define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
+#define ASYNC_SIZE  (PAGE_SIZE << ASYNC_ORDER)
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+#include <asm/lowcore.h>
+
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants must also be changed
+ */
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        unsigned int            cpu;            /* current CPU */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
+        struct restart_block    restart_block;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = 1,                    \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+        return (struct thread_info *)((*(unsigned long *) __LC_KERNEL_STACK)-THREAD_SIZE);
+}
+
+#define THREAD_SIZE_ORDER THREAD_ORDER
+
+#endif
+
+/*
+ * thread information flags bit numbers
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_RESTART_SVC         4       /* restart svc with new svc number */
+#define TIF_SYSCALL_AUDIT       5       /* syscall auditing active */
+#define TIF_SINGLE_STEP         6       /* deliver sigtrap on return to user */
+#define TIF_MCCK_PENDING        7       /* machine check handling is pending */
+#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling 
+                                           TIF_NEED_RESCHED */
+#define TIF_31BIT               18      /* 32bit process */ 
+#define TIF_MEMDIE              19
+#define TIF_RESTORE_SIGMASK     20      /* restore signal mask in do_signal() */
+
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_RESTART_SVC        (1<<TIF_RESTART_SVC)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SINGLE_STEP        (1<<TIF_SINGLE_STEP)
+#define _TIF_MCCK_PENDING       (1<<TIF_MCCK_PENDING)
+#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_31BIT              (1<<TIF_31BIT)
+
+#endif /* __KERNEL__ */
+
+#define PREEMPT_ACTIVE          0x4000000
+
+#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/s390/include/asm/timer.h b/arch/s390/include/asm/timer.h
new file mode 100644
index 000000000000..d98d79e35cd6
--- /dev/null
+++ b/arch/s390/include/asm/timer.h
@@ -0,0 +1,65 @@
+/*
+ *  include/asm-s390/timer.h
+ *
+ *  (C) Copyright IBM Corp. 2003,2006
+ *  Virtual CPU timer
+ *
+ *  Author: Jan Glauber (jang@de.ibm.com)
+ */
+
+#ifndef _ASM_S390_TIMER_H
+#define _ASM_S390_TIMER_H
+
+#ifdef __KERNEL__
+
+#include <linux/timer.h>
+
+#define VTIMER_MAX_SLICE (0x7ffffffffffff000LL)
+
+struct vtimer_list {
+        struct list_head entry;
+
+        int cpu;
+        __u64 expires;
+        __u64 interval;
+
+        spinlock_t lock;
+        unsigned long magic;
+
+        void (*function)(unsigned long);
+        unsigned long data;
+};
+
+/* the offset value will wrap after ca. 71 years */
+struct vtimer_queue {
+        struct list_head list;
+        spinlock_t lock;
+        __u64 to_expire;          /* current event expire time */
+        __u64 offset;             /* list offset to zero */
+        __u64 idle;               /* temp var for idle */
+};
+
+extern void init_virt_timer(struct vtimer_list *timer);
+extern void add_virt_timer(void *new);
+extern void add_virt_timer_periodic(void *new);
+extern int mod_virt_timer(struct vtimer_list *timer, __u64 expires);
+extern int del_virt_timer(struct vtimer_list *timer);
+
+extern void init_cpu_vtimer(void);
+extern void vtime_init(void);
+
+#ifdef CONFIG_VIRT_TIMER
+
+extern void vtime_start_cpu_timer(void);
+extern void vtime_stop_cpu_timer(void);
+
+#else
+
+static inline void vtime_start_cpu_timer(void) { }
+static inline void vtime_stop_cpu_timer(void) { }
+
+#endif /* CONFIG_VIRT_TIMER */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_S390_TIMER_H */
diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h
new file mode 100644
index 000000000000..d744c3d62de5
--- /dev/null
+++ b/arch/s390/include/asm/timex.h
@@ -0,0 +1,88 @@
+/*
+ *  include/asm-s390/timex.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *
+ *  Derived from "include/asm-i386/timex.h"
+ *    Copyright (C) 1992, Linus Torvalds
+ */
+
+#ifndef _ASM_S390_TIMEX_H
+#define _ASM_S390_TIMEX_H
+
+/* Inline functions for clock register access. */
+static inline int set_clock(__u64 time)
+{
+        int cc;
+
+        asm volatile(
+                "   sck   0(%2)\n"
+                "   ipm   %0\n"
+                "   srl   %0,28\n"
+                : "=d" (cc) : "m" (time), "a" (&time) : "cc");
+        return cc;
+}
+
+static inline int store_clock(__u64 *time)
+{
+        int cc;
+
+        asm volatile(
+                "   stck  0(%2)\n"
+                "   ipm   %0\n"
+                "   srl   %0,28\n"
+                : "=d" (cc), "=m" (*time) : "a" (time) : "cc");
+        return cc;
+}
+
+static inline void set_clock_comparator(__u64 time)
+{
+        asm volatile("sckc 0(%1)" : : "m" (time), "a" (&time));
+}
+
+static inline void store_clock_comparator(__u64 *time)
+{
+        asm volatile("stckc 0(%1)" : "=m" (*time) : "a" (time));
+}
+
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
+
+typedef unsigned long long cycles_t;
+
+static inline unsigned long long get_clock (void)
+{
+        unsigned long long clk;
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+        asm volatile("stck %0" : "=Q" (clk) : : "cc");
+#else /* __GNUC__ */
+        asm volatile("stck 0(%1)" : "=m" (clk) : "a" (&clk) : "cc");
+#endif /* __GNUC__ */
+        return clk;
+}
+
+static inline unsigned long long get_clock_xt(void)
+{
+        unsigned char clk[16];
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
+        asm volatile("stcke %0" : "=Q" (clk) : : "cc");
+#else /* __GNUC__ */
+        asm volatile("stcke 0(%1)" : "=m" (clk)
+                                   : "a" (clk) : "cc");
+#endif /* __GNUC__ */
+
+        return *((unsigned long long *)&clk[1]);
+}
+
+static inline cycles_t get_cycles(void)
+{
+        return (cycles_t) get_clock() >> 2;
+}
+
+int get_sync_clock(unsigned long long *clock);
+void init_cpu_timer(void);
+unsigned long long monotonic_clock(void);
+
+#endif
diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h
new file mode 100644
index 000000000000..3d8a96d39d9d
--- /dev/null
+++ b/arch/s390/include/asm/tlb.h
@@ -0,0 +1,156 @@
+#ifndef _S390_TLB_H
+#define _S390_TLB_H
+
+/*
+ * TLB flushing on s390 is complicated. The following requirement
+ * from the principles of operation is the most arduous:
+ *
+ * "A valid table entry must not be changed while it is attached
+ * to any CPU and may be used for translation by that CPU except to
+ * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
+ * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
+ * table entry, or (3) make a change by means of a COMPARE AND SWAP
+ * AND PURGE instruction that purges the TLB."
+ *
+ * The modification of a pte of an active mm struct therefore is
+ * a two step process: i) invalidate the pte, ii) store the new pte.
+ * This is true for the page protection bit as well.
+ * The only possible optimization is to flush at the beginning of
+ * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
+ *
+ * Pages used for the page tables is a different story. FIXME: more
+ */
+
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <asm/processor.h>
+#include <asm/pgalloc.h>
+#include <asm/smp.h>
+#include <asm/tlbflush.h>
+
+#ifndef CONFIG_SMP
+#define TLB_NR_PTRS     1
+#else
+#define TLB_NR_PTRS     508
+#endif
+
+struct mmu_gather {
+        struct mm_struct *mm;
+        unsigned int fullmm;
+        unsigned int nr_ptes;
+        unsigned int nr_pxds;
+        void *array[TLB_NR_PTRS];
+};
+
+DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm,
+                                                unsigned int full_mm_flush)
+{
+        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
+
+        tlb->mm = mm;
+        tlb->fullmm = full_mm_flush || (num_online_cpus() == 1) ||
+                (atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm);
+        tlb->nr_ptes = 0;
+        tlb->nr_pxds = TLB_NR_PTRS;
+        if (tlb->fullmm)
+                __tlb_flush_mm(mm);
+        return tlb;
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb,
+                                 unsigned long start, unsigned long end)
+{
+        if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < TLB_NR_PTRS))
+                __tlb_flush_mm(tlb->mm);
+        while (tlb->nr_ptes > 0)
+                pte_free(tlb->mm, tlb->array[--tlb->nr_ptes]);
+        while (tlb->nr_pxds < TLB_NR_PTRS)
+                /* pgd_free frees the pointer as region or segment table */
+                pgd_free(tlb->mm, tlb->array[tlb->nr_pxds++]);
+}
+
+static inline void tlb_finish_mmu(struct mmu_gather *tlb,
+                                  unsigned long start, unsigned long end)
+{
+        tlb_flush_mmu(tlb, start, end);
+
+        /* keep the page table cache within bounds */
+        check_pgt_cache();
+
+        put_cpu_var(mmu_gathers);
+}
+
+/*
+ * Release the page cache reference for a pte removed by
+ * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
+ * has already been freed, so just do free_page_and_swap_cache.
+ */
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        free_page_and_swap_cache(page);
+}
+
+/*
+ * pte_free_tlb frees a pte table and clears the CRSTE for the
+ * page table from the tlb.
+ */
+static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte)
+{
+        if (!tlb->fullmm) {
+                tlb->array[tlb->nr_ptes++] = pte;
+                if (tlb->nr_ptes >= tlb->nr_pxds)
+                        tlb_flush_mmu(tlb, 0, 0);
+        } else
+                pte_free(tlb->mm, pte);
+}
+
+/*
+ * pmd_free_tlb frees a pmd table and clears the CRSTE for the
+ * segment table entry from the tlb.
+ * If the mm uses a two level page table the single pmd is freed
+ * as the pgd. pmd_free_tlb checks the asce_limit against 2GB
+ * to avoid the double free of the pmd in this case.
+ */
+static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd)
+{
+#ifdef __s390x__
+        if (tlb->mm->context.asce_limit <= (1UL << 31))
+                return;
+        if (!tlb->fullmm) {
+                tlb->array[--tlb->nr_pxds] = pmd;
+                if (tlb->nr_ptes >= tlb->nr_pxds)
+                        tlb_flush_mmu(tlb, 0, 0);
+        } else
+                pmd_free(tlb->mm, pmd);
+#endif
+}
+
+/*
+ * pud_free_tlb frees a pud table and clears the CRSTE for the
+ * region third table entry from the tlb.
+ * If the mm uses a three level page table the single pud is freed
+ * as the pgd. pud_free_tlb checks the asce_limit against 4TB
+ * to avoid the double free of the pud in this case.
+ */
+static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud)
+{
+#ifdef __s390x__
+        if (tlb->mm->context.asce_limit <= (1UL << 42))
+                return;
+        if (!tlb->fullmm) {
+                tlb->array[--tlb->nr_pxds] = pud;
+                if (tlb->nr_ptes >= tlb->nr_pxds)
+                        tlb_flush_mmu(tlb, 0, 0);
+        } else
+                pud_free(tlb->mm, pud);
+#endif
+}
+
+#define tlb_start_vma(tlb, vma)                 do { } while (0)
+#define tlb_end_vma(tlb, vma)                   do { } while (0)
+#define tlb_remove_tlb_entry(tlb, ptep, addr)   do { } while (0)
+#define tlb_migrate_finish(mm)                  do { } while (0)
+
+#endif /* _S390_TLB_H */
diff --git a/arch/s390/include/asm/tlbflush.h b/arch/s390/include/asm/tlbflush.h
new file mode 100644
index 000000000000..d60394b9745e
--- /dev/null
+++ b/arch/s390/include/asm/tlbflush.h
@@ -0,0 +1,140 @@
+#ifndef _S390_TLBFLUSH_H
+#define _S390_TLBFLUSH_H
+
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <asm/processor.h>
+#include <asm/pgalloc.h>
+
+/*
+ * Flush all tlb entries on the local cpu.
+ */
+static inline void __tlb_flush_local(void)
+{
+        asm volatile("ptlb" : : : "memory");
+}
+
+#ifdef CONFIG_SMP
+/*
+ * Flush all tlb entries on all cpus.
+ */
+void smp_ptlb_all(void);
+
+static inline void __tlb_flush_global(void)
+{
+        register unsigned long reg2 asm("2");
+        register unsigned long reg3 asm("3");
+        register unsigned long reg4 asm("4");
+        long dummy;
+
+#ifndef __s390x__
+        if (!MACHINE_HAS_CSP) {
+                smp_ptlb_all();
+                return;
+        }
+#endif /* __s390x__ */
+
+        dummy = 0;
+        reg2 = reg3 = 0;
+        reg4 = ((unsigned long) &dummy) + 1;
+        asm volatile(
+                "       csp     %0,%2"
+                : : "d" (reg2), "d" (reg3), "d" (reg4), "m" (dummy) : "cc" );
+}
+
+static inline void __tlb_flush_full(struct mm_struct *mm)
+{
+        cpumask_t local_cpumask;
+
+        preempt_disable();
+        /*
+         * If the process only ran on the local cpu, do a local flush.
+         */
+        local_cpumask = cpumask_of_cpu(smp_processor_id());
+        if (cpus_equal(mm->cpu_vm_mask, local_cpumask))
+                __tlb_flush_local();
+        else
+                __tlb_flush_global();
+        preempt_enable();
+}
+#else
+#define __tlb_flush_full(mm)    __tlb_flush_local()
+#endif
+
+/*
+ * Flush all tlb entries of a page table on all cpus.
+ */
+static inline void __tlb_flush_idte(unsigned long asce)
+{
+        asm volatile(
+                "       .insn   rrf,0xb98e0000,0,%0,%1,0"
+                : : "a" (2048), "a" (asce) : "cc" );
+}
+
+static inline void __tlb_flush_mm(struct mm_struct * mm)
+{
+        if (unlikely(cpus_empty(mm->cpu_vm_mask)))
+                return;
+        /*
+         * If the machine has IDTE we prefer to do a per mm flush
+         * on all cpus instead of doing a local flush if the mm
+         * only ran on the local cpu.
+         */
+        if (MACHINE_HAS_IDTE) {
+                if (mm->context.noexec)
+                        __tlb_flush_idte((unsigned long)
+                                         get_shadow_table(mm->pgd) |
+                                         mm->context.asce_bits);
+                __tlb_flush_idte((unsigned long) mm->pgd |
+                                 mm->context.asce_bits);
+                return;
+        }
+        __tlb_flush_full(mm);
+}
+
+static inline void __tlb_flush_mm_cond(struct mm_struct * mm)
+{
+        if (atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm)
+                __tlb_flush_mm(mm);
+}
+
+/*
+ * TLB flushing:
+ *  flush_tlb() - flushes the current mm struct TLBs
+ *  flush_tlb_all() - flushes all processes TLBs
+ *  flush_tlb_mm(mm) - flushes the specified mm context TLB's
+ *  flush_tlb_page(vma, vmaddr) - flushes one page
+ *  flush_tlb_range(vma, start, end) - flushes a range of pages
+ *  flush_tlb_kernel_range(start, end) - flushes a range of kernel pages
+ */
+
+/*
+ * flush_tlb_mm goes together with ptep_set_wrprotect for the
+ * copy_page_range operation and flush_tlb_range is related to
+ * ptep_get_and_clear for change_protection. ptep_set_wrprotect and
+ * ptep_get_and_clear do not flush the TLBs directly if the mm has
+ * only one user. At the end of the update the flush_tlb_mm and
+ * flush_tlb_range functions need to do the flush.
+ */
+#define flush_tlb()                             do { } while (0)
+#define flush_tlb_all()                         do { } while (0)
+#define flush_tlb_page(vma, addr)               do { } while (0)
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+        __tlb_flush_mm_cond(mm);
+}
+
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                                   unsigned long start, unsigned long end)
+{
+        __tlb_flush_mm_cond(vma->vm_mm);
+}
+
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+        __tlb_flush_mm(&init_mm);
+}
+
+#endif /* _S390_TLBFLUSH_H */
diff --git a/arch/s390/include/asm/todclk.h b/arch/s390/include/asm/todclk.h
new file mode 100644
index 000000000000..c7f62055488a
--- /dev/null
+++ b/arch/s390/include/asm/todclk.h
@@ -0,0 +1,23 @@
+/*
+ * File...........: linux/include/asm/todclk.h
+ * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
+ * Bugreports.to..: <Linux390@de.ibm.com>
+ * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000
+ *
+ * History of changes (starts July 2000)
+ */
+
+#ifndef __ASM_TODCLK_H
+#define __ASM_TODCLK_H
+
+#ifdef __KERNEL__
+
+#define TOD_uSEC (0x1000ULL)
+#define TOD_mSEC (1000 * TOD_uSEC)
+#define TOD_SEC (1000 * TOD_mSEC)
+#define TOD_MIN (60 * TOD_SEC)
+#define TOD_HOUR (60 * TOD_MIN)
+
+#endif
+
+#endif
diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h
new file mode 100644
index 000000000000..d96c91643458
--- /dev/null
+++ b/arch/s390/include/asm/topology.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_S390_TOPOLOGY_H
+#define _ASM_S390_TOPOLOGY_H
+
+#include <linux/cpumask.h>
+
+#define mc_capable()    (1)
+
+cpumask_t cpu_coregroup_map(unsigned int cpu);
+
+extern cpumask_t cpu_core_map[NR_CPUS];
+
+#define topology_core_siblings(cpu)     (cpu_core_map[cpu])
+
+int topology_set_cpu_management(int fc);
+void topology_schedule_update(void);
+
+#define POLARIZATION_UNKNWN     (-1)
+#define POLARIZATION_HRZ        (0)
+#define POLARIZATION_VL         (1)
+#define POLARIZATION_VM         (2)
+#define POLARIZATION_VH         (3)
+
+#ifdef CONFIG_SMP
+void s390_init_cpu_topology(void);
+#else
+static inline void s390_init_cpu_topology(void)
+{
+};
+#endif
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_S390_TOPOLOGY_H */
diff --git a/arch/s390/include/asm/types.h b/arch/s390/include/asm/types.h
new file mode 100644
index 000000000000..41c547656130
--- /dev/null
+++ b/arch/s390/include/asm/types.h
@@ -0,0 +1,63 @@
+/*
+ *  include/asm-s390/types.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/types.h"
+ */
+
+#ifndef _S390_TYPES_H
+#define _S390_TYPES_H
+
+#ifndef __s390x__
+# include <asm-generic/int-ll64.h>
+#else
+# include <asm-generic/int-l64.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/* A address type so that arithmetic can be done on it & it can be upgraded to
+   64 bit when necessary 
+*/
+typedef unsigned long addr_t; 
+typedef __signed__ long saddr_t;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#ifndef __s390x__
+#define BITS_PER_LONG 32
+#else
+#define BITS_PER_LONG 64
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef u64 dma64_addr_t;
+#ifdef __s390x__
+/* DMA addresses come in 32-bit and 64-bit flavours. */
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+
+#ifndef __s390x__
+typedef union {
+        unsigned long long pair;
+        struct {
+                unsigned long even;
+                unsigned long odd;
+        } subreg;
+} register_pair;
+
+#endif /* ! __s390x__   */
+#endif /* __ASSEMBLY__  */
+#endif /* __KERNEL__    */
+#endif /* _S390_TYPES_H */
diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h
new file mode 100644
index 000000000000..0235970278f0
--- /dev/null
+++ b/arch/s390/include/asm/uaccess.h
@@ -0,0 +1,363 @@
+/*
+ *  include/asm-s390/uaccess.h
+ *
+ *  S390 version
+ *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Hartmut Penner (hp@de.ibm.com),
+ *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ *  Derived from "include/asm-i386/uaccess.h"
+ */
+#ifndef __S390_UACCESS_H
+#define __S390_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/sched.h>
+#include <linux/errno.h>
+
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+
+#define MAKE_MM_SEG(a)  ((mm_segment_t) { (a) })
+
+
+#define KERNEL_DS       MAKE_MM_SEG(0)
+#define USER_DS         MAKE_MM_SEG(1)
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current->thread.mm_segment)
+
+#define set_fs(x) \
+({                                                                      \
+        unsigned long __pto;                                            \
+        current->thread.mm_segment = (x);                               \
+        __pto = current->thread.mm_segment.ar4 ?                        \
+                S390_lowcore.user_asce : S390_lowcore.kernel_asce;      \
+        __ctl_load(__pto, 7, 7);                                        \
+})
+
+#define segment_eq(a,b) ((a).ar4 == (b).ar4)
+
+
+static inline int __access_ok(const void __user *addr, unsigned long size)
+{
+        return 1;
+}
+#define access_ok(type,addr,size) __access_ok(addr,size)
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry
+{
+        unsigned long insn, fixup;
+};
+
+struct uaccess_ops {
+        size_t (*copy_from_user)(size_t, const void __user *, void *);
+        size_t (*copy_from_user_small)(size_t, const void __user *, void *);
+        size_t (*copy_to_user)(size_t, void __user *, const void *);
+        size_t (*copy_to_user_small)(size_t, void __user *, const void *);
+        size_t (*copy_in_user)(size_t, void __user *, const void __user *);
+        size_t (*clear_user)(size_t, void __user *);
+        size_t (*strnlen_user)(size_t, const char __user *);
+        size_t (*strncpy_from_user)(size_t, const char __user *, char *);
+        int (*futex_atomic_op)(int op, int __user *, int oparg, int *old);
+        int (*futex_atomic_cmpxchg)(int __user *, int old, int new);
+};
+
+extern struct uaccess_ops uaccess;
+extern struct uaccess_ops uaccess_std;
+extern struct uaccess_ops uaccess_mvcos;
+extern struct uaccess_ops uaccess_mvcos_switch;
+extern struct uaccess_ops uaccess_pt;
+
+static inline int __put_user_fn(size_t size, void __user *ptr, void *x)
+{
+        size = uaccess.copy_to_user_small(size, ptr, x);
+        return size ? -EFAULT : size;
+}
+
+static inline int __get_user_fn(size_t size, const void __user *ptr, void *x)
+{
+        size = uaccess.copy_from_user_small(size, ptr, x);
+        return size ? -EFAULT : size;
+}
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ */
+#define __put_user(x, ptr) \
+({                                                              \
+        __typeof__(*(ptr)) __x = (x);                           \
+        int __pu_err = -EFAULT;                                 \
+        __chk_user_ptr(ptr);                                    \
+        switch (sizeof (*(ptr))) {                              \
+        case 1:                                                 \
+        case 2:                                                 \
+        case 4:                                                 \
+        case 8:                                                 \
+                __pu_err = __put_user_fn(sizeof (*(ptr)),       \
+                                         ptr, &__x);            \
+                break;                                          \
+        default:                                                \
+                __put_user_bad();                               \
+                break;                                          \
+         }                                                      \
+        __pu_err;                                               \
+})
+
+#define put_user(x, ptr)                                        \
+({                                                              \
+        might_sleep();                                          \
+        __put_user(x, ptr);                                     \
+})
+
+
+extern int __put_user_bad(void) __attribute__((noreturn));
+
+#define __get_user(x, ptr)                                      \
+({                                                              \
+        int __gu_err = -EFAULT;                                 \
+        __chk_user_ptr(ptr);                                    \
+        switch (sizeof(*(ptr))) {                               \
+        case 1: {                                               \
+                unsigned char __x;                              \
+                __gu_err = __get_user_fn(sizeof (*(ptr)),       \
+                                         ptr, &__x);            \
+                (x) = *(__force __typeof__(*(ptr)) *) &__x;     \
+                break;                                          \
+        };                                                      \
+        case 2: {                                               \
+                unsigned short __x;                             \
+                __gu_err = __get_user_fn(sizeof (*(ptr)),       \
+                                         ptr, &__x);            \
+                (x) = *(__force __typeof__(*(ptr)) *) &__x;     \
+                break;                                          \
+        };                                                      \
+        case 4: {                                               \
+                unsigned int __x;                               \
+                __gu_err = __get_user_fn(sizeof (*(ptr)),       \
+                                         ptr, &__x);            \
+                (x) = *(__force __typeof__(*(ptr)) *) &__x;     \
+                break;                                          \
+        };                                                      \
+        case 8: {                                               \
+                unsigned long long __x;                         \
+                __gu_err = __get_user_fn(sizeof (*(ptr)),       \
+                                         ptr, &__x);            \
+                (x) = *(__force __typeof__(*(ptr)) *) &__x;     \
+                break;                                          \
+        };                                                      \
+        default:                                                \
+                __get_user_bad();                               \
+                break;                                          \
+        }                                                       \
+        __gu_err;                                               \
+})
+
+#define get_user(x, ptr)                                        \
+({                                                              \
+        might_sleep();                                          \
+        __get_user(x, ptr);                                     \
+})
+
+extern int __get_user_bad(void) __attribute__((noreturn));
+
+#define __put_user_unaligned __put_user
+#define __get_user_unaligned __get_user
+
+/**
+ * __copy_to_user: - Copy a block of data into user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from kernel space to user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+static inline unsigned long __must_check
+__copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        if (__builtin_constant_p(n) && (n <= 256))
+                return uaccess.copy_to_user_small(n, to, from);
+        else
+                return uaccess.copy_to_user(n, to, from);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+/**
+ * copy_to_user: - Copy a block of data into user space.
+ * @to:   Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from kernel space to user space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+static inline unsigned long __must_check
+copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        might_sleep();
+        if (access_ok(VERIFY_WRITE, to, n))
+                n = __copy_to_user(to, from, n);
+        return n;
+}
+
+/**
+ * __copy_from_user: - Copy a block of data from user space, with less checking.
+ * @to:   Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from user space to kernel space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+static inline unsigned long __must_check
+__copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        if (__builtin_constant_p(n) && (n <= 256))
+                return uaccess.copy_from_user_small(n, from, to);
+        else
+                return uaccess.copy_from_user(n, from, to);
+}
+
+/**
+ * copy_from_user: - Copy a block of data from user space.
+ * @to:   Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from user space to kernel space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+static inline unsigned long __must_check
+copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        might_sleep();
+        if (access_ok(VERIFY_READ, from, n))
+                n = __copy_from_user(to, from, n);
+        else
+                memset(to, 0, n);
+        return n;
+}
+
+static inline unsigned long __must_check
+__copy_in_user(void __user *to, const void __user *from, unsigned long n)
+{
+        return uaccess.copy_in_user(n, to, from);
+}
+
+static inline unsigned long __must_check
+copy_in_user(void __user *to, const void __user *from, unsigned long n)
+{
+        might_sleep();
+        if (__access_ok(from,n) && __access_ok(to,n))
+                n = __copy_in_user(to, from, n);
+        return n;
+}
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+static inline long __must_check
+strncpy_from_user(char *dst, const char __user *src, long count)
+{
+        long res = -EFAULT;
+        might_sleep();
+        if (access_ok(VERIFY_READ, src, 1))
+                res = uaccess.strncpy_from_user(count, src, dst);
+        return res;
+}
+
+static inline unsigned long
+strnlen_user(const char __user * src, unsigned long n)
+{
+        might_sleep();
+        return uaccess.strnlen_user(n, src);
+}
+
+/**
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+#define strlen_user(str) strnlen_user(str, ~0UL)
+
+/*
+ * Zero Userspace
+ */
+
+static inline unsigned long __must_check
+__clear_user(void __user *to, unsigned long n)
+{
+        return uaccess.clear_user(n, to);
+}
+
+static inline unsigned long __must_check
+clear_user(void __user *to, unsigned long n)
+{
+        might_sleep();
+        if (access_ok(VERIFY_WRITE, to, n))
+                n = uaccess.clear_user(n, to);
+        return n;
+}
+
+#endif /* __S390_UACCESS_H */
diff --git a/arch/s390/include/asm/ucontext.h b/arch/s390/include/asm/ucontext.h
new file mode 100644
index 000000000000..d69bec0b03f5
--- /dev/null
+++ b/arch/s390/include/asm/ucontext.h
@@ -0,0 +1,20 @@
+/*
+ *  include/asm-s390/ucontext.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/ucontext.h"
+ */
+
+#ifndef _ASM_S390_UCONTEXT_H
+#define _ASM_S390_UCONTEXT_H
+
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        _sigregs          uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+
+#endif /* !_ASM_S390_UCONTEXT_H */
diff --git a/arch/s390/include/asm/unaligned.h b/arch/s390/include/asm/unaligned.h
new file mode 100644
index 000000000000..da9627afe5d8
--- /dev/null
+++ b/arch/s390/include/asm/unaligned.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_S390_UNALIGNED_H
+#define _ASM_S390_UNALIGNED_H
+
+/*
+ * The S390 can do unaligned accesses itself. 
+ */
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned   __get_unaligned_be
+#define put_unaligned   __put_unaligned_be
+
+#endif /* _ASM_S390_UNALIGNED_H */
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
new file mode 100644
index 000000000000..c8ad350d1444
--- /dev/null
+++ b/arch/s390/include/asm/unistd.h
@@ -0,0 +1,411 @@
+/*
+ *  include/asm-s390/unistd.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/unistd.h"
+ */
+
+#ifndef _ASM_S390_UNISTD_H_
+#define _ASM_S390_UNISTD_H_
+
+/*
+ * This file contains the system call numbers.
+ */
+
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_restart_syscall      7
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_umount              22
+#define __NR_ptrace              26
+#define __NR_alarm               27
+#define __NR_pause               29
+#define __NR_utime               30
+#define __NR_access              33
+#define __NR_nice                34
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_brk                 45
+#define __NR_signal              48
+#define __NR_acct                51
+#define __NR_umount2             52
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_setpgid             57
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_symlink             83
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_readdir             89
+#define __NR_mmap                90
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_socketcall         102
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_lookup_dcookie     110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_ipc                117
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_sigprocmask        126
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_get_kernel_syms    130
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define __NR_getdents           141
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+#define __NR_mlock              150
+#define __NR_munlock            151
+#define __NR_mlockall           152
+#define __NR_munlockall         153
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+#define __NR_mremap             163
+#define __NR_query_module       167
+#define __NR_poll               168
+#define __NR_nfsservctl         169
+#define __NR_prctl              172
+#define __NR_rt_sigreturn       173
+#define __NR_rt_sigaction       174
+#define __NR_rt_sigprocmask     175
+#define __NR_rt_sigpending      176
+#define __NR_rt_sigtimedwait    177
+#define __NR_rt_sigqueueinfo    178
+#define __NR_rt_sigsuspend      179
+#define __NR_pread64            180
+#define __NR_pwrite64           181
+#define __NR_getcwd             183
+#define __NR_capget             184
+#define __NR_capset             185
+#define __NR_sigaltstack        186
+#define __NR_sendfile           187
+#define __NR_getpmsg            188
+#define __NR_putpmsg            189
+#define __NR_vfork              190
+#define __NR_pivot_root         217
+#define __NR_mincore            218
+#define __NR_madvise            219
+#define __NR_getdents64         220
+#define __NR_readahead          222
+#define __NR_setxattr           224
+#define __NR_lsetxattr          225
+#define __NR_fsetxattr          226
+#define __NR_getxattr           227
+#define __NR_lgetxattr          228
+#define __NR_fgetxattr          229
+#define __NR_listxattr          230
+#define __NR_llistxattr         231
+#define __NR_flistxattr         232
+#define __NR_removexattr        233
+#define __NR_lremovexattr       234
+#define __NR_fremovexattr       235
+#define __NR_gettid             236
+#define __NR_tkill              237
+#define __NR_futex              238
+#define __NR_sched_setaffinity  239
+#define __NR_sched_getaffinity  240
+#define __NR_tgkill             241
+/* Number 242 is reserved for tux */
+#define __NR_io_setup           243
+#define __NR_io_destroy         244
+#define __NR_io_getevents       245
+#define __NR_io_submit          246
+#define __NR_io_cancel          247
+#define __NR_exit_group         248
+#define __NR_epoll_create       249
+#define __NR_epoll_ctl          250
+#define __NR_epoll_wait         251
+#define __NR_set_tid_address    252
+#define __NR_fadvise64          253
+#define __NR_timer_create       254
+#define __NR_timer_settime      (__NR_timer_create+1)
+#define __NR_timer_gettime      (__NR_timer_create+2)
+#define __NR_timer_getoverrun   (__NR_timer_create+3)
+#define __NR_timer_delete       (__NR_timer_create+4)
+#define __NR_clock_settime      (__NR_timer_create+5)
+#define __NR_clock_gettime      (__NR_timer_create+6)
+#define __NR_clock_getres       (__NR_timer_create+7)
+#define __NR_clock_nanosleep    (__NR_timer_create+8)
+/* Number 263 is reserved for vserver */
+#define __NR_statfs64           265
+#define __NR_fstatfs64          266
+#define __NR_remap_file_pages   267
+/* Number 268 is reserved for new sys_mbind */
+/* Number 269 is reserved for new sys_get_mempolicy */
+/* Number 270 is reserved for new sys_set_mempolicy */
+#define __NR_mq_open            271
+#define __NR_mq_unlink          272
+#define __NR_mq_timedsend       273
+#define __NR_mq_timedreceive    274
+#define __NR_mq_notify          275
+#define __NR_mq_getsetattr      276
+#define __NR_kexec_load         277
+#define __NR_add_key            278
+#define __NR_request_key        279
+#define __NR_keyctl             280
+#define __NR_waitid             281
+#define __NR_ioprio_set         282
+#define __NR_ioprio_get         283
+#define __NR_inotify_init       284
+#define __NR_inotify_add_watch  285
+#define __NR_inotify_rm_watch   286
+/* Number 287 is reserved for new sys_migrate_pages */
+#define __NR_openat             288
+#define __NR_mkdirat            289
+#define __NR_mknodat            290
+#define __NR_fchownat           291
+#define __NR_futimesat          292
+#define __NR_unlinkat           294
+#define __NR_renameat           295
+#define __NR_linkat             296
+#define __NR_symlinkat          297
+#define __NR_readlinkat         298
+#define __NR_fchmodat           299
+#define __NR_faccessat          300
+#define __NR_pselect6           301
+#define __NR_ppoll              302
+#define __NR_unshare            303
+#define __NR_set_robust_list    304
+#define __NR_get_robust_list    305
+#define __NR_splice             306
+#define __NR_sync_file_range    307
+#define __NR_tee                308
+#define __NR_vmsplice           309
+/* Number 310 is reserved for new sys_move_pages */
+#define __NR_getcpu             311
+#define __NR_epoll_pwait        312
+#define __NR_utimes             313
+#define __NR_fallocate          314
+#define __NR_utimensat          315
+#define __NR_signalfd           316
+#define __NR_timerfd            317
+#define __NR_eventfd            318
+#define __NR_timerfd_create     319
+#define __NR_timerfd_settime    320
+#define __NR_timerfd_gettime    321
+#define __NR_signalfd4          322
+#define __NR_eventfd2           323
+#define __NR_inotify_init1      324
+#define __NR_pipe2              325
+#define __NR_dup3               326
+#define __NR_epoll_create1      327
+#define NR_syscalls 328
+
+/* 
+ * There are some system calls that are not present on 64 bit, some
+ * have a different name although they do the same (e.g. __NR_chown32
+ * is __NR_chown on 64 bit).
+ */
+#ifndef __s390x__
+
+#define __NR_time                13
+#define __NR_lchown              16
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_getrlimit           76
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_fchown              95
+#define __NR_ioperm             101
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR__newselect         142
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+#define __NR_setresgid          170
+#define __NR_getresgid          171
+#define __NR_chown              182
+#define __NR_ugetrlimit         191     /* SuS compliant getrlimit */
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#define __NR_lchown32           198
+#define __NR_getuid32           199
+#define __NR_getgid32           200
+#define __NR_geteuid32          201
+#define __NR_getegid32          202
+#define __NR_setreuid32         203
+#define __NR_setregid32         204
+#define __NR_getgroups32        205
+#define __NR_setgroups32        206
+#define __NR_fchown32           207
+#define __NR_setresuid32        208
+#define __NR_getresuid32        209
+#define __NR_setresgid32        210
+#define __NR_getresgid32        211
+#define __NR_chown32            212
+#define __NR_setuid32           213
+#define __NR_setgid32           214
+#define __NR_setfsuid32         215
+#define __NR_setfsgid32         216
+#define __NR_fcntl64            221
+#define __NR_sendfile64         223
+#define __NR_fadvise64_64       264
+#define __NR_fstatat64          293
+
+#else
+
+#define __NR_select             142
+#define __NR_getrlimit          191     /* SuS compliant getrlimit */
+#define __NR_lchown             198
+#define __NR_getuid             199
+#define __NR_getgid             200
+#define __NR_geteuid            201
+#define __NR_getegid            202
+#define __NR_setreuid           203
+#define __NR_setregid           204
+#define __NR_getgroups          205
+#define __NR_setgroups          206
+#define __NR_fchown             207
+#define __NR_setresuid          208
+#define __NR_getresuid          209
+#define __NR_setresgid          210
+#define __NR_getresgid          211
+#define __NR_chown              212
+#define __NR_setuid             213
+#define __NR_setgid             214
+#define __NR_setfsuid           215
+#define __NR_setfsgid           216
+#define __NR_newfstatat         293
+
+#endif
+
+#ifdef __KERNEL__
+
+#ifndef CONFIG_64BIT
+#define __IGNORE_select
+#else
+#define __IGNORE_time
+#endif
+
+/* Ignore NUMA system calls. Not wired up on s390. */
+#define __IGNORE_mbind
+#define __IGNORE_get_mempolicy
+#define __IGNORE_set_mempolicy
+#define __IGNORE_migrate_pages
+#define __IGNORE_move_pages
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+# ifndef CONFIG_64BIT
+#   define __ARCH_WANT_STAT64
+#   define __ARCH_WANT_SYS_TIME
+# endif
+# ifdef CONFIG_COMPAT
+#   define __ARCH_WANT_COMPAT_SYS_TIME
+#   define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
+# endif
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_S390_UNISTD_H_ */
diff --git a/arch/s390/include/asm/user.h b/arch/s390/include/asm/user.h
new file mode 100644
index 000000000000..1b050e35fdc6
--- /dev/null
+++ b/arch/s390/include/asm/user.h
@@ -0,0 +1,76 @@
+/*
+ *  include/asm-s390/user.h
+ *
+ *  S390 version
+ *
+ *  Derived from "include/asm-i386/usr.h"
+ */
+
+#ifndef _S390_USER_H
+#define _S390_USER_H
+
+#include <asm/page.h>
+#include <asm/ptrace.h>
+/* Core file format: The core file is written in such a way that gdb
+   can understand it and provide useful information to the user (under
+   linux we use the 'trad-core' bfd).  There are quite a number of
+   obstacles to being able to view the contents of the floating point
+   registers, and until these are solved you will not be able to view the
+   contents of them.  Actually, you can read in the core file and look at
+   the contents of the user struct to find out what the floating point
+   registers contain.
+   The actual file contents are as follows:
+   UPAGE: 1 page consisting of a user struct that tells gdb what is present
+   in the file.  Directly after this is a copy of the task_struct, which
+   is currently not used by gdb, but it may come in useful at some point.
+   All of the registers are stored as part of the upage.  The upage should
+   always be only one page.
+   DATA: The data area is stored.  We use current->end_text to
+   current->brk to pick up all of the user variables, plus any memory
+   that may have been malloced.  No attempt is made to determine if a page
+   is demand-zero or if a page is totally unused, we just cover the entire
+   range.  All of the addresses are rounded in such a way that an integral
+   number of pages is written.
+   STACK: We need the stack information in order to get a meaningful
+   backtrace.  We need to write the data from (esp) to
+   current->start_stack, so we round each of these off in order to be able
+   to write an integer number of pages.
+   The minimum core file size is 3 pages, or 12288 bytes.
+*/
+
+
+/*
+ * This is the old layout of "struct pt_regs", and
+ * is still the layout used by user mode (the new
+ * pt_regs doesn't have all registers as the kernel
+ * doesn't use the extra segment registers)
+ */
+
+/* When the kernel dumps core, it starts by dumping the user struct -
+   this will be used by gdb to figure out where the data and stack segments
+   are within the file, and what virtual addresses to use. */
+struct user {
+/* We start with the registers, to mimic the way that "memory" is returned
+   from the ptrace(3,...) function.  */
+  struct user_regs_struct regs;         /* Where the registers are actually stored */
+/* The rest of this junk is to help gdb figure out what goes where */
+  unsigned long int u_tsize;    /* Text segment size (pages). */
+  unsigned long int u_dsize;    /* Data segment size (pages). */
+  unsigned long int u_ssize;    /* Stack segment size (pages). */
+  unsigned long start_code;     /* Starting virtual address of text. */
+  unsigned long start_stack;    /* Starting virtual address of stack area.
+                                   This is actually the bottom of the stack,
+                                   the top of the stack is always found in the
+                                   esp register.  */
+  long int signal;              /* Signal that caused the core dump. */
+  unsigned long u_ar0;          /* Used by gdb to help find the values for */
+                                /* the registers. */
+  unsigned long magic;          /* To uniquely identify a core file */
+  char u_comm[32];              /* User command that was responsible */
+};
+#define NBPG PAGE_SIZE
+#define UPAGES 1
+#define HOST_TEXT_START_ADDR (u.start_code)
+#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _S390_USER_H */
diff --git a/arch/s390/include/asm/vtoc.h b/arch/s390/include/asm/vtoc.h
new file mode 100644
index 000000000000..3a5267d90d29
--- /dev/null
+++ b/arch/s390/include/asm/vtoc.h
@@ -0,0 +1,203 @@
+/*
+ * include/asm-s390/vtoc.h
+ *
+ * This file contains volume label definitions for DASD devices.
+ *
+ * (C) Copyright IBM Corp. 2005
+ *
+ * Author(s): Volker Sameske <sameske@de.ibm.com>
+ *
+ */
+
+#ifndef _ASM_S390_VTOC_H
+#define _ASM_S390_VTOC_H
+
+#include <linux/types.h>
+
+struct vtoc_ttr
+{
+        __u16 tt;
+        __u8 r;
+} __attribute__ ((packed));
+
+struct vtoc_cchhb
+{
+        __u16 cc;
+        __u16 hh;
+        __u8 b;
+} __attribute__ ((packed));
+
+struct vtoc_cchh
+{
+        __u16 cc;
+        __u16 hh;
+} __attribute__ ((packed));
+
+struct vtoc_labeldate
+{
+        __u8 year;
+        __u16 day;
+} __attribute__ ((packed));
+
+struct vtoc_volume_label
+{
+        char volkey[4];         /* volume key = volume label */
+        char vollbl[4];         /* volume label */
+        char volid[6];          /* volume identifier */
+        __u8 security;          /* security byte */
+        struct vtoc_cchhb vtoc; /* VTOC address */
+        char res1[5];           /* reserved */
+        char cisize[4];         /* CI-size for FBA,... */
+                                /* ...blanks for CKD */
+        char blkperci[4];       /* no of blocks per CI (FBA), blanks for CKD */
+        char labperci[4];       /* no of labels per CI (FBA), blanks for CKD */
+        char res2[4];           /* reserved */
+        char lvtoc[14];         /* owner code for LVTOC */
+        char res3[29];          /* reserved */
+} __attribute__ ((packed));
+
+struct vtoc_extent
+{
+        __u8 typeind;                   /* extent type indicator */
+        __u8 seqno;                     /* extent sequence number */
+        struct vtoc_cchh llimit;        /* starting point of this extent */
+        struct vtoc_cchh ulimit;        /* ending point of this extent */
+} __attribute__ ((packed));
+
+struct vtoc_dev_const
+{
+        __u16 DS4DSCYL; /* number of logical cyls */
+        __u16 DS4DSTRK; /* number of tracks in a logical cylinder */
+        __u16 DS4DEVTK; /* device track length */
+        __u8 DS4DEVI;   /* non-last keyed record overhead */
+        __u8 DS4DEVL;   /* last keyed record overhead */
+        __u8 DS4DEVK;   /* non-keyed record overhead differential */
+        __u8 DS4DEVFG;  /* flag byte */
+        __u16 DS4DEVTL; /* device tolerance */
+        __u8 DS4DEVDT;  /* number of DSCB's per track */
+        __u8 DS4DEVDB;  /* number of directory blocks per track */
+} __attribute__ ((packed));
+
+struct vtoc_format1_label
+{
+        char DS1DSNAM[44];      /* data set name */
+        __u8 DS1FMTID;          /* format identifier */
+        char DS1DSSN[6];        /* data set serial number */
+        __u16 DS1VOLSQ;         /* volume sequence number */
+        struct vtoc_labeldate DS1CREDT; /* creation date: ydd */
+        struct vtoc_labeldate DS1EXPDT; /* expiration date */
+        __u8 DS1NOEPV;          /* number of extents on volume */
+        __u8 DS1NOBDB;          /* no. of bytes used in last direction blk */
+        __u8 DS1FLAG1;          /* flag 1 */
+        char DS1SYSCD[13];      /* system code */
+        struct vtoc_labeldate DS1REFD; /* date last referenced  */
+        __u8 DS1SMSFG;          /* system managed storage indicators */
+        __u8 DS1SCXTF;          /* sec. space extension flag byte */
+        __u16 DS1SCXTV;         /* secondary space extension value */
+        __u8 DS1DSRG1;          /* data set organisation byte 1 */
+        __u8 DS1DSRG2;          /* data set organisation byte 2 */
+        __u8 DS1RECFM;          /* record format */
+        __u8 DS1OPTCD;          /* option code */
+        __u16 DS1BLKL;          /* block length */
+        __u16 DS1LRECL;         /* record length */
+        __u8 DS1KEYL;           /* key length */
+        __u16 DS1RKP;           /* relative key position */
+        __u8 DS1DSIND;          /* data set indicators */
+        __u8 DS1SCAL1;          /* secondary allocation flag byte */
+        char DS1SCAL3[3];       /* secondary allocation quantity */
+        struct vtoc_ttr DS1LSTAR; /* last used track and block on track */
+        __u16 DS1TRBAL;         /* space remaining on last used track */
+        __u16 res1;             /* reserved */
+        struct vtoc_extent DS1EXT1; /* first extent description */
+        struct vtoc_extent DS1EXT2; /* second extent description */
+        struct vtoc_extent DS1EXT3; /* third extent description */
+        struct vtoc_cchhb DS1PTRDS; /* possible pointer to f2 or f3 DSCB */
+} __attribute__ ((packed));
+
+struct vtoc_format4_label
+{
+        char DS4KEYCD[44];      /* key code for VTOC labels: 44 times 0x04 */
+        __u8 DS4IDFMT;          /* format identifier */
+        struct vtoc_cchhb DS4HPCHR; /* highest address of a format 1 DSCB */
+        __u16 DS4DSREC;         /* number of available DSCB's */
+        struct vtoc_cchh DS4HCCHH; /* CCHH of next available alternate track */
+        __u16 DS4NOATK;         /* number of remaining alternate tracks */
+        __u8 DS4VTOCI;          /* VTOC indicators */
+        __u8 DS4NOEXT;          /* number of extents in VTOC */
+        __u8 DS4SMSFG;          /* system managed storage indicators */
+        __u8 DS4DEVAC;          /* number of alternate cylinders.
+                                 * Subtract from first two bytes of
+                                 * DS4DEVSZ to get number of usable
+                                 * cylinders. can be zero. valid
+                                 * only if DS4DEVAV on. */
+        struct vtoc_dev_const DS4DEVCT; /* device constants */
+        char DS4AMTIM[8];       /* VSAM time stamp */
+        char DS4AMCAT[3];       /* VSAM catalog indicator */
+        char DS4R2TIM[8];       /* VSAM volume/catalog match time stamp */
+        char res1[5];           /* reserved */
+        char DS4F6PTR[5];       /* pointer to first format 6 DSCB */
+        struct vtoc_extent DS4VTOCE; /* VTOC extent description */
+        char res2[10];          /* reserved */
+        __u8 DS4EFLVL;          /* extended free-space management level */
+        struct vtoc_cchhb DS4EFPTR; /* pointer to extended free-space info */
+        char res3[9];           /* reserved */
+} __attribute__ ((packed));
+
+struct vtoc_ds5ext
+{
+        __u16 t;        /* RTA of the first track of free extent */
+        __u16 fc;       /* number of whole cylinders in free ext. */
+        __u8 ft;        /* number of remaining free tracks */
+} __attribute__ ((packed));
+
+struct vtoc_format5_label
+{
+        char DS5KEYID[4];       /* key identifier */
+        struct vtoc_ds5ext DS5AVEXT; /* first available (free-space) extent. */
+        struct vtoc_ds5ext DS5EXTAV[7]; /* seven available extents */
+        __u8 DS5FMTID;          /* format identifier */
+        struct vtoc_ds5ext DS5MAVET[18]; /* eighteen available extents */
+        struct vtoc_cchhb DS5PTRDS; /* pointer to next format5 DSCB */
+} __attribute__ ((packed));
+
+struct vtoc_ds7ext
+{
+        __u32 a; /* starting RTA value */
+        __u32 b; /* ending RTA value + 1 */
+} __attribute__ ((packed));
+
+struct vtoc_format7_label
+{
+        char DS7KEYID[4];       /* key identifier */
+        struct vtoc_ds7ext DS7EXTNT[5]; /* space for 5 extent descriptions */
+        __u8 DS7FMTID;          /* format identifier */
+        struct vtoc_ds7ext DS7ADEXT[11]; /* space for 11 extent descriptions */
+        char res1[2];           /* reserved */
+        struct vtoc_cchhb DS7PTRDS; /* pointer to next FMT7 DSCB */
+} __attribute__ ((packed));
+
+struct vtoc_cms_label {
+        __u8 label_id[4];               /* Label identifier */
+        __u8 vol_id[6];         /* Volid */
+        __u16 version_id;               /* Version identifier */
+        __u32 block_size;               /* Disk block size */
+        __u32 origin_ptr;               /* Disk origin pointer */
+        __u32 usable_count;     /* Number of usable cylinders/blocks */
+        __u32 formatted_count;  /* Maximum number of formatted cylinders/
+                                 * blocks */
+        __u32 block_count;      /* Disk size in CMS blocks */
+        __u32 used_count;               /* Number of CMS blocks in use */
+        __u32 fst_size;         /* File Status Table (FST) size */
+        __u32 fst_count;                /* Number of FSTs per CMS block */
+        __u8 format_date[6];    /* Disk FORMAT date */
+        __u8 reserved1[2];
+        __u32 disk_offset;      /* Disk offset when reserved*/
+        __u32 map_block;                /* Allocation Map Block with next hole */
+        __u32 hblk_disp;                /* Displacement into HBLK data of next hole */
+        __u32 user_disp;                /* Displacement into user part of Allocation
+                                 * map */
+        __u8 reserved2[4];
+        __u8 segment_name[8];   /* Name of shared segment */
+} __attribute__ ((packed));
+
+#endif /* _ASM_S390_VTOC_H */
diff --git a/arch/s390/include/asm/xor.h b/arch/s390/include/asm/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/arch/s390/include/asm/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/arch/s390/include/asm/zcrypt.h b/arch/s390/include/asm/zcrypt.h
new file mode 100644
index 000000000000..00d3bbd44117
--- /dev/null
+++ b/arch/s390/include/asm/zcrypt.h
@@ -0,0 +1,276 @@
+/*
+ *  include/asm-s390/zcrypt.h
+ *
+ *  zcrypt 2.1.0 (user-visible header)
+ *
+ *  Copyright (C)  2001, 2006 IBM Corporation
+ *  Author(s): Robert Burroughs
+ *             Eric Rossman (edrossma@us.ibm.com)
+ *
+ *  Hotplug & misc device support: Jochen Roehrig (roehrig@de.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_S390_ZCRYPT_H
+#define __ASM_S390_ZCRYPT_H
+
+#define ZCRYPT_VERSION 2
+#define ZCRYPT_RELEASE 1
+#define ZCRYPT_VARIANT 1
+
+#include <linux/ioctl.h>
+#include <linux/compiler.h>
+
+/**
+ * struct ica_rsa_modexpo
+ *
+ * Requirements:
+ * - outputdatalength is at least as large as inputdatalength.
+ * - All key parts are right justified in their fields, padded on
+ *   the left with zeroes.
+ * - length(b_key) = inputdatalength
+ * - length(n_modulus) = inputdatalength
+ */
+struct ica_rsa_modexpo {
+        char __user *   inputdata;
+        unsigned int    inputdatalength;
+        char __user *   outputdata;
+        unsigned int    outputdatalength;
+        char __user *   b_key;
+        char __user *   n_modulus;
+};
+
+/**
+ * struct ica_rsa_modexpo_crt
+ *
+ * Requirements:
+ * - inputdatalength is even.
+ * - outputdatalength is at least as large as inputdatalength.
+ * - All key parts are right justified in their fields, padded on
+ *   the left with zeroes.
+ * - length(bp_key)     = inputdatalength/2 + 8
+ * - length(bq_key)     = inputdatalength/2
+ * - length(np_key)     = inputdatalength/2 + 8
+ * - length(nq_key)     = inputdatalength/2
+ * - length(u_mult_inv) = inputdatalength/2 + 8
+ */
+struct ica_rsa_modexpo_crt {
+        char __user *   inputdata;
+        unsigned int    inputdatalength;
+        char __user *   outputdata;
+        unsigned int    outputdatalength;
+        char __user *   bp_key;
+        char __user *   bq_key;
+        char __user *   np_prime;
+        char __user *   nq_prime;
+        char __user *   u_mult_inv;
+};
+
+/**
+ * CPRBX
+ *        Note that all shorts and ints are big-endian.
+ *        All pointer fields are 16 bytes long, and mean nothing.
+ *
+ *        A request CPRB is followed by a request_parameter_block.
+ *
+ *        The request (or reply) parameter block is organized thus:
+ *          function code
+ *          VUD block
+ *          key block
+ */
+struct CPRBX {
+        unsigned short  cprb_len;       /* CPRB length        220        */
+        unsigned char   cprb_ver_id;    /* CPRB version id.   0x02       */
+        unsigned char   pad_000[3];     /* Alignment pad bytes           */
+        unsigned char   func_id[2];     /* function id        0x5432     */
+        unsigned char   cprb_flags[4];  /* Flags                         */
+        unsigned int    req_parml;      /* request parameter buffer len  */
+        unsigned int    req_datal;      /* request data buffer           */
+        unsigned int    rpl_msgbl;      /* reply  message block length   */
+        unsigned int    rpld_parml;     /* replied parameter block len   */
+        unsigned int    rpl_datal;      /* reply data block len          */
+        unsigned int    rpld_datal;     /* replied data block len        */
+        unsigned int    req_extbl;      /* request extension block len   */
+        unsigned char   pad_001[4];     /* reserved                      */
+        unsigned int    rpld_extbl;     /* replied extension block len   */
+        unsigned char   padx000[16 - sizeof (char *)];
+        unsigned char * req_parmb;      /* request parm block 'address'  */
+        unsigned char   padx001[16 - sizeof (char *)];
+        unsigned char * req_datab;      /* request data block 'address'  */
+        unsigned char   padx002[16 - sizeof (char *)];
+        unsigned char * rpl_parmb;      /* reply parm block 'address'    */
+        unsigned char   padx003[16 - sizeof (char *)];
+        unsigned char * rpl_datab;      /* reply data block 'address'    */
+        unsigned char   padx004[16 - sizeof (char *)];
+        unsigned char * req_extb;       /* request extension block 'addr'*/
+        unsigned char   padx005[16 - sizeof (char *)];
+        unsigned char * rpl_extb;       /* reply extension block 'address'*/
+        unsigned short  ccp_rtcode;     /* server return code            */
+        unsigned short  ccp_rscode;     /* server reason code            */
+        unsigned int    mac_data_len;   /* Mac Data Length               */
+        unsigned char   logon_id[8];    /* Logon Identifier              */
+        unsigned char   mac_value[8];   /* Mac Value                     */
+        unsigned char   mac_content_flgs;/* Mac content flag byte        */
+        unsigned char   pad_002;        /* Alignment                     */
+        unsigned short  domain;         /* Domain                        */
+        unsigned char   usage_domain[4];/* Usage domain                  */
+        unsigned char   cntrl_domain[4];/* Control domain                */
+        unsigned char   S390enf_mask[4];/* S/390 enforcement mask        */
+        unsigned char   pad_004[36];    /* reserved                      */
+} __attribute__((packed));
+
+/**
+ * xcRB
+ */
+struct ica_xcRB {
+        unsigned short  agent_ID;
+        unsigned int    user_defined;
+        unsigned short  request_ID;
+        unsigned int    request_control_blk_length;
+        unsigned char   padding1[16 - sizeof (char *)];
+        char __user *   request_control_blk_addr;
+        unsigned int    request_data_length;
+        char            padding2[16 - sizeof (char *)];
+        char __user *   request_data_address;
+        unsigned int    reply_control_blk_length;
+        char            padding3[16 - sizeof (char *)];
+        char __user *   reply_control_blk_addr;
+        unsigned int    reply_data_length;
+        char            padding4[16 - sizeof (char *)];
+        char __user *   reply_data_addr;
+        unsigned short  priority_window;
+        unsigned int    status;
+} __attribute__((packed));
+#define AUTOSELECT ((unsigned int)0xFFFFFFFF)
+
+#define ZCRYPT_IOCTL_MAGIC 'z'
+
+/**
+ * Interface notes:
+ *
+ * The ioctl()s which are implemented (along with relevant details)
+ * are:
+ *
+ *   ICARSAMODEXPO
+ *     Perform an RSA operation using a Modulus-Exponent pair
+ *     This takes an ica_rsa_modexpo struct as its arg.
+ *
+ *     NOTE: please refer to the comments preceding this structure
+ *           for the implementation details for the contents of the
+ *           block
+ *
+ *   ICARSACRT
+ *     Perform an RSA operation using a Chinese-Remainder Theorem key
+ *     This takes an ica_rsa_modexpo_crt struct as its arg.
+ *
+ *     NOTE: please refer to the comments preceding this structure
+ *           for the implementation details for the contents of the
+ *           block
+ *
+ *   ZSECSENDCPRB
+ *     Send an arbitrary CPRB to a crypto card.
+ *
+ *   Z90STAT_STATUS_MASK
+ *     Return an 64 element array of unsigned chars for the status of
+ *     all devices.
+ *       0x01: PCICA
+ *       0x02: PCICC
+ *       0x03: PCIXCC_MCL2
+ *       0x04: PCIXCC_MCL3
+ *       0x05: CEX2C
+ *       0x06: CEX2A
+ *       0x0d: device is disabled via the proc filesystem
+ *
+ *   Z90STAT_QDEPTH_MASK
+ *     Return an 64 element array of unsigned chars for the queue
+ *     depth of all devices.
+ *
+ *   Z90STAT_PERDEV_REQCNT
+ *     Return an 64 element array of unsigned integers for the number
+ *     of successfully completed requests per device since the device
+ *     was detected and made available.
+ *
+ *   Z90STAT_REQUESTQ_COUNT
+ *     Return an integer count of the number of entries waiting to be
+ *     sent to a device.
+ *
+ *   Z90STAT_PENDINGQ_COUNT
+ *     Return an integer count of the number of entries sent to all
+ *     devices awaiting the reply.
+ *
+ *   Z90STAT_TOTALOPEN_COUNT
+ *     Return an integer count of the number of open file handles.
+ *
+ *   Z90STAT_DOMAIN_INDEX
+ *     Return the integer value of the Cryptographic Domain.
+ *
+ *   The following ioctls are deprecated and should be no longer used:
+ *
+ *   Z90STAT_TOTALCOUNT
+ *     Return an integer count of all device types together.
+ *
+ *   Z90STAT_PCICACOUNT
+ *     Return an integer count of all PCICAs.
+ *
+ *   Z90STAT_PCICCCOUNT
+ *     Return an integer count of all PCICCs.
+ *
+ *   Z90STAT_PCIXCCMCL2COUNT
+ *     Return an integer count of all MCL2 PCIXCCs.
+ *
+ *   Z90STAT_PCIXCCMCL3COUNT
+ *     Return an integer count of all MCL3 PCIXCCs.
+ *
+ *   Z90STAT_CEX2CCOUNT
+ *     Return an integer count of all CEX2Cs.
+ *
+ *   Z90STAT_CEX2ACOUNT
+ *     Return an integer count of all CEX2As.
+ *
+ *   ICAZ90STATUS
+ *     Return some device driver status in a ica_z90_status struct
+ *     This takes an ica_z90_status struct as its arg.
+ *
+ *   Z90STAT_PCIXCCCOUNT
+ *     Return an integer count of all PCIXCCs (MCL2 + MCL3).
+ *     This is DEPRECATED now that MCL3 PCIXCCs are treated differently from
+ *     MCL2 PCIXCCs.
+ */
+
+/**
+ * Supported ioctl calls
+ */
+#define ICARSAMODEXPO   _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x05, 0)
+#define ICARSACRT       _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x06, 0)
+#define ZSECSENDCPRB    _IOC(_IOC_READ|_IOC_WRITE, ZCRYPT_IOCTL_MAGIC, 0x81, 0)
+
+/* New status calls */
+#define Z90STAT_TOTALCOUNT      _IOR(ZCRYPT_IOCTL_MAGIC, 0x40, int)
+#define Z90STAT_PCICACOUNT      _IOR(ZCRYPT_IOCTL_MAGIC, 0x41, int)
+#define Z90STAT_PCICCCOUNT      _IOR(ZCRYPT_IOCTL_MAGIC, 0x42, int)
+#define Z90STAT_PCIXCCMCL2COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4b, int)
+#define Z90STAT_PCIXCCMCL3COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x4c, int)
+#define Z90STAT_CEX2CCOUNT      _IOR(ZCRYPT_IOCTL_MAGIC, 0x4d, int)
+#define Z90STAT_CEX2ACOUNT      _IOR(ZCRYPT_IOCTL_MAGIC, 0x4e, int)
+#define Z90STAT_REQUESTQ_COUNT  _IOR(ZCRYPT_IOCTL_MAGIC, 0x44, int)
+#define Z90STAT_PENDINGQ_COUNT  _IOR(ZCRYPT_IOCTL_MAGIC, 0x45, int)
+#define Z90STAT_TOTALOPEN_COUNT _IOR(ZCRYPT_IOCTL_MAGIC, 0x46, int)
+#define Z90STAT_DOMAIN_INDEX    _IOR(ZCRYPT_IOCTL_MAGIC, 0x47, int)
+#define Z90STAT_STATUS_MASK     _IOR(ZCRYPT_IOCTL_MAGIC, 0x48, char[64])
+#define Z90STAT_QDEPTH_MASK     _IOR(ZCRYPT_IOCTL_MAGIC, 0x49, char[64])
+#define Z90STAT_PERDEV_REQCNT   _IOR(ZCRYPT_IOCTL_MAGIC, 0x4a, int[64])
+
+#endif /* __ASM_S390_ZCRYPT_H */
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index d003a6e16afb..328a20e880b5 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -1732,3 +1732,40 @@ compat_sys_timerfd_gettime_wrapper:
         lgfr    %r2,%r2                 # int
         llgtr   %r3,%r3                 # struct compat_itimerspec *
         jg      compat_sys_timerfd_gettime
+
+        .globl compat_sys_signalfd4_wrapper
+compat_sys_signalfd4_wrapper:
+        lgfr    %r2,%r2                 # int
+        llgtr   %r3,%r3                 # compat_sigset_t *
+        llgfr   %r4,%r4                 # compat_size_t
+        lgfr    %r5,%r5                 # int
+        jg      compat_sys_signalfd4
+
+        .globl sys_eventfd2_wrapper
+sys_eventfd2_wrapper:
+        llgfr   %r2,%r2                 # unsigned int
+        lgfr    %r3,%r3                 # int
+        jg      sys_eventfd2
+
+        .globl  sys_inotify_init1_wrapper
+sys_inotify_init1_wrapper:
+        lgfr    %r2,%r2                 # int
+        jg      sys_inotify_init1
+
+        .globl  sys_pipe2_wrapper
+sys_pipe2_wrapper:
+        llgtr   %r2,%r2                 # u32 *
+        lgfr    %r3,%r3                 # int
+        jg      sys_pipe2               # branch to system call
+
+        .globl  sys_dup3_wrapper
+sys_dup3_wrapper:
+        llgfr   %r2,%r2                 # unsigned int
+        llgfr   %r3,%r3                 # unsigned int
+        lgfr    %r4,%r4                 # int
+        jg      sys_dup3                # branch to system call
+
+        .globl  sys_epoll_create1_wrapper
+sys_epoll_create1_wrapper:
+        lgfr    %r2,%r2                 # int
+        jg      sys_epoll_create1       # branch to system call
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index 54b2779b5e2f..2dcf590faba6 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -1705,7 +1705,10 @@ void __init setup_ipl(void)
 
 void __init ipl_update_parameters(void)
 {
-        if (diag308(DIAG308_STORE, &ipl_block) == DIAG308_RC_OK)
+        int rc;
+
+        rc = diag308(DIAG308_STORE, &ipl_block);
+        if ((rc == DIAG308_RC_OK) || (rc == DIAG308_RC_NOCONFIG))
                 diag308_set_works = 1;
 }
 
diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c
index 4f82e5b5f879..569079ec4ff0 100644
--- a/arch/s390/kernel/kprobes.c
+++ b/arch/s390/kernel/kprobes.c
@@ -197,7 +197,7 @@ void __kprobes arch_arm_kprobe(struct kprobe *p)
         args.new = BREAKPOINT_INSTRUCTION;
 
         kcb->kprobe_status = KPROBE_SWAP_INST;
-        stop_machine_run(swap_instruction, &args, NR_CPUS);
+        stop_machine(swap_instruction, &args, NULL);
         kcb->kprobe_status = status;
 }
 
@@ -212,7 +212,7 @@ void __kprobes arch_disarm_kprobe(struct kprobe *p)
         args.new = p->opcode;
 
         kcb->kprobe_status = KPROBE_SWAP_INST;
-        stop_machine_run(swap_instruction, &args, NR_CPUS);
+        stop_machine(swap_instruction, &args, NULL);
         kcb->kprobe_status = status;
 }
 
@@ -331,7 +331,7 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
                  * No kprobe at this address. The fault has not been
                  * caused by a kprobe breakpoint. The race of breakpoint
                  * vs. kprobe remove does not exist because on s390 we
-                 * use stop_machine_run to arm/disarm the breakpoints.
+                 * use stop_machine to arm/disarm the breakpoints.
                  */
                 goto no_kprobe;
 
diff --git a/arch/s390/kernel/mem_detect.c b/arch/s390/kernel/mem_detect.c
index 18ed7abe16c5..9872999c66d1 100644
--- a/arch/s390/kernel/mem_detect.c
+++ b/arch/s390/kernel/mem_detect.c
@@ -9,27 +9,6 @@
 #include <asm/sclp.h>
 #include <asm/setup.h>
 
-static int memory_fast_detect(struct mem_chunk *chunk)
-{
-        unsigned long val0 = 0;
-        unsigned long val1 = 0xc;
-        int rc = -EOPNOTSUPP;
-
-        if (ipl_flags & IPL_NSS_VALID)
-                return -EOPNOTSUPP;
-        asm volatile(
-                "       diag    %1,%2,0x260\n"
-                "0:     lhi     %0,0\n"
-                "1:\n"
-                EX_TABLE(0b,1b)
-                : "+d" (rc), "+d" (val0), "+d" (val1) : : "cc");
-
-        if (rc || val0 != val1)
-                return -EOPNOTSUPP;
-        chunk->size = val0 + 1;
-        return 0;
-}
-
 static inline int tprot(unsigned long addr)
 {
         int rc = -EFAULT;
@@ -84,8 +63,6 @@ void detect_memory_layout(struct mem_chunk chunk[])
         unsigned long flags, cr0;
 
         memset(chunk, 0, MEMORY_CHUNKS * sizeof(struct mem_chunk));
-        if (memory_fast_detect(&chunk[0]) == 0)
-                return;
         /* Disable IRQs, DAT and low address protection so tprot does the
          * right thing and we don't get scheduled away with low address
          * protection disabled.
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index c87ec687d4c6..c66d35e55142 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -330,3 +330,9 @@ SYSCALL(sys_eventfd,sys_eventfd,sys_eventfd_wrapper)
 SYSCALL(sys_timerfd_create,sys_timerfd_create,sys_timerfd_create_wrapper)
 SYSCALL(sys_timerfd_settime,sys_timerfd_settime,compat_sys_timerfd_settime_wrapper) /* 320 */
 SYSCALL(sys_timerfd_gettime,sys_timerfd_gettime,compat_sys_timerfd_gettime_wrapper)
+SYSCALL(sys_signalfd4,sys_signalfd4,compat_sys_signalfd4_wrapper)
+SYSCALL(sys_eventfd2,sys_eventfd2,sys_eventfd2_wrapper)
+SYSCALL(sys_inotify_init1,sys_inotify_init1,sys_inotify_init1_wrapper)
+SYSCALL(sys_pipe2,sys_pipe2,sys_pipe2_wrapper) /* 325 */
+SYSCALL(sys_dup3,sys_dup3,sys_dup3_wrapper)
+SYSCALL(sys_epoll_create1,sys_epoll_create1,sys_epoll_create1_wrapper)
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index ab70d9bd9261..ca114fe46ffb 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -1348,7 +1348,7 @@ early_param("stp", early_parse_stp);
 /*
  * Reset STP attachment.
  */
-static void stp_reset(void)
+static void __init stp_reset(void)
 {
         int rc;
 
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index 2e2d2ffb6a07..d1faf5c54405 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -158,6 +158,7 @@ static int handle_stfl(struct kvm_vcpu *vcpu)
 
         vcpu->stat.instruction_stfl++;
         facility_list &= ~(1UL<<24); /* no stfle */
+        facility_list &= ~(1UL<<23); /* no large pages */
 
         rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list),
                            &facility_list, sizeof(facility_list));
diff --git a/arch/s390/lib/delay.c b/arch/s390/lib/delay.c
index eae21a8ac72d..fc6ab6094df8 100644
--- a/arch/s390/lib/delay.c
+++ b/arch/s390/lib/delay.c
@@ -43,7 +43,7 @@ void __udelay(unsigned long usecs)
                 local_bh_disable();
         local_irq_save(flags);
         if (raw_irqs_disabled_flags(flags)) {
-                old_cc = S390_lowcore.clock_comparator;
+                old_cc = local_tick_disable();
                 S390_lowcore.clock_comparator = -1ULL;
                 __ctl_store(cr0, 0, 0);
                 dummy = (cr0 & 0xffff00e0) | 0x00000800;
@@ -65,7 +65,7 @@ void __udelay(unsigned long usecs)
 
         if (raw_irqs_disabled_flags(flags)) {
                 __ctl_load(cr0, 0, 0);
-                S390_lowcore.clock_comparator = old_cc;
+                local_tick_enable(old_cc);
         }
         if (!irq_context)
                 _local_bh_enable();
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 4993b0f594eb..1169130a97ef 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -179,7 +179,7 @@ int arch_add_memory(int nid, u64 start, u64 size)
         int rc;
 
         pgdat = NODE_DATA(nid);
-        zone = pgdat->node_zones + ZONE_NORMAL;
+        zone = pgdat->node_zones + ZONE_MOVABLE;
         rc = vmem_add_mapping(start, size);
         if (rc)
                 return rc;
@@ -189,3 +189,14 @@ int arch_add_memory(int nid, u64 start, u64 size)
         return rc;
 }
 #endif /* CONFIG_MEMORY_HOTPLUG */
+
+#ifdef CONFIG_MEMORY_HOTREMOVE
+int remove_memory(u64 start, u64 size)
+{
+        unsigned long start_pfn, end_pfn;
+
+        start_pfn = PFN_DOWN(start);
+        end_pfn = start_pfn + PFN_DOWN(size);
+        return offline_pages(start_pfn, end_pfn, 120 * HZ);
+}
+#endif /* CONFIG_MEMORY_HOTREMOVE */
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8879938f3356..5131d50f851a 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -11,6 +11,7 @@ config SUPERH
         select HAVE_CLK
         select HAVE_IDE
         select HAVE_OPROFILE
+        select HAVE_GENERIC_DMA_COHERENT
         help
           The SuperH is a RISC processor targeted for use in embedded systems
           and consumer electronics; it was also used in the Sega Dreamcast
@@ -23,6 +24,11 @@ config SUPERH32
 config SUPERH64
         def_bool y if CPU_SH5
 
+config ARCH_DEFCONFIG
+        string
+        default "arch/sh/configs/shx3_defconfig" if SUPERH32
+        default "arch/sh/configs/cayman_defconfig" if SUPERH64
+
 config RWSEM_GENERIC_SPINLOCK
         def_bool y
 
@@ -42,6 +48,9 @@ config GENERIC_HWEIGHT
 config GENERIC_HARDIRQS
         def_bool y
 
+config GENERIC_HARDIRQS_NO__DO_IRQ
+        def_bool y
+
 config GENERIC_IRQ_PROBE
         def_bool y
 
@@ -57,6 +66,10 @@ config GENERIC_TIME
 config GENERIC_CLOCKEVENTS
         def_bool n
 
+config GENERIC_LOCKBREAK
+        def_bool y
+        depends on SMP && PREEMPT
+
 config SYS_SUPPORTS_PM
         bool
 
@@ -88,9 +101,6 @@ config ARCH_HAS_ILOG2_U64
 config ARCH_NO_VIRT_TO_BUS
         def_bool y
 
-config ARCH_SUPPORTS_AOUT
-        def_bool y
-
 config IO_TRAPPED
         bool
 
@@ -347,219 +357,10 @@ config CPU_SUBTYPE_SH5_103
 endchoice
 
 source "arch/sh/mm/Kconfig"
+ 
 source "arch/sh/Kconfig.cpu"
 
-menu "Board support"
-
-config SOLUTION_ENGINE
-        bool
-
-config SH_SOLUTION_ENGINE
-        bool "SolutionEngine"
-        select SOLUTION_ENGINE
-        select CPU_HAS_IPR_IRQ
-        depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \
-          CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
-          CPU_SUBTYPE_SH7750R 
-        help
-          Select SolutionEngine if configuring for a Hitachi SH7705, SH7709,
-          SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board.
-
-config SH_7206_SOLUTION_ENGINE
-        bool "SolutionEngine7206"
-        select SOLUTION_ENGINE
-        depends on CPU_SUBTYPE_SH7206
-        help
-          Select 7206 SolutionEngine if configuring for a Hitachi SH7206
-          evaluation board.
-
-config SH_7619_SOLUTION_ENGINE
-        bool "SolutionEngine7619"
-        select SOLUTION_ENGINE
-        depends on CPU_SUBTYPE_SH7619
-        help
-          Select 7619 SolutionEngine if configuring for a Hitachi SH7619
-          evaluation board.
-        
-config SH_7721_SOLUTION_ENGINE
-        bool "SolutionEngine7721"
-        select SOLUTION_ENGINE
-        depends on CPU_SUBTYPE_SH7721
-        help
-          Select 7721 SolutionEngine if configuring for a Hitachi SH7721
-          evaluation board.
-
-config SH_7722_SOLUTION_ENGINE
-        bool "SolutionEngine7722"
-        select SOLUTION_ENGINE
-        depends on CPU_SUBTYPE_SH7722
-        help
-          Select 7722 SolutionEngine if configuring for a Hitachi SH772
-          evaluation board.
-
-config SH_7751_SOLUTION_ENGINE
-        bool "SolutionEngine7751"
-        select SOLUTION_ENGINE
-        select CPU_HAS_IPR_IRQ
-        depends on CPU_SUBTYPE_SH7751
-        help
-          Select 7751 SolutionEngine if configuring for a Hitachi SH7751
-          evaluation board.
-          
-config SH_7780_SOLUTION_ENGINE
-        bool "SolutionEngine7780"
-        select SOLUTION_ENGINE
-        select SYS_SUPPORTS_PCI
-        depends on CPU_SUBTYPE_SH7780
-        help
-          Select 7780 SolutionEngine if configuring for a Renesas SH7780
-          evaluation board.
-
-config SH_7343_SOLUTION_ENGINE
-        bool "SolutionEngine7343"
-        select SOLUTION_ENGINE
-        depends on CPU_SUBTYPE_SH7343
-        help
-          Select 7343 SolutionEngine if configuring for a Hitachi
-          SH7343 (SH-Mobile 3AS) evaluation board.
-
-config SH_7751_SYSTEMH
-        bool "SystemH7751R"
-        depends on CPU_SUBTYPE_SH7751R
-        help
-          Select SystemH if you are configuring for a Renesas SystemH
-          7751R evaluation board.
-
-config SH_HP6XX
-        bool "HP6XX"
-        select SYS_SUPPORTS_APM_EMULATION
-        select HD6446X_SERIES
-        depends on CPU_SUBTYPE_SH7709
-        help
-          Select HP6XX if configuring for a HP jornada HP6xx.
-          More information (hardware only) at
-          <http://www.hp.com/jornada/>.
-
-config SH_DREAMCAST
-        bool "Dreamcast"
-        select SYS_SUPPORTS_PCI
-        depends on CPU_SUBTYPE_SH7091
-        help
-          Select Dreamcast if configuring for a SEGA Dreamcast.
-          More information at <http://www.linux-sh.org>
-
-config SH_SH03
-        bool "Interface CTP/PCI-SH03"
-        depends on CPU_SUBTYPE_SH7751
-        select CPU_HAS_IPR_IRQ
-        select SYS_SUPPORTS_PCI
-        help
-          CTP/PCI-SH03 is a CPU module computer that is produced
-          by Interface Corporation.
-          More information at <http://www.interface.co.jp>
-
-config SH_SECUREEDGE5410
-        bool "SecureEdge5410"
-        depends on CPU_SUBTYPE_SH7751R
-        select CPU_HAS_IPR_IRQ
-        select SYS_SUPPORTS_PCI
-        help
-          Select SecureEdge5410 if configuring for a SnapGear SH board.
-          This includes both the OEM SecureEdge products as well as the
-          SME product line.
-
-config SH_RTS7751R2D
-        bool "RTS7751R2D"
-        depends on CPU_SUBTYPE_SH7751R
-        select SYS_SUPPORTS_PCI
-        select IO_TRAPPED
-        help
-          Select RTS7751R2D if configuring for a Renesas Technology
-          Sales SH-Graphics board.
-
-config SH_SDK7780
-        bool "SDK7780R3"
-        depends on CPU_SUBTYPE_SH7780
-        select SYS_SUPPORTS_PCI
-        help
-          Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3
-          evaluation board.
-
-config SH_HIGHLANDER
-        bool "Highlander"
-        depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
-        select SYS_SUPPORTS_PCI
-        select IO_TRAPPED
-
-config SH_MIGOR
-        bool "Migo-R"
-        depends on CPU_SUBTYPE_SH7722
-        help
-          Select Migo-R if configuring for the SH7722 Migo-R platform
-          by Renesas System Solutions Asia Pte. Ltd.
-
-config SH_EDOSK7705
-        bool "EDOSK7705"
-        depends on CPU_SUBTYPE_SH7705
-
-config SH_SH4202_MICRODEV
-        bool "SH4-202 MicroDev"
-        depends on CPU_SUBTYPE_SH4_202
-        help
-          Select SH4-202 MicroDev if configuring for a SuperH MicroDev board
-          with an SH4-202 CPU.
-
-config SH_LANDISK
-        bool "LANDISK"
-        depends on CPU_SUBTYPE_SH7751R
-        select SYS_SUPPORTS_PCI
-        help
-          I-O DATA DEVICE, INC. "LANDISK Series" support.
-
-config SH_TITAN
-        bool "TITAN"
-        depends on CPU_SUBTYPE_SH7751R
-        select CPU_HAS_IPR_IRQ
-        select SYS_SUPPORTS_PCI
-        help
-          Select Titan if you are configuring for a Nimble Microsystems
-          NetEngine NP51R.
-
-config SH_SHMIN
-        bool "SHMIN"
-        depends on CPU_SUBTYPE_SH7706
-        select CPU_HAS_IPR_IRQ
-        help
-          Select SHMIN if configuring for the SHMIN board.
-
-config SH_LBOX_RE2
-        bool "L-BOX RE2"
-        depends on CPU_SUBTYPE_SH7751R
-        select SYS_SUPPORTS_PCI
-        help
-          Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
-
-config SH_X3PROTO
-        bool "SH-X3 Prototype board"
-        depends on CPU_SUBTYPE_SHX3
-
-config SH_MAGIC_PANEL_R2
-        bool "Magic Panel R2"
-        depends on CPU_SUBTYPE_SH7720
-        help
-          Select Magic Panel R2 if configuring for Magic Panel R2.
-
-config SH_CAYMAN
-        bool "Hitachi Cayman"
-        depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
-        select SYS_SUPPORTS_PCI
-
-endmenu
-
-source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
-source "arch/sh/boards/renesas/r7780rp/Kconfig"
-source "arch/sh/boards/renesas/sdk7780/Kconfig"
-source "arch/sh/boards/magicpanelr2/Kconfig"
+source "arch/sh/boards/Kconfig"
 
 menu "Timer and clock configuration"
 
@@ -686,6 +487,23 @@ config CRASH_DUMP
 
           For more details see Documentation/kdump/kdump.txt
 
+config SECCOMP
+        bool "Enable seccomp to safely compute untrusted bytecode"
+        depends on PROC_FS
+        default y
+        help
+          This kernel feature is useful for number crunching applications
+          that may need to compute untrusted bytecode during their
+          execution. By using pipes or other transports made available to
+          the process as file descriptors supporting the read/write
+          syscalls, it's possible to isolate those applications in
+          their own address space using seccomp. Once seccomp is
+          enabled via prctl, it cannot be disabled and the task is only
+          allowed to execute a few safe syscalls defined by each seccomp
+          mode.
+
+          If unsure, say N.
+
 config SMP
         bool "Symmetric multi-processing support"
         depends on SYS_SUPPORTS_SMP
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 0f4549860226..4d2d102e00d5 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -36,7 +36,8 @@ config EARLY_SCIF_CONSOLE_PORT
         default "0xff804000" if CPU_SUBTYPE_MXG
         default "0xffc30000" if CPU_SUBTYPE_SHX3
         default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
-                                CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
+                                CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
+                                CPU_SUBTYPE_SH7343
         default "0xffe80000" if CPU_SH4
         default "0xffea0000" if CPU_SUBTYPE_SH7785
         default "0xfffe8000" if CPU_SUBTYPE_SH7203
@@ -181,7 +182,7 @@ if SUPERH64
 
 config SH64_PROC_ASIDS
         bool "Debug: report ASIDs through /proc/asids"
-        depends on PROC_FS
+        depends on PROC_FS && MMU
 
 config SH64_SR_WATCH
         bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index fb7b1b15e392..01d85c74481d 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -68,7 +68,7 @@ OBJCOPYFLAGS	:= -O binary -R .note -R .note.gnu.build-id -R .comment \
 defaultimage-$(CONFIG_SUPERH32) := zImage
 
 # Set some sensible Kbuild defaults
-KBUILD_DEFCONFIG        := r7780mp_defconfig
+KBUILD_DEFCONFIG        := shx3_defconfig
 KBUILD_IMAGE            := $(defaultimage-y)
 
 #
@@ -91,47 +91,32 @@ LDFLAGS_vmlinux		+= --defsym 'jiffies=jiffies_64+4'
 LDFLAGS                 += -EB
 endif
 
-KBUILD_CFLAGS           += -pipe $(cflags-y)
-KBUILD_AFLAGS           += $(cflags-y)
-
 head-y                  := arch/sh/kernel/init_task.o
 head-$(CONFIG_SUPERH32) += arch/sh/kernel/head_32.o
 head-$(CONFIG_SUPERH64) += arch/sh/kernel/head_64.o
 
-LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
-
-core-y                          += arch/sh/kernel/ arch/sh/mm/
+core-y                          += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
 core-$(CONFIG_SH_FPU_EMU)       += arch/sh/math-emu/
 
-# Boards
-machdir-$(CONFIG_SH_SOLUTION_ENGINE)            += se/770x
-machdir-$(CONFIG_SH_7722_SOLUTION_ENGINE)       += se/7722
-machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE)       += se/7751
-machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE)       += se/7780
-machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE)       += se/7343
-machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE)       += se/7721
-machdir-$(CONFIG_SH_HP6XX)                      += hp6xx
-machdir-$(CONFIG_SH_DREAMCAST)                  += dreamcast
-machdir-$(CONFIG_SH_SH03)                       += sh03
-machdir-$(CONFIG_SH_SECUREEDGE5410)             += snapgear
-machdir-$(CONFIG_SH_RTS7751R2D)                 += renesas/rts7751r2d
-machdir-$(CONFIG_SH_7751_SYSTEMH)               += renesas/systemh
-machdir-$(CONFIG_SH_EDOSK7705)                  += renesas/edosk7705
-machdir-$(CONFIG_SH_HIGHLANDER)                 += renesas/r7780rp
-machdir-$(CONFIG_SH_MIGOR)                      += renesas/migor
-machdir-$(CONFIG_SH_SDK7780)                    += renesas/sdk7780
-machdir-$(CONFIG_SH_X3PROTO)                    += renesas/x3proto
-machdir-$(CONFIG_SH_SH4202_MICRODEV)            += superh/microdev
-machdir-$(CONFIG_SH_LANDISK)                    += landisk
-machdir-$(CONFIG_SH_TITAN)                      += titan
-machdir-$(CONFIG_SH_SHMIN)                      += shmin
-machdir-$(CONFIG_SH_7206_SOLUTION_ENGINE)       += se/7206
-machdir-$(CONFIG_SH_7619_SOLUTION_ENGINE)       += se/7619
-machdir-$(CONFIG_SH_LBOX_RE2)                   += lboxre2
-machdir-$(CONFIG_SH_MAGIC_PANEL_R2)             += magicpanelr2
-machdir-$(CONFIG_SH_CAYMAN)                     += cayman
-
-incdir-y        := $(notdir $(machdir-y))
+# Mach groups
+machdir-$(CONFIG_SOLUTION_ENGINE)               += mach-se
+machdir-$(CONFIG_SH_HP6XX)                      += mach-hp6xx
+machdir-$(CONFIG_SH_DREAMCAST)                  += mach-dreamcast
+machdir-$(CONFIG_SH_SH03)                       += mach-sh03
+machdir-$(CONFIG_SH_SECUREEDGE5410)             += mach-snapgear
+machdir-$(CONFIG_SH_RTS7751R2D)                 += mach-r2d
+machdir-$(CONFIG_SH_7751_SYSTEMH)               += mach-systemh
+machdir-$(CONFIG_SH_EDOSK7705)                  += mach-edosk7705
+machdir-$(CONFIG_SH_HIGHLANDER)                 += mach-highlander
+machdir-$(CONFIG_SH_MIGOR)                      += mach-migor
+machdir-$(CONFIG_SH_SDK7780)                    += mach-sdk7780
+machdir-$(CONFIG_SH_X3PROTO)                    += mach-x3proto
+machdir-$(CONFIG_SH_SH7763RDP)                  += mach-sh7763rdp
+machdir-$(CONFIG_SH_SH4202_MICRODEV)            += mach-microdev
+machdir-$(CONFIG_SH_LANDISK)                    += mach-landisk
+machdir-$(CONFIG_SH_TITAN)                      += mach-titan
+machdir-$(CONFIG_SH_LBOX_RE2)                   += mach-lboxre2
+machdir-$(CONFIG_SH_CAYMAN)                     += mach-cayman
 
 ifneq ($(machdir-y),)
 core-y  += $(addprefix arch/sh/boards/, \
@@ -141,67 +126,40 @@ endif
 # Companion chips
 core-$(CONFIG_HD6446X_SERIES)   += arch/sh/cchips/hd6446x/
 
-cpuincdir-$(CONFIG_CPU_SH2)     := cpu-sh2
-cpuincdir-$(CONFIG_CPU_SH2A)    := cpu-sh2a
-cpuincdir-$(CONFIG_CPU_SH3)     := cpu-sh3
-cpuincdir-$(CONFIG_CPU_SH4)     := cpu-sh4
-cpuincdir-$(CONFIG_CPU_SH5)     := cpu-sh5
-
-libs-$(CONFIG_SUPERH32)         := arch/sh/lib/ $(libs-y)
-libs-$(CONFIG_SUPERH64)         := arch/sh/lib64/ $(libs-y)
-libs-y                          += $(LIBGCC)
+#
+# CPU header paths
+#
+# These are ordered by optimization level. A CPU family that is a subset
+# of another (ie, SH-2A / SH-2), is picked up first, with increasing
+# levels of genericness if nothing more suitable is situated in the
+# hierarchy.
+#
+# As an example, in order of preference, SH-2A > SH-2 > common definitions.
+#
+cpuincdir-$(CONFIG_CPU_SH2A)    += cpu-sh2a
+cpuincdir-$(CONFIG_CPU_SH2)     += cpu-sh2
+cpuincdir-$(CONFIG_CPU_SH3)     += cpu-sh3
+cpuincdir-$(CONFIG_CPU_SH4)     += cpu-sh4
+cpuincdir-$(CONFIG_CPU_SH5)     += cpu-sh5
+cpuincdir-y                     += cpu-common   # Must be last
 
 drivers-y                       += arch/sh/drivers/
 drivers-$(CONFIG_OPROFILE)      += arch/sh/oprofile/
 
 boot := arch/sh/boot
 
-ifneq ($(KBUILD_SRC),)
-incdir-prefix   := $(srctree)/include/asm-sh/
-else
-incdir-prefix   :=
-endif
+cflags-y        += $(foreach d, $(cpuincdir-y), -Iarch/sh/include/$(d)) \
+                   $(foreach d, $(machdir-y), -Iarch/sh/include/$(d))
 
-#       Update machine arch and proc symlinks if something which affects
-#       them changed.  We use .arch and .mach to indicate when they were
-#       updated last, otherwise make uses the target directory mtime.
+KBUILD_CFLAGS           += -pipe $(cflags-y)
+KBUILD_CPPFLAGS         += $(cflags-y)
+KBUILD_AFLAGS           += $(cflags-y)
 
-include/asm-sh/.cpu: $(wildcard include/config/cpu/*.h) \
-                     include/config/auto.conf FORCE
-        @echo '  SYMLINK include/asm-sh/cpu -> include/asm-sh/$(cpuincdir-y)'
-        $(Q)if [ ! -d include/asm-sh ]; then mkdir -p include/asm-sh; fi
-        $(Q)ln -fsn $(incdir-prefix)$(cpuincdir-y) include/asm-sh/cpu
-        @touch $@
+LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
 
-#       Most boards have their own mach directories.  For the ones that
-#       don't, just reference the parent directory so the semantics are
-#       kept roughly the same.
-#
-#       When multiple boards are compiled in at the same time, preference
-#       for the mach link is given to whichever has a directory for its
-#       headers. However, this is only a workaround until platforms that
-#       can live in the same kernel image back away from relying on the
-#       mach link.
-
-include/asm-sh/.mach: $(wildcard include/config/sh/*.h) \
-                      include/config/auto.conf FORCE
-        $(Q)if [ ! -d include/asm-sh ]; then mkdir -p include/asm-sh; fi
-        $(Q)rm -f include/asm-sh/mach
-        $(Q)for i in $(incdir-y); do \
-        if [ -d $(srctree)/include/asm-sh/$$i ]; then \
-                echo -n '  SYMLINK include/asm-sh/mach -> '; \
-                echo -e "include/asm-sh/$$i"; \
-                ln -fsn $(incdir-prefix)$$i \
-                        include/asm-sh/mach; \
-        else \
-                if [ ! -d include/asm-sh/mach ]; then \
-                        echo -n '  SYMLINK include/asm-sh/mach -> '; \
-                        echo -e 'include/asm-sh'; \
-                        ln -fsn $(incdir-prefix)../asm-sh include/asm-sh/mach; \
-                fi; \
-        fi; \
-        done
-        @touch $@
+libs-$(CONFIG_SUPERH32)         := arch/sh/lib/ $(libs-y)
+libs-$(CONFIG_SUPERH64)         := arch/sh/lib64/ $(libs-y)
+libs-y                          += $(LIBGCC)
 
 PHONY += maketools FORCE
 
@@ -215,8 +173,7 @@ zImage uImage uImage.srec vmlinux.srec: vmlinux
 
 compressed: zImage
 
-archprepare: include/asm-sh/.cpu include/asm-sh/.mach maketools \
-             arch/sh/lib64/syscalltab.h
+archprepare: maketools arch/sh/lib64/syscalltab.h
 
 archclean:
         $(Q)$(MAKE) $(clean)=$(boot)
@@ -258,6 +215,4 @@ arch/sh/lib64/syscalltab.h: arch/sh/kernel/syscalls_64.S
         $(call filechk,gen-syscalltab)
 
 CLEAN_FILES += arch/sh/lib64/syscalltab.h \
-               include/asm-sh/machtypes.h \
-               include/asm-sh/cpu include/asm-sh/.cpu \
-               include/asm-sh/mach include/asm-sh/.mach
+               include/asm-sh/machtypes.h
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
new file mode 100644
index 000000000000..ae194869fd60
--- /dev/null
+++ b/arch/sh/boards/Kconfig
@@ -0,0 +1,258 @@
+menu "Board support"
+
+config SOLUTION_ENGINE
+        bool
+
+config SH_SOLUTION_ENGINE
+        bool "SolutionEngine"
+        select SOLUTION_ENGINE
+        select CPU_HAS_IPR_IRQ
+        depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \
+          CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+          CPU_SUBTYPE_SH7750R 
+        help
+          Select SolutionEngine if configuring for a Hitachi SH7705, SH7709,
+          SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board.
+
+config SH_7206_SOLUTION_ENGINE
+        bool "SolutionEngine7206"
+        select SOLUTION_ENGINE
+        depends on CPU_SUBTYPE_SH7206
+        help
+          Select 7206 SolutionEngine if configuring for a Hitachi SH7206
+          evaluation board.
+
+config SH_7619_SOLUTION_ENGINE
+        bool "SolutionEngine7619"
+        select SOLUTION_ENGINE
+        depends on CPU_SUBTYPE_SH7619
+        help
+          Select 7619 SolutionEngine if configuring for a Hitachi SH7619
+          evaluation board.
+        
+config SH_7721_SOLUTION_ENGINE
+        bool "SolutionEngine7721"
+        select SOLUTION_ENGINE
+        depends on CPU_SUBTYPE_SH7721
+        help
+          Select 7721 SolutionEngine if configuring for a Hitachi SH7721
+          evaluation board.
+
+config SH_7722_SOLUTION_ENGINE
+        bool "SolutionEngine7722"
+        select SOLUTION_ENGINE
+        depends on CPU_SUBTYPE_SH7722
+        help
+          Select 7722 SolutionEngine if configuring for a Hitachi SH772
+          evaluation board.
+
+config SH_7751_SOLUTION_ENGINE
+        bool "SolutionEngine7751"
+        select SOLUTION_ENGINE
+        select CPU_HAS_IPR_IRQ
+        depends on CPU_SUBTYPE_SH7751
+        help
+          Select 7751 SolutionEngine if configuring for a Hitachi SH7751
+          evaluation board.
+          
+config SH_7780_SOLUTION_ENGINE
+        bool "SolutionEngine7780"
+        select SOLUTION_ENGINE
+        select SYS_SUPPORTS_PCI
+        depends on CPU_SUBTYPE_SH7780
+        help
+          Select 7780 SolutionEngine if configuring for a Renesas SH7780
+          evaluation board.
+
+config SH_7343_SOLUTION_ENGINE
+        bool "SolutionEngine7343"
+        select SOLUTION_ENGINE
+        depends on CPU_SUBTYPE_SH7343
+        help
+          Select 7343 SolutionEngine if configuring for a Hitachi
+          SH7343 (SH-Mobile 3AS) evaluation board.
+
+config SH_7751_SYSTEMH
+        bool "SystemH7751R"
+        depends on CPU_SUBTYPE_SH7751R
+        help
+          Select SystemH if you are configuring for a Renesas SystemH
+          7751R evaluation board.
+
+config SH_HP6XX
+        bool "HP6XX"
+        select SYS_SUPPORTS_APM_EMULATION
+        select HD6446X_SERIES
+        depends on CPU_SUBTYPE_SH7709
+        help
+          Select HP6XX if configuring for a HP jornada HP6xx.
+          More information (hardware only) at
+          <http://www.hp.com/jornada/>.
+
+config SH_DREAMCAST
+        bool "Dreamcast"
+        select SYS_SUPPORTS_PCI
+        depends on CPU_SUBTYPE_SH7091
+        help
+          Select Dreamcast if configuring for a SEGA Dreamcast.
+          More information at <http://www.linux-sh.org>
+
+config SH_SH03
+        bool "Interface CTP/PCI-SH03"
+        depends on CPU_SUBTYPE_SH7751
+        select CPU_HAS_IPR_IRQ
+        select SYS_SUPPORTS_PCI
+        help
+          CTP/PCI-SH03 is a CPU module computer that is produced
+          by Interface Corporation.
+          More information at <http://www.interface.co.jp>
+
+config SH_SECUREEDGE5410
+        bool "SecureEdge5410"
+        depends on CPU_SUBTYPE_SH7751R
+        select CPU_HAS_IPR_IRQ
+        select SYS_SUPPORTS_PCI
+        help
+          Select SecureEdge5410 if configuring for a SnapGear SH board.
+          This includes both the OEM SecureEdge products as well as the
+          SME product line.
+
+config SH_RTS7751R2D
+        bool "RTS7751R2D"
+        depends on CPU_SUBTYPE_SH7751R
+        select SYS_SUPPORTS_PCI
+        select IO_TRAPPED
+        help
+          Select RTS7751R2D if configuring for a Renesas Technology
+          Sales SH-Graphics board.
+
+config SH_RSK7203
+        bool "RSK7203"
+        depends on CPU_SUBTYPE_SH7203
+
+config SH_SDK7780
+        bool "SDK7780R3"
+        depends on CPU_SUBTYPE_SH7780
+        select SYS_SUPPORTS_PCI
+        help
+          Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3
+          evaluation board.
+
+config SH_HIGHLANDER
+        bool "Highlander"
+        depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
+        select SYS_SUPPORTS_PCI
+        select IO_TRAPPED
+
+config SH_SH7785LCR
+        bool "SH7785LCR"
+        depends on CPU_SUBTYPE_SH7785
+        select SYS_SUPPORTS_PCI
+        select IO_TRAPPED
+
+config SH_SH7785LCR_29BIT_PHYSMAPS
+        bool "SH7785LCR 29bit physmaps"
+        depends on SH_SH7785LCR
+        default y
+        help
+          This board has 2 physical memory maps. It can be changed with
+          DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
+          you can access all on-board device in 29bit address mode.
+
+config SH_MIGOR
+        bool "Migo-R"
+        depends on CPU_SUBTYPE_SH7722
+        help
+          Select Migo-R if configuring for the SH7722 Migo-R platform
+          by Renesas System Solutions Asia Pte. Ltd.
+
+config SH_AP325RXA
+        bool "AP-325RXA"
+        depends on CPU_SUBTYPE_SH7723
+        help
+          Renesas "AP-325RXA" support.
+          Compatible with ALGO SYSTEM CO.,LTD. "AP-320A"
+
+config SH_SH7763RDP
+        bool "SH7763RDP"
+        depends on CPU_SUBTYPE_SH7763
+        help
+          Select SH7763RDP if configuring for a Renesas SH7763
+          evaluation board.
+
+config SH_EDOSK7705
+        bool "EDOSK7705"
+        depends on CPU_SUBTYPE_SH7705
+
+config SH_SH4202_MICRODEV
+        bool "SH4-202 MicroDev"
+        depends on CPU_SUBTYPE_SH4_202
+        help
+          Select SH4-202 MicroDev if configuring for a SuperH MicroDev board
+          with an SH4-202 CPU.
+
+config SH_LANDISK
+        bool "LANDISK"
+        depends on CPU_SUBTYPE_SH7751R
+        select SYS_SUPPORTS_PCI
+        help
+          I-O DATA DEVICE, INC. "LANDISK Series" support.
+
+config SH_TITAN
+        bool "TITAN"
+        depends on CPU_SUBTYPE_SH7751R
+        select CPU_HAS_IPR_IRQ
+        select SYS_SUPPORTS_PCI
+        help
+          Select Titan if you are configuring for a Nimble Microsystems
+          NetEngine NP51R.
+
+config SH_SHMIN
+        bool "SHMIN"
+        depends on CPU_SUBTYPE_SH7706
+        select CPU_HAS_IPR_IRQ
+        help
+          Select SHMIN if configuring for the SHMIN board.
+
+config SH_LBOX_RE2
+        bool "L-BOX RE2"
+        depends on CPU_SUBTYPE_SH7751R
+        select SYS_SUPPORTS_PCI
+        help
+          Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
+
+config SH_X3PROTO
+        bool "SH-X3 Prototype board"
+        depends on CPU_SUBTYPE_SHX3
+
+config SH_MAGIC_PANEL_R2
+        bool "Magic Panel R2"
+        depends on CPU_SUBTYPE_SH7720
+        help
+          Select Magic Panel R2 if configuring for Magic Panel R2.
+
+config SH_CAYMAN
+        bool "Hitachi Cayman"
+        depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
+        select SYS_SUPPORTS_PCI
+
+endmenu
+
+source "arch/sh/boards/mach-r2d/Kconfig"
+source "arch/sh/boards/mach-highlander/Kconfig"
+source "arch/sh/boards/mach-sdk7780/Kconfig"
+source "arch/sh/boards/mach-migor/Kconfig"
+
+if SH_MAGIC_PANEL_R2
+
+menu "Magic Panel R2 options"
+
+config SH_MAGIC_PANEL_R2_VERSION
+        int SH_MAGIC_PANEL_R2_VERSION
+        default "3"
+        help
+          Set the version of the Magic Panel R2
+
+endmenu
+
+endif
diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile
new file mode 100644
index 000000000000..463022c7df3c
--- /dev/null
+++ b/arch/sh/boards/Makefile
@@ -0,0 +1,8 @@
+#
+# Specific board support, not covered by a mach group.
+#
+obj-$(CONFIG_SH_AP325RXA)       += board-ap325rxa.o
+obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
+obj-$(CONFIG_SH_RSK7203)        += board-rsk7203.o
+obj-$(CONFIG_SH_SH7785LCR)      += board-sh7785lcr.o
+obj-$(CONFIG_SH_SHMIN)          += board-shmin.o
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
new file mode 100644
index 000000000000..025d4fe55a58
--- /dev/null
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -0,0 +1,316 @@
+/*
+ * Renesas - AP-325RXA
+ * (Compatible with Algo System ., LTD. - AP-320A)
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Author : Yusuke Goda <goda.yuske@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/smc911x.h>
+#include <media/soc_camera_platform.h>
+#include <media/sh_mobile_ceu.h>
+#include <asm/sh_mobile_lcdc.h>
+#include <asm/io.h>
+#include <asm/clock.h>
+
+static struct smc911x_platdata smc911x_info = {
+        .flags = SMC911X_USE_32BIT,
+        .irq_flags = IRQF_TRIGGER_LOW,
+};
+
+static struct resource smc9118_resources[] = {
+        [0] = {
+                .start  = 0xb6080000,
+                .end    = 0xb60fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 35,
+                .end    = 35,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device smc9118_device = {
+        .name           = "smc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc9118_resources),
+        .resource       = smc9118_resources,
+        .dev            = {
+                .platform_data = &smc911x_info,
+        },
+};
+
+static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
+        {
+                 .name = "uboot",
+                 .offset = 0,
+                 .size = (1 * 1024 * 1024),
+                 .mask_flags = MTD_WRITEABLE,   /* Read-only */
+        }, {
+                 .name = "kernel",
+                 .offset = MTDPART_OFS_APPEND,
+                 .size = (2 * 1024 * 1024),
+        }, {
+                 .name = "other",
+                 .offset = MTDPART_OFS_APPEND,
+                 .size = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data ap325rxa_nor_flash_data = {
+        .width          = 2,
+        .parts          = ap325rxa_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
+};
+
+static struct resource ap325rxa_nor_flash_resources[] = {
+        [0] = {
+                .name   = "NOR Flash",
+                .start  = 0x00000000,
+                .end    = 0x00ffffff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device ap325rxa_nor_flash_device = {
+        .name           = "physmap-flash",
+        .resource       = ap325rxa_nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(ap325rxa_nor_flash_resources),
+        .dev            = {
+                .platform_data = &ap325rxa_nor_flash_data,
+        },
+};
+
+#define FPGA_LCDREG     0xB4100180
+#define FPGA_BKLREG     0xB4100212
+#define FPGA_LCDREG_VAL 0x0018
+#define PORT_PHCR       0xA405010E
+#define PORT_PLCR       0xA4050114
+#define PORT_PMCR       0xA4050116
+#define PORT_PRCR       0xA405011C
+#define PORT_PSCR       0xA405011E
+#define PORT_PZCR       0xA405014C
+#define PORT_HIZCRA     0xA4050158
+#define PORT_MSELCRB    0xA4050182
+#define PORT_PSDR       0xA405013E
+#define PORT_PZDR       0xA405016C
+#define PORT_PSELD      0xA4050154
+
+static void ap320_wvga_power_on(void *board_data)
+{
+        msleep(100);
+
+        /* ASD AP-320/325 LCD ON */
+        ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
+
+        /* backlight */
+        ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR);
+        ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR);
+        ctrl_outw(0x100, FPGA_BKLREG);
+}
+
+static struct sh_mobile_lcdc_info lcdc_info = {
+        .clock_source = LCDC_CLK_EXTERNAL,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .interface_type = RGB18,
+                .clock_divider = 1,
+                .lcd_cfg = {
+                        .name = "LB070WV1",
+                        .xres = 800,
+                        .yres = 480,
+                        .left_margin = 40,
+                        .right_margin = 160,
+                        .hsync_len = 8,
+                        .upper_margin = 63,
+                        .lower_margin = 80,
+                        .vsync_len = 1,
+                        .sync = 0, /* hsync and vsync are active low */
+                },
+                .board_cfg = {
+                        .display_on = ap320_wvga_power_on,
+                },
+        }
+};
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000, /* P4-only space */
+                .end    = 0xfe941fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+        .resource       = lcdc_resources,
+        .dev            = {
+                .platform_data  = &lcdc_info,
+        },
+};
+
+#ifdef CONFIG_I2C
+static unsigned char camera_ncm03j_magic[] =
+{
+        0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
+        0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
+        0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
+        0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
+        0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
+        0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
+        0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
+        0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
+        0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
+        0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
+        0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
+        0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
+        0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
+        0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
+        0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
+        0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
+};
+
+static int camera_set_capture(struct soc_camera_platform_info *info,
+                              int enable)
+{
+        struct i2c_adapter *a = i2c_get_adapter(0);
+        struct i2c_msg msg;
+        int ret = 0;
+        int i;
+
+        if (!enable)
+                return 0; /* no disable for now */
+
+        for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
+                u_int8_t buf[8];
+
+                msg.addr = 0x6e;
+                msg.buf = buf;
+                msg.len = 2;
+                msg.flags = 0;
+
+                buf[0] = camera_ncm03j_magic[i];
+                buf[1] = camera_ncm03j_magic[i + 1];
+
+                ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
+        }
+
+        return ret;
+}
+
+static struct soc_camera_platform_info camera_info = {
+        .iface = 0,
+        .format_name = "UYVY",
+        .format_depth = 16,
+        .format = {
+                .pixelformat = V4L2_PIX_FMT_UYVY,
+                .colorspace = V4L2_COLORSPACE_SMPTE170M,
+                .width = 640,
+                .height = 480,
+        },
+        .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
+        SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
+        .set_capture = camera_set_capture,
+};
+
+static struct platform_device camera_device = {
+        .name           = "soc_camera_platform",
+        .dev            = {
+                .platform_data  = &camera_info,
+        },
+};
+#endif /* CONFIG_I2C */
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+        .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
+        SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
+};
+
+static struct resource ceu_resources[] = {
+        [0] = {
+                .name   = "CEU",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 52,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu_device = {
+        .name           = "sh_mobile_ceu",
+        .num_resources  = ARRAY_SIZE(ceu_resources),
+        .resource       = ceu_resources,
+        .dev            = {
+                .platform_data  = &sh_mobile_ceu_info,
+        },
+};
+
+static struct platform_device *ap325rxa_devices[] __initdata = {
+        &smc9118_device,
+        &ap325rxa_nor_flash_device,
+        &lcdc_device,
+        &ceu_device,
+#ifdef CONFIG_I2C
+        &camera_device,
+#endif
+};
+
+static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
+};
+
+static int __init ap325rxa_devices_setup(void)
+{
+        clk_always_enable("mstp200"); /* LCDC */
+        clk_always_enable("mstp203"); /* CEU */
+
+        platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
+
+        i2c_register_board_info(0, ap325rxa_i2c_devices,
+                                ARRAY_SIZE(ap325rxa_i2c_devices));
+ 
+        return platform_add_devices(ap325rxa_devices,
+                                ARRAY_SIZE(ap325rxa_devices));
+}
+device_initcall(ap325rxa_devices_setup);
+
+static void __init ap325rxa_setup(char **cmdline_p)
+{
+        /* LCDC configuration */
+        ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR);
+        ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR);
+        ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR);
+        ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR);
+        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA);
+
+        /* CEU */
+        ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
+        ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD);
+        ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR);
+        ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR);
+}
+
+static struct sh_machine_vector mv_ap325rxa __initmv = {
+        .mv_name = "AP-325RXA",
+        .mv_setup = ap325rxa_setup,
+};
diff --git a/arch/sh/boards/magicpanelr2/setup.c b/arch/sh/boards/board-magicpanelr2.c
index f3b8b07ea5d6..f3b8b07ea5d6 100644
--- a/arch/sh/boards/magicpanelr2/setup.c
+++ b/arch/sh/boards/board-magicpanelr2.c
diff --git a/arch/sh/boards/board-rsk7203.c b/arch/sh/boards/board-rsk7203.c
new file mode 100644
index 000000000000..ffbedc59a973
--- /dev/null
+++ b/arch/sh/boards/board-rsk7203.c
@@ -0,0 +1,136 @@
+/*
+ * Renesas Technology Europe RSK+ 7203 Support.
+ *
+ * Copyright (C) 2008 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/map.h>
+#include <linux/smc911x.h>
+#include <asm/machvec.h>
+#include <asm/io.h>
+
+static struct smc911x_platdata smc911x_info = {
+        .flags          = SMC911X_USE_16BIT,
+        .irq_flags      = IRQF_TRIGGER_LOW,
+};
+
+static struct resource smc911x_resources[] = {
+        [0] = {
+                .start          = 0x24000000,
+                .end            = 0x24000000 + 0x100,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = 64,
+                .end            = 64,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device smc911x_device = {
+        .name           = "smc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc911x_resources),
+        .resource       = smc911x_resources,
+        .dev            = {
+                .platform_data = &smc911x_info,
+        },
+};
+
+static const char *probes[] = { "cmdlinepart", NULL };
+
+static struct mtd_partition *parsed_partitions;
+
+static struct mtd_partition rsk7203_partitions[] = {
+        {
+                .name           = "Bootloader",
+                .offset         = 0x00000000,
+                .size           = 0x00040000,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "Kernel",
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = 0x001c0000,
+        }, {
+                .name           = "Flash_FS",
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = MTDPART_SIZ_FULL,
+        }
+};
+
+static struct physmap_flash_data flash_data = {
+        .width          = 2,
+};
+
+static struct resource flash_resource = {
+        .start          = 0x20000000,
+        .end            = 0x20400000,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device flash_device = {
+        .name           = "physmap-flash",
+        .id             = -1,
+        .resource       = &flash_resource,
+        .num_resources  = 1,
+        .dev            = {
+                .platform_data = &flash_data,
+        },
+};
+
+static struct mtd_info *flash_mtd;
+
+static struct map_info rsk7203_flash_map = {
+        .name           = "RSK+ Flash",
+        .size           = 0x400000,
+        .bankwidth      = 2,
+};
+
+static void __init set_mtd_partitions(void)
+{
+        int nr_parts = 0;
+
+        simple_map_init(&rsk7203_flash_map);
+        flash_mtd = do_map_probe("cfi_probe", &rsk7203_flash_map);
+        nr_parts = parse_mtd_partitions(flash_mtd, probes,
+                                        &parsed_partitions, 0);
+        /* If there is no partition table, used the hard coded table */
+        if (nr_parts <= 0) {
+                flash_data.parts = rsk7203_partitions;
+                flash_data.nr_parts = ARRAY_SIZE(rsk7203_partitions);
+        } else {
+                flash_data.nr_parts = nr_parts;
+                flash_data.parts = parsed_partitions;
+        }
+}
+
+
+static struct platform_device *rsk7203_devices[] __initdata = {
+        &smc911x_device,
+        &flash_device,
+};
+
+static int __init rsk7203_devices_setup(void)
+{
+        set_mtd_partitions();
+        return platform_add_devices(rsk7203_devices,
+                                    ARRAY_SIZE(rsk7203_devices));
+}
+device_initcall(rsk7203_devices_setup);
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_rsk7203 __initmv = {
+        .mv_name        = "RSK+7203",
+};
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
new file mode 100644
index 000000000000..b95d674ee704
--- /dev/null
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -0,0 +1,302 @@
+/*
+ * Renesas Technology Corp. R0P7785LC0011RL Support.
+ *
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sm501.h>
+#include <linux/sm501-regs.h>
+#include <linux/fb.h>
+#include <linux/mtd/physmap.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-pca-platform.h>
+#include <linux/i2c-algo-pca.h>
+#include <asm/heartbeat.h>
+#include <asm/sh7785lcr.h>
+
+/*
+ * NOTE: This board has 2 physical memory maps.
+ *       Please look at include/asm-sh/sh7785lcr.h or hardware manual.
+ */
+static struct resource heartbeat_resources[] = {
+        [0] = {
+                .start  = PLD_LEDCR,
+                .end    = PLD_LEDCR,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct heartbeat_data heartbeat_data = {
+        .regsize = 8,
+};
+
+static struct platform_device heartbeat_device = {
+        .name           = "heartbeat",
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &heartbeat_data,
+        },
+        .num_resources  = ARRAY_SIZE(heartbeat_resources),
+        .resource       = heartbeat_resources,
+};
+
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 4 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 4,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = NOR_FLASH_ADDR,
+                .end    = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
+static struct resource r8a66597_usb_host_resources[] = {
+        [0] = {
+                .name   = "r8a66597_hcd",
+                .start  = R8A66597_ADDR,
+                .end    = R8A66597_ADDR + R8A66597_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "r8a66597_hcd",
+                .start  = 2,
+                .end    = 2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device r8a66597_usb_host_device = {
+        .name           = "r8a66597_hcd",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(r8a66597_usb_host_resources),
+        .resource       = r8a66597_usb_host_resources,
+};
+
+static struct resource sm501_resources[] = {
+        [0]     = {
+                .start  = SM107_MEM_ADDR,
+                .end    = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = SM107_REG_ADDR,
+                .end    = SM107_REG_ADDR + SM107_REG_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2]     = {
+                .start  = 10,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct fb_videomode sm501_default_mode_crt = {
+        .pixclock       = 35714,        /* 28MHz */
+        .xres           = 640,
+        .yres           = 480,
+        .left_margin    = 105,
+        .right_margin   = 16,
+        .upper_margin   = 33,
+        .lower_margin   = 10,
+        .hsync_len      = 39,
+        .vsync_len      = 2,
+        .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+};
+
+static struct fb_videomode sm501_default_mode_pnl = {
+        .pixclock       = 40000,        /* 25MHz */
+        .xres           = 640,
+        .yres           = 480,
+        .left_margin    = 2,
+        .right_margin   = 16,
+        .upper_margin   = 33,
+        .lower_margin   = 10,
+        .hsync_len      = 39,
+        .vsync_len      = 2,
+        .sync           = 0,
+};
+
+static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
+        .def_bpp        = 16,
+        .def_mode       = &sm501_default_mode_pnl,
+        .flags          = SM501FB_FLAG_USE_INIT_MODE |
+                          SM501FB_FLAG_USE_HWCURSOR |
+                          SM501FB_FLAG_USE_HWACCEL |
+                          SM501FB_FLAG_DISABLE_AT_EXIT |
+                          SM501FB_FLAG_PANEL_NO_VBIASEN,
+};
+
+static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
+        .def_bpp        = 16,
+        .def_mode       = &sm501_default_mode_crt,
+        .flags          = SM501FB_FLAG_USE_INIT_MODE |
+                          SM501FB_FLAG_USE_HWCURSOR |
+                          SM501FB_FLAG_USE_HWACCEL |
+                          SM501FB_FLAG_DISABLE_AT_EXIT,
+};
+
+static struct sm501_platdata_fb sm501_fb_pdata = {
+        .fb_route       = SM501_FB_OWN,
+        .fb_crt         = &sm501_pdata_fbsub_crt,
+        .fb_pnl         = &sm501_pdata_fbsub_pnl,
+};
+
+static struct sm501_initdata sm501_initdata = {
+        .gpio_high      = {
+                .set    = 0x00001fe0,
+                .mask   = 0x0,
+        },
+        .devices        = 0,
+        .mclk           = 84 * 1000000,
+        .m1xclk         = 112 * 1000000,
+};
+
+static struct sm501_platdata sm501_platform_data = {
+        .init           = &sm501_initdata,
+        .fb             = &sm501_fb_pdata,
+};
+
+static struct platform_device sm501_device = {
+        .name           = "sm501",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &sm501_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(sm501_resources),
+        .resource       = sm501_resources,
+};
+
+static struct resource i2c_resources[] = {
+        [0] = {
+                .start  = PCA9564_ADDR,
+                .end    = PCA9564_ADDR + PCA9564_SIZE - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
+        },
+        [1] = {
+                .start  = 12,
+                .end    = 12,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
+        .gpio                   = 0,
+        .i2c_clock_speed        = I2C_PCA_CON_330kHz,
+        .timeout                = 100,
+};
+
+static struct platform_device i2c_device = {
+        .name           = "i2c-pca-platform",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &i2c_platform_data,
+        },
+        .num_resources  = ARRAY_SIZE(i2c_resources),
+        .resource       = i2c_resources,
+};
+
+static struct platform_device *sh7785lcr_devices[] __initdata = {
+        &heartbeat_device,
+        &nor_flash_device,
+        &r8a66597_usb_host_device,
+        &sm501_device,
+        &i2c_device,
+};
+
+static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("r2025sd", 0x32),
+        },
+};
+
+static int __init sh7785lcr_devices_setup(void)
+{
+        i2c_register_board_info(0, sh7785lcr_i2c_devices,
+                                ARRAY_SIZE(sh7785lcr_i2c_devices));
+
+        return platform_add_devices(sh7785lcr_devices,
+                                    ARRAY_SIZE(sh7785lcr_devices));
+}
+__initcall(sh7785lcr_devices_setup);
+
+/* Initialize IRQ setting */
+void __init init_sh7785lcr_IRQ(void)
+{
+        plat_irq_setup_pins(IRQ_MODE_IRQ7654);
+        plat_irq_setup_pins(IRQ_MODE_IRQ3210);
+}
+
+static void sh7785lcr_power_off(void)
+{
+        ctrl_outb(0x01, P2SEGADDR(PLD_POFCR));
+}
+
+/* Initialize the board */
+static void __init sh7785lcr_setup(char **cmdline_p)
+{
+        void __iomem *sm501_reg;
+
+        printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
+
+        pm_power_off = sh7785lcr_power_off;
+
+        /* sm501 DRAM configuration */
+        sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
+        writel(0x000307c2, sm501_reg);
+}
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_sh7785lcr __initmv = {
+        .mv_name                = "SH7785LCR",
+        .mv_setup               = sh7785lcr_setup,
+        .mv_init_irq            = init_sh7785lcr_IRQ,
+};
+
diff --git a/arch/sh/boards/shmin/setup.c b/arch/sh/boards/board-shmin.c
index 16e5dae8ecfb..16e5dae8ecfb 100644
--- a/arch/sh/boards/shmin/setup.c
+++ b/arch/sh/boards/board-shmin.c
diff --git a/arch/sh/boards/cayman/Makefile b/arch/sh/boards/mach-cayman/Makefile
index 489a8f867368..489a8f867368 100644
--- a/arch/sh/boards/cayman/Makefile
+++ b/arch/sh/boards/mach-cayman/Makefile
diff --git a/arch/sh/boards/cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index 30ec7bebfaf1..ceb37ae92c70 100644
--- a/arch/sh/boards/cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -13,7 +13,7 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/signal.h>
-#include <asm/cpu/irq.h>
+#include <cpu/irq.h>
 #include <asm/page.h>
 
 /* Setup for the SMSC FDC37C935 / LAN91C100FD */
diff --git a/arch/sh/boards/cayman/led.c b/arch/sh/boards/mach-cayman/led.c
index a808eac4ecd6..a808eac4ecd6 100644
--- a/arch/sh/boards/cayman/led.c
+++ b/arch/sh/boards/mach-cayman/led.c
diff --git a/arch/sh/boards/cayman/setup.c b/arch/sh/boards/mach-cayman/setup.c
index 8c9fa472d8f5..e7f9cc5f2ff1 100644
--- a/arch/sh/boards/cayman/setup.c
+++ b/arch/sh/boards/mach-cayman/setup.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
-#include <asm/cpu/irq.h>
+#include <cpu/irq.h>
 
 /*
  * Platform Dependent Interrupt Priorities.
diff --git a/arch/sh/boards/dreamcast/Makefile b/arch/sh/boards/mach-dreamcast/Makefile
index 7b97546c7e5f..7b97546c7e5f 100644
--- a/arch/sh/boards/dreamcast/Makefile
+++ b/arch/sh/boards/mach-dreamcast/Makefile
diff --git a/arch/sh/boards/dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index 9d0673a9092a..67bdc33dd411 100644
--- a/arch/sh/boards/dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -12,7 +12,7 @@
 #include <linux/irq.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/dreamcast/sysasic.h>
+#include <mach/sysasic.h>
 
 /* Dreamcast System ASIC Hardware Events -
 
diff --git a/arch/sh/boards/dreamcast/rtc.c b/arch/sh/boards/mach-dreamcast/rtc.c
index b3a876a3b859..a7433685798d 100644
--- a/arch/sh/boards/dreamcast/rtc.c
+++ b/arch/sh/boards/mach-dreamcast/rtc.c
@@ -30,7 +30,7 @@
  *
  * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch.
  */
-void aica_rtc_gettimeofday(struct timespec *ts)
+static void aica_rtc_gettimeofday(struct timespec *ts)
 {
         unsigned long val1, val2;
 
@@ -54,7 +54,7 @@ void aica_rtc_gettimeofday(struct timespec *ts)
  *
  * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter.
  */
-int aica_rtc_settimeofday(const time_t secs)
+static int aica_rtc_settimeofday(const time_t secs)
 {
         unsigned long val1, val2;
         unsigned long adj = secs + TWENTY_YEARS;
diff --git a/arch/sh/boards/dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c
index 2581c8cd5df7..7d944fc75e93 100644
--- a/arch/sh/boards/dreamcast/setup.c
+++ b/arch/sh/boards/mach-dreamcast/setup.c
@@ -26,7 +26,7 @@
 #include <asm/irq.h>
 #include <asm/rtc.h>
 #include <asm/machvec.h>
-#include <asm/mach/sysasic.h>
+#include <mach/sysasic.h>
 
 extern struct hw_interrupt_type systemasic_int;
 extern void aica_time_init(void);
diff --git a/arch/sh/boards/renesas/edosk7705/Makefile b/arch/sh/boards/mach-edosk7705/Makefile
index 14bdd531f116..14bdd531f116 100644
--- a/arch/sh/boards/renesas/edosk7705/Makefile
+++ b/arch/sh/boards/mach-edosk7705/Makefile
diff --git a/arch/sh/boards/renesas/edosk7705/io.c b/arch/sh/boards/mach-edosk7705/io.c
index 541cea2a652f..541cea2a652f 100644
--- a/arch/sh/boards/renesas/edosk7705/io.c
+++ b/arch/sh/boards/mach-edosk7705/io.c
diff --git a/arch/sh/boards/renesas/edosk7705/setup.c b/arch/sh/boards/mach-edosk7705/setup.c
index f076c45308dd..f076c45308dd 100644
--- a/arch/sh/boards/renesas/edosk7705/setup.c
+++ b/arch/sh/boards/mach-edosk7705/setup.c
diff --git a/arch/sh/boards/renesas/r7780rp/Kconfig b/arch/sh/boards/mach-highlander/Kconfig
index fc8f28e04ba3..fc8f28e04ba3 100644
--- a/arch/sh/boards/renesas/r7780rp/Kconfig
+++ b/arch/sh/boards/mach-highlander/Kconfig
diff --git a/arch/sh/boards/renesas/r7780rp/Makefile b/arch/sh/boards/mach-highlander/Makefile
index 20a10080b11f..20a10080b11f 100644
--- a/arch/sh/boards/renesas/r7780rp/Makefile
+++ b/arch/sh/boards/mach-highlander/Makefile
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c b/arch/sh/boards/mach-highlander/irq-r7780mp.c
index ae1cfcb29700..ae1cfcb29700 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7780mp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780mp.c
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c b/arch/sh/boards/mach-highlander/irq-r7780rp.c
index 9d3921fe27c0..9d3921fe27c0 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7780rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780rp.c
diff --git a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c b/arch/sh/boards/mach-highlander/irq-r7785rp.c
index 896c045aa39d..896c045aa39d 100644
--- a/arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7785rp.c
diff --git a/arch/sh/boards/renesas/r7780rp/psw.c b/arch/sh/boards/mach-highlander/psw.c
index c844dfa5d58d..be8d5477fc65 100644
--- a/arch/sh/boards/renesas/r7780rp/psw.c
+++ b/arch/sh/boards/mach-highlander/psw.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <asm/mach/r7780rp.h>
+#include <asm/r7780rp.h>
 #include <asm/push-switch.h>
 
 static irqreturn_t psw_irq_handler(int irq, void *arg)
diff --git a/arch/sh/boards/renesas/r7780rp/setup.c b/arch/sh/boards/mach-highlander/setup.c
index bc79afb6fc4c..bc79afb6fc4c 100644
--- a/arch/sh/boards/renesas/r7780rp/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
diff --git a/arch/sh/boards/hp6xx/Makefile b/arch/sh/boards/mach-hp6xx/Makefile
index b3124278247c..b3124278247c 100644
--- a/arch/sh/boards/hp6xx/Makefile
+++ b/arch/sh/boards/mach-hp6xx/Makefile
diff --git a/arch/sh/boards/hp6xx/hp6xx_apm.c b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
index 177f4f028e0d..177f4f028e0d 100644
--- a/arch/sh/boards/hp6xx/hp6xx_apm.c
+++ b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
diff --git a/arch/sh/boards/hp6xx/pm.c b/arch/sh/boards/mach-hp6xx/pm.c
index d22f6eac9cca..e96684def788 100644
--- a/arch/sh/boards/hp6xx/pm.c
+++ b/arch/sh/boards/mach-hp6xx/pm.c
@@ -13,7 +13,7 @@
 #include <asm/io.h>
 #include <asm/hd64461.h>
 #include <asm/hp6xx.h>
-#include <asm/cpu/dac.h>
+#include <cpu/dac.h>
 #include <asm/pm.h>
 
 #define STBCR           0xffffff82
diff --git a/arch/sh/boards/hp6xx/pm_wakeup.S b/arch/sh/boards/mach-hp6xx/pm_wakeup.S
index 45e9bf0b9115..44b648cf6f23 100644
--- a/arch/sh/boards/hp6xx/pm_wakeup.S
+++ b/arch/sh/boards/mach-hp6xx/pm_wakeup.S
@@ -8,7 +8,7 @@
  */
 
 #include <linux/linkage.h>
-#include <asm/cpu/mmu_context.h>
+#include <cpu/mmu_context.h>
 
 #define k0      r0
 #define k1      r1
diff --git a/arch/sh/boards/hp6xx/setup.c b/arch/sh/boards/mach-hp6xx/setup.c
index 2f414ac3c690..475b46caec1f 100644
--- a/arch/sh/boards/hp6xx/setup.c
+++ b/arch/sh/boards/mach-hp6xx/setup.c
@@ -16,7 +16,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/hp6xx.h>
-#include <asm/cpu/dac.h>
+#include <cpu/dac.h>
 
 #define SCPCR   0xa4000116
 #define SCPDR   0xa4000136
diff --git a/arch/sh/boards/landisk/Makefile b/arch/sh/boards/mach-landisk/Makefile
index a696b4277fa9..a696b4277fa9 100644
--- a/arch/sh/boards/landisk/Makefile
+++ b/arch/sh/boards/mach-landisk/Makefile
diff --git a/arch/sh/boards/landisk/gio.c b/arch/sh/boards/mach-landisk/gio.c
index 0c15b0a50b99..25cdf7358000 100644
--- a/arch/sh/boards/landisk/gio.c
+++ b/arch/sh/boards/mach-landisk/gio.c
@@ -20,8 +20,8 @@
 #include <linux/fs.h>
 #include <asm/io.h>
 #include <asm/uaccess.h>
-#include <asm/landisk/gio.h>
-#include <asm/landisk/iodata_landisk.h>
+#include <mach-landisk/mach/gio.h>
+#include <mach-landisk/mach/iodata_landisk.h>
 
 #define DEVCOUNT                4
 #define GIO_MINOR               2       /* GIO minor no. */
diff --git a/arch/sh/boards/landisk/irq.c b/arch/sh/boards/mach-landisk/irq.c
index 258649491d44..7b284cde1f58 100644
--- a/arch/sh/boards/landisk/irq.c
+++ b/arch/sh/boards/mach-landisk/irq.c
@@ -16,7 +16,7 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <asm/landisk/iodata_landisk.h>
+#include <mach-landisk/mach/iodata_landisk.h>
 
 static void disable_landisk_irq(unsigned int irq)
 {
diff --git a/arch/sh/boards/landisk/psw.c b/arch/sh/boards/mach-landisk/psw.c
index 5a9b70b5decb..e6b0efa098d1 100644
--- a/arch/sh/boards/landisk/psw.c
+++ b/arch/sh/boards/mach-landisk/psw.c
@@ -14,7 +14,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <asm/landisk/iodata_landisk.h>
+#include <mach-landisk/mach/iodata_landisk.h>
 #include <asm/push-switch.h>
 
 static irqreturn_t psw_irq_handler(int irq, void *arg)
diff --git a/arch/sh/boards/landisk/setup.c b/arch/sh/boards/mach-landisk/setup.c
index 2b708ec72558..db22ea2e6d49 100644
--- a/arch/sh/boards/landisk/setup.c
+++ b/arch/sh/boards/mach-landisk/setup.c
@@ -18,7 +18,7 @@
 #include <linux/pm.h>
 #include <linux/mm.h>
 #include <asm/machvec.h>
-#include <asm/landisk/iodata_landisk.h>
+#include <mach-landisk/mach/iodata_landisk.h>
 #include <asm/io.h>
 
 void init_landisk_IRQ(void);
diff --git a/arch/sh/boards/lboxre2/Makefile b/arch/sh/boards/mach-lboxre2/Makefile
index e9ed140c06f6..e9ed140c06f6 100644
--- a/arch/sh/boards/lboxre2/Makefile
+++ b/arch/sh/boards/mach-lboxre2/Makefile
diff --git a/arch/sh/boards/lboxre2/irq.c b/arch/sh/boards/mach-lboxre2/irq.c
index 5a1c3bbe7b50..5a1c3bbe7b50 100644
--- a/arch/sh/boards/lboxre2/irq.c
+++ b/arch/sh/boards/mach-lboxre2/irq.c
diff --git a/arch/sh/boards/lboxre2/setup.c b/arch/sh/boards/mach-lboxre2/setup.c
index c74440d38ee9..c74440d38ee9 100644
--- a/arch/sh/boards/lboxre2/setup.c
+++ b/arch/sh/boards/mach-lboxre2/setup.c
diff --git a/arch/sh/boards/superh/microdev/Makefile b/arch/sh/boards/mach-microdev/Makefile
index 1387dd6c85eb..1387dd6c85eb 100644
--- a/arch/sh/boards/superh/microdev/Makefile
+++ b/arch/sh/boards/mach-microdev/Makefile
diff --git a/arch/sh/boards/superh/microdev/io.c b/arch/sh/boards/mach-microdev/io.c
index 9f8a540f7e14..9f8a540f7e14 100644
--- a/arch/sh/boards/superh/microdev/io.c
+++ b/arch/sh/boards/mach-microdev/io.c
diff --git a/arch/sh/boards/superh/microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index 4d335077a3ff..4d335077a3ff 100644
--- a/arch/sh/boards/superh/microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
diff --git a/arch/sh/boards/superh/microdev/led.c b/arch/sh/boards/mach-microdev/led.c
index 36e54b47a752..36e54b47a752 100644
--- a/arch/sh/boards/superh/microdev/led.c
+++ b/arch/sh/boards/mach-microdev/led.c
diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c
index fc8cd06d66cf..fc8cd06d66cf 100644
--- a/arch/sh/boards/superh/microdev/setup.c
+++ b/arch/sh/boards/mach-microdev/setup.c
diff --git a/arch/sh/boards/mach-migor/Kconfig b/arch/sh/boards/mach-migor/Kconfig
new file mode 100644
index 000000000000..a7b3b728ec3c
--- /dev/null
+++ b/arch/sh/boards/mach-migor/Kconfig
@@ -0,0 +1,15 @@
+if SH_MIGOR
+
+choice
+        prompt "Migo-R LCD Panel Board Selection"
+        default SH_MIGOR_QVGA
+
+config SH_MIGOR_QVGA
+        bool "QVGA (320x240)"
+
+config SH_MIGOR_RTA_WVGA
+        bool "RTA WVGA (800x480)"
+
+endchoice
+
+endif
diff --git a/arch/sh/boards/mach-migor/Makefile b/arch/sh/boards/mach-migor/Makefile
new file mode 100644
index 000000000000..5f231dd25c0e
--- /dev/null
+++ b/arch/sh/boards/mach-migor/Makefile
@@ -0,0 +1,2 @@
+obj-y    := setup.o
+obj-$(CONFIG_SH_MIGOR_QVGA)     +=  lcd_qvga.o
diff --git a/arch/sh/boards/mach-migor/lcd_qvga.c b/arch/sh/boards/mach-migor/lcd_qvga.c
new file mode 100644
index 000000000000..6e9609596448
--- /dev/null
+++ b/arch/sh/boards/mach-migor/lcd_qvga.c
@@ -0,0 +1,165 @@
+/*
+ * Support for SuperH MigoR Quarter VGA LCD Panel
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * Based on lcd_powertip.c from Kenati Technologies Pvt Ltd.
+ * Copyright (c) 2007 Ujjwal Pande <ujjwal@kenati.com>,
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/sh_mobile_lcdc.h>
+#include <asm/migor.h>
+
+/* LCD Module is a PH240320T according to board schematics. This module
+ * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?)
+ * Driver IC. This IC is connected to the SH7722 built-in LCDC using a
+ * SYS-80 interface configured in 16 bit mode.
+ *
+ * Index 0: "Device Code Read" returns 0x1505.
+ */
+
+static void reset_lcd_module(void)
+{
+        ctrl_outb(ctrl_inb(PORT_PHDR) & ~0x04, PORT_PHDR);
+        mdelay(2);
+        ctrl_outb(ctrl_inb(PORT_PHDR) | 0x04, PORT_PHDR);
+        mdelay(1);
+}
+
+/* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */
+
+static unsigned long adjust_reg18(unsigned short data)
+{
+        unsigned long tmp1, tmp2;
+
+        tmp1 = (data<<1 | 0x00000001) & 0x000001FF;
+        tmp2 = (data<<2 | 0x00000200) & 0x0003FE00;
+        return tmp1 | tmp2;
+}
+
+static void write_reg(void *sys_ops_handle,
+                       struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
+                       unsigned short reg, unsigned short data)
+{
+        sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data));
+}
+
+static void write_reg16(void *sys_ops_handle,
+                        struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
+                        unsigned short reg, unsigned short data)
+{
+        sys_ops->write_index(sys_ops_handle, adjust_reg18(reg));
+        sys_ops->write_data(sys_ops_handle, adjust_reg18(data));
+}
+
+static unsigned long read_reg16(void *sys_ops_handle,
+                                struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
+                                unsigned short reg)
+{
+        unsigned long data;
+
+        sys_ops->write_index(sys_ops_handle, adjust_reg18(reg));
+        data = sys_ops->read_data(sys_ops_handle);
+        return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00);
+}
+
+static void migor_lcd_qvga_seq(void *sys_ops_handle,
+                               struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
+                               unsigned short const *data, int no_data)
+{
+        int i;
+
+        for (i = 0; i < no_data; i += 2)
+                write_reg16(sys_ops_handle, sys_ops, data[i], data[i + 1]);
+}
+
+static const unsigned short sync_data[] = {
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+};
+
+static const unsigned short magic0_data[] = {
+        0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001,
+        0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116,
+        0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8,
+};
+
+static const unsigned short magic1_data[] = {
+        0x0030, 0x0307, 0x0031, 0x0303, 0x0032, 0x0603, 0x0033, 0x0202,
+        0x0034, 0x0202, 0x0035, 0x0202, 0x0036, 0x1F1F, 0x0037, 0x0303,
+        0x0038, 0x0303, 0x0039, 0x0603, 0x003A, 0x0202, 0x003B, 0x0102,
+        0x003C, 0x0204, 0x003D, 0x0000, 0x0001, 0x0100, 0x0002, 0x0300,
+        0x0003, 0x5028, 0x0020, 0x00ef, 0x0021, 0x0000, 0x0004, 0x0000,
+        0x0009, 0x0000, 0x000A, 0x0008, 0x000C, 0x0000, 0x000D, 0x0000,
+        0x0015, 0x8000,
+};
+
+static const unsigned short magic2_data[] = {
+        0x0061, 0x0001, 0x0092, 0x0100, 0x0093, 0x0001, 0x0007, 0x0021,
+};
+
+static const unsigned short magic3_data[] = {
+        0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061,
+};
+
+int migor_lcd_qvga_setup(void *board_data, void *sohandle,
+                         struct sh_mobile_lcdc_sys_bus_ops *so)
+{
+        unsigned long xres = 320;
+        unsigned long yres = 240;
+        int k;
+
+        reset_lcd_module();
+        migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data));
+
+        if (read_reg16(sohandle, so, 0) != 0x1505)
+                return -ENODEV;
+
+        pr_info("Migo-R QVGA LCD Module detected.\n");
+
+        migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data));
+        write_reg16(sohandle, so, 0x00A4, 0x0001);
+        mdelay(10);
+
+        migor_lcd_qvga_seq(sohandle, so, magic0_data, ARRAY_SIZE(magic0_data));
+        mdelay(100);
+
+        migor_lcd_qvga_seq(sohandle, so, magic1_data, ARRAY_SIZE(magic1_data));
+        write_reg16(sohandle, so, 0x0050, 0xef - (yres - 1));
+        write_reg16(sohandle, so, 0x0051, 0x00ef);
+        write_reg16(sohandle, so, 0x0052, 0x0000);
+        write_reg16(sohandle, so, 0x0053, xres - 1);
+
+        migor_lcd_qvga_seq(sohandle, so, magic2_data, ARRAY_SIZE(magic2_data));
+        mdelay(10);
+
+        migor_lcd_qvga_seq(sohandle, so, magic3_data, ARRAY_SIZE(magic3_data));
+        mdelay(40);
+
+        /* clear GRAM to avoid displaying garbage */
+
+        write_reg16(sohandle, so, 0x0020, 0x0000); /* horiz addr */
+        write_reg16(sohandle, so, 0x0021, 0x0000); /* vert addr */
+
+        for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */
+                write_reg16(sohandle, so, 0x0022, 0x0000);
+
+        write_reg16(sohandle, so, 0x0020, 0x0000); /* reset horiz addr */
+        write_reg16(sohandle, so, 0x0021, 0x0000); /* reset vert addr */
+        write_reg16(sohandle, so, 0x0007, 0x0173);
+        mdelay(40);
+
+        /* enable display */
+        write_reg(sohandle, so, 0x00, 0x22);
+        mdelay(100);
+        return 0;
+}
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
new file mode 100644
index 000000000000..e499ee384d58
--- /dev/null
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -0,0 +1,527 @@
+/*
+ * Renesas System Solutions Asia Pte. Ltd - Migo-R
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/i2c.h>
+#include <linux/smc91x.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <media/soc_camera_platform.h>
+#include <media/sh_mobile_ceu.h>
+#include <asm/clock.h>
+#include <asm/machvec.h>
+#include <asm/io.h>
+#include <asm/sh_keysc.h>
+#include <asm/sh_mobile_lcdc.h>
+#include <asm/migor.h>
+
+/* Address     IRQ  Size  Bus  Description
+ * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
+ * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
+ * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
+ * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
+ * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
+ */
+
+static struct smc91x_platdata smc91x_info = {
+        .flags = SMC91X_USE_16BIT,
+};
+
+static struct resource smc91x_eth_resources[] = {
+        [0] = {
+                .name   = "SMC91C111" ,
+                .start  = 0x10000300,
+                .end    = 0x1000030f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 32, /* IRQ0 */
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+        },
+};
+
+static struct platform_device smc91x_eth_device = {
+        .name           = "smc91x",
+        .num_resources  = ARRAY_SIZE(smc91x_eth_resources),
+        .resource       = smc91x_eth_resources,
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
+};
+
+static struct sh_keysc_info sh_keysc_info = {
+        .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
+        .scan_timing = 3,
+        .delay = 5,
+        .keycodes = {
+                0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
+                0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
+                0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
+                0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
+                0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
+        },
+};
+
+static struct resource sh_keysc_resources[] = {
+        [0] = {
+                .start  = 0x044b0000,
+                .end    = 0x044b000f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 79,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sh_keysc_device = {
+        .name           = "sh_keysc",
+        .num_resources  = ARRAY_SIZE(sh_keysc_resources),
+        .resource       = sh_keysc_resources,
+        .dev    = {
+                .platform_data  = &sh_keysc_info,
+        },
+};
+
+static struct mtd_partition migor_nor_flash_partitions[] =
+{
+        {
+                .name = "uboot",
+                .offset = 0,
+                .size = (1 * 1024 * 1024),
+                .mask_flags = MTD_WRITEABLE,    /* Read-only */
+        },
+        {
+                .name = "rootfs",
+                .offset = MTDPART_OFS_APPEND,
+                .size = (15 * 1024 * 1024),
+        },
+        {
+                .name = "other",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data migor_nor_flash_data = {
+        .width          = 2,
+        .parts          = migor_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(migor_nor_flash_partitions),
+};
+
+static struct resource migor_nor_flash_resources[] = {
+        [0] = {
+                .name           = "NOR Flash",
+                .start          = 0x00000000,
+                .end            = 0x03ffffff,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device migor_nor_flash_device = {
+        .name           = "physmap-flash",
+        .resource       = migor_nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(migor_nor_flash_resources),
+        .dev            = {
+                .platform_data = &migor_nor_flash_data,
+        },
+};
+
+static struct mtd_partition migor_nand_flash_partitions[] = {
+        {
+                .name           = "nanddata1",
+                .offset         = 0x0,
+                .size           = 512 * 1024 * 1024,
+        },
+        {
+                .name           = "nanddata2",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024 * 1024,
+        },
+};
+
+static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
+                                     unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        if (ctrl & NAND_CLE)
+                writeb(cmd, chip->IO_ADDR_W + 0x00400000);
+        else if (ctrl & NAND_ALE)
+                writeb(cmd, chip->IO_ADDR_W + 0x00800000);
+        else
+                writeb(cmd, chip->IO_ADDR_W);
+}
+
+static int migor_nand_flash_ready(struct mtd_info *mtd)
+{
+        return ctrl_inb(PORT_PADR) & 0x02; /* PTA1 */
+}
+
+struct platform_nand_data migor_nand_flash_data = {
+        .chip = {
+                .nr_chips = 1,
+                .partitions = migor_nand_flash_partitions,
+                .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
+                .chip_delay = 20,
+                .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
+        },
+        .ctrl = {
+                .dev_ready = migor_nand_flash_ready,
+                .cmd_ctrl = migor_nand_flash_cmd_ctl,
+        },
+};
+
+static struct resource migor_nand_flash_resources[] = {
+        [0] = {
+                .name           = "NAND Flash",
+                .start          = 0x18000000,
+                .end            = 0x18ffffff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device migor_nand_flash_device = {
+        .name           = "gen_nand",
+        .resource       = migor_nand_flash_resources,
+        .num_resources  = ARRAY_SIZE(migor_nand_flash_resources),
+        .dev            = {
+                .platform_data = &migor_nand_flash_data,
+        }
+};
+
+static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
+#ifdef CONFIG_SH_MIGOR_RTA_WVGA
+        .clock_source = LCDC_CLK_BUS,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .interface_type = RGB16,
+                .clock_divider = 2,
+                .lcd_cfg = {
+                        .name = "LB070WV1",
+                        .xres = 800,
+                        .yres = 480,
+                        .left_margin = 64,
+                        .right_margin = 16,
+                        .hsync_len = 120,
+                        .upper_margin = 1,
+                        .lower_margin = 17,
+                        .vsync_len = 2,
+                        .sync = 0,
+                },
+        }
+#endif
+#ifdef CONFIG_SH_MIGOR_QVGA
+        .clock_source = LCDC_CLK_PERIPHERAL,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .interface_type = SYS16A,
+                .clock_divider = 10,
+                .lcd_cfg = {
+                        .name = "PH240320T",
+                        .xres = 320,
+                        .yres = 240,
+                        .left_margin = 0,
+                        .right_margin = 16,
+                        .hsync_len = 8,
+                        .upper_margin = 1,
+                        .lower_margin = 17,
+                        .vsync_len = 2,
+                        .sync = FB_SYNC_HOR_HIGH_ACT,
+                },
+                .board_cfg = {
+                        .setup_sys = migor_lcd_qvga_setup,
+                },
+                .sys_bus_cfg = {
+                        .ldmt2r = 0x06000a09,
+                        .ldmt3r = 0x180e3418,
+                },
+        }
+#endif
+};
+
+static struct resource migor_lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000, /* P4-only space */
+                .end    = 0xfe941fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device migor_lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(migor_lcdc_resources),
+        .resource       = migor_lcdc_resources,
+        .dev    = {
+                .platform_data  = &sh_mobile_lcdc_info,
+        },
+};
+
+static struct clk *camera_clk;
+
+static void camera_power_on(void)
+{
+        unsigned char value;
+
+        camera_clk = clk_get(NULL, "video_clk");
+        clk_set_rate(camera_clk, 24000000);
+        clk_enable(camera_clk); /* start VIO_CKO */
+
+        mdelay(10);
+        value = ctrl_inb(PORT_PTDR);
+        value &= ~0x09;
+#ifndef CONFIG_SH_MIGOR_RTA_WVGA
+        value |= 0x01;
+#endif
+        ctrl_outb(value, PORT_PTDR);
+        mdelay(10);
+
+        ctrl_outb(value | 8, PORT_PTDR);
+}
+
+static void camera_power_off(void)
+{
+        clk_disable(camera_clk); /* stop VIO_CKO */
+        clk_put(camera_clk);
+
+        ctrl_outb(ctrl_inb(PORT_PTDR) & ~0x08, PORT_PTDR);
+}
+
+#ifdef CONFIG_I2C
+static unsigned char camera_ov772x_magic[] =
+{
+        0x09, 0x01, 0x0c, 0x10, 0x0d, 0x41, 0x0e, 0x01,
+        0x12, 0x00, 0x13, 0x8F, 0x14, 0x4A, 0x15, 0x00,
+        0x16, 0x00, 0x17, 0x23, 0x18, 0xa0, 0x19, 0x07,
+        0x1a, 0xf0, 0x1b, 0x40, 0x1f, 0x00, 0x20, 0x10,
+        0x22, 0xff, 0x23, 0x01, 0x28, 0x00, 0x29, 0xa0,
+        0x2a, 0x00, 0x2b, 0x00, 0x2c, 0xf0, 0x2d, 0x00,
+        0x2e, 0x00, 0x30, 0x80, 0x31, 0x60, 0x32, 0x00,
+        0x33, 0x00, 0x34, 0x00, 0x3d, 0x80, 0x3e, 0xe2,
+        0x3f, 0x1f, 0x42, 0x80, 0x43, 0x80, 0x44, 0x80,
+        0x45, 0x80, 0x46, 0x00, 0x47, 0x00, 0x48, 0x00,
+        0x49, 0x50, 0x4a, 0x30, 0x4b, 0x50, 0x4c, 0x50,
+        0x4d, 0x00, 0x4e, 0xef, 0x4f, 0x10, 0x50, 0x60,
+        0x51, 0x00, 0x52, 0x00, 0x53, 0x24, 0x54, 0x7a,
+        0x55, 0xfc, 0x62, 0xff, 0x63, 0xf0, 0x64, 0x1f,
+        0x65, 0x00, 0x66, 0x10, 0x67, 0x00, 0x68, 0x00,
+        0x69, 0x5c, 0x6a, 0x11, 0x6b, 0xa2, 0x6c, 0x01,
+        0x6d, 0x50, 0x6e, 0x80, 0x6f, 0x80, 0x70, 0x0f,
+        0x71, 0x00, 0x72, 0x00, 0x73, 0x0f, 0x74, 0x0f,
+        0x75, 0xff, 0x78, 0x10, 0x79, 0x70, 0x7a, 0x70,
+        0x7b, 0xf0, 0x7c, 0xf0, 0x7d, 0xf0, 0x7e, 0x0e,
+        0x7f, 0x1a, 0x80, 0x31, 0x81, 0x5a, 0x82, 0x69,
+        0x83, 0x75, 0x84, 0x7e, 0x85, 0x88, 0x86, 0x8f,
+        0x87, 0x96, 0x88, 0xa3, 0x89, 0xaf, 0x8a, 0xc4,
+        0x8b, 0xd7, 0x8c, 0xe8, 0x8d, 0x20, 0x8e, 0x00,
+        0x8f, 0x00, 0x90, 0x08, 0x91, 0x10, 0x92, 0x1f,
+        0x93, 0x01, 0x94, 0x2c, 0x95, 0x24, 0x96, 0x08,
+        0x97, 0x14, 0x98, 0x24, 0x99, 0x38, 0x9a, 0x9e,
+        0x9b, 0x00, 0x9c, 0x40, 0x9e, 0x11, 0x9f, 0x02,
+        0xa0, 0x00, 0xa1, 0x40, 0xa2, 0x40, 0xa3, 0x06,
+        0xa4, 0x00, 0xa6, 0x00, 0xa7, 0x40, 0xa8, 0x40,
+        0xa9, 0x80, 0xaa, 0x80, 0xab, 0x06, 0xac, 0xff,
+        0x12, 0x06, 0x64, 0x3f, 0x12, 0x46, 0x17, 0x3f,
+        0x18, 0x50, 0x19, 0x03, 0x1a, 0x78, 0x29, 0x50,
+        0x2c, 0x78,
+};
+
+static int ov772x_set_capture(struct soc_camera_platform_info *info,
+                              int enable)
+{
+        struct i2c_adapter *a = i2c_get_adapter(0);
+        struct i2c_msg msg;
+        int ret = 0;
+        int i;
+
+        if (!enable)
+                return 0; /* camera_power_off() is enough */
+
+        for (i = 0; i < ARRAY_SIZE(camera_ov772x_magic); i += 2) {
+                u_int8_t buf[8];
+
+                msg.addr = 0x21;
+                msg.buf = buf;
+                msg.len = 2;
+                msg.flags = 0;
+
+                buf[0] = camera_ov772x_magic[i];
+                buf[1] = camera_ov772x_magic[i + 1];
+
+                ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
+        }
+
+        return ret;
+}
+
+static struct soc_camera_platform_info ov772x_info = {
+        .iface = 0,
+        .format_name = "RGB565",
+        .format_depth = 16,
+        .format = {
+                .pixelformat = V4L2_PIX_FMT_RGB565,
+                .colorspace = V4L2_COLORSPACE_SRGB,
+                .width = 320,
+                .height = 240,
+        },
+        .bus_param =  SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
+        SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
+        .set_capture = ov772x_set_capture,
+};
+
+static struct platform_device migor_camera_device = {
+        .name           = "soc_camera_platform",
+        .dev    = {
+                .platform_data  = &ov772x_info,
+        },
+};
+#endif /* CONFIG_I2C */
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+        .flags = SOCAM_MASTER | SOCAM_DATAWIDTH_8 | SOCAM_PCLK_SAMPLE_RISING \
+        | SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_HIGH,
+        .enable_camera = camera_power_on,
+        .disable_camera = camera_power_off,
+};
+
+static struct resource migor_ceu_resources[] = {
+        [0] = {
+                .name   = "CEU",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 52,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device migor_ceu_device = {
+        .name           = "sh_mobile_ceu",
+        .num_resources  = ARRAY_SIZE(migor_ceu_resources),
+        .resource       = migor_ceu_resources,
+        .dev    = {
+                .platform_data  = &sh_mobile_ceu_info,
+        },
+};
+
+static struct platform_device *migor_devices[] __initdata = {
+        &smc91x_eth_device,
+        &sh_keysc_device,
+        &migor_lcdc_device,
+        &migor_ceu_device,
+#ifdef CONFIG_I2C
+        &migor_camera_device,
+#endif
+        &migor_nor_flash_device,
+        &migor_nand_flash_device,
+};
+
+static struct i2c_board_info migor_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rs5c372b", 0x32),
+        },
+        {
+                I2C_BOARD_INFO("migor_ts", 0x51),
+                .irq = 38, /* IRQ6 */
+        },
+};
+
+static int __init migor_devices_setup(void)
+{
+        clk_always_enable("mstp214"); /* KEYSC */
+        clk_always_enable("mstp200"); /* LCDC */
+        clk_always_enable("mstp203"); /* CEU */
+
+        platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
+
+        i2c_register_board_info(0, migor_i2c_devices,
+                                ARRAY_SIZE(migor_i2c_devices));
+ 
+        return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
+}
+__initcall(migor_devices_setup);
+
+static void __init migor_setup(char **cmdline_p)
+{
+        /* SMC91C111 - Enable IRQ0 */
+        ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR);
+
+        /* KEYSC */
+        ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR);
+        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR);
+        ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA);
+        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+        ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
+
+        /* NAND Flash */
+        ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR);
+        ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200,
+                  BSC_CS6ABCR);
+
+        /* Touch Panel - Enable IRQ6 */
+        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR);
+        ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA);
+        ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC);
+
+#ifdef CONFIG_SH_MIGOR_RTA_WVGA
+        /* LCDC - WVGA - Enable RGB Interface signals */
+        ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR);
+        ctrl_outw(0x0000, PORT_PHCR);
+        ctrl_outw(0x0000, PORT_PLCR);
+        ctrl_outw(0x0000, PORT_PMCR);
+        ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x000f, PORT_PRCR);
+        ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x000d) | 0x0400, PORT_PSELD);
+        ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0100, PORT_MSELCRB);
+        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA);
+#endif
+#ifdef CONFIG_SH_MIGOR_QVGA
+        /* LCDC - QVGA - Enable SYS Interface signals */
+        ctrl_outw(ctrl_inw(PORT_PACR) & ~0x0003, PORT_PACR);
+        ctrl_outw((ctrl_inw(PORT_PHCR) & ~0xcfff) | 0x0010, PORT_PHCR);
+        ctrl_outw(0x0000, PORT_PLCR);
+        ctrl_outw(0x0000, PORT_PMCR);
+        ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x030f, PORT_PRCR);
+        ctrl_outw((ctrl_inw(PORT_PSELD) & ~0x0001) | 0x0420, PORT_PSELD);
+        ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x0100, PORT_MSELCRB);
+        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01e0, PORT_HIZCRA);
+#endif
+
+        /* CEU */
+        ctrl_outw((ctrl_inw(PORT_PTCR) & ~0x03c3) | 0x0051, PORT_PTCR);
+        ctrl_outw(ctrl_inw(PORT_PUCR) & ~0x03ff, PORT_PUCR);
+        ctrl_outw(ctrl_inw(PORT_PVCR) & ~0x03ff, PORT_PVCR);
+        ctrl_outw(ctrl_inw(PORT_PWCR) & ~0x3c00, PORT_PWCR);
+        ctrl_outw(ctrl_inw(PORT_PSELC) | 0x0001, PORT_PSELC);
+        ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x2000, PORT_PSELD);
+        ctrl_outw(ctrl_inw(PORT_PSELE) | 0x000f, PORT_PSELE);
+        ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2200, PORT_MSELCRB);
+        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x0a00, PORT_HIZCRA);
+        ctrl_outw(ctrl_inw(PORT_HIZCRB) & ~0x0003, PORT_HIZCRB);
+}
+
+static struct sh_machine_vector mv_migor __initmv = {
+        .mv_name                = "Migo-R",
+        .mv_setup               = migor_setup,
+};
diff --git a/arch/sh/boards/renesas/rts7751r2d/Kconfig b/arch/sh/boards/mach-r2d/Kconfig
index 8122a9667fc9..8122a9667fc9 100644
--- a/arch/sh/boards/renesas/rts7751r2d/Kconfig
+++ b/arch/sh/boards/mach-r2d/Kconfig
diff --git a/arch/sh/boards/renesas/rts7751r2d/Makefile b/arch/sh/boards/mach-r2d/Makefile
index 0d4c75a72be0..0d4c75a72be0 100644
--- a/arch/sh/boards/renesas/rts7751r2d/Makefile
+++ b/arch/sh/boards/mach-r2d/Makefile
diff --git a/arch/sh/boards/renesas/rts7751r2d/irq.c b/arch/sh/boards/mach-r2d/irq.c
index 8e49f6e51247..8e49f6e51247 100644
--- a/arch/sh/boards/renesas/rts7751r2d/irq.c
+++ b/arch/sh/boards/mach-r2d/irq.c
diff --git a/arch/sh/boards/renesas/rts7751r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c
index 2308e8753bcd..2308e8753bcd 100644
--- a/arch/sh/boards/renesas/rts7751r2d/setup.c
+++ b/arch/sh/boards/mach-r2d/setup.c
diff --git a/arch/sh/boards/renesas/sdk7780/Kconfig b/arch/sh/boards/mach-sdk7780/Kconfig
index 065f1df09bf1..065f1df09bf1 100644
--- a/arch/sh/boards/renesas/sdk7780/Kconfig
+++ b/arch/sh/boards/mach-sdk7780/Kconfig
diff --git a/arch/sh/boards/renesas/sdk7780/Makefile b/arch/sh/boards/mach-sdk7780/Makefile
index 3d8f0befc35d..3d8f0befc35d 100644
--- a/arch/sh/boards/renesas/sdk7780/Makefile
+++ b/arch/sh/boards/mach-sdk7780/Makefile
diff --git a/arch/sh/boards/renesas/sdk7780/irq.c b/arch/sh/boards/mach-sdk7780/irq.c
index 87cdc578f6ff..87cdc578f6ff 100644
--- a/arch/sh/boards/renesas/sdk7780/irq.c
+++ b/arch/sh/boards/mach-sdk7780/irq.c
diff --git a/arch/sh/boards/renesas/sdk7780/setup.c b/arch/sh/boards/mach-sdk7780/setup.c
index acc5932587f1..acc5932587f1 100644
--- a/arch/sh/boards/renesas/sdk7780/setup.c
+++ b/arch/sh/boards/mach-sdk7780/setup.c
diff --git a/arch/sh/boards/se/7206/Makefile b/arch/sh/boards/mach-se/7206/Makefile
index 63e7ed699f39..63e7ed699f39 100644
--- a/arch/sh/boards/se/7206/Makefile
+++ b/arch/sh/boards/mach-se/7206/Makefile
diff --git a/arch/sh/boards/se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c
index 1308e618e044..9c3a33210d61 100644
--- a/arch/sh/boards/se/7206/io.c
+++ b/arch/sh/boards/mach-se/7206/io.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <asm/io.h>
-#include <asm/se7206.h>
+#include <mach-se/mach/se7206.h>
 
 
 static inline void delay(void)
diff --git a/arch/sh/boards/se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c
index 9d5bfc77d0de..aef7f052851a 100644
--- a/arch/sh/boards/se/7206/irq.c
+++ b/arch/sh/boards/mach-se/7206/irq.c
@@ -10,7 +10,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
-#include <asm/se7206.h>
+#include <mach-se/mach/se7206.h>
 
 #define INTSTS0 0x31800000
 #define INTSTS1 0x31800002
diff --git a/arch/sh/boards/se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c
index 4fe84cc08406..f5466384972e 100644
--- a/arch/sh/boards/se/7206/setup.c
+++ b/arch/sh/boards/mach-se/7206/setup.c
@@ -10,7 +10,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/smc91x.h>
-#include <asm/se7206.h>
+#include <mach-se/mach/se7206.h>
 #include <asm/io.h>
 #include <asm/machvec.h>
 #include <asm/heartbeat.h>
diff --git a/arch/sh/boards/se/7343/Makefile b/arch/sh/boards/mach-se/7343/Makefile
index 3024796c6203..3024796c6203 100644
--- a/arch/sh/boards/se/7343/Makefile
+++ b/arch/sh/boards/mach-se/7343/Makefile
diff --git a/arch/sh/boards/se/7343/io.c b/arch/sh/boards/mach-se/7343/io.c
index 3a6d11424938..8741abc1da7b 100644
--- a/arch/sh/boards/se/7343/io.c
+++ b/arch/sh/boards/mach-se/7343/io.c
@@ -6,7 +6,7 @@
  */
 #include <linux/kernel.h>
 #include <asm/io.h>
-#include <asm/mach/se7343.h>
+#include <mach-se/mach/se7343.h>
 
 #define badio(fn, a) panic("bad i/o operation %s for %08lx.", #fn, a)
 
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
new file mode 100644
index 000000000000..051c29d4eae0
--- /dev/null
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -0,0 +1,79 @@
+/*
+ * linux/arch/sh/boards/se/7343/irq.c
+ *
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * Based on linux/arch/sh/boards/se/7722/irq.c
+ * Copyright (C) 2007  Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <mach-se/mach/se7343.h>
+
+static void disable_se7343_irq(unsigned int irq)
+{
+        unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
+        ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
+}
+
+static void enable_se7343_irq(unsigned int irq)
+{
+        unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
+        ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
+}
+
+static struct irq_chip se7343_irq_chip __read_mostly = {
+        .name           = "SE7343-FPGA",
+        .mask           = disable_se7343_irq,
+        .unmask         = enable_se7343_irq,
+        .mask_ack       = disable_se7343_irq,
+};
+
+static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned short intv = ctrl_inw(PA_CPLD_ST);
+        struct irq_desc *ext_desc;
+        unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
+
+        intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
+
+        while (intv) {
+                if (intv & 1) {
+                        ext_desc = irq_desc + ext_irq;
+                        handle_level_irq(ext_irq, ext_desc);
+                }
+                intv >>= 1;
+                ext_irq++;
+        }
+}
+
+/*
+ * Initialize IRQ setting
+ */
+void __init init_7343se_IRQ(void)
+{
+        int i;
+
+        ctrl_outw(0, PA_CPLD_IMSK);     /* disable all irqs */
+        ctrl_outw(0x2000, 0xb03fffec);  /* mrshpc irq enable */
+
+        for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
+                set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
+                                              &se7343_irq_chip,
+                                              handle_level_irq, "level");
+
+        set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
+        set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+        set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
+        set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+        set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
+        set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
+        set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
+        set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
+}
diff --git a/arch/sh/boards/se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c
index c9431b3a051b..486f40bf9274 100644
--- a/arch/sh/boards/se/7343/setup.c
+++ b/arch/sh/boards/mach-se/7343/setup.c
@@ -1,10 +1,11 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
 #include <asm/machvec.h>
-#include <asm/mach/se7343.h>
+#include <mach-se/mach/se7343.h>
+#include <asm/heartbeat.h>
 #include <asm/irq.h>
-
-void init_7343se_IRQ(void);
+#include <asm/io.h>
 
 static struct resource smc91x_resources[] = {
         [0] = {
@@ -17,8 +18,8 @@ static struct resource smc91x_resources[] = {
                  * shared with other devices via externel
                  * interrupt controller in FPGA...
                  */
-                .start  = EXT_IRQ2,
-                .end    = EXT_IRQ2,
+                .start  = SMC_IRQ,
+                .end    = SMC_IRQ,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -38,16 +39,65 @@ static struct resource heartbeat_resources[] = {
         },
 };
 
+static struct heartbeat_data heartbeat_data = {
+        .regsize = 16,
+};
+
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
+        .dev = {
+                .platform_data = &heartbeat_data,
+        },
         .num_resources  = ARRAY_SIZE(heartbeat_resources),
         .resource       = heartbeat_resources,
 };
 
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 128 * 1024,
+        },
+        {
+                .name           = "rootfs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 31 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 2,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = 0x00000000,
+                .end    = 0x01ffffff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
 static struct platform_device *sh7343se_platform_devices[] __initdata = {
         &smc91x_device,
         &heartbeat_device,
+        &nor_flash_device,
 };
 
 static int __init sh7343se_devices_setup(void)
@@ -55,10 +105,19 @@ static int __init sh7343se_devices_setup(void)
         return platform_add_devices(sh7343se_platform_devices,
                                     ARRAY_SIZE(sh7343se_platform_devices));
 }
+device_initcall(sh7343se_devices_setup);
 
+/*
+ * Initialize the board
+ */
 static void __init sh7343se_setup(char **cmdline_p)
 {
-        device_initcall(sh7343se_devices_setup);
+        ctrl_outw(0xf900, FPGA_OUT);    /* FPGA */
+
+        ctrl_outw(0x0002, PORT_PECR);   /* PORT E 1 = IRQ5 */
+        ctrl_outw(0x0020, PORT_PSELD);
+
+        printk(KERN_INFO "MS7343CP01 Setup...done\n");
 }
 
 /*
@@ -90,5 +149,4 @@ static struct sh_machine_vector mv_7343se __initmv = {
         .mv_outsl = sh7343se_outsl,
 
         .mv_init_irq = init_7343se_IRQ,
-        .mv_irq_demux = shmse_irq_demux,
 };
diff --git a/arch/sh/boards/se/770x/Makefile b/arch/sh/boards/mach-se/770x/Makefile
index 8e624b06d5ea..8e624b06d5ea 100644
--- a/arch/sh/boards/se/770x/Makefile
+++ b/arch/sh/boards/mach-se/770x/Makefile
diff --git a/arch/sh/boards/se/770x/io.c b/arch/sh/boards/mach-se/770x/io.c
index c4550473d4c3..28833c8786ea 100644
--- a/arch/sh/boards/se/770x/io.c
+++ b/arch/sh/boards/mach-se/770x/io.c
@@ -1,24 +1,12 @@
-/* $Id: io.c,v 1.7 2006/02/05 21:55:29 lethal Exp $
- *
- * linux/arch/sh/kernel/io_se.c
- *
+/*
  * Copyright (C) 2000  Kazumoto Kojima
  *
  * I/O routine for Hitachi SolutionEngine.
- *
  */
-
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <asm/io.h>
-#include <asm/se.h>
-
-/* SH pcmcia io window base, start and end.  */
-int sh_pcic_io_wbase = 0xb8400000;
-int sh_pcic_io_start;
-int sh_pcic_io_stop;
-int sh_pcic_io_type;
-int sh_pcic_io_dummy;
+#include <mach-se/mach/se.h>
 
 /* MS7750 requires special versions of in*, out* routines, since
    PC-like io ports are located at upper half byte of 16-bit word which
@@ -33,8 +21,6 @@ port2adr(unsigned int port)
                 return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
         else if (port >= 0x1000)
                 return (volatile __u16 *) (PA_83902 + (port << 1));
-        else if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
-                return (volatile __u16 *) (sh_pcic_io_wbase + (port &~ 1));
         else
                 return (volatile __u16 *) (PA_SUPERIO + (port << 1));
 }
@@ -51,32 +37,27 @@ shifted_port(unsigned long port)
 
 unsigned char se_inb(unsigned long port)
 {
-        if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
-                return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); 
-        else if (shifted_port(port))
-                return (*port2adr(port) >> 8); 
+        if (shifted_port(port))
+                return (*port2adr(port) >> 8);
         else
-                return (*port2adr(port))&0xff; 
+                return (*port2adr(port))&0xff;
 }
 
 unsigned char se_inb_p(unsigned long port)
 {
         unsigned long v;
 
-        if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
-                v = *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); 
-        else if (shifted_port(port))
-                v = (*port2adr(port) >> 8); 
+        if (shifted_port(port))
+                v = (*port2adr(port) >> 8);
         else
-                v = (*port2adr(port))&0xff; 
+                v = (*port2adr(port))&0xff;
         ctrl_delay();
         return v;
 }
 
 unsigned short se_inw(unsigned long port)
 {
-        if (port >= 0x2000 ||
-            (sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
+        if (port >= 0x2000)
                 return *port2adr(port);
         else
                 maybebadio(port);
@@ -91,9 +72,7 @@ unsigned int se_inl(unsigned long port)
 
 void se_outb(unsigned char value, unsigned long port)
 {
-        if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
-                *(__u8 *)(sh_pcic_io_wbase + port) = value; 
-        else if (shifted_port(port))
+        if (shifted_port(port))
                 *(port2adr(port)) = value << 8;
         else
                 *(port2adr(port)) = value;
@@ -101,9 +80,7 @@ void se_outb(unsigned char value, unsigned long port)
 
 void se_outb_p(unsigned char value, unsigned long port)
 {
-        if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
-                *(__u8 *)(sh_pcic_io_wbase + port) = value; 
-        else if (shifted_port(port))
+        if (shifted_port(port))
                 *(port2adr(port)) = value << 8;
         else
                 *(port2adr(port)) = value;
@@ -112,8 +89,7 @@ void se_outb_p(unsigned char value, unsigned long port)
 
 void se_outw(unsigned short value, unsigned long port)
 {
-        if (port >= 0x2000 ||
-            (sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
+        if (port >= 0x2000)
                 *port2adr(port) = value;
         else
                 maybebadio(port);
@@ -129,11 +105,7 @@ void se_insb(unsigned long port, void *addr, unsigned long count)
         volatile __u16 *p = port2adr(port);
         __u8 *ap = addr;
 
-        if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) {
-                volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + 0x40000 + port); 
-                while (count--)
-                        *ap++ = *bp;
-        } else if (shifted_port(port)) {
+        if (shifted_port(port)) {
                 while (count--)
                         *ap++ = *p >> 8;
         } else {
@@ -160,11 +132,7 @@ void se_outsb(unsigned long port, const void *addr, unsigned long count)
         volatile __u16 *p = port2adr(port);
         const __u8 *ap = addr;
 
-        if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) {
-                volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + port); 
-                while (count--)
-                        *bp = *ap++;
-        } else if (shifted_port(port)) {
+        if (shifted_port(port)) {
                 while (count--)
                         *p = *ap++ << 8;
         } else {
@@ -177,6 +145,7 @@ void se_outsw(unsigned long port, const void *addr, unsigned long count)
 {
         volatile __u16 *p = port2adr(port);
         const __u16 *ap = addr;
+
         while (count--)
                 *p = *ap++;
 }
diff --git a/arch/sh/boards/se/770x/irq.c b/arch/sh/boards/mach-se/770x/irq.c
index cdb0807928a5..ec1fea571b52 100644
--- a/arch/sh/boards/se/770x/irq.c
+++ b/arch/sh/boards/mach-se/770x/irq.c
@@ -13,7 +13,7 @@
 #include <linux/irq.h>
 #include <asm/irq.h>
 #include <asm/io.h>
-#include <asm/se.h>
+#include <mach-se/mach/se.h>
 
 static struct ipr_data ipr_irq_table[] = {
         /*
diff --git a/arch/sh/boards/se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c
index 318bc8a3969c..9123d9687bf7 100644
--- a/arch/sh/boards/se/770x/setup.c
+++ b/arch/sh/boards/mach-se/770x/setup.c
@@ -9,13 +9,11 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <asm/machvec.h>
-#include <asm/se.h>
+#include <mach-se/mach/se.h>
 #include <asm/io.h>
 #include <asm/smc37c93x.h>
 #include <asm/heartbeat.h>
 
-void init_se_IRQ(void);
-
 /*
  * Configure the Super I/O chip
  */
@@ -73,7 +71,7 @@ static struct resource cf_ide_resources[] = {
         },
         [1] = {
                 .start  = PA_MRSHPC_IO + 0x1f0 + 0x206,
-                .end    = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
+                .end    = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
@@ -115,9 +113,64 @@ static struct platform_device heartbeat_device = {
         .resource       = heartbeat_resources,
 };
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
+        defined(CONFIG_CPU_SUBTYPE_SH7712)
+/* SH771X Ethernet driver */
+static struct resource sh_eth0_resources[] = {
+        [0] = {
+                .start = SH_ETH0_BASE,
+                .end = SH_ETH0_BASE + 0x1B8,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = SH_ETH0_IRQ,
+                .end = SH_ETH0_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sh_eth0_device = {
+        .name = "sh-eth",
+        .id     = 0,
+        .dev = {
+                .platform_data = PHY_ID,
+        },
+        .num_resources = ARRAY_SIZE(sh_eth0_resources),
+        .resource = sh_eth0_resources,
+};
+
+static struct resource sh_eth1_resources[] = {
+        [0] = {
+                .start = SH_ETH1_BASE,
+                .end = SH_ETH1_BASE + 0x1B8,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = SH_ETH1_IRQ,
+                .end = SH_ETH1_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sh_eth1_device = {
+        .name = "sh-eth",
+        .id     = 1,
+        .dev = {
+                .platform_data = PHY_ID,
+        },
+        .num_resources = ARRAY_SIZE(sh_eth1_resources),
+        .resource = sh_eth1_resources,
+};
+#endif
+
 static struct platform_device *se_devices[] __initdata = {
         &heartbeat_device,
         &cf_ide_device,
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
+        defined(CONFIG_CPU_SUBTYPE_SH7712)
+        &sh_eth0_device,
+        &sh_eth1_device,
+#endif
 };
 
 static int __init se_devices_setup(void)
diff --git a/arch/sh/boards/se/7721/Makefile b/arch/sh/boards/mach-se/7721/Makefile
index 7f09030980b3..7f09030980b3 100644
--- a/arch/sh/boards/se/7721/Makefile
+++ b/arch/sh/boards/mach-se/7721/Makefile
diff --git a/arch/sh/boards/se/7721/irq.c b/arch/sh/boards/mach-se/7721/irq.c
index c4fdd622bf8b..b417acc4dad0 100644
--- a/arch/sh/boards/se/7721/irq.c
+++ b/arch/sh/boards/mach-se/7721/irq.c
@@ -11,7 +11,7 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <asm/se7721.h>
+#include <mach-se/mach/se7721.h>
 
 enum {
         UNUSED = 0,
diff --git a/arch/sh/boards/se/7721/setup.c b/arch/sh/boards/mach-se/7721/setup.c
index 1be3e92752f7..d3fc80ff4d83 100644
--- a/arch/sh/boards/se/7721/setup.c
+++ b/arch/sh/boards/mach-se/7721/setup.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <asm/machvec.h>
-#include <asm/se7721.h>
+#include <mach-se/mach/se7721.h>
 #include <asm/io.h>
 #include <asm/heartbeat.h>
 
diff --git a/arch/sh/boards/se/7722/Makefile b/arch/sh/boards/mach-se/7722/Makefile
index 8694373389e5..8694373389e5 100644
--- a/arch/sh/boards/se/7722/Makefile
+++ b/arch/sh/boards/mach-se/7722/Makefile
diff --git a/arch/sh/boards/se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index 0b03f3f610b8..02d21a3e2a8f 100644
--- a/arch/sh/boards/se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -14,7 +14,7 @@
 #include <linux/interrupt.h>
 #include <asm/irq.h>
 #include <asm/io.h>
-#include <asm/se7722.h>
+#include <mach-se/mach/se7722.h>
 
 static void disable_se7722_irq(unsigned int irq)
 {
diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index ede3957fc14a..fe6f96517e12 100644
--- a/arch/sh/boards/se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -16,7 +16,8 @@
 #include <linux/input.h>
 #include <linux/smc91x.h>
 #include <asm/machvec.h>
-#include <asm/se7722.h>
+#include <asm/clock.h>
+#include <mach-se/mach/se7722.h>
 #include <asm/io.h>
 #include <asm/heartbeat.h>
 #include <asm/sh_keysc.h>
@@ -145,6 +146,8 @@ static struct platform_device *se7722_devices[] __initdata = {
 
 static int __init se7722_devices_setup(void)
 {
+        clk_always_enable("mstp214"); /* KEYSC */
+
         return platform_add_devices(se7722_devices,
                 ARRAY_SIZE(se7722_devices));
 }
@@ -154,11 +157,6 @@ static void __init se7722_setup(char **cmdline_p)
 {
         ctrl_outw(0x010D, FPGA_OUT);    /* FPGA */
 
-        ctrl_outl(0x00051001, MSTPCR0);
-        ctrl_outl(0x00000000, MSTPCR1);
-        /* KEYSC, VOU, BEU, CEU, VEU, VPU, LCDC, USB */
-        ctrl_outl(0xffffb7c0, MSTPCR2);
-
         ctrl_outw(0x0000, PORT_PECR);   /* PORT E 1 = IRQ5 ,E 0 = BS */
         ctrl_outw(0x1000, PORT_PJCR);   /* PORT J 1 = IRQ1,J 0 =IRQ0 */
 
diff --git a/arch/sh/boards/se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile
index dbc29f3a9de5..dbc29f3a9de5 100644
--- a/arch/sh/boards/se/7751/Makefile
+++ b/arch/sh/boards/mach-se/7751/Makefile
diff --git a/arch/sh/boards/se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c
index e8d846cec89d..6287ae570319 100644
--- a/arch/sh/boards/se/7751/io.c
+++ b/arch/sh/boards/mach-se/7751/io.c
@@ -12,7 +12,7 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <asm/io.h>
-#include <asm/se7751.h>
+#include <mach-se/mach/se7751.h>
 #include <asm/addrspace.h>
 
 static inline volatile u16 *port2adr(unsigned int port)
diff --git a/arch/sh/boards/se/7751/irq.c b/arch/sh/boards/mach-se/7751/irq.c
index c3d12590e5db..5c9847ea1e7c 100644
--- a/arch/sh/boards/se/7751/irq.c
+++ b/arch/sh/boards/mach-se/7751/irq.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/irq.h>
-#include <asm/se7751.h>
+#include <mach-se/mach/se7751.h>
 
 static struct ipr_data ipr_irq_table[] = {
         { 13, 3, 3, 2 },
diff --git a/arch/sh/boards/se/7751/pci.c b/arch/sh/boards/mach-se/7751/pci.c
index 203b2923fe7f..203b2923fe7f 100644
--- a/arch/sh/boards/se/7751/pci.c
+++ b/arch/sh/boards/mach-se/7751/pci.c
diff --git a/arch/sh/boards/se/7751/setup.c b/arch/sh/boards/mach-se/7751/setup.c
index deefbfd92591..50572512e3e8 100644
--- a/arch/sh/boards/se/7751/setup.c
+++ b/arch/sh/boards/mach-se/7751/setup.c
@@ -11,7 +11,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <asm/machvec.h>
-#include <asm/se7751.h>
+#include <mach-se/mach/se7751.h>
 #include <asm/io.h>
 #include <asm/heartbeat.h>
 
diff --git a/arch/sh/boards/se/7780/Makefile b/arch/sh/boards/mach-se/7780/Makefile
index 6b88adae3ecc..6b88adae3ecc 100644
--- a/arch/sh/boards/se/7780/Makefile
+++ b/arch/sh/boards/mach-se/7780/Makefile
diff --git a/arch/sh/boards/se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c
index 6bd70da6bb47..66ad292c9fc3 100644
--- a/arch/sh/boards/se/7780/irq.c
+++ b/arch/sh/boards/mach-se/7780/irq.c
@@ -14,7 +14,7 @@
 #include <linux/interrupt.h>
 #include <asm/irq.h>
 #include <asm/io.h>
-#include <asm/se7780.h>
+#include <mach-se/mach/se7780.h>
 
 /*
  * Initialize IRQ setting
diff --git a/arch/sh/boards/se/7780/setup.c b/arch/sh/boards/mach-se/7780/setup.c
index 0f08ab3b2bec..1d3a867e94e3 100644
--- a/arch/sh/boards/se/7780/setup.c
+++ b/arch/sh/boards/mach-se/7780/setup.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <asm/machvec.h>
-#include <asm/se7780.h>
+#include <mach-se/mach/se7780.h>
 #include <asm/io.h>
 #include <asm/heartbeat.h>
 
diff --git a/arch/sh/boards/mach-se/Makefile b/arch/sh/boards/mach-se/Makefile
new file mode 100644
index 000000000000..2de42bae4b4f
--- /dev/null
+++ b/arch/sh/boards/mach-se/Makefile
@@ -0,0 +1,9 @@
+obj-$(CONFIG_SH_7619_SOLUTION_ENGINE)   += board-se7619.o
+
+obj-$(CONFIG_SH_SOLUTION_ENGINE)        += 770x/
+obj-$(CONFIG_SH_7206_SOLUTION_ENGINE)   += 7206/
+obj-$(CONFIG_SH_7722_SOLUTION_ENGINE)   += 7722/
+obj-$(CONFIG_SH_7751_SOLUTION_ENGINE)   += 7751/
+obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)   += 7780/
+obj-$(CONFIG_SH_7343_SOLUTION_ENGINE)   += 7343/
+obj-$(CONFIG_SH_7721_SOLUTION_ENGINE)   += 7721/
diff --git a/arch/sh/boards/se/7619/setup.c b/arch/sh/boards/mach-se/board-se7619.c
index 1d0ef7faa10d..1d0ef7faa10d 100644
--- a/arch/sh/boards/se/7619/setup.c
+++ b/arch/sh/boards/mach-se/board-se7619.c
diff --git a/arch/sh/boards/sh03/Makefile b/arch/sh/boards/mach-sh03/Makefile
index 400306a796ec..400306a796ec 100644
--- a/arch/sh/boards/sh03/Makefile
+++ b/arch/sh/boards/mach-sh03/Makefile
diff --git a/arch/sh/boards/sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c
index 0a9266bb51c5..0a9266bb51c5 100644
--- a/arch/sh/boards/sh03/rtc.c
+++ b/arch/sh/boards/mach-sh03/rtc.c
diff --git a/arch/sh/boards/sh03/setup.c b/arch/sh/boards/mach-sh03/setup.c
index 934ac4f1c48f..5771219be3fd 100644
--- a/arch/sh/boards/sh03/setup.c
+++ b/arch/sh/boards/mach-sh03/setup.c
@@ -11,8 +11,8 @@
 #include <linux/platform_device.h>
 #include <asm/io.h>
 #include <asm/rtc.h>
-#include <asm/sh03/io.h>
-#include <asm/sh03/sh03.h>
+#include <mach-sh03/mach/io.h>
+#include <mach-sh03/mach/sh03.h>
 #include <asm/addrspace.h>
 
 static void __init init_sh03_IRQ(void)
diff --git a/arch/sh/boards/mach-sh7763rdp/Makefile b/arch/sh/boards/mach-sh7763rdp/Makefile
new file mode 100644
index 000000000000..f6c0b55516d2
--- /dev/null
+++ b/arch/sh/boards/mach-sh7763rdp/Makefile
@@ -0,0 +1 @@
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/mach-sh7763rdp/irq.c b/arch/sh/boards/mach-sh7763rdp/irq.c
new file mode 100644
index 000000000000..fd850bad2dec
--- /dev/null
+++ b/arch/sh/boards/mach-sh7763rdp/irq.c
@@ -0,0 +1,45 @@
+/*
+ * linux/arch/sh/boards/renesas/sh7763rdp/irq.c
+ *
+ * Renesas Solutions SH7763RDP Support.
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008  Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sh7763rdp.h>
+
+#define INTC_BASE               (0xFFD00000)
+#define INTC_INT2PRI7   (INTC_BASE+0x4001C)
+#define INTC_INT2MSKCR  (INTC_BASE+0x4003C)
+#define INTC_INT2MSKCR1 (INTC_BASE+0x400D4)
+
+/*
+ * Initialize IRQ setting
+ */
+void __init init_sh7763rdp_IRQ(void)
+{
+        /* GPIO enabled */
+        ctrl_outl(1 << 25, INTC_INT2MSKCR);
+
+        /* enable GPIO interrupts */
+        ctrl_outl((ctrl_inl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
+                  INTC_INT2PRI7);
+
+        /* USBH enabled */
+        ctrl_outl(1 << 17, INTC_INT2MSKCR1);
+
+        /* GETHER enabled */
+        ctrl_outl(1 << 16, INTC_INT2MSKCR1);
+
+        /* DMAC enabled */
+        ctrl_outl(1 << 8, INTC_INT2MSKCR);
+}
diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
new file mode 100644
index 000000000000..925f16af7121
--- /dev/null
+++ b/arch/sh/boards/mach-sh7763rdp/setup.c
@@ -0,0 +1,128 @@
+/*
+ * linux/arch/sh/boards/renesas/sh7763rdp/setup.c
+ *
+ * Renesas Solutions sh7763rdp board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/mtd/physmap.h>
+#include <asm/io.h>
+#include <asm/sh7763rdp.h>
+
+/* NOR Flash */
+static struct mtd_partition sh7763rdp_nor_flash_partitions[] = {
+        {
+                .name = "U-Boot",
+                .offset = 0,
+                .size = (2 * 128 * 1024),
+                .mask_flags = MTD_WRITEABLE,    /* Read-only */
+        }, {
+                .name = "Linux-Kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size = (20 * 128 * 1024),
+        }, {
+                .name = "Root Filesystem",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data sh7763rdp_nor_flash_data = {
+        .width = 2,
+        .parts = sh7763rdp_nor_flash_partitions,
+        .nr_parts = ARRAY_SIZE(sh7763rdp_nor_flash_partitions),
+};
+
+static struct resource sh7763rdp_nor_flash_resources[] = {
+        [0] = {
+                .name = "NOR Flash",
+                .start = 0,
+                .end = (64 * 1024 * 1024),
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device sh7763rdp_nor_flash_device = {
+        .name = "physmap-flash",
+        .resource = sh7763rdp_nor_flash_resources,
+        .num_resources = ARRAY_SIZE(sh7763rdp_nor_flash_resources),
+        .dev = {
+                .platform_data = &sh7763rdp_nor_flash_data,
+        },
+};
+
+static struct platform_device *sh7763rdp_devices[] __initdata = {
+        &sh7763rdp_nor_flash_device,
+};
+
+static int __init sh7763rdp_devices_setup(void)
+{
+        return platform_add_devices(sh7763rdp_devices,
+                                    ARRAY_SIZE(sh7763rdp_devices));
+}
+__initcall(sh7763rdp_devices_setup);
+
+static void __init sh7763rdp_setup(char **cmdline_p)
+{
+        /* Board version check */
+        if (ctrl_inw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
+                printk(KERN_INFO "RTE Standard Configuration\n");
+        else
+                printk(KERN_INFO "RTA Standard Configuration\n");
+
+        /* USB pin select bits (clear bit 5-2 to 0) */
+        ctrl_outw((ctrl_inw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
+        /* USBH setup port I controls to other (clear bits 4-9 to 0) */
+        ctrl_outw(ctrl_inw(PORT_PICR) & 0xFC0F, PORT_PICR);
+
+        /* Select USB Host controller */
+        ctrl_outw(0x00, USB_USBHSC);
+
+        /* For LCD */
+        /* set PTJ7-1, bits 15-2 of PJCR to 0 */
+        ctrl_outw(ctrl_inw(PORT_PJCR) & 0x0003, PORT_PJCR);
+        /* set PTI5, bits 11-10 of PICR to 0 */
+        ctrl_outw(ctrl_inw(PORT_PICR) & 0xF3FF, PORT_PICR);
+        ctrl_outw(0, PORT_PKCR);
+        ctrl_outw(0, PORT_PLCR);
+        /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */
+        ctrl_outw((ctrl_inw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
+        /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */
+        ctrl_outw((ctrl_inw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
+
+        /* For HAC */
+        /* bit3-0  0100:HAC & SSI1 enable */
+        ctrl_outw((ctrl_inw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
+        /* bit14      1:SSI_HAC_CLK enable */
+        ctrl_outw(ctrl_inw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
+
+        /* SH-Ether */
+        ctrl_outw((ctrl_inw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
+        ctrl_outw(0x0, PORT_PFCR);
+        ctrl_outw(0x0, PORT_PFCR);
+        ctrl_outw(0x0, PORT_PFCR);
+
+        /* MMC */
+        /*selects SCIF and MMC other functions */
+        ctrl_outw(0x0001, PORT_PSEL0);
+        /* MMC clock operates */
+        ctrl_outl(ctrl_inl(MSTPCR1) & ~0x8, MSTPCR1);
+        ctrl_outw(ctrl_inw(PORT_PACR) & ~0x3000, PORT_PACR);
+        ctrl_outw(ctrl_inw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
+}
+
+static struct sh_machine_vector mv_sh7763rdp __initmv = {
+        .mv_name = "sh7763drp",
+        .mv_setup = sh7763rdp_setup,
+        .mv_nr_irqs = 112,
+        .mv_init_irq = init_sh7763rdp_IRQ,
+};
diff --git a/arch/sh/boards/snapgear/Makefile b/arch/sh/boards/mach-snapgear/Makefile
index d2d2f4b6a502..d2d2f4b6a502 100644
--- a/arch/sh/boards/snapgear/Makefile
+++ b/arch/sh/boards/mach-snapgear/Makefile
diff --git a/arch/sh/boards/snapgear/io.c b/arch/sh/boards/mach-snapgear/io.c
index 0f4824264557..0f4824264557 100644
--- a/arch/sh/boards/snapgear/io.c
+++ b/arch/sh/boards/mach-snapgear/io.c
diff --git a/arch/sh/boards/snapgear/setup.c b/arch/sh/boards/mach-snapgear/setup.c
index 7022483f98e8..a5e349d3dda2 100644
--- a/arch/sh/boards/snapgear/setup.c
+++ b/arch/sh/boards/mach-snapgear/setup.c
@@ -22,7 +22,7 @@
 #include <asm/snapgear.h>
 #include <asm/irq.h>
 #include <asm/io.h>
-#include <asm/cpu/timer.h>
+#include <cpu/timer.h>
 
 /*
  * EraseConfig handling functions
diff --git a/arch/sh/boards/renesas/systemh/Makefile b/arch/sh/boards/mach-systemh/Makefile
index 2cc6a23d9d39..2cc6a23d9d39 100644
--- a/arch/sh/boards/renesas/systemh/Makefile
+++ b/arch/sh/boards/mach-systemh/Makefile
diff --git a/arch/sh/boards/renesas/systemh/io.c b/arch/sh/boards/mach-systemh/io.c
index 1b767e1a1428..1b767e1a1428 100644
--- a/arch/sh/boards/renesas/systemh/io.c
+++ b/arch/sh/boards/mach-systemh/io.c
diff --git a/arch/sh/boards/renesas/systemh/irq.c b/arch/sh/boards/mach-systemh/irq.c
index 0ba2fe674c47..601c9c8cdbec 100644
--- a/arch/sh/boards/renesas/systemh/irq.c
+++ b/arch/sh/boards/mach-systemh/irq.c
@@ -11,9 +11,8 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
 
-#include <linux/hdreg.h>
-#include <linux/ide.h>
 #include <asm/io.h>
 #include <asm/systemh7751.h>
 #include <asm/smc37c93x.h>
diff --git a/arch/sh/boards/renesas/systemh/setup.c b/arch/sh/boards/mach-systemh/setup.c
index ee78af842778..ee78af842778 100644
--- a/arch/sh/boards/renesas/systemh/setup.c
+++ b/arch/sh/boards/mach-systemh/setup.c
diff --git a/arch/sh/boards/titan/Makefile b/arch/sh/boards/mach-titan/Makefile
index 08d753700062..08d753700062 100644
--- a/arch/sh/boards/titan/Makefile
+++ b/arch/sh/boards/mach-titan/Makefile
diff --git a/arch/sh/boards/titan/io.c b/arch/sh/boards/mach-titan/io.c
index 4730c1dd697d..4730c1dd697d 100644
--- a/arch/sh/boards/titan/io.c
+++ b/arch/sh/boards/mach-titan/io.c
diff --git a/arch/sh/boards/titan/setup.c b/arch/sh/boards/mach-titan/setup.c
index 5de3b2ad71af..5de3b2ad71af 100644
--- a/arch/sh/boards/titan/setup.c
+++ b/arch/sh/boards/mach-titan/setup.c
diff --git a/arch/sh/boards/renesas/x3proto/Makefile b/arch/sh/boards/mach-x3proto/Makefile
index 983e4551fecf..983e4551fecf 100644
--- a/arch/sh/boards/renesas/x3proto/Makefile
+++ b/arch/sh/boards/mach-x3proto/Makefile
diff --git a/arch/sh/boards/renesas/x3proto/ilsel.c b/arch/sh/boards/mach-x3proto/ilsel.c
index b5c673c39337..b5c673c39337 100644
--- a/arch/sh/boards/renesas/x3proto/ilsel.c
+++ b/arch/sh/boards/mach-x3proto/ilsel.c
diff --git a/arch/sh/boards/renesas/x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c
index abc5b6d418fe..abc5b6d418fe 100644
--- a/arch/sh/boards/renesas/x3proto/setup.c
+++ b/arch/sh/boards/mach-x3proto/setup.c
diff --git a/arch/sh/boards/magicpanelr2/Kconfig b/arch/sh/boards/magicpanelr2/Kconfig
deleted file mode 100644
index b0abddc3e84f..000000000000
--- a/arch/sh/boards/magicpanelr2/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-if SH_MAGIC_PANEL_R2
-
-menu "Magic Panel R2 options"
-
-config SH_MAGIC_PANEL_R2_VERSION
-        int SH_MAGIC_PANEL_R2_VERSION
-        default "3"
-        help
-          Set the version of the Magic Panel R2
-
-endmenu
-
-endif
diff --git a/arch/sh/boards/magicpanelr2/Makefile b/arch/sh/boards/magicpanelr2/Makefile
deleted file mode 100644
index 7a6d586b9072..000000000000
--- a/arch/sh/boards/magicpanelr2/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Magic Panel specific parts
-#
-
-obj-y    := setup.o
\ No newline at end of file
diff --git a/arch/sh/boards/renesas/migor/Makefile b/arch/sh/boards/renesas/migor/Makefile
deleted file mode 100644
index 77037567633b..000000000000
--- a/arch/sh/boards/renesas/migor/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y    := setup.o
diff --git a/arch/sh/boards/renesas/migor/setup.c b/arch/sh/boards/renesas/migor/setup.c
deleted file mode 100644
index 963c99322095..000000000000
--- a/arch/sh/boards/renesas/migor/setup.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Renesas System Solutions Asia Pte. Ltd - Migo-R
- *
- * Copyright (C) 2008 Magnus Damm
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/input.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/nand.h>
-#include <linux/i2c.h>
-#include <linux/smc91x.h>
-#include <asm/machvec.h>
-#include <asm/io.h>
-#include <asm/sh_keysc.h>
-#include <asm/migor.h>
-
-/* Address     IRQ  Size  Bus  Description
- * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
- * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
- * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
- * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
- * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
- */
-
-static struct smc91x_platdata smc91x_info = {
-        .flags = SMC91X_USE_16BIT,
-};
-
-static struct resource smc91x_eth_resources[] = {
-        [0] = {
-                .name   = "SMC91C111" ,
-                .start  = 0x10000300,
-                .end    = 0x1000030f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 32, /* IRQ0 */
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
-};
-
-static struct platform_device smc91x_eth_device = {
-        .name           = "smc91x",
-        .num_resources  = ARRAY_SIZE(smc91x_eth_resources),
-        .resource       = smc91x_eth_resources,
-        .dev    = {
-                .platform_data  = &smc91x_info,
-        },
-};
-
-static struct sh_keysc_info sh_keysc_info = {
-        .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
-        .scan_timing = 3,
-        .delay = 5,
-        .keycodes = {
-                0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
-                0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
-                0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
-                0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
-                0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
-        },
-};
-
-static struct resource sh_keysc_resources[] = {
-        [0] = {
-                .start  = 0x044b0000,
-                .end    = 0x044b000f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 79,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device sh_keysc_device = {
-        .name           = "sh_keysc",
-        .num_resources  = ARRAY_SIZE(sh_keysc_resources),
-        .resource       = sh_keysc_resources,
-        .dev    = {
-                .platform_data  = &sh_keysc_info,
-        },
-};
-
-static struct mtd_partition migor_nor_flash_partitions[] =
-{
-        {
-                .name = "uboot",
-                .offset = 0,
-                .size = (1 * 1024 * 1024),
-                .mask_flags = MTD_WRITEABLE,    /* Read-only */
-        },
-        {
-                .name = "rootfs",
-                .offset = MTDPART_OFS_APPEND,
-                .size = (15 * 1024 * 1024),
-        },
-        {
-                .name = "other",
-                .offset = MTDPART_OFS_APPEND,
-                .size = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct physmap_flash_data migor_nor_flash_data = {
-        .width          = 2,
-        .parts          = migor_nor_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(migor_nor_flash_partitions),
-};
-
-static struct resource migor_nor_flash_resources[] = {
-        [0] = {
-                .name           = "NOR Flash",
-                .start          = 0x00000000,
-                .end            = 0x03ffffff,
-                .flags          = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device migor_nor_flash_device = {
-        .name           = "physmap-flash",
-        .resource       = migor_nor_flash_resources,
-        .num_resources  = ARRAY_SIZE(migor_nor_flash_resources),
-        .dev            = {
-                .platform_data = &migor_nor_flash_data,
-        },
-};
-
-static struct mtd_partition migor_nand_flash_partitions[] = {
-        {
-                .name           = "nanddata1",
-                .offset         = 0x0,
-                .size           = 512 * 1024 * 1024,
-        },
-        {
-                .name           = "nanddata2",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 512 * 1024 * 1024,
-        },
-};
-
-static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
-                                     unsigned int ctrl)
-{
-        struct nand_chip *chip = mtd->priv;
-
-        if (cmd == NAND_CMD_NONE)
-                return;
-
-        if (ctrl & NAND_CLE)
-                writeb(cmd, chip->IO_ADDR_W + 0x00400000);
-        else if (ctrl & NAND_ALE)
-                writeb(cmd, chip->IO_ADDR_W + 0x00800000);
-        else
-                writeb(cmd, chip->IO_ADDR_W);
-}
-
-static int migor_nand_flash_ready(struct mtd_info *mtd)
-{
-        return ctrl_inb(PORT_PADR) & 0x02; /* PTA1 */
-}
-
-struct platform_nand_data migor_nand_flash_data = {
-        .chip = {
-                .nr_chips = 1,
-                .partitions = migor_nand_flash_partitions,
-                .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
-                .chip_delay = 20,
-                .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
-        },
-        .ctrl = {
-                .dev_ready = migor_nand_flash_ready,
-                .cmd_ctrl = migor_nand_flash_cmd_ctl,
-        },
-};
-
-static struct resource migor_nand_flash_resources[] = {
-        [0] = {
-                .name           = "NAND Flash",
-                .start          = 0x18000000,
-                .end            = 0x18ffffff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device migor_nand_flash_device = {
-        .name           = "gen_nand",
-        .resource       = migor_nand_flash_resources,
-        .num_resources  = ARRAY_SIZE(migor_nand_flash_resources),
-        .dev            = {
-                .platform_data = &migor_nand_flash_data,
-        }
-};
-
-static struct platform_device *migor_devices[] __initdata = {
-        &smc91x_eth_device,
-        &sh_keysc_device,
-        &migor_nor_flash_device,
-        &migor_nand_flash_device,
-};
-
-static struct i2c_board_info __initdata migor_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("rs5c372b", 0x32),
-        },
-        {
-                I2C_BOARD_INFO("migor_ts", 0x51),
-                .irq = 38, /* IRQ6 */
-        },
-};
-
-static int __init migor_devices_setup(void)
-{
-        i2c_register_board_info(0, migor_i2c_devices,
-                                ARRAY_SIZE(migor_i2c_devices));
- 
-        return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
-}
-__initcall(migor_devices_setup);
-
-static void __init migor_setup(char **cmdline_p)
-{
-        /* SMC91C111 - Enable IRQ0 */
-        ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR);
-
-        /* KEYSC */
-        ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR);
-        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR);
-        ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA);
-        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
-        ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
-        ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2);
-
-        /* NAND Flash */
-        ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR);
-        ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200,
-                  BSC_CS6ABCR);
-
-        /* I2C */
-        ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1);
-
-        /* Touch Panel - Enable IRQ6 */
-        ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR);
-        ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA);
-        ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC);
-}
-
-static struct sh_machine_vector mv_migor __initmv = {
-        .mv_name                = "Migo-R",
-        .mv_setup               = migor_setup,
-};
diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c
deleted file mode 100644
index 763f6deba814..000000000000
--- a/arch/sh/boards/se/7343/irq.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * arch/sh/boards/se/7343/irq.c
- *
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/mach/se7343.h>
-
-static void
-disable_intreq_irq(unsigned int irq)
-{
-        int bit = irq - OFFCHIP_IRQ_BASE;
-        u16 val;
-
-        val = ctrl_inw(PA_CPLD_IMSK);
-        val |= 1 << bit;
-        ctrl_outw(val, PA_CPLD_IMSK);
-}
-
-static void
-enable_intreq_irq(unsigned int irq)
-{
-        int bit = irq - OFFCHIP_IRQ_BASE;
-        u16 val;
-
-        val = ctrl_inw(PA_CPLD_IMSK);
-        val &= ~(1 << bit);
-        ctrl_outw(val, PA_CPLD_IMSK);
-}
-
-static void
-mask_and_ack_intreq_irq(unsigned int irq)
-{
-        disable_intreq_irq(irq);
-}
-
-static unsigned int
-startup_intreq_irq(unsigned int irq)
-{
-        enable_intreq_irq(irq);
-        return 0;
-}
-
-static void
-shutdown_intreq_irq(unsigned int irq)
-{
-        disable_intreq_irq(irq);
-}
-
-static void
-end_intreq_irq(unsigned int irq)
-{
-        if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-                enable_intreq_irq(irq);
-}
-
-static struct hw_interrupt_type intreq_irq_type = {
-        .typename = "FPGA-IRQ",
-        .startup = startup_intreq_irq,
-        .shutdown = shutdown_intreq_irq,
-        .enable = enable_intreq_irq,
-        .disable = disable_intreq_irq,
-        .ack = mask_and_ack_intreq_irq,
-        .end = end_intreq_irq
-};
-
-static void
-make_intreq_irq(unsigned int irq)
-{
-        disable_irq_nosync(irq);
-        irq_desc[irq].chip = &intreq_irq_type;
-        disable_intreq_irq(irq);
-}
-
-int
-shmse_irq_demux(int irq)
-{
-        int bit;
-        volatile u16 val;
-
-        if (irq == IRQ5_IRQ) {
-                /* Read status Register */
-                val = ctrl_inw(PA_CPLD_ST);
-                bit = ffs(val);
-                if (bit != 0)
-                        return OFFCHIP_IRQ_BASE + bit - 1;
-        }
-        return irq;
-}
-
-/* IRQ5 is multiplexed between the following sources:
- * 1. PC Card socket
- * 2. Extension slot
- * 3. USB Controller
- * 4. Serial Controller
- *
- * We configure IRQ5 as a cascade IRQ.
- */
-static struct irqaction irq5 = {
-        .handler = no_action,
-        .mask = CPU_MASK_NONE,
-        .name = "IRQ5-cascade",
-};
-
-static struct ipr_data se7343_irq5_ipr_map[] = {
-        { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
-};
-static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
-        { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
-        { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
-};
-static struct ipr_data se7343_other_ipr_map[] = {
-        { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
-        { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
-        { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
-        { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
-        { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
-        { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
-
-        /* I2C block */
-        { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
-        { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
-        { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
-        { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
-
-        { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
-        { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
-        { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
-        { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
-
-        /* SIOF */
-        { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
-
-        /* SIU */
-        { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
-
-        /* VIO interrupt */
-        { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
-        { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
-        { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
-
-        /*MFI interrupt*/
-
-        { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
-
-        /* LCD controller */
-        { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
-};
-
-/*
- * Initialize IRQ setting
- */
-void __init
-init_7343se_IRQ(void)
-{
-        /* Setup Multiplexed interrupts */
-        ctrl_outw(8, PA_CPLD_MODESET);  /* Set all CPLD interrupts to active
-                                         * low.
-                                         */
-        /* Mask all CPLD controller interrupts */
-        ctrl_outw(0x0fff, PA_CPLD_IMSK);
-
-        /* PC Card interrupts */
-        make_intreq_irq(PC_IRQ0);
-        make_intreq_irq(PC_IRQ1);
-        make_intreq_irq(PC_IRQ2);
-        make_intreq_irq(PC_IRQ3);
-
-        /* Extension Slot Interrupts */
-        make_intreq_irq(EXT_IRQ0);
-        make_intreq_irq(EXT_IRQ1);
-        make_intreq_irq(EXT_IRQ2);
-        make_intreq_irq(EXT_IRQ3);
-
-        /* USB Controller interrupts */
-        make_intreq_irq(USB_IRQ0);
-        make_intreq_irq(USB_IRQ1);
-
-        /* Serial Controller interrupts */
-        make_intreq_irq(UART_IRQ0);
-        make_intreq_irq(UART_IRQ1);
-
-        /* Setup all external interrupts to be active low */
-        ctrl_outw(0xaaaa, INTC_ICR1);
-
-        make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
-
-        setup_irq(IRQ5_IRQ, &irq5);
-        /* Set port control to use IRQ5 */
-        *(u16 *)0xA4050108 &= ~0xc;
-
-        make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
-
-        ctrl_outb(0x0f, INTC_IMCR5);    /* enable SCIF IRQ */
-
-        make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
-
-        ctrl_outw(0x2000, PA_MRSHPC + 0x0c);    /* mrshpc irq enable */
-}
diff --git a/arch/sh/boards/se/7619/Makefile b/arch/sh/boards/se/7619/Makefile
deleted file mode 100644
index d21775c28cda..000000000000
--- a/arch/sh/boards/se/7619/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the 7619 SolutionEngine specific parts of the kernel
-#
-
-obj-y    := setup.o
diff --git a/arch/sh/boards/shmin/Makefile b/arch/sh/boards/shmin/Makefile
deleted file mode 100644
index 3190cc72430e..000000000000
--- a/arch/sh/boards/shmin/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the SHMIN board.
-#
-
-obj-y    := setup.o
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index 89b408620dcb..5b54965eef98 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -18,9 +18,10 @@ CONFIG_PAGE_OFFSET	?= 0x80000000
 CONFIG_MEMORY_START     ?= 0x0c000000
 CONFIG_BOOT_LINK_OFFSET ?= 0x00800000
 CONFIG_ZERO_PAGE_OFFSET ?= 0x00001000
+CONFIG_ENTRY_OFFSET     ?= 0x00001000
 
 export CONFIG_PAGE_OFFSET CONFIG_MEMORY_START CONFIG_BOOT_LINK_OFFSET \
-       CONFIG_ZERO_PAGE_OFFSET
+       CONFIG_ZERO_PAGE_OFFSET CONFIG_ENTRY_OFFSET
 
 targets := zImage vmlinux.srec uImage uImage.srec
 subdir- := compressed
@@ -40,7 +41,7 @@ KERNEL_LOAD	:= $(shell /bin/bash -c 'printf "0x%08x" \
 KERNEL_ENTRY    := $(shell /bin/bash -c 'printf "0x%08x" \
                      $$[$(CONFIG_PAGE_OFFSET)  + \
                         $(CONFIG_MEMORY_START) + \
-                        $(CONFIG_ZERO_PAGE_OFFSET)+0x1000]')
+                        $(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]')
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
diff --git a/arch/sh/boot/compressed/Makefile_32 b/arch/sh/boot/compressed/Makefile_32
index c0d25fb1aa60..47685f618ae7 100644
--- a/arch/sh/boot/compressed/Makefile_32
+++ b/arch/sh/boot/compressed/Makefile_32
@@ -35,8 +35,7 @@ $(obj)/vmlinux.bin: vmlinux FORCE
 $(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
         $(call if_changed,gzip)
 
-LDFLAGS_piggy.o := -r --format binary --oformat elf32-sh-linux -T
 OBJCOPYFLAGS += -R .empty_zero_page
 
-$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.gz FORCE
-        $(call if_changed,ld)
+$(obj)/piggy.o: $(obj)/piggy.S $(obj)/vmlinux.bin.gz FORCE
+        $(call if_changed,as_o_S)
diff --git a/arch/sh/boot/compressed/Makefile_64 b/arch/sh/boot/compressed/Makefile_64
index 912f3e205a0d..658d4f915556 100644
--- a/arch/sh/boot/compressed/Makefile_64
+++ b/arch/sh/boot/compressed/Makefile_64
@@ -37,8 +37,7 @@ $(obj)/vmlinux.bin: vmlinux FORCE
 $(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
         $(call if_changed,gzip)
 
-LDFLAGS_piggy.o := -r --format binary --oformat elf32-sh64-linux -T
 OBJCOPYFLAGS += -R .empty_zero_page
 
-$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.gz FORCE
-        $(call if_changed,ld)
+$(obj)/piggy.o: $(obj)/piggy.S $(obj)/vmlinux.bin.gz FORCE
+        $(call if_changed,as_o_S)
diff --git a/arch/sh/boot/compressed/head_64.S b/arch/sh/boot/compressed/head_64.S
index f72c1989f5f2..622eac3cf556 100644
--- a/arch/sh/boot/compressed/head_64.S
+++ b/arch/sh/boot/compressed/head_64.S
@@ -14,8 +14,8 @@
  *   Copyright (C) 2002 Stuart Menefy (stuart.menefy@st.com)
  */
 #include <asm/cache.h>
-#include <asm/cpu/mmu_context.h>
-#include <asm/cpu/registers.h>
+#include <cpu/mmu_context.h>
+#include <cpu/registers.h>
 
 /*
  * Fixed TLB entries to identity map the beginning of RAM
diff --git a/arch/sh/boot/compressed/piggy.S b/arch/sh/boot/compressed/piggy.S
new file mode 100644
index 000000000000..566071926b13
--- /dev/null
+++ b/arch/sh/boot/compressed/piggy.S
@@ -0,0 +1,8 @@
+        .global input_len, input_data
+        .data
+input_len:
+        .long   input_data_end - input_data
+input_data:
+        .incbin "arch/sh/boot/compressed/vmlinux.bin.gz"
+input_data_end:
+        .end
diff --git a/arch/sh/boot/compressed/vmlinux.scr b/arch/sh/boot/compressed/vmlinux.scr
deleted file mode 100644
index 1ed9d791f863..000000000000
--- a/arch/sh/boot/compressed/vmlinux.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-SECTIONS
-{
-  .data : { 
-        input_len = .;
-        LONG(input_data_end - input_data) input_data = .; 
-        *(.data) 
-        input_data_end = .; 
-        }
-}
diff --git a/arch/sh/configs/ap325rxa_defconfig b/arch/sh/configs/ap325rxa_defconfig
new file mode 100644
index 000000000000..29926a9b9ce2
--- /dev/null
+++ b/arch/sh/configs/ap325rxa_defconfig
@@ -0,0 +1,964 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:18:59 2008
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+CONFIG_CPU_SH4A=y
+CONFIG_CPU_SHX2=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+CONFIG_CPU_SUBTYPE_SH7723=y
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x08000000
+CONFIG_29BIT=y
+# CONFIG_X2TLB is not set
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+# CONFIG_SH_STORE_QUEUES is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+CONFIG_SH_AP325RXA=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
+CONFIG_SH_PCLK_FREQ=33333333
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+# CONFIG_HEARTBEAT is not set
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_GUSA=y
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=tty1 console=ttySC5,38400 root=/dev/nfs ip=dhcp"
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xffffffff
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_STNIC is not set
+# CONFIG_SMC91X is not set
+CONFIG_SMC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_CODEPAGE_932=y
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_SH_KGDB is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/dreamcast_defconfig b/arch/sh/configs/dreamcast_defconfig
index 57728788b753..3dc1cbd8a981 100644
--- a/arch/sh/configs/dreamcast_defconfig
+++ b/arch/sh/configs/dreamcast_defconfig
@@ -1,14 +1,17 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23-rc7
-# Fri Sep 21 15:46:27 2007
+# Linux kernel version: 2.6.27-rc1
+# Mon Aug  4 16:49:13 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_TIME=y
@@ -37,12 +40,15 @@ CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -55,21 +61,39 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -80,6 +104,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -93,13 +118,17 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
 CONFIG_CPU_SH4=y
 # CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -108,6 +137,7 @@ CONFIG_CPU_SH4=y
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
 # CONFIG_CPU_SUBTYPE_SH7712 is not set
 # CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 CONFIG_CPU_SUBTYPE_SH7091=y
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -116,14 +146,17 @@ CONFIG_CPU_SUBTYPE_SH7091=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 # CONFIG_CPU_SUBTYPE_SH7785 is not set
 # CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
@@ -133,6 +166,7 @@ CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x0c000000
 CONFIG_MEMORY_SIZE=0x01000000
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
@@ -142,12 +176,15 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_HUGETLB_PAGE_SIZE_64K=y
 # CONFIG_HUGETLB_PAGE_SIZE_256K is not set
 # CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
 # CONFIG_HUGETLB_PAGE_SIZE_4MB is not set
 # CONFIG_HUGETLB_PAGE_SIZE_64MB is not set
+# CONFIG_HUGETLB_PAGE_SIZE_512MB is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -155,6 +192,8 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -194,6 +233,7 @@ CONFIG_SH_PCLK_FREQ=49876504
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -204,7 +244,10 @@ CONFIG_CPU_FREQ_TABLE=y
 CONFIG_CPU_FREQ_STAT=y
 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
@@ -239,12 +282,16 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
 # CONFIG_CRASH_DUMP is not set
+CONFIG_SECCOMP=y
 # CONFIG_PREEMPT_NONE is not set
 # CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
-CONFIG_PREEMPT_BKL=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
 
 #
 # Boot options
@@ -263,10 +310,7 @@ CONFIG_PCI=y
 CONFIG_SH_PCIDMA_NONCOHERENT=y
 CONFIG_PCI_AUTO=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+CONFIG_PCI_LEGACY=y
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 
@@ -275,10 +319,6 @@ CONFIG_PCI_AUTO=y
 #
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -291,6 +331,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -309,6 +350,7 @@ CONFIG_IP_FIB_HASH=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
@@ -316,8 +358,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -334,10 +374,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -345,6 +381,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
@@ -366,6 +403,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_STANDALONE is not set
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
@@ -374,6 +412,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_MTD is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
+CONFIG_GDROM=y
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
@@ -384,11 +423,15 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_PHANTOM is not set
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -400,44 +443,49 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
+# CONFIG_FUSION is not set
 
 #
-# Fusion MPT device support
+# IEEE 1394 (FireWire) support
 #
-# CONFIG_FUSION is not set
 
 #
-# IEEE 1394 (FireWire) support
+# Enable only one of the two stacks, unless you know what you are doing
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
+# CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
@@ -449,6 +497,7 @@ CONFIG_8139TOO=y
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
 # CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
@@ -464,12 +513,12 @@ CONFIG_8139TOO=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -491,7 +540,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -505,6 +553,8 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_MAPLE=y
+# CONFIG_KEYBOARD_SH_KEYSC is not set
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
@@ -530,10 +580,13 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -553,6 +606,19 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -568,45 +634,40 @@ CONFIG_SH_WDT=y
 #
 # CONFIG_PCIPCWATCHDOG is not set
 # CONFIG_WDTPCI is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
 
 #
-# SPI support
+# Sonics Silicon Backplane
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
-# CONFIG_DAB is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DAB is not set
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=m
 CONFIG_FB=y
@@ -615,11 +676,12 @@ CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -653,7 +715,15 @@ CONFIG_FB_PVR2=y
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SH_MOBILE_LCDC is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -680,49 +750,30 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_SUPERH_MONO is not set
 # CONFIG_LOGO_SUPERH_VGA16 is not set
 CONFIG_LOGO_SUPERH_CLUT224=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -735,14 +786,11 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -771,7 +819,6 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -786,14 +833,14 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
@@ -807,35 +854,25 @@ CONFIG_RAMFS=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-CONFIG_PROFILING=y
-# CONFIG_OPROFILE is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 # CONFIG_EARLY_SCIF_CONSOLE is not set
 # CONFIG_SH_KGDB is not set
@@ -845,14 +882,95 @@ CONFIG_ENABLE_MUST_CHECK=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-# CONFIG_CRYPTO is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/hp6xx_defconfig b/arch/sh/configs/hp6xx_defconfig
index 756d38dc2f71..41e25b3a5b01 100644
--- a/arch/sh/configs/hp6xx_defconfig
+++ b/arch/sh/configs/hp6xx_defconfig
@@ -1,9 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23-rc4
-# Tue Sep 11 19:42:44 2007
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:24:57 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -20,6 +22,7 @@ CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -34,12 +37,15 @@ CONFIG_SWAP=y
 # CONFIG_SYSVIPC is not set
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_USER_NS is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
@@ -52,6 +58,7 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -64,6 +71,19 @@ CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
@@ -73,6 +93,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -86,13 +107,17 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
 CONFIG_CPU_SH3=y
 # CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -101,6 +126,7 @@ CONFIG_CPU_SUBTYPE_SH7709=y
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
 # CONFIG_CPU_SUBTYPE_SH7712 is not set
 # CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -109,14 +135,17 @@ CONFIG_CPU_SUBTYPE_SH7709=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 # CONFIG_CPU_SUBTYPE_SH7785 is not set
 # CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
@@ -126,6 +155,7 @@ CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x0d000000
 CONFIG_MEMORY_SIZE=0x00400000
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
@@ -135,7 +165,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -143,6 +175,8 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -181,6 +215,7 @@ CONFIG_SH_PCLK_FREQ=22110000
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -219,11 +254,14 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
 # CONFIG_CRASH_DUMP is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
 
 #
 # Boot options
@@ -237,10 +275,6 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
 #
 CONFIG_ISA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
@@ -263,11 +297,12 @@ CONFIG_BINFMT_ELF=y
 #
 # Power management options (EXPERIMENTAL)
 #
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM=y
-CONFIG_PM_LEGACY=y
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
 CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
 CONFIG_APM_EMULATION=y
 
 #
@@ -282,9 +317,12 @@ CONFIG_APM_EMULATION=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_STANDALONE is not set
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_MTD is not set
 # CONFIG_PARPORT is not set
@@ -294,8 +332,11 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -332,6 +373,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
 CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
@@ -342,14 +384,17 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
 # CONFIG_SCSI_NCR53C406A is not set
 # CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_PSI240I is not set
 # CONFIG_SCSI_QLOGIC_FAS is not set
 # CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_T128 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
 # CONFIG_PATA_LEGACY is not set
 # CONFIG_PATA_PCMCIA is not set
 # CONFIG_PATA_QDI is not set
@@ -370,11 +415,9 @@ CONFIG_INPUT_POLLDEV=y
 #
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_TSDEV=y
-CONFIG_INPUT_TSDEV_SCREEN_X=240
-CONFIG_INPUT_TSDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
 
 #
 # Input Device Drivers
@@ -387,6 +430,7 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
 CONFIG_KEYBOARD_HP6XX=y
+# CONFIG_KEYBOARD_SH_KEYSC is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
@@ -395,12 +439,15 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 CONFIG_TOUCHSCREEN_HP600=y
+# CONFIG_TOUCHSCREEN_HTCPEN is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -417,9 +464,11 @@ CONFIG_SERIO=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -439,7 +488,6 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=64
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
@@ -454,39 +502,45 @@ CONFIG_HW_RANDOM=y
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
-# CONFIG_DAB is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_HP680=y
+# CONFIG_DAB is not set
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_VGASTATE is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
@@ -495,11 +549,12 @@ CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -511,7 +566,20 @@ CONFIG_FB_DEFERRED_IO=y
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_HIT=y
+CONFIG_FB_SH_MOBILE_LCDC=y
 # CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
+CONFIG_BACKLIGHT_HP680=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -533,15 +601,13 @@ CONFIG_FONT_PEARL_8x8=y
 # CONFIG_FONT_SUN12x22 is not set
 # CONFIG_FONT_10x18 is not set
 # CONFIG_LOGO is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -564,9 +630,10 @@ CONFIG_RTC_INTF_DEV=y
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
@@ -575,23 +642,7 @@ CONFIG_RTC_INTF_DEV=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SH=y
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -606,13 +657,10 @@ CONFIG_EXT2_FS=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -643,7 +691,6 @@ CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLBFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -658,8 +705,11 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 
@@ -668,10 +718,6 @@ CONFIG_RAMFS=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_437 is not set
@@ -714,22 +760,21 @@ CONFIG_NLS_CODEPAGE_850=y
 # CONFIG_NLS_UTF8 is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 # CONFIG_EARLY_SCIF_CONSOLE is not set
 # CONFIG_SH_KGDB is not set
@@ -739,50 +784,95 @@ CONFIG_ENABLE_MUST_CHECK=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_BLKCIPHER=y
 CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_LZO is not set
 # CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig
index 38f934ab50c7..99cc39c5c6ca 100644
--- a/arch/sh/configs/landisk_defconfig
+++ b/arch/sh/configs/landisk_defconfig
@@ -1,44 +1,53 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.19
-# Thu Dec  7 17:13:04 2006
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:35:07 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-# CONFIG_GENERIC_TIME is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_SYS_SUPPORTS_PCI=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
-CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
@@ -50,34 +59,48 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -91,67 +114,26 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
-# CONFIG_SH_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SOLUTION_ENGINE is not set
-# CONFIG_SH_7300_SOLUTION_ENGINE is not set
-# CONFIG_SH_7343_SOLUTION_ENGINE is not set
-# CONFIG_SH_73180_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SYSTEMH is not set
-# CONFIG_SH_HP6XX is not set
-# CONFIG_SH_EC3104 is not set
-# CONFIG_SH_SATURN is not set
-# CONFIG_SH_DREAMCAST is not set
-# CONFIG_SH_BIGSUR is not set
-# CONFIG_SH_MPC1211 is not set
-# CONFIG_SH_SH03 is not set
-# CONFIG_SH_SECUREEDGE5410 is not set
-# CONFIG_SH_HS7751RVOIP is not set
-# CONFIG_SH_7710VOIPGW is not set
-# CONFIG_SH_RTS7751R2D is not set
-# CONFIG_SH_R7780RP is not set
-# CONFIG_SH_EDOSK7705 is not set
-# CONFIG_SH_SH4202_MICRODEV is not set
-CONFIG_SH_LANDISK=y
-# CONFIG_SH_TITAN is not set
-# CONFIG_SH_SHMIN is not set
-# CONFIG_SH_7206_SOLUTION_ENGINE is not set
-# CONFIG_SH_7619_SOLUTION_ENGINE is not set
-# CONFIG_SH_UNKNOWN is not set
-
-#
-# Processor selection
-#
 CONFIG_CPU_SH4=y
-
-#
-# SH-2 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7604 is not set
 # CONFIG_CPU_SUBTYPE_SH7619 is not set
-
-#
-# SH-2A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
-
-#
-# SH-3 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7300 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
 # CONFIG_CPU_SUBTYPE_SH7708 is not set
 # CONFIG_CPU_SUBTYPE_SH7709 is not set
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
-
-#
-# SH-4 Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -160,53 +142,60 @@ CONFIG_CPU_SH4=y
 CONFIG_CPU_SUBTYPE_SH7751R=y
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-
-#
-# ST40 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
-
-#
-# SH-4A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 # CONFIG_CPU_SUBTYPE_SH7785 is not set
-
-#
-# SH4AL-DSP Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH73180 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
 #
+CONFIG_QUICKLIST=y
 CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x0c000000
 CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
 
 #
 # Cache configuration
 #
 # CONFIG_SH_DIRECT_MAPPED is not set
-# CONFIG_SH_WRITETHROUGH is not set
-# CONFIG_SH_OCRAM is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
 
 #
 # Processor features
@@ -214,19 +203,32 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_CPU_LITTLE_ENDIAN=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_SH_FPU=y
-# CONFIG_SH_DSP is not set
 # CONFIG_SH_STORE_QUEUES is not set
 CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_INTC_IRQ=y
 CONFIG_CPU_HAS_SR_RB=y
 CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
 
 #
-# Timer support
+# Board support
+#
+# CONFIG_SH_7751_SYSTEMH is not set
+# CONFIG_SH_SECUREEDGE5410 is not set
+# CONFIG_SH_RTS7751R2D is not set
+CONFIG_SH_LANDISK=y
+# CONFIG_SH_TITAN is not set
+# CONFIG_SH_LBOX_RE2 is not set
+
+#
+# Timer and clock configuration
 #
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
 CONFIG_SH_PCLK_FREQ=33333333
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -241,12 +243,11 @@ CONFIG_SH_PCLK_FREQ=33333333
 #
 # Companion Chips
 #
-# CONFIG_HD6446X_SERIES is not set
-CONFIG_HEARTBEAT=y
 
 #
 # Additional SuperH Device Drivers
 #
+CONFIG_HEARTBEAT=y
 # CONFIG_PUSH_SWITCH is not set
 
 #
@@ -254,13 +255,17 @@ CONFIG_HEARTBEAT=y
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_KEXEC=y
-# CONFIG_SMP is not set
+# CONFIG_CRASH_DUMP is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
 
 #
 # Boot options
@@ -273,16 +278,12 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
 #
 # Bus options
 #
-CONFIG_ISA=y
 CONFIG_PCI=y
 CONFIG_SH_PCIDMA_NONCOHERENT=y
 CONFIG_PCI_AUTO=y
 CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
-# CONFIG_PCI_MULTITHREAD_PROBE is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
@@ -301,29 +302,16 @@ CONFIG_YENTA_ENE_TUNE=y
 CONFIG_YENTA_TOSHIBA=y
 # CONFIG_PD6729 is not set
 # CONFIG_I82092 is not set
-# CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
-CONFIG_PCMCIA_PROBE=y
 CONFIG_PCCARD_NONSTATIC=y
-
-#
-# PCI Hotplug Support
-#
 # CONFIG_HOTPLUG_PCI is not set
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_FLAT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
-# Power management options (EXPERIMENTAL)
-#
-# CONFIG_PM is not set
-
-#
 # Networking
 #
 CONFIG_NET=y
@@ -331,13 +319,14 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -364,49 +353,36 @@ CONFIG_IP_PNP=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-
-#
-# IP: Virtual Server Configuration
-#
 # CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
 
 #
 # Core Netfilter Configuration
 #
-# CONFIG_NETFILTER_NETLINK is not set
-# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
 # CONFIG_NETFILTER_XTABLES is not set
 
 #
 # IP: Netfilter Configuration
 #
 CONFIG_IP_NF_QUEUE=m
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -421,10 +397,6 @@ CONFIG_ATALK=m
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -432,9 +404,20 @@ CONFIG_ATALK=m
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -443,35 +426,17 @@ CONFIG_ATALK=m
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 # CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNP is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
@@ -484,63 +449,66 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_IDE_MAX_HWIFS=4
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 # CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_DELKIN is not set
 CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
 CONFIG_BLK_DEV_IDESCSI=y
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
 CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_SHARE_IRQ=y
+CONFIG_IDEPCI_PCIBUS_ORDER=y
 CONFIG_BLK_DEV_OFFBOARD=y
 CONFIG_BLK_DEV_GENERIC=y
 # CONFIG_BLK_DEV_OPTI621 is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-CONFIG_IDEDMA_PCI_AUTO=y
-CONFIG_IDEDMA_ONLYDISK=y
 CONFIG_BLK_DEV_AEC62XX=y
 # CONFIG_BLK_DEV_ALI15X3 is not set
 # CONFIG_BLK_DEV_AMD74XX is not set
 # CONFIG_BLK_DEV_CMD64X is not set
 # CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
 # CONFIG_BLK_DEV_CS5520 is not set
 # CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_JMICRON is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8213 is not set
 # CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
@@ -550,18 +518,15 @@ CONFIG_BLK_DEV_AEC62XX=y
 # CONFIG_BLK_DEV_SLC90E66 is not set
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
 CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-CONFIG_IDEDMA_AUTO=y
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
@@ -583,6 +548,7 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -590,77 +556,43 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 # CONFIG_SCSI_3W_9XXX is not set
 # CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_AIC79XX is not set
 # CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_IN2000 is not set
 # CONFIG_SCSI_ARCMSR is not set
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
 # CONFIG_MEGARAID_SAS is not set
 # CONFIG_SCSI_HPTIOP is not set
 # CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_DTC3280 is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_GENERIC_NCR5380 is not set
-# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_PSI240I is not set
-# CONFIG_SCSI_QLOGIC_FAS is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
 # CONFIG_SCSI_QLA_FC is not set
 # CONFIG_SCSI_QLA_ISCSI is not set
 # CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_T128 is not set
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
 # CONFIG_ATA is not set
-
-#
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -671,76 +603,49 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 # CONFIG_BLK_DEV_DM is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
-# I2O device support
+# Enable only one of the two stacks, unless you know what you are doing
 #
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 CONFIG_TUN=m
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NET_VENDOR_SMC is not set
 # CONFIG_SMC91X is not set
-# CONFIG_NET_VENDOR_RACAL is not set
-
-#
-# Tulip family network device support
-#
+# CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
-# CONFIG_AT1700 is not set
-# CONFIG_DEPCA is not set
 # CONFIG_HP100 is not set
-# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_AC3200 is not set
-# CONFIG_APRICOT is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_CS89x0 is not set
-# CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
@@ -748,18 +653,20 @@ CONFIG_NET_PCI=y
 # CONFIG_NE2K_PCI is not set
 CONFIG_8139CP=y
 # CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
-
-#
-# Ethernet (1000 Mbit)
-#
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
@@ -767,58 +674,53 @@ CONFIG_8139CP=y
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
-
-#
-# Ethernet (10000 Mbit)
-#
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
 # CONFIG_S2IO is not set
 # CONFIG_MYRI10GE is not set
 # CONFIG_NETXEN_NIC is not set
-
-#
-# Token Ring devices
-#
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Wireless LAN
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
-# PCMCIA network device support
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -826,6 +728,7 @@ CONFIG_8139CP=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -835,7 +738,6 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -845,6 +747,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -858,10 +761,13 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -880,22 +786,10 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 
 #
 # PCMCIA character devices
@@ -903,65 +797,77 @@ CONFIG_HW_RANDOM=y
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
+CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_I5K_AMB is not set
 # CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
-CONFIG_VIDEO_DEV=m
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-CONFIG_VIDEO_V4L2=y
 
 #
-# Video Capture Adapters
+# Multimedia core support
 #
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
 
 #
-# Video Capture Adapters
+# Multimedia drivers
 #
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
 CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
 # CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_PMS is not set
 # CONFIG_VIDEO_CPIA is not set
 # CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_STRADIS is not set
-
-#
-# V4L USB devices
-#
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VIDEO_CLASS is not set
+# CONFIG_USB_GSPCA is not set
 CONFIG_VIDEO_USBVIDEO=m
 CONFIG_USB_VICAM=m
 CONFIG_USB_IBMCAM=m
@@ -975,106 +881,100 @@ CONFIG_USB_STV680=m
 # CONFIG_USB_ZC0301 is not set
 CONFIG_USB_PWC=m
 # CONFIG_USB_PWC_DEBUG is not set
-
-#
-# Radio Adapters
-#
-# CONFIG_RADIO_CADET is not set
-# CONFIG_RADIO_RTRACK is not set
-# CONFIG_RADIO_RTRACK2 is not set
-# CONFIG_RADIO_AZTECH is not set
-# CONFIG_RADIO_GEMTEK is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+CONFIG_RADIO_ADAPTERS=y
 # CONFIG_RADIO_GEMTEK_PCI is not set
 # CONFIG_RADIO_MAXIRADIO is not set
 # CONFIG_RADIO_MAESTRO is not set
-# CONFIG_RADIO_SF16FMI is not set
-# CONFIG_RADIO_SF16FMR2 is not set
-# CONFIG_RADIO_TERRATEC is not set
-# CONFIG_RADIO_TRUST is not set
-# CONFIG_RADIO_TYPHOON is not set
-# CONFIG_RADIO_ZOLTRIX is not set
 CONFIG_USB_DSBR=m
+# CONFIG_USB_SI470X is not set
+# CONFIG_DAB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
-CONFIG_USB_DABUSB=m
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-CONFIG_FIRMWARE_EDID=y
-# CONFIG_FB is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
-# CONFIG_MDA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FONT_8x16=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
 # CONFIG_SND is not set
+CONFIG_SOUND_PRIME=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# Open Sound System
+# USB Input Devices
 #
-CONFIG_SOUND_PRIME=m
-# CONFIG_OSS_OBSOLETE_DRIVER is not set
-# CONFIG_SOUND_BT878 is not set
-# CONFIG_SOUND_ES1371 is not set
-# CONFIG_SOUND_ICH is not set
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
-# CONFIG_SOUND_VIA82CXXX is not set
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
 
 #
-# USB support
+# USB HID Boot Protocol drivers
 #
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_MULTITHREAD_PROBE is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 CONFIG_USB_PRINTER=m
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1094,66 +994,28 @@ CONFIG_USB_STORAGE_SDDR09=y
 CONFIG_USB_STORAGE_SDDR55=y
 CONFIG_USB_STORAGE_JUMPSHOT=y
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-CONFIG_USB_HIDINPUT=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
 # CONFIG_USB_SERIAL_GENERIC is not set
 # CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_AIRPRIME is not set
 # CONFIG_USB_SERIAL_ARK3116 is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
 # CONFIG_USB_SERIAL_CP2101 is not set
@@ -1168,6 +1030,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m
 # CONFIG_USB_SERIAL_EDGEPORT_TI is not set
 # CONFIG_USB_SERIAL_GARMIN is not set
 # CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KLSI is not set
@@ -1175,8 +1038,11 @@ CONFIG_USB_SERIAL_FTDI_SIO=m
 # CONFIG_USB_SERIAL_MCT_U232 is not set
 # CONFIG_USB_SERIAL_MOS7720 is not set
 # CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
 # CONFIG_USB_SERIAL_NAVMAN is not set
 CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
 # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
@@ -1197,6 +1063,7 @@ CONFIG_USB_EMI26=m
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -1208,61 +1075,18 @@ CONFIG_USB_SISUSBVGA=m
 CONFIG_USB_SISUSBVGA_CON=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -1276,7 +1100,6 @@ CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 CONFIG_REISERFS_FS=y
 # CONFIG_REISERFS_CHECK is not set
@@ -1285,14 +1108,11 @@ CONFIG_REISERFS_FS=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-CONFIG_ROMFS_FS=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1328,7 +1148,6 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLBFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1343,26 +1162,24 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
 # CONFIG_SYSV_FS is not set
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
 # CONFIG_UFS_DEBUG is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
@@ -1376,17 +1193,12 @@ CONFIG_SMB_FS=m
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -1427,46 +1239,128 @@ CONFIG_NLS_CODEPAGE_932=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 CONFIG_SH_STANDARD_BIOS=y
 # CONFIG_EARLY_SCIF_CONSOLE is not set
 # CONFIG_EARLY_PRINTK is not set
-# CONFIG_KGDB is not set
+# CONFIG_SH_KGDB is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig
index b68b6cdbb78f..aecdfd33c695 100644
--- a/arch/sh/configs/lboxre2_defconfig
+++ b/arch/sh/configs/lboxre2_defconfig
@@ -1,9 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21-rc4
-# Sat Mar 24 22:04:27 2007
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:39:41 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -11,37 +13,40 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-# CONFIG_GENERIC_TIME is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_SYS_SUPPORTS_PCI=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -54,34 +59,48 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -95,66 +114,26 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
-# CONFIG_SH_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SOLUTION_ENGINE is not set
-# CONFIG_SH_7300_SOLUTION_ENGINE is not set
-# CONFIG_SH_7343_SOLUTION_ENGINE is not set
-# CONFIG_SH_73180_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SYSTEMH is not set
-# CONFIG_SH_HP6XX is not set
-# CONFIG_SH_SATURN is not set
-# CONFIG_SH_DREAMCAST is not set
-# CONFIG_SH_MPC1211 is not set
-# CONFIG_SH_SH03 is not set
-# CONFIG_SH_SECUREEDGE5410 is not set
-# CONFIG_SH_HS7751RVOIP is not set
-# CONFIG_SH_7710VOIPGW is not set
-# CONFIG_SH_RTS7751R2D is not set
-# CONFIG_SH_HIGHLANDER is not set
-# CONFIG_SH_EDOSK7705 is not set
-# CONFIG_SH_SH4202_MICRODEV is not set
-# CONFIG_SH_LANDISK is not set
-# CONFIG_SH_TITAN is not set
-# CONFIG_SH_SHMIN is not set
-# CONFIG_SH_7206_SOLUTION_ENGINE is not set
-# CONFIG_SH_7619_SOLUTION_ENGINE is not set
-CONFIG_SH_LBOX_RE2=y
-# CONFIG_SH_UNKNOWN is not set
-
-#
-# Processor selection
-#
 CONFIG_CPU_SH4=y
-
-#
-# SH-2 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7604 is not set
 # CONFIG_CPU_SUBTYPE_SH7619 is not set
-
-#
-# SH-2A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
-
-#
-# SH-3 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7300 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
 # CONFIG_CPU_SUBTYPE_SH7708 is not set
 # CONFIG_CPU_SUBTYPE_SH7709 is not set
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
-
-#
-# SH-4 Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -163,55 +142,60 @@ CONFIG_CPU_SH4=y
 CONFIG_CPU_SUBTYPE_SH7751R=y
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-
-#
-# ST40 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
-
-#
-# SH-4A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 # CONFIG_CPU_SUBTYPE_SH7785 is not set
-
-#
-# SH4AL-DSP Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH73180 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
 #
+CONFIG_QUICKLIST=y
 CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x0c000000
 CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
 
 #
 # Cache configuration
 #
 # CONFIG_SH_DIRECT_MAPPED is not set
-# CONFIG_SH_WRITETHROUGH is not set
-# CONFIG_SH_OCRAM is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
 
 #
 # Processor features
@@ -219,12 +203,21 @@ CONFIG_ZONE_DMA_FLAG=0
 CONFIG_CPU_LITTLE_ENDIAN=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_SH_FPU=y
-# CONFIG_SH_DSP is not set
 # CONFIG_SH_STORE_QUEUES is not set
 CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_INTC_IRQ=y
 CONFIG_CPU_HAS_SR_RB=y
 CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+# CONFIG_SH_7751_SYSTEMH is not set
+# CONFIG_SH_SECUREEDGE5410 is not set
+# CONFIG_SH_RTS7751R2D is not set
+# CONFIG_SH_LANDISK is not set
+# CONFIG_SH_TITAN is not set
+CONFIG_SH_LBOX_RE2=y
 
 #
 # Timer and clock configuration
@@ -232,6 +225,10 @@ CONFIG_CPU_HAS_PTEA=y
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
 CONFIG_SH_PCLK_FREQ=40000000
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -246,7 +243,6 @@ CONFIG_SH_PCLK_FREQ=40000000
 #
 # Companion Chips
 #
-# CONFIG_HD6446X_SERIES is not set
 
 #
 # Additional SuperH Device Drivers
@@ -262,11 +258,14 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_KEXEC=y
-# CONFIG_SMP is not set
+# CONFIG_CRASH_DUMP is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
 
 #
 # Boot options
@@ -280,15 +279,12 @@ CONFIG_CMDLINE="console=ttySC1,115200 root=/dev/sda1"
 #
 # Bus options
 #
-CONFIG_ISA=y
 CONFIG_PCI=y
 CONFIG_SH_PCIDMA_NONCOHERENT=y
 CONFIG_PCI_AUTO=y
 CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
 CONFIG_PCCARD=y
 CONFIG_PCMCIA_DEBUG=y
 CONFIG_PCMCIA=y
@@ -306,29 +302,16 @@ CONFIG_YENTA_O2=y
 # CONFIG_YENTA_TOSHIBA is not set
 # CONFIG_PD6729 is not set
 # CONFIG_I82092 is not set
-# CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
-CONFIG_PCMCIA_PROBE=y
 CONFIG_PCCARD_NONSTATIC=y
-
-#
-# PCI Hotplug Support
-#
 # CONFIG_HOTPLUG_PCI is not set
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_FLAT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
-# Power management options (EXPERIMENTAL)
-#
-# CONFIG_PM is not set
-
-#
 # Networking
 #
 CONFIG_NET=y
@@ -336,7 +319,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -344,6 +326,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -370,29 +353,26 @@ CONFIG_IP_PNP=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-
-#
-# IP: Virtual Server Configuration
-#
 # CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
 
 #
 # Core Netfilter Configuration
 #
-# CONFIG_NETFILTER_NETLINK is not set
-# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
 # CONFIG_NETFILTER_XTABLES is not set
 
 #
@@ -401,20 +381,8 @@ CONFIG_NETFILTER=y
 # CONFIG_IP_NF_QUEUE is not set
 # CONFIG_IP_NF_IPTABLES is not set
 # CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -427,10 +395,6 @@ CONFIG_NETFILTER=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -438,9 +402,20 @@ CONFIG_NETFILTER=y
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -449,36 +424,17 @@ CONFIG_NETFILTER=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 # CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNP is not set
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
@@ -490,19 +446,18 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -510,6 +465,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
@@ -531,6 +487,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -538,71 +495,49 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 # CONFIG_SCSI_3W_9XXX is not set
 # CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_AIC79XX is not set
 # CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_IN2000 is not set
 # CONFIG_SCSI_ARCMSR is not set
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
 # CONFIG_MEGARAID_SAS is not set
 # CONFIG_SCSI_HPTIOP is not set
 # CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_DTC3280 is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_GENERIC_NCR5380 is not set
-# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_PSI240I is not set
-# CONFIG_SCSI_QLOGIC_FAS is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
 # CONFIG_SCSI_QLA_FC is not set
 # CONFIG_SCSI_QLA_ISCSI is not set
 # CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_T128 is not set
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
@@ -612,7 +547,6 @@ CONFIG_ATA=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -622,6 +556,7 @@ CONFIG_ATA=y
 # CONFIG_PATA_AMD is not set
 # CONFIG_PATA_ARTOP is not set
 # CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
 # CONFIG_PATA_CMD64X is not set
 # CONFIG_PATA_CS5520 is not set
 # CONFIG_PATA_CS5530 is not set
@@ -635,18 +570,18 @@ CONFIG_ATA=y
 # CONFIG_PATA_IT821X is not set
 # CONFIG_PATA_IT8213 is not set
 # CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_LEGACY is not set
 # CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_MARVELL is not set
 # CONFIG_PATA_MPIIX is not set
 # CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
 # CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
 # CONFIG_PATA_OPTI is not set
 # CONFIG_PATA_OPTIDMA is not set
 # CONFIG_PATA_PCMCIA is not set
 # CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_QDI is not set
 # CONFIG_PATA_RADISYS is not set
 # CONFIG_PATA_RZ1000 is not set
 # CONFIG_PATA_SC1200 is not set
@@ -656,88 +591,52 @@ CONFIG_ATA=y
 # CONFIG_PATA_SIS is not set
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
-# CONFIG_PATA_WINBOND_VLB is not set
 CONFIG_PATA_PLATFORM=y
-
-#
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
-# I2O device support
+# Enable only one of the two stacks, unless you know what you are doing
 #
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NET_VENDOR_SMC is not set
 # CONFIG_SMC91X is not set
-# CONFIG_NET_VENDOR_RACAL is not set
-
-#
-# Tulip family network device support
-#
+# CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
-# CONFIG_AT1700 is not set
-# CONFIG_DEPCA is not set
 # CONFIG_HP100 is not set
-# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_AC3200 is not set
-# CONFIG_APRICOT is not set
 # CONFIG_B44 is not set
 # CONFIG_FORCEDETH is not set
-# CONFIG_CS89x0 is not set
-# CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 # CONFIG_E100 is not set
 # CONFIG_FEALNX is not set
@@ -749,19 +648,20 @@ CONFIG_8139TOO_PIO=y
 CONFIG_8139TOO_TUNE_TWISTER=y
 # CONFIG_8139TOO_8129 is not set
 # CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
+CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
@@ -769,36 +669,33 @@ CONFIG_8139TOO_TUNE_TWISTER=y
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
+# CONFIG_ATL1E is not set
+CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
 # CONFIG_S2IO is not set
 # CONFIG_MYRI10GE is not set
 # CONFIG_NETXEN_NIC is not set
-
-#
-# Token Ring devices
-#
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
 # CONFIG_TR is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 CONFIG_NET_PCMCIA=y
 # CONFIG_PCMCIA_3C589 is not set
 # CONFIG_PCMCIA_3C574 is not set
@@ -808,29 +705,16 @@ CONFIG_PCMCIA_PCNET=y
 # CONFIG_PCMCIA_SMC91C92 is not set
 # CONFIG_PCMCIA_XIRC2PS is not set
 # CONFIG_PCMCIA_AXNET is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -838,6 +722,7 @@ CONFIG_PCMCIA_PCNET=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -847,7 +732,6 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -857,6 +741,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -870,10 +755,13 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -892,22 +780,10 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 
 #
 # PCMCIA character devices
@@ -915,125 +791,104 @@ CONFIG_HW_RANDOM=y
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
+CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_I5K_AMB is not set
 # CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Console display driver support
+# Display device support
 #
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# Sound
+# Console display driver support
 #
+CONFIG_DUMMY_CONSOLE=y
 # CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
+CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
-
-#
-# USB support
-#
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1047,37 +902,29 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-
-#
-# RTC drivers
-#
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_SH is not set
 # CONFIG_RTC_DRV_TEST is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
 
 #
-# DMA Devices
+# SPI RTC drivers
 #
 
 #
-# Auxiliary Display support
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Virtualization
+# on-CPU RTC drivers
 #
+# CONFIG_RTC_DRV_SH is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -1091,20 +938,16 @@ CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-CONFIG_ROMFS_FS=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1136,7 +979,6 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLBFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1151,14 +993,14 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
@@ -1166,17 +1008,12 @@ CONFIG_RAMFS=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -1217,30 +1054,24 @@ CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 CONFIG_SH_STANDARD_BIOS=y
 # CONFIG_EARLY_SCIF_CONSOLE is not set
 # CONFIG_EARLY_PRINTK is not set
@@ -1251,20 +1082,100 @@ CONFIG_SH_STANDARD_BIOS=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/magicpanelr2_defconfig b/arch/sh/configs/magicpanelr2_defconfig
index f8398a5f10ee..a3a80f3d27c0 100644
--- a/arch/sh/configs/magicpanelr2_defconfig
+++ b/arch/sh/configs/magicpanelr2_defconfig
@@ -1,9 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23-rc2
-# Fri Aug 17 12:15:16 2007
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:41:08 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -18,6 +20,7 @@ CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -35,12 +38,16 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
 CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -48,6 +55,7 @@ CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -55,6 +63,7 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -67,10 +76,24 @@ CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 CONFIG_MODVERSIONS=y
@@ -81,6 +104,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -94,13 +118,17 @@ CONFIG_IOSCHED_NOOP=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
 CONFIG_CPU_SH3=y
 # CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -109,6 +137,7 @@ CONFIG_CPU_SH3=y
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
 # CONFIG_CPU_SUBTYPE_SH7712 is not set
 CONFIG_CPU_SUBTYPE_SH7720=y
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -117,14 +146,17 @@ CONFIG_CPU_SUBTYPE_SH7720=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 # CONFIG_CPU_SUBTYPE_SH7785 is not set
 # CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
@@ -134,6 +166,7 @@ CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x0C000000
 CONFIG_MEMORY_SIZE=0x03F00000
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
@@ -143,7 +176,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -151,6 +186,8 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -173,7 +210,6 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SH_DSP=y
 CONFIG_SH_ADC=y
 CONFIG_CPU_HAS_INTEVT=y
-CONFIG_CPU_HAS_INTC_IRQ=y
 CONFIG_CPU_HAS_SR_RB=y
 CONFIG_CPU_HAS_DSP=y
 
@@ -196,6 +232,7 @@ CONFIG_SH_PCLK_FREQ=24000000
 # CONFIG_TICK_ONESHOT is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -228,11 +265,14 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
 # CONFIG_CRASH_DUMP is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
 
 #
 # Boot options
@@ -245,10 +285,6 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
 # Bus options
 #
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
 # CONFIG_PCCARD is not set
 
 #
@@ -289,6 +325,7 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
@@ -296,8 +333,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -314,10 +349,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -325,6 +356,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
@@ -346,9 +378,12 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -362,6 +397,7 @@ CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
 # CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
 # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -374,6 +410,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -408,7 +445,6 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_PHYSMAP_START=0x0000000
 CONFIG_MTD_PHYSMAP_LEN=0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=0
-# CONFIG_MTD_SOLUTIONENGINE is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -440,11 +476,14 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -457,18 +496,24 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 # CONFIG_SMC91X is not set
 CONFIG_SMC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -477,10 +522,10 @@ CONFIG_SMC911X=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -502,7 +547,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -516,6 +560,7 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
@@ -539,9 +584,11 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -569,60 +616,72 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 CONFIG_DAB=y
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
 
 #
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
@@ -644,9 +703,10 @@ CONFIG_RTC_INTF_DEV=y
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
@@ -655,23 +715,7 @@ CONFIG_RTC_INTF_DEV=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SH=y
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -684,18 +728,14 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
 # CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -724,7 +764,6 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLBFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -744,30 +783,29 @@ CONFIG_JFFS2_FS_DEBUG=0
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-CONFIG_SUNRPC_BIND34=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -781,10 +819,6 @@ CONFIG_SUNRPC_BIND34=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="cp437"
 CONFIG_NLS_CODEPAGE_437=y
@@ -825,23 +859,16 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
@@ -852,6 +879,7 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
@@ -866,11 +894,16 @@ CONFIG_DEBUG_KOBJECT=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
-# CONFIG_FORCED_INLINING is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 CONFIG_EARLY_SCIF_CONSOLE=y
 CONFIG_EARLY_SCIF_CONSOLE_PORT=0xa4430000
@@ -879,6 +912,7 @@ CONFIG_EARLY_PRINTK=y
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_4KSTACKS is not set
+# CONFIG_IRQSTACKS is not set
 CONFIG_SH_KGDB=y
 
 #
@@ -904,14 +938,17 @@ CONFIG_KGDB_DEFBITS_8=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/microdev_defconfig b/arch/sh/configs/microdev_defconfig
index e89d951c3c16..e4b900e72dcd 100644
--- a/arch/sh/configs/microdev_defconfig
+++ b/arch/sh/configs/microdev_defconfig
@@ -1,28 +1,35 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.18
-# Tue Oct  3 11:27:01 2006
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:47:16 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
@@ -31,10 +38,16 @@ CONFIG_SWAP=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
@@ -47,29 +60,42 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 # CONFIG_MODULES is not set
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -83,59 +109,26 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
-# CONFIG_SH_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SOLUTION_ENGINE is not set
-# CONFIG_SH_7300_SOLUTION_ENGINE is not set
-# CONFIG_SH_7343_SOLUTION_ENGINE is not set
-# CONFIG_SH_73180_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SYSTEMH is not set
-# CONFIG_SH_HP6XX is not set
-# CONFIG_SH_EC3104 is not set
-# CONFIG_SH_SATURN is not set
-# CONFIG_SH_DREAMCAST is not set
-# CONFIG_SH_BIGSUR is not set
-# CONFIG_SH_MPC1211 is not set
-# CONFIG_SH_SH03 is not set
-# CONFIG_SH_SECUREEDGE5410 is not set
-# CONFIG_SH_HS7751RVOIP is not set
-# CONFIG_SH_7710VOIPGW is not set
-# CONFIG_SH_RTS7751R2D is not set
-# CONFIG_SH_R7780RP is not set
-# CONFIG_SH_EDOSK7705 is not set
-CONFIG_SH_SH4202_MICRODEV=y
-# CONFIG_SH_LANDISK is not set
-# CONFIG_SH_TITAN is not set
-# CONFIG_SH_SHMIN is not set
-# CONFIG_SH_UNKNOWN is not set
-
-#
-# Processor selection
-#
 CONFIG_CPU_SH4=y
-
-#
-# SH-2 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7604 is not set
-
-#
-# SH-3 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7300 is not set
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
 # CONFIG_CPU_SUBTYPE_SH7708 is not set
 # CONFIG_CPU_SUBTYPE_SH7709 is not set
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
-
-#
-# SH-4 Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -144,67 +137,94 @@ CONFIG_CPU_SH4=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 CONFIG_CPU_SUBTYPE_SH4_202=y
-
-#
-# ST40 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
-
-#
-# SH-4A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
-
-#
-# SH4AL-DSP Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH73180 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
 #
+CONFIG_QUICKLIST=y
 CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x08000000
 CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_HUGETLB_PAGE_SIZE_64K=y
+# CONFIG_HUGETLB_PAGE_SIZE_256K is not set
 # CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
+# CONFIG_HUGETLB_PAGE_SIZE_4MB is not set
+# CONFIG_HUGETLB_PAGE_SIZE_64MB is not set
+# CONFIG_HUGETLB_PAGE_SIZE_512MB is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
 
 #
 # Cache configuration
 #
 # CONFIG_SH_DIRECT_MAPPED is not set
-CONFIG_SH_WRITETHROUGH=y
-# CONFIG_SH_OCRAM is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
 
 #
 # Processor features
 #
 CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_SH_FPU=y
-# CONFIG_SH_DSP is not set
 # CONFIG_SH_STORE_QUEUES is not set
 CONFIG_CPU_HAS_INTEVT=y
 CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
 
 #
-# Timer support
+# Board support
+#
+CONFIG_SH_SH4202_MICRODEV=y
+
+#
+# Timer and clock configuration
 #
 CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
 CONFIG_SH_PCLK_FREQ=66000000
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -214,6 +234,7 @@ CONFIG_SH_PCLK_FREQ=66000000
 #
 # DMA support
 #
+CONFIG_SH_DMA_API=y
 CONFIG_SH_DMA=y
 CONFIG_NR_ONCHIP_DMA_CHANNELS=4
 # CONFIG_NR_DMA_CHANNELS_BOOL is not set
@@ -221,22 +242,30 @@ CONFIG_NR_ONCHIP_DMA_CHANNELS=4
 #
 # Companion Chips
 #
-# CONFIG_HD6446X_SERIES is not set
+
+#
+# Additional SuperH Device Drivers
+#
 CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
 
 #
 # Kernel features
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
-# CONFIG_SMP is not set
+# CONFIG_CRASH_DUMP is not set
 # CONFIG_PREEMPT_NONE is not set
 # CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
-CONFIG_PREEMPT_BKL=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
 
 #
 # Boot options
@@ -251,30 +280,16 @@ CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/hda1"
 # Bus options
 #
 CONFIG_SUPERHYWAY=y
-# CONFIG_PCI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
-# PCI Hotplug Support
-#
-
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_FLAT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
-# Power management options (EXPERIMENTAL)
-#
-# CONFIG_PM is not set
-
-#
 # Networking
 #
 CONFIG_NET=y
@@ -282,12 +297,13 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 # CONFIG_PACKET is not set
 # CONFIG_UNIX is not set
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -308,30 +324,19 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_TUNNEL is not set
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -344,10 +349,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -355,9 +356,20 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -366,159 +378,96 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 # CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_IDE_MAX_HWIFS=1
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
 CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -536,6 +485,7 @@ CONFIG_SMC91X=y
 # Character devices
 #
 # CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -554,143 +504,93 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
 # CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
-CONFIG_VIDEO_V4L2=y
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-CONFIG_FIRMWARE_EDID=y
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
+# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -702,20 +602,18 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_POSIX_ACL is not set
 # CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -747,7 +645,6 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -762,21 +659,20 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
@@ -789,17 +685,12 @@ CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_437 is not set
@@ -840,76 +731,127 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_UNWIND_INFO is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 # CONFIG_EARLY_SCIF_CONSOLE is not set
-# CONFIG_KGDB is not set
+# CONFIG_SH_KGDB is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
 
 #
-# Cryptographic options
+# Crypto core or helper
 #
-CONFIG_CRYPTO=y
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_BLKCIPHER=y
 CONFIG_CRYPTO_MANAGER=y
-# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Hardware crypto devices
+# Compression
 #
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig
index 287408b2ace6..c4b3e1d8950d 100644
--- a/arch/sh/configs/migor_defconfig
+++ b/arch/sh/configs/migor_defconfig
@@ -1,10 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc3
-# Thu May 22 14:30:07 2008
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:44:41 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -77,9 +78,14 @@ CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
 CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -90,12 +96,13 @@ CONFIG_MODULES=y
 # CONFIG_MODULE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
+CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -173,7 +180,9 @@ CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_FLATMEM_MANUAL is not set
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -216,6 +225,8 @@ CONFIG_CPU_HAS_DSP=y
 #
 # CONFIG_SH_7722_SOLUTION_ENGINE is not set
 CONFIG_SH_MIGOR=y
+CONFIG_SH_MIGOR_QVGA=y
+# CONFIG_SH_MIGOR_RTA_WVGA is not set
 
 #
 # Timer and clock configuration
@@ -362,6 +373,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
@@ -378,6 +390,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -475,6 +489,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -521,10 +536,10 @@ CONFIG_SCSI_WAIT_SCAN=m
 CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -537,6 +552,7 @@ CONFIG_MII=y
 # CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -602,6 +618,7 @@ CONFIG_KEYBOARD_SH_KEYSC=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -636,21 +653,35 @@ CONFIG_I2C_BOARDINFO=y
 #
 # I2C Hardware Bus support
 #
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
+CONFIG_I2C_SH_MOBILE=y
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
 # CONFIG_I2C_PCA_PLATFORM is not set
-CONFIG_I2C_SH_MOBILE=y
+# CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
@@ -663,6 +694,7 @@ CONFIG_I2C_SH_MOBILE=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -674,6 +706,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 
@@ -710,10 +743,6 @@ CONFIG_SSB_POSSIBLE=y
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
@@ -738,7 +767,7 @@ CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_ATMEL_USBA is not set
 # CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_PXA25X is not set
 CONFIG_USB_GADGET_M66592=y
 CONFIG_USB_M66592=y
 CONFIG_SUPERH_BUILT_IN_M66592=y
@@ -757,6 +786,7 @@ CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_G_SERIAL=y
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
@@ -790,6 +820,7 @@ CONFIG_RTC_DRV_RS5C372=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
@@ -810,6 +841,7 @@ CONFIG_RTC_DRV_RS5C372=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SH=y
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -870,6 +902,7 @@ CONFIG_TMPFS=y
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -899,6 +932,7 @@ CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 CONFIG_EARLY_SCIF_CONSOLE=y
@@ -955,6 +989,10 @@ CONFIG_CRYPTO=y
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
@@ -994,6 +1032,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/r7780mp_defconfig b/arch/sh/configs/r7780mp_defconfig
index 1a072615ffd4..57a300797584 100644
--- a/arch/sh/configs/r7780mp_defconfig
+++ b/arch/sh/configs/r7780mp_defconfig
@@ -1,10 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc4
-# Thu Mar  6 15:39:59 2008
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:51:13 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -84,13 +85,20 @@ CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
 CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SLABINFO=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -101,6 +109,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -115,7 +124,6 @@ CONFIG_IOSCHED_NOOP=y
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
 
 #
 # System type
@@ -126,6 +134,7 @@ CONFIG_CPU_SH4A=y
 # CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
 # CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -143,6 +152,7 @@ CONFIG_CPU_SH4A=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
 # CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 CONFIG_CPU_SUBTYPE_SH7780=y
@@ -173,7 +183,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_HUGETLB_PAGE_SIZE_64K=y
 # CONFIG_HUGETLB_PAGE_SIZE_256K is not set
 # CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
@@ -188,6 +200,7 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -268,7 +281,7 @@ CONFIG_KEXEC=y
 # CONFIG_PREEMPT_NONE is not set
 # CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
-CONFIG_RCU_TRACE=y
+# CONFIG_PREEMPT_RCU is not set
 CONFIG_GUSA=y
 
 #
@@ -348,14 +361,13 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+CONFIG_STP=m
 CONFIG_BRIDGE=m
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
@@ -384,6 +396,7 @@ CONFIG_LLC=m
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
@@ -400,6 +413,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -420,12 +435,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_PHANTOM is not set
 CONFIG_EEPROM_93CX6=y
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -499,9 +516,13 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
@@ -511,7 +532,6 @@ CONFIG_ATA=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 CONFIG_SATA_SIL=y
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -556,17 +576,21 @@ CONFIG_SATA_SIL=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 CONFIG_PATA_PLATFORM=y
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -585,6 +609,7 @@ CONFIG_AX88796_93CX6=y
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
+# CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -593,7 +618,6 @@ CONFIG_AX88796_93CX6=y
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 CONFIG_NET_PCI=y
 CONFIG_PCNET32=m
-# CONFIG_PCNET32_NAPI is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
@@ -616,32 +640,28 @@ CONFIG_8139TOO_8129=y
 # CONFIG_TLAN is not set
 CONFIG_VIA_RHINE=m
 CONFIG_VIA_RHINE_MMIO=y
-# CONFIG_VIA_RHINE_NAPI is not set
 # CONFIG_SC92031 is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 CONFIG_E1000=m
-# CONFIG_E1000_NAPI is not set
 # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
 # CONFIG_E1000E is not set
-# CONFIG_E1000E_ENABLED is not set
 # CONFIG_IP1000 is not set
 # CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 CONFIG_R8169=y
-# CONFIG_R8169_NAPI is not set
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
@@ -654,6 +674,7 @@ CONFIG_NETDEV_10000=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
 # CONFIG_TR is not set
 
 #
@@ -661,6 +682,7 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
@@ -701,6 +723,7 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
@@ -722,6 +745,7 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 # CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 # CONFIG_NOZOMI is not set
 
@@ -750,12 +774,7 @@ CONFIG_HW_RANDOM=y
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
@@ -776,6 +795,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
 CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -787,13 +807,24 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 CONFIG_DAB=y
 
 #
@@ -809,24 +840,9 @@ CONFIG_DAB=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
 # CONFIG_SND is not set
-
-#
-# Open Sound System
-#
 CONFIG_SOUND_PRIME=m
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -836,6 +852,8 @@ CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -844,6 +862,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -879,10 +898,7 @@ CONFIG_RTC_INTF_DEV=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SH=y
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -903,7 +919,6 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
@@ -957,6 +972,7 @@ CONFIG_CONFIGFS_FS=m
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -967,20 +983,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_BIND34 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1043,6 +1056,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
@@ -1050,9 +1064,12 @@ CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -1066,6 +1083,8 @@ CONFIG_SCHED_DEBUG=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_FRAME_POINTER is not set
@@ -1091,51 +1110,84 @@ CONFIG_DEBUG_STACKOVERFLOW=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_BLKCIPHER=y
-# CONFIG_CRYPTO_SEQIV is not set
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
@@ -1144,8 +1196,10 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/r7785rp_defconfig b/arch/sh/configs/r7785rp_defconfig
index 0dc1ce7b9349..1d09d24d4298 100644
--- a/arch/sh/configs/r7785rp_defconfig
+++ b/arch/sh/configs/r7785rp_defconfig
@@ -1,10 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc3
-# Fri Nov 23 14:03:57 2007
+# Linux kernel version: 2.6.26
+# Wed Jul 30 00:59:19 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -21,6 +22,8 @@ CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_IO_TRAPPED=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -39,18 +42,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -64,20 +65,37 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
 CONFIG_ANON_INODES=y
 # CONFIG_EPOLL is not set
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -88,6 +106,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -101,6 +120,7 @@ CONFIG_IOSCHED_NOOP=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
@@ -109,7 +129,10 @@ CONFIG_CPU_SH4=y
 CONFIG_CPU_SH4A=y
 CONFIG_CPU_SHX2=y
 # CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -118,6 +141,7 @@ CONFIG_CPU_SHX2=y
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
 # CONFIG_CPU_SUBTYPE_SH7712 is not set
 # CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -126,12 +150,15 @@ CONFIG_CPU_SHX2=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 CONFIG_CPU_SUBTYPE_SH7785=y
 # CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
 # CONFIG_CPU_SUBTYPE_SH5_101 is not set
 # CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
@@ -157,7 +184,9 @@ CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 # CONFIG_HUGETLB_PAGE_SIZE_64K is not set
 # CONFIG_HUGETLB_PAGE_SIZE_256K is not set
 CONFIG_HUGETLB_PAGE_SIZE_1MB=y
@@ -173,6 +202,7 @@ CONFIG_HAVE_MEMORY_PRESENT=y
 CONFIG_SPARSEMEM_STATIC=y
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 # CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -202,6 +232,7 @@ CONFIG_CPU_HAS_FPU=y
 # Board support
 #
 CONFIG_SH_HIGHLANDER=y
+# CONFIG_SH_SH7785LCR is not set
 # CONFIG_SH_R7780RP is not set
 # CONFIG_SH_R7780MP is not set
 CONFIG_SH_R7785RP=y
@@ -245,12 +276,13 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_KEXEC=y
 # CONFIG_CRASH_DUMP is not set
 # CONFIG_PREEMPT_NONE is not set
 # CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
-CONFIG_PREEMPT_BKL=y
+# CONFIG_PREEMPT_RCU is not set
 CONFIG_GUSA=y
 
 #
@@ -295,6 +327,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -329,14 +362,13 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+CONFIG_STP=m
 CONFIG_BRIDGE=m
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
@@ -355,6 +387,7 @@ CONFIG_LLC=m
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
@@ -364,6 +397,7 @@ CONFIG_LLC=m
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
@@ -380,6 +414,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -397,14 +433,18 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_PHANTOM is not set
 CONFIG_EEPROM_93CX6=y
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -464,6 +504,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
@@ -476,9 +517,13 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
@@ -488,7 +533,6 @@ CONFIG_ATA=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 CONFIG_SATA_SIL=y
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -517,6 +561,7 @@ CONFIG_SATA_SIL=y
 # CONFIG_PATA_MPIIX is not set
 # CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
 # CONFIG_PATA_NS87410 is not set
 # CONFIG_PATA_NS87415 is not set
 # CONFIG_PATA_OPTI is not set
@@ -532,24 +577,27 @@ CONFIG_SATA_SIL=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 CONFIG_PATA_PLATFORM=y
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_IP1000 is not set
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
@@ -576,20 +624,21 @@ CONFIG_NETDEV_1000=y
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
 # CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 CONFIG_R8169=y
-# CONFIG_R8169_NAPI is not set
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
@@ -601,6 +650,8 @@ CONFIG_NETDEV_10000=y
 # CONFIG_NIU is not set
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
 # CONFIG_TR is not set
 
 #
@@ -608,13 +659,13 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -649,6 +700,7 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
@@ -670,7 +722,9 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 # CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -697,12 +751,7 @@ CONFIG_HW_RANDOM=y
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
@@ -722,6 +771,8 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -733,13 +784,24 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -751,15 +813,15 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
 # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -792,6 +854,8 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_SH_MOBILE_LCDC=m
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
@@ -800,24 +864,9 @@ CONFIG_FB_DEFERRED_IO=y
 #
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_LOGO is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
 # CONFIG_SND is not set
-
-#
-# Open Sound System
-#
 CONFIG_SOUND_PRIME=m
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -827,17 +876,17 @@ CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -861,9 +910,10 @@ CONFIG_RTC_INTF_DEV=y
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
@@ -872,10 +922,7 @@ CONFIG_RTC_INTF_DEV=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SH=y
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -896,14 +943,11 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 CONFIG_FUSE_FS=m
@@ -951,8 +995,11 @@ CONFIG_CONFIGFS_FS=m
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -960,20 +1007,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_BIND34 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1028,10 +1072,6 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1040,6 +1080,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
@@ -1050,6 +1091,7 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_SPINLOCK=y
@@ -1066,12 +1108,14 @@ CONFIG_STACKTRACE=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
 CONFIG_SH_STANDARD_BIOS=y
@@ -1091,54 +1135,96 @@ CONFIG_4KSTACKS=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_BLKCIPHER=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/rsk7203_defconfig b/arch/sh/configs/rsk7203_defconfig
index a0ebd439cbd2..840fe3843ffa 100644
--- a/arch/sh/configs/rsk7203_defconfig
+++ b/arch/sh/configs/rsk7203_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Tue Jun  3 13:02:42 2008
+# Linux kernel version: 2.6.26
+# Mon Jul 28 22:23:03 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
@@ -33,21 +33,22 @@ CONFIG_LOCALVERSION=""
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=y
+# CONFIG_IKCONFIG_PROC is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -72,26 +73,36 @@ CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
+# CONFIG_SLAB is not set
 # CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
+CONFIG_SLOB=y
 CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
-CONFIG_SLABINFO=y
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_MODULES is not set
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -162,7 +173,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -196,6 +209,7 @@ CONFIG_CPU_HAS_FPU=y
 #
 # Board support
 #
+CONFIG_SH_RSK7203=y
 
 #
 # Timer and clock configuration
@@ -274,6 +288,7 @@ CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ignore_loglevel"
 #
 # Executable file formats
 #
+CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_SHARED_FLAT=y
@@ -424,8 +439,8 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x20000000
-CONFIG_MTD_PHYSMAP_LEN=0x01000000
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=4
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -456,9 +471,11 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -475,7 +492,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -487,15 +503,15 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
-CONFIG_SMC91X=y
+# CONFIG_SMC91X is not set
+CONFIG_SMC911X=y
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 # CONFIG_B44 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_NETDEV_10000=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
 # Wireless LAN
@@ -503,6 +519,15 @@ CONFIG_NETDEV_10000=y
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
 # CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -587,6 +612,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 
@@ -605,6 +631,7 @@ CONFIG_SSB_POSSIBLE=y
 # Multimedia drivers
 #
 CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
@@ -618,26 +645,96 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_R8A66597_HCD=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -677,6 +774,7 @@ CONFIG_RTC_INTF_DEV=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SH=y
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -734,6 +832,7 @@ CONFIG_SYSFS=y
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 CONFIG_ROMFS_FS=y
@@ -743,12 +842,11 @@ CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 # CONFIG_NFS_V3 is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -775,16 +873,20 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_OBJECTS=y
+# CONFIG_DEBUG_OBJECTS_SELFTEST is not set
+# CONFIG_DEBUG_OBJECTS_FREE is not set
+# CONFIG_DEBUG_OBJECTS_TIMERS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -797,12 +899,14 @@ CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_WRITECOUNT=y
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_SG=y
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
@@ -830,6 +934,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/rts7751r2d1_defconfig b/arch/sh/configs/rts7751r2d1_defconfig
index 3a915fd436d9..8413236c1b37 100644
--- a/arch/sh/configs/rts7751r2d1_defconfig
+++ b/arch/sh/configs/rts7751r2d1_defconfig
@@ -1,10 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24
-# Thu Feb  7 16:25:55 2008
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:55:52 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -20,6 +21,8 @@ CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_IO_TRAPPED=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -36,17 +39,15 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
@@ -76,22 +77,31 @@ CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
 CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 # CONFIG_MODULE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
+CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -106,7 +116,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
 
 #
 # System type
@@ -116,6 +125,7 @@ CONFIG_CPU_SH4=y
 # CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
 # CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -133,6 +143,7 @@ CONFIG_CPU_SH4=y
 CONFIG_CPU_SUBTYPE_SH7751R=y
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
 # CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -140,6 +151,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
 # CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
 # CONFIG_CPU_SUBTYPE_SH5_101 is not set
 # CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
@@ -161,7 +173,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -170,6 +184,7 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -256,7 +271,6 @@ CONFIG_HZ=250
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-CONFIG_RCU_TRACE=y
 CONFIG_GUSA=y
 # CONFIG_GUSA_RB is not set
 
@@ -332,8 +346,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -367,6 +379,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
@@ -383,6 +396,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 # CONFIG_MTD is not set
@@ -399,14 +414,18 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_PHANTOM is not set
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -466,6 +485,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
@@ -478,9 +498,13 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
@@ -490,7 +514,6 @@ CONFIG_ATA=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -535,17 +558,21 @@ CONFIG_ATA=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 CONFIG_PATA_PLATFORM=y
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -564,6 +591,7 @@ CONFIG_MII=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 # CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -599,7 +627,6 @@ CONFIG_NETDEV_1000=y
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
 # CONFIG_E1000E is not set
-# CONFIG_E1000E_ENABLED is not set
 # CONFIG_IP1000 is not set
 # CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
@@ -609,12 +636,12 @@ CONFIG_NETDEV_1000=y
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
@@ -627,6 +654,7 @@ CONFIG_NETDEV_10000=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
 # CONFIG_TR is not set
 
 #
@@ -634,6 +662,7 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -690,9 +719,11 @@ CONFIG_INPUT=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 # CONFIG_NOZOMI is not set
 
@@ -726,10 +757,6 @@ CONFIG_HW_RANDOM=y
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 
@@ -765,6 +792,8 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -776,13 +805,24 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 CONFIG_DAB=y
 # CONFIG_USB_DABUSB is not set
 
@@ -802,8 +842,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -836,6 +876,8 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_SH_MOBILE_LCDC=m
 CONFIG_FB_SM501=y
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
@@ -862,15 +904,7 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_SUPERH_MONO is not set
 # CONFIG_LOGO_SUPERH_VGA16 is not set
 CONFIG_LOGO_SUPERH_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -884,21 +918,17 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_VMASTER=y
 CONFIG_SND_MPU401_UART=m
 CONFIG_SND_OPL3_LIB=m
 CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
+# CONFIG_SND_AC97_POWER_SAVE is not set
+CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
 # CONFIG_SND_ALI5451 is not set
@@ -907,6 +937,7 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_AU8810 is not set
 # CONFIG_SND_AU8820 is not set
 # CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
 # CONFIG_SND_AZT3328 is not set
 # CONFIG_SND_BT87X is not set
 # CONFIG_SND_CA0106 is not set
@@ -957,43 +988,13 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 CONFIG_SND_YMFPCI=m
-CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y
-# CONFIG_SND_AC97_POWER_SAVE is not set
-
-#
-# SPI devices
-#
-
-#
-# SUPERH devices
-#
-
-#
-# USB devices
-#
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPERH=y
+CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
-
-#
-# System on Chip audio support
-#
 # CONFIG_SND_SOC is not set
-
-#
-# SoC Audio support for SuperH
-#
-
-#
-# ALSA SoC audio for Freescale SOCs
-#
-
-#
-# Open Sound System
-#
 CONFIG_SOUND_PRIME=m
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
@@ -1022,12 +1023,16 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_EHCI_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1041,6 +1046,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1060,7 +1066,9 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 CONFIG_USB_LIBUSUAL=y
 
 #
@@ -1096,9 +1104,12 @@ CONFIG_USB_LIBUSUAL=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -1118,6 +1129,8 @@ CONFIG_RTC_INTF_DEV=y
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 CONFIG_RTC_DRV_R9701=y
 # CONFIG_RTC_DRV_RS5C348 is not set
@@ -1137,10 +1150,7 @@ CONFIG_RTC_DRV_R9701=y
 # on-CPU RTC drivers
 #
 # CONFIG_RTC_DRV_SH is not set
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -1155,14 +1165,11 @@ CONFIG_EXT2_FS=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1208,8 +1215,11 @@ CONFIG_TMPFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1275,12 +1285,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 CONFIG_EARLY_SCIF_CONSOLE=y
@@ -1295,48 +1307,81 @@ CONFIG_EARLY_PRINTK=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Crypto core or helper
+#
 # CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
@@ -1345,8 +1390,10 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/rts7751r2dplus_defconfig b/arch/sh/configs/rts7751r2dplus_defconfig
index 0a6d3b9e648b..7d9fa6e9ded5 100644
--- a/arch/sh/configs/rts7751r2dplus_defconfig
+++ b/arch/sh/configs/rts7751r2dplus_defconfig
@@ -1,10 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24
-# Thu Feb  7 16:17:47 2008
+# Linux kernel version: 2.6.26
+# Wed Jul 30 01:59:18 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -20,6 +21,8 @@ CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_IO_TRAPPED=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -36,17 +39,15 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
@@ -76,22 +77,31 @@ CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
 CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 # CONFIG_MODULE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
+CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -106,7 +116,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
 
 #
 # System type
@@ -116,6 +125,7 @@ CONFIG_CPU_SH4=y
 # CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
 # CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -133,6 +143,7 @@ CONFIG_CPU_SH4=y
 CONFIG_CPU_SUBTYPE_SH7751R=y
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
 # CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -140,6 +151,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
 # CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
 # CONFIG_CPU_SUBTYPE_SH5_101 is not set
 # CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
@@ -161,7 +173,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -170,6 +184,7 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -256,7 +271,6 @@ CONFIG_HZ=250
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
-CONFIG_RCU_TRACE=y
 CONFIG_GUSA=y
 # CONFIG_GUSA_RB is not set
 
@@ -332,8 +346,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -367,6 +379,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
@@ -383,6 +396,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 # CONFIG_MTD is not set
@@ -399,14 +414,18 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_PHANTOM is not set
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -466,6 +485,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
@@ -478,9 +498,13 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
@@ -490,7 +514,6 @@ CONFIG_ATA=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -535,17 +558,21 @@ CONFIG_ATA=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 CONFIG_PATA_PLATFORM=y
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -564,6 +591,7 @@ CONFIG_MII=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 # CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -599,7 +627,6 @@ CONFIG_NETDEV_1000=y
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
 # CONFIG_E1000E is not set
-# CONFIG_E1000E_ENABLED is not set
 # CONFIG_IP1000 is not set
 # CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
@@ -609,12 +636,12 @@ CONFIG_NETDEV_1000=y
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 # CONFIG_BNX2 is not set
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
@@ -627,6 +654,7 @@ CONFIG_NETDEV_10000=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
+# CONFIG_SFC is not set
 # CONFIG_TR is not set
 
 #
@@ -634,6 +662,7 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -690,9 +719,11 @@ CONFIG_INPUT=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 # CONFIG_NOZOMI is not set
 
@@ -726,10 +757,6 @@ CONFIG_HW_RANDOM=y
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 
@@ -765,6 +792,8 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -776,13 +805,24 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 CONFIG_DAB=y
 # CONFIG_USB_DABUSB is not set
 
@@ -802,8 +842,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -836,6 +876,8 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_SH_MOBILE_LCDC=m
 CONFIG_FB_SM501=y
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
@@ -862,15 +904,7 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_SUPERH_MONO is not set
 # CONFIG_LOGO_SUPERH_VGA16 is not set
 CONFIG_LOGO_SUPERH_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -884,21 +918,17 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_VMASTER=y
 CONFIG_SND_MPU401_UART=m
 CONFIG_SND_OPL3_LIB=m
 CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
+# CONFIG_SND_AC97_POWER_SAVE is not set
+CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
 # CONFIG_SND_ALI5451 is not set
@@ -907,6 +937,7 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_AU8810 is not set
 # CONFIG_SND_AU8820 is not set
 # CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
 # CONFIG_SND_AZT3328 is not set
 # CONFIG_SND_BT87X is not set
 # CONFIG_SND_CA0106 is not set
@@ -957,43 +988,13 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 CONFIG_SND_YMFPCI=m
-CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y
-# CONFIG_SND_AC97_POWER_SAVE is not set
-
-#
-# SPI devices
-#
-
-#
-# SUPERH devices
-#
-
-#
-# USB devices
-#
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPERH=y
+CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
-
-#
-# System on Chip audio support
-#
 # CONFIG_SND_SOC is not set
-
-#
-# SoC Audio support for SuperH
-#
-
-#
-# ALSA SoC audio for Freescale SOCs
-#
-
-#
-# Open Sound System
-#
 CONFIG_SOUND_PRIME=m
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
@@ -1022,12 +1023,16 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_EHCI_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1041,6 +1046,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1060,7 +1066,9 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 CONFIG_USB_LIBUSUAL=y
 
 #
@@ -1096,9 +1104,12 @@ CONFIG_USB_LIBUSUAL=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -1118,6 +1129,8 @@ CONFIG_RTC_INTF_DEV=y
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 CONFIG_RTC_DRV_R9701=y
 # CONFIG_RTC_DRV_RS5C348 is not set
@@ -1137,10 +1150,7 @@ CONFIG_RTC_DRV_R9701=y
 # on-CPU RTC drivers
 #
 # CONFIG_RTC_DRV_SH is not set
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -1155,14 +1165,11 @@ CONFIG_EXT2_FS=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1208,8 +1215,11 @@ CONFIG_TMPFS=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1275,12 +1285,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 CONFIG_EARLY_SCIF_CONSOLE=y
@@ -1295,48 +1307,81 @@ CONFIG_EARLY_PRINTK=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Crypto core or helper
+#
 # CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
@@ -1345,8 +1390,10 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/sdk7780_defconfig b/arch/sh/configs/sdk7780_defconfig
index bb9bcd6591ab..6d834f242905 100644
--- a/arch/sh/configs/sdk7780_defconfig
+++ b/arch/sh/configs/sdk7780_defconfig
@@ -1,10 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc7
-# Tue Jan 22 11:34:03 2008
+# Linux kernel version: 2.6.26
+# Wed Jul 30 02:00:12 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -20,6 +21,7 @@ CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -38,24 +40,23 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=18
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -63,11 +64,13 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
@@ -75,11 +78,24 @@ CONFIG_SLUB_DEBUG=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
@@ -90,6 +106,7 @@ CONFIG_LBD=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -103,6 +120,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
@@ -113,6 +131,7 @@ CONFIG_CPU_SH4A=y
 # CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
 # CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -130,6 +149,7 @@ CONFIG_CPU_SH4A=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
 # CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 CONFIG_CPU_SUBTYPE_SH7780=y
@@ -137,6 +157,7 @@ CONFIG_CPU_SUBTYPE_SH7780=y
 # CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
 # CONFIG_CPU_SUBTYPE_SH5_101 is not set
 # CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
@@ -159,7 +180,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_HUGETLB_PAGE_SIZE_64K=y
 # CONFIG_HUGETLB_PAGE_SIZE_256K is not set
 # CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
@@ -174,6 +197,7 @@ CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_RESOURCES_64BIT=y
 CONFIG_ZONE_DMA_FLAG=0
@@ -205,7 +229,6 @@ CONFIG_CPU_HAS_FPU=y
 # CONFIG_SH_7780_SOLUTION_ENGINE is not set
 CONFIG_SH_SDK7780=y
 # CONFIG_SH_HIGHLANDER is not set
-# CONFIG_SH_SDK7780_STANDALONE is not set
 CONFIG_SH_SDK7780_BASE=y
 
 #
@@ -250,12 +273,13 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
 # CONFIG_CRASH_DUMP is not set
 # CONFIG_PREEMPT_NONE is not set
 # CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
-CONFIG_PREEMPT_BKL=y
+# CONFIG_PREEMPT_RCU is not set
 CONFIG_GUSA=y
 
 #
@@ -321,6 +345,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
@@ -370,8 +395,10 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=y
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
 # CONFIG_IPV6_TUNNEL is not set
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
@@ -397,7 +424,6 @@ CONFIG_NET_SCHED=y
 # CONFIG_NET_SCH_HTB is not set
 # CONFIG_NET_SCH_HFSC is not set
 # CONFIG_NET_SCH_PRIO is not set
-# CONFIG_NET_SCH_RR is not set
 # CONFIG_NET_SCH_RED is not set
 # CONFIG_NET_SCH_SFQ is not set
 # CONFIG_NET_SCH_TEQL is not set
@@ -405,7 +431,6 @@ CONFIG_NET_SCHED=y
 # CONFIG_NET_SCH_GRED is not set
 # CONFIG_NET_SCH_DSMARK is not set
 # CONFIG_NET_SCH_NETEM is not set
-# CONFIG_NET_SCH_INGRESS is not set
 
 #
 # Classification
@@ -417,9 +442,9 @@ CONFIG_NET_SCHED=y
 # CONFIG_NET_CLS_U32 is not set
 # CONFIG_NET_CLS_RSVP is not set
 # CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
 # CONFIG_NET_EMATCH is not set
 # CONFIG_NET_CLS_ACT is not set
-# CONFIG_NET_CLS_POLICE is not set
 CONFIG_NET_SCH_FIFO=y
 
 #
@@ -427,6 +452,7 @@ CONFIG_NET_SCH_FIFO=y
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
@@ -452,6 +478,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -475,16 +503,18 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 # CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 CONFIG_IDE_MAX_HWIFS=4
 CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
@@ -492,6 +522,7 @@ CONFIG_IDEDISK_MULTI_MODE=y
 # CONFIG_BLK_DEV_IDECS is not set
 # CONFIG_BLK_DEV_DELKIN is not set
 CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_BLK_DEV_IDESCSI is not set
@@ -501,14 +532,12 @@ CONFIG_IDE_PROC_FS=y
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
 CONFIG_BLK_DEV_PLATFORM=y
 
 #
 # PCI IDE chipsets support
 #
 CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
 CONFIG_IDEPCI_PCIBUS_ORDER=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_BLK_DEV_GENERIC=y
@@ -518,10 +547,8 @@ CONFIG_BLK_DEV_GENERIC=y
 # CONFIG_BLK_DEV_AMD74XX is not set
 # CONFIG_BLK_DEV_CMD64X is not set
 # CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
 # CONFIG_BLK_DEV_CS5520 is not set
 # CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_JMICRON is not set
 # CONFIG_BLK_DEV_SC1200 is not set
@@ -537,10 +564,7 @@ CONFIG_BLK_DEV_GENERIC=y
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -600,6 +624,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_IPR is not set
@@ -613,9 +638,13 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
 # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
@@ -625,7 +654,6 @@ CONFIG_ATA=y
 # CONFIG_SATA_PROMISE is not set
 # CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIL24 is not set
 # CONFIG_SATA_SIS is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
@@ -654,6 +682,7 @@ CONFIG_ATA=y
 # CONFIG_PATA_MPIIX is not set
 # CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
 # CONFIG_PATA_NS87410 is not set
 # CONFIG_PATA_NS87415 is not set
 # CONFIG_PATA_OPTI is not set
@@ -670,6 +699,7 @@ CONFIG_ATA=y
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 # CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
 CONFIG_MD=y
 # CONFIG_BLK_DEV_MD is not set
 CONFIG_BLK_DEV_DM=y
@@ -686,11 +716,14 @@ CONFIG_BLK_DEV_DM=y
 #
 # IEEE 1394 (FireWire) support
 #
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -708,6 +741,7 @@ CONFIG_MII=y
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
 CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
@@ -726,6 +760,7 @@ CONFIG_SMC91X=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -743,7 +778,6 @@ CONFIG_SMC91X=y
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
 CONFIG_NETCONSOLE=y
 # CONFIG_NETCONSOLE_DYNAMIC is not set
 CONFIG_NETPOLL=y
@@ -780,6 +814,7 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
 CONFIG_MOUSE_PS2_ALPS=y
@@ -812,10 +847,13 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -847,22 +885,20 @@ CONFIG_HW_RANDOM=y
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 # CONFIG_W1 is not set
 CONFIG_POWER_SUPPLY=y
 # CONFIG_POWER_SUPPLY_DEBUG is not set
 # CONFIG_PDA_POWER is not set
 # CONFIG_BATTERY_DS2760 is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -870,8 +906,10 @@ CONFIG_POWER_SUPPLY=y
 #
 CONFIG_SSB_POSSIBLE=y
 CONFIG_SSB=y
+CONFIG_SSB_SPROM=y
 CONFIG_SSB_PCIHOST_POSSIBLE=y
 CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
 CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
 # CONFIG_SSB_PCMCIAHOST is not set
 # CONFIG_SSB_SILENT is not set
@@ -882,13 +920,24 @@ CONFIG_SSB_DRIVER_PCICORE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -900,15 +949,15 @@ CONFIG_SSB_DRIVER_PCICORE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
 # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -941,6 +990,8 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_SH_MOBILE_LCDC=m
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
@@ -970,24 +1021,9 @@ CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_LOGO_SUPERH_MONO=y
 CONFIG_LOGO_SUPERH_VGA16=y
 CONFIG_LOGO_SUPERH_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
 # CONFIG_SND is not set
-
-#
-# Open Sound System
-#
 CONFIG_SOUND_PRIME=y
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -1006,6 +1042,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -1014,15 +1051,18 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 # CONFIG_USB_OHCI_HCD is not set
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
@@ -1033,6 +1073,7 @@ CONFIG_USB_EHCI_HCD=y
 #
 # CONFIG_USB_ACM is not set
 CONFIG_USB_PRINTER=y
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1054,6 +1095,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -1067,10 +1109,6 @@ CONFIG_USB_MON=y
 # USB port drivers
 #
 # CONFIG_USB_USS720 is not set
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1096,16 +1134,10 @@ CONFIG_USB_MON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 
@@ -1117,13 +1149,11 @@ CONFIG_LEDS_CLASS=y
 # LED Triggers
 #
 # CONFIG_LEDS_TRIGGERS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
-
-#
-# Userspace I/O
-#
 # CONFIG_UIO is not set
 
 #
@@ -1145,14 +1175,11 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-CONFIG_MINIX_FS=y
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 CONFIG_AUTOFS4_FS=y
 # CONFIG_FUSE_FS is not set
@@ -1203,8 +1230,11 @@ CONFIG_HUGETLB_PAGE=y
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1212,19 +1242,16 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1279,7 +1306,6 @@ CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=y
 # CONFIG_DLM is not set
-# CONFIG_INSTRUMENTATION is not set
 
 #
 # Kernel hacking
@@ -1288,6 +1314,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 # CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_UNUSED_SYMBOLS=y
 # CONFIG_DEBUG_FS is not set
@@ -1295,10 +1322,14 @@ CONFIG_UNUSED_SYMBOLS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
 CONFIG_DEBUG_PREEMPT=y
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
@@ -1313,12 +1344,14 @@ CONFIG_DEBUG_PREEMPT=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_FRAME_POINTER is not set
-# CONFIG_FORCED_INLINING is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
 CONFIG_SH_STANDARD_BIOS=y
@@ -1338,52 +1371,94 @@ CONFIG_DEBUG_STACKOVERFLOW=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
 CONFIG_CRYPTO_ALGAPI=y
 # CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
 # CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/sh/configs/se7206_defconfig b/arch/sh/configs/se7206_defconfig
index 6b34baa26eae..af15cbef12ba 100644
--- a/arch/sh/configs/se7206_defconfig
+++ b/arch/sh/configs/se7206_defconfig
@@ -1,10 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Tue Jun  3 20:27:08 2008
+# Linux kernel version: 2.6.26
+# Wed Jul 30 02:06:07 2008
 #
 CONFIG_SUPERH=y
 CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -87,9 +88,14 @@ CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
@@ -99,12 +105,13 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
+CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -175,7 +182,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -294,6 +303,7 @@ CONFIG_CF_BASE_ADDR=0xb8000000
 #
 # Executable file formats
 #
+CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_SHARED_FLAT=y
@@ -487,6 +497,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_93CX6=y
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -503,7 +514,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -516,6 +526,7 @@ CONFIG_MII=y
 # CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -583,6 +594,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -594,6 +606,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 
@@ -625,10 +638,6 @@ CONFIG_SSB_POSSIBLE=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
@@ -669,6 +678,7 @@ CONFIG_RTC_INTF_DEV=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SH=y
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -728,6 +738,7 @@ CONFIG_CONFIGFS_FS=y
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 CONFIG_ROMFS_FS=y
@@ -738,13 +749,12 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -776,6 +786,8 @@ CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -795,6 +807,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 CONFIG_DEBUG_VM=y
 # CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 CONFIG_DEBUG_LIST=y
 # CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
@@ -860,6 +873,10 @@ CONFIG_CRYPTO_ALGAPI=y
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
@@ -899,6 +916,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_FIRST_BIT is not set
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
 CONFIG_CRC7=y
diff --git a/arch/sh/configs/se7343_defconfig b/arch/sh/configs/se7343_defconfig
index 84c0075e2ad4..4e30b70377e2 100644
--- a/arch/sh/configs/se7343_defconfig
+++ b/arch/sh/configs/se7343_defconfig
@@ -1,40 +1,56 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.18
-# Tue Oct  3 11:46:17 2006
+# Linux kernel version: 2.6.26
+# Wed Jul 30 02:08:38 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
-CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
@@ -46,33 +62,47 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 # CONFIG_FUTEX is not set
+CONFIG_ANON_INODES=y
 # CONFIG_EPOLL is not set
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 # CONFIG_SHMEM is not set
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-
-#
-# Block layer
-#
+CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -86,62 +116,28 @@ CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
-CONFIG_SOLUTION_ENGINE=y
-# CONFIG_SH_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SOLUTION_ENGINE is not set
-# CONFIG_SH_7300_SOLUTION_ENGINE is not set
-CONFIG_SH_7343_SOLUTION_ENGINE=y
-# CONFIG_SH_73180_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SYSTEMH is not set
-# CONFIG_SH_HP6XX is not set
-# CONFIG_SH_EC3104 is not set
-# CONFIG_SH_SATURN is not set
-# CONFIG_SH_DREAMCAST is not set
-# CONFIG_SH_BIGSUR is not set
-# CONFIG_SH_MPC1211 is not set
-# CONFIG_SH_SH03 is not set
-# CONFIG_SH_SECUREEDGE5410 is not set
-# CONFIG_SH_HS7751RVOIP is not set
-# CONFIG_SH_7710VOIPGW is not set
-# CONFIG_SH_RTS7751R2D is not set
-# CONFIG_SH_R7780RP is not set
-# CONFIG_SH_EDOSK7705 is not set
-# CONFIG_SH_SH4202_MICRODEV is not set
-# CONFIG_SH_LANDISK is not set
-# CONFIG_SH_TITAN is not set
-# CONFIG_SH_SHMIN is not set
-# CONFIG_SH_UNKNOWN is not set
-
-#
-# Processor selection
-#
 CONFIG_CPU_SH4=y
 CONFIG_CPU_SH4A=y
 CONFIG_CPU_SH4AL_DSP=y
-
-#
-# SH-2 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7604 is not set
-
-#
-# SH-3 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7300 is not set
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
 # CONFIG_CPU_SUBTYPE_SH7708 is not set
 # CONFIG_CPU_SUBTYPE_SH7709 is not set
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
-
-#
-# SH-4 Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -150,67 +146,89 @@ CONFIG_CPU_SH4AL_DSP=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-
-#
-# ST40 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
-
-#
-# SH-4A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
-
-#
-# SH4AL-DSP Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH73180 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
 CONFIG_CPU_SUBTYPE_SH7343=y
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
 #
+CONFIG_QUICKLIST=y
 CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x0c000000
 CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_32BIT=y
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
 
 #
 # Cache configuration
 #
 # CONFIG_SH_DIRECT_MAPPED is not set
-# CONFIG_SH_WRITETHROUGH is not set
-# CONFIG_SH_OCRAM is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
 
 #
 # Processor features
 #
 CONFIG_CPU_LITTLE_ENDIAN=y
-# CONFIG_SH_FPU is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
 # CONFIG_SH_FPU_EMU is not set
 CONFIG_SH_DSP=y
 # CONFIG_SH_STORE_QUEUES is not set
 CONFIG_CPU_HAS_INTEVT=y
 CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_DSP=y
+
+#
+# Board support
+#
+CONFIG_SOLUTION_ENGINE=y
+CONFIG_SH_7343_SOLUTION_ENGINE=y
 
 #
-# Timer support
+# Timer and clock configuration
 #
 CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
 CONFIG_SH_PCLK_FREQ=27000000
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -225,57 +243,50 @@ CONFIG_SH_PCLK_FREQ=27000000
 #
 # Companion Chips
 #
-# CONFIG_HD6446X_SERIES is not set
+
+#
+# Additional SuperH Device Drivers
+#
 CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
 
 #
 # Kernel features
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
-# CONFIG_SMP is not set
+# CONFIG_CRASH_DUMP is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
 
 #
 # Boot options
 #
 CONFIG_ZERO_PAGE_OFFSET=0x00001000
 CONFIG_BOOT_LINK_OFFSET=0x00800000
-# CONFIG_UBC_WAKEUP is not set
 # CONFIG_CMDLINE_BOOL is not set
 
 #
 # Bus options
 #
-# CONFIG_PCI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_CF_ENABLER is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
-# PCI Hotplug Support
-#
-
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_FLAT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
-# Power management options (EXPERIMENTAL)
-#
-# CONFIG_PM is not set
-
-#
 # Networking
 #
 CONFIG_NET=y
@@ -283,22 +294,20 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
+# CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_ARPD is not set
@@ -310,29 +319,18 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_TUNNEL is not set
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -345,10 +343,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -356,9 +350,20 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -367,36 +372,34 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -422,13 +425,15 @@ CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -445,130 +450,102 @@ CONFIG_MTD_RAM=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 
 #
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
+# SCSI support type (disk, tape, CD-ROM)
 #
-# CONFIG_ATA is not set
+# CONFIG_BLK_DEV_SD is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
 
 #
-# Multi-device support (RAID and LVM)
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-# CONFIG_MD is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
+# SCSI Transports
 #
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_STNIC is not set
 CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -576,13 +553,13 @@ CONFIG_SMC91X=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
 #
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -592,6 +569,7 @@ CONFIG_INPUT=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -605,9 +583,11 @@ CONFIG_INPUT=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -626,156 +606,106 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_UNIX98_PTYS is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-
-#
-# I2C Algorithms
-#
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
-# CONFIG_SENSORS_EEPROM is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
+# CONFIG_I2C is not set
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Dallas's 1-wire bus
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Hardware Monitoring support
+# Multifunction device drivers
 #
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
-# Misc devices
+# Multimedia devices
 #
 
 #
-# Multimedia devices
+# Multimedia core support
 #
 CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
 CONFIG_VIDEO_V4L1_COMPAT=y
-CONFIG_VIDEO_V4L2=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
 
 #
-# Video Capture Adapters
-#
-
-#
-# Video Capture Adapters
+# Multimedia drivers
 #
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
 CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
 # CONFIG_VIDEO_VIVI is not set
 # CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_TUNER_3036 is not set
-
-#
-# Radio Adapters
-#
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-CONFIG_FIRMWARE_EDID=y
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_EPSON1355 is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_VIRTUAL is not set
 
 #
-# Console display driver support
+# Frame buffer hardware drivers
 #
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
-# CONFIG_LOGO is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_SH_MOBILE_LCDC=m
+# CONFIG_FB_VIRTUAL is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
-CONFIG_SOUND=y
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# Advanced Linux Sound Architecture
+# Console display driver support
 #
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
@@ -791,96 +721,49 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_VIRMIDI is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# Open Sound System
-#
+CONFIG_SND_SUPERH=y
+# CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
 #
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -909,7 +792,6 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLBFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -922,35 +804,34 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
+CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
 # CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_ROOT_NFS=y
+# CONFIG_NFSD_V4 is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
@@ -963,56 +844,136 @@ CONFIG_SUNRPC=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
-# CONFIG_EARLY_SCIF_CONSOLE is not set
-# CONFIG_KGDB is not set
+CONFIG_EARLY_SCIF_CONSOLE=y
+CONFIG_EARLY_SCIF_CONSOLE_PORT=0xffe00000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_SH_KGDB is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/se7619_defconfig b/arch/sh/configs/se7619_defconfig
index 3a3c3c1f507d..80c1c72edb56 100644
--- a/arch/sh/configs/se7619_defconfig
+++ b/arch/sh/configs/se7619_defconfig
@@ -1,9 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22-rc4
-# Fri Jun 15 19:43:06 2007
+# Linux kernel version: 2.6.26
+# Wed Jul 30 02:12:32 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -17,27 +19,26 @@ CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SYSVIPC is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -49,6 +50,7 @@ CONFIG_EMBEDDED=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 # CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 # CONFIG_BASE_FULL is not set
 # CONFIG_FUTEX is not set
 CONFIG_ANON_INODES=y
@@ -60,20 +62,26 @@ CONFIG_EVENTFD=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_SLABINFO=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=1
-
-#
-# Loadable module support
-#
 # CONFIG_MODULES is not set
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -87,14 +95,17 @@ CONFIG_IOSCHED_NOOP=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
 CONFIG_CPU_SH2=y
 CONFIG_CPU_SUBTYPE_SH7619=y
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
-# CONFIG_CPU_SUBTYPE_SH7300 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -102,6 +113,8 @@ CONFIG_CPU_SUBTYPE_SH7619=y
 # CONFIG_CPU_SUBTYPE_SH7709 is not set
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
 # CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -110,14 +123,17 @@ CONFIG_CPU_SUBTYPE_SH7619=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 # CONFIG_CPU_SUBTYPE_SH7785 is not set
-# CONFIG_CPU_SUBTYPE_SH73180 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
@@ -126,6 +142,7 @@ CONFIG_QUICKLIST=y
 CONFIG_PAGE_OFFSET=0x00000000
 CONFIG_MEMORY_START=0x0c000000
 CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_DEFAULT=y
@@ -134,7 +151,9 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_ENTRY_OFFSET=0x00001000
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -142,6 +161,8 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
@@ -151,7 +172,9 @@ CONFIG_NR_QUICK=2
 # Cache configuration
 #
 # CONFIG_SH_DIRECT_MAPPED is not set
-CONFIG_SH_WRITETHROUGH=y
+# CONFIG_CACHE_WRITEBACK is not set
+CONFIG_CACHE_WRITETHROUGH=y
+# CONFIG_CACHE_OFF is not set
 
 #
 # Processor features
@@ -159,8 +182,6 @@ CONFIG_SH_WRITETHROUGH=y
 # CONFIG_CPU_LITTLE_ENDIAN is not set
 CONFIG_CPU_BIG_ENDIAN=y
 # CONFIG_SH_FPU_EMU is not set
-# CONFIG_SH_DSP is not set
-CONFIG_CPU_HAS_IPR_IRQ=y
 
 #
 # Board support
@@ -185,7 +206,6 @@ CONFIG_SH_CLK_MD=5
 #
 # DMA support
 #
-# CONFIG_SH_DMA is not set
 
 #
 # Companion Chips
@@ -205,11 +225,13 @@ CONFIG_HZ_100=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=100
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
 # CONFIG_CRASH_DUMP is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
 
 #
 # Boot options
@@ -221,15 +243,13 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
 #
 # Bus options
 #
+# CONFIG_CF_ENABLER is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# PCCARD (PCMCIA/CardBus) support
-#
-
-#
 # Executable file formats
 #
+CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
@@ -250,10 +270,6 @@ CONFIG_BINFMT_ZFLAT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
@@ -263,6 +279,7 @@ CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
 # CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
 # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -275,6 +292,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -334,29 +352,17 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
-
-#
-# Misc devices
-#
-# CONFIG_BLINK is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -364,21 +370,10 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 #
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# ISDN subsystem
-#
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -386,13 +381,13 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
 #
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -416,6 +411,7 @@ CONFIG_INPUT=y
 # Character devices
 #
 # CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -433,123 +429,84 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_UNIX98_PTYS is not set
 # CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Dallas's 1-wire bus
+# Sonics Silicon Backplane
 #
-# CONFIG_W1 is not set
-# CONFIG_HWMON is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
-CONFIG_DAB=y
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_DAB=y
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
+# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
+CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -561,12 +518,9 @@ CONFIG_HID=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-CONFIG_ROMFS_FS=y
+# CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -592,7 +546,6 @@ CONFIG_PROC_SYSCTL=y
 # CONFIG_SYSFS is not set
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 
 #
 # Miscellaneous filesystems
@@ -607,8 +560,11 @@ CONFIG_RAMFS=y
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 
@@ -617,28 +573,23 @@ CONFIG_RAMFS=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 # CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 # CONFIG_EARLY_SCIF_CONSOLE is not set
 
@@ -646,20 +597,20 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # Security options
 #
 # CONFIG_KEYS is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_HAS_IOMEM=y
diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig
index 2dd83af988f0..7be79cd04eb0 100644
--- a/arch/sh/configs/se7712_defconfig
+++ b/arch/sh/configs/se7712_defconfig
@@ -1,53 +1,57 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21-rc4
-# Wed Mar 28 10:19:02 2007
+# Linux kernel version: 2.6.26-rc6
+# Wed Jun 18 16:36:08 2008
 #
 CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-# CONFIG_GENERIC_TIME is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -55,33 +59,41 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 # CONFIG_BUG is not set
 CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 # CONFIG_BASE_FULL is not set
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 # CONFIG_SHMEM is not set
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=1
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 # CONFIG_MODULE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 # CONFIG_KMOD is not set
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -95,57 +107,17 @@ CONFIG_IOSCHED_NOOP=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System type
 #
-CONFIG_SOLUTION_ENGINE=y
-CONFIG_SH_SOLUTION_ENGINE=y
-# CONFIG_SH_7751_SOLUTION_ENGINE is not set
-# CONFIG_SH_7300_SOLUTION_ENGINE is not set
-# CONFIG_SH_7343_SOLUTION_ENGINE is not set
-# CONFIG_SH_73180_SOLUTION_ENGINE is not set
-# CONFIG_SH_7751_SYSTEMH is not set
-# CONFIG_SH_HP6XX is not set
-# CONFIG_SH_SATURN is not set
-# CONFIG_SH_DREAMCAST is not set
-# CONFIG_SH_MPC1211 is not set
-# CONFIG_SH_SH03 is not set
-# CONFIG_SH_SECUREEDGE5410 is not set
-# CONFIG_SH_HS7751RVOIP is not set
-# CONFIG_SH_7710VOIPGW is not set
-# CONFIG_SH_RTS7751R2D is not set
-# CONFIG_SH_HIGHLANDER is not set
-# CONFIG_SH_EDOSK7705 is not set
-# CONFIG_SH_SH4202_MICRODEV is not set
-# CONFIG_SH_LANDISK is not set
-# CONFIG_SH_TITAN is not set
-# CONFIG_SH_SHMIN is not set
-# CONFIG_SH_7206_SOLUTION_ENGINE is not set
-# CONFIG_SH_7619_SOLUTION_ENGINE is not set
-# CONFIG_SH_LBOX_RE2 is not set
-# CONFIG_SH_UNKNOWN is not set
-
-#
-# Processor selection
-#
 CONFIG_CPU_SH3=y
-
-#
-# SH-2 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7604 is not set
 # CONFIG_CPU_SUBTYPE_SH7619 is not set
-
-#
-# SH-2A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
 # CONFIG_CPU_SUBTYPE_SH7206 is not set
-
-#
-# SH-3 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH7300 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
 # CONFIG_CPU_SUBTYPE_SH7705 is not set
 # CONFIG_CPU_SUBTYPE_SH7706 is not set
 # CONFIG_CPU_SUBTYPE_SH7707 is not set
@@ -153,10 +125,8 @@ CONFIG_CPU_SH3=y
 # CONFIG_CPU_SUBTYPE_SH7709 is not set
 # CONFIG_CPU_SUBTYPE_SH7710 is not set
 CONFIG_CPU_SUBTYPE_SH7712=y
-
-#
-# SH-4 Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
 # CONFIG_CPU_SUBTYPE_SH7750 is not set
 # CONFIG_CPU_SUBTYPE_SH7091 is not set
 # CONFIG_CPU_SUBTYPE_SH7750R is not set
@@ -165,37 +135,37 @@ CONFIG_CPU_SUBTYPE_SH7712=y
 # CONFIG_CPU_SUBTYPE_SH7751R is not set
 # CONFIG_CPU_SUBTYPE_SH7760 is not set
 # CONFIG_CPU_SUBTYPE_SH4_202 is not set
-
-#
-# ST40 Processor Support
-#
-# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
-# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
-
-#
-# SH-4A Processor Support
-#
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
 # CONFIG_CPU_SUBTYPE_SH7770 is not set
 # CONFIG_CPU_SUBTYPE_SH7780 is not set
 # CONFIG_CPU_SUBTYPE_SH7785 is not set
-
-#
-# SH4AL-DSP Processor Support
-#
-# CONFIG_CPU_SUBTYPE_SH73180 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
 # CONFIG_CPU_SUBTYPE_SH7343 is not set
 # CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
 
 #
 # Memory management options
 #
+CONFIG_QUICKLIST=y
 CONFIG_MMU=y
 CONFIG_PAGE_OFFSET=0x80000000
 CONFIG_MEMORY_START=0x0c000000
 CONFIG_MEMORY_SIZE=0x02000000
+CONFIG_29BIT=y
 CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -203,21 +173,21 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
 
 #
 # Cache configuration
 #
 # CONFIG_SH_DIRECT_MAPPED is not set
-# CONFIG_SH_WRITETHROUGH is not set
-# CONFIG_SH_OCRAM is not set
-CONFIG_CF_ENABLER=y
-# CONFIG_CF_AREA5 is not set
-CONFIG_CF_AREA6=y
-CONFIG_CF_BASE_ADDR=0xb8000000
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
 
 #
 # Processor features
@@ -230,6 +200,14 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_HAS_INTEVT=y
 CONFIG_CPU_HAS_IPR_IRQ=y
 CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_DSP=y
+
+#
+# Board support
+#
+CONFIG_SOLUTION_ENGINE=y
+CONFIG_SH_SOLUTION_ENGINE=y
+# CONFIG_SH_AP325RXA is not set
 
 #
 # Timer and clock configuration
@@ -237,6 +215,10 @@ CONFIG_CPU_HAS_SR_RB=y
 CONFIG_SH_TMU=y
 CONFIG_SH_TIMER_IRQ=16
 CONFIG_SH_PCLK_FREQ=66666666
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
 # CPU Frequency scaling
@@ -251,7 +233,6 @@ CONFIG_SH_PCLK_FREQ=66666666
 #
 # Companion Chips
 #
-# CONFIG_HD6446X_SERIES is not set
 
 #
 # Additional SuperH Device Drivers
@@ -267,48 +248,40 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 # CONFIG_KEXEC is not set
-# CONFIG_SMP is not set
+# CONFIG_CRASH_DUMP is not set
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
 
 #
 # Boot options
 #
 CONFIG_ZERO_PAGE_OFFSET=0x00001000
 CONFIG_BOOT_LINK_OFFSET=0x00800000
-# CONFIG_UBC_WAKEUP is not set
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/sda1"
 
 #
 # Bus options
 #
-# CONFIG_PCI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+CONFIG_CF_ENABLER=y
+# CONFIG_CF_AREA5 is not set
+CONFIG_CF_AREA6=y
+CONFIG_CF_BASE_ADDR=0xb8000000
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
-# PCI Hotplug Support
-#
-
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_FLAT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
-# Power management options (EXPERIMENTAL)
-#
-# CONFIG_PM is not set
-
-#
 # Networking
 #
 CONFIG_NET=y
@@ -316,7 +289,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
@@ -324,6 +296,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
 # CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
@@ -334,11 +307,10 @@ CONFIG_ASK_IP_FIB_HASH=y
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_MULTIPLE_TABLES=y
 CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
 CONFIG_IP_ROUTE_VERBOSE=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
+CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
@@ -355,30 +327,17 @@ CONFIG_INET_TUNNEL=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -391,15 +350,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_FIFO=y
-CONFIG_NET_SCH_CLK_JIFFIES=y
-# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
-# CONFIG_NET_SCH_CLK_CPU is not set
 
 #
 # Queueing/Scheduling
@@ -408,6 +359,7 @@ CONFIG_NET_SCH_CBQ=y
 CONFIG_NET_SCH_HTB=y
 CONFIG_NET_SCH_HFSC=y
 CONFIG_NET_SCH_PRIO=y
+# CONFIG_NET_SCH_RR is not set
 CONFIG_NET_SCH_RED=y
 CONFIG_NET_SCH_SFQ=y
 CONFIG_NET_SCH_TEQL=y
@@ -415,7 +367,6 @@ CONFIG_NET_SCH_TBF=y
 CONFIG_NET_SCH_GRED=y
 CONFIG_NET_SCH_DSMARK=y
 CONFIG_NET_SCH_NETEM=y
-CONFIG_NET_SCH_INGRESS=y
 
 #
 # Classification
@@ -429,50 +380,55 @@ CONFIG_NET_CLS_FW=y
 # CONFIG_NET_CLS_U32 is not set
 # CONFIG_NET_CLS_RSVP is not set
 # CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
 # CONFIG_NET_EMATCH is not set
 # CONFIG_NET_CLS_ACT is not set
-# CONFIG_NET_CLS_POLICE is not set
 CONFIG_NET_CLS_IND=y
-CONFIG_NET_ESTIMATOR=y
+CONFIG_NET_SCH_FIFO=y
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_AF_RXRPC is not set
 CONFIG_FIB_RULES=y
 
 #
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
 # Device Drivers
 #
 
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -485,6 +441,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -510,7 +467,6 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -533,44 +489,25 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -578,6 +515,7 @@ CONFIG_MTD_CFI_UTIL=y
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
@@ -599,6 +537,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -606,94 +545,72 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
 CONFIG_PATA_PLATFORM=y
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_STNIC is not set
+CONFIG_SH_ETH=y
+# CONFIG_SMC91X is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -711,6 +628,7 @@ CONFIG_NETDEVICES=y
 # Character devices
 #
 # CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -728,99 +646,78 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 # CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=m
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# Hardware Monitoring support
+# Sonics Silicon Backplane
 #
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
-# CONFIG_SOUND is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# USB support
+# Sound
 #
-# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 
@@ -834,40 +731,10 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_TRIGGERS=y
 # CONFIG_LEDS_TRIGGER_TIMER is not set
 # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -877,20 +744,21 @@ CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
 # CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -919,7 +787,6 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLBFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -935,68 +802,67 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-# CONFIG_NFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
 # CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
@@ -1004,21 +870,28 @@ CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
-# CONFIG_FORCED_INLINING is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 # CONFIG_SH_STANDARD_BIOS is not set
 # CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DEBUG_BOOTMEM is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_4KSTACKS is not set
+# CONFIG_IRQSTACKS is not set
 # CONFIG_SH_KGDB is not set
 
 #
@@ -1026,62 +899,100 @@ CONFIG_FRAME_POINTER=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
 
 #
-# Cryptographic options
+# Crypto core or helper
 #
-CONFIG_CRYPTO=y
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_BLKCIPHER=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
 CONFIG_CRYPTO_SHA1=y
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
 # CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Hardware crypto devices
+# Compression
 #
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 CONFIG_CRC_CCITT=y
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/sh7763rdp_defconfig b/arch/sh/configs/sh7763rdp_defconfig
new file mode 100644
index 000000000000..83f3fe5db3e5
--- /dev/null
+++ b/arch/sh/configs/sh7763rdp_defconfig
@@ -0,0 +1,1052 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc4
+# Fri Jun  6 12:20:17 2008
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+CONFIG_CPU_SH4A=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+CONFIG_CPU_SUBTYPE_SH7763=y
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_29BIT=y
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+# CONFIG_SH_STORE_QUEUES is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+CONFIG_SH_SH7763RDP=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=28
+CONFIG_SH_PCLK_FREQ=66666666
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+# CONFIG_HEARTBEAT is not set
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttySC2,115200 root=/dev/sda1 rootdelay=10"
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_STNIC is not set
+# CONFIG_SMC91X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=3
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_SH_KGDB is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/sh7785lcr_defconfig b/arch/sh/configs/sh7785lcr_defconfig
new file mode 100644
index 000000000000..ff72697365d1
--- /dev/null
+++ b/arch/sh/configs/sh7785lcr_defconfig
@@ -0,0 +1,1388 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc8
+# Tue Jul 15 21:37:59 2008
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_SYS_SUPPORTS_NUMA=y
+CONFIG_SYS_SUPPORTS_PCI=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_IO_TRAPPED=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+CONFIG_CPU_SH4A=y
+CONFIG_CPU_SHX2=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+CONFIG_CPU_SUBTYPE_SH7785=y
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x08000000
+CONFIG_MEMORY_SIZE=0x08000000
+CONFIG_29BIT=y
+# CONFIG_PMB is not set
+# CONFIG_X2TLB is not set
+CONFIG_VSYSCALL=y
+# CONFIG_NUMA is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=2
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+CONFIG_SH_STORE_QUEUES=y
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_PTEA=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+# CONFIG_SH_HIGHLANDER is not set
+CONFIG_SH_SH7785LCR=y
+CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=28
+CONFIG_SH_PCLK_FREQ=50000000
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_KEXEC=y
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_GUSA=y
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_SH_PCIDMA_NONCOHERENT=y
+CONFIG_PCI_AUTO=y
+CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=0
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_SATA_SIL=y
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_R8169=y
+# CONFIG_R8169_NAPI is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_ALGOPCA=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+CONFIG_I2C_PCA_PLATFORM=y
+# CONFIG_I2C_SH_MOBILE is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_SM501=y
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_SUPERH_MONO is not set
+# CONFIG_LOGO_SUPERH_VGA16 is not set
+# CONFIG_LOGO_SUPERH_CLUT224 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_R8A66597_HCD=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_RS5C372=y
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SH is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_CODEPAGE_932=y
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DEBUG_BOOTMEM is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_4KSTACKS is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_SH_KGDB is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/sh/drivers/dma/dma-g2.c b/arch/sh/drivers/dma/dma-g2.c
index 0caf11bb7e27..af7bb589c2c8 100644
--- a/arch/sh/drivers/dma/dma-g2.c
+++ b/arch/sh/drivers/dma/dma-g2.c
@@ -14,8 +14,8 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <asm/cacheflush.h>
-#include <asm/mach/sysasic.h>
-#include <asm/mach/dma.h>
+#include <mach/sysasic.h>
+#include <mach/dma.h>
 #include <asm/dma.h>
 
 struct g2_channel {
diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c
index 838fad566eaf..391cbe1c2956 100644
--- a/arch/sh/drivers/dma/dma-pvr2.c
+++ b/arch/sh/drivers/dma/dma-pvr2.c
@@ -13,8 +13,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
-#include <asm/mach/sysasic.h>
-#include <asm/mach/dma.h>
+#include <mach/sysasic.h>
+#include <mach/dma.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 71ff3d6f26e2..b2ffe649c7c0 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -14,7 +14,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
-#include <asm/dreamcast/dma.h>
+#include <mach-dreamcast/mach/dma.h>
 #include <asm/dma.h>
 #include <asm/io.h>
 #include "dma-sh.h"
diff --git a/arch/sh/drivers/dma/dma-sh.h b/arch/sh/drivers/dma/dma-sh.h
index 0f591fbc922d..b05af34fc15d 100644
--- a/arch/sh/drivers/dma/dma-sh.h
+++ b/arch/sh/drivers/dma/dma-sh.h
@@ -11,7 +11,7 @@
 #ifndef __DMA_SH_H
 #define __DMA_SH_H
 
-#include <asm/cpu/dma.h>
+#include <cpu/dma.h>
 
 /* Definitions for the SuperH DMAC */
 #define REQ_L   0x00000000
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 0718805774e8..847e90894d1b 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_SH_LANDISK)		+= ops-landisk.o
 obj-$(CONFIG_SH_LBOX_RE2)               += ops-lboxre2.o fixups-lboxre2.o
 obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)   += ops-se7780.o fixups-se7780.o
 obj-$(CONFIG_SH_CAYMAN)                 += ops-cayman.o
+obj-$(CONFIG_SH_SH7785LCR)              += ops-sh7785lcr.o fixups-sh7785lcr.o
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index c44699301eeb..2bf85cf091e1 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -26,7 +26,7 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/mach/pci.h>
+#include <mach/pci.h>
 
 static void __init gapspci_fixup_resources(struct pci_dev *dev)
 {
diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c
new file mode 100644
index 000000000000..4949e601387a
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-sh7785lcr.c
@@ -0,0 +1,46 @@
+/*
+ * arch/sh/drivers/pci/fixups-sh7785lcr.c
+ *
+ * R0P7785LC0011RL PCI fixups
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * Based on arch/sh/drivers/pci/fixups-r7780rp.c
+ * Copyright (C) 2003  Lineo uSolutions, Inc.
+ * Copyright (C) 2004 - 2006  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/pci.h>
+#include "pci-sh4.h"
+
+int pci_fixup_pcic(void)
+{
+        pci_write_reg(0x000043ff, SH4_PCIINTM);
+        pci_write_reg(0x0000380f, SH4_PCIAINTM);
+
+        pci_write_reg(0xfbb00047, SH7780_PCICMD);
+        pci_write_reg(0x00000000, SH7780_PCIIBAR);
+
+        pci_write_reg(0x00011912, SH7780_PCISVID);
+        pci_write_reg(0x08000000, SH7780_PCICSCR0);
+        pci_write_reg(0x0000001b, SH7780_PCICSAR0);
+        pci_write_reg(0xfd000000, SH7780_PCICSCR1);
+        pci_write_reg(0x0000000f, SH7780_PCICSAR1);
+
+        pci_write_reg(0xfd000000, SH7780_PCIMBR0);
+        pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
+
+#ifdef CONFIG_32BIT
+        pci_write_reg(0xc0000000, SH7780_PCIMBR2);
+        pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
+#endif
+
+        /* Set IOBR for windows containing area specified in pci.h */
+        pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
+                      SH7780_PCIIOBR);
+        pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR);
+
+        return 0;
+}
diff --git a/arch/sh/drivers/pci/ops-cayman.c b/arch/sh/drivers/pci/ops-cayman.c
index 980275ffa30b..5ccf9ea3a9de 100644
--- a/arch/sh/drivers/pci/ops-cayman.c
+++ b/arch/sh/drivers/pci/ops-cayman.c
@@ -2,7 +2,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/types.h>
-#include <asm/cpu/irq.h>
+#include <cpu/irq.h>
 #include "pci-sh5.h"
 
 static inline u8 bridge_swizzle(u8 pin, u8 slot)
diff --git a/arch/sh/drivers/pci/ops-dreamcast.c b/arch/sh/drivers/pci/ops-dreamcast.c
index e1284fc69361..f5d2a2aa6f3f 100644
--- a/arch/sh/drivers/pci/ops-dreamcast.c
+++ b/arch/sh/drivers/pci/ops-dreamcast.c
@@ -22,10 +22,11 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/pci.h>
+#include <linux/module.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/mach/pci.h>
+#include <mach/pci.h>
 
 static struct resource gapspci_io_resource = {
         .name   = "GAPSPCI IO",
@@ -48,6 +49,7 @@ struct pci_channel board_pci_channels[] = {
           &gapspci_mem_resource, 0, 1 },
         { 0, }
 };
+EXPORT_SYMBOL(board_pci_channels);
 
 /*
  * The !gapspci_config_access case really shouldn't happen, ever, unless
diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c
index bbdb48c124a2..3145c62484d6 100644
--- a/arch/sh/drivers/pci/ops-se7780.c
+++ b/arch/sh/drivers/pci/ops-se7780.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/pci.h>
-#include <asm/se7780.h>
+#include <mach-se/mach/se7780.h>
 #include <asm/io.h>
 #include "pci-sh4.h"
 
diff --git a/arch/sh/drivers/pci/ops-sh7785lcr.c b/arch/sh/drivers/pci/ops-sh7785lcr.c
new file mode 100644
index 000000000000..b3bd68702059
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-sh7785lcr.c
@@ -0,0 +1,66 @@
+/*
+ * Author:  Ian DaSilva (idasilva@mvista.com)
+ *
+ * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * PCI initialization for the Renesas R0P7785LC0011RL board
+ * Based on arch/sh/drivers/pci/ops-r7780rp.c
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include "pci-sh4.h"
+
+static char irq_tab[] __initdata = {
+        65, 66, 67, 68,
+};
+
+int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
+{
+        return irq_tab[slot];
+}
+
+static struct resource sh7785_io_resource = {
+        .name   = "SH7785_IO",
+        .start  = SH7780_PCI_IO_BASE,
+        .end    = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource sh7785_mem_resource = {
+        .name   = "SH7785_mem",
+        .start  = SH7780_PCI_MEMORY_BASE,
+        .end    = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM
+};
+
+struct pci_channel board_pci_channels[] = {
+        { &sh4_pci_ops, &sh7785_io_resource, &sh7785_mem_resource, 0, 0xff },
+        { NULL, NULL, NULL, 0, 0 },
+};
+EXPORT_SYMBOL(board_pci_channels);
+
+static struct sh4_pci_address_map sh7785_pci_map = {
+        .window0        = {
+                .base   = SH7780_CS2_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+
+        .window1        = {
+                .base   = SH7780_CS3_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+
+        .flags  = SH4_PCIC_NO_RESET,
+};
+
+int __init pcibios_init_platform(void)
+{
+        return sh7780_pcic_init(&sh7785_pci_map);
+}
diff --git a/arch/sh/drivers/pci/pci-auto.c b/arch/sh/drivers/pci/pci-auto.c
index ea404704ace8..cf48b12ee58c 100644
--- a/arch/sh/drivers/pci/pci-auto.c
+++ b/arch/sh/drivers/pci/pci-auto.c
@@ -78,7 +78,7 @@ static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
 }
 
 #define EARLY_PCI_OP(rw, size, type)                                    \
-int early_##rw##_config_##size(struct pci_channel *hose,                \
+static int early_##rw##_config_##size(struct pci_channel *hose,         \
         int top_bus, int bus, int devfn, int offset, type value)        \
 {                                                                       \
         return pci_##rw##_config_##size(                                \
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
index a00a4df8c02d..7a97438762c8 100644
--- a/arch/sh/drivers/pci/pci-sh5.c
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -19,7 +19,7 @@
 #include <linux/delay.h>
 #include <linux/types.h>
 #include <linux/irq.h>
-#include <asm/cpu/irq.h>
+#include <cpu/irq.h>
 #include <asm/pci.h>
 #include <asm/io.h>
 #include "pci-sh5.h"
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index f57095a2617c..d3839e609aac 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -135,7 +135,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
  *  If we set up a device for bus mastering, we need to check and set
  *  the latency timer as it may not be properly set.
  */
-unsigned int pcibios_max_latency = 255;
+static unsigned int pcibios_max_latency = 255;
 
 void pcibios_set_master(struct pci_dev *dev)
 {
diff --git a/arch/sh/include/asm/.gitignore b/arch/sh/include/asm/.gitignore
new file mode 100644
index 000000000000..378db779fb6c
--- /dev/null
+++ b/arch/sh/include/asm/.gitignore
@@ -0,0 +1 @@
+machtypes.h
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
new file mode 100644
index 000000000000..43910cdf78a5
--- /dev/null
+++ b/arch/sh/include/asm/Kbuild
@@ -0,0 +1,8 @@
+include include/asm-generic/Kbuild.asm
+
+header-y += cpu-features.h
+
+unifdef-y += unistd_32.h
+unifdef-y += unistd_64.h
+unifdef-y += posix_types_32.h
+unifdef-y += posix_types_64.h
diff --git a/arch/sh/include/asm/adc.h b/arch/sh/include/asm/adc.h
new file mode 100644
index 000000000000..48824c1fab80
--- /dev/null
+++ b/arch/sh/include/asm/adc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_ADC_H
+#define __ASM_ADC_H
+#ifdef __KERNEL__
+/*
+ * Copyright (C) 2004  Andriy Skulysh
+ */
+
+#include <cpu/adc.h>
+
+int adc_single(unsigned int channel);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_ADC_H */
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
new file mode 100644
index 000000000000..2702d81bfc0d
--- /dev/null
+++ b/arch/sh/include/asm/addrspace.h
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Kaz Kojima
+ *
+ * Defitions for the address spaces of the SH CPUs.
+ */
+#ifndef __ASM_SH_ADDRSPACE_H
+#define __ASM_SH_ADDRSPACE_H
+
+#ifdef __KERNEL__
+
+#include <cpu/addrspace.h>
+
+/* If this CPU supports segmentation, hook up the helpers */
+#ifdef P1SEG
+
+/*
+   [ P0/U0 (virtual) ]          0x00000000     <------ User space
+   [ P1 (fixed)   cached ]      0x80000000     <------ Kernel space
+   [ P2 (fixed)  non-cachable]  0xA0000000     <------ Physical access
+   [ P3 (virtual) cached]       0xC0000000     <------ vmalloced area
+   [ P4 control   ]             0xE0000000
+ */
+
+/* Returns the privileged segment base of a given address  */
+#define PXSEG(a)        (((unsigned long)(a)) & 0xe0000000)
+
+/* Returns the physical address of a PnSEG (n=1,2) address   */
+#define PHYSADDR(a)     (((unsigned long)(a)) & 0x1fffffff)
+
+#ifdef CONFIG_29BIT
+/*
+ * Map an address to a certain privileged segment
+ */
+#define P1SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
+#define P2SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
+#define P3SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
+#define P4SEGADDR(a)    \
+        ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
+#endif /* 29BIT */
+#endif /* P1SEG */
+
+/* Check if an address can be reached in 29 bits */
+#define IS_29BIT(a)     (((unsigned long)(a)) < 0x20000000)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_ADDRSPACE_H */
diff --git a/arch/sh/include/asm/atomic-grb.h b/arch/sh/include/asm/atomic-grb.h
new file mode 100644
index 000000000000..4c5b7dbfcedb
--- /dev/null
+++ b/arch/sh/include/asm/atomic-grb.h
@@ -0,0 +1,169 @@
+#ifndef __ASM_SH_ATOMIC_GRB_H
+#define __ASM_SH_ATOMIC_GRB_H
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   add     %2,   %0      \n\t" /* add */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory" , "r0", "r1");
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov     r15,  r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   sub     %2,   %0      \n\t" /* sub */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory" , "r0", "r1");
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   add     %2,   %0      \n\t" /* add */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory" , "r0", "r1");
+
+        return tmp;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   sub     %2,   %0      \n\t" /* sub */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (i)
+                : "memory", "r0", "r1");
+
+        return tmp;
+}
+
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+{
+        int tmp;
+        unsigned int _mask = ~mask;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   and     %2,   %0      \n\t" /* add */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (_mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+        int tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   or      %2,   %0      \n\t" /* or */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (v)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+        int ret;
+
+        __asm__ __volatile__ (
+                "   .align 2            \n\t"
+                "   mova     1f,  r0    \n\t"
+                "   nop                 \n\t"
+                "   mov     r15,  r1    \n\t"
+                "   mov    #-8,  r15    \n\t"
+                "   mov.l   @%1,  %0    \n\t"
+                "   cmp/eq   %2,  %0    \n\t"
+                "   bf       1f         \n\t"
+                "   mov.l    %3, @%1    \n\t"
+                "1: mov      r1,  r15   \n\t"
+                : "=&r" (ret)
+                : "r" (v), "r" (old), "r" (new)
+                : "memory" , "r0", "r1" , "t");
+
+        return ret;
+}
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int ret;
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "   .align 2            \n\t"
+                "   mova    1f,   r0    \n\t"
+                "   nop                 \n\t"
+                "   mov    r15,   r1    \n\t"
+                "   mov    #-12,  r15   \n\t"
+                "   mov.l  @%2,   %1    \n\t"
+                "   mov     %1,   %0    \n\t"
+                "   cmp/eq  %4,   %0    \n\t"
+                "   bt/s    1f          \n\t"
+                "    add    %3,   %1    \n\t"
+                "   mov.l   %1,  @%2    \n\t"
+                "1: mov     r1,   r15   \n\t"
+                : "=&r" (ret), "=&r" (tmp)
+                : "r" (v), "r" (a), "r" (u)
+                : "memory" , "r0", "r1" , "t");
+
+        return ret != u;
+}
+#endif /* __ASM_SH_ATOMIC_GRB_H */
diff --git a/arch/sh/include/asm/atomic-irq.h b/arch/sh/include/asm/atomic-irq.h
new file mode 100644
index 000000000000..74f7943cff6f
--- /dev/null
+++ b/arch/sh/include/asm/atomic-irq.h
@@ -0,0 +1,71 @@
+#ifndef __ASM_SH_ATOMIC_IRQ_H
+#define __ASM_SH_ATOMIC_IRQ_H
+
+/*
+ * To get proper branch prediction for the main line, we must branch
+ * forward to code at the end of this object's .text section, then
+ * branch back to restart the operation.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v += i;
+        local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v -= i;
+        local_irq_restore(flags);
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        unsigned long temp, flags;
+
+        local_irq_save(flags);
+        temp = *(long *)v;
+        temp += i;
+        *(long *)v = temp;
+        local_irq_restore(flags);
+
+        return temp;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        unsigned long temp, flags;
+
+        local_irq_save(flags);
+        temp = *(long *)v;
+        temp -= i;
+        *(long *)v = temp;
+        local_irq_restore(flags);
+
+        return temp;
+}
+
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v &= ~mask;
+        local_irq_restore(flags);
+}
+
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *(long *)v |= mask;
+        local_irq_restore(flags);
+}
+
+#endif /* __ASM_SH_ATOMIC_IRQ_H */
diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic-llsc.h
new file mode 100644
index 000000000000..4b00b78e3f4f
--- /dev/null
+++ b/arch/sh/include/asm/atomic-llsc.h
@@ -0,0 +1,107 @@
+#ifndef __ASM_SH_ATOMIC_LLSC_H
+#define __ASM_SH_ATOMIC_LLSC_H
+
+/*
+ * To get proper branch prediction for the main line, we must branch
+ * forward to code at the end of this object's .text section, then
+ * branch back to restart the operation.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_add    \n"
+"       add     %1, %0                          \n"
+"       movco.l %0, @%2                         \n"
+"       bf      1b                              \n"
+        : "=&z" (tmp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_sub    \n"
+"       sub     %1, %0                          \n"
+"       movco.l %0, @%2                         \n"
+"       bf      1b                              \n"
+        : "=&z" (tmp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+}
+
+/*
+ * SH-4A note:
+ *
+ * We basically get atomic_xxx_return() for free compared with
+ * atomic_xxx(). movli.l/movco.l require r0 due to the instruction
+ * encoding, so the retval is automatically set without having to
+ * do any special work.
+ */
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        unsigned long temp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_add_return     \n"
+"       add     %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+"       synco                                           \n"
+        : "=&z" (temp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+
+        return temp;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        unsigned long temp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_sub_return     \n"
+"       sub     %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+"       synco                                           \n"
+        : "=&z" (temp)
+        : "r" (i), "r" (&v->counter)
+        : "t");
+
+        return temp;
+}
+
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_clear_mask     \n"
+"       and     %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+        : "=&z" (tmp)
+        : "r" (~mask), "r" (&v->counter)
+        : "t");
+}
+
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+"1:     movli.l @%2, %0         ! atomic_set_mask       \n"
+"       or      %1, %0                                  \n"
+"       movco.l %0, @%2                                 \n"
+"       bf      1b                                      \n"
+        : "=&z" (tmp)
+        : "r" (mask), "r" (&v->counter)
+        : "t");
+}
+
+#endif /* __ASM_SH_ATOMIC_LLSC_H */
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
new file mode 100644
index 000000000000..c043ef003028
--- /dev/null
+++ b/arch/sh/include/asm/atomic.h
@@ -0,0 +1,89 @@
+#ifndef __ASM_SH_ATOMIC_H
+#define __ASM_SH_ATOMIC_H
+
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ *
+ */
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i)  ( (atomic_t) { (i) } )
+
+#define atomic_read(v)          ((v)->counter)
+#define atomic_set(v,i)         ((v)->counter = (i))
+
+#include <linux/compiler.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_GUSA_RB)
+#include <asm/atomic-grb.h>
+#elif defined(CONFIG_CPU_SH4A)
+#include <asm/atomic-llsc.h>
+#else
+#include <asm/atomic-irq.h>
+#endif
+
+#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
+
+#define atomic_dec_return(v) atomic_sub_return(1,(v))
+#define atomic_inc_return(v) atomic_add_return(1,(v))
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
+#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
+
+#define atomic_inc(v) atomic_add(1,(v))
+#define atomic_dec(v) atomic_sub(1,(v))
+
+#ifndef CONFIG_GUSA_RB
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+        int ret;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        ret = v->counter;
+        if (likely(ret == old))
+                v->counter = new;
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int ret;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        ret = v->counter;
+        if (ret != u)
+                v->counter += a;
+        local_irq_restore(flags);
+
+        return ret != u;
+}
+#endif
+
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+/* Atomic operations are already serializing on SH */
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+
+#include <asm-generic/atomic.h>
+#endif /* __ASM_SH_ATOMIC_H */
diff --git a/arch/sh/include/asm/auxvec.h b/arch/sh/include/asm/auxvec.h
new file mode 100644
index 000000000000..483effd65e00
--- /dev/null
+++ b/arch/sh/include/asm/auxvec.h
@@ -0,0 +1,36 @@
+#ifndef __ASM_SH_AUXVEC_H
+#define __ASM_SH_AUXVEC_H
+
+/*
+ * Architecture-neutral AT_ values in 0-17, leave some room
+ * for more of them.
+ */
+
+/*
+ * This entry gives some information about the FPU initialization
+ * performed by the kernel.
+ */
+#define AT_FPUCW                18      /* Used FPU control word.  */
+
+#if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__)
+/*
+ * Only define this in the vsyscall case, the entry point to
+ * the vsyscall page gets placed here. The kernel will attempt
+ * to build a gate VMA we don't care about otherwise..
+ */
+#define AT_SYSINFO_EHDR         33
+#endif
+
+/*
+ * More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
+ * value is -1, then the cache doesn't exist.  Otherwise:
+ *
+ *    bit 0-3:    Cache set-associativity; 0 means fully associative.
+ *    bit 4-7:    Log2 of cacheline size.
+ *    bit 8-31:   Size of the entire cache >> 8.
+ */
+#define AT_L1I_CACHESHAPE       34
+#define AT_L1D_CACHESHAPE       35
+#define AT_L2_CACHESHAPE        36
+
+#endif /* __ASM_SH_AUXVEC_H */
diff --git a/arch/sh/include/asm/bitops-grb.h b/arch/sh/include/asm/bitops-grb.h
new file mode 100644
index 000000000000..a5907b94395b
--- /dev/null
+++ b/arch/sh/include/asm/bitops-grb.h
@@ -0,0 +1,169 @@
+#ifndef __ASM_SH_BITOPS_GRB_H
+#define __ASM_SH_BITOPS_GRB_H
+
+static inline void set_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   or      %2,   %0      \n\t" /* or */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline void clear_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = ~(1 << (nr & 0x1f));
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   and     %2,   %0      \n\t" /* and */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline void change_bit(int nr, volatile void * addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   xor     %2,   %0      \n\t" /* xor */
+                "   mov.l   %0,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1");
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov   #-14,   r15     \n\t" /* LOGIN: r15 = size */
+                "   mov.l  @%2,   %0      \n\t" /* load old value */
+                "   mov     %0,   %1      \n\t"
+                "   tst     %1,   %3      \n\t" /* T = ((*a & mask) == 0) */
+                "   mov    #-1,   %1      \n\t" /* retvat = -1 */
+                "   negc    %1,   %1      \n\t" /* retval = (mask & *a) != 0 */
+                "   or      %3,   %0      \n\t"
+                "   mov.l   %0,  @%2      \n\t" /* store new value */
+                "1: mov     r1,  r15      \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "=&r" (retval),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1" ,"t");
+
+        return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+        int     mask, retval,not_mask;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        not_mask = ~mask;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov   #-14,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%2,   %0      \n\t" /* load old value */
+                "   mov     %0,   %1      \n\t" /* %1 = *a */
+                "   tst     %1,   %3      \n\t" /* T = ((*a & mask) == 0) */
+                "   mov    #-1,   %1      \n\t" /* retvat = -1 */
+                "   negc    %1,   %1      \n\t" /* retval = (mask & *a) != 0 */
+                "   and     %4,   %0      \n\t"
+                "   mov.l   %0,  @%2      \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "=&r" (retval),
+                  "+r"  (a)
+                : "r"   (mask),
+                  "r"   (not_mask)
+                : "memory" , "r0", "r1", "t");
+
+        return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long tmp;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov   #-14,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%2,   %0      \n\t" /* load old value */
+                "   mov     %0,   %1      \n\t" /* %1 = *a */
+                "   tst     %1,   %3      \n\t" /* T = ((*a & mask) == 0) */
+                "   mov    #-1,   %1      \n\t" /* retvat = -1 */
+                "   negc    %1,   %1      \n\t" /* retval = (mask & *a) != 0 */
+                "   xor     %3,   %0      \n\t"
+                "   mov.l   %0,  @%2      \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (tmp),
+                  "=&r" (retval),
+                  "+r"  (a)
+                : "r"   (mask)
+                : "memory" , "r0", "r1", "t");
+
+        return retval;
+}
+#endif /* __ASM_SH_BITOPS_GRB_H */
diff --git a/arch/sh/include/asm/bitops-irq.h b/arch/sh/include/asm/bitops-irq.h
new file mode 100644
index 000000000000..653a12750584
--- /dev/null
+++ b/arch/sh/include/asm/bitops-irq.h
@@ -0,0 +1,91 @@
+#ifndef __ASM_SH_BITOPS_IRQ_H
+#define __ASM_SH_BITOPS_IRQ_H
+
+static inline void set_bit(int nr, volatile void *addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a |= mask;
+        local_irq_restore(flags);
+}
+
+static inline void clear_bit(int nr, volatile void *addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a &= ~mask;
+        local_irq_restore(flags);
+}
+
+static inline void change_bit(int nr, volatile void *addr)
+{
+        int     mask;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a ^= mask;
+        local_irq_restore(flags);
+}
+
+static inline int test_and_set_bit(int nr, volatile void *addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a |= mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void *addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a &= ~mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void *addr)
+{
+        int     mask, retval;
+        volatile unsigned int *a = addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a ^= mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+#endif /* __ASM_SH_BITOPS_IRQ_H */
diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h
new file mode 100644
index 000000000000..d7d382f63ee5
--- /dev/null
+++ b/arch/sh/include/asm/bitops.h
@@ -0,0 +1,103 @@
+#ifndef __ASM_SH_BITOPS_H
+#define __ASM_SH_BITOPS_H
+
+#ifdef __KERNEL__
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <asm/system.h>
+/* For __swab32 */
+#include <asm/byteorder.h>
+
+#ifdef CONFIG_GUSA_RB
+#include <asm/bitops-grb.h>
+#else
+#include <asm/bitops-irq.h>
+#endif
+
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()      barrier()
+#define smp_mb__after_clear_bit()       barrier()
+
+#include <asm-generic/bitops/non-atomic.h>
+
+#ifdef CONFIG_SUPERH32
+static inline unsigned long ffz(unsigned long word)
+{
+        unsigned long result;
+
+        __asm__("1:\n\t"
+                "shlr   %1\n\t"
+                "bt/s   1b\n\t"
+                " add   #1, %0"
+                : "=r" (result), "=r" (word)
+                : "0" (~0L), "1" (word)
+                : "t");
+        return result;
+}
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+        unsigned long result;
+
+        __asm__("1:\n\t"
+                "shlr   %1\n\t"
+                "bf/s   1b\n\t"
+                " add   #1, %0"
+                : "=r" (result), "=r" (word)
+                : "0" (~0L), "1" (word)
+                : "t");
+        return result;
+}
+#else
+static inline unsigned long ffz(unsigned long word)
+{
+        unsigned long result, __d2, __d3;
+
+        __asm__("gettr  tr0, %2\n\t"
+                "pta    $+32, tr0\n\t"
+                "andi   %1, 1, %3\n\t"
+                "beq    %3, r63, tr0\n\t"
+                "pta    $+4, tr0\n"
+                "0:\n\t"
+                "shlri.l        %1, 1, %1\n\t"
+                "addi   %0, 1, %0\n\t"
+                "andi   %1, 1, %3\n\t"
+                "beqi   %3, 1, tr0\n"
+                "1:\n\t"
+                "ptabs  %2, tr0\n\t"
+                : "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
+                : "0" (0L), "1" (word));
+
+        return result;
+}
+
+#include <asm-generic/bitops/__ffs.h>
+#endif
+
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_BITOPS_H */
diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h
new file mode 100644
index 000000000000..c01718040166
--- /dev/null
+++ b/arch/sh/include/asm/bug.h
@@ -0,0 +1,79 @@
+#ifndef __ASM_SH_BUG_H
+#define __ASM_SH_BUG_H
+
+#define TRAPA_BUG_OPCODE        0xc33e  /* trapa #0x3e */
+
+#ifdef CONFIG_GENERIC_BUG
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_WARN_ON
+
+/**
+ * _EMIT_BUG_ENTRY
+ * %1 - __FILE__
+ * %2 - __LINE__
+ * %3 - trap type
+ * %4 - sizeof(struct bug_entry)
+ *
+ * The trapa opcode itself sits in %0.
+ * The %O notation is used to avoid # generation.
+ *
+ * The offending file and line are encoded in the __bug_table section.
+ */
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#define _EMIT_BUG_ENTRY                         \
+        "\t.pushsection __bug_table,\"a\"\n"    \
+        "2:\t.long 1b, %O1\n"                   \
+        "\t.short %O2, %O3\n"                   \
+        "\t.org 2b+%O4\n"                       \
+        "\t.popsection\n"
+#else
+#define _EMIT_BUG_ENTRY                         \
+        "\t.pushsection __bug_table,\"a\"\n"    \
+        "2:\t.long 1b\n"                        \
+        "\t.short %O3\n"                        \
+        "\t.org 2b+%O4\n"                       \
+        "\t.popsection\n"
+#endif
+
+#define BUG()                                           \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "1:\t.short %O0\n"                      \
+                _EMIT_BUG_ENTRY                         \
+                 :                                      \
+                 : "n" (TRAPA_BUG_OPCODE),              \
+                   "i" (__FILE__),                      \
+                   "i" (__LINE__), "i" (0),             \
+                   "i" (sizeof(struct bug_entry)));     \
+} while (0)
+
+#define __WARN()                                        \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "1:\t.short %O0\n"                      \
+                 _EMIT_BUG_ENTRY                        \
+                 :                                      \
+                 : "n" (TRAPA_BUG_OPCODE),              \
+                   "i" (__FILE__),                      \
+                   "i" (__LINE__),                      \
+                   "i" (BUGFLAG_WARNING),               \
+                   "i" (sizeof(struct bug_entry)));     \
+} while (0)
+
+#define WARN_ON(x) ({                                           \
+        int __ret_warn_on = !!(x);                              \
+        if (__builtin_constant_p(__ret_warn_on)) {              \
+                if (__ret_warn_on)                              \
+                        __WARN();                               \
+        } else {                                                \
+                if (unlikely(__ret_warn_on))                    \
+                        __WARN();                               \
+        }                                                       \
+        unlikely(__ret_warn_on);                                \
+})
+
+#endif /* CONFIG_GENERIC_BUG */
+
+#include <asm-generic/bug.h>
+
+#endif /* __ASM_SH_BUG_H */
diff --git a/arch/sh/include/asm/bugs.h b/arch/sh/include/asm/bugs.h
new file mode 100644
index 000000000000..121b2ecddfc3
--- /dev/null
+++ b/arch/sh/include/asm/bugs.h
@@ -0,0 +1,73 @@
+#ifndef __ASM_SH_BUGS_H
+#define __ASM_SH_BUGS_H
+
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ *      void check_bugs(void);
+ */
+
+/*
+ * I don't know of any Super-H bugs yet.
+ */
+
+#include <asm/processor.h>
+
+static void __init check_bugs(void)
+{
+        extern unsigned long loops_per_jiffy;
+        char *p = &init_utsname()->machine[2]; /* "sh" */
+
+        current_cpu_data.loops_per_jiffy = loops_per_jiffy;
+
+        switch (current_cpu_data.type) {
+        case CPU_SH7619:
+                *p++ = '2';
+                break;
+        case CPU_SH7203 ... CPU_MXG:
+                *p++ = '2';
+                *p++ = 'a';
+                break;
+        case CPU_SH7705 ... CPU_SH7729:
+                *p++ = '3';
+                break;
+        case CPU_SH7750 ... CPU_SH4_501:
+                *p++ = '4';
+                break;
+        case CPU_SH7763 ... CPU_SHX3:
+                *p++ = '4';
+                *p++ = 'a';
+                break;
+        case CPU_SH7343 ... CPU_SH7366:
+                *p++ = '4';
+                *p++ = 'a';
+                *p++ = 'l';
+                *p++ = '-';
+                *p++ = 'd';
+                *p++ = 's';
+                *p++ = 'p';
+                break;
+        case CPU_SH5_101 ... CPU_SH5_103:
+                *p++ = '6';
+                *p++ = '4';
+                break;
+        case CPU_SH_NONE:
+                /*
+                 * Specifically use CPU_SH_NONE rather than default:,
+                 * so we're able to have the compiler whine about
+                 * unhandled enumerations.
+                 */
+                break;
+        }
+
+        printk("CPU: %s\n", get_cpu_subtype(&current_cpu_data));
+
+#ifndef __LITTLE_ENDIAN__
+        /* 'eb' means 'Endian Big' */
+        *p++ = 'e';
+        *p++ = 'b';
+#endif
+        *p = '\0';
+}
+#endif /* __ASM_SH_BUGS_H */
diff --git a/arch/sh/include/asm/byteorder.h b/arch/sh/include/asm/byteorder.h
new file mode 100644
index 000000000000..4c13e6117563
--- /dev/null
+++ b/arch/sh/include/asm/byteorder.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_SH_BYTEORDER_H
+#define __ASM_SH_BYTEORDER_H
+
+/*
+ * Copyright (C) 1999  Niibe Yutaka
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ */
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+        __asm__(
+#ifdef __SH5__
+                "byterev        %0, %0\n\t"
+                "shari          %0, 32, %0"
+#else
+                "swap.b         %0, %0\n\t"
+                "swap.w         %0, %0\n\t"
+                "swap.b         %0, %0"
+#endif
+                : "=r" (x)
+                : "0" (x));
+
+        return x;
+}
+
+static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+        __asm__(
+#ifdef __SH5__
+                "byterev        %0, %0\n\t"
+                "shari          %0, 32, %0"
+#else
+                "swap.b         %0, %0"
+#endif
+                : "=r" (x)
+                :  "0" (x));
+
+        return x;
+}
+
+static inline __u64 ___arch__swab64(__u64 val)
+{
+        union {
+                struct { __u32 a,b; } s;
+                __u64 u;
+        } v, w;
+        v.u = val;
+        w.s.b = ___arch__swab32(v.s.a);
+        w.s.a = ___arch__swab32(v.s.b);
+        return w.u;
+}
+
+#define __arch__swab64(x) ___arch__swab64(x)
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif /* __ASM_SH_BYTEORDER_H */
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
new file mode 100644
index 000000000000..02df18ea9608
--- /dev/null
+++ b/arch/sh/include/asm/cache.h
@@ -0,0 +1,51 @@
+/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
+ *
+ * include/asm-sh/cache.h
+ *
+ * Copyright 1999 (C) Niibe Yutaka
+ * Copyright 2002, 2003 (C) Paul Mundt
+ */
+#ifndef __ASM_SH_CACHE_H
+#define __ASM_SH_CACHE_H
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <cpu/cache.h>
+
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+#ifndef __ASSEMBLY__
+struct cache_info {
+        unsigned int ways;              /* Number of cache ways */
+        unsigned int sets;              /* Number of cache sets */
+        unsigned int linesz;            /* Cache line size (bytes) */
+
+        unsigned int way_size;          /* sets * line size */
+
+        /*
+         * way_incr is the address offset for accessing the next way
+         * in memory mapped cache array ops.
+         */
+        unsigned int way_incr;
+        unsigned int entry_shift;
+        unsigned int entry_mask;
+
+        /*
+         * Compute a mask which selects the address bits which overlap between
+         * 1. those used to select the cache set during indexing
+         * 2. those in the physical page number.
+         */
+        unsigned int alias_mask;
+
+        unsigned int n_aliases;         /* Number of aliases */
+
+        unsigned long flags;
+};
+
+int __init detect_cpu_and_cache_system(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_CACHE_H */
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
new file mode 100644
index 000000000000..09acbc32d6c7
--- /dev/null
+++ b/arch/sh/include/asm/cacheflush.h
@@ -0,0 +1,81 @@
+#ifndef __ASM_SH_CACHEFLUSH_H
+#define __ASM_SH_CACHEFLUSH_H
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_CACHE_OFF
+/*
+ * Nothing to do when the cache is disabled, initial flush and explicit
+ * disabling is handled at CPU init time.
+ *
+ * See arch/sh/kernel/cpu/init.c:cache_init().
+ */
+#define p3_cache_init()                         do { } while (0)
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_dcache_page(page)                 do { } while (0)
+#define flush_icache_range(start, end)          do { } while (0)
+#define flush_icache_page(vma,pg)               do { } while (0)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+#define flush_cache_sigtramp(vaddr)             do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define __flush_wback_region(start, size)       do { (void)(start); } while (0)
+#define __flush_purge_region(start, size)       do { (void)(start); } while (0)
+#define __flush_invalidate_region(start, size)  do { (void)(start); } while (0)
+#else
+#include <cpu/cacheflush.h>
+
+/*
+ * Consistent DMA requires that the __flush_xxx() primitives must be set
+ * for any of the enabled non-coherent caches (most of the UP CPUs),
+ * regardless of PIPT or VIPT cache configurations.
+ */
+
+/* Flush (write-back only) a region (smaller than a page) */
+extern void __flush_wback_region(void *start, int size);
+/* Flush (write-back & invalidate) a region (smaller than a page) */
+extern void __flush_purge_region(void *start, int size);
+/* Flush (invalidate only) a region (smaller than a page) */
+extern void __flush_invalidate_region(void *start, int size);
+#endif
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+        flush_dcache_page(page);
+}
+
+#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
+extern void copy_to_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+
+extern void copy_from_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+#else
+#define copy_to_user_page(vma, page, vaddr, dst, src, len)      \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+                flush_icache_user_range(vma, page, vaddr, len); \
+        } while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len)    \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+        } while (0)
+#endif
+
+#define flush_cache_vmap(start, end)            flush_cache_all()
+#define flush_cache_vunmap(start, end)          flush_cache_all()
+
+#define HAVE_ARCH_UNMAPPED_AREA
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/checksum.h b/arch/sh/include/asm/checksum.h
new file mode 100644
index 000000000000..67496ab0ef04
--- /dev/null
+++ b/arch/sh/include/asm/checksum.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_SUPERH32
+# include "checksum_32.h"
+#else
+# include "checksum_64.h"
+#endif
diff --git a/arch/sh/include/asm/checksum_32.h b/arch/sh/include/asm/checksum_32.h
new file mode 100644
index 000000000000..14b7ac2f0a07
--- /dev/null
+++ b/arch/sh/include/asm/checksum_32.h
@@ -0,0 +1,215 @@
+#ifndef __ASM_SH_CHECKSUM_H
+#define __ASM_SH_CHECKSUM_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka
+ */
+
+#include <linux/in6.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ * the same as csum_partial, but copies from src while it
+ * checksums, and handles user-space pointer exceptions correctly, when needed.
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst,
+                                            int len, __wsum sum,
+                                            int *src_err_ptr, int *dst_err_ptr);
+
+/*
+ *      Note: when you get a NULL pointer exception here this means someone
+ *      passed in an incorrect kernel address to one of these functions.
+ *
+ *      If you use these functions directly please don't forget the
+ *      access_ok().
+ */
+static inline
+__wsum csum_partial_copy_nocheck(const void *src, void *dst,
+                                 int len, __wsum sum)
+{
+        return csum_partial_copy_generic(src, dst, len, sum, NULL, NULL);
+}
+
+static inline
+__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
+                                   int len, __wsum sum, int *err_ptr)
+{
+        return csum_partial_copy_generic((__force const void *)src, dst,
+                                        len, sum, err_ptr, NULL);
+}
+
+/*
+ *      Fold a partial checksum
+ */
+
+static inline __sum16 csum_fold(__wsum sum)
+{
+        unsigned int __dummy;
+        __asm__("swap.w %0, %1\n\t"
+                "extu.w %0, %0\n\t"
+                "extu.w %1, %1\n\t"
+                "add    %1, %0\n\t"
+                "swap.w %0, %1\n\t"
+                "add    %1, %0\n\t"
+                "not    %0, %0\n\t"
+                : "=r" (sum), "=&r" (__dummy)
+                : "0" (sum)
+                : "t");
+        return (__force __sum16)sum;
+}
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ *
+ *      i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted
+ *      for linux by * Arnt Gulbrandsen.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+        unsigned int sum, __dummy0, __dummy1;
+
+        __asm__ __volatile__(
+                "mov.l  @%1+, %0\n\t"
+                "mov.l  @%1+, %3\n\t"
+                "add    #-2, %2\n\t"
+                "clrt\n\t"
+                "1:\t"
+                "addc   %3, %0\n\t"
+                "movt   %4\n\t"
+                "mov.l  @%1+, %3\n\t"
+                "dt     %2\n\t"
+                "bf/s   1b\n\t"
+                " cmp/eq #1, %4\n\t"
+                "addc   %3, %0\n\t"
+                "addc   %2, %0"     /* Here %2 is 0, add carry-bit */
+        /* Since the input registers which are loaded with iph and ihl
+           are modified, we must also specify them as outputs, or gcc
+           will assume they contain their original values. */
+        : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
+        : "1" (iph), "2" (ihl)
+        : "t", "memory");
+
+        return  csum_fold(sum);
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        __wsum sum)
+{
+#ifdef __LITTLE_ENDIAN__
+        unsigned long len_proto = (proto + len) << 8;
+#else
+        unsigned long len_proto = proto + len;
+#endif
+        __asm__("clrt\n\t"
+                "addc   %0, %1\n\t"
+                "addc   %2, %1\n\t"
+                "addc   %3, %1\n\t"
+                "movt   %0\n\t"
+                "add    %1, %0"
+                : "=r" (sum), "=r" (len_proto)
+                : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum)
+                : "t");
+
+        return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+    return csum_fold(csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+                                      const struct in6_addr *daddr,
+                                      __u32 len, unsigned short proto,
+                                      __wsum sum)
+{
+        unsigned int __dummy;
+        __asm__("clrt\n\t"
+                "mov.l  @(0,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(4,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(8,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(12,%2), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(0,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(4,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(8,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "mov.l  @(12,%3), %1\n\t"
+                "addc   %1, %0\n\t"
+                "addc   %4, %0\n\t"
+                "addc   %5, %0\n\t"
+                "movt   %1\n\t"
+                "add    %1, %0\n"
+                : "=r" (sum), "=&r" (__dummy)
+                : "r" (saddr), "r" (daddr),
+                  "r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
+                : "t");
+
+        return csum_fold(sum);
+}
+
+/*
+ *      Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+static inline __wsum csum_and_copy_to_user(const void *src,
+                                           void __user *dst,
+                                           int len, __wsum sum,
+                                           int *err_ptr)
+{
+        if (access_ok(VERIFY_WRITE, dst, len))
+                return csum_partial_copy_generic((__force const void *)src,
+                                                dst, len, sum, NULL, err_ptr);
+
+        if (len)
+                *err_ptr = -EFAULT;
+
+        return (__force __wsum)-1; /* invalid checksum */
+}
+#endif /* __ASM_SH_CHECKSUM_H */
diff --git a/arch/sh/include/asm/checksum_64.h b/arch/sh/include/asm/checksum_64.h
new file mode 100644
index 000000000000..9c62a031a8f5
--- /dev/null
+++ b/arch/sh/include/asm/checksum_64.h
@@ -0,0 +1,78 @@
+#ifndef __ASM_SH_CHECKSUM_64_H
+#define __ASM_SH_CHECKSUM_64_H
+
+/*
+ * include/asm-sh/checksum_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ *      Note: when you get a NULL pointer exception here this means someone
+ *      passed in an incorrect kernel address to one of these functions.
+ *
+ *      If you use these functions directly please don't forget the
+ *      access_ok().
+ */
+
+
+__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len,
+                                       __wsum sum);
+
+__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
+                                         int len, __wsum sum, int *err_ptr);
+
+static inline __sum16 csum_fold(__wsum csum)
+{
+        u32 sum = (__force u32)csum;
+        sum = (sum & 0xffff) + (sum >> 16);
+        sum = (sum & 0xffff) + (sum >> 16);
+        return (__force __sum16)~sum;
+}
+
+__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+
+__wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                 unsigned short len, unsigned short proto,
+                                 __wsum sum);
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#endif /* __ASM_SH_CHECKSUM_64_H */
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
new file mode 100644
index 000000000000..720dfab7b15e
--- /dev/null
+++ b/arch/sh/include/asm/clock.h
@@ -0,0 +1,97 @@
+#ifndef __ASM_SH_CLOCK_H
+#define __ASM_SH_CLOCK_H
+
+#include <linux/kref.h>
+#include <linux/list.h>
+#include <linux/seq_file.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk;
+
+struct clk_ops {
+        void (*init)(struct clk *clk);
+        void (*enable)(struct clk *clk);
+        void (*disable)(struct clk *clk);
+        void (*recalc)(struct clk *clk);
+        int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
+        long (*round_rate)(struct clk *clk, unsigned long rate);
+};
+
+struct clk {
+        struct list_head        node;
+        const char              *name;
+        int                     id;
+        struct module           *owner;
+
+        struct clk              *parent;
+        struct clk_ops          *ops;
+
+        struct kref             kref;
+
+        unsigned long           rate;
+        unsigned long           flags;
+        unsigned long           arch_flags;
+};
+
+#define CLK_ALWAYS_ENABLED      (1 << 0)
+#define CLK_RATE_PROPAGATES     (1 << 1)
+
+/* Should be defined by processor-specific code */
+void arch_init_clk_ops(struct clk_ops **, int type);
+
+/* arch/sh/kernel/cpu/clock.c */
+int clk_init(void);
+
+void clk_recalc_rate(struct clk *);
+
+int clk_register(struct clk *);
+void clk_unregister(struct clk *);
+
+static inline int clk_always_enable(const char *id)
+{
+        struct clk *clk;
+        int ret;
+
+        clk = clk_get(NULL, id);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        ret = clk_enable(clk);
+        if (ret)
+                clk_put(clk);
+
+        return ret;
+}
+
+/* the exported API, in addition to clk_set_rate */
+/**
+ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ * @algo_id: algorithm id to be passed down to ops->set_rate
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
+
+enum clk_sh_algo_id {
+        NO_CHANGE = 0,
+
+        IUS_N1_N1,
+        IUS_322,
+        IUS_522,
+        IUS_N11,
+
+        SB_N1,
+
+        SB3_N1,
+        SB3_32,
+        SB3_43,
+        SB3_54,
+
+        BP_N1,
+
+        IP_N1,
+};
+#endif /* __ASM_SH_CLOCK_H */
diff --git a/arch/sh/include/asm/cmpxchg-grb.h b/arch/sh/include/asm/cmpxchg-grb.h
new file mode 100644
index 000000000000..e2681abe764f
--- /dev/null
+++ b/arch/sh/include/asm/cmpxchg-grb.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_SH_CMPXCHG_GRB_H
+#define __ASM_SH_CMPXCHG_GRB_H
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__ (
+                "   .align 2              \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   nop                   \n\t"
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-4,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   mov.l   %2,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (retval),
+                  "+r"  (m)
+                : "r"   (val)
+                : "memory", "r0", "r1");
+
+        return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__ (
+                "   .align  2             \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-6,   r15     \n\t" /* LOGIN */
+                "   mov.b  @%1,   %0      \n\t" /* load  old value */
+                "   extu.b  %0,   %0      \n\t" /* extend as unsigned */
+                "   mov.b   %2,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (retval),
+                  "+r"  (m)
+                : "r"   (val)
+                : "memory" , "r0", "r1");
+
+        return retval;
+}
+
+static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
+                                          unsigned long new)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__ (
+                "   .align  2             \n\t"
+                "   mova    1f,   r0      \n\t" /* r0 = end point */
+                "   nop                   \n\t"
+                "   mov    r15,   r1      \n\t" /* r1 = saved sp */
+                "   mov    #-8,   r15     \n\t" /* LOGIN */
+                "   mov.l  @%1,   %0      \n\t" /* load  old value */
+                "   cmp/eq  %0,   %2      \n\t"
+                "   bf            1f      \n\t" /* if not equal */
+                "   mov.l   %2,   @%1     \n\t" /* store new value */
+                "1: mov     r1,   r15     \n\t" /* LOGOUT */
+                : "=&r" (retval),
+                  "+r"  (m)
+                : "r"   (new)
+                : "memory" , "r0", "r1", "t");
+
+        return retval;
+}
+
+#endif /* __ASM_SH_CMPXCHG_GRB_H */
diff --git a/arch/sh/include/asm/cmpxchg-irq.h b/arch/sh/include/asm/cmpxchg-irq.h
new file mode 100644
index 000000000000..43049ec0554b
--- /dev/null
+++ b/arch/sh/include/asm/cmpxchg-irq.h
@@ -0,0 +1,40 @@
+#ifndef __ASM_SH_CMPXCHG_IRQ_H
+#define __ASM_SH_CMPXCHG_IRQ_H
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+        unsigned long flags, retval;
+
+        local_irq_save(flags);
+        retval = *m;
+        *m = val;
+        local_irq_restore(flags);
+        return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+        unsigned long flags, retval;
+
+        local_irq_save(flags);
+        retval = *m;
+        *m = val & 0xff;
+        local_irq_restore(flags);
+        return retval;
+}
+
+static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
+        unsigned long new)
+{
+        __u32 retval;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        retval = *m;
+        if (retval == old)
+                *m = new;
+        local_irq_restore(flags);       /* implies memory barrier  */
+        return retval;
+}
+
+#endif /* __ASM_SH_CMPXCHG_IRQ_H */
diff --git a/arch/sh/include/asm/cpu-features.h b/arch/sh/include/asm/cpu-features.h
new file mode 100644
index 000000000000..86308aa39731
--- /dev/null
+++ b/arch/sh/include/asm/cpu-features.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_SH_CPU_FEATURES_H
+#define __ASM_SH_CPU_FEATURES_H
+
+/*
+ * Processor flags
+ *
+ * Note: When adding a new flag, keep cpu_flags[] in
+ * arch/sh/kernel/setup.c in sync so symbolic name
+ * mapping of the processor flags has a chance of being
+ * reasonably accurate.
+ *
+ * These flags are also available through the ELF
+ * auxiliary vector as AT_HWCAP.
+ */
+#define CPU_HAS_FPU             0x0001  /* Hardware FPU support */
+#define CPU_HAS_P2_FLUSH_BUG    0x0002  /* Need to flush the cache in P2 area */
+#define CPU_HAS_MMU_PAGE_ASSOC  0x0004  /* SH3: TLB way selection bit support */
+#define CPU_HAS_DSP             0x0008  /* SH-DSP: DSP support */
+#define CPU_HAS_PERF_COUNTER    0x0010  /* Hardware performance counters */
+#define CPU_HAS_PTEA            0x0020  /* PTEA register */
+#define CPU_HAS_LLSC            0x0040  /* movli.l/movco.l */
+#define CPU_HAS_L2_CACHE        0x0080  /* Secondary cache / URAM */
+#define CPU_HAS_OP32            0x0100  /* 32-bit instruction support */
+
+#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/arch/sh/include/asm/cputime.h b/arch/sh/include/asm/cputime.h
new file mode 100644
index 000000000000..6ca395d1393e
--- /dev/null
+++ b/arch/sh/include/asm/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __SH_CPUTIME_H
+#define __SH_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __SH_CPUTIME_H */
diff --git a/arch/sh/include/asm/current.h b/arch/sh/include/asm/current.h
new file mode 100644
index 000000000000..62b63880b333
--- /dev/null
+++ b/arch/sh/include/asm/current.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_SH_CURRENT_H
+#define __ASM_SH_CURRENT_H
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ */
+
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static __inline__ struct task_struct * get_current(void)
+{
+        return current_thread_info()->task;
+}
+
+#define current get_current()
+
+#endif /* __ASM_SH_CURRENT_H */
diff --git a/arch/sh/include/asm/delay.h b/arch/sh/include/asm/delay.h
new file mode 100644
index 000000000000..4b16bf9b56bd
--- /dev/null
+++ b/arch/sh/include/asm/delay.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_SH_DELAY_H
+#define __ASM_SH_DELAY_H
+
+/*
+ * Copyright (C) 1993 Linus Torvalds
+ *
+ * Delay routines calling functions in arch/sh/lib/delay.c
+ */
+
+extern void __bad_udelay(void);
+extern void __bad_ndelay(void);
+
+extern void __udelay(unsigned long usecs);
+extern void __ndelay(unsigned long nsecs);
+extern void __const_udelay(unsigned long xloops);
+extern void __delay(unsigned long loops);
+
+#define udelay(n) (__builtin_constant_p(n) ? \
+        ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \
+        __udelay(n))
+
+#define ndelay(n) (__builtin_constant_p(n) ? \
+        ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
+        __ndelay(n))
+
+#endif /* __ASM_SH_DELAY_H */
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
new file mode 100644
index 000000000000..efd511d0803a
--- /dev/null
+++ b/arch/sh/include/asm/device.h
@@ -0,0 +1,12 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#include <asm-generic/device.h>
+
+struct platform_device;
+/* allocate contiguous memory chunk and fill in struct resource */
+int platform_resource_setup_memory(struct platform_device *pdev,
+                                   char *name, unsigned long memsize);
+
diff --git a/arch/sh/include/asm/div64.h b/arch/sh/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/sh/include/asm/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..627315ecdb52
--- /dev/null
+++ b/arch/sh/include/asm/dma-mapping.h
@@ -0,0 +1,193 @@
+#ifndef __ASM_SH_DMA_MAPPING_H
+#define __ASM_SH_DMA_MAPPING_H
+
+#include <linux/mm.h>
+#include <linux/scatterlist.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm-generic/dma-coherent.h>
+
+extern struct bus_type pci_bus_type;
+
+#define dma_supported(dev, mask)        (1)
+
+static inline int dma_set_mask(struct device *dev, u64 mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = mask;
+
+        return 0;
+}
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                         dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_coherent(struct device *dev, size_t size,
+                       void *vaddr, dma_addr_t dma_handle);
+
+void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+                    enum dma_data_direction dir);
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_is_consistent(d, h) (1)
+
+static inline dma_addr_t dma_map_single(struct device *dev,
+                                        void *ptr, size_t size,
+                                        enum dma_data_direction dir)
+{
+#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+        if (dev->bus == &pci_bus_type)
+                return virt_to_phys(ptr);
+#endif
+        dma_cache_sync(dev, ptr, size, dir);
+
+        return virt_to_phys(ptr);
+}
+
+#define dma_unmap_single(dev, addr, size, dir)  do { } while (0)
+
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+                             int nents, enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nents; i++) {
+#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+                dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
+#endif
+                sg[i].dma_address = sg_phys(&sg[i]);
+        }
+
+        return nents;
+}
+
+#define dma_unmap_sg(dev, sg, nents, dir)       do { } while (0)
+
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      unsigned long offset, size_t size,
+                                      enum dma_data_direction dir)
+{
+        return dma_map_single(dev, page_address(page) + offset, size, dir);
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                  size_t size, enum dma_data_direction dir)
+{
+        dma_unmap_single(dev, dma_address, size, dir);
+}
+
+static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
+                                   size_t size, enum dma_data_direction dir)
+{
+#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+        if (dev->bus == &pci_bus_type)
+                return;
+#endif
+        dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir);
+}
+
+static inline void dma_sync_single_range(struct device *dev,
+                                         dma_addr_t dma_handle,
+                                         unsigned long offset, size_t size,
+                                         enum dma_data_direction dir)
+{
+#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+        if (dev->bus == &pci_bus_type)
+                return;
+#endif
+        dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir);
+}
+
+static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
+                               int nelems, enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nelems; i++) {
+#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
+                dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
+#endif
+                sg[i].dma_address = sg_phys(&sg[i]);
+        }
+}
+
+static inline void dma_sync_single_for_cpu(struct device *dev,
+                                           dma_addr_t dma_handle, size_t size,
+                                           enum dma_data_direction dir)
+{
+        dma_sync_single(dev, dma_handle, size, dir);
+}
+
+static inline void dma_sync_single_for_device(struct device *dev,
+                                              dma_addr_t dma_handle,
+                                              size_t size,
+                                              enum dma_data_direction dir)
+{
+        dma_sync_single(dev, dma_handle, size, dir);
+}
+
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+                                                 dma_addr_t dma_handle,
+                                                 unsigned long offset,
+                                                 size_t size,
+                                                 enum dma_data_direction direction)
+{
+        dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
+}
+
+static inline void dma_sync_single_range_for_device(struct device *dev,
+                                                    dma_addr_t dma_handle,
+                                                    unsigned long offset,
+                                                    size_t size,
+                                                    enum dma_data_direction direction)
+{
+        dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
+}
+
+
+static inline void dma_sync_sg_for_cpu(struct device *dev,
+                                       struct scatterlist *sg, int nelems,
+                                       enum dma_data_direction dir)
+{
+        dma_sync_sg(dev, sg, nelems, dir);
+}
+
+static inline void dma_sync_sg_for_device(struct device *dev,
+                                          struct scatterlist *sg, int nelems,
+                                          enum dma_data_direction dir)
+{
+        dma_sync_sg(dev, sg, nelems, dir);
+}
+
+
+static inline int dma_get_cache_alignment(void)
+{
+        /*
+         * Each processor family will define its own L1_CACHE_SHIFT,
+         * L1_CACHE_BYTES wraps to this, so this is always safe.
+         */
+        return L1_CACHE_BYTES;
+}
+
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return dma_addr == 0;
+}
+
+#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+
+extern int
+dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+                            dma_addr_t device_addr, size_t size, int flags);
+
+extern void
+dma_release_declared_memory(struct device *dev);
+
+extern void *
+dma_mark_declared_memory_occupied(struct device *dev,
+                                  dma_addr_t device_addr, size_t size);
+
+#endif /* __ASM_SH_DMA_MAPPING_H */
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h
new file mode 100644
index 000000000000..beca7128e2ab
--- /dev/null
+++ b/arch/sh/include/asm/dma.h
@@ -0,0 +1,166 @@
+/*
+ * include/asm-sh/dma.h
+ *
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DMA_H
+#define __ASM_SH_DMA_H
+#ifdef __KERNEL__
+
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/sysdev.h>
+#include <cpu/dma.h>
+
+/* The maximum address that we can perform a DMA transfer to on this platform */
+/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
+   occurrence should be flagged as an error.  */
+/* But... */
+/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET+0x10000000)
+
+#ifdef CONFIG_NR_DMA_CHANNELS
+#  define MAX_DMA_CHANNELS      (CONFIG_NR_DMA_CHANNELS)
+#else
+#  define MAX_DMA_CHANNELS      (CONFIG_NR_ONCHIP_DMA_CHANNELS)
+#endif
+
+/*
+ * Read and write modes can mean drastically different things depending on the
+ * channel configuration. Consult your DMAC documentation and module
+ * implementation for further clues.
+ */
+#define DMA_MODE_READ           0x00
+#define DMA_MODE_WRITE          0x01
+#define DMA_MODE_MASK           0x01
+
+#define DMA_AUTOINIT            0x10
+
+/*
+ * DMAC (dma_info) flags
+ */
+enum {
+        DMAC_CHANNELS_CONFIGURED        = 0x01,
+        DMAC_CHANNELS_TEI_CAPABLE       = 0x02, /* Transfer end interrupt */
+};
+
+/*
+ * DMA channel capabilities / flags
+ */
+enum {
+        DMA_CONFIGURED                  = 0x01,
+
+        /*
+         * Transfer end interrupt, inherited from DMAC.
+         * wait_queue used in dma_wait_for_completion.
+         */
+        DMA_TEI_CAPABLE                 = 0x02,
+};
+
+extern spinlock_t dma_spin_lock;
+
+struct dma_channel;
+
+struct dma_ops {
+        int (*request)(struct dma_channel *chan);
+        void (*free)(struct dma_channel *chan);
+
+        int (*get_residue)(struct dma_channel *chan);
+        int (*xfer)(struct dma_channel *chan);
+        int (*configure)(struct dma_channel *chan, unsigned long flags);
+        int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
+};
+
+struct dma_channel {
+        char dev_id[16];                /* unique name per DMAC of channel */
+
+        unsigned int chan;              /* DMAC channel number */
+        unsigned int vchan;             /* Virtual channel number */
+
+        unsigned int mode;
+        unsigned int count;
+
+        unsigned long sar;
+        unsigned long dar;
+
+        const char **caps;
+
+        unsigned long flags;
+        atomic_t busy;
+
+        wait_queue_head_t wait_queue;
+
+        struct sys_device dev;
+        void *priv_data;
+};
+
+struct dma_info {
+        struct platform_device *pdev;
+
+        const char *name;
+        unsigned int nr_channels;
+        unsigned long flags;
+
+        struct dma_ops *ops;
+        struct dma_channel *channels;
+
+        struct list_head list;
+        int first_channel_nr;
+        int first_vchannel_nr;
+};
+
+struct dma_chan_caps {
+        int ch_num;
+        const char **caplist;
+};
+
+#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
+
+/* arch/sh/drivers/dma/dma-api.c */
+extern int dma_xfer(unsigned int chan, unsigned long from,
+                    unsigned long to, size_t size, unsigned int mode);
+
+#define dma_write(chan, from, to, size) \
+        dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
+#define dma_write_page(chan, from, to)  \
+        dma_write(chan, from, to, PAGE_SIZE)
+
+#define dma_read(chan, from, to, size)  \
+        dma_xfer(chan, from, to, size, DMA_MODE_READ)
+#define dma_read_page(chan, from, to)   \
+        dma_read(chan, from, to, PAGE_SIZE)
+
+extern int request_dma_bycap(const char **dmac, const char **caps,
+                             const char *dev_id);
+extern int request_dma(unsigned int chan, const char *dev_id);
+extern void free_dma(unsigned int chan);
+extern int get_dma_residue(unsigned int chan);
+extern struct dma_info *get_dma_info(unsigned int chan);
+extern struct dma_channel *get_dma_channel(unsigned int chan);
+extern void dma_wait_for_completion(unsigned int chan);
+extern void dma_configure_channel(unsigned int chan, unsigned long flags);
+
+extern int register_dmac(struct dma_info *info);
+extern void unregister_dmac(struct dma_info *info);
+extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
+
+extern int dma_extend(unsigned int chan, unsigned long op, void *param);
+extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
+
+/* arch/sh/drivers/dma/dma-sysfs.c */
+extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
+extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_DMA_H */
diff --git a/arch/sh/include/asm/dmabrg.h b/arch/sh/include/asm/dmabrg.h
new file mode 100644
index 000000000000..c5edba216cf1
--- /dev/null
+++ b/arch/sh/include/asm/dmabrg.h
@@ -0,0 +1,23 @@
+/*
+ * SH7760 DMABRG (USB/Audio) support
+ */
+
+#ifndef _DMABRG_H_
+#define _DMABRG_H_
+
+/* IRQ sources */
+#define DMABRGIRQ_USBDMA        0
+#define DMABRGIRQ_USBDMAERR     1
+#define DMABRGIRQ_A0TXF         2
+#define DMABRGIRQ_A0TXH         3
+#define DMABRGIRQ_A0RXF         4
+#define DMABRGIRQ_A0RXH         5
+#define DMABRGIRQ_A1TXF         6
+#define DMABRGIRQ_A1TXH         7
+#define DMABRGIRQ_A1RXF         8
+#define DMABRGIRQ_A1RXH         9
+
+extern int dmabrg_request_irq(unsigned int, void(*)(void *), void *);
+extern void dmabrg_free_irq(unsigned int);
+
+#endif
diff --git a/arch/sh/include/asm/edosk7705.h b/arch/sh/include/asm/edosk7705.h
new file mode 100644
index 000000000000..5bdc9d9be3de
--- /dev/null
+++ b/arch/sh/include/asm/edosk7705.h
@@ -0,0 +1,30 @@
+/*
+ * include/asm-sh/edosk7705.h
+ *
+ * Modified version of io_se.h for the EDOSK7705 specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for an Hitachi EDOSK7705 development board
+ */
+
+#ifndef __ASM_SH_EDOSK7705_IO_H
+#define __ASM_SH_EDOSK7705_IO_H
+
+#include <asm/io_generic.h>
+
+extern unsigned char sh_edosk7705_inb(unsigned long port);
+extern unsigned int sh_edosk7705_inl(unsigned long port);
+
+extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
+extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
+
+extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
+extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
+extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
+
+extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
+
+#endif /* __ASM_SH_EDOSK7705_IO_H */
diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
new file mode 100644
index 000000000000..f01449a8d378
--- /dev/null
+++ b/arch/sh/include/asm/elf.h
@@ -0,0 +1,244 @@
+#ifndef __ASM_SH_ELF_H
+#define __ASM_SH_ELF_H
+
+#include <linux/utsname.h>
+#include <asm/auxvec.h>
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+/* ELF header e_flags defines */
+#define EF_SH_PIC               0x100   /* -fpic */
+#define EF_SH_FDPIC             0x8000  /* -mfdpic */
+
+/* SH (particularly SHcompact) relocation types  */
+#define R_SH_NONE               0
+#define R_SH_DIR32              1
+#define R_SH_REL32              2
+#define R_SH_DIR8WPN            3
+#define R_SH_IND12W             4
+#define R_SH_DIR8WPL            5
+#define R_SH_DIR8WPZ            6
+#define R_SH_DIR8BP             7
+#define R_SH_DIR8W              8
+#define R_SH_DIR8L              9
+#define R_SH_SWITCH16           25
+#define R_SH_SWITCH32           26
+#define R_SH_USES               27
+#define R_SH_COUNT              28
+#define R_SH_ALIGN              29
+#define R_SH_CODE               30
+#define R_SH_DATA               31
+#define R_SH_LABEL              32
+#define R_SH_SWITCH8            33
+#define R_SH_GNU_VTINHERIT      34
+#define R_SH_GNU_VTENTRY        35
+#define R_SH_TLS_GD_32          144
+#define R_SH_TLS_LD_32          145
+#define R_SH_TLS_LDO_32         146
+#define R_SH_TLS_IE_32          147
+#define R_SH_TLS_LE_32          148
+#define R_SH_TLS_DTPMOD32       149
+#define R_SH_TLS_DTPOFF32       150
+#define R_SH_TLS_TPOFF32        151
+#define R_SH_GOT32              160
+#define R_SH_PLT32              161
+#define R_SH_COPY               162
+#define R_SH_GLOB_DAT           163
+#define R_SH_JMP_SLOT           164
+#define R_SH_RELATIVE           165
+#define R_SH_GOTOFF             166
+#define R_SH_GOTPC              167
+
+/* FDPIC relocs */
+#define R_SH_GOT20              70
+#define R_SH_GOTOFF20           71
+#define R_SH_GOTFUNCDESC        72
+#define R_SH_GOTFUNCDESC20      73
+#define R_SH_GOTOFFFUNCDESC     74
+#define R_SH_GOTOFFFUNCDESC20   75
+#define R_SH_FUNCDESC           76
+#define R_SH_FUNCDESC_VALUE     77
+
+#if 0 /* XXX - later .. */
+#define R_SH_GOT20              198
+#define R_SH_GOTOFF20           199
+#define R_SH_GOTFUNCDESC        200
+#define R_SH_GOTFUNCDESC20      201
+#define R_SH_GOTOFFFUNCDESC     202
+#define R_SH_GOTOFFFUNCDESC20   203
+#define R_SH_FUNCDESC           204
+#define R_SH_FUNCDESC_VALUE     205
+#endif
+
+/* SHmedia relocs */
+#define R_SH_IMM_LOW16          246
+#define R_SH_IMM_LOW16_PCREL    247
+#define R_SH_IMM_MEDLOW16       248
+#define R_SH_IMM_MEDLOW16_PCREL 249
+/* Keep this the last entry.  */
+#define R_SH_NUM                256
+
+/*
+ * ELF register definitions..
+ */
+
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_fpu_struct elf_fpregset_t;
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+#ifdef __LITTLE_ENDIAN__
+#define ELF_DATA        ELFDATA2LSB
+#else
+#define ELF_DATA        ELFDATA2MSB
+#endif
+#define ELF_ARCH        EM_SH
+
+#ifdef __KERNEL__
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)               ((x)->e_machine == EM_SH)
+#define elf_check_fdpic(x)              ((x)->e_flags & EF_SH_FDPIC)
+#define elf_check_const_displacement(x) ((x)->e_flags & EF_SH_PIC)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_FDPIC_CORE_EFLAGS   EF_SH_FDPIC
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)
+
+#define ELF_CORE_COPY_REGS(_dest,_regs)                         \
+        memcpy((char *) &_dest, (char *) _regs,                 \
+               sizeof(struct pt_regs));
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this CPU supports.  This could be done in user space,
+   but it's not easy, and we've already done it here.  */
+
+#define ELF_HWCAP       (boot_cpu_data.flags)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.
+
+   For the moment, we have only optimizations for the Intel generations,
+   but that could change... */
+
+#define ELF_PLATFORM    (utsname()->machine)
+
+#ifdef __SH5__
+#define ELF_PLAT_INIT(_r, load_addr) \
+  do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
+       _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
+       _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
+       _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; _r->regs[15]=0; \
+       _r->regs[16]=0; _r->regs[17]=0; _r->regs[18]=0; _r->regs[19]=0; \
+       _r->regs[20]=0; _r->regs[21]=0; _r->regs[22]=0; _r->regs[23]=0; \
+       _r->regs[24]=0; _r->regs[25]=0; _r->regs[26]=0; _r->regs[27]=0; \
+       _r->regs[28]=0; _r->regs[29]=0; _r->regs[30]=0; _r->regs[31]=0; \
+       _r->regs[32]=0; _r->regs[33]=0; _r->regs[34]=0; _r->regs[35]=0; \
+       _r->regs[36]=0; _r->regs[37]=0; _r->regs[38]=0; _r->regs[39]=0; \
+       _r->regs[40]=0; _r->regs[41]=0; _r->regs[42]=0; _r->regs[43]=0; \
+       _r->regs[44]=0; _r->regs[45]=0; _r->regs[46]=0; _r->regs[47]=0; \
+       _r->regs[48]=0; _r->regs[49]=0; _r->regs[50]=0; _r->regs[51]=0; \
+       _r->regs[52]=0; _r->regs[53]=0; _r->regs[54]=0; _r->regs[55]=0; \
+       _r->regs[56]=0; _r->regs[57]=0; _r->regs[58]=0; _r->regs[59]=0; \
+       _r->regs[60]=0; _r->regs[61]=0; _r->regs[62]=0; \
+       _r->tregs[0]=0; _r->tregs[1]=0; _r->tregs[2]=0; _r->tregs[3]=0; \
+       _r->tregs[4]=0; _r->tregs[5]=0; _r->tregs[6]=0; _r->tregs[7]=0; \
+       _r->sr = SR_FD | SR_MMU; } while (0)
+#else
+#define ELF_PLAT_INIT(_r, load_addr) \
+  do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
+       _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
+       _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
+       _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \
+       _r->sr = SR_FD; } while (0)
+
+#define ELF_FDPIC_PLAT_INIT(_r, _exec_map_addr, _interp_map_addr,       \
+                            _dynamic_addr)                              \
+do {                                                                    \
+        _r->regs[0]     = 0;                                            \
+        _r->regs[1]     = 0;                                            \
+        _r->regs[2]     = 0;                                            \
+        _r->regs[3]     = 0;                                            \
+        _r->regs[4]     = 0;                                            \
+        _r->regs[5]     = 0;                                            \
+        _r->regs[6]     = 0;                                            \
+        _r->regs[7]     = 0;                                            \
+        _r->regs[8]     = _exec_map_addr;                               \
+        _r->regs[9]     = _interp_map_addr;                             \
+        _r->regs[10]    = _dynamic_addr;                                \
+        _r->regs[11]    = 0;                                            \
+        _r->regs[12]    = 0;                                            \
+        _r->regs[13]    = 0;                                            \
+        _r->regs[14]    = 0;                                            \
+        _r->sr          = SR_FD;                                        \
+} while (0)
+#endif
+
+#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
+struct task_struct;
+extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
+extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
+
+#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
+#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
+
+#ifdef CONFIG_VSYSCALL
+/* vDSO has arch_setup_additional_pages */
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+struct linux_binprm;
+extern int arch_setup_additional_pages(struct linux_binprm *bprm,
+                                       int executable_stack);
+
+extern unsigned int vdso_enabled;
+extern void __kernel_vsyscall;
+
+#define VDSO_BASE               ((unsigned long)current->mm->context.vdso)
+#define VDSO_SYM(x)             (VDSO_BASE + (unsigned long)(x))
+
+#define VSYSCALL_AUX_ENT                                        \
+        if (vdso_enabled)                                       \
+                NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
+#else
+#define VSYSCALL_AUX_ENT
+#endif /* CONFIG_VSYSCALL */
+
+#ifdef CONFIG_SH_FPU
+#define FPU_AUX_ENT     NEW_AUX_ENT(AT_FPUCW, FPSCR_INIT)
+#else
+#define FPU_AUX_ENT
+#endif
+
+extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
+
+/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
+#define ARCH_DLINFO                                             \
+do {                                                            \
+        /* Optional FPU initialization */                       \
+        FPU_AUX_ENT;                                            \
+                                                                \
+        /* Optional vsyscall entry */                           \
+        VSYSCALL_AUX_ENT;                                       \
+                                                                \
+        /* Cache desc */                                        \
+        NEW_AUX_ENT(AT_L1I_CACHESHAPE, l1i_cache_shape);        \
+        NEW_AUX_ENT(AT_L1D_CACHESHAPE, l1d_cache_shape);        \
+        NEW_AUX_ENT(AT_L2_CACHESHAPE, l2_cache_shape);          \
+} while (0)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_ELF_H */
diff --git a/arch/sh/include/asm/emergency-restart.h b/arch/sh/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/sh/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/sh/include/asm/entry-macros.S b/arch/sh/include/asm/entry-macros.S
new file mode 100644
index 000000000000..2dab0b8d9454
--- /dev/null
+++ b/arch/sh/include/asm/entry-macros.S
@@ -0,0 +1,33 @@
+! entry.S macro define
+        
+        .macro  cli
+        stc     sr, r0
+        or      #0xf0, r0
+        ldc     r0, sr
+        .endm
+
+        .macro  sti
+        mov     #0xf0, r11
+        extu.b  r11, r11
+        not     r11, r11
+        stc     sr, r10
+        and     r11, r10
+#ifdef CONFIG_CPU_HAS_SR_RB
+        stc     k_g_imask, r11
+        or      r11, r10
+#endif
+        ldc     r10, sr
+        .endm
+
+        .macro  get_current_thread_info, ti, tmp
+#ifdef CONFIG_CPU_HAS_SR_RB
+        stc     r7_bank, \ti
+#else
+        mov     #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
+        shll8   \tmp
+        shll2   \tmp
+        mov     r15, \ti
+        and     \tmp, \ti
+#endif  
+        .endm
+
diff --git a/arch/sh/include/asm/errno.h b/arch/sh/include/asm/errno.h
new file mode 100644
index 000000000000..51cf6f9cebb8
--- /dev/null
+++ b/arch/sh/include/asm/errno.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_ERRNO_H
+#define __ASM_SH_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#endif /* __ASM_SH_ERRNO_H */
diff --git a/arch/sh/include/asm/fb.h b/arch/sh/include/asm/fb.h
new file mode 100644
index 000000000000..d92e99cd8c8a
--- /dev/null
+++ b/arch/sh/include/asm/fb.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+        vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/sh/include/asm/fcntl.h b/arch/sh/include/asm/fcntl.h
new file mode 100644
index 000000000000..46ab12db5739
--- /dev/null
+++ b/arch/sh/include/asm/fcntl.h
@@ -0,0 +1 @@
+#include <asm-generic/fcntl.h>
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
new file mode 100644
index 000000000000..721fcc4d5e98
--- /dev/null
+++ b/arch/sh/include/asm/fixmap.h
@@ -0,0 +1,117 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <linux/kernel.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special  addresses
+ * from the end of P3 backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanizm,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+#define FIX_N_COLOURS 16
+        FIX_CMAP_BEGIN,
+        FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
+        FIX_UNCACHED,
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        __end_of_fixed_addresses
+};
+
+extern void __set_fixmap(enum fixed_addresses idx,
+                         unsigned long phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between vmalloc'ed areas and
+ * the start of the fixmap, and leave one page empty
+ * at the top of mem..
+ */
+#ifdef CONFIG_SUPERH32
+#define FIXADDR_TOP     (P4SEG - PAGE_SIZE)
+#else
+#define FIXADDR_TOP     (0xff000000 - PAGE_SIZE)
+#endif
+#define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+#endif
diff --git a/arch/sh/include/asm/flat.h b/arch/sh/include/asm/flat.h
new file mode 100644
index 000000000000..0cc800299e06
--- /dev/null
+++ b/arch/sh/include/asm/flat.h
@@ -0,0 +1,24 @@
+/*
+ * include/asm-sh/flat.h
+ *
+ * uClinux flat-format executables
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive for
+ * more details.
+ */
+#ifndef __ASM_SH_FLAT_H
+#define __ASM_SH_FLAT_H
+
+#define flat_stack_align(sp)                    /* nothing needed */
+#define flat_argvp_envp_on_stack()              0
+#define flat_old_ram_flag(flags)                (flags)
+#define flat_reloc_valid(reloc, size)           ((reloc) <= (size))
+#define flat_get_addr_from_rp(rp, relval, flags, p)     get_unaligned(rp)
+#define flat_put_addr_at_rp(rp, val, relval)    put_unaligned(val,rp)
+#define flat_get_relocate_addr(rel)             (rel)
+#define flat_set_persistent(relval, p)          ({ (void)p; 0; })
+
+#endif /* __ASM_SH_FLAT_H */
diff --git a/arch/sh/include/asm/fpu.h b/arch/sh/include/asm/fpu.h
new file mode 100644
index 000000000000..91462fea1507
--- /dev/null
+++ b/arch/sh/include/asm/fpu.h
@@ -0,0 +1,55 @@
+#ifndef __ASM_SH_FPU_H
+#define __ASM_SH_FPU_H
+
+#ifndef __ASSEMBLY__
+#include <linux/preempt.h>
+#include <asm/ptrace.h>
+
+#ifdef CONFIG_SH_FPU
+static inline void release_fpu(struct pt_regs *regs)
+{
+        regs->sr |= SR_FD;
+}
+
+static inline void grab_fpu(struct pt_regs *regs)
+{
+        regs->sr &= ~SR_FD;
+}
+
+struct task_struct;
+
+extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
+#else
+
+#define release_fpu(regs)       do { } while (0)
+#define grab_fpu(regs)          do { } while (0)
+
+static inline void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
+{
+        clear_tsk_thread_flag(tsk, TIF_USEDFPU);
+}
+#endif
+
+extern int do_fpu_inst(unsigned short, struct pt_regs *);
+
+static inline void unlazy_fpu(struct task_struct *tsk, struct pt_regs *regs)
+{
+        preempt_disable();
+        if (test_tsk_thread_flag(tsk, TIF_USEDFPU))
+                save_fpu(tsk, regs);
+        preempt_enable();
+}
+
+static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs)
+{
+        preempt_disable();
+        if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) {
+                clear_tsk_thread_flag(tsk, TIF_USEDFPU);
+                release_fpu(regs);
+        }
+        preempt_enable();
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_FPU_H */
diff --git a/arch/sh/include/asm/freq.h b/arch/sh/include/asm/freq.h
new file mode 100644
index 000000000000..4ece90b09b9c
--- /dev/null
+++ b/arch/sh/include/asm/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_SH_FREQ_H
+#define __ASM_SH_FREQ_H
+#ifdef __KERNEL__
+
+#include <cpu/freq.h>
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_FREQ_H */
diff --git a/arch/sh/include/asm/futex-irq.h b/arch/sh/include/asm/futex-irq.h
new file mode 100644
index 000000000000..a9f16a7f9aea
--- /dev/null
+++ b/arch/sh/include/asm/futex-irq.h
@@ -0,0 +1,111 @@
+#ifndef __ASM_SH_FUTEX_IRQ_H
+#define __ASM_SH_FUTEX_IRQ_H
+
+#include <asm/system.h>
+
+static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval + oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr,
+                                          int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval | oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval & oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr,
+                                           int *oldval)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+
+        ret = get_user(*oldval, uaddr);
+        if (!ret)
+                ret = put_user(*oldval ^ oparg, uaddr);
+
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr,
+                                                   int oldval, int newval)
+{
+        unsigned long flags;
+        int ret, prev = 0;
+
+        local_irq_save(flags);
+
+        ret = get_user(prev, uaddr);
+        if (!ret && oldval == prev)
+                ret = put_user(newval, uaddr);
+
+        local_irq_restore(flags);
+
+        if (ret)
+                return ret;
+
+        return prev;
+}
+
+#endif /* __ASM_SH_FUTEX_IRQ_H */
diff --git a/arch/sh/include/asm/futex.h b/arch/sh/include/asm/futex.h
new file mode 100644
index 000000000000..68256ec5fa35
--- /dev/null
+++ b/arch/sh/include/asm/futex.h
@@ -0,0 +1,77 @@
+#ifndef __ASM_SH_FUTEX_H
+#define __ASM_SH_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+/* XXX: UP variants, fix for SH-4A and SMP.. */
+#include <asm/futex-irq.h>
+
+static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_ADD:
+                ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_OR:
+                ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_ANDN:
+                ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
+                break;
+        case FUTEX_OP_XOR:
+                ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
+                break;
+        default:
+                ret = -ENOSYS;
+                break;
+        }
+
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval);
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_FUTEX_H */
diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h
new file mode 100644
index 000000000000..cf32bd2df881
--- /dev/null
+++ b/arch/sh/include/asm/gpio.h
@@ -0,0 +1,19 @@
+/*
+ *  include/asm-sh/gpio.h
+ *
+ *  Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ *  Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_GPIO_H
+#define __ASM_SH_GPIO_H
+
+#if defined(CONFIG_CPU_SH3)
+#include <cpu/gpio.h>
+#endif
+
+#endif /* __ASM_SH_GPIO_H */
diff --git a/arch/sh/include/asm/hardirq.h b/arch/sh/include/asm/hardirq.h
new file mode 100644
index 000000000000..715ee237fc77
--- /dev/null
+++ b/arch/sh/include/asm/hardirq.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_SH_HARDIRQ_H
+#define __ASM_SH_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/irq.h>
+
+/* entry.S is sensitive to the offsets of these fields */
+typedef struct {
+        unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+extern void ack_bad_irq(unsigned int irq);
+
+#endif /* __ASM_SH_HARDIRQ_H */
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
new file mode 100644
index 000000000000..8c1353baf00f
--- /dev/null
+++ b/arch/sh/include/asm/hd64461.h
@@ -0,0 +1,250 @@
+#ifndef __ASM_SH_HD64461
+#define __ASM_SH_HD64461
+/*
+ *      Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *      Copyright (C) 2004 Paul Mundt
+ *      Copyright (C) 2000 YAEGASHI Takeshi
+ *
+ *              Hitachi HD64461 companion chip support
+ *      (please note manual reference 0x10000000 = 0xb0000000)
+ */
+
+/* Constants for PCMCIA mappings */
+#define HD64461_PCC_WINDOW      0x01000000
+
+/* Area 6 - Slot 0 - memory and/or IO card */
+#define HD64461_PCC0_BASE       (CONFIG_HD64461_IOBASE + 0x8000000)
+#define HD64461_PCC0_ATTR       (HD64461_PCC0_BASE)                             /* 0xb80000000 */
+#define HD64461_PCC0_COMM       (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)          /* 0xb90000000 */
+#define HD64461_PCC0_IO         (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)        /* 0xba0000000 */
+
+/* Area 5 - Slot 1 - memory card only */
+#define HD64461_PCC1_BASE       (CONFIG_HD64461_IOBASE + 0x4000000)
+#define HD64461_PCC1_ATTR       (HD64461_PCC1_BASE)                             /* 0xb4000000 */
+#define HD64461_PCC1_COMM       (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)          /* 0xb5000000 */
+
+/* Standby Control Register for HD64461 */
+#define HD64461_STBCR                   CONFIG_HD64461_IOBASE
+#define HD64461_STBCR_CKIO_STBY         0x2000
+#define HD64461_STBCR_SAFECKE_IST       0x1000
+#define HD64461_STBCR_SLCKE_IST         0x0800
+#define HD64461_STBCR_SAFECKE_OST       0x0400
+#define HD64461_STBCR_SLCKE_OST         0x0200
+#define HD64461_STBCR_SMIAST            0x0100
+#define HD64461_STBCR_SLCDST            0x0080
+#define HD64461_STBCR_SPC0ST            0x0040
+#define HD64461_STBCR_SPC1ST            0x0020
+#define HD64461_STBCR_SAFEST            0x0010
+#define HD64461_STBCR_STM0ST            0x0008
+#define HD64461_STBCR_STM1ST            0x0004
+#define HD64461_STBCR_SIRST             0x0002
+#define HD64461_STBCR_SURTST            0x0001
+
+/* System Configuration Register */
+#define HD64461_SYSCR           (CONFIG_HD64461_IOBASE + 0x02)
+
+/* CPU Data Bus Control Register */
+#define HD64461_SCPUCR          (CONFIG_HD64461_IOBASE + 0x04)
+
+/* Base Address Register */
+#define HD64461_LCDCBAR         (CONFIG_HD64461_IOBASE + 0x1000)
+
+/* Line increment address */
+#define HD64461_LCDCLOR         (CONFIG_HD64461_IOBASE + 0x1002)
+
+/* Controls LCD controller */
+#define HD64461_LCDCCR          (CONFIG_HD64461_IOBASE + 0x1004)
+
+/* LCCDR control bits */
+#define HD64461_LCDCCR_STBACK   0x0400  /* Standby Back */
+#define HD64461_LCDCCR_STREQ    0x0100  /* Standby Request */
+#define HD64461_LCDCCR_MOFF     0x0080  /* Memory Off */
+#define HD64461_LCDCCR_REFSEL   0x0040  /* Refresh Select */
+#define HD64461_LCDCCR_EPON     0x0020  /* End Power On */
+#define HD64461_LCDCCR_SPON     0x0010  /* Start Power On */
+
+/* Controls LCD (1) */
+#define HD64461_LDR1            (CONFIG_HD64461_IOBASE + 0x1010)
+#define HD64461_LDR1_DON        0x01    /* Display On */
+#define HD64461_LDR1_DINV       0x80    /* Display Invert */
+
+/* Controls LCD (2) */
+#define HD64461_LDR2            (CONFIG_HD64461_IOBASE + 0x1012)
+#define HD64461_LDHNCR          (CONFIG_HD64461_IOBASE + 0x1014)        /* Number of horizontal characters */
+#define HD64461_LDHNSR          (CONFIG_HD64461_IOBASE + 0x1016)        /* Specify output start position + width of CL1 */
+#define HD64461_LDVNTR          (CONFIG_HD64461_IOBASE + 0x1018)        /* Specify total vertical lines */
+#define HD64461_LDVNDR          (CONFIG_HD64461_IOBASE + 0x101a)        /* specify number of display vertical lines */
+#define HD64461_LDVSPR          (CONFIG_HD64461_IOBASE + 0x101c)        /* specify vertical synchronization pos and AC nr */
+
+/* Controls LCD (3) */
+#define HD64461_LDR3            (CONFIG_HD64461_IOBASE + 0x101e)
+
+/* Palette Registers */
+#define HD64461_CPTWAR          (CONFIG_HD64461_IOBASE + 0x1030)        /* Color Palette Write Address Register */
+#define HD64461_CPTWDR          (CONFIG_HD64461_IOBASE + 0x1032)        /* Color Palette Write Data Register */
+#define HD64461_CPTRAR          (CONFIG_HD64461_IOBASE + 0x1034)        /* Color Palette Read Address Register */
+#define HD64461_CPTRDR          (CONFIG_HD64461_IOBASE + 0x1036)        /* Color Palette Read Data Register */
+
+#define HD64461_GRDOR           (CONFIG_HD64461_IOBASE + 0x1040)        /* Display Resolution Offset Register */
+#define HD64461_GRSCR           (CONFIG_HD64461_IOBASE + 0x1042)        /* Solid Color Register */
+#define HD64461_GRCFGR          (CONFIG_HD64461_IOBASE + 0x1044)        /* Accelerator Configuration Register */
+
+#define HD64461_GRCFGR_ACCSTATUS        0x10    /* Accelerator Status */
+#define HD64461_GRCFGR_ACCRESET         0x08    /* Accelerator Reset */
+#define HD64461_GRCFGR_ACCSTART_BITBLT  0x06    /* Accelerator Start BITBLT */
+#define HD64461_GRCFGR_ACCSTART_LINE    0x04    /* Accelerator Start Line Drawing */
+#define HD64461_GRCFGR_COLORDEPTH16     0x01    /* Sets Colordepth 16 for Accelerator */
+#define HD64461_GRCFGR_COLORDEPTH8      0x01    /* Sets Colordepth 8 for Accelerator */
+
+/* Line Drawing Registers */
+#define HD64461_LNSARH          (CONFIG_HD64461_IOBASE + 0x1046)        /* Line Start Address Register (H) */
+#define HD64461_LNSARL          (CONFIG_HD64461_IOBASE + 0x1048)        /* Line Start Address Register (L) */
+#define HD64461_LNAXLR          (CONFIG_HD64461_IOBASE + 0x104a)        /* Axis Pixel Length Register */
+#define HD64461_LNDGR           (CONFIG_HD64461_IOBASE + 0x104c)        /* Diagonal Register */
+#define HD64461_LNAXR           (CONFIG_HD64461_IOBASE + 0x104e)        /* Axial Register */
+#define HD64461_LNERTR          (CONFIG_HD64461_IOBASE + 0x1050)        /* Start Error Term Register */
+#define HD64461_LNMDR           (CONFIG_HD64461_IOBASE + 0x1052)        /* Line Mode Register */
+
+/* BitBLT Registers */
+#define HD64461_BBTSSARH        (CONFIG_HD64461_IOBASE + 0x1054)        /* Source Start Address Register (H) */
+#define HD64461_BBTSSARL        (CONFIG_HD64461_IOBASE + 0x1056)        /* Source Start Address Register (L) */
+#define HD64461_BBTDSARH        (CONFIG_HD64461_IOBASE + 0x1058)        /* Destination Start Address Register (H) */
+#define HD64461_BBTDSARL        (CONFIG_HD64461_IOBASE + 0x105a)        /* Destination Start Address Register (L) */
+#define HD64461_BBTDWR          (CONFIG_HD64461_IOBASE + 0x105c)        /* Destination Block Width Register */
+#define HD64461_BBTDHR          (CONFIG_HD64461_IOBASE + 0x105e)        /* Destination Block Height Register */
+#define HD64461_BBTPARH         (CONFIG_HD64461_IOBASE + 0x1060)        /* Pattern Start Address Register (H) */
+#define HD64461_BBTPARL         (CONFIG_HD64461_IOBASE + 0x1062)        /* Pattern Start Address Register (L) */
+#define HD64461_BBTMARH         (CONFIG_HD64461_IOBASE + 0x1064)        /* Mask Start Address Register (H) */
+#define HD64461_BBTMARL         (CONFIG_HD64461_IOBASE + 0x1066)        /* Mask Start Address Register (L) */
+#define HD64461_BBTROPR         (CONFIG_HD64461_IOBASE + 0x1068)        /* ROP Register */
+#define HD64461_BBTMDR          (CONFIG_HD64461_IOBASE + 0x106a)        /* BitBLT Mode Register */
+
+/* PC Card Controller Registers */
+/* Maps to Physical Area 6 */
+#define HD64461_PCC0ISR         (CONFIG_HD64461_IOBASE + 0x2000)        /* socket 0 interface status */
+#define HD64461_PCC0GCR         (CONFIG_HD64461_IOBASE + 0x2002)        /* socket 0 general control */
+#define HD64461_PCC0CSCR        (CONFIG_HD64461_IOBASE + 0x2004)        /* socket 0 card status change */
+#define HD64461_PCC0CSCIER      (CONFIG_HD64461_IOBASE + 0x2006)        /* socket 0 card status change interrupt enable */
+#define HD64461_PCC0SCR         (CONFIG_HD64461_IOBASE + 0x2008)        /* socket 0 software control */
+/* Maps to Physical Area 5 */
+#define HD64461_PCC1ISR         (CONFIG_HD64461_IOBASE + 0x2010)        /* socket 1 interface status */
+#define HD64461_PCC1GCR         (CONFIG_HD64461_IOBASE + 0x2012)        /* socket 1 general control */
+#define HD64461_PCC1CSCR        (CONFIG_HD64461_IOBASE + 0x2014)        /* socket 1 card status change */
+#define HD64461_PCC1CSCIER      (CONFIG_HD64461_IOBASE + 0x2016)        /* socket 1 card status change interrupt enable */
+#define HD64461_PCC1SCR         (CONFIG_HD64461_IOBASE + 0x2018)        /* socket 1 software control */
+
+/* PCC Interface Status Register */
+#define HD64461_PCCISR_READY            0x80    /* card ready */
+#define HD64461_PCCISR_MWP              0x40    /* card write-protected */
+#define HD64461_PCCISR_VS2              0x20    /* voltage select pin 2 */
+#define HD64461_PCCISR_VS1              0x10    /* voltage select pin 1 */
+#define HD64461_PCCISR_CD2              0x08    /* card detect 2 */
+#define HD64461_PCCISR_CD1              0x04    /* card detect 1 */
+#define HD64461_PCCISR_BVD2             0x02    /* battery 1 */
+#define HD64461_PCCISR_BVD1             0x01    /* battery 1 */
+
+#define HD64461_PCCISR_PCD_MASK         0x0c    /* card detect */
+#define HD64461_PCCISR_BVD_MASK         0x03    /* battery voltage */
+#define HD64461_PCCISR_BVD_BATGOOD      0x03    /* battery good */
+#define HD64461_PCCISR_BVD_BATWARN      0x01    /* battery low warning */
+#define HD64461_PCCISR_BVD_BATDEAD1     0x02    /* battery dead */
+#define HD64461_PCCISR_BVD_BATDEAD2     0x00    /* battery dead */
+
+/* PCC General Control Register */
+#define HD64461_PCCGCR_DRVE             0x80    /* output drive */
+#define HD64461_PCCGCR_PCCR             0x40    /* PC card reset */
+#define HD64461_PCCGCR_PCCT             0x20    /* PC card type, 1=IO&mem, 0=mem */
+#define HD64461_PCCGCR_VCC0             0x10    /* voltage control pin VCC0SEL0 */
+#define HD64461_PCCGCR_PMMOD            0x08    /* memory mode */
+#define HD64461_PCCGCR_PA25             0x04    /* pin A25 */
+#define HD64461_PCCGCR_PA24             0x02    /* pin A24 */
+#define HD64461_PCCGCR_REG              0x01    /* pin PCC0REG# */
+
+/* PCC Card Status Change Register */
+#define HD64461_PCCCSCR_SCDI            0x80    /* sw card detect intr */
+#define HD64461_PCCCSCR_SRV1            0x40    /* reserved */
+#define HD64461_PCCCSCR_IREQ            0x20    /* IREQ intr req */
+#define HD64461_PCCCSCR_SC              0x10    /* STSCHG (status change) pin */
+#define HD64461_PCCCSCR_CDC             0x08    /* CD (card detect) change */
+#define HD64461_PCCCSCR_RC              0x04    /* READY change */
+#define HD64461_PCCCSCR_BW              0x02    /* battery warning change */
+#define HD64461_PCCCSCR_BD              0x01    /* battery dead change */
+
+/* PCC Card Status Change Interrupt Enable Register */
+#define HD64461_PCCCSCIER_CRE           0x80    /* change reset enable */
+#define HD64461_PCCCSCIER_IREQE_MASK    0x60    /* IREQ enable */
+#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00   /* IREQ disabled */
+#define HD64461_PCCCSCIER_IREQE_LEVEL   0x20    /* IREQ level-triggered */
+#define HD64461_PCCCSCIER_IREQE_FALLING 0x40    /* IREQ falling-edge-trig */
+#define HD64461_PCCCSCIER_IREQE_RISING  0x60    /* IREQ rising-edge-trig */
+
+#define HD64461_PCCCSCIER_SCE           0x10    /* status change enable */
+#define HD64461_PCCCSCIER_CDE           0x08    /* card detect change enable */
+#define HD64461_PCCCSCIER_RE            0x04    /* ready change enable */
+#define HD64461_PCCCSCIER_BWE           0x02    /* battery warn change enable */
+#define HD64461_PCCCSCIER_BDE           0x01    /* battery dead change enable*/
+
+/* PCC Software Control Register */
+#define HD64461_PCCSCR_VCC1             0x02    /* voltage control pin 1 */
+#define HD64461_PCCSCR_SWP              0x01    /* write protect */
+
+/* PCC0 Output Pins Control Register */
+#define HD64461_P0OCR           (CONFIG_HD64461_IOBASE + 0x202a)
+
+/* PCC1 Output Pins Control Register */
+#define HD64461_P1OCR           (CONFIG_HD64461_IOBASE + 0x202c)
+
+/* PC Card General Control Register */
+#define HD64461_PGCR            (CONFIG_HD64461_IOBASE + 0x202e)
+
+/* Port Control Registers */
+#define HD64461_GPACR           (CONFIG_HD64461_IOBASE + 0x4000)        /* Port A - Handles IRDA/TIMER */
+#define HD64461_GPBCR           (CONFIG_HD64461_IOBASE + 0x4002)        /* Port B - Handles UART */
+#define HD64461_GPCCR           (CONFIG_HD64461_IOBASE + 0x4004)        /* Port C - Handles PCMCIA 1 */
+#define HD64461_GPDCR           (CONFIG_HD64461_IOBASE + 0x4006)        /* Port D - Handles PCMCIA 1 */
+
+/* Port Control Data Registers */
+#define HD64461_GPADR           (CONFIG_HD64461_IOBASE + 0x4010)        /* A */
+#define HD64461_GPBDR           (CONFIG_HD64461_IOBASE + 0x4012)        /* B */
+#define HD64461_GPCDR           (CONFIG_HD64461_IOBASE + 0x4014)        /* C */
+#define HD64461_GPDDR           (CONFIG_HD64461_IOBASE + 0x4016)        /* D */
+
+/* Interrupt Control Registers */
+#define HD64461_GPAICR          (CONFIG_HD64461_IOBASE + 0x4020)        /* A */
+#define HD64461_GPBICR          (CONFIG_HD64461_IOBASE + 0x4022)        /* B */
+#define HD64461_GPCICR          (CONFIG_HD64461_IOBASE + 0x4024)        /* C */
+#define HD64461_GPDICR          (CONFIG_HD64461_IOBASE + 0x4026)        /* D */
+
+/* Interrupt Status Registers */
+#define HD64461_GPAISR          (CONFIG_HD64461_IOBASE + 0x4040)        /* A */
+#define HD64461_GPBISR          (CONFIG_HD64461_IOBASE + 0x4042)        /* B */
+#define HD64461_GPCISR          (CONFIG_HD64461_IOBASE + 0x4044)        /* C */
+#define HD64461_GPDISR          (CONFIG_HD64461_IOBASE + 0x4046)        /* D */
+
+/* Interrupt Request Register & Interrupt Mask Register */
+#define HD64461_NIRR            (CONFIG_HD64461_IOBASE + 0x5000)
+#define HD64461_NIMR            (CONFIG_HD64461_IOBASE + 0x5002)
+
+#define HD64461_IRQBASE         OFFCHIP_IRQ_BASE
+#define OFFCHIP_IRQ_BASE        64
+#define HD64461_IRQ_NUM         16
+
+#define HD64461_IRQ_UART        (HD64461_IRQBASE+5)
+#define HD64461_IRQ_IRDA        (HD64461_IRQBASE+6)
+#define HD64461_IRQ_TMU1        (HD64461_IRQBASE+9)
+#define HD64461_IRQ_TMU0        (HD64461_IRQBASE+10)
+#define HD64461_IRQ_GPIO        (HD64461_IRQBASE+11)
+#define HD64461_IRQ_AFE         (HD64461_IRQBASE+12)
+#define HD64461_IRQ_PCC1        (HD64461_IRQBASE+13)
+#define HD64461_IRQ_PCC0        (HD64461_IRQBASE+14)
+
+#define __IO_PREFIX     hd64461
+#include <asm/io_generic.h>
+
+/* arch/sh/cchips/hd6446x/hd64461/setup.c */
+int hd64461_irq_demux(int irq);
+void hd64461_register_irq_demux(int irq,
+                                int (*demux) (int irq, void *dev), void *dev);
+void hd64461_unregister_irq_demux(int irq);
+
+#endif
diff --git a/arch/sh/include/asm/hd64465/gpio.h b/arch/sh/include/asm/hd64465/gpio.h
new file mode 100644
index 000000000000..a3cdca2713dd
--- /dev/null
+++ b/arch/sh/include/asm/hd64465/gpio.h
@@ -0,0 +1,46 @@
+#ifndef _ASM_SH_HD64465_GPIO_
+#define _ASM_SH_HD64465_GPIO_ 1
+/*
+ * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
+ *
+ * Hitachi HD64465 companion chip: General Purpose IO pins support.
+ * This layer enables other device drivers to configure GPIO
+ * pins, get and set their values, and register an interrupt
+ * routine for when input pins change in hardware.
+ *
+ * by Greg Banks <gbanks@pocketpenguins.com>
+ * (c) 2000 PocketPenguins Inc.
+ */
+#include <asm/hd64465.h>
+
+/* Macro to construct a portpin number (used in all
+ * subsequent functions) from a port letter and a pin
+ * number, e.g. HD64465_GPIO_PORTPIN('A', 5).
+ */
+#define HD64465_GPIO_PORTPIN(port,pin)  (((port)-'A')<<3|(pin))
+
+/* Pin configuration constants for _configure() */
+#define HD64465_GPIO_FUNCTION2  0       /* use the pin's *other* function */
+#define HD64465_GPIO_OUT        1       /* output */
+#define HD64465_GPIO_IN_PULLUP  2       /* input, pull-up MOS on */
+#define HD64465_GPIO_IN         3       /* input */
+
+/* Configure a pin's direction */
+extern void hd64465_gpio_configure(int portpin, int direction);
+
+/* Get, set value */
+extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
+extern unsigned int hd64465_gpio_get_pin(int portpin);
+extern void hd64465_gpio_set_port(int port, unsigned int value);
+extern unsigned int hd64465_gpio_get_port(int port);
+
+/* mode constants for _register_irq() */
+#define HD64465_GPIO_FALLING    0
+#define HD64465_GPIO_RISING     1
+
+/* Interrupt on external value change */
+extern void hd64465_gpio_register_irq(int portpin, int mode,
+        void (*handler)(int portpin, void *dev), void *dev);
+extern void hd64465_gpio_unregister_irq(int portpin);
+
+#endif /* _ASM_SH_HD64465_GPIO_  */
diff --git a/arch/sh/include/asm/hd64465/hd64465.h b/arch/sh/include/asm/hd64465/hd64465.h
new file mode 100644
index 000000000000..cfd0e803d2a2
--- /dev/null
+++ b/arch/sh/include/asm/hd64465/hd64465.h
@@ -0,0 +1,256 @@
+#ifndef _ASM_SH_HD64465_
+#define _ASM_SH_HD64465_ 1
+/*
+ * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
+ *
+ * Hitachi HD64465 companion chip support
+ *
+ * by Greg Banks <gbanks@pocketpenguins.com>
+ * (c) 2000 PocketPenguins Inc.
+ *
+ * Derived from <asm/hd64461.h> which bore the message:
+ * Copyright (C) 2000 YAEGASHI Takeshi
+ */
+#include <asm/io.h>
+#include <asm/irq.h>
+
+/*
+ * Note that registers are defined here as virtual port numbers,
+ * which have no meaning except to get translated by hd64465_isa_port2addr()
+ * to an address in the range 0xb0000000-0xb3ffffff.  Note that
+ * this translation happens to consist of adding the lower 16 bits
+ * of the virtual port number to 0xb0000000.  Note also that the manual
+ * shows addresses as absolute physical addresses starting at 0x10000000,
+ * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
+ * manual, and accessed using address 0xb0005000 - Greg.
+ */
+
+/* System registers */
+#define HD64465_REG_SRR     0x1000c     /* System Revision Register */
+#define HD64465_REG_SDID    0x10010     /* System Device ID Reg */
+#define     HD64465_SDID            0x8122  /* 64465 device ID */
+
+/* Power Management registers */
+#define HD64465_REG_SMSCR   0x10000     /* System Module Standby Control Reg */
+#define     HD64465_SMSCR_PS2ST     0x4000  /* PS/2 Standby */
+#define     HD64465_SMSCR_ADCST     0x1000  /* ADC Standby */
+#define     HD64465_SMSCR_UARTST    0x0800  /* UART Standby */
+#define     HD64465_SMSCR_SCDIST    0x0200  /* Serial Codec Standby */
+#define     HD64465_SMSCR_PPST      0x0100  /* Parallel Port Standby */
+#define     HD64465_SMSCR_PC0ST     0x0040  /* PCMCIA0 Standby */
+#define     HD64465_SMSCR_PC1ST     0x0020  /* PCMCIA1 Standby */
+#define     HD64465_SMSCR_AFEST     0x0010  /* AFE Standby */
+#define     HD64465_SMSCR_TM0ST     0x0008  /* Timer0 Standby */
+#define     HD64465_SMSCR_TM1ST     0x0004  /* Timer1 Standby */
+#define     HD64465_SMSCR_IRDAST    0x0002  /* IRDA Standby */
+#define     HD64465_SMSCR_KBCST     0x0001  /* Keyboard Controller Standby */
+ 
+/* Interrupt Controller registers */
+#define HD64465_REG_NIRR    0x15000     /* Interrupt Request Register */
+#define HD64465_REG_NIMR    0x15002     /* Interrupt Mask Register */
+#define HD64465_REG_NITR    0x15004     /* Interrupt Trigger Mode Register */
+
+/* Timer registers */
+#define HD64465_REG_TCVR1   0x16000     /* Timer 1 constant value register  */
+#define HD64465_REG_TCVR0   0x16002     /* Timer 0 constant value register  */
+#define HD64465_REG_TRVR1   0x16004     /* Timer 1 read value register  */
+#define HD64465_REG_TRVR0   0x16006     /* Timer 0 read value register  */
+#define HD64465_REG_TCR1    0x16008     /* Timer 1 control register  */
+#define HD64465_REG_TCR0    0x1600A     /* Timer 0 control register  */
+#define     HD64465_TCR_EADT    0x10        /* Enable ADTRIG# signal */
+#define     HD64465_TCR_ETMO    0x08        /* Enable TMO signal */
+#define     HD64465_TCR_PST_MASK 0x06       /* Clock Prescale */
+#define     HD64465_TCR_PST_1   0x06        /* 1:1 */
+#define     HD64465_TCR_PST_4   0x04        /* 1:4 */
+#define     HD64465_TCR_PST_8   0x02        /* 1:8 */
+#define     HD64465_TCR_PST_16  0x00        /* 1:16 */
+#define     HD64465_TCR_TSTP    0x01        /* Start/Stop timer */
+#define HD64465_REG_TIRR    0x1600C     /* Timer interrupt request register  */
+#define HD64465_REG_TIDR    0x1600E     /* Timer interrupt disable register  */
+#define HD64465_REG_PWM1CS  0x16010     /* PWM 1 clock scale register  */
+#define HD64465_REG_PWM1LPC 0x16012     /* PWM 1 low pulse width counter register  */
+#define HD64465_REG_PWM1HPC 0x16014     /* PWM 1 high pulse width counter register  */
+#define HD64465_REG_PWM0CS  0x16018     /* PWM 0 clock scale register  */
+#define HD64465_REG_PWM0LPC 0x1601A     /* PWM 0 low pulse width counter register  */
+#define HD64465_REG_PWM0HPC 0x1601C     /* PWM 0 high pulse width counter register  */
+
+/* Analog/Digital Converter registers */
+#define HD64465_REG_ADDRA   0x1E000     /* A/D data register A */
+#define HD64465_REG_ADDRB   0x1E002     /* A/D data register B */
+#define HD64465_REG_ADDRC   0x1E004     /* A/D data register C */
+#define HD64465_REG_ADDRD   0x1E006     /* A/D data register D */
+#define HD64465_REG_ADCSR   0x1E008     /* A/D control/status register */
+#define     HD64465_ADCSR_ADF       0x80    /* A/D End Flag */
+#define     HD64465_ADCSR_ADST      0x40    /* A/D Start Flag */
+#define     HD64465_ADCSR_ADIS      0x20    /* A/D Interrupt Status */
+#define     HD64465_ADCSR_TRGE      0x10    /* A/D Trigger Enable */
+#define     HD64465_ADCSR_ADIE      0x08    /* A/D Interrupt Enable */
+#define     HD64465_ADCSR_SCAN      0x04    /* A/D Scan Mode */
+#define     HD64465_ADCSR_CH_MASK   0x03    /* A/D Channel */
+#define HD64465_REG_ADCALCR 0x1E00A     /* A/D calibration sample control */
+#define HD64465_REG_ADCAL   0x1E00C     /* A/D calibration data register */
+
+
+/* General Purpose I/O ports registers */
+#define HD64465_REG_GPACR   0x14000     /* Port A Control Register */
+#define HD64465_REG_GPBCR   0x14002     /* Port B Control Register */
+#define HD64465_REG_GPCCR   0x14004     /* Port C Control Register */
+#define HD64465_REG_GPDCR   0x14006     /* Port D Control Register */
+#define HD64465_REG_GPECR   0x14008     /* Port E Control Register */
+#define HD64465_REG_GPADR   0x14010     /* Port A Data Register */
+#define HD64465_REG_GPBDR   0x14012     /* Port B Data Register */
+#define HD64465_REG_GPCDR   0x14014     /* Port C Data Register */
+#define HD64465_REG_GPDDR   0x14016     /* Port D Data Register */
+#define HD64465_REG_GPEDR   0x14018     /* Port E Data Register */
+#define HD64465_REG_GPAICR  0x14020     /* Port A Interrupt Control Register */
+#define HD64465_REG_GPBICR  0x14022     /* Port B Interrupt Control Register */
+#define HD64465_REG_GPCICR  0x14024     /* Port C Interrupt Control Register */
+#define HD64465_REG_GPDICR  0x14026     /* Port D Interrupt Control Register */
+#define HD64465_REG_GPEICR  0x14028     /* Port E Interrupt Control Register */
+#define HD64465_REG_GPAISR  0x14040     /* Port A Interrupt Status Register */
+#define HD64465_REG_GPBISR  0x14042     /* Port B Interrupt Status Register */
+#define HD64465_REG_GPCISR  0x14044     /* Port C Interrupt Status Register */
+#define HD64465_REG_GPDISR  0x14046     /* Port D Interrupt Status Register */
+#define HD64465_REG_GPEISR  0x14048     /* Port E Interrupt Status Register */
+
+/* PCMCIA bridge interface */
+#define HD64465_REG_PCC0ISR     0x12000 /* socket 0 interface status */ 
+#define     HD64465_PCCISR_PREADY        0x80    /* mem card ready / io card IREQ */
+#define     HD64465_PCCISR_PIREQ         0x80
+#define     HD64465_PCCISR_PMWP          0x40    /* mem card write-protected */
+#define     HD64465_PCCISR_PVS2          0x20    /* voltage select pin 2 */
+#define     HD64465_PCCISR_PVS1          0x10    /* voltage select pin 1 */
+#define     HD64465_PCCISR_PCD_MASK      0x0c    /* card detect */
+#define     HD64465_PCCISR_PBVD_MASK     0x03    /* battery voltage */
+#define     HD64465_PCCISR_PBVD_BATGOOD  0x03    /* battery good */
+#define     HD64465_PCCISR_PBVD_BATWARN  0x01    /* battery low warning */
+#define     HD64465_PCCISR_PBVD_BATDEAD1 0x02    /* battery dead */
+#define     HD64465_PCCISR_PBVD_BATDEAD2 0x00    /* battery dead */
+#define HD64465_REG_PCC0GCR     0x12002 /* socket 0 general control */ 
+#define     HD64465_PCCGCR_PDRV          0x80    /* output drive */
+#define     HD64465_PCCGCR_PCCR          0x40    /* PC card reset */
+#define     HD64465_PCCGCR_PCCT          0x20    /* PC card type, 1=IO&mem, 0=mem */
+#define     HD64465_PCCGCR_PVCC0         0x10    /* voltage control pin VCC0SEL0 */
+#define     HD64465_PCCGCR_PMMOD         0x08    /* memory mode */
+#define     HD64465_PCCGCR_PPA25         0x04    /* pin A25 */
+#define     HD64465_PCCGCR_PPA24         0x02    /* pin A24 */
+#define     HD64465_PCCGCR_PREG          0x01    /* ping PCC0REG# */
+#define HD64465_REG_PCC0CSCR    0x12004 /* socket 0 card status change */ 
+#define     HD64465_PCCCSCR_PSCDI        0x80    /* sw card detect intr */
+#define     HD64465_PCCCSCR_PSWSEL       0x40    /* power select */
+#define     HD64465_PCCCSCR_PIREQ        0x20    /* IREQ intr req */
+#define     HD64465_PCCCSCR_PSC          0x10    /* STSCHG (status change) pin */
+#define     HD64465_PCCCSCR_PCDC         0x08    /* CD (card detect) change */
+#define     HD64465_PCCCSCR_PRC          0x04    /* ready change */
+#define     HD64465_PCCCSCR_PBW          0x02    /* battery warning change */
+#define     HD64465_PCCCSCR_PBD          0x01    /* battery dead change */
+#define HD64465_REG_PCC0CSCIER  0x12006 /* socket 0 card status change interrupt enable */ 
+#define     HD64465_PCCCSCIER_PCRE       0x80    /* change reset enable */
+#define     HD64465_PCCCSCIER_PIREQE_MASK       0x60   /* IREQ enable */
+#define     HD64465_PCCCSCIER_PIREQE_DISABLED   0x00   /* IREQ disabled */
+#define     HD64465_PCCCSCIER_PIREQE_LEVEL      0x20   /* IREQ level-triggered */
+#define     HD64465_PCCCSCIER_PIREQE_FALLING    0x40   /* IREQ falling-edge-trig */
+#define     HD64465_PCCCSCIER_PIREQE_RISING     0x60   /* IREQ rising-edge-trig */
+#define     HD64465_PCCCSCIER_PSCE       0x10    /* status change enable */
+#define     HD64465_PCCCSCIER_PCDE       0x08    /* card detect change enable */
+#define     HD64465_PCCCSCIER_PRE        0x04    /* ready change enable */
+#define     HD64465_PCCCSCIER_PBWE       0x02    /* battery warn change enable */
+#define     HD64465_PCCCSCIER_PBDE       0x01    /* battery dead change enable*/
+#define HD64465_REG_PCC0SCR     0x12008 /* socket 0 software control */ 
+#define     HD64465_PCCSCR_SHDN          0x10    /* TPS2206 SHutDowN pin */
+#define     HD64465_PCCSCR_SWP           0x01    /* write protect */
+#define HD64465_REG_PCCPSR      0x1200A /* serial power switch control */ 
+#define HD64465_REG_PCC1ISR     0x12010 /* socket 1 interface status */ 
+#define HD64465_REG_PCC1GCR     0x12012 /* socket 1 general control */ 
+#define HD64465_REG_PCC1CSCR    0x12014 /* socket 1 card status change */ 
+#define HD64465_REG_PCC1CSCIER  0x12016 /* socket 1 card status change interrupt enable */ 
+#define HD64465_REG_PCC1SCR     0x12018 /* socket 1 software control */ 
+
+
+/* PS/2 Keyboard and mouse controller -- *not* register compatible */
+#define HD64465_REG_KBCSR       0x1dc00 /* Keyboard Control/Status reg */
+#define     HD64465_KBCSR_KBCIE          0x8000    /* KBCK Input Enable */
+#define     HD64465_KBCSR_KBCOE          0x4000    /* KBCK Output Enable */
+#define     HD64465_KBCSR_KBDOE          0x2000    /* KB DATA Output Enable */
+#define     HD64465_KBCSR_KBCD           0x1000    /* KBCK Driven */
+#define     HD64465_KBCSR_KBDD           0x0800    /* KB DATA Driven */
+#define     HD64465_KBCSR_KBCS           0x0400    /* KBCK pin Status */
+#define     HD64465_KBCSR_KBDS           0x0200    /* KB DATA pin Status */
+#define     HD64465_KBCSR_KBDP           0x0100    /* KB DATA Parity bit */
+#define     HD64465_KBCSR_KBD_MASK       0x00ff    /* KD DATA shift reg */
+#define HD64465_REG_KBISR       0x1dc04 /* Keyboard Interrupt Status reg */
+#define     HD64465_KBISR_KBRDF          0x0001    /* KB Received Data Full */
+#define HD64465_REG_MSCSR       0x1dc10 /* Mouse Control/Status reg */
+#define HD64465_REG_MSISR       0x1dc14 /* Mouse Interrupt Status reg */
+
+
+/*
+ * Logical address at which the HD64465 is mapped.  Note that this
+ * should always be in the P2 segment (uncached and untranslated).
+ */
+#ifndef CONFIG_HD64465_IOBASE
+#define CONFIG_HD64465_IOBASE   0xb0000000
+#endif
+/*
+ * The HD64465 multiplexes all its modules' interrupts onto
+ * this single interrupt.
+ */
+#ifndef CONFIG_HD64465_IRQ
+#define CONFIG_HD64465_IRQ      5
+#endif
+
+
+#define _HD64465_IO_MASK        0xf8000000
+#define is_hd64465_addr(addr) \
+        ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
+
+/*
+ * A range of 16 virtual interrupts generated by
+ * demuxing the HD64465 muxed interrupt.
+ */
+#define HD64465_IRQ_BASE        OFFCHIP_IRQ_BASE
+#define HD64465_IRQ_NUM         16
+#define HD64465_IRQ_ADC         (HD64465_IRQ_BASE+0)
+#define HD64465_IRQ_USB         (HD64465_IRQ_BASE+1)
+#define HD64465_IRQ_SCDI        (HD64465_IRQ_BASE+2)
+#define HD64465_IRQ_PARALLEL    (HD64465_IRQ_BASE+3)
+/* bit 4 is reserved */
+#define HD64465_IRQ_UART        (HD64465_IRQ_BASE+5)
+#define HD64465_IRQ_IRDA        (HD64465_IRQ_BASE+6)
+#define HD64465_IRQ_PS2MOUSE    (HD64465_IRQ_BASE+7)
+#define HD64465_IRQ_KBC         (HD64465_IRQ_BASE+8)
+#define HD64465_IRQ_TIMER1      (HD64465_IRQ_BASE+9)
+#define HD64465_IRQ_TIMER0      (HD64465_IRQ_BASE+10)
+#define HD64465_IRQ_GPIO        (HD64465_IRQ_BASE+11)
+#define HD64465_IRQ_AFE         (HD64465_IRQ_BASE+12)
+#define HD64465_IRQ_PCMCIA1     (HD64465_IRQ_BASE+13)
+#define HD64465_IRQ_PCMCIA0     (HD64465_IRQ_BASE+14)
+#define HD64465_IRQ_PS2KBD      (HD64465_IRQ_BASE+15)
+
+/* Constants for PCMCIA mappings */
+#define HD64465_PCC_WINDOW      0x01000000
+
+#define HD64465_PCC0_BASE       0xb8000000      /* area 6 */
+#define HD64465_PCC0_ATTR       (HD64465_PCC0_BASE)
+#define HD64465_PCC0_COMM       (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
+#define HD64465_PCC0_IO         (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
+
+#define HD64465_PCC1_BASE       0xb4000000      /* area 5 */
+#define HD64465_PCC1_ATTR       (HD64465_PCC1_BASE)
+#define HD64465_PCC1_COMM       (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
+#define HD64465_PCC1_IO         (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
+
+/*
+ * Base of USB controller interface (as memory)
+ */
+#define HD64465_USB_BASE        (CONFIG_HD64465_IOBASE+0xb000)
+#define HD64465_USB_LEN         0x1000
+/*
+ * Base of embedded SRAM, used for USB controller.
+ */
+#define HD64465_SRAM_BASE       (CONFIG_HD64465_IOBASE+0x9000)
+#define HD64465_SRAM_LEN        0x1000
+
+
+
+#endif /* _ASM_SH_HD64465_  */
diff --git a/arch/sh/include/asm/hd64465/io.h b/arch/sh/include/asm/hd64465/io.h
new file mode 100644
index 000000000000..139f1472e5bb
--- /dev/null
+++ b/arch/sh/include/asm/hd64465/io.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/hd64465/io.h
+ *
+ * By Greg Banks <gbanks@pocketpenguins.com>
+ * (c) 2000 PocketPenguins Inc.
+ *
+ * Derived from io_hd64461.h, which bore the message:
+ * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
+ */
+
+#ifndef _ASM_SH_IO_HD64465_H
+#define _ASM_SH_IO_HD64465_H
+
+extern unsigned char hd64465_inb(unsigned long port);
+extern unsigned short hd64465_inw(unsigned long port);
+extern unsigned int hd64465_inl(unsigned long port);
+
+extern void hd64465_outb(unsigned char value, unsigned long port);
+extern void hd64465_outw(unsigned short value, unsigned long port);
+extern void hd64465_outl(unsigned int value, unsigned long port);
+
+extern unsigned char hd64465_inb_p(unsigned long port);
+extern void hd64465_outb_p(unsigned char value, unsigned long port);
+
+extern unsigned long hd64465_isa_port2addr(unsigned long offset);
+extern int hd64465_irq_demux(int irq);
+/* Provision for generic secondary demux step -- used by PCMCIA code */
+extern void hd64465_register_irq_demux(int irq,
+                int (*demux)(int irq, void *dev), void *dev);
+extern void hd64465_unregister_irq_demux(int irq);
+/* Set this variable to 1 to see port traffic */
+extern int hd64465_io_debug;
+/* Map a range of ports to a range of kernel virtual memory.
+ */
+extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
+                             unsigned long addr, unsigned char shift);
+extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
+
+#endif /* _ASM_SH_IO_HD64465_H */
diff --git a/arch/sh/include/asm/heartbeat.h b/arch/sh/include/asm/heartbeat.h
new file mode 100644
index 000000000000..724a43ed245e
--- /dev/null
+++ b/arch/sh/include/asm/heartbeat.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_SH_HEARTBEAT_H
+#define __ASM_SH_HEARTBEAT_H
+
+#include <linux/timer.h>
+
+#define HEARTBEAT_INVERTED      (1 << 0)
+
+struct heartbeat_data {
+        void __iomem *base;
+        unsigned char *bit_pos;
+        unsigned int nr_bits;
+        struct timer_list timer;
+        unsigned int regsize;
+        unsigned long flags;
+};
+
+#endif /* __ASM_SH_HEARTBEAT_H */
diff --git a/arch/sh/include/asm/hp6xx.h b/arch/sh/include/asm/hp6xx.h
new file mode 100644
index 000000000000..0d4165a32dcd
--- /dev/null
+++ b/arch/sh/include/asm/hp6xx.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_HP6XX_H
+#define __ASM_SH_HP6XX_H
+
+/*
+ * Copyright (C) 2003, 2004, 2005  Andriy Skulysh
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define HP680_BTN_IRQ           32      /* IRQ0_IRQ */
+#define HP680_TS_IRQ            35      /* IRQ3_IRQ */
+#define HP680_HD64461_IRQ       36      /* IRQ4_IRQ */
+
+#define DAC_LCD_BRIGHTNESS      0
+#define DAC_SPEAKER_VOLUME      1
+
+#define PGDR_OPENED             0x01
+#define PGDR_MAIN_BATTERY_OUT   0x04
+#define PGDR_PLAY_BUTTON        0x08
+#define PGDR_REWIND_BUTTON      0x10
+#define PGDR_RECORD_BUTTON      0x20
+
+#define PHDR_TS_PEN_DOWN        0x08
+
+#define PJDR_LED_BLINK          0x02
+
+#define PKDR_LED_GREEN          0x10
+
+#define SCPDR_TS_SCAN_ENABLE    0x20
+#define SCPDR_TS_SCAN_Y         0x02
+#define SCPDR_TS_SCAN_X         0x01
+
+#define SCPCR_TS_ENABLE         0x405
+#define SCPCR_TS_MASK           0xc0f
+
+#define ADC_CHANNEL_TS_Y        1
+#define ADC_CHANNEL_TS_X        2
+#define ADC_CHANNEL_BATTERY     3
+#define ADC_CHANNEL_BACKUP      4
+#define ADC_CHANNEL_CHARGE      5
+
+#define HD64461_GPADR_SPEAKER   0x01
+#define HD64461_GPADR_PCMCIA0   (0x02|0x08)
+
+#define HD64461_GPBDR_LCDOFF    0x01
+#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78
+#define HD64461_GPBDR_LED_RED   0x80
+
+#include <asm/hd64461.h>
+#include <asm/io.h>
+
+#define PJDR    0xa4000130
+#define PKDR    0xa4000132
+
+#endif /* __ASM_SH_HP6XX_H */
diff --git a/arch/sh/include/asm/hugetlb.h b/arch/sh/include/asm/hugetlb.h
new file mode 100644
index 000000000000..967068fb79ac
--- /dev/null
+++ b/arch/sh/include/asm/hugetlb.h
@@ -0,0 +1,92 @@
+#ifndef _ASM_SH_HUGETLB_H
+#define _ASM_SH_HUGETLB_H
+
+#include <asm/page.h>
+
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr,
+                                         unsigned long len) {
+        return 0;
+}
+
+/*
+ * If the arch doesn't supply something else, assume that hugepage
+ * size aligned regions are ok without further preparation.
+ */
+static inline int prepare_hugepage_range(struct file *file,
+                        unsigned long addr, unsigned long len)
+{
+        if (len & ~HPAGE_MASK)
+                return -EINVAL;
+        if (addr & ~HPAGE_MASK)
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm) {
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr, unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        return *ptep;
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+#endif /* _ASM_SH_HUGETLB_H */
diff --git a/arch/sh/include/asm/hw_irq.h b/arch/sh/include/asm/hw_irq.h
new file mode 100644
index 000000000000..d557b00111bf
--- /dev/null
+++ b/arch/sh/include/asm/hw_irq.h
@@ -0,0 +1,123 @@
+#ifndef __ASM_SH_HW_IRQ_H
+#define __ASM_SH_HW_IRQ_H
+
+#include <linux/init.h>
+#include <asm/atomic.h>
+
+extern atomic_t irq_err_count;
+
+struct ipr_data {
+        unsigned char irq;
+        unsigned char ipr_idx;          /* Index for the IPR registered */
+        unsigned char shift;            /* Number of bits to shift the data */
+        unsigned char priority;         /* The priority */
+};
+
+struct ipr_desc {
+        unsigned long *ipr_offsets;
+        unsigned int nr_offsets;
+        struct ipr_data *ipr_data;
+        unsigned int nr_irqs;
+        struct irq_chip chip;
+};
+
+void register_ipr_controller(struct ipr_desc *);
+
+typedef unsigned char intc_enum;
+
+struct intc_vect {
+        intc_enum enum_id;
+        unsigned short vect;
+};
+
+#define INTC_VECT(enum_id, vect) { enum_id, vect }
+#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
+
+struct intc_group {
+        intc_enum enum_id;
+        intc_enum enum_ids[32];
+};
+
+#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
+
+struct intc_mask_reg {
+        unsigned long set_reg, clr_reg, reg_width;
+        intc_enum enum_ids[32];
+#ifdef CONFIG_SMP
+        unsigned long smp;
+#endif
+};
+
+struct intc_prio_reg {
+        unsigned long set_reg, clr_reg, reg_width, field_width;
+        intc_enum enum_ids[16];
+#ifdef CONFIG_SMP
+        unsigned long smp;
+#endif
+};
+
+struct intc_sense_reg {
+        unsigned long reg, reg_width, field_width;
+        intc_enum enum_ids[16];
+};
+
+#ifdef CONFIG_SMP
+#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
+#else
+#define INTC_SMP(stride, nr)
+#endif
+
+struct intc_desc {
+        struct intc_vect *vectors;
+        unsigned int nr_vectors;
+        struct intc_group *groups;
+        unsigned int nr_groups;
+        struct intc_mask_reg *mask_regs;
+        unsigned int nr_mask_regs;
+        struct intc_prio_reg *prio_regs;
+        unsigned int nr_prio_regs;
+        struct intc_sense_reg *sense_regs;
+        unsigned int nr_sense_regs;
+        char *name;
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+        struct intc_mask_reg *ack_regs;
+        unsigned int nr_ack_regs;
+#endif
+};
+
+#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
+#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,            \
+        mask_regs, prio_regs, sense_regs)                               \
+struct intc_desc symbol __initdata = {                                  \
+        _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
+        _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
+        _INTC_ARRAY(sense_regs),                                        \
+        chipname,                                                       \
+}
+
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
+#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,        \
+        mask_regs, prio_regs, sense_regs, ack_regs)                     \
+struct intc_desc symbol __initdata = {                                  \
+        _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
+        _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
+        _INTC_ARRAY(sense_regs),                                        \
+        chipname,                                                       \
+        _INTC_ARRAY(ack_regs),                                          \
+}
+#endif
+
+void __init register_intc_controller(struct intc_desc *desc);
+int intc_set_priority(unsigned int irq, unsigned int prio);
+
+void __init plat_irq_setup(void);
+#ifdef CONFIG_CPU_SH3
+void __init plat_irq_setup_sh3(void);
+#endif
+
+enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
+       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
+       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
+void __init plat_irq_setup_pins(int mode);
+
+#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/arch/sh/include/asm/i2c-sh7760.h b/arch/sh/include/asm/i2c-sh7760.h
new file mode 100644
index 000000000000..24182116711f
--- /dev/null
+++ b/arch/sh/include/asm/i2c-sh7760.h
@@ -0,0 +1,22 @@
+/*
+ * MMIO/IRQ and platform data for SH7760 I2C channels
+ */
+
+#ifndef _I2C_SH7760_H_
+#define _I2C_SH7760_H_
+
+#define SH7760_I2C_DEVNAME      "sh7760-i2c"
+
+#define SH7760_I2C0_MMIO        0xFE140000
+#define SH7760_I2C0_MMIOEND     0xFE14003B
+#define SH7760_I2C0_IRQ         62
+
+#define SH7760_I2C1_MMIO        0xFE150000
+#define SH7760_I2C1_MMIOEND     0xFE15003B
+#define SH7760_I2C1_IRQ         63
+
+struct sh7760_i2c_platdata {
+        unsigned int speed_khz;
+};
+
+#endif
diff --git a/arch/sh/include/asm/ilsel.h b/arch/sh/include/asm/ilsel.h
new file mode 100644
index 000000000000..e3d304b280f6
--- /dev/null
+++ b/arch/sh/include/asm/ilsel.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_SH_ILSEL_H
+#define __ASM_SH_ILSEL_H
+
+typedef enum {
+        ILSEL_NONE,
+        ILSEL_LAN,
+        ILSEL_USBH_I,
+        ILSEL_USBH_S,
+        ILSEL_USBH_V,
+        ILSEL_RTC,
+        ILSEL_USBP_I,
+        ILSEL_USBP_S,
+        ILSEL_USBP_V,
+        ILSEL_KEY,
+
+        /*
+         * ILSEL Aliases - corner cases for interleaved level tables.
+         *
+         * Someone thought this was a good idea and less hassle than
+         * demuxing a shared vector, really.
+         */
+
+        /* ILSEL0 and 2 */
+        ILSEL_FPGA0,
+        ILSEL_FPGA1,
+        ILSEL_EX1,
+        ILSEL_EX2,
+        ILSEL_EX3,
+        ILSEL_EX4,
+
+        /* ILSEL1 and 3 */
+        ILSEL_FPGA2 = ILSEL_FPGA0,
+        ILSEL_FPGA3 = ILSEL_FPGA1,
+        ILSEL_EX5 = ILSEL_EX1,
+        ILSEL_EX6 = ILSEL_EX2,
+        ILSEL_EX7 = ILSEL_EX3,
+        ILSEL_EX8 = ILSEL_EX4,
+} ilsel_source_t;
+
+/* arch/sh/boards/renesas/x3proto/ilsel.c */
+int ilsel_enable(ilsel_source_t set);
+int ilsel_enable_fixed(ilsel_source_t set, unsigned int level);
+void ilsel_disable(unsigned int irq);
+
+#endif /* __ASM_SH_ILSEL_H */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
new file mode 100644
index 000000000000..a4fbf0c84fb1
--- /dev/null
+++ b/arch/sh/include/asm/io.h
@@ -0,0 +1,366 @@
+#ifndef __ASM_SH_IO_H
+#define __ASM_SH_IO_H
+
+/*
+ * Convention:
+ *    read{b,w,l}/write{b,w,l} are for PCI,
+ *    while in{b,w,l}/out{b,w,l} are for ISA
+ * These may (will) be platform specific function.
+ * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
+ * and 'string' versions: ins{b,w,l}/outs{b,w,l}
+ * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
+ * do not have a memory barrier after them.
+ *
+ * In addition, we have
+ *   ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
+ *   which are processor specific.
+ */
+
+/*
+ * We follow the Alpha convention here:
+ *  __inb expands to an inline function call (which calls via the mv)
+ *  _inb  is a real function call (note ___raw fns are _ version of __raw)
+ *  inb   by default expands to _inb, but the machine specific code may
+ *        define it to __inb if it chooses.
+ */
+#include <asm/cache.h>
+#include <asm/system.h>
+#include <asm/addrspace.h>
+#include <asm/machvec.h>
+#include <asm/pgtable.h>
+#include <asm-generic/iomap.h>
+
+#ifdef __KERNEL__
+
+/*
+ * Depending on which platform we are running on, we need different
+ * I/O functions.
+ */
+#define __IO_PREFIX     generic
+#include <asm/io_generic.h>
+#include <asm/io_trapped.h>
+
+#define maybebadio(port) \
+  printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
+         __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
+
+/*
+ * Since boards are able to define their own set of I/O routines through
+ * their respective machine vector, we always wrap through the mv.
+ *
+ * Also, in the event that a board hasn't provided its own definition for
+ * a given routine, it will be wrapped to generic code at run-time.
+ */
+
+#define __inb(p)        sh_mv.mv_inb((p))
+#define __inw(p)        sh_mv.mv_inw((p))
+#define __inl(p)        sh_mv.mv_inl((p))
+#define __outb(x,p)     sh_mv.mv_outb((x),(p))
+#define __outw(x,p)     sh_mv.mv_outw((x),(p))
+#define __outl(x,p)     sh_mv.mv_outl((x),(p))
+
+#define __inb_p(p)      sh_mv.mv_inb_p((p))
+#define __inw_p(p)      sh_mv.mv_inw_p((p))
+#define __inl_p(p)      sh_mv.mv_inl_p((p))
+#define __outb_p(x,p)   sh_mv.mv_outb_p((x),(p))
+#define __outw_p(x,p)   sh_mv.mv_outw_p((x),(p))
+#define __outl_p(x,p)   sh_mv.mv_outl_p((x),(p))
+
+#define __insb(p,b,c)   sh_mv.mv_insb((p), (b), (c))
+#define __insw(p,b,c)   sh_mv.mv_insw((p), (b), (c))
+#define __insl(p,b,c)   sh_mv.mv_insl((p), (b), (c))
+#define __outsb(p,b,c)  sh_mv.mv_outsb((p), (b), (c))
+#define __outsw(p,b,c)  sh_mv.mv_outsw((p), (b), (c))
+#define __outsl(p,b,c)  sh_mv.mv_outsl((p), (b), (c))
+
+#define __readb(a)      sh_mv.mv_readb((a))
+#define __readw(a)      sh_mv.mv_readw((a))
+#define __readl(a)      sh_mv.mv_readl((a))
+#define __writeb(v,a)   sh_mv.mv_writeb((v),(a))
+#define __writew(v,a)   sh_mv.mv_writew((v),(a))
+#define __writel(v,a)   sh_mv.mv_writel((v),(a))
+
+#define inb             __inb
+#define inw             __inw
+#define inl             __inl
+#define outb            __outb
+#define outw            __outw
+#define outl            __outl
+
+#define inb_p           __inb_p
+#define inw_p           __inw_p
+#define inl_p           __inl_p
+#define outb_p          __outb_p
+#define outw_p          __outw_p
+#define outl_p          __outl_p
+
+#define insb            __insb
+#define insw            __insw
+#define insl            __insl
+#define outsb           __outsb
+#define outsw           __outsw
+#define outsl           __outsl
+
+#define __raw_readb(a)          __readb((void __iomem *)(a))
+#define __raw_readw(a)          __readw((void __iomem *)(a))
+#define __raw_readl(a)          __readl((void __iomem *)(a))
+#define __raw_writeb(v, a)      __writeb(v, (void __iomem *)(a))
+#define __raw_writew(v, a)      __writew(v, (void __iomem *)(a))
+#define __raw_writel(v, a)      __writel(v, (void __iomem *)(a))
+
+void __raw_writesl(unsigned long addr, const void *data, int longlen);
+void __raw_readsl(unsigned long addr, void *data, int longlen);
+
+/*
+ * The platform header files may define some of these macros to use
+ * the inlined versions where appropriate.  These macros may also be
+ * redefined by userlevel programs.
+ */
+#ifdef __readb
+# define readb(a)       ({ unsigned int r_ = __raw_readb(a); mb(); r_; })
+#endif
+#ifdef __raw_readw
+# define readw(a)       ({ unsigned int r_ = __raw_readw(a); mb(); r_; })
+#endif
+#ifdef __raw_readl
+# define readl(a)       ({ unsigned int r_ = __raw_readl(a); mb(); r_; })
+#endif
+
+#ifdef __raw_writeb
+# define writeb(v,a)    ({ __raw_writeb((v),(a)); mb(); })
+#endif
+#ifdef __raw_writew
+# define writew(v,a)    ({ __raw_writew((v),(a)); mb(); })
+#endif
+#ifdef __raw_writel
+# define writel(v,a)    ({ __raw_writel((v),(a)); mb(); })
+#endif
+
+#define __BUILD_MEMORY_STRING(bwlq, type)                               \
+                                                                        \
+static inline void writes##bwlq(volatile void __iomem *mem,             \
+                                const void *addr, unsigned int count)   \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                __raw_write##bwlq(*__addr, mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
+                               unsigned int count)                      \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __raw_read##bwlq(mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}
+
+__BUILD_MEMORY_STRING(b, u8)
+__BUILD_MEMORY_STRING(w, u16)
+#define writesl __raw_writesl
+#define readsl  __raw_readsl
+
+#define readb_relaxed(a) readb(a)
+#define readw_relaxed(a) readw(a)
+#define readl_relaxed(a) readl(a)
+
+/* Simple MMIO */
+#define ioread8(a)              readb(a)
+#define ioread16(a)             readw(a)
+#define ioread16be(a)           be16_to_cpu(__raw_readw((a)))
+#define ioread32(a)             readl(a)
+#define ioread32be(a)           be32_to_cpu(__raw_readl((a)))
+
+#define iowrite8(v,a)           writeb((v),(a))
+#define iowrite16(v,a)          writew((v),(a))
+#define iowrite16be(v,a)        __raw_writew(cpu_to_be16((v)),(a))
+#define iowrite32(v,a)          writel((v),(a))
+#define iowrite32be(v,a)        __raw_writel(cpu_to_be32((v)),(a))
+
+#define ioread8_rep(a, d, c)    readsb((a), (d), (c))
+#define ioread16_rep(a, d, c)   readsw((a), (d), (c))
+#define ioread32_rep(a, d, c)   readsl((a), (d), (c))
+
+#define iowrite8_rep(a, s, c)   writesb((a), (s), (c))
+#define iowrite16_rep(a, s, c)  writesw((a), (s), (c))
+#define iowrite32_rep(a, s, c)  writesl((a), (s), (c))
+
+#define mmiowb()        wmb()   /* synco on SH-4A, otherwise a nop */
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * This function provides a method for the generic case where a board-specific
+ * ioport_map simply needs to return the port + some arbitrary port base.
+ *
+ * We use this at board setup time to implicitly set the port base, and
+ * as a result, we can use the generic ioport_map.
+ */
+static inline void __set_io_port_base(unsigned long pbase)
+{
+        extern unsigned long generic_io_base;
+
+        generic_io_base = pbase;
+}
+
+#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
+
+/* We really want to try and get these to memcpy etc */
+extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
+extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
+extern void memset_io(volatile void __iomem *, int, unsigned long);
+
+/* SuperH on-chip I/O functions */
+static inline unsigned char ctrl_inb(unsigned long addr)
+{
+        return *(volatile unsigned char*)addr;
+}
+
+static inline unsigned short ctrl_inw(unsigned long addr)
+{
+        return *(volatile unsigned short*)addr;
+}
+
+static inline unsigned int ctrl_inl(unsigned long addr)
+{
+        return *(volatile unsigned long*)addr;
+}
+
+static inline unsigned long long ctrl_inq(unsigned long addr)
+{
+        return *(volatile unsigned long long*)addr;
+}
+
+static inline void ctrl_outb(unsigned char b, unsigned long addr)
+{
+        *(volatile unsigned char*)addr = b;
+}
+
+static inline void ctrl_outw(unsigned short b, unsigned long addr)
+{
+        *(volatile unsigned short*)addr = b;
+}
+
+static inline void ctrl_outl(unsigned int b, unsigned long addr)
+{
+        *(volatile unsigned long*)addr = b;
+}
+
+static inline void ctrl_outq(unsigned long long b, unsigned long addr)
+{
+        *(volatile unsigned long long*)addr = b;
+}
+
+static inline void ctrl_delay(void)
+{
+#ifdef P2SEG
+        ctrl_inw(P2SEG);
+#endif
+}
+
+/* Quad-word real-mode I/O, don't ask.. */
+unsigned long long peek_real_address_q(unsigned long long addr);
+unsigned long long poke_real_address_q(unsigned long long addr,
+                                       unsigned long long val);
+
+#if !defined(CONFIG_MMU)
+#define virt_to_phys(address)   ((unsigned long)(address))
+#define phys_to_virt(address)   ((void *)(address))
+#else
+#define virt_to_phys(address)   (__pa(address))
+#define phys_to_virt(address)   (__va(address))
+#endif
+
+/*
+ * On 32-bit SH, we traditionally have the whole physical address space
+ * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
+ * not need to do anything but place the address in the proper segment.
+ * This is true for P1 and P2 addresses, as well as some P3 ones.
+ * However, most of the P3 addresses and newer cores using extended
+ * addressing need to map through page tables, so the ioremap()
+ * implementation becomes a bit more complicated.
+ *
+ * See arch/sh/mm/ioremap.c for additional notes on this.
+ *
+ * We cheat a bit and always return uncachable areas until we've fixed
+ * the drivers to handle caching properly.
+ *
+ * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
+ * doesn't exist, so everything must go through page tables.
+ */
+#ifdef CONFIG_MMU
+void __iomem *__ioremap(unsigned long offset, unsigned long size,
+                        unsigned long flags);
+void __iounmap(void __iomem *addr);
+
+/* arch/sh/mm/ioremap_64.c */
+unsigned long onchip_remap(unsigned long addr, unsigned long size,
+                           const char *name);
+extern void onchip_unmap(unsigned long vaddr);
+#else
+#define __ioremap(offset, size, flags)  ((void __iomem *)(offset))
+#define __iounmap(addr)                 do { } while (0)
+#define onchip_remap(addr, size, name)  (addr)
+#define onchip_unmap(addr)              do { } while (0)
+#endif /* CONFIG_MMU */
+
+static inline void __iomem *
+__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
+{
+#ifdef CONFIG_SUPERH32
+        unsigned long last_addr = offset + size - 1;
+#endif
+        void __iomem *ret;
+
+        ret = __ioremap_trapped(offset, size);
+        if (ret)
+                return ret;
+
+#ifdef CONFIG_SUPERH32
+        /*
+         * For P1 and P2 space this is trivial, as everything is already
+         * mapped. Uncached access for P1 addresses are done through P2.
+         * In the P3 case or for addresses outside of the 29-bit space,
+         * mapping must be done by the PMB or by using page tables.
+         */
+        if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
+                if (unlikely(flags & _PAGE_CACHABLE))
+                        return (void __iomem *)P1SEGADDR(offset);
+
+                return (void __iomem *)P2SEGADDR(offset);
+        }
+#endif
+
+        return __ioremap(offset, size, flags);
+}
+
+#define ioremap(offset, size)                           \
+        __ioremap_mode((offset), (size), 0)
+#define ioremap_nocache(offset, size)                   \
+        __ioremap_mode((offset), (size), 0)
+#define ioremap_cache(offset, size)                     \
+        __ioremap_mode((offset), (size), _PAGE_CACHABLE)
+#define p3_ioremap(offset, size, flags)                 \
+        __ioremap((offset), (size), (flags))
+#define iounmap(addr)                                   \
+        __iounmap((addr))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/io_generic.h b/arch/sh/include/asm/io_generic.h
new file mode 100644
index 000000000000..92fc6070d7b3
--- /dev/null
+++ b/arch/sh/include/asm/io_generic.h
@@ -0,0 +1,49 @@
+/*
+ * Trivial I/O routine definitions, intentionally meant to be included
+ * multiple times. Ugly I/O routine concatenation helpers taken from
+ * alpha. Must be included _before_ io.h to avoid preprocessor-induced
+ * routine mismatch.
+ */
+#define IO_CONCAT(a,b)  _IO_CONCAT(a,b)
+#define _IO_CONCAT(a,b) a ## _ ## b
+
+#ifndef __IO_PREFIX
+#error "Don't include this header without a valid system prefix"
+#endif
+
+u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
+u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
+u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
+
+void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
+
+u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
+u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
+u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
+void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
+void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
+
+void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
+void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
+
+u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *);
+u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *);
+u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *);
+void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *);
+void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *);
+void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *);
+
+void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
+void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
+
+void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
+void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
+
+#undef __IO_PREFIX
diff --git a/arch/sh/include/asm/io_trapped.h b/arch/sh/include/asm/io_trapped.h
new file mode 100644
index 000000000000..f1251d4f0ba9
--- /dev/null
+++ b/arch/sh/include/asm/io_trapped.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_IO_TRAPPED_H
+#define __ASM_SH_IO_TRAPPED_H
+
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <asm/page.h>
+
+#define IO_TRAPPED_MAGIC 0xfeedbeef
+
+struct trapped_io {
+        unsigned int magic;
+        struct resource *resource;
+        unsigned int num_resources;
+        unsigned int minimum_bus_width;
+        struct list_head list;
+        void __iomem *virt_base;
+} __aligned(PAGE_SIZE);
+
+#ifdef CONFIG_IO_TRAPPED
+int register_trapped_io(struct trapped_io *tiop);
+int handle_trapped_io(struct pt_regs *regs, unsigned long address);
+
+void __iomem *match_trapped_io_handler(struct list_head *list,
+                                       unsigned long offset,
+                                       unsigned long size);
+
+#ifdef CONFIG_HAS_IOMEM
+extern struct list_head trapped_mem;
+
+static inline void __iomem *
+__ioremap_trapped(unsigned long offset, unsigned long size)
+{
+        return match_trapped_io_handler(&trapped_mem, offset, size);
+}
+#else
+#define __ioremap_trapped(offset, size) NULL
+#endif
+
+#ifdef CONFIG_HAS_IOPORT
+extern struct list_head trapped_io;
+
+static inline void __iomem *
+__ioport_map_trapped(unsigned long offset, unsigned long size)
+{
+        return match_trapped_io_handler(&trapped_io, offset, size);
+}
+#else
+#define __ioport_map_trapped(offset, size) NULL
+#endif
+
+#else
+#define register_trapped_io(tiop) (-1)
+#define handle_trapped_io(tiop, address) 0
+#define __ioremap_trapped(offset, size) NULL
+#define __ioport_map_trapped(offset, size) NULL
+#endif
+
+#endif /* __ASM_SH_IO_TRAPPED_H */
diff --git a/arch/sh/include/asm/ioctl.h b/arch/sh/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/sh/include/asm/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/arch/sh/include/asm/ioctls.h b/arch/sh/include/asm/ioctls.h
new file mode 100644
index 000000000000..c212c371a4a5
--- /dev/null
+++ b/arch/sh/include/asm/ioctls.h
@@ -0,0 +1,103 @@
+#ifndef __ASM_SH_IOCTLS_H
+#define __ASM_SH_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define FIOCLEX         _IO('f', 1)
+#define FIONCLEX        _IO('f', 2)
+#define FIOASYNC        _IOW('f', 125, int)
+#define FIONBIO         _IOW('f', 126, int)
+#define FIONREAD        _IOR('f', 127, int)
+#define TIOCINQ         FIONREAD
+#define FIOQSIZE        _IOR('f', 128, loff_t)
+
+#define TCGETS          0x5401
+#define TCSETS          0x5402
+#define TCSETSW         0x5403
+#define TCSETSF         0x5404
+
+#define TCGETA          0x80127417      /* _IOR('t', 23, struct termio) */
+#define TCSETA          0x40127418      /* _IOW('t', 24, struct termio) */
+#define TCSETAW         0x40127419      /* _IOW('t', 25, struct termio) */
+#define TCSETAF         0x4012741C      /* _IOW('t', 28, struct termio) */
+
+#define TCSBRK          _IO('t', 29)
+#define TCXONC          _IO('t', 30)
+#define TCFLSH          _IO('t', 31)
+
+#define TIOCSWINSZ      0x40087467      /* _IOW('t', 103, struct winsize) */
+#define TIOCGWINSZ      0x80087468      /* _IOR('t', 104, struct winsize) */
+#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
+#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
+#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
+
+#define TIOCSPGRP       _IOW('t', 118, int)
+#define TIOCGPGRP       _IOR('t', 119, int)
+
+#define TIOCEXCL        _IO('T', 12) /* 0x540C */
+#define TIOCNXCL        _IO('T', 13) /* 0x540D */
+#define TIOCSCTTY       _IO('T', 14) /* 0x540E */
+
+#define TIOCSTI         _IOW('T', 18, char) /* 0x5412 */
+#define TIOCMGET        _IOR('T', 21, unsigned int) /* 0x5415 */
+#define TIOCMBIS        _IOW('T', 22, unsigned int) /* 0x5416 */
+#define TIOCMBIC        _IOW('T', 23, unsigned int) /* 0x5417 */
+#define TIOCMSET        _IOW('T', 24, unsigned int) /* 0x5418 */
+# define TIOCM_LE       0x001
+# define TIOCM_DTR      0x002
+# define TIOCM_RTS      0x004
+# define TIOCM_ST       0x008
+# define TIOCM_SR       0x010
+# define TIOCM_CTS      0x020
+# define TIOCM_CAR      0x040
+# define TIOCM_RNG      0x080
+# define TIOCM_DSR      0x100
+# define TIOCM_CD       TIOCM_CAR
+# define TIOCM_RI       TIOCM_RNG
+
+#define TIOCGSOFTCAR    _IOR('T', 25, unsigned int) /* 0x5419 */
+#define TIOCSSOFTCAR    _IOW('T', 26, unsigned int) /* 0x541A */
+#define TIOCLINUX       _IOW('T', 28, char) /* 0x541C */
+#define TIOCCONS        _IO('T', 29) /* 0x541D */
+#define TIOCGSERIAL     0x803C541E      /* _IOR('T', 30, struct serial_struct) 0x541E */
+#define TIOCSSERIAL     0x403C541F      /* _IOW('T', 31, struct serial_struct) 0x541F */
+#define TIOCPKT         _IOW('T', 32, int) /* 0x5420 */
+# define TIOCPKT_DATA            0
+# define TIOCPKT_FLUSHREAD       1
+# define TIOCPKT_FLUSHWRITE      2
+# define TIOCPKT_STOP            4
+# define TIOCPKT_START           8
+# define TIOCPKT_NOSTOP         16
+# define TIOCPKT_DOSTOP         32
+
+
+#define TIOCNOTTY       _IO('T', 34) /* 0x5422 */
+#define TIOCSETD        _IOW('T', 35, int) /* 0x5423 */
+#define TIOCGETD        _IOR('T', 36, int) /* 0x5424 */
+#define TCSBRKP         _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */
+#define TIOCSBRK        _IO('T', 39) /* 0x5427 */ /* BSD compatibility */
+#define TIOCCBRK        _IO('T', 40) /* 0x5428 */ /* BSD compatibility */
+#define TIOCGSID        _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */
+#define TCGETS2         _IOR('T', 42, struct termios2)
+#define TCSETS2         _IOW('T', 43, struct termios2)
+#define TCSETSW2        _IOW('T', 44, struct termios2)
+#define TCSETSF2        _IOW('T', 45, struct termios2)
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define TIOCSERCONFIG   _IO('T', 83) /* 0x5453 */
+#define TIOCSERGWILD    _IOR('T', 84,  int) /* 0x5454 */
+#define TIOCSERSWILD    _IOW('T', 85,  int) /* 0x5455 */
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x80d85458      /* _IOR('T', 88, struct async_struct) 0x5458 */ /* For debugging only */
+#define TIOCSERGETLSR   _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */
+  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+# define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
+#define TIOCSERGETMULTI 0x80A8545A      /* _IOR('T', 90, struct serial_multiport_struct) 0x545A */ /* Get multiport config */
+#define TIOCSERSETMULTI 0x40A8545B      /* _IOW('T', 91, struct serial_multiport_struct) 0x545B */ /* Set multiport config */
+
+#define TIOCMIWAIT      _IO('T', 92) /* 0x545C */       /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+
+#endif /* __ASM_SH_IOCTLS_H */
diff --git a/arch/sh/include/asm/ipcbuf.h b/arch/sh/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..5ffc9972a7ea
--- /dev/null
+++ b/arch/sh/include/asm/ipcbuf.h
@@ -0,0 +1,29 @@
+#ifndef __ASM_SH_IPCBUF_H__
+#define __ASM_SH_IPCBUF_H__
+
+/*
+ * The ipc64_perm structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid32_t        uid;
+        __kernel_gid32_t        gid;
+        __kernel_uid32_t        cuid;
+        __kernel_gid32_t        cgid;
+        __kernel_mode_t         mode;
+        unsigned short          __pad1;
+        unsigned short          seq;
+        unsigned short          __pad2;
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+#endif /* __ASM_SH_IPCBUF_H__ */
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
new file mode 100644
index 000000000000..6195a531c1b0
--- /dev/null
+++ b/arch/sh/include/asm/irq.h
@@ -0,0 +1,57 @@
+#ifndef __ASM_SH_IRQ_H
+#define __ASM_SH_IRQ_H
+
+#include <asm/machvec.h>
+
+/*
+ * A sane default based on a reasonable vector table size, platforms are
+ * advised to cap this at the hard limit that they're interested in
+ * through the machvec.
+ */
+#define NR_IRQS 256
+
+/*
+ * Convert back and forth between INTEVT and IRQ values.
+ */
+#ifdef CONFIG_CPU_HAS_INTEVT
+#define evt2irq(evt)            (((evt) >> 5) - 16)
+#define irq2evt(irq)            (((irq) + 16) << 5)
+#else
+#define evt2irq(evt)            (evt)
+#define irq2evt(irq)            (irq)
+#endif
+
+/*
+ * Simple Mask Register Support
+ */
+extern void make_maskreg_irq(unsigned int irq);
+extern unsigned short *irq_mask_register;
+
+/*
+ * PINT IRQs
+ */
+void init_IRQ_pint(void);
+void make_imask_irq(unsigned int irq);
+
+static inline int generic_irq_demux(int irq)
+{
+        return irq;
+}
+
+#define irq_canonicalize(irq)   (irq)
+#define irq_demux(irq)          sh_mv.mv_irq_demux(irq)
+
+#ifdef CONFIG_IRQSTACKS
+extern void irq_ctx_init(int cpu);
+extern void irq_ctx_exit(int cpu);
+# define __ARCH_HAS_DO_SOFTIRQ
+#else
+# define irq_ctx_init(cpu) do { } while (0)
+# define irq_ctx_exit(cpu) do { } while (0)
+#endif
+
+#ifdef CONFIG_CPU_SH5
+#include <cpu/irq.h>
+#endif
+
+#endif /* __ASM_SH_IRQ_H */
diff --git a/arch/sh/include/asm/irq_regs.h b/arch/sh/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/sh/include/asm/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/arch/sh/include/asm/irqflags.h b/arch/sh/include/asm/irqflags.h
new file mode 100644
index 000000000000..46e71da5be6b
--- /dev/null
+++ b/arch/sh/include/asm/irqflags.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+
+#ifdef CONFIG_SUPERH32
+#include "irqflags_32.h"
+#else
+#include "irqflags_64.h"
+#endif
+
+#define raw_local_save_flags(flags) \
+                do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags != 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        return raw_irqs_disabled_flags(flags);
+}
+
+#define raw_local_irq_save(flags) \
+                do { (flags) = __raw_local_irq_save(); } while (0)
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        if ((flags & 0xf0) != 0xf0)
+                raw_local_irq_enable();
+}
+
+#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/arch/sh/include/asm/irqflags_32.h b/arch/sh/include/asm/irqflags_32.h
new file mode 100644
index 000000000000..60218f541340
--- /dev/null
+++ b/arch/sh/include/asm/irqflags_32.h
@@ -0,0 +1,99 @@
+#ifndef __ASM_SH_IRQFLAGS_32_H
+#define __ASM_SH_IRQFLAGS_32_H
+
+static inline void raw_local_irq_enable(void)
+{
+        unsigned long __dummy0, __dummy1;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+                "stc    r6_bank, %1\n\t"
+                "or     %1, %0\n\t"
+#endif
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x000000f0)
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline void set_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "or     %2, %0\n\t"
+                "and    %3, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "r" (0x10000000), "r" (0xffffff0f)
+                : "memory"
+        );
+}
+
+static inline void clear_bl_bit(void)
+{
+        unsigned long __dummy0, __dummy1;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    %2, %0\n\t"
+                "ldc    %0, sr\n\t"
+                : "=&r" (__dummy0), "=r" (__dummy1)
+                : "1" (~0x10000000)
+                : "memory"
+        );
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "stc    sr, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags)
+                : /* no inputs */
+                : "memory"
+        );
+
+        return flags;
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags, __dummy;
+
+        __asm__ __volatile__ (
+                "stc    sr, %1\n\t"
+                "mov    %1, %0\n\t"
+                "or     #0xf0, %0\n\t"
+                "ldc    %0, sr\n\t"
+                "mov    %1, %0\n\t"
+                "and    #0xf0, %0\n\t"
+                : "=&z" (flags), "=&r" (__dummy)
+                : /* no inputs */
+                : "memory"
+        );
+
+        return flags;
+}
+
+#endif /* __ASM_SH_IRQFLAGS_32_H */
diff --git a/arch/sh/include/asm/irqflags_64.h b/arch/sh/include/asm/irqflags_64.h
new file mode 100644
index 000000000000..88f65222c1d4
--- /dev/null
+++ b/arch/sh/include/asm/irqflags_64.h
@@ -0,0 +1,85 @@
+#ifndef __ASM_SH_IRQFLAGS_64_H
+#define __ASM_SH_IRQFLAGS_64_H
+
+#include <cpu/registers.h>
+
+#define SR_MASK_LL      0x00000000000000f0LL
+#define SR_BL_LL        0x0000000010000000LL
+
+static inline void raw_local_irq_enable(void)
+{
+        unsigned long long __dummy0, __dummy1 = ~SR_MASK_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "and       %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+}
+
+static inline void raw_local_irq_disable(void)
+{
+        unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "or        %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+}
+
+static inline void set_bl_bit(void)
+{
+        unsigned long long __dummy0, __dummy1 = SR_BL_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "or        %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+
+}
+
+static inline void clear_bl_bit(void)
+{
+        unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
+
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "and       %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy0)
+                             : "r" (__dummy1));
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long long __dummy = SR_MASK_LL;
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "getcon " __SR ", %0\n\t"
+                "and    %0, %1, %0"
+                : "=&r" (flags)
+                : "r" (__dummy));
+
+        return flags;
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long long __dummy0, __dummy1 = SR_MASK_LL;
+        unsigned long flags;
+
+        __asm__ __volatile__ (
+                "getcon " __SR ", %1\n\t"
+                "or     %1, r63, %0\n\t"
+                "or     %1, %2, %1\n\t"
+                "putcon %1, " __SR "\n\t"
+                "and    %0, %2, %0"
+                : "=&r" (flags), "=&r" (__dummy0)
+                : "r" (__dummy1));
+
+        return flags;
+}
+
+#endif /* __ASM_SH_IRQFLAGS_64_H */
diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h
new file mode 100644
index 000000000000..49cd69051a88
--- /dev/null
+++ b/arch/sh/include/asm/kdebug.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_SH_KDEBUG_H
+#define __ASM_SH_KDEBUG_H
+
+/* Grossly misnamed. */
+enum die_val {
+        DIE_TRAP,
+};
+
+#endif /* __ASM_SH_KDEBUG_H */
diff --git a/arch/sh/include/asm/kexec.h b/arch/sh/include/asm/kexec.h
new file mode 100644
index 000000000000..00f4260ef09b
--- /dev/null
+++ b/arch/sh/include/asm/kexec.h
@@ -0,0 +1,62 @@
+#ifndef __ASM_SH_KEXEC_H
+#define __ASM_SH_KEXEC_H
+
+#include <asm/ptrace.h>
+#include <asm/string.h>
+
+/*
+ * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
+ * I.e. Maximum page that is mapped directly into kernel memory,
+ * and kmap is not required.
+ *
+ * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
+ * calculation for the amount of memory directly mappable into the
+ * kernel memory space.
+ */
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
+
+#define KEXEC_CONTROL_CODE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_SH
+
+static inline void crash_setup_regs(struct pt_regs *newregs,
+                                    struct pt_regs *oldregs)
+{
+        if (oldregs)
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        else {
+                __asm__ __volatile__ ("mov r0, %0" : "=r" (newregs->regs[0]));
+                __asm__ __volatile__ ("mov r1, %0" : "=r" (newregs->regs[1]));
+                __asm__ __volatile__ ("mov r2, %0" : "=r" (newregs->regs[2]));
+                __asm__ __volatile__ ("mov r3, %0" : "=r" (newregs->regs[3]));
+                __asm__ __volatile__ ("mov r4, %0" : "=r" (newregs->regs[4]));
+                __asm__ __volatile__ ("mov r5, %0" : "=r" (newregs->regs[5]));
+                __asm__ __volatile__ ("mov r6, %0" : "=r" (newregs->regs[6]));
+                __asm__ __volatile__ ("mov r7, %0" : "=r" (newregs->regs[7]));
+                __asm__ __volatile__ ("mov r8, %0" : "=r" (newregs->regs[8]));
+                __asm__ __volatile__ ("mov r9, %0" : "=r" (newregs->regs[9]));
+                __asm__ __volatile__ ("mov r10, %0" : "=r" (newregs->regs[10]));
+                __asm__ __volatile__ ("mov r11, %0" : "=r" (newregs->regs[11]));
+                __asm__ __volatile__ ("mov r12, %0" : "=r" (newregs->regs[12]));
+                __asm__ __volatile__ ("mov r13, %0" : "=r" (newregs->regs[13]));
+                __asm__ __volatile__ ("mov r14, %0" : "=r" (newregs->regs[14]));
+                __asm__ __volatile__ ("mov r15, %0" : "=r" (newregs->regs[15]));
+
+                __asm__ __volatile__ ("sts pr, %0" : "=r" (newregs->pr));
+                __asm__ __volatile__ ("sts macl, %0" : "=r" (newregs->macl));
+                __asm__ __volatile__ ("sts mach, %0" : "=r" (newregs->mach));
+
+                __asm__ __volatile__ ("stc gbr, %0" : "=r" (newregs->gbr));
+                __asm__ __volatile__ ("stc sr, %0" : "=r" (newregs->sr));
+
+                newregs->pc = (unsigned long)current_text_addr();
+        }
+}
+#endif /* __ASM_SH_KEXEC_H */
diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h
new file mode 100644
index 000000000000..24e42078f36f
--- /dev/null
+++ b/arch/sh/include/asm/kgdb.h
@@ -0,0 +1,69 @@
+/*
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on original code by Glenn Engel, Jim Kingdon,
+ * David Grothe <dave@gcom.com>, Tigran Aivazian, <tigran@sco.com> and
+ * Amit S. Kale <akale@veritas.com>
+ * 
+ * Super-H port based on sh-stub.c (Ben Lee and Steve Chamberlain) by
+ * Henry Bell <henry.bell@st.com>
+ * 
+ * Header file for low-level support for remote debug using GDB. 
+ *
+ */
+
+#ifndef __KGDB_H
+#define __KGDB_H
+
+#include <asm/ptrace.h>
+
+/* Same as pt_regs but has vbr in place of syscall_nr */
+struct kgdb_regs {
+        unsigned long regs[16];
+        unsigned long pc;
+        unsigned long pr;
+        unsigned long sr;
+        unsigned long gbr;
+        unsigned long mach;
+        unsigned long macl;
+        unsigned long vbr;
+};
+
+/* State info */
+extern char kgdb_in_gdb_mode;
+extern int kgdb_nofault;        /* Ignore bus errors (in gdb mem access) */
+extern char in_nmi;             /* Debounce flag to prevent NMI reentry*/
+
+/* SCI */
+extern int kgdb_portnum;
+extern int kgdb_baud;
+extern char kgdb_parity;
+extern char kgdb_bits;
+
+/* Init and interface stuff */
+extern int kgdb_init(void);
+extern int (*kgdb_getchar)(void);
+extern void (*kgdb_putchar)(int);
+
+/* Trap functions */
+typedef void (kgdb_debug_hook_t)(struct pt_regs *regs);
+typedef void (kgdb_bus_error_hook_t)(void);
+extern kgdb_debug_hook_t  *kgdb_debug_hook;
+extern kgdb_bus_error_hook_t *kgdb_bus_err_hook;
+
+/* Console */
+struct console;
+void kgdb_console_write(struct console *co, const char *s, unsigned count);
+extern int kgdb_console_setup(struct console *, char *);
+
+/* Prototypes for jmp fns */
+#define _JBLEN 9
+typedef        int jmp_buf[_JBLEN];
+extern void    longjmp(jmp_buf __jmpb, int __retval);
+extern int     setjmp(jmp_buf __jmpb);
+
+/* Forced breakpoint */
+#define breakpoint()    __asm__ __volatile__("trapa   #0x3c")
+
+#endif
diff --git a/arch/sh/include/asm/kmap_types.h b/arch/sh/include/asm/kmap_types.h
new file mode 100644
index 000000000000..84d565c696be
--- /dev/null
+++ b/arch/sh/include/asm/kmap_types.h
@@ -0,0 +1,32 @@
+#ifndef __SH_KMAP_TYPES_H
+#define __SH_KMAP_TYPES_H
+
+/* Dummy header just to define km_type. */
+
+
+#ifdef CONFIG_DEBUG_HIGHMEM
+# define D(n) __KM_FENCE_##n ,
+#else
+# define D(n)
+#endif
+
+enum km_type {
+D(0)    KM_BOUNCE_READ,
+D(1)    KM_SKB_SUNRPC_DATA,
+D(2)    KM_SKB_DATA_SOFTIRQ,
+D(3)    KM_USER0,
+D(4)    KM_USER1,
+D(5)    KM_BIO_SRC_IRQ,
+D(6)    KM_BIO_DST_IRQ,
+D(7)    KM_PTE0,
+D(8)    KM_PTE1,
+D(9)    KM_IRQ0,
+D(10)   KM_IRQ1,
+D(11)   KM_SOFTIRQ0,
+D(12)   KM_SOFTIRQ1,
+D(13)   KM_TYPE_NR
+};
+
+#undef D
+
+#endif
diff --git a/arch/sh/include/asm/lboxre2.h b/arch/sh/include/asm/lboxre2.h
new file mode 100644
index 000000000000..e6d160504923
--- /dev/null
+++ b/arch/sh/include/asm/lboxre2.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_LBOXRE2_H
+#define __ASM_SH_LBOXRE2_H
+
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * NTT COMWARE L-BOX RE2 support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define IRQ_CF1         9       /* CF1 */
+#define IRQ_CF0         10      /* CF0 */
+#define IRQ_INTD        11      /* INTD */
+#define IRQ_ETH1        12      /* Ether1 */
+#define IRQ_ETH0        13      /* Ether0 */
+#define IRQ_INTA        14      /* INTA */
+
+void init_lboxre2_IRQ(void);
+
+#define __IO_PREFIX     lboxre2
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_LBOXRE2_H */
diff --git a/arch/sh/include/asm/linkage.h b/arch/sh/include/asm/linkage.h
new file mode 100644
index 000000000000..3565a4f4009f
--- /dev/null
+++ b/arch/sh/include/asm/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .balign 4
+#define __ALIGN_STR ".balign 4"
+
+#endif
diff --git a/arch/sh/include/asm/local.h b/arch/sh/include/asm/local.h
new file mode 100644
index 000000000000..9ed9b9cb459a
--- /dev/null
+++ b/arch/sh/include/asm/local.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_SH_LOCAL_H
+#define __ASM_SH_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif /* __ASM_SH_LOCAL_H */
+
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
new file mode 100644
index 000000000000..b2e4124070ae
--- /dev/null
+++ b/arch/sh/include/asm/machvec.h
@@ -0,0 +1,70 @@
+/*
+ * include/asm-sh/machvec.h
+ *
+ * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+
+#ifndef _ASM_SH_MACHVEC_H
+#define _ASM_SH_MACHVEC_H
+
+#include <linux/types.h>
+#include <linux/time.h>
+#include <asm/machtypes.h>
+
+struct device;
+
+struct sh_machine_vector {
+        void (*mv_setup)(char **cmdline_p);
+        const char *mv_name;
+        int mv_nr_irqs;
+
+        u8 (*mv_inb)(unsigned long);
+        u16 (*mv_inw)(unsigned long);
+        u32 (*mv_inl)(unsigned long);
+        void (*mv_outb)(u8, unsigned long);
+        void (*mv_outw)(u16, unsigned long);
+        void (*mv_outl)(u32, unsigned long);
+
+        u8 (*mv_inb_p)(unsigned long);
+        u16 (*mv_inw_p)(unsigned long);
+        u32 (*mv_inl_p)(unsigned long);
+        void (*mv_outb_p)(u8, unsigned long);
+        void (*mv_outw_p)(u16, unsigned long);
+        void (*mv_outl_p)(u32, unsigned long);
+
+        void (*mv_insb)(unsigned long, void *dst, unsigned long count);
+        void (*mv_insw)(unsigned long, void *dst, unsigned long count);
+        void (*mv_insl)(unsigned long, void *dst, unsigned long count);
+        void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
+        void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
+        void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
+
+        u8 (*mv_readb)(void __iomem *);
+        u16 (*mv_readw)(void __iomem *);
+        u32 (*mv_readl)(void __iomem *);
+        void (*mv_writeb)(u8, void __iomem *);
+        void (*mv_writew)(u16, void __iomem *);
+        void (*mv_writel)(u32, void __iomem *);
+
+        int (*mv_irq_demux)(int irq);
+
+        void (*mv_init_irq)(void);
+        void (*mv_init_pci)(void);
+
+        void (*mv_heartbeat)(void);
+
+        void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
+        void (*mv_ioport_unmap)(void __iomem *);
+};
+
+extern struct sh_machine_vector sh_mv;
+
+#define get_system_type()       sh_mv.mv_name
+
+#define __initmv \
+        __used __section(.machvec.init)
+
+#endif /* _ASM_SH_MACHVEC_H */
diff --git a/arch/sh/include/asm/magicpanelr2.h b/arch/sh/include/asm/magicpanelr2.h
new file mode 100644
index 000000000000..c644a77ee357
--- /dev/null
+++ b/arch/sh/include/asm/magicpanelr2.h
@@ -0,0 +1,67 @@
+/*
+ *  include/asm-sh/magicpanelr2.h
+ *
+ *  Copyright (C) 2007  Markus Brunner, Mark Jonas
+ *
+ *  I/O addresses and bitmasks for Magic Panel Release 2 board
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_SH_MAGICPANELR2_H
+#define __ASM_SH_MAGICPANELR2_H
+
+#include <asm/gpio.h>
+
+#define __IO_PREFIX mpr2
+#include <asm/io_generic.h>
+
+
+#define SETBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) | mask, reg)
+#define SETBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) | mask, reg)
+#define SETBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) | mask, reg)
+#define CLRBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) & ~mask, reg)
+#define CLRBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) & ~mask, reg)
+#define CLRBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) & ~mask, reg)
+
+
+#define PA_LED          PORT_PADR      /* LED */
+
+
+/* BSC */
+#define CMNCR           0xA4FD0000UL
+#define CS0BCR          0xA4FD0004UL
+#define CS2BCR          0xA4FD0008UL
+#define CS3BCR          0xA4FD000CUL
+#define CS4BCR          0xA4FD0010UL
+#define CS5ABCR         0xA4FD0014UL
+#define CS5BBCR         0xA4FD0018UL
+#define CS6ABCR         0xA4FD001CUL
+#define CS6BBCR         0xA4FD0020UL
+#define CS0WCR          0xA4FD0024UL
+#define CS2WCR          0xA4FD0028UL
+#define CS3WCR          0xA4FD002CUL
+#define CS4WCR          0xA4FD0030UL
+#define CS5AWCR         0xA4FD0034UL
+#define CS5BWCR         0xA4FD0038UL
+#define CS6AWCR         0xA4FD003CUL
+#define CS6BWCR         0xA4FD0040UL
+
+
+/* usb */
+
+#define PORT_UTRCTL             0xA405012CUL
+#define PORT_UCLKCR_W           0xA40A0008UL
+
+#define INTC_ICR0               0xA414FEE0UL
+#define INTC_ICR1               0xA4140010UL
+#define INTC_ICR2               0xA4140012UL
+
+/* MTD */
+
+#define MPR2_MTD_BOOTLOADER_SIZE        0x00060000UL
+#define MPR2_MTD_KERNEL_SIZE            0x00200000UL
+
+#endif  /* __ASM_SH_MAGICPANELR2_H */
diff --git a/arch/sh/include/asm/mc146818rtc.h b/arch/sh/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..0aee96a97330
--- /dev/null
+++ b/arch/sh/include/asm/mc146818rtc.h
@@ -0,0 +1,7 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/arch/sh/include/asm/microdev.h b/arch/sh/include/asm/microdev.h
new file mode 100644
index 000000000000..1aed15856e11
--- /dev/null
+++ b/arch/sh/include/asm/microdev.h
@@ -0,0 +1,80 @@
+/*
+ * linux/include/asm-sh/microdev.h
+ *
+ * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
+ *
+ * Definitions for the SuperH SH4-202 MicroDev board.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+#ifndef __ASM_SH_MICRODEV_H
+#define __ASM_SH_MICRODEV_H
+
+extern void init_microdev_irq(void);
+extern void microdev_print_fpga_intc_status(void);
+
+/*
+ * The following are useful macros for manipulating the interrupt
+ * controller (INTC) on the CPU-board FPGA.  should be noted that there
+ * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
+ * these are two different things, both of which need to be prorammed to
+ * correctly route - unfortunately, they have the same name and
+ * abbreviations!
+ */
+#define MICRODEV_FPGA_INTC_BASE         0xa6110000ul                            /* INTC base address on CPU-board FPGA */
+#define MICRODEV_FPGA_INTENB_REG        (MICRODEV_FPGA_INTC_BASE+0ul)           /* Interrupt Enable Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTDSB_REG        (MICRODEV_FPGA_INTC_BASE+8ul)           /* Interrupt Disable Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTC_MASK(n)      (1ul<<(n))                              /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
+#define MICRODEV_FPGA_INTPRI_REG(n)     (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4))                      /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
+#define MICRODEV_FPGA_INTPRI_MASK(n)    (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTSRC_REG        (MICRODEV_FPGA_INTC_BASE+0x30ul)        /* Interrupt Source Register on INTC on CPU-board FPGA */
+#define MICRODEV_FPGA_INTREQ_REG        (MICRODEV_FPGA_INTC_BASE+0x38ul)        /* Interrupt Request Register on INTC on CPU-board FPGA */
+
+
+/*
+ * The following are the IRQ numbers for the Linux Kernel for external
+ * interrupts.  i.e. the numbers seen by 'cat /proc/interrupt'.
+ */
+#define MICRODEV_LINUX_IRQ_KEYBOARD      1      /* SuperIO Keyboard */
+#define MICRODEV_LINUX_IRQ_SERIAL1       2      /* SuperIO Serial #1 */
+#define MICRODEV_LINUX_IRQ_ETHERNET      3      /* on-board Ethnernet */
+#define MICRODEV_LINUX_IRQ_SERIAL2       4      /* SuperIO Serial #2 */
+#define MICRODEV_LINUX_IRQ_USB_HC        7      /* on-board USB HC */
+#define MICRODEV_LINUX_IRQ_MOUSE        12      /* SuperIO PS/2 Mouse */
+#define MICRODEV_LINUX_IRQ_IDE2         13      /* SuperIO IDE #2 */
+#define MICRODEV_LINUX_IRQ_IDE1         14      /* SuperIO IDE #1 */
+
+/*
+ * The following are the IRQ numbers for the INTC on the FPGA for
+ * external interrupts.  i.e. the bits in the INTC registers in the
+ * FPGA.
+ */
+#define MICRODEV_FPGA_IRQ_KEYBOARD       1      /* SuperIO Keyboard */
+#define MICRODEV_FPGA_IRQ_SERIAL1        3      /* SuperIO Serial #1 */
+#define MICRODEV_FPGA_IRQ_SERIAL2        4      /* SuperIO Serial #2 */
+#define MICRODEV_FPGA_IRQ_MOUSE         12      /* SuperIO PS/2 Mouse */
+#define MICRODEV_FPGA_IRQ_IDE1          14      /* SuperIO IDE #1 */
+#define MICRODEV_FPGA_IRQ_IDE2          15      /* SuperIO IDE #2 */
+#define MICRODEV_FPGA_IRQ_USB_HC        16      /* on-board USB HC */
+#define MICRODEV_FPGA_IRQ_ETHERNET      18      /* on-board Ethnernet */
+
+#define MICRODEV_IRQ_PCI_INTA            8
+#define MICRODEV_IRQ_PCI_INTB            9
+#define MICRODEV_IRQ_PCI_INTC           10
+#define MICRODEV_IRQ_PCI_INTD           11
+
+#define __IO_PREFIX microdev
+#include <asm/io_generic.h>
+
+#if defined(CONFIG_PCI)
+unsigned char  microdev_pci_inb(unsigned long port);
+unsigned short microdev_pci_inw(unsigned long port);
+unsigned long  microdev_pci_inl(unsigned long port);
+void           microdev_pci_outb(unsigned char  data, unsigned long port);
+void           microdev_pci_outw(unsigned short data, unsigned long port);
+void           microdev_pci_outl(unsigned long  data, unsigned long port);
+#endif
+
+#endif /* __ASM_SH_MICRODEV_H */
diff --git a/arch/sh/include/asm/migor.h b/arch/sh/include/asm/migor.h
new file mode 100644
index 000000000000..10016e0f4a4e
--- /dev/null
+++ b/arch/sh/include/asm/migor.h
@@ -0,0 +1,65 @@
+#ifndef __ASM_SH_MIGOR_H
+#define __ASM_SH_MIGOR_H
+
+/*
+ * linux/include/asm-sh/migor.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ *
+ * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* GPIO */
+#define PORT_PACR 0xa4050100
+#define PORT_PDCR 0xa4050106
+#define PORT_PECR 0xa4050108
+#define PORT_PHCR 0xa405010e
+#define PORT_PJCR 0xa4050110
+#define PORT_PKCR 0xa4050112
+#define PORT_PLCR 0xa4050114
+#define PORT_PMCR 0xa4050116
+#define PORT_PRCR 0xa405011c
+#define PORT_PTCR 0xa4050140
+#define PORT_PUCR 0xa4050142
+#define PORT_PVCR 0xa4050144
+#define PORT_PWCR 0xa4050146
+#define PORT_PXCR 0xa4050148
+#define PORT_PYCR 0xa405014a
+#define PORT_PZCR 0xa405014c
+#define PORT_PADR 0xa4050120
+#define PORT_PHDR 0xa405012e
+#define PORT_PTDR 0xa4050160
+#define PORT_PWDR 0xa4050166
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRC 0xa405015c
+
+#define PORT_MSELCRB 0xa4050182
+
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+
+#define PORT_PSELA 0xa405014e
+#define PORT_PSELB 0xa4050150
+#define PORT_PSELC 0xa4050152
+#define PORT_PSELD 0xa4050154
+#define PORT_PSELE 0xa4050156
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRB 0xa405015a
+#define PORT_HIZCRC 0xa405015c
+
+#define BSC_CS6ABCR 0xfec1001c
+
+#include <asm/sh_mobile_lcdc.h>
+
+int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
+                         struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
+
+#endif /* __ASM_SH_MIGOR_H */
diff --git a/arch/sh/include/asm/mman.h b/arch/sh/include/asm/mman.h
new file mode 100644
index 000000000000..156eb0225cf6
--- /dev/null
+++ b/arch/sh/include/asm/mman.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_SH_MMAN_H
+#define __ASM_SH_MMAN_H
+
+#include <asm-generic/mman.h>
+
+#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
+#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
+#define MAP_LOCKED      0x2000          /* pages are locked */
+#define MAP_NORESERVE   0x4000          /* don't check for reservations */
+#define MAP_POPULATE    0x8000          /* populate (prefault) page tables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#endif /* __ASM_SH_MMAN_H */
diff --git a/arch/sh/include/asm/mmu.h b/arch/sh/include/asm/mmu.h
new file mode 100644
index 000000000000..fdcb93bc6d11
--- /dev/null
+++ b/arch/sh/include/asm/mmu.h
@@ -0,0 +1,76 @@
+#ifndef __MMU_H
+#define __MMU_H
+
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_id_t[NR_CPUS];
+
+typedef struct {
+#ifdef CONFIG_MMU
+        mm_context_id_t         id;
+        void                    *vdso;
+#else
+        struct vm_list_struct   *vmlist;
+        unsigned long           end_brk;
+#endif
+#ifdef CONFIG_BINFMT_ELF_FDPIC
+        unsigned long           exec_fdpic_loadmap;
+        unsigned long           interp_fdpic_loadmap;
+#endif
+} mm_context_t;
+
+/*
+ * Privileged Space Mapping Buffer (PMB) definitions
+ */
+#define PMB_PASCR               0xff000070
+#define PMB_IRMCR               0xff000078
+
+#define PMB_ADDR                0xf6100000
+#define PMB_DATA                0xf7100000
+#define PMB_ENTRY_MAX           16
+#define PMB_E_MASK              0x0000000f
+#define PMB_E_SHIFT             8
+
+#define PMB_SZ_16M              0x00000000
+#define PMB_SZ_64M              0x00000010
+#define PMB_SZ_128M             0x00000080
+#define PMB_SZ_512M             0x00000090
+#define PMB_SZ_MASK             PMB_SZ_512M
+#define PMB_C                   0x00000008
+#define PMB_WT                  0x00000001
+#define PMB_UB                  0x00000200
+#define PMB_V                   0x00000100
+
+#define PMB_NO_ENTRY            (-1)
+
+struct pmb_entry;
+
+struct pmb_entry {
+        unsigned long vpn;
+        unsigned long ppn;
+        unsigned long flags;
+
+        /*
+         * 0 .. NR_PMB_ENTRIES for specific entry selection, or
+         * PMB_NO_ENTRY to search for a free one
+         */
+        int entry;
+
+        struct pmb_entry *next;
+        /* Adjacent entry link for contiguous multi-entry mappings */
+        struct pmb_entry *link;
+};
+
+/* arch/sh/mm/pmb.c */
+int __set_pmb_entry(unsigned long vpn, unsigned long ppn,
+                    unsigned long flags, int *entry);
+int set_pmb_entry(struct pmb_entry *pmbe);
+void clear_pmb_entry(struct pmb_entry *pmbe);
+struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
+                            unsigned long flags);
+void pmb_free(struct pmb_entry *pmbe);
+long pmb_remap(unsigned long virt, unsigned long phys,
+               unsigned long size, unsigned long flags);
+void pmb_unmap(unsigned long addr);
+
+#endif /* __MMU_H */
+
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h
new file mode 100644
index 000000000000..04c0c9733ad6
--- /dev/null
+++ b/arch/sh/include/asm/mmu_context.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 - 2007 Paul Mundt
+ *
+ * ASID handling idea taken from MIPS implementation.
+ */
+#ifndef __ASM_SH_MMU_CONTEXT_H
+#define __ASM_SH_MMU_CONTEXT_H
+
+#ifdef __KERNEL__
+#include <cpu/mmu_context.h>
+#include <asm/tlbflush.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm-generic/mm_hooks.h>
+
+/*
+ * The MMU "context" consists of two things:
+ *    (a) TLB cache version (or round, cycle whatever expression you like)
+ *    (b) ASID (Address Space IDentifier)
+ */
+#define MMU_CONTEXT_ASID_MASK           0x000000ff
+#define MMU_CONTEXT_VERSION_MASK        0xffffff00
+#define MMU_CONTEXT_FIRST_VERSION       0x00000100
+#define NO_CONTEXT                      0
+
+/* ASID is 8-bit value, so it can't be 0x100 */
+#define MMU_NO_ASID                     0x100
+
+#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
+
+#ifdef CONFIG_MMU
+#define cpu_context(cpu, mm)    ((mm)->context.id[cpu])
+
+#define cpu_asid(cpu, mm)       \
+        (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)
+
+/*
+ * Virtual Page Number mask
+ */
+#define MMU_VPN_MASK    0xfffff000
+
+#if defined(CONFIG_SUPERH32)
+#include "mmu_context_32.h"
+#else
+#include "mmu_context_64.h"
+#endif
+
+/*
+ * Get MMU context if needed.
+ */
+static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
+{
+        unsigned long asid = asid_cache(cpu);
+
+        /* Check if we have old version of context. */
+        if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
+                /* It's up to date, do nothing */
+                return;
+
+        /* It's old, we need to get new context with new version. */
+        if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
+                /*
+                 * We exhaust ASID of this version.
+                 * Flush all TLB and start new cycle.
+                 */
+                flush_tlb_all();
+
+#ifdef CONFIG_SUPERH64
+                /*
+                 * The SH-5 cache uses the ASIDs, requiring both the I and D
+                 * cache to be flushed when the ASID is exhausted. Weak.
+                 */
+                flush_cache_all();
+#endif
+
+                /*
+                 * Fix version; Note that we avoid version #0
+                 * to distingush NO_CONTEXT.
+                 */
+                if (!asid)
+                        asid = MMU_CONTEXT_FIRST_VERSION;
+        }
+
+        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
+}
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+static inline int init_new_context(struct task_struct *tsk,
+                                   struct mm_struct *mm)
+{
+        int i;
+
+        for (i = 0; i < num_online_cpus(); i++)
+                cpu_context(i, mm) = NO_CONTEXT;
+
+        return 0;
+}
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
+{
+        get_mmu_context(mm, cpu);
+        set_asid(cpu_asid(cpu, mm));
+}
+
+static inline void switch_mm(struct mm_struct *prev,
+                             struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned int cpu = smp_processor_id();
+
+        if (likely(prev != next)) {
+                cpu_set(cpu, next->cpu_vm_mask);
+                set_TTB(next->pgd);
+                activate_context(next, cpu);
+        } else
+                if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
+                        activate_context(next, cpu);
+}
+#else
+#define get_mmu_context(mm)             do { } while (0)
+#define init_new_context(tsk,mm)        (0)
+#define destroy_context(mm)             do { } while (0)
+#define set_asid(asid)                  do { } while (0)
+#define get_asid()                      (0)
+#define cpu_asid(cpu, mm)               ({ (void)cpu; 0; })
+#define switch_and_save_asid(asid)      (0)
+#define set_TTB(pgd)                    do { } while (0)
+#define get_TTB()                       (0)
+#define activate_context(mm,cpu)        do { } while (0)
+#define switch_mm(prev,next,tsk)        do { } while (0)
+#endif /* CONFIG_MMU */
+
+#define activate_mm(prev, next)         switch_mm((prev),(next),NULL)
+#define deactivate_mm(tsk,mm)           do { } while (0)
+#define enter_lazy_tlb(mm,tsk)          do { } while (0)
+
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
+/*
+ * If this processor has an MMU, we need methods to turn it off/on ..
+ * paging_init() will also have to be updated for the processor in
+ * question.
+ */
+static inline void enable_mmu(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        /* Enable MMU */
+        ctrl_outl(MMU_CONTROL_INIT, MMUCR);
+        ctrl_barrier();
+
+        if (asid_cache(cpu) == NO_CONTEXT)
+                asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
+
+        set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
+}
+
+static inline void disable_mmu(void)
+{
+        unsigned long cr;
+
+        cr = ctrl_inl(MMUCR);
+        cr &= ~MMU_CONTROL_INIT;
+        ctrl_outl(cr, MMUCR);
+
+        ctrl_barrier();
+}
+#else
+/*
+ * MMU control handlers for processors lacking memory
+ * management hardware.
+ */
+#define enable_mmu()    do { } while (0)
+#define disable_mmu()   do { } while (0)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_MMU_CONTEXT_H */
diff --git a/arch/sh/include/asm/mmu_context_32.h b/arch/sh/include/asm/mmu_context_32.h
new file mode 100644
index 000000000000..f4f9aebd68b7
--- /dev/null
+++ b/arch/sh/include/asm/mmu_context_32.h
@@ -0,0 +1,47 @@
+#ifndef __ASM_SH_MMU_CONTEXT_32_H
+#define __ASM_SH_MMU_CONTEXT_32_H
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        /* Do nothing */
+}
+
+static inline void set_asid(unsigned long asid)
+{
+        unsigned long __dummy;
+
+        __asm__ __volatile__ ("mov.l    %2, %0\n\t"
+                              "and      %3, %0\n\t"
+                              "or       %1, %0\n\t"
+                              "mov.l    %0, %2"
+                              : "=&r" (__dummy)
+                              : "r" (asid), "m" (__m(MMU_PTEH)),
+                                "r" (0xffffff00));
+}
+
+static inline unsigned long get_asid(void)
+{
+        unsigned long asid;
+
+        __asm__ __volatile__ ("mov.l    %1, %0"
+                              : "=r" (asid)
+                              : "m" (__m(MMU_PTEH)));
+        asid &= MMU_CONTEXT_ASID_MASK;
+        return asid;
+}
+
+/* MMU_TTB is used for optimizing the fault handling. */
+static inline void set_TTB(pgd_t *pgd)
+{
+        ctrl_outl((unsigned long)pgd, MMU_TTB);
+}
+
+static inline pgd_t *get_TTB(void)
+{
+        return (pgd_t *)ctrl_inl(MMU_TTB);
+}
+#endif /* __ASM_SH_MMU_CONTEXT_32_H */
diff --git a/arch/sh/include/asm/mmu_context_64.h b/arch/sh/include/asm/mmu_context_64.h
new file mode 100644
index 000000000000..de121025d87f
--- /dev/null
+++ b/arch/sh/include/asm/mmu_context_64.h
@@ -0,0 +1,78 @@
+#ifndef __ASM_SH_MMU_CONTEXT_64_H
+#define __ASM_SH_MMU_CONTEXT_64_H
+
+/*
+ * sh64-specific mmu_context interface.
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003 - 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <cpu/registers.h>
+#include <asm/cacheflush.h>
+
+#define SR_ASID_MASK            0xffffffffff00ffffULL
+#define SR_ASID_SHIFT           16
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        /* Well, at least free TLB entries */
+        flush_tlb_mm(mm);
+}
+
+static inline unsigned long get_asid(void)
+{
+        unsigned long long sr;
+
+        asm volatile ("getcon   " __SR ", %0\n\t"
+                      : "=r" (sr));
+
+        sr = (sr >> SR_ASID_SHIFT) & MMU_CONTEXT_ASID_MASK;
+        return (unsigned long) sr;
+}
+
+/* Set ASID into SR */
+static inline void set_asid(unsigned long asid)
+{
+        unsigned long long sr, pc;
+
+        asm volatile ("getcon   " __SR ", %0" : "=r" (sr));
+
+        sr = (sr & SR_ASID_MASK) | (asid << SR_ASID_SHIFT);
+
+        /*
+         * It is possible that this function may be inlined and so to avoid
+         * the assembler reporting duplicate symbols we make use of the
+         * gas trick of generating symbols using numerics and forward
+         * reference.
+         */
+        asm volatile ("movi     1, %1\n\t"
+                      "shlli    %1, 28, %1\n\t"
+                      "or       %0, %1, %1\n\t"
+                      "putcon   %1, " __SR "\n\t"
+                      "putcon   %0, " __SSR "\n\t"
+                      "movi     1f, %1\n\t"
+                      "ori      %1, 1 , %1\n\t"
+                      "putcon   %1, " __SPC "\n\t"
+                      "rte\n"
+                      "1:\n\t"
+                      : "=r" (sr), "=r" (pc) : "0" (sr));
+}
+
+/* arch/sh/kernel/cpu/sh5/entry.S */
+extern unsigned long switch_and_save_asid(unsigned long new_asid);
+
+/* No spare register to twiddle, so use a software cache */
+extern pgd_t *mmu_pdtp_cache;
+
+#define set_TTB(pgd)    (mmu_pdtp_cache = (pgd))
+#define get_TTB()       (mmu_pdtp_cache)
+
+#endif /* __ASM_SH_MMU_CONTEXT_64_H */
diff --git a/arch/sh/include/asm/mmzone.h b/arch/sh/include/asm/mmzone.h
new file mode 100644
index 000000000000..2969253c4042
--- /dev/null
+++ b/arch/sh/include/asm/mmzone.h
@@ -0,0 +1,48 @@
+#ifndef __ASM_SH_MMZONE_H
+#define __ASM_SH_MMZONE_H
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+extern struct pglist_data *node_data[];
+#define NODE_DATA(nid)          (node_data[nid])
+
+#define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
+#define node_end_pfn(nid)       (NODE_DATA(nid)->node_start_pfn + \
+                                 NODE_DATA(nid)->node_spanned_pages)
+
+static inline int pfn_to_nid(unsigned long pfn)
+{
+        int nid;
+
+        for (nid = 0; nid < MAX_NUMNODES; nid++)
+                if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid))
+                        break;
+
+        return nid;
+}
+
+static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn)
+{
+        return NODE_DATA(pfn_to_nid(pfn));
+}
+
+/* arch/sh/mm/numa.c */
+void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end);
+#else
+static inline void
+setup_bootmem_node(int nid, unsigned long start, unsigned long end)
+{
+}
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
+/* Platform specific mem init */
+void __init plat_mem_setup(void);
+
+/* arch/sh/kernel/setup.c */
+void __init setup_bootmem_allocator(unsigned long start_pfn);
+void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
+                               unsigned long end_pfn);
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_MMZONE_H */
diff --git a/arch/sh/include/asm/module.h b/arch/sh/include/asm/module.h
new file mode 100644
index 000000000000..46eccd331660
--- /dev/null
+++ b/arch/sh/include/asm/module.h
@@ -0,0 +1,44 @@
+#ifndef _ASM_SH_MODULE_H
+#define _ASM_SH_MODULE_H
+
+/*
+ * This file contains the SH architecture specific module code.
+ */
+
+struct mod_arch_specific {
+        /* Nothing to see here .. */
+};
+
+#define Elf_Shdr                Elf32_Shdr
+#define Elf_Sym                 Elf32_Sym
+#define Elf_Ehdr                Elf32_Ehdr
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+# ifdef CONFIG_CPU_SH2
+#  define MODULE_PROC_FAMILY "SH2LE "
+# elif defined  CONFIG_CPU_SH3
+#  define MODULE_PROC_FAMILY "SH3LE "
+# elif defined  CONFIG_CPU_SH4
+#  define MODULE_PROC_FAMILY "SH4LE "
+# elif defined  CONFIG_CPU_SH5
+#  define MODULE_PROC_FAMILY "SH5LE "
+# else
+#  error unknown processor family
+# endif
+#else
+# ifdef CONFIG_CPU_SH2
+#  define MODULE_PROC_FAMILY "SH2BE "
+# elif defined  CONFIG_CPU_SH3
+#  define MODULE_PROC_FAMILY "SH3BE "
+# elif defined  CONFIG_CPU_SH4
+#  define MODULE_PROC_FAMILY "SH4BE "
+# elif defined  CONFIG_CPU_SH5
+#  define MODULE_PROC_FAMILY "SH5BE "
+# else
+#  error unknown processor family
+# endif
+#endif
+
+#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY
+
+#endif /* _ASM_SH_MODULE_H */
diff --git a/arch/sh/include/asm/msgbuf.h b/arch/sh/include/asm/msgbuf.h
new file mode 100644
index 000000000000..517432343fb5
--- /dev/null
+++ b/arch/sh/include/asm/msgbuf.h
@@ -0,0 +1,31 @@
+#ifndef __ASM_SH_MSGBUF_H
+#define __ASM_SH_MSGBUF_H
+
+/* 
+ * The msqid64_ds structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned long   __unused1;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned long   __unused2;
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long   __unused3;
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* __ASM_SH_MSGBUF_H */
diff --git a/arch/sh/include/asm/mutex.h b/arch/sh/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/sh/include/asm/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
new file mode 100644
index 000000000000..77fb8bf02e4e
--- /dev/null
+++ b/arch/sh/include/asm/page.h
@@ -0,0 +1,183 @@
+#ifndef __ASM_SH_PAGE_H
+#define __ASM_SH_PAGE_H
+
+/*
+ * Copyright (C) 1999  Niibe Yutaka
+ */
+
+#include <linux/const.h>
+
+/* PAGE_SHIFT determines the page size */
+#if defined(CONFIG_PAGE_SIZE_4KB)
+# define PAGE_SHIFT     12
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+# define PAGE_SHIFT     13
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+# define PAGE_SHIFT     14
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+# define PAGE_SHIFT     16
+#else
+# error "Bogus kernel page size?"
+#endif
+
+#define PAGE_SIZE       (_AC(1, UL) << PAGE_SHIFT)
+#define PAGE_MASK       (~(PAGE_SIZE-1))
+#define PTE_MASK        PAGE_MASK
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define HPAGE_SHIFT     16
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#define HPAGE_SHIFT     18
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#define HPAGE_SHIFT     20
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define HPAGE_SHIFT     22
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#define HPAGE_SHIFT     26
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
+#define HPAGE_SHIFT     29
+#endif
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define HPAGE_SIZE              (1UL << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE-1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT-PAGE_SHIFT)
+#endif
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long shm_align_mask;
+extern unsigned long max_low_pfn, min_low_pfn;
+extern unsigned long memory_start, memory_end;
+
+extern void clear_page(void *to);
+extern void copy_page(void *to, void *from);
+
+#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
+        (defined(CONFIG_CPU_SH5) || defined(CONFIG_CPU_SH4) || \
+         defined(CONFIG_SH7705_CACHE_32KB))
+struct page;
+struct vm_area_struct;
+extern void clear_user_page(void *to, unsigned long address, struct page *page);
+extern void copy_user_page(void *to, void *from, unsigned long address,
+                           struct page *page);
+#if defined(CONFIG_CPU_SH4)
+extern void copy_user_highpage(struct page *to, struct page *from,
+                               unsigned long vaddr, struct vm_area_struct *vma);
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+#endif
+#else
+#define clear_user_page(page, vaddr, pg)        clear_page(page)
+#define copy_user_page(to, from, vaddr, pg)     copy_page(to, from)
+#endif
+
+/*
+ * These are used to make use of C type-checking..
+ */
+#ifdef CONFIG_X2TLB
+typedef struct { unsigned long pte_low, pte_high; } pte_t;
+typedef struct { unsigned long long pgprot; } pgprot_t;
+typedef struct { unsigned long long pgd; } pgd_t;
+#define pte_val(x) \
+        ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+#define __pte(x) \
+        ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
+#elif defined(CONFIG_SUPERH32)
+typedef struct { unsigned long pte_low; } pte_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pgd; } pgd_t;
+#define pte_val(x)      ((x).pte_low)
+#define __pte(x)        ((pte_t) { (x) } )
+#else
+typedef struct { unsigned long long pte_low; } pte_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pgd; } pgd_t;
+#define pte_val(x)      ((x).pte_low)
+#define __pte(x)        ((pte_t) { (x) } )
+#endif
+
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pgd(x) ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+typedef struct page *pgtable_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * __MEMORY_START and SIZE are the physical addresses and size of RAM.
+ */
+#define __MEMORY_START          CONFIG_MEMORY_START
+#define __MEMORY_SIZE           CONFIG_MEMORY_SIZE
+
+/*
+ * PAGE_OFFSET is the virtual address of the start of kernel address
+ * space.
+ */
+#define PAGE_OFFSET             CONFIG_PAGE_OFFSET
+
+/*
+ * Virtual to physical RAM address translation.
+ *
+ * In 29 bit mode, the physical offset of RAM from address 0 is visible in
+ * the kernel virtual address space, and thus we don't have to take
+ * this into account when translating. However in 32 bit mode this offset
+ * is not visible (it is part of the PMB mapping) and so needs to be
+ * added or subtracted as required.
+ */
+#ifdef CONFIG_32BIT
+#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START)
+#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START))
+#else
+#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
+#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
+#endif
+
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+
+/*
+ * PFN = physical frame number (ie PFN 0 == physical address 0)
+ * PFN_START is the PFN of the first page of RAM. By defining this we
+ * don't have struct page entries for the portion of address space
+ * between physical address 0 and the start of RAM.
+ */
+#define PFN_START               (__MEMORY_START >> PAGE_SHIFT)
+#define ARCH_PFN_OFFSET         (PFN_START)
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#ifdef CONFIG_FLATMEM
+#define pfn_valid(pfn)          ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
+#endif
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/page.h>
+
+/* vDSO support */
+#ifdef CONFIG_VSYSCALL
+#define __HAVE_ARCH_GATE_AREA
+#endif
+
+/*
+ * Some drivers need to perform DMA into kmalloc'ed buffers
+ * and so we have to increase the kmalloc minalign for this.
+ */
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
+
+#ifdef CONFIG_SUPERH64
+/*
+ * While BYTES_PER_WORD == 4 on the current sh64 ABI, GCC will still
+ * happily generate {ld/st}.q pairs, requiring us to have 8-byte
+ * alignment to avoid traps. The kmalloc alignment is gauranteed by
+ * virtue of L1_CACHE_BYTES, requiring this to only be special cased
+ * for slab caches.
+ */
+#define ARCH_SLAB_MINALIGN      8
+#endif
+
+#endif /* __ASM_SH_PAGE_H */
diff --git a/arch/sh/include/asm/param.h b/arch/sh/include/asm/param.h
new file mode 100644
index 000000000000..ae245afdfd6a
--- /dev/null
+++ b/arch/sh/include/asm/param.h
@@ -0,0 +1,22 @@
+#ifndef __ASM_SH_PARAM_H
+#define __ASM_SH_PARAM_H
+
+#ifdef __KERNEL__
+# define HZ             CONFIG_HZ
+# define USER_HZ        100             /* User interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)       /* frequency at which times() counts */
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   4096
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif /* __ASM_SH_PARAM_H */
diff --git a/arch/sh/include/asm/parport.h b/arch/sh/include/asm/parport.h
new file mode 100644
index 000000000000..f67ba60a2acd
--- /dev/null
+++ b/arch/sh/include/asm/parport.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+#ifndef __ASM_SH_PARPORT_H
+#define __ASM_SH_PARPORT_H
+
+static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
+
+static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
+{
+        return parport_pc_find_isa_ports(autoirq, autodma);
+}
+
+#endif /* __ASM_SH_PARPORT_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
new file mode 100644
index 000000000000..df1d383e18a5
--- /dev/null
+++ b/arch/sh/include/asm/pci.h
@@ -0,0 +1,144 @@
+#ifndef __ASM_SH_PCI_H
+#define __ASM_SH_PCI_H
+
+#ifdef __KERNEL__
+
+#include <linux/dma-mapping.h>
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+   already-configured bus numbers - to be used for buggy BIOSes
+   or architectures with incomplete PCI setup by the loader */
+
+#define pcibios_assign_all_busses()     1
+#define pcibios_scan_all_fns(a, b)      0
+
+/*
+ * A board can define one or more PCI channels that represent built-in (or
+ * external) PCI controllers.
+ */
+struct pci_channel {
+        struct pci_ops *pci_ops;
+        struct resource *io_resource;
+        struct resource *mem_resource;
+        int first_devfn;
+        int last_devfn;
+};
+
+/*
+ * Each board initializes this array and terminates it with a NULL entry.
+ */
+extern struct pci_channel board_pci_channels[];
+
+#define PCIBIOS_MIN_IO          board_pci_channels->io_resource->start
+#define PCIBIOS_MIN_MEM         board_pci_channels->mem_resource->start
+
+/*
+ * I/O routine helpers
+ */
+#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
+#define PCI_IO_AREA             0xFE400000
+#define PCI_IO_SIZE             0x00400000
+#elif defined(CONFIG_CPU_SH5)
+extern unsigned long PCI_IO_AREA;
+#define PCI_IO_SIZE             0x00010000
+#else
+#define PCI_IO_AREA             0xFE240000
+#define PCI_IO_SIZE             0x00040000
+#endif
+
+#define PCI_MEM_SIZE            0x01000000
+
+#define SH4_PCIIOBR_MASK        0xFFFC0000
+#define pci_ioaddr(addr)        (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
+
+#if defined(CONFIG_PCI)
+#define is_pci_ioaddr(port)             \
+        (((port) >= PCIBIOS_MIN_IO) &&  \
+         ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
+#define is_pci_memaddr(port)            \
+        (((port) >= PCIBIOS_MIN_MEM) && \
+         ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
+#else
+#define is_pci_ioaddr(port)     (0)
+#define is_pci_memaddr(port)    (0)
+#endif
+
+struct pci_dev;
+
+extern void pcibios_set_master(struct pci_dev *dev);
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/* Dynamic DMA mapping stuff.
+ * SuperH has everything mapped statically like x86.
+ */
+
+/* The PCI address space does equal the physical memory
+ * address space.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (1)
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/scatterlist.h>
+#include <linux/string.h>
+#include <asm/io.h>
+
+/* pci_unmap_{single,page} being a nop depends upon the
+ * configuration.
+ */
+#ifdef CONFIG_SH_PCIDMA_NONCOHERENT
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+#else
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+#endif
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
+/* Board-specific fixup routines. */
+void pcibios_fixup(void);
+int pcibios_init_platform(void);
+int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
+
+#ifdef CONFIG_PCI_AUTO
+int pciauto_assign_resources(int busno, struct pci_channel *hose);
+#endif
+
+#endif /* __KERNEL__ */
+
+/* generic pci stuff */
+#include <asm-generic/pci.h>
+
+/* generic DMA-mapping stuff */
+#include <asm-generic/pci-dma-compat.h>
+
+#endif /* __ASM_SH_PCI_H */
+
diff --git a/arch/sh/include/asm/percpu.h b/arch/sh/include/asm/percpu.h
new file mode 100644
index 000000000000..4db4b39a4399
--- /dev/null
+++ b/arch/sh/include/asm/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ARCH_SH_PERCPU
+#define __ARCH_SH_PERCPU
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_SH_PERCPU */
diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h
new file mode 100644
index 000000000000..84dd2db7104c
--- /dev/null
+++ b/arch/sh/include/asm/pgalloc.h
@@ -0,0 +1,96 @@
+#ifndef __ASM_SH_PGALLOC_H
+#define __ASM_SH_PGALLOC_H
+
+#include <linux/quicklist.h>
+#include <asm/page.h>
+
+#define QUICK_PGD 0     /* We preserve special mappings over free */
+#define QUICK_PT 1      /* Other page table pages that are zero on free */
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+                                       pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+                                pgtable_t pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+static inline void pgd_ctor(void *x)
+{
+        pgd_t *pgd = x;
+
+        memcpy(pgd + USER_PTRS_PER_PGD,
+               swapper_pg_dir + USER_PTRS_PER_PGD,
+               (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+}
+
+/*
+ * Allocate and free page tables.
+ */
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
+}
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        quicklist_free(QUICK_PGD, NULL, pgd);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long address)
+{
+        return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+                                        unsigned long address)
+{
+        struct page *page;
+        void *pg;
+
+        pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
+        if (!pg)
+                return NULL;
+        page = virt_to_page(pg);
+        pgtable_page_ctor(page);
+        return page;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        quicklist_free(QUICK_PT, NULL, pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+{
+        pgtable_page_dtor(pte);
+        quicklist_free_page(QUICK_PT, NULL, pte);
+}
+
+#define __pte_free_tlb(tlb,pte)                         \
+do {                                                    \
+        pgtable_page_dtor(pte);                         \
+        tlb_remove_page((tlb), (pte));                  \
+} while (0)
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+
+#define pmd_free(mm, x)                 do { } while (0)
+#define __pmd_free_tlb(tlb,x)           do { } while (0)
+
+static inline void check_pgt_cache(void)
+{
+        quicklist_trim(QUICK_PGD, NULL, 25, 16);
+        quicklist_trim(QUICK_PT, NULL, 25, 16);
+}
+
+#endif /* __ASM_SH_PGALLOC_H */
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
new file mode 100644
index 000000000000..a4a8f8b93463
--- /dev/null
+++ b/arch/sh/include/asm/pgtable.h
@@ -0,0 +1,152 @@
+/*
+ * This file contains the functions and defines necessary to modify and
+ * use the SuperH page table tree.
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2002 - 2007 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ */
+#ifndef __ASM_SH_PGTABLE_H
+#define __ASM_SH_PGTABLE_H
+
+#include <asm-generic/pgtable-nopmd.h>
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/addrspace.h>
+#include <asm/fixmap.h>
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Effective and physical address definitions, to aid with sign
+ * extension.
+ */
+#define NEFF            32
+#define NEFF_SIGN       (1LL << (NEFF - 1))
+#define NEFF_MASK       (-1LL << NEFF)
+
+#ifdef CONFIG_29BIT
+#define NPHYS           29
+#else
+#define NPHYS           32
+#endif
+
+#define NPHYS_SIGN      (1LL << (NPHYS - 1))
+#define NPHYS_MASK      (-1LL << NPHYS)
+
+/*
+ * traditional two-level paging structure
+ */
+/* PTE bits */
+#if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
+# define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
+#else
+# define PTE_MAGNITUDE  2       /* 32-bit PTEs */
+#endif
+#define PTE_SHIFT       PAGE_SHIFT
+#define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
+
+/* PGD bits */
+#define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/* Entries per level */
+#define PTRS_PER_PTE    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
+#define PTRS_PER_PGD    (PAGE_SIZE / sizeof(pgd_t))
+
+#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
+#define FIRST_USER_ADDRESS      0
+
+#ifdef CONFIG_32BIT
+#define PHYS_ADDR_MASK          0xffffffff
+#else
+#define PHYS_ADDR_MASK          0x1fffffff
+#endif
+
+#define PTE_PHYS_MASK           (PHYS_ADDR_MASK & PAGE_MASK)
+
+#ifdef CONFIG_SUPERH32
+#define VMALLOC_START   (P3SEG)
+#else
+#define VMALLOC_START   (0xf0000000)
+#endif
+#define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
+
+#if defined(CONFIG_SUPERH32)
+#include <asm/pgtable_32.h>
+#else
+#include <asm/pgtable_64.h>
+#endif
+
+/*
+ * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
+ * protection for execute, and considers it the same as a read. Also, write
+ * permission implies read permission. This is the closest we can get..
+ *
+ * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
+ * not only supporting separate execute, read, and write bits, but having
+ * completely separate permission bits for user and kernel space.
+ */
+         /*xwr*/
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_EXECREAD
+#define __P101  PAGE_EXECREAD
+#define __P110  PAGE_COPY
+#define __P111  PAGE_COPY
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_WRITEONLY
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_EXECREAD
+#define __S101  PAGE_EXECREAD
+#define __S110  PAGE_RWX
+#define __S111  PAGE_RWX
+
+typedef pte_t *pte_addr_t;
+
+#define kern_addr_valid(addr)   (1)
+
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+
+#define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
+        defined(CONFIG_SH7705_CACHE_32KB))
+struct mm_struct;
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
+#endif
+
+struct vm_area_struct;
+extern void update_mmu_cache(struct vm_area_struct * vma,
+                             unsigned long address, pte_t pte);
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern void paging_init(void);
+extern void page_table_range_init(unsigned long start, unsigned long end,
+                                  pgd_t *pgd);
+
+#include <asm-generic/pgtable.h>
+
+#endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
new file mode 100644
index 000000000000..72ea209195bd
--- /dev/null
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -0,0 +1,479 @@
+#ifndef __ASM_SH_PGTABLE_32_H
+#define __ASM_SH_PGTABLE_32_H
+
+/*
+ * Linux PTEL encoding.
+ *
+ * Hardware and software bit definitions for the PTEL value (see below for
+ * notes on SH-X2 MMUs and 64-bit PTEs):
+ *
+ * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
+ *
+ * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
+ *   hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
+ *   which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
+ *
+ *   In order to keep this relatively clean, do not use these for defining
+ *   SH-3 specific flags until all of the other unused bits have been
+ *   exhausted.
+ *
+ * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
+ *
+ * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
+ *   Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
+ *
+ * - On 29 bit platforms, bits 31 to 29 are used for the space attributes
+ *   and timing control which (together with bit 0) are moved into the
+ *   old-style PTEA on the parts that support it.
+ *
+ * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
+ *
+ * SH-X2 MMUs and extended PTEs
+ *
+ * SH-X2 supports an extended mode TLB with split data arrays due to the
+ * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
+ * SZ bit placeholders still exist in data array 1, but are implemented as
+ * reserved bits, with the real logic existing in data array 2.
+ *
+ * The downside to this is that we can no longer fit everything in to a 32-bit
+ * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
+ * side, this gives us quite a few spare bits to play with for future usage.
+ */
+/* Legacy and compat mode bits */
+#define _PAGE_WT        0x001           /* WT-bit on SH-4, 0 on SH-3 */
+#define _PAGE_HW_SHARED 0x002           /* SH-bit  : shared among processes */
+#define _PAGE_DIRTY     0x004           /* D-bit   : page changed */
+#define _PAGE_CACHABLE  0x008           /* C-bit   : cachable */
+#define _PAGE_SZ0       0x010           /* SZ0-bit : Size of page */
+#define _PAGE_RW        0x020           /* PR0-bit : write access allowed */
+#define _PAGE_USER      0x040           /* PR1-bit : user space access allowed*/
+#define _PAGE_SZ1       0x080           /* SZ1-bit : Size of page (on SH-4) */
+#define _PAGE_PRESENT   0x100           /* V-bit   : page is valid */
+#define _PAGE_PROTNONE  0x200           /* software: if not present  */
+#define _PAGE_ACCESSED  0x400           /* software: page referenced */
+#define _PAGE_FILE      _PAGE_WT        /* software: pagecache or swap? */
+
+#define _PAGE_SZ_MASK   (_PAGE_SZ0 | _PAGE_SZ1)
+#define _PAGE_PR_MASK   (_PAGE_RW | _PAGE_USER)
+
+/* Extended mode bits */
+#define _PAGE_EXT_ESZ0          0x0010  /* ESZ0-bit: Size of page */
+#define _PAGE_EXT_ESZ1          0x0020  /* ESZ1-bit: Size of page */
+#define _PAGE_EXT_ESZ2          0x0040  /* ESZ2-bit: Size of page */
+#define _PAGE_EXT_ESZ3          0x0080  /* ESZ3-bit: Size of page */
+
+#define _PAGE_EXT_USER_EXEC     0x0100  /* EPR0-bit: User space executable */
+#define _PAGE_EXT_USER_WRITE    0x0200  /* EPR1-bit: User space writable */
+#define _PAGE_EXT_USER_READ     0x0400  /* EPR2-bit: User space readable */
+
+#define _PAGE_EXT_KERN_EXEC     0x0800  /* EPR3-bit: Kernel space executable */
+#define _PAGE_EXT_KERN_WRITE    0x1000  /* EPR4-bit: Kernel space writable */
+#define _PAGE_EXT_KERN_READ     0x2000  /* EPR5-bit: Kernel space readable */
+
+/* Wrapper for extended mode pgprot twiddling */
+#define _PAGE_EXT(x)            ((unsigned long long)(x) << 32)
+
+/* software: moves to PTEA.TC (Timing Control) */
+#define _PAGE_PCC_AREA5 0x00000000      /* use BSC registers for area5 */
+#define _PAGE_PCC_AREA6 0x80000000      /* use BSC registers for area6 */
+
+/* software: moves to PTEA.SA[2:0] (Space Attributes) */
+#define _PAGE_PCC_IODYN 0x00000001      /* IO space, dynamically sized bus */
+#define _PAGE_PCC_IO8   0x20000000      /* IO space, 8 bit bus */
+#define _PAGE_PCC_IO16  0x20000001      /* IO space, 16 bit bus */
+#define _PAGE_PCC_COM8  0x40000000      /* Common Memory space, 8 bit bus */
+#define _PAGE_PCC_COM16 0x40000001      /* Common Memory space, 16 bit bus */
+#define _PAGE_PCC_ATR8  0x60000000      /* Attribute Memory space, 8 bit bus */
+#define _PAGE_PCC_ATR16 0x60000001      /* Attribute Memory space, 6 bit bus */
+
+/* Mask which drops unused bits from the PTEL value */
+#if defined(CONFIG_CPU_SH3)
+#define _PAGE_CLEAR_FLAGS       (_PAGE_PROTNONE | _PAGE_ACCESSED| \
+                                 _PAGE_FILE     | _PAGE_SZ1     | \
+                                 _PAGE_HW_SHARED)
+#elif defined(CONFIG_X2TLB)
+/* Get rid of the legacy PR/SZ bits when using extended mode */
+#define _PAGE_CLEAR_FLAGS       (_PAGE_PROTNONE | _PAGE_ACCESSED | \
+                                 _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
+#else
+#define _PAGE_CLEAR_FLAGS       (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
+#endif
+
+#define _PAGE_FLAGS_HARDWARE_MASK       (PHYS_ADDR_MASK & ~(_PAGE_CLEAR_FLAGS))
+
+/* Hardware flags, page size encoding */
+#if !defined(CONFIG_MMU)
+# define _PAGE_FLAGS_HARD       0ULL
+#elif defined(CONFIG_X2TLB)
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ0)
+# elif defined(CONFIG_PAGE_SIZE_8KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ1)
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_EXT(_PAGE_EXT_ESZ2)
+# endif
+#else
+# if defined(CONFIG_PAGE_SIZE_4KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ0
+# elif defined(CONFIG_PAGE_SIZE_64KB)
+#  define _PAGE_FLAGS_HARD      _PAGE_SZ1
+# endif
+#endif
+
+#if defined(CONFIG_X2TLB)
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ3)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
+#  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
+# endif
+#else
+# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#  define _PAGE_SZHUGE  (_PAGE_SZ1)
+# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#  define _PAGE_SZHUGE  (_PAGE_SZ0 | _PAGE_SZ1)
+# endif
+#endif
+
+/*
+ * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
+ * to make pte_mkhuge() happy.
+ */
+#ifndef _PAGE_SZHUGE
+# define _PAGE_SZHUGE   (_PAGE_FLAGS_HARD)
+#endif
+
+#define _PAGE_CHG_MASK \
+        (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ  | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_USER_READ  | \
+                                           _PAGE_EXT_USER_WRITE))
+
+#define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
+                                           _PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_USER_EXEC | \
+                                           _PAGE_EXT_USER_READ))
+
+#define PAGE_COPY       PAGE_EXECREAD
+
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_USER_READ))
+
+#define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_USER_WRITE))
+
+#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                                 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_READ  | \
+                                           _PAGE_EXT_KERN_EXEC  | \
+                                           _PAGE_EXT_USER_WRITE | \
+                                           _PAGE_EXT_USER_READ  | \
+                                           _PAGE_EXT_USER_EXEC))
+
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
+
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC))
+
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_EXEC))
+
+#define PAGE_KERNEL_PCC(slot, type) \
+                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
+                                           _PAGE_EXT_KERN_WRITE | \
+                                           _PAGE_EXT_KERN_EXEC) \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
+
+#elif defined(CONFIG_MMU) /* SH-X TLB */
+#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
+                                 _PAGE_CACHABLE | _PAGE_ACCESSED | \
+                                 _PAGE_FLAGS_HARD)
+
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
+
+#define PAGE_EXECREAD   PAGE_READONLY
+#define PAGE_RWX        PAGE_SHARED
+#define PAGE_WRITEONLY  PAGE_SHARED
+
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
+                                 _PAGE_FLAGS_HARD)
+
+#define PAGE_KERNEL_RO  __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | \
+                                 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
+
+#define PAGE_KERNEL_PCC(slot, type) \
+                        __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
+                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
+                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
+                                 (type))
+#else /* no mmu */
+#define PAGE_NONE               __pgprot(0)
+#define PAGE_SHARED             __pgprot(0)
+#define PAGE_COPY               __pgprot(0)
+#define PAGE_EXECREAD           __pgprot(0)
+#define PAGE_RWX                __pgprot(0)
+#define PAGE_READONLY           __pgprot(0)
+#define PAGE_WRITEONLY          __pgprot(0)
+#define PAGE_KERNEL             __pgprot(0)
+#define PAGE_KERNEL_NOCACHE     __pgprot(0)
+#define PAGE_KERNEL_RO          __pgprot(0)
+
+#define PAGE_KERNEL_PCC(slot, type) \
+                                __pgprot(0)
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Certain architectures need to do special things when PTEs
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+#ifdef CONFIG_X2TLB
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+        ptep->pte_high = pte.pte_high;
+        smp_wmb();
+        ptep->pte_low = pte.pte_low;
+}
+#else
+#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#endif
+
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+/*
+ * (pmds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
+
+#define pfn_pte(pfn, prot) \
+        __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot) \
+        __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+#define pte_none(x)             (!pte_val(x))
+#define pte_present(x)          ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
+
+#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
+
+#define pmd_none(x)     (!pmd_val(x))
+#define pmd_present(x)  (pmd_val(x))
+#define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
+#define pmd_bad(x)      (pmd_val(x) & ~PAGE_MASK)
+
+#define pages_to_mb(x)  ((x) >> (20-PAGE_SHIFT))
+#define pte_page(x)     pfn_to_page(pte_pfn(x))
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+#define pte_not_present(pte)    (!((pte).pte_low & _PAGE_PRESENT))
+#define pte_dirty(pte)          ((pte).pte_low & _PAGE_DIRTY)
+#define pte_young(pte)          ((pte).pte_low & _PAGE_ACCESSED)
+#define pte_file(pte)           ((pte).pte_low & _PAGE_FILE)
+#define pte_special(pte)        (0)
+
+#ifdef CONFIG_X2TLB
+#define pte_write(pte)          ((pte).pte_high & _PAGE_EXT_USER_WRITE)
+#else
+#define pte_write(pte)          ((pte).pte_low & _PAGE_RW)
+#endif
+
+#define PTE_BIT_FUNC(h,fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
+
+#ifdef CONFIG_X2TLB
+/*
+ * We cheat a bit in the SH-X2 TLB case. As the permission bits are
+ * individually toggled (and user permissions are entirely decoupled from
+ * kernel permissions), we attempt to couple them a bit more sanely here.
+ */
+PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
+PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
+PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
+#else
+PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
+PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
+PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
+#endif
+
+PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
+PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
+PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
+
+static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
+
+/*
+ * Macro and implementation to make a page protection as uncachable.
+ */
+#define pgprot_writecombine(prot) \
+        __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
+
+#define pgprot_noncached         pgprot_writecombine
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ *
+ * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
+ */
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte.pte_low &= _PAGE_CHG_MASK;
+        pte.pte_low |= pgprot_val(newprot);
+
+#ifdef CONFIG_X2TLB
+        pte.pte_high |= pgprot_val(newprot) >> 32;
+#endif
+
+        return pte;
+}
+
+#define pmd_page_vaddr(pmd)     ((unsigned long)pmd_val(pmd))
+#define pmd_page(pmd)           (virt_to_page(pmd_val(pmd)))
+
+/* to find an entry in a page-table-directory. */
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address)   pgd_offset(&init_mm, address)
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(address)      ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, address) \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
+#define pte_offset_map(dir, address)            pte_offset_kernel(dir, address)
+#define pte_offset_map_nested(dir, address)     pte_offset_kernel(dir, address)
+
+#define pte_unmap(pte)          do { } while (0)
+#define pte_unmap_nested(pte)   do { } while (0)
+
+#ifdef CONFIG_X2TLB
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
+               &(e), (e).pte_high, (e).pte_low)
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
+#else
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+#endif
+
+/*
+ * Encode and de-code a swap entry
+ *
+ * Constraints:
+ *      _PAGE_FILE at bit 0
+ *      _PAGE_PRESENT at bit 8
+ *      _PAGE_PROTNONE at bit 9
+ *
+ * For the normal case, we encode the swap type into bits 0:7 and the
+ * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
+ * preserved bits in the low 32-bits and use the upper 32 as the swap
+ * offset (along with a 5-bit type), following the same approach as x86
+ * PAE. This keeps the logic quite simple, and allows for a full 32
+ * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
+ * in the pte_low case.
+ *
+ * As is evident by the Alpha code, if we ever get a 64-bit unsigned
+ * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
+ * much cleaner..
+ *
+ * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
+ *       and _PAGE_PROTNONE bits
+ */
+#ifdef CONFIG_X2TLB
+#define __swp_type(x)                   ((x).val & 0x1f)
+#define __swp_offset(x)                 ((x).val >> 5)
+#define __swp_entry(type, offset)       ((swp_entry_t){ (type) | (offset) << 5})
+#define __pte_to_swp_entry(pte)         ((swp_entry_t){ (pte).pte_high })
+#define __swp_entry_to_pte(x)           ((pte_t){ 0, (x).val })
+
+/*
+ * Encode and decode a nonlinear file mapping entry
+ */
+#define pte_to_pgoff(pte)               ((pte).pte_high)
+#define pgoff_to_pte(off)               ((pte_t) { _PAGE_FILE, (off) })
+
+#define PTE_FILE_MAX_BITS               32
+#else
+#define __swp_type(x)                   ((x).val & 0xff)
+#define __swp_offset(x)                 ((x).val >> 10)
+#define __swp_entry(type, offset)       ((swp_entry_t){(type) | (offset) <<10})
+
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 1 })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 1 })
+
+/*
+ * Encode and decode a nonlinear file mapping entry
+ */
+#define PTE_FILE_MAX_BITS       29
+#define pte_to_pgoff(pte)       (pte_val(pte) >> 1)
+#define pgoff_to_pte(off)       ((pte_t) { ((off) << 1) | _PAGE_FILE })
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_PGTABLE_32_H */
diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h
new file mode 100644
index 000000000000..c78990cda557
--- /dev/null
+++ b/arch/sh/include/asm/pgtable_64.h
@@ -0,0 +1,314 @@
+#ifndef __ASM_SH_PGTABLE_64_H
+#define __ASM_SH_PGTABLE_64_H
+
+/*
+ * include/asm-sh/pgtable_64.h
+ *
+ * This file contains the functions and defines necessary to modify and use
+ * the SuperH page table tree.
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ * Copyright (C) 2003, 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/threads.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+
+/*
+ * Error outputs.
+ */
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * Table setting routines. Used within arch/mm only.
+ */
+#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
+
+static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
+{
+        unsigned long long x = ((unsigned long long) pteval.pte_low);
+        unsigned long long *xp = (unsigned long long *) pteptr;
+        /*
+         * Sign-extend based on NPHYS.
+         */
+        *(xp) = (x & NPHYS_SIGN) ? (x | NPHYS_MASK) : x;
+}
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
+{
+        pmd_val(*pmdp) = (unsigned long) ptep;
+}
+
+/*
+ * PGD defines. Top level.
+ */
+
+/* To find an entry in a generic PGD. */
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define __pgd_offset(address) pgd_index(address)
+#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
+
+/* To find an entry in a kernel PGD. */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/*
+ * PMD level access routines. Same notes as above.
+ */
+#define _PMD_EMPTY              0x0
+/* Either the PMD is empty or present, it's not paged out */
+#define pmd_present(pmd_entry)  (pmd_val(pmd_entry) & _PAGE_PRESENT)
+#define pmd_clear(pmd_entry_p)  (set_pmd((pmd_entry_p), __pmd(_PMD_EMPTY)))
+#define pmd_none(pmd_entry)     (pmd_val((pmd_entry)) == _PMD_EMPTY)
+#define pmd_bad(pmd_entry)      ((pmd_val(pmd_entry) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
+
+#define pmd_page_vaddr(pmd_entry) \
+        ((unsigned long) __va(pmd_val(pmd_entry) & PAGE_MASK))
+
+#define pmd_page(pmd) \
+        (virt_to_page(pmd_val(pmd)))
+
+/* PMD to PTE dereferencing */
+#define pte_index(address) \
+                ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+
+#define pte_offset_kernel(dir, addr) \
+                ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
+
+#define pte_offset_map(dir,addr)        pte_offset_kernel(dir, addr)
+#define pte_offset_map_nested(dir,addr) pte_offset_kernel(dir, addr)
+#define pte_unmap(pte)          do { } while (0)
+#define pte_unmap_nested(pte)   do { } while (0)
+
+#ifndef __ASSEMBLY__
+#define IOBASE_VADDR    0xff000000
+#define IOBASE_END      0xffffffff
+
+/*
+ * PTEL coherent flags.
+ * See Chapter 17 ST50 CPU Core Volume 1, Architecture.
+ */
+/* The bits that are required in the SH-5 TLB are placed in the h/w-defined
+   positions, to avoid expensive bit shuffling on every refill.  The remaining
+   bits are used for s/w purposes and masked out on each refill.
+
+   Note, the PTE slots are used to hold data of type swp_entry_t when a page is
+   swapped out.  Only the _PAGE_PRESENT flag is significant when the page is
+   swapped out, and it must be placed so that it doesn't overlap either the
+   type or offset fields of swp_entry_t.  For x86, offset is at [31:8] and type
+   at [6:1], with _PAGE_PRESENT at bit 0 for both pte_t and swp_entry_t.  This
+   scheme doesn't map to SH-5 because bit [0] controls cacheability.  So bit
+   [2] is used for _PAGE_PRESENT and the type field of swp_entry_t is split
+   into 2 pieces.  That is handled by SWP_ENTRY and SWP_TYPE below. */
+#define _PAGE_WT        0x001  /* CB0: if cacheable, 1->write-thru, 0->write-back */
+#define _PAGE_DEVICE    0x001  /* CB0: if uncacheable, 1->device (i.e. no write-combining or reordering at bus level) */
+#define _PAGE_CACHABLE  0x002  /* CB1: uncachable/cachable */
+#define _PAGE_PRESENT   0x004  /* software: page referenced */
+#define _PAGE_FILE      0x004  /* software: only when !present */
+#define _PAGE_SIZE0     0x008  /* SZ0-bit : size of page */
+#define _PAGE_SIZE1     0x010  /* SZ1-bit : size of page */
+#define _PAGE_SHARED    0x020  /* software: reflects PTEH's SH */
+#define _PAGE_READ      0x040  /* PR0-bit : read access allowed */
+#define _PAGE_EXECUTE   0x080  /* PR1-bit : execute access allowed */
+#define _PAGE_WRITE     0x100  /* PR2-bit : write access allowed */
+#define _PAGE_USER      0x200  /* PR3-bit : user space access allowed */
+#define _PAGE_DIRTY     0x400  /* software: page accessed in write */
+#define _PAGE_ACCESSED  0x800  /* software: page referenced */
+
+/* Mask which drops software flags */
+#define _PAGE_FLAGS_HARDWARE_MASK       0xfffffffffffff3dbLL
+
+/*
+ * HugeTLB support
+ */
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define _PAGE_SZHUGE    (_PAGE_SIZE0)
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
+#define _PAGE_SZHUGE    (_PAGE_SIZE1)
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
+#define _PAGE_SZHUGE    (_PAGE_SIZE0 | _PAGE_SIZE1)
+#endif
+
+/*
+ * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
+ * to make pte_mkhuge() happy.
+ */
+#ifndef _PAGE_SZHUGE
+# define _PAGE_SZHUGE   (0)
+#endif
+
+/*
+ * Default flags for a Kernel page.
+ * This is fundametally also SHARED because the main use of this define
+ * (other than for PGD/PMD entries) is for the VMALLOC pool which is
+ * contextless.
+ *
+ * _PAGE_EXECUTE is required for modules
+ *
+ */
+#define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                         _PAGE_EXECUTE | \
+                         _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_DIRTY | \
+                         _PAGE_SHARED)
+
+/* Default flags for a User page */
+#define _PAGE_TABLE     (_KERNPG_TABLE | _PAGE_USER)
+
+#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+
+/*
+ * We have full permissions (Read/Write/Execute/Shared).
+ */
+#define _PAGE_COMMON    (_PAGE_PRESENT | _PAGE_USER | \
+                         _PAGE_CACHABLE | _PAGE_ACCESSED)
+
+#define PAGE_NONE       __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED)
+#define PAGE_SHARED     __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_WRITE | \
+                                 _PAGE_SHARED)
+#define PAGE_EXECREAD   __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_EXECUTE)
+
+/*
+ * We need to include PAGE_EXECUTE in PAGE_COPY because it is the default
+ * protection mode for the stack.
+ */
+#define PAGE_COPY       PAGE_EXECREAD
+
+#define PAGE_READONLY   __pgprot(_PAGE_COMMON | _PAGE_READ)
+#define PAGE_WRITEONLY  __pgprot(_PAGE_COMMON | _PAGE_WRITE)
+#define PAGE_RWX        __pgprot(_PAGE_COMMON | _PAGE_READ | \
+                                 _PAGE_WRITE | _PAGE_EXECUTE)
+#define PAGE_KERNEL     __pgprot(_KERNPG_TABLE)
+
+#define PAGE_KERNEL_NOCACHE \
+                        __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                                 _PAGE_EXECUTE | _PAGE_ACCESSED | \
+                                 _PAGE_DIRTY | _PAGE_SHARED)
+
+/* Make it a device mapping for maximum safety (e.g. for mapping device
+   registers into user-space via /dev/map).  */
+#define pgprot_noncached(x) __pgprot(((x).pgprot & ~(_PAGE_CACHABLE)) | _PAGE_DEVICE)
+#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
+
+/*
+ * Handling allocation failures during page table setup.
+ */
+extern void __handle_bad_pmd_kernel(pmd_t * pmd);
+#define __handle_bad_pmd(x)     __handle_bad_pmd_kernel(x)
+
+/*
+ * PTE level access routines.
+ *
+ * Note1:
+ * It's the tree walk leaf. This is physical address to be stored.
+ *
+ * Note 2:
+ * Regarding the choice of _PTE_EMPTY:
+
+   We must choose a bit pattern that cannot be valid, whether or not the page
+   is present.  bit[2]==1 => present, bit[2]==0 => swapped out.  If swapped
+   out, bits [31:8], [6:3], [1:0] are under swapper control, so only bit[7] is
+   left for us to select.  If we force bit[7]==0 when swapped out, we could use
+   the combination bit[7,2]=2'b10 to indicate an empty PTE.  Alternatively, if
+   we force bit[7]==1 when swapped out, we can use all zeroes to indicate
+   empty.  This is convenient, because the page tables get cleared to zero
+   when they are allocated.
+
+ */
+#define _PTE_EMPTY      0x0
+#define pte_present(x)  (pte_val(x) & _PAGE_PRESENT)
+#define pte_clear(mm,addr,xp)   (set_pte_at(mm, addr, xp, __pte(_PTE_EMPTY)))
+#define pte_none(x)     (pte_val(x) == _PTE_EMPTY)
+
+/*
+ * Some definitions to translate between mem_map, PTEs, and page
+ * addresses:
+ */
+
+/*
+ * Given a PTE, return the index of the mem_map[] entry corresponding
+ * to the page frame the PTE. Get the absolute physical address, make
+ * a relative physical address and translate it to an index.
+ */
+#define pte_pagenr(x)           (((unsigned long) (pte_val(x)) - \
+                                 __MEMORY_START) >> PAGE_SHIFT)
+
+/*
+ * Given a PTE, return the "struct page *".
+ */
+#define pte_page(x)             (mem_map + pte_pagenr(x))
+
+/*
+ * Return number of (down rounded) MB corresponding to x pages.
+ */
+#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
+
+
+/*
+ * The following have defined behavior only work if pte_present() is true.
+ */
+static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)   { return pte_val(pte) & _PAGE_FILE; }
+static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_special(pte_t pte){ return 0; }
+
+static inline pte_t pte_wrprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
+static inline pte_t pte_mkclean(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
+static inline pte_t pte_mkold(pte_t pte)        { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
+static inline pte_t pte_mkwrite(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; }
+static inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
+static inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
+static inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
+static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
+
+
+/*
+ * Conversion functions: convert a page and protection to a page entry.
+ *
+ * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
+ */
+#define mk_pte(page,pgprot)                                                     \
+({                                                                              \
+        pte_t __pte;                                                            \
+                                                                                \
+        set_pte(&__pte, __pte((((page)-mem_map) << PAGE_SHIFT) |                \
+                __MEMORY_START | pgprot_val((pgprot))));                        \
+        __pte;                                                                  \
+})
+
+/*
+ * This takes a (absolute) physical page address that is used
+ * by the remapping functions
+ */
+#define mk_pte_phys(physpage, pgprot) \
+({ pte_t __pte; set_pte(&__pte, __pte(physpage | pgprot_val(pgprot))); __pte; })
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
+
+/* Encode and decode a swap entry */
+#define __swp_type(x)                   (((x).val & 3) + (((x).val >> 1) & 0x3c))
+#define __swp_offset(x)                 ((x).val >> 8)
+#define __swp_entry(type, offset)       ((swp_entry_t) { ((offset << 8) + ((type & 0x3c) << 1) + (type & 3)) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
+
+/* Encode and decode a nonlinear file mapping entry */
+#define PTE_FILE_MAX_BITS               29
+#define pte_to_pgoff(pte)               (pte_val(pte))
+#define pgoff_to_pte(off)               ((pte_t) { (off) | _PAGE_FILE })
+
+#endif /* !__ASSEMBLY__ */
+
+#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot)      __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+#endif /* __ASM_SH_PGTABLE_64_H */
diff --git a/arch/sh/include/asm/pm.h b/arch/sh/include/asm/pm.h
new file mode 100644
index 000000000000..56fdbd6b1c94
--- /dev/null
+++ b/arch/sh/include/asm/pm.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 2006 (c) Andriy Skulysh <askulysh@gmail.com>
+ *
+ */
+#ifndef __ASM_SH_PM_H
+#define __ASM_SH_PM_H
+
+extern u8 wakeup_start;
+extern u8 wakeup_end;
+
+void pm_enter(void);
+
+#endif
diff --git a/arch/sh/include/asm/poll.h b/arch/sh/include/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/sh/include/asm/poll.h
@@ -0,0 +1 @@
+#include <asm-generic/poll.h>
diff --git a/arch/sh/include/asm/posix_types.h b/arch/sh/include/asm/posix_types.h
new file mode 100644
index 000000000000..4eeb723aee7e
--- /dev/null
+++ b/arch/sh/include/asm/posix_types.h
@@ -0,0 +1,13 @@
+#ifdef __KERNEL__
+# ifdef CONFIG_SUPERH32
+#  include "posix_types_32.h"
+# else
+#  include "posix_types_64.h"
+# endif
+#else
+# ifdef __SH5__
+#  include "posix_types_64.h"
+# else
+#  include "posix_types_32.h"
+# endif
+#endif /* __KERNEL__ */
diff --git a/arch/sh/include/asm/posix_types_32.h b/arch/sh/include/asm/posix_types_32.h
new file mode 100644
index 000000000000..0a3d2f54ab27
--- /dev/null
+++ b/arch/sh/include/asm/posix_types_32.h
@@ -0,0 +1,122 @@
+#ifndef __ASM_SH_POSIX_TYPES_H
+#define __ASM_SH_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned short  __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned short  __kernel_ipc_pid_t;
+typedef unsigned short  __kernel_uid_t;
+typedef unsigned short  __kernel_gid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+
+typedef unsigned short  __kernel_old_uid_t;
+typedef unsigned short  __kernel_old_gid_t;
+typedef unsigned short  __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+        int     val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+        int     __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef  __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef  __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef  __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{ 
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef  __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+        unsigned long *__tmp = __p->fds_bits;
+        int __i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                case 16:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        __tmp[ 8] = 0; __tmp[ 9] = 0;
+                        __tmp[10] = 0; __tmp[11] = 0;
+                        __tmp[12] = 0; __tmp[13] = 0;
+                        __tmp[14] = 0; __tmp[15] = 0;
+                        return;
+
+                case 8:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        return;
+
+                case 4:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        return;
+                }
+        }
+        __i = __FDSET_LONGS;
+        while (__i) {
+                __i--;
+                *__tmp = 0;
+                __tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH_POSIX_TYPES_H */
diff --git a/arch/sh/include/asm/posix_types_64.h b/arch/sh/include/asm/posix_types_64.h
new file mode 100644
index 000000000000..0620317a6f0f
--- /dev/null
+++ b/arch/sh/include/asm/posix_types_64.h
@@ -0,0 +1,131 @@
+#ifndef __ASM_SH64_POSIX_TYPES_H
+#define __ASM_SH64_POSIX_TYPES_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * include/asm-sh64/posix_types.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned short  __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned short  __kernel_ipc_pid_t;
+typedef unsigned short  __kernel_uid_t;
+typedef unsigned short  __kernel_gid_t;
+typedef long unsigned int       __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+
+typedef unsigned short  __kernel_old_uid_t;
+typedef unsigned short  __kernel_old_gid_t;
+typedef unsigned short  __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+        int     val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+        int     __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef  __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef  __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef  __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef  __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+        unsigned long *__tmp = __p->fds_bits;
+        int __i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                case 16:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        __tmp[ 8] = 0; __tmp[ 9] = 0;
+                        __tmp[10] = 0; __tmp[11] = 0;
+                        __tmp[12] = 0; __tmp[13] = 0;
+                        __tmp[14] = 0; __tmp[15] = 0;
+                        return;
+
+                case 8:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        return;
+
+                case 4:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        return;
+                }
+        }
+        __i = __FDSET_LONGS;
+        while (__i) {
+                __i--;
+                *__tmp = 0;
+                __tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH64_POSIX_TYPES_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
new file mode 100644
index 000000000000..15d9f92ca383
--- /dev/null
+++ b/arch/sh/include/asm/processor.h
@@ -0,0 +1,66 @@
+#ifndef __ASM_SH_PROCESSOR_H
+#define __ASM_SH_PROCESSOR_H
+
+#include <asm/cpu-features.h>
+#include <asm/segment.h>
+
+#ifndef __ASSEMBLY__
+/*
+ *  CPU type and hardware bug flags. Kept separately for each CPU.
+ *
+ *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
+ *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
+ *  for parsing the subtype in get_cpu_subtype().
+ */
+enum cpu_type {
+        /* SH-2 types */
+        CPU_SH7619,
+
+        /* SH-2A types */
+        CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
+
+        /* SH-3 types */
+        CPU_SH7705, CPU_SH7706, CPU_SH7707,
+        CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
+        CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
+        CPU_SH7720, CPU_SH7721, CPU_SH7729,
+
+        /* SH-4 types */
+        CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
+        CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
+
+        /* SH-4A types */
+        CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+        CPU_SH7723, CPU_SHX3,
+
+        /* SH4AL-DSP types */
+        CPU_SH7343, CPU_SH7722, CPU_SH7366,
+
+        /* SH-5 types */
+        CPU_SH5_101, CPU_SH5_103,
+
+        /* Unknown subtype */
+        CPU_SH_NONE
+};
+
+/* Forward decl */
+struct sh_cpuinfo;
+
+/* arch/sh/kernel/setup.c */
+const char *get_cpu_subtype(struct sh_cpuinfo *c);
+
+#ifdef CONFIG_VSYSCALL
+int vsyscall_init(void);
+#else
+#define vsyscall_init() do { } while (0)
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_SUPERH32
+# include "processor_32.h"
+#else
+# include "processor_64.h"
+#endif
+
+#endif /* __ASM_SH_PROCESSOR_H */
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
new file mode 100644
index 000000000000..0dadd75bd93c
--- /dev/null
+++ b/arch/sh/include/asm/processor_32.h
@@ -0,0 +1,216 @@
+/*
+ * include/asm-sh/processor.h
+ *
+ * Copyright (C) 1999, 2000  Niibe Yutaka
+ * Copyright (C) 2002, 2003  Paul Mundt
+ */
+
+#ifndef __ASM_SH_PROCESSOR_32_H
+#define __ASM_SH_PROCESSOR_32_H
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <asm/page.h>
+#include <asm/types.h>
+#include <asm/cache.h>
+#include <asm/ptrace.h>
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ void *pc; __asm__("mova  1f, %0\n.align 2\n1:":"=z" (pc)); pc; })
+
+/* Core Processor Version Register */
+#define CCN_PVR         0xff000030
+#define CCN_CVR         0xff000040
+#define CCN_PRR         0xff000044
+
+struct sh_cpuinfo {
+        unsigned int type;
+        int cut_major, cut_minor;
+        unsigned long loops_per_jiffy;
+        unsigned long asid_cache;
+
+        struct cache_info icache;       /* Primary I-cache */
+        struct cache_info dcache;       /* Primary D-cache */
+        struct cache_info scache;       /* Secondary cache */
+
+        unsigned long flags;
+} __attribute__ ((aligned(L1_CACHE_BYTES)));
+
+extern struct sh_cpuinfo cpu_data[];
+#define boot_cpu_data cpu_data[0]
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+
+/*
+ * User space process size: 2GB.
+ *
+ * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
+ */
+#define TASK_SIZE       0x7c000000UL
+
+#define STACK_TOP       TASK_SIZE
+#define STACK_TOP_MAX   STACK_TOP
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (TASK_SIZE / 3)
+
+/*
+ * Bit of SR register
+ *
+ * FD-bit:
+ *     When it's set, it means the processor doesn't have right to use FPU,
+ *     and it results exception when the floating operation is executed.
+ *
+ * IMASK-bit:
+ *     Interrupt level mask
+ */
+#define SR_DSP          0x00001000
+#define SR_IMASK        0x000000f0
+#define SR_FD           0x00008000
+
+/*
+ * FPU structure and data
+ */
+
+struct sh_fpu_hard_struct {
+        unsigned long fp_regs[16];
+        unsigned long xfp_regs[16];
+        unsigned long fpscr;
+        unsigned long fpul;
+
+        long status; /* software status information */
+};
+
+/* Dummy fpu emulator  */
+struct sh_fpu_soft_struct {
+        unsigned long fp_regs[16];
+        unsigned long xfp_regs[16];
+        unsigned long fpscr;
+        unsigned long fpul;
+
+        unsigned char lookahead;
+        unsigned long entry_pc;
+};
+
+union sh_fpu_union {
+        struct sh_fpu_hard_struct hard;
+        struct sh_fpu_soft_struct soft;
+};
+
+struct thread_struct {
+        /* Saved registers when thread is descheduled */
+        unsigned long sp;
+        unsigned long pc;
+
+        /* Hardware debugging registers */
+        unsigned long ubc_pc;
+
+        /* floating point info */
+        union sh_fpu_union fpu;
+};
+
+/* Count of active tasks with UBC settings */
+extern int ubc_usercnt;
+
+#define INIT_THREAD  {                                          \
+        .sp = sizeof(init_stack) + (long) &init_stack,          \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define start_thread(regs, new_pc, new_sp)       \
+        set_fs(USER_DS);                         \
+        regs->pr = 0;                            \
+        regs->sr = SR_FD;       /* User mode. */ \
+        regs->pc = new_pc;                       \
+        regs->regs[15] = new_sp
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+struct mm_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(p, mm)    do { } while(0)
+#define release_segments(mm)    do { } while(0)
+
+/*
+ * FPU lazy state save handling.
+ */
+
+static __inline__ void disable_fpu(void)
+{
+        unsigned long __dummy;
+
+        /* Set FD flag in SR */
+        __asm__ __volatile__("stc       sr, %0\n\t"
+                             "or        %1, %0\n\t"
+                             "ldc       %0, sr"
+                             : "=&r" (__dummy)
+                             : "r" (SR_FD));
+}
+
+static __inline__ void enable_fpu(void)
+{
+        unsigned long __dummy;
+
+        /* Clear out FD flag in SR */
+        __asm__ __volatile__("stc       sr, %0\n\t"
+                             "and       %1, %0\n\t"
+                             "ldc       %0, sr"
+                             : "=&r" (__dummy)
+                             : "r" (~SR_FD));
+}
+
+/* Double presision, NANS as NANS, rounding to nearest, no exceptions */
+#define FPSCR_INIT  0x00080000
+
+#define FPSCR_CAUSE_MASK        0x0001f000      /* Cause bits */
+#define FPSCR_FLAG_MASK         0x0000007c      /* Flag bits */
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+#define thread_saved_pc(tsk)    (tsk->thread.pc)
+
+void show_trace(struct task_struct *tsk, unsigned long *sp,
+                struct pt_regs *regs);
+extern unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)  (task_pt_regs(tsk)->pc)
+#define KSTK_ESP(tsk)  (task_pt_regs(tsk)->regs[15])
+
+#define cpu_sleep()     __asm__ __volatile__ ("sleep" : : : "memory")
+#define cpu_relax()     barrier()
+
+#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \
+    defined(CONFIG_CPU_SH4)
+#define PREFETCH_STRIDE         L1_CACHE_BYTES
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+static inline void prefetch(void *x)
+{
+        __asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory");
+}
+
+#define prefetchw(x)    prefetch(x)
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_PROCESSOR_32_H */
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
new file mode 100644
index 000000000000..770d5169983b
--- /dev/null
+++ b/arch/sh/include/asm/processor_64.h
@@ -0,0 +1,275 @@
+#ifndef __ASM_SH_PROCESSOR_64_H
+#define __ASM_SH_PROCESSOR_64_H
+
+/*
+ * include/asm-sh/processor_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003  Paul Mundt
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <asm/page.h>
+#include <asm/types.h>
+#include <asm/cache.h>
+#include <asm/ptrace.h>
+#include <cpu/registers.h>
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ \
+void *pc; \
+unsigned long long __dummy = 0; \
+__asm__("gettr  tr0, %1\n\t" \
+        "pta    4, tr0\n\t" \
+        "gettr  tr0, %0\n\t" \
+        "ptabs  %1, tr0\n\t"    \
+        :"=r" (pc), "=r" (__dummy) \
+        : "1" (__dummy)); \
+pc; })
+
+/*
+ * TLB information structure
+ *
+ * Defined for both I and D tlb, per-processor.
+ */
+struct tlb_info {
+        unsigned long long next;
+        unsigned long long first;
+        unsigned long long last;
+
+        unsigned int entries;
+        unsigned int step;
+
+        unsigned long flags;
+};
+
+struct sh_cpuinfo {
+        enum cpu_type type;
+        unsigned long loops_per_jiffy;
+        unsigned long asid_cache;
+
+        unsigned int cpu_clock, master_clock, bus_clock, module_clock;
+
+        /* Cache info */
+        struct cache_info icache;
+        struct cache_info dcache;
+        struct cache_info scache;
+
+        /* TLB info */
+        struct tlb_info itlb;
+        struct tlb_info dtlb;
+
+        unsigned long flags;
+};
+
+extern struct sh_cpuinfo cpu_data[];
+#define boot_cpu_data cpu_data[0]
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+
+#endif
+
+/*
+ * User space process size: 2GB - 4k.
+ */
+#define TASK_SIZE       0x7ffff000UL
+
+#define STACK_TOP       TASK_SIZE
+#define STACK_TOP_MAX   STACK_TOP
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (TASK_SIZE / 3)
+
+/*
+ * Bit of SR register
+ *
+ * FD-bit:
+ *     When it's set, it means the processor doesn't have right to use FPU,
+ *     and it results exception when the floating operation is executed.
+ *
+ * IMASK-bit:
+ *     Interrupt level mask
+ *
+ * STEP-bit:
+ *     Single step bit
+ *
+ */
+#if defined(CONFIG_SH64_SR_WATCH)
+#define SR_MMU   0x84000000
+#else
+#define SR_MMU   0x80000000
+#endif
+
+#define SR_IMASK 0x000000f0
+#define SR_FD    0x00008000
+#define SR_SSTEP 0x08000000
+
+#ifndef __ASSEMBLY__
+
+/*
+ * FPU structure and data : require 8-byte alignment as we need to access it
+   with fld.p, fst.p
+ */
+
+struct sh_fpu_hard_struct {
+        unsigned long fp_regs[64];
+        unsigned int fpscr;
+        /* long status; * software status information */
+};
+
+#if 0
+/* Dummy fpu emulator  */
+struct sh_fpu_soft_struct {
+        unsigned long long fp_regs[32];
+        unsigned int fpscr;
+        unsigned char lookahead;
+        unsigned long entry_pc;
+};
+#endif
+
+union sh_fpu_union {
+        struct sh_fpu_hard_struct hard;
+        /* 'hard' itself only produces 32 bit alignment, yet we need
+           to access it using 64 bit load/store as well. */
+        unsigned long long alignment_dummy;
+};
+
+struct thread_struct {
+        unsigned long sp;
+        unsigned long pc;
+        /* This stores the address of the pt_regs built during a context
+           switch, or of the register save area built for a kernel mode
+           exception.  It is used for backtracing the stack of a sleeping task
+           or one that traps in kernel mode. */
+        struct pt_regs *kregs;
+        /* This stores the address of the pt_regs constructed on entry from
+           user mode.  It is a fixed value over the lifetime of a process, or
+           NULL for a kernel thread. */
+        struct pt_regs *uregs;
+
+        unsigned long trap_no, error_code;
+        unsigned long address;
+        /* Hardware debugging registers may come here */
+
+        /* floating point info */
+        union sh_fpu_union fpu;
+};
+
+#define INIT_MMAP \
+{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
+
+extern  struct pt_regs fake_swapper_regs;
+
+#define INIT_THREAD  {                          \
+        .sp             = sizeof(init_stack) +  \
+                          (long) &init_stack,   \
+        .pc             = 0,                    \
+        .kregs          = &fake_swapper_regs,   \
+        .uregs          = NULL,                 \
+        .trap_no        = 0,                    \
+        .error_code     = 0,                    \
+        .address        = 0,                    \
+        .fpu            = { { { 0, } }, }       \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define SR_USER (SR_MMU | SR_FD)
+
+#define start_thread(regs, new_pc, new_sp)                      \
+        set_fs(USER_DS);                                        \
+        regs->sr = SR_USER;     /* User mode. */                \
+        regs->pc = new_pc - 4;  /* Compensate syscall exit */   \
+        regs->pc |= 1;          /* Set SHmedia ! */             \
+        regs->regs[18] = 0;                                     \
+        regs->regs[15] = new_sp
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+struct mm_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(p, mm)    do { } while (0)
+#define release_segments(mm)    do { } while (0)
+#define forget_segments()       do { } while (0)
+#define prepare_to_copy(tsk)    do { } while (0)
+/*
+ * FPU lazy state save handling.
+ */
+
+static inline void disable_fpu(void)
+{
+        unsigned long long __dummy;
+
+        /* Set FD flag in SR */
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "or        %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy)
+                             : "r" (SR_FD));
+}
+
+static inline void enable_fpu(void)
+{
+        unsigned long long __dummy;
+
+        /* Clear out FD flag in SR */
+        __asm__ __volatile__("getcon    " __SR ", %0\n\t"
+                             "and       %0, %1, %0\n\t"
+                             "putcon    %0, " __SR "\n\t"
+                             : "=&r" (__dummy)
+                             : "r" (~SR_FD));
+}
+
+/* Round to nearest, no exceptions on inexact, overflow, underflow,
+   zero-divide, invalid.  Configure option for whether to flush denorms to
+   zero, or except if a denorm is encountered.  */
+#if defined(CONFIG_SH64_FPU_DENORM_FLUSH)
+#define FPSCR_INIT  0x00040000
+#else
+#define FPSCR_INIT  0x00000000
+#endif
+
+#ifdef CONFIG_SH_FPU
+/* Initialise the FP state of a task */
+void fpinit(struct sh_fpu_hard_struct *fpregs);
+#else
+#define fpinit(fpregs)  do { } while (0)
+#endif
+
+extern struct task_struct *last_task_used_math;
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+#define thread_saved_pc(tsk)    (tsk->thread.pc)
+
+extern unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)  ((tsk)->thread.pc)
+#define KSTK_ESP(tsk)  ((tsk)->thread.sp)
+
+#define cpu_relax()     barrier()
+
+#endif  /* __ASSEMBLY__ */
+#endif /* __ASM_SH_PROCESSOR_64_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
new file mode 100644
index 000000000000..b86aeabba61a
--- /dev/null
+++ b/arch/sh/include/asm/ptrace.h
@@ -0,0 +1,139 @@
+#ifndef __ASM_SH_PTRACE_H
+#define __ASM_SH_PTRACE_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka
+ *
+ */
+#if defined(__SH5__)
+struct pt_regs {
+        unsigned long long pc;
+        unsigned long long sr;
+        unsigned long long syscall_nr;
+        unsigned long long regs[63];
+        unsigned long long tregs[8];
+        unsigned long long pad[2];
+};
+#else
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *       0 - 15 are integer registers
+ *      17 - 22 are control/special registers
+ *      24 - 39 fp registers
+ *      40 - 47 xd registers
+ *      48 -    fpscr register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *      16 --- program counter (PC)
+ *      22 --- syscall #
+ *      23 --- floating point communication register
+ */
+#define REG_REG0         0
+#define REG_REG15       15
+
+#define REG_PC          16
+
+#define REG_PR          17
+#define REG_SR          18
+#define REG_GBR         19
+#define REG_MACH        20
+#define REG_MACL        21
+
+#define REG_SYSCALL     22
+
+#define REG_FPREG0      23
+#define REG_FPREG15     38
+#define REG_XFREG0      39
+#define REG_XFREG15     54
+
+#define REG_FPSCR       55
+#define REG_FPUL        56
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+        unsigned long regs[16];
+        unsigned long pc;
+        unsigned long pr;
+        unsigned long sr;
+        unsigned long gbr;
+        unsigned long mach;
+        unsigned long macl;
+        long tra;
+};
+
+/*
+ * This struct defines the way the DSP registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_dspregs {
+        unsigned long   a1;
+        unsigned long   a0g;
+        unsigned long   a1g;
+        unsigned long   m0;
+        unsigned long   m1;
+        unsigned long   a0;
+        unsigned long   x0;
+        unsigned long   x1;
+        unsigned long   y0;
+        unsigned long   y1;
+        unsigned long   dsr;
+        unsigned long   rs;
+        unsigned long   re;
+        unsigned long   mod;
+};
+
+#define PTRACE_GETFDPIC         31      /* get the ELF fdpic loadmap address */
+
+#define PTRACE_GETFDPIC_EXEC    0       /* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP  1       /* [addr] request the interpreter loadmap */
+
+#define PTRACE_GETDSPREGS       55
+#define PTRACE_SETDSPREGS       56
+#endif
+
+#ifdef __KERNEL__
+#include <asm/addrspace.h>
+
+#define user_mode(regs)                 (((regs)->sr & 0x40000000)==0)
+#define instruction_pointer(regs)       ((unsigned long)(regs)->pc)
+
+extern void show_regs(struct pt_regs *);
+
+/*
+ * These are defined as per linux/ptrace.h.
+ */
+struct task_struct;
+
+#define arch_has_single_step()  (1)
+extern void user_enable_single_step(struct task_struct *);
+extern void user_disable_single_step(struct task_struct *);
+
+#ifdef CONFIG_SH_DSP
+#define task_pt_regs(task) \
+        ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+                 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
+#else
+#define task_pt_regs(task) \
+        ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+                 - sizeof(unsigned long)) - 1)
+#endif
+
+static inline unsigned long profile_pc(struct pt_regs *regs)
+{
+        unsigned long pc = instruction_pointer(regs);
+
+#ifdef P2SEG
+        if (pc >= P2SEG && pc < P3SEG)
+                pc -= 0x20000000;
+#endif
+
+        return pc;
+}
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_PTRACE_H */
diff --git a/arch/sh/include/asm/push-switch.h b/arch/sh/include/asm/push-switch.h
new file mode 100644
index 000000000000..4903f9e52dd8
--- /dev/null
+++ b/arch/sh/include/asm/push-switch.h
@@ -0,0 +1,31 @@
+#ifndef __ASM_SH_PUSH_SWITCH_H
+#define __ASM_SH_PUSH_SWITCH_H
+
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+
+struct push_switch {
+        /* switch state */
+        unsigned int            state:1;
+        /* debounce timer */
+        struct timer_list       debounce;
+        /* workqueue */
+        struct work_struct      work;
+        /* platform device, for workqueue handler */
+        struct platform_device  *pdev;
+};
+
+struct push_switch_platform_info {
+        /* IRQ handler */
+        irqreturn_t             (*irq_handler)(int irq, void *data);
+        /* Special IRQ flags */
+        unsigned int            irq_flags;
+        /* Bit location of switch */
+        unsigned int            bit;
+        /* Symbolic switch name */
+        const char              *name;
+};
+
+#endif /* __ASM_SH_PUSH_SWITCH_H */
diff --git a/arch/sh/include/asm/r7780rp.h b/arch/sh/include/asm/r7780rp.h
new file mode 100644
index 000000000000..306f7359f7d4
--- /dev/null
+++ b/arch/sh/include/asm/r7780rp.h
@@ -0,0 +1,198 @@
+#ifndef __ASM_SH_RENESAS_R7780RP_H
+#define __ASM_SH_RENESAS_R7780RP_H
+
+/* Box specific addresses.  */
+#if defined(CONFIG_SH_R7780MP)
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_SDPOW        (-1)
+
+#define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON       (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_IRLPRI1      (PA_BCR+0x0004) /* Interrupt Priorty 1 */
+#define PA_IRLPRI2      (PA_BCR+0x0006) /* Interrupt Priorty 2 */
+#define PA_IRLPRI3      (PA_BCR+0x0008) /* Interrupt Priorty 3 */
+#define PA_IRLPRI4      (PA_BCR+0x000a) /* Interrupt Priorty 4 */
+#define PA_RSTCTL       (PA_BCR+0x000c) /* Reset Control */
+#define PA_PCIBD        (PA_BCR+0x000e) /* PCI Board detect control */
+#define PA_PCICD        (PA_BCR+0x0010) /* PCI Conector detect control */
+#define PA_EXTGIO       (PA_BCR+0x0016) /* Extension GPIO Control */
+#define PA_IVDRMON      (PA_BCR+0x0018) /* iVDR Moniter control */
+#define PA_IVDRCTL      (PA_BCR+0x001a) /* iVDR control */
+#define PA_OBLED        (PA_BCR+0x001c) /* On Board LED control */
+#define PA_OBSW         (PA_BCR+0x001e) /* On Board Switch control */
+#define PA_AUDIOSEL     (PA_BCR+0x0020) /* Sound Interface Select control */
+#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS       (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS       (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBSW         (PA_BCR+0x0200) /* Debug Board Switch control */
+#define PA_CFCTL        (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW        (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR   (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR0       (PA_BCR+0x0400) /* SCIF0 Serial mode control */
+#define PA_SCBRR0       (PA_BCR+0x0404) /* SCIF0 Bit rate control */
+#define PA_SCSCR0       (PA_BCR+0x0408) /* SCIF0 Serial control */
+#define PA_SCFTDR0      (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
+#define PA_SCFSR0       (PA_BCR+0x0410) /* SCIF0 Serial status control */
+#define PA_SCFRDR0      (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
+#define PA_SCFCR0       (PA_BCR+0x0418) /* SCIF0 FIFO control */
+#define PA_SCTFDR0      (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
+#define PA_SCRFDR0      (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
+#define PA_SCSPTR0      (PA_BCR+0x0424) /* SCIF0 Serial Port control */
+#define PA_SCLSR0       (PA_BCR+0x0428) /* SCIF0 Line Status control */
+#define PA_SCRER0       (PA_BCR+0x042c) /* SCIF0 Serial Error control */
+#define PA_SCSMR1       (PA_BCR+0x0500) /* SCIF1 Serial mode control */
+#define PA_SCBRR1       (PA_BCR+0x0504) /* SCIF1 Bit rate control */
+#define PA_SCSCR1       (PA_BCR+0x0508) /* SCIF1 Serial control */
+#define PA_SCFTDR1      (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
+#define PA_SCFSR1       (PA_BCR+0x0510) /* SCIF1 Serial status control */
+#define PA_SCFRDR1      (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
+#define PA_SCFCR1       (PA_BCR+0x0518) /* SCIF1 FIFO control */
+#define PA_SCTFDR1      (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
+#define PA_SCRFDR1      (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
+#define PA_SCSPTR1      (PA_BCR+0x0524) /* SCIF1 Serial Port control */
+#define PA_SCLSR1       (PA_BCR+0x0528) /* SCIF1 Line Status control */
+#define PA_SCRER1       (PA_BCR+0x052c) /* SCIF1 Serial Error control */
+#define PA_SMCR         (PA_BCR+0x0600) /* 2-wire Serial control */
+#define PA_SMSMADR      (PA_BCR+0x0602) /* 2-wire Serial Slave control */
+#define PA_SMMR         (PA_BCR+0x0604) /* 2-wire Serial Mode control */
+#define PA_SMSADR1      (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
+#define PA_VERREG       (PA_BCR+0x0700) /* FPGA Version Register */
+#define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */
+#define PA_PMR          (PA_BCR+0x0900) /*  */
+
+#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
+#define IVDR_CK_ON      8               /* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7780RP)
+#define PA_POFF         (-1)
+
+#define PA_BCR          0xa5000000      /* FPGA */
+#define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON       (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_SDPOW        (PA_BCR+0x0004) /* SD Power control */
+#define PA_RSTCTL       (PA_BCR+0x0006) /* Device Reset control */
+#define PA_PCIBD        (PA_BCR+0x0008) /* PCI Board detect control */
+#define PA_PCICD        (PA_BCR+0x000a) /* PCI Conector detect control */
+#define PA_ZIGIO1       (PA_BCR+0x000c) /* Zigbee IO control 1 */
+#define PA_ZIGIO2       (PA_BCR+0x000e) /* Zigbee IO control 2 */
+#define PA_ZIGIO3       (PA_BCR+0x0010) /* Zigbee IO control 3 */
+#define PA_ZIGIO4       (PA_BCR+0x0012) /* Zigbee IO control 4 */
+#define PA_IVDRMON      (PA_BCR+0x0014) /* iVDR Moniter control */
+#define PA_IVDRCTL      (PA_BCR+0x0016) /* iVDR control */
+#define PA_OBLED        (PA_BCR+0x0018) /* On Board LED control */
+#define PA_OBSW         (PA_BCR+0x001a) /* On Board Switch control */
+#define PA_AUDIOSEL     (PA_BCR+0x001c) /* Sound Interface Select control */
+#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS       (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS       (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBDET        (PA_BCR+0x0200) /* Debug Board detect control */
+#define PA_DBDISPCTL    (PA_BCR+0x0202) /* Debug Board Dot timing control */
+#define PA_DBSW         (PA_BCR+0x0204) /* Debug Board Switch control */
+#define PA_CFCTL        (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW        (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR   (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR        (PA_BCR+0x0400) /* SCIF Serial mode control */
+#define PA_SCBRR        (PA_BCR+0x0402) /* SCIF Bit rate control */
+#define PA_SCSCR        (PA_BCR+0x0404) /* SCIF Serial control */
+#define PA_SCFDTR       (PA_BCR+0x0406) /* SCIF Send FIFO control */
+#define PA_SCFSR        (PA_BCR+0x0408) /* SCIF Serial status control */
+#define PA_SCFRDR       (PA_BCR+0x040a) /* SCIF Receive FIFO control */
+#define PA_SCFCR        (PA_BCR+0x040c) /* SCIF FIFO control */
+#define PA_SCFDR        (PA_BCR+0x040e) /* SCIF FIFO data control */
+#define PA_SCLSR        (PA_BCR+0x0412) /* SCIF Line Status control */
+#define PA_SMCR         (PA_BCR+0x0500) /* 2-wire Serial control */
+#define PA_SMSMADR      (PA_BCR+0x0502) /* 2-wire Serial Slave control */
+#define PA_SMMR         (PA_BCR+0x0504) /* 2-wire Serial Mode control */
+#define PA_SMSADR1      (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
+#define PA_VERREG       (PA_BCR+0x0600) /* FPGA Version Register */
+
+#define PA_AX88796L     0xa5800400      /* AX88796L Area */
+#define PA_SC1602BSLB   0xa6000000      /* SC1602BSLB Area */
+#define PA_IDE_OFFSET   0x1f0           /* CF IDE Offset */
+#define AX88796L_IO_BASE        0x1000  /* AX88796L IO Base Address */
+
+#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
+
+#define IVDR_CK_ON      8               /* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7785RP)
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_SDPOW        (-1)
+
+#define PA_PCISCR       (PA_BCR+0x0000)
+#define PA_IRLPRA       (PA_BCR+0x0002)
+#define PA_IRLPRB       (PA_BCR+0x0004)
+#define PA_IRLPRC       (PA_BCR+0x0006)
+#define PA_IRLPRD       (PA_BCR+0x0008)
+#define IRLCNTR1        (PA_BCR+0x0010)
+#define PA_IRLPRE       (PA_BCR+0x000a)
+#define PA_IRLPRF       (PA_BCR+0x000c)
+#define PA_EXIRLCR      (PA_BCR+0x000e)
+#define PA_IRLMCR1      (PA_BCR+0x0010)
+#define PA_IRLMCR2      (PA_BCR+0x0012)
+#define PA_IRLSSR1      (PA_BCR+0x0014)
+#define PA_IRLSSR2      (PA_BCR+0x0016)
+#define PA_CFTCR        (PA_BCR+0x0100)
+#define PA_CFPCR        (PA_BCR+0x0102)
+#define PA_PCICR        (PA_BCR+0x0110)
+#define PA_IVDRCTL      (PA_BCR+0x0112)
+#define PA_IVDRSR       (PA_BCR+0x0114)
+#define PA_PDRSTCR      (PA_BCR+0x0116)
+#define PA_POFF         (PA_BCR+0x0120)
+#define PA_LCDCR        (PA_BCR+0x0130)
+#define PA_TPCR         (PA_BCR+0x0140)
+#define PA_TPCKCR       (PA_BCR+0x0142)
+#define PA_TPRSTR       (PA_BCR+0x0144)
+#define PA_TPXPDR       (PA_BCR+0x0146)
+#define PA_TPYPDR       (PA_BCR+0x0148)
+#define PA_GPIOPFR      (PA_BCR+0x0150)
+#define PA_GPIODR       (PA_BCR+0x0152)
+#define PA_OBLED        (PA_BCR+0x0154)
+#define PA_SWSR         (PA_BCR+0x0156)
+#define PA_VERREG       (PA_BCR+0x0158)
+#define PA_SMCR         (PA_BCR+0x0200)
+#define PA_SMSMADR      (PA_BCR+0x0202)
+#define PA_SMMR         (PA_BCR+0x0204)
+#define PA_SMSADR1      (PA_BCR+0x0206)
+#define PA_SMSADR32     (PA_BCR+0x0244)
+#define PA_SMTRDR1      (PA_BCR+0x0246)
+#define PA_SMTRDR16     (PA_BCR+0x0264)
+#define PA_CU3MDR       (PA_BCR+0x0300)
+#define PA_CU5MDR       (PA_BCR+0x0302)
+#define PA_MMSR         (PA_BCR+0x0400)
+
+#define IVDR_CK_ON      4               /* iVDR Clock ON */
+#endif
+
+#define HL_FPGA_IRQ_BASE        200
+#define HL_NR_IRL               15
+
+#define IRQ_AX88796             (HL_FPGA_IRQ_BASE + 0)
+#define IRQ_CF                  (HL_FPGA_IRQ_BASE + 1)
+#define IRQ_PSW                 (HL_FPGA_IRQ_BASE + 2)
+#define IRQ_EXT0                (HL_FPGA_IRQ_BASE + 3)
+#define IRQ_EXT1                (HL_FPGA_IRQ_BASE + 4)
+#define IRQ_EXT2                (HL_FPGA_IRQ_BASE + 5)
+#define IRQ_EXT3                (HL_FPGA_IRQ_BASE + 6)
+#define IRQ_EXT4                (HL_FPGA_IRQ_BASE + 7)
+#define IRQ_EXT5                (HL_FPGA_IRQ_BASE + 8)
+#define IRQ_EXT6                (HL_FPGA_IRQ_BASE + 9)
+#define IRQ_EXT7                (HL_FPGA_IRQ_BASE + 10)
+#define IRQ_SMBUS               (HL_FPGA_IRQ_BASE + 11)
+#define IRQ_TP                  (HL_FPGA_IRQ_BASE + 12)
+#define IRQ_RTC                 (HL_FPGA_IRQ_BASE + 13)
+#define IRQ_TH_ALERT            (HL_FPGA_IRQ_BASE + 14)
+#define IRQ_SCIF0               (HL_FPGA_IRQ_BASE + 15)
+#define IRQ_SCIF1               (HL_FPGA_IRQ_BASE + 16)
+
+unsigned char *highlander_plat_irq_setup(void);
+
+#endif  /* __ASM_SH_RENESAS_R7780RP */
diff --git a/arch/sh/include/asm/resource.h b/arch/sh/include/asm/resource.h
new file mode 100644
index 000000000000..9c2499a86ec0
--- /dev/null
+++ b/arch/sh/include/asm/resource.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_RESOURCE_H
+#define __ASM_SH_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif /* __ASM_SH_RESOURCE_H */
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
new file mode 100644
index 000000000000..1813f4202a24
--- /dev/null
+++ b/arch/sh/include/asm/rtc.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_RTC_H
+#define _ASM_RTC_H
+
+extern void (*board_time_init)(void);
+extern void (*rtc_sh_get_time)(struct timespec *);
+extern int (*rtc_sh_set_time)(const time_t);
+
+#define RTC_CAP_4_DIGIT_YEAR    (1 << 0)
+
+struct sh_rtc_platform_info {
+        unsigned long capabilities;
+};
+
+#include <cpu/rtc.h>
+
+#endif /* _ASM_RTC_H */
diff --git a/arch/sh/include/asm/rts7751r2d.h b/arch/sh/include/asm/rts7751r2d.h
new file mode 100644
index 000000000000..0a800157b826
--- /dev/null
+++ b/arch/sh/include/asm/rts7751r2d.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
+#define __ASM_SH_RENESAS_RTS7751R2D_H
+
+/*
+ * linux/include/asm-sh/renesas_rts7751r2d.h
+ *
+ * Copyright (C) 2000  Atom Create Engineering Co., Ltd.
+ *
+ * Renesas Technology Sales RTS7751R2D support
+ */
+
+/* Board specific addresses.  */
+
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_IRLMON       0xa4000002      /* Interrupt Status control */
+#define PA_CFCTL        0xa4000004      /* CF Timing control */
+#define PA_CFPOW        0xa4000006      /* CF Power control */
+#define PA_DISPCTL      0xa4000008      /* Display Timing control */
+#define PA_SDMPOW       0xa400000a      /* SD Power control */
+#define PA_RTCCE        0xa400000c      /* RTC(9701) Enable control */
+#define PA_PCICD        0xa400000e      /* PCI Extention detect control */
+#define PA_VOYAGERRTS   0xa4000020      /* VOYAGER Reset control */
+
+#define PA_R2D1_AXRST           0xa4000022      /* AX_LAN Reset control */
+#define PA_R2D1_CFRST           0xa4000024      /* CF Reset control */
+#define PA_R2D1_ADMRTS          0xa4000026      /* SD Reset control */
+#define PA_R2D1_EXTRST          0xa4000028      /* Extention Reset control */
+#define PA_R2D1_CFCDINTCLR      0xa400002a      /* CF Insert Interrupt clear */
+
+#define PA_R2DPLUS_CFRST        0xa4000022      /* CF Reset control */
+#define PA_R2DPLUS_ADMRTS       0xa4000024      /* SD Reset control */
+#define PA_R2DPLUS_EXTRST       0xa4000026      /* Extention Reset control */
+#define PA_R2DPLUS_CFCDINTCLR   0xa4000028      /* CF Insert Interrupt clear */
+#define PA_R2DPLUS_KEYCTLCLR    0xa400002a      /* Key Interrupt clear */
+
+#define PA_POWOFF       0xa4000030      /* Board Power OFF control */
+#define PA_VERREG       0xa4000032      /* FPGA Version Register */
+#define PA_INPORT       0xa4000034      /* KEY Input Port control */
+#define PA_OUTPORT      0xa4000036      /* LED control */
+#define PA_BVERREG      0xa4000038      /* Board Revision Register */
+
+#define PA_AX88796L     0xaa000400      /* AX88796L Area */
+#define PA_VOYAGER      0xab000000      /* VOYAGER GX Area */
+#define PA_IDE_OFFSET   0x1f0           /* CF IDE Offset */
+#define AX88796L_IO_BASE        0x1000  /* AX88796L IO Base Address */
+
+#define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
+
+#define R2D_FPGA_IRQ_BASE       100
+
+#define IRQ_VOYAGER             (R2D_FPGA_IRQ_BASE + 0)
+#define IRQ_EXT                 (R2D_FPGA_IRQ_BASE + 1)
+#define IRQ_TP                  (R2D_FPGA_IRQ_BASE + 2)
+#define IRQ_RTC_T               (R2D_FPGA_IRQ_BASE + 3)
+#define IRQ_RTC_A               (R2D_FPGA_IRQ_BASE + 4)
+#define IRQ_SDCARD              (R2D_FPGA_IRQ_BASE + 5)
+#define IRQ_CF_CD               (R2D_FPGA_IRQ_BASE + 6)
+#define IRQ_CF_IDE              (R2D_FPGA_IRQ_BASE + 7)
+#define IRQ_AX88796             (R2D_FPGA_IRQ_BASE + 8)
+#define IRQ_KEY                 (R2D_FPGA_IRQ_BASE + 9)
+#define IRQ_PCI_INTA            (R2D_FPGA_IRQ_BASE + 10)
+#define IRQ_PCI_INTB            (R2D_FPGA_IRQ_BASE + 11)
+#define IRQ_PCI_INTC            (R2D_FPGA_IRQ_BASE + 12)
+#define IRQ_PCI_INTD            (R2D_FPGA_IRQ_BASE + 13)
+
+/* arch/sh/boards/renesas/rts7751r2d/irq.c */
+void init_rts7751r2d_IRQ(void);
+int rts7751r2d_irq_demux(int);
+
+#endif  /* __ASM_SH_RENESAS_RTS7751R2D */
diff --git a/arch/sh/include/asm/rwsem.h b/arch/sh/include/asm/rwsem.h
new file mode 100644
index 000000000000..1987f3ea7f1b
--- /dev/null
+++ b/arch/sh/include/asm/rwsem.h
@@ -0,0 +1,188 @@
+/*
+ * include/asm-sh/rwsem.h: R/W semaphores for SH using the stuff
+ * in lib/rwsem.c.
+ */
+
+#ifndef _ASM_SH_RWSEM_H
+#define _ASM_SH_RWSEM_H
+
+#ifndef _LINUX_RWSEM_H
+#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
+#endif
+
+#ifdef __KERNEL__
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+
+/*
+ * the semaphore definition
+ */
+struct rw_semaphore {
+        long            count;
+#define RWSEM_UNLOCKED_VALUE            0x00000000
+#define RWSEM_ACTIVE_BIAS               0x00000001
+#define RWSEM_ACTIVE_MASK               0x0000ffff
+#define RWSEM_WAITING_BIAS              (-0x00010000)
+#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
+          LIST_HEAD_INIT((name).wait_list) \
+          __RWSEM_DEP_MAP_INIT(name) }
+
+#define DECLARE_RWSEM(name)             \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                         \
+do {                                            \
+        static struct lock_class_key __key;     \
+                                                \
+        __init_rwsem((sem), #sem, &__key);      \
+} while (0)
+
+static inline void init_rwsem(struct rw_semaphore *sem)
+{
+        sem->count = RWSEM_UNLOCKED_VALUE;
+        spin_lock_init(&sem->wait_lock);
+        INIT_LIST_HEAD(&sem->wait_list);
+}
+
+/*
+ * lock for reading
+ */
+static inline void __down_read(struct rw_semaphore *sem)
+{
+        if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
+                smp_wmb();
+        else
+                rwsem_down_read_failed(sem);
+}
+
+static inline int __down_read_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        while ((tmp = sem->count) >= 0) {
+                if (tmp == cmpxchg(&sem->count, tmp,
+                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
+                        smp_wmb();
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/*
+ * lock for writing
+ */
+static inline void __down_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
+                                (atomic_t *)(&sem->count));
+        if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
+                smp_wmb();
+        else
+                rwsem_down_write_failed(sem);
+}
+
+static inline int __down_write_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
+                      RWSEM_ACTIVE_WRITE_BIAS);
+        smp_wmb();
+        return tmp == RWSEM_UNLOCKED_VALUE;
+}
+
+/*
+ * unlock after reading
+ */
+static inline void __up_read(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_dec_return((atomic_t *)(&sem->count));
+        if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * unlock after writing
+ */
+static inline void __up_write(struct rw_semaphore *sem)
+{
+        smp_wmb();
+        if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
+                              (atomic_t *)(&sem->count)) < 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * implement atomic add functionality
+ */
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+{
+        atomic_add(delta, (atomic_t *)(&sem->count));
+}
+
+/*
+ * downgrade write lock to read lock
+ */
+static inline void __downgrade_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
+        if (tmp < 0)
+                rwsem_downgrade_wake(sem);
+}
+
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        __down_write(sem);
+}
+
+/*
+ * implement exchange and add functionality
+ */
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+{
+        smp_mb();
+        return atomic_add_return(delta, (atomic_t *)(&sem->count));
+}
+
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_SH_RWSEM_H */
diff --git a/arch/sh/include/asm/scatterlist.h b/arch/sh/include/asm/scatterlist.h
new file mode 100644
index 000000000000..2084d0373693
--- /dev/null
+++ b/arch/sh/include/asm/scatterlist.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_SCATTERLIST_H
+#define __ASM_SH_SCATTERLIST_H
+
+#include <asm/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+    unsigned long sg_magic;
+#endif
+    unsigned long page_link;
+    unsigned int offset;/* for highmem, page offset */
+    dma_addr_t dma_address;
+    unsigned int length;
+};
+
+#define ISA_DMA_THRESHOLD       PHYS_ADDR_MASK
+
+/* These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+#endif /* !(__ASM_SH_SCATTERLIST_H) */
diff --git a/arch/sh/include/asm/sdk7780.h b/arch/sh/include/asm/sdk7780.h
new file mode 100644
index 000000000000..697dc865f21b
--- /dev/null
+++ b/arch/sh/include/asm/sdk7780.h
@@ -0,0 +1,81 @@
+#ifndef __ASM_SH_RENESAS_SDK7780_H
+#define __ASM_SH_RENESAS_SDK7780_H
+
+/*
+ * linux/include/asm-sh/sdk7780.h
+ *
+ * Renesas Solutions SH7780 SDK Support
+ * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM                  0xa0000000      /* EPROM */
+#define PA_ROM_SIZE             0x00400000      /* EPROM size 4M byte */
+#define PA_FROM                 0xa0800000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x00400000      /* Flash-ROM size 4M byte */
+#define PA_EXT1                 0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM                0xa8000000      /* DDR-SDRAM(Area2/3) 128MB */
+#define PA_SDRAM_SIZE   0x08000000
+
+#define PA_EXT4                 0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+#define PA_EXT_USER             PA_EXT4         /* User Expansion Space */
+
+#define PA_PERIPHERAL   PA_AREA5_IO
+
+/* SRAM/Reserved */
+#define PA_RESERVED     (PA_PERIPHERAL + 0)
+/* FPGA base address */
+#define PA_FPGA         (PA_PERIPHERAL + 0x01000000)
+/* SMC LAN91C111 */
+#define PA_LAN          (PA_PERIPHERAL + 0x01800000)
+
+
+#define FPGA_SRSTR      (PA_FPGA + 0x000)       /* System reset */
+#define FPGA_IRQ0SR     (PA_FPGA + 0x010)       /* IRQ0 status */
+#define FPGA_IRQ0MR     (PA_FPGA + 0x020)       /* IRQ0 mask */
+#define FPGA_BDMR       (PA_FPGA + 0x030)       /* Board operating mode */
+#define FPGA_INTT0PRTR  (PA_FPGA + 0x040)       /* Interrupt test mode0 port */
+#define FPGA_INTT0SELR  (PA_FPGA + 0x050)       /* Int. test mode0 select */
+#define FPGA_INTT1POLR  (PA_FPGA + 0x060)       /* Int. test mode0 polarity */
+#define FPGA_NMIR       (PA_FPGA + 0x070)       /* NMI source */
+#define FPGA_NMIMR      (PA_FPGA + 0x080)       /* NMI mask */
+#define FPGA_IRQR       (PA_FPGA + 0x090)       /* IRQX source */
+#define FPGA_IRQMR      (PA_FPGA + 0x0A0)       /* IRQX mask */
+#define FPGA_SLEDR      (PA_FPGA + 0x0B0)       /* LED control */
+#define PA_LED                  FPGA_SLEDR
+#define FPGA_MAPSWR     (PA_FPGA + 0x0C0)       /* Map switch */
+#define FPGA_FPVERR     (PA_FPGA + 0x0D0)       /* FPGA version */
+#define FPGA_FPDATER    (PA_FPGA + 0x0E0)       /* FPGA date */
+#define FPGA_RSE        (PA_FPGA + 0x100)       /* Reset source */
+#define FPGA_EASR       (PA_FPGA + 0x110)       /* External area select */
+#define FPGA_SPER       (PA_FPGA + 0x120)       /* Serial port enable */
+#define FPGA_IMSR       (PA_FPGA + 0x130)       /* Interrupt mode select */
+#define FPGA_PCIMR      (PA_FPGA + 0x140)       /* PCI Mode */
+#define FPGA_DIPSWMR    (PA_FPGA + 0x150)       /* DIPSW monitor */
+#define FPGA_FPODR      (PA_FPGA + 0x160)       /* Output port data */
+#define FPGA_ATAESR     (PA_FPGA + 0x170)       /* ATA extended bus status */
+#define FPGA_IRQPOLR    (PA_FPGA + 0x180)       /* IRQx polarity */
+
+
+#define SDK7780_NR_IRL                  15
+/* IDE/ATA interrupt */
+#define IRQ_CFCARD                              14
+/* SMC interrupt */
+#define IRQ_ETHERNET                    6
+
+
+/* arch/sh/boards/renesas/sdk7780/irq.c */
+void init_sdk7780_IRQ(void);
+
+#define __IO_PREFIX             sdk7780
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_RENESAS_SDK7780_H */
diff --git a/arch/sh/include/asm/seccomp.h b/arch/sh/include/asm/seccomp.h
new file mode 100644
index 000000000000..3280ed3802ef
--- /dev/null
+++ b/arch/sh/include/asm/seccomp.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_SECCOMP_H
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#endif /* __ASM_SECCOMP_H */
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
new file mode 100644
index 000000000000..8f8f4ad400df
--- /dev/null
+++ b/arch/sh/include/asm/sections.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_SH_SECTIONS_H
+#define __ASM_SH_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern long __machvec_start, __machvec_end;
+extern char __uncached_start, __uncached_end;
+extern char _ebss[];
+
+#endif /* __ASM_SH_SECTIONS_H */
+
diff --git a/arch/sh/include/asm/segment.h b/arch/sh/include/asm/segment.h
new file mode 100644
index 000000000000..5e2725f4ac49
--- /dev/null
+++ b/arch/sh/include/asm/segment.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_SH_SEGMENT_H
+#define __ASM_SH_SEGMENT_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+#define KERNEL_DS       MAKE_MM_SEG(0xFFFFFFFFUL)
+#ifdef CONFIG_MMU
+#define USER_DS         MAKE_MM_SEG(PAGE_OFFSET)
+#else
+#define USER_DS         KERNEL_DS
+#endif
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+#define get_ds()        (KERNEL_DS)
+
+#define get_fs()        (current_thread_info()->addr_limit)
+#define set_fs(x)       (current_thread_info()->addr_limit = (x))
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_SEGMENT_H */
diff --git a/arch/sh/include/asm/sembuf.h b/arch/sh/include/asm/sembuf.h
new file mode 100644
index 000000000000..d79f3bd570b2
--- /dev/null
+++ b/arch/sh/include/asm/sembuf.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_SH_SEMBUF_H
+#define __ASM_SH_SEMBUF_H
+
+/* 
+ * The semid64_ds structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        unsigned long   __unused1;
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   __unused2;
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* __ASM_SH_SEMBUF_H */
diff --git a/arch/sh/include/asm/serial.h b/arch/sh/include/asm/serial.h
new file mode 100644
index 000000000000..e13cc948ee60
--- /dev/null
+++ b/arch/sh/include/asm/serial.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-sh/serial.h
+ *
+ * Configuration details for 8250, 16450, 16550, etc. serial ports
+ */
+
+#ifndef _ASM_SERIAL_H
+#define _ASM_SERIAL_H
+
+#include <linux/kernel.h>
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+#ifdef CONFIG_HD64465
+#include <asm/hd64465/hd64465.h>
+
+#define SERIAL_PORT_DFNS                   \
+        /* UART CLK   PORT IRQ     FLAGS        */                      \
+        { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS }  /* ttyS0 */
+
+#else
+
+#define SERIAL_PORT_DFNS
+
+#endif
+
+#endif /* _ASM_SERIAL_H */
diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h
new file mode 100644
index 000000000000..55a2bd328d99
--- /dev/null
+++ b/arch/sh/include/asm/setup.h
@@ -0,0 +1,27 @@
+#ifndef _SH_SETUP_H
+#define _SH_SETUP_H
+
+#define COMMAND_LINE_SIZE 256
+
+#ifdef __KERNEL__
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+#define PARAM   ((unsigned char *)empty_zero_page)
+
+#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
+#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
+#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
+#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
+#define INITRD_START (*(unsigned long *) (PARAM+0x010))
+#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
+/* ... */
+#define COMMAND_LINE ((char *) (PARAM+0x100))
+
+int setup_early_printk(char *);
+void sh_mv_setup(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _SH_SETUP_H */
diff --git a/arch/sh/include/asm/sfp-machine.h b/arch/sh/include/asm/sfp-machine.h
new file mode 100644
index 000000000000..d3c548443f2a
--- /dev/null
+++ b/arch/sh/include/asm/sfp-machine.h
@@ -0,0 +1,84 @@
+/* Machine-dependent software floating-point definitions.
+   SuperH kernel version.
+   Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Richard Henderson (rth@cygnus.com),
+                  Jakub Jelinek (jj@ultra.linux.cz),
+                  David S. Miller (davem@redhat.com) and
+                  Peter Maydell (pmaydell@chiark.greenend.org.uk).
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If
+   not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _SFP_MACHINE_H
+#define _SFP_MACHINE_H
+
+#define _FP_W_TYPE_SIZE         32
+#define _FP_W_TYPE              unsigned long
+#define _FP_WS_TYPE             signed long
+#define _FP_I_TYPE              long
+
+#define _FP_MUL_MEAT_S(R,X,Y)                                   \
+  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y)                                   \
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y)                                   \
+  _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_udiv(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S           ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D           ((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q           ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S           0
+#define _FP_NANSIGN_D           0
+#define _FP_NANSIGN_Q           0
+
+#define _FP_KEEPNANFRACP 1
+
+/*
+ * If one NaN is signaling and the other is not,
+ * we choose that one, otherwise we choose X.
+ */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
+  do {                                                          \
+    if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)          \
+        && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs))     \
+      {                                                         \
+        R##_s = Y##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,Y);                                \
+      }                                                         \
+    else                                                        \
+      {                                                         \
+        R##_s = X##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,X);                                \
+      }                                                         \
+    R##_c = FP_CLS_NAN;                                         \
+  } while (0)
+
+//#define FP_ROUNDMODE          FPSCR_RM
+#define FP_DENORM_ZERO          1/*FPSCR_DN*/
+
+/* Exception flags. */
+#define FP_EX_INVALID           (1<<4)
+#define FP_EX_DIVZERO           (1<<3)
+#define FP_EX_OVERFLOW          (1<<2)
+#define FP_EX_UNDERFLOW         (1<<1)
+#define FP_EX_INEXACT           (1<<0)
+
+#endif
+
diff --git a/arch/sh/include/asm/sh7760fb.h b/arch/sh/include/asm/sh7760fb.h
new file mode 100644
index 000000000000..8767f61aceca
--- /dev/null
+++ b/arch/sh/include/asm/sh7760fb.h
@@ -0,0 +1,197 @@
+/*
+ * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
+ *
+ * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
+ *                      Manuel Lauss <mano@roarinelk.homelinux.net>
+ * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ */
+
+#ifndef _ASM_SH_SH7760FB_H
+#define _ASM_SH_SH7760FB_H
+
+/*
+ * some bits of the colormap registers should be written as zero.
+ * create a mask for that.
+ */
+#define SH7760FB_PALETTE_MASK 0x00f8fcf8
+
+/* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
+#define SH7760FB_DMA_MASK 0x0C000000
+
+/* palette */
+#define LDPR(x) (((x) << 2))
+
+/* framebuffer registers and bits */
+#define LDICKR 0x400
+#define LDMTR 0x402
+/* see sh7760fb.h for LDMTR bits */
+#define LDDFR 0x404
+#define LDDFR_PABD (1 << 8)
+#define LDDFR_COLOR_MASK 0x7F
+#define LDSMR 0x406
+#define LDSMR_ROT (1 << 13)
+#define LDSARU 0x408
+#define LDSARL 0x40c
+#define LDLAOR 0x410
+#define LDPALCR 0x412
+#define LDPALCR_PALS (1 << 4)
+#define LDPALCR_PALEN (1 << 0)
+#define LDHCNR 0x414
+#define LDHSYNR 0x416
+#define LDVDLNR 0x418
+#define LDVTLNR 0x41a
+#define LDVSYNR 0x41c
+#define LDACLNR 0x41e
+#define LDINTR 0x420
+#define LDPMMR 0x424
+#define LDPSPR 0x426
+#define LDCNTR 0x428
+#define LDCNTR_DON (1 << 0)
+#define LDCNTR_DON2 (1 << 4)
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7763
+# define LDLIRNR       0x440
+/* LDINTR bit */
+# define LDINTR_MINTEN (1 << 15)
+# define LDINTR_FINTEN (1 << 14)
+# define LDINTR_VSINTEN (1 << 13)
+# define LDINTR_VEINTEN (1 << 12)
+# define LDINTR_MINTS (1 << 11)
+# define LDINTR_FINTS (1 << 10)
+# define LDINTR_VSINTS (1 << 9)
+# define LDINTR_VEINTS (1 << 8)
+# define VINT_START (LDINTR_VSINTEN)
+# define VINT_CHECK (LDINTR_VSINTS)
+#else
+/* LDINTR bit */
+# define LDINTR_VINTSEL (1 << 12)
+# define LDINTR_VINTE (1 << 8)
+# define LDINTR_VINTS (1 << 0)
+# define VINT_START (LDINTR_VINTSEL)
+# define VINT_CHECK (LDINTR_VINTS)
+#endif
+
+/* HSYNC polarity inversion */
+#define LDMTR_FLMPOL (1 << 15)
+
+/* VSYNC polarity inversion */
+#define LDMTR_CL1POL (1 << 14)
+
+/* DISPLAY-ENABLE polarity inversion */
+#define LDMTR_DISPEN_LOWACT (1 << 13)
+
+/* DISPLAY DATA BUS polarity inversion */
+#define LDMTR_DPOL_LOWACT (1 << 12)
+
+/* AC modulation signal enable */
+#define LDMTR_MCNT (1 << 10)
+
+/* Disable output of HSYNC during VSYNC period */
+#define LDMTR_CL1CNT (1 << 9)
+
+/* Disable output of VSYNC during VSYNC period */
+#define LDMTR_CL2CNT (1 << 8)
+
+/* Display types supported by the LCDC */
+#define LDMTR_STN_MONO_4       0x00
+#define LDMTR_STN_MONO_8       0x01
+#define LDMTR_STN_COLOR_4      0x08
+#define LDMTR_STN_COLOR_8      0x09
+#define LDMTR_STN_COLOR_12     0x0A
+#define LDMTR_STN_COLOR_16     0x0B
+#define LDMTR_DSTN_MONO_8      0x11
+#define LDMTR_DSTN_MONO_16     0x13
+#define LDMTR_DSTN_COLOR_8     0x19
+#define LDMTR_DSTN_COLOR_12    0x1A
+#define LDMTR_DSTN_COLOR_16    0x1B
+#define LDMTR_TFT_COLOR_16     0x2B
+
+/* framebuffer color layout */
+#define LDDFR_1BPP_MONO 0x00
+#define LDDFR_2BPP_MONO 0x01
+#define LDDFR_4BPP_MONO 0x02
+#define LDDFR_6BPP_MONO 0x04
+#define LDDFR_4BPP 0x0A
+#define LDDFR_8BPP 0x0C
+#define LDDFR_16BPP_RGB555 0x1D
+#define LDDFR_16BPP_RGB565 0x2D
+
+/* LCDC Pixclock sources */
+#define LCDC_CLKSRC_BUSCLOCK 0
+#define LCDC_CLKSRC_PERIPHERAL 1
+#define LCDC_CLKSRC_EXTERNAL 2
+
+#define LDICKR_CLKSRC(x) \
+       (((x) & 3) << 12)
+
+/* LCDC pixclock input divider. Set to 1 at a minimum! */
+#define LDICKR_CLKDIV(x) \
+       ((x) & 0x1f)
+
+struct sh7760fb_platdata {
+
+        /* Set this member to a valid fb_videmode for the display you
+         * wish to use.  The following members must be initialized:
+         * xres, yres, hsync_len, vsync_len, sync,
+         * {left,right,upper,lower}_margin.
+         * The driver uses the above members to calculate register values
+         * and memory requirements. Other members are ignored but may
+         * be used by other framebuffer layer components.
+         */
+        struct fb_videomode *def_mode;
+
+        /* LDMTR includes display type and signal polarity.  The
+         * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo
+         * data above; however the polarities of the following signals
+         * must be encoded in the ldmtr member:
+         * Display Enable signal (default high-active)  DISPEN_LOWACT
+         * Display Data signals (default high-active)   DPOL_LOWACT
+         * AC Modulation signal (default off)           MCNT
+         * Hsync-During-Vsync suppression (default off) CL1CNT
+         * Vsync-during-vsync suppression (default off) CL2CNT
+         * NOTE: also set a display type!
+         * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16})
+         */
+        u16 ldmtr;
+
+        /* LDDFR controls framebuffer image format (depth, organization)
+         * Use ONE of the LDDFR_?BPP_* macros!
+         */
+        u16 lddfr;
+
+        /* LDPMMR and LDPSPR control the timing of the power signals
+         * for the display. Please read the SH7760 Hardware Manual,
+         * Chapters 30.3.17, 30.3.18 and 30.4.6!
+         */
+        u16 ldpmmr;
+        u16 ldpspr;
+
+        /* LDACLNR contains the line numbers after which the AC modulation
+         * signal is to toggle. Set to ZERO for TFTs or displays which
+         * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual).
+         */
+        u16 ldaclnr;
+
+        /* LDICKR contains information on pixelclock source and config.
+         * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros.
+         * minimal value for CLKDIV() must be 1!.
+         */
+        u16 ldickr;
+
+        /* set this member to 1 if you wish to use the LCDC's hardware
+         * rotation function.  This is limited to displays <= 320x200
+         * pixels resolution!
+         */
+        int rotate;             /* set to 1 to rotate 90 CCW */
+
+        /* set this to 1 to suppress vsync irq use. */
+        int novsync;
+
+        /* blanking hook for platform. Set this if your platform can do
+         * more than the LCDC in terms of blanking (e.g. disable clock
+         * generator / backlight power supply / etc.
+         */
+        void (*blank) (int);
+};
+
+#endif /* _ASM_SH_SH7760FB_H */
diff --git a/arch/sh/include/asm/sh7763rdp.h b/arch/sh/include/asm/sh7763rdp.h
new file mode 100644
index 000000000000..8750cc852977
--- /dev/null
+++ b/arch/sh/include/asm/sh7763rdp.h
@@ -0,0 +1,54 @@
+#ifndef __ASM_SH_SH7763RDP_H
+#define __ASM_SH_SH7763RDP_H
+
+/*
+ * linux/include/asm-sh/sh7763drp.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* clock control */
+#define MSTPCR1 0xFFC80038
+
+/* PORT */
+#define PORT_PSEL0      0xFFEF0070
+#define PORT_PSEL1      0xFFEF0072
+#define PORT_PSEL2      0xFFEF0074
+#define PORT_PSEL3      0xFFEF0076
+#define PORT_PSEL4      0xFFEF0078
+
+#define PORT_PACR       0xFFEF0000
+#define PORT_PCCR       0xFFEF0004
+#define PORT_PFCR       0xFFEF000A
+#define PORT_PGCR       0xFFEF000C
+#define PORT_PHCR       0xFFEF000E
+#define PORT_PICR       0xFFEF0010
+#define PORT_PJCR       0xFFEF0012
+#define PORT_PKCR       0xFFEF0014
+#define PORT_PLCR       0xFFEF0016
+#define PORT_PMCR       0xFFEF0018
+#define PORT_PNCR       0xFFEF001A
+
+/* FPGA */
+#define CPLD_BOARD_ID_ERV_REG   0xB1000000
+#define CPLD_CPLD_CMD_REG               0xB1000006
+
+/*
+ * USB SH7763RDP board can use Host only.
+ */
+#define USB_USBHSC      0xFFEC80f0
+
+/* arch/sh/boards/renesas/sh7763rdp/irq.c */
+void init_sh7763rdp_IRQ(void);
+int sh7763rdp_irq_demux(int irq);
+#define __IO_PREFIX     sh7763rdp
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SH7763RDP_H */
diff --git a/arch/sh/include/asm/sh7785lcr.h b/arch/sh/include/asm/sh7785lcr.h
new file mode 100644
index 000000000000..1ce27d5c7491
--- /dev/null
+++ b/arch/sh/include/asm/sh7785lcr.h
@@ -0,0 +1,55 @@
+#ifndef __ASM_SH_RENESAS_SH7785LCR_H
+#define __ASM_SH_RENESAS_SH7785LCR_H
+
+/*
+ * This board has 2 physical memory maps.
+ * It can be changed with DIP switch(S2-5).
+ *
+ * phys address                 | S2-5 = OFF    | S2-5 = ON
+ * -----------------------------+---------------+---------------
+ * 0x00000000 - 0x03ffffff(CS0) | NOR Flash     | NOR Flash
+ * 0x04000000 - 0x05ffffff(CS1) | PLD           | PLD
+ * 0x06000000 - 0x07ffffff(CS1) | reserved      | I2C
+ * 0x08000000 - 0x0bffffff(CS2) | USB           | DDR SDRAM
+ * 0x0c000000 - 0x0fffffff(CS3) | SD            | DDR SDRAM
+ * 0x10000000 - 0x13ffffff(CS4) | SM107         | SM107
+ * 0x14000000 - 0x17ffffff(CS5) | I2C           | USB
+ * 0x18000000 - 0x1bffffff(CS6) | reserved      | SD
+ * 0x40000000 - 0x5fffffff      | DDR SDRAM     | (cannot use)
+ *
+ */
+
+#define NOR_FLASH_ADDR          0x00000000
+#define NOR_FLASH_SIZE          0x04000000
+
+#define PLD_BASE_ADDR           0x04000000
+#define PLD_PCICR               (PLD_BASE_ADDR + 0x00)
+#define PLD_LCD_BK_CONTR        (PLD_BASE_ADDR + 0x02)
+#define PLD_LOCALCR             (PLD_BASE_ADDR + 0x04)
+#define PLD_POFCR               (PLD_BASE_ADDR + 0x06)
+#define PLD_LEDCR               (PLD_BASE_ADDR + 0x08)
+#define PLD_SWSR                (PLD_BASE_ADDR + 0x0a)
+#define PLD_VERSR               (PLD_BASE_ADDR + 0x0c)
+#define PLD_MMSR                (PLD_BASE_ADDR + 0x0e)
+
+#define SM107_MEM_ADDR          0x10000000
+#define SM107_MEM_SIZE          0x00e00000
+#define SM107_REG_ADDR          0x13e00000
+#define SM107_REG_SIZE          0x00200000
+
+#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
+#define R8A66597_ADDR           0x14000000      /* USB */
+#define CG200_ADDR              0x18000000      /* SD */
+#define PCA9564_ADDR            0x06000000      /* I2C */
+#else
+#define R8A66597_ADDR           0x08000000
+#define CG200_ADDR              0x0c000000
+#define PCA9564_ADDR            0x14000000
+#endif
+
+#define R8A66597_SIZE           0x00000100
+#define CG200_SIZE              0x00010000
+#define PCA9564_SIZE            0x00000100
+
+#endif  /* __ASM_SH_RENESAS_SH7785LCR_H */
+
diff --git a/arch/sh/include/asm/sh_bios.h b/arch/sh/include/asm/sh_bios.h
new file mode 100644
index 000000000000..0ca261956e3d
--- /dev/null
+++ b/arch/sh/include/asm/sh_bios.h
@@ -0,0 +1,19 @@
+#ifndef __ASM_SH_BIOS_H
+#define __ASM_SH_BIOS_H
+
+/*
+ * Copyright (C) 2000 Greg Banks, Mitch Davis
+ * C API to interface to the standard LinuxSH BIOS
+ * usually from within the early stages of kernel boot.
+ */
+
+
+extern void sh_bios_console_write(const char *buf, unsigned int len);
+extern void sh_bios_char_out(char ch);
+extern int sh_bios_in_gdb_mode(void);
+extern void sh_bios_gdb_detach(void);
+
+extern void sh_bios_get_node_addr(unsigned char *node_addr);
+extern void sh_bios_shutdown(unsigned int how);
+
+#endif /* __ASM_SH_BIOS_H */
diff --git a/arch/sh/include/asm/sh_keysc.h b/arch/sh/include/asm/sh_keysc.h
new file mode 100644
index 000000000000..b5a4dd5a9729
--- /dev/null
+++ b/arch/sh/include/asm/sh_keysc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_KEYSC_H__
+#define __ASM_KEYSC_H__
+
+#define SH_KEYSC_MAXKEYS 30
+
+struct sh_keysc_info {
+        enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
+        int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
+        int delay;
+        int keycodes[SH_KEYSC_MAXKEYS];
+};
+
+#endif /* __ASM_KEYSC_H__ */
diff --git a/arch/sh/include/asm/sh_mobile_lcdc.h b/arch/sh/include/asm/sh_mobile_lcdc.h
new file mode 100644
index 000000000000..27677727df4d
--- /dev/null
+++ b/arch/sh/include/asm/sh_mobile_lcdc.h
@@ -0,0 +1,66 @@
+#ifndef __ASM_SH_MOBILE_LCDC_H__
+#define __ASM_SH_MOBILE_LCDC_H__
+
+#include <linux/fb.h>
+
+enum { RGB8,   /* 24bpp, 8:8:8 */
+       RGB9,   /* 18bpp, 9:9 */
+       RGB12A, /* 24bpp, 12:12 */
+       RGB12B, /* 12bpp */
+       RGB16,  /* 16bpp */
+       RGB18,  /* 18bpp */
+       RGB24,  /* 24bpp */
+       SYS8A,  /* 24bpp, 8:8:8 */
+       SYS8B,  /* 18bpp, 8:8:2 */
+       SYS8C,  /* 18bpp, 2:8:8 */
+       SYS8D,  /* 16bpp, 8:8 */
+       SYS9,   /* 18bpp, 9:9 */
+       SYS12,  /* 24bpp, 12:12 */
+       SYS16A, /* 16bpp */
+       SYS16B, /* 18bpp, 16:2 */
+       SYS16C, /* 18bpp, 2:16 */
+       SYS18,  /* 18bpp */
+       SYS24 };/* 24bpp */
+
+enum { LCDC_CHAN_DISABLED = 0,
+       LCDC_CHAN_MAINLCD,
+       LCDC_CHAN_SUBLCD };
+
+enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
+
+struct sh_mobile_lcdc_sys_bus_cfg {
+        unsigned long ldmt2r;
+        unsigned long ldmt3r;
+};
+
+struct sh_mobile_lcdc_sys_bus_ops {
+        void (*write_index)(void *handle, unsigned long data);
+        void (*write_data)(void *handle, unsigned long data);
+        unsigned long (*read_data)(void *handle);
+};
+
+struct sh_mobile_lcdc_board_cfg {
+        void *board_data;
+        int (*setup_sys)(void *board_data, void *sys_ops_handle,
+                         struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
+        void (*display_on)(void *board_data);
+        void (*display_off)(void *board_data);
+};
+
+struct sh_mobile_lcdc_chan_cfg {
+        int chan;
+        int bpp;
+        int interface_type; /* selects RGBn or SYSn I/F, see above */
+        int clock_divider;
+        struct fb_videomode lcd_cfg;
+        struct sh_mobile_lcdc_board_cfg board_cfg;
+        struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
+};
+
+struct sh_mobile_lcdc_info {
+        unsigned long lddckr;
+        int clock_source;
+        struct sh_mobile_lcdc_chan_cfg ch[2];
+};
+
+#endif /* __ASM_SH_MOBILE_LCDC_H__ */
diff --git a/arch/sh/include/asm/shmbuf.h b/arch/sh/include/asm/shmbuf.h
new file mode 100644
index 000000000000..b2101f490521
--- /dev/null
+++ b/arch/sh/include/asm/shmbuf.h
@@ -0,0 +1,42 @@
+#ifndef __ASM_SH_SHMBUF_H
+#define __ASM_SH_SHMBUF_H
+
+/* 
+ * The shmid64_ds structure for i386 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        unsigned long           __unused1;
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        unsigned long           __unused2;
+        __kernel_time_t         shm_ctime;      /* last change time */
+        unsigned long           __unused3;
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused4;
+        unsigned long           __unused5;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* __ASM_SH_SHMBUF_H */
diff --git a/arch/sh/include/asm/shmin.h b/arch/sh/include/asm/shmin.h
new file mode 100644
index 000000000000..36ba138a81fb
--- /dev/null
+++ b/arch/sh/include/asm/shmin.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_SH_SHMIN_H
+#define __ASM_SH_SHMIN_H
+
+#define SHMIN_IO_BASE 0xb0000000UL
+
+#define SHMIN_NE_IRQ IRQ2_IRQ
+#define SHMIN_NE_BASE 0x300
+
+#endif
diff --git a/arch/sh/include/asm/shmparam.h b/arch/sh/include/asm/shmparam.h
new file mode 100644
index 000000000000..ba1758d90106
--- /dev/null
+++ b/arch/sh/include/asm/shmparam.h
@@ -0,0 +1,22 @@
+/*
+ * include/asm-sh/shmparam.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2006 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_SHMPARAM_H
+#define __ASM_SH_SHMPARAM_H
+
+/*
+ * SH-4 and SH-3 7705 have an aliasing dcache. Bump this up to a sensible value
+ * for everyone, and work out the specifics from the probed cache descriptor.
+ */
+#define SHMLBA  0x4000           /* attach addr a multiple of this */
+
+#define __ARCH_FORCE_SHMLBA
+
+#endif /* __ASM_SH_SHMPARAM_H */
diff --git a/arch/sh/include/asm/sigcontext.h b/arch/sh/include/asm/sigcontext.h
new file mode 100644
index 000000000000..8ce1435bc0bf
--- /dev/null
+++ b/arch/sh/include/asm/sigcontext.h
@@ -0,0 +1,40 @@
+#ifndef __ASM_SH_SIGCONTEXT_H
+#define __ASM_SH_SIGCONTEXT_H
+
+struct sigcontext {
+        unsigned long   oldmask;
+
+#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
+        /* CPU registers */
+        unsigned long long sc_regs[63];
+        unsigned long long sc_tregs[8];
+        unsigned long long sc_pc;
+        unsigned long long sc_sr;
+
+        /* FPU registers */
+        unsigned long long sc_fpregs[32];
+        unsigned int sc_fpscr;
+        unsigned int sc_fpvalid;
+#else
+        /* CPU registers */
+        unsigned long sc_regs[16];
+        unsigned long sc_pc;
+        unsigned long sc_pr;
+        unsigned long sc_sr;
+        unsigned long sc_gbr;
+        unsigned long sc_mach;
+        unsigned long sc_macl;
+
+#if defined(__SH4__) || defined(CONFIG_CPU_SH4) || \
+    defined(__SH2A__) || defined(CONFIG_CPU_SH2A)
+        /* FPU registers */
+        unsigned long sc_fpregs[16];
+        unsigned long sc_xfpregs[16];
+        unsigned int sc_fpscr;
+        unsigned int sc_fpul;
+        unsigned int sc_ownedfp;
+#endif
+#endif
+};
+
+#endif /* __ASM_SH_SIGCONTEXT_H */
diff --git a/arch/sh/include/asm/siginfo.h b/arch/sh/include/asm/siginfo.h
new file mode 100644
index 000000000000..813040ed68a9
--- /dev/null
+++ b/arch/sh/include/asm/siginfo.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_SIGINFO_H
+#define __ASM_SH_SIGINFO_H
+
+#include <asm-generic/siginfo.h>
+
+#endif /* __ASM_SH_SIGINFO_H */
diff --git a/arch/sh/include/asm/signal.h b/arch/sh/include/asm/signal.h
new file mode 100644
index 000000000000..5c5c1e852089
--- /dev/null
+++ b/arch/sh/include/asm/signal.h
@@ -0,0 +1,160 @@
+#ifndef __ASM_SH_SIGNAL_H
+#define __ASM_SH_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct pt_regs;
+struct siginfo;
+
+#ifdef __KERNEL__
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define _NSIG           64
+#define _NSIG_BPW       32
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+#define NSIG            32
+typedef unsigned long sigset_t;
+
+#endif /* __KERNEL__ */
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002
+#define SA_SIGINFO      0x00000004
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000
+
+/* 
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#include <asm-generic/signal.h>
+
+#ifdef __KERNEL__
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+struct sigaction {
+        union {
+          __sighandler_t _sa_handler;
+          void (*_sa_sigaction)(int, struct siginfo *, void *);
+        } _u;
+        sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+#define sa_handler      _u._sa_handler
+#define sa_sigaction    _u._sa_sigaction
+
+#endif /* __KERNEL__ */
+
+typedef struct sigaltstack {
+        void *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_SIGNAL_H */
diff --git a/arch/sh/include/asm/smc37c93x.h b/arch/sh/include/asm/smc37c93x.h
new file mode 100644
index 000000000000..585da2a8fc45
--- /dev/null
+++ b/arch/sh/include/asm/smc37c93x.h
@@ -0,0 +1,190 @@
+#ifndef __ASM_SH_SMC37C93X_H
+#define __ASM_SH_SMC37C93X_H
+
+/*
+ * linux/include/asm-sh/smc37c93x.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * SMSC 37C93x Super IO Chip support
+ */
+
+/* Default base I/O address */
+#define FDC_PRIMARY_BASE        0x3f0
+#define IDE1_PRIMARY_BASE       0x1f0
+#define IDE1_SECONDARY_BASE     0x170
+#define PARPORT_PRIMARY_BASE    0x378
+#define COM1_PRIMARY_BASE       0x2f8
+#define COM2_PRIMARY_BASE       0x3f8
+#define RTC_PRIMARY_BASE        0x070
+#define KBC_PRIMARY_BASE        0x060
+#define AUXIO_PRIMARY_BASE      0x000   /* XXX */
+
+/* Logical device number */
+#define LDN_FDC                 0
+#define LDN_IDE1                1
+#define LDN_IDE2                2
+#define LDN_PARPORT             3
+#define LDN_COM1                4
+#define LDN_COM2                5
+#define LDN_RTC                 6
+#define LDN_KBC                 7
+#define LDN_AUXIO               8
+
+/* Configuration port and key */
+#define CONFIG_PORT             0x3f0
+#define INDEX_PORT              CONFIG_PORT
+#define DATA_PORT               0x3f1
+#define CONFIG_ENTER            0x55
+#define CONFIG_EXIT             0xaa
+
+/* Configuration index */
+#define CURRENT_LDN_INDEX       0x07
+#define POWER_CONTROL_INDEX     0x22
+#define ACTIVATE_INDEX          0x30
+#define IO_BASE_HI_INDEX        0x60
+#define IO_BASE_LO_INDEX        0x61
+#define IRQ_SELECT_INDEX        0x70
+#define DMA_SELECT_INDEX        0x74
+
+#define GPIO46_INDEX            0xc6
+#define GPIO47_INDEX            0xc7
+
+/* UART stuff. Only for debugging.  */
+/* UART Register */
+
+#define UART_RBR        0x0     /* Receiver Buffer Register (Read Only) */
+#define UART_THR        0x0     /* Transmitter Holding Register (Write Only) */
+#define UART_IER        0x2     /* Interrupt Enable Register */
+#define UART_IIR        0x4     /* Interrupt Ident Register (Read Only) */
+#define UART_FCR        0x4     /* FIFO Control Register (Write Only) */
+#define UART_LCR        0x6     /* Line Control Register */
+#define UART_MCR        0x8     /* MODEM Control Register */
+#define UART_LSR        0xa     /* Line Status Register */
+#define UART_MSR        0xc     /* MODEM Status Register */
+#define UART_SCR        0xe     /* Scratch Register */
+#define UART_DLL        0x0     /* Divisor Latch (LS) */
+#define UART_DLM        0x2     /* Divisor Latch (MS) */
+
+#ifndef __ASSEMBLY__
+typedef struct uart_reg {
+        volatile __u16 rbr;
+        volatile __u16 ier;
+        volatile __u16 iir;
+        volatile __u16 lcr;
+        volatile __u16 mcr;
+        volatile __u16 lsr;
+        volatile __u16 msr;
+        volatile __u16 scr;
+} uart_reg;
+#endif /* ! __ASSEMBLY__ */
+
+/* Alias for Write Only Register */
+
+#define thr     rbr
+#define tcr     iir
+
+/* Alias for Divisor Latch Register */
+
+#define dll     rbr
+#define dlm     ier
+#define fcr     iir
+
+/* Interrupt Enable Register */
+
+#define IER_ERDAI       0x0100  /* Enable Received Data Available Interrupt */
+#define IER_ETHREI      0x0200  /* Enable Transmitter Holding Register Empty Interrupt */
+#define IER_ELSI        0x0400  /* Enable Receiver Line Status Interrupt */
+#define IER_EMSI        0x0800  /* Enable MODEM Status Interrupt */
+
+/* Interrupt Ident Register */
+
+#define IIR_IP          0x0100  /* "0" if Interrupt Pending */
+#define IIR_IIB0        0x0200  /* Interrupt ID Bit 0 */
+#define IIR_IIB1        0x0400  /* Interrupt ID Bit 1 */
+#define IIR_IIB2        0x0800  /* Interrupt ID Bit 2 */
+#define IIR_FIFO        0xc000  /* FIFOs enabled */
+
+/* FIFO Control Register */
+
+#define FCR_FEN         0x0100  /* FIFO enable */
+#define FCR_RFRES       0x0200  /* Receiver FIFO reset */
+#define FCR_TFRES       0x0400  /* Transmitter FIFO reset */
+#define FCR_DMA         0x0800  /* DMA mode select */
+#define FCR_RTL         0x4000  /* Receiver triger (LSB) */
+#define FCR_RTM         0x8000  /* Receiver triger (MSB) */
+
+/* Line Control Register */
+
+#define LCR_WLS0        0x0100  /* Word Length Select Bit 0 */
+#define LCR_WLS1        0x0200  /* Word Length Select Bit 1 */
+#define LCR_STB         0x0400  /* Number of Stop Bits */
+#define LCR_PEN         0x0800  /* Parity Enable */
+#define LCR_EPS         0x1000  /* Even Parity Select */
+#define LCR_SP          0x2000  /* Stick Parity */
+#define LCR_SB          0x4000  /* Set Break */
+#define LCR_DLAB        0x8000  /* Divisor Latch Access Bit */
+
+/* MODEM Control Register */
+
+#define MCR_DTR         0x0100  /* Data Terminal Ready */
+#define MCR_RTS         0x0200  /* Request to Send */
+#define MCR_OUT1        0x0400  /* Out 1 */
+#define MCR_IRQEN       0x0800  /* IRQ Enable */
+#define MCR_LOOP        0x1000  /* Loop */
+
+/* Line Status Register */
+
+#define LSR_DR          0x0100  /* Data Ready */
+#define LSR_OE          0x0200  /* Overrun Error */
+#define LSR_PE          0x0400  /* Parity Error */
+#define LSR_FE          0x0800  /* Framing Error */
+#define LSR_BI          0x1000  /* Break Interrupt */
+#define LSR_THRE        0x2000  /* Transmitter Holding Register Empty */
+#define LSR_TEMT        0x4000  /* Transmitter Empty */
+#define LSR_FIFOE       0x8000  /* Receiver FIFO error */
+
+/* MODEM Status Register */
+
+#define MSR_DCTS        0x0100  /* Delta Clear to Send */
+#define MSR_DDSR        0x0200  /* Delta Data Set Ready */
+#define MSR_TERI        0x0400  /* Trailing Edge Ring Indicator */
+#define MSR_DDCD        0x0800  /* Delta Data Carrier Detect */
+#define MSR_CTS         0x1000  /* Clear to Send */
+#define MSR_DSR         0x2000  /* Data Set Ready */
+#define MSR_RI          0x4000  /* Ring Indicator */
+#define MSR_DCD         0x8000  /* Data Carrier Detect */
+
+/* Baud Rate Divisor */
+
+#define UART_CLK        (1843200)       /* 1.8432 MHz */
+#define UART_BAUD(x)    (UART_CLK / (16 * (x)))
+
+/* RTC register definition */
+#define RTC_SECONDS             0
+#define RTC_SECONDS_ALARM       1
+#define RTC_MINUTES             2
+#define RTC_MINUTES_ALARM       3
+#define RTC_HOURS               4
+#define RTC_HOURS_ALARM         5
+#define RTC_DAY_OF_WEEK         6
+#define RTC_DAY_OF_MONTH        7
+#define RTC_MONTH               8
+#define RTC_YEAR                9
+#define RTC_FREQ_SELECT         10
+# define RTC_UIP 0x80
+# define RTC_DIV_CTL 0x70
+/* This RTC can work under 32.768KHz clock only.  */
+# define RTC_OSC_ENABLE 0x20
+# define RTC_OSC_DISABLE 0x00
+#define RTC_CONTROL             11
+# define RTC_SET 0x80
+# define RTC_PIE 0x40
+# define RTC_AIE 0x20
+# define RTC_UIE 0x10
+# define RTC_SQWE 0x08
+# define RTC_DM_BINARY 0x04
+# define RTC_24H 0x02
+# define RTC_DST_EN 0x01
+
+#endif  /* __ASM_SH_SMC37C93X_H */
diff --git a/arch/sh/include/asm/smp.h b/arch/sh/include/asm/smp.h
new file mode 100644
index 000000000000..593343cd26ee
--- /dev/null
+++ b/arch/sh/include/asm/smp.h
@@ -0,0 +1,50 @@
+#ifndef __ASM_SH_SMP_H
+#define __ASM_SH_SMP_H
+
+#include <linux/bitops.h>
+#include <linux/cpumask.h>
+
+#ifdef CONFIG_SMP
+
+#include <linux/spinlock.h>
+#include <asm/atomic.h>
+#include <asm/current.h>
+
+#define raw_smp_processor_id()  (current_thread_info()->cpu)
+#define hard_smp_processor_id() plat_smp_processor_id()
+
+/* Map from cpu id to sequential logical cpu number. */
+extern int __cpu_number_map[NR_CPUS];
+#define cpu_number_map(cpu)  __cpu_number_map[cpu]
+
+/* The reverse map from sequential logical cpu number to cpu id.  */
+extern int __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
+
+/* I've no idea what the real meaning of this is */
+#define PROC_CHANGE_PENALTY     20
+
+#define NO_PROC_ID      (-1)
+
+#define SMP_MSG_FUNCTION        0
+#define SMP_MSG_RESCHEDULE      1
+#define SMP_MSG_FUNCTION_SINGLE 2
+#define SMP_MSG_NR              3
+
+void plat_smp_setup(void);
+void plat_prepare_cpus(unsigned int max_cpus);
+int plat_smp_processor_id(void);
+void plat_start_cpu(unsigned int cpu, unsigned long entry_point);
+void plat_send_ipi(unsigned int cpu, unsigned int message);
+int plat_register_ipi_handler(unsigned int message,
+                              void (*handler)(void *), void *arg);
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
+#else
+
+#define hard_smp_processor_id() (0)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_SH_SMP_H */
diff --git a/arch/sh/include/asm/snapgear.h b/arch/sh/include/asm/snapgear.h
new file mode 100644
index 000000000000..042d95f51c4d
--- /dev/null
+++ b/arch/sh/include/asm/snapgear.h
@@ -0,0 +1,71 @@
+/*
+ * include/asm-sh/snapgear.h
+ *
+ * Modified version of io_se.h for the snapgear-specific functions.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * IO functions for a SnapGear
+ */
+
+#ifndef _ASM_SH_IO_SNAPGEAR_H
+#define _ASM_SH_IO_SNAPGEAR_H
+
+#if defined(CONFIG_CPU_SH4)
+/*
+ * The external interrupt lines, these take up ints 0 - 15 inclusive
+ * depending on the priority for the interrupt.  In fact the priority
+ * is the interrupt :-)
+ */
+
+#define IRL0_IRQ        2
+#define IRL0_PRIORITY   13
+
+#define IRL1_IRQ        5
+#define IRL1_PRIORITY   10
+
+#define IRL2_IRQ        8
+#define IRL2_PRIORITY   7
+
+#define IRL3_IRQ        11
+#define IRL3_PRIORITY   4
+#endif
+
+#define __IO_PREFIX     snapgear
+#include <asm/io_generic.h>
+
+#ifdef CONFIG_SH_SECUREEDGE5410
+/*
+ * We need to remember what was written to the ioport as some bits
+ * are shared with other functions and you cannot read back what was
+ * written :-|
+ *
+ * Bit        Read                   Write
+ * -----------------------------------------------
+ * D0         DCD on ttySC1          power
+ * D1         Reset Switch           heatbeat
+ * D2         ttySC0 CTS (7100)      LAN
+ * D3         -                      WAN
+ * D4         ttySC0 DCD (7100)      CONSOLE
+ * D5         -                      ONLINE
+ * D6         -                      VPN
+ * D7         -                      DTR on ttySC1
+ * D8         -                      ttySC0 RTS (7100)
+ * D9         -                      ttySC0 DTR (7100)
+ * D10        -                      RTC SCLK
+ * D11        RTC DATA               RTC DATA
+ * D12        -                      RTS RESET
+ */
+
+#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
+extern unsigned short secureedge5410_ioport;
+
+#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
+         (secureedge5410_ioport = \
+                        ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
+#define SECUREEDGE_READ_IOPORT() \
+         ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
+#endif
+
+#endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/arch/sh/include/asm/socket.h b/arch/sh/include/asm/socket.h
new file mode 100644
index 000000000000..6d4bf6512959
--- /dev/null
+++ b/arch/sh/include/asm/socket.h
@@ -0,0 +1,57 @@
+#ifndef __ASM_SH_SOCKET_H
+#define __ASM_SH_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_RCVBUFFORCE  32
+#define SO_SNDBUFFORCE  33
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC              31
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#endif /* __ASM_SH_SOCKET_H */
diff --git a/arch/sh/include/asm/sockios.h b/arch/sh/include/asm/sockios.h
new file mode 100644
index 000000000000..cf8b96b1f9ab
--- /dev/null
+++ b/arch/sh/include/asm/sockios.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_SH_SOCKIOS_H
+#define __ASM_SH_SOCKIOS_H
+
+/* Socket-level I/O control calls. */
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP      _IOR('s', 100, struct timeval) /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    _IOR('s', 101, struct timespec) /* Get stamp (timespec) */
+#endif /* __ASM_SH_SOCKIOS_H */
diff --git a/arch/sh/include/asm/sparsemem.h b/arch/sh/include/asm/sparsemem.h
new file mode 100644
index 000000000000..547a540b6667
--- /dev/null
+++ b/arch/sh/include/asm/sparsemem.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_SH_SPARSEMEM_H
+#define __ASM_SH_SPARSEMEM_H
+
+#ifdef __KERNEL__
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSADDR_BITS            2^N: how much physical address space we have
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#define SECTION_SIZE_BITS       26
+#define MAX_PHYSADDR_BITS       32
+#define MAX_PHYSMEM_BITS        32
+
+#endif
+
+#endif /* __ASM_SH_SPARSEMEM_H */
diff --git a/arch/sh/include/asm/spi.h b/arch/sh/include/asm/spi.h
new file mode 100644
index 000000000000..e96f5b0953c8
--- /dev/null
+++ b/arch/sh/include/asm/spi.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SPI_H__
+#define __ASM_SPI_H__
+
+struct sh_spi_info;
+
+struct sh_spi_info {
+        int                      bus_num;
+        int                      num_chipselect;
+
+        void (*chip_select)(struct sh_spi_info *spi, int cs, int state);
+};
+
+#endif /* __ASM_SPI_H__ */
diff --git a/arch/sh/include/asm/spinlock.h b/arch/sh/include/asm/spinlock.h
new file mode 100644
index 000000000000..e793181d64da
--- /dev/null
+++ b/arch/sh/include/asm/spinlock.h
@@ -0,0 +1,223 @@
+/*
+ * include/asm-sh/spinlock.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ * Copyright (C) 2006, 2007 Akio Idehara
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_SPINLOCK_H
+#define __ASM_SH_SPINLOCK_H
+
+/*
+ * The only locking implemented here uses SH-4A opcodes. For others,
+ * split this out as per atomic-*.h.
+ */
+#ifndef CONFIG_CPU_SH4A
+#error "Need movli.l/movco.l for spinlocks"
+#endif
+
+/*
+ * Your basic SMP spinlocks, allowing only a single CPU anywhere
+ */
+
+#define __raw_spin_is_locked(x)         ((x)->lock <= 0)
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define __raw_spin_unlock_wait(x) \
+        do { cpu_relax(); } while ((x)->lock)
+
+/*
+ * Simple spin lock operations.  There are two variants, one clears IRQ's
+ * on the local processor, one does not.
+ *
+ * We make no fairness assumptions.  They have a cost.
+ */
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+        unsigned long tmp;
+        unsigned long oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_spin_lock       \n\t"
+                "mov            %0, %1                          \n\t"
+                "mov            #0, %0                          \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "cmp/pl         %1                              \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&lock->lock)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "mov            #1, %0 ! __raw_spin_unlock      \n\t"
+                "mov.l          %0, @%1                         \n\t"
+                : "=&z" (tmp)
+                : "r" (&lock->lock)
+                : "t", "memory"
+        );
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+        unsigned long tmp, oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_spin_trylock    \n\t"
+                "mov            %0, %1                          \n\t"
+                "mov            #0, %0                          \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&lock->lock)
+                : "t", "memory"
+        );
+
+        return oldval;
+}
+
+/*
+ * Read-write spinlocks, allowing multiple readers but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts but no interrupt
+ * writers. For those circumstances we can "mix" irq-safe locks - any writer
+ * needs to get a irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_read_can_lock(x)  ((x)->lock > 0)
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
+
+static inline void __raw_read_lock(raw_rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! __raw_read_lock       \n\t"
+                "cmp/pl         %0                              \n\t"
+                "bf             1b                              \n\t"
+                "add            #-1, %0                         \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp)
+                : "r" (&rw->lock)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! __raw_read_unlock     \n\t"
+                "add            #1, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp)
+                : "r" (&rw->lock)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%1, %0 ! __raw_write_lock      \n\t"
+                "cmp/hs         %2, %0                          \n\t"
+                "bf             1b                              \n\t"
+                "sub            %2, %0                          \n\t"
+                "movco.l        %0, @%1                         \n\t"
+                "bf             1b                              \n\t"
+                : "=&z" (tmp)
+                : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+                : "t", "memory"
+        );
+}
+
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+        __asm__ __volatile__ (
+                "mov.l          %1, @%0 ! __raw_write_unlock    \n\t"
+                :
+                : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+                : "t", "memory"
+        );
+}
+
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+        unsigned long tmp, oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_read_trylock    \n\t"
+                "mov            %0, %1                          \n\t"
+                "cmp/pl         %0                              \n\t"
+                "bf             2f                              \n\t"
+                "add            #-1, %0                         \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "2:                                             \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&rw->lock)
+                : "t", "memory"
+        );
+
+        return (oldval > 0);
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+        unsigned long tmp, oldval;
+
+        __asm__ __volatile__ (
+                "1:                                             \n\t"
+                "movli.l        @%2, %0 ! __raw_write_trylock   \n\t"
+                "mov            %0, %1                          \n\t"
+                "cmp/hs         %3, %0                          \n\t"
+                "bf             2f                              \n\t"
+                "sub            %3, %0                          \n\t"
+                "2:                                             \n\t"
+                "movco.l        %0, @%2                         \n\t"
+                "bf             1b                              \n\t"
+                "synco                                          \n\t"
+                : "=&z" (tmp), "=&r" (oldval)
+                : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
+                : "t", "memory"
+        );
+
+        return (oldval > (RW_LOCK_BIAS - 1));
+}
+
+#define _raw_spin_relax(lock)   cpu_relax()
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#endif /* __ASM_SH_SPINLOCK_H */
diff --git a/arch/sh/include/asm/spinlock_types.h b/arch/sh/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..b4d244e7b60c
--- /dev/null
+++ b/arch/sh/include/asm/spinlock_types.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_SH_SPINLOCK_TYPES_H
+#define __ASM_SH_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED                { 1 }
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_rwlock_t;
+
+#define RW_LOCK_BIAS                    0x01000000
+#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+
+#endif
diff --git a/arch/sh/include/asm/stat.h b/arch/sh/include/asm/stat.h
new file mode 100644
index 000000000000..e1810cc6e3da
--- /dev/null
+++ b/arch/sh/include/asm/stat.h
@@ -0,0 +1,138 @@
+#ifndef __ASM_SH_STAT_H
+#define __ASM_SH_STAT_H
+
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
+struct stat {
+        unsigned short st_dev;
+        unsigned short __pad1;
+        unsigned long st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned short __pad2;
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+        unsigned short  st_dev;
+        unsigned char   __pad0[10];
+
+        unsigned long   st_ino;
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned long   st_uid;
+        unsigned long   st_gid;
+
+        unsigned short  st_rdev;
+        unsigned char   __pad3[10];
+
+        long long       st_size;
+        unsigned long   st_blksize;
+
+        unsigned long   st_blocks;      /* Number 512-byte blocks allocated. */
+        unsigned long   __pad4;         /* future possible st_blocks high bits */
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;  /* will be high 32 bits of ctime someday */
+
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+#else
+struct stat {
+        unsigned long  st_dev;
+        unsigned long  st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned long  st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+        unsigned long long      st_dev;
+        unsigned char   __pad0[4];
+
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long   __st_ino;
+
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned long   st_uid;
+        unsigned long   st_gid;
+
+        unsigned long long      st_rdev;
+        unsigned char   __pad3[4];
+
+        long long       st_size;
+        unsigned long   st_blksize;
+
+        unsigned long long      st_blocks;      /* Number 512-byte blocks allocated. */
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+
+        unsigned long long      st_ino;
+};
+
+#define STAT_HAVE_NSEC 1
+#endif
+
+#endif /* __ASM_SH_STAT_H */
diff --git a/arch/sh/include/asm/statfs.h b/arch/sh/include/asm/statfs.h
new file mode 100644
index 000000000000..9202a023328f
--- /dev/null
+++ b/arch/sh/include/asm/statfs.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_STATFS_H
+#define __ASM_SH_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif /* __ASM_SH_STATFS_H */
diff --git a/arch/sh/include/asm/string.h b/arch/sh/include/asm/string.h
new file mode 100644
index 000000000000..8c1ea21dc0ae
--- /dev/null
+++ b/arch/sh/include/asm/string.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_SUPERH32
+# include "string_32.h"
+#else
+# include "string_64.h"
+#endif
diff --git a/arch/sh/include/asm/string_32.h b/arch/sh/include/asm/string_32.h
new file mode 100644
index 000000000000..55f8db6bc1d7
--- /dev/null
+++ b/arch/sh/include/asm/string_32.h
@@ -0,0 +1,131 @@
+#ifndef __ASM_SH_STRING_H
+#define __ASM_SH_STRING_H
+
+#ifdef __KERNEL__
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * But consider these trivial functions to be public domain.
+ */
+
+#define __HAVE_ARCH_STRCPY
+static inline char *strcpy(char *__dest, const char *__src)
+{
+        register char *__xdest = __dest;
+        unsigned long __dummy;
+
+        __asm__ __volatile__("1:\n\t"
+                             "mov.b     @%1+, %2\n\t"
+                             "mov.b     %2, @%0\n\t"
+                             "cmp/eq    #0, %2\n\t"
+                             "bf/s      1b\n\t"
+                             " add      #1, %0\n\t"
+                             : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+                             : "0" (__dest), "1" (__src)
+                             : "memory", "t");
+
+        return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *__dest, const char *__src, size_t __n)
+{
+        register char *__xdest = __dest;
+        unsigned long __dummy;
+
+        if (__n == 0)
+                return __xdest;
+
+        __asm__ __volatile__(
+                "1:\n"
+                "mov.b  @%1+, %2\n\t"
+                "mov.b  %2, @%0\n\t"
+                "cmp/eq #0, %2\n\t"
+                "bt/s   2f\n\t"
+                " cmp/eq        %5,%1\n\t"
+                "bf/s   1b\n\t"
+                " add   #1, %0\n"
+                "2:"
+                : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+                : "0" (__dest), "1" (__src), "r" (__src+__n)
+                : "memory", "t");
+
+        return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *__cs, const char *__ct)
+{
+        register int __res;
+        unsigned long __dummy;
+
+        __asm__ __volatile__(
+                "mov.b  @%1+, %3\n"
+                "1:\n\t"
+                "mov.b  @%0+, %2\n\t"
+                "cmp/eq #0, %3\n\t"
+                "bt     2f\n\t"
+                "cmp/eq %2, %3\n\t"
+                "bt/s   1b\n\t"
+                " mov.b @%1+, %3\n\t"
+                "add    #-2, %1\n\t"
+                "mov.b  @%1, %3\n\t"
+                "sub    %3, %2\n"
+                "2:"
+                : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+                : "0" (__cs), "1" (__ct)
+                : "t");
+
+        return __res;
+}
+
+#define __HAVE_ARCH_STRNCMP
+static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
+{
+        register int __res;
+        unsigned long __dummy;
+
+        if (__n == 0)
+                return 0;
+
+        __asm__ __volatile__(
+                "mov.b  @%1+, %3\n"
+                "1:\n\t"
+                "mov.b  @%0+, %2\n\t"
+                "cmp/eq %6, %0\n\t"
+                "bt/s   2f\n\t"
+                " cmp/eq #0, %3\n\t"
+                "bt/s   3f\n\t"
+                " cmp/eq %3, %2\n\t"
+                "bt/s   1b\n\t"
+                " mov.b @%1+, %3\n\t"
+                "add    #-2, %1\n\t"
+                "mov.b  @%1, %3\n"
+                "2:\n\t"
+                "sub    %3, %2\n"
+                "3:"
+                :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+                : "0" (__cs), "1" (__ct), "r" (__cs+__n)
+                : "t");
+
+        return __res;
+}
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#define __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *__s, int __c, size_t __n);
+
+#define __HAVE_ARCH_STRLEN
+extern size_t strlen(const char *);
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_STRING_H */
diff --git a/arch/sh/include/asm/string_64.h b/arch/sh/include/asm/string_64.h
new file mode 100644
index 000000000000..aa1fef229c78
--- /dev/null
+++ b/arch/sh/include/asm/string_64.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_SH_STRING_64_H
+#define __ASM_SH_STRING_64_H
+
+/*
+ * include/asm-sh/string_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *dest, const void *src, size_t count);
+
+#endif /* __ASM_SH_STRING_64_H */
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
new file mode 100644
index 000000000000..056d68cd2108
--- /dev/null
+++ b/arch/sh/include/asm/system.h
@@ -0,0 +1,190 @@
+#ifndef __ASM_SH_SYSTEM_H
+#define __ASM_SH_SYSTEM_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
+ * Copyright (C) 2002 Paul Mundt
+ */
+
+#include <linux/irqflags.h>
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
+
+#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
+#define __icbi()                        \
+{                                       \
+        unsigned long __addr;           \
+        __addr = 0xa8000000;            \
+        __asm__ __volatile__(           \
+                "icbi   %0\n\t"         \
+                : /* no output */       \
+                : "m" (__m(__addr)));   \
+}
+#endif
+
+/*
+ * A brief note on ctrl_barrier(), the control register write barrier.
+ *
+ * Legacy SH cores typically require a sequence of 8 nops after
+ * modification of a control register in order for the changes to take
+ * effect. On newer cores (like the sh4a and sh5) this is accomplished
+ * with icbi.
+ *
+ * Also note that on sh4a in the icbi case we can forego a synco for the
+ * write barrier, as it's not necessary for control registers.
+ *
+ * Historically we have only done this type of barrier for the MMUCR, but
+ * it's also necessary for the CCR, so we make it generic here instead.
+ */
+#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
+#define mb()            __asm__ __volatile__ ("synco": : :"memory")
+#define rmb()           mb()
+#define wmb()           __asm__ __volatile__ ("synco": : :"memory")
+#define ctrl_barrier()  __icbi()
+#define read_barrier_depends()  do { } while(0)
+#else
+#define mb()            __asm__ __volatile__ ("": : :"memory")
+#define rmb()           mb()
+#define wmb()           __asm__ __volatile__ ("": : :"memory")
+#define ctrl_barrier()  __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
+#define read_barrier_depends()  do { } while(0)
+#endif
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif
+
+#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
+
+#ifdef CONFIG_GUSA_RB
+#include <asm/cmpxchg-grb.h>
+#else
+#include <asm/cmpxchg-irq.h>
+#endif
+
+extern void __xchg_called_with_bad_pointer(void);
+
+#define __xchg(ptr, x, size)                            \
+({                                                      \
+        unsigned long __xchg__res;                      \
+        volatile void *__xchg_ptr = (ptr);              \
+        switch (size) {                                 \
+        case 4:                                         \
+                __xchg__res = xchg_u32(__xchg_ptr, x);  \
+                break;                                  \
+        case 1:                                         \
+                __xchg__res = xchg_u8(__xchg_ptr, x);   \
+                break;                                  \
+        default:                                        \
+                __xchg_called_with_bad_pointer();       \
+                __xchg__res = x;                        \
+                break;                                  \
+        }                                               \
+                                                        \
+        __xchg__res;                                    \
+})
+
+#define xchg(ptr,x)     \
+        ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
+
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
+                unsigned long new, int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32(ptr, old, new);
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)                                                 \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
+
+extern void *set_exception_table_vec(unsigned int vec, void *handler);
+
+static inline void *set_exception_table_evt(unsigned int evt, void *handler)
+{
+        return set_exception_table_vec(evt >> 5, handler);
+}
+
+/*
+ * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
+ */
+#ifdef CONFIG_CPU_SH2A
+extern unsigned int instruction_size(unsigned int insn);
+#elif defined(CONFIG_SUPERH32)
+#define instruction_size(insn)  (2)
+#else
+#define instruction_size(insn)  (4)
+#endif
+
+extern unsigned long cached_to_uncached;
+
+extern struct dentry *sh_debugfs_root;
+
+void per_cpu_trap_init(void);
+
+asmlinkage void break_point_trap(void);
+
+#ifdef CONFIG_SUPERH32
+#define BUILD_TRAP_HANDLER(name)                                        \
+asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
+                                    unsigned long r6, unsigned long r7, \
+                                    struct pt_regs __regs)
+
+#define TRAP_HANDLER_DECL                               \
+        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);  \
+        unsigned int vec = regs->tra;                   \
+        (void)vec;
+#else
+#define BUILD_TRAP_HANDLER(name)        \
+asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
+#define TRAP_HANDLER_DECL
+#endif
+
+BUILD_TRAP_HANDLER(address_error);
+BUILD_TRAP_HANDLER(debug);
+BUILD_TRAP_HANDLER(bug);
+BUILD_TRAP_HANDLER(fpu_error);
+BUILD_TRAP_HANDLER(fpu_state_restore);
+
+#define arch_align_stack(x) (x)
+
+struct mem_access {
+        unsigned long (*from)(void *dst, const void *src, unsigned long cnt);
+        unsigned long (*to)(void *dst, const void *src, unsigned long cnt);
+};
+
+#ifdef CONFIG_SUPERH32
+# include "system_32.h"
+#else
+# include "system_64.h"
+#endif
+
+#endif
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
new file mode 100644
index 000000000000..f11bcf0855ed
--- /dev/null
+++ b/arch/sh/include/asm/system_32.h
@@ -0,0 +1,102 @@
+#ifndef __ASM_SH_SYSTEM_32_H
+#define __ASM_SH_SYSTEM_32_H
+
+#include <linux/types.h>
+
+struct task_struct *__switch_to(struct task_struct *prev,
+                                struct task_struct *next);
+
+/*
+ *      switch_to() should switch tasks to task nr n, first
+ */
+#define switch_to(prev, next, last)                                     \
+do {                                                                    \
+        register u32 *__ts1 __asm__ ("r1") = (u32 *)&prev->thread.sp;   \
+        register u32 *__ts2 __asm__ ("r2") = (u32 *)&prev->thread.pc;   \
+        register u32 *__ts4 __asm__ ("r4") = (u32 *)prev;               \
+        register u32 *__ts5 __asm__ ("r5") = (u32 *)next;               \
+        register u32 *__ts6 __asm__ ("r6") = (u32 *)&next->thread.sp;   \
+        register u32 __ts7 __asm__ ("r7") = next->thread.pc;            \
+        struct task_struct *__last;                                     \
+                                                                        \
+        __asm__ __volatile__ (                                          \
+                ".balign 4\n\t"                                         \
+                "stc.l  gbr, @-r15\n\t"                                 \
+                "sts.l  pr, @-r15\n\t"                                  \
+                "mov.l  r8, @-r15\n\t"                                  \
+                "mov.l  r9, @-r15\n\t"                                  \
+                "mov.l  r10, @-r15\n\t"                                 \
+                "mov.l  r11, @-r15\n\t"                                 \
+                "mov.l  r12, @-r15\n\t"                                 \
+                "mov.l  r13, @-r15\n\t"                                 \
+                "mov.l  r14, @-r15\n\t"                                 \
+                "mov.l  r15, @r1\t! save SP\n\t"                        \
+                "mov.l  @r6, r15\t! change to new stack\n\t"            \
+                "mova   1f, %0\n\t"                                     \
+                "mov.l  %0, @r2\t! save PC\n\t"                         \
+                "mov.l  2f, %0\n\t"                                     \
+                "jmp    @%0\t! call __switch_to\n\t"                    \
+                " lds   r7, pr\t!  with return to new PC\n\t"           \
+                ".balign        4\n"                                    \
+                "2:\n\t"                                                \
+                ".long  __switch_to\n"                                  \
+                "1:\n\t"                                                \
+                "mov.l  @r15+, r14\n\t"                                 \
+                "mov.l  @r15+, r13\n\t"                                 \
+                "mov.l  @r15+, r12\n\t"                                 \
+                "mov.l  @r15+, r11\n\t"                                 \
+                "mov.l  @r15+, r10\n\t"                                 \
+                "mov.l  @r15+, r9\n\t"                                  \
+                "mov.l  @r15+, r8\n\t"                                  \
+                "lds.l  @r15+, pr\n\t"                                  \
+                "ldc.l  @r15+, gbr\n\t"                                 \
+                : "=z" (__last)                                         \
+                : "r" (__ts1), "r" (__ts2), "r" (__ts4),                \
+                  "r" (__ts5), "r" (__ts6), "r" (__ts7)                 \
+                : "r3", "t");                                           \
+                                                                        \
+        last = __last;                                                  \
+} while (0)
+
+#define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text")))
+
+/*
+ * Jump to uncached area.
+ * When handling TLB or caches, we need to do it from an uncached area.
+ */
+#define jump_to_uncached()                      \
+do {                                            \
+        unsigned long __dummy;                  \
+                                                \
+        __asm__ __volatile__(                   \
+                "mova   1f, %0\n\t"             \
+                "add    %1, %0\n\t"             \
+                "jmp    @%0\n\t"                \
+                " nop\n\t"                      \
+                ".balign 4\n"                   \
+                "1:"                            \
+                : "=&z" (__dummy)               \
+                : "r" (cached_to_uncached));    \
+} while (0)
+
+/*
+ * Back to cached area.
+ */
+#define back_to_cached()                                \
+do {                                                    \
+        unsigned long __dummy;                          \
+        ctrl_barrier();                                 \
+        __asm__ __volatile__(                           \
+                "mov.l  1f, %0\n\t"                     \
+                "jmp    @%0\n\t"                        \
+                " nop\n\t"                              \
+                ".balign 4\n"                           \
+                "1:     .long 2f\n"                     \
+                "2:"                                    \
+                : "=&r" (__dummy));                     \
+} while (0)
+
+int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
+                            struct mem_access *ma);
+
+#endif /* __ASM_SH_SYSTEM_32_H */
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
new file mode 100644
index 000000000000..943acf5ea07c
--- /dev/null
+++ b/arch/sh/include/asm/system_64.h
@@ -0,0 +1,40 @@
+#ifndef __ASM_SH_SYSTEM_64_H
+#define __ASM_SH_SYSTEM_64_H
+
+/*
+ * include/asm-sh/system_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003  Paul Mundt
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/processor.h>
+
+/*
+ *      switch_to() should switch tasks to task nr n, first
+ */
+struct task_struct *sh64_switch_to(struct task_struct *prev,
+                                   struct thread_struct *prev_thread,
+                                   struct task_struct *next,
+                                   struct thread_struct *next_thread);
+
+#define switch_to(prev,next,last)                               \
+do {                                                            \
+        if (last_task_used_math != next) {                      \
+                struct pt_regs *regs = next->thread.uregs;      \
+                if (regs) regs->sr |= SR_FD;                    \
+        }                                                       \
+        last = sh64_switch_to(prev, &prev->thread, next,        \
+                              &next->thread);                   \
+} while (0)
+
+#define __uses_jump_to_uncached
+
+#define jump_to_uncached()      do { } while (0)
+#define back_to_cached()        do { } while (0)
+
+#endif /* __ASM_SH_SYSTEM_64_H */
diff --git a/arch/sh/include/asm/systemh7751.h b/arch/sh/include/asm/systemh7751.h
new file mode 100644
index 000000000000..4161122c84ef
--- /dev/null
+++ b/arch/sh/include/asm/systemh7751.h
@@ -0,0 +1,71 @@
+#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
+#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
+
+/*
+ * linux/include/asm-sh/systemh/7751systemh.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SystemH support
+
+ * Modified for 7751 SystemH by
+ * Jonathan Short, 2002.
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0x01000000      /* EPROM */
+#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0x12000000
+#define PA_EXT4_SIZE    0x02000000
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0       0xb9000000      /* Dip switch 5,6 */
+#define PA_DIPSW1       0xb9000002      /* Dip switch 7,8 */
+#define PA_LED          0xba000000      /* LED */
+#define PA_BCR          0xbb000000      /* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE     (PA_MRSHPC + 4)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA       (PA_BCR + 0)
+#define BCR_ILCRB       (PA_BCR + 2)
+#define BCR_ILCRC       (PA_BCR + 4)
+#define BCR_ILCRD       (PA_BCR + 6)
+#define BCR_ILCRE       (PA_BCR + 8)
+#define BCR_ILCRF       (PA_BCR + 10)
+#define BCR_ILCRG       (PA_BCR + 12)
+
+#define IRQ_79C973      13
+
+#define __IO_PREFIX     sh7751systemh
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/arch/sh/include/asm/termbits.h b/arch/sh/include/asm/termbits.h
new file mode 100644
index 000000000000..77db116948cf
--- /dev/null
+++ b/arch/sh/include/asm/termbits.h
@@ -0,0 +1,198 @@
+#ifndef __ASM_SH_TERMBITS_H
+#define __ASM_SH_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define    BOTHER 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000          /* input baud rate */
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif /* __ASM_SH_TERMBITS_H */
diff --git a/arch/sh/include/asm/termios.h b/arch/sh/include/asm/termios.h
new file mode 100644
index 000000000000..0a8c793c76f2
--- /dev/null
+++ b/arch/sh/include/asm/termios.h
@@ -0,0 +1,90 @@
+#ifndef __ASM_SH_TERMIOS_H
+#define __ASM_SH_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+#ifdef __KERNEL__
+
+/*      intr=^C         quit=^\         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
+        unsigned short __tmp; \
+        get_user(__tmp,&(termio)->x); \
+        *(unsigned short *) &(termios)->x = __tmp; \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line,  &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif  /* __KERNEL__ */
+
+#endif  /* __ASM_SH_TERMIOS_H */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
new file mode 100644
index 000000000000..0a894cafb1dd
--- /dev/null
+++ b/arch/sh/include/asm/thread_info.h
@@ -0,0 +1,162 @@
+#ifndef __ASM_SH_THREAD_INFO_H
+#define __ASM_SH_THREAD_INFO_H
+
+/* SuperH version
+ * Copyright (C) 2002  Niibe Yutaka
+ *
+ * The copyright of original i386 version is:
+ *
+ *  Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ *  - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+#ifdef __KERNEL__
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        __u32                   cpu;
+        int                     preempt_count; /* 0 => preemptable, <0 => BUG */
+        mm_segment_t            addr_limit;     /* thread address space */
+        struct restart_block    restart_block;
+        unsigned long           previous_sp;    /* sp of previous stack in case
+                                                   of nested IRQ stacks */
+        __u8                    supervisor_stack[0];
+};
+
+#endif
+
+#define PREEMPT_ACTIVE          0x10000000
+
+#if defined(CONFIG_4KSTACKS)
+#define THREAD_SIZE_ORDER       (0)
+#elif defined(CONFIG_PAGE_SIZE_4KB)
+#define THREAD_SIZE_ORDER       (1)
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+#define THREAD_SIZE_ORDER       (1)
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+#define THREAD_SIZE_ORDER       (0)
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+#define THREAD_SIZE_ORDER       (0)
+#else
+#error "Unknown thread size"
+#endif
+
+#define THREAD_SIZE     (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define STACK_WARN      (THREAD_SIZE >> 3)
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ */
+#ifndef __ASSEMBLY__
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = 1,                    \
+        .addr_limit     = KERNEL_DS,            \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* how to get the current stack pointer from C */
+register unsigned long current_stack_pointer asm("r15") __used;
+
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+        struct thread_info *ti;
+#if defined(CONFIG_SUPERH64)
+        __asm__ __volatile__ ("getcon   cr17, %0" : "=r" (ti));
+#elif defined(CONFIG_CPU_HAS_SR_RB)
+        __asm__ __volatile__ ("stc      r7_bank, %0" : "=r" (ti));
+#else
+        unsigned long __dummy;
+
+        __asm__ __volatile__ (
+                "mov    r15, %0\n\t"
+                "and    %1, %0\n\t"
+                : "=&r" (ti), "=r" (__dummy)
+                : "1" (~(THREAD_SIZE - 1))
+                : "memory");
+#endif
+
+        return ti;
+}
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+/* thread information allocation */
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(ti)   kzalloc(THREAD_SIZE, GFP_KERNEL)
+#else
+#define alloc_thread_info(ti)   kmalloc(THREAD_SIZE, GFP_KERNEL)
+#endif
+#define free_thread_info(ti)    kfree(ti)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_SIGPENDING          1       /* signal pending */
+#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
+#define TIF_RESTORE_SIGMASK     3       /* restore signal mask in do_signal() */
+#define TIF_SINGLESTEP          4       /* singlestepping active */
+#define TIF_SYSCALL_AUDIT       5       /* syscall auditing active */
+#define TIF_SECCOMP             6       /* secure computing */
+#define TIF_NOTIFY_RESUME       7       /* callback before returning to user */
+#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE              18
+#define TIF_FREEZE              19      /* Freezing for suspend */
+
+#define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
+#define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
+#define _TIF_SINGLESTEP         (1 << TIF_SINGLESTEP)
+#define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP            (1 << TIF_SECCOMP)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
+#define _TIF_USEDFPU            (1 << TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE             (1 << TIF_FREEZE)
+
+/*
+ * _TIF_ALLWORK_MASK and _TIF_WORK_MASK need to fit within a byte, or we
+ * blow the tst immediate size constraints and need to fix up
+ * arch/sh/kernel/entry-common.S.
+ */
+
+/* work to do in syscall trace */
+#define _TIF_WORK_SYSCALL_MASK  (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
+                                 _TIF_SYSCALL_AUDIT | _TIF_SECCOMP)
+
+/* work to do on any return to u-space */
+#define _TIF_ALLWORK_MASK       (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING      | \
+                                 _TIF_NEED_RESCHED  | _TIF_SYSCALL_AUDIT   | \
+                                 _TIF_SINGLESTEP    | _TIF_RESTORE_SIGMASK | \
+                                 _TIF_NOTIFY_RESUME)
+
+/* work to do on interrupt/exception return */
+#define _TIF_WORK_MASK          (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \
+                                 _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP))
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_THREAD_INFO_H */
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
new file mode 100644
index 000000000000..a7ca3a195bb5
--- /dev/null
+++ b/arch/sh/include/asm/timer.h
@@ -0,0 +1,44 @@
+#ifndef __ASM_SH_TIMER_H
+#define __ASM_SH_TIMER_H
+
+#include <linux/sysdev.h>
+#include <linux/clocksource.h>
+#include <cpu/timer.h>
+
+struct sys_timer_ops {
+        int (*init)(void);
+        int (*start)(void);
+        int (*stop)(void);
+        cycle_t (*read)(void);
+#ifndef CONFIG_GENERIC_TIME
+        unsigned long (*get_offset)(void);
+#endif
+};
+
+struct sys_timer {
+        const char              *name;
+
+        struct sys_device       dev;
+        struct sys_timer_ops    *ops;
+};
+
+#define TICK_SIZE (tick_nsec / 1000)
+
+extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
+extern struct sys_timer *sys_timer;
+
+#ifndef CONFIG_GENERIC_TIME
+static inline unsigned long get_timer_offset(void)
+{
+        return sys_timer->ops->get_offset();
+}
+#endif
+
+/* arch/sh/kernel/timers/timer.c */
+struct sys_timer *get_sys_timer(void);
+
+/* arch/sh/kernel/time.c */
+void handle_timer_tick(void);
+extern unsigned long sh_hpt_frequency;
+
+#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/timex.h b/arch/sh/include/asm/timex.h
new file mode 100644
index 000000000000..a873e24113cf
--- /dev/null
+++ b/arch/sh/include/asm/timex.h
@@ -0,0 +1,18 @@
+/*
+ * linux/include/asm-sh/timex.h
+ *
+ * sh architecture timex specifications
+ */
+#ifndef __ASM_SH_TIMEX_H
+#define __ASM_SH_TIMEX_H
+
+#define CLOCK_TICK_RATE         (CONFIG_SH_PCLK_FREQ / 4) /* Underlying HZ */
+
+typedef unsigned long long cycles_t;
+
+static __inline__ cycles_t get_cycles (void)
+{
+        return 0;
+}
+
+#endif /* __ASM_SH_TIMEX_H */
diff --git a/arch/sh/include/asm/titan.h b/arch/sh/include/asm/titan.h
new file mode 100644
index 000000000000..03f3583c8918
--- /dev/null
+++ b/arch/sh/include/asm/titan.h
@@ -0,0 +1,17 @@
+/*
+ * Platform defintions for Titan
+ */
+#ifndef _ASM_SH_TITAN_H
+#define _ASM_SH_TITAN_H
+
+#define __IO_PREFIX titan
+#include <asm/io_generic.h>
+
+/* IRQ assignments */
+#define TITAN_IRQ_WAN           2       /* eth0 (WAN) */
+#define TITAN_IRQ_LAN           5       /* eth1 (LAN) */
+#define TITAN_IRQ_MPCIA         8       /* mPCI A */
+#define TITAN_IRQ_MPCIB         11      /* mPCI B */
+#define TITAN_IRQ_USB           11      /* USB */
+
+#endif /* __ASM_SH_TITAN_H */
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
new file mode 100644
index 000000000000..88ff1ae8a6b8
--- /dev/null
+++ b/arch/sh/include/asm/tlb.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_TLB_H
+#define __ASM_SH_TLB_H
+
+#ifdef CONFIG_SUPERH64
+# include "tlb_64.h"
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define tlb_start_vma(tlb, vma) \
+        flush_cache_range(vma, vma->vm_start, vma->vm_end)
+
+#define tlb_end_vma(tlb, vma)   \
+        flush_tlb_range(vma, vma->vm_start, vma->vm_end)
+
+#define __tlb_remove_tlb_entry(tlb, pte, address)       do { } while (0)
+
+/*
+ * Flush whole TLBs for MM
+ */
+#define tlb_flush(tlb)                          flush_tlb_mm((tlb)->mm)
+
+#include <linux/pagemap.h>
+#include <asm-generic/tlb.h>
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_TLB_H */
diff --git a/arch/sh/include/asm/tlb_64.h b/arch/sh/include/asm/tlb_64.h
new file mode 100644
index 000000000000..ef0ae2a28f23
--- /dev/null
+++ b/arch/sh/include/asm/tlb_64.h
@@ -0,0 +1,71 @@
+/*
+ * include/asm-sh/tlb_64.h
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_TLB_64_H
+#define __ASM_SH_TLB_64_H
+
+/* ITLB defines */
+#define ITLB_FIXED      0x00000000      /* First fixed ITLB, see head.S */
+#define ITLB_LAST_VAR_UNRESTRICTED      0x000003F0      /* Last ITLB */
+
+/* DTLB defines */
+#define DTLB_FIXED      0x00800000      /* First fixed DTLB, see head.S */
+#define DTLB_LAST_VAR_UNRESTRICTED      0x008003F0      /* Last DTLB */
+
+#ifndef __ASSEMBLY__
+
+/**
+ * for_each_dtlb_entry - Iterate over free (non-wired) DTLB entries
+ *
+ * @tlb:        TLB entry
+ */
+#define for_each_dtlb_entry(tlb)                \
+        for (tlb  = cpu_data->dtlb.first;       \
+             tlb <= cpu_data->dtlb.last;        \
+             tlb += cpu_data->dtlb.step)
+
+/**
+ * for_each_itlb_entry - Iterate over free (non-wired) ITLB entries
+ *
+ * @tlb:        TLB entry
+ */
+#define for_each_itlb_entry(tlb)                \
+        for (tlb  = cpu_data->itlb.first;       \
+             tlb <= cpu_data->itlb.last;        \
+             tlb += cpu_data->itlb.step)
+
+/**
+ * __flush_tlb_slot - Flushes TLB slot @slot.
+ *
+ * @slot:       Address of TLB slot.
+ */
+static inline void __flush_tlb_slot(unsigned long long slot)
+{
+        __asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
+}
+
+#ifdef CONFIG_MMU
+/* arch/sh64/mm/tlb.c */
+int sh64_tlb_init(void);
+unsigned long long sh64_next_free_dtlb_entry(void);
+unsigned long long sh64_get_wired_dtlb_entry(void);
+int sh64_put_wired_dtlb_entry(unsigned long long entry);
+void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
+                         unsigned long asid, unsigned long paddr);
+void sh64_teardown_tlb_slot(unsigned long long config_addr);
+#else
+#define sh64_tlb_init()                                 do { } while (0)
+#define sh64_next_free_dtlb_entry()                     (0)
+#define sh64_get_wired_dtlb_entry()                     (0)
+#define sh64_put_wired_dtlb_entry(entry)                do { } while (0)
+#define sh64_setup_tlb_slot(conf, virt, asid, phys)     do { } while (0)
+#define sh64_teardown_tlb_slot(addr)                    do { } while (0)
+#endif /* CONFIG_MMU */
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_TLB_64_H */
diff --git a/arch/sh/include/asm/tlbflush.h b/arch/sh/include/asm/tlbflush.h
new file mode 100644
index 000000000000..e0ac97221ae6
--- /dev/null
+++ b/arch/sh/include/asm/tlbflush.h
@@ -0,0 +1,49 @@
+#ifndef __ASM_SH_TLBFLUSH_H
+#define __ASM_SH_TLBFLUSH_H
+
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLBs
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ */
+extern void local_flush_tlb_all(void);
+extern void local_flush_tlb_mm(struct mm_struct *mm);
+extern void local_flush_tlb_range(struct vm_area_struct *vma,
+                                  unsigned long start,
+                                  unsigned long end);
+extern void local_flush_tlb_page(struct vm_area_struct *vma,
+                                 unsigned long page);
+extern void local_flush_tlb_kernel_range(unsigned long start,
+                                         unsigned long end);
+extern void local_flush_tlb_one(unsigned long asid, unsigned long page);
+
+#ifdef CONFIG_SMP
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+                            unsigned long end);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_tlb_one(unsigned long asid, unsigned long page);
+
+#else
+
+#define flush_tlb_all()                 local_flush_tlb_all()
+#define flush_tlb_mm(mm)                local_flush_tlb_mm(mm)
+#define flush_tlb_page(vma, page)       local_flush_tlb_page(vma, page)
+#define flush_tlb_one(asid, page)       local_flush_tlb_one(asid, page)
+
+#define flush_tlb_range(vma, start, end)        \
+        local_flush_tlb_range(vma, start, end)
+
+#define flush_tlb_kernel_range(start, end)      \
+        local_flush_tlb_kernel_range(start, end)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_SH_TLBFLUSH_H */
diff --git a/arch/sh/include/asm/topology.h b/arch/sh/include/asm/topology.h
new file mode 100644
index 000000000000..95f0085e098a
--- /dev/null
+++ b/arch/sh/include/asm/topology.h
@@ -0,0 +1,47 @@
+#ifndef _ASM_SH_TOPOLOGY_H
+#define _ASM_SH_TOPOLOGY_H
+
+#ifdef CONFIG_NUMA
+
+/* sched_domains SD_NODE_INIT for sh machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .child                  = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 8,                    \
+        .max_interval           = 32,                   \
+        .busy_factor            = 32,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 2,                    \
+        .newidle_idx            = 2,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_FORK       \
+                                | SD_BALANCE_EXEC       \
+                                | SD_SERIALIZE          \
+                                | SD_WAKE_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+        .nr_balance_failed      = 0,                    \
+}
+
+#define cpu_to_node(cpu)        ((void)(cpu),0)
+#define parent_node(node)       ((void)(node),0)
+
+#define node_to_cpumask(node)   ((void)node, cpu_online_map)
+#define node_to_first_cpu(node) ((void)(node),0)
+
+#define pcibus_to_node(bus)     ((void)(bus), -1)
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
+#endif
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_SH_TOPOLOGY_H */
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
new file mode 100644
index 000000000000..beea4e6f8dfd
--- /dev/null
+++ b/arch/sh/include/asm/types.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_SH_TYPES_H
+#define __ASM_SH_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#ifdef CONFIG_SUPERH32
+typedef u16 opcode_t;
+#else
+typedef u32 opcode_t;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_TYPES_H */
diff --git a/arch/sh/include/asm/uaccess.h b/arch/sh/include/asm/uaccess.h
new file mode 100644
index 000000000000..075848f43b6a
--- /dev/null
+++ b/arch/sh/include/asm/uaccess.h
@@ -0,0 +1,258 @@
+#ifndef __ASM_SH_UACCESS_H
+#define __ASM_SH_UACCESS_H
+
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <asm/segment.h>
+
+#define VERIFY_READ    0
+#define VERIFY_WRITE   1
+
+#define __addr_ok(addr) \
+        ((unsigned long __force)(addr) < current_thread_info()->addr_limit.seg)
+
+/*
+ * __access_ok: Check if address with size is OK or not.
+ *
+ * Uhhuh, this needs 33-bit arithmetic. We have a carry..
+ *
+ * sum := addr + size;  carry? --> flag = true;
+ * if (sum >= addr_limit) flag = true;
+ */
+#define __access_ok(addr, size)         \
+        (__addr_ok((addr) + (size)))
+#define access_ok(type, addr, size)     \
+        (__chk_user_ptr(addr),          \
+         __access_ok((unsigned long __force)(addr), (size)))
+
+/*
+ * Uh, these should become the main single-value transfer routines ...
+ * They automatically use the right size if we just have the right
+ * pointer type ...
+ *
+ * As SuperH uses the same address space for kernel and user data, we
+ * can just do these as direct assignments.
+ *
+ * Careful to not
+ * (a) re-use the arguments for side effects (sizeof is ok)
+ * (b) require any knowledge of processes at this stage
+ */
+#define put_user(x,ptr)         __put_user_check((x), (ptr), sizeof(*(ptr)))
+#define get_user(x,ptr)         __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * The "__xxx" versions do not do address space checking, useful when
+ * doing multiple accesses to the same area (the user has to do the
+ * checks by hand with "access_ok()")
+ */
+#define __put_user(x,ptr)       __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+#define __get_user(x,ptr)       __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct __user *)(x))
+
+#define __get_user_nocheck(x,ptr,size)                          \
+({                                                              \
+        long __gu_err;                                          \
+        unsigned long __gu_val;                                 \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);     \
+        __chk_user_ptr(ptr);                                    \
+        __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+
+#define __get_user_check(x,ptr,size)                                    \
+({                                                                      \
+        long __gu_err = -EFAULT;                                        \
+        unsigned long __gu_val = 0;                                     \
+        const __typeof__(*(ptr)) *__gu_addr = (ptr);                    \
+        if (likely(access_ok(VERIFY_READ, __gu_addr, (size))))          \
+                __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                             \
+        __gu_err;                                                       \
+})
+
+#define __put_user_nocheck(x,ptr,size)                          \
+({                                                              \
+        long __pu_err;                                          \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
+        __typeof__(*(ptr)) __pu_val = x;                        \
+        __chk_user_ptr(ptr);                                    \
+        __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+        __pu_err;                                               \
+})
+
+#define __put_user_check(x,ptr,size)                            \
+({                                                              \
+        long __pu_err = -EFAULT;                                \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
+        __typeof__(*(ptr)) __pu_val = x;                        \
+        if (likely(access_ok(VERIFY_WRITE, __pu_addr, size)))   \
+                __put_user_size(__pu_val, __pu_addr, (size),    \
+                                __pu_err);                      \
+        __pu_err;                                               \
+})
+
+#ifdef CONFIG_SUPERH32
+# include "uaccess_32.h"
+#else
+# include "uaccess_64.h"
+#endif
+
+/* Generic arbitrary sized copy.  */
+/* Return the number of bytes NOT copied */
+__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n);
+
+static __always_inline unsigned long
+__copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        return __copy_user(to, (__force void *)from, n);
+}
+
+static __always_inline unsigned long __must_check
+__copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        return __copy_user((__force void *)to, from, n);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+/*
+ * Clear the area and return remaining number of bytes
+ * (on failure.  Usually it's 0.)
+ */
+__kernel_size_t __clear_user(void *addr, __kernel_size_t size);
+
+#define clear_user(addr,n)                                              \
+({                                                                      \
+        void __user * __cl_addr = (addr);                               \
+        unsigned long __cl_size = (n);                                  \
+                                                                        \
+        if (__cl_size && access_ok(VERIFY_WRITE,                        \
+                ((unsigned long)(__cl_addr)), __cl_size))               \
+                __cl_size = __clear_user(__cl_addr, __cl_size);         \
+                                                                        \
+        __cl_size;                                                      \
+})
+
+/**
+ * strncpy_from_user: - Copy a NUL terminated string from userspace.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+#define strncpy_from_user(dest,src,count)                               \
+({                                                                      \
+        unsigned long __sfu_src = (unsigned long)(src);                 \
+        int __sfu_count = (int)(count);                                 \
+        long __sfu_res = -EFAULT;                                       \
+                                                                        \
+        if (__access_ok(__sfu_src, __sfu_count))                        \
+                __sfu_res = __strncpy_from_user((unsigned long)(dest),  \
+                                __sfu_src, __sfu_count);                \
+                                                                        \
+        __sfu_res;                                                      \
+})
+
+static inline unsigned long
+copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        unsigned long __copy_from = (unsigned long) from;
+        __kernel_size_t __copy_size = (__kernel_size_t) n;
+
+        if (__copy_size && __access_ok(__copy_from, __copy_size))
+                return __copy_user(to, from, __copy_size);
+
+        return __copy_size;
+}
+
+static inline unsigned long
+copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        unsigned long __copy_to = (unsigned long) to;
+        __kernel_size_t __copy_size = (__kernel_size_t) n;
+
+        if (__copy_size && __access_ok(__copy_to, __copy_size))
+                return __copy_user(to, from, __copy_size);
+
+        return __copy_size;
+}
+
+/**
+ * strnlen_user: - Get the size of a string in user space.
+ * @s: The string to measure.
+ * @n: The maximum valid length
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ * If the string is too long, returns a value greater than @n.
+ */
+static inline long strnlen_user(const char __user *s, long n)
+{
+        if (!__addr_ok(s))
+                return 0;
+        else
+                return __strnlen_user(s, n);
+}
+
+/**
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+#define strlen_user(str)        strnlen_user(str, ~0UL >> 1)
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+struct exception_table_entry {
+        unsigned long insn, fixup;
+};
+
+#if defined(CONFIG_SUPERH64) && defined(CONFIG_MMU)
+#define ARCH_HAS_SEARCH_EXTABLE
+#endif
+
+int fixup_exception(struct pt_regs *regs);
+/* Returns 0 if exception not found and fixup.unit otherwise.  */
+unsigned long search_exception_table(unsigned long addr);
+const struct exception_table_entry *search_exception_tables(unsigned long addr);
+
+
+#endif /* __ASM_SH_UACCESS_H */
diff --git a/arch/sh/include/asm/uaccess_32.h b/arch/sh/include/asm/uaccess_32.h
new file mode 100644
index 000000000000..ae0d24f6653f
--- /dev/null
+++ b/arch/sh/include/asm/uaccess_32.h
@@ -0,0 +1,248 @@
+/*
+ * User space memory access functions
+ *
+ * Copyright (C) 1999, 2002  Niibe Yutaka
+ * Copyright (C) 2003 - 2008  Paul Mundt
+ *
+ *  Based on:
+ *     MIPS implementation version 1.15 by
+ *              Copyright (C) 1996, 1997, 1998 by Ralf Baechle
+ *     and i386 version.
+ */
+#ifndef __ASM_SH_UACCESS_32_H
+#define __ASM_SH_UACCESS_32_H
+
+#define __get_user_size(x,ptr,size,retval)                      \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                __get_user_asm(x, ptr, retval, "b");            \
+                break;                                          \
+        case 2:                                                 \
+                __get_user_asm(x, ptr, retval, "w");            \
+                break;                                          \
+        case 4:                                                 \
+                __get_user_asm(x, ptr, retval, "l");            \
+                break;                                          \
+        default:                                                \
+                __get_user_unknown();                           \
+                break;                                          \
+        }                                                       \
+} while (0)
+
+#ifdef CONFIG_MMU
+#define __get_user_asm(x, addr, err, insn) \
+({ \
+__asm__ __volatile__( \
+        "1:\n\t" \
+        "mov." insn "   %2, %1\n\t" \
+        "2:\n" \
+        ".section       .fixup,\"ax\"\n" \
+        "3:\n\t" \
+        "mov    #0, %1\n\t" \
+        "mov.l  4f, %0\n\t" \
+        "jmp    @%0\n\t" \
+        " mov   %3, %0\n\t" \
+        ".balign        4\n" \
+        "4:     .long   2b\n\t" \
+        ".previous\n" \
+        ".section       __ex_table,\"a\"\n\t" \
+        ".long  1b, 3b\n\t" \
+        ".previous" \
+        :"=&r" (err), "=&r" (x) \
+        :"m" (__m(addr)), "i" (-EFAULT), "0" (err)); })
+#else
+#define __get_user_asm(x, addr, err, insn)              \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "mov." insn "   %1, %0\n\t"             \
+                : "=&r" (x)                             \
+                : "m" (__m(addr))                       \
+        );                                              \
+} while (0)
+#endif /* CONFIG_MMU */
+
+extern void __get_user_unknown(void);
+
+#define __put_user_size(x,ptr,size,retval)              \
+do {                                                    \
+        retval = 0;                                     \
+        switch (size) {                                 \
+        case 1:                                         \
+                __put_user_asm(x, ptr, retval, "b");    \
+                break;                                  \
+        case 2:                                         \
+                __put_user_asm(x, ptr, retval, "w");    \
+                break;                                  \
+        case 4:                                         \
+                __put_user_asm(x, ptr, retval, "l");    \
+                break;                                  \
+        case 8:                                         \
+                __put_user_u64(x, ptr, retval);         \
+                break;                                  \
+        default:                                        \
+                __put_user_unknown();                   \
+        }                                               \
+} while (0)
+
+#ifdef CONFIG_MMU
+#define __put_user_asm(x, addr, err, insn)                      \
+do {                                                            \
+        __asm__ __volatile__ (                                  \
+                "1:\n\t"                                        \
+                "mov." insn "   %1, %2\n\t"                     \
+                "2:\n"                                          \
+                ".section       .fixup,\"ax\"\n"                \
+                "3:\n\t"                                        \
+                "mov.l  4f, %0\n\t"                             \
+                "jmp    @%0\n\t"                                \
+                " mov   %3, %0\n\t"                             \
+                ".balign        4\n"                            \
+                "4:     .long   2b\n\t"                         \
+                ".previous\n"                                   \
+                ".section       __ex_table,\"a\"\n\t"           \
+                ".long  1b, 3b\n\t"                             \
+                ".previous"                                     \
+                : "=&r" (err)                                   \
+                : "r" (x), "m" (__m(addr)), "i" (-EFAULT),      \
+                  "0" (err)                                     \
+                : "memory"                                      \
+        );                                                      \
+} while (0)
+#else
+#define __put_user_asm(x, addr, err, insn)              \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "mov." insn "   %0, %1\n\t"             \
+                : /* no outputs */                      \
+                : "r" (x), "m" (__m(addr))              \
+                : "memory"                              \
+        );                                              \
+} while (0)
+#endif /* CONFIG_MMU */
+
+#if defined(CONFIG_CPU_LITTLE_ENDIAN)
+#define __put_user_u64(val,addr,retval) \
+({ \
+__asm__ __volatile__( \
+        "1:\n\t" \
+        "mov.l  %R1,%2\n\t" \
+        "mov.l  %S1,%T2\n\t" \
+        "2:\n" \
+        ".section       .fixup,\"ax\"\n" \
+        "3:\n\t" \
+        "mov.l  4f,%0\n\t" \
+        "jmp    @%0\n\t" \
+        " mov   %3,%0\n\t" \
+        ".balign        4\n" \
+        "4:     .long   2b\n\t" \
+        ".previous\n" \
+        ".section       __ex_table,\"a\"\n\t" \
+        ".long  1b, 3b\n\t" \
+        ".previous" \
+        : "=r" (retval) \
+        : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \
+        : "memory"); })
+#else
+#define __put_user_u64(val,addr,retval) \
+({ \
+__asm__ __volatile__( \
+        "1:\n\t" \
+        "mov.l  %S1,%2\n\t" \
+        "mov.l  %R1,%T2\n\t" \
+        "2:\n" \
+        ".section       .fixup,\"ax\"\n" \
+        "3:\n\t" \
+        "mov.l  4f,%0\n\t" \
+        "jmp    @%0\n\t" \
+        " mov   %3,%0\n\t" \
+        ".balign        4\n" \
+        "4:     .long   2b\n\t" \
+        ".previous\n" \
+        ".section       __ex_table,\"a\"\n\t" \
+        ".long  1b, 3b\n\t" \
+        ".previous" \
+        : "=r" (retval) \
+        : "r" (val), "m" (__m(addr)), "i" (-EFAULT), "0" (retval) \
+        : "memory"); })
+#endif
+
+extern void __put_user_unknown(void);
+
+static inline int
+__strncpy_from_user(unsigned long __dest, unsigned long __user __src, int __count)
+{
+        __kernel_size_t res;
+        unsigned long __dummy, _d, _s, _c;
+
+        __asm__ __volatile__(
+                "9:\n"
+                "mov.b  @%2+, %1\n\t"
+                "cmp/eq #0, %1\n\t"
+                "bt/s   2f\n"
+                "1:\n"
+                "mov.b  %1, @%3\n\t"
+                "dt     %4\n\t"
+                "bf/s   9b\n\t"
+                " add   #1, %3\n\t"
+                "2:\n\t"
+                "sub    %4, %0\n"
+                "3:\n"
+                ".section .fixup,\"ax\"\n"
+                "4:\n\t"
+                "mov.l  5f, %1\n\t"
+                "jmp    @%1\n\t"
+                " mov   %9, %0\n\t"
+                ".balign 4\n"
+                "5:     .long 3b\n"
+                ".previous\n"
+                ".section __ex_table,\"a\"\n"
+                "       .balign 4\n"
+                "       .long 9b,4b\n"
+                ".previous"
+                : "=r" (res), "=&z" (__dummy), "=r" (_s), "=r" (_d), "=r"(_c)
+                : "0" (__count), "2" (__src), "3" (__dest), "4" (__count),
+                  "i" (-EFAULT)
+                : "memory", "t");
+
+        return res;
+}
+
+/*
+ * Return the size of a string (including the ending 0 even when we have
+ * exceeded the maximum string length).
+ */
+static inline long __strnlen_user(const char __user *__s, long __n)
+{
+        unsigned long res;
+        unsigned long __dummy;
+
+        __asm__ __volatile__(
+                "1:\t"
+                "mov.b  @(%0,%3), %1\n\t"
+                "cmp/eq %4, %0\n\t"
+                "bt/s   2f\n\t"
+                " add   #1, %0\n\t"
+                "tst    %1, %1\n\t"
+                "bf     1b\n\t"
+                "2:\n"
+                ".section .fixup,\"ax\"\n"
+                "3:\n\t"
+                "mov.l  4f, %1\n\t"
+                "jmp    @%1\n\t"
+                " mov   #0, %0\n"
+                ".balign 4\n"
+                "4:     .long 2b\n"
+                ".previous\n"
+                ".section __ex_table,\"a\"\n"
+                "       .balign 4\n"
+                "       .long 1b,3b\n"
+                ".previous"
+                : "=z" (res), "=&r" (__dummy)
+                : "0" (0), "r" (__s), "r" (__n)
+                : "t");
+        return res;
+}
+
+#endif /* __ASM_SH_UACCESS_32_H */
diff --git a/arch/sh/include/asm/uaccess_64.h b/arch/sh/include/asm/uaccess_64.h
new file mode 100644
index 000000000000..81b3d515fcb3
--- /dev/null
+++ b/arch/sh/include/asm/uaccess_64.h
@@ -0,0 +1,79 @@
+#ifndef __ASM_SH_UACCESS_64_H
+#define __ASM_SH_UACCESS_64_H
+
+/*
+ * include/asm-sh/uaccess_64.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ * User space memory access functions
+ *
+ * Copyright (C) 1999  Niibe Yutaka
+ *
+ *  Based on:
+ *     MIPS implementation version 1.15 by
+ *              Copyright (C) 1996, 1997, 1998 by Ralf Baechle
+ *     and i386 version.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#define __get_user_size(x,ptr,size,retval)                      \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                retval = __get_user_asm_b(x, ptr);              \
+                break;                                          \
+        case 2:                                                 \
+                retval = __get_user_asm_w(x, ptr);              \
+                break;                                          \
+        case 4:                                                 \
+                retval = __get_user_asm_l(x, ptr);              \
+                break;                                          \
+        case 8:                                                 \
+                retval = __get_user_asm_q(x, ptr);              \
+                break;                                          \
+        default:                                                \
+                __get_user_unknown();                           \
+                break;                                          \
+        }                                                       \
+} while (0)
+
+extern long __get_user_asm_b(void *, long);
+extern long __get_user_asm_w(void *, long);
+extern long __get_user_asm_l(void *, long);
+extern long __get_user_asm_q(void *, long);
+extern void __get_user_unknown(void);
+
+#define __put_user_size(x,ptr,size,retval)                      \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                retval = __put_user_asm_b(x, ptr);              \
+                break;                                          \
+        case 2:                                                 \
+                retval = __put_user_asm_w(x, ptr);              \
+                break;                                          \
+        case 4:                                                 \
+                retval = __put_user_asm_l(x, ptr);              \
+                break;                                          \
+        case 8:                                                 \
+                retval = __put_user_asm_q(x, ptr);              \
+                break;                                          \
+        default:                                                \
+                __put_user_unknown();                           \
+        }                                                       \
+} while (0)
+
+extern long __put_user_asm_b(void *, long);
+extern long __put_user_asm_w(void *, long);
+extern long __put_user_asm_l(void *, long);
+extern long __put_user_asm_q(void *, long);
+extern void __put_user_unknown(void);
+
+#endif /* __ASM_SH_UACCESS_64_H */
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
new file mode 100644
index 000000000000..a7b9028bbfbb
--- /dev/null
+++ b/arch/sh/include/asm/ubc.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-sh/ubc.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_UBC_H
+#define __ASM_SH_UBC_H
+#ifdef __KERNEL__
+
+#include <cpu/ubc.h>
+
+/* User Break Controller */
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
+#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
+#else
+#define UBC_TYPE_SH7729 0
+#endif
+
+#define BAMR_ASID               (1 << 2)
+#define BAMR_NONE               0
+#define BAMR_10                 0x1
+#define BAMR_12                 0x2
+#define BAMR_ALL                0x3
+#define BAMR_16                 0x8
+#define BAMR_20                 0x9
+
+#define BBR_INST                (1 << 4)
+#define BBR_DATA                (2 << 4)
+#define BBR_READ                (1 << 2)
+#define BBR_WRITE               (2 << 2)
+#define BBR_BYTE                0x1
+#define BBR_HALF                0x2
+#define BBR_LONG                0x3
+#define BBR_QUAD                (1 << 6)        /* SH7750 */
+#define BBR_CPU                 (1 << 6)        /* SH7709A,SH7729 */
+#define BBR_DMA                 (2 << 6)        /* SH7709A,SH7729 */
+
+#define BRCR_CMFA               (1 << 15)
+#define BRCR_CMFB               (1 << 14)
+#define BRCR_PCTE               (1 << 11)
+#define BRCR_PCBA               (1 << 10)       /* 1: after execution */
+#define BRCR_DBEB               (1 << 7)
+#define BRCR_PCBB               (1 << 6)
+#define BRCR_SEQ                (1 << 3)
+#define BRCR_UBDE               (1 << 0)
+
+#ifndef __ASSEMBLY__
+/* arch/sh/kernel/cpu/ubc.S */
+extern void ubc_sleep(void);
+
+#ifdef CONFIG_UBC_WAKEUP
+extern void ubc_wakeup(void);
+#else
+#define ubc_wakeup()    do { } while (0)
+#endif
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_UBC_H */
diff --git a/arch/sh/include/asm/ucontext.h b/arch/sh/include/asm/ucontext.h
new file mode 100644
index 000000000000..202ef1d5a3c4
--- /dev/null
+++ b/arch/sh/include/asm/ucontext.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_SH_UCONTEXT_H
+#define __ASM_SH_UCONTEXT_H
+
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        struct sigcontext uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+
+#endif /* __ASM_SH_UCONTEXT_H */
diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h
new file mode 100644
index 000000000000..c1641a01d50f
--- /dev/null
+++ b/arch/sh/include/asm/unaligned.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_SH_UNALIGNED_H
+#define _ASM_SH_UNALIGNED_H
+
+/* SH can't handle unaligned accesses. */
+#ifdef __LITTLE_ENDIAN__
+# include <linux/unaligned/le_struct.h>
+# include <linux/unaligned/be_byteshift.h>
+# include <linux/unaligned/generic.h>
+# define get_unaligned  __get_unaligned_le
+# define put_unaligned  __put_unaligned_le
+#else
+# include <linux/unaligned/be_struct.h>
+# include <linux/unaligned/le_byteshift.h>
+# include <linux/unaligned/generic.h>
+# define get_unaligned  __get_unaligned_be
+# define put_unaligned  __put_unaligned_be
+#endif
+
+#endif /* _ASM_SH_UNALIGNED_H */
diff --git a/arch/sh/include/asm/unistd.h b/arch/sh/include/asm/unistd.h
new file mode 100644
index 000000000000..65be656ead7d
--- /dev/null
+++ b/arch/sh/include/asm/unistd.h
@@ -0,0 +1,13 @@
+#ifdef __KERNEL__
+# ifdef CONFIG_SUPERH32
+#  include "unistd_32.h"
+# else
+#  include "unistd_64.h"
+# endif
+#else
+# ifdef __SH5__
+#  include "unistd_64.h"
+# else
+#  include "unistd_32.h"
+# endif
+#endif
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
new file mode 100644
index 000000000000..d52c000cf924
--- /dev/null
+++ b/arch/sh/include/asm/unistd_32.h
@@ -0,0 +1,384 @@
+#ifndef __ASM_SH_UNISTD_H
+#define __ASM_SH_UNISTD_H
+
+/*
+ * Copyright (C) 1999  Niibe Yutaka
+ */
+
+/*
+ * This file contains the system call numbers.
+ */
+
+#define __NR_restart_syscall      0
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_waitpid              7
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_time                13
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lchown              16
+#define __NR_break               17
+#define __NR_oldstat             18
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_umount              22
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_ptrace              26
+#define __NR_alarm               27
+#define __NR_oldfstat            28
+#define __NR_pause               29
+#define __NR_utime               30
+#define __NR_stty                31
+#define __NR_gtty                32
+#define __NR_access              33
+#define __NR_nice                34
+#define __NR_ftime               35
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_prof                44
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_signal              48
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_umount2             52
+#define __NR_lock                53
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_mpx                 56
+#define __NR_setpgid             57
+#define __NR_ulimit              58
+#define __NR_oldolduname         59
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_sgetmask            68
+#define __NR_ssetmask            69
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrlimit           76     /* Back compatible 2Gig limited rlimit */
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_select              82
+#define __NR_symlink             83
+#define __NR_oldlstat            84
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_readdir             89
+#define __NR_mmap                90
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_profil              98
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_ioperm             101
+#define __NR_socketcall         102
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_olduname           109
+#define __NR_iopl               110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_vm86old            113
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_ipc                117
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_modify_ldt         123
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_sigprocmask        126
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_get_kernel_syms    130
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+#define __NR__newselect         142
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+#define __NR_mlock              150
+#define __NR_munlock            151
+#define __NR_mlockall           152
+#define __NR_munlockall         153
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+#define __NR_mremap             163
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+#define __NR_vm86               166
+#define __NR_query_module       167
+#define __NR_poll               168
+#define __NR_nfsservctl         169
+#define __NR_setresgid          170
+#define __NR_getresgid          171
+#define __NR_prctl              172
+#define __NR_rt_sigreturn       173
+#define __NR_rt_sigaction       174
+#define __NR_rt_sigprocmask     175
+#define __NR_rt_sigpending      176
+#define __NR_rt_sigtimedwait    177
+#define __NR_rt_sigqueueinfo    178
+#define __NR_rt_sigsuspend      179
+#define __NR_pread64            180
+#define __NR_pwrite64           181
+#define __NR_chown              182
+#define __NR_getcwd             183
+#define __NR_capget             184
+#define __NR_capset             185
+#define __NR_sigaltstack        186
+#define __NR_sendfile           187
+#define __NR_streams1           188     /* some people actually want it */
+#define __NR_streams2           189     /* some people actually want it */
+#define __NR_vfork              190
+#define __NR_ugetrlimit         191     /* SuS compliant getrlimit */
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#define __NR_lchown32           198
+#define __NR_getuid32           199
+#define __NR_getgid32           200
+#define __NR_geteuid32          201
+#define __NR_getegid32          202
+#define __NR_setreuid32         203
+#define __NR_setregid32         204
+#define __NR_getgroups32        205
+#define __NR_setgroups32        206
+#define __NR_fchown32           207
+#define __NR_setresuid32        208
+#define __NR_getresuid32        209
+#define __NR_setresgid32        210
+#define __NR_getresgid32        211
+#define __NR_chown32            212
+#define __NR_setuid32           213
+#define __NR_setgid32           214
+#define __NR_setfsuid32         215
+#define __NR_setfsgid32         216
+#define __NR_pivot_root         217
+#define __NR_mincore            218
+#define __NR_madvise            219
+#define __NR_getdents64         220
+#define __NR_fcntl64            221
+/* 223 is unused */
+#define __NR_gettid             224
+#define __NR_readahead          225
+#define __NR_setxattr           226
+#define __NR_lsetxattr          227
+#define __NR_fsetxattr          228
+#define __NR_getxattr           229
+#define __NR_lgetxattr          230
+#define __NR_fgetxattr          231
+#define __NR_listxattr          232
+#define __NR_llistxattr         233
+#define __NR_flistxattr         234
+#define __NR_removexattr        235
+#define __NR_lremovexattr       236
+#define __NR_fremovexattr       237
+#define __NR_tkill              238
+#define __NR_sendfile64         239
+#define __NR_futex              240
+#define __NR_sched_setaffinity  241
+#define __NR_sched_getaffinity  242
+#define __NR_set_thread_area    243
+#define __NR_get_thread_area    244
+#define __NR_io_setup           245
+#define __NR_io_destroy         246
+#define __NR_io_getevents       247
+#define __NR_io_submit          248
+#define __NR_io_cancel          249
+#define __NR_fadvise64          250
+
+#define __NR_exit_group         252
+#define __NR_lookup_dcookie     253
+#define __NR_epoll_create       254
+#define __NR_epoll_ctl          255
+#define __NR_epoll_wait         256
+#define __NR_remap_file_pages   257
+#define __NR_set_tid_address    258
+#define __NR_timer_create       259
+#define __NR_timer_settime      (__NR_timer_create+1)
+#define __NR_timer_gettime      (__NR_timer_create+2)
+#define __NR_timer_getoverrun   (__NR_timer_create+3)
+#define __NR_timer_delete       (__NR_timer_create+4)
+#define __NR_clock_settime      (__NR_timer_create+5)
+#define __NR_clock_gettime      (__NR_timer_create+6)
+#define __NR_clock_getres       (__NR_timer_create+7)
+#define __NR_clock_nanosleep    (__NR_timer_create+8)
+#define __NR_statfs64           268
+#define __NR_fstatfs64          269
+#define __NR_tgkill             270
+#define __NR_utimes             271
+#define __NR_fadvise64_64       272
+#define __NR_vserver            273
+#define __NR_mbind              274
+#define __NR_get_mempolicy      275
+#define __NR_set_mempolicy      276
+#define __NR_mq_open            277
+#define __NR_mq_unlink          (__NR_mq_open+1)
+#define __NR_mq_timedsend       (__NR_mq_open+2)
+#define __NR_mq_timedreceive    (__NR_mq_open+3)
+#define __NR_mq_notify          (__NR_mq_open+4)
+#define __NR_mq_getsetattr      (__NR_mq_open+5)
+#define __NR_kexec_load         283
+#define __NR_waitid             284
+#define __NR_add_key            285
+#define __NR_request_key        286
+#define __NR_keyctl             287
+#define __NR_ioprio_set         288
+#define __NR_ioprio_get         289
+#define __NR_inotify_init       290
+#define __NR_inotify_add_watch  291
+#define __NR_inotify_rm_watch   292
+/* 293 is unused */
+#define __NR_migrate_pages      294
+#define __NR_openat             295
+#define __NR_mkdirat            296
+#define __NR_mknodat            297
+#define __NR_fchownat           298
+#define __NR_futimesat          299
+#define __NR_fstatat64          300
+#define __NR_unlinkat           301
+#define __NR_renameat           302
+#define __NR_linkat             303
+#define __NR_symlinkat          304
+#define __NR_readlinkat         305
+#define __NR_fchmodat           306
+#define __NR_faccessat          307
+#define __NR_pselect6           308
+#define __NR_ppoll              309
+#define __NR_unshare            310
+#define __NR_set_robust_list    311
+#define __NR_get_robust_list    312
+#define __NR_splice             313
+#define __NR_sync_file_range    314
+#define __NR_tee                315
+#define __NR_vmsplice           316
+#define __NR_move_pages         317
+#define __NR_getcpu             318
+#define __NR_epoll_pwait        319
+#define __NR_utimensat          320
+#define __NR_signalfd           321
+#define __NR_timerfd_create     322
+#define __NR_eventfd            323
+#define __NR_fallocate          324
+#define __NR_timerfd_settime    325
+#define __NR_timerfd_gettime    326
+#define __NR_signalfd4          327
+#define __NR_eventfd2           328
+#define __NR_epoll_create1      329
+#define __NR_dup3               330
+#define __NR_pipe2              331
+#define __NR_inotify_init1      332
+
+#define NR_syscalls 333
+
+#ifdef __KERNEL__
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#ifndef cond_syscall
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_UNISTD_H */
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
new file mode 100644
index 000000000000..7c54e91753c1
--- /dev/null
+++ b/arch/sh/include/asm/unistd_64.h
@@ -0,0 +1,423 @@
+#ifndef __ASM_SH_UNISTD_64_H
+#define __ASM_SH_UNISTD_64_H
+
+/*
+ * include/asm-sh/unistd_64.h
+ *
+ * This file contains the system call numbers.
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003 - 2007 Paul Mundt
+ * Copyright (C) 2004  Sean McGoogan
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#define __NR_restart_syscall      0
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_waitpid              7
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_time                13
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lchown              16
+#define __NR_break               17
+#define __NR_oldstat             18
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_umount              22
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_ptrace              26
+#define __NR_alarm               27
+#define __NR_oldfstat            28
+#define __NR_pause               29
+#define __NR_utime               30
+#define __NR_stty                31
+#define __NR_gtty                32
+#define __NR_access              33
+#define __NR_nice                34
+#define __NR_ftime               35
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_prof                44
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_signal              48
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_umount2             52
+#define __NR_lock                53
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_mpx                 56
+#define __NR_setpgid             57
+#define __NR_ulimit              58
+#define __NR_oldolduname         59
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_sgetmask            68
+#define __NR_ssetmask            69
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrlimit           76     /* Back compatible 2Gig limited rlimit */
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_select              82
+#define __NR_symlink             83
+#define __NR_oldlstat            84
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_readdir             89
+#define __NR_mmap                90
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_profil              98
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_ioperm             101
+#define __NR_socketcall         102     /* old implementation of socket systemcall */
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_olduname           109
+#define __NR_iopl               110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_vm86old            113
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_ipc                117
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_modify_ldt         123
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_sigprocmask        126
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_get_kernel_syms    130
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+#define __NR__newselect         142
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+#define __NR_mlock              150
+#define __NR_munlock            151
+#define __NR_mlockall           152
+#define __NR_munlockall         153
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+#define __NR_mremap             163
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+#define __NR_vm86               166
+#define __NR_query_module       167
+#define __NR_poll               168
+#define __NR_nfsservctl         169
+#define __NR_setresgid          170
+#define __NR_getresgid          171
+#define __NR_prctl              172
+#define __NR_rt_sigreturn       173
+#define __NR_rt_sigaction       174
+#define __NR_rt_sigprocmask     175
+#define __NR_rt_sigpending      176
+#define __NR_rt_sigtimedwait    177
+#define __NR_rt_sigqueueinfo    178
+#define __NR_rt_sigsuspend      179
+#define __NR_pread64            180
+#define __NR_pwrite64           181
+#define __NR_chown              182
+#define __NR_getcwd             183
+#define __NR_capget             184
+#define __NR_capset             185
+#define __NR_sigaltstack        186
+#define __NR_sendfile           187
+#define __NR_streams1           188     /* some people actually want it */
+#define __NR_streams2           189     /* some people actually want it */
+#define __NR_vfork              190
+#define __NR_ugetrlimit         191     /* SuS compliant getrlimit */
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#define __NR_lchown32           198
+#define __NR_getuid32           199
+#define __NR_getgid32           200
+#define __NR_geteuid32          201
+#define __NR_getegid32          202
+#define __NR_setreuid32         203
+#define __NR_setregid32         204
+#define __NR_getgroups32        205
+#define __NR_setgroups32        206
+#define __NR_fchown32           207
+#define __NR_setresuid32        208
+#define __NR_getresuid32        209
+#define __NR_setresgid32        210
+#define __NR_getresgid32        211
+#define __NR_chown32            212
+#define __NR_setuid32           213
+#define __NR_setgid32           214
+#define __NR_setfsuid32         215
+#define __NR_setfsgid32         216
+#define __NR_pivot_root         217
+#define __NR_mincore            218
+#define __NR_madvise            219
+
+/* Non-multiplexed socket family */
+#define __NR_socket             220
+#define __NR_bind               221
+#define __NR_connect            222
+#define __NR_listen             223
+#define __NR_accept             224
+#define __NR_getsockname        225
+#define __NR_getpeername        226
+#define __NR_socketpair         227
+#define __NR_send               228
+#define __NR_sendto             229
+#define __NR_recv               230
+#define __NR_recvfrom           231
+#define __NR_shutdown           232
+#define __NR_setsockopt         233
+#define __NR_getsockopt         234
+#define __NR_sendmsg            235
+#define __NR_recvmsg            236
+
+/* Non-multiplexed IPC family */
+#define __NR_semop              237
+#define __NR_semget             238
+#define __NR_semctl             239
+#define __NR_msgsnd             240
+#define __NR_msgrcv             241
+#define __NR_msgget             242
+#define __NR_msgctl             243
+#if 0
+#define __NR_shmatcall          244
+#endif
+#define __NR_shmdt              245
+#define __NR_shmget             246
+#define __NR_shmctl             247
+
+#define __NR_getdents64         248
+#define __NR_fcntl64            249
+/* 223 is unused */
+#define __NR_gettid             252
+#define __NR_readahead          253
+#define __NR_setxattr           254
+#define __NR_lsetxattr          255
+#define __NR_fsetxattr          256
+#define __NR_getxattr           257
+#define __NR_lgetxattr          258
+#define __NR_fgetxattr          269
+#define __NR_listxattr          260
+#define __NR_llistxattr         261
+#define __NR_flistxattr         262
+#define __NR_removexattr        263
+#define __NR_lremovexattr       264
+#define __NR_fremovexattr       265
+#define __NR_tkill              266
+#define __NR_sendfile64         267
+#define __NR_futex              268
+#define __NR_sched_setaffinity  269
+#define __NR_sched_getaffinity  270
+#define __NR_set_thread_area    271
+#define __NR_get_thread_area    272
+#define __NR_io_setup           273
+#define __NR_io_destroy         274
+#define __NR_io_getevents       275
+#define __NR_io_submit          276
+#define __NR_io_cancel          277
+#define __NR_fadvise64          278
+#define __NR_exit_group         280
+
+#define __NR_lookup_dcookie     281
+#define __NR_epoll_create       282
+#define __NR_epoll_ctl          283
+#define __NR_epoll_wait         284
+#define __NR_remap_file_pages   285
+#define __NR_set_tid_address    286
+#define __NR_timer_create       287
+#define __NR_timer_settime      (__NR_timer_create+1)
+#define __NR_timer_gettime      (__NR_timer_create+2)
+#define __NR_timer_getoverrun   (__NR_timer_create+3)
+#define __NR_timer_delete       (__NR_timer_create+4)
+#define __NR_clock_settime      (__NR_timer_create+5)
+#define __NR_clock_gettime      (__NR_timer_create+6)
+#define __NR_clock_getres       (__NR_timer_create+7)
+#define __NR_clock_nanosleep    (__NR_timer_create+8)
+#define __NR_statfs64           296
+#define __NR_fstatfs64          297
+#define __NR_tgkill             298
+#define __NR_utimes             299
+#define __NR_fadvise64_64       300
+#define __NR_vserver            301
+#define __NR_mbind              302
+#define __NR_get_mempolicy      303
+#define __NR_set_mempolicy      304
+#define __NR_mq_open            305
+#define __NR_mq_unlink          (__NR_mq_open+1)
+#define __NR_mq_timedsend       (__NR_mq_open+2)
+#define __NR_mq_timedreceive    (__NR_mq_open+3)
+#define __NR_mq_notify          (__NR_mq_open+4)
+#define __NR_mq_getsetattr      (__NR_mq_open+5)
+#define __NR_kexec_load         311
+#define __NR_waitid             312
+#define __NR_add_key            313
+#define __NR_request_key        314
+#define __NR_keyctl             315
+#define __NR_ioprio_set         316
+#define __NR_ioprio_get         317
+#define __NR_inotify_init       318
+#define __NR_inotify_add_watch  319
+#define __NR_inotify_rm_watch   320
+/* 321 is unused */
+#define __NR_migrate_pages      322
+#define __NR_openat             323
+#define __NR_mkdirat            324
+#define __NR_mknodat            325
+#define __NR_fchownat           326
+#define __NR_futimesat          327
+#define __NR_fstatat64          328
+#define __NR_unlinkat           329
+#define __NR_renameat           330
+#define __NR_linkat             331
+#define __NR_symlinkat          332
+#define __NR_readlinkat         333
+#define __NR_fchmodat           334
+#define __NR_faccessat          335
+#define __NR_pselect6           336
+#define __NR_ppoll              337
+#define __NR_unshare            338
+#define __NR_set_robust_list    339
+#define __NR_get_robust_list    340
+#define __NR_splice             341
+#define __NR_sync_file_range    342
+#define __NR_tee                343
+#define __NR_vmsplice           344
+#define __NR_move_pages         345
+#define __NR_getcpu             346
+#define __NR_epoll_pwait        347
+#define __NR_utimensat          348
+#define __NR_signalfd           349
+#define __NR_timerfd_create     350
+#define __NR_eventfd            351
+#define __NR_fallocate          352
+#define __NR_timerfd_settime    353
+#define __NR_timerfd_gettime    354
+#define __NR_signalfd4          355
+#define __NR_eventfd2           356
+#define __NR_epoll_create1      357
+#define __NR_dup3               358
+#define __NR_pipe2              359
+#define __NR_inotify_init1      360
+
+#ifdef __KERNEL__
+
+#define NR_syscalls 361
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#ifndef cond_syscall
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_UNISTD_64_H */
diff --git a/arch/sh/include/asm/user.h b/arch/sh/include/asm/user.h
new file mode 100644
index 000000000000..8fd3cf6c58d4
--- /dev/null
+++ b/arch/sh/include/asm/user.h
@@ -0,0 +1,67 @@
+#ifndef __ASM_SH_USER_H
+#define __ASM_SH_USER_H
+
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/*
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd).  The file contents are as follows:
+ *
+ *  upage: 1 page consisting of a user struct that tells gdb
+ *      what is present in the file.  Directly after this is a
+ *      copy of the task_struct, which is currently not used by gdb,
+ *      but it may come in handy at some point.  All of the registers
+ *      are stored as part of the upage.  The upage should always be
+ *      only one page long.
+ *  data: The data segment follows next.  We use current->end_text to
+ *      current->brk to pick up all of the user variables, plus any memory
+ *      that may have been sbrk'ed.  No attempt is made to determine if a
+ *      page is demand-zero or if a page is totally unused, we just cover
+ *      the entire range.  All of the addresses are rounded in such a way
+ *      that an integral number of pages is written.
+ *  stack: We need the stack information in order to get a meaningful
+ *      backtrace.  We need to write the data from usp to
+ *      current->start_stack, so we round each of these in order to be able
+ *      to write an integer number of pages.
+ */
+
+#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
+struct user_fpu_struct {
+        unsigned long fp_regs[32];
+        unsigned int fpscr;
+};
+#else
+struct user_fpu_struct {
+        unsigned long fp_regs[16];
+        unsigned long xfp_regs[16];
+        unsigned long fpscr;
+        unsigned long fpul;
+};
+#endif
+
+struct user {
+        struct pt_regs  regs;                   /* entire machine state */
+        struct user_fpu_struct fpu;     /* Math Co-processor registers  */
+        int u_fpvalid;          /* True if math co-processor being used */
+        size_t          u_tsize;                /* text size (pages) */
+        size_t          u_dsize;                /* data size (pages) */
+        size_t          u_ssize;                /* stack size (pages) */
+        unsigned long   start_code;             /* text starting address */
+        unsigned long   start_data;             /* data starting address */
+        unsigned long   start_stack;            /* stack starting address */
+        long int        signal;                 /* signal causing core dump */
+        unsigned long   u_ar0;                  /* help gdb find registers */
+        struct user_fpu_struct* u_fpstate;      /* Math Co-processor pointer */
+        unsigned long   magic;                  /* identifies a core file */
+        char            u_comm[32];             /* user command name */
+};
+
+#define NBPG                    PAGE_SIZE
+#define UPAGES                  1
+#define HOST_TEXT_START_ADDR    (u.start_code)
+#define HOST_DATA_START_ADDR    (u.start_data)
+#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* __ASM_SH_USER_H */
diff --git a/arch/sh/include/asm/vga.h b/arch/sh/include/asm/vga.h
new file mode 100644
index 000000000000..06a5de8ace1a
--- /dev/null
+++ b/arch/sh/include/asm/vga.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_VGA_H
+#define __ASM_SH_VGA_H
+
+/* Stupid drivers. */
+
+#endif /* __ASM_SH_VGA_H */
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h
new file mode 100644
index 000000000000..f024fed00a72
--- /dev/null
+++ b/arch/sh/include/asm/watchdog.h
@@ -0,0 +1,107 @@
+/*
+ * include/asm-sh/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_SH_WATCHDOG_H
+#define __ASM_SH_WATCHDOG_H
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <cpu/watchdog.h>
+#include <asm/io.h>
+
+/* 
+ * See cpu-sh2/watchdog.h for explanation of this stupidity..
+ */
+#ifndef WTCNT_R
+#  define WTCNT_R       WTCNT
+#endif
+
+#ifndef WTCSR_R
+#  define WTCSR_R       WTCSR
+#endif
+
+#define WTCNT_HIGH      0x5a
+#define WTCSR_HIGH      0xa5
+
+#define WTCSR_CKS2      0x04
+#define WTCSR_CKS1      0x02
+#define WTCSR_CKS0      0x01
+
+/*
+ * CKS0-2 supports a number of clock division ratios. At the time the watchdog
+ * is enabled, it defaults to a 41 usec overflow period .. we overload this to
+ * something a little more reasonable, and really can't deal with anything
+ * lower than WTCSR_CKS_1024, else we drop back into the usec range.
+ *
+ * Clock Division Ratio         Overflow Period
+ * --------------------------------------------
+ *     1/32 (initial value)       41 usecs
+ *     1/64                       82 usecs
+ *     1/128                     164 usecs
+ *     1/256                     328 usecs
+ *     1/512                     656 usecs
+ *     1/1024                   1.31 msecs
+ *     1/2048                   2.62 msecs
+ *     1/4096                   5.25 msecs
+ */
+#define WTCSR_CKS_32    0x00
+#define WTCSR_CKS_64    0x01
+#define WTCSR_CKS_128   0x02
+#define WTCSR_CKS_256   0x03
+#define WTCSR_CKS_512   0x04
+#define WTCSR_CKS_1024  0x05
+#define WTCSR_CKS_2048  0x06
+#define WTCSR_CKS_4096  0x07
+
+/**
+ *      sh_wdt_read_cnt - Read from Counter
+ *      Reads back the WTCNT value.
+ */
+static inline __u8 sh_wdt_read_cnt(void)
+{
+        return ctrl_inb(WTCNT_R);
+}
+
+/**
+ *      sh_wdt_write_cnt - Write to Counter
+ *      @val: Value to write
+ *
+ *      Writes the given value @val to the lower byte of the timer counter.
+ *      The upper byte is set manually on each write.
+ */
+static inline void sh_wdt_write_cnt(__u8 val)
+{
+        ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
+}
+
+/**
+ *      sh_wdt_read_csr - Read from Control/Status Register
+ *
+ *      Reads back the WTCSR value.
+ */
+static inline __u8 sh_wdt_read_csr(void)
+{
+        return ctrl_inb(WTCSR_R);
+}
+
+/**
+ *      sh_wdt_write_csr - Write to Control/Status Register
+ *      @val: Value to write
+ *
+ *      Writes the given value @val to the lower byte of the control/status
+ *      register. The upper byte is set manually on each write.
+ */
+static inline void sh_wdt_write_csr(__u8 val)
+{
+        ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_WATCHDOG_H */
diff --git a/arch/sh/include/asm/xor.h b/arch/sh/include/asm/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/arch/sh/include/asm/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/arch/sh/include/cpu-common/cpu/addrspace.h b/arch/sh/include/cpu-common/cpu/addrspace.h
new file mode 100644
index 000000000000..2b9ab93efa4e
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/addrspace.h
@@ -0,0 +1,19 @@
+/*
+ * Definitions for the address spaces of the SH-2 CPUs.
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_ADDRSPACE_H
+#define __ASM_CPU_SH2_ADDRSPACE_H
+
+#define P0SEG           0x00000000
+#define P1SEG           0x80000000
+#define P2SEG           0xa0000000
+#define P3SEG           0xc0000000
+#define P4SEG           0xe0000000
+
+#endif /* __ASM_CPU_SH2_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-common/cpu/cacheflush.h b/arch/sh/include/cpu-common/cpu/cacheflush.h
new file mode 100644
index 000000000000..c3db00b73605
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/cacheflush.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/cpu-sh2/cacheflush.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
+#define __ASM_CPU_SH2_CACHEFLUSH_H
+
+/*
+ * Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_dup mm(mm) handles cache flushing when forking
+ *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
+ *  - flush_cache_range(vma, start, end) flushes a range of pages
+ *
+ *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
+ *  - flush_icache_range(start, end) flushes(invalidates) a range for icache
+ *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
+ *
+ *  Caches are indexed (effectively) by physical address on SH-2, so
+ *  we don't need them.
+ */
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_dcache_page(page)                 do { } while (0)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+#define flush_icache_range(start, end)          do { } while (0)
+#define flush_icache_page(vma,pg)               do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_sigtramp(vaddr)             do { } while (0)
+
+#define p3_cache_init()                         do { } while (0)
+
+#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-common/cpu/mmu_context.h b/arch/sh/include/cpu-common/cpu/mmu_context.h
new file mode 100644
index 000000000000..beeb299e01ec
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/mmu_context.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-sh/cpu-sh2/mmu_context.h
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
+#define __ASM_CPU_SH2_MMU_CONTEXT_H
+
+/* No MMU */
+
+#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
+
diff --git a/arch/sh/include/cpu-common/cpu/rtc.h b/arch/sh/include/cpu-common/cpu/rtc.h
new file mode 100644
index 000000000000..39e2d6e94782
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH2_RTC_H
+#define __ASM_SH_CPU_SH2_RTC_H
+
+#define rtc_reg_size            sizeof(u16)
+#define RTC_BIT_INVERTED        0
+#define RTC_DEF_CAPABILITIES    0UL
+
+#endif /* __ASM_SH_CPU_SH2_RTC_H */
diff --git a/arch/sh/include/cpu-common/cpu/sigcontext.h b/arch/sh/include/cpu-common/cpu/sigcontext.h
new file mode 100644
index 000000000000..fe5c15dd6e87
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/sigcontext.h
@@ -0,0 +1,17 @@
+#ifndef __ASM_CPU_SH2_SIGCONTEXT_H
+#define __ASM_CPU_SH2_SIGCONTEXT_H
+
+struct sigcontext {
+        unsigned long   oldmask;
+
+        /* CPU registers */
+        unsigned long sc_regs[16];
+        unsigned long sc_pc;
+        unsigned long sc_pr;
+        unsigned long sc_sr;
+        unsigned long sc_gbr;
+        unsigned long sc_mach;
+        unsigned long sc_macl;
+};
+
+#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */
diff --git a/arch/sh/include/cpu-common/cpu/timer.h b/arch/sh/include/cpu-common/cpu/timer.h
new file mode 100644
index 000000000000..a39c241e8195
--- /dev/null
+++ b/arch/sh/include/cpu-common/cpu/timer.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_CPU_SH2_TIMER_H
+#define __ASM_CPU_SH2_TIMER_H
+
+/* Nothing needed yet */
+
+#endif /* __ASM_CPU_SH2_TIMER_H */
diff --git a/arch/sh/include/cpu-sh2/cpu/cache.h b/arch/sh/include/cpu-sh2/cpu/cache.h
new file mode 100644
index 000000000000..673515bc4135
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/cache.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-sh/cpu-sh2/cache.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_CACHE_H
+#define __ASM_CPU_SH2_CACHE_H
+
+#define L1_CACHE_SHIFT  4
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define CCR             0xffffffec
+
+#define CCR_CACHE_CE    0x01    /* Cache enable */
+#define CCR_CACHE_WT    0x02    /* CCR[bit1=1,bit2=1] */
+                                /* 0x00000000-0x7fffffff: Write-through  */
+                                /* 0x80000000-0x9fffffff: Write-back     */
+                                /* 0xc0000000-0xdfffffff: Write-through  */
+#define CCR_CACHE_CB    0x04    /* CCR[bit1=0,bit2=0] */
+                                /* 0x00000000-0x7fffffff: Write-back     */
+                                /* 0x80000000-0x9fffffff: Write-through  */
+                                /* 0xc0000000-0xdfffffff: Write-back     */
+#define CCR_CACHE_CF    0x08    /* Cache invalidate */
+
+#define CACHE_OC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_DATA_ARRAY     0xf1000000
+
+#define CCR_CACHE_ENABLE        CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
+#define CACHE_PHYSADDR_MASK     0x1ffffc00
+
+#endif
+
+#endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/arch/sh/include/cpu-sh2/cpu/dma.h b/arch/sh/include/cpu-sh2/cpu/dma.h
new file mode 100644
index 000000000000..d66b43cdc637
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/dma.h
@@ -0,0 +1,23 @@
+/*
+ * Definitions for the SH-2 DMAC.
+ *
+ * Copyright (C) 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_DMA_H
+#define __ASM_CPU_SH2_DMA_H
+
+#define SH_MAX_DMA_CHANNELS     2
+
+#define SAR     ((unsigned long[]){ 0xffffff80, 0xffffff90 })
+#define DAR     ((unsigned long[]){ 0xffffff84, 0xffffff94 })
+#define DMATCR  ((unsigned long[]){ 0xffffff88, 0xffffff98 })
+#define CHCR    ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
+
+#define DMAOR   0xffffffb0
+
+#endif /* __ASM_CPU_SH2_DMA_H */
+
diff --git a/arch/sh/include/cpu-sh2/cpu/freq.h b/arch/sh/include/cpu-sh2/cpu/freq.h
new file mode 100644
index 000000000000..31de475da70b
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_FREQ_H
+#define __ASM_CPU_SH2_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define FREQCR  0xf815ff80
+#endif
+
+#endif /* __ASM_CPU_SH2_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh2/cpu/ubc.h b/arch/sh/include/cpu-sh2/cpu/ubc.h
new file mode 100644
index 000000000000..ba0e87f19c7a
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/ubc.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-sh/cpu-sh2/ubc.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_UBC_H
+#define __ASM_CPU_SH2_UBC_H
+
+#define UBC_BARA                0xffffff40
+#define UBC_BAMRA               0xffffff44
+#define UBC_BBRA                0xffffff48
+#define UBC_BARB                0xffffff60
+#define UBC_BAMRB               0xffffff64
+#define UBC_BBRB                0xffffff68
+#define UBC_BDRB                0xffffff70
+#define UBC_BDMRB               0xffffff74
+#define UBC_BRCR                0xffffff78
+
+/*
+ * We don't have any ASID changes to make in the UBC on the SH-2.
+ *
+ * Make these purposely invalid to track misuse.
+ */
+#define UBC_BASRA               0x00000000
+#define UBC_BASRB               0x00000000
+
+#endif /* __ASM_CPU_SH2_UBC_H */
+
diff --git a/arch/sh/include/cpu-sh2/cpu/watchdog.h b/arch/sh/include/cpu-sh2/cpu/watchdog.h
new file mode 100644
index 000000000000..393161c9c6d0
--- /dev/null
+++ b/arch/sh/include/cpu-sh2/cpu/watchdog.h
@@ -0,0 +1,69 @@
+/*
+ * include/asm-sh/cpu-sh2/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_WATCHDOG_H
+#define __ASM_CPU_SH2_WATCHDOG_H
+
+/*
+ * More SH-2 brilliance .. its not good enough that we can't read
+ * and write the same sizes to WTCNT, now we have to read and write
+ * with different sizes at different addresses for WTCNT _and_ RSTCSR.
+ *
+ * At least on the bright side no one has managed to screw over WTCSR
+ * in this fashion .. yet.
+ */
+/* Register definitions */
+#define WTCNT           0xfffffe80
+#define WTCSR           0xfffffe80
+#define RSTCSR          0xfffffe82
+
+#define WTCNT_R         (WTCNT + 1)
+#define RSTCSR_R        (RSTCSR + 1)
+
+/* Bit definitions */
+#define WTCSR_IOVF      0x80
+#define WTCSR_WT        0x40
+#define WTCSR_TME       0x20
+#define WTCSR_RSTS      0x00
+
+#define RSTCSR_RSTS     0x20
+
+/**
+ *      sh_wdt_read_rstcsr - Read from Reset Control/Status Register
+ *
+ *      Reads back the RSTCSR value.
+ */
+static inline __u8 sh_wdt_read_rstcsr(void)
+{
+        /*
+         * Same read/write brain-damage as for WTCNT here..
+         */
+        return ctrl_inb(RSTCSR_R);
+}
+
+/**
+ *      sh_wdt_write_csr - Write to Reset Control/Status Register
+ *
+ *      @val: Value to write
+ *
+ *      Writes the given value @val to the lower byte of the control/status
+ *      register. The upper byte is set manually on each write.
+ */
+static inline void sh_wdt_write_rstcsr(__u8 val)
+{
+        /*
+         * Note: Due to the brain-damaged nature of this register,
+         * we can't presently touch the WOVF bit, since the upper byte
+         * has to be swapped for this. So just leave it alone..
+         */
+        ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
+}
+
+#endif /* __ASM_CPU_SH2_WATCHDOG_H */
+
diff --git a/arch/sh/include/cpu-sh2a/cpu/addrspace.h b/arch/sh/include/cpu-sh2a/cpu/addrspace.h
new file mode 100644
index 000000000000..31eb4b58aa6d
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/addrspace.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_SH_CPU_SH2A_ADDRSPACE_H
+#define __ASM_SH_CPU_SH2A_ADDRSPACE_H
+
+#define P0SEG           0x00000000
+#define P1SEG           0x00000000
+#define P2SEG           0x20000000
+#define P3SEG           0x40000000
+#define P4SEG           0x60000000
+
+#endif /* __ASM_SH_CPU_SH2A_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/cache.h b/arch/sh/include/cpu-sh2a/cpu/cache.h
new file mode 100644
index 000000000000..defb0baa5a06
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/cache.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-sh/cpu-sh2a/cache.h
+ *
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_CACHE_H
+#define __ASM_CPU_SH2A_CACHE_H
+
+#define L1_CACHE_SHIFT  4
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#define CCR             0xfffc1000 /* CCR1 */
+#define CCR2            0xfffc1004
+
+/*
+ * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
+ * listed here are reserved.
+ */
+#define CCR_CACHE_CB    0x0000  /* Hack */
+#define CCR_CACHE_OCE   0x0001
+#define CCR_CACHE_WT    0x0002
+#define CCR_CACHE_OCI   0x0008  /* OCF */
+#define CCR_CACHE_ICE   0x0100
+#define CCR_CACHE_ICI   0x0800  /* ICF */
+
+#define CACHE_IC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY  0xf0800000
+
+#define CCR_CACHE_ENABLE        (CCR_CACHE_OCE | CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI | CCR_CACHE_ICI)
+#define CCR_ICACHE_INVALIDATE   CCR_CACHE_ICI
+#define CCR_OCACHE_INVALIDATE   CCR_CACHE_OCI
+#define CACHE_PHYSADDR_MASK     0x1ffffc00
+
+#endif /* __ASM_CPU_SH2A_CACHE_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
new file mode 100644
index 000000000000..3d3b9205d2ac
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_CPU_SH2A_CACHEFLUSH_H
+#define __ASM_CPU_SH2A_CACHEFLUSH_H
+
+/* 
+ * Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_dup mm(mm) handles cache flushing when forking
+ *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
+ *  - flush_cache_range(vma, start, end) flushes a range of pages
+ *
+ *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
+ *  - flush_icache_range(start, end) flushes(invalidates) a range for icache
+ *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
+ *
+ *  Caches are indexed (effectively) by physical address on SH-2, so
+ *  we don't need them.
+ */
+#define flush_cache_all()                       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_dup_mm(mm)                  do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
+#define flush_dcache_page(page)                 do { } while (0)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+void flush_icache_range(unsigned long start, unsigned long end);
+#define flush_icache_page(vma,pg)               do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_sigtramp(vaddr)             do { } while (0)
+
+#define p3_cache_init()                         do { } while (0)
+#endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/dma.h b/arch/sh/include/cpu-sh2a/cpu/dma.h
new file mode 100644
index 000000000000..27a13ef4fdfc
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/dma.h
@@ -0,0 +1 @@
+#include <cpu-sh2/cpu/dma.h>
diff --git a/arch/sh/include/cpu-sh2a/cpu/freq.h b/arch/sh/include/cpu-sh2a/cpu/freq.h
new file mode 100644
index 000000000000..830fd43b6cdc
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/freq.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-sh/cpu-sh2a/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_FREQ_H
+#define __ASM_CPU_SH2A_FREQ_H
+
+#define FREQCR  0xfffe0010
+
+#endif /* __ASM_CPU_SH2A_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh2a/cpu/rtc.h b/arch/sh/include/cpu-sh2a/cpu/rtc.h
new file mode 100644
index 000000000000..afb511e2bed7
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH2A_RTC_H
+#define __ASM_SH_CPU_SH2A_RTC_H
+
+#define rtc_reg_size            sizeof(u16)
+#define RTC_BIT_INVERTED        0
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH2A_RTC_H */
diff --git a/arch/sh/include/cpu-sh2a/cpu/ubc.h b/arch/sh/include/cpu-sh2a/cpu/ubc.h
new file mode 100644
index 000000000000..8ce2fc1cf625
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/ubc.h
@@ -0,0 +1 @@
+#include <cpu-sh2/cpu/ubc.h>
diff --git a/arch/sh/include/cpu-sh2a/cpu/watchdog.h b/arch/sh/include/cpu-sh2a/cpu/watchdog.h
new file mode 100644
index 000000000000..e7e8259e468c
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/watchdog.h
@@ -0,0 +1 @@
+#include <cpu-sh2/cpu/watchdog.h>
diff --git a/arch/sh/include/cpu-sh3/cpu/adc.h b/arch/sh/include/cpu-sh3/cpu/adc.h
new file mode 100644
index 000000000000..b289e3ca19a6
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/adc.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_CPU_SH3_ADC_H
+#define __ASM_CPU_SH3_ADC_H
+
+/*
+ * Copyright (C) 2004  Andriy Skulysh
+ */
+
+
+#define ADDRAH  0xa4000080
+#define ADDRAL  0xa4000082
+#define ADDRBH  0xa4000084
+#define ADDRBL  0xa4000086
+#define ADDRCH  0xa4000088
+#define ADDRCL  0xa400008a
+#define ADDRDH  0xa400008c
+#define ADDRDL  0xa400008e
+#define ADCSR   0xa4000090
+
+#define ADCSR_ADF       0x80
+#define ADCSR_ADIE      0x40
+#define ADCSR_ADST      0x20
+#define ADCSR_MULTI     0x10
+#define ADCSR_CKS       0x08
+#define ADCSR_CH_MASK   0x07
+
+#define ADCR    0xa4000092
+
+#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/cache.h b/arch/sh/include/cpu-sh3/cpu/cache.h
new file mode 100644
index 000000000000..bee2d81c56bf
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/cache.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-sh/cpu-sh3/cache.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_CACHE_H
+#define __ASM_CPU_SH3_CACHE_H
+
+#define L1_CACHE_SHIFT  4
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#define CCR             0xffffffec      /* Address of Cache Control Register */
+
+#define CCR_CACHE_CE    0x01    /* Cache Enable */
+#define CCR_CACHE_WT    0x02    /* Write-Through (for P0,U0,P3) (else writeback) */
+#define CCR_CACHE_CB    0x04    /* Write-Back (for P1) (else writethrough) */
+#define CCR_CACHE_CF    0x08    /* Cache Flush */
+#define CCR_CACHE_ORA   0x20    /* RAM mode */
+
+#define CACHE_OC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_PHYSADDR_MASK     0x1ffffc00
+
+#define CCR_CACHE_ENABLE        CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE    CCR_CACHE_CF
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define CCR3_REG        0xa40000b4
+#define CCR_CACHE_16KB  0x00010000
+#define CCR_CACHE_32KB  0x00020000
+#endif
+
+#endif /* __ASM_CPU_SH3_CACHE_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/cacheflush.h b/arch/sh/include/cpu-sh3/cpu/cacheflush.h
new file mode 100644
index 000000000000..abc909880807
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/cacheflush.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-sh/cpu-sh3/cacheflush.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
+#define __ASM_CPU_SH3_CACHEFLUSH_H
+
+#if defined(CONFIG_SH7705_CACHE_32KB)
+/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
+ * SH4. Unlike the SH4 this is a unified cache so we need to do some work
+ * in mmap when 'exec'ing a new binary
+ */
+ /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
+#define CACHE_ALIAS 0x00001000
+
+#define PG_mapped       PG_arch_1
+
+void flush_cache_all(void);
+void flush_cache_mm(struct mm_struct *mm);
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                              unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
+void flush_dcache_page(struct page *pg);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#else
+#include <cpu-common/cpu/cacheflush.h>
+#endif
+
+#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dac.h b/arch/sh/include/cpu-sh3/cpu/dac.h
new file mode 100644
index 000000000000..05fda8316ebc
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dac.h
@@ -0,0 +1,41 @@
+#ifndef __ASM_CPU_SH3_DAC_H
+#define __ASM_CPU_SH3_DAC_H
+
+/*
+ * Copyright (C) 2003  Andriy Skulysh
+ */
+
+
+#define DADR0   0xa40000a0
+#define DADR1   0xa40000a2
+#define DACR    0xa40000a4
+#define DACR_DAOE1      0x80
+#define DACR_DAOE0      0x40
+#define DACR_DAE        0x20
+
+
+static __inline__ void sh_dac_enable(int channel)
+{
+        unsigned char v;
+        v = ctrl_inb(DACR);
+        if(channel) v |= DACR_DAOE1;
+        else v |= DACR_DAOE0;
+        ctrl_outb(v,DACR);
+}
+
+static __inline__ void sh_dac_disable(int channel)
+{
+        unsigned char v;
+        v = ctrl_inb(DACR);
+        if(channel) v &= ~DACR_DAOE1;
+        else v &= ~DACR_DAOE0;
+        ctrl_outb(v,DACR);
+}
+
+static __inline__ void sh_dac_output(u8 value, int channel)
+{
+        if(channel) ctrl_outb(value,DADR1);
+        else ctrl_outb(value,DADR0);
+}
+
+#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
new file mode 100644
index 000000000000..6813c3220a1d
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -0,0 +1,51 @@
+#ifndef __ASM_CPU_SH3_DMA_H
+#define __ASM_CPU_SH3_DMA_H
+
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define SH_DMAC_BASE    0xa4010020
+#else
+#define SH_DMAC_BASE    0xa4000020
+#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
+#define DMTE0_IRQ       48
+#define DMTE1_IRQ       49
+#define DMTE2_IRQ       50
+#define DMTE3_IRQ       51
+#define DMTE4_IRQ       76
+#define DMTE5_IRQ       77
+#endif
+
+/* Definitions for the SuperH DMAC */
+#define TM_BURST        0x00000020
+#define TS_8            0x00000000
+#define TS_16           0x00000008
+#define TS_32           0x00000010
+#define TS_128          0x00000018
+
+#define CHCR_TS_MASK    0x18
+#define CHCR_TS_SHIFT   3
+
+#define DMAOR_INIT      DMAOR_DME
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ */
+enum {
+        XMIT_SZ_8BIT,
+        XMIT_SZ_16BIT,
+        XMIT_SZ_32BIT,
+        XMIT_SZ_128BIT,
+};
+
+static unsigned int ts_shift[] __maybe_unused = {
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_128BIT]        = 4,
+};
+
+#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/freq.h b/arch/sh/include/cpu-sh3/cpu/freq.h
new file mode 100644
index 000000000000..53c62302b2e3
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/freq.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-sh/cpu-sh3/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_FREQ_H
+#define __ASM_CPU_SH3_FREQ_H
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7712
+#define FRQCR                   0xA415FF80
+#else
+#define FRQCR                   0xffffff80
+#endif
+
+#define MIN_DIVISOR_NR          0
+#define MAX_DIVISOR_NR          4
+
+#define FRQCR_CKOEN     0x0100
+#define FRQCR_PLLEN     0x0080
+#define FRQCR_PSTBY     0x0040
+
+#endif /* __ASM_CPU_SH3_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/gpio.h b/arch/sh/include/cpu-sh3/cpu/gpio.h
new file mode 100644
index 000000000000..4e53eb314b8f
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/gpio.h
@@ -0,0 +1,67 @@
+/*
+ *  include/asm-sh/cpu-sh3/gpio.h
+ *
+ *  Copyright (C) 2007  Markus Brunner, Mark Jonas
+ *
+ *  Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _CPU_SH3_GPIO_H
+#define _CPU_SH3_GPIO_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+
+/* Control registers */
+#define PORT_PACR       0xA4050100UL
+#define PORT_PBCR       0xA4050102UL
+#define PORT_PCCR       0xA4050104UL
+#define PORT_PDCR       0xA4050106UL
+#define PORT_PECR       0xA4050108UL
+#define PORT_PFCR       0xA405010AUL
+#define PORT_PGCR       0xA405010CUL
+#define PORT_PHCR       0xA405010EUL
+#define PORT_PJCR       0xA4050110UL
+#define PORT_PKCR       0xA4050112UL
+#define PORT_PLCR       0xA4050114UL
+#define PORT_PMCR       0xA4050116UL
+#define PORT_PPCR       0xA4050118UL
+#define PORT_PRCR       0xA405011AUL
+#define PORT_PSCR       0xA405011CUL
+#define PORT_PTCR       0xA405011EUL
+#define PORT_PUCR       0xA4050120UL
+#define PORT_PVCR       0xA4050122UL
+
+/* Data registers */
+#define PORT_PADR       0xA4050140UL
+/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
+#define PORT_PBDR       0xA4050142UL
+#define PORT_PCDR       0xA4050144UL
+#define PORT_PDDR       0xA4050146UL
+#define PORT_PEDR       0xA4050148UL
+#define PORT_PFDR       0xA405014AUL
+#define PORT_PGDR       0xA405014CUL
+#define PORT_PHDR       0xA405014EUL
+#define PORT_PJDR       0xA4050150UL
+#define PORT_PKDR       0xA4050152UL
+#define PORT_PLDR       0xA4050154UL
+#define PORT_PMDR       0xA4050156UL
+#define PORT_PPDR       0xA4050158UL
+#define PORT_PRDR       0xA405015AUL
+#define PORT_PSDR       0xA405015CUL
+#define PORT_PTDR       0xA405015EUL
+#define PORT_PUDR       0xA4050160UL
+#define PORT_PVDR       0xA4050162UL
+
+/* Pin Select Registers */
+#define PORT_PSELA      0xA4050124UL
+#define PORT_PSELB      0xA4050126UL
+#define PORT_PSELC      0xA4050128UL
+#define PORT_PSELD      0xA405012AUL
+
+#endif
+
+#endif
diff --git a/arch/sh/include/cpu-sh3/cpu/mmu_context.h b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
new file mode 100644
index 000000000000..ab09da73ce77
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/cpu-sh3/mmu_context.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
+#define __ASM_CPU_SH3_MMU_CONTEXT_H
+
+#define MMU_PTEH        0xFFFFFFF0      /* Page table entry register HIGH */
+#define MMU_PTEL        0xFFFFFFF4      /* Page table entry register LOW */
+#define MMU_TTB         0xFFFFFFF8      /* Translation table base register */
+#define MMU_TEA         0xFFFFFFFC      /* TLB Exception Address */
+
+#define MMUCR           0xFFFFFFE0      /* MMU Control Register */
+
+#define MMU_TLB_ADDRESS_ARRAY   0xF2000000
+#define MMU_PAGE_ASSOC_BIT      0x80
+
+#define MMU_NTLB_ENTRIES        128     /* for 7708 */
+#define MMU_NTLB_WAYS           4
+#define MMU_CONTROL_INIT        0x007   /* SV=0, TF=1, IX=1, AT=1 */
+
+#define TRA     0xffffffd0
+#define EXPEVT  0xffffffd4
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7712) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define INTEVT  0xa4000000      /* INTEVTE2(0xa4000000) */
+#else
+#define INTEVT  0xffffffd8
+#endif
+
+#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/timer.h b/arch/sh/include/cpu-sh3/cpu/timer.h
new file mode 100644
index 000000000000..793acf12aa08
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/timer.h
@@ -0,0 +1,67 @@
+/*
+ * include/asm-sh/cpu-sh3/timer.h
+ *
+ * Copyright (C) 2004 Lineo Solutions, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_TIMER_H
+#define __ASM_CPU_SH3_TIMER_H
+
+/*
+ * ---------------------------------------------------------------------------
+ * TMU Common definitions for SH3 processors
+ *      SH7706
+ *      SH7709S
+ *      SH7727
+ *      SH7729R
+ *      SH7710
+ *      SH7720
+ *      SH7710
+ * ---------------------------------------------------------------------------
+ */
+
+#if  !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define TMU_TOCR        0xfffffe90      /* Byte access */
+#endif
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define TMU_012_TSTR    0xa412fe92      /* Byte access */
+
+#define TMU0_TCOR       0xa412fe94      /* Long access */
+#define TMU0_TCNT       0xa412fe98      /* Long access */
+#define TMU0_TCR        0xa412fe9c      /* Word access */
+
+#define TMU1_TCOR       0xa412fea0      /* Long access */
+#define TMU1_TCNT       0xa412fea4      /* Long access */
+#define TMU1_TCR        0xa412fea8      /* Word access */
+
+#define TMU2_TCOR       0xa412feac      /* Long access */
+#define TMU2_TCNT       0xa412feb0      /* Long access */
+#define TMU2_TCR        0xa412feb4      /* Word access */
+
+#else
+#define TMU_012_TSTR    0xfffffe92      /* Byte access */
+
+#define TMU0_TCOR       0xfffffe94      /* Long access */
+#define TMU0_TCNT       0xfffffe98      /* Long access */
+#define TMU0_TCR        0xfffffe9c      /* Word access */
+
+#define TMU1_TCOR       0xfffffea0      /* Long access */
+#define TMU1_TCNT       0xfffffea4      /* Long access */
+#define TMU1_TCR        0xfffffea8      /* Word access */
+
+#define TMU2_TCOR       0xfffffeac      /* Long access */
+#define TMU2_TCNT       0xfffffeb0      /* Long access */
+#define TMU2_TCR        0xfffffeb4      /* Word access */
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define TMU2_TCPR2      0xfffffeb8      /* Long access */
+#endif
+#endif
+
+#endif /* __ASM_CPU_SH3_TIMER_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/ubc.h b/arch/sh/include/cpu-sh3/cpu/ubc.h
new file mode 100644
index 000000000000..4e6381d5ff7a
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/ubc.h
@@ -0,0 +1,42 @@
+/*
+ * include/asm-sh/cpu-sh3/ubc.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_UBC_H
+#define __ASM_CPU_SH3_UBC_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define UBC_BARA                0xa4ffffb0
+#define UBC_BAMRA               0xa4ffffb4
+#define UBC_BBRA                0xa4ffffb8
+#define UBC_BASRA               0xffffffe4
+#define UBC_BARB                0xa4ffffa0
+#define UBC_BAMRB               0xa4ffffa4
+#define UBC_BBRB                0xa4ffffa8
+#define UBC_BASRB               0xffffffe8
+#define UBC_BDRB                0xa4ffff90
+#define UBC_BDMRB               0xa4ffff94
+#define UBC_BRCR                0xa4ffff98
+#else
+#define UBC_BARA                0xffffffb0
+#define UBC_BAMRA               0xffffffb4
+#define UBC_BBRA                0xffffffb8
+#define UBC_BASRA               0xffffffe4
+#define UBC_BARB                0xffffffa0
+#define UBC_BAMRB               0xffffffa4
+#define UBC_BBRB                0xffffffa8
+#define UBC_BASRB               0xffffffe8
+#define UBC_BDRB                0xffffff90
+#define UBC_BDMRB               0xffffff94
+#define UBC_BRCR                0xffffff98
+#endif
+
+#endif /* __ASM_CPU_SH3_UBC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/watchdog.h b/arch/sh/include/cpu-sh3/cpu/watchdog.h
new file mode 100644
index 000000000000..4ee0347298d8
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/watchdog.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/cpu-sh3/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH3_WATCHDOG_H
+#define __ASM_CPU_SH3_WATCHDOG_H
+
+/* Register definitions */
+#define WTCNT           0xffffff84
+#define WTCSR           0xffffff86
+
+/* Bit definitions */
+#define WTCSR_TME       0x80
+#define WTCSR_WT        0x40
+#define WTCSR_RSTS      0x20
+#define WTCSR_WOVF      0x10
+#define WTCSR_IOVF      0x08
+
+#endif /* __ASM_CPU_SH3_WATCHDOG_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/addrspace.h b/arch/sh/include/cpu-sh4/cpu/addrspace.h
new file mode 100644
index 000000000000..a3fa733c1c7d
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/addrspace.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Kaz Kojima
+ *
+ * Defitions for the address spaces of the SH-4 CPUs.
+ */
+#ifndef __ASM_CPU_SH4_ADDRSPACE_H
+#define __ASM_CPU_SH4_ADDRSPACE_H
+
+#define P0SEG           0x00000000
+#define P1SEG           0x80000000
+#define P2SEG           0xa0000000
+#define P3SEG           0xc0000000
+#define P4SEG           0xe0000000
+
+/* Detailed P4SEG  */
+#define P4SEG_STORE_QUE (P4SEG)
+#define P4SEG_IC_ADDR   0xf0000000
+#define P4SEG_IC_DATA   0xf1000000
+#define P4SEG_ITLB_ADDR 0xf2000000
+#define P4SEG_ITLB_DATA 0xf3000000
+#define P4SEG_OC_ADDR   0xf4000000
+#define P4SEG_OC_DATA   0xf5000000
+#define P4SEG_TLB_ADDR  0xf6000000
+#define P4SEG_TLB_DATA  0xf7000000
+#define P4SEG_REG_BASE  0xff000000
+
+#define PA_AREA5_IO     0xb4000000      /* Area 5 IO Memory */
+#define PA_AREA6_IO     0xb8000000      /* Area 6 IO Memory */
+
+#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h
new file mode 100644
index 000000000000..1c61ebf5c8e3
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/cache.h
@@ -0,0 +1,42 @@
+/*
+ * include/asm-sh/cpu-sh4/cache.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_CACHE_H
+#define __ASM_CPU_SH4_CACHE_H
+
+#define L1_CACHE_SHIFT  5
+
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
+#define CCR             0xff00001c      /* Address of Cache Control Register */
+#define CCR_CACHE_OCE   0x0001  /* Operand Cache Enable */
+#define CCR_CACHE_WT    0x0002  /* Write-Through (for P0,U0,P3) (else writeback)*/
+#define CCR_CACHE_CB    0x0004  /* Copy-Back (for P1) (else writethrough) */
+#define CCR_CACHE_OCI   0x0008  /* OC Invalidate */
+#define CCR_CACHE_ORA   0x0020  /* OC RAM Mode */
+#define CCR_CACHE_OIX   0x0080  /* OC Index Enable */
+#define CCR_CACHE_ICE   0x0100  /* Instruction Cache Enable */
+#define CCR_CACHE_ICI   0x0800  /* IC Invalidate */
+#define CCR_CACHE_IIX   0x8000  /* IC Index Enable */
+#ifndef CONFIG_CPU_SH4A
+#define CCR_CACHE_EMODE 0x80000000      /* EMODE Enable */
+#endif
+
+/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
+#define CCR_CACHE_ENABLE        (CCR_CACHE_OCE|CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI|CCR_CACHE_ICI)
+
+#define CACHE_IC_ADDRESS_ARRAY  0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY  0xf4000000
+
+#endif /* __ASM_CPU_SH4_CACHE_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/cacheflush.h b/arch/sh/include/cpu-sh4/cpu/cacheflush.h
new file mode 100644
index 000000000000..065306d376eb
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/cacheflush.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-sh/cpu-sh4/cacheflush.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
+#define __ASM_CPU_SH4_CACHEFLUSH_H
+
+/*
+ *  Caches are broken on SH-4 (unless we use write-through
+ *  caching; in which case they're only semi-broken),
+ *  so we need them.
+ */
+void flush_cache_all(void);
+void flush_dcache_all(void);
+void flush_cache_mm(struct mm_struct *mm);
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                       unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
+                      unsigned long pfn);
+void flush_dcache_page(struct page *pg);
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
+                             unsigned long addr, int len);
+
+#define flush_icache_page(vma,pg)               do { } while (0)
+
+/* Initialization of P3 area for copy_user_page */
+void p3_cache_init(void);
+
+#define PG_mapped       PG_arch_1
+
+#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
new file mode 100644
index 000000000000..71b426a6e482
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
@@ -0,0 +1,39 @@
+#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
+#define __ASM_SH_CPU_SH4_DMA_SH7780_H
+
+#define REQ_HE  0x000000C0
+#define REQ_H   0x00000080
+#define REQ_LE  0x00000040
+#define TM_BURST 0x0000020
+#define TS_8    0x00000000
+#define TS_16   0x00000008
+#define TS_32   0x00000010
+#define TS_16BLK        0x00000018
+#define TS_32BLK        0x00100000
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ *
+ * Defaults to a 64-bit transfer size.
+ */
+enum {
+        XMIT_SZ_8BIT,
+        XMIT_SZ_16BIT,
+        XMIT_SZ_32BIT,
+        XMIT_SZ_128BIT,
+        XMIT_SZ_256BIT,
+};
+
+/*
+ * The DMA count is defined as the number of bytes to transfer.
+ */
+static unsigned int ts_shift[] __maybe_unused = {
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_128BIT]        = 4,
+        [XMIT_SZ_256BIT]        = 5,
+};
+
+#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
new file mode 100644
index 000000000000..235b7cd1fc9a
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -0,0 +1,65 @@
+#ifndef __ASM_CPU_SH4_DMA_H
+#define __ASM_CPU_SH4_DMA_H
+
+#define DMAOR_INIT      ( 0x8000 | DMAOR_DME )
+
+/* SH7751/7760/7780 DMA IRQ sources */
+#define DMTE0_IRQ       34
+#define DMTE1_IRQ       35
+#define DMTE2_IRQ       36
+#define DMTE3_IRQ       37
+#define DMTE4_IRQ       44
+#define DMTE5_IRQ       45
+#define DMTE6_IRQ       46
+#define DMTE7_IRQ       47
+#define DMAE_IRQ        38
+
+#ifdef CONFIG_CPU_SH4A
+#define SH_DMAC_BASE    0xfc808020
+
+#define CHCR_TS_MASK    0x18
+#define CHCR_TS_SHIFT   3
+
+#include <cpu/dma-sh7780.h>
+#else
+#define SH_DMAC_BASE    0xffa00000
+
+/* Definitions for the SuperH DMAC */
+#define TM_BURST        0x0000080
+#define TS_8            0x00000010
+#define TS_16           0x00000020
+#define TS_32           0x00000030
+#define TS_64           0x00000000
+
+#define CHCR_TS_MASK    0x70
+#define CHCR_TS_SHIFT   4
+
+#define DMAOR_COD       0x00000008
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ *
+ * Defaults to a 64-bit transfer size.
+ */
+enum {
+        XMIT_SZ_64BIT,
+        XMIT_SZ_8BIT,
+        XMIT_SZ_16BIT,
+        XMIT_SZ_32BIT,
+        XMIT_SZ_256BIT,
+};
+
+/*
+ * The DMA count is defined as the number of bytes to transfer.
+ */
+static unsigned int ts_shift[] __maybe_unused = {
+        [XMIT_SZ_64BIT]         = 3,
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_256BIT]        = 5,
+};
+#endif
+
+#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/fpu.h b/arch/sh/include/cpu-sh4/cpu/fpu.h
new file mode 100644
index 000000000000..febef7342528
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/fpu.h
@@ -0,0 +1,32 @@
+/*
+ * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h
+ *
+ * Copyright (C) 2006 STMicroelectronics Limited
+ * Author: Carl Shaw <carl.shaw@st.com>
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License Version 2.  See linux/COPYING for more information.
+ *
+ * Definitions for SH4 FPU operations
+ */
+
+#ifndef __CPU_SH4_FPU_H
+#define __CPU_SH4_FPU_H
+
+#define FPSCR_ENABLE_MASK       0x00000f80UL
+
+#define FPSCR_FMOV_DOUBLE       (1<<1)
+
+#define FPSCR_CAUSE_INEXACT     (1<<12)
+#define FPSCR_CAUSE_UNDERFLOW   (1<<13)
+#define FPSCR_CAUSE_OVERFLOW    (1<<14)
+#define FPSCR_CAUSE_DIVZERO     (1<<15)
+#define FPSCR_CAUSE_INVALID     (1<<16)
+#define FPSCR_CAUSE_ERROR       (1<<17)
+
+#define FPSCR_DBL_PRECISION     (1<<19)
+#define FPSCR_ROUNDING_MODE(x)  ((x >> 20) & 3)
+#define FPSCR_RM_NEAREST        (0)
+#define FPSCR_RM_ZERO           (1)
+
+#endif
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
new file mode 100644
index 000000000000..c23af81c2e70
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -0,0 +1,44 @@
+/*
+ * include/asm-sh/cpu-sh4/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_FREQ_H
+#define __ASM_CPU_SH4_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7723) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7343) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7366)
+#define FRQCR                   0xa4150000
+#define VCLKCR                  0xa4150004
+#define SCLKACR                 0xa4150008
+#define SCLKBCR                 0xa415000c
+#define IrDACLKCR               0xa4150010
+#define MSTPCR0                 0xa4150030
+#define MSTPCR1                 0xa4150034
+#define MSTPCR2                 0xa4150038
+#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7780)
+#define FRQCR                   0xffc80000
+#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
+#define FRQCR0                  0xffc80000
+#define FRQCR1                  0xffc80004
+#define FRQMR1                  0xffc80014
+#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
+#define FRQCR                   0xffc00014
+#else
+#define FRQCR                   0xffc00000
+#define FRQCR_PSTBY             0x0200
+#define FRQCR_PLLEN             0x0400
+#define FRQCR_CKOEN             0x0800
+#endif
+#define MIN_DIVISOR_NR          0
+#define MAX_DIVISOR_NR          3
+
+#endif /* __ASM_CPU_SH4_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
new file mode 100644
index 000000000000..9ea8eb27b18e
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -0,0 +1,63 @@
+/*
+ * include/asm-sh/cpu-sh4/mmu_context.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
+#define __ASM_CPU_SH4_MMU_CONTEXT_H
+
+#define MMU_PTEH        0xFF000000      /* Page table entry register HIGH */
+#define MMU_PTEL        0xFF000004      /* Page table entry register LOW */
+#define MMU_TTB         0xFF000008      /* Translation table base register */
+#define MMU_TEA         0xFF00000C      /* TLB Exception Address */
+#define MMU_PTEA        0xFF000034      /* Page table entry assistance register */
+
+#define MMUCR           0xFF000010      /* MMU Control Register */
+
+#define MMU_ITLB_ADDRESS_ARRAY  0xF2000000
+#define MMU_UTLB_ADDRESS_ARRAY  0xF6000000
+#define MMU_PAGE_ASSOC_BIT      0x80
+
+#define MMUCR_TI                (1<<2)
+
+#ifdef CONFIG_X2TLB
+#define MMUCR_ME                (1 << 7)
+#else
+#define MMUCR_ME                (0)
+#endif
+
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
+#define MMUCR_SE                (1 << 4)
+#else
+#define MMUCR_SE                (0)
+#endif
+
+#ifdef CONFIG_SH_STORE_QUEUES
+#define MMUCR_SQMD              (1 << 9)
+#else
+#define MMUCR_SQMD              (0)
+#endif
+
+#define MMU_NTLB_ENTRIES        64
+#define MMU_CONTROL_INIT        (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
+
+#define MMU_ITLB_DATA_ARRAY     0xF3000000
+#define MMU_UTLB_DATA_ARRAY     0xF7000000
+
+#define MMU_UTLB_ENTRIES           64
+#define MMU_U_ENTRY_SHIFT           8
+#define MMU_UTLB_VALID          0x100
+#define MMU_ITLB_ENTRIES            4
+#define MMU_I_ENTRY_SHIFT           8
+#define MMU_ITLB_VALID          0x100
+
+#define TRA     0xff000020
+#define EXPEVT  0xff000024
+#define INTEVT  0xff000028
+
+#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/rtc.h b/arch/sh/include/cpu-sh4/cpu/rtc.h
new file mode 100644
index 000000000000..25b1e6adfe8c
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/rtc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SH_CPU_SH4_RTC_H
+#define __ASM_SH_CPU_SH4_RTC_H
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7723
+#define rtc_reg_size            sizeof(u16)
+#else
+#define rtc_reg_size            sizeof(u32)
+#endif
+
+#define RTC_BIT_INVERTED        0x40    /* bug on SH7750, SH7750S */
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH4_RTC_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/sigcontext.h b/arch/sh/include/cpu-sh4/cpu/sigcontext.h
new file mode 100644
index 000000000000..ab392f120e06
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sigcontext.h
@@ -0,0 +1,24 @@
+#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
+#define __ASM_CPU_SH4_SIGCONTEXT_H
+
+struct sigcontext {
+        unsigned long   oldmask;
+
+        /* CPU registers */
+        unsigned long sc_regs[16];
+        unsigned long sc_pc;
+        unsigned long sc_pr;
+        unsigned long sc_sr;
+        unsigned long sc_gbr;
+        unsigned long sc_mach;
+        unsigned long sc_macl;
+
+        /* FPU registers */
+        unsigned long sc_fpregs[16];
+        unsigned long sc_xfpregs[16];
+        unsigned int sc_fpscr;
+        unsigned int sc_fpul;
+        unsigned int sc_ownedfp;
+};
+
+#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/sq.h b/arch/sh/include/cpu-sh4/cpu/sq.h
new file mode 100644
index 000000000000..586d6491816a
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sq.h
@@ -0,0 +1,35 @@
+/*
+ * include/asm-sh/cpu-sh4/sq.h
+ *
+ * Copyright (C) 2001, 2002, 2003  Paul Mundt
+ * Copyright (C) 2001, 2002  M. R. Brown
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_SQ_H
+#define __ASM_CPU_SH4_SQ_H
+
+#include <asm/addrspace.h>
+
+/*
+ * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
+ * mapped to any physical address space. Since data is written (and aligned)
+ * to 32-byte boundaries, we need to be sure that all allocations are aligned.
+ */
+#define SQ_SIZE                 32
+#define SQ_ALIGN_MASK           (~(SQ_SIZE - 1))
+#define SQ_ALIGN(addr)          (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
+
+#define SQ_QACR0                (P4SEG_REG_BASE  + 0x38)
+#define SQ_QACR1                (P4SEG_REG_BASE  + 0x3c)
+#define SQ_ADDRMAX              (P4SEG_STORE_QUE + 0x04000000)
+
+/* arch/sh/kernel/cpu/sh4/sq.c */
+unsigned long sq_remap(unsigned long phys, unsigned int size,
+                       const char *name, unsigned long flags);
+void sq_unmap(unsigned long vaddr);
+void sq_flush_range(unsigned long start, unsigned int len);
+
+#endif /* __ASM_CPU_SH4_SQ_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h
new file mode 100644
index 000000000000..d1e796b96888
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/timer.h
@@ -0,0 +1,60 @@
+/*
+ * include/asm-sh/cpu-sh4/timer.h
+ *
+ * Copyright (C) 2004 Lineo Solutions, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_TIMER_H
+#define __ASM_CPU_SH4_TIMER_H
+
+/*
+ * ---------------------------------------------------------------------------
+ * TMU Common definitions for SH4 processors
+ *      SH7750S/SH7750R
+ *      SH7751/SH7751R
+ *      SH7760
+ *      SH-X3
+ * ---------------------------------------------------------------------------
+ */
+#ifdef CONFIG_CPU_SUBTYPE_SHX3
+#define TMU_012_BASE    0xffc10000
+#define TMU_345_BASE    0xffc20000
+#else
+#define TMU_012_BASE    0xffd80000
+#define TMU_345_BASE    0xfe100000
+#endif
+
+#define TMU_TOCR        TMU_012_BASE    /* Not supported on all CPUs */
+
+#define TMU_012_TSTR    (TMU_012_BASE + 0x04)
+#define TMU_345_TSTR    (TMU_345_BASE + 0x04)
+
+#define TMU0_TCOR       (TMU_012_BASE + 0x08)
+#define TMU0_TCNT       (TMU_012_BASE + 0x0c)
+#define TMU0_TCR        (TMU_012_BASE + 0x10)
+
+#define TMU1_TCOR       (TMU_012_BASE + 0x14)
+#define TMU1_TCNT       (TMU_012_BASE + 0x18)
+#define TMU1_TCR        (TMU_012_BASE + 0x1c)
+
+#define TMU2_TCOR       (TMU_012_BASE + 0x20)
+#define TMU2_TCNT       (TMU_012_BASE + 0x24)
+#define TMU2_TCR        (TMU_012_BASE + 0x28)
+#define TMU2_TCPR       (TMU_012_BASE + 0x2c)
+
+#define TMU3_TCOR       (TMU_345_BASE + 0x08)
+#define TMU3_TCNT       (TMU_345_BASE + 0x0c)
+#define TMU3_TCR        (TMU_345_BASE + 0x10)
+
+#define TMU4_TCOR       (TMU_345_BASE + 0x14)
+#define TMU4_TCNT       (TMU_345_BASE + 0x18)
+#define TMU4_TCR        (TMU_345_BASE + 0x1c)
+
+#define TMU5_TCOR       (TMU_345_BASE + 0x20)
+#define TMU5_TCNT       (TMU_345_BASE + 0x24)
+#define TMU5_TCR        (TMU_345_BASE + 0x28)
+
+#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/ubc.h b/arch/sh/include/cpu-sh4/cpu/ubc.h
new file mode 100644
index 000000000000..c86e17050935
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/ubc.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-sh/cpu-sh4/ubc.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2003 Paul Mundt
+ * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_UBC_H
+#define __ASM_CPU_SH4_UBC_H
+
+#if defined(CONFIG_CPU_SH4A)
+#define UBC_CBR0                0xff200000
+#define UBC_CRR0                0xff200004
+#define UBC_CAR0                0xff200008
+#define UBC_CAMR0               0xff20000c
+#define UBC_CBR1                0xff200020
+#define UBC_CRR1                0xff200024
+#define UBC_CAR1                0xff200028
+#define UBC_CAMR1               0xff20002c
+#define UBC_CDR1                0xff200030
+#define UBC_CDMR1               0xff200034
+#define UBC_CETR1               0xff200038
+#define UBC_CCMFR               0xff200600
+#define UBC_CBCR                0xff200620
+
+/* CBR  */
+#define UBC_CBR_AIE             (0x01<<30)
+#define UBC_CBR_ID_INST         (0x01<<4)
+#define UBC_CBR_RW_READ         (0x01<<1)
+#define UBC_CBR_CE              (0x01)
+
+#define UBC_CBR_AIV_MASK        (0x00FF0000)
+#define UBC_CBR_AIV_SHIFT       (16)
+#define UBC_CBR_AIV_SET(asid)   (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
+
+#define UBC_CBR_INIT            0x20000000
+
+/* CRR  */
+#define UBC_CRR_RES             (0x01<<13)
+#define UBC_CRR_PCB             (0x01<<1)
+#define UBC_CRR_BIE             (0x01)
+
+#define UBC_CRR_INIT            0x00002000
+
+#else   /* CONFIG_CPU_SH4 */
+#define UBC_BARA                0xff200000
+#define UBC_BAMRA               0xff200004
+#define UBC_BBRA                0xff200008
+#define UBC_BASRA               0xff000014
+#define UBC_BARB                0xff20000c
+#define UBC_BAMRB               0xff200010
+#define UBC_BBRB                0xff200014
+#define UBC_BASRB               0xff000018
+#define UBC_BDRB                0xff200018
+#define UBC_BDMRB               0xff20001c
+#define UBC_BRCR                0xff200020
+#endif  /* CONFIG_CPU_SH4 */
+
+#endif /* __ASM_CPU_SH4_UBC_H */
+
diff --git a/arch/sh/include/cpu-sh4/cpu/watchdog.h b/arch/sh/include/cpu-sh4/cpu/watchdog.h
new file mode 100644
index 000000000000..259f6a0ce23d
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/watchdog.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/cpu-sh4/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH4_WATCHDOG_H
+#define __ASM_CPU_SH4_WATCHDOG_H
+
+/* Register definitions */
+#define WTCNT           0xffc00008
+#define WTCSR           0xffc0000c
+
+/* Bit definitions */
+#define WTCSR_TME       0x80
+#define WTCSR_WT        0x40
+#define WTCSR_RSTS      0x20
+#define WTCSR_WOVF      0x10
+#define WTCSR_IOVF      0x08
+
+#endif /* __ASM_CPU_SH4_WATCHDOG_H */
+
diff --git a/arch/sh/include/cpu-sh5/cpu/addrspace.h b/arch/sh/include/cpu-sh5/cpu/addrspace.h
new file mode 100644
index 000000000000..dc36b9a03af6
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/addrspace.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
+#define __ASM_SH_CPU_SH5_ADDRSPACE_H
+
+#define PHYS_PERIPHERAL_BLOCK   0x09000000
+#define PHYS_DMAC_BLOCK         0x0e000000
+#define PHYS_PCI_BLOCK          0x60000000
+#define PHYS_EMI_BLOCK          0xff000000
+
+/* No segmentation.. */
+
+#endif /* __ASM_SH_CPU_SH5_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cache.h b/arch/sh/include/cpu-sh5/cpu/cache.h
new file mode 100644
index 000000000000..ed050ab526f2
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cache.h
@@ -0,0 +1,97 @@
+#ifndef __ASM_SH_CPU_SH5_CACHE_H
+#define __ASM_SH_CPU_SH5_CACHE_H
+
+/*
+ * include/asm-sh/cpu-sh5/cache.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#define L1_CACHE_SHIFT          5
+
+/* Valid and Dirty bits */
+#define SH_CACHE_VALID          (1LL<<0)
+#define SH_CACHE_UPDATED        (1LL<<57)
+
+/* Unimplemented compat bits.. */
+#define SH_CACHE_COMBINED       0
+#define SH_CACHE_ASSOC          0
+
+/* Cache flags */
+#define SH_CACHE_MODE_WT        (1LL<<0)
+#define SH_CACHE_MODE_WB        (1LL<<1)
+
+/*
+ * Control Registers.
+ */
+#define ICCR_BASE       0x01600000      /* Instruction Cache Control Register */
+#define ICCR_REG0       0               /* Register 0 offset */
+#define ICCR_REG1       1               /* Register 1 offset */
+#define ICCR0           ICCR_BASE+ICCR_REG0
+#define ICCR1           ICCR_BASE+ICCR_REG1
+
+#define ICCR0_OFF       0x0             /* Set ICACHE off */
+#define ICCR0_ON        0x1             /* Set ICACHE on */
+#define ICCR0_ICI       0x2             /* Invalidate all in IC */
+
+#define ICCR1_NOLOCK    0x0             /* Set No Locking */
+
+#define OCCR_BASE       0x01E00000      /* Operand Cache Control Register */
+#define OCCR_REG0       0               /* Register 0 offset */
+#define OCCR_REG1       1               /* Register 1 offset */
+#define OCCR0           OCCR_BASE+OCCR_REG0
+#define OCCR1           OCCR_BASE+OCCR_REG1
+
+#define OCCR0_OFF       0x0             /* Set OCACHE off */
+#define OCCR0_ON        0x1             /* Set OCACHE on */
+#define OCCR0_OCI       0x2             /* Invalidate all in OC */
+#define OCCR0_WT        0x4             /* Set OCACHE in WT Mode */
+#define OCCR0_WB        0x0             /* Set OCACHE in WB Mode */
+
+#define OCCR1_NOLOCK    0x0             /* Set No Locking */
+
+/*
+ * SH-5
+ * A bit of description here, for neff=32.
+ *
+ *                               |<--- tag  (19 bits) --->|
+ * +-----------------------------+-----------------+------+----------+------+
+ * |                             |                 | ways |set index |offset|
+ * +-----------------------------+-----------------+------+----------+------+
+ *                                ^                 2 bits   8 bits   5 bits
+ *                                +- Bit 31
+ *
+ * Cacheline size is based on offset: 5 bits = 32 bytes per line
+ * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
+ * have a broader space for registers. These are outlined by
+ * CACHE_?C_*_STEP below.
+ *
+ */
+
+/* Instruction cache */
+#define CACHE_IC_ADDRESS_ARRAY 0x01000000
+
+/* Operand Cache */
+#define CACHE_OC_ADDRESS_ARRAY 0x01800000
+
+/* These declarations relate to cache 'synonyms' in the operand cache.  A
+   'synonym' occurs where effective address bits overlap between those used for
+   indexing the cache sets and those passed to the MMU for translation.  In the
+   case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
+
+#define CACHE_OC_N_SYNBITS  1               /* Number of synonym bits */
+#define CACHE_OC_SYN_SHIFT  12
+/* Mask to select synonym bit(s) */
+#define CACHE_OC_SYN_MASK   (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
+
+/*
+ * Instruction cache can't be invalidated based on physical addresses.
+ * No Instruction Cache defines required, then.
+ */
+
+#endif /* __ASM_SH_CPU_SH5_CACHE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
new file mode 100644
index 000000000000..5a11f0b7e66a
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H
+#define __ASM_SH_CPU_SH5_CACHEFLUSH_H
+
+#ifndef __ASSEMBLY__
+
+struct vm_area_struct;
+struct page;
+struct mm_struct;
+
+extern void flush_cache_all(void);
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_sigtramp(unsigned long vaddr);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                              unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
+extern void flush_dcache_page(struct page *pg);
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void flush_icache_user_range(struct vm_area_struct *vma,
+                                    struct page *page, unsigned long addr,
+                                    int len);
+
+#define flush_cache_dup_mm(mm)  flush_cache_mm(mm)
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+#define flush_icache_page(vma, page)    do { } while (0)
+void p3_cache_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */
+
diff --git a/arch/sh/include/cpu-sh5/cpu/dma.h b/arch/sh/include/cpu-sh5/cpu/dma.h
new file mode 100644
index 000000000000..7bf6bb3d35ed
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/dma.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_CPU_SH5_DMA_H
+#define __ASM_SH_CPU_SH5_DMA_H
+
+/* Nothing yet */
+
+#endif /* __ASM_SH_CPU_SH5_DMA_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/irq.h b/arch/sh/include/cpu-sh5/cpu/irq.h
new file mode 100644
index 000000000000..f0f0756e6e84
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/irq.h
@@ -0,0 +1,117 @@
+#ifndef __ASM_SH_CPU_SH5_IRQ_H
+#define __ASM_SH_CPU_SH5_IRQ_H
+
+/*
+ * include/asm-sh/cpu-sh5/irq.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+
+/*
+ * Encoded IRQs are not considered worth to be supported.
+ * Main reason is that there's no per-encoded-interrupt
+ * enable/disable mechanism (as there was in SH3/4).
+ * An all enabled/all disabled is worth only if there's
+ * a cascaded IC to disable/enable/ack on. Until such
+ * IC is available there's no such support.
+ *
+ * Presumably Encoded IRQs may use extra IRQs beyond 64,
+ * below. Some logic must be added to cope with IRQ_IRL?
+ * in an exclusive way.
+ *
+ * Priorities are set at Platform level, when IRQ_IRL0-3
+ * are set to 0 Encoding is allowed. Otherwise it's not
+ * allowed.
+ */
+
+/* Independent IRQs */
+#define IRQ_IRL0        0
+#define IRQ_IRL1        1
+#define IRQ_IRL2        2
+#define IRQ_IRL3        3
+
+#define IRQ_INTA        4
+#define IRQ_INTB        5
+#define IRQ_INTC        6
+#define IRQ_INTD        7
+
+#define IRQ_SERR        12
+#define IRQ_ERR         13
+#define IRQ_PWR3        14
+#define IRQ_PWR2        15
+#define IRQ_PWR1        16
+#define IRQ_PWR0        17
+
+#define IRQ_DMTE0       18
+#define IRQ_DMTE1       19
+#define IRQ_DMTE2       20
+#define IRQ_DMTE3       21
+#define IRQ_DAERR       22
+
+#define IRQ_TUNI0       32
+#define IRQ_TUNI1       33
+#define IRQ_TUNI2       34
+#define IRQ_TICPI2      35
+
+#define IRQ_ATI         36
+#define IRQ_PRI         37
+#define IRQ_CUI         38
+
+#define IRQ_ERI         39
+#define IRQ_RXI         40
+#define IRQ_BRI         41
+#define IRQ_TXI         42
+
+#define IRQ_ITI         63
+
+#define NR_INTC_IRQS    64
+
+#ifdef CONFIG_SH_CAYMAN
+#define NR_EXT_IRQS     32
+#define START_EXT_IRQS  64
+
+/* PCI bus 2 uses encoded external interrupts on the Cayman board */
+#define IRQ_P2INTA      (START_EXT_IRQS + (3*8) + 0)
+#define IRQ_P2INTB      (START_EXT_IRQS + (3*8) + 1)
+#define IRQ_P2INTC      (START_EXT_IRQS + (3*8) + 2)
+#define IRQ_P2INTD      (START_EXT_IRQS + (3*8) + 3)
+
+#define I8042_KBD_IRQ   (START_EXT_IRQS + 2)
+#define I8042_AUX_IRQ   (START_EXT_IRQS + 6)
+
+#define IRQ_CFCARD      (START_EXT_IRQS + 7)
+#define IRQ_PCMCIA      (0)
+
+#else
+#define NR_EXT_IRQS     0
+#endif
+
+/* Default IRQs, fixed */
+#define TIMER_IRQ       IRQ_TUNI0
+#define RTC_IRQ         IRQ_CUI
+
+/* Default Priorities, Platform may choose differently */
+#define NO_PRIORITY     0       /* Disabled */
+#define TIMER_PRIORITY  2
+#define RTC_PRIORITY    TIMER_PRIORITY
+#define SCIF_PRIORITY   3
+#define INTD_PRIORITY   3
+#define IRL3_PRIORITY   4
+#define INTC_PRIORITY   6
+#define IRL2_PRIORITY   7
+#define INTB_PRIORITY   9
+#define IRL1_PRIORITY   10
+#define INTA_PRIORITY   12
+#define IRL0_PRIORITY   13
+#define TOP_PRIORITY    15
+
+extern int intc_evt_to_irq[(0xE20/0x20)+1];
+int intc_irq_describe(char* p, int irq);
+extern int platform_int_priority[NR_INTC_IRQS];
+
+#endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/mmu_context.h b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
new file mode 100644
index 000000000000..68a1d2cff457
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
+#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H
+
+/* Common defines */
+#define TLB_STEP        0x00000010
+#define TLB_PTEH        0x00000000
+#define TLB_PTEL        0x00000008
+
+/* PTEH defines */
+#define PTEH_ASID_SHIFT 2
+#define PTEH_VALID      0x0000000000000001
+#define PTEH_SHARED     0x0000000000000002
+#define PTEH_MATCH_ASID 0x00000000000003ff
+
+#ifndef __ASSEMBLY__
+/* This has to be a common function because the next location to fill
+ * information is shared. */
+extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/registers.h b/arch/sh/include/cpu-sh5/cpu/registers.h
new file mode 100644
index 000000000000..6664ea6f1566
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/registers.h
@@ -0,0 +1,106 @@
+#ifndef __ASM_SH_CPU_SH5_REGISTERS_H
+#define __ASM_SH_CPU_SH5_REGISTERS_H
+
+/*
+ * include/asm-sh/cpu-sh5/registers.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifdef __ASSEMBLY__
+/* =====================================================================
+**
+** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
+**            Assigns symbolic names to control & target registers.
+*/
+
+/*
+ * Define some useful aliases for control registers.
+ */
+#define SR      cr0
+#define SSR     cr1
+#define PSSR    cr2
+                        /* cr3 UNDEFINED */
+#define INTEVT  cr4
+#define EXPEVT  cr5
+#define PEXPEVT cr6
+#define TRA     cr7
+#define SPC     cr8
+#define PSPC    cr9
+#define RESVEC  cr10
+#define VBR     cr11
+                        /* cr12 UNDEFINED */
+#define TEA     cr13
+                        /* cr14-cr15 UNDEFINED */
+#define DCR     cr16
+#define KCR0    cr17
+#define KCR1    cr18
+                        /* cr19-cr31 UNDEFINED */
+                        /* cr32-cr61 RESERVED */
+#define CTC     cr62
+#define USR     cr63
+
+/*
+ * ABI dependent registers (general purpose set)
+ */
+#define RET     r2
+#define ARG1    r2
+#define ARG2    r3
+#define ARG3    r4
+#define ARG4    r5
+#define ARG5    r6
+#define ARG6    r7
+#define SP      r15
+#define LINK    r18
+#define ZERO    r63
+
+/*
+ * Status register defines: used only by assembly sources (and
+ *                          syntax independednt)
+ */
+#define SR_RESET_VAL    0x0000000050008000
+#define SR_HARMLESS     0x00000000500080f0      /* Write ignores for most */
+#define SR_ENABLE_FPU   0xffffffffffff7fff      /* AND with this */
+
+#if defined (CONFIG_SH64_SR_WATCH)
+#define SR_ENABLE_MMU   0x0000000084000000      /* OR with this */
+#else
+#define SR_ENABLE_MMU   0x0000000080000000      /* OR with this */
+#endif
+
+#define SR_UNBLOCK_EXC  0xffffffffefffffff      /* AND with this */
+#define SR_BLOCK_EXC    0x0000000010000000      /* OR with this */
+
+#else   /* Not __ASSEMBLY__ syntax */
+
+/*
+** Stringify reg. name
+*/
+#define __str(x)  #x
+
+/* Stringify control register names for use in inline assembly */
+#define __SR __str(SR)
+#define __SSR __str(SSR)
+#define __PSSR __str(PSSR)
+#define __INTEVT __str(INTEVT)
+#define __EXPEVT __str(EXPEVT)
+#define __PEXPEVT __str(PEXPEVT)
+#define __TRA __str(TRA)
+#define __SPC __str(SPC)
+#define __PSPC __str(PSPC)
+#define __RESVEC __str(RESVEC)
+#define __VBR __str(VBR)
+#define __TEA __str(TEA)
+#define __DCR __str(DCR)
+#define __KCR0 __str(KCR0)
+#define __KCR1 __str(KCR1)
+#define __CTC __str(CTC)
+#define __USR __str(USR)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/rtc.h b/arch/sh/include/cpu-sh5/cpu/rtc.h
new file mode 100644
index 000000000000..12ea0ed144e1
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH5_RTC_H
+#define __ASM_SH_CPU_SH5_RTC_H
+
+#define rtc_reg_size            sizeof(u32)
+#define RTC_BIT_INVERTED        0       /* The SH-5 RTC is surprisingly sane! */
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH5_RTC_H */
diff --git a/arch/sh/include/mach-dreamcast/mach/dma.h b/arch/sh/include/mach-dreamcast/mach/dma.h
new file mode 100644
index 000000000000..ddd68e788705
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/dma.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-sh/dreamcast/dma.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DREAMCAST_DMA_H
+#define __ASM_SH_DREAMCAST_DMA_H
+
+/* Number of DMA channels */
+#define ONCHIP_NR_DMA_CHANNELS  4
+#define G2_NR_DMA_CHANNELS      4
+#define PVR2_NR_DMA_CHANNELS    1
+
+/* Channels for cascading */
+#define PVR2_CASCADE_CHAN       2
+#define G2_CASCADE_CHAN         3
+
+/* PVR2 DMA Registers */
+#define PVR2_DMA_BASE           0xa05f6800
+#define PVR2_DMA_ADDR           (PVR2_DMA_BASE + 0)
+#define PVR2_DMA_COUNT          (PVR2_DMA_BASE + 4)
+#define PVR2_DMA_MODE           (PVR2_DMA_BASE + 8)
+#define PVR2_DMA_LMMODE0        (PVR2_DMA_BASE + 132)
+#define PVR2_DMA_LMMODE1        (PVR2_DMA_BASE + 136)
+
+/* G2 DMA Register */
+#define G2_DMA_BASE             0xa05f7800
+
+#endif /* __ASM_SH_DREAMCAST_DMA_H */
+
diff --git a/arch/sh/include/mach-dreamcast/mach/maple.h b/arch/sh/include/mach-dreamcast/mach/maple.h
new file mode 100644
index 000000000000..51f6a87f1f11
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/maple.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_MAPLE_H
+#define __ASM_MAPLE_H
+
+#define MAPLE_PORTS 4
+#define MAPLE_PNP_INTERVAL HZ
+#define MAPLE_MAXPACKETS 8
+#define MAPLE_DMA_ORDER 14
+#define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER)
+#define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \
+                          MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
+
+/* Maple Bus registers */
+#define MAPLE_BASE     0xa05f6c00
+#define MAPLE_DMAADDR  (MAPLE_BASE+0x04)
+#define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
+#define MAPLE_ENABLE   (MAPLE_BASE+0x14)
+#define MAPLE_STATE    (MAPLE_BASE+0x18)
+#define MAPLE_SPEED    (MAPLE_BASE+0x80)
+#define MAPLE_RESET    (MAPLE_BASE+0x8c)
+
+#define MAPLE_MAGIC    0x6155404f
+#define MAPLE_2MBPS    0
+#define MAPLE_TIMEOUT(n) ((n)<<15)
+
+/* Function codes */
+#define MAPLE_FUNC_CONTROLLER 0x001
+#define MAPLE_FUNC_MEMCARD    0x002
+#define MAPLE_FUNC_LCD        0x004
+#define MAPLE_FUNC_CLOCK      0x008
+#define MAPLE_FUNC_MICROPHONE 0x010
+#define MAPLE_FUNC_ARGUN      0x020
+#define MAPLE_FUNC_KEYBOARD   0x040
+#define MAPLE_FUNC_LIGHTGUN   0x080
+#define MAPLE_FUNC_PURUPURU   0x100
+#define MAPLE_FUNC_MOUSE      0x200
+
+#endif /* __ASM_MAPLE_H */
diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h
new file mode 100644
index 000000000000..75fc9009e092
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/pci.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/dreamcast/pci.h
+ *
+ * Copyright (C) 2001, 2002  M. R. Brown
+ * Copyright (C) 2002, 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DREAMCAST_PCI_H
+#define __ASM_SH_DREAMCAST_PCI_H
+
+#include <mach-dreamcast/mach/sysasic.h>
+
+#define GAPSPCI_REGS            0x01001400
+#define GAPSPCI_DMA_BASE        0x01840000
+#define GAPSPCI_DMA_SIZE        32768
+#define GAPSPCI_BBA_CONFIG      0x01001600
+#define GAPSPCI_BBA_CONFIG_SIZE 0x2000
+
+#define GAPSPCI_IRQ             HW_EVENT_EXTERNAL
+
+#endif /* __ASM_SH_DREAMCAST_PCI_H */
+
diff --git a/arch/sh/include/mach-dreamcast/mach/sysasic.h b/arch/sh/include/mach-dreamcast/mach/sysasic.h
new file mode 100644
index 000000000000..f33426608a87
--- /dev/null
+++ b/arch/sh/include/mach-dreamcast/mach/sysasic.h
@@ -0,0 +1,43 @@
+/* include/asm-sh/dreamcast/sysasic.h
+ *
+ * Definitions for the Dreamcast System ASIC and related peripherals.
+ *
+ * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
+ * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
+ *
+ * This file is part of the LinuxDC project (www.linuxdc.org)
+ *
+ * Released under the terms of the GNU GPL v2.0.
+ *
+ */
+#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
+#define __ASM_SH_DREAMCAST_SYSASIC_H
+
+#include <asm/irq.h>
+
+/* Hardware events -
+
+   Each of these events correspond to a bit within the Event Mask Registers/
+   Event Status Registers.  Because of the virtual IRQ numbering scheme, a
+   base offset must be used when calculating the virtual IRQ that each event
+   takes.
+*/
+
+#define HW_EVENT_IRQ_BASE  48
+
+/* IRQ 13 */
+#define HW_EVENT_VSYNC     (HW_EVENT_IRQ_BASE +  5) /* VSync */
+#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
+#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
+#define HW_EVENT_G2_DMA    (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
+#define HW_EVENT_PVR2_DMA  (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
+
+/* IRQ 11 */
+#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
+#define HW_EVENT_AICA_SYS  (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
+#define HW_EVENT_EXTERNAL  (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
+
+#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
+
+#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
+
diff --git a/arch/sh/include/mach-landisk/mach/gio.h b/arch/sh/include/mach-landisk/mach/gio.h
new file mode 100644
index 000000000000..35d7368b718a
--- /dev/null
+++ b/arch/sh/include/mach-landisk/mach/gio.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_SH_LANDISK_GIO_H
+#define __ASM_SH_LANDISK_GIO_H
+
+#include <linux/ioctl.h>
+
+/* version */
+#define VERSION_STR     "1.00"
+
+/* Driver name */
+#define GIO_DRIVER_NAME         "/dev/giodrv"
+
+/* Use 'k' as magic number */
+#define GIODRV_IOC_MAGIC  'k'
+
+#define GIODRV_IOCRESET    _IO(GIODRV_IOC_MAGIC, 0)
+/*
+ * S means "Set" through a ptr,
+ * T means "Tell" directly
+ * G means "Get" (to a pointed var)
+ * Q means "Query", response is on the return value
+ * X means "eXchange": G and S atomically
+ * H means "sHift": T and Q atomically
+ */
+#define GIODRV_IOCSGIODATA1   _IOW(GIODRV_IOC_MAGIC,  1, unsigned char *)
+#define GIODRV_IOCGGIODATA1   _IOR(GIODRV_IOC_MAGIC,  2, unsigned char *)
+#define GIODRV_IOCSGIODATA2   _IOW(GIODRV_IOC_MAGIC,  3, unsigned short *)
+#define GIODRV_IOCGGIODATA2   _IOR(GIODRV_IOC_MAGIC,  4, unsigned short *)
+#define GIODRV_IOCSGIODATA4   _IOW(GIODRV_IOC_MAGIC,  5, unsigned long *)
+#define GIODRV_IOCGGIODATA4   _IOR(GIODRV_IOC_MAGIC,  6, unsigned long *)
+#define GIODRV_IOCSGIOSETADDR _IOW(GIODRV_IOC_MAGIC,  7, unsigned long *)
+#define GIODRV_IOCHARDRESET   _IO(GIODRV_IOC_MAGIC, 8) /* debugging tool */
+#define GIODRV_IOC_MAXNR 8
+
+#define GIO_READ 0x00000000
+#define GIO_WRITE 0x00000001
+
+#endif /* __ASM_SH_LANDISK_GIO_H  */
diff --git a/arch/sh/include/mach-landisk/mach/iodata_landisk.h b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
new file mode 100644
index 000000000000..6fb04ab38b9f
--- /dev/null
+++ b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
@@ -0,0 +1,42 @@
+#ifndef __ASM_SH_IODATA_LANDISK_H
+#define __ASM_SH_IODATA_LANDISK_H
+
+/*
+ * linux/include/asm-sh/landisk/iodata_landisk.h
+ *
+ * Copyright (C) 2000  Atom Create Engineering Co., Ltd.
+ *
+ * IO-DATA LANDISK support
+ */
+
+/* Box specific addresses.  */
+
+#define PA_USB          0xa4000000      /* USB Controller M66590 */
+
+#define PA_ATARST       0xb0000000      /* ATA/FATA Access Control Register */
+#define PA_LED          0xb0000001      /* LED Control Register */
+#define PA_STATUS       0xb0000002      /* Switch Status Register */
+#define PA_SHUTDOWN     0xb0000003      /* Shutdown Control Register */
+#define PA_PCIPME       0xb0000004      /* PCI PME Status Register */
+#define PA_IMASK        0xb0000005      /* Interrupt Mask Register */
+/* 2003.10.31 I-O DATA NSD NWG  add.    for shutdown port clear */
+#define PA_PWRINT_CLR   0xb0000006      /* Shutdown Interrupt clear Register */
+
+#define PA_PIDE_OFFSET  0x40            /* CF IDE Offset */
+#define PA_SIDE_OFFSET  0x40            /* HDD IDE Offset */
+
+#define IRQ_PCIINTA     5               /* PCI INTA IRQ */
+#define IRQ_PCIINTB     6               /* PCI INTB IRQ */
+#define IRQ_PCIINDC     7               /* PCI INTC IRQ */
+#define IRQ_PCIINTD     8               /* PCI INTD IRQ */
+#define IRQ_ATA         9               /* ATA IRQ */
+#define IRQ_FATA        10              /* FATA IRQ */
+#define IRQ_POWER       11              /* Power Switch IRQ */
+#define IRQ_BUTTON      12              /* USL-5P Button IRQ */
+#define IRQ_FAULT       13              /* USL-5P Fault  IRQ */
+
+#define __IO_PREFIX landisk
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_IODATA_LANDISK_H */
+
diff --git a/arch/sh/include/mach-se/mach/se.h b/arch/sh/include/mach-se/mach/se.h
new file mode 100644
index 000000000000..eb23000e1bbe
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se.h
@@ -0,0 +1,99 @@
+#ifndef __ASM_SH_HITACHI_SE_H
+#define __ASM_SH_HITACHI_SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_se.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0x01000000      /* EPROM */
+#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0x12000000
+#define PA_EXT4_SIZE    0x02000000
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
+
+#define PA_83902        0xb0000000      /* DP83902A */
+#define PA_83902_IF     0xb0040000      /* DP83902A remote io port */
+#define PA_83902_RST    0xb0080000      /* DP83902A reset port */
+
+#define PA_SUPERIO      0xb0400000      /* SMC37C935A super io chip */
+#define PA_DIPSW0       0xb0800000      /* Dip switch 5,6 */
+#define PA_DIPSW1       0xb0800002      /* Dip switch 7,8 */
+#define PA_LED          0xb0c00000      /* LED */
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define PA_BCR          0xb0e00000
+#else
+#define PA_BCR          0xb1400000      /* FPGA */
+#endif
+
+#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA       (PA_BCR + 0)
+#define BCR_ILCRB       (PA_BCR + 2)
+#define BCR_ILCRC       (PA_BCR + 4)
+#define BCR_ILCRD       (PA_BCR + 6)
+#define BCR_ILCRE       (PA_BCR + 8)
+#define BCR_ILCRF       (PA_BCR + 10)
+#define BCR_ILCRG       (PA_BCR + 12)
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define IRQ_STNIC       12
+#define IRQ_CFCARD      14
+#else
+#define IRQ_STNIC       10
+#define IRQ_CFCARD      7
+#endif
+
+/* SH Ether support (SH7710/SH7712) */
+/* Base address */
+#define SH_ETH0_BASE 0xA7000000
+#define SH_ETH1_BASE 0xA7000400
+/* PHY ID */
+#if defined(CONFIG_CPU_SUBTYPE_SH7710)
+# define PHY_ID 0x00
+#elif defined(CONFIG_CPU_SUBTYPE_SH7712)
+# define PHY_ID 0x01
+#endif
+/* Ether IRQ */
+#define SH_ETH0_IRQ     80
+#define SH_ETH1_IRQ     81
+#define SH_TSU_IRQ      82
+
+void init_se_IRQ(void);
+
+#define __IO_PREFIX     se
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_HITACHI_SE_H */
diff --git a/arch/sh/include/mach-se/mach/se7206.h b/arch/sh/include/mach-se/mach/se7206.h
new file mode 100644
index 000000000000..698eb80389ab
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7206.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SH_SE7206_H
+#define __ASM_SH_SE7206_H
+
+#define PA_SMSC         0x30000000
+#define PA_MRSHPC       0x34000000
+#define PA_LED          0x31400000
+
+void init_se7206_IRQ(void);
+
+#define __IO_PREFIX     se7206
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SE7206_H */
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
new file mode 100644
index 000000000000..98458460e632
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -0,0 +1,149 @@
+#ifndef __ASM_SH_HITACHI_SE7343_H
+#define __ASM_SH_HITACHI_SE7343_H
+
+/*
+ * include/asm-sh/se/se7343.h
+ *
+ * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
+ *
+ * SH-Mobile SolutionEngine 7343 support
+ */
+
+/* Box specific addresses.  */
+
+/* Area 0 */
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte(Actually 2MB) */
+#define PA_FROM         0x00400000      /* Flash ROM */
+#define PA_FROM_SIZE    0x00400000      /* Flash size 4M byte */
+#define PA_SRAM         0x00800000      /* SRAM */
+#define PA_FROM_SIZE    0x00400000      /* SRAM size 4M byte */
+/* Area 1 */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+/* Area 2 */
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+/* Area 3 */
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+/* Area 4 */
+#define PA_PCIC         0x10000000      /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC       0xb03fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb0400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb0500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb0600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+#define PA_LED          0xb0C00000      /* LED */
+#define LED_SHIFT       0
+#define PA_DIPSW        0xb0900000      /* Dip switch 31 */
+#define PA_CPLD_MODESET 0xb1400004      /* CPLD Mode set register */
+#define PA_CPLD_ST      0xb1400008      /* CPLD Interrupt status register */
+#define PA_CPLD_IMSK    0xb140000a      /* CPLD Interrupt mask register */
+/* Area 5 */
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+/* Area 6 */
+#define PA_LCD1         0xb8000000
+#define PA_LCD2         0xb8800000
+
+#define PORT_PACR       0xA4050100
+#define PORT_PBCR       0xA4050102
+#define PORT_PCCR       0xA4050104
+#define PORT_PDCR       0xA4050106
+#define PORT_PECR       0xA4050108
+#define PORT_PFCR       0xA405010A
+#define PORT_PGCR       0xA405010C
+#define PORT_PHCR       0xA405010E
+#define PORT_PJCR       0xA4050110
+#define PORT_PKCR       0xA4050112
+#define PORT_PLCR       0xA4050114
+#define PORT_PMCR       0xA4050116
+#define PORT_PNCR       0xA4050118
+#define PORT_PQCR       0xA405011A
+#define PORT_PRCR       0xA405011C
+#define PORT_PSCR       0xA405011E
+#define PORT_PTCR       0xA4050140
+#define PORT_PUCR       0xA4050142
+#define PORT_PVCR       0xA4050144
+#define PORT_PWCR       0xA4050146
+#define PORT_PYCR       0xA4050148
+#define PORT_PZCR       0xA405014A
+
+#define PORT_PSELA      0xA405014C
+#define PORT_PSELB      0xA405014E
+#define PORT_PSELC      0xA4050150
+#define PORT_PSELD      0xA4050152
+#define PORT_PSELE      0xA4050154
+
+#define PORT_HIZCRA     0xA4050156
+#define PORT_HIZCRB     0xA4050158
+#define PORT_HIZCRC     0xA405015C
+
+#define PORT_DRVCR      0xA4050180
+
+#define PORT_PADR       0xA4050120
+#define PORT_PBDR       0xA4050122
+#define PORT_PCDR       0xA4050124
+#define PORT_PDDR       0xA4050126
+#define PORT_PEDR       0xA4050128
+#define PORT_PFDR       0xA405012A
+#define PORT_PGDR       0xA405012C
+#define PORT_PHDR       0xA405012E
+#define PORT_PJDR       0xA4050130
+#define PORT_PKDR       0xA4050132
+#define PORT_PLDR       0xA4050134
+#define PORT_PMDR       0xA4050136
+#define PORT_PNDR       0xA4050138
+#define PORT_PQDR       0xA405013A
+#define PORT_PRDR       0xA405013C
+#define PORT_PTDR       0xA4050160
+#define PORT_PUDR       0xA4050162
+#define PORT_PVDR       0xA4050164
+#define PORT_PWDR       0xA4050166
+#define PORT_PYDR       0xA4050168
+
+#define FPGA_IN         0xb1400000
+#define FPGA_OUT        0xb1400002
+
+#define __IO_PREFIX     sh7343se
+#include <asm/io_generic.h>
+
+#define IRQ0_IRQ        32
+#define IRQ1_IRQ        33
+#define IRQ4_IRQ        36
+#define IRQ5_IRQ        37
+
+#define SE7343_FPGA_IRQ_MRSHPC0 0
+#define SE7343_FPGA_IRQ_MRSHPC1 1
+#define SE7343_FPGA_IRQ_MRSHPC2 2
+#define SE7343_FPGA_IRQ_MRSHPC3 3
+#define SE7343_FPGA_IRQ_SMC     6       /* EXT_IRQ2 */
+#define SE7343_FPGA_IRQ_USB     8
+
+#define SE7343_FPGA_IRQ_NR      11
+#define SE7343_FPGA_IRQ_BASE    120
+
+#define MRSHPC_IRQ3     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
+#define MRSHPC_IRQ2     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
+#define MRSHPC_IRQ1     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
+#define MRSHPC_IRQ0     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
+#define SMC_IRQ         (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
+#define USB_IRQ         (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
+
+/* arch/sh/boards/se/7343/irq.c */
+void init_7343se_IRQ(void);
+
+#endif  /* __ASM_SH_HITACHI_SE7343_H */
diff --git a/arch/sh/include/mach-se/mach/se7721.h b/arch/sh/include/mach-se/mach/se7721.h
new file mode 100644
index 000000000000..b957f6041193
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7721.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#ifndef __ASM_SH_SE7721_H
+#define __ASM_SH_SE7721_H
+#include <asm/addrspace.h>
+
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH  2               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00200000      /* EPROM size 2M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM        0xaC000000      /* SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+
+#define PA_PERIPHERAL   0xB8000000
+
+#define PA_PCIC         PA_PERIPHERAL
+#define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)
+#define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)
+#define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)
+#define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO        (PA_MRSHPC + 30)
+
+#define PA_LED          0xB6800000      /* 8bit LED */
+#define PA_FPGA         0xB7000000      /* FPGA base address */
+
+#define MRSHPC_IRQ0     10
+
+#define FPGA_ILSR1      (PA_FPGA + 0x02)
+#define FPGA_ILSR2      (PA_FPGA + 0x03)
+#define FPGA_ILSR3      (PA_FPGA + 0x04)
+#define FPGA_ILSR4      (PA_FPGA + 0x05)
+#define FPGA_ILSR5      (PA_FPGA + 0x06)
+#define FPGA_ILSR6      (PA_FPGA + 0x07)
+#define FPGA_ILSR7      (PA_FPGA + 0x08)
+#define FPGA_ILSR8      (PA_FPGA + 0x09)
+
+void init_se7721_IRQ(void);
+
+#define __IO_PREFIX             se7721
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7721_H */
diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h
new file mode 100644
index 000000000000..e971d9a82f4a
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7722.h
@@ -0,0 +1,112 @@
+#ifndef __ASM_SH_SE7722_H
+#define __ASM_SH_SE7722_H
+
+/*
+ * linux/include/asm-sh/se7722.h
+ *
+ * Copyright (C) 2007  Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7722 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00200000      /* EPROM size 2M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM        0xaC000000      /* DDR-SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+
+#define PA_PERIPHERAL   0xB0000000
+
+#define PA_PCIC         PA_PERIPHERAL                   /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)    /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)    /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)    /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)    /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define PA_LED          (PA_PERIPHERAL + 0x00800000)    /* 8bit LED */
+#define PA_FPGA         (PA_PERIPHERAL + 0x01800000)    /* FPGA base address */
+
+#define PA_LAN          (PA_AREA6_IO + 0)               /* SMC LAN91C111 */
+/* GPIO */
+#define FPGA_IN         0xb1840000UL
+#define FPGA_OUT        0xb1840004UL
+
+#define PORT_PECR       0xA4050108UL
+#define PORT_PJCR       0xA4050110UL
+#define PORT_PSELD      0xA4050154UL
+#define PORT_PSELB      0xA4050150UL
+
+#define PORT_PSELC      0xA4050152UL
+#define PORT_PKCR       0xA4050112UL
+#define PORT_PHCR       0xA405010EUL
+#define PORT_PLCR       0xA4050114UL
+#define PORT_PMCR       0xA4050116UL
+#define PORT_PRCR       0xA405011CUL
+#define PORT_PXCR       0xA4050148UL
+#define PORT_PSELA      0xA405014EUL
+#define PORT_PYCR       0xA405014AUL
+#define PORT_PZCR       0xA405014CUL
+#define PORT_HIZCRA     0xA4050158UL
+#define PORT_HIZCRC     0xA405015CUL
+
+/* IRQ */
+#define IRQ0_IRQ        32
+#define IRQ1_IRQ        33
+
+#define IRQ01_MODE      0xb1800000
+#define IRQ01_STS       0xb1800004
+#define IRQ01_MASK      0xb1800008
+
+/* Bits in IRQ01_* registers */
+
+#define SE7722_FPGA_IRQ_USB     0 /* IRQ0 */
+#define SE7722_FPGA_IRQ_SMC     1 /* IRQ0 */
+#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
+#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
+
+#define SE7722_FPGA_IRQ_NR      6
+#define SE7722_FPGA_IRQ_BASE    110
+
+#define MRSHPC_IRQ3     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3)
+#define MRSHPC_IRQ2     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2)
+#define MRSHPC_IRQ1     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1)
+#define MRSHPC_IRQ0     (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0)
+#define SMC_IRQ         (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC)
+#define USB_IRQ         (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB)
+
+/* arch/sh/boards/se/7722/irq.c */
+void init_se7722_IRQ(void);
+
+#define __IO_PREFIX             se7722
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7722_H */
diff --git a/arch/sh/include/mach-se/mach/se7751.h b/arch/sh/include/mach-se/mach/se7751.h
new file mode 100644
index 000000000000..b36792ac5d66
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7751.h
@@ -0,0 +1,73 @@
+#ifndef __ASM_SH_HITACHI_7751SE_H
+#define __ASM_SH_HITACHI_7751SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_7751se.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+
+ * Modified for 7751 Solution Engine by
+ * Ian da Silva and Jeremy Siegel, 2001.
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM          0x00000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0x01000000      /* EPROM */
+#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
+#define PA_EXT1         0x04000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_EXT2         0x08000000
+#define PA_EXT2_SIZE    0x04000000
+#define PA_SDRAM        0x0c000000
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0x12000000
+#define PA_EXT4_SIZE    0x02000000
+#define PA_EXT5         0x14000000
+#define PA_EXT5_SIZE    0x04000000
+#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
+
+#define PA_DIPSW0       0xb9000000      /* Dip switch 5,6 */
+#define PA_DIPSW1       0xb9000002      /* Dip switch 7,8 */
+#define PA_LED          0xba000000      /* LED */
+#define PA_BCR          0xbb000000      /* FPGA on the MS7751SE01 */
+
+#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
+#define MRSHPC_MODE     (PA_MRSHPC + 4)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define BCR_ILCRA       (PA_BCR + 0)
+#define BCR_ILCRB       (PA_BCR + 2)
+#define BCR_ILCRC       (PA_BCR + 4)
+#define BCR_ILCRD       (PA_BCR + 6)
+#define BCR_ILCRE       (PA_BCR + 8)
+#define BCR_ILCRF       (PA_BCR + 10)
+#define BCR_ILCRG       (PA_BCR + 12)
+
+#define IRQ_79C973      13
+
+void init_7751se_IRQ(void);
+
+#define __IO_PREFIX     sh7751se
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_HITACHI_7751SE_H */
diff --git a/arch/sh/include/mach-se/mach/se7780.h b/arch/sh/include/mach-se/mach/se7780.h
new file mode 100644
index 000000000000..40e9b41458cd
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7780.h
@@ -0,0 +1,108 @@
+#ifndef __ASM_SH_SE7780_H
+#define __ASM_SH_SE7780_H
+
+/*
+ * linux/include/asm-sh/se7780.h
+ *
+ * Copyright (C) 2006,2007  Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7780 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SM501        PA_EXT1         /* Graphic IC (SM501) */
+#define PA_SM501_SIZE   PA_EXT1_SIZE    /* Graphic IC (SM501) */
+#define PA_SDRAM        0xa8000000      /* DDR-SDRAM(Area2/3) 128MB */
+#define PA_SDRAM_SIZE   0x08000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+#define PA_EXT_FLASH    PA_EXT4         /* Expansion Flash-ROM */
+
+#define PA_PERIPHERAL   PA_AREA6_IO     /* SW6-6=ON */
+
+#define PA_LAN          (PA_PERIPHERAL + 0)             /* SMC LAN91C111 */
+#define PA_LED_DISP     (PA_PERIPHERAL + 0x02000000)    /* 8words LED Display */
+#define DISP_CHAR_RAM   (7 << 3)
+#define DISP_SEL0_ADDR  (DISP_CHAR_RAM + 0)
+#define DISP_SEL1_ADDR  (DISP_CHAR_RAM + 1)
+#define DISP_SEL2_ADDR  (DISP_CHAR_RAM + 2)
+#define DISP_SEL3_ADDR  (DISP_CHAR_RAM + 3)
+#define DISP_SEL4_ADDR  (DISP_CHAR_RAM + 4)
+#define DISP_SEL5_ADDR  (DISP_CHAR_RAM + 5)
+#define DISP_SEL6_ADDR  (DISP_CHAR_RAM + 6)
+#define DISP_SEL7_ADDR  (DISP_CHAR_RAM + 7)
+
+#define DISP_UDC_RAM    (5 << 3)
+#define PA_FPGA         (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
+
+/* FPGA register address and bit */
+#define FPGA_SFTRST             (PA_FPGA + 0)   /* Soft reset register */
+#define FPGA_INTMSK1            (PA_FPGA + 2)   /* Interrupt Mask register 1 */
+#define FPGA_INTMSK2            (PA_FPGA + 4)   /* Interrupt Mask register 2 */
+#define FPGA_INTSEL1            (PA_FPGA + 6)   /* Interrupt select register 1 */
+#define FPGA_INTSEL2            (PA_FPGA + 8)   /* Interrupt select register 2 */
+#define FPGA_INTSEL3            (PA_FPGA + 10)  /* Interrupt select register 3 */
+#define FPGA_PCI_INTSEL1        (PA_FPGA + 12)  /* PCI Interrupt select register 1 */
+#define FPGA_PCI_INTSEL2        (PA_FPGA + 14)  /* PCI Interrupt select register 2 */
+#define FPGA_INTSET             (PA_FPGA + 16)  /* IRQ/IRL select register */
+#define FPGA_INTSTS1            (PA_FPGA + 18)  /* Interrupt status register 1 */
+#define FPGA_INTSTS2            (PA_FPGA + 20)  /* Interrupt status register 2 */
+#define FPGA_REQSEL             (PA_FPGA + 22)  /* REQ/GNT select register */
+#define FPGA_DBG_LED            (PA_FPGA + 32)  /* Debug LED(D-LED[8:1] */
+#define PA_LED                  FPGA_DBG_LED
+#define FPGA_IVDRID             (PA_FPGA + 36)  /* iVDR ID Register */
+#define FPGA_IVDRPW             (PA_FPGA + 38)  /* iVDR Power ON Register */
+#define FPGA_MMCID              (PA_FPGA + 40)  /* MMC ID Register */
+
+/* FPGA INTSEL position */
+/* INTSEL1 */
+#define IRQPOS_SMC91CX          (0 * 4)
+#define IRQPOS_SM501            (1 * 4)
+/* INTSEL2 */
+#define IRQPOS_EXTINT1          (0 * 4)
+#define IRQPOS_EXTINT2          (1 * 4)
+#define IRQPOS_EXTINT3          (2 * 4)
+#define IRQPOS_EXTINT4          (3 * 4)
+/* INTSEL3 */
+#define IRQPOS_PCCPW            (0 * 4)
+
+/* IDE interrupt */
+#define IRQ_IDE0                67 /* iVDR */
+
+/* SMC interrupt */
+#define SMC_IRQ                 8
+
+/* SM501 interrupt */
+#define SM501_IRQ               0
+
+/* interrupt pin */
+#define IRQPIN_EXTINT1          0 /* IRQ0 pin */
+#define IRQPIN_EXTINT2          1 /* IRQ1 pin */
+#define IRQPIN_EXTINT3          2 /* IRQ2 pin */
+#define IRQPIN_SMC91CX          3 /* IRQ3 pin */
+#define IRQPIN_EXTINT4          4 /* IRQ4 pin */
+#define IRQPIN_PCC0             5 /* IRQ5 pin */
+#define IRQPIN_PCC2             6 /* IRQ6 pin */
+#define IRQPIN_SM501            7 /* IRQ7 pin */
+#define IRQPIN_PCCPW            7 /* IRQ7 pin */
+
+/* arch/sh/boards/se/7780/irq.c */
+void init_se7780_IRQ(void);
+
+#define __IO_PREFIX             se7780
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7780_H */
diff --git a/arch/sh/include/mach-sh03/mach/io.h b/arch/sh/include/mach-sh03/mach/io.h
new file mode 100644
index 000000000000..c39c785bba94
--- /dev/null
+++ b/arch/sh/include/mach-sh03/mach/io.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/sh03/io.h
+ *
+ * Copyright 2004 Interface Co.,Ltd. Saito.K
+ *
+ * IO functions for an Interface CTP/PCI-SH03
+ */
+
+#ifndef _ASM_SH_IO_SH03_H
+#define _ASM_SH_IO_SH03_H
+
+#include <linux/time.h>
+
+#define IRL0_IRQ        2
+#define IRL0_PRIORITY   13
+#define IRL1_IRQ        5
+#define IRL1_PRIORITY   10
+#define IRL2_IRQ        8
+#define IRL2_PRIORITY   7
+#define IRL3_IRQ        11
+#define IRL3_PRIORITY   4
+
+void heartbeat_sh03(void);
+
+#endif /* _ASM_SH_IO_SH03_H */
diff --git a/arch/sh/include/mach-sh03/mach/sh03.h b/arch/sh/include/mach-sh03/mach/sh03.h
new file mode 100644
index 000000000000..19c40b80428d
--- /dev/null
+++ b/arch/sh/include/mach-sh03/mach/sh03.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_SH_SH03_H
+#define __ASM_SH_SH03_H
+
+/*
+ * linux/include/asm-sh/sh03/sh03.h
+ *
+ * Copyright (C) 2004  Interface Co., Ltd. Saito.K
+ *
+ * Interface CTP/PCI-SH03 support
+ */
+
+#define PA_PCI_IO       (0xbe240000)    /* PCI I/O space */
+#define PA_PCI_MEM      (0xbd000000)    /* PCI MEM space */
+
+#define PCIPAR          (0xa4000cf8)    /* PCI Config address */
+#define PCIPDR          (0xa4000cfc)    /* PCI Config data    */
+
+#endif  /* __ASM_SH_SH03_H */
diff --git a/arch/sh/kernel/.gitignore b/arch/sh/kernel/.gitignore
new file mode 100644
index 000000000000..c5f676c3c224
--- /dev/null
+++ b/arch/sh/kernel/.gitignore
@@ -0,0 +1 @@
+vmlinux.lds
diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32
index 4bbdce36b92b..0e6905fe9fec 100644
--- a/arch/sh/kernel/Makefile_32
+++ b/arch/sh/kernel/Makefile_32
@@ -21,7 +21,7 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
-obj-$(CONFIG_BINFMT_ELF)        += dump_task.o
+obj-$(CONFIG_ELF_CORE)          += dump_task.o
 obj-$(CONFIG_IO_TRAPPED)        += io_trapped.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c
index 01ff4d05aab0..bea40339919b 100644
--- a/arch/sh/kernel/cf-enabler.c
+++ b/arch/sh/kernel/cf-enabler.c
@@ -80,11 +80,11 @@ static int __init cf_init_default(void)
 }
 
 #if defined(CONFIG_SH_SOLUTION_ENGINE)
-#include <asm/se.h>
+#include <mach-se/mach/se.h>
 #elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
-#include <asm/se7722.h>
+#include <mach-se/mach/se7722.h>
 #elif defined(CONFIG_SH_7721_SOLUTION_ENGINE)
-#include <asm/se7721.h>
+#include <mach-se/mach/se7721.h>
 #endif
 
 /*
@@ -157,7 +157,7 @@ static int __init cf_init_se(void)
 }
 #endif
 
-int __init cf_init(void)
+static int __init cf_init(void)
 {
         if (mach_is_se() || mach_is_7722se() || mach_is_7721se())
                 return cf_init_se();
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index b5f1e23ed57c..f5eb56e6bc59 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -88,7 +88,7 @@ static void propagate_rate(struct clk *clk)
         }
 }
 
-int __clk_enable(struct clk *clk)
+static int __clk_enable(struct clk *clk)
 {
         /*
          * See if this is the first time we're enabling the clock, some
@@ -111,7 +111,6 @@ int __clk_enable(struct clk *clk)
 
         return 0;
 }
-EXPORT_SYMBOL_GPL(__clk_enable);
 
 int clk_enable(struct clk *clk)
 {
@@ -131,7 +130,7 @@ static void clk_kref_release(struct kref *kref)
         /* Nothing to do */
 }
 
-void __clk_disable(struct clk *clk)
+static void __clk_disable(struct clk *clk)
 {
         int count = kref_put(&clk->kref, clk_kref_release);
 
@@ -143,7 +142,6 @@ void __clk_disable(struct clk *clk)
                         clk->ops->disable(clk);
         }
 }
-EXPORT_SYMBOL_GPL(__clk_disable);
 
 void clk_disable(struct clk *clk)
 {
@@ -310,15 +308,11 @@ static int show_clocks(char *buf, char **start, off_t off,
         list_for_each_entry_reverse(clk, &clock_list, node) {
                 unsigned long rate = clk_get_rate(clk);
 
-                /*
-                 * Don't bother listing dummy clocks with no ancestry
-                 * that only support enable and disable ops.
-                 */
-                if (unlikely(!rate && !clk->parent))
-                        continue;
-
-                p += sprintf(p, "%-12s\t: %ld.%02ldMHz\n", clk->name,
-                             rate / 1000000, (rate % 1000000) / 10000);
+                p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name,
+                             rate / 1000000, (rate % 1000000) / 10000,
+                             ((clk->flags & CLK_ALWAYS_ENABLED) ||
+                              (atomic_read(&clk->kref.refcount) != 1)) ?
+                             "enabled" : "disabled");
         }
 
         return p - buf;
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 79baa47af977..726f0335da76 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -20,7 +20,7 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/bitops.h>
-#include <asm/cpu/irq.h>
+#include <cpu/irq.h>
 #include <asm/page.h>
 
 /*
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
index da5dae787888..8c70e201bde0 100644
--- a/arch/sh/kernel/cpu/irq/intc.c
+++ b/arch/sh/kernel/cpu/irq/intc.c
@@ -62,7 +62,7 @@ struct intc_desc_int {
 #endif
 
 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
 static unsigned long ack_handle[NR_IRQS];
 #endif
 
@@ -231,7 +231,7 @@ static void intc_disable(unsigned int irq)
         }
 }
 
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
 static void intc_mask_ack(unsigned int irq)
 {
         struct intc_desc_int *d = get_intc_desc(irq);
@@ -244,8 +244,23 @@ static void intc_mask_ack(unsigned int irq)
 
         if (handle) {
                 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
-                ctrl_inb(addr);
-                ctrl_outb(0x3f ^ set_field(0, 1, handle), addr);
+                switch (_INTC_FN(handle)) {
+                case REG_FN_MODIFY_BASE + 0:    /* 8bit */
+                        ctrl_inb(addr);
+                        ctrl_outb(0xff ^ set_field(0, 1, handle), addr);
+                        break;
+                case REG_FN_MODIFY_BASE + 1:    /* 16bit */
+                        ctrl_inw(addr);
+                        ctrl_outw(0xffff ^ set_field(0, 1, handle), addr);
+                        break;
+                case REG_FN_MODIFY_BASE + 3:    /* 32bit */
+                        ctrl_inl(addr);
+                        ctrl_outl(0xffffffff ^ set_field(0, 1, handle), addr);
+                        break;
+                default:
+                        BUG();
+                        break;
+                }
         }
 }
 #endif
@@ -466,7 +481,7 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc,
         return 0;
 }
 
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
 static unsigned int __init intc_ack_data(struct intc_desc *desc,
                                           struct intc_desc_int *d,
                                           intc_enum enum_id)
@@ -601,7 +616,7 @@ static void __init intc_register_irq(struct intc_desc *desc,
         /* irq should be disabled by default */
         d->chip.mask(irq);
 
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
         if (desc->ack_regs)
                 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
 #endif
@@ -635,7 +650,7 @@ void __init register_intc_controller(struct intc_desc *desc)
         d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
         d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
 
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
         d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
 #endif
         d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
@@ -676,7 +691,7 @@ void __init register_intc_controller(struct intc_desc *desc)
         d->chip.mask_ack = intc_disable;
         d->chip.set_type = intc_set_sense;
 
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
         if (desc->ack_regs) {
                 for (i = 0; i < desc->nr_ack_regs; i++)
                         k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S
index 0fc89069d8c7..becc54c45692 100644
--- a/arch/sh/kernel/cpu/sh2/entry.S
+++ b/arch/sh/kernel/cpu/sh2/entry.S
@@ -3,7 +3,7 @@
  *
  * The SH-2 exception entry
  *
- * Copyright (C) 2005,2006 Yoshinori Sato
+ * Copyright (C) 2005-2008 Yoshinori Sato
  * Copyright (C) 2005  AXE,Inc.
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -14,7 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
-#include <asm/cpu/mmu_context.h>
+#include <cpu/mmu_context.h>
 #include <asm/unistd.h>
 #include <asm/errno.h>
 #include <asm/page.h>
@@ -36,43 +36,41 @@ OFF_TRA	=  (16*4+6*4)
 #include <asm/entry-macros.S>
 
 ENTRY(exception_handler)
-        ! already saved r0/r1
+        ! stack
+        ! r0 <- point sp
+        ! r1
+        ! pc
+        ! sr
+        ! r0 = temporary
+        ! r1 = vector (pseudo EXPEVT / INTEVT / TRA)
         mov.l   r2,@-sp
         mov.l   r3,@-sp
-        mov     r0,r1
         cli
         mov.l   $cpu_mode,r2
         mov.l   @r2,r0
         mov.l   @(5*4,r15),r3   ! previous SR
-        shll2   r3              ! set "S" flag
-        rotl    r0              ! T <- "S" flag
-        rotl    r0              ! "S" flag is LSB
-        rotcr   r3              ! T -> r3:b30
-        shlr    r3
-        shlr    r0
-        bt/s    1f
-         mov.l  r3,@(5*4,r15)   ! copy cpu mode to SR
+        or      r0,r3           ! set MD
+        tst     r0,r0
+        bf/s    1f              ! previous mode check
+         mov.l  r3,@(5*4,r15)   ! update SR
         ! switch to kernel mode
-        mov     #1,r0
-        rotr    r0
-        rotr    r0
+        mov.l   __md_bit,r0
         mov.l   r0,@r2          ! enter kernel mode
         mov.l   $current_thread_info,r2
         mov.l   @r2,r2
-        mov     #0x20,r0
+        mov     #(THREAD_SIZE >> 8),r0
         shll8   r0
         add     r2,r0
         mov     r15,r2          ! r2 = user stack top
         mov     r0,r15          ! switch kernel stack
-        add     #-4,r15         ! dummy
         mov.l   r1,@-r15        ! TRA
         sts.l   macl, @-r15
         sts.l   mach, @-r15
         stc.l   gbr, @-r15
-        mov.l   @(4*4,r2),r0
-        mov.l   @(5*4,r2),r1
-        mov.l   r1,@-r15        ! original SR
+        mov.l   @(5*4,r2),r0
+        mov.l   r0,@-r15        ! original SR
         sts.l   pr,@-r15
+        mov.l   @(4*4,r2),r0
         mov.l   r0,@-r15        ! original PC
         mov     r2,r3
         add     #(4+2)*4,r3     ! rewind r0 - r3 + exception frame
@@ -88,14 +86,15 @@ ENTRY(exception_handler)
         mov.l   r6,@-r15
         mov.l   r5,@-r15
         mov.l   r4,@-r15
+        mov     r1,r9           ! save TRA
         mov     r2,r8           ! copy user -> kernel stack
-        mov.l   @r8+,r3
+        mov.l   @(0,r8),r3
         mov.l   r3,@-r15
-        mov.l   @r8+,r2
+        mov.l   @(4,r8),r2
         mov.l   r2,@-r15
-        mov.l   @r8+,r1
+        mov.l   @(12,r8),r1
         mov.l   r1,@-r15
-        mov.l   @r8+,r0
+        mov.l   @(8,r8),r0
         bra     2f
          mov.l  r0,@-r15
 1:
@@ -107,10 +106,11 @@ ENTRY(exception_handler)
         mov.l   r0,@-r15        
         mov.l   @r2+,r0         ! old R2
         mov.l   r0,@-r15        
-        mov.l   @r2+,r0         ! old R1
-        mov.l   r0,@-r15        
-        mov.l   @r2+,r0         ! old R0
+        mov.l   @(4,r2),r0      ! old R1
         mov.l   r0,@-r15        
+        mov.l   @r2,r0          ! old R0
+        mov.l   r0,@-r15
+        add     #8,r2
         mov.l   @r2+,r3         ! old PC
         mov.l   @r2+,r0         ! old SR
         add     #-4,r2          ! exception frame stub (sr)
@@ -135,14 +135,12 @@ ENTRY(exception_handler)
         mov.l   r6,@-r2
         mov.l   r5,@-r2
         mov.l   r4,@-r2
+        mov     r1,r9
         mov.l   @(OFF_R0,r15),r0
         mov.l   @(OFF_R1,r15),r1
         mov.l   @(OFF_R2,r15),r2
         mov.l   @(OFF_R3,r15),r3
 2:
-        mov     #OFF_TRA,r8
-        add     r15,r8
-        mov.l   @r8,r9  
         mov     #64,r8
         cmp/hs  r8,r9
         bt      interrupt_entry ! vec >= 64 is interrupt
@@ -150,26 +148,14 @@ ENTRY(exception_handler)
         cmp/hs  r8,r9
         bt      trap_entry      ! 64 > vec >= 32  is trap
 
-#if defined(CONFIG_SH_FPU)
-        mov     #13,r8
-        cmp/eq  r8,r9
-        bt      10f             ! fpu
-        nop
-#endif
-
         mov.l   4f,r8
         mov     r9,r4
         shll2   r9
         add     r9,r8
-        mov.l   @r8,r8
-        mov     #0,r9
-        cmp/eq  r9,r8
+        mov.l   @r8,r8          ! exception handler address
+        tst     r8,r8
         bf      3f
         mov.l   8f,r8           ! unhandled exception
-#if defined(CONFIG_SH_FPU)
-10:
-        mov.l   9f, r8          ! unhandled exception
-#endif
 3:
         mov.l   5f,r10
         jmp     @r8
@@ -188,10 +174,7 @@ interrupt_entry:
 5:      .long   ret_from_exception
 6:      .long   ret_from_irq
 7:      .long   do_IRQ
-8:      .long   do_exception_error
-#ifdef CONFIG_SH_FPU
-9:      .long   fpu_error_trap_handler
-#endif
+8:      .long   exception_error
 
 trap_entry:
         mov     #0x30,r8
@@ -200,24 +183,9 @@ trap_entry:
         add     #-0x10,r9       ! convert SH2 to SH3/4 ABI
 1:      
         shll2   r9                      ! TRA
-        mov     #OFF_TRA,r8
-        add     r15,r8
-        mov.l   r9,@r8
-        mov     r9,r8
-#ifdef CONFIG_TRACE_IRQFLAGS
-        mov.l   2f, r9
-        jsr     @r9
-         nop
-#endif
-        sti
-        bra     system_call
-         nop
+        bra     system_call     ! jump common systemcall entry
+         mov    r9,r8
         
-        .align  2
-#ifdef CONFIG_TRACE_IRQFLAGS
-2:      .long   trace_hardirqs_on
-#endif
-
 #if defined(CONFIG_SH_STANDARD_BIOS)
         /* Unwind the stack and jmp to the debug entry */
 ENTRY(sh_bios_handler)
@@ -240,7 +208,7 @@ ENTRY(sh_bios_handler)
         mov.l   @r2,r2
         stc     sr,r3
         mov.l   r2,@r0
-        mov.l   r3,@r0
+        mov.l   r3,@(4,r0)
         mov.l   r1,@(8,r0)      
         mov.l   @r15+, r0
         mov.l   @r15+, r1
@@ -272,22 +240,30 @@ ENTRY(address_error_trap_handler)
         mov.l   1f,r0
         jmp     @r0
          mov    #0,r5                           ! writeaccess is unknown
-        .align  2
 
+        .align  2
 1:      .long   do_address_error
 
 restore_all:
-        cli
-#ifdef CONFIG_TRACE_IRQFLAGS
-        mov.l   1f, r0
-        jsr     @r0
-         nop
-#endif
+        stc     sr,r0
+        or      #0xf0,r0
+        ldc     r0,sr                           ! all interrupt block (same BL = 1)
+        ! restore special register
+        ! overlap exception frame
+        mov     r15,r0
+        add     #17*4,r0
+        lds.l   @r0+,pr
+        add     #4,r0
+        ldc.l   @r0+,gbr
+        lds.l   @r0+,mach
+        lds.l   @r0+,macl
         mov     r15,r0
         mov.l   $cpu_mode,r2
         mov     #OFF_SR,r3
         mov.l   @(r0,r3),r1
-        mov.l   r1,@r2
+        mov.l   __md_bit,r3
+        and     r1,r3                           ! copy MD bit
+        mov.l   r3,@r2
         shll2   r1                              ! clear MD bit
         shlr2   r1
         mov.l   @(OFF_SP,r0),r2
@@ -297,12 +273,6 @@ restore_all:
         mov     #OFF_PC,r3
         mov.l   @(r0,r3),r1
         mov.l   r1,@r2                          ! set pc
-        add     #4*16+4,r0
-        lds.l   @r0+,pr
-        add     #4,r0                           ! skip sr
-        ldc.l   @r0+,gbr
-        lds.l   @r0+,mach
-        lds.l   @r0+,macl
         get_current_thread_info r0, r1
         mov.l   $current_thread_info,r1
         mov.l   r0,@r1
@@ -326,9 +296,8 @@ restore_all:
          nop
 
         .align 2
-#ifdef CONFIG_TRACE_IRQFLAGS
-1:     .long   trace_hardirqs_off
-#endif
+__md_bit:
+        .long   0x40000000
 $current_thread_info:
         .long   __current_thread_info
 $cpu_mode:      
diff --git a/arch/sh/kernel/cpu/sh2/ex.S b/arch/sh/kernel/cpu/sh2/ex.S
index 6d285af7846c..85b0bf81fc1d 100644
--- a/arch/sh/kernel/cpu/sh2/ex.S
+++ b/arch/sh/kernel/cpu/sh2/ex.S
@@ -18,16 +18,17 @@
 exception_entry:        
 no      =       0
         .rept   256
-        mov.l   r0,@-sp
-        mov     #no,r0
+        mov.l   r1,@-sp
         bra     exception_trampoline
-        and     #0xff,r0
+        mov     #no,r1
 no      =       no + 1
         .endr
 exception_trampoline:
-        mov.l   r1,@-sp
-        mov.l   $exception_handler,r1
-        jmp     @r1
+        mov.l   r0,@-sp
+        mov.l   $exception_handler,r0
+        extu.b  r1,r1
+        jmp     @r0
+          extu.w        r1,r1
 
         .align  2
 $exception_entry:
@@ -41,6 +42,6 @@ $exception_handler:
 ENTRY(vbr_base)
 vector  =       0
         .rept   256
-        .long   exception_entry + vector * 8
+        .long   exception_entry + vector * 6
 vector  =       vector + 1
         .endr
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index cc530f4d84d6..56e5878e5516 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -96,8 +96,32 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct resource eth_resources[] = {
+        [0] = {
+                .start = 0xfb000000,
+                .end =   0xfb0001c8,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = 85,
+                .end = 85,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device eth_device = {
+        .name = "sh-eth",
+        .id     = -1,
+        .dev = {
+                .platform_data = (void *)1,
+        },
+        .num_resources = ARRAY_SIZE(eth_resources),
+        .resource = eth_resources,
+};
+
 static struct platform_device *sh7619_devices[] __initdata = {
         &sci_device,
+        &eth_device,
 };
 
 static int __init sh7619_devices_setup(void)
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index 7e2b90cfa7bf..1ab1ecf4c768 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -4,7 +4,7 @@
 
 obj-y   := common.o probe.o opcode_helper.o
 
-common-y        += $(addprefix ../sh2/, ex.o entry.o)
+common-y        += ex.o entry.o
 
 obj-$(CONFIG_SH_FPU)    += fpu.o
 
diff --git a/arch/sh/kernel/cpu/sh2a/entry.S b/arch/sh/kernel/cpu/sh2a/entry.S
new file mode 100644
index 000000000000..ab3903eeda5c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/entry.S
@@ -0,0 +1,249 @@
+/*
+ * arch/sh/kernel/cpu/sh2a/entry.S
+ *
+ * The SH-2A exception entry
+ *
+ * Copyright (C) 2008 Yoshinori Sato
+ * Based on arch/sh/kernel/cpu/sh2/entry.S
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <cpu/mmu_context.h>
+#include <asm/unistd.h>
+#include <asm/errno.h>
+#include <asm/page.h>
+        
+/* Offsets to the stack */
+OFF_R0  =  0            /* Return value. New ABI also arg4 */
+OFF_R1  =  4            /* New ABI: arg5 */
+OFF_R2  =  8            /* New ABI: arg6 */
+OFF_R3  =  12           /* New ABI: syscall_nr */
+OFF_R4  =  16           /* New ABI: arg0 */
+OFF_R5  =  20           /* New ABI: arg1 */
+OFF_R6  =  24           /* New ABI: arg2 */
+OFF_R7  =  28           /* New ABI: arg3 */
+OFF_SP  =  (15*4)
+OFF_PC  =  (16*4)
+OFF_SR  =  (16*4+2*4)
+OFF_TRA =  (16*4+6*4)
+
+#include <asm/entry-macros.S>
+
+ENTRY(exception_handler)
+        ! stack
+        ! r0 <- point sp
+        ! r1
+        ! pc
+        ! sr
+        ! r0 = temporary
+        ! r1 = vector (pseudo EXPEVT / INTEVT / TRA)
+        mov.l   r2,@-sp
+        cli
+        mov.l   $cpu_mode,r2
+        bld.b   #6,@(0,r2)      !previus SR.MD
+        bst.b   #6,@(4*4,r15)   !set cpu mode to SR.MD
+        bt      1f
+        ! switch to kernel mode
+        bset.b  #6,@(0,r2)      !set SR.MD
+        mov.l   $current_thread_info,r2
+        mov.l   @r2,r2
+        mov     #(THREAD_SIZE >> 8),r0
+        shll8   r0
+        add     r2,r0           ! r0 = kernel stack tail
+        mov     r15,r2          ! r2 = user stack top
+        mov     r0,r15          ! switch kernel stack
+        mov.l   r1,@-r15        ! TRA
+        sts.l   macl, @-r15
+        sts.l   mach, @-r15
+        stc.l   gbr, @-r15
+        mov.l   @(4*4,r2),r0
+        mov.l   r0,@-r15        ! original SR
+        sts.l   pr,@-r15
+        mov.l   @(3*4,r2),r0
+        mov.l   r0,@-r15        ! original PC
+        mov     r2,r0
+        add     #(3+2)*4,r0     ! rewind r0 - r3 + exception frame
+        lds     r0,pr           ! pr = original SP
+        movmu.l r3,@-r15        ! save regs
+        mov     r2,r8           ! r8 =  previus stack top
+        mov     r1,r9           ! r9 = interrupt vector
+        ! restore previous stack
+        mov.l   @r8+,r2
+        mov.l   @r8+,r0
+        mov.l   @r8+,r1
+        bra     2f
+         movml.l r2,@-r15
+1:
+        ! in kernel exception
+        mov     r15,r2
+        add     #-((OFF_TRA + 4) - OFF_PC) + 5*4,r15
+        movmu.l r3,@-r15
+        mov     r2,r8           ! r8 = previous stack top
+        mov     r1,r9           ! r9 = interrupt vector
+        ! restore exception frame & regs
+        mov.l   @r8+,r2         ! old R2
+        mov.l   @r8+,r0         ! old R0
+        mov.l   @r8+,r1         ! old R1
+        mov.l   @r8+,r10        ! old PC
+        mov.l   @r8+,r11        ! old SR
+        movml.l r2,@-r15
+        mov.l   r10,@(OFF_PC,r15)
+        mov.l   r11,@(OFF_SR,r15)
+        mov.l   r8,@(OFF_SP,r15)        ! save old sp
+        mov     r15,r8
+        add     #OFF_TRA + 4,r8
+        mov.l   r9,@-r8
+        sts.l   macl,@-r8
+        sts.l   mach,@-r8
+        stc.l   gbr,@-r8
+        add     #-4,r8
+        sts.l   pr,@-r8
+2:
+        ! dispatch exception / interrupt
+        mov     #64,r8
+        cmp/hs  r8,r9
+        bt      interrupt_entry ! vec >= 64 is interrupt
+        mov     #32,r8
+        cmp/hs  r8,r9
+        bt      trap_entry      ! 64 > vec >= 32  is trap
+
+        mov.l   4f,r8
+        mov     r9,r4
+        shll2   r9
+        add     r9,r8
+        mov.l   @r8,r8          ! exception handler address
+        tst     r8,r8
+        bf      3f
+        mov.l   8f,r8           ! unhandled exception
+3:
+        mov.l   5f,r10
+        jmp     @r8
+         lds    r10,pr
+
+interrupt_entry:
+        mov     r9,r4
+        mov     r15,r5
+        mov.l   7f,r8
+        mov.l   6f,r9
+        jmp     @r8
+         lds    r9,pr
+
+        .align  2
+4:      .long   exception_handling_table
+5:      .long   ret_from_exception
+6:      .long   ret_from_irq
+7:      .long   do_IRQ
+8:      .long   exception_error
+
+trap_entry:
+        mov     #0x30,r8
+        cmp/ge  r8,r9           ! vector 0x20-0x2f is systemcall
+        bt      1f
+        add     #-0x10,r9       ! convert SH2 to SH3/4 ABI
+1:      
+        shll2   r9                      ! TRA
+        bra     system_call     ! jump common systemcall entry
+         mov    r9,r8
+        
+#if defined(CONFIG_SH_STANDARD_BIOS)
+        /* Unwind the stack and jmp to the debug entry */
+ENTRY(sh_bios_handler)
+        mov     r15,r0
+        add     #(22-4)*4-4,r0
+        ldc.l   @r0+,gbr
+        lds.l   @r0+,mach
+        lds.l   @r0+,macl
+        mov     r15,r0
+        mov.l   @(OFF_SP,r0),r1
+        mov.l   @(OFF_SR,r2),r3
+        mov.l   r3,@-r1
+        mov.l   @(OFF_SP,r2),r3
+        mov.l   r3,@-r1
+        mov     r15,r0
+        add     #(22-4)*4-8,r0
+        mov.l   1f,r2
+        mov.l   @r2,r2
+        stc     sr,r3
+        mov.l   r2,@r0
+        mov.l   r3,@(4,r0)
+        mov.l   r1,@(8,r0)
+        movml.l @r15+,r14
+        add     #8,r15
+        lds.l   @r15+, pr
+        rte
+         mov.l  @r15+,r15
+        .align  2
+1:      .long   gdb_vbr_vector
+#endif /* CONFIG_SH_STANDARD_BIOS */
+
+ENTRY(address_error_trap_handler)
+        mov     r15,r4                          ! regs
+        mov.l   @(OFF_PC,r15),r6                ! pc
+        mov.l   1f,r0
+        jmp     @r0
+         mov    #0,r5                           ! writeaccess is unknown
+
+        .align  2
+1:      .long   do_address_error
+
+restore_all:
+        stc     sr,r0
+        or      #0xf0,r0
+        ldc     r0,sr                           ! all interrupt block (same BL = 1)
+        ! restore special register
+        ! overlap exception frame
+        mov     r15,r0
+        add     #17*4,r0
+        lds.l   @r0+,pr
+        add     #4,r0
+        ldc.l   @r0+,gbr
+        lds.l   @r0+,mach
+        lds.l   @r0+,macl
+        mov     r15,r0
+        mov.l   $cpu_mode,r2
+        bld.b   #6,@(OFF_SR,r15)
+        bst.b   #6,@(0,r2)                      ! save CPU mode
+        mov.l   @(OFF_SR,r0),r1
+        shll2   r1
+        shlr2   r1                              ! clear MD bit
+        mov.l   @(OFF_SP,r0),r2
+        add     #-8,r2
+        mov.l   r2,@(OFF_SP,r0)                 ! point exception frame top
+        mov.l   r1,@(4,r2)                      ! set sr
+        mov.l   @(OFF_PC,r0),r1
+        mov.l   r1,@r2                          ! set pc
+        get_current_thread_info r0, r1
+        mov.l   $current_thread_info,r1
+        mov.l   r0,@r1
+        movml.l @r15+,r14
+        mov.l   @r15,r15
+        rte
+         nop
+
+        .align 2
+$current_thread_info:
+        .long   __current_thread_info
+$cpu_mode:      
+        .long   __cpu_mode
+                
+! common exception handler
+#include "../../entry-common.S"
+        
+        .data
+! cpu operation mode 
+! bit30 = MD (compatible SH3/4)
+__cpu_mode:
+        .long   0x40000000
+                
+        .section        .bss
+__current_thread_info:
+        .long   0
+
+ENTRY(exception_handling_table)
+        .space  4*32
diff --git a/arch/sh/kernel/cpu/sh2a/ex.S b/arch/sh/kernel/cpu/sh2a/ex.S
new file mode 100644
index 000000000000..3ead9e63965a
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/ex.S
@@ -0,0 +1,72 @@
+/*
+ * arch/sh/kernel/cpu/sh2a/ex.S
+ *
+ * The SH-2A exception vector table
+ *
+ * Copyright (C) 2008 Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/linkage.h>
+
+!
+! convert Exception Vector to Exception Number
+!
+
+! exception no 0 to 255
+exception_entry0:
+no      =       0
+        .rept   256
+        mov.l   r1,@-sp
+        bra     exception_trampoline0
+        mov     #no,r1
+no      =       no + 1
+        .endr
+exception_trampoline0:
+        mov.l   r0,@-sp
+        mov.l   1f,r0
+        extu.b  r1,r1
+        jmp     @r0
+          extu.w        r1,r1
+         
+        .align  2
+1:      .long   exception_handler
+
+! exception no 256 to 511
+exception_entry1:
+no      =       0
+        .rept   256
+        mov.l   r1,@-sp
+        bra     exception_trampoline1
+        mov     #no,r1
+no      =       no + 1
+        .endr
+exception_trampoline1:
+        mov.l   r0,@-sp
+        extu.b  r1,r1
+        movi20  #0x100,r0
+        add     r0,r1
+        mov.l   1f,r0
+        jmp     @r0
+          extu.w        r1,r1
+        
+        .align  2
+1:      .long   exception_handler
+
+        !
+! Exception Vector Base
+!
+        .align  2
+ENTRY(vbr_base)
+vector  =       0
+        .rept   256
+        .long   exception_entry0 + vector * 6
+vector  =       vector + 1
+        .endr
+        .rept   256
+        .long   exception_entry1 + vector * 6
+vector  =       vector + 1
+        .endr
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index 4004073f98cd..3fe482dd05c1 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -14,7 +14,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 #include <asm/unistd.h>
-#include <asm/cpu/mmu_context.h>
+#include <cpu/mmu_context.h>
 #include <asm/page.h>
 
 ! NOTE:
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index 11b6d9c6edae..dac429726899 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -4,7 +4,7 @@
  *  The SH-3 and SH-4 exception vector table.
 
  *  Copyright (C) 1999, 2000, 2002  Niibe Yutaka
- *  Copyright (C) 2003 - 2006  Paul Mundt
+ *  Copyright (C) 2003 - 2008  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,13 +12,30 @@
  */
 #include <linux/linkage.h>
 
+#if !defined(CONFIG_MMU)
+#define tlb_miss_load                   exception_error
+#define tlb_miss_store                  exception_error
+#define initial_page_write              exception_error
+#define tlb_protection_violation_load   exception_error
+#define tlb_protection_violation_store  exception_error
+#define address_error_load              exception_error
+#define address_error_store             exception_error
+#endif
+
+#if !defined(CONFIG_SH_FPU)
+#define fpu_error_trap_handler          exception_error
+#endif
+
+#if !defined(CONFIG_KGDB_NMI)
+#define kgdb_handle_exception           exception_error
+#endif
+
         .align 2
         .data
 
 ENTRY(exception_handling_table)
         .long   exception_error         /* 000 */
         .long   exception_error
-#if defined(CONFIG_MMU)
         .long   tlb_miss_load           /* 040 */
         .long   tlb_miss_store
         .long   initial_page_write
@@ -26,30 +43,13 @@ ENTRY(exception_handling_table)
         .long   tlb_protection_violation_store
         .long   address_error_load
         .long   address_error_store     /* 100 */
-#else
-        .long   exception_error ! tlb miss load         /* 040 */
-        .long   exception_error ! tlb miss store
-        .long   exception_error ! initial page write
-        .long   exception_error ! tlb prot violation load
-        .long   exception_error ! tlb prot violation store
-        .long   exception_error ! address error load
-        .long   exception_error ! address error store   /* 100 */
-#endif
-#if defined(CONFIG_SH_FPU)
         .long   fpu_error_trap_handler  /* 120 */
-#else
-        .long   exception_error         /* 120 */
-#endif
         .long   exception_error         /* 140 */
         .long   system_call     ! Unconditional Trap     /* 160 */
         .long   exception_error ! reserved_instruction (filled by trap_init) /* 180 */
         .long   exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
 ENTRY(nmi_slot)
-#if defined (CONFIG_KGDB_NMI)
         .long   kgdb_handle_exception   /* 1C0 */       ! Allow trap to debugger
-#else
-        .long   exception_none  /* 1C0 */       ! Not implemented yet
-#endif
 ENTRY(user_break_point_trap)
         .long   break_point_trap        /* 1E0 */
 
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index 8020796139f1..2d452f67fb87 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -13,7 +13,7 @@
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <linux/io.h>
-#include <asm/cpu/fpu.h>
+#include <cpu/fpu.h>
 #include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/fpu.h>
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index be4926969181..2e42572b1b11 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -50,14 +50,18 @@ int __init detect_cpu_and_cache_system(void)
         boot_cpu_data.dcache.ways               = 1;
         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
 
+        /* We don't know the chip cut */
+        boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;
+
         /*
          * Setup some generic flags we can probe on SH-4A parts
          */
-        if (((pvr >> 24) & 0xff) == 0x10) {
+        if (((pvr >> 16) & 0xff) == 0x10) {
                 if ((cvr & 0x10000000) == 0)
                         boot_cpu_data.flags |= CPU_HAS_DSP;
 
                 boot_cpu_data.flags |= CPU_HAS_LLSC;
+                boot_cpu_data.cut_major = pvr & 0x7f;
         }
 
         /* FPU detection works for everyone */
diff --git a/arch/sh/kernel/cpu/sh4/softfloat.c b/arch/sh/kernel/cpu/sh4/softfloat.c
index 7b2d337ee412..828cb57cb959 100644
--- a/arch/sh/kernel/cpu/sh4/softfloat.c
+++ b/arch/sh/kernel/cpu/sh4/softfloat.c
@@ -36,7 +36,7 @@
  * and Kamel Khelifi <kamel.khelifi@st.com>
  */
 #include <linux/kernel.h>
-#include <asm/cpu/fpu.h>
+#include <cpu/fpu.h>
 
 #define LIT64( a ) a##LL
 
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index 9561b02ade0e..8a8a993f55ea 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -22,7 +22,7 @@
 #include <linux/io.h>
 #include <asm/page.h>
 #include <asm/cacheflush.h>
-#include <asm/cpu/sq.h>
+#include <cpu/sq.h>
 
 struct sq_mapping;
 
@@ -199,7 +199,7 @@ EXPORT_SYMBOL(sq_remap);
 
 /**
  * sq_unmap - Unmap a Store Queue allocation
- * @map: Pre-allocated Store Queue mapping.
+ * @vaddr: Pre-allocated Store Queue mapping.
  *
  * Unmaps the store queue allocation @map that was previously created by
  * sq_remap(). Also frees up the pte that was previously inserted into
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index a880e7968750..9381ad8da263 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -21,7 +21,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7763)	:= clock-sh7763.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7770)      := clock-sh7770.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7780)      := clock-sh7780.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7785)      := clock-sh7785.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7343)      := clock-sh7343.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7343)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7722)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7723)      := clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7366)      := clock-sh7722.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
deleted file mode 100644
index 7adc4f16e95a..000000000000
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/sh/kernel/cpu/sh4a/clock-sh7343.c
- *
- * SH7343/SH7722 support for the clock framework
- *
- *  Copyright (C) 2006  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <asm/clock.h>
-#include <asm/freq.h>
-
-/*
- * SH7343/SH7722 uses a common set of multipliers and divisors, so this
- * is quite simple..
- */
-static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
-
-#define pll_calc() (((ctrl_inl(FRQCR) >> 24) & 0x1f) + 1)
-
-static void master_clk_init(struct clk *clk)
-{
-        clk->parent = clk_get(NULL, "cpu_clk");
-}
-
-static void master_clk_recalc(struct clk *clk)
-{
-        int idx = (ctrl_inl(FRQCR) & 0x000f);
-        clk->rate *= clk->parent->rate * multipliers[idx] / divisors[idx];
-}
-
-static struct clk_ops sh7343_master_clk_ops = {
-        .init           = master_clk_init,
-        .recalc         = master_clk_recalc,
-};
-
-static void module_clk_init(struct clk *clk)
-{
-        clk->parent = NULL;
-        clk->rate = CONFIG_SH_PCLK_FREQ;
-}
-
-static struct clk_ops sh7343_module_clk_ops = {
-        .init           = module_clk_init,
-};
-
-static void bus_clk_init(struct clk *clk)
-{
-        clk->parent = clk_get(NULL, "cpu_clk");
-}
-
-static void bus_clk_recalc(struct clk *clk)
-{
-        int idx = (ctrl_inl(FRQCR) >> 8) & 0x000f;
-        clk->rate = clk->parent->rate * multipliers[idx] / divisors[idx];
-}
-
-static struct clk_ops sh7343_bus_clk_ops = {
-        .init           = bus_clk_init,
-        .recalc         = bus_clk_recalc,
-};
-
-static void cpu_clk_init(struct clk *clk)
-{
-        clk->parent = clk_get(NULL, "module_clk");
-        clk->flags |= CLK_RATE_PROPAGATES;
-        clk_set_rate(clk, clk_get_rate(clk));
-}
-
-static void cpu_clk_recalc(struct clk *clk)
-{
-        int idx = (ctrl_inl(FRQCR) >> 20) & 0x000f;
-        clk->rate = clk->parent->rate * pll_calc() *
-                multipliers[idx] / divisors[idx];
-}
-
-static struct clk_ops sh7343_cpu_clk_ops = {
-        .init           = cpu_clk_init,
-        .recalc         = cpu_clk_recalc,
-};
-
-static struct clk_ops *sh7343_clk_ops[] = {
-        &sh7343_master_clk_ops,
-        &sh7343_module_clk_ops,
-        &sh7343_bus_clk_ops,
-        &sh7343_cpu_clk_ops,
-};
-
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(sh7343_clk_ops))
-                *ops = sh7343_clk_ops[idx];
-}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 299138ebe160..db913855c2fd 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -1,7 +1,7 @@
 /*
  * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
  *
- * SH7722 & SH7366 support for the clock framework
+ * SH7343, SH7722, SH7723 & SH7366 support for the clock framework
  *
  * Copyright (c) 2006-2007 Nomad Global Solutions Inc
  * Based on code for sh7343 by Paul Mundt
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/errno.h>
+#include <linux/stringify.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
@@ -411,40 +412,40 @@ static struct clk_ops sh7722_frqcr_clk_ops = {
  * clock ops methods for SIU A/B and IrDA clock
  *
  */
-static int sh7722_siu_which(struct clk *clk)
+
+#ifndef CONFIG_CPU_SUBTYPE_SH7343
+
+static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
 {
-        if (!strcmp(clk->name, "siu_a_clk"))
-                return 0;
-        if (!strcmp(clk->name, "siu_b_clk"))
-                return 1;
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
-        if (!strcmp(clk->name, "irda_clk"))
-                return 2;
-#endif
-        return -EINVAL;
+        unsigned long r;
+        int div;
+
+        r = ctrl_inl(clk->arch_flags);
+        div = sh7722_find_divisors(clk->parent->rate, rate);
+        if (div < 0)
+                return div;
+        r = (r & ~0xF) | div;
+        ctrl_outl(r, clk->arch_flags);
+        return 0;
 }
 
-static unsigned long sh7722_siu_regs[] = {
-        [0] = SCLKACR,
-        [1] = SCLKBCR,
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
-        [2] = IrDACLKCR,
-#endif
-};
+static void sh7722_siu_recalc(struct clk *clk)
+{
+        unsigned long r;
+
+        r = ctrl_inl(clk->arch_flags);
+        clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
+}
 
 static int sh7722_siu_start_stop(struct clk *clk, int enable)
 {
-        int siu = sh7722_siu_which(clk);
         unsigned long r;
 
-        if (siu < 0)
-                return siu;
-        BUG_ON(siu > 2);
-        r = ctrl_inl(sh7722_siu_regs[siu]);
+        r = ctrl_inl(clk->arch_flags);
         if (enable)
-                ctrl_outl(r & ~(1 << 8), sh7722_siu_regs[siu]);
+                ctrl_outl(r & ~(1 << 8), clk->arch_flags);
         else
-                ctrl_outl(r | (1 << 8), sh7722_siu_regs[siu]);
+                ctrl_outl(r | (1 << 8), clk->arch_flags);
         return 0;
 }
 
@@ -458,6 +459,15 @@ static void sh7722_siu_disable(struct clk *clk)
         sh7722_siu_start_stop(clk, 0);
 }
 
+static struct clk_ops sh7722_siu_clk_ops = {
+        .recalc = sh7722_siu_recalc,
+        .set_rate = sh7722_siu_set_rate,
+        .enable = sh7722_siu_enable,
+        .disable = sh7722_siu_disable,
+};
+
+#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
+
 static void sh7722_video_enable(struct clk *clk)
 {
         unsigned long r;
@@ -494,43 +504,6 @@ static void sh7722_video_recalc(struct clk *clk)
         clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
 }
 
-static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
-{
-        int siu = sh7722_siu_which(clk);
-        unsigned long r;
-        int div;
-
-        if (siu < 0)
-                return siu;
-        BUG_ON(siu > 2);
-        r = ctrl_inl(sh7722_siu_regs[siu]);
-        div = sh7722_find_divisors(clk->parent->rate, rate);
-        if (div < 0)
-                return div;
-        r = (r & ~0xF) | div;
-        ctrl_outl(r, sh7722_siu_regs[siu]);
-        return 0;
-}
-
-static void sh7722_siu_recalc(struct clk *clk)
-{
-        int siu = sh7722_siu_which(clk);
-        unsigned long r;
-
-        if (siu < 0)
-                return /* siu */ ;
-        BUG_ON(siu > 2);
-        r = ctrl_inl(sh7722_siu_regs[siu]);
-        clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
-}
-
-static struct clk_ops sh7722_siu_clk_ops = {
-        .recalc = sh7722_siu_recalc,
-        .set_rate = sh7722_siu_set_rate,
-        .enable = sh7722_siu_enable,
-        .disable = sh7722_siu_disable,
-};
-
 static struct clk_ops sh7722_video_clk_ops = {
         .recalc = sh7722_video_recalc,
         .set_rate = sh7722_video_set_rate,
@@ -560,6 +533,9 @@ static struct clk sh7722_sdram_clock = {
         .ops = &sh7722_frqcr_clk_ops,
 };
 
+
+#ifndef CONFIG_CPU_SUBTYPE_SH7343
+
 /*
  * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
  * methods of clk_ops determine which register they should access by
@@ -567,36 +543,151 @@ static struct clk sh7722_sdram_clock = {
  */
 static struct clk sh7722_siu_a_clock = {
         .name = "siu_a_clk",
+        .arch_flags = SCLKACR,
         .ops = &sh7722_siu_clk_ops,
 };
 
 static struct clk sh7722_siu_b_clock = {
         .name = "siu_b_clk",
+        .arch_flags = SCLKBCR,
         .ops = &sh7722_siu_clk_ops,
 };
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
 static struct clk sh7722_irda_clock = {
         .name = "irda_clk",
+        .arch_flags = IrDACLKCR,
         .ops = &sh7722_siu_clk_ops,
 };
 #endif
+#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
 
 static struct clk sh7722_video_clock = {
         .name = "video_clk",
         .ops = &sh7722_video_clk_ops,
 };
 
+static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg,
+                                    int enable)
+{
+        unsigned long bit = clk->arch_flags;
+        unsigned long r;
+
+        r = ctrl_inl(reg);
+
+        if (enable)
+                r &= ~(1 << bit);
+        else
+                r |= (1 << bit);
+
+        ctrl_outl(r, reg);
+        return 0;
+}
+
+static void sh7722_mstpcr0_enable(struct clk *clk)
+{
+        sh7722_mstpcr_start_stop(clk, MSTPCR0, 1);
+}
+
+static void sh7722_mstpcr0_disable(struct clk *clk)
+{
+        sh7722_mstpcr_start_stop(clk, MSTPCR0, 0);
+}
+
+static void sh7722_mstpcr1_enable(struct clk *clk)
+{
+        sh7722_mstpcr_start_stop(clk, MSTPCR1, 1);
+}
+
+static void sh7722_mstpcr1_disable(struct clk *clk)
+{
+        sh7722_mstpcr_start_stop(clk, MSTPCR1, 0);
+}
+
+static void sh7722_mstpcr2_enable(struct clk *clk)
+{
+        sh7722_mstpcr_start_stop(clk, MSTPCR2, 1);
+}
+
+static void sh7722_mstpcr2_disable(struct clk *clk)
+{
+        sh7722_mstpcr_start_stop(clk, MSTPCR2, 0);
+}
+
+static struct clk_ops sh7722_mstpcr0_clk_ops = {
+        .enable = sh7722_mstpcr0_enable,
+        .disable = sh7722_mstpcr0_disable,
+};
+
+static struct clk_ops sh7722_mstpcr1_clk_ops = {
+        .enable = sh7722_mstpcr1_enable,
+        .disable = sh7722_mstpcr1_disable,
+};
+
+static struct clk_ops sh7722_mstpcr2_clk_ops = {
+        .enable = sh7722_mstpcr2_enable,
+        .disable = sh7722_mstpcr2_disable,
+};
+
+#define DECLARE_MSTPCRN(regnr, bitnr, bitstr)           \
+{                                                       \
+        .name = "mstp" __stringify(regnr) bitstr,       \
+        .arch_flags = bitnr,                            \
+        .ops = &sh7722_mstpcr ## regnr ## _clk_ops,     \
+}
+
+#define DECLARE_MSTPCR(regnr) \
+        DECLARE_MSTPCRN(regnr, 31, "31"), \
+        DECLARE_MSTPCRN(regnr, 30, "30"), \
+        DECLARE_MSTPCRN(regnr, 29, "29"), \
+        DECLARE_MSTPCRN(regnr, 28, "28"), \
+        DECLARE_MSTPCRN(regnr, 27, "27"), \
+        DECLARE_MSTPCRN(regnr, 26, "26"), \
+        DECLARE_MSTPCRN(regnr, 25, "25"), \
+        DECLARE_MSTPCRN(regnr, 24, "24"), \
+        DECLARE_MSTPCRN(regnr, 23, "23"), \
+        DECLARE_MSTPCRN(regnr, 22, "22"), \
+        DECLARE_MSTPCRN(regnr, 21, "21"), \
+        DECLARE_MSTPCRN(regnr, 20, "20"), \
+        DECLARE_MSTPCRN(regnr, 19, "19"), \
+        DECLARE_MSTPCRN(regnr, 18, "18"), \
+        DECLARE_MSTPCRN(regnr, 17, "17"), \
+        DECLARE_MSTPCRN(regnr, 16, "16"), \
+        DECLARE_MSTPCRN(regnr, 15, "15"), \
+        DECLARE_MSTPCRN(regnr, 14, "14"), \
+        DECLARE_MSTPCRN(regnr, 13, "13"), \
+        DECLARE_MSTPCRN(regnr, 12, "12"), \
+        DECLARE_MSTPCRN(regnr, 11, "11"), \
+        DECLARE_MSTPCRN(regnr, 10, "10"), \
+        DECLARE_MSTPCRN(regnr, 9, "09"), \
+        DECLARE_MSTPCRN(regnr, 8, "08"), \
+        DECLARE_MSTPCRN(regnr, 7, "07"), \
+        DECLARE_MSTPCRN(regnr, 6, "06"), \
+        DECLARE_MSTPCRN(regnr, 5, "05"), \
+        DECLARE_MSTPCRN(regnr, 4, "04"), \
+        DECLARE_MSTPCRN(regnr, 3, "03"), \
+        DECLARE_MSTPCRN(regnr, 2, "02"), \
+        DECLARE_MSTPCRN(regnr, 1, "01"), \
+        DECLARE_MSTPCRN(regnr, 0, "00")
+
+static struct clk sh7722_mstpcr[] = {
+        DECLARE_MSTPCR(0),
+        DECLARE_MSTPCR(1),
+        DECLARE_MSTPCR(2),
+};
+
 static struct clk *sh7722_clocks[] = {
         &sh7722_umem_clock,
         &sh7722_sh_clock,
         &sh7722_peripheral_clock,
         &sh7722_sdram_clock,
+#ifndef CONFIG_CPU_SUBTYPE_SH7343
         &sh7722_siu_a_clock,
         &sh7722_siu_b_clock,
 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
         &sh7722_irda_clock,
 #endif
+#endif
         &sh7722_video_clock,
 };
 
@@ -629,5 +720,11 @@ int __init arch_clk_init(void)
                 clk_register(sh7722_clocks[i]);
         }
         clk_put(master);
+
+        for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) {
+                pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name);
+                clk_register(&sh7722_mstpcr[i]);
+        }
+
         return 0;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 6d4f50cd4aaf..78881b4214da 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -11,6 +11,104 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/uio_driver.h>
+#include <asm/clock.h>
+
+static struct resource iic0_resources[] = {
+        [0] = {
+                .name   = "IIC0",
+                .start  = 0x04470000,
+                .end    = 0x04470017,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .end    = 99,
+                .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic0_device = {
+        .name           = "i2c-sh_mobile",
+        .num_resources  = ARRAY_SIZE(iic0_resources),
+        .resource       = iic0_resources,
+};
+
+static struct resource iic1_resources[] = {
+        [0] = {
+                .name   = "IIC1",
+                .start  = 0x04750000,
+                .end    = 0x04750017,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 44,
+                .end    = 47,
+                .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic1_device = {
+        .name           = "i2c-sh_mobile",
+        .num_resources  = ARRAY_SIZE(iic1_resources),
+        .resource       = iic1_resources,
+};
+
+static struct uio_info vpu_platform_data = {
+        .name = "VPU4",
+        .version = "0",
+        .irq = 60,
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe9022eb,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+static struct uio_info veu_platform_data = {
+        .name = "VEU",
+        .version = "0",
+        .irq = 54,
+};
+
+static struct resource veu_resources[] = {
+        [0] = {
+                .name   = "VEU",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200b7,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu_platform_data,
+        },
+        .resource       = veu_resources,
+        .num_resources  = ARRAY_SIZE(veu_resources),
+};
 
 static struct plat_sci_port sci_platform_data[] = {
         {
@@ -32,16 +130,171 @@ static struct platform_device sci_device = {
 };
 
 static struct platform_device *sh7343_devices[] __initdata = {
+        &iic0_device,
+        &iic1_device,
         &sci_device,
+        &vpu_device,
+        &veu_device,
 };
 
 static int __init sh7343_devices_setup(void)
 {
+        clk_always_enable("mstp031"); /* TLB */
+        clk_always_enable("mstp030"); /* IC */
+        clk_always_enable("mstp029"); /* OC */
+        clk_always_enable("mstp028"); /* URAM */
+        clk_always_enable("mstp026"); /* XYMEM */
+        clk_always_enable("mstp023"); /* INTC3 */
+        clk_always_enable("mstp022"); /* INTC */
+        clk_always_enable("mstp020"); /* SuperHyway */
+        clk_always_enable("mstp109"); /* I2C0 */
+        clk_always_enable("mstp108"); /* I2C1 */
+        clk_always_enable("mstp202"); /* VEU */
+        clk_always_enable("mstp201"); /* VPU */
+
+        platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
+        platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
+
         return platform_add_devices(sh7343_devices,
                                     ARRAY_SIZE(sh7343_devices));
 }
 __initcall(sh7343_devices_setup);
 
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+        DMAC0, DMAC1, DMAC2, DMAC3,
+        VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
+        MFI, VPU, TPU, Z3D4, USBI0, USBI1,
+        MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
+        DMAC4, DMAC5, DMAC_DADERR,
+        KEYSC,
+        SCIF, SCIF1, SCIF2, SCIF3, SCIF4,
+        SIOF0, SIOF1, SIO,
+        FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
+        I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
+        I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
+        SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
+        IRDA,
+        SDHI0, SDHI1, SDHI2, SDHI3,
+        CMT, TSIF, SIU,
+        TMU0, TMU1, TMU2,
+        JPU, LCDC,
+
+        /* interrupt groups */
+
+        DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
+        INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
+        INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
+        INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
+        INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
+        INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
+        INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
+        INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
+        INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
+        INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
+        INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
+        INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
+        INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
+        INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
+        INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
+        INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
+        INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
+        INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
+        INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
+        INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
+        INTC_VECT(SIO, 0xd00),
+        INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
+        INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
+        INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
+        INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
+        INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
+        INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
+        INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
+        INTC_VECT(SIU, 0xf80),
+        INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
+        INTC_VECT(TMU2, 0x440),
+        INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
+        INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
+        INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
+        INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
+        INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
+                   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
+        INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
+        INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
+        INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
+        INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
+        INTC_GROUP(USB, USBI0, USBI1),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
+          { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
+        { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
+          { 0, 0, 0, VPU, 0, 0, 0, MFI } },
+        { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
+          { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
+        { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
+          { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
+        { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
+          { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
+        { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
+          { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
+        { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
+          { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
+            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
+        { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
+          { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
+        { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
+          { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
+        { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
+          { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
+        { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
+          { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
+        { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
+        { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
+        { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
+        { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
+        { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
+        { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
+        { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
+        { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
+        { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
+        { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
+        { 0xa4140010, 0, 32, 4, /* INTPRI00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+        { 0xa414001c, 16, 2, /* ICR1 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xa4140024, 0, 8, /* INTREQ00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
+                             mask_registers, prio_registers, sense_registers,
+                             ack_registers);
+
 void __init plat_irq_setup(void)
 {
+        register_intc_controller(&intc_desc);
 }
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index f26b5cdad0d1..6851dba02f31 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -13,6 +13,112 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/uio_driver.h>
+#include <asm/clock.h>
+
+static struct resource iic_resources[] = {
+        [0] = {
+                .name   = "IIC",
+                .start  = 0x04470000,
+                .end    = 0x04470017,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .end    = 99,
+                .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic_device = {
+        .name           = "i2c-sh_mobile",
+        .num_resources  = ARRAY_SIZE(iic_resources),
+        .resource       = iic_resources,
+};
+
+static struct uio_info vpu_platform_data = {
+        .name = "VPU5",
+        .version = "0",
+        .irq = 60,
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe902807,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+static struct uio_info veu0_platform_data = {
+        .name = "VEU",
+        .version = "0",
+        .irq = 54,
+};
+
+static struct resource veu0_resources[] = {
+        [0] = {
+                .name   = "VEU(1)",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200b7,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu0_platform_data,
+        },
+        .resource       = veu0_resources,
+        .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+static struct uio_info veu1_platform_data = {
+        .name = "VEU",
+        .version = "0",
+        .irq = 27,
+};
+
+static struct resource veu1_resources[] = {
+        [0] = {
+                .name   = "VEU(2)",
+                .start  = 0xfe924000,
+                .end    = 0xfe9240b7,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &veu1_platform_data,
+        },
+        .resource       = veu1_resources,
+        .num_resources  = ARRAY_SIZE(veu1_resources),
+};
 
 static struct plat_sci_port sci_platform_data[] = {
         {
@@ -34,11 +140,32 @@ static struct platform_device sci_device = {
 };
 
 static struct platform_device *sh7366_devices[] __initdata = {
+        &iic_device,
         &sci_device,
+        &vpu_device,
+        &veu0_device,
+        &veu1_device,
 };
 
 static int __init sh7366_devices_setup(void)
 {
+        clk_always_enable("mstp031"); /* TLB */
+        clk_always_enable("mstp030"); /* IC */
+        clk_always_enable("mstp029"); /* OC */
+        clk_always_enable("mstp028"); /* RSMEM */
+        clk_always_enable("mstp026"); /* XYMEM */
+        clk_always_enable("mstp023"); /* INTC3 */
+        clk_always_enable("mstp022"); /* INTC */
+        clk_always_enable("mstp020"); /* SuperHyway */
+        clk_always_enable("mstp109"); /* I2C */
+        clk_always_enable("mstp207"); /* VEU-2 */
+        clk_always_enable("mstp202"); /* VEU-1 */
+        clk_always_enable("mstp201"); /* VPU */
+
+        platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
+        platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
+        platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
+
         return platform_add_devices(sh7366_devices,
                                     ARRAY_SIZE(sh7366_devices));
 }
@@ -97,7 +224,7 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(SIU, 0xf80),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
         INTC_VECT(TMU2, 0x440),
-        INTC_VECT(VEU2, 0x580), INTC_VECT(LCDC, 0x580),
+        INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
 };
 
 static struct intc_group groups[] __initdata = {
@@ -163,8 +290,14 @@ static struct intc_sense_reg sense_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC(intc_desc, "sh7366", vectors, groups,
-                         mask_registers, prio_registers, sense_registers);
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xa4140024, 0, 8, /* INTREQ00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups,
+                             mask_registers, prio_registers, sense_registers,
+                             ack_registers);
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 62ebccf18b3c..de1ede92176e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -12,6 +12,8 @@
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
 #include <linux/mm.h>
+#include <linux/uio_driver.h>
+#include <asm/clock.h>
 #include <asm/mmzone.h>
 
 static struct resource usbf_resources[] = {
@@ -59,6 +61,62 @@ static struct platform_device iic_device = {
         .resource       = iic_resources,
 };
 
+static struct uio_info vpu_platform_data = {
+        .name = "VPU4",
+        .version = "0",
+        .irq = 60,
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe9022eb,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+static struct uio_info veu_platform_data = {
+        .name = "VEU",
+        .version = "0",
+        .irq = 54,
+};
+
+static struct resource veu_resources[] = {
+        [0] = {
+                .name   = "VEU",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200b7,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu_platform_data,
+        },
+        .resource       = veu_resources,
+        .num_resources  = ARRAY_SIZE(veu_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffe00000,
@@ -95,10 +153,27 @@ static struct platform_device *sh7722_devices[] __initdata = {
         &usbf_device,
         &iic_device,
         &sci_device,
+        &vpu_device,
+        &veu_device,
 };
 
 static int __init sh7722_devices_setup(void)
 {
+        clk_always_enable("mstp031"); /* TLB */
+        clk_always_enable("mstp030"); /* IC */
+        clk_always_enable("mstp029"); /* OC */
+        clk_always_enable("mstp028"); /* URAM */
+        clk_always_enable("mstp026"); /* XYMEM */
+        clk_always_enable("mstp022"); /* INTC */
+        clk_always_enable("mstp020"); /* SuperHyway */
+        clk_always_enable("mstp109"); /* I2C */
+        clk_always_enable("mstp211"); /* USB */
+        clk_always_enable("mstp202"); /* VEU */
+        clk_always_enable("mstp201"); /* VPU */
+
+        platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
+        platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
+
         return platform_add_devices(sh7722_devices,
                                     ARRAY_SIZE(sh7722_devices));
 }
@@ -229,8 +304,14 @@ static struct intc_sense_reg sense_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups,
-                         mask_registers, prio_registers, sense_registers);
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xa4140024, 0, 8, /* INTREQ00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
+                             mask_registers, prio_registers, sense_registers,
+                             ack_registers);
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a0470f2f5479..cd6baffdc896 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -12,8 +12,94 @@
 #include <linux/serial.h>
 #include <linux/mm.h>
 #include <linux/serial_sci.h>
+#include <linux/uio_driver.h>
+#include <asm/clock.h>
 #include <asm/mmzone.h>
 
+static struct uio_info vpu_platform_data = {
+        .name = "VPU5",
+        .version = "0",
+        .irq = 60,
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe902807,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+static struct uio_info veu0_platform_data = {
+        .name = "VEU",
+        .version = "0",
+        .irq = 54,
+};
+
+static struct resource veu0_resources[] = {
+        [0] = {
+                .name   = "VEU2H0",
+                .start  = 0xfe920000,
+                .end    = 0xfe92027b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu0_platform_data,
+        },
+        .resource       = veu0_resources,
+        .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+static struct uio_info veu1_platform_data = {
+        .name = "VEU",
+        .version = "0",
+        .irq = 27,
+};
+
+static struct resource veu1_resources[] = {
+        [0] = {
+                .name   = "VEU2H1",
+                .start  = 0xfe924000,
+                .end    = 0xfe92427b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &veu1_platform_data,
+        },
+        .resource       = veu1_resources,
+        .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffe00000,
@@ -113,14 +199,56 @@ static struct platform_device sh7723_usb_host_device = {
         .resource       = sh7723_usb_host_resources,
 };
 
+static struct resource iic_resources[] = {
+        [0] = {
+                .name   = "IIC",
+                .start  = 0x04470000,
+                .end    = 0x04470017,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .end    = 99,
+                .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic_device = {
+        .name           = "i2c-sh_mobile",
+        .num_resources  = ARRAY_SIZE(iic_resources),
+        .resource       = iic_resources,
+};
+
 static struct platform_device *sh7723_devices[] __initdata = {
         &sci_device,
         &rtc_device,
+        &iic_device,
         &sh7723_usb_host_device,
+        &vpu_device,
+        &veu0_device,
+        &veu1_device,
 };
 
 static int __init sh7723_devices_setup(void)
 {
+        clk_always_enable("mstp031"); /* TLB */
+        clk_always_enable("mstp030"); /* IC */
+        clk_always_enable("mstp029"); /* OC */
+        clk_always_enable("mstp024"); /* FPU */
+        clk_always_enable("mstp022"); /* INTC */
+        clk_always_enable("mstp020"); /* SuperHyway */
+        clk_always_enable("mstp000"); /* MERAM */
+        clk_always_enable("mstp109"); /* I2C */
+        clk_always_enable("mstp108"); /* RTC */
+        clk_always_enable("mstp211"); /* USB */
+        clk_always_enable("mstp206"); /* VEU2H1 */
+        clk_always_enable("mstp202"); /* VEU2H0 */
+        clk_always_enable("mstp201"); /* VPU */
+
+        platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
+        platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
+        platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
+
         return platform_add_devices(sh7723_devices,
                                     ARRAY_SIZE(sh7723_devices));
 }
@@ -326,8 +454,14 @@ static struct intc_sense_reg sense_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
-                         mask_registers, prio_registers, sense_registers);
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xa4140024, 0, 8, /* INTREQ00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
+                             mask_registers, prio_registers, sense_registers,
+                             ack_registers);
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index f189a559462b..3c5b629887a8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2006  Paul Mundt
  *  Copyright (C) 2007  Yoshihiro Shimoda
+ *  Copyright (C) 2008  Nobuhiro Iwamatsu
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -56,6 +57,11 @@ static struct plat_sci_port sci_platform_data[] = {
                 .type           = PORT_SCIF,
                 .irqs           = { 76, 77, 79, 78 },
         }, {
+                .mapbase        = 0xffe10000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 104, 105, 107, 106 },
+        }, {
                 .flags = 0,
         }
 };
@@ -208,8 +214,8 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
-        INTC_VECT(SCIF1_ERI, 0xf00), INTC_VECT(SCIF1_RXI, 0xf20),
-        INTC_VECT(SCIF1_BRI, 0xf40), INTC_VECT(SCIF1_TXI, 0xf60),
+        INTC_VECT(SCIF2_ERI, 0xf00), INTC_VECT(SCIF2_RXI, 0xf20),
+        INTC_VECT(SCIF2_BRI, 0xf40), INTC_VECT(SCIF2_TXI, 0xf60),
         INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0),
         INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0),
 };
@@ -290,9 +296,14 @@ static struct intc_sense_reg irq_sense_registers[] __initdata = {
                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC(intc_irq_desc, "sh7763-irq", irq_vectors,
-                        NULL, irq_mask_registers, irq_prio_registers,
-                        irq_sense_registers);
+static struct intc_mask_reg irq_ack_registers[] __initdata = {
+        { 0xffd00024, 0, 32, /* INTREQ */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
+                             NULL, irq_mask_registers, irq_prio_registers,
+                             irq_sense_registers, irq_ack_registers);
 
 
 /* External interrupt pins in IRL mode */
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 18dbbe23fea1..fb8200cc7440 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -217,9 +217,14 @@ static struct intc_sense_reg irq_sense_registers[] __initdata = {
                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
-                         NULL, irq_mask_registers, irq_prio_registers,
-                         irq_sense_registers);
+static struct intc_mask_reg irq_ack_registers[] __initdata = {
+        { 0xffd00024, 0, 32, /* INTREQ */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
+                             NULL, irq_mask_registers, irq_prio_registers,
+                             irq_sense_registers, irq_ack_registers);
 
 /* External interrupt pins in IRL mode */
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 621e7329ec63..30baa63b24c8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -238,13 +238,18 @@ static struct intc_sense_reg sense_registers[] __initdata = {
                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
-                         NULL, mask_registers, prio_registers,
-                         sense_registers);
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xffd00024, 0, 32, /* INTREQ */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
+                             vectors_irq0123, NULL, mask_registers,
+                             prio_registers, sense_registers, ack_registers);
 
-static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
-                         NULL, mask_registers, prio_registers,
-                         sense_registers);
+static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
+                             vectors_irq4567, NULL, mask_registers,
+                             prio_registers, sense_registers, ack_registers);
 
 /* External interrupt pins in IRL mode */
 
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index 05372ed6c568..04c7da968146 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -11,7 +11,7 @@
  */
 #include <linux/errno.h>
 #include <linux/sys.h>
-#include <asm/cpu/registers.h>
+#include <cpu/registers.h>
 #include <asm/processor.h>
 #include <asm/unistd.h>
 #include <asm/thread_info.h>
@@ -987,11 +987,11 @@ work_resched:
 work_notifysig:
         gettr   tr1, LINK
 
-        movi    do_signal, r6
+        movi    do_notify_resume, r6
         ptabs   r6, tr0
         or      SP, ZERO, r2
-        or      ZERO, ZERO, r3
-        blink   tr0, LINK           /* Call do_signal(regs, 0), return here */
+        or      r7, ZERO, r3
+        blink   tr0, LINK           /* Call do_notify_resume(regs, current_thread_info->flags), return here */
 
 restore_all:
         /* Do prefetches */
@@ -1300,18 +1300,20 @@ syscall_allowed:
 
         getcon  KCR0, r2
         ld.l    r2, TI_FLAGS, r4
-        movi    (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | _TIF_SYSCALL_AUDIT), r6
+        movi    _TIF_WORK_SYSCALL_MASK, r6
         and     r6, r4, r6
         beq/l   r6, ZERO, tr0
 
         /* Trace it by calling syscall_trace before and after */
-        movi    syscall_trace, r4
+        movi    do_syscall_trace_enter, r4
         or      SP, ZERO, r2
-        or      ZERO, ZERO, r3
         ptabs   r4, tr0
         blink   tr0, LINK
 
-        /* Reload syscall number as r5 is trashed by syscall_trace */
+        /* Save the retval */
+        st.q    SP, FRAME_R(2), r2
+
+        /* Reload syscall number as r5 is trashed by do_syscall_trace_enter */
         ld.q    SP, FRAME_S(FSYSCALL_ID), r5
         andi    r5, 0x1ff, r5
 
@@ -1343,9 +1345,8 @@ syscall_ret_trace:
         /* We get back here only if under trace */
         st.q    SP, FRAME_R(9), r2      /* Save return value */
 
-        movi    syscall_trace, LINK
+        movi    do_syscall_trace_leave, LINK
         or      SP, ZERO, r2
-        movi    1, r3
         ptabs   LINK, tr0
         blink   tr0, LINK
 
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index 718bd2356b34..0bc17def55a7 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -192,7 +192,7 @@ work_resched:
         .align  2
 1:      .long   schedule
 2:      .long   do_notify_resume
-3:      .long   restore_all
+3:      .long   resume_userspace
 #ifdef CONFIG_TRACE_IRQFLAGS
 4:      .long   trace_hardirqs_on
 5:      .long   trace_hardirqs_off
@@ -202,7 +202,7 @@ work_resched:
 syscall_exit_work:
         ! r0: current_thread_info->flags
         ! r8: current_thread_info
-        tst     #_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | _TIF_SYSCALL_AUDIT, r0
+        tst     #_TIF_WORK_SYSCALL_MASK, r0
         bt/s    work_pending
          tst    #_TIF_NEED_RESCHED, r0
 #ifdef CONFIG_TRACE_IRQFLAGS
@@ -211,10 +211,8 @@ syscall_exit_work:
          nop
 #endif
         sti
-        ! XXX setup arguments...
         mov     r15, r4
-        mov     #1, r5
-        mov.l   4f, r0                  ! do_syscall_trace
+        mov.l   8f, r0                  ! do_syscall_trace_leave
         jsr     @r0
          nop
         bra     resume_userspace
@@ -223,12 +221,11 @@ syscall_exit_work:
         .align  2
 syscall_trace_entry:
         !                       Yes it is traced.
-        ! XXX setup arguments...
         mov     r15, r4
-        mov     #0, r5
-        mov.l   4f, r11         ! Call do_syscall_trace which notifies
+        mov.l   7f, r11         ! Call do_syscall_trace_enter which notifies
         jsr     @r11            ! superior (will chomp R[0-7])
          nop
+        mov.l   r0, @(OFF_R0,r15)       ! Save return value
         !                       Reload R0-R4 from kernel stack, where the
         !                       parent may have modified them using
         !                       ptrace(POKEUSR).  (Note that R0-R2 are
@@ -351,7 +348,7 @@ ENTRY(system_call)
         !
         get_current_thread_info r8, r10
         mov.l   @(TI_FLAGS,r8), r8
-        mov     #(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT), r10
+        mov     #_TIF_WORK_SYSCALL_MASK, r10
         tst     r10, r8
         bf      syscall_trace_entry
         !
@@ -389,8 +386,9 @@ syscall_exit:
 #endif
 2:      .long   NR_syscalls
 3:      .long   sys_call_table
-4:      .long   do_syscall_trace
 #ifdef CONFIG_TRACE_IRQFLAGS
 5:      .long   trace_hardirqs_on
 6:      .long   trace_hardirqs_off
 #endif
+7:      .long   do_syscall_trace_enter
+8:      .long   do_syscall_trace_leave
diff --git a/arch/sh/kernel/head_64.S b/arch/sh/kernel/head_64.S
index f42d4c0feb76..7ccfb995a398 100644
--- a/arch/sh/kernel/head_64.S
+++ b/arch/sh/kernel/head_64.S
@@ -11,8 +11,8 @@
 #include <asm/page.h>
 #include <asm/cache.h>
 #include <asm/tlb.h>
-#include <asm/cpu/registers.h>
-#include <asm/cpu/mmu_context.h>
+#include <cpu/registers.h>
+#include <cpu/mmu_context.h>
 #include <asm/thread_info.h>
 
 /*
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index a2a99e487e33..64b7690c664c 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -15,7 +15,7 @@
 #include <asm/machvec.h>
 #include <asm/uaccess.h>
 #include <asm/thread_info.h>
-#include <asm/cpu/mmu_context.h>
+#include <cpu/mmu_context.h>
 
 atomic_t irq_err_count;
 
diff --git a/arch/sh/kernel/machine_kexec.c b/arch/sh/kernel/machine_kexec.c
index ec1eadce4aaa..4703dff174d5 100644
--- a/arch/sh/kernel/machine_kexec.c
+++ b/arch/sh/kernel/machine_kexec.c
@@ -13,6 +13,7 @@
 #include <linux/kexec.h>
 #include <linux/delay.h>
 #include <linux/reboot.h>
+#include <linux/numa.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
@@ -104,3 +105,10 @@ void machine_kexec(struct kimage *image)
         (*rnk)(page_list, reboot_code_buffer, image->start, vbr_reg);
 }
 
+void arch_crash_save_vmcoreinfo(void)
+{
+#ifdef CONFIG_NUMA
+        VMCOREINFO_SYMBOL(node_data);
+        VMCOREINFO_LENGTH(node_data, MAX_NUMNODES);
+#endif
+}
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index 5482e65375a9..c43081039dd5 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -27,6 +27,7 @@
 #include <linux/moduleloader.h>
 #include <linux/elf.h>
 #include <linux/vmalloc.h>
+#include <linux/bug.h>
 #include <linux/fs.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
@@ -36,7 +37,8 @@ void *module_alloc(unsigned long size)
 {
         if (size == 0)
                 return NULL;
-        return vmalloc(size);
+
+        return vmalloc_exec(size);
 }
 
 
@@ -145,9 +147,10 @@ int module_finalize(const Elf_Ehdr *hdr,
                     const Elf_Shdr *sechdrs,
                     struct module *me)
 {
-        return 0;
+        return module_bug_finalize(hdr, sechdrs, me);
 }
 
 void module_arch_cleanup(struct module *mod)
 {
+        module_bug_cleanup(mod);
 }
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 921892c351da..3326a45749d9 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -34,18 +34,6 @@ void (*pm_idle)(void);
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void disable_hlt(void)
-{
-        hlt_counter++;
-}
-EXPORT_SYMBOL(disable_hlt);
-
-void enable_hlt(void)
-{
-        hlt_counter--;
-}
-EXPORT_SYMBOL(enable_hlt);
-
 static int __init nohlt_setup(char *__unused)
 {
         hlt_counter = 1;
@@ -60,7 +48,7 @@ static int __init hlt_setup(char *__unused)
 }
 __setup("hlt", hlt_setup);
 
-void default_idle(void)
+static void default_idle(void)
 {
         if (!hlt_counter) {
                 clear_thread_flag(TIF_POLLING_NRFLAG);
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index 0283d8133075..b9dbd2d3b4a5 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -36,16 +36,6 @@ static int hlt_counter = 1;
 
 #define HARD_IDLE_TIMEOUT (HZ / 3)
 
-void disable_hlt(void)
-{
-        hlt_counter++;
-}
-
-void enable_hlt(void)
-{
-        hlt_counter--;
-}
-
 static int __init nohlt_setup(char *__unused)
 {
         hlt_counter = 1;
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index fddb547f3c2b..035cb300d3dc 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -20,6 +20,8 @@
 #include <linux/signal.h>
 #include <linux/io.h>
 #include <linux/audit.h>
+#include <linux/seccomp.h>
+#include <linux/tracehook.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -57,7 +59,23 @@ static inline int put_stack_long(struct task_struct *task, int offset,
         return 0;
 }
 
-static void ptrace_disable_singlestep(struct task_struct *child)
+void user_enable_single_step(struct task_struct *child)
+{
+        struct pt_regs *regs = task_pt_regs(child);
+        long pc;
+
+        pc = get_stack_long(child, (long)&regs->pc);
+
+        /* Next scheduling will set up UBC */
+        if (child->thread.ubc_pc == 0)
+                ubc_usercnt += 1;
+
+        child->thread.ubc_pc = pc;
+
+        set_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+
+void user_disable_single_step(struct task_struct *child)
 {
         clear_tsk_thread_flag(child, TIF_SINGLESTEP);
 
@@ -81,7 +99,7 @@ static void ptrace_disable_singlestep(struct task_struct *child)
  */
 void ptrace_disable(struct task_struct *child)
 {
-        ptrace_disable_singlestep(child);
+        user_disable_single_step(child);
 }
 
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
@@ -90,12 +108,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         int ret;
 
         switch (request) {
-        /* when I and D space are separate, these will need to be fixed. */
-        case PTRACE_PEEKTEXT: /* read word at location addr. */
-        case PTRACE_PEEKDATA:
-                ret = generic_ptrace_peekdata(child, addr, data);
-                break;
-
         /* read the word at location addr in the USER area. */
         case PTRACE_PEEKUSR: {
                 unsigned long tmp;
@@ -125,12 +137,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 break;
         }
 
-        /* when I and D space are separate, this will have to be fixed. */
-        case PTRACE_POKETEXT: /* write the word at location addr. */
-        case PTRACE_POKEDATA:
-                ret = generic_ptrace_pokedata(child, addr, data);
-                break;
-
         case PTRACE_POKEUSR: /* write the word at location addr in the USER area */
                 ret = -EIO;
                 if ((addr & 3) || addr < 0 ||
@@ -151,67 +157,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 }
                 break;
 
-        case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
-        case PTRACE_CONT: { /* restart after signal. */
-                ret = -EIO;
-                if (!valid_signal(data))
-                        break;
-                if (request == PTRACE_SYSCALL)
-                        set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-                else
-                        clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-
-                ptrace_disable_singlestep(child);
-
-                child->exit_code = data;
-                wake_up_process(child);
-                ret = 0;
-                break;
-        }
-
-/*
- * make the child exit.  Best I can do is send it a sigkill.
- * perhaps it should be put in the status that it wants to
- * exit.
- */
-        case PTRACE_KILL: {
-                ret = 0;
-                if (child->exit_state == EXIT_ZOMBIE)   /* already dead */
-                        break;
-                ptrace_disable_singlestep(child);
-                child->exit_code = SIGKILL;
-                wake_up_process(child);
-                break;
-        }
-
-        case PTRACE_SINGLESTEP: {  /* set the trap flag. */
-                long pc;
-                struct pt_regs *regs = NULL;
-
-                ret = -EIO;
-                if (!valid_signal(data))
-                        break;
-                clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-                if ((child->ptrace & PT_DTRACE) == 0) {
-                        /* Spurious delayed TF traps may occur */
-                        child->ptrace |= PT_DTRACE;
-                }
-
-                pc = get_stack_long(child, (long)&regs->pc);
-
-                /* Next scheduling will set up UBC */
-                if (child->thread.ubc_pc == 0)
-                        ubc_usercnt += 1;
-                child->thread.ubc_pc = pc;
-
-                set_tsk_thread_flag(child, TIF_SINGLESTEP);
-                child->exit_code = data;
-                /* give it a chance to run. */
-                wake_up_process(child);
-                ret = 0;
-                break;
-        }
-
 #ifdef CONFIG_SH_DSP
         case PTRACE_GETDSPREGS: {
                 unsigned long dp;
@@ -241,6 +186,29 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 break;
         }
 #endif
+#ifdef CONFIG_BINFMT_ELF_FDPIC
+        case PTRACE_GETFDPIC: {
+                unsigned long tmp = 0;
+
+                switch (addr) {
+                case PTRACE_GETFDPIC_EXEC:
+                        tmp = child->mm->context.exec_fdpic_loadmap;
+                        break;
+                case PTRACE_GETFDPIC_INTERP:
+                        tmp = child->mm->context.interp_fdpic_loadmap;
+                        break;
+                default:
+                        break;
+                }
+
+                ret = 0;
+                if (put_user(tmp, (unsigned long *) data)) {
+                        ret = -EFAULT;
+                        break;
+                }
+                break;
+        }
+#endif
         default:
                 ret = ptrace_request(child, request, addr, data);
                 break;
@@ -249,39 +217,49 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         return ret;
 }
 
-asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
+static inline int audit_arch(void)
 {
-        struct task_struct *tsk = current;
+        int arch = EM_SH;
 
-        if (unlikely(current->audit_context) && entryexit)
-                audit_syscall_exit(AUDITSC_RESULT(regs->regs[0]),
-                                   regs->regs[0]);
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        arch |= __AUDIT_ARCH_LE;
+#endif
 
-        if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
-            !test_thread_flag(TIF_SINGLESTEP))
-                goto out;
-        if (!(tsk->ptrace & PT_PTRACED))
-                goto out;
+        return arch;
+}
 
-        /* the 0x80 provides a way for the tracing parent to distinguish
-           between a syscall stop and SIGTRAP delivery */
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) &&
-                                 !test_thread_flag(TIF_SINGLESTEP) ? 0x80 : 0));
+asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
+{
+        long ret = 0;
 
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (tsk->exit_code) {
-                send_sig(tsk->exit_code, tsk, 1);
-                tsk->exit_code = 0;
-        }
+        secure_computing(regs->regs[0]);
 
-out:
-        if (unlikely(current->audit_context) && !entryexit)
-                audit_syscall_entry(AUDIT_ARCH_SH, regs->regs[3],
+        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
+            tracehook_report_syscall_entry(regs))
+                /*
+                 * Tracing decided this syscall should not happen.
+                 * We'll return a bogus call number to get an ENOSYS
+                 * error, but leave the original number in regs->regs[0].
+                 */
+                ret = -1L;
+
+        if (unlikely(current->audit_context))
+                audit_syscall_entry(audit_arch(), regs->regs[3],
                                     regs->regs[4], regs->regs[5],
                                     regs->regs[6], regs->regs[7]);
 
+        return ret ?: regs->regs[0];
+}
+
+asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
+{
+        int step;
+
+        if (unlikely(current->audit_context))
+                audit_syscall_exit(AUDITSC_RESULT(regs->regs[0]),
+                                   regs->regs[0]);
+
+        step = test_thread_flag(TIF_SINGLESTEP);
+        if (step || test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, step);
 }
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index d453c47dc522..5922edd416db 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -27,6 +27,8 @@
 #include <linux/signal.h>
 #include <linux/syscalls.h>
 #include <linux/audit.h>
+#include <linux/seccomp.h>
+#include <linux/tracehook.h>
 #include <asm/io.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -120,18 +122,23 @@ put_fpu_long(struct task_struct *task, unsigned long addr, unsigned long data)
         return 0;
 }
 
+void user_enable_single_step(struct task_struct *child)
+{
+        struct pt_regs *regs = child->thread.uregs;
+
+        regs->sr |= SR_SSTEP;   /* auto-resetting upon exception */
+}
+
+void user_disable_single_step(struct task_struct *child)
+{
+        regs->sr &= ~SR_SSTEP;
+}
 
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
         int ret;
 
         switch (request) {
-        /* when I and D space are separate, these will need to be fixed. */
-        case PTRACE_PEEKTEXT: /* read word at location addr. */
-        case PTRACE_PEEKDATA:
-                ret = generic_ptrace_peekdata(child, addr, data);
-                break;
-
         /* read the word at location addr in the USER area. */
         case PTRACE_PEEKUSR: {
                 unsigned long tmp;
@@ -154,12 +161,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 break;
         }
 
-        /* when I and D space are separate, this will have to be fixed. */
-        case PTRACE_POKETEXT: /* write the word at location addr. */
-        case PTRACE_POKEDATA:
-                ret = generic_ptrace_pokedata(child, addr, data);
-                break;
-
         case PTRACE_POKEUSR:
                 /* write the word at location addr in the USER area. We must
                    disallow any changes to certain SR bits or u_fpvalid, since
@@ -191,58 +192,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 }
                 break;
 
-        case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
-        case PTRACE_CONT: { /* restart after signal. */
-                ret = -EIO;
-                if (!valid_signal(data))
-                        break;
-                if (request == PTRACE_SYSCALL)
-                        set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-                else
-                        clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-                child->exit_code = data;
-                wake_up_process(child);
-                ret = 0;
-                break;
-        }
-
-/*
- * make the child exit.  Best I can do is send it a sigkill.
- * perhaps it should be put in the status that it wants to
- * exit.
- */
-        case PTRACE_KILL: {
-                ret = 0;
-                if (child->exit_state == EXIT_ZOMBIE)   /* already dead */
-                        break;
-                child->exit_code = SIGKILL;
-                wake_up_process(child);
-                break;
-        }
-
-        case PTRACE_SINGLESTEP: {  /* set the trap flag. */
-                struct pt_regs *regs;
-
-                ret = -EIO;
-                if (!valid_signal(data))
-                        break;
-                clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-                if ((child->ptrace & PT_DTRACE) == 0) {
-                        /* Spurious delayed TF traps may occur */
-                        child->ptrace |= PT_DTRACE;
-                }
-
-                regs = child->thread.uregs;
-
-                regs->sr |= SR_SSTEP;   /* auto-resetting upon exception */
-
-                child->exit_code = data;
-                /* give it a chance to run. */
-                wake_up_process(child);
-                ret = 0;
-                break;
-        }
-
         default:
                 ret = ptrace_request(child, request, addr, data);
                 break;
@@ -273,38 +222,51 @@ asmlinkage int sh64_ptrace(long request, long pid, long addr, long data)
         return sys_ptrace(request, pid, addr, data);
 }
 
-asmlinkage void syscall_trace(struct pt_regs *regs, int entryexit)
+static inline int audit_arch(void)
 {
-        struct task_struct *tsk = current;
+        int arch = EM_SH;
 
-        if (unlikely(current->audit_context) && entryexit)
-                audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]),
-                                   regs->regs[9]);
+#ifdef CONFIG_64BIT
+        arch |= __AUDIT_ARCH_64BIT;
+#endif
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        arch |= __AUDIT_ARCH_LE;
+#endif
 
-        if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
-            !test_thread_flag(TIF_SINGLESTEP))
-                goto out;
-        if (!(tsk->ptrace & PT_PTRACED))
-                goto out;
-
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) &&
-                                !test_thread_flag(TIF_SINGLESTEP) ? 0x80 : 0));
-
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (tsk->exit_code) {
-                send_sig(tsk->exit_code, tsk, 1);
-                tsk->exit_code = 0;
-        }
+        return arch;
+}
 
-out:
-        if (unlikely(current->audit_context) && !entryexit)
-                audit_syscall_entry(AUDIT_ARCH_SH, regs->regs[1],
+asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs)
+{
+        long long ret = 0;
+
+        secure_computing(regs->regs[9]);
+
+        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
+            tracehook_report_syscall_entry(regs))
+                /*
+                 * Tracing decided this syscall should not happen.
+                 * We'll return a bogus call number to get an ENOSYS
+                 * error, but leave the original number in regs->regs[0].
+                 */
+                ret = -1LL;
+
+        if (unlikely(current->audit_context))
+                audit_syscall_entry(audit_arch(), regs->regs[1],
                                     regs->regs[2], regs->regs[3],
                                     regs->regs[4], regs->regs[5]);
+
+        return ret ?: regs->regs[9];
+}
+
+asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
+{
+        if (unlikely(current->audit_context))
+                audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]),
+                                   regs->regs[9]);
+
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, 0);
 }
 
 /* Called with interrupts disabled */
@@ -338,5 +300,5 @@ asmlinkage void do_software_break_point(unsigned long long vec,
  */
 void ptrace_disable(struct task_struct *child)
 {
-        /* nothing to do.. */
+        user_disable_single_step(child);
 }
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index bca2bbc575db..a35207655e7b 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -25,6 +25,7 @@
 #include <linux/smp.h>
 #include <linux/err.h>
 #include <linux/debugfs.h>
+#include <linux/crash_dump.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/page.h>
@@ -286,6 +287,25 @@ static void __init setup_memory(void)
 extern void __init setup_memory(void);
 #endif
 
+/*
+ * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
+ * is_kdump_kernel() to determine if we are booting after a panic. Hence
+ * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
+ */
+#ifdef CONFIG_CRASH_DUMP
+/* elfcorehdr= specifies the location of elf core header
+ * stored by the crashed kernel.
+ */
+static int __init parse_elfcorehdr(char *arg)
+{
+        if (!arg)
+                return -EINVAL;
+        elfcorehdr_addr = memparse(arg, &arg);
+        return 0;
+}
+early_param("elfcorehdr", parse_elfcorehdr);
+#endif
+
 void __init setup_arch(char **cmdline_p)
 {
         enable_mmu();
@@ -398,6 +418,7 @@ const char *get_cpu_subtype(struct sh_cpuinfo *c)
 {
         return cpu_name[c->type];
 }
+EXPORT_SYMBOL(get_cpu_subtype);
 
 #ifdef CONFIG_PROC_FS
 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
@@ -452,6 +473,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         seq_printf(m, "processor\t: %d\n", cpu);
         seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
         seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
+        if (c->cut_major == -1)
+                seq_printf(m, "cut\t\t: unknown\n");
+        else if (c->cut_minor == -1)
+                seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
+        else
+                seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
 
         show_cpuflags(m, c);
 
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index f311551d9a05..51689d29ad45 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -24,6 +24,7 @@
 #include <linux/binfmts.h>
 #include <linux/freezer.h>
 #include <linux/io.h>
+#include <linux/tracehook.h>
 #include <asm/system.h>
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
@@ -33,6 +34,11 @@
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
+struct fdpic_func_descriptor {
+        unsigned long   text;
+        unsigned long   GOT;
+};
+
 /*
  * Atomically swap in the new signal mask, and wait for a signal.
  */
@@ -368,6 +374,7 @@ static int setup_frame(int sig, struct k_sigaction *ka,
                 err |= __put_user(OR_R0_R0, &frame->retcode[6]);
                 err |= __put_user((__NR_sigreturn), &frame->retcode[7]);
                 regs->pr = (unsigned long) frame->retcode;
+                flush_icache_range(regs->pr, regs->pr + sizeof(frame->retcode));
         }
 
         if (err)
@@ -378,18 +385,21 @@ static int setup_frame(int sig, struct k_sigaction *ka,
         regs->regs[4] = signal; /* Arg for signal handler */
         regs->regs[5] = 0;
         regs->regs[6] = (unsigned long) &frame->sc;
-        regs->pc = (unsigned long) ka->sa.sa_handler;
+
+        if (current->personality & FDPIC_FUNCPTRS) {
+                struct fdpic_func_descriptor __user *funcptr =
+                        (struct fdpic_func_descriptor __user *)ka->sa.sa_handler;
+
+                __get_user(regs->pc, &funcptr->text);
+                __get_user(regs->regs[12], &funcptr->GOT);
+        } else
+                regs->pc = (unsigned long)ka->sa.sa_handler;
 
         set_fs(USER_DS);
 
         pr_debug("SIG deliver (%s:%d): sp=%p pc=%08lx pr=%08lx\n",
                  current->comm, task_pid_nr(current), frame, regs->pc, regs->pr);
 
-        flush_cache_sigtramp(regs->pr);
-
-        if ((-regs->pr & (L1_CACHE_BYTES-1)) < sizeof(frame->retcode))
-                flush_cache_sigtramp(regs->pr + L1_CACHE_BYTES);
-
         return 0;
 
 give_sigsegv:
@@ -458,17 +468,22 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         regs->regs[4] = signal; /* Arg for signal handler */
         regs->regs[5] = (unsigned long) &frame->info;
         regs->regs[6] = (unsigned long) &frame->uc;
-        regs->pc = (unsigned long) ka->sa.sa_handler;
+
+        if (current->personality & FDPIC_FUNCPTRS) {
+                struct fdpic_func_descriptor __user *funcptr =
+                        (struct fdpic_func_descriptor __user *)ka->sa.sa_handler;
+
+                __get_user(regs->pc, &funcptr->text);
+                __get_user(regs->regs[12], &funcptr->GOT);
+        } else
+                regs->pc = (unsigned long)ka->sa.sa_handler;
 
         set_fs(USER_DS);
 
         pr_debug("SIG deliver (%s:%d): sp=%p pc=%08lx pr=%08lx\n",
                  current->comm, task_pid_nr(current), frame, regs->pc, regs->pr);
 
-        flush_cache_sigtramp(regs->pr);
-
-        if ((-regs->pr & (L1_CACHE_BYTES-1)) < sizeof(frame->retcode))
-                flush_cache_sigtramp(regs->pr + L1_CACHE_BYTES);
+        flush_icache_range(regs->pr, regs->pr + sizeof(frame->retcode));
 
         return 0;
 
@@ -493,14 +508,13 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
                 switch (regs->regs[0]) {
                         case -ERESTART_RESTARTBLOCK:
                         case -ERESTARTNOHAND:
+                        no_system_call_restart:
                                 regs->regs[0] = -EINTR;
                                 break;
 
                         case -ERESTARTSYS:
-                                if (!(ka->sa.sa_flags & SA_RESTART)) {
-                                        regs->regs[0] = -EINTR;
-                                        break;
-                                }
+                                if (!(ka->sa.sa_flags & SA_RESTART))
+                                        goto no_system_call_restart;
                         /* fallthrough */
                         case -ERESTARTNOINTR:
                                 regs->regs[0] = save_r0;
@@ -575,12 +589,15 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
                          * clear the TIF_RESTORE_SIGMASK flag */
                         if (test_thread_flag(TIF_RESTORE_SIGMASK))
                                 clear_thread_flag(TIF_RESTORE_SIGMASK);
+
+                        tracehook_signal_handler(signr, &info, &ka, regs,
+                                        test_thread_flag(TIF_SINGLESTEP));
                 }
 
                 return;
         }
 
- no_signal:
+no_signal:
         /* Did we come from a system call? */
         if (regs->tra >= 0) {
                 /* Restart the system call - no handlers present */
@@ -604,9 +621,14 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
 }
 
 asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned int save_r0,
-                                 __u32 thread_info_flags)
+                                 unsigned long thread_info_flags)
 {
         /* deal with pending signal delivery */
-        if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
+        if (thread_info_flags & _TIF_SIGPENDING)
                 do_signal(regs, save_r0);
+
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+        }
 }
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 552eb810cd85..1d62dfef77f1 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -22,6 +22,7 @@
 #include <linux/ptrace.h>
 #include <linux/unistd.h>
 #include <linux/stddef.h>
+#include <linux/tracehook.h>
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -42,7 +43,84 @@
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
-asmlinkage int do_signal(struct pt_regs *regs, sigset_t *oldset);
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ *
+ * Note that we go through the signals twice: once to check the signals that
+ * the kernel can handle, and then we build all the user-level signal handling
+ * stack-frames in one go after that.
+ */
+static int do_signal(struct pt_regs *regs, sigset_t *oldset)
+{
+        siginfo_t info;
+        int signr;
+        struct k_sigaction ka;
+
+        /*
+         * We want the common case to go fast, which
+         * is why we may in certain cases get here from
+         * kernel mode. Just return without doing anything
+         * if so.
+         */
+        if (!user_mode(regs))
+                return 1;
+
+        if (try_to_freeze())
+                goto no_signal;
+
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else if (!oldset)
+                oldset = &current->blocked;
+
+        signr = get_signal_to_deliver(&info, &ka, regs, 0);
+
+        if (signr > 0) {
+                /* Whee!  Actually deliver the signal.  */
+                handle_signal(signr, &info, &ka, oldset, regs);
+
+                /*
+                 * If a signal was successfully delivered, the saved sigmask
+                 * is in its frame, and we can clear the TIF_RESTORE_SIGMASK
+                 * flag.
+                 */
+                if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                        clear_thread_flag(TIF_RESTORE_SIGMASK);
+
+                tracehook_signal_handler(signr, &info, &ka, regs, 0);
+                return 1;
+        }
+
+no_signal:
+        /* Did we come from a system call? */
+        if (regs->syscall_nr >= 0) {
+                /* Restart the system call - no handlers present */
+                switch (regs->regs[REG_RET]) {
+                case -ERESTARTNOHAND:
+                case -ERESTARTSYS:
+                case -ERESTARTNOINTR:
+                        /* Decode Syscall # */
+                        regs->regs[REG_RET] = regs->syscall_nr;
+                        regs->pc -= 4;
+                        break;
+
+                case -ERESTART_RESTARTBLOCK:
+                        regs->regs[REG_RET] = __NR_restart_syscall;
+                        regs->pc -= 4;
+                        break;
+                }
+        }
+
+        /* No signal to deliver -- put the saved sigmask back */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
+
+        return 0;
+}
 
 /*
  * Atomically swap in the new signal mask, and wait for a signal.
@@ -643,14 +721,13 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
                 switch (regs->regs[REG_RET]) {
                         case -ERESTART_RESTARTBLOCK:
                         case -ERESTARTNOHAND:
+                        no_system_call_restart:
                                 regs->regs[REG_RET] = -EINTR;
                                 break;
 
                         case -ERESTARTSYS:
-                                if (!(ka->sa.sa_flags & SA_RESTART)) {
-                                        regs->regs[REG_RET] = -EINTR;
-                                        break;
-                                }
+                                if (!(ka->sa.sa_flags & SA_RESTART))
+                                        goto no_system_call_restart;
                         /* fallthrough */
                         case -ERESTARTNOINTR:
                                 /* Decode syscall # */
@@ -673,80 +750,13 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
         spin_unlock_irq(&current->sighand->siglock);
 }
 
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Note that we go through the signals twice: once to check the signals that
- * the kernel can handle, and then we build all the user-level signal handling
- * stack-frames in one go after that.
- */
-int do_signal(struct pt_regs *regs, sigset_t *oldset)
+asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags)
 {
-        siginfo_t info;
-        int signr;
-        struct k_sigaction ka;
-
-        /*
-         * We want the common case to go fast, which
-         * is why we may in certain cases get here from
-         * kernel mode. Just return without doing anything
-         * if so.
-         */
-        if (!user_mode(regs))
-                return 1;
-
-        if (try_to_freeze())
-                goto no_signal;
-
-        if (test_thread_flag(TIF_RESTORE_SIGMASK))
-                oldset = &current->saved_sigmask;
-        else if (!oldset)
-                oldset = &current->blocked;
-
-        signr = get_signal_to_deliver(&info, &ka, regs, 0);
-
-        if (signr > 0) {
-                /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &info, &ka, oldset, regs);
+        if (thread_info_flags & _TIF_SIGPENDING)
+                do_signal(regs, 0);
 
-                /*
-                 * If a signal was successfully delivered, the saved sigmask
-                 * is in its frame, and we can clear the TIF_RESTORE_SIGMASK
-                 * flag.
-                 */
-                if (test_thread_flag(TIF_RESTORE_SIGMASK))
-                        clear_thread_flag(TIF_RESTORE_SIGMASK);
-
-                return 1;
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
         }
-
-no_signal:
-        /* Did we come from a system call? */
-        if (regs->syscall_nr >= 0) {
-                /* Restart the system call - no handlers present */
-                switch (regs->regs[REG_RET]) {
-                case -ERESTARTNOHAND:
-                case -ERESTARTSYS:
-                case -ERESTARTNOINTR:
-                        /* Decode Syscall # */
-                        regs->regs[REG_RET] = regs->syscall_nr;
-                        regs->pc -= 4;
-                        break;
-
-                case -ERESTART_RESTARTBLOCK:
-                        regs->regs[REG_RET] = __NR_restart_syscall;
-                        regs->pc -= 4;
-                        break;
-                }
-        }
-
-        /* No signal to deliver -- put the saved sigmask back */
-        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
-                clear_thread_flag(TIF_RESTORE_SIGMASK);
-                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
-        }
-
-        return 0;
 }
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index a46cc3a41148..0af693e65764 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -343,3 +343,9 @@ ENTRY(sys_call_table)
         .long sys_fallocate
         .long sys_timerfd_settime       /* 325 */
         .long sys_timerfd_gettime
+        .long sys_signalfd4
+        .long sys_eventfd2
+        .long sys_epoll_create1
+        .long sys_dup3                  /* 330 */
+        .long sys_pipe2
+        .long sys_inotify_init1
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index d5d7843aad94..0b436aa3cad7 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -381,3 +381,9 @@ sys_call_table:
         .long sys_fallocate
         .long sys_timerfd_settime
         .long sys_timerfd_gettime
+        .long sys_signalfd4             /* 355 */
+        .long sys_eventfd2
+        .long sys_epoll_create1
+        .long sys_dup3
+        .long sys_pipe2
+        .long sys_inotify_init1         /* 360 */
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
index 7281342c044d..0758b5ee8180 100644
--- a/arch/sh/kernel/time_32.c
+++ b/arch/sh/kernel/time_32.c
@@ -211,7 +211,7 @@ unsigned long sh_hpt_frequency = 0;
 
 #define NSEC_PER_CYC_SHIFT      10
 
-struct clocksource clocksource_sh = {
+static struct clocksource clocksource_sh = {
         .name           = "SuperH",
         .rating         = 200,
         .mask           = CLOCKSOURCE_MASK(32),
diff --git a/arch/sh/kernel/time_64.c b/arch/sh/kernel/time_64.c
index 022a55f1c1d4..791edabf7d83 100644
--- a/arch/sh/kernel/time_64.c
+++ b/arch/sh/kernel/time_64.c
@@ -33,8 +33,8 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
-#include <asm/cpu/registers.h>   /* required by inline __asm__ stmt. */
-#include <asm/cpu/irq.h>
+#include <cpu/registers.h>       /* required by inline __asm__ stmt. */
+#include <cpu/irq.h>
 #include <asm/addrspace.h>
 #include <asm/processor.h>
 #include <asm/uaccess.h>
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index 8935570008d2..1ca9ad49b541 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -209,7 +209,7 @@ static int tmu_timer_init(void)
         return 0;
 }
 
-struct sys_timer_ops tmu_timer_ops = {
+static struct sys_timer_ops tmu_timer_ops = {
         .init           = tmu_timer_init,
         .start          = tmu_timer_start,
         .stop           = tmu_timer_stop,
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index e08b3bfeb656..511a9426cec5 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -43,6 +43,7 @@
 # define TRAP_ILLEGAL_SLOT_INST 6
 # define TRAP_ADDRESS_ERROR     9
 # ifdef CONFIG_CPU_SH2A
+#  define TRAP_FPU_ERROR        13
 #  define TRAP_DIVZERO_ERROR    17
 #  define TRAP_DIVOVF_ERROR     18
 # endif
@@ -851,6 +852,9 @@ void __init trap_init(void)
 #ifdef CONFIG_CPU_SH2A
         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
+#ifdef CONFIG_SH_FPU
+        set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
+#endif
 #endif
 
         /* Setup VBR for boot cpu */
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index ebb55d1149f5..8596cc78e18d 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -2,9 +2,11 @@
 # Makefile for SuperH-specific library files..
 #
 
-lib-y  = delay.o io.o memset.o memmove.o memchr.o \
+lib-y  = delay.o memset.o memmove.o memchr.o \
          checksum.o strlen.o div64.o div64-generic.o
 
+obj-y                           += io.o
+
 memcpy-y                        := memcpy.o
 memcpy-$(CONFIG_CPU_SH4)        := memcpy-sh4.o
 
diff --git a/arch/sh/lib64/panic.c b/arch/sh/lib64/panic.c
index ff559e2a96f7..da32ba7b5fcc 100644
--- a/arch/sh/lib64/panic.c
+++ b/arch/sh/lib64/panic.c
@@ -8,7 +8,7 @@
 
 #include <linux/kernel.h>
 #include <asm/io.h>
-#include <asm/cpu/registers.h>
+#include <cpu/registers.h>
 
 /* THIS IS A PHYSICAL ADDRESS */
 #define HDSP2534_ADDR (0x04002100)
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 5fd218430b19..9c131cac91a4 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -145,25 +145,39 @@ choice
 
 config PAGE_SIZE_4KB
         bool "4kB"
-        depends on !X2TLB
+        depends on !MMU || !X2TLB
         help
           This is the default page size used by all SuperH CPUs.
 
 config PAGE_SIZE_8KB
         bool "8kB"
-        depends on X2TLB
+        depends on !MMU || X2TLB
         help
           This enables 8kB pages as supported by SH-X2 and later MMUs.
 
+config PAGE_SIZE_16KB
+        bool "16kB"
+        depends on !MMU
+        help
+          This enables 16kB pages on MMU-less SH systems.
+
 config PAGE_SIZE_64KB
         bool "64kB"
-        depends on CPU_SH4 || CPU_SH5
+        depends on !MMU || CPU_SH4 || CPU_SH5
         help
           This enables support for 64kB pages, possible on all SH-4
           CPUs and later.
 
 endchoice
 
+config ENTRY_OFFSET
+        hex
+        default "0x00001000" if PAGE_SIZE_4KB
+        default "0x00002000" if PAGE_SIZE_8KB
+        default "0x00004000" if PAGE_SIZE_16KB
+        default "0x00010000" if PAGE_SIZE_64KB
+        default "0x00000000"
+
 choice
         prompt "HugeTLB page size"
         depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU
@@ -223,7 +237,6 @@ choice
 
 config CACHE_WRITEBACK
         bool "Write-back"
-        depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
 
 config CACHE_WRITETHROUGH
         bool "Write-through"
diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32
index e295db60b91b..70e0906023cc 100644
--- a/arch/sh/mm/Makefile_32
+++ b/arch/sh/mm/Makefile_32
@@ -5,12 +5,15 @@
 obj-y                   := init.o extable_32.o consistent.o
 
 ifndef CONFIG_CACHE_OFF
-obj-$(CONFIG_CPU_SH2)           += cache-sh2.o
-obj-$(CONFIG_CPU_SH3)           += cache-sh3.o
-obj-$(CONFIG_CPU_SH4)           += cache-sh4.o
-obj-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
+cache-$(CONFIG_CPU_SH2)         := cache-sh2.o
+cache-$(CONFIG_CPU_SH2A)        := cache-sh2a.o
+cache-$(CONFIG_CPU_SH3)         := cache-sh3.o
+cache-$(CONFIG_CPU_SH4)         := cache-sh4.o
+cache-$(CONFIG_SH7705_CACHE_32KB)       += cache-sh7705.o
 endif
 
+obj-y                   += $(cache-y)
+
 mmu-y                   := tlb-nommu.o pg-nommu.o
 mmu-$(CONFIG_MMU)       := fault_32.o tlbflush_32.o ioremap_32.o
 
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index c5b56d52b7d2..0e189ccd4a77 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -120,7 +120,7 @@ static const struct file_operations cache_debugfs_fops = {
         .open           = cache_debugfs_open,
         .read           = seq_read,
         .llseek         = seq_lseek,
-        .release        = seq_release,
+        .release        = single_release,
 };
 
 static int __init cache_debugfs_init(void)
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 6614033f6be9..c4e80d2b764b 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -2,6 +2,7 @@
  * arch/sh/mm/cache-sh2.c
  *
  * Copyright (C) 2002 Paul Mundt
+ * Copyright (C) 2008 Yoshinori Sato
  *
  * Released under the terms of the GNU GPL v2.0.
  */
@@ -24,8 +25,15 @@ void __flush_wback_region(void *start, int size)
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                /* FIXME cache purge */
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
+                unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
+                int way;
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(addr | (way << 12));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, addr | (way << 12));
+                        }
+                }
         }
 }
 
@@ -37,21 +45,40 @@ void __flush_purge_region(void *start, int size)
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
-        }
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES)
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
 }
 
 void __flush_invalidate_region(void *start, int size)
 {
+#ifdef CONFIG_CACHE_WRITEBACK
+        /*
+         * SH-2 does not support individual line invalidation, only a
+         * global invalidate.
+         */
+        unsigned long ccr;
+        unsigned long flags;
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        ccr = ctrl_inl(CCR);
+        ccr |= CCR_CACHE_INVALIDATE;
+        ctrl_outl(ccr, CCR);
+
+        back_to_cached();
+        local_irq_restore(flags);
+#else
         unsigned long v;
         unsigned long begin, end;
 
         begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
         end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
                 & ~(L1_CACHE_BYTES-1);
-        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
-        }
-}
 
+        for (v = begin; v < end; v+=L1_CACHE_BYTES)
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
+#endif
+}
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
new file mode 100644
index 000000000000..62c0c5f35120
--- /dev/null
+++ b/arch/sh/mm/cache-sh2a.c
@@ -0,0 +1,129 @@
+/*
+ * arch/sh/mm/cache-sh2a.c
+ *
+ * Copyright (C) 2008 Yoshinori Sato
+ *
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+
+#include <asm/cache.h>
+#include <asm/addrspace.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+
+void __flush_wback_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
+                int way;
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(addr | (way << 11));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, addr | (way << 11));
+                        }
+                }
+        }
+
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+void __flush_purge_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+void __flush_invalidate_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+        unsigned long flags;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+        local_irq_save(flags);
+        jump_to_uncached();
+
+#ifdef CONFIG_CACHE_WRITEBACK
+        ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+        /* I-cache invalidate */
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+#else
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                          CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
+        }
+#endif
+        back_to_cached();
+        local_irq_restore(flags);
+}
+
+/* WBack O-Cache and flush I-Cache */
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+        unsigned long v;
+        unsigned long flags;
+
+        start = start & ~(L1_CACHE_BYTES-1);
+        end = (end + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
+
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        for (v = start; v < end; v+=L1_CACHE_BYTES) {
+                unsigned long addr = (v & 0x000007f0);
+                int way;
+                /* O-Cache writeback */
+                for (way = 0; way < 4; way++) {
+                        unsigned long data =  ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
+                                data &= ~SH_CACHE_UPDATED;
+                                ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        }
+                }
+                /* I-Cache invalidate */
+                ctrl_outl(addr,
+                          CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
+        }
+
+        back_to_cached();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 43d7ff6b6ec7..1fdc8d90254a 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -4,6 +4,7 @@
  * Copyright (C) 1999, 2000, 2002  Niibe Yutaka
  * Copyright (C) 2001 - 2007  Paul Mundt
  * Copyright (C) 2003  Richard Curnow
+ * Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -22,6 +23,7 @@
  * entirety.
  */
 #define MAX_DCACHE_PAGES        64      /* XXX: Tune for ways */
+#define MAX_ICACHE_PAGES        32
 
 static void __flush_dcache_segment_1way(unsigned long start,
                                         unsigned long extent);
@@ -178,42 +180,45 @@ void __flush_invalidate_region(void *start, int size)
 /*
  * Write back the range of D-cache, and purge the I-cache.
  *
- * Called from kernel/module.c:sys_init_module and routine for a.out format.
+ * Called from kernel/module.c:sys_init_module and routine for a.out format,
+ * signal handler code and kprobes code
  */
 void flush_icache_range(unsigned long start, unsigned long end)
 {
-        flush_cache_all();
-}
-
-/*
- * Write back the D-cache and purge the I-cache for signal trampoline.
- * .. which happens to be the same behavior as flush_icache_range().
- * So, we simply flush out a line.
- */
-void __uses_jump_to_uncached flush_cache_sigtramp(unsigned long addr)
-{
-        unsigned long v, index;
-        unsigned long flags;
+        int icacheaddr;
+        unsigned long flags, v;
         int i;
 
-        v = addr & ~(L1_CACHE_BYTES-1);
-        asm volatile("ocbwb     %0"
-                     : /* no output */
-                     : "m" (__m(v)));
-
-        index = CACHE_IC_ADDRESS_ARRAY |
-                        (v & boot_cpu_data.icache.entry_mask);
-
-        local_irq_save(flags);
-        jump_to_uncached();
-
-        for (i = 0; i < boot_cpu_data.icache.ways;
-             i++, index += boot_cpu_data.icache.way_incr)
-                ctrl_outl(0, index);    /* Clear out Valid-bit */
-
-        back_to_cached();
-        wmb();
-        local_irq_restore(flags);
+       /* If there are too many pages then just blow the caches */
+        if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
+                flush_cache_all();
+       } else {
+               /* selectively flush d-cache then invalidate the i-cache */
+               /* this is inefficient, so only use for small ranges */
+               start &= ~(L1_CACHE_BYTES-1);
+               end += L1_CACHE_BYTES-1;
+               end &= ~(L1_CACHE_BYTES-1);
+
+               local_irq_save(flags);
+               jump_to_uncached();
+
+               for (v = start; v < end; v+=L1_CACHE_BYTES) {
+                       asm volatile("ocbwb     %0"
+                                    : /* no output */
+                                    : "m" (__m(v)));
+
+                       icacheaddr = CACHE_IC_ADDRESS_ARRAY | (
+                                       v & cpu_data->icache.entry_mask);
+
+                       for (i = 0; i < cpu_data->icache.ways;
+                               i++, icacheaddr += cpu_data->icache.way_incr)
+                                       /* Clear i-cache line valid-bit */
+                                       ctrl_outl(0, icacheaddr);
+               }
+
+                back_to_cached();
+                local_irq_restore(flags);
+        }
 }
 
 static inline void flush_cache_4096(unsigned long start,
diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index d3c33fc5b1c2..b2ce014401b5 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -10,6 +10,7 @@
  * for more details.
  */
 #include <linux/mm.h>
+#include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <asm/cacheflush.h>
 #include <asm/addrspace.h>
@@ -27,21 +28,10 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
                            dma_addr_t *dma_handle, gfp_t gfp)
 {
         void *ret, *ret_nocache;
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
         int order = get_order(size);
 
-        if (mem) {
-                int page = bitmap_find_free_region(mem->bitmap, mem->size,
-                                                     order);
-                if (page >= 0) {
-                        *dma_handle = mem->device_base + (page << PAGE_SHIFT);
-                        ret = mem->virt_base + (page << PAGE_SHIFT);
-                        memset(ret, 0, size);
-                        return ret;
-                }
-                if (mem->flags & DMA_MEMORY_EXCLUSIVE)
-                        return NULL;
-        }
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+                return ret;
 
         ret = (void *)__get_free_pages(gfp, order);
         if (!ret)
@@ -71,11 +61,7 @@ void dma_free_coherent(struct device *dev, size_t size,
         struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
         int order = get_order(size);
 
-        if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) {
-                int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
-
-                bitmap_release_region(mem->bitmap, page, order);
-        } else {
+        if (!dma_release_from_coherent(dev, order, vaddr)) {
                 WARN_ON(irqs_disabled());       /* for portability */
                 BUG_ON(mem && mem->flags & DMA_MEMORY_EXCLUSIVE);
                 free_pages((unsigned long)phys_to_virt(dma_handle), order);
@@ -84,83 +70,6 @@ void dma_free_coherent(struct device *dev, size_t size,
 }
 EXPORT_SYMBOL(dma_free_coherent);
 
-int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
-                                dma_addr_t device_addr, size_t size, int flags)
-{
-        void __iomem *mem_base = NULL;
-        int pages = size >> PAGE_SHIFT;
-        int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
-
-        if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
-                goto out;
-        if (!size)
-                goto out;
-        if (dev->dma_mem)
-                goto out;
-
-        /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
-
-        mem_base = ioremap_nocache(bus_addr, size);
-        if (!mem_base)
-                goto out;
-
-        dev->dma_mem = kmalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
-        if (!dev->dma_mem)
-                goto out;
-        dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-        if (!dev->dma_mem->bitmap)
-                goto free1_out;
-
-        dev->dma_mem->virt_base = mem_base;
-        dev->dma_mem->device_base = device_addr;
-        dev->dma_mem->size = pages;
-        dev->dma_mem->flags = flags;
-
-        if (flags & DMA_MEMORY_MAP)
-                return DMA_MEMORY_MAP;
-
-        return DMA_MEMORY_IO;
-
- free1_out:
-        kfree(dev->dma_mem);
- out:
-        if (mem_base)
-                iounmap(mem_base);
-        return 0;
-}
-EXPORT_SYMBOL(dma_declare_coherent_memory);
-
-void dma_release_declared_memory(struct device *dev)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-
-        if (!mem)
-                return;
-        dev->dma_mem = NULL;
-        iounmap(mem->virt_base);
-        kfree(mem->bitmap);
-        kfree(mem);
-}
-EXPORT_SYMBOL(dma_release_declared_memory);
-
-void *dma_mark_declared_memory_occupied(struct device *dev,
-                                        dma_addr_t device_addr, size_t size)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-        int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT;
-        int pos, err;
-
-        if (!mem)
-                return ERR_PTR(-EINVAL);
-
-        pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
-        err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
-        if (err != 0)
-                return ERR_PTR(err);
-        return mem->virt_base + (pos << PAGE_SHIFT);
-}
-EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
-
 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                     enum dma_data_direction direction)
 {
@@ -185,3 +94,32 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
         }
 }
 EXPORT_SYMBOL(dma_cache_sync);
+
+int platform_resource_setup_memory(struct platform_device *pdev,
+                                   char *name, unsigned long memsize)
+{
+        struct resource *r;
+        dma_addr_t dma_handle;
+        void *buf;
+
+        r = pdev->resource + pdev->num_resources - 1;
+        if (r->flags) {
+                pr_warning("%s: unable to find empty space for resource\n",
+                        name);
+                return -EINVAL;
+        }
+
+        buf = dma_alloc_coherent(NULL, memsize, &dma_handle, GFP_KERNEL);
+        if (!buf) {
+                pr_warning("%s: unable to allocate memory\n", name);
+                return -ENOMEM;
+        }
+
+        memset(buf, 0, memsize);
+
+        r->flags = IORESOURCE_MEM;
+        r->start = dma_handle;
+        r->end = r->start + memsize - 1;
+        r->name = name;
+        return 0;
+}
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index d1fa27594c6e..0c776fdfbdda 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -37,16 +37,12 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
         int fault;
         siginfo_t info;
 
-        trace_hardirqs_on();
-        local_irq_enable();
-
 #ifdef CONFIG_SH_KGDB
         if (kgdb_nofault && kgdb_bus_err_hook)
                 kgdb_bus_err_hook();
 #endif
 
         tsk = current;
-        mm = tsk->mm;
         si_code = SEGV_MAPERR;
 
         if (unlikely(address >= TASK_SIZE)) {
@@ -88,6 +84,14 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
                 return;
         }
 
+        /* Only enable interrupts if they were on before the fault */
+        if ((regs->sr & SR_IMASK) != SR_IMASK) {
+                trace_hardirqs_on();
+                local_irq_enable();
+        }
+
+        mm = tsk->mm;
+
         /*
          * If we're in an interrupt or have no user
          * context, we must not take the fault..
diff --git a/arch/sh/mm/fault_64.c b/arch/sh/mm/fault_64.c
index 399d53710d2f..bd63b961b2a9 100644
--- a/arch/sh/mm/fault_64.c
+++ b/arch/sh/mm/fault_64.c
@@ -39,7 +39,7 @@
 #include <asm/uaccess.h>
 #include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
-#include <asm/cpu/registers.h>
+#include <cpu/registers.h>
 
 /* Callable from fault.c, so not static */
 inline void __do_tlb_refill(unsigned long address,
diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c
index 8c7a9ca79879..38870e0fc182 100644
--- a/arch/sh/mm/pg-sh4.c
+++ b/arch/sh/mm/pg-sh4.c
@@ -111,7 +111,7 @@ EXPORT_SYMBOL(copy_user_highpage);
 /*
  * For SH-4, we have our own implementation for ptep_get_and_clear
  */
-inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
         pte_t pte = *ptep;
 
diff --git a/arch/sh/mm/pg-sh7705.c b/arch/sh/mm/pg-sh7705.c
index 7f885b7f8aff..eaf25147194c 100644
--- a/arch/sh/mm/pg-sh7705.c
+++ b/arch/sh/mm/pg-sh7705.c
@@ -118,7 +118,7 @@ void copy_user_page(void *to, void *from, unsigned long address, struct page *pg
  * For SH7705, we have our own implementation for ptep_get_and_clear
  * Copied from pg-sh4.c
  */
-inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
         pte_t pte = *ptep;
 
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 46911bcbf17b..cef727669c87 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -385,7 +385,7 @@ static const struct file_operations pmb_debugfs_fops = {
         .open           = pmb_debugfs_open,
         .read           = seq_read,
         .llseek         = seq_lseek,
-        .release        = seq_release,
+        .release        = single_release,
 };
 
 static int __init pmb_debugfs_init(void)
diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c
index f34274a1ded3..dae131243bcc 100644
--- a/arch/sh/mm/tlb-sh5.c
+++ b/arch/sh/mm/tlb-sh5.c
@@ -15,9 +15,7 @@
 #include <asm/mmu_context.h>
 
 /**
- * sh64_tlb_init
- *
- * Perform initial setup for the DTLB and ITLB.
+ * sh64_tlb_init - Perform initial setup for the DTLB and ITLB.
  */
 int __init sh64_tlb_init(void)
 {
@@ -46,9 +44,7 @@ int __init sh64_tlb_init(void)
 }
 
 /**
- * sh64_next_free_dtlb_entry
- *
- * Find the next available DTLB entry
+ * sh64_next_free_dtlb_entry - Find the next available DTLB entry
  */
 unsigned long long sh64_next_free_dtlb_entry(void)
 {
@@ -56,9 +52,7 @@ unsigned long long sh64_next_free_dtlb_entry(void)
 }
 
 /**
- * sh64_get_wired_dtlb_entry
- *
- * Allocate a wired (locked-in) entry in the DTLB
+ * sh64_get_wired_dtlb_entry - Allocate a wired (locked-in) entry in the DTLB
  */
 unsigned long long sh64_get_wired_dtlb_entry(void)
 {
@@ -71,12 +65,10 @@ unsigned long long sh64_get_wired_dtlb_entry(void)
 }
 
 /**
- * sh64_put_wired_dtlb_entry
+ * sh64_put_wired_dtlb_entry - Free a wired (locked-in) entry in the DTLB.
  *
  * @entry:      Address of TLB slot.
  *
- * Free a wired (locked-in) entry in the DTLB.
- *
  * Works like a stack, last one to allocate must be first one to free.
  */
 int sh64_put_wired_dtlb_entry(unsigned long long entry)
@@ -115,7 +107,7 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry)
 }
 
 /**
- * sh64_setup_tlb_slot
+ * sh64_setup_tlb_slot - Load up a translation in a wired slot.
  *
  * @config_addr:        Address of TLB slot.
  * @eaddr:              Virtual address.
@@ -154,7 +146,7 @@ inline void sh64_setup_tlb_slot(unsigned long long config_addr,
 }
 
 /**
- * sh64_teardown_tlb_slot
+ * sh64_teardown_tlb_slot - Teardown a translation.
  *
  * @config_addr:        Address of TLB slot.
  *
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 1bba7d36be90..0a11cc08f0a5 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -46,3 +46,7 @@ R2D_1			RTS7751R2D_1
 CAYMAN                  SH_CAYMAN
 SDK7780                 SH_SDK7780
 MIGOR                   SH_MIGOR
+RSK7203                 SH_RSK7203
+AP325RXA                SH_AP325RXA
+SH7763RDP               SH_SH7763RDP
+SH7785LCR               SH_SH7785LCR
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 375de7c6d082..a214002114ed 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -68,6 +68,7 @@ config SPARC
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_ARCH_KGDB if !SMP
+        select HAVE_ARCH_TRACEHOOK
 
 # Identify this as a Sparc32 build
 config SPARC32
diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild
new file mode 100644
index 000000000000..a5f0ce734ff7
--- /dev/null
+++ b/arch/sparc/include/asm/Kbuild
@@ -0,0 +1,45 @@
+# User exported sparc header files
+include include/asm-generic/Kbuild.asm
+
+header-y += ipcbuf_32.h
+header-y += ipcbuf_64.h
+header-y += posix_types_32.h
+header-y += posix_types_64.h
+header-y += ptrace_32.h
+header-y += ptrace_64.h
+header-y += sigcontext_32.h
+header-y += sigcontext_64.h
+header-y += siginfo_32.h
+header-y += siginfo_64.h
+header-y += signal_32.h
+header-y += signal_64.h
+header-y += stat_32.h
+header-y += stat_64.h
+header-y += statfs_32.h
+header-y += statfs_64.h
+header-y += unistd_32.h
+header-y += unistd_64.h
+
+header-y += apc.h
+header-y += asi.h
+header-y += bpp.h
+header-y += display7seg.h
+header-y += envctrl.h
+header-y += fbio.h
+header-y += jsflash.h
+header-y += openprom.h
+header-y += openprom_32.h
+header-y += openprom_64.h
+header-y += openpromio.h
+header-y += perfctr.h
+header-y += psrcompat.h
+header-y += psr.h
+header-y += pstate.h
+header-y += reg.h
+header-y += reg_32.h
+header-y += reg_64.h
+header-y += traps.h
+header-y += uctx.h
+header-y += utrap.h
+header-y += vfc_ioctls.h
+header-y += watchdog.h
diff --git a/arch/sparc/include/asm/agp.h b/arch/sparc/include/asm/agp.h
new file mode 100644
index 000000000000..c2456870b05c
--- /dev/null
+++ b/arch/sparc/include/asm/agp.h
@@ -0,0 +1,20 @@
+#ifndef AGP_H
+#define AGP_H 1
+
+/* dummy for now */
+
+#define map_page_into_agp(page)
+#define unmap_page_from_agp(page)
+#define flush_agp_cache() mb()
+
+/* Convert a physical address to an address suitable for the GART. */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+/* GATT allocation. Returns/accepts GATT kernel virtual address. */
+#define alloc_gatt_pages(order)         \
+        ((char *)__get_free_pages(GFP_KERNEL, (order)))
+#define free_gatt_pages(table, order)   \
+        free_pages((unsigned long)(table), (order))
+
+#endif
diff --git a/arch/sparc/include/asm/apb.h b/arch/sparc/include/asm/apb.h
new file mode 100644
index 000000000000..8f3b57db810f
--- /dev/null
+++ b/arch/sparc/include/asm/apb.h
@@ -0,0 +1,36 @@
+/*
+ * apb.h: Advanced PCI Bridge Configuration Registers and Bits
+ *
+ * Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
+ */
+
+#ifndef _SPARC64_APB_H
+#define _SPARC64_APB_H
+
+#define APB_TICK_REGISTER                       0xb0
+#define APB_INT_ACK                             0xb8
+#define APB_PRIMARY_MASTER_RETRY_LIMIT          0xc0
+#define APB_DMA_ASFR                            0xc8
+#define APB_DMA_AFAR                            0xd0
+#define APB_PIO_TARGET_RETRY_LIMIT              0xd8
+#define APB_PIO_TARGET_LATENCY_TIMER            0xd9
+#define APB_DMA_TARGET_RETRY_LIMIT              0xda
+#define APB_DMA_TARGET_LATENCY_TIMER            0xdb
+#define APB_SECONDARY_MASTER_RETRY_LIMIT        0xdc
+#define APB_SECONDARY_CONTROL                   0xdd
+#define APB_IO_ADDRESS_MAP                      0xde
+#define APB_MEM_ADDRESS_MAP                     0xdf
+
+#define APB_PCI_CONTROL_LOW                     0xe0
+#  define APB_PCI_CTL_LOW_ARB_PARK                      (1 << 21)
+#  define APB_PCI_CTL_LOW_ERRINT_EN                     (1 << 8)
+
+#define APB_PCI_CONTROL_HIGH                    0xe4
+#  define APB_PCI_CTL_HIGH_SERR                         (1 << 2)
+#  define APB_PCI_CTL_HIGH_ARBITER_EN                   (1 << 0)
+
+#define APB_PIO_ASFR                            0xe8
+#define APB_PIO_AFAR                            0xf0
+#define APB_DIAG_REGISTER                       0xf8
+
+#endif /* !(_SPARC64_APB_H) */
diff --git a/arch/sparc/include/asm/apc.h b/arch/sparc/include/asm/apc.h
new file mode 100644
index 000000000000..24e9a7d4d97e
--- /dev/null
+++ b/arch/sparc/include/asm/apc.h
@@ -0,0 +1,64 @@
+/* apc - Driver definitions for power management functions
+ * of Aurora Personality Chip (APC) on SPARCstation-4/5 and 
+ * derivatives
+ *
+ * Copyright (c) 2001 Eric Brower (ebrower@usa.net)
+ *
+ */
+
+#ifndef _SPARC_APC_H
+#define _SPARC_APC_H
+
+#include <linux/ioctl.h>
+
+#define APC_IOC 'A'
+
+#define APCIOCGFANCTL _IOR(APC_IOC, 0x00, int)  /* Get fan speed        */
+#define APCIOCSFANCTL _IOW(APC_IOC, 0x01, int)  /* Set fan speed        */
+
+#define APCIOCGCPWR   _IOR(APC_IOC, 0x02, int)  /* Get CPOWER state     */
+#define APCIOCSCPWR   _IOW(APC_IOC, 0x03, int)  /* Set CPOWER state     */
+
+#define APCIOCGBPORT   _IOR(APC_IOC, 0x04, int) /* Get BPORT state      */
+#define APCIOCSBPORT   _IOW(APC_IOC, 0x05, int) /* Set BPORT state      */
+
+/*
+ * Register offsets
+ */
+#define APC_IDLE_REG    0x00
+#define APC_FANCTL_REG  0x20
+#define APC_CPOWER_REG  0x24
+#define APC_BPORT_REG   0x30
+
+#define APC_REGMASK             0x01
+#define APC_BPMASK              0x03
+
+/*
+ * IDLE - CPU standby values (set to initiate standby)
+ */
+#define APC_IDLE_ON             0x01
+
+/*
+ * FANCTL - Fan speed control state values
+ */
+#define APC_FANCTL_HI   0x00    /* Fan speed high       */
+#define APC_FANCTL_LO   0x01    /* Fan speed low        */
+
+/*
+ * CPWR - Convenience power outlet state values 
+ */
+#define APC_CPOWER_ON   0x00    /* Conv power on        */
+#define APC_CPOWER_OFF  0x01    /* Conv power off       */
+
+/*
+ * BPA/BPB - Read-Write "Bit Ports" state values (reset to 0 at power-on)
+ *
+ * WARNING: Internal usage of bit ports is platform dependent--
+ * don't modify BPORT settings unless you know what you are doing.
+ * 
+ * On SS5 BPA seems to toggle onboard ethernet loopback... -E
+ */
+#define APC_BPORT_A             0x01    /* Bit Port A           */
+#define APC_BPORT_B             0x02    /* Bit Port B           */
+
+#endif /* !(_SPARC_APC_H) */
diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
new file mode 100644
index 000000000000..74703c5ef985
--- /dev/null
+++ b/arch/sparc/include/asm/asi.h
@@ -0,0 +1,262 @@
+#ifndef _SPARC_ASI_H
+#define _SPARC_ASI_H
+
+/* asi.h:  Address Space Identifier values for the sparc.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
+ * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
+ */
+
+/* The first batch are for the sun4c. */
+
+#define ASI_NULL1           0x00
+#define ASI_NULL2           0x01
+
+/* sun4c and sun4 control registers and mmu/vac ops */
+#define ASI_CONTROL         0x02
+#define ASI_SEGMAP          0x03
+#define ASI_PTE             0x04
+#define ASI_HWFLUSHSEG      0x05
+#define ASI_HWFLUSHPAGE     0x06
+#define ASI_REGMAP          0x06
+#define ASI_HWFLUSHCONTEXT  0x07
+
+#define ASI_USERTXT         0x08
+#define ASI_KERNELTXT       0x09
+#define ASI_USERDATA        0x0a
+#define ASI_KERNELDATA      0x0b
+
+/* VAC Cache flushing on sun4c and sun4 */
+#define ASI_FLUSHSEG        0x0c
+#define ASI_FLUSHPG         0x0d
+#define ASI_FLUSHCTX        0x0e
+
+/* SPARCstation-5: only 6 bits are decoded. */
+/* wo = Write Only, rw = Read Write;        */
+/* ss = Single Size, as = All Sizes;        */
+#define ASI_M_RES00         0x00   /* Don't touch... */
+#define ASI_M_UNA01         0x01   /* Same here... */
+#define ASI_M_MXCC          0x02   /* Access to TI VIKING MXCC registers */
+#define ASI_M_FLUSH_PROBE   0x03   /* Reference MMU Flush/Probe; rw, ss */
+#define ASI_M_MMUREGS       0x04   /* MMU Registers; rw, ss */
+#define ASI_M_TLBDIAG       0x05   /* MMU TLB only Diagnostics */
+#define ASI_M_DIAGS         0x06   /* Reference MMU Diagnostics */
+#define ASI_M_IODIAG        0x07   /* MMU I/O TLB only Diagnostics */
+#define ASI_M_USERTXT       0x08   /* Same as ASI_USERTXT; rw, as */
+#define ASI_M_KERNELTXT     0x09   /* Same as ASI_KERNELTXT; rw, as */
+#define ASI_M_USERDATA      0x0A   /* Same as ASI_USERDATA; rw, as */
+#define ASI_M_KERNELDATA    0x0B   /* Same as ASI_KERNELDATA; rw, as */
+#define ASI_M_TXTC_TAG      0x0C   /* Instruction Cache Tag; rw, ss */
+#define ASI_M_TXTC_DATA     0x0D   /* Instruction Cache Data; rw, ss */
+#define ASI_M_DATAC_TAG     0x0E   /* Data Cache Tag; rw, ss */
+#define ASI_M_DATAC_DATA    0x0F   /* Data Cache Data; rw, ss */
+
+/* The following cache flushing ASIs work only with the 'sta'
+ * instruction. Results are unpredictable for 'swap' and 'ldstuba',
+ * so don't do it.
+ */
+
+/* These ASI flushes affect external caches too. */
+#define ASI_M_FLUSH_PAGE    0x10   /* Flush I&D Cache Line (page); wo, ss */
+#define ASI_M_FLUSH_SEG     0x11   /* Flush I&D Cache Line (seg); wo, ss */
+#define ASI_M_FLUSH_REGION  0x12   /* Flush I&D Cache Line (region); wo, ss */
+#define ASI_M_FLUSH_CTX     0x13   /* Flush I&D Cache Line (context); wo, ss */
+#define ASI_M_FLUSH_USER    0x14   /* Flush I&D Cache Line (user); wo, ss */
+
+/* Block-copy operations are available only on certain V8 cpus. */
+#define ASI_M_BCOPY         0x17   /* Block copy */
+
+/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
+#define ASI_M_IFLUSH_PAGE   0x18   /* Flush I Cache Line (page); wo, ss */
+#define ASI_M_IFLUSH_SEG    0x19   /* Flush I Cache Line (seg); wo, ss */
+#define ASI_M_IFLUSH_REGION 0x1A   /* Flush I Cache Line (region); wo, ss */
+#define ASI_M_IFLUSH_CTX    0x1B   /* Flush I Cache Line (context); wo, ss */
+#define ASI_M_IFLUSH_USER   0x1C   /* Flush I Cache Line (user); wo, ss */
+
+/* Block-fill operations are available on certain V8 cpus */
+#define ASI_M_BFILL         0x1F
+
+/* This allows direct access to main memory, actually 0x20 to 0x2f are
+ * the available ASI's for physical ram pass-through, but I don't have
+ * any idea what the other ones do....
+ */
+
+#define ASI_M_BYPASS       0x20   /* Reference MMU bypass; rw, as */
+#define ASI_M_FBMEM        0x29   /* Graphics card frame buffer access */
+#define ASI_M_VMEUS        0x2A   /* VME user 16-bit access */
+#define ASI_M_VMEPS        0x2B   /* VME priv 16-bit access */
+#define ASI_M_VMEUT        0x2C   /* VME user 32-bit access */
+#define ASI_M_VMEPT        0x2D   /* VME priv 32-bit access */
+#define ASI_M_SBUS         0x2E   /* Direct SBus access */
+#define ASI_M_CTL          0x2F   /* Control Space (ECC and MXCC are here) */
+
+
+/* This is ROSS HyperSparc only. */
+#define ASI_M_FLUSH_IWHOLE 0x31   /* Flush entire ICACHE; wo, ss */
+
+/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
+#define ASI_M_IC_FLCLEAR   0x36
+#define ASI_M_DC_FLCLEAR   0x37
+
+#define ASI_M_DCDR         0x39   /* Data Cache Diagnostics Register rw, ss */
+
+#define ASI_M_VIKING_TMP1  0x40   /* Emulation temporary 1 on Viking */
+/* only available on SuperSparc I */
+/* #define ASI_M_VIKING_TMP2  0x41 */  /* Emulation temporary 2 on Viking */
+
+#define ASI_M_ACTION       0x4c   /* Breakpoint Action Register (GNU/Viking) */
+
+/* V9 Architecture mandary ASIs. */
+#define ASI_N                   0x04 /* Nucleus                         */
+#define ASI_NL                  0x0c /* Nucleus, little endian          */
+#define ASI_AIUP                0x10 /* Primary, user                   */
+#define ASI_AIUS                0x11 /* Secondary, user                 */
+#define ASI_AIUPL               0x18 /* Primary, user, little endian    */
+#define ASI_AIUSL               0x19 /* Secondary, user, little endian  */
+#define ASI_P                   0x80 /* Primary, implicit               */
+#define ASI_S                   0x81 /* Secondary, implicit             */
+#define ASI_PNF                 0x82 /* Primary, no fault               */
+#define ASI_SNF                 0x83 /* Secondary, no fault             */
+#define ASI_PL                  0x88 /* Primary, implicit, l-endian     */
+#define ASI_SL                  0x89 /* Secondary, implicit, l-endian   */
+#define ASI_PNFL                0x8a /* Primary, no fault, l-endian     */
+#define ASI_SNFL                0x8b /* Secondary, no fault, l-endian   */
+
+/* SpitFire and later extended ASIs.  The "(III)" marker designates
+ * UltraSparc-III and later specific ASIs.  The "(CMT)" marker designates
+ * Chip Multi Threading specific ASIs.  "(NG)" designates Niagara specific
+ * ASIs, "(4V)" designates SUN4V specific ASIs.
+ */
+#define ASI_PHYS_USE_EC         0x14 /* PADDR, E-cachable               */
+#define ASI_PHYS_BYPASS_EC_E    0x15 /* PADDR, E-bit                    */
+#define ASI_BLK_AIUP_4V         0x16 /* (4V) Prim, user, block ld/st    */
+#define ASI_BLK_AIUS_4V         0x17 /* (4V) Sec, user, block ld/st     */
+#define ASI_PHYS_USE_EC_L       0x1c /* PADDR, E-cachable, little endian*/
+#define ASI_PHYS_BYPASS_EC_E_L  0x1d /* PADDR, E-bit, little endian     */
+#define ASI_BLK_AIUP_L_4V       0x1e /* (4V) Prim, user, block, l-endian*/
+#define ASI_BLK_AIUS_L_4V       0x1f /* (4V) Sec, user, block, l-endian */
+#define ASI_SCRATCHPAD          0x20 /* (4V) Scratch Pad Registers      */
+#define ASI_MMU                 0x21 /* (4V) MMU Context Registers      */
+#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
+                                         * secondary, user
+                                         */
+#define ASI_NUCLEUS_QUAD_LDD    0x24 /* Cachable, qword load            */
+#define ASI_QUEUE               0x25 /* (4V) Interrupt Queue Registers  */
+#define ASI_QUAD_LDD_PHYS_4V    0x26 /* (4V) Physical, qword load       */
+#define ASI_NUCLEUS_QUAD_LDD_L  0x2c /* Cachable, qword load, l-endian  */
+#define ASI_QUAD_LDD_PHYS_L_4V  0x2e /* (4V) Phys, qword load, l-endian */
+#define ASI_PCACHE_DATA_STATUS  0x30 /* (III) PCache data stat RAM diag */
+#define ASI_PCACHE_DATA         0x31 /* (III) PCache data RAM diag      */
+#define ASI_PCACHE_TAG          0x32 /* (III) PCache tag RAM diag       */
+#define ASI_PCACHE_SNOOP_TAG    0x33 /* (III) PCache snoop tag RAM diag */
+#define ASI_QUAD_LDD_PHYS       0x34 /* (III+) PADDR, qword load        */
+#define ASI_WCACHE_VALID_BITS   0x38 /* (III) WCache Valid Bits diag    */
+#define ASI_WCACHE_DATA         0x39 /* (III) WCache data RAM diag      */
+#define ASI_WCACHE_TAG          0x3a /* (III) WCache tag RAM diag       */
+#define ASI_WCACHE_SNOOP_TAG    0x3b /* (III) WCache snoop tag RAM diag */
+#define ASI_QUAD_LDD_PHYS_L     0x3c /* (III+) PADDR, qw-load, l-endian */
+#define ASI_SRAM_FAST_INIT      0x40 /* (III+) Fast SRAM init           */
+#define ASI_CORE_AVAILABLE      0x41 /* (CMT) LP Available              */
+#define ASI_CORE_ENABLE_STAT    0x41 /* (CMT) LP Enable Status          */
+#define ASI_CORE_ENABLE         0x41 /* (CMT) LP Enable RW              */
+#define ASI_XIR_STEERING        0x41 /* (CMT) XIR Steering RW           */
+#define ASI_CORE_RUNNING_RW     0x41 /* (CMT) LP Running RW             */
+#define ASI_CORE_RUNNING_W1S    0x41 /* (CMT) LP Running Write-One Set  */
+#define ASI_CORE_RUNNING_W1C    0x41 /* (CMT) LP Running Write-One Clr  */
+#define ASI_CORE_RUNNING_STAT   0x41 /* (CMT) LP Running Status         */
+#define ASI_CMT_ERROR_STEERING  0x41 /* (CMT) Error Steering RW         */
+#define ASI_DCACHE_INVALIDATE   0x42 /* (III) DCache Invalidate diag    */
+#define ASI_DCACHE_UTAG         0x43 /* (III) DCache uTag diag          */
+#define ASI_DCACHE_SNOOP_TAG    0x44 /* (III) DCache snoop tag RAM diag */
+#define ASI_LSU_CONTROL         0x45 /* Load-store control unit         */
+#define ASI_DCU_CONTROL_REG     0x45 /* (III) DCache Unit Control reg   */
+#define ASI_DCACHE_DATA         0x46 /* DCache data-ram diag access     */
+#define ASI_DCACHE_TAG          0x47 /* Dcache tag/valid ram diag access*/
+#define ASI_INTR_DISPATCH_STAT  0x48 /* IRQ vector dispatch status      */
+#define ASI_INTR_RECEIVE        0x49 /* IRQ vector receive status       */
+#define ASI_UPA_CONFIG          0x4a /* UPA config space                */
+#define ASI_JBUS_CONFIG         0x4a /* (IIIi) JBUS Config Register     */
+#define ASI_SAFARI_CONFIG       0x4a /* (III) Safari Config Register    */
+#define ASI_SAFARI_ADDRESS      0x4a /* (III) Safari Address Register   */
+#define ASI_ESTATE_ERROR_EN     0x4b /* E-cache error enable space      */
+#define ASI_AFSR                0x4c /* Async fault status register     */
+#define ASI_AFAR                0x4d /* Async fault address register    */
+#define ASI_EC_TAG_DATA         0x4e /* E-cache tag/valid ram diag acc  */
+#define ASI_IMMU                0x50 /* Insn-MMU main register space    */
+#define ASI_IMMU_TSB_8KB_PTR    0x51 /* Insn-MMU 8KB TSB pointer reg    */
+#define ASI_IMMU_TSB_64KB_PTR   0x52 /* Insn-MMU 64KB TSB pointer reg   */
+#define ASI_ITLB_DATA_IN        0x54 /* Insn-MMU TLB data in reg        */
+#define ASI_ITLB_DATA_ACCESS    0x55 /* Insn-MMU TLB data access reg    */
+#define ASI_ITLB_TAG_READ       0x56 /* Insn-MMU TLB tag read reg       */
+#define ASI_IMMU_DEMAP          0x57 /* Insn-MMU TLB demap              */
+#define ASI_DMMU                0x58 /* Data-MMU main register space    */
+#define ASI_DMMU_TSB_8KB_PTR    0x59 /* Data-MMU 8KB TSB pointer reg    */
+#define ASI_DMMU_TSB_64KB_PTR   0x5a /* Data-MMU 16KB TSB pointer reg   */
+#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
+#define ASI_DTLB_DATA_IN        0x5c /* Data-MMU TLB data in reg        */
+#define ASI_DTLB_DATA_ACCESS    0x5d /* Data-MMU TLB data access reg    */
+#define ASI_DTLB_TAG_READ       0x5e /* Data-MMU TLB tag read reg       */
+#define ASI_DMMU_DEMAP          0x5f /* Data-MMU TLB demap              */
+#define ASI_IIU_INST_TRAP       0x60 /* (III) Instruction Breakpoint    */
+#define ASI_INTR_ID             0x63 /* (CMT) Interrupt ID register     */
+#define ASI_CORE_ID             0x63 /* (CMT) LP ID register            */
+#define ASI_CESR_ID             0x63 /* (CMT) CESR ID register          */
+#define ASI_IC_INSTR            0x66 /* Insn cache instrucion ram diag  */
+#define ASI_IC_TAG              0x67 /* Insn cache tag/valid ram diag   */
+#define ASI_IC_STAG             0x68 /* (III) Insn cache snoop tag ram  */
+#define ASI_IC_PRE_DECODE       0x6e /* Insn cache pre-decode ram diag  */
+#define ASI_IC_NEXT_FIELD       0x6f /* Insn cache next-field ram diag  */
+#define ASI_BRPRED_ARRAY        0x6f /* (III) Branch Prediction RAM diag*/
+#define ASI_BLK_AIUP            0x70 /* Primary, user, block load/store */
+#define ASI_BLK_AIUS            0x71 /* Secondary, user, block ld/st    */
+#define ASI_MCU_CTRL_REG        0x72 /* (III) Memory controller regs    */
+#define ASI_EC_DATA             0x74 /* (III) E-cache data staging reg  */
+#define ASI_EC_CTRL             0x75 /* (III) E-cache control reg       */
+#define ASI_EC_W                0x76 /* E-cache diag write access       */
+#define ASI_UDB_ERROR_W         0x77 /* External UDB error regs W       */
+#define ASI_UDB_CONTROL_W       0x77 /* External UDB control regs W     */
+#define ASI_INTR_W              0x77 /* IRQ vector dispatch write       */
+#define ASI_INTR_DATAN_W        0x77 /* (III) Out irq vector data reg N */
+#define ASI_INTR_DISPATCH_W     0x77 /* (III) Interrupt vector dispatch */
+#define ASI_BLK_AIUPL           0x78 /* Primary, user, little, blk ld/st*/
+#define ASI_BLK_AIUSL           0x79 /* Secondary, user, little, blk ld/st*/
+#define ASI_EC_R                0x7e /* E-cache diag read access        */
+#define ASI_UDBH_ERROR_R        0x7f /* External UDB error regs rd hi   */
+#define ASI_UDBL_ERROR_R        0x7f /* External UDB error regs rd low  */
+#define ASI_UDBH_CONTROL_R      0x7f /* External UDB control regs rd hi */
+#define ASI_UDBL_CONTROL_R      0x7f /* External UDB control regs rd low*/
+#define ASI_INTR_R              0x7f /* IRQ vector dispatch read        */
+#define ASI_INTR_DATAN_R        0x7f /* (III) In irq vector data reg N  */
+#define ASI_PST8_P              0xc0 /* Primary, 8 8-bit, partial       */
+#define ASI_PST8_S              0xc1 /* Secondary, 8 8-bit, partial     */
+#define ASI_PST16_P             0xc2 /* Primary, 4 16-bit, partial      */
+#define ASI_PST16_S             0xc3 /* Secondary, 4 16-bit, partial    */
+#define ASI_PST32_P             0xc4 /* Primary, 2 32-bit, partial      */
+#define ASI_PST32_S             0xc5 /* Secondary, 2 32-bit, partial    */
+#define ASI_PST8_PL             0xc8 /* Primary, 8 8-bit, partial, L    */
+#define ASI_PST8_SL             0xc9 /* Secondary, 8 8-bit, partial, L  */
+#define ASI_PST16_PL            0xca /* Primary, 4 16-bit, partial, L   */
+#define ASI_PST16_SL            0xcb /* Secondary, 4 16-bit, partial, L */
+#define ASI_PST32_PL            0xcc /* Primary, 2 32-bit, partial, L   */
+#define ASI_PST32_SL            0xcd /* Secondary, 2 32-bit, partial, L */
+#define ASI_FL8_P               0xd0 /* Primary, 1 8-bit, fpu ld/st     */
+#define ASI_FL8_S               0xd1 /* Secondary, 1 8-bit, fpu ld/st   */
+#define ASI_FL16_P              0xd2 /* Primary, 1 16-bit, fpu ld/st    */
+#define ASI_FL16_S              0xd3 /* Secondary, 1 16-bit, fpu ld/st  */
+#define ASI_FL8_PL              0xd8 /* Primary, 1 8-bit, fpu ld/st, L  */
+#define ASI_FL8_SL              0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
+#define ASI_FL16_PL             0xda /* Primary, 1 16-bit, fpu ld/st, L */
+#define ASI_FL16_SL             0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
+#define ASI_BLK_COMMIT_P        0xe0 /* Primary, blk store commit       */
+#define ASI_BLK_COMMIT_S        0xe1 /* Secondary, blk store commit     */
+#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
+                                      * primary, implicit
+                                      */
+#define ASI_BLK_P               0xf0 /* Primary, blk ld/st              */
+#define ASI_BLK_S               0xf1 /* Secondary, blk ld/st            */
+#define ASI_BLK_PL              0xf8 /* Primary, blk ld/st, little      */
+#define ASI_BLK_SL              0xf9 /* Secondary, blk ld/st, little    */
+
+#endif /* _SPARC_ASI_H */
diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h
new file mode 100644
index 000000000000..a619a4d97aae
--- /dev/null
+++ b/arch/sparc/include/asm/asmmacro.h
@@ -0,0 +1,45 @@
+/* asmmacro.h: Assembler macros.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
+ */
+
+#ifndef _SPARC_ASMMACRO_H
+#define _SPARC_ASMMACRO_H
+
+#include <asm/btfixup.h>
+#include <asm/asi.h>
+
+#define GET_PROCESSOR4M_ID(reg) \
+        rd      %tbr, %reg; \
+        srl     %reg, 12, %reg; \
+        and     %reg, 3, %reg;
+
+#define GET_PROCESSOR4D_ID(reg) \
+        lda     [%g0] ASI_M_VIKING_TMP1, %reg;
+
+/* All trap entry points _must_ begin with this macro or else you
+ * lose.  It makes sure the kernel has a proper window so that
+ * c-code can be called.
+ */
+#define SAVE_ALL_HEAD \
+        sethi   %hi(trap_setup), %l4; \
+        jmpl    %l4 + %lo(trap_setup), %l6;
+#define SAVE_ALL \
+        SAVE_ALL_HEAD \
+         nop;
+
+/* All traps low-level code here must end with this macro. */
+#define RESTORE_ALL b ret_trap_entry; clr %l6;
+
+/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
+   likes byte accesses. These are to avoid ifdef mania. */
+
+#ifdef CONFIG_SUN4
+#define lduXa   lduha
+#define stXa    stha
+#else
+#define lduXa   lduba
+#define stXa    stba
+#endif
+
+#endif /* !(_SPARC_ASMMACRO_H) */
diff --git a/arch/sparc/include/asm/atomic.h b/arch/sparc/include/asm/atomic.h
new file mode 100644
index 000000000000..8ff83d8cc33f
--- /dev/null
+++ b/arch/sparc/include/asm/atomic.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_ATOMIC_H
+#define ___ASM_SPARC_ATOMIC_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/atomic_64.h>
+#else
+#include <asm/atomic_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/atomic_32.h b/arch/sparc/include/asm/atomic_32.h
new file mode 100644
index 000000000000..5c944b5a8040
--- /dev/null
+++ b/arch/sparc/include/asm/atomic_32.h
@@ -0,0 +1,165 @@
+/* atomic.h: These still suck, but the I-cache hit rate is higher.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
+ * Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)
+ *
+ * Additions by Keith M Wesolowski (wesolows@foobazco.org) based
+ * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
+ */
+
+#ifndef __ARCH_SPARC_ATOMIC__
+#define __ARCH_SPARC_ATOMIC__
+
+#include <linux/types.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+#ifdef __KERNEL__
+
+#define ATOMIC_INIT(i)  { (i) }
+
+extern int __atomic_add_return(int, atomic_t *);
+extern int atomic_cmpxchg(atomic_t *, int, int);
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+extern int atomic_add_unless(atomic_t *, int, int);
+extern void atomic_set(atomic_t *, int);
+
+#define atomic_read(v)          ((v)->counter)
+
+#define atomic_add(i, v)        ((void)__atomic_add_return( (int)(i), (v)))
+#define atomic_sub(i, v)        ((void)__atomic_add_return(-(int)(i), (v)))
+#define atomic_inc(v)           ((void)__atomic_add_return(        1, (v)))
+#define atomic_dec(v)           ((void)__atomic_add_return(       -1, (v)))
+
+#define atomic_add_return(i, v) (__atomic_add_return( (int)(i), (v)))
+#define atomic_sub_return(i, v) (__atomic_add_return(-(int)(i), (v)))
+#define atomic_inc_return(v)    (__atomic_add_return(        1, (v)))
+#define atomic_dec_return(v)    (__atomic_add_return(       -1, (v)))
+
+#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
+#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+/* This is the old 24-bit implementation.  It's still used internally
+ * by some sparc-specific code, notably the semaphore implementation.
+ */
+typedef struct { volatile int counter; } atomic24_t;
+
+#ifndef CONFIG_SMP
+
+#define ATOMIC24_INIT(i)  { (i) }
+#define atomic24_read(v)          ((v)->counter)
+#define atomic24_set(v, i)        (((v)->counter) = i)
+
+#else
+/* We do the bulk of the actual work out of line in two common
+ * routines in assembler, see arch/sparc/lib/atomic.S for the
+ * "fun" details.
+ *
+ * For SMP the trick is you embed the spin lock byte within
+ * the word, use the low byte so signedness is easily retained
+ * via a quick arithmetic shift.  It looks like this:
+ *
+ *      ----------------------------------------
+ *      | signed 24-bit counter value |  lock  |  atomic_t
+ *      ----------------------------------------
+ *       31                          8 7      0
+ */
+
+#define ATOMIC24_INIT(i)        { ((i) << 8) }
+
+static inline int atomic24_read(const atomic24_t *v)
+{
+        int ret = v->counter;
+
+        while(ret & 0xff)
+                ret = v->counter;
+
+        return ret >> 8;
+}
+
+#define atomic24_set(v, i)      (((v)->counter) = ((i) << 8))
+#endif
+
+static inline int __atomic24_add(int i, atomic24_t *v)
+{
+        register volatile int *ptr asm("g1");
+        register int increment asm("g2");
+        register int tmp1 asm("g3");
+        register int tmp2 asm("g4");
+        register int tmp3 asm("g7");
+
+        ptr = &v->counter;
+        increment = i;
+
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___atomic24_add\n\t"
+        " add   %%o7, 8, %%o7\n"
+        : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
+        : "0" (increment), "r" (ptr)
+        : "memory", "cc");
+
+        return increment;
+}
+
+static inline int __atomic24_sub(int i, atomic24_t *v)
+{
+        register volatile int *ptr asm("g1");
+        register int increment asm("g2");
+        register int tmp1 asm("g3");
+        register int tmp2 asm("g4");
+        register int tmp3 asm("g7");
+
+        ptr = &v->counter;
+        increment = i;
+
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___atomic24_sub\n\t"
+        " add   %%o7, 8, %%o7\n"
+        : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
+        : "0" (increment), "r" (ptr)
+        : "memory", "cc");
+
+        return increment;
+}
+
+#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
+#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
+
+#define atomic24_dec_return(v) __atomic24_sub(1, (v))
+#define atomic24_inc_return(v) __atomic24_add(1, (v))
+
+#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
+#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
+
+#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
+#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
+
+#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
+
+/* Atomic operations are already serializing */
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+
+#endif /* !(__KERNEL__) */
+
+#include <asm-generic/atomic.h>
+#endif /* !(__ARCH_SPARC_ATOMIC__) */
diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h
new file mode 100644
index 000000000000..2c71ec4a3b18
--- /dev/null
+++ b/arch/sparc/include/asm/atomic_64.h
@@ -0,0 +1,128 @@
+/* atomic.h: Thankfully the V9 is at least reasonable for this
+ *           stuff.
+ *
+ * Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __ARCH_SPARC64_ATOMIC__
+#define __ARCH_SPARC64_ATOMIC__
+
+#include <linux/types.h>
+#include <asm/system.h>
+
+typedef struct { volatile int counter; } atomic_t;
+typedef struct { volatile __s64 counter; } atomic64_t;
+
+#define ATOMIC_INIT(i)          { (i) }
+#define ATOMIC64_INIT(i)        { (i) }
+
+#define atomic_read(v)          ((v)->counter)
+#define atomic64_read(v)        ((v)->counter)
+
+#define atomic_set(v, i)        (((v)->counter) = i)
+#define atomic64_set(v, i)      (((v)->counter) = i)
+
+extern void atomic_add(int, atomic_t *);
+extern void atomic64_add(int, atomic64_t *);
+extern void atomic_sub(int, atomic_t *);
+extern void atomic64_sub(int, atomic64_t *);
+
+extern int atomic_add_ret(int, atomic_t *);
+extern int atomic64_add_ret(int, atomic64_t *);
+extern int atomic_sub_ret(int, atomic_t *);
+extern int atomic64_sub_ret(int, atomic64_t *);
+
+#define atomic_dec_return(v) atomic_sub_ret(1, v)
+#define atomic64_dec_return(v) atomic64_sub_ret(1, v)
+
+#define atomic_inc_return(v) atomic_add_ret(1, v)
+#define atomic64_inc_return(v) atomic64_add_ret(1, v)
+
+#define atomic_sub_return(i, v) atomic_sub_ret(i, v)
+#define atomic64_sub_return(i, v) atomic64_sub_ret(i, v)
+
+#define atomic_add_return(i, v) atomic_add_ret(i, v)
+#define atomic64_add_return(i, v) atomic64_add_ret(i, v)
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
+
+#define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)
+#define atomic64_sub_and_test(i, v) (atomic64_sub_ret(i, v) == 0)
+
+#define atomic_dec_and_test(v) (atomic_sub_ret(1, v) == 0)
+#define atomic64_dec_and_test(v) (atomic64_sub_ret(1, v) == 0)
+
+#define atomic_inc(v) atomic_add(1, v)
+#define atomic64_inc(v) atomic64_add(1, v)
+
+#define atomic_dec(v) atomic_sub(1, v)
+#define atomic64_dec(v) atomic64_sub(1, v)
+
+#define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)
+#define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0)
+
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+#define atomic64_cmpxchg(v, o, n) \
+        ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+/* Atomic operations are already serializing */
+#ifdef CONFIG_SMP
+#define smp_mb__before_atomic_dec()     membar_storeload_loadload();
+#define smp_mb__after_atomic_dec()      membar_storeload_storestore();
+#define smp_mb__before_atomic_inc()     membar_storeload_loadload();
+#define smp_mb__after_atomic_inc()      membar_storeload_storestore();
+#else
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+#endif
+
+#include <asm-generic/atomic.h>
+#endif /* !(__ARCH_SPARC64_ATOMIC__) */
diff --git a/arch/sparc/include/asm/auxio.h b/arch/sparc/include/asm/auxio.h
new file mode 100644
index 000000000000..13dc67f03011
--- /dev/null
+++ b/arch/sparc/include/asm/auxio.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_AUXIO_H
+#define ___ASM_SPARC_AUXIO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/auxio_64.h>
+#else
+#include <asm/auxio_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/auxio_32.h b/arch/sparc/include/asm/auxio_32.h
new file mode 100644
index 000000000000..e03e088be95f
--- /dev/null
+++ b/arch/sparc/include/asm/auxio_32.h
@@ -0,0 +1,89 @@
+/*
+ * auxio.h:  Definitions and code for the Auxiliary I/O register.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_AUXIO_H
+#define _SPARC_AUXIO_H
+
+#include <asm/system.h>
+#include <asm/vaddrs.h>
+
+/* This register is an unsigned char in IO space.  It does two things.
+ * First, it is used to control the front panel LED light on machines
+ * that have it (good for testing entry points to trap handlers and irq's)
+ * Secondly, it controls various floppy drive parameters.
+ */
+#define AUXIO_ORMEIN      0xf0    /* All writes must set these bits. */
+#define AUXIO_ORMEIN4M    0xc0    /* sun4m - All writes must set these bits. */
+#define AUXIO_FLPY_DENS   0x20    /* Floppy density, high if set. Read only. */
+#define AUXIO_FLPY_DCHG   0x10    /* A disk change occurred.  Read only. */
+#define AUXIO_EDGE_ON     0x10    /* sun4m - On means Jumper block is in. */
+#define AUXIO_FLPY_DSEL   0x08    /* Drive select/start-motor. Write only. */
+#define AUXIO_LINK_TEST   0x08    /* sun4m - On means TPE Carrier detect. */
+
+/* Set the following to one, then zero, after doing a pseudo DMA transfer. */
+#define AUXIO_FLPY_TCNT   0x04    /* Floppy terminal count. Write only. */
+
+/* Set the following to zero to eject the floppy. */
+#define AUXIO_FLPY_EJCT   0x02    /* Eject floppy disk.  Write only. */
+#define AUXIO_LED         0x01    /* On if set, off if unset. Read/Write */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * NOTE: these routines are implementation dependent--
+ * understand the hardware you are querying!
+ */
+extern void set_auxio(unsigned char bits_on, unsigned char bits_off);
+extern unsigned char get_auxio(void); /* .../asm/floppy.h */
+
+/*
+ * The following routines are provided for driver-compatibility
+ * with sparc64 (primarily sunlance.c)
+ */
+
+#define AUXIO_LTE_ON    1
+#define AUXIO_LTE_OFF   0
+
+/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
+ *
+ * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
+ */
+#define auxio_set_lte(on) \
+do { \
+        if(on) { \
+                set_auxio(AUXIO_LINK_TEST, 0); \
+        } else { \
+                set_auxio(0, AUXIO_LINK_TEST); \
+        } \
+} while (0)
+
+#define AUXIO_LED_ON    1
+#define AUXIO_LED_OFF   0
+
+/* auxio_set_led - Set system front panel LED
+ *
+ * on - AUXIO_LED_ON or AUXIO_LED_OFF
+ */
+#define auxio_set_led(on) \
+do { \
+        if(on) { \
+                set_auxio(AUXIO_LED, 0); \
+        } else { \
+                set_auxio(0, AUXIO_LED); \
+        } \
+} while (0)
+
+#endif /* !(__ASSEMBLY__) */
+
+
+/* AUXIO2 (Power Off Control) */
+extern __volatile__ unsigned char * auxio_power_register;
+
+#define AUXIO_POWER_DETECT_FAILURE      32
+#define AUXIO_POWER_CLEAR_FAILURE       2
+#define AUXIO_POWER_OFF                 1
+
+
+#endif /* !(_SPARC_AUXIO_H) */
diff --git a/arch/sparc/include/asm/auxio_64.h b/arch/sparc/include/asm/auxio_64.h
new file mode 100644
index 000000000000..f61cd1e3e395
--- /dev/null
+++ b/arch/sparc/include/asm/auxio_64.h
@@ -0,0 +1,100 @@
+/*
+ * auxio.h:  Definitions and code for the Auxiliary I/O registers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Refactoring for unified NCR/PCIO support 2002 Eric Brower (ebrower@usa.net)
+ */
+#ifndef _SPARC64_AUXIO_H
+#define _SPARC64_AUXIO_H
+
+/* AUXIO implementations:
+ * sbus-based NCR89C105 "Slavio"
+ *      LED/Floppy (AUX1) register
+ *      Power (AUX2) register
+ *
+ * ebus-based auxio on PCIO
+ *      LED Auxio Register
+ *      Power Auxio Register
+ *
+ * Register definitions from NCR _NCR89C105 Chip Specification_
+ *
+ * SLAVIO AUX1 @ 0x1900000
+ * -------------------------------------------------
+ * | (R) | (R) |  D  | (R) |  E  |  M  |  T  |  L  |
+ * -------------------------------------------------
+ * (R) - bit 7:6,4 are reserved and should be masked in s/w
+ *  D  - Floppy Density Sense (1=high density) R/O
+ *  E  - Link Test Enable, directly reflected on AT&T 7213 LTE pin
+ *  M  - Monitor/Mouse Mux, directly reflected on MON_MSE_MUX pin
+ *  T  - Terminal Count: sends TC pulse to 82077 floppy controller
+ *  L  - System LED on front panel (0=off, 1=on)
+ */
+#define AUXIO_AUX1_MASK         0xc0 /* Mask bits               */
+#define AUXIO_AUX1_FDENS        0x20 /* Floppy Density Sense    */
+#define AUXIO_AUX1_LTE          0x08 /* Link Test Enable        */
+#define AUXIO_AUX1_MMUX         0x04 /* Monitor/Mouse Mux       */
+#define AUXIO_AUX1_FTCNT        0x02 /* Terminal Count,         */
+#define AUXIO_AUX1_LED          0x01 /* System LED              */
+
+/* SLAVIO AUX2 @ 0x1910000
+ * -------------------------------------------------
+ * | (R) | (R) |  D  | (R) | (R) | (R) |  C  |  F  |
+ * -------------------------------------------------
+ * (R) - bits 7:6,4:2 are reserved and should be masked in s/w
+ *  D  - Power Failure Detect (1=power fail)
+ *  C  - Clear Power Failure Detect Int (1=clear)
+ *  F  - Power Off (1=power off)
+ */
+#define AUXIO_AUX2_MASK         0xdc /* Mask Bits               */
+#define AUXIO_AUX2_PFAILDET     0x20 /* Power Fail Detect       */
+#define AUXIO_AUX2_PFAILCLR     0x02 /* Clear Pwr Fail Det Intr */
+#define AUXIO_AUX2_PWR_OFF      0x01 /* Power Off               */
+
+/* Register definitions from Sun Microsystems _PCIO_ p/n 802-7837
+ *
+ * PCIO LED Auxio @ 0x726000
+ * -------------------------------------------------
+ * |             31:1 Unused                 | LED |
+ * -------------------------------------------------
+ * Bits 31:1 unused
+ * LED - System LED on front panel (0=off, 1=on)
+ */
+#define AUXIO_PCIO_LED          0x01 /* System LED              */
+
+/* PCIO Power Auxio @ 0x724000
+ * -------------------------------------------------
+ * |             31:2 Unused           | CPO | SPO |
+ * -------------------------------------------------
+ * Bits 31:2 unused
+ * CPO - Courtesy Power Off (1=off)
+ * SPO - System Power Off   (1=off)
+ */
+#define AUXIO_PCIO_CPWR_OFF     0x02 /* Courtesy Power Off      */
+#define AUXIO_PCIO_SPWR_OFF     0x01 /* System Power Off        */
+
+#ifndef __ASSEMBLY__
+
+extern void __iomem *auxio_register;
+
+#define AUXIO_LTE_ON    1
+#define AUXIO_LTE_OFF   0
+
+/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)
+ *
+ * on - AUXIO_LTE_ON or AUXIO_LTE_OFF
+ */
+extern void auxio_set_lte(int on);
+
+#define AUXIO_LED_ON    1
+#define AUXIO_LED_OFF   0
+
+/* auxio_set_led - Set system front panel LED
+ *
+ * on - AUXIO_LED_ON or AUXIO_LED_OFF
+ */
+extern void auxio_set_led(int on);
+
+#endif /* ifndef __ASSEMBLY__ */
+
+#endif /* !(_SPARC64_AUXIO_H) */
diff --git a/arch/sparc/include/asm/auxvec.h b/arch/sparc/include/asm/auxvec.h
new file mode 100644
index 000000000000..ad6f360261f6
--- /dev/null
+++ b/arch/sparc/include/asm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMSPARC_AUXVEC_H
+#define __ASMSPARC_AUXVEC_H
+
+#endif /* !(__ASMSPARC_AUXVEC_H) */
diff --git a/arch/sparc/include/asm/backoff.h b/arch/sparc/include/asm/backoff.h
new file mode 100644
index 000000000000..fa1fdf67e350
--- /dev/null
+++ b/arch/sparc/include/asm/backoff.h
@@ -0,0 +1,31 @@
+#ifndef _SPARC64_BACKOFF_H
+#define _SPARC64_BACKOFF_H
+
+#define BACKOFF_LIMIT   (4 * 1024)
+
+#ifdef CONFIG_SMP
+
+#define BACKOFF_SETUP(reg)      \
+        mov     1, reg
+
+#define BACKOFF_SPIN(reg, tmp, label)   \
+        mov     reg, tmp; \
+88:     brnz,pt tmp, 88b; \
+         sub    tmp, 1, tmp; \
+        set     BACKOFF_LIMIT, tmp; \
+        cmp     reg, tmp; \
+        bg,pn   %xcc, label; \
+         nop; \
+        ba,pt   %xcc, label; \
+         sllx   reg, 1, reg;
+
+#else
+
+#define BACKOFF_SETUP(reg)
+#define BACKOFF_SPIN(reg, tmp, label) \
+        ba,pt   %xcc, label; \
+         nop;
+
+#endif
+
+#endif /* _SPARC64_BACKOFF_H */
diff --git a/arch/sparc/include/asm/bbc.h b/arch/sparc/include/asm/bbc.h
new file mode 100644
index 000000000000..423a85800aae
--- /dev/null
+++ b/arch/sparc/include/asm/bbc.h
@@ -0,0 +1,225 @@
+/*
+ * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
+ *        systems.
+ *
+ * Copyright (C) 2000 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _SPARC64_BBC_H
+#define _SPARC64_BBC_H
+
+/* Register sizes are indicated by "B" (Byte, 1-byte),
+ * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
+ * "Q" (Quad, 8 bytes) inside brackets.
+ */
+
+#define BBC_AID         0x00    /* [B] Agent ID                 */
+#define BBC_DEVP        0x01    /* [B] Device Present           */
+#define BBC_ARB         0x02    /* [B] Arbitration              */
+#define BBC_QUIESCE     0x03    /* [B] Quiesce                  */
+#define BBC_WDACTION    0x04    /* [B] Watchdog Action          */
+#define BBC_SPG         0x06    /* [B] Soft POR Gen             */
+#define BBC_SXG         0x07    /* [B] Soft XIR Gen             */
+#define BBC_PSRC        0x08    /* [W] POR Source               */
+#define BBC_XSRC        0x0c    /* [B] XIR Source               */
+#define BBC_CSC         0x0d    /* [B] Clock Synthesizers Control*/
+#define BBC_ES_CTRL     0x0e    /* [H] Energy Star Control      */
+#define BBC_ES_ACT      0x10    /* [W] E* Assert Change Time    */
+#define BBC_ES_DACT     0x14    /* [B] E* De-Assert Change Time */
+#define BBC_ES_DABT     0x15    /* [B] E* De-Assert Bypass Time */
+#define BBC_ES_ABT      0x16    /* [H] E* Assert Bypass Time    */
+#define BBC_ES_PST      0x18    /* [W] E* PLL Settle Time       */
+#define BBC_ES_FSL      0x1c    /* [W] E* Frequency Switch Latency*/
+#define BBC_EBUST       0x20    /* [Q] EBUS Timing              */
+#define BBC_JTAG_CMD    0x28    /* [W] JTAG+ Command            */
+#define BBC_JTAG_CTRL   0x2c    /* [B] JTAG+ Control            */
+#define BBC_I2C_SEL     0x2d    /* [B] I2C Selection            */
+#define BBC_I2C_0_S1    0x2e    /* [B] I2C ctrlr-0 reg S1       */
+#define BBC_I2C_0_S0    0x2f    /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
+#define BBC_I2C_1_S1    0x30    /* [B] I2C ctrlr-1 reg S1       */
+#define BBC_I2C_1_S0    0x31    /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
+#define BBC_KBD_BEEP    0x32    /* [B] Keyboard Beep            */
+#define BBC_KBD_BCNT    0x34    /* [W] Keyboard Beep Counter    */
+
+#define BBC_REGS_SIZE   0x40
+
+/* There is a 2K scratch ram area at offset 0x80000 but I doubt
+ * we will use it for anything.
+ */
+
+/* Agent ID register.  This register shows the Safari Agent ID
+ * for the processors.  The value returned depends upon which
+ * cpu is reading the register.
+ */
+#define BBC_AID_ID      0x07    /* Safari ID            */
+#define BBC_AID_RESV    0xf8    /* Reserved             */
+
+/* Device Present register.  One can determine which cpus are actually
+ * present in the machine by interrogating this register.
+ */
+#define BBC_DEVP_CPU0   0x01    /* Processor 0 present  */
+#define BBC_DEVP_CPU1   0x02    /* Processor 1 present  */
+#define BBC_DEVP_CPU2   0x04    /* Processor 2 present  */
+#define BBC_DEVP_CPU3   0x08    /* Processor 3 present  */
+#define BBC_DEVP_RESV   0xf0    /* Reserved             */
+
+/* Arbitration register.  This register is used to block access to
+ * the BBC from a particular cpu.
+ */
+#define BBC_ARB_CPU0    0x01    /* Enable cpu 0 BBC arbitratrion */
+#define BBC_ARB_CPU1    0x02    /* Enable cpu 1 BBC arbitratrion */
+#define BBC_ARB_CPU2    0x04    /* Enable cpu 2 BBC arbitratrion */
+#define BBC_ARB_CPU3    0x08    /* Enable cpu 3 BBC arbitratrion */
+#define BBC_ARB_RESV    0xf0    /* Reserved                      */
+
+/* Quiesce register.  Bus and BBC segments for cpus can be disabled
+ * with this register, ie. for hot plugging.
+ */
+#define BBC_QUIESCE_S02 0x01    /* Quiesce Safari segment for cpu 0 and 2 */
+#define BBC_QUIESCE_S13 0x02    /* Quiesce Safari segment for cpu 1 and 3 */
+#define BBC_QUIESCE_B02 0x04    /* Quiesce BBC segment for cpu 0 and 2    */
+#define BBC_QUIESCE_B13 0x08    /* Quiesce BBC segment for cpu 1 and 3    */
+#define BBC_QUIESCE_FD0 0x10    /* Disable Fatal_Error[0] reporting       */
+#define BBC_QUIESCE_FD1 0x20    /* Disable Fatal_Error[1] reporting       */
+#define BBC_QUIESCE_FD2 0x40    /* Disable Fatal_Error[2] reporting       */
+#define BBC_QUIESCE_FD3 0x80    /* Disable Fatal_Error[3] reporting       */
+
+/* Watchdog Action register.  When the watchdog device timer expires
+ * a line is enabled to the BBC.  The action BBC takes when this line
+ * is asserted can be controlled by this regiser.
+ */
+#define BBC_WDACTION_RST  0x01  /* When set, watchdog causes system reset.
+                                 * When clear, BBC ignores watchdog signal.
+                                 */
+#define BBC_WDACTION_RESV 0xfe  /* Reserved */
+
+/* Soft_POR_GEN register.  The POR (Power On Reset) signal may be asserted
+ * for specific processors or all processors via this register.
+ */
+#define BBC_SPG_CPU0    0x01 /* Assert POR for processor 0      */
+#define BBC_SPG_CPU1    0x02 /* Assert POR for processor 1      */
+#define BBC_SPG_CPU2    0x04 /* Assert POR for processor 2      */
+#define BBC_SPG_CPU3    0x08 /* Assert POR for processor 3      */
+#define BBC_SPG_CPUALL  0x10 /* Reset all processors and reset
+                              * the entire system.
+                              */
+#define BBC_SPG_RESV    0xe0 /* Reserved                        */
+
+/* Soft_XIR_GEN register.  The XIR (eXternally Initiated Reset) signal
+ * may be asserted to specific processors via this register.
+ */
+#define BBC_SXG_CPU0    0x01 /* Assert XIR for processor 0      */
+#define BBC_SXG_CPU1    0x02 /* Assert XIR for processor 1      */
+#define BBC_SXG_CPU2    0x04 /* Assert XIR for processor 2      */
+#define BBC_SXG_CPU3    0x08 /* Assert XIR for processor 3      */
+#define BBC_SXG_RESV    0xf0 /* Reserved                        */
+
+/* POR Source register.  One may identify the cause of the most recent
+ * reset by reading this register.
+ */
+#define BBC_PSRC_SPG0   0x0001 /* CPU 0 reset via BBC_SPG register      */
+#define BBC_PSRC_SPG1   0x0002 /* CPU 1 reset via BBC_SPG register      */
+#define BBC_PSRC_SPG2   0x0004 /* CPU 2 reset via BBC_SPG register      */
+#define BBC_PSRC_SPG3   0x0008 /* CPU 3 reset via BBC_SPG register      */
+#define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register     */
+#define BBC_PSRC_JTAG   0x0020 /* System reset via JTAG+                */
+#define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle   */
+#define BBC_PSRC_PWRUP  0x0080 /* System reset via power-up             */
+#define BBC_PSRC_FE0    0x0100 /* CPU 0 reported Fatal_Error            */
+#define BBC_PSRC_FE1    0x0200 /* CPU 1 reported Fatal_Error            */
+#define BBC_PSRC_FE2    0x0400 /* CPU 2 reported Fatal_Error            */
+#define BBC_PSRC_FE3    0x0800 /* CPU 3 reported Fatal_Error            */
+#define BBC_PSRC_FE4    0x1000 /* Schizo reported Fatal_Error           */
+#define BBC_PSRC_FE5    0x2000 /* Safari device 5 reported Fatal_Error  */
+#define BBC_PSRC_FE6    0x4000 /* CPMS reported Fatal_Error             */
+#define BBC_PSRC_SYNTH  0x8000 /* System reset when on-board clock synthesizers
+                                * were updated.
+                                */
+#define BBC_PSRC_WDT   0x10000 /* System reset via Super I/O watchdog   */
+#define BBC_PSRC_RSC   0x20000 /* System reset via RSC remote monitoring
+                                * device
+                                */
+
+/* XIR Source register.  The source of an XIR event sent to a processor may
+ * be determined via this register.
+ */
+#define BBC_XSRC_SXG0   0x01    /* CPU 0 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG1   0x02    /* CPU 1 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG2   0x04    /* CPU 2 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG3   0x08    /* CPU 3 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_JTAG   0x10    /* All CPUs received XIR via JTAG+         */
+#define BBC_XSRC_W_OR_B 0x20    /* All CPUs received XIR either because:
+                                 * a) Super I/O watchdog fired, or
+                                 * b) XIR push button was activated
+                                 */
+#define BBC_XSRC_RESV   0xc0    /* Reserved                                */
+
+/* Clock Synthesizers Control register.  This register provides the big-bang
+ * programming interface to the two clock synthesizers of the machine.
+ */
+#define BBC_CSC_SLOAD   0x01    /* Directly connected to S_LOAD pins    */
+#define BBC_CSC_SDATA   0x02    /* Directly connected to S_DATA pins    */
+#define BBC_CSC_SCLOCK  0x04    /* Directly connected to S_CLOCK pins   */
+#define BBC_CSC_RESV    0x78    /* Reserved                             */
+#define BBC_CSC_RST     0x80    /* Generate system reset when S_LOAD==1 */
+
+/* Energy Star Control register.  This register is used to generate the
+ * clock frequency change trigger to the main system devices (Schizo and
+ * the processors).  The transition occurs when bits in this register
+ * go from 0 to 1, only one bit must be set at once else no action
+ * occurs.  Basically the sequence of events is:
+ * a) Choose new frequency: full, 1/2 or 1/32
+ * b) Program this desired frequency into the cpus and Schizo.
+ * c) Set the same value in this register.
+ * d) 16 system clocks later, clear this register.
+ */
+#define BBC_ES_CTRL_1_1         0x01    /* Full frequency       */
+#define BBC_ES_CTRL_1_2         0x02    /* 1/2 frequency        */
+#define BBC_ES_CTRL_1_32        0x20    /* 1/32 frequency       */
+#define BBC_ES_RESV             0xdc    /* Reserved             */
+
+/* Energy Star Assert Change Time register.  This determines the number
+ * of BBC clock cycles (which is half the system frequency) between
+ * the detection of FREEZE_ACK being asserted and the assertion of
+ * the CLK_CHANGE_L[2:0] signals.
+ */
+#define BBC_ES_ACT_VAL  0xff
+
+/* Energy Star Assert Bypass Time register.  This determines the number
+ * of BBC clock cycles (which is half the system frequency) between
+ * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
+ * the ESTAR_PLL_BYPASS signal.
+ */
+#define BBC_ES_ABT_VAL  0xffff
+
+/* Energy Star PLL Settle Time register.  This determines the number of
+ * BBC clock cycles (which is half the system frequency) between the
+ * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
+ * signal.
+ */
+#define BBC_ES_PST_VAL  0xffffffff
+
+/* Energy Star Frequency Switch Latency register.  This is the number of
+ * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
+ * edge of the Safari clock at the new frequency.
+ */
+#define BBC_ES_FSL_VAL  0xffffffff
+
+/* Keyboard Beep control register.  This is a simple enabler for the audio
+ * beep sound.
+ */
+#define BBC_KBD_BEEP_ENABLE     0x01 /* Enable beep     */
+#define BBC_KBD_BEEP_RESV       0xfe /* Reserved        */
+
+/* Keyboard Beep Counter register.  There is a free-running counter inside
+ * the BBC which runs at half the system clock.  The bit set in this register
+ * determines when the audio sound is generated.  So for example if bit
+ * 10 is set, the audio beep will oscillate at 1/(2**12).  The keyboard beep
+ * generator automatically selects a different bit to use if the system clock
+ * is changed via Energy Star.
+ */
+#define BBC_KBD_BCNT_BITS       0x0007fc00
+#define BBC_KBC_BCNT_RESV       0xfff803ff
+
+#endif /* _SPARC64_BBC_H */
+
diff --git a/arch/sparc/include/asm/bitext.h b/arch/sparc/include/asm/bitext.h
new file mode 100644
index 000000000000..297b2f2fcb49
--- /dev/null
+++ b/arch/sparc/include/asm/bitext.h
@@ -0,0 +1,27 @@
+/*
+ * bitext.h: Bit string operations on the sparc, specific to architecture.
+ *
+ * Copyright 2002 Pete Zaitcev <zaitcev@yahoo.com>
+ */
+
+#ifndef _SPARC_BITEXT_H
+#define _SPARC_BITEXT_H
+
+#include <linux/spinlock.h>
+
+struct bit_map {
+        spinlock_t lock;
+        unsigned long *map;
+        int size;
+        int used;
+        int last_off;
+        int last_size;
+        int first_free;
+        int num_colors;
+};
+
+extern int bit_map_string_get(struct bit_map *t, int len, int align);
+extern void bit_map_clear(struct bit_map *t, int offset, int len);
+extern void bit_map_init(struct bit_map *t, unsigned long *map, int size);
+
+#endif /* defined(_SPARC_BITEXT_H) */
diff --git a/arch/sparc/include/asm/bitops.h b/arch/sparc/include/asm/bitops.h
new file mode 100644
index 000000000000..b1edd94bd64f
--- /dev/null
+++ b/arch/sparc/include/asm/bitops.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_BITOPS_H
+#define ___ASM_SPARC_BITOPS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/bitops_64.h>
+#else
+#include <asm/bitops_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/bitops_32.h b/arch/sparc/include/asm/bitops_32.h
new file mode 100644
index 000000000000..68b98a7e6454
--- /dev/null
+++ b/arch/sparc/include/asm/bitops_32.h
@@ -0,0 +1,111 @@
+/*
+ * bitops.h: Bit string operations on the Sparc.
+ *
+ * Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright 1996 Eddie C. Dost   (ecd@skynet.be)
+ * Copyright 2001 Anton Blanchard (anton@samba.org)
+ */
+
+#ifndef _SPARC_BITOPS_H
+#define _SPARC_BITOPS_H
+
+#include <linux/compiler.h>
+#include <asm/byteorder.h>
+
+#ifdef __KERNEL__
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+extern unsigned long ___set_bit(unsigned long *addr, unsigned long mask);
+extern unsigned long ___clear_bit(unsigned long *addr, unsigned long mask);
+extern unsigned long ___change_bit(unsigned long *addr, unsigned long mask);
+
+/*
+ * Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
+ * is in the highest of the four bytes and bit '31' is the high bit
+ * within the first byte. Sparc is BIG-Endian. Unless noted otherwise
+ * all bit-ops return 0 if bit was previously clear and != 0 otherwise.
+ */
+static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *ADDR, mask;
+
+        ADDR = ((unsigned long *) addr) + (nr >> 5);
+        mask = 1 << (nr & 31);
+
+        return ___set_bit(ADDR, mask) != 0;
+}
+
+static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *ADDR, mask;
+
+        ADDR = ((unsigned long *) addr) + (nr >> 5);
+        mask = 1 << (nr & 31);
+
+        (void) ___set_bit(ADDR, mask);
+}
+
+static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *ADDR, mask;
+
+        ADDR = ((unsigned long *) addr) + (nr >> 5);
+        mask = 1 << (nr & 31);
+
+        return ___clear_bit(ADDR, mask) != 0;
+}
+
+static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *ADDR, mask;
+
+        ADDR = ((unsigned long *) addr) + (nr >> 5);
+        mask = 1 << (nr & 31);
+
+        (void) ___clear_bit(ADDR, mask);
+}
+
+static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *ADDR, mask;
+
+        ADDR = ((unsigned long *) addr) + (nr >> 5);
+        mask = 1 << (nr & 31);
+
+        return ___change_bit(ADDR, mask) != 0;
+}
+
+static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *ADDR, mask;
+
+        ADDR = ((unsigned long *) addr) + (nr >> 5);
+        mask = 1 << (nr & 31);
+
+        (void) ___change_bit(ADDR, mask);
+}
+
+#include <asm-generic/bitops/non-atomic.h>
+
+#define smp_mb__before_clear_bit()      do { } while(0)
+#define smp_mb__after_clear_bit()       do { } while(0)
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* defined(_SPARC_BITOPS_H) */
diff --git a/arch/sparc/include/asm/bitops_64.h b/arch/sparc/include/asm/bitops_64.h
new file mode 100644
index 000000000000..bb87b8080220
--- /dev/null
+++ b/arch/sparc/include/asm/bitops_64.h
@@ -0,0 +1,107 @@
+/*
+ * bitops.h: Bit string operations on the V9.
+ *
+ * Copyright 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC64_BITOPS_H
+#define _SPARC64_BITOPS_H
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+#include <asm/byteorder.h>
+
+extern int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
+extern int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
+extern int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
+extern void set_bit(unsigned long nr, volatile unsigned long *addr);
+extern void clear_bit(unsigned long nr, volatile unsigned long *addr);
+extern void change_bit(unsigned long nr, volatile unsigned long *addr);
+
+#include <asm-generic/bitops/non-atomic.h>
+
+#ifdef CONFIG_SMP
+#define smp_mb__before_clear_bit()      membar_storeload_loadload()
+#define smp_mb__after_clear_bit()       membar_storeload_storestore()
+#else
+#define smp_mb__before_clear_bit()      barrier()
+#define smp_mb__after_clear_bit()       barrier()
+#endif
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ffs.h>
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#ifdef ULTRA_HAS_POPULATION_COUNT
+
+static inline unsigned int hweight64(unsigned long w)
+{
+        unsigned int res;
+
+        __asm__ ("popc %1,%0" : "=r" (res) : "r" (w));
+        return res;
+}
+
+static inline unsigned int hweight32(unsigned int w)
+{
+        unsigned int res;
+
+        __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffffffff));
+        return res;
+}
+
+static inline unsigned int hweight16(unsigned int w)
+{
+        unsigned int res;
+
+        __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffff));
+        return res;
+}
+
+static inline unsigned int hweight8(unsigned int w)
+{
+        unsigned int res;
+
+        __asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xff));
+        return res;
+}
+
+#else
+
+#include <asm-generic/bitops/hweight.h>
+
+#endif
+#include <asm-generic/bitops/lock.h>
+#endif /* __KERNEL__ */
+
+#include <asm-generic/bitops/find.h>
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/ext2-non-atomic.h>
+
+#define ext2_set_bit_atomic(lock,nr,addr) \
+        test_and_set_bit((nr) ^ 0x38,(unsigned long *)(addr))
+#define ext2_clear_bit_atomic(lock,nr,addr) \
+        test_and_clear_bit((nr) ^ 0x38,(unsigned long *)(addr))
+
+#include <asm-generic/bitops/minix.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* defined(_SPARC64_BITOPS_H) */
diff --git a/arch/sparc/include/asm/bpp.h b/arch/sparc/include/asm/bpp.h
new file mode 100644
index 000000000000..31f515e499a7
--- /dev/null
+++ b/arch/sparc/include/asm/bpp.h
@@ -0,0 +1,73 @@
+#ifndef _SPARC_BPP_H
+#define _SPARC_BPP_H
+
+/*
+ * Copyright (c) 1995 Picture Elements
+ *      Stephen Williams
+ *      Gus Baldauf
+ *
+ * Linux/SPARC port by Peter Zaitcev.
+ * Integration into SPARC tree by Tom Dyas.
+ */
+
+#include  <linux/ioctl.h>
+
+/*
+ * This is a driver that supports IEEE Std 1284-1994 communications
+ * with compliant or compatible devices. It will use whatever features
+ * the device supports, prefering those that are typically faster.
+ *
+ * When the device is opened, it is left in COMPATIBILITY mode, and
+ * writes work like any printer device. The driver only attempt to
+ * negotiate 1284 modes when needed so that plugs can be pulled,
+ * switch boxes switched, etc., without disrupting things. It will
+ * also leave the device in compatibility mode when closed.
+ */
+
+
+
+/*
+ * This driver also supplies ioctls to manually manipulate the
+ * pins. This is great for testing devices, or writing code to deal
+ * with bizzarro-mode of the ACME Special TurboThingy Plus.
+ *
+ * NOTE: These ioctl currently do not interact well with
+ * read/write. Caveat emptor.
+ *
+ * PUT_PINS allows us to assign the sense of all the pins, including
+ * the data pins if being driven by the host. The GET_PINS returns the
+ * pins that the peripheral drives, including data if appropriate.
+ */
+
+# define BPP_PUT_PINS _IOW('B', 1, int)
+# define BPP_GET_PINS _IOR('B', 2, char) /* that's bogus - should've been _IO */
+# define BPP_PUT_DATA _IOW('B', 3, int)
+# define BPP_GET_DATA _IOR('B', 4, char) /* ditto */
+
+/*
+ * Set the data bus to input mode. Disengage the data bin driver and
+ * be prepared to read values from the peripheral. If the arg is 0,
+ * then revert the bus to output mode.
+ */
+# define BPP_SET_INPUT _IOW('B', 5, int)
+
+/*
+ * These bits apply to the PUT operation...
+ */
+# define BPP_PP_nStrobe   0x0001
+# define BPP_PP_nAutoFd   0x0002
+# define BPP_PP_nInit     0x0004
+# define BPP_PP_nSelectIn 0x0008
+
+/*
+ * These apply to the GET operation, which also reads the current value
+ * of the previously put values. A bit mask of these will be returned
+ * as a bit mask in the return code of the ioctl().
+ */
+# define BPP_GP_nAck   0x0100
+# define BPP_GP_Busy   0x0200
+# define BPP_GP_PError 0x0400
+# define BPP_GP_Select 0x0800
+# define BPP_GP_nFault 0x1000
+
+#endif
diff --git a/arch/sparc/include/asm/btfixup.h b/arch/sparc/include/asm/btfixup.h
new file mode 100644
index 000000000000..797722cf69f2
--- /dev/null
+++ b/arch/sparc/include/asm/btfixup.h
@@ -0,0 +1,208 @@
+/*
+ *  asm/btfixup.h:    Macros for boot time linking.
+ *
+ *  Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+ 
+#ifndef _SPARC_BTFIXUP_H
+#define _SPARC_BTFIXUP_H
+
+#include <linux/init.h>
+
+#ifndef __ASSEMBLY__
+
+#ifdef MODULE
+extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void);
+
+#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module()
+#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module()
+#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module()
+#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module()
+#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module
+
+#else
+
+#define BTFIXUP_SIMM13(__name) ___sf_##__name()
+#define BTFIXUP_HALF(__name) ___af_##__name()
+#define BTFIXUP_SETHI(__name) ___hf_##__name()
+#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name)
+/* This must be written in assembly and present in a sethi */
+#define BTFIXUP_BLACKBOX(__name) ___b_##__name
+#endif /* MODULE */
+
+/* Fixup call xx */
+
+#define BTFIXUPDEF_CALL(__type, __name, __args...)                                      \
+        extern __type ___f_##__name(__args);                                            \
+        extern unsigned ___fs_##__name[3];
+#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...)                                \
+        extern __type ___f_##__name(__args) __attribute_const__;                        \
+        extern unsigned ___fs_##__name[3];
+#define BTFIXUP_CALL(__name) ___f_##__name
+
+#define BTFIXUPDEF_BLACKBOX(__name)                                                     \
+        extern unsigned ___bs_##__name[2];
+
+/* Put bottom 13bits into some register variable */
+
+#define BTFIXUPDEF_SIMM13(__name)                                                       \
+        static inline unsigned int ___sf_##__name(void) __attribute_const__;            \
+        extern unsigned ___ss_##__name[2];                                              \
+        static inline unsigned int ___sf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret));                  \
+                return ret;                                                             \
+        }
+#define BTFIXUPDEF_SIMM13_INIT(__name,__val)                                            \
+        static inline unsigned int ___sf_##__name(void) __attribute_const__;            \
+        extern unsigned ___ss_##__name[2];                                              \
+        static inline unsigned int ___sf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
+                return ret;                                                             \
+        }
+
+/* Put either bottom 13 bits, or upper 22 bits into some register variable
+ * (depending on the value, this will lead into sethi FIX, reg; or
+ * mov FIX, reg; )
+ */
+
+#define BTFIXUPDEF_HALF(__name)                                                         \
+        static inline unsigned int ___af_##__name(void) __attribute_const__;            \
+        extern unsigned ___as_##__name[2];                                              \
+        static inline unsigned int ___af_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret));                  \
+                return ret;                                                             \
+        }
+#define BTFIXUPDEF_HALF_INIT(__name,__val)                                              \
+        static inline unsigned int ___af_##__name(void) __attribute_const__;            \
+        extern unsigned ___as_##__name[2];                                              \
+        static inline unsigned int ___af_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
+                return ret;                                                             \
+        }
+
+/* Put upper 22 bits into some register variable */
+
+#define BTFIXUPDEF_SETHI(__name)                                                        \
+        static inline unsigned int ___hf_##__name(void) __attribute_const__;            \
+        extern unsigned ___hs_##__name[2];                                              \
+        static inline unsigned int ___hf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret));               \
+                return ret;                                                             \
+        }
+#define BTFIXUPDEF_SETHI_INIT(__name,__val)                                             \
+        static inline unsigned int ___hf_##__name(void) __attribute_const__;            \
+        extern unsigned ___hs_##__name[2];                                              \
+        static inline unsigned int ___hf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" :         \
+                         "=r"(ret));                                                    \
+                return ret;                                                             \
+        }
+
+/* Put a full 32bit integer into some register variable */
+
+#define BTFIXUPDEF_INT(__name)                                                          \
+        extern unsigned char ___i_##__name;                                             \
+        extern unsigned ___is_##__name[2];
+
+#define BTFIXUPCALL_NORM        0x00000000                      /* Always call */
+#define BTFIXUPCALL_NOP         0x01000000                      /* Possibly optimize to nop */
+#define BTFIXUPCALL_RETINT(i)   (0x90102000|((i) & 0x1fff))     /* Possibly optimize to mov i, %o0 */
+#define BTFIXUPCALL_ORINT(i)    (0x90122000|((i) & 0x1fff))     /* Possibly optimize to or %o0, i, %o0 */
+#define BTFIXUPCALL_RETO0       0x01000000                      /* Return first parameter, actually a nop */
+#define BTFIXUPCALL_ANDNINT(i)  (0x902a2000|((i) & 0x1fff))     /* Possibly optimize to andn %o0, i, %o0 */
+#define BTFIXUPCALL_SWAPO0O1    0xd27a0000                      /* Possibly optimize to swap [%o0],%o1 */
+#define BTFIXUPCALL_SWAPO0G0    0xc07a0000                      /* Possibly optimize to swap [%o0],%g0 */
+#define BTFIXUPCALL_SWAPG1G2    0xc4784000                      /* Possibly optimize to swap [%g1],%g2 */
+#define BTFIXUPCALL_STG0O0      0xc0220000                      /* Possibly optimize to st %g0,[%o0] */
+#define BTFIXUPCALL_STO1O0      0xd2220000                      /* Possibly optimize to st %o1,[%o0] */
+
+#define BTFIXUPSET_CALL(__name, __addr, __insn)                                         \
+        do {                                                                            \
+                ___fs_##__name[0] |= 1;                                                 \
+                ___fs_##__name[1] = (unsigned long)__addr;                              \
+                ___fs_##__name[2] = __insn;                                             \
+        } while (0)
+        
+#define BTFIXUPSET_BLACKBOX(__name, __func)                                             \
+        do {                                                                            \
+                ___bs_##__name[0] |= 1;                                                 \
+                ___bs_##__name[1] = (unsigned long)__func;                              \
+        } while (0)
+        
+#define BTFIXUPCOPY_CALL(__name, __from)                                                \
+        do {                                                                            \
+                ___fs_##__name[0] |= 1;                                                 \
+                ___fs_##__name[1] = ___fs_##__from[1];                                  \
+                ___fs_##__name[2] = ___fs_##__from[2];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_SIMM13(__name, __val)                                                \
+        do {                                                                            \
+                ___ss_##__name[0] |= 1;                                                 \
+                ___ss_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_SIMM13(__name, __from)                                              \
+        do {                                                                            \
+                ___ss_##__name[0] |= 1;                                                 \
+                ___ss_##__name[1] = ___ss_##__from[1];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_HALF(__name, __val)                                                  \
+        do {                                                                            \
+                ___as_##__name[0] |= 1;                                                 \
+                ___as_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_HALF(__name, __from)                                                \
+        do {                                                                            \
+                ___as_##__name[0] |= 1;                                                 \
+                ___as_##__name[1] = ___as_##__from[1];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_SETHI(__name, __val)                                                 \
+        do {                                                                            \
+                ___hs_##__name[0] |= 1;                                                 \
+                ___hs_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_SETHI(__name, __from)                                               \
+        do {                                                                            \
+                ___hs_##__name[0] |= 1;                                                 \
+                ___hs_##__name[1] = ___hs_##__from[1];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_INT(__name, __val)                                                   \
+        do {                                                                            \
+                ___is_##__name[0] |= 1;                                                 \
+                ___is_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_INT(__name, __from)                                                 \
+        do {                                                                            \
+                ___is_##__name[0] |= 1;                                                 \
+                ___is_##__name[1] = ___is_##__from[1];                                  \
+        } while (0)
+        
+#define BTFIXUPVAL_CALL(__name)                                                         \
+        ((unsigned long)___fs_##__name[1])
+        
+extern void btfixup(void);
+
+#else /* __ASSEMBLY__ */
+
+#define BTFIXUP_SETHI(__name)                   %hi(___h_ ## __name)
+#define BTFIXUP_SETHI_INIT(__name,__val)        %hi(___h_ ## __name ## __btset_ ## __val)
+
+#endif /* __ASSEMBLY__ */
+        
+#endif /* !(_SPARC_BTFIXUP_H) */
diff --git a/arch/sparc/include/asm/bug.h b/arch/sparc/include/asm/bug.h
new file mode 100644
index 000000000000..8a59e5a8c217
--- /dev/null
+++ b/arch/sparc/include/asm/bug.h
@@ -0,0 +1,22 @@
+#ifndef _SPARC_BUG_H
+#define _SPARC_BUG_H
+
+#ifdef CONFIG_BUG
+#include <linux/compiler.h>
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+extern void do_BUG(const char *file, int line);
+#define BUG() do {                                      \
+        do_BUG(__FILE__, __LINE__);                     \
+        __builtin_trap();                               \
+} while (0)
+#else
+#define BUG()           __builtin_trap()
+#endif
+
+#define HAVE_ARCH_BUG
+#endif
+
+#include <asm-generic/bug.h>
+
+#endif
diff --git a/arch/sparc/include/asm/bugs.h b/arch/sparc/include/asm/bugs.h
new file mode 100644
index 000000000000..e179bc12f64a
--- /dev/null
+++ b/arch/sparc/include/asm/bugs.h
@@ -0,0 +1,24 @@
+/* include/asm/bugs.h:  Sparc probes for various bugs.
+ *
+ * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifdef CONFIG_SPARC32
+#include <asm/cpudata.h>
+#endif
+
+#ifdef CONFIG_SPARC64
+#include <asm/sstate.h>
+#endif
+
+extern unsigned long loops_per_jiffy;
+
+static void __init check_bugs(void)
+{
+#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP)
+        cpu_data(0).udelay_val = loops_per_jiffy;
+#endif
+#ifdef CONFIG_SPARC64
+        sstate_running();
+#endif
+}
diff --git a/arch/sparc/include/asm/byteorder.h b/arch/sparc/include/asm/byteorder.h
new file mode 100644
index 000000000000..bcd83aa351c5
--- /dev/null
+++ b/arch/sparc/include/asm/byteorder.h
@@ -0,0 +1,57 @@
+#ifndef _SPARC_BYTEORDER_H
+#define _SPARC_BYTEORDER_H
+
+#include <asm/types.h>
+#include <asm/asi.h>
+
+#ifdef __GNUC__
+
+#ifdef CONFIG_SPARC32
+#define __SWAB_64_THRU_32__
+#endif
+
+#ifdef CONFIG_SPARC64
+
+static inline __u16 ___arch__swab16p(const __u16 *addr)
+{
+        __u16 ret;
+
+        __asm__ __volatile__ ("lduha [%1] %2, %0"
+                              : "=r" (ret)
+                              : "r" (addr), "i" (ASI_PL));
+        return ret;
+}
+
+static inline __u32 ___arch__swab32p(const __u32 *addr)
+{
+        __u32 ret;
+
+        __asm__ __volatile__ ("lduwa [%1] %2, %0"
+                              : "=r" (ret)
+                              : "r" (addr), "i" (ASI_PL));
+        return ret;
+}
+
+static inline __u64 ___arch__swab64p(const __u64 *addr)
+{
+        __u64 ret;
+
+        __asm__ __volatile__ ("ldxa [%1] %2, %0"
+                              : "=r" (ret)
+                              : "r" (addr), "i" (ASI_PL));
+        return ret;
+}
+
+#define __arch__swab16p(x) ___arch__swab16p(x)
+#define __arch__swab32p(x) ___arch__swab32p(x)
+#define __arch__swab64p(x) ___arch__swab64p(x)
+
+#endif /* CONFIG_SPARC64 */
+
+#define __BYTEORDER_HAS_U64__
+
+#endif
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _SPARC_BYTEORDER_H */
diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
new file mode 100644
index 000000000000..41f85ae4bd4a
--- /dev/null
+++ b/arch/sparc/include/asm/cache.h
@@ -0,0 +1,138 @@
+/* cache.h:  Cache specific code for the Sparc.  These include flushing
+ *           and direct tag/data line access.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC_CACHE_H
+#define _SPARC_CACHE_H
+
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
+
+#ifdef CONFIG_SPARC32
+#define SMP_CACHE_BYTES_SHIFT 5
+#else
+#define SMP_CACHE_BYTES_SHIFT 6
+#endif
+
+#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
+
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+#ifdef CONFIG_SPARC32
+#include <asm/asi.h>
+
+/* Direct access to the instruction cache is provided through and
+ * alternate address space.  The IDC bit must be off in the ICCR on
+ * HyperSparcs for these accesses to work.  The code below does not do
+ * any checking, the caller must do so.  These routines are for
+ * diagnostics only, but could end up being useful.  Use with care.
+ * Also, you are asking for trouble if you execute these in one of the
+ * three instructions following a %asr/%psr access or modification.
+ */
+
+/* First, cache-tag access. */
+static inline unsigned int get_icache_tag(int setnum, int tagnum)
+{
+        unsigned int vaddr, retval;
+
+        vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (vaddr), "i" (ASI_M_TXTC_TAG));
+        return retval;
+}
+
+static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
+{
+        unsigned int vaddr;
+
+        vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
+        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+                             "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
+                             "memory");
+}
+
+/* Second cache-data access.  The data is returned two-32bit quantities
+ * at a time.
+ */
+static inline void get_icache_data(int setnum, int tagnum, int subblock,
+                                       unsigned int *data)
+{
+        unsigned int value1, value2, vaddr;
+
+        vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
+                ((subblock&0x3) << 3);
+        __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
+                             "or %%g0, %%g2, %0\n\t"
+                             "or %%g0, %%g3, %1\n\t" :
+                             "=r" (value1), "=r" (value2) :
+                             "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
+                             "g2", "g3");
+        data[0] = value1; data[1] = value2;
+}
+
+static inline void put_icache_data(int setnum, int tagnum, int subblock,
+                                       unsigned int *data)
+{
+        unsigned int value1, value2, vaddr;
+
+        vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
+                ((subblock&0x3) << 3);
+        value1 = data[0]; value2 = data[1];
+        __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
+                             "or %%g0, %1, %%g3\n\t"
+                             "stda %%g2, [%2] %3\n\t" : :
+                             "r" (value1), "r" (value2), 
+                             "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
+                             "g2", "g3", "memory" /* no joke */);
+}
+
+/* Different types of flushes with the ICACHE.  Some of the flushes
+ * affect both the ICACHE and the external cache.  Others only clear
+ * the ICACHE entries on the cpu itself.  V8's (most) allow
+ * granularity of flushes on the packet (element in line), whole line,
+ * and entire cache (ie. all lines) level.  The ICACHE only flushes are
+ * ROSS HyperSparc specific and are in ross.h
+ */
+
+/* Flushes which clear out both the on-chip and external caches */
+static inline void flush_ei_page(unsigned int addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
+                             "memory");
+}
+
+static inline void flush_ei_seg(unsigned int addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_SEG) :
+                             "memory");
+}
+
+static inline void flush_ei_region(unsigned int addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_REGION) :
+                             "memory");
+}
+
+static inline void flush_ei_ctx(unsigned int addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_CTX) :
+                             "memory");
+}
+
+static inline void flush_ei_user(unsigned int addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_USER) :
+                             "memory");
+}
+#endif /* CONFIG_SPARC32 */
+
+#endif /* !(_SPARC_CACHE_H) */
diff --git a/arch/sparc/include/asm/cacheflush.h b/arch/sparc/include/asm/cacheflush.h
new file mode 100644
index 000000000000..049168087b19
--- /dev/null
+++ b/arch/sparc/include/asm/cacheflush.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_CACHEFLUSH_H
+#define ___ASM_SPARC_CACHEFLUSH_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/cacheflush_64.h>
+#else
+#include <asm/cacheflush_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/cacheflush_32.h b/arch/sparc/include/asm/cacheflush_32.h
new file mode 100644
index 000000000000..68ac10910271
--- /dev/null
+++ b/arch/sparc/include/asm/cacheflush_32.h
@@ -0,0 +1,85 @@
+#ifndef _SPARC_CACHEFLUSH_H
+#define _SPARC_CACHEFLUSH_H
+
+#include <linux/mm.h>           /* Common for other includes */
+// #include <linux/kernel.h> from pgalloc.h
+// #include <linux/sched.h>  from pgalloc.h
+
+// #include <asm/page.h>
+#include <asm/btfixup.h>
+
+/*
+ * Fine grained cache flushing.
+ */
+#ifdef CONFIG_SMP
+
+BTFIXUPDEF_CALL(void, local_flush_cache_all, void)
+BTFIXUPDEF_CALL(void, local_flush_cache_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, local_flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, local_flush_cache_page, struct vm_area_struct *, unsigned long)
+
+#define local_flush_cache_all() BTFIXUP_CALL(local_flush_cache_all)()
+#define local_flush_cache_mm(mm) BTFIXUP_CALL(local_flush_cache_mm)(mm)
+#define local_flush_cache_range(vma,start,end) BTFIXUP_CALL(local_flush_cache_range)(vma,start,end)
+#define local_flush_cache_page(vma,addr) BTFIXUP_CALL(local_flush_cache_page)(vma,addr)
+
+BTFIXUPDEF_CALL(void, local_flush_page_to_ram, unsigned long)
+BTFIXUPDEF_CALL(void, local_flush_sig_insns, struct mm_struct *, unsigned long)
+
+#define local_flush_page_to_ram(addr) BTFIXUP_CALL(local_flush_page_to_ram)(addr)
+#define local_flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(local_flush_sig_insns)(mm,insn_addr)
+
+extern void smp_flush_cache_all(void);
+extern void smp_flush_cache_mm(struct mm_struct *mm);
+extern void smp_flush_cache_range(struct vm_area_struct *vma,
+                                  unsigned long start,
+                                  unsigned long end);
+extern void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
+
+extern void smp_flush_page_to_ram(unsigned long page);
+extern void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
+
+#endif /* CONFIG_SMP */
+
+BTFIXUPDEF_CALL(void, flush_cache_all, void)
+BTFIXUPDEF_CALL(void, flush_cache_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long)
+
+#define flush_cache_all() BTFIXUP_CALL(flush_cache_all)()
+#define flush_cache_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
+#define flush_cache_dup_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
+#define flush_cache_range(vma,start,end) BTFIXUP_CALL(flush_cache_range)(vma,start,end)
+#define flush_cache_page(vma,addr,pfn) BTFIXUP_CALL(flush_cache_page)(vma,addr)
+#define flush_icache_range(start, end)          do { } while (0)
+#define flush_icache_page(vma, pg)              do { } while (0)
+
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+        } while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+        } while (0)
+
+BTFIXUPDEF_CALL(void, __flush_page_to_ram, unsigned long)
+BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long)
+
+#define __flush_page_to_ram(addr) BTFIXUP_CALL(__flush_page_to_ram)(addr)
+#define flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(flush_sig_insns)(mm,insn_addr)
+
+extern void sparc_flush_page_to_ram(struct page *page);
+
+#define flush_dcache_page(page)                 sparc_flush_page_to_ram(page)
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+#define flush_cache_vmap(start, end)            flush_cache_all()
+#define flush_cache_vunmap(start, end)          flush_cache_all()
+
+#endif /* _SPARC_CACHEFLUSH_H */
diff --git a/arch/sparc/include/asm/cacheflush_64.h b/arch/sparc/include/asm/cacheflush_64.h
new file mode 100644
index 000000000000..c43321729b3b
--- /dev/null
+++ b/arch/sparc/include/asm/cacheflush_64.h
@@ -0,0 +1,76 @@
+#ifndef _SPARC64_CACHEFLUSH_H
+#define _SPARC64_CACHEFLUSH_H
+
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/mm.h>
+
+/* Cache flush operations. */
+
+/* These are the same regardless of whether this is an SMP kernel or not. */
+#define flush_cache_mm(__mm) \
+        do { if ((__mm) == current->mm) flushw_user(); } while(0)
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+#define flush_cache_range(vma, start, end) \
+        flush_cache_mm((vma)->vm_mm)
+#define flush_cache_page(vma, page, pfn) \
+        flush_cache_mm((vma)->vm_mm)
+
+/*
+ * On spitfire, the icache doesn't snoop local stores and we don't
+ * use block commit stores (which invalidate icache lines) during
+ * module load, so we need this.
+ */
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void __flush_icache_page(unsigned long);
+
+extern void __flush_dcache_page(void *addr, int flush_icache);
+extern void flush_dcache_page_impl(struct page *page);
+#ifdef CONFIG_SMP
+extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
+extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
+#else
+#define smp_flush_dcache_page_impl(page,cpu) flush_dcache_page_impl(page)
+#define flush_dcache_page_all(mm,page) flush_dcache_page_impl(page)
+#endif
+
+extern void __flush_dcache_range(unsigned long start, unsigned long end);
+extern void flush_dcache_page(struct page *page);
+
+#define flush_icache_page(vma, pg)      do { } while(0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+
+extern void flush_ptrace_access(struct vm_area_struct *, struct page *,
+                                unsigned long uaddr, void *kaddr,
+                                unsigned long len, int write);
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
+        do {                                                            \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));        \
+                memcpy(dst, src, len);                                  \
+                flush_ptrace_access(vma, page, vaddr, src, len, 0);     \
+        } while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
+        do {                                                            \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));        \
+                memcpy(dst, src, len);                                  \
+                flush_ptrace_access(vma, page, vaddr, dst, len, 1);     \
+        } while (0)
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+#define flush_cache_vmap(start, end)            do { } while (0)
+#define flush_cache_vunmap(start, end)          do { } while (0)
+
+#ifdef CONFIG_DEBUG_PAGEALLOC
+/* internal debugging function */
+void kernel_map_pages(struct page *page, int numpages, int enable);
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _SPARC64_CACHEFLUSH_H */
diff --git a/arch/sparc/include/asm/chafsr.h b/arch/sparc/include/asm/chafsr.h
new file mode 100644
index 000000000000..85c69b38220b
--- /dev/null
+++ b/arch/sparc/include/asm/chafsr.h
@@ -0,0 +1,241 @@
+#ifndef _SPARC64_CHAFSR_H
+#define _SPARC64_CHAFSR_H
+
+/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
+
+/* Comments indicate which processor variants on which the bit definition
+ * is valid.  Codes are:
+ * ch   -->     cheetah
+ * ch+  -->     cheetah plus
+ * jp   -->     jalapeno
+ */
+
+/* All bits of this register except M_SYNDROME and E_SYNDROME are
+ * read, write 1 to clear.  M_SYNDROME and E_SYNDROME are read-only.
+ */
+
+/* Software bit set by linux trap handlers to indicate that the trap was
+ * signalled at %tl >= 1.
+ */
+#define CHAFSR_TL1              (1UL << 63UL) /* n/a */
+
+/* Unmapped error from system bus for prefetch queue or
+ * store queue read operation
+ */
+#define CHPAFSR_DTO             (1UL << 59UL) /* ch+ */
+
+/* Bus error from system bus for prefetch queue or store queue
+ * read operation
+ */
+#define CHPAFSR_DBERR           (1UL << 58UL) /* ch+ */
+
+/* Hardware corrected E-cache Tag ECC error */
+#define CHPAFSR_THCE            (1UL << 57UL) /* ch+ */
+/* System interface protocol error, hw timeout caused */
+#define JPAFSR_JETO             (1UL << 57UL) /* jp */
+
+/* SW handled correctable E-cache Tag ECC error */
+#define CHPAFSR_TSCE            (1UL << 56UL) /* ch+ */
+/* Parity error on system snoop results */
+#define JPAFSR_SCE              (1UL << 56UL) /* jp */
+
+/* Uncorrectable E-cache Tag ECC error */
+#define CHPAFSR_TUE             (1UL << 55UL) /* ch+ */
+/* System interface protocol error, illegal command detected */
+#define JPAFSR_JEIC             (1UL << 55UL) /* jp */
+
+/* Uncorrectable system bus data ECC error due to prefetch
+ * or store fill request
+ */
+#define CHPAFSR_DUE             (1UL << 54UL) /* ch+ */
+/* System interface protocol error, illegal ADTYPE detected */
+#define JPAFSR_JEIT             (1UL << 54UL) /* jp */
+
+/* Multiple errors of the same type have occurred.  This bit is set when
+ * an uncorrectable error or a SW correctable error occurs and the status
+ * bit to report that error is already set.  When multiple errors of
+ * different types are indicated by setting multiple status bits.
+ *
+ * This bit is not set if multiple HW corrected errors with the same
+ * status bit occur, only uncorrectable and SW correctable ones have
+ * this behavior.
+ *
+ * This bit is not set when multiple ECC errors happen within a single
+ * 64-byte system bus transaction.  Only the first ECC error in a 16-byte
+ * subunit will be logged.  All errors in subsequent 16-byte subunits
+ * from the same 64-byte transaction are ignored.
+ */
+#define CHAFSR_ME               (1UL << 53UL) /* ch,ch+,jp */
+
+/* Privileged state error has occurred.  This is a capture of PSTATE.PRIV
+ * at the time the error is detected.
+ */
+#define CHAFSR_PRIV             (1UL << 52UL) /* ch,ch+,jp */
+
+/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
+ * bits and record the most recently detected errors.  Bits accumulate
+ * errors that have been detected since the last write to clear the bit.
+ */
+
+/* System interface protocol error.  The processor asserts its' ERROR
+ * pin when this event occurs and it also logs a specific cause code
+ * into a JTAG scannable flop.
+ */
+#define CHAFSR_PERR             (1UL << 51UL) /* ch,ch+,jp */
+
+/* Internal processor error.  The processor asserts its' ERROR
+ * pin when this event occurs and it also logs a specific cause code
+ * into a JTAG scannable flop.
+ */
+#define CHAFSR_IERR             (1UL << 50UL) /* ch,ch+,jp */
+
+/* System request parity error on incoming address */
+#define CHAFSR_ISAP             (1UL << 49UL) /* ch,ch+,jp */
+
+/* HW Corrected system bus MTAG ECC error */
+#define CHAFSR_EMC              (1UL << 48UL) /* ch,ch+ */
+/* Parity error on L2 cache tag SRAM */
+#define JPAFSR_ETP              (1UL << 48UL) /* jp */
+
+/* Uncorrectable system bus MTAG ECC error */
+#define CHAFSR_EMU              (1UL << 47UL) /* ch,ch+ */
+/* Out of range memory error has occurred */
+#define JPAFSR_OM               (1UL << 47UL) /* jp */
+
+/* HW Corrected system bus data ECC error for read of interrupt vector */
+#define CHAFSR_IVC              (1UL << 46UL) /* ch,ch+ */
+/* Error due to unsupported store */
+#define JPAFSR_UMS              (1UL << 46UL) /* jp */
+
+/* Uncorrectable system bus data ECC error for read of interrupt vector */
+#define CHAFSR_IVU              (1UL << 45UL) /* ch,ch+,jp */
+
+/* Unmapped error from system bus */
+#define CHAFSR_TO               (1UL << 44UL) /* ch,ch+,jp */
+
+/* Bus error response from system bus */
+#define CHAFSR_BERR             (1UL << 43UL) /* ch,ch+,jp */
+
+/* SW Correctable E-cache ECC error for instruction fetch or data access
+ * other than block load.
+ */
+#define CHAFSR_UCC              (1UL << 42UL) /* ch,ch+,jp */
+
+/* Uncorrectable E-cache ECC error for instruction fetch or data access
+ * other than block load.
+ */
+#define CHAFSR_UCU              (1UL << 41UL) /* ch,ch+,jp */
+
+/* Copyout HW Corrected ECC error */
+#define CHAFSR_CPC              (1UL << 40UL) /* ch,ch+,jp */
+
+/* Copyout Uncorrectable ECC error */
+#define CHAFSR_CPU              (1UL << 39UL) /* ch,ch+,jp */
+
+/* HW Corrected ECC error from E-cache for writeback */
+#define CHAFSR_WDC              (1UL << 38UL) /* ch,ch+,jp */
+
+/* Uncorrectable ECC error from E-cache for writeback */
+#define CHAFSR_WDU              (1UL << 37UL) /* ch,ch+,jp */
+
+/* HW Corrected ECC error from E-cache for store merge or block load */
+#define CHAFSR_EDC              (1UL << 36UL) /* ch,ch+,jp */
+
+/* Uncorrectable ECC error from E-cache for store merge or block load */
+#define CHAFSR_EDU              (1UL << 35UL) /* ch,ch+,jp */
+
+/* Uncorrectable system bus data ECC error for read of memory or I/O */
+#define CHAFSR_UE               (1UL << 34UL) /* ch,ch+,jp */
+
+/* HW Corrected system bus data ECC error for read of memory or I/O */
+#define CHAFSR_CE               (1UL << 33UL) /* ch,ch+,jp */
+
+/* Uncorrectable ECC error from remote cache/memory */
+#define JPAFSR_RUE              (1UL << 32UL) /* jp */
+
+/* Correctable ECC error from remote cache/memory */
+#define JPAFSR_RCE              (1UL << 31UL) /* jp */
+
+/* JBUS parity error on returned read data */
+#define JPAFSR_BP               (1UL << 30UL) /* jp */
+
+/* JBUS parity error on data for writeback or block store */
+#define JPAFSR_WBP              (1UL << 29UL) /* jp */
+
+/* Foreign read to DRAM incurring correctable ECC error */
+#define JPAFSR_FRC              (1UL << 28UL) /* jp */
+
+/* Foreign read to DRAM incurring uncorrectable ECC error */
+#define JPAFSR_FRU              (1UL << 27UL) /* jp */
+
+#define CHAFSR_ERRORS           (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
+                                 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
+                                 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
+                                 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
+                                 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
+#define CHPAFSR_ERRORS          (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
+                                 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
+                                 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
+                                 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
+                                 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
+                                 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
+                                 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
+#define JPAFSR_ERRORS           (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
+                                 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
+                                 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
+                                 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
+                                 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
+                                 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
+                                 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
+                                 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
+                                 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
+                                 JPAFSR_FRC | JPAFSR_FRU)
+
+/* Active JBUS request signal when error occurred */
+#define JPAFSR_JBREQ            (0x7UL << 24UL) /* jp */
+#define JPAFSR_JBREQ_SHIFT      24UL
+
+/* L2 cache way information */
+#define JPAFSR_ETW              (0x3UL << 22UL) /* jp */
+#define JPAFSR_ETW_SHIFT        22UL
+
+/* System bus MTAG ECC syndrome.  This field captures the status of the
+ * first occurrence of the highest-priority error according to the M_SYND
+ * overwrite policy.  After the AFSR sticky bit, corresponding to the error
+ * for which the M_SYND is reported, is cleared, the contents of the M_SYND
+ * field will be unchanged by will be unfrozen for further error capture.
+ */
+#define CHAFSR_M_SYNDROME       (0xfUL << 16UL) /* ch,ch+,jp */
+#define CHAFSR_M_SYNDROME_SHIFT 16UL
+
+/* Agenid Id of the foreign device causing the UE/CE errors */
+#define JPAFSR_AID              (0x1fUL << 9UL) /* jp */
+#define JPAFSR_AID_SHIFT        9UL
+
+/* System bus or E-cache data ECC syndrome.  This field captures the status
+ * of the first occurrence of the highest-priority error according to the
+ * E_SYND overwrite policy.  After the AFSR sticky bit, corresponding to the
+ * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
+ * field will be unchanged but will be unfrozen for further error capture.
+ */
+#define CHAFSR_E_SYNDROME       (0x1ffUL << 0UL) /* ch,ch+,jp */
+#define CHAFSR_E_SYNDROME_SHIFT 0UL
+
+/* The AFSR must be explicitly cleared by software, it is not cleared automatically
+ * by a read.  Writes to bits <51:33> with bits set will clear the corresponding
+ * bits in the AFSR.  Bits associated with disrupting traps must be cleared before
+ * interrupts are re-enabled to prevent multiple traps for the same error.  I.e.
+ * PSTATE.IE and AFSR bits control delivery of disrupting traps.
+ *
+ * Since there is only one AFAR, when multiple events have been logged by the
+ * bits in the AFSR, at most one of these events will have its status captured
+ * in the AFAR.  The highest priority of those event bits will get AFAR logging.
+ * The AFAR will be unlocked and available to capture the address of another event
+ * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
+ * cleared.  For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
+ * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
+ * and ready for another event, even though AFSR.CE is still set.  The same rules
+ * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
+ */
+
+#endif /* _SPARC64_CHAFSR_H */
diff --git a/arch/sparc/include/asm/checksum.h b/arch/sparc/include/asm/checksum.h
new file mode 100644
index 000000000000..7ac0d7497bc5
--- /dev/null
+++ b/arch/sparc/include/asm/checksum.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_CHECKSUM_H
+#define ___ASM_SPARC_CHECKSUM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/checksum_64.h>
+#else
+#include <asm/checksum_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/checksum_32.h b/arch/sparc/include/asm/checksum_32.h
new file mode 100644
index 000000000000..bdbda1453aa9
--- /dev/null
+++ b/arch/sparc/include/asm/checksum_32.h
@@ -0,0 +1,241 @@
+#ifndef __SPARC_CHECKSUM_H
+#define __SPARC_CHECKSUM_H
+
+/*  checksum.h:  IP/UDP/TCP checksum routines on the Sparc.
+ *
+ *  Copyright(C) 1995 Linus Torvalds
+ *  Copyright(C) 1995 Miguel de Icaza
+ *  Copyright(C) 1996 David S. Miller
+ *  Copyright(C) 1996 Eddie C. Dost
+ *  Copyright(C) 1997 Jakub Jelinek
+ *
+ * derived from:
+ *      Alpha checksum c-code
+ *      ix86 inline assembly
+ *      RFC1071 Computing the Internet Checksum
+ */
+
+#include <linux/in6.h>
+#include <asm/uaccess.h>
+
+/* computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+extern __wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/* the same as csum_partial, but copies from fs:src while it
+ * checksums
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+extern unsigned int __csum_partial_copy_sparc_generic (const unsigned char *, unsigned char *);
+
+static inline __wsum
+csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
+{
+        register unsigned int ret asm("o0") = (unsigned int)src;
+        register char *d asm("o1") = dst;
+        register int l asm("g1") = len;
+
+        __asm__ __volatile__ (
+                "call __csum_partial_copy_sparc_generic\n\t"
+                " mov %6, %%g7\n"
+        : "=&r" (ret), "=&r" (d), "=&r" (l)
+        : "0" (ret), "1" (d), "2" (l), "r" (sum)
+        : "o2", "o3", "o4", "o5", "o7",
+          "g2", "g3", "g4", "g5", "g7",
+          "memory", "cc");
+        return (__force __wsum)ret;
+}
+
+static inline __wsum
+csum_partial_copy_from_user(const void __user *src, void *dst, int len,
+                            __wsum sum, int *err)
+  {
+        register unsigned long ret asm("o0") = (unsigned long)src;
+        register char *d asm("o1") = dst;
+        register int l asm("g1") = len;
+        register __wsum s asm("g7") = sum;
+
+        __asm__ __volatile__ (
+        ".section __ex_table,#alloc\n\t"
+        ".align 4\n\t"
+        ".word 1f,2\n\t"
+        ".previous\n"
+        "1:\n\t"
+        "call __csum_partial_copy_sparc_generic\n\t"
+        " st %8, [%%sp + 64]\n"
+        : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
+        : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
+        : "o2", "o3", "o4", "o5", "o7", "g2", "g3", "g4", "g5",
+          "cc", "memory");
+        return (__force __wsum)ret;
+}
+
+static inline __wsum
+csum_partial_copy_to_user(const void *src, void __user *dst, int len,
+                          __wsum sum, int *err)
+{
+        if (!access_ok (VERIFY_WRITE, dst, len)) {
+                *err = -EFAULT;
+                return sum;
+        } else {
+                register unsigned long ret asm("o0") = (unsigned long)src;
+                register char __user *d asm("o1") = dst;
+                register int l asm("g1") = len;
+                register __wsum s asm("g7") = sum;
+
+                __asm__ __volatile__ (
+                ".section __ex_table,#alloc\n\t"
+                ".align 4\n\t"
+                ".word 1f,1\n\t"
+                ".previous\n"
+                "1:\n\t"
+                "call __csum_partial_copy_sparc_generic\n\t"
+                " st %8, [%%sp + 64]\n"
+                : "=&r" (ret), "=&r" (d), "=&r" (l), "=&r" (s)
+                : "0" (ret), "1" (d), "2" (l), "3" (s), "r" (err)
+                : "o2", "o3", "o4", "o5", "o7",
+                  "g2", "g3", "g4", "g5",
+                  "cc", "memory");
+                return (__force __wsum)ret;
+        }
+}
+
+#define HAVE_CSUM_COPY_USER
+#define csum_and_copy_to_user csum_partial_copy_to_user
+
+/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
+ * the majority of the time.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+        __sum16 sum;
+
+        /* Note: We must read %2 before we touch %0 for the first time,
+         *       because GCC can legitimately use the same register for
+         *       both operands.
+         */
+        __asm__ __volatile__("sub\t%2, 4, %%g4\n\t"
+                             "ld\t[%1 + 0x00], %0\n\t"
+                             "ld\t[%1 + 0x04], %%g2\n\t"
+                             "ld\t[%1 + 0x08], %%g3\n\t"
+                             "addcc\t%%g2, %0, %0\n\t"
+                             "addxcc\t%%g3, %0, %0\n\t"
+                             "ld\t[%1 + 0x0c], %%g2\n\t"
+                             "ld\t[%1 + 0x10], %%g3\n\t"
+                             "addxcc\t%%g2, %0, %0\n\t"
+                             "addx\t%0, %%g0, %0\n"
+                             "1:\taddcc\t%%g3, %0, %0\n\t"
+                             "add\t%1, 4, %1\n\t"
+                             "addxcc\t%0, %%g0, %0\n\t"
+                             "subcc\t%%g4, 1, %%g4\n\t"
+                             "be,a\t2f\n\t"
+                             "sll\t%0, 16, %%g2\n\t"
+                             "b\t1b\n\t"
+                             "ld\t[%1 + 0x10], %%g3\n"
+                             "2:\taddcc\t%0, %%g2, %%g2\n\t"
+                             "srl\t%%g2, 16, %0\n\t"
+                             "addx\t%0, %%g0, %0\n\t"
+                             "xnor\t%%g0, %0, %0"
+                             : "=r" (sum), "=&r" (iph)
+                             : "r" (ihl), "1" (iph)
+                             : "g2", "g3", "g4", "cc", "memory");
+        return sum;
+}
+
+/* Fold a partial checksum without adding pseudo headers. */
+static inline __sum16 csum_fold(__wsum sum)
+{
+        unsigned int tmp;
+
+        __asm__ __volatile__("addcc\t%0, %1, %1\n\t"
+                             "srl\t%1, 16, %1\n\t"
+                             "addx\t%1, %%g0, %1\n\t"
+                             "xnor\t%%g0, %1, %0"
+                             : "=&r" (sum), "=r" (tmp)
+                             : "0" (sum), "1" ((__force u32)sum<<16)
+                             : "cc");
+        return (__force __sum16)sum;
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                               unsigned short len,
+                                               unsigned short proto,
+                                               __wsum sum)
+{
+        __asm__ __volatile__("addcc\t%1, %0, %0\n\t"
+                             "addxcc\t%2, %0, %0\n\t"
+                             "addxcc\t%3, %0, %0\n\t"
+                             "addx\t%0, %%g0, %0\n\t"
+                             : "=r" (sum), "=r" (saddr)
+                             : "r" (daddr), "r" (proto + len), "0" (sum),
+                               "1" (saddr)
+                             : "cc");
+        return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+
+static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+                                      const struct in6_addr *daddr,
+                                      __u32 len, unsigned short proto,
+                                      __wsum sum)
+{
+        __asm__ __volatile__ (
+                "addcc  %3, %4, %%g4\n\t"
+                "addxcc %5, %%g4, %%g4\n\t"
+                "ld     [%2 + 0x0c], %%g2\n\t"
+                "ld     [%2 + 0x08], %%g3\n\t"
+                "addxcc %%g2, %%g4, %%g4\n\t"
+                "ld     [%2 + 0x04], %%g2\n\t"
+                "addxcc %%g3, %%g4, %%g4\n\t"
+                "ld     [%2 + 0x00], %%g3\n\t"
+                "addxcc %%g2, %%g4, %%g4\n\t"
+                "ld     [%1 + 0x0c], %%g2\n\t"
+                "addxcc %%g3, %%g4, %%g4\n\t"
+                "ld     [%1 + 0x08], %%g3\n\t"
+                "addxcc %%g2, %%g4, %%g4\n\t"
+                "ld     [%1 + 0x04], %%g2\n\t"
+                "addxcc %%g3, %%g4, %%g4\n\t"
+                "ld     [%1 + 0x00], %%g3\n\t"
+                "addxcc %%g2, %%g4, %%g4\n\t"
+                "addxcc %%g3, %%g4, %0\n\t"
+                "addx   0, %0, %0\n"
+                : "=&r" (sum)
+                : "r" (saddr), "r" (daddr),
+                  "r"(htonl(len)), "r"(htonl(proto)), "r"(sum)
+                : "g2", "g3", "g4", "cc");
+
+        return csum_fold(sum);
+}
+
+/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#endif /* !(__SPARC_CHECKSUM_H) */
diff --git a/arch/sparc/include/asm/checksum_64.h b/arch/sparc/include/asm/checksum_64.h
new file mode 100644
index 000000000000..019b9615e43c
--- /dev/null
+++ b/arch/sparc/include/asm/checksum_64.h
@@ -0,0 +1,167 @@
+#ifndef __SPARC64_CHECKSUM_H
+#define __SPARC64_CHECKSUM_H
+
+/*  checksum.h:  IP/UDP/TCP checksum routines on the V9.
+ *
+ *  Copyright(C) 1995 Linus Torvalds
+ *  Copyright(C) 1995 Miguel de Icaza
+ *  Copyright(C) 1996 David S. Miller
+ *  Copyright(C) 1996 Eddie C. Dost
+ *  Copyright(C) 1997 Jakub Jelinek
+ *
+ * derived from:
+ *      Alpha checksum c-code
+ *      ix86 inline assembly
+ *      RFC1071 Computing the Internet Checksum
+ */
+
+#include <linux/in6.h>
+#include <asm/uaccess.h>
+
+/* computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+extern __wsum csum_partial(const void * buff, int len, __wsum sum);
+
+/* the same as csum_partial, but copies from user space while it
+ * checksums
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
+                                              int len, __wsum sum);
+
+extern long __csum_partial_copy_from_user(const void __user *src,
+                                          void *dst, int len,
+                                          __wsum sum);
+
+static inline __wsum
+csum_partial_copy_from_user(const void __user *src,
+                            void *dst, int len,
+                            __wsum sum, int *err)
+{
+        long ret = __csum_partial_copy_from_user(src, dst, len, sum);
+        if (ret < 0)
+                *err = -EFAULT;
+        return (__force __wsum) ret;
+}
+
+/*
+ *      Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+extern long __csum_partial_copy_to_user(const void *src,
+                                        void __user *dst, int len,
+                                          __wsum sum);
+
+static inline __wsum
+csum_and_copy_to_user(const void *src,
+                      void __user *dst, int len,
+                      __wsum sum, int *err)
+{
+        long ret = __csum_partial_copy_to_user(src, dst, len, sum);
+        if (ret < 0)
+                *err = -EFAULT;
+        return (__force __wsum) ret;
+}
+
+/* ihl is always 5 or greater, almost always is 5, and iph is word aligned
+ * the majority of the time.
+ */
+extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+
+/* Fold a partial checksum without adding pseudo headers. */
+static inline __sum16 csum_fold(__wsum sum)
+{
+        unsigned int tmp;
+
+        __asm__ __volatile__(
+"       addcc           %0, %1, %1\n"
+"       srl             %1, 16, %1\n"
+"       addc            %1, %%g0, %1\n"
+"       xnor            %%g0, %1, %0\n"
+        : "=&r" (sum), "=r" (tmp)
+        : "0" (sum), "1" ((__force u32)sum<<16)
+        : "cc");
+        return (__force __sum16)sum;
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
+                                               unsigned int len,
+                                               unsigned short proto,
+                                               __wsum sum)
+{
+        __asm__ __volatile__(
+"       addcc           %1, %0, %0\n"
+"       addccc          %2, %0, %0\n"
+"       addccc          %3, %0, %0\n"
+"       addc            %0, %%g0, %0\n"
+        : "=r" (sum), "=r" (saddr)
+        : "r" (daddr), "r" (proto + len), "0" (sum), "1" (saddr)
+        : "cc");
+        return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+
+static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+                                      const struct in6_addr *daddr,
+                                      __u32 len, unsigned short proto,
+                                      __wsum sum)
+{
+        __asm__ __volatile__ (
+"       addcc           %3, %4, %%g7\n"
+"       addccc          %5, %%g7, %%g7\n"
+"       lduw            [%2 + 0x0c], %%g2\n"
+"       lduw            [%2 + 0x08], %%g3\n"
+"       addccc          %%g2, %%g7, %%g7\n"
+"       lduw            [%2 + 0x04], %%g2\n"
+"       addccc          %%g3, %%g7, %%g7\n"
+"       lduw            [%2 + 0x00], %%g3\n"
+"       addccc          %%g2, %%g7, %%g7\n"
+"       lduw            [%1 + 0x0c], %%g2\n"
+"       addccc          %%g3, %%g7, %%g7\n"
+"       lduw            [%1 + 0x08], %%g3\n"
+"       addccc          %%g2, %%g7, %%g7\n"
+"       lduw            [%1 + 0x04], %%g2\n"
+"       addccc          %%g3, %%g7, %%g7\n"
+"       lduw            [%1 + 0x00], %%g3\n"
+"       addccc          %%g2, %%g7, %%g7\n"
+"       addccc          %%g3, %%g7, %0\n"
+"       addc            0, %0, %0\n"
+        : "=&r" (sum)
+        : "r" (saddr), "r" (daddr), "r"(htonl(len)),
+          "r"(htonl(proto)), "r"(sum)
+        : "g2", "g3", "g7", "cc");
+
+        return csum_fold(sum);
+}
+
+/* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#endif /* !(__SPARC64_CHECKSUM_H) */
diff --git a/arch/sparc/include/asm/chmctrl.h b/arch/sparc/include/asm/chmctrl.h
new file mode 100644
index 000000000000..859b4a4b0d30
--- /dev/null
+++ b/arch/sparc/include/asm/chmctrl.h
@@ -0,0 +1,183 @@
+#ifndef _SPARC64_CHMCTRL_H
+#define _SPARC64_CHMCTRL_H
+
+/* Cheetah memory controller programmable registers. */
+#define CHMCTRL_TCTRL1          0x00 /* Memory Timing Control I         */
+#define CHMCTRL_TCTRL2          0x08 /* Memory Timing Control II        */
+#define CHMCTRL_TCTRL3          0x38 /* Memory Timing Control III       */
+#define CHMCTRL_TCTRL4          0x40 /* Memory Timing Control IV        */
+#define CHMCTRL_DECODE1         0x10 /* Memory Address Decode I         */
+#define CHMCTRL_DECODE2         0x18 /* Memory Address Decode II        */
+#define CHMCTRL_DECODE3         0x20 /* Memory Address Decode III       */
+#define CHMCTRL_DECODE4         0x28 /* Memory Address Decode IV        */
+#define CHMCTRL_MACTRL          0x30 /* Memory Address Control          */
+
+/* Memory Timing Control I */
+#define TCTRL1_SDRAMCTL_DLY     0xf000000000000000UL
+#define TCTRL1_SDRAMCTL_DLY_SHIFT     60
+#define TCTRL1_SDRAMCLK_DLY     0x0e00000000000000UL
+#define TCTRL1_SDRAMCLK_DLY_SHIFT     57
+#define TCTRL1_R                0x0100000000000000UL
+#define TCTRL1_R_SHIFT                56
+#define TCTRL1_AUTORFR_CYCLE    0x00fe000000000000UL
+#define TCTRL1_AUTORFR_CYCLE_SHIFT    49
+#define TCTRL1_RD_WAIT          0x0001f00000000000UL
+#define TCTRL1_RD_WAIT_SHIFT          44
+#define TCTRL1_PC_CYCLE         0x00000fc000000000UL
+#define TCTRL1_PC_CYCLE_SHIFT         38
+#define TCTRL1_WR_MORE_RAS_PW   0x0000003f00000000UL
+#define TCTRL1_WR_MORE_RAS_PW_SHIFT   32
+#define TCTRL1_RD_MORE_RAW_PW   0x00000000fc000000UL
+#define TCTRL1_RD_MORE_RAS_PW_SHIFT   26
+#define TCTRL1_ACT_WR_DLY       0x0000000003f00000UL
+#define TCTRL1_ACT_WR_DLY_SHIFT       20
+#define TCTRL1_ACT_RD_DLY       0x00000000000fc000UL
+#define TCTRL1_ACT_RD_DLY_SHIFT       14
+#define TCTRL1_BANK_PRESENT     0x0000000000003000UL
+#define TCTRL1_BANK_PRESENT_SHIFT     12
+#define TCTRL1_RFR_INT          0x0000000000000ff8UL
+#define TCTRL1_RFR_INT_SHIFT          3
+#define TCTRL1_SET_MODE_REG     0x0000000000000004UL
+#define TCTRL1_SET_MODE_REG_SHIFT     2
+#define TCTRL1_RFR_ENABLE       0x0000000000000002UL
+#define TCTRL1_RFR_ENABLE_SHIFT       1
+#define TCTRL1_PRECHG_ALL       0x0000000000000001UL
+#define TCTRL1_PRECHG_ALL_SHIFT       0
+
+/* Memory Timing Control II */
+#define TCTRL2_WR_MSEL_DLY      0xfc00000000000000UL
+#define TCTRL2_WR_MSEL_DLY_SHIFT      58
+#define TCTRL2_RD_MSEL_DLY      0x03f0000000000000UL
+#define TCTRL2_RD_MSEL_DLY_SHIFT      52
+#define TCTRL2_WRDATA_THLD      0x000c000000000000UL
+#define TCTRL2_WRDATA_THLD_SHIFT      50
+#define TCTRL2_RDWR_RD_TI_DLY   0x0003f00000000000UL
+#define TCTRL2_RDWR_RD_TI_DLY_SHIFT   44
+#define TCTRL2_AUTOPRECHG_ENBL  0x0000080000000000UL
+#define TCTRL2_AUTOPRECHG_ENBL_SHIFT  43
+#define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL
+#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
+#define TCTRL2_RDWR_1_DLY       0x0000003f00000000UL
+#define TCTRL2_RDWR_1_DLY_SHIFT       32
+#define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL
+#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
+#define TCTRL2_WRWR_1_DLY       0x0000000007e00000UL
+#define TCTRL2_WRWR_1_DLY_SHIFT       21
+#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
+#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
+#define TCTRL2_R                0x0000000000008000UL
+#define TCTRL2_R_SHIFT                15
+#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
+#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
+
+/* Memory Timing Control III */
+#define TCTRL3_SDRAM_CTL_DLY    0xf000000000000000UL
+#define TCTRL3_SDRAM_CTL_DLY_SHIFT    60
+#define TCTRL3_SDRAM_CLK_DLY    0x0e00000000000000UL
+#define TCTRL3_SDRAM_CLK_DLY_SHIFT    57
+#define TCTRL3_R                0x0100000000000000UL
+#define TCTRL3_R_SHIFT                56
+#define TCTRL3_AUTO_RFR_CYCLE   0x00fe000000000000UL
+#define TCTRL3_AUTO_RFR_CYCLE_SHIFT   49
+#define TCTRL3_RD_WAIT          0x0001f00000000000UL
+#define TCTRL3_RD_WAIT_SHIFT          44
+#define TCTRL3_PC_CYCLE         0x00000fc000000000UL
+#define TCTRL3_PC_CYCLE_SHIFT         38
+#define TCTRL3_WR_MORE_RAW_PW   0x0000003f00000000UL
+#define TCTRL3_WR_MORE_RAW_PW_SHIFT   32
+#define TCTRL3_RD_MORE_RAW_PW   0x00000000fc000000UL
+#define TCTRL3_RD_MORE_RAW_PW_SHIFT   26
+#define TCTRL3_ACT_WR_DLY       0x0000000003f00000UL
+#define TCTRL3_ACT_WR_DLY_SHIFT       20
+#define TCTRL3_ACT_RD_DLY       0x00000000000fc000UL
+#define TCTRL3_ACT_RD_DLY_SHIFT       14
+#define TCTRL3_BANK_PRESENT     0x0000000000003000UL
+#define TCTRL3_BANK_PRESENT_SHIFT     12
+#define TCTRL3_RFR_INT          0x0000000000000ff8UL
+#define TCTRL3_RFR_INT_SHIFT          3
+#define TCTRL3_SET_MODE_REG     0x0000000000000004UL
+#define TCTRL3_SET_MODE_REG_SHIFT     2
+#define TCTRL3_RFR_ENABLE       0x0000000000000002UL
+#define TCTRL3_RFR_ENABLE_SHIFT       1
+#define TCTRL3_PRECHG_ALL       0x0000000000000001UL
+#define TCTRL3_PRECHG_ALL_SHIFT       0
+
+/* Memory Timing Control IV */
+#define TCTRL4_WR_MSEL_DLY      0xfc00000000000000UL
+#define TCTRL4_WR_MSEL_DLY_SHIFT      58
+#define TCTRL4_RD_MSEL_DLY      0x03f0000000000000UL
+#define TCTRL4_RD_MSEL_DLY_SHIFT      52
+#define TCTRL4_WRDATA_THLD      0x000c000000000000UL
+#define TCTRL4_WRDATA_THLD_SHIFT      50
+#define TCTRL4_RDWR_RD_RI_DLY   0x0003f00000000000UL
+#define TCTRL4_RDWR_RD_RI_DLY_SHIFT   44
+#define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL
+#define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
+#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
+#define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
+#define TCTRL4_RD_WR_TI_DLY     0x0000003f00000000UL
+#define TCTRL4_RD_WR_TI_DLY_SHIFT     32
+#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
+#define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
+#define TCTRL4_WR_WR_TI_DLY     0x0000000007e00000UL
+#define TCTRL4_WR_WR_TI_DLY_SHIFT     21
+#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
+#define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
+#define TCTRL4_R                0x0000000000008000UL
+#define TCTRL4_R_SHIFT                15
+#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
+#define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
+
+/* All 4 memory address decoding registers have the
+ * same layout.
+ */
+#define MEM_DECODE_VALID        0x8000000000000000UL /* Valid */
+#define MEM_DECODE_VALID_SHIFT        63
+#define MEM_DECODE_UK           0x001ffe0000000000UL /* Upper mask */
+#define MEM_DECODE_UK_SHIFT           41
+#define MEM_DECODE_UM           0x0000001ffff00000UL /* Upper match */
+#define MEM_DECODE_UM_SHIFT           20
+#define MEM_DECODE_LK           0x000000000003c000UL /* Lower mask */
+#define MEM_DECODE_LK_SHIFT           14
+#define MEM_DECODE_LM           0x0000000000000f00UL /* Lower match */
+#define MEM_DECODE_LM_SHIFT           8
+
+#define PA_UPPER_BITS           0x000007fffc000000UL
+#define PA_UPPER_BITS_SHIFT     26
+#define PA_LOWER_BITS           0x00000000000003c0UL
+#define PA_LOWER_BITS_SHIFT     6
+
+#define MACTRL_R0                        0x8000000000000000UL
+#define MACTRL_R0_SHIFT                  63
+#define MACTRL_ADDR_LE_PW                0x7000000000000000UL
+#define MACTRL_ADDR_LE_PW_SHIFT          60
+#define MACTRL_CMD_PW                    0x0f00000000000000UL
+#define MACTRL_CMD_PW_SHIFT              56
+#define MACTRL_HALF_MODE_WR_MSEL_DLY     0x00fc000000000000UL
+#define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
+#define MACTRL_HALF_MODE_RD_MSEL_DLY     0x0003f00000000000UL
+#define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
+#define MACTRL_HALF_MODE_SDRAM_CTL_DLY   0x00000f0000000000UL
+#define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
+#define MACTRL_HALF_MODE_SDRAM_CLK_DLY   0x000000e000000000UL
+#define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
+#define MACTRL_R1                        0x0000001000000000UL
+#define MACTRL_R1_SHIFT                      36
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
+#define MACTRL_ENC_INTLV_B3              0x00000000f8000000UL
+#define MACTRL_ENC_INTLV_B3_SHIFT              27
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
+#define MACTRL_ENC_INTLV_B2              0x00000000007c0000UL
+#define MACTRL_ENC_INTLV_B2_SHIFT              18
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
+#define MACTRL_ENC_INTLV_B1              0x0000000000003e00UL
+#define MACTRL_ENC_INTLV_B1_SHIFT               9
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT  5
+#define MACTRL_ENC_INTLV_B0              0x000000000000001fUL
+#define MACTRL_ENC_INTLV_B0_SHIFT               0
+
+#endif /* _SPARC64_CHMCTRL_H */
diff --git a/arch/sparc/include/asm/clock.h b/arch/sparc/include/asm/clock.h
new file mode 100644
index 000000000000..2cf99dadec56
--- /dev/null
+++ b/arch/sparc/include/asm/clock.h
@@ -0,0 +1,11 @@
+/*
+ * clock.h:  Definitions for clock operations on the Sparc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_CLOCK_H
+#define _SPARC_CLOCK_H
+
+/* Foo for now. */
+
+#endif /* !(_SPARC_CLOCK_H) */
diff --git a/arch/sparc/include/asm/cmt.h b/arch/sparc/include/asm/cmt.h
new file mode 100644
index 000000000000..870db5928577
--- /dev/null
+++ b/arch/sparc/include/asm/cmt.h
@@ -0,0 +1,59 @@
+#ifndef _SPARC64_CMT_H
+#define _SPARC64_CMT_H
+
+/* cmt.h: Chip Multi-Threading register definitions
+ *
+ * Copyright (C) 2004 David S. Miller (davem@redhat.com)
+ */
+
+/* ASI_CORE_ID - private */
+#define LP_ID           0x0000000000000010UL
+#define  LP_ID_MAX      0x00000000003f0000UL
+#define  LP_ID_ID       0x000000000000003fUL
+
+/* ASI_INTR_ID - private */
+#define LP_INTR_ID      0x0000000000000000UL
+#define  LP_INTR_ID_ID  0x00000000000003ffUL
+
+/* ASI_CESR_ID - private */
+#define CESR_ID         0x0000000000000040UL
+#define  CESR_ID_ID     0x00000000000000ffUL
+
+/* ASI_CORE_AVAILABLE - shared */
+#define LP_AVAIL        0x0000000000000000UL
+#define  LP_AVAIL_1     0x0000000000000002UL
+#define  LP_AVAIL_0     0x0000000000000001UL
+
+/* ASI_CORE_ENABLE_STATUS - shared */
+#define LP_ENAB_STAT    0x0000000000000010UL
+#define  LP_ENAB_STAT_1 0x0000000000000002UL
+#define  LP_ENAB_STAT_0 0x0000000000000001UL
+
+/* ASI_CORE_ENABLE - shared */
+#define LP_ENAB         0x0000000000000020UL
+#define  LP_ENAB_1      0x0000000000000002UL
+#define  LP_ENAB_0      0x0000000000000001UL
+
+/* ASI_CORE_RUNNING - shared */
+#define LP_RUNNING_RW   0x0000000000000050UL
+#define LP_RUNNING_W1S  0x0000000000000060UL
+#define LP_RUNNING_W1C  0x0000000000000068UL
+#define  LP_RUNNING_1   0x0000000000000002UL
+#define  LP_RUNNING_0   0x0000000000000001UL
+
+/* ASI_CORE_RUNNING_STAT - shared */
+#define LP_RUN_STAT     0x0000000000000058UL
+#define  LP_RUN_STAT_1  0x0000000000000002UL
+#define  LP_RUN_STAT_0  0x0000000000000001UL
+
+/* ASI_XIR_STEERING - shared */
+#define LP_XIR_STEER    0x0000000000000030UL
+#define  LP_XIR_STEER_1 0x0000000000000002UL
+#define  LP_XIR_STEER_0 0x0000000000000001UL
+
+/* ASI_CMT_ERROR_STEERING - shared */
+#define CMT_ER_STEER    0x0000000000000040UL
+#define  CMT_ER_STEER_1 0x0000000000000002UL
+#define  CMT_ER_STEER_0 0x0000000000000001UL
+
+#endif /* _SPARC64_CMT_H */
diff --git a/arch/sparc/include/asm/compat.h b/arch/sparc/include/asm/compat.h
new file mode 100644
index 000000000000..f260b58f5ce9
--- /dev/null
+++ b/arch/sparc/include/asm/compat.h
@@ -0,0 +1,243 @@
+#ifndef _ASM_SPARC64_COMPAT_H
+#define _ASM_SPARC64_COMPAT_H
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+
+#define COMPAT_USER_HZ  100
+
+typedef u32             compat_size_t;
+typedef s32             compat_ssize_t;
+typedef s32             compat_time_t;
+typedef s32             compat_clock_t;
+typedef s32             compat_pid_t;
+typedef u16             __compat_uid_t;
+typedef u16             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
+typedef u16             compat_mode_t;
+typedef u32             compat_ino_t;
+typedef u16             compat_dev_t;
+typedef s32             compat_off_t;
+typedef s64             compat_loff_t;
+typedef s16             compat_nlink_t;
+typedef u16             compat_ipc_pid_t;
+typedef s32             compat_daddr_t;
+typedef u32             compat_caddr_t;
+typedef __kernel_fsid_t compat_fsid_t;
+typedef s32             compat_key_t;
+typedef s32             compat_timer_t;
+
+typedef s32             compat_int_t;
+typedef s32             compat_long_t;
+typedef s64             compat_s64;
+typedef u32             compat_uint_t;
+typedef u32             compat_ulong_t;
+typedef u64             compat_u64;
+
+struct compat_timespec {
+        compat_time_t   tv_sec;
+        s32             tv_nsec;
+};
+
+struct compat_timeval {
+        compat_time_t   tv_sec;
+        s32             tv_usec;
+};
+
+struct compat_stat {
+        compat_dev_t    st_dev;
+        compat_ino_t    st_ino;
+        compat_mode_t   st_mode;
+        compat_nlink_t  st_nlink;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
+        compat_dev_t    st_rdev;
+        compat_off_t    st_size;
+        compat_time_t   st_atime;
+        compat_ulong_t  st_atime_nsec;
+        compat_time_t   st_mtime;
+        compat_ulong_t  st_mtime_nsec;
+        compat_time_t   st_ctime;
+        compat_ulong_t  st_ctime_nsec;
+        compat_off_t    st_blksize;
+        compat_off_t    st_blocks;
+        u32             __unused4[2];
+};
+
+struct compat_stat64 {
+        unsigned long long      st_dev;
+
+        unsigned long long      st_ino;
+
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned int    st_uid;
+        unsigned int    st_gid;
+
+        unsigned long long      st_rdev;
+
+        unsigned char   __pad3[8];
+
+        long long       st_size;
+        unsigned int    st_blksize;
+
+        unsigned char   __pad4[8];
+        unsigned int    st_blocks;
+
+        unsigned int    st_atime;
+        unsigned int    st_atime_nsec;
+
+        unsigned int    st_mtime;
+        unsigned int    st_mtime_nsec;
+
+        unsigned int    st_ctime;
+        unsigned int    st_ctime_nsec;
+
+        unsigned int    __unused4;
+        unsigned int    __unused5;
+};
+
+struct compat_flock {
+        short           l_type;
+        short           l_whence;
+        compat_off_t    l_start;
+        compat_off_t    l_len;
+        compat_pid_t    l_pid;
+        short           __unused;
+};
+
+#define F_GETLK64       12
+#define F_SETLK64       13
+#define F_SETLKW64      14
+
+struct compat_flock64 {
+        short           l_type;
+        short           l_whence;
+        compat_loff_t   l_start;
+        compat_loff_t   l_len;
+        compat_pid_t    l_pid;
+        short           __unused;
+};
+
+struct compat_statfs {
+        int             f_type;
+        int             f_bsize;
+        int             f_blocks;
+        int             f_bfree;
+        int             f_bavail;
+        int             f_files;
+        int             f_ffree;
+        compat_fsid_t   f_fsid;
+        int             f_namelen;      /* SunOS ignores this field. */
+        int             f_frsize;
+        int             f_spare[5];
+};
+
+#define COMPAT_RLIM_INFINITY 0x7fffffff
+
+typedef u32             compat_old_sigset_t;
+
+#define _COMPAT_NSIG            64
+#define _COMPAT_NSIG_BPW        32
+
+typedef u32             compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX        0x7fffffff
+#define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
+
+/*
+ * A pointer passed in from user mode. This should not
+ * be used for syscall parameters, just declare them
+ * as pointers because the syscall entry code will have
+ * appropriately converted them already.
+ */
+typedef u32             compat_uptr_t;
+
+static inline void __user *compat_ptr(compat_uptr_t uptr)
+{
+        return (void __user *)(unsigned long)uptr;
+}
+
+static inline compat_uptr_t ptr_to_compat(void __user *uptr)
+{
+        return (u32)(unsigned long)uptr;
+}
+
+static inline void __user *compat_alloc_user_space(long len)
+{
+        struct pt_regs *regs = current_thread_info()->kregs;
+        unsigned long usp = regs->u_regs[UREG_I6];
+
+        if (!(test_thread_flag(TIF_32BIT)))
+                usp += STACK_BIAS;
+        else
+                usp &= 0xffffffffUL;
+
+        usp -= len;
+        usp &= ~0x7UL;
+
+        return (void __user *) usp;
+}
+
+struct compat_ipc64_perm {
+        compat_key_t key;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
+        unsigned short __pad1;
+        compat_mode_t mode;
+        unsigned short __pad2;
+        unsigned short seq;
+        unsigned long __unused1;        /* yes they really are 64bit pads */
+        unsigned long __unused2;
+};
+
+struct compat_semid64_ds {
+        struct compat_ipc64_perm sem_perm;
+        unsigned int    __pad1;
+        compat_time_t   sem_otime;
+        unsigned int    __pad2;
+        compat_time_t   sem_ctime;
+        u32             sem_nsems;
+        u32             __unused1;
+        u32             __unused2;
+};
+
+struct compat_msqid64_ds {
+        struct compat_ipc64_perm msg_perm;
+        unsigned int    __pad1;
+        compat_time_t   msg_stime;
+        unsigned int    __pad2;
+        compat_time_t   msg_rtime;
+        unsigned int    __pad3;
+        compat_time_t   msg_ctime;
+        unsigned int    msg_cbytes;
+        unsigned int    msg_qnum;
+        unsigned int    msg_qbytes;
+        compat_pid_t    msg_lspid;
+        compat_pid_t    msg_lrpid;
+        unsigned int    __unused1;
+        unsigned int    __unused2;
+};
+
+struct compat_shmid64_ds {
+        struct compat_ipc64_perm shm_perm;
+        unsigned int    __pad1;
+        compat_time_t   shm_atime;
+        unsigned int    __pad2;
+        compat_time_t   shm_dtime;
+        unsigned int    __pad3;
+        compat_time_t   shm_ctime;
+        compat_size_t   shm_segsz;
+        compat_pid_t    shm_cpid;
+        compat_pid_t    shm_lpid;
+        unsigned int    shm_nattch;
+        unsigned int    __unused1;
+        unsigned int    __unused2;
+};
+
+#endif /* _ASM_SPARC64_COMPAT_H */
diff --git a/arch/sparc/include/asm/compat_signal.h b/arch/sparc/include/asm/compat_signal.h
new file mode 100644
index 000000000000..b759eab9b51c
--- /dev/null
+++ b/arch/sparc/include/asm/compat_signal.h
@@ -0,0 +1,29 @@
+#ifndef _COMPAT_SIGNAL_H
+#define _COMPAT_SIGNAL_H
+
+#include <linux/compat.h>
+#include <asm/signal.h>
+
+#ifdef CONFIG_COMPAT
+struct __new_sigaction32 {
+        unsigned                sa_handler;
+        unsigned int            sa_flags;
+        unsigned                sa_restorer;     /* not used by Linux/SPARC yet */
+        compat_sigset_t         sa_mask;
+};
+
+struct __old_sigaction32 {
+        unsigned                sa_handler;
+        compat_old_sigset_t     sa_mask;
+        unsigned int            sa_flags;
+        unsigned                sa_restorer;     /* not used by Linux/SPARC yet */
+};
+
+typedef struct sigaltstack32 {
+        u32                     ss_sp;
+        int                     ss_flags;
+        compat_size_t           ss_size;
+} stack_t32;
+#endif
+
+#endif /* !(_COMPAT_SIGNAL_H) */
diff --git a/arch/sparc/include/asm/contregs.h b/arch/sparc/include/asm/contregs.h
new file mode 100644
index 000000000000..48fa8a4ef357
--- /dev/null
+++ b/arch/sparc/include/asm/contregs.h
@@ -0,0 +1,53 @@
+#ifndef _SPARC_CONTREGS_H
+#define _SPARC_CONTREGS_H
+
+/* contregs.h:  Addresses of registers in the ASI_CONTROL alternate address
+ *              space. These are for the mmu's context register, etc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* 3=sun3
+   4=sun4 (as in sun4 sysmaint student book)
+   c=sun4c (according to davem) */
+
+#define AC_IDPROM     0x00000000    /* 34  ID PROM, R/O, byte, 32 bytes      */
+#define AC_PAGEMAP    0x10000000    /* 3   Pagemap R/W, long                 */
+#define AC_SEGMAP     0x20000000    /* 3   Segment map, byte                 */
+#define AC_CONTEXT    0x30000000    /* 34c current mmu-context               */
+#define AC_SENABLE    0x40000000    /* 34c system dvma/cache/reset enable reg*/
+#define AC_UDVMA_ENB  0x50000000    /* 34  Not used on Sun boards, byte      */
+#define AC_BUS_ERROR  0x60000000    /* 34  Not cleared on read, byte.        */
+#define AC_SYNC_ERR   0x60000000    /*  c fault type                         */
+#define AC_SYNC_VA    0x60000004    /*  c fault virtual address              */
+#define AC_ASYNC_ERR  0x60000008    /*  c asynchronous fault type            */
+#define AC_ASYNC_VA   0x6000000c    /*  c async fault virtual address        */
+#define AC_LEDS       0x70000000    /* 34  Zero turns on LEDs, byte          */
+#define AC_CACHETAGS  0x80000000    /* 34c direct access to the VAC tags     */
+#define AC_CACHEDDATA 0x90000000    /* 3 c direct access to the VAC data     */
+#define AC_UDVMA_MAP  0xD0000000    /* 4  Not used on Sun boards, byte       */
+#define AC_VME_VECTOR 0xE0000000    /* 4  For non-Autovector VME, byte       */
+#define AC_BOOT_SCC   0xF0000000    /* 34  bypass to access Zilog 8530. byte.*/
+
+/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress        */
+#define AC_M_PCR      0x0000        /* shv Processor Control Reg             */
+#define AC_M_CTPR     0x0100        /* shv Context Table Pointer Reg         */
+#define AC_M_CXR      0x0200        /* shv Context Register                  */
+#define AC_M_SFSR     0x0300        /* shv Synchronous Fault Status Reg      */
+#define AC_M_SFAR     0x0400        /* shv Synchronous Fault Address Reg     */
+#define AC_M_AFSR     0x0500        /*  hv Asynchronous Fault Status Reg     */
+#define AC_M_AFAR     0x0600        /*  hv Asynchronous Fault Address Reg    */
+#define AC_M_RESET    0x0700        /*  hv Reset Reg                         */
+#define AC_M_RPR      0x1000        /*  hv Root Pointer Reg                  */
+#define AC_M_TSUTRCR  0x1000        /* s   TLB Replacement Ctrl Reg          */
+#define AC_M_IAPTP    0x1100        /*  hv Instruction Access PTP            */
+#define AC_M_DAPTP    0x1200        /*  hv Data Access PTP                   */
+#define AC_M_ITR      0x1300        /*  hv Index Tag Register                */
+#define AC_M_TRCR     0x1400        /*  hv TLB Replacement Control Reg       */
+#define AC_M_SFSRX    0x1300        /* s   Synch Fault Status Reg prim       */
+#define AC_M_SFARX    0x1400        /* s   Synch Fault Address Reg prim      */
+#define AC_M_RPR1     0x1500        /*  h  Root Pointer Reg (entry 2)        */
+#define AC_M_IAPTP1   0x1600        /*  h  Instruction Access PTP (entry 2)  */
+#define AC_M_DAPTP1   0x1700        /*  h  Data Access PTP (entry 2)         */
+
+#endif /* _SPARC_CONTREGS_H */
diff --git a/arch/sparc/include/asm/cpudata.h b/arch/sparc/include/asm/cpudata.h
new file mode 100644
index 000000000000..b5976de7cacd
--- /dev/null
+++ b/arch/sparc/include/asm/cpudata.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_CPUDATA_H
+#define ___ASM_SPARC_CPUDATA_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/cpudata_64.h>
+#else
+#include <asm/cpudata_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/cpudata_32.h b/arch/sparc/include/asm/cpudata_32.h
new file mode 100644
index 000000000000..31d48a0e32c7
--- /dev/null
+++ b/arch/sparc/include/asm/cpudata_32.h
@@ -0,0 +1,27 @@
+/* cpudata.h: Per-cpu parameters.
+ *
+ * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org)
+ *
+ * Based on include/asm/cpudata.h and Linux 2.4 smp.h
+ * both (C) David S. Miller.
+ */
+
+#ifndef _SPARC_CPUDATA_H
+#define _SPARC_CPUDATA_H
+
+#include <linux/percpu.h>
+
+typedef struct {
+        unsigned long udelay_val;
+        unsigned long clock_tick;
+        unsigned int multiplier;
+        unsigned int counter;
+        int prom_node;
+        int mid;
+        int next;
+} cpuinfo_sparc;
+
+DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
+#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
+
+#endif /* _SPARC_CPUDATA_H */
diff --git a/arch/sparc/include/asm/cpudata_64.h b/arch/sparc/include/asm/cpudata_64.h
new file mode 100644
index 000000000000..532975ecfe10
--- /dev/null
+++ b/arch/sparc/include/asm/cpudata_64.h
@@ -0,0 +1,240 @@
+/* cpudata.h: Per-cpu parameters.
+ *
+ * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_CPUDATA_H
+#define _SPARC64_CPUDATA_H
+
+#include <asm/hypervisor.h>
+#include <asm/asi.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/percpu.h>
+#include <linux/threads.h>
+
+typedef struct {
+        /* Dcache line 1 */
+        unsigned int    __softirq_pending; /* must be 1st, see rtrap.S */
+        unsigned int    __pad0;
+        unsigned long   clock_tick;     /* %tick's per second */
+        unsigned long   __pad;
+        unsigned int    __pad1;
+        unsigned int    __pad2;
+
+        /* Dcache line 2, rarely used */
+        unsigned int    dcache_size;
+        unsigned int    dcache_line_size;
+        unsigned int    icache_size;
+        unsigned int    icache_line_size;
+        unsigned int    ecache_size;
+        unsigned int    ecache_line_size;
+        int             core_id;
+        int             proc_id;
+} cpuinfo_sparc;
+
+DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
+#define cpu_data(__cpu)         per_cpu(__cpu_data, (__cpu))
+#define local_cpu_data()        __get_cpu_var(__cpu_data)
+
+/* Trap handling code needs to get at a few critical values upon
+ * trap entry and to process TSB misses.  These cannot be in the
+ * per_cpu() area as we really need to lock them into the TLB and
+ * thus make them part of the main kernel image.  As a result we
+ * try to make this as small as possible.
+ *
+ * This is padded out and aligned to 64-bytes to avoid false sharing
+ * on SMP.
+ */
+
+/* If you modify the size of this structure, please update
+ * TRAP_BLOCK_SZ_SHIFT below.
+ */
+struct thread_info;
+struct trap_per_cpu {
+/* D-cache line 1: Basic thread information, cpu and device mondo queues */
+        struct thread_info      *thread;
+        unsigned long           pgd_paddr;
+        unsigned long           cpu_mondo_pa;
+        unsigned long           dev_mondo_pa;
+
+/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
+        unsigned long           resum_mondo_pa;
+        unsigned long           resum_kernel_buf_pa;
+        unsigned long           nonresum_mondo_pa;
+        unsigned long           nonresum_kernel_buf_pa;
+
+/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
+        struct hv_fault_status  fault_info;
+
+/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
+        unsigned long           cpu_mondo_block_pa;
+        unsigned long           cpu_list_pa;
+        unsigned long           tsb_huge;
+        unsigned long           tsb_huge_temp;
+
+/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
+        unsigned long           irq_worklist_pa;
+        unsigned int            cpu_mondo_qmask;
+        unsigned int            dev_mondo_qmask;
+        unsigned int            resum_qmask;
+        unsigned int            nonresum_qmask;
+        void                    *hdesc;
+} __attribute__((aligned(64)));
+extern struct trap_per_cpu trap_block[NR_CPUS];
+extern void init_cur_cpu_trap(struct thread_info *);
+extern void setup_tba(void);
+extern int ncpus_probed;
+extern void __init cpu_probe(void);
+extern const struct seq_operations cpuinfo_op;
+
+extern unsigned long real_hard_smp_processor_id(void);
+
+struct cpuid_patch_entry {
+        unsigned int    addr;
+        unsigned int    cheetah_safari[4];
+        unsigned int    cheetah_jbus[4];
+        unsigned int    starfire[4];
+        unsigned int    sun4v[4];
+};
+extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
+
+struct sun4v_1insn_patch_entry {
+        unsigned int    addr;
+        unsigned int    insn;
+};
+extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
+        __sun4v_1insn_patch_end;
+
+struct sun4v_2insn_patch_entry {
+        unsigned int    addr;
+        unsigned int    insns[2];
+};
+extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
+        __sun4v_2insn_patch_end;
+
+#endif /* !(__ASSEMBLY__) */
+
+#define TRAP_PER_CPU_THREAD             0x00
+#define TRAP_PER_CPU_PGD_PADDR          0x08
+#define TRAP_PER_CPU_CPU_MONDO_PA       0x10
+#define TRAP_PER_CPU_DEV_MONDO_PA       0x18
+#define TRAP_PER_CPU_RESUM_MONDO_PA     0x20
+#define TRAP_PER_CPU_RESUM_KBUF_PA      0x28
+#define TRAP_PER_CPU_NONRESUM_MONDO_PA  0x30
+#define TRAP_PER_CPU_NONRESUM_KBUF_PA   0x38
+#define TRAP_PER_CPU_FAULT_INFO         0x40
+#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
+#define TRAP_PER_CPU_CPU_LIST_PA        0xc8
+#define TRAP_PER_CPU_TSB_HUGE           0xd0
+#define TRAP_PER_CPU_TSB_HUGE_TEMP      0xd8
+#define TRAP_PER_CPU_IRQ_WORKLIST_PA    0xe0
+#define TRAP_PER_CPU_CPU_MONDO_QMASK    0xe8
+#define TRAP_PER_CPU_DEV_MONDO_QMASK    0xec
+#define TRAP_PER_CPU_RESUM_QMASK        0xf0
+#define TRAP_PER_CPU_NONRESUM_QMASK     0xf4
+
+#define TRAP_BLOCK_SZ_SHIFT             8
+
+#include <asm/scratchpad.h>
+
+#define __GET_CPUID(REG)                                \
+        /* Spitfire implementation (default). */        \
+661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
+        srlx            REG, 17, REG;                   \
+         and            REG, 0x1f, REG;                 \
+        nop;                                            \
+        .section        .cpuid_patch, "ax";             \
+        /* Instruction location. */                     \
+        .word           661b;                           \
+        /* Cheetah Safari implementation. */            \
+        ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
+        srlx            REG, 17, REG;                   \
+        and             REG, 0x3ff, REG;                \
+        nop;                                            \
+        /* Cheetah JBUS implementation. */              \
+        ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
+        srlx            REG, 17, REG;                   \
+        and             REG, 0x1f, REG;                 \
+        nop;                                            \
+        /* Starfire implementation. */                  \
+        sethi           %hi(0x1fff40000d0 >> 9), REG;   \
+        sllx            REG, 9, REG;                    \
+        or              REG, 0xd0, REG;                 \
+        lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
+        /* sun4v implementation. */                     \
+        mov             SCRATCHPAD_CPUID, REG;          \
+        ldxa            [REG] ASI_SCRATCHPAD, REG;      \
+        nop;                                            \
+        nop;                                            \
+        .previous;
+
+#ifdef CONFIG_SMP
+
+#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        __GET_CPUID(TMP)                        \
+        sethi   %hi(trap_block), DEST;          \
+        sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
+        or      DEST, %lo(trap_block), DEST;    \
+        add     DEST, TMP, DEST;                \
+
+/* Clobbers TMP, current address space PGD phys address into DEST.  */
+#define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
+
+/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
+#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
+
+/* Clobbers TMP, loads DEST with current thread info pointer.  */
+#define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
+
+/* Given the current thread info pointer in THR, load the per-cpu
+ * area base of the current processor into DEST.  REG1, REG2, and REG3 are
+ * clobbered.
+ *
+ * You absolutely cannot use DEST as a temporary in this code.  The
+ * reason is that traps can happen during execution, and return from
+ * trap will load the fully resolved DEST per-cpu base.  This can corrupt
+ * the calculations done by the macro mid-stream.
+ */
+#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
+        lduh    [THR + TI_CPU], REG1;                   \
+        sethi   %hi(__per_cpu_shift), REG3;             \
+        sethi   %hi(__per_cpu_base), REG2;              \
+        ldx     [REG3 + %lo(__per_cpu_shift)], REG3;    \
+        ldx     [REG2 + %lo(__per_cpu_base)], REG2;     \
+        sllx    REG1, REG3, REG3;                       \
+        add     REG3, REG2, DEST;
+
+#else
+
+#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        sethi   %hi(trap_block), DEST;          \
+        or      DEST, %lo(trap_block), DEST;    \
+
+/* Uniprocessor versions, we know the cpuid is zero.  */
+#define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
+
+/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
+#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
+
+#define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
+
+/* No per-cpu areas on uniprocessor, so no need to load DEST.  */
+#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
+
+#endif /* !(CONFIG_SMP) */
+
+#endif /* _SPARC64_CPUDATA_H */
diff --git a/arch/sparc/include/asm/cputime.h b/arch/sparc/include/asm/cputime.h
new file mode 100644
index 000000000000..1a642b81e019
--- /dev/null
+++ b/arch/sparc/include/asm/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __SPARC_CPUTIME_H
+#define __SPARC_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __SPARC_CPUTIME_H */
diff --git a/arch/sparc/include/asm/current.h b/arch/sparc/include/asm/current.h
new file mode 100644
index 000000000000..10a0df55a574
--- /dev/null
+++ b/arch/sparc/include/asm/current.h
@@ -0,0 +1,34 @@
+/* include/asm/current.h
+ *
+ * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ * Copyright (C) 2002 Pete Zaitcev (zaitcev@yahoo.com)
+ * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
+ *
+ *  Derived from "include/asm-s390/current.h" by
+ *  Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *  Derived from "include/asm-i386/current.h"
+*/
+#ifndef _SPARC_CURRENT_H
+#define _SPARC_CURRENT_H
+
+#include <linux/thread_info.h>
+
+#ifdef CONFIG_SPARC64
+register struct task_struct *current asm("g4");
+#endif
+
+#ifdef CONFIG_SPARC32
+/* We might want to consider using %g4 like sparc64 to shave a few cycles.
+ *
+ * Two stage process (inline + #define) for type-checking.
+ * We also obfuscate get_current() to check if anyone used that by mistake.
+ */
+struct task_struct;
+static inline struct task_struct *__get_current(void)
+{
+        return current_thread_info()->task;
+}
+#define current __get_current()
+#endif
+
+#endif /* !(_SPARC_CURRENT_H) */
diff --git a/arch/sparc/include/asm/cypress.h b/arch/sparc/include/asm/cypress.h
new file mode 100644
index 000000000000..95e9772ea394
--- /dev/null
+++ b/arch/sparc/include/asm/cypress.h
@@ -0,0 +1,79 @@
+/*
+ * cypress.h: Cypress module specific definitions and defines.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_CYPRESS_H
+#define _SPARC_CYPRESS_H
+
+/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */
+
+/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
+ *
+ * ---------------------------------------------------------------
+ * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME|
+ * ---------------------------------------------------------------
+ *  31    24 23-22 21-20 19 18-15 14 13  12 11 10  9  8 7-2  1  0
+ *
+ * MCA: MultiChip Access -- Used for configuration of multiple
+ *      CY7C604/605 cache units.
+ * MCM: MultiChip Mask -- Again, for multiple cache unit config.
+ * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
+ * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
+ * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
+ * C: Cacheable -- Indicates whether accesses are cacheable while
+ *    the MMU is off.  0=no 1=yes
+ * MR: MemoryReflection -- Indicates whether the bus attached to the
+ *     MBus supports memory reflection. 0=no 1=yes (605 only)
+ * CM: CacheMode -- Indicates whether the cache is operating in write
+ *     through or copy-back mode. 0=write-through 1=copy-back
+ * CL: CacheLock -- Indicates if the entire cache is locked or not.
+ *     0=not-locked 1=locked  (604 only)
+ * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
+ * NF: NoFault -- Do faults generate traps? 0=yes 1=no
+ * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
+ */
+
+#define CYPRESS_MCA       0x00c00000
+#define CYPRESS_MCM       0x00300000
+#define CYPRESS_MVALID    0x00080000
+#define CYPRESS_MIDMASK   0x00078000   /* Only on 605 */
+#define CYPRESS_BMODE     0x00004000
+#define CYPRESS_ACENABLE  0x00002000
+#define CYPRESS_MRFLCT    0x00000800   /* Only on 605 */
+#define CYPRESS_CMODE     0x00000400
+#define CYPRESS_CLOCK     0x00000200   /* Only on 604 */
+#define CYPRESS_CENABLE   0x00000100
+#define CYPRESS_NFAULT    0x00000002
+#define CYPRESS_MENABLE   0x00000001
+
+static inline void cypress_flush_page(unsigned long page)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (page), "i" (ASI_M_FLUSH_PAGE));
+}
+
+static inline void cypress_flush_segment(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_SEG));
+}
+
+static inline void cypress_flush_region(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_REGION));
+}
+
+static inline void cypress_flush_context(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
+                             "i" (ASI_M_FLUSH_CTX));
+}
+
+/* XXX Displacement flushes for buggy chips and initial testing
+ * XXX go here.
+ */
+
+#endif /* !(_SPARC_CYPRESS_H) */
diff --git a/arch/sparc/include/asm/dcr.h b/arch/sparc/include/asm/dcr.h
new file mode 100644
index 000000000000..620c9ba642e9
--- /dev/null
+++ b/arch/sparc/include/asm/dcr.h
@@ -0,0 +1,14 @@
+#ifndef _SPARC64_DCR_H
+#define _SPARC64_DCR_H
+
+/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */
+#define DCR_DPE         0x0000000000001000 /* III+: D$ Parity Error Enable      */
+#define DCR_OBS         0x0000000000000fc0 /* Observability Bus Controls        */
+#define DCR_BPE         0x0000000000000020 /* Branch Predict Enable             */
+#define DCR_RPE         0x0000000000000010 /* Return Address Prediction Enable  */
+#define DCR_SI          0x0000000000000008 /* Single Instruction Disable        */
+#define DCR_IPE         0x0000000000000004 /* III+: I$ Parity Error Enable      */
+#define DCR_IFPOE       0x0000000000000002 /* IRQ FP Operation Enable           */
+#define DCR_MS          0x0000000000000001 /* Multi-Scalar dispatch             */
+
+#endif /* _SPARC64_DCR_H */
diff --git a/arch/sparc/include/asm/dcu.h b/arch/sparc/include/asm/dcu.h
new file mode 100644
index 000000000000..0f704e106a1b
--- /dev/null
+++ b/arch/sparc/include/asm/dcu.h
@@ -0,0 +1,27 @@
+#ifndef _SPARC64_DCU_H
+#define _SPARC64_DCU_H
+
+#include <linux/const.h>
+
+/* UltraSparc-III Data Cache Unit Control Register */
+#define DCU_CP  _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
+#define DCU_CV  _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
+#define DCU_ME  _AC(0x0000800000000000,UL) /* NC-store Merging Enable   */
+#define DCU_RE  _AC(0x0000400000000000,UL) /* RAW bypass Enable         */
+#define DCU_PE  _AC(0x0000200000000000,UL) /* PCache Enable             */
+#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable        */
+#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable        */
+#define DCU_SL  _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
+#define DCU_WE  _AC(0x0000020000000000,UL) /* WCache enable             */
+#define DCU_PM  _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask   */
+#define DCU_VM  _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask   */
+#define DCU_PR  _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
+#define DCU_PW  _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
+#define DCU_VR  _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
+#define DCU_VW  _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
+#define DCU_DM  _AC(0x0000000000000008,UL) /* DMMU Enable               */
+#define DCU_IM  _AC(0x0000000000000004,UL) /* IMMU Enable               */
+#define DCU_DC  _AC(0x0000000000000002,UL) /* Data Cache Enable         */
+#define DCU_IC  _AC(0x0000000000000001,UL) /* Instruction Cache Enable  */
+
+#endif /* _SPARC64_DCU_H */
diff --git a/arch/sparc/include/asm/delay.h b/arch/sparc/include/asm/delay.h
new file mode 100644
index 000000000000..467caa2a97a0
--- /dev/null
+++ b/arch/sparc/include/asm/delay.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_DELAY_H
+#define ___ASM_SPARC_DELAY_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/delay_64.h>
+#else
+#include <asm/delay_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/delay_32.h b/arch/sparc/include/asm/delay_32.h
new file mode 100644
index 000000000000..bc9aba2bead6
--- /dev/null
+++ b/arch/sparc/include/asm/delay_32.h
@@ -0,0 +1,34 @@
+/*
+ * delay.h: Linux delay routines on the Sparc.
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu).
+ */
+
+#ifndef __SPARC_DELAY_H
+#define __SPARC_DELAY_H
+
+#include <asm/cpudata.h>
+
+static inline void __delay(unsigned long loops)
+{
+        __asm__ __volatile__("cmp %0, 0\n\t"
+                             "1: bne 1b\n\t"
+                             "subcc %0, 1, %0\n" :
+                             "=&r" (loops) :
+                             "0" (loops) :
+                             "cc");
+}
+
+/* This is too messy with inline asm on the Sparc. */
+extern void __udelay(unsigned long usecs, unsigned long lpj);
+extern void __ndelay(unsigned long nsecs, unsigned long lpj);
+
+#ifdef CONFIG_SMP
+#define __udelay_val    cpu_data(smp_processor_id()).udelay_val
+#else /* SMP */
+#define __udelay_val    loops_per_jiffy
+#endif /* SMP */
+#define udelay(__usecs) __udelay(__usecs, __udelay_val)
+#define ndelay(__nsecs) __ndelay(__nsecs, __udelay_val)
+
+#endif /* defined(__SPARC_DELAY_H) */
diff --git a/arch/sparc/include/asm/delay_64.h b/arch/sparc/include/asm/delay_64.h
new file mode 100644
index 000000000000..a77aa622d762
--- /dev/null
+++ b/arch/sparc/include/asm/delay_64.h
@@ -0,0 +1,17 @@
+/* delay.h: Linux delay routines on sparc64.
+ *
+ * Copyright (C) 1996, 2004, 2007 David S. Miller (davem@davemloft.net).
+ */
+
+#ifndef _SPARC64_DELAY_H
+#define _SPARC64_DELAY_H
+
+#ifndef __ASSEMBLY__
+
+extern void __delay(unsigned long loops);
+extern void udelay(unsigned long usecs);
+#define mdelay(n)       udelay((n) * 1000)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _SPARC64_DELAY_H */
diff --git a/arch/sparc/include/asm/device.h b/arch/sparc/include/asm/device.h
new file mode 100644
index 000000000000..19790eb99cc6
--- /dev/null
+++ b/arch/sparc/include/asm/device.h
@@ -0,0 +1,23 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#ifndef _ASM_SPARC_DEVICE_H
+#define _ASM_SPARC_DEVICE_H
+
+struct device_node;
+struct of_device;
+
+struct dev_archdata {
+        void                    *iommu;
+        void                    *stc;
+        void                    *host_controller;
+
+        struct device_node      *prom_node;
+        struct of_device        *op;
+
+        int                     numa_node;
+};
+
+#endif /* _ASM_SPARC_DEVICE_H */
diff --git a/arch/sparc/include/asm/display7seg.h b/arch/sparc/include/asm/display7seg.h
new file mode 100644
index 000000000000..86d4a901df24
--- /dev/null
+++ b/arch/sparc/include/asm/display7seg.h
@@ -0,0 +1,79 @@
+/*
+ *
+ * display7seg - Driver interface for the 7-segment display
+ * present on Sun Microsystems CP1400 and CP1500
+ *
+ * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
+ *
+ */
+
+#ifndef __display7seg_h__
+#define __display7seg_h__
+
+#define D7S_IOC 'p'
+
+#define D7SIOCRD _IOR(D7S_IOC, 0x45, int)       /* Read device state    */
+#define D7SIOCWR _IOW(D7S_IOC, 0x46, int)       /* Write device state   */
+#define D7SIOCTM _IO (D7S_IOC, 0x47)            /* Translate mode (FLIP)*/
+
+/*
+ * ioctl flag definitions
+ *
+ * POINT        - Toggle decimal point  (0=absent 1=present)
+ * ALARM        - Toggle alarm LED              (0=green  1=red)
+ * FLIP         - Toggle inverted mode  (0=normal 1=flipped)
+ * bits 0-4     - Character displayed   (see definitions below)
+ *
+ * Display segments are defined as follows,
+ * subject to D7S_FLIP register state:
+ *
+ *    a
+ *   ---
+ * f|   |b
+ *   -g-
+ * e|   |c
+ *   ---
+ *    d
+ */
+
+#define D7S_POINT       (1 << 7)        /* Decimal point*/
+#define D7S_ALARM       (1 << 6)        /* Alarm LED    */
+#define D7S_FLIP        (1 << 5)        /* Flip display */
+
+#define D7S_0           0x00            /* Numerals 0-9 */
+#define D7S_1           0x01
+#define D7S_2           0x02
+#define D7S_3           0x03
+#define D7S_4           0x04
+#define D7S_5           0x05
+#define D7S_6           0x06
+#define D7S_7           0x07
+#define D7S_8           0x08
+#define D7S_9           0x09
+#define D7S_A           0x0A            /* Letters A-F, H, L, P */
+#define D7S_B           0x0B
+#define D7S_C           0x0C
+#define D7S_D           0x0D
+#define D7S_E           0x0E
+#define D7S_F           0x0F
+#define D7S_H           0x10
+#define D7S_E2          0x11
+#define D7S_L           0x12
+#define D7S_P           0x13
+#define D7S_SEGA        0x14            /* Individual segments */
+#define D7S_SEGB        0x15
+#define D7S_SEGC        0x16
+#define D7S_SEGD        0x17
+#define D7S_SEGE        0x18
+#define D7S_SEGF        0x19
+#define D7S_SEGG        0x1A
+#define D7S_SEGABFG 0x1B                /* Segment groupings */
+#define D7S_SEGCDEG     0x1C
+#define D7S_SEGBCEF 0x1D
+#define D7S_SEGADG      0x1E
+#define D7S_BLANK       0x1F            /* Clear all segments */
+
+#define D7S_MIN_VAL     0x0
+#define D7S_MAX_VAL     0x1F
+
+#endif /* ifndef __display7seg_h__ */
diff --git a/arch/sparc/include/asm/div64.h b/arch/sparc/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/sparc/include/asm/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/arch/sparc/include/asm/dma-mapping.h b/arch/sparc/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..0f4150e26619
--- /dev/null
+++ b/arch/sparc/include/asm/dma-mapping.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_DMA_MAPPING_H
+#define ___ASM_SPARC_DMA_MAPPING_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/dma-mapping_64.h>
+#else
+#include <asm/dma-mapping_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/dma-mapping_32.h b/arch/sparc/include/asm/dma-mapping_32.h
new file mode 100644
index 000000000000..f3a641e6b2c8
--- /dev/null
+++ b/arch/sparc/include/asm/dma-mapping_32.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_SPARC_DMA_MAPPING_H
+#define _ASM_SPARC_DMA_MAPPING_H
+
+
+#ifdef CONFIG_PCI
+#include <asm-generic/dma-mapping.h>
+#else
+#include <asm-generic/dma-mapping-broken.h>
+#endif /* PCI */
+
+#endif /* _ASM_SPARC_DMA_MAPPING_H */
diff --git a/arch/sparc/include/asm/dma-mapping_64.h b/arch/sparc/include/asm/dma-mapping_64.h
new file mode 100644
index 000000000000..bfa64f9702d5
--- /dev/null
+++ b/arch/sparc/include/asm/dma-mapping_64.h
@@ -0,0 +1,154 @@
+#ifndef _ASM_SPARC64_DMA_MAPPING_H
+#define _ASM_SPARC64_DMA_MAPPING_H
+
+#include <linux/scatterlist.h>
+#include <linux/mm.h>
+
+#define DMA_ERROR_CODE  (~(dma_addr_t)0x0)
+
+struct dma_ops {
+        void *(*alloc_coherent)(struct device *dev, size_t size,
+                                dma_addr_t *dma_handle, gfp_t flag);
+        void (*free_coherent)(struct device *dev, size_t size,
+                              void *cpu_addr, dma_addr_t dma_handle);
+        dma_addr_t (*map_single)(struct device *dev, void *cpu_addr,
+                                 size_t size,
+                                 enum dma_data_direction direction);
+        void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
+                             size_t size,
+                             enum dma_data_direction direction);
+        int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
+                      enum dma_data_direction direction);
+        void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
+                         int nhwentries,
+                         enum dma_data_direction direction);
+        void (*sync_single_for_cpu)(struct device *dev,
+                                    dma_addr_t dma_handle, size_t size,
+                                    enum dma_data_direction direction);
+        void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
+                                int nelems,
+                                enum dma_data_direction direction);
+};
+extern const struct dma_ops *dma_ops;
+
+extern int dma_supported(struct device *dev, u64 mask);
+extern int dma_set_mask(struct device *dev, u64 dma_mask);
+
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t flag)
+{
+        return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *cpu_addr, dma_addr_t dma_handle)
+{
+        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+}
+
+static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                                        size_t size,
+                                        enum dma_data_direction direction)
+{
+        return dma_ops->map_single(dev, cpu_addr, size, direction);
+}
+
+static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                                    size_t size,
+                                    enum dma_data_direction direction)
+{
+        dma_ops->unmap_single(dev, dma_addr, size, direction);
+}
+
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      unsigned long offset, size_t size,
+                                      enum dma_data_direction direction)
+{
+        return dma_ops->map_single(dev, page_address(page) + offset,
+                                   size, direction);
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                  size_t size,
+                                  enum dma_data_direction direction)
+{
+        dma_ops->unmap_single(dev, dma_address, size, direction);
+}
+
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+                             int nents, enum dma_data_direction direction)
+{
+        return dma_ops->map_sg(dev, sg, nents, direction);
+}
+
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction direction)
+{
+        dma_ops->unmap_sg(dev, sg, nents, direction);
+}
+
+static inline void dma_sync_single_for_cpu(struct device *dev,
+                                           dma_addr_t dma_handle, size_t size,
+                                           enum dma_data_direction direction)
+{
+        dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
+}
+
+static inline void dma_sync_single_for_device(struct device *dev,
+                                              dma_addr_t dma_handle,
+                                              size_t size,
+                                              enum dma_data_direction direction)
+{
+        /* No flushing needed to sync cpu writes to the device.  */
+}
+
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+                                                 dma_addr_t dma_handle,
+                                                 unsigned long offset,
+                                                 size_t size,
+                                                 enum dma_data_direction direction)
+{
+        dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
+}
+
+static inline void dma_sync_single_range_for_device(struct device *dev,
+                                                    dma_addr_t dma_handle,
+                                                    unsigned long offset,
+                                                    size_t size,
+                                                    enum dma_data_direction direction)
+{
+        /* No flushing needed to sync cpu writes to the device.  */
+}
+
+
+static inline void dma_sync_sg_for_cpu(struct device *dev,
+                                       struct scatterlist *sg, int nelems,
+                                       enum dma_data_direction direction)
+{
+        dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
+}
+
+static inline void dma_sync_sg_for_device(struct device *dev,
+                                          struct scatterlist *sg, int nelems,
+                                          enum dma_data_direction direction)
+{
+        /* No flushing needed to sync cpu writes to the device.  */
+}
+
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return (dma_addr == DMA_ERROR_CODE);
+}
+
+static inline int dma_get_cache_alignment(void)
+{
+        /* no easy way to get cache size on all processors, so return
+         * the maximum possible, to be safe */
+        return (1 << INTERNODE_CACHE_SHIFT);
+}
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_is_consistent(d, h) (1)
+
+#endif /* _ASM_SPARC64_DMA_MAPPING_H */
diff --git a/arch/sparc/include/asm/dma.h b/arch/sparc/include/asm/dma.h
new file mode 100644
index 000000000000..aa1d90ac04c5
--- /dev/null
+++ b/arch/sparc/include/asm/dma.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_DMA_H
+#define ___ASM_SPARC_DMA_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/dma_64.h>
+#else
+#include <asm/dma_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/dma_32.h b/arch/sparc/include/asm/dma_32.h
new file mode 100644
index 000000000000..cf7189c0079b
--- /dev/null
+++ b/arch/sparc/include/asm/dma_32.h
@@ -0,0 +1,288 @@
+/* include/asm/dma.h
+ *
+ * Copyright 1995 (C) David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _ASM_SPARC_DMA_H
+#define _ASM_SPARC_DMA_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <asm/vac-ops.h>  /* for invalidate's, etc. */
+#include <asm/sbus.h>
+#include <asm/delay.h>
+#include <asm/oplib.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+
+struct page;
+extern spinlock_t  dma_spin_lock;
+
+static inline unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static inline void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* These are irrelevant for Sparc DMA, but we leave it in so that
+ * things can compile.
+ */
+#define MAX_DMA_CHANNELS 8
+#define MAX_DMA_ADDRESS  (~0UL)
+#define DMA_MODE_READ    1
+#define DMA_MODE_WRITE   2
+
+/* Useful constants */
+#define SIZE_16MB      (16*1024*1024)
+#define SIZE_64K       (64*1024)
+
+/* SBUS DMA controller reg offsets */
+#define DMA_CSR         0x00UL          /* rw  DMA control/status register    0x00   */
+#define DMA_ADDR        0x04UL          /* rw  DMA transfer address register  0x04   */
+#define DMA_COUNT       0x08UL          /* rw  DMA transfer count register    0x08   */
+#define DMA_TEST        0x0cUL          /* rw  DMA test/debug register        0x0c   */
+
+/* DVMA chip revisions */
+enum dvma_rev {
+        dvmarev0,
+        dvmaesc1,
+        dvmarev1,
+        dvmarev2,
+        dvmarev3,
+        dvmarevplus,
+        dvmahme
+};
+
+#define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
+
+/* Linux DMA information structure, filled during probe. */
+struct sbus_dma {
+        struct sbus_dma *next;
+        struct sbus_dev *sdev;
+        void __iomem *regs;
+
+        /* Status, misc info */
+        int node;                /* Prom node for this DMA device */
+        int running;             /* Are we doing DMA now? */
+        int allocated;           /* Are we "owned" by anyone yet? */
+
+        /* Transfer information. */
+        unsigned long addr;      /* Start address of current transfer */
+        int nbytes;              /* Size of current transfer */
+        int realbytes;           /* For splitting up large transfers, etc. */
+
+        /* DMA revision */
+        enum dvma_rev revision;
+};
+
+extern struct sbus_dma *dma_chain;
+
+/* Broken hardware... */
+#ifdef CONFIG_SUN4
+/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
+ * Or is rev0 present only on sun4 boxes? -jj */
+#define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
+#else
+#define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev1)
+#endif
+#define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
+
+/* Main routines in dma.c */
+extern void dvma_init(struct sbus_bus *);
+
+/* Fields in the cond_reg register */
+/* First, the version identification bits */
+#define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
+#define DMA_VERS0        0x00000000        /* Sunray DMA version */
+#define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
+#define DMA_VERS1        0x80000000        /* DMA rev 1 */
+#define DMA_VERS2        0xa0000000        /* DMA rev 2 */
+#define DMA_VERHME       0xb0000000        /* DMA hme gate array */
+#define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
+
+#define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
+#define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
+#define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
+#define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
+#define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
+#define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
+#define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
+#define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
+#define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
+#define DMA_RST_BPP      DMA_RST_SCSI      /* Reset the BPP controller */
+#define DMA_ST_WRITE     0x00000100        /* write from device to memory */
+#define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
+#define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
+#define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
+#define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
+#define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
+#define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
+#define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
+#define DMA_SCSI_SBUS64  0x00008000        /* HME: Enable 64-bit SBUS mode. */
+#define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
+#define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
+#define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
+#define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
+#define DMA_E_BURSTS     0x000c0000        /* ENET: SBUS r/w burst mask */
+#define DMA_E_BURST32    0x00040000        /* ENET: SBUS 32 byte r/w burst */
+#define DMA_E_BURST16    0x00000000        /* ENET: SBUS 16 byte r/w burst */
+#define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
+#define DMA_BRST64       0x00080000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
+#define DMA_BRST32       0x00040000        /* SCSI/BPP: 32byte bursts */
+#define DMA_BRST16       0x00000000        /* SCSI/BPP: 16byte bursts */
+#define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
+#define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
+#define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
+#define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
+#define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
+#define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
+#define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
+#define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
+#define DMA_BPP_ON       DMA_SCSI_ON       /* Enable BPP dma */
+#define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
+#define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
+#define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
+#define DMA_RESET_FAS366 0x08000000        /* HME: Assert RESET to FAS366 */
+
+/* Values describing the burst-size property from the PROM */
+#define DMA_BURST1       0x01
+#define DMA_BURST2       0x02
+#define DMA_BURST4       0x04
+#define DMA_BURST8       0x08
+#define DMA_BURST16      0x10
+#define DMA_BURST32      0x20
+#define DMA_BURST64      0x40
+#define DMA_BURSTBITS    0x7f
+
+/* Determine highest possible final transfer address given a base */
+#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
+
+/* Yes, I hack a lot of elisp in my spare time... */
+#define DMA_ERROR_P(regs)  ((((regs)->cond_reg) & DMA_HNDL_ERROR))
+#define DMA_IRQ_P(regs)    ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
+#define DMA_WRITE_P(regs)  ((((regs)->cond_reg) & DMA_ST_WRITE))
+#define DMA_OFF(regs)      ((((regs)->cond_reg) &= (~DMA_ENABLE)))
+#define DMA_INTSOFF(regs)  ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
+#define DMA_INTSON(regs)   ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
+#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
+#define DMA_SETSTART(regs, addr)  ((((regs)->st_addr) = (char *) addr))
+#define DMA_BEGINDMA_W(regs) \
+        ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
+#define DMA_BEGINDMA_R(regs) \
+        ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
+
+/* For certain DMA chips, we need to disable ints upon irq entry
+ * and turn them back on when we are done.  So in any ESP interrupt
+ * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
+ * when leaving the handler.  You have been warned...
+ */
+#define DMA_IRQ_ENTRY(dma, dregs) do { \
+        if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
+   } while (0)
+
+#define DMA_IRQ_EXIT(dma, dregs) do { \
+        if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
+   } while(0)
+
+#if 0   /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
+/* Pause until counter runs out or BIT isn't set in the DMA condition
+ * register.
+ */
+static inline void sparc_dma_pause(struct sparc_dma_registers *regs,
+                                       unsigned long bit)
+{
+        int ctr = 50000;   /* Let's find some bugs ;) */
+
+        /* Busy wait until the bit is not set any more */
+        while((regs->cond_reg&bit) && (ctr>0)) {
+                ctr--;
+                __delay(5);
+        }
+
+        /* Check for bogus outcome. */
+        if(!ctr)
+                panic("DMA timeout");
+}
+
+/* Reset the friggin' thing... */
+#define DMA_RESET(dma) do { \
+        struct sparc_dma_registers *regs = dma->regs;                      \
+        /* Let the current FIFO drain itself */                            \
+        sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN));                         \
+        /* Reset the logic */                                              \
+        regs->cond_reg |= (DMA_RST_SCSI);     /* assert */                 \
+        __delay(400);                         /* let the bits set ;) */    \
+        regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */              \
+        sparc_dma_enable_interrupts(regs);    /* Re-enable interrupts */   \
+        /* Enable FAST transfers if available */                           \
+        if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS;            \
+        dma->running = 0;                                                  \
+} while(0)
+#endif
+
+#define for_each_dvma(dma) \
+        for((dma) = dma_chain; (dma); (dma) = (dma)->next)
+
+extern int get_dma_list(char *);
+extern int request_dma(unsigned int, __const__ char *);
+extern void free_dma(unsigned int);
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+/* Routines for data transfer buffers. */
+BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
+BTFIXUPDEF_CALL(void,   mmu_unlockarea, char *, unsigned long)
+
+#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
+#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
+
+/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
+BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus)
+BTFIXUPDEF_CALL(void,  mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
+BTFIXUPDEF_CALL(void,  mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus)
+BTFIXUPDEF_CALL(void,  mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus)
+
+#define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus)
+#define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus)
+#define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus)
+#define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus)
+
+/*
+ * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
+ *
+ * The mmu_map_dma_area establishes two mappings in one go.
+ * These mappings point to pages normally mapped at 'va' (linear address).
+ * First mapping is for CPU visible address at 'a', uncached.
+ * This is an alias, but it works because it is an uncached mapping.
+ * Second mapping is for device visible address, or "bus" address.
+ * The bus address is returned at '*pba'.
+ *
+ * These functions seem distinct, but are hard to split. On sun4c,
+ * at least for now, 'a' is equal to bus address, and retured in *pba.
+ * On sun4m, page attributes depend on the CPU type, so we have to
+ * know if we are mapping RAM or I/O, so it has to be an additional argument
+ * to a separate mapping function for CPU visible mappings.
+ */
+BTFIXUPDEF_CALL(int,  mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len)
+BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa)
+BTFIXUPDEF_CALL(void,  mmu_unmap_dma_area, unsigned long busa, int len)
+
+#define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len)
+#define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len)
+#define mmu_translate_dvma(ba)     BTFIXUP_CALL(mmu_translate_dvma)(ba)
+
+#endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/arch/sparc/include/asm/dma_64.h b/arch/sparc/include/asm/dma_64.h
new file mode 100644
index 000000000000..46a8aecffc02
--- /dev/null
+++ b/arch/sparc/include/asm/dma_64.h
@@ -0,0 +1,205 @@
+/*
+ * include/asm/dma.h
+ *
+ * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _ASM_SPARC64_DMA_H
+#define _ASM_SPARC64_DMA_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+#include <asm/sbus.h>
+#include <asm/delay.h>
+#include <asm/oplib.h>
+
+/* These are irrelevant for Sparc DMA, but we leave it in so that
+ * things can compile.
+ */
+#define MAX_DMA_CHANNELS 8
+#define DMA_MODE_READ    1
+#define DMA_MODE_WRITE   2
+#define MAX_DMA_ADDRESS  (~0UL)
+
+/* Useful constants */
+#define SIZE_16MB      (16*1024*1024)
+#define SIZE_64K       (64*1024)
+
+/* SBUS DMA controller reg offsets */
+#define DMA_CSR         0x00UL          /* rw  DMA control/status register    0x00   */
+#define DMA_ADDR        0x04UL          /* rw  DMA transfer address register  0x04   */
+#define DMA_COUNT       0x08UL          /* rw  DMA transfer count register    0x08   */
+#define DMA_TEST        0x0cUL          /* rw  DMA test/debug register        0x0c   */
+
+/* DVMA chip revisions */
+enum dvma_rev {
+        dvmarev0,
+        dvmaesc1,
+        dvmarev1,
+        dvmarev2,
+        dvmarev3,
+        dvmarevplus,
+        dvmahme
+};
+
+#define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
+
+/* Linux DMA information structure, filled during probe. */
+struct sbus_dma {
+        struct sbus_dma *next;
+        struct sbus_dev *sdev;
+        void __iomem *regs;
+
+        /* Status, misc info */
+        int node;                /* Prom node for this DMA device */
+        int running;             /* Are we doing DMA now? */
+        int allocated;           /* Are we "owned" by anyone yet? */
+
+        /* Transfer information. */
+        u32 addr;                /* Start address of current transfer */
+        int nbytes;              /* Size of current transfer */
+        int realbytes;           /* For splitting up large transfers, etc. */
+
+        /* DMA revision */
+        enum dvma_rev revision;
+};
+
+extern struct sbus_dma *dma_chain;
+
+/* Broken hardware... */
+#define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev1)
+#define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
+
+/* Main routines in dma.c */
+extern void dvma_init(struct sbus_bus *);
+
+/* Fields in the cond_reg register */
+/* First, the version identification bits */
+#define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
+#define DMA_VERS0        0x00000000        /* Sunray DMA version */
+#define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
+#define DMA_VERS1        0x80000000        /* DMA rev 1 */
+#define DMA_VERS2        0xa0000000        /* DMA rev 2 */
+#define DMA_VERHME       0xb0000000        /* DMA hme gate array */
+#define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
+
+#define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
+#define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
+#define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
+#define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
+#define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
+#define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
+#define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
+#define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
+#define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
+#define DMA_ST_WRITE     0x00000100        /* write from device to memory */
+#define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
+#define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
+#define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
+#define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
+#define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
+#define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
+#define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
+#define DMA_SCSI_SBUS64  0x00008000        /* HME: Enable 64-bit SBUS mode. */
+#define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
+#define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
+#define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
+#define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
+#define DMA_E_BURSTS     0x000c0000        /* ENET: SBUS r/w burst mask */
+#define DMA_E_BURST32    0x00040000        /* ENET: SBUS 32 byte r/w burst */
+#define DMA_E_BURST16    0x00000000        /* ENET: SBUS 16 byte r/w burst */
+#define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
+#define DMA_BRST64       0x000c0000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
+#define DMA_BRST32       0x00040000        /* SCSI: 32byte bursts */
+#define DMA_BRST16       0x00000000        /* SCSI: 16byte bursts */
+#define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
+#define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
+#define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
+#define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
+#define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
+#define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
+#define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
+#define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
+#define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
+#define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
+#define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
+#define DMA_RESET_FAS366 0x08000000        /* HME: Assert RESET to FAS366 */
+
+/* Values describing the burst-size property from the PROM */
+#define DMA_BURST1       0x01
+#define DMA_BURST2       0x02
+#define DMA_BURST4       0x04
+#define DMA_BURST8       0x08
+#define DMA_BURST16      0x10
+#define DMA_BURST32      0x20
+#define DMA_BURST64      0x40
+#define DMA_BURSTBITS    0x7f
+
+/* Determine highest possible final transfer address given a base */
+#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
+
+/* Yes, I hack a lot of elisp in my spare time... */
+#define DMA_ERROR_P(regs)  ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
+#define DMA_IRQ_P(regs)    ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
+#define DMA_WRITE_P(regs)  ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
+#define DMA_OFF(__regs)         \
+do {    u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+        tmp &= ~DMA_ENABLE; \
+        sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_INTSOFF(__regs)     \
+do {    u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+        tmp &= ~DMA_INT_ENAB; \
+        sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_INTSON(__regs)      \
+do {    u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+        tmp |= DMA_INT_ENAB; \
+        sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_PUNTFIFO(__regs)    \
+do {    u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+        tmp |= DMA_FIFO_INV; \
+        sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_SETSTART(__regs, __addr)    \
+        sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
+#define DMA_BEGINDMA_W(__regs)  \
+do {    u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+        tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
+        sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+#define DMA_BEGINDMA_R(__regs)  \
+do {    u32 tmp = sbus_readl((__regs) + DMA_CSR); \
+        tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
+        tmp &= ~DMA_ST_WRITE; \
+        sbus_writel(tmp, (__regs) + DMA_CSR); \
+} while(0)
+
+/* For certain DMA chips, we need to disable ints upon irq entry
+ * and turn them back on when we are done.  So in any ESP interrupt
+ * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
+ * when leaving the handler.  You have been warned...
+ */
+#define DMA_IRQ_ENTRY(dma, dregs) do { \
+        if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
+   } while (0)
+
+#define DMA_IRQ_EXIT(dma, dregs) do { \
+        if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
+   } while(0)
+
+#define for_each_dvma(dma) \
+        for((dma) = dma_chain; (dma); (dma) = (dma)->next)
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif /* !(_ASM_SPARC64_DMA_H) */
diff --git a/arch/sparc/include/asm/ebus.h b/arch/sparc/include/asm/ebus.h
new file mode 100644
index 000000000000..83a6d16c22e6
--- /dev/null
+++ b/arch/sparc/include/asm/ebus.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_EBUS_H
+#define ___ASM_SPARC_EBUS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/ebus_64.h>
+#else
+#include <asm/ebus_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/ebus_32.h b/arch/sparc/include/asm/ebus_32.h
new file mode 100644
index 000000000000..29cb7dfc6b79
--- /dev/null
+++ b/arch/sparc/include/asm/ebus_32.h
@@ -0,0 +1,99 @@
+/*
+ * ebus.h: PCI to Ebus pseudo driver software state.
+ *
+ * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
+ *
+ * Adopted for sparc by V. Roganov and G. Raiko.
+ */
+
+#ifndef __SPARC_EBUS_H
+#define __SPARC_EBUS_H
+
+#ifndef _LINUX_IOPORT_H
+#include <linux/ioport.h>
+#endif
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+
+struct linux_ebus_child {
+        struct linux_ebus_child         *next;
+        struct linux_ebus_device        *parent;
+        struct linux_ebus               *bus;
+        struct device_node              *prom_node;
+        struct resource                  resource[PROMREG_MAX];
+        int                              num_addrs;
+        unsigned int                     irqs[PROMINTR_MAX];
+        int                              num_irqs;
+};
+
+struct linux_ebus_device {
+        struct of_device                ofdev;
+        struct linux_ebus_device        *next;
+        struct linux_ebus_child         *children;
+        struct linux_ebus               *bus;
+        struct device_node              *prom_node;
+        struct resource                  resource[PROMREG_MAX];
+        int                              num_addrs;
+        unsigned int                     irqs[PROMINTR_MAX];
+        int                              num_irqs;
+};
+#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
+
+struct linux_ebus {
+        struct of_device                ofdev;
+        struct linux_ebus               *next;
+        struct linux_ebus_device        *devices;
+        struct linux_pbm_info           *parent;
+        struct pci_dev                  *self;
+        struct device_node              *prom_node;
+};
+#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
+
+struct linux_ebus_dma {
+        unsigned int dcsr;
+        unsigned int dacr;
+        unsigned int dbcr;
+};
+
+#define EBUS_DCSR_INT_PEND      0x00000001
+#define EBUS_DCSR_ERR_PEND      0x00000002
+#define EBUS_DCSR_DRAIN         0x00000004
+#define EBUS_DCSR_INT_EN        0x00000010
+#define EBUS_DCSR_RESET         0x00000080
+#define EBUS_DCSR_WRITE         0x00000100
+#define EBUS_DCSR_EN_DMA        0x00000200
+#define EBUS_DCSR_CYC_PEND      0x00000400
+#define EBUS_DCSR_DIAG_RD_DONE  0x00000800
+#define EBUS_DCSR_DIAG_WR_DONE  0x00001000
+#define EBUS_DCSR_EN_CNT        0x00002000
+#define EBUS_DCSR_TC            0x00004000
+#define EBUS_DCSR_DIS_CSR_DRN   0x00010000
+#define EBUS_DCSR_BURST_SZ_MASK 0x000c0000
+#define EBUS_DCSR_BURST_SZ_1    0x00080000
+#define EBUS_DCSR_BURST_SZ_4    0x00000000
+#define EBUS_DCSR_BURST_SZ_8    0x00040000
+#define EBUS_DCSR_BURST_SZ_16   0x000c0000
+#define EBUS_DCSR_DIAG_EN       0x00100000
+#define EBUS_DCSR_DIS_ERR_PEND  0x00400000
+#define EBUS_DCSR_TCI_DIS       0x00800000
+#define EBUS_DCSR_EN_NEXT       0x01000000
+#define EBUS_DCSR_DMA_ON        0x02000000
+#define EBUS_DCSR_A_LOADED      0x04000000
+#define EBUS_DCSR_NA_LOADED     0x08000000
+#define EBUS_DCSR_DEV_ID_MASK   0xf0000000
+
+extern struct linux_ebus                *ebus_chain;
+
+extern void ebus_init(void);
+
+#define for_each_ebus(bus)                                              \
+        for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
+
+#define for_each_ebusdev(dev, bus)                                      \
+        for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
+
+#define for_each_edevchild(dev, child)                                  \
+        for((child) = (dev)->children; (child); (child) = (child)->next)
+
+#endif /* !(__SPARC_EBUS_H) */
diff --git a/arch/sparc/include/asm/ebus_64.h b/arch/sparc/include/asm/ebus_64.h
new file mode 100644
index 000000000000..fcc62b97ced5
--- /dev/null
+++ b/arch/sparc/include/asm/ebus_64.h
@@ -0,0 +1,94 @@
+/*
+ * ebus.h: PCI to Ebus pseudo driver software state.
+ *
+ * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
+ * Copyright (C) 1999 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __SPARC64_EBUS_H
+#define __SPARC64_EBUS_H
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+
+struct linux_ebus_child {
+        struct linux_ebus_child         *next;
+        struct linux_ebus_device        *parent;
+        struct linux_ebus               *bus;
+        struct device_node              *prom_node;
+        struct resource                  resource[PROMREG_MAX];
+        int                              num_addrs;
+        unsigned int                     irqs[PROMINTR_MAX];
+        int                              num_irqs;
+};
+
+struct linux_ebus_device {
+        struct of_device                ofdev;
+        struct linux_ebus_device        *next;
+        struct linux_ebus_child         *children;
+        struct linux_ebus               *bus;
+        struct device_node              *prom_node;
+        struct resource                  resource[PROMREG_MAX];
+        int                              num_addrs;
+        unsigned int                     irqs[PROMINTR_MAX];
+        int                              num_irqs;
+};
+#define to_ebus_device(d) container_of(d, struct linux_ebus_device, ofdev.dev)
+
+struct linux_ebus {
+        struct of_device                ofdev;
+        struct linux_ebus               *next;
+        struct linux_ebus_device        *devices;
+        struct pci_dev                  *self;
+        int                              index;
+        int                              is_rio;
+        struct device_node              *prom_node;
+};
+#define to_ebus(d) container_of(d, struct linux_ebus, ofdev.dev)
+
+struct ebus_dma_info {
+        spinlock_t      lock;
+        void __iomem    *regs;
+
+        unsigned int    flags;
+#define EBUS_DMA_FLAG_USE_EBDMA_HANDLER         0x00000001
+#define EBUS_DMA_FLAG_TCI_DISABLE               0x00000002
+
+        /* These are only valid is EBUS_DMA_FLAG_USE_EBDMA_HANDLER is
+         * set.
+         */
+        void (*callback)(struct ebus_dma_info *p, int event, void *cookie);
+        void *client_cookie;
+        unsigned int    irq;
+#define EBUS_DMA_EVENT_ERROR    1
+#define EBUS_DMA_EVENT_DMA      2
+#define EBUS_DMA_EVENT_DEVICE   4
+
+        unsigned char   name[64];
+};
+
+extern int ebus_dma_register(struct ebus_dma_info *p);
+extern int ebus_dma_irq_enable(struct ebus_dma_info *p, int on);
+extern void ebus_dma_unregister(struct ebus_dma_info *p);
+extern int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr,
+                            size_t len);
+extern void ebus_dma_prepare(struct ebus_dma_info *p, int write);
+extern unsigned int ebus_dma_residue(struct ebus_dma_info *p);
+extern unsigned int ebus_dma_addr(struct ebus_dma_info *p);
+extern void ebus_dma_enable(struct ebus_dma_info *p, int on);
+
+extern struct linux_ebus                *ebus_chain;
+
+extern void ebus_init(void);
+
+#define for_each_ebus(bus)                                              \
+        for((bus) = ebus_chain; (bus); (bus) = (bus)->next)
+
+#define for_each_ebusdev(dev, bus)                                      \
+        for((dev) = (bus)->devices; (dev); (dev) = (dev)->next)
+
+#define for_each_edevchild(dev, child)                                  \
+        for((child) = (dev)->children; (child); (child) = (child)->next)
+
+#endif /* !(__SPARC64_EBUS_H) */
diff --git a/arch/sparc/include/asm/ecc.h b/arch/sparc/include/asm/ecc.h
new file mode 100644
index 000000000000..ccb84b66fef1
--- /dev/null
+++ b/arch/sparc/include/asm/ecc.h
@@ -0,0 +1,122 @@
+/*
+ * ecc.h: Definitions and defines for the external cache/memory
+ *        controller on the sun4m.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_ECC_H
+#define _SPARC_ECC_H
+
+/* These registers are accessed through the SRMMU passthrough ASI 0x20 */
+#define ECC_ENABLE     0x00000000       /* ECC enable register */
+#define ECC_FSTATUS    0x00000008       /* ECC fault status register */
+#define ECC_FADDR      0x00000010       /* ECC fault address register */
+#define ECC_DIGNOSTIC  0x00000018       /* ECC diagnostics register */
+#define ECC_MBAENAB    0x00000020       /* MBus arbiter enable register */
+#define ECC_DMESG      0x00001000       /* Diagnostic message passing area */
+
+/* ECC MBus Arbiter Enable register:
+ *
+ * ----------------------------------------
+ * |              |SBUS|MOD3|MOD2|MOD1|RSV|
+ * ----------------------------------------
+ *  31           5   4   3    2    1    0
+ *
+ * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
+ * MOD3: Enable MBus Arbiter on MBus module 3  0=off 1=on
+ * MOD2: Enable MBus Arbiter on MBus module 2  0=off 1=on
+ * MOD1: Enable MBus Arbiter on MBus module 1  0=off 1=on
+ */
+
+#define ECC_MBAE_SBUS     0x00000010
+#define ECC_MBAE_MOD3     0x00000008
+#define ECC_MBAE_MOD2     0x00000004
+#define ECC_MBAE_MOD1     0x00000002 
+
+/* ECC Fault Control Register layout:
+ *
+ * -----------------------------
+ * |    RESV   | ECHECK | EINT |
+ * -----------------------------
+ *  31        2     1       0
+ *
+ * ECHECK:  Enable ECC checking.  0=off 1=on
+ * EINT:  Enable Interrupts for correctable errors. 0=off 1=on
+ */ 
+#define ECC_FCR_CHECK    0x00000002
+#define ECC_FCR_INTENAB  0x00000001
+
+/* ECC Fault Address Register Zero layout:
+ *
+ * -----------------------------------------------------
+ * | MID | S | RSV |  VA   | BM |AT| C| SZ |TYP| PADDR |
+ * -----------------------------------------------------
+ *  31-28  27 26-22  21-14   13  12 11 10-8 7-4   3-0
+ *
+ * MID: ModuleID of the faulting processor. ie. who did it?
+ * S: Supervisor/Privileged access? 0=no 1=yes
+ * VA: Bits 19-12 of the virtual faulting address, these are the
+ *     superset bits in the virtual cache and can be used for
+ *     a flush operation if necessary.
+ * BM: Boot mode? 0=no 1=yes  This is just like the SRMMU boot
+ *     mode bit.
+ * AT: Did this fault happen during an atomic instruction? 0=no
+ *     1=yes.  This means either an 'ldstub' or 'swap' instruction
+ *     was in progress (but not finished) when this fault happened.
+ *     This indicated whether the bus was locked when the fault
+ *     occurred.
+ * C: Did the pte for this access indicate that it was cacheable?
+ *    0=no 1=yes
+ * SZ: The size of the transaction.
+ * TYP: The transaction type.
+ * PADDR: Bits 35-32 of the physical address for the fault.
+ */
+#define ECC_FADDR0_MIDMASK   0xf0000000
+#define ECC_FADDR0_S         0x08000000
+#define ECC_FADDR0_VADDR     0x003fc000
+#define ECC_FADDR0_BMODE     0x00002000
+#define ECC_FADDR0_ATOMIC    0x00001000
+#define ECC_FADDR0_CACHE     0x00000800
+#define ECC_FADDR0_SIZE      0x00000700
+#define ECC_FADDR0_TYPE      0x000000f0
+#define ECC_FADDR0_PADDR     0x0000000f
+
+/* ECC Fault Address Register One layout:
+ *
+ * -------------------------------------
+ * |          Physical Address 31-0    |
+ * -------------------------------------
+ *  31                               0
+ *
+ * You get the upper 4 bits of the physical address from the
+ * PADDR field in ECC Fault Address Zero register.
+ */
+
+/* ECC Fault Status Register layout:
+ *
+ * ----------------------------------------------
+ * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
+ * ----------------------------------------------
+ *  31-18  17  16    15-8    7-4   3    2    1 0
+ *
+ * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
+ * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
+ * SYNDROME: Controller is mentally unstable.
+ * DWORD:
+ * UNC: Uncorrectable error.  0=no 1=yes
+ * TIMEO: Timeout occurred. 0=no 1=yes
+ * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
+ * C: Correctable error? 0=no 1=yes
+ */
+
+#define ECC_FSR_C2ERR    0x00020000
+#define ECC_FSR_MULT     0x00010000
+#define ECC_FSR_SYND     0x0000ff00
+#define ECC_FSR_DWORD    0x000000f0
+#define ECC_FSR_UNC      0x00000008
+#define ECC_FSR_TIMEO    0x00000004
+#define ECC_FSR_BADSLOT  0x00000002
+#define ECC_FSR_C        0x00000001
+
+#endif /* !(_SPARC_ECC_H) */
diff --git a/arch/sparc/include/asm/eeprom.h b/arch/sparc/include/asm/eeprom.h
new file mode 100644
index 000000000000..e17beeceb405
--- /dev/null
+++ b/arch/sparc/include/asm/eeprom.h
@@ -0,0 +1,9 @@
+/*
+ * eeprom.h:  Definitions for the Sun eeprom.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* The EEPROM and the Mostek Mk48t02 use the same IO address space
+ * for their registers/data areas.  The IDPROM lives here too.
+ */
diff --git a/arch/sparc/include/asm/elf.h b/arch/sparc/include/asm/elf.h
new file mode 100644
index 000000000000..0a2816c50b07
--- /dev/null
+++ b/arch/sparc/include/asm/elf.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_ELF_H
+#define ___ASM_SPARC_ELF_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/elf_64.h>
+#else
+#include <asm/elf_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h
new file mode 100644
index 000000000000..d043f80bc2fd
--- /dev/null
+++ b/arch/sparc/include/asm/elf_32.h
@@ -0,0 +1,145 @@
+#ifndef __ASMSPARC_ELF_H
+#define __ASMSPARC_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+
+/*
+ * Sparc section types
+ */
+#define STT_REGISTER            13
+
+/*
+ * Sparc ELF relocation types
+ */
+#define R_SPARC_NONE            0
+#define R_SPARC_8               1
+#define R_SPARC_16              2
+#define R_SPARC_32              3
+#define R_SPARC_DISP8           4
+#define R_SPARC_DISP16          5
+#define R_SPARC_DISP32          6
+#define R_SPARC_WDISP30         7
+#define R_SPARC_WDISP22         8
+#define R_SPARC_HI22            9
+#define R_SPARC_22              10
+#define R_SPARC_13              11
+#define R_SPARC_LO10            12
+#define R_SPARC_GOT10           13
+#define R_SPARC_GOT13           14
+#define R_SPARC_GOT22           15
+#define R_SPARC_PC10            16
+#define R_SPARC_PC22            17
+#define R_SPARC_WPLT30          18
+#define R_SPARC_COPY            19
+#define R_SPARC_GLOB_DAT        20
+#define R_SPARC_JMP_SLOT        21
+#define R_SPARC_RELATIVE        22
+#define R_SPARC_UA32            23
+#define R_SPARC_PLT32           24
+#define R_SPARC_HIPLT22         25
+#define R_SPARC_LOPLT10         26
+#define R_SPARC_PCPLT32         27
+#define R_SPARC_PCPLT22         28
+#define R_SPARC_PCPLT10         29
+#define R_SPARC_10              30
+#define R_SPARC_11              31
+#define R_SPARC_64              32
+#define R_SPARC_OLO10           33
+#define R_SPARC_WDISP16         40
+#define R_SPARC_WDISP19         41
+#define R_SPARC_7               43
+#define R_SPARC_5               44
+#define R_SPARC_6               45
+
+/* Bits present in AT_HWCAP, primarily for Sparc32.  */
+
+#define HWCAP_SPARC_FLUSH       1    /* CPU supports flush instruction. */
+#define HWCAP_SPARC_STBAR       2
+#define HWCAP_SPARC_SWAP        4
+#define HWCAP_SPARC_MULDIV      8
+#define HWCAP_SPARC_V9          16
+#define HWCAP_SPARC_ULTRA3      32
+
+#define CORE_DUMP_USE_REGSET
+
+/* Format is:
+ *      G0 --> G7
+ *      O0 --> O7
+ *      L0 --> L7
+ *      I0 --> I7
+ *      PSR, PC, nPC, Y, WIM, TBR
+ */
+typedef unsigned long elf_greg_t;
+#define ELF_NGREG 38
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct {
+        union {
+                unsigned long   pr_regs[32];
+                double          pr_dregs[16];
+        } pr_fr;
+        unsigned long __unused;
+        unsigned long   pr_fsr;
+        unsigned char   pr_qcnt;
+        unsigned char   pr_q_entrysize;
+        unsigned char   pr_en;
+        unsigned int    pr_q[64];
+} elf_fpregset_t;
+
+#include <asm/mbus.h>
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_SPARC)
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_ARCH        EM_SPARC
+#define ELF_CLASS       ELFCLASS32
+#define ELF_DATA        ELFDATA2MSB
+
+#define USE_ELF_CORE_DUMP
+#ifndef CONFIG_SUN4
+#define ELF_EXEC_PAGESIZE       4096
+#else
+#define ELF_EXEC_PAGESIZE       8192
+#endif
+
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE         (TASK_UNMAPPED_BASE)
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  This can NOT be done in userspace
+   on Sparc.  */
+
+/* Sun4c has none of the capabilities, most sun4m's have them all.
+ * XXX This is gross, set some global variable at boot time. -DaveM
+ */
+#define ELF_HWCAP       ((ARCH_SUN4C_SUN4) ? 0 : \
+                         (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
+                          HWCAP_SPARC_SWAP | \
+                          ((srmmu_modtype != Cypress && \
+                            srmmu_modtype != Cypress_vE && \
+                            srmmu_modtype != Cypress_vD) ? \
+                           HWCAP_SPARC_MULDIV : 0)))
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo. */
+
+#define ELF_PLATFORM    (NULL)
+
+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+
+#endif /* !(__ASMSPARC_ELF_H) */
diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
new file mode 100644
index 000000000000..0818a1308f4e
--- /dev/null
+++ b/arch/sparc/include/asm/elf_64.h
@@ -0,0 +1,217 @@
+#ifndef __ASM_SPARC64_ELF_H
+#define __ASM_SPARC64_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/uaccess.h>
+#include <asm/spitfire.h>
+
+/*
+ * Sparc section types
+ */
+#define STT_REGISTER            13
+
+/*
+ * Sparc ELF relocation types
+ */
+#define R_SPARC_NONE            0
+#define R_SPARC_8               1
+#define R_SPARC_16              2
+#define R_SPARC_32              3
+#define R_SPARC_DISP8           4
+#define R_SPARC_DISP16          5
+#define R_SPARC_DISP32          6
+#define R_SPARC_WDISP30         7
+#define R_SPARC_WDISP22         8
+#define R_SPARC_HI22            9
+#define R_SPARC_22              10
+#define R_SPARC_13              11
+#define R_SPARC_LO10            12
+#define R_SPARC_GOT10           13
+#define R_SPARC_GOT13           14
+#define R_SPARC_GOT22           15
+#define R_SPARC_PC10            16
+#define R_SPARC_PC22            17
+#define R_SPARC_WPLT30          18
+#define R_SPARC_COPY            19
+#define R_SPARC_GLOB_DAT        20
+#define R_SPARC_JMP_SLOT        21
+#define R_SPARC_RELATIVE        22
+#define R_SPARC_UA32            23
+#define R_SPARC_PLT32           24
+#define R_SPARC_HIPLT22         25
+#define R_SPARC_LOPLT10         26
+#define R_SPARC_PCPLT32         27
+#define R_SPARC_PCPLT22         28
+#define R_SPARC_PCPLT10         29
+#define R_SPARC_10              30
+#define R_SPARC_11              31
+#define R_SPARC_64              32
+#define R_SPARC_OLO10           33
+#define R_SPARC_WDISP16         40
+#define R_SPARC_WDISP19         41
+#define R_SPARC_7               43
+#define R_SPARC_5               44
+#define R_SPARC_6               45
+
+/* Bits present in AT_HWCAP, primarily for Sparc32.  */
+
+#define HWCAP_SPARC_FLUSH       1    /* CPU supports flush instruction. */
+#define HWCAP_SPARC_STBAR       2
+#define HWCAP_SPARC_SWAP        4
+#define HWCAP_SPARC_MULDIV      8
+#define HWCAP_SPARC_V9          16
+#define HWCAP_SPARC_ULTRA3      32
+#define HWCAP_SPARC_BLKINIT     64
+#define HWCAP_SPARC_N2          128
+
+#define CORE_DUMP_USE_REGSET
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_ARCH                EM_SPARCV9
+#define ELF_CLASS               ELFCLASS64
+#define ELF_DATA                ELFDATA2MSB
+
+/* Format of 64-bit elf_gregset_t is:
+ *      G0 --> G7
+ *      O0 --> O7
+ *      L0 --> L7
+ *      I0 --> I7
+ *      TSTATE
+ *      TPC
+ *      TNPC
+ *      Y
+ */
+typedef unsigned long elf_greg_t;
+#define ELF_NGREG 36
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct {
+        unsigned long   pr_regs[32];
+        unsigned long   pr_fsr;
+        unsigned long   pr_gsr;
+        unsigned long   pr_fprs;
+} elf_fpregset_t;
+
+/* Format of 32-bit elf_gregset_t is:
+ *      G0 --> G7
+ *      O0 --> O7
+ *      L0 --> L7
+ *      I0 --> I7
+ *      PSR, PC, nPC, Y, WIM, TBR
+ */
+typedef unsigned int compat_elf_greg_t;
+#define COMPAT_ELF_NGREG 38
+typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
+
+typedef struct {
+        union {
+                unsigned int    pr_regs[32];
+                unsigned long   pr_dregs[16];
+        } pr_fr;
+        unsigned int __unused;
+        unsigned int    pr_fsr;
+        unsigned char   pr_qcnt;
+        unsigned char   pr_q_entrysize;
+        unsigned char   pr_en;
+        unsigned int    pr_q[64];
+} compat_elf_fpregset_t;
+
+/* UltraSparc extensions.  Still unused, but will be eventually.  */
+typedef struct {
+        unsigned int pr_type;
+        unsigned int pr_align;
+        union {
+                struct {
+                        union {
+                                unsigned int    pr_regs[32];
+                                unsigned long   pr_dregs[16];
+                                long double     pr_qregs[8];
+                        } pr_xfr;
+                } pr_v8p;
+                unsigned int    pr_xfsr;
+                unsigned int    pr_fprs;
+                unsigned int    pr_xg[8];
+                unsigned int    pr_xo[8];
+                unsigned long   pr_tstate;
+                unsigned int    pr_filler[8];
+        } pr_un;
+} elf_xregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)               ((x)->e_machine == ELF_ARCH)
+#define compat_elf_check_arch(x)        ((x)->e_machine == EM_SPARC || \
+                                         (x)->e_machine == EM_SPARC32PLUS)
+#define compat_start_thread             start_thread32
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE         0x0000010000000000UL
+#define COMPAT_ELF_ET_DYN_BASE  0x0000000070000000UL
+
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  */
+
+/* On Ultra, we support all of the v8 capabilities. */
+static inline unsigned int sparc64_elf_hwcap(void)
+{
+        unsigned int cap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
+                            HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
+                            HWCAP_SPARC_V9);
+
+        if (tlb_type == cheetah || tlb_type == cheetah_plus)
+                cap |= HWCAP_SPARC_ULTRA3;
+        else if (tlb_type == hypervisor) {
+                if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
+                        cap |= HWCAP_SPARC_BLKINIT;
+                if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
+                        cap |= HWCAP_SPARC_N2;
+        }
+
+        return cap;
+}
+
+#define ELF_HWCAP       sparc64_elf_hwcap();
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.  */
+
+#define ELF_PLATFORM    (NULL)
+
+#define SET_PERSONALITY(ex, ibcs2)                      \
+do {    unsigned long new_flags = current_thread_info()->flags; \
+        new_flags &= _TIF_32BIT;                        \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)       \
+                new_flags |= _TIF_32BIT;                \
+        else                                            \
+                new_flags &= ~_TIF_32BIT;               \
+        if ((current_thread_info()->flags & _TIF_32BIT) \
+            != new_flags)                               \
+                set_thread_flag(TIF_ABI_PENDING);       \
+        else                                            \
+                clear_thread_flag(TIF_ABI_PENDING);     \
+        /* flush_thread will update pgd cache */        \
+        if (ibcs2)                                      \
+                set_personality(PER_SVR4);              \
+        else if (current->personality != PER_LINUX32)   \
+                set_personality(PER_LINUX);             \
+} while (0)
+
+#endif /* !(__ASM_SPARC64_ELF_H) */
diff --git a/arch/sparc/include/asm/emergency-restart.h b/arch/sparc/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/sparc/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/sparc/include/asm/envctrl.h b/arch/sparc/include/asm/envctrl.h
new file mode 100644
index 000000000000..624fa7e2da8e
--- /dev/null
+++ b/arch/sparc/include/asm/envctrl.h
@@ -0,0 +1,103 @@
+/*
+ *
+ * envctrl.h: Definitions for access to the i2c environment
+ *            monitoring on Ultrasparc systems.
+ *
+ * Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
+ * Copyright (C) 2000  Vinh Truong  (vinh.truong@eng.sun.com)
+ * VT - Add all ioctl commands and environment status definitions
+ * VT - Add application note
+ */
+#ifndef _SPARC64_ENVCTRL_H
+#define _SPARC64_ENVCTRL_H 1
+
+#include <linux/ioctl.h>
+
+/* Application note:
+ *
+ * The driver supports 4 operations: open(), close(), ioctl(), read()
+ * The device name is /dev/envctrl.
+ * Below is sample usage:
+ *
+ *      fd = open("/dev/envtrl", O_RDONLY);
+ *      if (ioctl(fd, ENVCTRL_READ_SHUTDOWN_TEMPERATURE, 0) < 0)
+ *              printf("error\n");
+ *      ret = read(fd, buf, 10);
+ *      close(fd);
+ *
+ * Notice in the case of cpu voltage and temperature, the default is
+ * cpu0.  If we need to know the info of cpu1, cpu2, cpu3, we need to
+ * pass in cpu number in ioctl() last parameter.  For example, to
+ * get the voltage of cpu2:
+ *
+ *      ioctlbuf[0] = 2;
+ *      if (ioctl(fd, ENVCTRL_READ_CPU_VOLTAGE, ioctlbuf) < 0)
+ *              printf("error\n");
+ *      ret = read(fd, buf, 10);
+ *
+ * All the return values are in ascii.  So check read return value
+ * and do appropriate conversions in your application.
+ */
+
+/* IOCTL commands */
+
+/* Note: these commands reflect possible monitor features.
+ * Some boards choose to support some of the features only.
+ */
+#define ENVCTRL_RD_CPU_TEMPERATURE      _IOR('p', 0x40, int)
+#define ENVCTRL_RD_CPU_VOLTAGE          _IOR('p', 0x41, int)
+#define ENVCTRL_RD_FAN_STATUS           _IOR('p', 0x42, int)
+#define ENVCTRL_RD_WARNING_TEMPERATURE  _IOR('p', 0x43, int)
+#define ENVCTRL_RD_SHUTDOWN_TEMPERATURE _IOR('p', 0x44, int)
+#define ENVCTRL_RD_VOLTAGE_STATUS       _IOR('p', 0x45, int)
+#define ENVCTRL_RD_SCSI_TEMPERATURE     _IOR('p', 0x46, int)
+#define ENVCTRL_RD_ETHERNET_TEMPERATURE _IOR('p', 0x47, int)
+#define ENVCTRL_RD_MTHRBD_TEMPERATURE   _IOR('p', 0x48, int)
+
+#define ENVCTRL_RD_GLOBALADDRESS        _IOR('p', 0x49, int)
+
+/* Read return values for a voltage status request. */
+#define ENVCTRL_VOLTAGE_POWERSUPPLY_GOOD        0x01
+#define ENVCTRL_VOLTAGE_BAD                     0x02
+#define ENVCTRL_POWERSUPPLY_BAD                 0x03
+#define ENVCTRL_VOLTAGE_POWERSUPPLY_BAD         0x04
+
+/* Read return values for a fan status request.
+ * A failure match means either the fan fails or
+ * the fan is not connected.  Some boards have optional
+ * connectors to connect extra fans.
+ *
+ * There are maximum 8 monitor fans.  Some are cpu fans
+ * some are system fans.  The mask below only indicates
+ * fan by order number.
+ * Below is a sample application:
+ *
+ *      if (ioctl(fd, ENVCTRL_READ_FAN_STATUS, 0) < 0) {
+ *              printf("ioctl fan failed\n");
+ *      }
+ *      if (read(fd, rslt, 1) <= 0) {
+ *              printf("error or fan not monitored\n");
+ *      } else {
+ *              if (rslt[0] == ENVCTRL_ALL_FANS_GOOD) {
+ *                      printf("all fans good\n");
+ *      } else if (rslt[0] == ENVCTRL_ALL_FANS_BAD) {
+ *              printf("all fans bad\n");
+ *      } else {
+ *              if (rslt[0] & ENVCTRL_FAN0_FAILURE_MASK) {
+ *                      printf("fan 0 failed or not connected\n");
+ *      }
+ *      ......
+ */
+
+#define ENVCTRL_ALL_FANS_GOOD                   0x00
+#define ENVCTRL_FAN0_FAILURE_MASK               0x01
+#define ENVCTRL_FAN1_FAILURE_MASK               0x02
+#define ENVCTRL_FAN2_FAILURE_MASK               0x04
+#define ENVCTRL_FAN3_FAILURE_MASK               0x08
+#define ENVCTRL_FAN4_FAILURE_MASK               0x10
+#define ENVCTRL_FAN5_FAILURE_MASK               0x20
+#define ENVCTRL_FAN6_FAILURE_MASK               0x40
+#define ENVCTRL_FAN7_FAILURE_MASK               0x80
+#define ENVCTRL_ALL_FANS_BAD                    0xFF
+
+#endif /* !(_SPARC64_ENVCTRL_H) */
diff --git a/arch/sparc/include/asm/errno.h b/arch/sparc/include/asm/errno.h
new file mode 100644
index 000000000000..a9ef172977de
--- /dev/null
+++ b/arch/sparc/include/asm/errno.h
@@ -0,0 +1,113 @@
+#ifndef _SPARC_ERRNO_H
+#define _SPARC_ERRNO_H
+
+/* These match the SunOS error numbering scheme. */
+
+#include <asm-generic/errno-base.h>
+
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define EINPROGRESS     36      /* Operation now in progress */
+#define EALREADY        37      /* Operation already in progress */
+#define ENOTSOCK        38      /* Socket operation on non-socket */
+#define EDESTADDRREQ    39      /* Destination address required */
+#define EMSGSIZE        40      /* Message too long */
+#define EPROTOTYPE      41      /* Protocol wrong type for socket */
+#define ENOPROTOOPT     42      /* Protocol not available */
+#define EPROTONOSUPPORT 43      /* Protocol not supported */
+#define ESOCKTNOSUPPORT 44      /* Socket type not supported */
+#define EOPNOTSUPP      45      /* Op not supported on transport endpoint */
+#define EPFNOSUPPORT    46      /* Protocol family not supported */
+#define EAFNOSUPPORT    47      /* Address family not supported by protocol */
+#define EADDRINUSE      48      /* Address already in use */
+#define EADDRNOTAVAIL   49      /* Cannot assign requested address */
+#define ENETDOWN        50      /* Network is down */
+#define ENETUNREACH     51      /* Network is unreachable */
+#define ENETRESET       52      /* Net dropped connection because of reset */
+#define ECONNABORTED    53      /* Software caused connection abort */
+#define ECONNRESET      54      /* Connection reset by peer */
+#define ENOBUFS         55      /* No buffer space available */
+#define EISCONN         56      /* Transport endpoint is already connected */
+#define ENOTCONN        57      /* Transport endpoint is not connected */
+#define ESHUTDOWN       58      /* No send after transport endpoint shutdown */
+#define ETOOMANYREFS    59      /* Too many references: cannot splice */
+#define ETIMEDOUT       60      /* Connection timed out */
+#define ECONNREFUSED    61      /* Connection refused */
+#define ELOOP           62      /* Too many symbolic links encountered */
+#define ENAMETOOLONG    63      /* File name too long */
+#define EHOSTDOWN       64      /* Host is down */
+#define EHOSTUNREACH    65      /* No route to host */
+#define ENOTEMPTY       66      /* Directory not empty */
+#define EPROCLIM        67      /* SUNOS: Too many processes */
+#define EUSERS          68      /* Too many users */
+#define EDQUOT          69      /* Quota exceeded */
+#define ESTALE          70      /* Stale NFS file handle */
+#define EREMOTE         71      /* Object is remote */
+#define ENOSTR          72      /* Device not a stream */
+#define ETIME           73      /* Timer expired */
+#define ENOSR           74      /* Out of streams resources */
+#define ENOMSG          75      /* No message of desired type */
+#define EBADMSG         76      /* Not a data message */
+#define EIDRM           77      /* Identifier removed */
+#define EDEADLK         78      /* Resource deadlock would occur */
+#define ENOLCK          79      /* No record locks available */
+#define ENONET          80      /* Machine is not on the network */
+#define ERREMOTE        81      /* SunOS: Too many lvls of remote in path */
+#define ENOLINK         82      /* Link has been severed */
+#define EADV            83      /* Advertise error */
+#define ESRMNT          84      /* Srmount error */
+#define ECOMM           85      /* Communication error on send */
+#define EPROTO          86      /* Protocol error */
+#define EMULTIHOP       87      /* Multihop attempted */
+#define EDOTDOT         88      /* RFS specific error */
+#define EREMCHG         89      /* Remote address changed */
+#define ENOSYS          90      /* Function not implemented */
+
+/* The rest have no SunOS equivalent. */
+#define ESTRPIPE        91      /* Streams pipe error */
+#define EOVERFLOW       92      /* Value too large for defined data type */
+#define EBADFD          93      /* File descriptor in bad state */
+#define ECHRNG          94      /* Channel number out of range */
+#define EL2NSYNC        95      /* Level 2 not synchronized */
+#define EL3HLT          96      /* Level 3 halted */
+#define EL3RST          97      /* Level 3 reset */
+#define ELNRNG          98      /* Link number out of range */
+#define EUNATCH         99      /* Protocol driver not attached */
+#define ENOCSI          100     /* No CSI structure available */
+#define EL2HLT          101     /* Level 2 halted */
+#define EBADE           102     /* Invalid exchange */
+#define EBADR           103     /* Invalid request descriptor */
+#define EXFULL          104     /* Exchange full */
+#define ENOANO          105     /* No anode */
+#define EBADRQC         106     /* Invalid request code */
+#define EBADSLT         107     /* Invalid slot */
+#define EDEADLOCK       108     /* File locking deadlock error */
+#define EBFONT          109     /* Bad font file format */
+#define ELIBEXEC        110     /* Cannot exec a shared library directly */
+#define ENODATA         111     /* No data available */
+#define ELIBBAD         112     /* Accessing a corrupted shared library */
+#define ENOPKG          113     /* Package not installed */
+#define ELIBACC         114     /* Can not access a needed shared library */
+#define ENOTUNIQ        115     /* Name not unique on network */
+#define ERESTART        116     /* Interrupted syscall should be restarted */
+#define EUCLEAN         117     /* Structure needs cleaning */
+#define ENOTNAM         118     /* Not a XENIX named type file */
+#define ENAVAIL         119     /* No XENIX semaphores available */
+#define EISNAM          120     /* Is a named type file */
+#define EREMOTEIO       121     /* Remote I/O error */
+#define EILSEQ          122     /* Illegal byte sequence */
+#define ELIBMAX         123     /* Atmpt to link in too many shared libs */
+#define ELIBSCN         124     /* .lib section in a.out corrupted */
+
+#define ENOMEDIUM       125     /* No medium found */
+#define EMEDIUMTYPE     126     /* Wrong medium type */
+#define ECANCELED       127     /* Operation Cancelled */
+#define ENOKEY          128     /* Required key not available */
+#define EKEYEXPIRED     129     /* Key has expired */
+#define EKEYREVOKED     130     /* Key has been revoked */
+#define EKEYREJECTED    131     /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD      132     /* Owner died */
+#define ENOTRECOVERABLE 133     /* State not recoverable */
+
+#endif
diff --git a/arch/sparc/include/asm/estate.h b/arch/sparc/include/asm/estate.h
new file mode 100644
index 000000000000..520c08560d1b
--- /dev/null
+++ b/arch/sparc/include/asm/estate.h
@@ -0,0 +1,49 @@
+#ifndef _SPARC64_ESTATE_H
+#define _SPARC64_ESTATE_H
+
+/* UltraSPARC-III E-cache Error Enable */
+#define ESTATE_ERROR_FMT        0x0000000000040000 /* Force MTAG ECC            */
+#define ESTATE_ERROR_FMESS      0x000000000003c000 /* Forced MTAG ECC val       */
+#define ESTATE_ERROR_FMD        0x0000000000002000 /* Force DATA ECC            */
+#define ESTATE_ERROR_FDECC      0x0000000000001ff0 /* Forced DATA ECC val       */
+#define ESTATE_ERROR_UCEEN      0x0000000000000008 /* See below                 */
+#define ESTATE_ERROR_NCEEN      0x0000000000000002 /* See below                 */
+#define ESTATE_ERROR_CEEN       0x0000000000000001 /* See below                 */
+
+/* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
+ * errors 2) uncorrectable E-cache errors.  Such events only occur on reads
+ * of the E-cache by the local processor for: 1) data loads 2) instruction
+ * fetches 3) atomic operations.  Such events _cannot_ occur for: 1) merge
+ * 2) writeback 2) copyout.  The AFSR bits associated with these traps are
+ * UCC and UCU.
+ */
+
+/* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
+ * for uncorrectable ECC errors and system errors.
+ *
+ * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
+ * or system bus BusERR:
+ * 1) As the result of an instruction fetch, will generate instruction_access_error
+ * 2) As the result of a load etc. will generate data_access_error.
+ * 3) As the result of store merge completion, writeback, or copyout will
+ *    generate a disrupting ECC_error trap.
+ * 4) As the result of such errors on instruction vector fetch can generate any
+ *    of the 3 trap types.
+ *
+ * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
+ * BERR, and TO.
+ */
+
+/* CEEN enables the ECC_error trap for hardware corrected ECC errors.  System bus
+ * reads resulting in a hardware corrected data or MTAG ECC error will generate an
+ * ECC_error disrupting trap with this bit enabled.
+ *
+ * This same trap will also be generated when a hardware corrected ECC error results
+ * during store merge, writeback, and copyout operations.
+ */
+
+/* In general, if the trap enable bits above are disabled the AFSR bits will still
+ * log the events even though the trap will not be generated by the processor.
+ */
+
+#endif /* _SPARC64_ESTATE_H */
diff --git a/arch/sparc/include/asm/fb.h b/arch/sparc/include/asm/fb.h
new file mode 100644
index 000000000000..b83e44729655
--- /dev/null
+++ b/arch/sparc/include/asm/fb.h
@@ -0,0 +1,29 @@
+#ifndef _SPARC_FB_H_
+#define _SPARC_FB_H_
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+#include <asm/prom.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+#ifdef CONFIG_SPARC64
+        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+#endif
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        struct device *dev = info->device;
+        struct device_node *node;
+
+        node = dev->archdata.prom_node;
+        if (node &&
+            node == of_console_device)
+                return 1;
+
+        return 0;
+}
+
+#endif /* _SPARC_FB_H_ */
diff --git a/arch/sparc/include/asm/fbio.h b/arch/sparc/include/asm/fbio.h
new file mode 100644
index 000000000000..b9215a0907d3
--- /dev/null
+++ b/arch/sparc/include/asm/fbio.h
@@ -0,0 +1,330 @@
+#ifndef __LINUX_FBIO_H
+#define __LINUX_FBIO_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+/* Constants used for fbio SunOS compatibility */
+/* (C) 1996 Miguel de Icaza */
+
+/* Frame buffer types */
+#define FBTYPE_NOTYPE           -1
+#define FBTYPE_SUN1BW           0   /* mono */
+#define FBTYPE_SUN1COLOR        1 
+#define FBTYPE_SUN2BW           2 
+#define FBTYPE_SUN2COLOR        3 
+#define FBTYPE_SUN2GP           4 
+#define FBTYPE_SUN5COLOR        5 
+#define FBTYPE_SUN3COLOR        6 
+#define FBTYPE_MEMCOLOR         7 
+#define FBTYPE_SUN4COLOR        8 
+ 
+#define FBTYPE_NOTSUN1          9 
+#define FBTYPE_NOTSUN2          10
+#define FBTYPE_NOTSUN3          11
+ 
+#define FBTYPE_SUNFAST_COLOR    12  /* cg6 */
+#define FBTYPE_SUNROP_COLOR     13
+#define FBTYPE_SUNFB_VIDEO      14
+#define FBTYPE_SUNGIFB          15
+#define FBTYPE_SUNGPLAS         16
+#define FBTYPE_SUNGP3           17
+#define FBTYPE_SUNGT            18
+#define FBTYPE_SUNLEO           19      /* zx Leo card */
+#define FBTYPE_MDICOLOR         20      /* cg14 */
+#define FBTYPE_TCXCOLOR         21      /* SUNW,tcx card */
+
+#define FBTYPE_LASTPLUSONE      21      /* This is not last + 1 in fact... */
+
+/* Does not seem to be listed in the Sun file either */
+#define FBTYPE_CREATOR          22
+#define FBTYPE_PCI_IGA1682      23
+#define FBTYPE_P9100COLOR       24
+
+#define FBTYPE_PCI_GENERIC      1000
+#define FBTYPE_PCI_MACH64       1001
+
+/* fbio ioctls */
+/* Returned by FBIOGTYPE */
+struct  fbtype {
+        int     fb_type;        /* fb type, see above */
+        int     fb_height;      /* pixels */
+        int     fb_width;       /* pixels */
+        int     fb_depth;
+        int     fb_cmsize;      /* color map entries */
+        int     fb_size;        /* fb size in bytes */
+};
+#define FBIOGTYPE _IOR('F', 0, struct fbtype)
+
+struct  fbcmap {
+        int             index;          /* first element (0 origin) */
+        int             count;
+        unsigned char   __user *red;
+        unsigned char   __user *green;
+        unsigned char   __user *blue;
+};
+
+#ifdef __KERNEL__
+#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
+#else
+#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
+#endif
+
+/* # of device specific values */
+#define FB_ATTR_NDEVSPECIFIC    8
+/* # of possible emulations */
+#define FB_ATTR_NEMUTYPES       4
+ 
+struct fbsattr {
+        int     flags;
+        int     emu_type;       /* -1 if none */
+        int     dev_specific[FB_ATTR_NDEVSPECIFIC];
+};
+ 
+struct fbgattr {
+        int     real_type;      /* real frame buffer type */
+        int     owner;          /* unknown */
+        struct fbtype fbtype;   /* real frame buffer fbtype */
+        struct fbsattr sattr;   
+        int     emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
+};
+#define FBIOSATTR  _IOW('F', 5, struct fbgattr) /* Unsupported: */
+#define FBIOGATTR  _IOR('F', 6, struct fbgattr) /* supported */
+
+#define FBIOSVIDEO _IOW('F', 7, int)
+#define FBIOGVIDEO _IOR('F', 8, int)
+
+struct fbcursor {
+        short set;              /* what to set, choose from the list above */
+        short enable;           /* cursor on/off */
+        struct fbcurpos pos;    /* cursor position */
+        struct fbcurpos hot;    /* cursor hot spot */
+        struct fbcmap cmap;     /* color map info */
+        struct fbcurpos size;   /* cursor bit map size */
+        char __user *image;     /* cursor image bits */
+        char __user *mask;      /* cursor mask bits */
+};
+
+/* set/get cursor attributes/shape */
+#define FBIOSCURSOR     _IOW('F', 24, struct fbcursor)
+#define FBIOGCURSOR     _IOWR('F', 25, struct fbcursor)
+ 
+/* set/get cursor position */
+#define FBIOSCURPOS     _IOW('F', 26, struct fbcurpos)
+#define FBIOGCURPOS     _IOW('F', 27, struct fbcurpos)
+ 
+/* get max cursor size */
+#define FBIOGCURMAX     _IOR('F', 28, struct fbcurpos)
+
+/* wid manipulation */
+struct fb_wid_alloc {
+#define FB_WID_SHARED_8         0
+#define FB_WID_SHARED_24        1
+#define FB_WID_DBL_8            2
+#define FB_WID_DBL_24           3
+        __u32   wa_type;
+        __s32   wa_index;       /* Set on return */
+        __u32   wa_count;       
+};
+struct fb_wid_item {
+        __u32   wi_type;
+        __s32   wi_index;
+        __u32   wi_attrs;
+        __u32   wi_values[32];
+};
+struct fb_wid_list {
+        __u32   wl_flags;
+        __u32   wl_count;
+        struct fb_wid_item      *wl_list;
+};
+
+#define FBIO_WID_ALLOC  _IOWR('F', 30, struct fb_wid_alloc)
+#define FBIO_WID_FREE   _IOW('F', 31, struct fb_wid_alloc)
+#define FBIO_WID_PUT    _IOW('F', 32, struct fb_wid_list)
+#define FBIO_WID_GET    _IOWR('F', 33, struct fb_wid_list)
+
+/* Creator ioctls */
+#define FFB_IOCTL       ('F'<<8)
+#define FFB_SYS_INFO            (FFB_IOCTL|80)
+#define FFB_CLUTREAD            (FFB_IOCTL|81)
+#define FFB_CLUTPOST            (FFB_IOCTL|82)
+#define FFB_SETDIAGMODE         (FFB_IOCTL|83)
+#define FFB_GETMONITORID        (FFB_IOCTL|84)
+#define FFB_GETVIDEOMODE        (FFB_IOCTL|85)
+#define FFB_SETVIDEOMODE        (FFB_IOCTL|86)
+#define FFB_SETSERVER           (FFB_IOCTL|87)
+#define FFB_SETOVCTL            (FFB_IOCTL|88)
+#define FFB_GETOVCTL            (FFB_IOCTL|89)
+#define FFB_GETSAXNUM           (FFB_IOCTL|90)
+#define FFB_FBDEBUG             (FFB_IOCTL|91)
+
+/* Cg14 ioctls */
+#define MDI_IOCTL          ('M'<<8)
+#define MDI_RESET          (MDI_IOCTL|1)
+#define MDI_GET_CFGINFO    (MDI_IOCTL|2)
+#define MDI_SET_PIXELMODE  (MDI_IOCTL|3)
+#    define MDI_32_PIX     32
+#    define MDI_16_PIX     16
+#    define MDI_8_PIX      8
+
+struct mdi_cfginfo {
+        int     mdi_ncluts;     /* Number of implemented CLUTs in this MDI */
+        int     mdi_type;       /* FBTYPE name */
+        int     mdi_height;     /* height */
+        int     mdi_width;      /* widht */
+        int     mdi_size;       /* available ram */
+        int     mdi_mode;       /* 8bpp, 16bpp or 32bpp */
+        int     mdi_pixfreq;    /* pixel clock (from PROM) */
+};
+
+/* SparcLinux specific ioctl for the MDI, should be replaced for
+ * the SET_XLUT/SET_CLUTn ioctls instead
+ */
+#define MDI_CLEAR_XLUT       (MDI_IOCTL|9)
+
+/* leo & ffb ioctls */
+struct fb_clut_alloc {
+        __u32   clutid; /* Set on return */
+        __u32   flag;
+        __u32   index;
+};
+
+struct fb_clut {
+#define FB_CLUT_WAIT    0x00000001      /* Not yet implemented */
+        __u32   flag;
+        __u32   clutid;
+        __u32   offset;
+        __u32   count;
+        char *  red;
+        char *  green;
+        char *  blue;
+};
+
+struct fb_clut32 {
+        __u32   flag;
+        __u32   clutid;
+        __u32   offset;
+        __u32   count;
+        __u32   red;
+        __u32   green;
+        __u32   blue;
+};
+
+#define LEO_CLUTALLOC   _IOWR('L', 53, struct fb_clut_alloc)
+#define LEO_CLUTFREE    _IOW('L', 54, struct fb_clut_alloc)
+#define LEO_CLUTREAD    _IOW('L', 55, struct fb_clut)
+#define LEO_CLUTPOST    _IOW('L', 56, struct fb_clut)
+#define LEO_SETGAMMA    _IOW('L', 68, int) /* Not yet implemented */
+#define LEO_GETGAMMA    _IOR('L', 69, int) /* Not yet implemented */
+
+#ifdef __KERNEL__
+/* Addresses on the fd of a cgsix that are mappable */
+#define CG6_FBC    0x70000000
+#define CG6_TEC    0x70001000
+#define CG6_BTREGS 0x70002000
+#define CG6_FHC    0x70004000
+#define CG6_THC    0x70005000
+#define CG6_ROM    0x70006000
+#define CG6_RAM    0x70016000
+#define CG6_DHC    0x80000000
+
+#define CG3_MMAP_OFFSET 0x4000000
+
+/* Addresses on the fd of a tcx that are mappable */
+#define TCX_RAM8BIT             0x00000000
+#define TCX_RAM24BIT            0x01000000
+#define TCX_UNK3                0x10000000
+#define TCX_UNK4                0x20000000
+#define TCX_CONTROLPLANE        0x28000000
+#define TCX_UNK6                0x30000000
+#define TCX_UNK7                0x38000000
+#define TCX_TEC                 0x70000000
+#define TCX_BTREGS              0x70002000
+#define TCX_THC                 0x70004000
+#define TCX_DHC                 0x70008000
+#define TCX_ALT                 0x7000a000
+#define TCX_SYNC                0x7000e000
+#define TCX_UNK2                0x70010000
+
+/* CG14 definitions */
+
+/* Offsets into the OBIO space: */
+#define CG14_REGS        0       /* registers */
+#define CG14_CURSORREGS  0x1000  /* cursor registers */
+#define CG14_DACREGS     0x2000  /* DAC registers */
+#define CG14_XLUT        0x3000  /* X Look Up Table -- ??? */
+#define CG14_CLUT1       0x4000  /* Color Look Up Table */
+#define CG14_CLUT2       0x5000  /* Color Look Up Table */
+#define CG14_CLUT3       0x6000  /* Color Look Up Table */
+#define CG14_AUTO        0xf000
+
+#endif /* KERNEL */
+
+/* These are exported to userland for applications to use */
+/* Mappable offsets for the cg14: control registers */
+#define MDI_DIRECT_MAP 0x10000000
+#define MDI_CTLREG_MAP 0x20000000
+#define MDI_CURSOR_MAP 0x30000000
+#define MDI_SHDW_VRT_MAP 0x40000000
+
+/* Mappable offsets for the cg14: frame buffer resolutions */
+/* 32 bits */
+#define MDI_CHUNKY_XBGR_MAP 0x50000000
+#define MDI_CHUNKY_BGR_MAP 0x60000000
+
+/* 16 bits */
+#define MDI_PLANAR_X16_MAP 0x70000000
+#define MDI_PLANAR_C16_MAP 0x80000000
+
+/* 8 bit is done as CG3 MMAP offset */
+/* 32 bits, planar */
+#define MDI_PLANAR_X32_MAP 0x90000000
+#define MDI_PLANAR_B32_MAP 0xa0000000
+#define MDI_PLANAR_G32_MAP 0xb0000000
+#define MDI_PLANAR_R32_MAP 0xc0000000
+
+/* Mappable offsets on leo */
+#define LEO_SS0_MAP            0x00000000
+#define LEO_LC_SS0_USR_MAP     0x00800000
+#define LEO_LD_SS0_MAP         0x00801000
+#define LEO_LX_CURSOR_MAP      0x00802000
+#define LEO_SS1_MAP            0x00803000
+#define LEO_LC_SS1_USR_MAP     0x01003000
+#define LEO_LD_SS1_MAP         0x01004000
+#define LEO_UNK_MAP            0x01005000
+#define LEO_LX_KRN_MAP         0x01006000
+#define LEO_LC_SS0_KRN_MAP     0x01007000
+#define LEO_LC_SS1_KRN_MAP     0x01008000
+#define LEO_LD_GBL_MAP         0x01009000
+#define LEO_UNK2_MAP           0x0100a000
+
+#ifdef __KERNEL__
+struct  fbcmap32 {
+        int             index;          /* first element (0 origin) */
+        int             count;
+        u32             red;
+        u32             green;
+        u32             blue;
+};
+
+#define FBIOPUTCMAP32   _IOW('F', 3, struct fbcmap32)
+#define FBIOGETCMAP32   _IOW('F', 4, struct fbcmap32)
+
+struct fbcursor32 {
+        short set;              /* what to set, choose from the list above */
+        short enable;           /* cursor on/off */
+        struct fbcurpos pos;    /* cursor position */
+        struct fbcurpos hot;    /* cursor hot spot */
+        struct fbcmap32 cmap;   /* color map info */
+        struct fbcurpos size;   /* cursor bit map size */
+        u32     image;          /* cursor image bits */
+        u32     mask;           /* cursor mask bits */
+};
+
+#define FBIOSCURSOR32   _IOW('F', 24, struct fbcursor32)
+#define FBIOGCURSOR32   _IOW('F', 25, struct fbcursor32)
+#endif
+
+#endif /* __LINUX_FBIO_H */
diff --git a/arch/sparc/include/asm/fcntl.h b/arch/sparc/include/asm/fcntl.h
new file mode 100644
index 000000000000..d4d9c9d852c3
--- /dev/null
+++ b/arch/sparc/include/asm/fcntl.h
@@ -0,0 +1,40 @@
+#ifndef _SPARC_FCNTL_H
+#define _SPARC_FCNTL_H
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+   located on an ext2 file system */
+#define O_APPEND        0x0008
+#define FASYNC          0x0040  /* fcntl, for BSD compatibility */
+#define O_CREAT         0x0200  /* not fcntl */
+#define O_TRUNC         0x0400  /* not fcntl */
+#define O_EXCL          0x0800  /* not fcntl */
+#define O_SYNC          0x2000
+#define O_NONBLOCK      0x4000
+#if defined(__sparc__) && defined(__arch64__)
+#define O_NDELAY        0x0004
+#else
+#define O_NDELAY        (0x0004 | O_NONBLOCK)
+#endif
+#define O_NOCTTY        0x8000  /* not fcntl */
+#define O_LARGEFILE     0x40000
+#define O_DIRECT        0x100000 /* direct disk access hint */
+#define O_NOATIME       0x200000
+#define O_CLOEXEC       0x400000
+
+#define F_GETOWN        5       /*  for sockets. */
+#define F_SETOWN        6       /*  for sockets. */
+#define F_GETLK         7
+#define F_SETLK         8
+#define F_SETLKW        9
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK         1
+#define F_WRLCK         2
+#define F_UNLCK         3
+
+#define __ARCH_FLOCK_PAD        short __unused;
+#define __ARCH_FLOCK64_PAD      short __unused;
+
+#include <asm-generic/fcntl.h>
+
+#endif
diff --git a/arch/sparc/include/asm/fhc.h b/arch/sparc/include/asm/fhc.h
new file mode 100644
index 000000000000..788cbc46a116
--- /dev/null
+++ b/arch/sparc/include/asm/fhc.h
@@ -0,0 +1,121 @@
+/*
+ * fhc.h: Structures for central/fhc pseudo driver on Sunfire/Starfire/Wildfire.
+ *
+ * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _SPARC64_FHC_H
+#define _SPARC64_FHC_H
+
+#include <linux/timer.h>
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/upa.h>
+
+struct linux_fhc;
+
+/* Clock board register offsets. */
+#define CLOCK_CTRL      0x00UL  /* Main control */
+#define CLOCK_STAT1     0x10UL  /* Status one */
+#define CLOCK_STAT2     0x20UL  /* Status two */
+#define CLOCK_PWRSTAT   0x30UL  /* Power status */
+#define CLOCK_PWRPRES   0x40UL  /* Power presence */
+#define CLOCK_TEMP      0x50UL  /* Temperature */
+#define CLOCK_IRQDIAG   0x60UL  /* IRQ diagnostics */
+#define CLOCK_PWRSTAT2  0x70UL  /* Power status two */
+
+#define CLOCK_CTRL_LLED         0x04    /* Left LED, 0 == on */
+#define CLOCK_CTRL_MLED         0x02    /* Mid LED, 1 == on */
+#define CLOCK_CTRL_RLED         0x01    /* RIght LED, 1 == on */
+
+struct linux_central {
+        struct linux_fhc                *child;
+        unsigned long                   cfreg;
+        unsigned long                   clkregs;
+        unsigned long                   clkver;
+        int                             slots;
+        struct device_node              *prom_node;
+
+        struct linux_prom_ranges        central_ranges[PROMREG_MAX];
+        int                             num_central_ranges;
+};
+
+/* Firehose controller register offsets */
+struct fhc_regs {
+        unsigned long                   pregs;  /* FHC internal regs */
+#define FHC_PREGS_ID    0x00UL  /* FHC ID */
+#define  FHC_ID_VERS            0xf0000000 /* Version of this FHC               */
+#define  FHC_ID_PARTID          0x0ffff000 /* Part ID code (0x0f9f == FHC)      */
+#define  FHC_ID_MANUF           0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/
+#define  FHC_ID_RESV            0x00000001 /* Read as one                       */
+#define FHC_PREGS_RCS   0x10UL  /* FHC Reset Control/Status Register */
+#define  FHC_RCS_POR            0x80000000 /* Last reset was a power cycle      */
+#define  FHC_RCS_SPOR           0x40000000 /* Last reset was sw power on reset  */
+#define  FHC_RCS_SXIR           0x20000000 /* Last reset was sw XIR reset       */
+#define  FHC_RCS_BPOR           0x10000000 /* Last reset was due to POR button  */
+#define  FHC_RCS_BXIR           0x08000000 /* Last reset was due to XIR button  */
+#define  FHC_RCS_WEVENT         0x04000000 /* CPU reset was due to wakeup event */
+#define  FHC_RCS_CFATAL         0x02000000 /* Centerplane Fatal Error signalled */
+#define  FHC_RCS_FENAB          0x01000000 /* Fatal errors elicit system reset  */
+#define FHC_PREGS_CTRL  0x20UL  /* FHC Control Register */
+#define  FHC_CONTROL_ICS        0x00100000 /* Ignore Centerplane Signals        */
+#define  FHC_CONTROL_FRST       0x00080000 /* Fatal Error Reset Enable          */
+#define  FHC_CONTROL_LFAT       0x00040000 /* AC/DC signalled a local error     */
+#define  FHC_CONTROL_SLINE      0x00010000 /* Firmware Synchronization Line     */
+#define  FHC_CONTROL_DCD        0x00008000 /* DC-->DC Converter Disable         */
+#define  FHC_CONTROL_POFF       0x00004000 /* AC/DC Controller PLL Disable      */
+#define  FHC_CONTROL_FOFF       0x00002000 /* FHC Controller PLL Disable        */
+#define  FHC_CONTROL_AOFF       0x00001000 /* CPU A SRAM/SBD Low Power Mode     */
+#define  FHC_CONTROL_BOFF       0x00000800 /* CPU B SRAM/SBD Low Power Mode     */
+#define  FHC_CONTROL_PSOFF      0x00000400 /* Turns off this FHC's power supply */
+#define  FHC_CONTROL_IXIST      0x00000200 /* 0=FHC tells clock board it exists */
+#define  FHC_CONTROL_XMSTR      0x00000100 /* 1=Causes this FHC to be XIR master*/
+#define  FHC_CONTROL_LLED       0x00000040 /* 0=Left LED ON                     */
+#define  FHC_CONTROL_MLED       0x00000020 /* 1=Middle LED ON                   */
+#define  FHC_CONTROL_RLED       0x00000010 /* 1=Right LED                       */
+#define  FHC_CONTROL_BPINS      0x00000003 /* Spare Bidirectional Pins          */
+#define FHC_PREGS_BSR   0x30UL  /* FHC Board Status Register */
+#define  FHC_BSR_DA64           0x00040000 /* Port A: 0=128bit 1=64bit data path */
+#define  FHC_BSR_DB64           0x00020000 /* Port B: 0=128bit 1=64bit data path */
+#define  FHC_BSR_BID            0x0001e000 /* Board ID                           */
+#define  FHC_BSR_SA             0x00001c00 /* Port A UPA Speed (from the pins)   */
+#define  FHC_BSR_SB             0x00000380 /* Port B UPA Speed (from the pins)   */
+#define  FHC_BSR_NDIAG          0x00000040 /* Not in Diag Mode                   */
+#define  FHC_BSR_NTBED          0x00000020 /* Not in TestBED Mode                */
+#define  FHC_BSR_NIA            0x0000001c /* Jumper, bit 18 in PROM space       */
+#define  FHC_BSR_SI             0x00000001 /* Spare input pin value              */
+#define FHC_PREGS_ECC   0x40UL  /* FHC ECC Control Register (16 bits) */
+#define FHC_PREGS_JCTRL 0xf0UL  /* FHC JTAG Control Register */
+#define  FHC_JTAG_CTRL_MENAB    0x80000000 /* Indicates this is JTAG Master      */
+#define  FHC_JTAG_CTRL_MNONE    0x40000000 /* Indicates no JTAG Master present   */
+#define FHC_PREGS_JCMD  0x100UL /* FHC JTAG Command Register */
+        unsigned long                   ireg;   /* FHC IGN reg */
+#define FHC_IREG_IGN    0x00UL  /* This FHC's IGN */
+        unsigned long                   ffregs; /* FHC fanfail regs */
+#define FHC_FFREGS_IMAP 0x00UL  /* FHC Fanfail IMAP */
+#define FHC_FFREGS_ICLR 0x10UL  /* FHC Fanfail ICLR */
+        unsigned long                   sregs;  /* FHC system regs */
+#define FHC_SREGS_IMAP  0x00UL  /* FHC System IMAP */
+#define FHC_SREGS_ICLR  0x10UL  /* FHC System ICLR */
+        unsigned long                   uregs;  /* FHC uart regs */
+#define FHC_UREGS_IMAP  0x00UL  /* FHC Uart IMAP */
+#define FHC_UREGS_ICLR  0x10UL  /* FHC Uart ICLR */
+        unsigned long                   tregs;  /* FHC TOD regs */
+#define FHC_TREGS_IMAP  0x00UL  /* FHC TOD IMAP */
+#define FHC_TREGS_ICLR  0x10UL  /* FHC TOD ICLR */
+};
+
+struct linux_fhc {
+        struct linux_fhc                *next;
+        struct linux_central            *parent;        /* NULL if not central FHC */
+        struct fhc_regs                 fhc_regs;
+        int                             board;
+        int                             jtag_master;
+        struct device_node              *prom_node;
+
+        struct linux_prom_ranges        fhc_ranges[PROMREG_MAX];
+        int                             num_fhc_ranges;
+};
+
+#endif /* !(_SPARC64_FHC_H) */
diff --git a/arch/sparc/include/asm/fixmap.h b/arch/sparc/include/asm/fixmap.h
new file mode 100644
index 000000000000..f18fc0755adf
--- /dev/null
+++ b/arch/sparc/include/asm/fixmap.h
@@ -0,0 +1,110 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <linux/kernel.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special  addresses
+ * from the top of unused virtual memory (0xfd000000 - 1 page) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanism,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+        FIX_HOLE,
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN,
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        __end_of_fixed_addresses
+};
+
+extern void __set_fixmap (enum fixed_addresses idx,
+                                        unsigned long phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between IO pages at 0xfd000000 and
+ * the start of the fixmap.
+ */
+#define FIXADDR_TOP     (0xfcfff000UL)
+#define FIXADDR_SIZE    ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+#endif
diff --git a/arch/sparc/include/asm/floppy.h b/arch/sparc/include/asm/floppy.h
new file mode 100644
index 000000000000..faebd335b600
--- /dev/null
+++ b/arch/sparc/include/asm/floppy.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_FLOPPY_H
+#define ___ASM_SPARC_FLOPPY_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/floppy_64.h>
+#else
+#include <asm/floppy_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h
new file mode 100644
index 000000000000..ae3f00bf22ff
--- /dev/null
+++ b/arch/sparc/include/asm/floppy_32.h
@@ -0,0 +1,388 @@
+/* asm/floppy.h: Sparc specific parts of the Floppy driver.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef __ASM_SPARC_FLOPPY_H
+#define __ASM_SPARC_FLOPPY_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/idprom.h>
+#include <asm/machines.h>
+#include <asm/oplib.h>
+#include <asm/auxio.h>
+#include <asm/irq.h>
+
+/* We don't need no stinkin' I/O port allocation crap. */
+#undef release_region
+#undef request_region
+#define release_region(X, Y)    do { } while(0)
+#define request_region(X, Y, Z) (1)
+
+/* References:
+ * 1) Netbsd Sun floppy driver.
+ * 2) NCR 82077 controller manual
+ * 3) Intel 82077 controller manual
+ */
+struct sun_flpy_controller {
+        volatile unsigned char status_82072;  /* Main Status reg. */
+#define dcr_82072              status_82072   /* Digital Control reg. */
+#define status1_82077          status_82072   /* Auxiliary Status reg. 1 */
+
+        volatile unsigned char data_82072;    /* Data fifo. */
+#define status2_82077          data_82072     /* Auxiliary Status reg. 2 */
+
+        volatile unsigned char dor_82077;     /* Digital Output reg. */
+        volatile unsigned char tapectl_82077; /* What the? Tape control reg? */
+
+        volatile unsigned char status_82077;  /* Main Status Register. */
+#define drs_82077              status_82077   /* Digital Rate Select reg. */
+
+        volatile unsigned char data_82077;    /* Data fifo. */
+        volatile unsigned char ___unused;
+        volatile unsigned char dir_82077;     /* Digital Input reg. */
+#define dcr_82077              dir_82077      /* Config Control reg. */
+};
+
+/* You'll only ever find one controller on a SparcStation anyways. */
+static struct sun_flpy_controller *sun_fdc = NULL;
+extern volatile unsigned char *fdc_status;
+
+struct sun_floppy_ops {
+        unsigned char (*fd_inb)(int port);
+        void (*fd_outb)(unsigned char value, int port);
+};
+
+static struct sun_floppy_ops sun_fdops;
+
+#define fd_inb(port)              sun_fdops.fd_inb(port)
+#define fd_outb(value,port)       sun_fdops.fd_outb(value,port)
+#define fd_enable_dma()           sun_fd_enable_dma()
+#define fd_disable_dma()          sun_fd_disable_dma()
+#define fd_request_dma()          (0) /* nothing... */
+#define fd_free_dma()             /* nothing... */
+#define fd_clear_dma_ff()         /* nothing... */
+#define fd_set_dma_mode(mode)     sun_fd_set_dma_mode(mode)
+#define fd_set_dma_addr(addr)     sun_fd_set_dma_addr(addr)
+#define fd_set_dma_count(count)   sun_fd_set_dma_count(count)
+#define fd_enable_irq()           /* nothing... */
+#define fd_disable_irq()          /* nothing... */
+#define fd_cacheflush(addr, size) /* nothing... */
+#define fd_request_irq()          sun_fd_request_irq()
+#define fd_free_irq()             /* nothing... */
+#if 0  /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
+#define fd_dma_mem_alloc(size)    ((unsigned long) vmalloc(size))
+#define fd_dma_mem_free(addr,size) (vfree((void *)(addr)))
+#endif
+
+/* XXX This isn't really correct. XXX */
+#define get_dma_residue(x)        (0)
+
+#define FLOPPY0_TYPE  4
+#define FLOPPY1_TYPE  0
+
+/* Super paranoid... */
+#undef HAVE_DISABLE_HLT
+
+/* Here is where we catch the floppy driver trying to initialize,
+ * therefore this is where we call the PROM device tree probing
+ * routine etc. on the Sparc.
+ */
+#define FDC1                      sun_floppy_init()
+
+#define N_FDC    1
+#define N_DRIVE  8
+
+/* No 64k boundary crossing problems on the Sparc. */
+#define CROSS_64KB(a,s) (0)
+
+/* Routines unique to each controller type on a Sun. */
+static void sun_set_dor(unsigned char value, int fdc_82077)
+{
+        if (sparc_cpu_model == sun4c) {
+                unsigned int bits = 0;
+                if (value & 0x10)
+                        bits |= AUXIO_FLPY_DSEL;
+                if ((value & 0x80) == 0)
+                        bits |= AUXIO_FLPY_EJCT;
+                set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
+        }
+        if (fdc_82077) {
+                sun_fdc->dor_82077 = value;
+        }
+}
+
+static unsigned char sun_read_dir(void)
+{
+        if (sparc_cpu_model == sun4c)
+                return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0;
+        else
+                return sun_fdc->dir_82077;
+}
+
+static unsigned char sun_82072_fd_inb(int port)
+{
+        udelay(5);
+        switch(port & 7) {
+        default:
+                printk("floppy: Asked to read unknown port %d\n", port);
+                panic("floppy: Port bolixed.");
+        case 4: /* FD_STATUS */
+                return sun_fdc->status_82072 & ~STATUS_DMA;
+        case 5: /* FD_DATA */
+                return sun_fdc->data_82072;
+        case 7: /* FD_DIR */
+                return sun_read_dir();
+        };
+        panic("sun_82072_fd_inb: How did I get here?");
+}
+
+static void sun_82072_fd_outb(unsigned char value, int port)
+{
+        udelay(5);
+        switch(port & 7) {
+        default:
+                printk("floppy: Asked to write to unknown port %d\n", port);
+                panic("floppy: Port bolixed.");
+        case 2: /* FD_DOR */
+                sun_set_dor(value, 0);
+                break;
+        case 5: /* FD_DATA */
+                sun_fdc->data_82072 = value;
+                break;
+        case 7: /* FD_DCR */
+                sun_fdc->dcr_82072 = value;
+                break;
+        case 4: /* FD_STATUS */
+                sun_fdc->status_82072 = value;
+                break;
+        };
+        return;
+}
+
+static unsigned char sun_82077_fd_inb(int port)
+{
+        udelay(5);
+        switch(port & 7) {
+        default:
+                printk("floppy: Asked to read unknown port %d\n", port);
+                panic("floppy: Port bolixed.");
+        case 0: /* FD_STATUS_0 */
+                return sun_fdc->status1_82077;
+        case 1: /* FD_STATUS_1 */
+                return sun_fdc->status2_82077;
+        case 2: /* FD_DOR */
+                return sun_fdc->dor_82077;
+        case 3: /* FD_TDR */
+                return sun_fdc->tapectl_82077;
+        case 4: /* FD_STATUS */
+                return sun_fdc->status_82077 & ~STATUS_DMA;
+        case 5: /* FD_DATA */
+                return sun_fdc->data_82077;
+        case 7: /* FD_DIR */
+                return sun_read_dir();
+        };
+        panic("sun_82077_fd_inb: How did I get here?");
+}
+
+static void sun_82077_fd_outb(unsigned char value, int port)
+{
+        udelay(5);
+        switch(port & 7) {
+        default:
+                printk("floppy: Asked to write to unknown port %d\n", port);
+                panic("floppy: Port bolixed.");
+        case 2: /* FD_DOR */
+                sun_set_dor(value, 1);
+                break;
+        case 5: /* FD_DATA */
+                sun_fdc->data_82077 = value;
+                break;
+        case 7: /* FD_DCR */
+                sun_fdc->dcr_82077 = value;
+                break;
+        case 4: /* FD_STATUS */
+                sun_fdc->status_82077 = value;
+                break;
+        case 3: /* FD_TDR */
+                sun_fdc->tapectl_82077 = value;
+                break;
+        };
+        return;
+}
+
+/* For pseudo-dma (Sun floppy drives have no real DMA available to
+ * them so we must eat the data fifo bytes directly ourselves) we have
+ * three state variables.  doing_pdma tells our inline low-level
+ * assembly floppy interrupt entry point whether it should sit and eat
+ * bytes from the fifo or just transfer control up to the higher level
+ * floppy interrupt c-code.  I tried very hard but I could not get the
+ * pseudo-dma to work in c-code without getting many overruns and
+ * underruns.  If non-zero, doing_pdma encodes the direction of
+ * the transfer for debugging.  1=read 2=write
+ */
+extern char *pdma_vaddr;
+extern unsigned long pdma_size;
+extern volatile int doing_pdma;
+
+/* This is software state */
+extern char *pdma_base;
+extern unsigned long pdma_areasize;
+
+/* Common routines to all controller types on the Sparc. */
+static inline void virtual_dma_init(void)
+{
+        /* nothing... */
+}
+
+static inline void sun_fd_disable_dma(void)
+{
+        doing_pdma = 0;
+        if (pdma_base) {
+                mmu_unlockarea(pdma_base, pdma_areasize);
+                pdma_base = NULL;
+        }
+}
+
+static inline void sun_fd_set_dma_mode(int mode)
+{
+        switch(mode) {
+        case DMA_MODE_READ:
+                doing_pdma = 1;
+                break;
+        case DMA_MODE_WRITE:
+                doing_pdma = 2;
+                break;
+        default:
+                printk("Unknown dma mode %d\n", mode);
+                panic("floppy: Giving up...");
+        }
+}
+
+static inline void sun_fd_set_dma_addr(char *buffer)
+{
+        pdma_vaddr = buffer;
+}
+
+static inline void sun_fd_set_dma_count(int length)
+{
+        pdma_size = length;
+}
+
+static inline void sun_fd_enable_dma(void)
+{
+        pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
+        pdma_base = pdma_vaddr;
+        pdma_areasize = pdma_size;
+}
+
+/* Our low-level entry point in arch/sparc/kernel/entry.S */
+extern int sparc_floppy_request_irq(int irq, unsigned long flags,
+                                    irq_handler_t irq_handler);
+
+static int sun_fd_request_irq(void)
+{
+        static int once = 0;
+        int error;
+
+        if(!once) {
+                once = 1;
+                error = sparc_floppy_request_irq(FLOPPY_IRQ,
+                                                 IRQF_DISABLED,
+                                                 floppy_interrupt);
+                return ((error == 0) ? 0 : -1);
+        } else return 0;
+}
+
+static struct linux_prom_registers fd_regs[2];
+
+static int sun_floppy_init(void)
+{
+        char state[128];
+        int tnode, fd_node, num_regs;
+        struct resource r;
+
+        use_virtual_dma = 1;
+
+        FLOPPY_IRQ = 11;
+        /* Forget it if we aren't on a machine that could possibly
+         * ever have a floppy drive.
+         */
+        if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) ||
+           ((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) ||
+            (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) {
+                /* We certainly don't have a floppy controller. */
+                goto no_sun_fdc;
+        }
+        /* Well, try to find one. */
+        tnode = prom_getchild(prom_root_node);
+        fd_node = prom_searchsiblings(tnode, "obio");
+        if(fd_node != 0) {
+                tnode = prom_getchild(fd_node);
+                fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo");
+        } else {
+                fd_node = prom_searchsiblings(tnode, "fd");
+        }
+        if(fd_node == 0) {
+                goto no_sun_fdc;
+        }
+
+        /* The sun4m lets us know if the controller is actually usable. */
+        if(sparc_cpu_model == sun4m &&
+           prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
+                if(!strcmp(state, "disabled")) {
+                        goto no_sun_fdc;
+                }
+        }
+        num_regs = prom_getproperty(fd_node, "reg", (char *) fd_regs, sizeof(fd_regs));
+        num_regs = (num_regs / sizeof(fd_regs[0]));
+        prom_apply_obio_ranges(fd_regs, num_regs);
+        memset(&r, 0, sizeof(r));
+        r.flags = fd_regs[0].which_io;
+        r.start = fd_regs[0].phys_addr;
+        sun_fdc = (struct sun_flpy_controller *)
+            sbus_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
+
+        /* Last minute sanity check... */
+        if(sun_fdc->status_82072 == 0xff) {
+                sun_fdc = NULL;
+                goto no_sun_fdc;
+        }
+
+        sun_fdops.fd_inb = sun_82077_fd_inb;
+        sun_fdops.fd_outb = sun_82077_fd_outb;
+        fdc_status = &sun_fdc->status_82077;
+
+        if (sun_fdc->dor_82077 == 0x80) {
+                sun_fdc->dor_82077 = 0x02;
+                if (sun_fdc->dor_82077 == 0x80) {
+                        sun_fdops.fd_inb = sun_82072_fd_inb;
+                        sun_fdops.fd_outb = sun_82072_fd_outb;
+                        fdc_status = &sun_fdc->status_82072;
+                }
+        }
+
+        /* Success... */
+        allowed_drive_mask = 0x01;
+        return (int) sun_fdc;
+
+no_sun_fdc:
+        return -1;
+}
+
+static int sparc_eject(void)
+{
+        set_dor(0x00, 0xff, 0x90);
+        udelay(500);
+        set_dor(0x00, 0x6f, 0x00);
+        udelay(500);
+        return 0;
+}
+
+#define fd_eject(drive) sparc_eject()
+
+#define EXTRA_FLOPPY_PARAMS
+
+#endif /* !(__ASM_SPARC_FLOPPY_H) */
diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h
new file mode 100644
index 000000000000..c39db1060bc7
--- /dev/null
+++ b/arch/sparc/include/asm/floppy_64.h
@@ -0,0 +1,782 @@
+/* floppy.h: Sparc specific parts of the Floppy driver.
+ *
+ * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * Ultra/PCI support added: Sep 1997  Eddie C. Dost  (ecd@skynet.be)
+ */
+
+#ifndef __ASM_SPARC64_FLOPPY_H
+#define __ASM_SPARC64_FLOPPY_H
+
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/idprom.h>
+#include <asm/oplib.h>
+#include <asm/auxio.h>
+#include <asm/sbus.h>
+#include <asm/irq.h>
+
+
+/*
+ * Define this to enable exchanging drive 0 and 1 if only drive 1 is
+ * probed on PCI machines.
+ */
+#undef PCI_FDC_SWAP_DRIVES
+
+
+/* References:
+ * 1) Netbsd Sun floppy driver.
+ * 2) NCR 82077 controller manual
+ * 3) Intel 82077 controller manual
+ */
+struct sun_flpy_controller {
+        volatile unsigned char status1_82077; /* Auxiliary Status reg. 1 */
+        volatile unsigned char status2_82077; /* Auxiliary Status reg. 2 */
+        volatile unsigned char dor_82077;     /* Digital Output reg. */
+        volatile unsigned char tapectl_82077; /* Tape Control reg */
+        volatile unsigned char status_82077;  /* Main Status Register. */
+#define drs_82077              status_82077   /* Digital Rate Select reg. */
+        volatile unsigned char data_82077;    /* Data fifo. */
+        volatile unsigned char ___unused;
+        volatile unsigned char dir_82077;     /* Digital Input reg. */
+#define dcr_82077              dir_82077      /* Config Control reg. */
+};
+
+/* You'll only ever find one controller on an Ultra anyways. */
+static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
+unsigned long fdc_status;
+static struct sbus_dev *floppy_sdev = NULL;
+
+struct sun_floppy_ops {
+        unsigned char   (*fd_inb) (unsigned long port);
+        void            (*fd_outb) (unsigned char value, unsigned long port);
+        void            (*fd_enable_dma) (void);
+        void            (*fd_disable_dma) (void);
+        void            (*fd_set_dma_mode) (int);
+        void            (*fd_set_dma_addr) (char *);
+        void            (*fd_set_dma_count) (int);
+        unsigned int    (*get_dma_residue) (void);
+        int             (*fd_request_irq) (void);
+        void            (*fd_free_irq) (void);
+        int             (*fd_eject) (int);
+};
+
+static struct sun_floppy_ops sun_fdops;
+
+#define fd_inb(port)              sun_fdops.fd_inb(port)
+#define fd_outb(value,port)       sun_fdops.fd_outb(value,port)
+#define fd_enable_dma()           sun_fdops.fd_enable_dma()
+#define fd_disable_dma()          sun_fdops.fd_disable_dma()
+#define fd_request_dma()          (0) /* nothing... */
+#define fd_free_dma()             /* nothing... */
+#define fd_clear_dma_ff()         /* nothing... */
+#define fd_set_dma_mode(mode)     sun_fdops.fd_set_dma_mode(mode)
+#define fd_set_dma_addr(addr)     sun_fdops.fd_set_dma_addr(addr)
+#define fd_set_dma_count(count)   sun_fdops.fd_set_dma_count(count)
+#define get_dma_residue(x)        sun_fdops.get_dma_residue()
+#define fd_cacheflush(addr, size) /* nothing... */
+#define fd_request_irq()          sun_fdops.fd_request_irq()
+#define fd_free_irq()             sun_fdops.fd_free_irq()
+#define fd_eject(drive)           sun_fdops.fd_eject(drive)
+
+/* Super paranoid... */
+#undef HAVE_DISABLE_HLT
+
+static int sun_floppy_types[2] = { 0, 0 };
+
+/* Here is where we catch the floppy driver trying to initialize,
+ * therefore this is where we call the PROM device tree probing
+ * routine etc. on the Sparc.
+ */
+#define FLOPPY0_TYPE            sun_floppy_init()
+#define FLOPPY1_TYPE            sun_floppy_types[1]
+
+#define FDC1                    ((unsigned long)sun_fdc)
+
+#define N_FDC    1
+#define N_DRIVE  8
+
+/* No 64k boundary crossing problems on the Sparc. */
+#define CROSS_64KB(a,s) (0)
+
+static unsigned char sun_82077_fd_inb(unsigned long port)
+{
+        udelay(5);
+        switch(port & 7) {
+        default:
+                printk("floppy: Asked to read unknown port %lx\n", port);
+                panic("floppy: Port bolixed.");
+        case 4: /* FD_STATUS */
+                return sbus_readb(&sun_fdc->status_82077) & ~STATUS_DMA;
+        case 5: /* FD_DATA */
+                return sbus_readb(&sun_fdc->data_82077);
+        case 7: /* FD_DIR */
+                /* XXX: Is DCL on 0x80 in sun4m? */
+                return sbus_readb(&sun_fdc->dir_82077);
+        };
+        panic("sun_82072_fd_inb: How did I get here?");
+}
+
+static void sun_82077_fd_outb(unsigned char value, unsigned long port)
+{
+        udelay(5);
+        switch(port & 7) {
+        default:
+                printk("floppy: Asked to write to unknown port %lx\n", port);
+                panic("floppy: Port bolixed.");
+        case 2: /* FD_DOR */
+                /* Happily, the 82077 has a real DOR register. */
+                sbus_writeb(value, &sun_fdc->dor_82077);
+                break;
+        case 5: /* FD_DATA */
+                sbus_writeb(value, &sun_fdc->data_82077);
+                break;
+        case 7: /* FD_DCR */
+                sbus_writeb(value, &sun_fdc->dcr_82077);
+                break;
+        case 4: /* FD_STATUS */
+                sbus_writeb(value, &sun_fdc->status_82077);
+                break;
+        };
+        return;
+}
+
+/* For pseudo-dma (Sun floppy drives have no real DMA available to
+ * them so we must eat the data fifo bytes directly ourselves) we have
+ * three state variables.  doing_pdma tells our inline low-level
+ * assembly floppy interrupt entry point whether it should sit and eat
+ * bytes from the fifo or just transfer control up to the higher level
+ * floppy interrupt c-code.  I tried very hard but I could not get the
+ * pseudo-dma to work in c-code without getting many overruns and
+ * underruns.  If non-zero, doing_pdma encodes the direction of
+ * the transfer for debugging.  1=read 2=write
+ */
+unsigned char *pdma_vaddr;
+unsigned long pdma_size;
+volatile int doing_pdma = 0;
+
+/* This is software state */
+char *pdma_base = NULL;
+unsigned long pdma_areasize;
+
+/* Common routines to all controller types on the Sparc. */
+static void sun_fd_disable_dma(void)
+{
+        doing_pdma = 0;
+        if (pdma_base) {
+                mmu_unlockarea(pdma_base, pdma_areasize);
+                pdma_base = NULL;
+        }
+}
+
+static void sun_fd_set_dma_mode(int mode)
+{
+        switch(mode) {
+        case DMA_MODE_READ:
+                doing_pdma = 1;
+                break;
+        case DMA_MODE_WRITE:
+                doing_pdma = 2;
+                break;
+        default:
+                printk("Unknown dma mode %d\n", mode);
+                panic("floppy: Giving up...");
+        }
+}
+
+static void sun_fd_set_dma_addr(char *buffer)
+{
+        pdma_vaddr = buffer;
+}
+
+static void sun_fd_set_dma_count(int length)
+{
+        pdma_size = length;
+}
+
+static void sun_fd_enable_dma(void)
+{
+        pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
+        pdma_base = pdma_vaddr;
+        pdma_areasize = pdma_size;
+}
+
+irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie)
+{
+        if (likely(doing_pdma)) {
+                void __iomem *stat = (void __iomem *) fdc_status;
+                unsigned char *vaddr = pdma_vaddr;
+                unsigned long size = pdma_size;
+                u8 val;
+
+                while (size) {
+                        val = readb(stat);
+                        if (unlikely(!(val & 0x80))) {
+                                pdma_vaddr = vaddr;
+                                pdma_size = size;
+                                return IRQ_HANDLED;
+                        }
+                        if (unlikely(!(val & 0x20))) {
+                                pdma_vaddr = vaddr;
+                                pdma_size = size;
+                                doing_pdma = 0;
+                                goto main_interrupt;
+                        }
+                        if (val & 0x40) {
+                                /* read */
+                                *vaddr++ = readb(stat + 1);
+                        } else {
+                                unsigned char data = *vaddr++;
+
+                                /* write */
+                                writeb(data, stat + 1);
+                        }
+                        size--;
+                }
+
+                pdma_vaddr = vaddr;
+                pdma_size = size;
+
+                /* Send Terminal Count pulse to floppy controller. */
+                val = readb(auxio_register);
+                val |= AUXIO_AUX1_FTCNT;
+                writeb(val, auxio_register);
+                val &= ~AUXIO_AUX1_FTCNT;
+                writeb(val, auxio_register);
+
+                doing_pdma = 0;
+        }
+
+main_interrupt:
+        return floppy_interrupt(irq, dev_cookie);
+}
+
+static int sun_fd_request_irq(void)
+{
+        static int once = 0;
+        int error;
+
+        if(!once) {
+                once = 1;
+
+                error = request_irq(FLOPPY_IRQ, sparc_floppy_irq,
+                                    IRQF_DISABLED, "floppy", NULL);
+
+                return ((error == 0) ? 0 : -1);
+        }
+        return 0;
+}
+
+static void sun_fd_free_irq(void)
+{
+}
+
+static unsigned int sun_get_dma_residue(void)
+{
+        /* XXX This isn't really correct. XXX */
+        return 0;
+}
+
+static int sun_fd_eject(int drive)
+{
+        set_dor(0x00, 0xff, 0x90);
+        udelay(500);
+        set_dor(0x00, 0x6f, 0x00);
+        udelay(500);
+        return 0;
+}
+
+#ifdef CONFIG_PCI
+#include <asm/ebus.h>
+#include <asm/ns87303.h>
+
+static struct ebus_dma_info sun_pci_fd_ebus_dma;
+static struct pci_dev *sun_pci_ebus_dev;
+static int sun_pci_broken_drive = -1;
+
+struct sun_pci_dma_op {
+        unsigned int    addr;
+        int             len;
+        int             direction;
+        char            *buf;
+};
+static struct sun_pci_dma_op sun_pci_dma_current = { -1U, 0, 0, NULL};
+static struct sun_pci_dma_op sun_pci_dma_pending = { -1U, 0, 0, NULL};
+
+extern irqreturn_t floppy_interrupt(int irq, void *dev_id);
+
+static unsigned char sun_pci_fd_inb(unsigned long port)
+{
+        udelay(5);
+        return inb(port);
+}
+
+static void sun_pci_fd_outb(unsigned char val, unsigned long port)
+{
+        udelay(5);
+        outb(val, port);
+}
+
+static void sun_pci_fd_broken_outb(unsigned char val, unsigned long port)
+{
+        udelay(5);
+        /*
+         * XXX: Due to SUN's broken floppy connector on AX and AXi
+         *      we need to turn on MOTOR_0 also, if the floppy is
+         *      jumpered to DS1 (like most PC floppies are). I hope
+         *      this does not hurt correct hardware like the AXmp.
+         *      (Eddie, Sep 12 1998).
+         */
+        if (port == ((unsigned long)sun_fdc) + 2) {
+                if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x20)) {
+                        val |= 0x10;
+                }
+        }
+        outb(val, port);
+}
+
+#ifdef PCI_FDC_SWAP_DRIVES
+static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port)
+{
+        udelay(5);
+        /*
+         * XXX: Due to SUN's broken floppy connector on AX and AXi
+         *      we need to turn on MOTOR_0 also, if the floppy is
+         *      jumpered to DS1 (like most PC floppies are). I hope
+         *      this does not hurt correct hardware like the AXmp.
+         *      (Eddie, Sep 12 1998).
+         */
+        if (port == ((unsigned long)sun_fdc) + 2) {
+                if (((val & 0x03) == sun_pci_broken_drive) && (val & 0x10)) {
+                        val &= ~(0x03);
+                        val |= 0x21;
+                }
+        }
+        outb(val, port);
+}
+#endif /* PCI_FDC_SWAP_DRIVES */
+
+static void sun_pci_fd_enable_dma(void)
+{
+        BUG_ON((NULL == sun_pci_dma_pending.buf)        ||
+            (0    == sun_pci_dma_pending.len)   ||
+            (0    == sun_pci_dma_pending.direction));
+
+        sun_pci_dma_current.buf = sun_pci_dma_pending.buf;
+        sun_pci_dma_current.len = sun_pci_dma_pending.len;
+        sun_pci_dma_current.direction = sun_pci_dma_pending.direction;
+
+        sun_pci_dma_pending.buf  = NULL;
+        sun_pci_dma_pending.len  = 0;
+        sun_pci_dma_pending.direction = 0;
+        sun_pci_dma_pending.addr = -1U;
+
+        sun_pci_dma_current.addr =
+                pci_map_single(sun_pci_ebus_dev,
+                               sun_pci_dma_current.buf,
+                               sun_pci_dma_current.len,
+                               sun_pci_dma_current.direction);
+
+        ebus_dma_enable(&sun_pci_fd_ebus_dma, 1);
+
+        if (ebus_dma_request(&sun_pci_fd_ebus_dma,
+                             sun_pci_dma_current.addr,
+                             sun_pci_dma_current.len))
+                BUG();
+}
+
+static void sun_pci_fd_disable_dma(void)
+{
+        ebus_dma_enable(&sun_pci_fd_ebus_dma, 0);
+        if (sun_pci_dma_current.addr != -1U)
+                pci_unmap_single(sun_pci_ebus_dev,
+                                 sun_pci_dma_current.addr,
+                                 sun_pci_dma_current.len,
+                                 sun_pci_dma_current.direction);
+        sun_pci_dma_current.addr = -1U;
+}
+
+static void sun_pci_fd_set_dma_mode(int mode)
+{
+        if (mode == DMA_MODE_WRITE)
+                sun_pci_dma_pending.direction = PCI_DMA_TODEVICE;
+        else
+                sun_pci_dma_pending.direction = PCI_DMA_FROMDEVICE;
+
+        ebus_dma_prepare(&sun_pci_fd_ebus_dma, mode != DMA_MODE_WRITE);
+}
+
+static void sun_pci_fd_set_dma_count(int length)
+{
+        sun_pci_dma_pending.len = length;
+}
+
+static void sun_pci_fd_set_dma_addr(char *buffer)
+{
+        sun_pci_dma_pending.buf = buffer;
+}
+
+static unsigned int sun_pci_get_dma_residue(void)
+{
+        return ebus_dma_residue(&sun_pci_fd_ebus_dma);
+}
+
+static int sun_pci_fd_request_irq(void)
+{
+        return ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 1);
+}
+
+static void sun_pci_fd_free_irq(void)
+{
+        ebus_dma_irq_enable(&sun_pci_fd_ebus_dma, 0);
+}
+
+static int sun_pci_fd_eject(int drive)
+{
+        return -EINVAL;
+}
+
+void sun_pci_fd_dma_callback(struct ebus_dma_info *p, int event, void *cookie)
+{
+        floppy_interrupt(0, NULL);
+}
+
+/*
+ * Floppy probing, we'd like to use /dev/fd0 for a single Floppy on PCI,
+ * even if this is configured using DS1, thus looks like /dev/fd1 with
+ * the cabling used in Ultras.
+ */
+#define DOR     (port + 2)
+#define MSR     (port + 4)
+#define FIFO    (port + 5)
+
+static void sun_pci_fd_out_byte(unsigned long port, unsigned char val,
+                                unsigned long reg)
+{
+        unsigned char status;
+        int timeout = 1000;
+
+        while (!((status = inb(MSR)) & 0x80) && --timeout)
+                udelay(100);
+        outb(val, reg);
+}
+
+static unsigned char sun_pci_fd_sensei(unsigned long port)
+{
+        unsigned char result[2] = { 0x70, 0x00 };
+        unsigned char status;
+        int i = 0;
+
+        sun_pci_fd_out_byte(port, 0x08, FIFO);
+        do {
+                int timeout = 1000;
+
+                while (!((status = inb(MSR)) & 0x80) && --timeout)
+                        udelay(100);
+
+                if (!timeout)
+                        break;
+
+                if ((status & 0xf0) == 0xd0)
+                        result[i++] = inb(FIFO);
+                else
+                        break;
+        } while (i < 2);
+
+        return result[0];
+}
+
+static void sun_pci_fd_reset(unsigned long port)
+{
+        unsigned char mask = 0x00;
+        unsigned char status;
+        int timeout = 10000;
+
+        outb(0x80, MSR);
+        do {
+                status = sun_pci_fd_sensei(port);
+                if ((status & 0xc0) == 0xc0)
+                        mask |= 1 << (status & 0x03);
+                else
+                        udelay(100);
+        } while ((mask != 0x0f) && --timeout);
+}
+
+static int sun_pci_fd_test_drive(unsigned long port, int drive)
+{
+        unsigned char status, data;
+        int timeout = 1000;
+        int ready;
+
+        sun_pci_fd_reset(port);
+
+        data = (0x10 << drive) | 0x0c | drive;
+        sun_pci_fd_out_byte(port, data, DOR);
+
+        sun_pci_fd_out_byte(port, 0x07, FIFO);
+        sun_pci_fd_out_byte(port, drive & 0x03, FIFO);
+
+        do {
+                udelay(100);
+                status = sun_pci_fd_sensei(port);
+        } while (((status & 0xc0) == 0x80) && --timeout);
+
+        if (!timeout)
+                ready = 0;
+        else
+                ready = (status & 0x10) ? 0 : 1;
+
+        sun_pci_fd_reset(port);
+        return ready;
+}
+#undef FIFO
+#undef MSR
+#undef DOR
+
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCI
+static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
+{
+        if (!strcmp(edev->prom_node->name, "fdthree"))
+                return 1;
+        if (!strcmp(edev->prom_node->name, "floppy")) {
+                const char *compat;
+
+                compat = of_get_property(edev->prom_node,
+                                         "compatible", NULL);
+                if (compat && !strcmp(compat, "fdthree"))
+                        return 1;
+        }
+        return 0;
+}
+#endif
+
+static unsigned long __init sun_floppy_init(void)
+{
+        char state[128];
+        struct sbus_bus *bus;
+        struct sbus_dev *sdev = NULL;
+        static int initialized = 0;
+
+        if (initialized)
+                return sun_floppy_types[0];
+        initialized = 1;
+
+        for_all_sbusdev (sdev, bus) {
+                if (!strcmp(sdev->prom_name, "SUNW,fdtwo"))
+                        break;
+        }
+        if(sdev) {
+                floppy_sdev = sdev;
+                FLOPPY_IRQ = sdev->irqs[0];
+        } else {
+#ifdef CONFIG_PCI
+                struct linux_ebus *ebus;
+                struct linux_ebus_device *edev = NULL;
+                unsigned long config = 0;
+                void __iomem *auxio_reg;
+                const char *state_prop;
+
+                for_each_ebus(ebus) {
+                        for_each_ebusdev(edev, ebus) {
+                                if (ebus_fdthree_p(edev))
+                                        goto ebus_done;
+                        }
+                }
+        ebus_done:
+                if (!edev)
+                        return 0;
+
+                state_prop = of_get_property(edev->prom_node, "status", NULL);
+                if (state_prop && !strncmp(state_prop, "disabled", 8))
+                        return 0;
+
+                FLOPPY_IRQ = edev->irqs[0];
+
+                /* Make sure the high density bit is set, some systems
+                 * (most notably Ultra5/Ultra10) come up with it clear.
+                 */
+                auxio_reg = (void __iomem *) edev->resource[2].start;
+                writel(readl(auxio_reg)|0x2, auxio_reg);
+
+                sun_pci_ebus_dev = ebus->self;
+
+                spin_lock_init(&sun_pci_fd_ebus_dma.lock);
+
+                /* XXX ioremap */
+                sun_pci_fd_ebus_dma.regs = (void __iomem *)
+                        edev->resource[1].start;
+                if (!sun_pci_fd_ebus_dma.regs)
+                        return 0;
+
+                sun_pci_fd_ebus_dma.flags = (EBUS_DMA_FLAG_USE_EBDMA_HANDLER |
+                                             EBUS_DMA_FLAG_TCI_DISABLE);
+                sun_pci_fd_ebus_dma.callback = sun_pci_fd_dma_callback;
+                sun_pci_fd_ebus_dma.client_cookie = NULL;
+                sun_pci_fd_ebus_dma.irq = FLOPPY_IRQ;
+                strcpy(sun_pci_fd_ebus_dma.name, "floppy");
+                if (ebus_dma_register(&sun_pci_fd_ebus_dma))
+                        return 0;
+
+                /* XXX ioremap */
+                sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start;
+
+                sun_fdops.fd_inb = sun_pci_fd_inb;
+                sun_fdops.fd_outb = sun_pci_fd_outb;
+
+                can_use_virtual_dma = use_virtual_dma = 0;
+                sun_fdops.fd_enable_dma = sun_pci_fd_enable_dma;
+                sun_fdops.fd_disable_dma = sun_pci_fd_disable_dma;
+                sun_fdops.fd_set_dma_mode = sun_pci_fd_set_dma_mode;
+                sun_fdops.fd_set_dma_addr = sun_pci_fd_set_dma_addr;
+                sun_fdops.fd_set_dma_count = sun_pci_fd_set_dma_count;
+                sun_fdops.get_dma_residue = sun_pci_get_dma_residue;
+
+                sun_fdops.fd_request_irq = sun_pci_fd_request_irq;
+                sun_fdops.fd_free_irq = sun_pci_fd_free_irq;
+
+                sun_fdops.fd_eject = sun_pci_fd_eject;
+
+                fdc_status = (unsigned long) &sun_fdc->status_82077;
+
+                /*
+                 * XXX: Find out on which machines this is really needed.
+                 */
+                if (1) {
+                        sun_pci_broken_drive = 1;
+                        sun_fdops.fd_outb = sun_pci_fd_broken_outb;
+                }
+
+                allowed_drive_mask = 0;
+                if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 0))
+                        sun_floppy_types[0] = 4;
+                if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 1))
+                        sun_floppy_types[1] = 4;
+
+                /*
+                 * Find NS87303 SuperIO config registers (through ecpp).
+                 */
+                for_each_ebus(ebus) {
+                        for_each_ebusdev(edev, ebus) {
+                                if (!strcmp(edev->prom_node->name, "ecpp")) {
+                                        config = edev->resource[1].start;
+                                        goto config_done;
+                                }
+                        }
+                }
+        config_done:
+
+                /*
+                 * Sanity check, is this really the NS87303?
+                 */
+                switch (config & 0x3ff) {
+                case 0x02e:
+                case 0x15c:
+                case 0x26e:
+                case 0x398:
+                        break;
+                default:
+                        config = 0;
+                }
+
+                if (!config)
+                        return sun_floppy_types[0];
+
+                /* Enable PC-AT mode. */
+                ns87303_modify(config, ASC, 0, 0xc0);
+
+#ifdef PCI_FDC_SWAP_DRIVES
+                /*
+                 * If only Floppy 1 is present, swap drives.
+                 */
+                if (!sun_floppy_types[0] && sun_floppy_types[1]) {
+                        /*
+                         * Set the drive exchange bit in FCR on NS87303,
+                         * make sure other bits are sane before doing so.
+                         */
+                        ns87303_modify(config, FER, FER_EDM, 0);
+                        ns87303_modify(config, ASC, ASC_DRV2_SEL, 0);
+                        ns87303_modify(config, FCR, 0, FCR_LDE);
+
+                        config = sun_floppy_types[0];
+                        sun_floppy_types[0] = sun_floppy_types[1];
+                        sun_floppy_types[1] = config;
+
+                        if (sun_pci_broken_drive != -1) {
+                                sun_pci_broken_drive = 1 - sun_pci_broken_drive;
+                                sun_fdops.fd_outb = sun_pci_fd_lde_broken_outb;
+                        }
+                }
+#endif /* PCI_FDC_SWAP_DRIVES */
+
+                return sun_floppy_types[0];
+#else
+                return 0;
+#endif
+        }
+        prom_getproperty(sdev->prom_node, "status", state, sizeof(state));
+        if(!strncmp(state, "disabled", 8))
+                return 0;
+
+        /*
+         * We cannot do sbus_ioremap here: it does request_region,
+         * which the generic floppy driver tries to do once again.
+         * But we must use the sdev resource values as they have
+         * had parent ranges applied.
+         */
+        sun_fdc = (struct sun_flpy_controller *)
+                (sdev->resource[0].start +
+                 ((sdev->resource[0].flags & 0x1ffUL) << 32UL));
+
+        /* Last minute sanity check... */
+        if(sbus_readb(&sun_fdc->status1_82077) == 0xff) {
+                sun_fdc = (struct sun_flpy_controller *)-1;
+                return 0;
+        }
+
+        sun_fdops.fd_inb = sun_82077_fd_inb;
+        sun_fdops.fd_outb = sun_82077_fd_outb;
+
+        can_use_virtual_dma = use_virtual_dma = 1;
+        sun_fdops.fd_enable_dma = sun_fd_enable_dma;
+        sun_fdops.fd_disable_dma = sun_fd_disable_dma;
+        sun_fdops.fd_set_dma_mode = sun_fd_set_dma_mode;
+        sun_fdops.fd_set_dma_addr = sun_fd_set_dma_addr;
+        sun_fdops.fd_set_dma_count = sun_fd_set_dma_count;
+        sun_fdops.get_dma_residue = sun_get_dma_residue;
+
+        sun_fdops.fd_request_irq = sun_fd_request_irq;
+        sun_fdops.fd_free_irq = sun_fd_free_irq;
+
+        sun_fdops.fd_eject = sun_fd_eject;
+
+        fdc_status = (unsigned long) &sun_fdc->status_82077;
+
+        /* Success... */
+        allowed_drive_mask = 0x01;
+        sun_floppy_types[0] = 4;
+        sun_floppy_types[1] = 0;
+
+        return sun_floppy_types[0];
+}
+
+#define EXTRA_FLOPPY_PARAMS
+
+static DEFINE_SPINLOCK(dma_spin_lock);
+
+#define claim_dma_lock() \
+({      unsigned long flags; \
+        spin_lock_irqsave(&dma_spin_lock, flags); \
+        flags; \
+})
+
+#define release_dma_lock(__flags) \
+        spin_unlock_irqrestore(&dma_spin_lock, __flags);
+
+#endif /* !(__ASM_SPARC64_FLOPPY_H) */
diff --git a/arch/sparc/include/asm/fpumacro.h b/arch/sparc/include/asm/fpumacro.h
new file mode 100644
index 000000000000..cc463fec806f
--- /dev/null
+++ b/arch/sparc/include/asm/fpumacro.h
@@ -0,0 +1,33 @@
+/* fpumacro.h: FPU related macros.
+ *
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC64_FPUMACRO_H
+#define _SPARC64_FPUMACRO_H
+
+#include <asm/asi.h>
+#include <asm/visasm.h>
+
+struct fpustate {
+        u32     regs[64];
+};
+
+#define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs)
+
+static inline unsigned long fprs_read(void)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__("rd %%fprs, %0" : "=r" (retval));
+
+        return retval;
+}
+
+static inline void fprs_write(unsigned long val)
+{
+        __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val));
+}
+
+#endif /* !(_SPARC64_FPUMACRO_H) */
diff --git a/arch/sparc/include/asm/ftrace.h b/arch/sparc/include/asm/ftrace.h
new file mode 100644
index 000000000000..d27716cd38c1
--- /dev/null
+++ b/arch/sparc/include/asm/ftrace.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_SPARC64_FTRACE
+#define _ASM_SPARC64_FTRACE
+
+#ifdef CONFIG_MCOUNT
+#define MCOUNT_ADDR             ((long)(_mcount))
+#define MCOUNT_INSN_SIZE        4 /* sizeof mcount call */
+
+#ifndef __ASSEMBLY__
+extern void _mcount(void);
+#endif
+
+#endif
+
+#endif /* _ASM_SPARC64_FTRACE */
diff --git a/arch/sparc/include/asm/futex.h b/arch/sparc/include/asm/futex.h
new file mode 100644
index 000000000000..736335f36713
--- /dev/null
+++ b/arch/sparc/include/asm/futex.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_FUTEX_H
+#define ___ASM_SPARC_FUTEX_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/futex_64.h>
+#else
+#include <asm/futex_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/futex_32.h b/arch/sparc/include/asm/futex_32.h
new file mode 100644
index 000000000000..6a332a9f099c
--- /dev/null
+++ b/arch/sparc/include/asm/futex_32.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#include <asm-generic/futex.h>
+
+#endif
diff --git a/arch/sparc/include/asm/futex_64.h b/arch/sparc/include/asm/futex_64.h
new file mode 100644
index 000000000000..47f95839dc69
--- /dev/null
+++ b/arch/sparc/include/asm/futex_64.h
@@ -0,0 +1,110 @@
+#ifndef _SPARC64_FUTEX_H
+#define _SPARC64_FUTEX_H
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+#include <asm/system.h>
+
+#define __futex_cas_op(insn, ret, oldval, uaddr, oparg) \
+        __asm__ __volatile__(                           \
+        "\n1:   lduwa   [%3] %%asi, %2\n"               \
+        "       " insn "\n"                             \
+        "2:     casa    [%3] %%asi, %2, %1\n"           \
+        "       cmp     %2, %1\n"                       \
+        "       bne,pn  %%icc, 1b\n"                    \
+        "        mov    0, %0\n"                        \
+        "3:\n"                                          \
+        "       .section .fixup,#alloc,#execinstr\n"    \
+        "       .align  4\n"                            \
+        "4:     sethi   %%hi(3b), %0\n"                 \
+        "       jmpl    %0 + %%lo(3b), %%g0\n"          \
+        "        mov    %5, %0\n"                       \
+        "       .previous\n"                            \
+        "       .section __ex_table,\"a\"\n"            \
+        "       .align  4\n"                            \
+        "       .word   1b, 4b\n"                       \
+        "       .word   2b, 4b\n"                       \
+        "       .previous\n"                            \
+        : "=&r" (ret), "=&r" (oldval), "=&r" (tem)      \
+        : "r" (uaddr), "r" (oparg), "i" (-EFAULT)       \
+        : "memory")
+
+static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret, tem;
+
+        if (unlikely(!access_ok(VERIFY_WRITE, uaddr, sizeof(int))))
+                return -EFAULT;
+        if (unlikely((((unsigned long) uaddr) & 0x3UL)))
+                return -EINVAL;
+
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_cas_op("mov\t%4, %1", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_cas_op("add\t%2, %4, %1", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_cas_op("or\t%2, %4, %1", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_cas_op("andn\t%2, %4, %1", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_cas_op("xor\t%2, %4, %1", ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        __asm__ __volatile__(
+        "\n1:   casa    [%3] %%asi, %2, %0\n"
+        "2:\n"
+        "       .section .fixup,#alloc,#execinstr\n"
+        "       .align  4\n"
+        "3:     sethi   %%hi(2b), %0\n"
+        "       jmpl    %0 + %%lo(2b), %%g0\n"
+        "        mov    %4, %0\n"
+        "       .previous\n"
+        "       .section __ex_table,\"a\"\n"
+        "       .align  4\n"
+        "       .word   1b, 3b\n"
+        "       .previous\n"
+        : "=r" (newval)
+        : "0" (newval), "r" (oldval), "r" (uaddr), "i" (-EFAULT)
+        : "memory");
+
+        return newval;
+}
+
+#endif /* !(_SPARC64_FUTEX_H) */
diff --git a/arch/sparc/include/asm/hardirq.h b/arch/sparc/include/asm/hardirq.h
new file mode 100644
index 000000000000..44d4e2345148
--- /dev/null
+++ b/arch/sparc/include/asm/hardirq.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_HARDIRQ_H
+#define ___ASM_SPARC_HARDIRQ_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/hardirq_64.h>
+#else
+#include <asm/hardirq_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/hardirq_32.h b/arch/sparc/include/asm/hardirq_32.h
new file mode 100644
index 000000000000..4f63ed8df551
--- /dev/null
+++ b/arch/sparc/include/asm/hardirq_32.h
@@ -0,0 +1,23 @@
+/* hardirq.h: 32-bit Sparc hard IRQ support.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
+ */
+
+#ifndef __SPARC_HARDIRQ_H
+#define __SPARC_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/spinlock.h>
+#include <linux/cache.h>
+
+/* entry.S is sensitive to the offsets of these fields */ /* XXX P3 Is it? */
+typedef struct {
+        unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+#define HARDIRQ_BITS    8
+
+#endif /* __SPARC_HARDIRQ_H */
diff --git a/arch/sparc/include/asm/hardirq_64.h b/arch/sparc/include/asm/hardirq_64.h
new file mode 100644
index 000000000000..7c29fd1a87aa
--- /dev/null
+++ b/arch/sparc/include/asm/hardirq_64.h
@@ -0,0 +1,19 @@
+/* hardirq.h: 64-bit Sparc hard IRQ support.
+ *
+ * Copyright (C) 1997, 1998, 2005 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef __SPARC64_HARDIRQ_H
+#define __SPARC64_HARDIRQ_H
+
+#include <asm/cpudata.h>
+
+#define __ARCH_IRQ_STAT
+#define local_softirq_pending() \
+        (local_cpu_data().__softirq_pending)
+
+void ack_bad_irq(unsigned int irq);
+
+#define HARDIRQ_BITS    8
+
+#endif /* !(__SPARC64_HARDIRQ_H) */
diff --git a/arch/sparc/include/asm/head.h b/arch/sparc/include/asm/head.h
new file mode 100644
index 000000000000..be8f03f3e731
--- /dev/null
+++ b/arch/sparc/include/asm/head.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_HEAD_H
+#define ___ASM_SPARC_HEAD_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/head_64.h>
+#else
+#include <asm/head_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/head_32.h b/arch/sparc/include/asm/head_32.h
new file mode 100644
index 000000000000..7c35491a8b53
--- /dev/null
+++ b/arch/sparc/include/asm/head_32.h
@@ -0,0 +1,102 @@
+#ifndef __SPARC_HEAD_H
+#define __SPARC_HEAD_H
+
+#define KERNBASE        0xf0000000  /* First address the kernel will eventually be */
+#define LOAD_ADDR       0x4000      /* prom jumps to us here unless this is elf /boot */
+#define SUN4C_SEGSZ     (1 << 18)
+#define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2)  /* Used in boot remapping. */
+#define INTS_ENAB        0x01           /* entry.S uses this. */
+
+#define SUN4_PROM_VECTOR 0xFFE81000     /* SUN4 PROM needs to be hardwired */
+
+#define WRITE_PAUSE      nop; nop; nop; /* Have to do this after %wim/%psr chg */
+#define NOP_INSN         0x01000000     /* Used to patch sparc_save_state */
+
+/* Here are some trap goodies */
+
+/* Generic trap entry. */
+#define TRAP_ENTRY(type, label) \
+        rd %psr, %l0; b label; rd %wim, %l3; nop;
+
+/* Data/text faults. Defaults to sun4c version at boot time. */
+#define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7;
+#define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7;
+#define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
+#define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
+
+/* This is for traps we should NEVER get. */
+#define BAD_TRAP(num) \
+        rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
+
+/* This is for traps when we want just skip the instruction which caused it */
+#define SKIP_TRAP(type, name) \
+        jmpl %l2, %g0; rett %l2 + 4; nop; nop;
+
+/* Notice that for the system calls we pull a trick.  We load up a
+ * different pointer to the system call vector table in %l7, but call
+ * the same generic system call low-level entry point.  The trap table
+ * entry sequences are also HyperSparc pipeline friendly ;-)
+ */
+
+/* Software trap for Linux system calls. */
+#define LINUX_SYSCALL_TRAP \
+        sethi %hi(sys_call_table), %l7; \
+        or %l7, %lo(sys_call_table), %l7; \
+        b linux_sparc_syscall; \
+        rd %psr, %l0;
+
+#define BREAKPOINT_TRAP \
+        b breakpoint_trap; \
+        rd %psr,%l0; \
+        nop; \
+        nop;
+
+#ifdef CONFIG_KGDB
+#define KGDB_TRAP(num) \
+        b kgdb_trap_low; \
+        rd %psr,%l0; \
+        nop; \
+        nop;
+#else
+#define KGDB_TRAP(num) \
+        BAD_TRAP(num)
+#endif
+
+/* The Get Condition Codes software trap for userland. */
+#define GETCC_TRAP \
+        b getcc_trap_handler; mov %psr, %l0; nop; nop;
+
+/* The Set Condition Codes software trap for userland. */
+#define SETCC_TRAP \
+        b setcc_trap_handler; mov %psr, %l0; nop; nop;
+
+/* The Get PSR software trap for userland. */
+#define GETPSR_TRAP \
+        mov %psr, %i0; jmp %l2; rett %l2 + 4; nop;
+
+/* This is for hard interrupts from level 1-14, 15 is non-maskable (nmi) and
+ * gets handled with another macro.
+ */
+#define TRAP_ENTRY_INTERRUPT(int_level) \
+        mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
+
+/* NMI's (Non Maskable Interrupts) are special, you can't keep them
+ * from coming in, and basically if you get one, the shows over. ;(
+ * On the sun4c they are usually asynchronous memory errors, on the
+ * the sun4m they could be either due to mem errors or a software
+ * initiated interrupt from the prom/kern on an SMP box saying "I
+ * command you to do CPU tricks, read your mailbox for more info."
+ */
+#define NMI_TRAP \
+        rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop;
+
+/* Window overflows/underflows are special and we need to try to be as
+ * efficient as possible here....
+ */
+#define WINDOW_SPILL \
+        rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
+
+#define WINDOW_FILL \
+        rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
+
+#endif /* __SPARC_HEAD_H */
diff --git a/arch/sparc/include/asm/head_64.h b/arch/sparc/include/asm/head_64.h
new file mode 100644
index 000000000000..10e9dabc4c41
--- /dev/null
+++ b/arch/sparc/include/asm/head_64.h
@@ -0,0 +1,76 @@
+#ifndef _SPARC64_HEAD_H
+#define _SPARC64_HEAD_H
+
+#include <asm/pstate.h>
+
+        /* wrpr %g0, val, %gl */
+#define SET_GL(val)     \
+        .word   0xa1902000 | val
+
+        /* rdpr %gl, %gN */
+#define GET_GL_GLOBAL(N)        \
+        .word   0x81540000 | (N << 25)
+
+#define KERNBASE        0x400000
+
+#define PTREGS_OFF      (STACK_BIAS + STACKFRAME_SZ)
+
+#define __CHEETAH_ID    0x003e0014
+#define __JALAPENO_ID   0x003e0016
+#define __SERRANO_ID    0x003e0022
+
+#define CHEETAH_MANUF           0x003e
+#define CHEETAH_IMPL            0x0014 /* Ultra-III   */
+#define CHEETAH_PLUS_IMPL       0x0015 /* Ultra-III+  */
+#define JALAPENO_IMPL           0x0016 /* Ultra-IIIi  */
+#define JAGUAR_IMPL             0x0018 /* Ultra-IV    */
+#define PANTHER_IMPL            0x0019 /* Ultra-IV+   */
+#define SERRANO_IMPL            0x0022 /* Ultra-IIIi+ */
+
+#define BRANCH_IF_SUN4V(tmp1,label)             \
+        sethi   %hi(is_sun4v), %tmp1;           \
+        lduw    [%tmp1 + %lo(is_sun4v)], %tmp1; \
+        brnz,pn %tmp1, label;                   \
+         nop
+
+#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
+        rdpr    %ver, %tmp1;                    \
+        sethi   %hi(__CHEETAH_ID), %tmp2;       \
+        srlx    %tmp1, 32, %tmp1;               \
+        or      %tmp2, %lo(__CHEETAH_ID), %tmp2;\
+        cmp     %tmp1, %tmp2;                   \
+        be,pn   %icc, label;                    \
+         nop;
+
+#define BRANCH_IF_JALAPENO(tmp1,tmp2,label)     \
+        rdpr    %ver, %tmp1;                    \
+        sethi   %hi(__JALAPENO_ID), %tmp2;      \
+        srlx    %tmp1, 32, %tmp1;               \
+        or      %tmp2, %lo(__JALAPENO_ID), %tmp2;\
+        cmp     %tmp1, %tmp2;                   \
+        be,pn   %icc, label;                    \
+         nop;
+
+#define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label)     \
+        rdpr    %ver, %tmp1;                    \
+        srlx    %tmp1, (32 + 16), %tmp2;        \
+        cmp     %tmp2, CHEETAH_MANUF;           \
+        bne,pt  %xcc, 99f;                      \
+         sllx   %tmp1, 16, %tmp1;               \
+        srlx    %tmp1, (32 + 16), %tmp2;        \
+        cmp     %tmp2, CHEETAH_PLUS_IMPL;       \
+        bgeu,pt %xcc, label;                    \
+99:      nop;
+
+#define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label)  \
+        rdpr    %ver, %tmp1;                    \
+        srlx    %tmp1, (32 + 16), %tmp2;        \
+        cmp     %tmp2, CHEETAH_MANUF;           \
+        bne,pt  %xcc, 99f;                      \
+         sllx   %tmp1, 16, %tmp1;               \
+        srlx    %tmp1, (32 + 16), %tmp2;        \
+        cmp     %tmp2, CHEETAH_IMPL;            \
+        bgeu,pt %xcc, label;                    \
+99:      nop;
+
+#endif /* !(_SPARC64_HEAD_H) */
diff --git a/arch/sparc/include/asm/highmem.h b/arch/sparc/include/asm/highmem.h
new file mode 100644
index 000000000000..3de42e776274
--- /dev/null
+++ b/arch/sparc/include/asm/highmem.h
@@ -0,0 +1,81 @@
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with 
+ * up to 16 Terrabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/interrupt.h>
+#include <asm/fixmap.h>
+#include <asm/vaddrs.h>
+#include <asm/kmap_types.h>
+#include <asm/pgtable.h>
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+extern void kmap_init(void) __init;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.  Currently the simplest way to do this is to align the
+ * pkmap region on a pagetable boundary (4MB).
+ */
+#define LAST_PKMAP 1024
+#define PKMAP_SIZE (LAST_PKMAP << PAGE_SHIFT)
+#define PKMAP_BASE PMD_ALIGN(SRMMU_NOCACHE_VADDR + (SRMMU_MAX_NOCACHE_PAGES << PAGE_SHIFT))
+
+#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
+#define PKMAP_NR(virt)  ((virt - PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+#define PKMAP_END (PKMAP_ADDR(LAST_PKMAP))
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+static inline void *kmap(struct page *page)
+{
+        BUG_ON(in_interrupt());
+        if (!PageHighMem(page))
+                return page_address(page);
+        return kmap_high(page);
+}
+
+static inline void kunmap(struct page *page)
+{
+        BUG_ON(in_interrupt());
+        if (!PageHighMem(page))
+                return;
+        kunmap_high(page);
+}
+
+extern void *kmap_atomic(struct page *page, enum km_type type);
+extern void kunmap_atomic(void *kvaddr, enum km_type type);
+extern struct page *kmap_atomic_to_page(void *vaddr);
+
+#define flush_cache_kmaps()     flush_cache_all()
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/sparc/include/asm/hugetlb.h b/arch/sparc/include/asm/hugetlb.h
new file mode 100644
index 000000000000..177061064ee6
--- /dev/null
+++ b/arch/sparc/include/asm/hugetlb.h
@@ -0,0 +1,85 @@
+#ifndef _ASM_SPARC64_HUGETLB_H
+#define _ASM_SPARC64_HUGETLB_H
+
+#include <asm/page.h>
+
+
+void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                     pte_t *ptep, pte_t pte);
+
+pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep);
+
+void hugetlb_prefault_arch_hook(struct mm_struct *mm);
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr,
+                                         unsigned long len) {
+        return 0;
+}
+
+/*
+ * If the arch doesn't supply something else, assume that hugepage
+ * size aligned regions are ok without further preparation.
+ */
+static inline int prepare_hugepage_range(struct file *file,
+                        unsigned long addr, unsigned long len)
+{
+        if (len & ~HPAGE_MASK)
+                return -EINVAL;
+        if (addr & ~HPAGE_MASK)
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr, unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        return *ptep;
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+#endif /* _ASM_SPARC64_HUGETLB_H */
diff --git a/arch/sparc/include/asm/hvtramp.h b/arch/sparc/include/asm/hvtramp.h
new file mode 100644
index 000000000000..b2b9b947b3a4
--- /dev/null
+++ b/arch/sparc/include/asm/hvtramp.h
@@ -0,0 +1,37 @@
+#ifndef _SPARC64_HVTRAP_H
+#define _SPARC64_HVTRAP_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+struct hvtramp_mapping {
+        __u64           vaddr;
+        __u64           tte;
+};
+
+struct hvtramp_descr {
+        __u32                   cpu;
+        __u32                   num_mappings;
+        __u64                   fault_info_va;
+        __u64                   fault_info_pa;
+        __u64                   thread_reg;
+        struct hvtramp_mapping  maps[1];
+};
+
+extern void hv_cpu_startup(unsigned long hvdescr_pa);
+
+#endif
+
+#define HVTRAMP_DESCR_CPU               0x00
+#define HVTRAMP_DESCR_NUM_MAPPINGS      0x04
+#define HVTRAMP_DESCR_FAULT_INFO_VA     0x08
+#define HVTRAMP_DESCR_FAULT_INFO_PA     0x10
+#define HVTRAMP_DESCR_THREAD_REG        0x18
+#define HVTRAMP_DESCR_MAPS              0x20
+
+#define HVTRAMP_MAPPING_VADDR           0x00
+#define HVTRAMP_MAPPING_TTE             0x08
+#define HVTRAMP_MAPPING_SIZE            0x10
+
+#endif /* _SPARC64_HVTRAP_H */
diff --git a/arch/sparc/include/asm/hw_irq.h b/arch/sparc/include/asm/hw_irq.h
new file mode 100644
index 000000000000..8d30a7694be2
--- /dev/null
+++ b/arch/sparc/include/asm/hw_irq.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SPARC_HW_IRQ_H
+#define __ASM_SPARC_HW_IRQ_H
+
+/* Dummy include. */
+
+#endif
diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h
new file mode 100644
index 000000000000..109ae24ba242
--- /dev/null
+++ b/arch/sparc/include/asm/hypervisor.h
@@ -0,0 +1,2949 @@
+#ifndef _SPARC64_HYPERVISOR_H
+#define _SPARC64_HYPERVISOR_H
+
+/* Sun4v hypervisor interfaces and defines.
+ *
+ * Hypervisor calls are made via traps to software traps number 0x80
+ * and above.  Registers %o0 to %o5 serve as argument, status, and
+ * return value registers.
+ *
+ * There are two kinds of these traps.  First there are the normal
+ * "fast traps" which use software trap 0x80 and encode the function
+ * to invoke by number in register %o5.  Argument and return value
+ * handling is as follows:
+ *
+ * -----------------------------------------------
+ * |  %o5  | function number |     undefined     |
+ * |  %o0  |   argument 0    |   return status   |
+ * |  %o1  |   argument 1    |   return value 1  |
+ * |  %o2  |   argument 2    |   return value 2  |
+ * |  %o3  |   argument 3    |   return value 3  |
+ * |  %o4  |   argument 4    |   return value 4  |
+ * -----------------------------------------------
+ *
+ * The second type are "hyper-fast traps" which encode the function
+ * number in the software trap number itself.  So these use trap
+ * numbers > 0x80.  The register usage for hyper-fast traps is as
+ * follows:
+ *
+ * -----------------------------------------------
+ * |  %o0  |   argument 0    |   return status   |
+ * |  %o1  |   argument 1    |   return value 1  |
+ * |  %o2  |   argument 2    |   return value 2  |
+ * |  %o3  |   argument 3    |   return value 3  |
+ * |  %o4  |   argument 4    |   return value 4  |
+ * -----------------------------------------------
+ *
+ * Registers providing explicit arguments to the hypervisor calls
+ * are volatile across the call.  Upon return their values are
+ * undefined unless explicitly specified as containing a particular
+ * return value by the specific call.  The return status is always
+ * returned in register %o0, zero indicates a successful execution of
+ * the hypervisor call and other values indicate an error status as
+ * defined below.  So, for example, if a hyper-fast trap takes
+ * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
+ * the call and %o3, %o4, and %o5 would be preserved.
+ *
+ * If the hypervisor trap is invalid, or the fast trap function number
+ * is invalid, HV_EBADTRAP will be returned in %o0.  Also, all 64-bits
+ * of the argument and return values are significant.
+ */
+
+/* Trap numbers.  */
+#define HV_FAST_TRAP            0x80
+#define HV_MMU_MAP_ADDR_TRAP    0x83
+#define HV_MMU_UNMAP_ADDR_TRAP  0x84
+#define HV_TTRACE_ADDENTRY_TRAP 0x85
+#define HV_CORE_TRAP            0xff
+
+/* Error codes.  */
+#define HV_EOK                          0  /* Successful return            */
+#define HV_ENOCPU                       1  /* Invalid CPU id               */
+#define HV_ENORADDR                     2  /* Invalid real address         */
+#define HV_ENOINTR                      3  /* Invalid interrupt id         */
+#define HV_EBADPGSZ                     4  /* Invalid pagesize encoding    */
+#define HV_EBADTSB                      5  /* Invalid TSB description      */
+#define HV_EINVAL                       6  /* Invalid argument             */
+#define HV_EBADTRAP                     7  /* Invalid function number      */
+#define HV_EBADALIGN                    8  /* Invalid address alignment    */
+#define HV_EWOULDBLOCK                  9  /* Cannot complete w/o blocking */
+#define HV_ENOACCESS                    10 /* No access to resource        */
+#define HV_EIO                          11 /* I/O error                    */
+#define HV_ECPUERROR                    12 /* CPU in error state           */
+#define HV_ENOTSUPPORTED                13 /* Function not supported       */
+#define HV_ENOMAP                       14 /* No mapping found             */
+#define HV_ETOOMANY                     15 /* Too many items specified     */
+#define HV_ECHANNEL                     16 /* Invalid LDC channel          */
+#define HV_EBUSY                        17 /* Resource busy                */
+
+/* mach_exit()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_EXIT
+ * ARG0:        exit code
+ * ERRORS:      This service does not return.
+ *
+ * Stop all CPUs in the virtual domain and place them into the stopped
+ * state.  The 64-bit exit code may be passed to a service entity as
+ * the domain's exit status.  On systems without a service entity, the
+ * domain will undergo a reset, and the boot firmware will be
+ * reloaded.
+ *
+ * This function will never return to the guest that invokes it.
+ *
+ * Note: By convention an exit code of zero denotes a successful exit by
+ *       the guest code.  A non-zero exit code denotes a guest specific
+ *       error indication.
+ *
+ */
+#define HV_FAST_MACH_EXIT               0x00
+
+#ifndef __ASSEMBLY__
+extern void sun4v_mach_exit(unsigned long exit_code);
+#endif
+
+/* Domain services.  */
+
+/* mach_desc()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_DESC
+ * ARG0:        buffer
+ * ARG1:        length
+ * RET0:        status
+ * RET1:        length
+ * ERRORS:      HV_EBADALIGN    Buffer is badly aligned
+ *              HV_ENORADDR     Buffer is to an illegal real address.
+ *              HV_EINVAL       Buffer length is too small for complete
+ *                              machine description.
+ *
+ * Copy the most current machine description into the buffer indicated
+ * by the real address in ARG0.  The buffer provided must be 16 byte
+ * aligned.  Upon success or HV_EINVAL, this service returns the
+ * actual size of the machine description in the RET1 return value.
+ *
+ * Note: A method of determining the appropriate buffer size for the
+ *       machine description is to first call this service with a buffer
+ *       length of 0 bytes.
+ */
+#define HV_FAST_MACH_DESC               0x01
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
+                                     unsigned long buf_len,
+                                     unsigned long *real_buf_len);
+#endif
+
+/* mach_sir()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_SIR
+ * ERRORS:      This service does not return.
+ *
+ * Perform a software initiated reset of the virtual machine domain.
+ * All CPUs are captured as soon as possible, all hardware devices are
+ * returned to the entry default state, and the domain is restarted at
+ * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
+ * of the CPUs.  The single CPU restarted is selected as determined by
+ * platform specific policy.  Memory is preserved across this
+ * operation.
+ */
+#define HV_FAST_MACH_SIR                0x02
+
+#ifndef __ASSEMBLY__
+extern void sun4v_mach_sir(void);
+#endif
+
+/* mach_set_watchdog()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_SET_WATCHDOG
+ * ARG0:        timeout in milliseconds
+ * RET0:        status
+ * RET1:        time remaining in milliseconds
+ *
+ * A guest uses this API to set a watchdog timer.  Once the gues has set
+ * the timer, it must call the timer service again either to disable or
+ * postpone the expiration.  If the timer expires before being reset or
+ * disabled, then the hypervisor take a platform specific action leading
+ * to guest termination within a bounded time period.  The platform action
+ * may include recovery actions such as reporting the expiration to a
+ * Service Processor, and/or automatically restarting the gues.
+ *
+ * The 'timeout' parameter is specified in milliseconds, however the
+ * implementated granularity is given by the 'watchdog-resolution'
+ * property in the 'platform' node of the guest's machine description.
+ * The largest allowed timeout value is specified by the
+ * 'watchdog-max-timeout' property of the 'platform' node.
+ *
+ * If the 'timeout' argument is not zero, the watchdog timer is set to
+ * expire after a minimum of 'timeout' milliseconds.
+ *
+ * If the 'timeout' argument is zero, the watchdog timer is disabled.
+ *
+ * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
+ * property, the hypervisor leaves the watchdog timer state unchanged,
+ * and returns a status of EINVAL.
+ *
+ * The 'time remaining' return value is valid regardless of whether the
+ * return status is EOK or EINVAL.  A non-zero return value indicates the
+ * number of milliseconds that were remaining until the timer was to expire.
+ * If less than one millisecond remains, the return value is '1'.  If the
+ * watchdog timer was disabled at the time of the call, the return value is
+ * zero.
+ *
+ * If the hypervisor cannot support the exact timeout value requested, but
+ * can support a larger timeout value, the hypervisor may round the actual
+ * timeout to a value larger than the requested timeout, consequently the
+ * 'time remaining' return value may be larger than the previously requested
+ * timeout value.
+ *
+ * Any guest OS debugger should be aware that the watchdog service may be in
+ * use.  Consequently, it is recommended that the watchdog service is
+ * disabled upon debugger entry (e.g. reaching a breakpoint), and then
+ * re-enabled upon returning to normal execution.  The API has been designed
+ * with this in mind, and the 'time remaining' result of the disable call may
+ * be used directly as the timeout argument of the re-enable call.
+ */
+#define HV_FAST_MACH_SET_WATCHDOG       0x05
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
+                                             unsigned long *orig_timeout);
+#endif
+
+/* CPU services.
+ *
+ * CPUs represent devices that can execute software threads.  A single
+ * chip that contains multiple cores or strands is represented as
+ * multiple CPUs with unique CPU identifiers.  CPUs are exported to
+ * OBP via the machine description (and to the OS via the OBP device
+ * tree).  CPUs are always in one of three states: stopped, running,
+ * or error.
+ *
+ * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
+ * CPU within a logical domain.  Operations that are to be performed
+ * on multiple CPUs specify them via a CPU list.  A CPU list is an
+ * array in real memory, of which each 16-bit word is a CPU ID.  CPU
+ * lists are passed through the API as two arguments.  The first is
+ * the number of entries (16-bit words) in the CPU list, and the
+ * second is the (real address) pointer to the CPU ID list.
+ */
+
+/* cpu_start()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_START
+ * ARG0:        CPU ID
+ * ARG1:        PC
+ * ARG2:        RTBA
+ * ARG3:        target ARG0
+ * RET0:        status
+ * ERRORS:      ENOCPU          Invalid CPU ID
+ *              EINVAL          Target CPU ID is not in the stopped state
+ *              ENORADDR        Invalid PC or RTBA real address
+ *              EBADALIGN       Unaligned PC or unaligned RTBA
+ *              EWOULDBLOCK     Starting resources are not available
+ *
+ * Start CPU with given CPU ID with PC in %pc and with a real trap
+ * base address value of RTBA.  The indicated CPU must be in the
+ * stopped state.  The supplied RTBA must be aligned on a 256 byte
+ * boundary.  On successful completion, the specified CPU will be in
+ * the running state and will be supplied with "target ARG0" in %o0
+ * and RTBA in %tba.
+ */
+#define HV_FAST_CPU_START               0x10
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_start(unsigned long cpuid,
+                                     unsigned long pc,
+                                     unsigned long rtba,
+                                     unsigned long arg0);
+#endif
+
+/* cpu_stop()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_STOP
+ * ARG0:        CPU ID
+ * RET0:        status
+ * ERRORS:      ENOCPU          Invalid CPU ID
+ *              EINVAL          Target CPU ID is the current cpu
+ *              EINVAL          Target CPU ID is not in the running state
+ *              EWOULDBLOCK     Stopping resources are not available
+ *              ENOTSUPPORTED   Not supported on this platform
+ *
+ * The specified CPU is stopped.  The indicated CPU must be in the
+ * running state.  On completion, it will be in the stopped state.  It
+ * is not legal to stop the current CPU.
+ *
+ * Note: As this service cannot be used to stop the current cpu, this service
+ *       may not be used to stop the last running CPU in a domain.  To stop
+ *       and exit a running domain, a guest must use the mach_exit() service.
+ */
+#define HV_FAST_CPU_STOP                0x11
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
+#endif
+
+/* cpu_yield()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_YIELD
+ * RET0:        status
+ * ERRORS:      No possible error.
+ *
+ * Suspend execution on the current CPU.  Execution will resume when
+ * an interrupt (device, %stick_compare, or cross-call) is targeted to
+ * the CPU.  On some CPUs, this API may be used by the hypervisor to
+ * save power by disabling hardware strands.
+ */
+#define HV_FAST_CPU_YIELD               0x12
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_yield(void);
+#endif
+
+/* cpu_qconf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_QCONF
+ * ARG0:        queue
+ * ARG1:        base real address
+ * ARG2:        number of entries
+ * RET0:        status
+ * ERRORS:      ENORADDR        Invalid base real address
+ *              EINVAL          Invalid queue or number of entries is less
+ *                              than 2 or too large.
+ *              EBADALIGN       Base real address is not correctly aligned
+ *                              for size.
+ *
+ * Configure the given queue to be placed at the given base real
+ * address, with the given number of entries.  The number of entries
+ * must be a power of 2.  The base real address must be aligned
+ * exactly to match the queue size.  Each queue entry is 64 bytes
+ * long, so for example a 32 entry queue must be aligned on a 2048
+ * byte real address boundary.
+ *
+ * The specified queue is unconfigured if the number of entries is given
+ * as zero.
+ *
+ * For the current version of this API service, the argument queue is defined
+ * as follows:
+ *
+ *      queue           description
+ *      -----           -------------------------
+ *      0x3c            cpu mondo queue
+ *      0x3d            device mondo queue
+ *      0x3e            resumable error queue
+ *      0x3f            non-resumable error queue
+ *
+ * Note: The maximum number of entries for each queue for a specific cpu may
+ *       be determined from the machine description.
+ */
+#define HV_FAST_CPU_QCONF               0x14
+#define  HV_CPU_QUEUE_CPU_MONDO          0x3c
+#define  HV_CPU_QUEUE_DEVICE_MONDO       0x3d
+#define  HV_CPU_QUEUE_RES_ERROR          0x3e
+#define  HV_CPU_QUEUE_NONRES_ERROR       0x3f
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_qconf(unsigned long type,
+                                     unsigned long queue_paddr,
+                                     unsigned long num_queue_entries);
+#endif
+
+/* cpu_qinfo()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_QINFO
+ * ARG0:        queue
+ * RET0:        status
+ * RET1:        base real address
+ * RET1:        number of entries
+ * ERRORS:      EINVAL          Invalid queue
+ *
+ * Return the configuration info for the given queue.  The base real
+ * address and number of entries of the defined queue are returned.
+ * The queue argument values are the same as for cpu_qconf() above.
+ *
+ * If the specified queue is a valid queue number, but no queue has
+ * been defined, the number of entries will be set to zero and the
+ * base real address returned is undefined.
+ */
+#define HV_FAST_CPU_QINFO               0x15
+
+/* cpu_mondo_send()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_MONDO_SEND
+ * ARG0-1:      CPU list
+ * ARG2:        data real address
+ * RET0:        status
+ * ERRORS:      EBADALIGN       Mondo data is not 64-byte aligned or CPU list
+ *                              is not 2-byte aligned.
+ *              ENORADDR        Invalid data mondo address, or invalid cpu list
+ *                              address.
+ *              ENOCPU          Invalid cpu in CPU list
+ *              EWOULDBLOCK     Some or all of the listed CPUs did not receive
+ *                              the mondo
+ *              ECPUERROR       One or more of the listed CPUs are in error
+ *                              state, use HV_FAST_CPU_STATE to see which ones
+ *              EINVAL          CPU list includes caller's CPU ID
+ *
+ * Send a mondo interrupt to the CPUs in the given CPU list with the
+ * 64-bytes at the given data real address.  The data must be 64-byte
+ * aligned.  The mondo data will be delivered to the cpu_mondo queues
+ * of the recipient CPUs.
+ *
+ * In all cases, error or not, the CPUs in the CPU list to which the
+ * mondo has been successfully delivered will be indicated by having
+ * their entry in CPU list updated with the value 0xffff.
+ */
+#define HV_FAST_CPU_MONDO_SEND          0x42
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
+#endif
+
+/* cpu_myid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_MYID
+ * RET0:        status
+ * RET1:        CPU ID
+ * ERRORS:      No errors defined.
+ *
+ * Return the hypervisor ID handle for the current CPU.  Use by a
+ * virtual CPU to discover it's own identity.
+ */
+#define HV_FAST_CPU_MYID                0x16
+
+/* cpu_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_STATE
+ * ARG0:        CPU ID
+ * RET0:        status
+ * RET1:        state
+ * ERRORS:      ENOCPU          Invalid CPU ID
+ *
+ * Retrieve the current state of the CPU with the given CPU ID.
+ */
+#define HV_FAST_CPU_STATE               0x17
+#define  HV_CPU_STATE_STOPPED            0x01
+#define  HV_CPU_STATE_RUNNING            0x02
+#define  HV_CPU_STATE_ERROR              0x03
+
+#ifndef __ASSEMBLY__
+extern long sun4v_cpu_state(unsigned long cpuid);
+#endif
+
+/* cpu_set_rtba()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_SET_RTBA
+ * ARG0:        RTBA
+ * RET0:        status
+ * RET1:        previous RTBA
+ * ERRORS:      ENORADDR        Invalid RTBA real address
+ *              EBADALIGN       RTBA is incorrectly aligned for a trap table
+ *
+ * Set the real trap base address of the local cpu to the given RTBA.
+ * The supplied RTBA must be aligned on a 256 byte boundary.  Upon
+ * success the previous value of the RTBA is returned in RET1.
+ *
+ * Note: This service does not affect %tba
+ */
+#define HV_FAST_CPU_SET_RTBA            0x18
+
+/* cpu_set_rtba()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CPU_GET_RTBA
+ * RET0:        status
+ * RET1:        previous RTBA
+ * ERRORS:      No possible error.
+ *
+ * Returns the current value of RTBA in RET1.
+ */
+#define HV_FAST_CPU_GET_RTBA            0x19
+
+/* MMU services.
+ *
+ * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
+ */
+#ifndef __ASSEMBLY__
+struct hv_tsb_descr {
+        unsigned short          pgsz_idx;
+        unsigned short          assoc;
+        unsigned int            num_ttes;       /* in TTEs */
+        unsigned int            ctx_idx;
+        unsigned int            pgsz_mask;
+        unsigned long           tsb_base;
+        unsigned long           resv;
+};
+#endif
+#define HV_TSB_DESCR_PGSZ_IDX_OFFSET    0x00
+#define HV_TSB_DESCR_ASSOC_OFFSET       0x02
+#define HV_TSB_DESCR_NUM_TTES_OFFSET    0x04
+#define HV_TSB_DESCR_CTX_IDX_OFFSET     0x08
+#define HV_TSB_DESCR_PGSZ_MASK_OFFSET   0x0c
+#define HV_TSB_DESCR_TSB_BASE_OFFSET    0x10
+#define HV_TSB_DESCR_RESV_OFFSET        0x18
+
+/* Page size bitmask.  */
+#define HV_PGSZ_MASK_8K                 (1 << 0)
+#define HV_PGSZ_MASK_64K                (1 << 1)
+#define HV_PGSZ_MASK_512K               (1 << 2)
+#define HV_PGSZ_MASK_4MB                (1 << 3)
+#define HV_PGSZ_MASK_32MB               (1 << 4)
+#define HV_PGSZ_MASK_256MB              (1 << 5)
+#define HV_PGSZ_MASK_2GB                (1 << 6)
+#define HV_PGSZ_MASK_16GB               (1 << 7)
+
+/* Page size index.  The value given in the TSB descriptor must correspond
+ * to the smallest page size specified in the pgsz_mask page size bitmask.
+ */
+#define HV_PGSZ_IDX_8K                  0
+#define HV_PGSZ_IDX_64K                 1
+#define HV_PGSZ_IDX_512K                2
+#define HV_PGSZ_IDX_4MB                 3
+#define HV_PGSZ_IDX_32MB                4
+#define HV_PGSZ_IDX_256MB               5
+#define HV_PGSZ_IDX_2GB                 6
+#define HV_PGSZ_IDX_16GB                7
+
+/* MMU fault status area.
+ *
+ * MMU related faults have their status and fault address information
+ * placed into a memory region made available by privileged code.  Each
+ * virtual processor must make a mmu_fault_area_conf() call to tell the
+ * hypervisor where that processor's fault status should be stored.
+ *
+ * The fault status block is a multiple of 64-bytes and must be aligned
+ * on a 64-byte boundary.
+ */
+#ifndef __ASSEMBLY__
+struct hv_fault_status {
+        unsigned long           i_fault_type;
+        unsigned long           i_fault_addr;
+        unsigned long           i_fault_ctx;
+        unsigned long           i_reserved[5];
+        unsigned long           d_fault_type;
+        unsigned long           d_fault_addr;
+        unsigned long           d_fault_ctx;
+        unsigned long           d_reserved[5];
+};
+#endif
+#define HV_FAULT_I_TYPE_OFFSET  0x00
+#define HV_FAULT_I_ADDR_OFFSET  0x08
+#define HV_FAULT_I_CTX_OFFSET   0x10
+#define HV_FAULT_D_TYPE_OFFSET  0x40
+#define HV_FAULT_D_ADDR_OFFSET  0x48
+#define HV_FAULT_D_CTX_OFFSET   0x50
+
+#define HV_FAULT_TYPE_FAST_MISS 1
+#define HV_FAULT_TYPE_FAST_PROT 2
+#define HV_FAULT_TYPE_MMU_MISS  3
+#define HV_FAULT_TYPE_INV_RA    4
+#define HV_FAULT_TYPE_PRIV_VIOL 5
+#define HV_FAULT_TYPE_PROT_VIOL 6
+#define HV_FAULT_TYPE_NFO       7
+#define HV_FAULT_TYPE_NFO_SEFF  8
+#define HV_FAULT_TYPE_INV_VA    9
+#define HV_FAULT_TYPE_INV_ASI   10
+#define HV_FAULT_TYPE_NC_ATOMIC 11
+#define HV_FAULT_TYPE_PRIV_ACT  12
+#define HV_FAULT_TYPE_RESV1     13
+#define HV_FAULT_TYPE_UNALIGNED 14
+#define HV_FAULT_TYPE_INV_PGSZ  15
+/* Values 16 --> -2 are reserved.  */
+#define HV_FAULT_TYPE_MULTIPLE  -1
+
+/* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
+ * and mmu_{map,unmap}_perm_addr().
+ */
+#define HV_MMU_DMMU                     0x01
+#define HV_MMU_IMMU                     0x02
+#define HV_MMU_ALL                      (HV_MMU_DMMU | HV_MMU_IMMU)
+
+/* mmu_map_addr()
+ * TRAP:        HV_MMU_MAP_ADDR_TRAP
+ * ARG0:        virtual address
+ * ARG1:        mmu context
+ * ARG2:        TTE
+ * ARG3:        flags (HV_MMU_{IMMU,DMMU})
+ * ERRORS:      EINVAL          Invalid virtual address, mmu context, or flags
+ *              EBADPGSZ        Invalid page size value
+ *              ENORADDR        Invalid real address in TTE
+ *
+ * Create a non-permanent mapping using the given TTE, virtual
+ * address, and mmu context.  The flags argument determines which
+ * (data, or instruction, or both) TLB the mapping gets loaded into.
+ *
+ * The behavior is undefined if the valid bit is clear in the TTE.
+ *
+ * Note: This API call is for privileged code to specify temporary translation
+ *       mappings without the need to create and manage a TSB.
+ */
+
+/* mmu_unmap_addr()
+ * TRAP:        HV_MMU_UNMAP_ADDR_TRAP
+ * ARG0:        virtual address
+ * ARG1:        mmu context
+ * ARG2:        flags (HV_MMU_{IMMU,DMMU})
+ * ERRORS:      EINVAL          Invalid virtual address, mmu context, or flags
+ *
+ * Demaps the given virtual address in the given mmu context on this
+ * CPU.  This function is intended to be used to demap pages mapped
+ * with mmu_map_addr.  This service is equivalent to invoking
+ * mmu_demap_page() with only the current CPU in the CPU list. The
+ * flags argument determines which (data, or instruction, or both) TLB
+ * the mapping gets unmapped from.
+ *
+ * Attempting to perform an unmap operation for a previously defined
+ * permanent mapping will have undefined results.
+ */
+
+/* mmu_tsb_ctx0()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_TSB_CTX0
+ * ARG0:        number of TSB descriptions
+ * ARG1:        TSB descriptions pointer
+ * RET0:        status
+ * ERRORS:      ENORADDR                Invalid TSB descriptions pointer or
+ *                                      TSB base within a descriptor
+ *              EBADALIGN               TSB descriptions pointer is not aligned
+ *                                      to an 8-byte boundary, or TSB base
+ *                                      within a descriptor is not aligned for
+ *                                      the given TSB size
+ *              EBADPGSZ                Invalid page size in a TSB descriptor
+ *              EBADTSB                 Invalid associativity or size in a TSB
+ *                                      descriptor
+ *              EINVAL                  Invalid number of TSB descriptions, or
+ *                                      invalid context index in a TSB
+ *                                      descriptor, or index page size not
+ *                                      equal to smallest page size in page
+ *                                      size bitmask field.
+ *
+ * Configures the TSBs for the current CPU for virtual addresses with
+ * context zero.  The TSB descriptions pointer is a pointer to an
+ * array of the given number of TSB descriptions.
+ *
+ * Note: The maximum number of TSBs available to a virtual CPU is given by the
+ *       mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
+ *       machine description.
+ */
+#define HV_FAST_MMU_TSB_CTX0            0x20
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
+                                        unsigned long tsb_desc_ra);
+#endif
+
+/* mmu_tsb_ctxnon0()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_TSB_CTXNON0
+ * ARG0:        number of TSB descriptions
+ * ARG1:        TSB descriptions pointer
+ * RET0:        status
+ * ERRORS:      Same as for mmu_tsb_ctx0() above.
+ *
+ * Configures the TSBs for the current CPU for virtual addresses with
+ * non-zero contexts.  The TSB descriptions pointer is a pointer to an
+ * array of the given number of TSB descriptions.
+ *
+ * Note: A maximum of 16 TSBs may be specified in the TSB description list.
+ */
+#define HV_FAST_MMU_TSB_CTXNON0         0x21
+
+/* mmu_demap_page()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_DEMAP_PAGE
+ * ARG0:        reserved, must be zero
+ * ARG1:        reserved, must be zero
+ * ARG2:        virtual address
+ * ARG3:        mmu context
+ * ARG4:        flags (HV_MMU_{IMMU,DMMU})
+ * RET0:        status
+ * ERRORS:      EINVAL                  Invalid virutal address, context, or
+ *                                      flags value
+ *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
+ *
+ * Demaps any page mapping of the given virtual address in the given
+ * mmu context for the current virtual CPU.  Any virtually tagged
+ * caches are guaranteed to be kept consistent.  The flags argument
+ * determines which TLB (instruction, or data, or both) participate in
+ * the operation.
+ *
+ * ARG0 and ARG1 are both reserved and must be set to zero.
+ */
+#define HV_FAST_MMU_DEMAP_PAGE          0x22
+
+/* mmu_demap_ctx()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_DEMAP_CTX
+ * ARG0:        reserved, must be zero
+ * ARG1:        reserved, must be zero
+ * ARG2:        mmu context
+ * ARG3:        flags (HV_MMU_{IMMU,DMMU})
+ * RET0:        status
+ * ERRORS:      EINVAL                  Invalid context or flags value
+ *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
+ *
+ * Demaps all non-permanent virtual page mappings previously specified
+ * for the given context for the current virtual CPU.  Any virtual
+ * tagged caches are guaranteed to be kept consistent.  The flags
+ * argument determines which TLB (instruction, or data, or both)
+ * participate in the operation.
+ *
+ * ARG0 and ARG1 are both reserved and must be set to zero.
+ */
+#define HV_FAST_MMU_DEMAP_CTX           0x23
+
+/* mmu_demap_all()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_DEMAP_ALL
+ * ARG0:        reserved, must be zero
+ * ARG1:        reserved, must be zero
+ * ARG2:        flags (HV_MMU_{IMMU,DMMU})
+ * RET0:        status
+ * ERRORS:      EINVAL                  Invalid flags value
+ *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
+ *
+ * Demaps all non-permanent virtual page mappings previously specified
+ * for the current virtual CPU.  Any virtual tagged caches are
+ * guaranteed to be kept consistent.  The flags argument determines
+ * which TLB (instruction, or data, or both) participate in the
+ * operation.
+ *
+ * ARG0 and ARG1 are both reserved and must be set to zero.
+ */
+#define HV_FAST_MMU_DEMAP_ALL           0x24
+
+#ifndef __ASSEMBLY__
+extern void sun4v_mmu_demap_all(void);
+#endif
+
+/* mmu_map_perm_addr()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_MAP_PERM_ADDR
+ * ARG0:        virtual address
+ * ARG1:        reserved, must be zero
+ * ARG2:        TTE
+ * ARG3:        flags (HV_MMU_{IMMU,DMMU})
+ * RET0:        status
+ * ERRORS:      EINVAL                  Invalid virutal address or flags value
+ *              EBADPGSZ                Invalid page size value
+ *              ENORADDR                Invalid real address in TTE
+ *              ETOOMANY                Too many mappings (max of 8 reached)
+ *
+ * Create a permanent mapping using the given TTE and virtual address
+ * for context 0 on the calling virtual CPU.  A maximum of 8 such
+ * permanent mappings may be specified by privileged code.  Mappings
+ * may be removed with mmu_unmap_perm_addr().
+ *
+ * The behavior is undefined if a TTE with the valid bit clear is given.
+ *
+ * Note: This call is used to specify address space mappings for which
+ *       privileged code does not expect to receive misses.  For example,
+ *       this mechanism can be used to map kernel nucleus code and data.
+ */
+#define HV_FAST_MMU_MAP_PERM_ADDR       0x25
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
+                                             unsigned long set_to_zero,
+                                             unsigned long tte,
+                                             unsigned long flags);
+#endif
+
+/* mmu_fault_area_conf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_FAULT_AREA_CONF
+ * ARG0:        real address
+ * RET0:        status
+ * RET1:        previous mmu fault area real address
+ * ERRORS:      ENORADDR                Invalid real address
+ *              EBADALIGN               Invalid alignment for fault area
+ *
+ * Configure the MMU fault status area for the calling CPU.  A 64-byte
+ * aligned real address specifies where MMU fault status information
+ * is placed.  The return value is the previously specified area, or 0
+ * for the first invocation.  Specifying a fault area at real address
+ * 0 is not allowed.
+ */
+#define HV_FAST_MMU_FAULT_AREA_CONF     0x26
+
+/* mmu_enable()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_ENABLE
+ * ARG0:        enable flag
+ * ARG1:        return target address
+ * RET0:        status
+ * ERRORS:      ENORADDR                Invalid real address when disabling
+ *                                      translation.
+ *              EBADALIGN               The return target address is not
+ *                                      aligned to an instruction.
+ *              EINVAL                  The enable flag request the current
+ *                                      operating mode (e.g. disable if already
+ *                                      disabled)
+ *
+ * Enable or disable virtual address translation for the calling CPU
+ * within the virtual machine domain.  If the enable flag is zero,
+ * translation is disabled, any non-zero value will enable
+ * translation.
+ *
+ * When this function returns, the newly selected translation mode
+ * will be active.  If the mmu is being enabled, then the return
+ * target address is a virtual address else it is a real address.
+ *
+ * Upon successful completion, control will be returned to the given
+ * return target address (ie. the cpu will jump to that address).  On
+ * failure, the previous mmu mode remains and the trap simply returns
+ * as normal with the appropriate error code in RET0.
+ */
+#define HV_FAST_MMU_ENABLE              0x27
+
+/* mmu_unmap_perm_addr()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_UNMAP_PERM_ADDR
+ * ARG0:        virtual address
+ * ARG1:        reserved, must be zero
+ * ARG2:        flags (HV_MMU_{IMMU,DMMU})
+ * RET0:        status
+ * ERRORS:      EINVAL                  Invalid virutal address or flags value
+ *              ENOMAP                  Specified mapping was not found
+ *
+ * Demaps any permanent page mapping (established via
+ * mmu_map_perm_addr()) at the given virtual address for context 0 on
+ * the current virtual CPU.  Any virtual tagged caches are guaranteed
+ * to be kept consistent.
+ */
+#define HV_FAST_MMU_UNMAP_PERM_ADDR     0x28
+
+/* mmu_tsb_ctx0_info()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_TSB_CTX0_INFO
+ * ARG0:        max TSBs
+ * ARG1:        buffer pointer
+ * RET0:        status
+ * RET1:        number of TSBs
+ * ERRORS:      EINVAL                  Supplied buffer is too small
+ *              EBADALIGN               The buffer pointer is badly aligned
+ *              ENORADDR                Invalid real address for buffer pointer
+ *
+ * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
+ * into the provided buffer.  The size of the buffer is given in ARG1
+ * in terms of the number of TSB description entries.
+ *
+ * Upon return, RET1 always contains the number of TSB descriptions
+ * previously configured.  If zero TSBs were configured, EOK is
+ * returned with RET1 containing 0.
+ */
+#define HV_FAST_MMU_TSB_CTX0_INFO       0x29
+
+/* mmu_tsb_ctxnon0_info()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_TSB_CTXNON0_INFO
+ * ARG0:        max TSBs
+ * ARG1:        buffer pointer
+ * RET0:        status
+ * RET1:        number of TSBs
+ * ERRORS:      EINVAL                  Supplied buffer is too small
+ *              EBADALIGN               The buffer pointer is badly aligned
+ *              ENORADDR                Invalid real address for buffer pointer
+ *
+ * Return the TSB configuration as previous defined by
+ * mmu_tsb_ctxnon0() into the provided buffer.  The size of the buffer
+ * is given in ARG1 in terms of the number of TSB description entries.
+ *
+ * Upon return, RET1 always contains the number of TSB descriptions
+ * previously configured.  If zero TSBs were configured, EOK is
+ * returned with RET1 containing 0.
+ */
+#define HV_FAST_MMU_TSB_CTXNON0_INFO    0x2a
+
+/* mmu_fault_area_info()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMU_FAULT_AREA_INFO
+ * RET0:        status
+ * RET1:        fault area real address
+ * ERRORS:      No errors defined.
+ *
+ * Return the currently defined MMU fault status area for the current
+ * CPU.  The real address of the fault status area is returned in
+ * RET1, or 0 is returned in RET1 if no fault status area is defined.
+ *
+ * Note: mmu_fault_area_conf() may be called with the return value (RET1)
+ *       from this service if there is a need to save and restore the fault
+ *       area for a cpu.
+ */
+#define HV_FAST_MMU_FAULT_AREA_INFO     0x2b
+
+/* Cache and Memory services. */
+
+/* mem_scrub()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MEM_SCRUB
+ * ARG0:        real address
+ * ARG1:        length
+ * RET0:        status
+ * RET1:        length scrubbed
+ * ERRORS:      ENORADDR        Invalid real address
+ *              EBADALIGN       Start address or length are not correctly
+ *                              aligned
+ *              EINVAL          Length is zero
+ *
+ * Zero the memory contents in the range real address to real address
+ * plus length minus 1.  Also, valid ECC will be generated for that
+ * memory address range.  Scrubbing is started at the given real
+ * address, but may not scrub the entire given length.  The actual
+ * length scrubbed will be returned in RET1.
+ *
+ * The real address and length must be aligned on an 8K boundary, or
+ * contain the start address and length from a sun4v error report.
+ *
+ * Note: There are two uses for this function.  The first use is to block clear
+ *       and initialize memory and the second is to scrub an u ncorrectable
+ *       error reported via a resumable or non-resumable trap.  The second
+ *       use requires the arguments to be equal to the real address and length
+ *       provided in a sun4v memory error report.
+ */
+#define HV_FAST_MEM_SCRUB               0x31
+
+/* mem_sync()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MEM_SYNC
+ * ARG0:        real address
+ * ARG1:        length
+ * RET0:        status
+ * RET1:        length synced
+ * ERRORS:      ENORADDR        Invalid real address
+ *              EBADALIGN       Start address or length are not correctly
+ *                              aligned
+ *              EINVAL          Length is zero
+ *
+ * Force the next access within the real address to real address plus
+ * length minus 1 to be fetches from main system memory.  Less than
+ * the given length may be synced, the actual amount synced is
+ * returned in RET1.  The real address and length must be aligned on
+ * an 8K boundary.
+ */
+#define HV_FAST_MEM_SYNC                0x32
+
+/* Time of day services.
+ *
+ * The hypervisor maintains the time of day on a per-domain basis.
+ * Changing the time of day in one domain does not affect the time of
+ * day on any other domain.
+ *
+ * Time is described by a single unsigned 64-bit word which is the
+ * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
+ * 1970).
+ */
+
+/* tod_get()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_TOD_GET
+ * RET0:        status
+ * RET1:        TOD
+ * ERRORS:      EWOULDBLOCK     TOD resource is temporarily unavailable
+ *              ENOTSUPPORTED   If TOD not supported on this platform
+ *
+ * Return the current time of day.  May block if TOD access is
+ * temporarily not possible.
+ */
+#define HV_FAST_TOD_GET                 0x50
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_tod_get(unsigned long *time);
+#endif
+
+/* tod_set()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_TOD_SET
+ * ARG0:        TOD
+ * RET0:        status
+ * ERRORS:      EWOULDBLOCK     TOD resource is temporarily unavailable
+ *              ENOTSUPPORTED   If TOD not supported on this platform
+ *
+ * The current time of day is set to the value specified in ARG0.  May
+ * block if TOD access is temporarily not possible.
+ */
+#define HV_FAST_TOD_SET                 0x51
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_tod_set(unsigned long time);
+#endif
+
+/* Console services */
+
+/* con_getchar()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CONS_GETCHAR
+ * RET0:        status
+ * RET1:        character
+ * ERRORS:      EWOULDBLOCK     No character available.
+ *
+ * Returns a character from the console device.  If no character is
+ * available then an EWOULDBLOCK error is returned.  If a character is
+ * available, then the returned status is EOK and the character value
+ * is in RET1.
+ *
+ * A virtual BREAK is represented by the 64-bit value -1.
+ *
+ * A virtual HUP signal is represented by the 64-bit value -2.
+ */
+#define HV_FAST_CONS_GETCHAR            0x60
+
+/* con_putchar()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CONS_PUTCHAR
+ * ARG0:        character
+ * RET0:        status
+ * ERRORS:      EINVAL          Illegal character
+ *              EWOULDBLOCK     Output buffer currently full, would block
+ *
+ * Send a character to the console device.  Only character values
+ * between 0 and 255 may be used.  Values outside this range are
+ * invalid except for the 64-bit value -1 which is used to send a
+ * virtual BREAK.
+ */
+#define HV_FAST_CONS_PUTCHAR            0x61
+
+/* con_read()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CONS_READ
+ * ARG0:        buffer real address
+ * ARG1:        buffer size in bytes
+ * RET0:        status
+ * RET1:        bytes read or BREAK or HUP
+ * ERRORS:      EWOULDBLOCK     No character available.
+ *
+ * Reads characters into a buffer from the console device.  If no
+ * character is available then an EWOULDBLOCK error is returned.
+ * If a character is available, then the returned status is EOK
+ * and the number of bytes read into the given buffer is provided
+ * in RET1.
+ *
+ * A virtual BREAK is represented by the 64-bit RET1 value -1.
+ *
+ * A virtual HUP signal is represented by the 64-bit RET1 value -2.
+ *
+ * If BREAK or HUP are indicated, no bytes were read into buffer.
+ */
+#define HV_FAST_CONS_READ               0x62
+
+/* con_write()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CONS_WRITE
+ * ARG0:        buffer real address
+ * ARG1:        buffer size in bytes
+ * RET0:        status
+ * RET1:        bytes written
+ * ERRORS:      EWOULDBLOCK     Output buffer currently full, would block
+ *
+ * Send a characters in buffer to the console device.  Breaks must be
+ * sent using con_putchar().
+ */
+#define HV_FAST_CONS_WRITE              0x63
+
+#ifndef __ASSEMBLY__
+extern long sun4v_con_getchar(long *status);
+extern long sun4v_con_putchar(long c);
+extern long sun4v_con_read(unsigned long buffer,
+                           unsigned long size,
+                           unsigned long *bytes_read);
+extern unsigned long sun4v_con_write(unsigned long buffer,
+                                     unsigned long size,
+                                     unsigned long *bytes_written);
+#endif
+
+/* mach_set_soft_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_SET_SOFT_STATE
+ * ARG0:        software state
+ * ARG1:        software state description pointer
+ * RET0:        status
+ * ERRORS:      EINVAL          software state not valid or software state
+ *                              description is not NULL terminated
+ *              ENORADDR        software state description pointer is not a
+ *                              valid real address
+ *              EBADALIGNED     software state description is not correctly
+ *                              aligned
+ *
+ * This allows the guest to report it's soft state to the hypervisor.  There
+ * are two primary components to this state.  The first part states whether
+ * the guest software is running or not.  The second containts optional
+ * details specific to the software.
+ *
+ * The software state argument is defined below in HV_SOFT_STATE_*, and
+ * indicates whether the guest is operating normally or in a transitional
+ * state.
+ *
+ * The software state description argument is a real address of a data buffer
+ * of size 32-bytes aligned on a 32-byte boundary.  It is treated as a NULL
+ * terminated 7-bit ASCII string of up to 31 characters not including the
+ * NULL termination.
+ */
+#define HV_FAST_MACH_SET_SOFT_STATE     0x70
+#define  HV_SOFT_STATE_NORMAL            0x01
+#define  HV_SOFT_STATE_TRANSITION        0x02
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
+                                               unsigned long msg_string_ra);
+#endif
+
+/* mach_get_soft_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_GET_SOFT_STATE
+ * ARG0:        software state description pointer
+ * RET0:        status
+ * RET1:        software state
+ * ERRORS:      ENORADDR        software state description pointer is not a
+ *                              valid real address
+ *              EBADALIGNED     software state description is not correctly
+ *                              aligned
+ *
+ * Retrieve the current value of the guest's software state.  The rules
+ * for the software state pointer are the same as for mach_set_soft_state()
+ * above.
+ */
+#define HV_FAST_MACH_GET_SOFT_STATE     0x71
+
+/* svc_send()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_SVC_SEND
+ * ARG0:        service ID
+ * ARG1:        buffer real address
+ * ARG2:        buffer size
+ * RET0:        STATUS
+ * RET1:        sent_bytes
+ *
+ * Be careful, all output registers are clobbered by this operation,
+ * so for example it is not possible to save away a value in %o4
+ * across the trap.
+ */
+#define HV_FAST_SVC_SEND                0x80
+
+/* svc_recv()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_SVC_RECV
+ * ARG0:        service ID
+ * ARG1:        buffer real address
+ * ARG2:        buffer size
+ * RET0:        STATUS
+ * RET1:        recv_bytes
+ *
+ * Be careful, all output registers are clobbered by this operation,
+ * so for example it is not possible to save away a value in %o4
+ * across the trap.
+ */
+#define HV_FAST_SVC_RECV                0x81
+
+/* svc_getstatus()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_SVC_GETSTATUS
+ * ARG0:        service ID
+ * RET0:        STATUS
+ * RET1:        status bits
+ */
+#define HV_FAST_SVC_GETSTATUS           0x82
+
+/* svc_setstatus()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_SVC_SETSTATUS
+ * ARG0:        service ID
+ * ARG1:        bits to set
+ * RET0:        STATUS
+ */
+#define HV_FAST_SVC_SETSTATUS           0x83
+
+/* svc_clrstatus()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_SVC_CLRSTATUS
+ * ARG0:        service ID
+ * ARG1:        bits to clear
+ * RET0:        STATUS
+ */
+#define HV_FAST_SVC_CLRSTATUS           0x84
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_svc_send(unsigned long svc_id,
+                                    unsigned long buffer,
+                                    unsigned long buffer_size,
+                                    unsigned long *sent_bytes);
+extern unsigned long sun4v_svc_recv(unsigned long svc_id,
+                                    unsigned long buffer,
+                                    unsigned long buffer_size,
+                                    unsigned long *recv_bytes);
+extern unsigned long sun4v_svc_getstatus(unsigned long svc_id,
+                                         unsigned long *status_bits);
+extern unsigned long sun4v_svc_setstatus(unsigned long svc_id,
+                                         unsigned long status_bits);
+extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
+                                         unsigned long status_bits);
+#endif
+
+/* Trap trace services.
+ *
+ * The hypervisor provides a trap tracing capability for privileged
+ * code running on each virtual CPU.  Privileged code provides a
+ * round-robin trap trace queue within which the hypervisor writes
+ * 64-byte entries detailing hyperprivileged traps taken n behalf of
+ * privileged code.  This is provided as a debugging capability for
+ * privileged code.
+ *
+ * The trap trace control structure is 64-bytes long and placed at the
+ * start (offset 0) of the trap trace buffer, and is described as
+ * follows:
+ */
+#ifndef __ASSEMBLY__
+struct hv_trap_trace_control {
+        unsigned long           head_offset;
+        unsigned long           tail_offset;
+        unsigned long           __reserved[0x30 / sizeof(unsigned long)];
+};
+#endif
+#define HV_TRAP_TRACE_CTRL_HEAD_OFFSET  0x00
+#define HV_TRAP_TRACE_CTRL_TAIL_OFFSET  0x08
+
+/* The head offset is the offset of the most recently completed entry
+ * in the trap-trace buffer.  The tail offset is the offset of the
+ * next entry to be written.  The control structure is owned and
+ * modified by the hypervisor.  A guest may not modify the control
+ * structure contents.  Attempts to do so will result in undefined
+ * behavior for the guest.
+ *
+ * Each trap trace buffer entry is layed out as follows:
+ */
+#ifndef __ASSEMBLY__
+struct hv_trap_trace_entry {
+        unsigned char   type;           /* Hypervisor or guest entry?   */
+        unsigned char   hpstate;        /* Hyper-privileged state       */
+        unsigned char   tl;             /* Trap level                   */
+        unsigned char   gl;             /* Global register level        */
+        unsigned short  tt;             /* Trap type                    */
+        unsigned short  tag;            /* Extended trap identifier     */
+        unsigned long   tstate;         /* Trap state                   */
+        unsigned long   tick;           /* Tick                         */
+        unsigned long   tpc;            /* Trap PC                      */
+        unsigned long   f1;             /* Entry specific               */
+        unsigned long   f2;             /* Entry specific               */
+        unsigned long   f3;             /* Entry specific               */
+        unsigned long   f4;             /* Entry specific               */
+};
+#endif
+#define HV_TRAP_TRACE_ENTRY_TYPE        0x00
+#define HV_TRAP_TRACE_ENTRY_HPSTATE     0x01
+#define HV_TRAP_TRACE_ENTRY_TL          0x02
+#define HV_TRAP_TRACE_ENTRY_GL          0x03
+#define HV_TRAP_TRACE_ENTRY_TT          0x04
+#define HV_TRAP_TRACE_ENTRY_TAG         0x06
+#define HV_TRAP_TRACE_ENTRY_TSTATE      0x08
+#define HV_TRAP_TRACE_ENTRY_TICK        0x10
+#define HV_TRAP_TRACE_ENTRY_TPC         0x18
+#define HV_TRAP_TRACE_ENTRY_F1          0x20
+#define HV_TRAP_TRACE_ENTRY_F2          0x28
+#define HV_TRAP_TRACE_ENTRY_F3          0x30
+#define HV_TRAP_TRACE_ENTRY_F4          0x38
+
+/* The type field is encoded as follows.  */
+#define HV_TRAP_TYPE_UNDEF              0x00 /* Entry content undefined     */
+#define HV_TRAP_TYPE_HV                 0x01 /* Hypervisor trap entry       */
+#define HV_TRAP_TYPE_GUEST              0xff /* Added via ttrace_addentry() */
+
+/* ttrace_buf_conf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_TTRACE_BUF_CONF
+ * ARG0:        real address
+ * ARG1:        number of entries
+ * RET0:        status
+ * RET1:        number of entries
+ * ERRORS:      ENORADDR        Invalid real address
+ *              EINVAL          Size is too small
+ *              EBADALIGN       Real address not aligned on 64-byte boundary
+ *
+ * Requests hypervisor trap tracing and declares a virtual CPU's trap
+ * trace buffer to the hypervisor.  The real address supplies the real
+ * base address of the trap trace queue and must be 64-byte aligned.
+ * Specifying a value of 0 for the number of entries disables trap
+ * tracing for the calling virtual CPU.  The buffer allocated must be
+ * sized for a power of two number of 64-byte trap trace entries plus
+ * an initial 64-byte control structure.
+ *
+ * This may be invoked any number of times so that a virtual CPU may
+ * relocate a trap trace buffer or create "snapshots" of information.
+ *
+ * If the real address is illegal or badly aligned, then trap tracing
+ * is disabled and an error is returned.
+ *
+ * Upon failure with EINVAL, this service call returns in RET1 the
+ * minimum number of buffer entries required.  Upon other failures
+ * RET1 is undefined.
+ */
+#define HV_FAST_TTRACE_BUF_CONF         0x90
+
+/* ttrace_buf_info()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_TTRACE_BUF_INFO
+ * RET0:        status
+ * RET1:        real address
+ * RET2:        size
+ * ERRORS:      None defined.
+ *
+ * Returns the size and location of the previously declared trap-trace
+ * buffer.  In the event that no buffer was previously defined, or the
+ * buffer is disabled, this call will return a size of zero bytes.
+ */
+#define HV_FAST_TTRACE_BUF_INFO         0x91
+
+/* ttrace_enable()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_TTRACE_ENABLE
+ * ARG0:        enable
+ * RET0:        status
+ * RET1:        previous enable state
+ * ERRORS:      EINVAL          No trap trace buffer currently defined
+ *
+ * Enable or disable trap tracing, and return the previous enabled
+ * state in RET1.  Future systems may define various flags for the
+ * enable argument (ARG0), for the moment a guest should pass
+ * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
+ * tracing - which will ensure future compatability.
+ */
+#define HV_FAST_TTRACE_ENABLE           0x92
+
+/* ttrace_freeze()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_TTRACE_FREEZE
+ * ARG0:        freeze
+ * RET0:        status
+ * RET1:        previous freeze state
+ * ERRORS:      EINVAL          No trap trace buffer currently defined
+ *
+ * Freeze or unfreeze trap tracing, returning the previous freeze
+ * state in RET1.  A guest should pass a non-zero value to freeze and
+ * a zero value to unfreeze all tracing.  The returned previous state
+ * is 0 for not frozen and 1 for frozen.
+ */
+#define HV_FAST_TTRACE_FREEZE           0x93
+
+/* ttrace_addentry()
+ * TRAP:        HV_TTRACE_ADDENTRY_TRAP
+ * ARG0:        tag (16-bits)
+ * ARG1:        data word 0
+ * ARG2:        data word 1
+ * ARG3:        data word 2
+ * ARG4:        data word 3
+ * RET0:        status
+ * ERRORS:      EINVAL          No trap trace buffer currently defined
+ *
+ * Add an entry to the trap trace buffer.  Upon return only ARG0/RET0
+ * is modified - none of the other registers holding arguments are
+ * volatile across this hypervisor service.
+ */
+
+/* Core dump services.
+ *
+ * Since the hypervisor viraulizes and thus obscures a lot of the
+ * physical machine layout and state, traditional OS crash dumps can
+ * be difficult to diagnose especially when the problem is a
+ * configuration error of some sort.
+ *
+ * The dump services provide an opaque buffer into which the
+ * hypervisor can place it's internal state in order to assist in
+ * debugging such situations.  The contents are opaque and extremely
+ * platform and hypervisor implementation specific.  The guest, during
+ * a core dump, requests that the hypervisor update any information in
+ * the dump buffer in preparation to being dumped as part of the
+ * domain's memory image.
+ */
+
+/* dump_buf_update()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_DUMP_BUF_UPDATE
+ * ARG0:        real address
+ * ARG1:        size
+ * RET0:        status
+ * RET1:        required size of dump buffer
+ * ERRORS:      ENORADDR        Invalid real address
+ *              EBADALIGN       Real address is not aligned on a 64-byte
+ *                              boundary
+ *              EINVAL          Size is non-zero but less than minimum size
+ *                              required
+ *              ENOTSUPPORTED   Operation not supported on current logical
+ *                              domain
+ *
+ * Declare a domain dump buffer to the hypervisor.  The real address
+ * provided for the domain dump buffer must be 64-byte aligned.  The
+ * size specifies the size of the dump buffer and may be larger than
+ * the minimum size specified in the machine description.  The
+ * hypervisor will fill the dump buffer with opaque data.
+ *
+ * Note: A guest may elect to include dump buffer contents as part of a crash
+ *       dump to assist with debugging.  This function may be called any number
+ *       of times so that a guest may relocate a dump buffer, or create
+ *       "snapshots" of any dump-buffer information.  Each call to
+ *       dump_buf_update() atomically declares the new dump buffer to the
+ *       hypervisor.
+ *
+ * A specified size of 0 unconfigures the dump buffer.  If the real
+ * address is illegal or badly aligned, then any currently active dump
+ * buffer is disabled and an error is returned.
+ *
+ * In the event that the call fails with EINVAL, RET1 contains the
+ * minimum size requires by the hypervisor for a valid dump buffer.
+ */
+#define HV_FAST_DUMP_BUF_UPDATE         0x94
+
+/* dump_buf_info()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_DUMP_BUF_INFO
+ * RET0:        status
+ * RET1:        real address of current dump buffer
+ * RET2:        size of current dump buffer
+ * ERRORS:      No errors defined.
+ *
+ * Return the currently configures dump buffer description.  A
+ * returned size of 0 bytes indicates an undefined dump buffer.  In
+ * this case the return address in RET1 is undefined.
+ */
+#define HV_FAST_DUMP_BUF_INFO           0x95
+
+/* Device interrupt services.
+ *
+ * Device interrupts are allocated to system bus bridges by the hypervisor,
+ * and described to OBP in the machine description.  OBP then describes
+ * these interrupts to the OS via properties in the device tree.
+ *
+ * Terminology:
+ *
+ *      cpuid           Unique opaque value which represents a target cpu.
+ *
+ *      devhandle       Device handle.  It uniquely identifies a device, and
+ *                      consistes of the lower 28-bits of the hi-cell of the
+ *                      first entry of the device's "reg" property in the
+ *                      OBP device tree.
+ *
+ *      devino          Device interrupt number.  Specifies the relative
+ *                      interrupt number within the device.  The unique
+ *                      combination of devhandle and devino are used to
+ *                      identify a specific device interrupt.
+ *
+ *                      Note: The devino value is the same as the values in the
+ *                            "interrupts" property or "interrupt-map" property
+ *                            in the OBP device tree for that device.
+ *
+ *      sysino          System interrupt number.  A 64-bit unsigned interger
+ *                      representing a unique interrupt within a virtual
+ *                      machine.
+ *
+ *      intr_state      A flag representing the interrupt state for a given
+ *                      sysino.  The state values are defined below.
+ *
+ *      intr_enabled    A flag representing the 'enabled' state for a given
+ *                      sysino.  The enable values are defined below.
+ */
+
+#define HV_INTR_STATE_IDLE              0 /* Nothing pending */
+#define HV_INTR_STATE_RECEIVED          1 /* Interrupt received by hardware */
+#define HV_INTR_STATE_DELIVERED         2 /* Interrupt delivered to queue */
+
+#define HV_INTR_DISABLED                0 /* sysino not enabled */
+#define HV_INTR_ENABLED                 1 /* sysino enabled */
+
+/* intr_devino_to_sysino()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_INTR_DEVINO2SYSINO
+ * ARG0:        devhandle
+ * ARG1:        devino
+ * RET0:        status
+ * RET1:        sysino
+ * ERRORS:      EINVAL          Invalid devhandle/devino
+ *
+ * Converts a device specific interrupt number of the given
+ * devhandle/devino into a system specific ino (sysino).
+ */
+#define HV_FAST_INTR_DEVINO2SYSINO      0xa0
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
+                                            unsigned long devino);
+#endif
+
+/* intr_getenabled()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_INTR_GETENABLED
+ * ARG0:        sysino
+ * RET0:        status
+ * RET1:        intr_enabled (HV_INTR_{DISABLED,ENABLED})
+ * ERRORS:      EINVAL          Invalid sysino
+ *
+ * Returns interrupt enabled state in RET1 for the interrupt defined
+ * by the given sysino.
+ */
+#define HV_FAST_INTR_GETENABLED         0xa1
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
+#endif
+
+/* intr_setenabled()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_INTR_SETENABLED
+ * ARG0:        sysino
+ * ARG1:        intr_enabled (HV_INTR_{DISABLED,ENABLED})
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid sysino or intr_enabled value
+ *
+ * Set the 'enabled' state of the interrupt sysino.
+ */
+#define HV_FAST_INTR_SETENABLED         0xa2
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
+#endif
+
+/* intr_getstate()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_INTR_GETSTATE
+ * ARG0:        sysino
+ * RET0:        status
+ * RET1:        intr_state (HV_INTR_STATE_*)
+ * ERRORS:      EINVAL          Invalid sysino
+ *
+ * Returns current state of the interrupt defined by the given sysino.
+ */
+#define HV_FAST_INTR_GETSTATE           0xa3
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_getstate(unsigned long sysino);
+#endif
+
+/* intr_setstate()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_INTR_SETSTATE
+ * ARG0:        sysino
+ * ARG1:        intr_state (HV_INTR_STATE_*)
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid sysino or intr_state value
+ *
+ * Sets the current state of the interrupt described by the given sysino
+ * value.
+ *
+ * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
+ *       interrupt for sysino.
+ */
+#define HV_FAST_INTR_SETSTATE           0xa4
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
+#endif
+
+/* intr_gettarget()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_INTR_GETTARGET
+ * ARG0:        sysino
+ * RET0:        status
+ * RET1:        cpuid
+ * ERRORS:      EINVAL          Invalid sysino
+ *
+ * Returns CPU that is the current target of the interrupt defined by
+ * the given sysino.  The CPU value returned is undefined if the target
+ * has not been set via intr_settarget().
+ */
+#define HV_FAST_INTR_GETTARGET          0xa5
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
+#endif
+
+/* intr_settarget()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_INTR_SETTARGET
+ * ARG0:        sysino
+ * ARG1:        cpuid
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid sysino
+ *              ENOCPU          Invalid cpuid
+ *
+ * Set the target CPU for the interrupt defined by the given sysino.
+ */
+#define HV_FAST_INTR_SETTARGET          0xa6
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
+#endif
+
+/* vintr_get_cookie()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_COOKIE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        cookie
+ */
+#define HV_FAST_VINTR_GET_COOKIE        0xa7
+
+/* vintr_set_cookie()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_COOKIE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        cookie
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_COOKIE        0xa8
+
+/* vintr_get_valid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_VALID
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        valid state
+ */
+#define HV_FAST_VINTR_GET_VALID         0xa9
+
+/* vintr_set_valid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_VALID
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        valid state
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_VALID         0xaa
+
+/* vintr_get_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_STATE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        state
+ */
+#define HV_FAST_VINTR_GET_STATE         0xab
+
+/* vintr_set_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_STATE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        state
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_STATE         0xac
+
+/* vintr_get_target()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_TARGET
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        cpuid
+ */
+#define HV_FAST_VINTR_GET_TARGET        0xad
+
+/* vintr_set_target()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_TARGET
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        cpuid
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_TARGET        0xae
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long *cookie);
+extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long cookie);
+extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long *valid);
+extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long valid);
+extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long *state);
+extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long state);
+extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long *cpuid);
+extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long cpuid);
+#endif
+
+/* PCI IO services.
+ *
+ * See the terminology descriptions in the device interrupt services
+ * section above as those apply here too.  Here are terminology
+ * definitions specific to these PCI IO services:
+ *
+ *      tsbnum          TSB number.  Indentifies which io-tsb is used.
+ *                      For this version of the specification, tsbnum
+ *                      must be zero.
+ *
+ *      tsbindex        TSB index.  Identifies which entry in the TSB
+ *                      is used.  The first entry is zero.
+ *
+ *      tsbid           A 64-bit aligned data structure which contains
+ *                      a tsbnum and a tsbindex.  Bits 63:32 contain the
+ *                      tsbnum and bits 31:00 contain the tsbindex.
+ *
+ *                      Use the HV_PCI_TSBID() macro to construct such
+ *                      values.
+ *
+ *      io_attributes   IO attributes for IOMMU mappings.  One of more
+ *                      of the attritbute bits are stores in a 64-bit
+ *                      value.  The values are defined below.
+ *
+ *      r_addr          64-bit real address
+ *
+ *      pci_device      PCI device address.  A PCI device address identifies
+ *                      a specific device on a specific PCI bus segment.
+ *                      A PCI device address ia a 32-bit unsigned integer
+ *                      with the following format:
+ *
+ *                              00000000.bbbbbbbb.dddddfff.00000000
+ *
+ *                      Use the HV_PCI_DEVICE_BUILD() macro to construct
+ *                      such values.
+ *
+ *      pci_config_offset
+ *                      PCI configureation space offset.  For conventional
+ *                      PCI a value between 0 and 255.  For extended
+ *                      configuration space, a value between 0 and 4095.
+ *
+ *                      Note: For PCI configuration space accesses, the offset
+ *                            must be aligned to the access size.
+ *
+ *      error_flag      A return value which specifies if the action succeeded
+ *                      or failed.  0 means no error, non-0 means some error
+ *                      occurred while performing the service.
+ *
+ *      io_sync_direction
+ *                      Direction definition for pci_dma_sync(), defined
+ *                      below in HV_PCI_SYNC_*.
+ *
+ *      io_page_list    A list of io_page_addresses, an io_page_address is
+ *                      a real address.
+ *
+ *      io_page_list_p  A pointer to an io_page_list.
+ *
+ *      "size based byte swap" - Some functions do size based byte swapping
+ *                               which allows sw to access pointers and
+ *                               counters in native form when the processor
+ *                               operates in a different endianness than the
+ *                               IO bus.  Size-based byte swapping converts a
+ *                               multi-byte field between big-endian and
+ *                               little-endian format.
+ */
+
+#define HV_PCI_MAP_ATTR_READ            0x01
+#define HV_PCI_MAP_ATTR_WRITE           0x02
+
+#define HV_PCI_DEVICE_BUILD(b,d,f)      \
+        ((((b) & 0xff) << 16) | \
+         (((d) & 0x1f) << 11) | \
+         (((f) & 0x07) <<  8))
+
+#define HV_PCI_TSBID(__tsb_num, __tsb_index) \
+        ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
+
+#define HV_PCI_SYNC_FOR_DEVICE          0x01
+#define HV_PCI_SYNC_FOR_CPU             0x02
+
+/* pci_iommu_map()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_IOMMU_MAP
+ * ARG0:        devhandle
+ * ARG1:        tsbid
+ * ARG2:        #ttes
+ * ARG3:        io_attributes
+ * ARG4:        io_page_list_p
+ * RET0:        status
+ * RET1:        #ttes mapped
+ * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex/io_attributes
+ *              EBADALIGN       Improperly aligned real address
+ *              ENORADDR        Invalid real address
+ *
+ * Create IOMMU mappings in the sun4v device defined by the given
+ * devhandle.  The mappings are created in the TSB defined by the
+ * tsbnum component of the given tsbid.  The first mapping is created
+ * in the TSB i ndex defined by the tsbindex component of the given tsbid.
+ * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
+ * the second at tsbnum, tsbindex + 1, etc.
+ *
+ * All mappings are created with the attributes defined by the io_attributes
+ * argument.  The page mapping addresses are described in the io_page_list
+ * defined by the given io_page_list_p, which is a pointer to the io_page_list.
+ * The first entry in the io_page_list is the address for the first iotte, the
+ * 2nd for the 2nd iotte, and so on.
+ *
+ * Each io_page_address in the io_page_list must be appropriately aligned.
+ * #ttes must be greater than zero.  For this version of the spec, the tsbnum
+ * component of the given tsbid must be zero.
+ *
+ * Returns the actual number of mappings creates, which may be less than
+ * or equal to the argument #ttes.  If the function returns a value which
+ * is less than the #ttes, the caller may continus to call the function with
+ * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
+ * mapped.
+ *
+ * Note: This function does not imply an iotte cache flush.  The guest must
+ *       demap an entry before re-mapping it.
+ */
+#define HV_FAST_PCI_IOMMU_MAP           0xb0
+
+/* pci_iommu_demap()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_IOMMU_DEMAP
+ * ARG0:        devhandle
+ * ARG1:        tsbid
+ * ARG2:        #ttes
+ * RET0:        status
+ * RET1:        #ttes demapped
+ * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex
+ *
+ * Demap and flush IOMMU mappings in the device defined by the given
+ * devhandle.  Demaps up to #ttes entries in the TSB defined by the tsbnum
+ * component of the given tsbid, starting at the TSB index defined by the
+ * tsbindex component of the given tsbid.
+ *
+ * For this version of the spec, the tsbnum of the given tsbid must be zero.
+ * #ttes must be greater than zero.
+ *
+ * Returns the actual number of ttes demapped, which may be less than or equal
+ * to the argument #ttes.  If #ttes demapped is less than #ttes, the caller
+ * may continue to call this function with updated tsbid and #ttes arguments
+ * until all pages are demapped.
+ *
+ * Note: Entries do not have to be mapped to be demapped.  A demap of an
+ *       unmapped page will flush the entry from the tte cache.
+ */
+#define HV_FAST_PCI_IOMMU_DEMAP         0xb1
+
+/* pci_iommu_getmap()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_IOMMU_GETMAP
+ * ARG0:        devhandle
+ * ARG1:        tsbid
+ * RET0:        status
+ * RET1:        io_attributes
+ * RET2:        real address
+ * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex
+ *              ENOMAP          Mapping is not valid, no translation exists
+ *
+ * Read and return the mapping in the device described by the given devhandle
+ * and tsbid.  If successful, the io_attributes shall be returned in RET1
+ * and the page address of the mapping shall be returned in RET2.
+ *
+ * For this version of the spec, the tsbnum component of the given tsbid
+ * must be zero.
+ */
+#define HV_FAST_PCI_IOMMU_GETMAP        0xb2
+
+/* pci_iommu_getbypass()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_IOMMU_GETBYPASS
+ * ARG0:        devhandle
+ * ARG1:        real address
+ * ARG2:        io_attributes
+ * RET0:        status
+ * RET1:        io_addr
+ * ERRORS:      EINVAL          Invalid devhandle/io_attributes
+ *              ENORADDR        Invalid real address
+ *              ENOTSUPPORTED   Function not supported in this implementation.
+ *
+ * Create a "special" mapping in the device described by the given devhandle,
+ * for the given real address and attributes.  Return the IO address in RET1
+ * if successful.
+ */
+#define HV_FAST_PCI_IOMMU_GETBYPASS     0xb3
+
+/* pci_config_get()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_CONFIG_GET
+ * ARG0:        devhandle
+ * ARG1:        pci_device
+ * ARG2:        pci_config_offset
+ * ARG3:        size
+ * RET0:        status
+ * RET1:        error_flag
+ * RET2:        data
+ * ERRORS:      EINVAL          Invalid devhandle/pci_device/offset/size
+ *              EBADALIGN       pci_config_offset not size aligned
+ *              ENOACCESS       Access to this offset is not permitted
+ *
+ * Read PCI configuration space for the adapter described by the given
+ * devhandle.  Read size (1, 2, or 4) bytes of data from the given
+ * pci_device, at pci_config_offset from the beginning of the device's
+ * configuration space.  If there was no error, RET1 is set to zero and
+ * RET2 is set to the data read.  Insignificant bits in RET2 are not
+ * guarenteed to have any specific value and therefore must be ignored.
+ *
+ * The data returned in RET2 is size based byte swapped.
+ *
+ * If an error occurs during the read, set RET1 to a non-zero value.  The
+ * given pci_config_offset must be 'size' aligned.
+ */
+#define HV_FAST_PCI_CONFIG_GET          0xb4
+
+/* pci_config_put()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_CONFIG_PUT
+ * ARG0:        devhandle
+ * ARG1:        pci_device
+ * ARG2:        pci_config_offset
+ * ARG3:        size
+ * ARG4:        data
+ * RET0:        status
+ * RET1:        error_flag
+ * ERRORS:      EINVAL          Invalid devhandle/pci_device/offset/size
+ *              EBADALIGN       pci_config_offset not size aligned
+ *              ENOACCESS       Access to this offset is not permitted
+ *
+ * Write PCI configuration space for the adapter described by the given
+ * devhandle.  Write size (1, 2, or 4) bytes of data in a single operation,
+ * at pci_config_offset from the beginning of the device's configuration
+ * space.  The data argument contains the data to be written to configuration
+ * space.  Prior to writing, the data is size based byte swapped.
+ *
+ * If an error occurs during the write access, do not generate an error
+ * report, do set RET1 to a non-zero value.  Otherwise RET1 is zero.
+ * The given pci_config_offset must be 'size' aligned.
+ *
+ * This function is permitted to read from offset zero in the configuration
+ * space described by the given pci_device if necessary to ensure that the
+ * write access to config space completes.
+ */
+#define HV_FAST_PCI_CONFIG_PUT          0xb5
+
+/* pci_peek()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_PEEK
+ * ARG0:        devhandle
+ * ARG1:        real address
+ * ARG2:        size
+ * RET0:        status
+ * RET1:        error_flag
+ * RET2:        data
+ * ERRORS:      EINVAL          Invalid devhandle or size
+ *              EBADALIGN       Improperly aligned real address
+ *              ENORADDR        Bad real address
+ *              ENOACCESS       Guest access prohibited
+ *
+ * Attempt to read the IO address given by the given devhandle, real address,
+ * and size.  Size must be 1, 2, 4, or 8.  The read is performed as a single
+ * access operation using the given size.  If an error occurs when reading
+ * from the given location, do not generate an error report, but return a
+ * non-zero value in RET1.  If the read was successful, return zero in RET1
+ * and return the actual data read in RET2.  The data returned is size based
+ * byte swapped.
+ *
+ * Non-significant bits in RET2 are not guarenteed to have any specific value
+ * and therefore must be ignored.  If RET1 is returned as non-zero, the data
+ * value is not guarenteed to have any specific value and should be ignored.
+ *
+ * The caller must have permission to read from the given devhandle, real
+ * address, which must be an IO address.  The argument real address must be a
+ * size aligned address.
+ *
+ * The hypervisor implementation of this function must block access to any
+ * IO address that the guest does not have explicit permission to access.
+ */
+#define HV_FAST_PCI_PEEK                0xb6
+
+/* pci_poke()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_POKE
+ * ARG0:        devhandle
+ * ARG1:        real address
+ * ARG2:        size
+ * ARG3:        data
+ * ARG4:        pci_device
+ * RET0:        status
+ * RET1:        error_flag
+ * ERRORS:      EINVAL          Invalid devhandle, size, or pci_device
+ *              EBADALIGN       Improperly aligned real address
+ *              ENORADDR        Bad real address
+ *              ENOACCESS       Guest access prohibited
+ *              ENOTSUPPORTED   Function is not supported by implementation
+ *
+ * Attempt to write data to the IO address given by the given devhandle,
+ * real address, and size.  Size must be 1, 2, 4, or 8.  The write is
+ * performed as a single access operation using the given size. Prior to
+ * writing the data is size based swapped.
+ *
+ * If an error occurs when writing to the given location, do not generate an
+ * error report, but return a non-zero value in RET1.  If the write was
+ * successful, return zero in RET1.
+ *
+ * pci_device describes the configuration address of the device being
+ * written to.  The implementation may safely read from offset 0 with
+ * the configuration space of the device described by devhandle and
+ * pci_device in order to guarantee that the write portion of the operation
+ * completes
+ *
+ * Any error that occurs due to the read shall be reported using the normal
+ * error reporting mechanisms .. the read error is not suppressed.
+ *
+ * The caller must have permission to write to the given devhandle, real
+ * address, which must be an IO address.  The argument real address must be a
+ * size aligned address.  The caller must have permission to read from
+ * the given devhandle, pci_device cofiguration space offset 0.
+ *
+ * The hypervisor implementation of this function must block access to any
+ * IO address that the guest does not have explicit permission to access.
+ */
+#define HV_FAST_PCI_POKE                0xb7
+
+/* pci_dma_sync()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_DMA_SYNC
+ * ARG0:        devhandle
+ * ARG1:        real address
+ * ARG2:        size
+ * ARG3:        io_sync_direction
+ * RET0:        status
+ * RET1:        #synced
+ * ERRORS:      EINVAL          Invalid devhandle or io_sync_direction
+ *              ENORADDR        Bad real address
+ *
+ * Synchronize a memory region described by the given real address and size,
+ * for the device defined by the given devhandle using the direction(s)
+ * defined by the given io_sync_direction.  The argument size is the size of
+ * the memory region in bytes.
+ *
+ * Return the actual number of bytes synchronized in the return value #synced,
+ * which may be less than or equal to the argument size.  If the return
+ * value #synced is less than size, the caller must continue to call this
+ * function with updated real address and size arguments until the entire
+ * memory region is synchronized.
+ */
+#define HV_FAST_PCI_DMA_SYNC            0xb8
+
+/* PCI MSI services.  */
+
+#define HV_MSITYPE_MSI32                0x00
+#define HV_MSITYPE_MSI64                0x01
+
+#define HV_MSIQSTATE_IDLE               0x00
+#define HV_MSIQSTATE_ERROR              0x01
+
+#define HV_MSIQ_INVALID                 0x00
+#define HV_MSIQ_VALID                   0x01
+
+#define HV_MSISTATE_IDLE                0x00
+#define HV_MSISTATE_DELIVERED           0x01
+
+#define HV_MSIVALID_INVALID             0x00
+#define HV_MSIVALID_VALID               0x01
+
+#define HV_PCIE_MSGTYPE_PME_MSG         0x18
+#define HV_PCIE_MSGTYPE_PME_ACK_MSG     0x1b
+#define HV_PCIE_MSGTYPE_CORR_MSG        0x30
+#define HV_PCIE_MSGTYPE_NONFATAL_MSG    0x31
+#define HV_PCIE_MSGTYPE_FATAL_MSG       0x33
+
+#define HV_MSG_INVALID                  0x00
+#define HV_MSG_VALID                    0x01
+
+/* pci_msiq_conf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_CONF
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * ARG2:        real address
+ * ARG3:        number of entries
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle, msiqid or nentries
+ *              EBADALIGN       Improperly aligned real address
+ *              ENORADDR        Bad real address
+ *
+ * Configure the MSI queue given by the devhandle and msiqid arguments,
+ * and to be placed at the given real address and be of the given
+ * number of entries.  The real address must be aligned exactly to match
+ * the queue size.  Each queue entry is 64-bytes long, so f.e. a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary.  The MSI-EQ
+ * Head and Tail are initialized so that the MSI-EQ is 'empty'.
+ *
+ * Implementation Note: Certain implementations have fixed sized queues.  In
+ *                      that case, number of entries must contain the correct
+ *                      value.
+ */
+#define HV_FAST_PCI_MSIQ_CONF           0xc0
+
+/* pci_msiq_info()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_INFO
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * RET0:        status
+ * RET1:        real address
+ * RET2:        number of entries
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid
+ *
+ * Return the configuration information for the MSI queue described
+ * by the given devhandle and msiqid.  The base address of the queue
+ * is returned in ARG1 and the number of entries is returned in ARG2.
+ * If the queue is unconfigured, the real address is undefined and the
+ * number of entries will be returned as zero.
+ */
+#define HV_FAST_PCI_MSIQ_INFO           0xc1
+
+/* pci_msiq_getvalid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_GETVALID
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * RET0:        status
+ * RET1:        msiqvalid       (HV_MSIQ_VALID or HV_MSIQ_INVALID)
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid
+ *
+ * Get the valid state of the MSI-EQ described by the given devhandle and
+ * msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETVALID       0xc2
+
+/* pci_msiq_setvalid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_SETVALID
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * ARG2:        msiqvalid       (HV_MSIQ_VALID or HV_MSIQ_INVALID)
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqvalid
+ *                              value or MSI EQ is uninitialized
+ *
+ * Set the valid state of the MSI-EQ described by the given devhandle and
+ * msiqid to the given msiqvalid.
+ */
+#define HV_FAST_PCI_MSIQ_SETVALID       0xc3
+
+/* pci_msiq_getstate()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_GETSTATE
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * RET0:        status
+ * RET1:        msiqstate       (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid
+ *
+ * Get the state of the MSI-EQ described by the given devhandle and
+ * msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETSTATE       0xc4
+
+/* pci_msiq_getvalid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_GETVALID
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * ARG2:        msiqstate       (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqstate
+ *                              value or MSI EQ is uninitialized
+ *
+ * Set the state of the MSI-EQ described by the given devhandle and
+ * msiqid to the given msiqvalid.
+ */
+#define HV_FAST_PCI_MSIQ_SETSTATE       0xc5
+
+/* pci_msiq_gethead()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_GETHEAD
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * RET0:        status
+ * RET1:        msiqhead
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid
+ *
+ * Get the current MSI EQ queue head for the MSI-EQ described by the
+ * given devhandle and msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETHEAD        0xc6
+
+/* pci_msiq_sethead()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_SETHEAD
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * ARG2:        msiqhead
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqhead,
+ *                              or MSI EQ is uninitialized
+ *
+ * Set the current MSI EQ queue head for the MSI-EQ described by the
+ * given devhandle and msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_SETHEAD        0xc7
+
+/* pci_msiq_gettail()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSIQ_GETTAIL
+ * ARG0:        devhandle
+ * ARG1:        msiqid
+ * RET0:        status
+ * RET1:        msiqtail
+ * ERRORS:      EINVAL          Invalid devhandle or msiqid
+ *
+ * Get the current MSI EQ queue tail for the MSI-EQ described by the
+ * given devhandle and msiqid.
+ */
+#define HV_FAST_PCI_MSIQ_GETTAIL        0xc8
+
+/* pci_msi_getvalid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSI_GETVALID
+ * ARG0:        devhandle
+ * ARG1:        msinum
+ * RET0:        status
+ * RET1:        msivalidstate
+ * ERRORS:      EINVAL          Invalid devhandle or msinum
+ *
+ * Get the current valid/enabled state for the MSI defined by the
+ * given devhandle and msinum.
+ */
+#define HV_FAST_PCI_MSI_GETVALID        0xc9
+
+/* pci_msi_setvalid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSI_SETVALID
+ * ARG0:        devhandle
+ * ARG1:        msinum
+ * ARG2:        msivalidstate
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle or msinum or msivalidstate
+ *
+ * Set the current valid/enabled state for the MSI defined by the
+ * given devhandle and msinum.
+ */
+#define HV_FAST_PCI_MSI_SETVALID        0xca
+
+/* pci_msi_getmsiq()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSI_GETMSIQ
+ * ARG0:        devhandle
+ * ARG1:        msinum
+ * RET0:        status
+ * RET1:        msiqid
+ * ERRORS:      EINVAL          Invalid devhandle or msinum or MSI is unbound
+ *
+ * Get the MSI EQ that the MSI defined by the given devhandle and
+ * msinum is bound to.
+ */
+#define HV_FAST_PCI_MSI_GETMSIQ         0xcb
+
+/* pci_msi_setmsiq()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSI_SETMSIQ
+ * ARG0:        devhandle
+ * ARG1:        msinum
+ * ARG2:        msitype
+ * ARG3:        msiqid
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle or msinum or msiqid
+ *
+ * Set the MSI EQ that the MSI defined by the given devhandle and
+ * msinum is bound to.
+ */
+#define HV_FAST_PCI_MSI_SETMSIQ         0xcc
+
+/* pci_msi_getstate()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSI_GETSTATE
+ * ARG0:        devhandle
+ * ARG1:        msinum
+ * RET0:        status
+ * RET1:        msistate
+ * ERRORS:      EINVAL          Invalid devhandle or msinum
+ *
+ * Get the state of the MSI defined by the given devhandle and msinum.
+ * If not initialized, return HV_MSISTATE_IDLE.
+ */
+#define HV_FAST_PCI_MSI_GETSTATE        0xcd
+
+/* pci_msi_setstate()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSI_SETSTATE
+ * ARG0:        devhandle
+ * ARG1:        msinum
+ * ARG2:        msistate
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle or msinum or msistate
+ *
+ * Set the state of the MSI defined by the given devhandle and msinum.
+ */
+#define HV_FAST_PCI_MSI_SETSTATE        0xce
+
+/* pci_msg_getmsiq()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSG_GETMSIQ
+ * ARG0:        devhandle
+ * ARG1:        msgtype
+ * RET0:        status
+ * RET1:        msiqid
+ * ERRORS:      EINVAL          Invalid devhandle or msgtype
+ *
+ * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_GETMSIQ         0xd0
+
+/* pci_msg_setmsiq()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSG_SETMSIQ
+ * ARG0:        devhandle
+ * ARG1:        msgtype
+ * ARG2:        msiqid
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle, msgtype, or msiqid
+ *
+ * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_SETMSIQ         0xd1
+
+/* pci_msg_getvalid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSG_GETVALID
+ * ARG0:        devhandle
+ * ARG1:        msgtype
+ * RET0:        status
+ * RET1:        msgvalidstate
+ * ERRORS:      EINVAL          Invalid devhandle or msgtype
+ *
+ * Get the valid/enabled state of the MSG defined by the given
+ * devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_GETVALID        0xd2
+
+/* pci_msg_setvalid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_PCI_MSG_SETVALID
+ * ARG0:        devhandle
+ * ARG1:        msgtype
+ * ARG2:        msgvalidstate
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid devhandle or msgtype or msgvalidstate
+ *
+ * Set the valid/enabled state of the MSG defined by the given
+ * devhandle and msgtype.
+ */
+#define HV_FAST_PCI_MSG_SETVALID        0xd3
+
+/* Logical Domain Channel services.  */
+
+#define LDC_CHANNEL_DOWN                0
+#define LDC_CHANNEL_UP                  1
+#define LDC_CHANNEL_RESETTING           2
+
+/* ldc_tx_qconf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_QCONF
+ * ARG0:        channel ID
+ * ARG1:        real address base of queue
+ * ARG2:        num entries in queue
+ * RET0:        status
+ *
+ * Configure transmit queue for the LDC endpoint specified by the
+ * given channel ID, to be placed at the given real address, and
+ * be of the given num entries.  Num entries must be a power of two.
+ * The real address base of the queue must be aligned on the queue
+ * size.  Each queue entry is 64-bytes, so for example, a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary.
+ *
+ * Upon configuration of a valid transmit queue the head and tail
+ * pointers are set to a hypervisor specific identical value indicating
+ * that the queue initially is empty.
+ *
+ * The endpoint's transmit queue is un-configured if num entries is zero.
+ *
+ * The maximum number of entries for each queue for a specific cpu may be
+ * determined from the machine description.  A transmit queue may be
+ * specified even in the event that the LDC is down (peer endpoint has no
+ * receive queue specified).  Transmission will begin as soon as the peer
+ * endpoint defines a receive queue.
+ *
+ * It is recommended that a guest wait for a transmit queue to empty prior
+ * to reconfiguring it, or un-configuring it.  Re or un-configuring of a
+ * non-empty transmit queue behaves exactly as defined above, however it
+ * is undefined as to how many of the pending entries in the original queue
+ * will be delivered prior to the re-configuration taking effect.
+ * Furthermore, as the queue configuration causes a reset of the head and
+ * tail pointers there is no way for a guest to determine how many entries
+ * have been sent after the configuration operation.
+ */
+#define HV_FAST_LDC_TX_QCONF            0xe0
+
+/* ldc_tx_qinfo()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_QINFO
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        real address base of queue
+ * RET2:        num entries in queue
+ *
+ * Return the configuration info for the transmit queue of LDC endpoint
+ * defined by the given channel ID.  The real address is the currently
+ * defined real address base of the defined queue, and num entries is the
+ * size of the queue in terms of number of entries.
+ *
+ * If the specified channel ID is a valid endpoint number, but no transmit
+ * queue has been defined this service will return success, but with num
+ * entries set to zero and the real address will have an undefined value.
+ */
+#define HV_FAST_LDC_TX_QINFO            0xe1
+
+/* ldc_tx_get_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_GET_STATE
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        head offset
+ * RET2:        tail offset
+ * RET3:        channel state
+ *
+ * Return the transmit state, and the head and tail queue pointers, for
+ * the transmit queue of the LDC endpoint defined by the given channel ID.
+ * The head and tail values are the byte offset of the head and tail
+ * positions of the transmit queue for the specified endpoint.
+ */
+#define HV_FAST_LDC_TX_GET_STATE        0xe2
+
+/* ldc_tx_set_qtail()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_SET_QTAIL
+ * ARG0:        channel ID
+ * ARG1:        tail offset
+ * RET0:        status
+ *
+ * Update the tail pointer for the transmit queue associated with the LDC
+ * endpoint defined by the given channel ID.  The tail offset specified
+ * must be aligned on a 64 byte boundary, and calculated so as to increase
+ * the number of pending entries on the transmit queue.  Any attempt to
+ * decrease the number of pending transmit queue entires is considered
+ * an invalid tail offset and will result in an EINVAL error.
+ *
+ * Since the tail of the transmit queue may not be moved backwards, the
+ * transmit queue may be flushed by configuring a new transmit queue,
+ * whereupon the hypervisor will configure the initial transmit head and
+ * tail pointers to be equal.
+ */
+#define HV_FAST_LDC_TX_SET_QTAIL        0xe3
+
+/* ldc_rx_qconf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_QCONF
+ * ARG0:        channel ID
+ * ARG1:        real address base of queue
+ * ARG2:        num entries in queue
+ * RET0:        status
+ *
+ * Configure receive queue for the LDC endpoint specified by the
+ * given channel ID, to be placed at the given real address, and
+ * be of the given num entries.  Num entries must be a power of two.
+ * The real address base of the queue must be aligned on the queue
+ * size.  Each queue entry is 64-bytes, so for example, a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary.
+ *
+ * The endpoint's transmit queue is un-configured if num entries is zero.
+ *
+ * If a valid receive queue is specified for a local endpoint the LDC is
+ * in the up state for the purpose of transmission to this endpoint.
+ *
+ * The maximum number of entries for each queue for a specific cpu may be
+ * determined from the machine description.
+ *
+ * As receive queue configuration causes a reset of the queue's head and
+ * tail pointers there is no way for a gues to determine how many entries
+ * have been received between a preceeding ldc_get_rx_state() API call
+ * and the completion of the configuration operation.  It should be noted
+ * that datagram delivery is not guarenteed via domain channels anyway,
+ * and therefore any higher protocol should be resilient to datagram
+ * loss if necessary.  However, to overcome this specific race potential
+ * it is recommended, for example, that a higher level protocol be employed
+ * to ensure either retransmission, or ensure that no datagrams are pending
+ * on the peer endpoint's transmit queue prior to the configuration process.
+ */
+#define HV_FAST_LDC_RX_QCONF            0xe4
+
+/* ldc_rx_qinfo()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_QINFO
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        real address base of queue
+ * RET2:        num entries in queue
+ *
+ * Return the configuration info for the receive queue of LDC endpoint
+ * defined by the given channel ID.  The real address is the currently
+ * defined real address base of the defined queue, and num entries is the
+ * size of the queue in terms of number of entries.
+ *
+ * If the specified channel ID is a valid endpoint number, but no receive
+ * queue has been defined this service will return success, but with num
+ * entries set to zero and the real address will have an undefined value.
+ */
+#define HV_FAST_LDC_RX_QINFO            0xe5
+
+/* ldc_rx_get_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_GET_STATE
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        head offset
+ * RET2:        tail offset
+ * RET3:        channel state
+ *
+ * Return the receive state, and the head and tail queue pointers, for
+ * the receive queue of the LDC endpoint defined by the given channel ID.
+ * The head and tail values are the byte offset of the head and tail
+ * positions of the receive queue for the specified endpoint.
+ */
+#define HV_FAST_LDC_RX_GET_STATE        0xe6
+
+/* ldc_rx_set_qhead()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_SET_QHEAD
+ * ARG0:        channel ID
+ * ARG1:        head offset
+ * RET0:        status
+ *
+ * Update the head pointer for the receive queue associated with the LDC
+ * endpoint defined by the given channel ID.  The head offset specified
+ * must be aligned on a 64 byte boundary, and calculated so as to decrease
+ * the number of pending entries on the receive queue.  Any attempt to
+ * increase the number of pending receive queue entires is considered
+ * an invalid head offset and will result in an EINVAL error.
+ *
+ * The receive queue may be flushed by setting the head offset equal
+ * to the current tail offset.
+ */
+#define HV_FAST_LDC_RX_SET_QHEAD        0xe7
+
+/* LDC Map Table Entry.  Each slot is defined by a translation table
+ * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
+ * hypervisor invalidation cookie.
+ */
+#define LDC_MTE_PADDR   0x0fffffffffffe000 /* pa[55:13]          */
+#define LDC_MTE_COPY_W  0x0000000000000400 /* copy write access  */
+#define LDC_MTE_COPY_R  0x0000000000000200 /* copy read access   */
+#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
+#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access  */
+#define LDC_MTE_EXEC    0x0000000000000040 /* execute            */
+#define LDC_MTE_WRITE   0x0000000000000020 /* read               */
+#define LDC_MTE_READ    0x0000000000000010 /* write              */
+#define LDC_MTE_SZALL   0x000000000000000f /* page size bits     */
+#define LDC_MTE_SZ16GB  0x0000000000000007 /* 16GB page          */
+#define LDC_MTE_SZ2GB   0x0000000000000006 /* 2GB page           */
+#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page         */
+#define LDC_MTE_SZ32MB  0x0000000000000004 /* 32MB page          */
+#define LDC_MTE_SZ4MB   0x0000000000000003 /* 4MB page           */
+#define LDC_MTE_SZ512K  0x0000000000000002 /* 512K page          */
+#define LDC_MTE_SZ64K   0x0000000000000001 /* 64K page           */
+#define LDC_MTE_SZ8K    0x0000000000000000 /* 8K page            */
+
+#ifndef __ASSEMBLY__
+struct ldc_mtable_entry {
+        unsigned long   mte;
+        unsigned long   cookie;
+};
+#endif
+
+/* ldc_set_map_table()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_SET_MAP_TABLE
+ * ARG0:        channel ID
+ * ARG1:        table real address
+ * ARG2:        num entries
+ * RET0:        status
+ *
+ * Register the MTE table at the given table real address, with the
+ * specified num entries, for the LDC indicated by the given channel
+ * ID.
+ */
+#define HV_FAST_LDC_SET_MAP_TABLE       0xea
+
+/* ldc_get_map_table()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_GET_MAP_TABLE
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        table real address
+ * RET2:        num entries
+ *
+ * Return the configuration of the current mapping table registered
+ * for the given channel ID.
+ */
+#define HV_FAST_LDC_GET_MAP_TABLE       0xeb
+
+#define LDC_COPY_IN     0
+#define LDC_COPY_OUT    1
+
+/* ldc_copy()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_COPY
+ * ARG0:        channel ID
+ * ARG1:        LDC_COPY_* direction code
+ * ARG2:        target real address
+ * ARG3:        local real address
+ * ARG4:        length in bytes
+ * RET0:        status
+ * RET1:        actual length in bytes
+ */
+#define HV_FAST_LDC_COPY                0xec
+
+#define LDC_MEM_READ    1
+#define LDC_MEM_WRITE   2
+#define LDC_MEM_EXEC    4
+
+/* ldc_mapin()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_MAPIN
+ * ARG0:        channel ID
+ * ARG1:        cookie
+ * RET0:        status
+ * RET1:        real address
+ * RET2:        LDC_MEM_* permissions
+ */
+#define HV_FAST_LDC_MAPIN               0xed
+
+/* ldc_unmap()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_UNMAP
+ * ARG0:        real address
+ * RET0:        status
+ */
+#define HV_FAST_LDC_UNMAP               0xee
+
+/* ldc_revoke()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_REVOKE
+ * ARG0:        channel ID
+ * ARG1:        cookie
+ * ARG2:        ldc_mtable_entry cookie
+ * RET0:        status
+ */
+#define HV_FAST_LDC_REVOKE              0xef
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
+                                        unsigned long ra,
+                                        unsigned long num_entries);
+extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
+                                        unsigned long *ra,
+                                        unsigned long *num_entries);
+extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
+                                            unsigned long *head_off,
+                                            unsigned long *tail_off,
+                                            unsigned long *chan_state);
+extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
+                                            unsigned long tail_off);
+extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
+                                        unsigned long ra,
+                                        unsigned long num_entries);
+extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
+                                        unsigned long *ra,
+                                        unsigned long *num_entries);
+extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
+                                            unsigned long *head_off,
+                                            unsigned long *tail_off,
+                                            unsigned long *chan_state);
+extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
+                                            unsigned long head_off);
+extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
+                                             unsigned long ra,
+                                             unsigned long num_entries);
+extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
+                                             unsigned long *ra,
+                                             unsigned long *num_entries);
+extern unsigned long sun4v_ldc_copy(unsigned long channel,
+                                    unsigned long dir_code,
+                                    unsigned long tgt_raddr,
+                                    unsigned long lcl_raddr,
+                                    unsigned long len,
+                                    unsigned long *actual_len);
+extern unsigned long sun4v_ldc_mapin(unsigned long channel,
+                                     unsigned long cookie,
+                                     unsigned long *ra,
+                                     unsigned long *perm);
+extern unsigned long sun4v_ldc_unmap(unsigned long ra);
+extern unsigned long sun4v_ldc_revoke(unsigned long channel,
+                                      unsigned long cookie,
+                                      unsigned long mte_cookie);
+#endif
+
+/* Performance counter services.  */
+
+#define HV_PERF_JBUS_PERF_CTRL_REG      0x00
+#define HV_PERF_JBUS_PERF_CNT_REG       0x01
+#define HV_PERF_DRAM_PERF_CTRL_REG_0    0x02
+#define HV_PERF_DRAM_PERF_CNT_REG_0     0x03
+#define HV_PERF_DRAM_PERF_CTRL_REG_1    0x04
+#define HV_PERF_DRAM_PERF_CNT_REG_1     0x05
+#define HV_PERF_DRAM_PERF_CTRL_REG_2    0x06
+#define HV_PERF_DRAM_PERF_CNT_REG_2     0x07
+#define HV_PERF_DRAM_PERF_CTRL_REG_3    0x08
+#define HV_PERF_DRAM_PERF_CNT_REG_3     0x09
+
+/* get_perfreg()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_GET_PERFREG
+ * ARG0:        performance reg number
+ * RET0:        status
+ * RET1:        performance reg value
+ * ERRORS:      EINVAL          Invalid performance register number
+ *              ENOACCESS       No access allowed to performance counters
+ *
+ * Read the value of the given DRAM/JBUS performance counter/control register.
+ */
+#define HV_FAST_GET_PERFREG             0x100
+
+/* set_perfreg()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_SET_PERFREG
+ * ARG0:        performance reg number
+ * ARG1:        performance reg value
+ * RET0:        status
+ * ERRORS:      EINVAL          Invalid performance register number
+ *              ENOACCESS       No access allowed to performance counters
+ *
+ * Write the given performance reg value to the given DRAM/JBUS
+ * performance counter/control register.
+ */
+#define HV_FAST_SET_PERFREG             0x101
+
+/* MMU statistics services.
+ *
+ * The hypervisor maintains MMU statistics and privileged code provides
+ * a buffer where these statistics can be collected.  It is continually
+ * updated once configured.  The layout is as follows:
+ */
+#ifndef __ASSEMBLY__
+struct hv_mmu_statistics {
+        unsigned long immu_tsb_hits_ctx0_8k_tte;
+        unsigned long immu_tsb_ticks_ctx0_8k_tte;
+        unsigned long immu_tsb_hits_ctx0_64k_tte;
+        unsigned long immu_tsb_ticks_ctx0_64k_tte;
+        unsigned long __reserved1[2];
+        unsigned long immu_tsb_hits_ctx0_4mb_tte;
+        unsigned long immu_tsb_ticks_ctx0_4mb_tte;
+        unsigned long __reserved2[2];
+        unsigned long immu_tsb_hits_ctx0_256mb_tte;
+        unsigned long immu_tsb_ticks_ctx0_256mb_tte;
+        unsigned long __reserved3[4];
+        unsigned long immu_tsb_hits_ctxnon0_8k_tte;
+        unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
+        unsigned long immu_tsb_hits_ctxnon0_64k_tte;
+        unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
+        unsigned long __reserved4[2];
+        unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
+        unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
+        unsigned long __reserved5[2];
+        unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
+        unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
+        unsigned long __reserved6[4];
+        unsigned long dmmu_tsb_hits_ctx0_8k_tte;
+        unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
+        unsigned long dmmu_tsb_hits_ctx0_64k_tte;
+        unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
+        unsigned long __reserved7[2];
+        unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
+        unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
+        unsigned long __reserved8[2];
+        unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
+        unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
+        unsigned long __reserved9[4];
+        unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
+        unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
+        unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
+        unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
+        unsigned long __reserved10[2];
+        unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
+        unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
+        unsigned long __reserved11[2];
+        unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
+        unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
+        unsigned long __reserved12[4];
+};
+#endif
+
+/* mmustat_conf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMUSTAT_CONF
+ * ARG0:        real address
+ * RET0:        status
+ * RET1:        real address
+ * ERRORS:      ENORADDR        Invalid real address
+ *              EBADALIGN       Real address not aligned on 64-byte boundary
+ *              EBADTRAP        API not supported on this processor
+ *
+ * Enable MMU statistic gathering using the buffer at the given real
+ * address on the current virtual CPU.  The new buffer real address
+ * is given in ARG1, and the previously specified buffer real address
+ * is returned in RET1, or is returned as zero for the first invocation.
+ *
+ * If the passed in real address argument is zero, this will disable
+ * MMU statistic collection on the current virtual CPU.  If an error is
+ * returned then no statistics are collected.
+ *
+ * The buffer contents should be initialized to all zeros before being
+ * given to the hypervisor or else the statistics will be meaningless.
+ */
+#define HV_FAST_MMUSTAT_CONF            0x102
+
+/* mmustat_info()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MMUSTAT_INFO
+ * RET0:        status
+ * RET1:        real address
+ * ERRORS:      EBADTRAP        API not supported on this processor
+ *
+ * Return the current state and real address of the currently configured
+ * MMU statistics buffer on the current virtual CPU.
+ */
+#define HV_FAST_MMUSTAT_INFO            0x103
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
+extern unsigned long sun4v_mmustat_info(unsigned long *ra);
+#endif
+
+/* NCS crypto services  */
+
+/* ncs_request() sub-function numbers */
+#define HV_NCS_QCONF                    0x01
+#define HV_NCS_QTAIL_UPDATE             0x02
+
+#ifndef __ASSEMBLY__
+struct hv_ncs_queue_entry {
+        /* MAU Control Register */
+        unsigned long   mau_control;
+#define MAU_CONTROL_INV_PARITY  0x0000000000002000
+#define MAU_CONTROL_STRAND      0x0000000000001800
+#define MAU_CONTROL_BUSY        0x0000000000000400
+#define MAU_CONTROL_INT         0x0000000000000200
+#define MAU_CONTROL_OP          0x00000000000001c0
+#define MAU_CONTROL_OP_SHIFT    6
+#define MAU_OP_LOAD_MA_MEMORY   0x0
+#define MAU_OP_STORE_MA_MEMORY  0x1
+#define MAU_OP_MODULAR_MULT     0x2
+#define MAU_OP_MODULAR_REDUCE   0x3
+#define MAU_OP_MODULAR_EXP_LOOP 0x4
+#define MAU_CONTROL_LEN         0x000000000000003f
+#define MAU_CONTROL_LEN_SHIFT   0
+
+        /* Real address of bytes to load or store bytes
+         * into/out-of the MAU.
+         */
+        unsigned long   mau_mpa;
+
+        /* Modular Arithmetic MA Offset Register.  */
+        unsigned long   mau_ma;
+
+        /* Modular Arithmetic N Prime Register.  */
+        unsigned long   mau_np;
+};
+
+struct hv_ncs_qconf_arg {
+        unsigned long   mid;      /* MAU ID, 1 per core on Niagara */
+        unsigned long   base;     /* Real address base of queue */
+        unsigned long   end;      /* Real address end of queue */
+        unsigned long   num_ents; /* Number of entries in queue */
+};
+
+struct hv_ncs_qtail_update_arg {
+        unsigned long   mid;      /* MAU ID, 1 per core on Niagara */
+        unsigned long   tail;     /* New tail index to use */
+        unsigned long   syncflag; /* only SYNCFLAG_SYNC is implemented */
+#define HV_NCS_SYNCFLAG_SYNC    0x00
+#define HV_NCS_SYNCFLAG_ASYNC   0x01
+};
+#endif
+
+/* ncs_request()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_NCS_REQUEST
+ * ARG0:        NCS sub-function
+ * ARG1:        sub-function argument real address
+ * ARG2:        size in bytes of sub-function argument
+ * RET0:        status
+ *
+ * The MAU chip of the Niagara processor is not directly accessible
+ * to privileged code, instead it is programmed indirectly via this
+ * hypervisor API.
+ *
+ * The interfaces defines a queue of MAU operations to perform.
+ * Privileged code registers a queue with the hypervisor by invoking
+ * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
+ * base, end, and number of entries of the queue.  Each queue entry
+ * contains a MAU register struct block.
+ *
+ * The privileged code then proceeds to add entries to the queue and
+ * then invoke the HV_NCS_QTAIL_UPDATE sub-function.  Since only
+ * synchronous operations are supported by the current hypervisor,
+ * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
+ * completion and return HV_EOK, or return an error code.
+ *
+ * The real address of the sub-function argument must be aligned on at
+ * least an 8-byte boundary.
+ *
+ * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
+ * offset, into the queue and must be less than or equal the 'num_ents'
+ * argument given in the HV_NCS_QCONF call.
+ */
+#define HV_FAST_NCS_REQUEST             0x110
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_ncs_request(unsigned long request,
+                                       unsigned long arg_ra,
+                                       unsigned long arg_size);
+#endif
+
+#define HV_FAST_FIRE_GET_PERFREG        0x120
+#define HV_FAST_FIRE_SET_PERFREG        0x121
+
+/* Function numbers for HV_CORE_TRAP.  */
+#define HV_CORE_SET_VER                 0x00
+#define HV_CORE_PUTCHAR                 0x01
+#define HV_CORE_EXIT                    0x02
+#define HV_CORE_GET_VER                 0x03
+
+/* Hypervisor API groups for use with HV_CORE_SET_VER and
+ * HV_CORE_GET_VER.
+ */
+#define HV_GRP_SUN4V                    0x0000
+#define HV_GRP_CORE                     0x0001
+#define HV_GRP_INTR                     0x0002
+#define HV_GRP_SOFT_STATE               0x0003
+#define HV_GRP_PCI                      0x0100
+#define HV_GRP_LDOM                     0x0101
+#define HV_GRP_SVC_CHAN                 0x0102
+#define HV_GRP_NCS                      0x0103
+#define HV_GRP_RNG                      0x0104
+#define HV_GRP_NIAG_PERF                0x0200
+#define HV_GRP_FIRE_PERF                0x0201
+#define HV_GRP_N2_CPU                   0x0202
+#define HV_GRP_NIU                      0x0204
+#define HV_GRP_VF_CPU                   0x0205
+#define HV_GRP_DIAG                     0x0300
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_get_version(unsigned long group,
+                                       unsigned long *major,
+                                       unsigned long *minor);
+extern unsigned long sun4v_set_version(unsigned long group,
+                                       unsigned long major,
+                                       unsigned long minor,
+                                       unsigned long *actual_minor);
+
+extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
+                                unsigned long *minor);
+extern void sun4v_hvapi_unregister(unsigned long group);
+extern int sun4v_hvapi_get(unsigned long group,
+                           unsigned long *major,
+                           unsigned long *minor);
+extern void sun4v_hvapi_init(void);
+#endif
+
+#endif /* !(_SPARC64_HYPERVISOR_H) */
diff --git a/arch/sparc/include/asm/ide.h b/arch/sparc/include/asm/ide.h
new file mode 100644
index 000000000000..b7af3d658239
--- /dev/null
+++ b/arch/sparc/include/asm/ide.h
@@ -0,0 +1,97 @@
+/* ide.h: SPARC PCI specific IDE glue.
+ *
+ * Copyright (C) 1997  David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1998  Eddie C. Dost   (ecd@skynet.be)
+ * Adaptation from sparc64 version to sparc by Pete Zaitcev.
+ */
+
+#ifndef _SPARC_IDE_H
+#define _SPARC_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/io.h>
+#ifdef CONFIG_SPARC64
+#include <asm/pgalloc.h>
+#include <asm/spitfire.h>
+#include <asm/cacheflush.h>
+#include <asm/page.h>
+#else
+#include <asm/pgtable.h>
+#include <asm/psr.h>
+#endif
+
+#define __ide_insl(data_reg, buffer, wcount) \
+        __ide_insw(data_reg, buffer, (wcount)<<1)
+#define __ide_outsl(data_reg, buffer, wcount) \
+        __ide_outsw(data_reg, buffer, (wcount)<<1)
+
+/* On sparc, I/O ports and MMIO registers are accessed identically.  */
+#define __ide_mm_insw   __ide_insw
+#define __ide_mm_insl   __ide_insl
+#define __ide_mm_outsw  __ide_outsw
+#define __ide_mm_outsl  __ide_outsl
+
+static inline void __ide_insw(void __iomem *port, void *dst, u32 count)
+{
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+        unsigned long end = (unsigned long)dst + (count << 1);
+#endif
+        u16 *ps = dst;
+        u32 *pi;
+
+        if(((unsigned long)ps) & 0x2) {
+                *ps++ = __raw_readw(port);
+                count--;
+        }
+        pi = (u32 *)ps;
+        while(count >= 2) {
+                u32 w;
+
+                w  = __raw_readw(port) << 16;
+                w |= __raw_readw(port);
+                *pi++ = w;
+                count -= 2;
+        }
+        ps = (u16 *)pi;
+        if(count)
+                *ps++ = __raw_readw(port);
+
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+        __flush_dcache_range((unsigned long)dst, end);
+#endif
+}
+
+static inline void __ide_outsw(void __iomem *port, const void *src, u32 count)
+{
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+        unsigned long end = (unsigned long)src + (count << 1);
+#endif
+        const u16 *ps = src;
+        const u32 *pi;
+
+        if(((unsigned long)src) & 0x2) {
+                __raw_writew(*ps++, port);
+                count--;
+        }
+        pi = (const u32 *)ps;
+        while(count >= 2) {
+                u32 w;
+
+                w = *pi++;
+                __raw_writew((w >> 16), port);
+                __raw_writew(w, port);
+                count -= 2;
+        }
+        ps = (const u16 *)pi;
+        if(count)
+                __raw_writew(*ps, port);
+
+#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
+        __flush_dcache_range((unsigned long)src, end);
+#endif
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _SPARC_IDE_H */
diff --git a/arch/sparc/include/asm/idprom.h b/arch/sparc/include/asm/idprom.h
new file mode 100644
index 000000000000..6976aa2439c6
--- /dev/null
+++ b/arch/sparc/include/asm/idprom.h
@@ -0,0 +1,25 @@
+/*
+ * idprom.h: Macros and defines for idprom routines
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_IDPROM_H
+#define _SPARC_IDPROM_H
+
+#include <linux/types.h>
+
+struct idprom {
+        u8              id_format;      /* Format identifier (always 0x01) */
+        u8              id_machtype;    /* Machine type */
+        u8              id_ethaddr[6];  /* Hardware ethernet address */
+        s32             id_date;        /* Date of manufacture */
+        u32             id_sernum:24;   /* Unique serial number */
+        u8              id_cksum;       /* Checksum - xor of the data bytes */
+        u8              reserved[16];
+};
+
+extern struct idprom *idprom;
+extern void idprom_init(void);
+
+#endif /* !(_SPARC_IDPROM_H) */
diff --git a/arch/sparc/include/asm/intr_queue.h b/arch/sparc/include/asm/intr_queue.h
new file mode 100644
index 000000000000..206077dedc2a
--- /dev/null
+++ b/arch/sparc/include/asm/intr_queue.h
@@ -0,0 +1,15 @@
+#ifndef _SPARC64_INTR_QUEUE_H
+#define _SPARC64_INTR_QUEUE_H
+
+/* Sun4v interrupt queue registers, accessed via ASI_QUEUE.  */
+
+#define INTRQ_CPU_MONDO_HEAD      0x3c0 /* CPU mondo head                 */
+#define INTRQ_CPU_MONDO_TAIL      0x3c8 /* CPU mondo tail                 */
+#define INTRQ_DEVICE_MONDO_HEAD   0x3d0 /* Device mondo head              */
+#define INTRQ_DEVICE_MONDO_TAIL   0x3d8 /* Device mondo tail              */
+#define INTRQ_RESUM_MONDO_HEAD    0x3e0 /* Resumable error mondo head     */
+#define INTRQ_RESUM_MONDO_TAIL    0x3e8 /* Resumable error mondo tail     */
+#define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
+#define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
+
+#endif /* !(_SPARC64_INTR_QUEUE_H) */
diff --git a/arch/sparc/include/asm/io-unit.h b/arch/sparc/include/asm/io-unit.h
new file mode 100644
index 000000000000..96823b47fd45
--- /dev/null
+++ b/arch/sparc/include/asm/io-unit.h
@@ -0,0 +1,62 @@
+/* io-unit.h: Definitions for the sun4d IO-UNIT.
+ *
+ * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _SPARC_IO_UNIT_H
+#define _SPARC_IO_UNIT_H
+
+#include <linux/spinlock.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+/* The io-unit handles all virtual to physical address translations
+ * that occur between the SBUS and physical memory.  Access by
+ * the cpu to IO registers and similar go over the xdbus so are
+ * translated by the on chip SRMMU.  The io-unit and the srmmu do
+ * not need to have the same translations at all, in fact most
+ * of the time the translations they handle are a disjunct set.
+ * Basically the io-unit handles all dvma sbus activity.
+ */
+ 
+/* AIEEE, unlike the nice sun4m, these monsters have 
+   fixed DMA range 64M */
+ 
+#define IOUNIT_DMA_BASE     0xfc000000 /* TOP - 64M */
+#define IOUNIT_DMA_SIZE     0x04000000 /* 64M */
+/* We use last 1M for sparc_dvma_malloc */
+#define IOUNIT_DVMA_SIZE    0x00100000 /* 1M */
+
+/* The format of an iopte in the external page tables */
+#define IOUPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12])     */
+#define IOUPTE_CACHE         0x00000080 /* Cached (in Viking/MXCC)              */
+/* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d.
+ * XXX Actually, all you should need to do is find out where the registers
+ * XXX are and copy over the sparc64 implementation I wrote.  There may be
+ * XXX some horrible hwbugs though, so be careful.  -DaveM
+ */
+#define IOUPTE_STREAM        0x00000040 /* Translation can use streaming cache  */
+#define IOUPTE_INTRA         0x00000008 /* SBUS direct slot->slot transfer      */
+#define IOUPTE_WRITE         0x00000004 /* Writeable                            */
+#define IOUPTE_VALID         0x00000002 /* IOPTE is valid                       */
+#define IOUPTE_PARITY        0x00000001 /* Parity is checked during DVMA        */
+
+struct iounit_struct {
+        unsigned long           bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)];
+        spinlock_t              lock;
+        iopte_t                 *page_table;
+        unsigned long           rotor[3];
+        unsigned long           limit[4];
+};
+
+#define IOUNIT_BMAP1_START      0x00000000
+#define IOUNIT_BMAP1_END        (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1))
+#define IOUNIT_BMAP2_START      IOUNIT_BMAP1_END
+#define IOUNIT_BMAP2_END        IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2))
+#define IOUNIT_BMAPM_START      IOUNIT_BMAP2_END
+#define IOUNIT_BMAPM_END        ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
+
+extern __u32 iounit_map_dma_init(struct sbus_bus *, int);
+#define iounit_map_dma_finish(sbus, addr, len) mmu_release_scsi_one(addr, len, sbus)
+extern __u32 iounit_map_dma_page(__u32, void *, struct sbus_bus *);
+
+#endif /* !(_SPARC_IO_UNIT_H) */
diff --git a/arch/sparc/include/asm/io.h b/arch/sparc/include/asm/io.h
new file mode 100644
index 000000000000..a34b2994937a
--- /dev/null
+++ b/arch/sparc/include/asm/io.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_IO_H
+#define ___ASM_SPARC_IO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/io_64.h>
+#else
+#include <asm/io_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
new file mode 100644
index 000000000000..10d7da450070
--- /dev/null
+++ b/arch/sparc/include/asm/io_32.h
@@ -0,0 +1,326 @@
+#ifndef __SPARC_IO_H
+#define __SPARC_IO_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ioport.h>  /* struct resource */
+
+#include <asm/page.h>      /* IO address mapping routines need this */
+#include <asm/system.h>
+
+#define page_to_phys(page)      (((page) - mem_map) << PAGE_SHIFT)
+
+static inline u32 flip_dword (u32 l)
+{
+        return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
+}
+
+static inline u16 flip_word (u16 w)
+{
+        return ((w&0xff) << 8) | ((w>>8)&0xff);
+}
+
+#define mmiowb()
+
+/*
+ * Memory mapped I/O to PCI
+ */
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+        return *(__force volatile u8 *)addr;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+        return *(__force volatile u16 *)addr;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+        return *(__force volatile u32 *)addr;
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+        *(__force volatile u8 *)addr = b;
+}
+
+static inline void __raw_writew(u16 w, volatile void __iomem *addr)
+{
+        *(__force volatile u16 *)addr = w;
+}
+
+static inline void __raw_writel(u32 l, volatile void __iomem *addr)
+{
+        *(__force volatile u32 *)addr = l;
+}
+
+static inline u8 __readb(const volatile void __iomem *addr)
+{
+        return *(__force volatile u8 *)addr;
+}
+
+static inline u16 __readw(const volatile void __iomem *addr)
+{
+        return flip_word(*(__force volatile u16 *)addr);
+}
+
+static inline u32 __readl(const volatile void __iomem *addr)
+{
+        return flip_dword(*(__force volatile u32 *)addr);
+}
+
+static inline void __writeb(u8 b, volatile void __iomem *addr)
+{
+        *(__force volatile u8 *)addr = b;
+}
+
+static inline void __writew(u16 w, volatile void __iomem *addr)
+{
+        *(__force volatile u16 *)addr = flip_word(w);
+}
+
+static inline void __writel(u32 l, volatile void __iomem *addr)
+{
+        *(__force volatile u32 *)addr = flip_dword(l);
+}
+
+#define readb(__addr)           __readb(__addr)
+#define readw(__addr)           __readw(__addr)
+#define readl(__addr)           __readl(__addr)
+#define readb_relaxed(__addr)   readb(__addr)
+#define readw_relaxed(__addr)   readw(__addr)
+#define readl_relaxed(__addr)   readl(__addr)
+
+#define writeb(__b, __addr)     __writeb((__b),(__addr))
+#define writew(__w, __addr)     __writew((__w),(__addr))
+#define writel(__l, __addr)     __writel((__l),(__addr))
+
+/*
+ * I/O space operations
+ *
+ * Arrangement on a Sun is somewhat complicated.
+ *
+ * First of all, we want to use standard Linux drivers
+ * for keyboard, PC serial, etc. These drivers think
+ * they access I/O space and use inb/outb.
+ * On the other hand, EBus bridge accepts PCI *memory*
+ * cycles and converts them into ISA *I/O* cycles.
+ * Ergo, we want inb & outb to generate PCI memory cycles.
+ *
+ * If we want to issue PCI *I/O* cycles, we do this
+ * with a low 64K fixed window in PCIC. This window gets
+ * mapped somewhere into virtual kernel space and we
+ * can use inb/outb again.
+ */
+#define inb_local(__addr)       __readb((void __iomem *)(unsigned long)(__addr))
+#define inb(__addr)             __readb((void __iomem *)(unsigned long)(__addr))
+#define inw(__addr)             __readw((void __iomem *)(unsigned long)(__addr))
+#define inl(__addr)             __readl((void __iomem *)(unsigned long)(__addr))
+
+#define outb_local(__b, __addr) __writeb(__b, (void __iomem *)(unsigned long)(__addr))
+#define outb(__b, __addr)       __writeb(__b, (void __iomem *)(unsigned long)(__addr))
+#define outw(__w, __addr)       __writew(__w, (void __iomem *)(unsigned long)(__addr))
+#define outl(__l, __addr)       __writel(__l, (void __iomem *)(unsigned long)(__addr))
+
+#define inb_p(__addr)           inb(__addr)
+#define outb_p(__b, __addr)     outb(__b, __addr)
+#define inw_p(__addr)           inw(__addr)
+#define outw_p(__w, __addr)     outw(__w, __addr)
+#define inl_p(__addr)           inl(__addr)
+#define outl_p(__l, __addr)     outl(__l, __addr)
+
+void outsb(unsigned long addr, const void *src, unsigned long cnt);
+void outsw(unsigned long addr, const void *src, unsigned long cnt);
+void outsl(unsigned long addr, const void *src, unsigned long cnt);
+void insb(unsigned long addr, void *dst, unsigned long count);
+void insw(unsigned long addr, void *dst, unsigned long count);
+void insl(unsigned long addr, void *dst, unsigned long count);
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * SBus accessors.
+ *
+ * SBus has only one, memory mapped, I/O space.
+ * We do not need to flip bytes for SBus of course.
+ */
+static inline u8 _sbus_readb(const volatile void __iomem *addr)
+{
+        return *(__force volatile u8 *)addr;
+}
+
+static inline u16 _sbus_readw(const volatile void __iomem *addr)
+{
+        return *(__force volatile u16 *)addr;
+}
+
+static inline u32 _sbus_readl(const volatile void __iomem *addr)
+{
+        return *(__force volatile u32 *)addr;
+}
+
+static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
+{
+        *(__force volatile u8 *)addr = b;
+}
+
+static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
+{
+        *(__force volatile u16 *)addr = w;
+}
+
+static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
+{
+        *(__force volatile u32 *)addr = l;
+}
+
+/*
+ * The only reason for #define's is to hide casts to unsigned long.
+ */
+#define sbus_readb(__addr)              _sbus_readb(__addr)
+#define sbus_readw(__addr)              _sbus_readw(__addr)
+#define sbus_readl(__addr)              _sbus_readl(__addr)
+#define sbus_writeb(__b, __addr)        _sbus_writeb(__b, __addr)
+#define sbus_writew(__w, __addr)        _sbus_writew(__w, __addr)
+#define sbus_writel(__l, __addr)        _sbus_writel(__l, __addr)
+
+static inline void sbus_memset_io(volatile void __iomem *__dst, int c, __kernel_size_t n)
+{
+        while(n--) {
+                sbus_writeb(c, __dst);
+                __dst++;
+        }
+}
+
+static inline void
+_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
+{
+        volatile void __iomem *d = dst;
+
+        while (n--) {
+                writeb(c, d);
+                d++;
+        }
+}
+
+#define memset_io(d,c,sz)       _memset_io(d,c,sz)
+
+static inline void
+_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
+{
+        char *d = dst;
+
+        while (n--) {
+                char tmp = readb(src);
+                *d++ = tmp;
+                src++;
+        }
+}
+
+#define memcpy_fromio(d,s,sz)   _memcpy_fromio(d,s,sz)
+
+static inline void
+_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
+{
+        const char *s = src;
+        volatile void __iomem *d = dst;
+
+        while (n--) {
+                char tmp = *s++;
+                writeb(tmp, d);
+                d++;
+        }
+}
+
+#define memcpy_toio(d,s,sz)     _memcpy_toio(d,s,sz)
+
+#ifdef __KERNEL__
+
+/*
+ * Bus number may be embedded in the higher bits of the physical address.
+ * This is why we have no bus number argument to ioremap().
+ */
+extern void __iomem *ioremap(unsigned long offset, unsigned long size);
+#define ioremap_nocache(X,Y)    ioremap((X),(Y))
+#define ioremap_wc(X,Y)         ioremap((X),(Y))
+extern void iounmap(volatile void __iomem *addr);
+
+#define ioread8(X)                      readb(X)
+#define ioread16(X)                     readw(X)
+#define ioread32(X)                     readl(X)
+#define iowrite8(val,X)                 writeb(val,X)
+#define iowrite16(val,X)                writew(val,X)
+#define iowrite32(val,X)                writel(val,X)
+
+static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insb((unsigned long __force)port, buf, count);
+}
+static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insw((unsigned long __force)port, buf, count);
+}
+
+static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insl((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsb((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsw((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsl((unsigned long __force)port, buf, count);
+}
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+/*
+ * Bus number may be in res->flags... somewhere.
+ */
+extern void __iomem *sbus_ioremap(struct resource *res, unsigned long offset,
+    unsigned long size, char *name);
+extern void sbus_iounmap(volatile void __iomem *vaddr, unsigned long size);
+
+
+/*
+ * At the moment, we do not use CMOS_READ anywhere outside of rtc.c,
+ * so rtc_port is static in it. This should not change unless a new
+ * hardware pops up.
+ */
+#define RTC_PORT(x)   (rtc_port + (x))
+#define RTC_ALWAYS_BCD  0
+
+#endif
+
+#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED          1
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif /* !(__SPARC_IO_H) */
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
new file mode 100644
index 000000000000..0bff078ffdd0
--- /dev/null
+++ b/arch/sparc/include/asm/io_64.h
@@ -0,0 +1,511 @@
+#ifndef __SPARC64_IO_H
+#define __SPARC64_IO_H
+
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#include <asm/page.h>      /* IO address mapping routines need this */
+#include <asm/system.h>
+#include <asm/asi.h>
+
+/* PC crapola... */
+#define __SLOW_DOWN_IO  do { } while (0)
+#define SLOW_DOWN_IO    do { } while (0)
+
+/* BIO layer definitions. */
+extern unsigned long kern_base, kern_size;
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+
+static inline u8 _inb(unsigned long addr)
+{
+        u8 ret;
+
+        __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+
+        return ret;
+}
+
+static inline u16 _inw(unsigned long addr)
+{
+        u16 ret;
+
+        __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+
+        return ret;
+}
+
+static inline u32 _inl(unsigned long addr)
+{
+        u32 ret;
+
+        __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+
+        return ret;
+}
+
+static inline void _outb(u8 b, unsigned long addr)
+{
+        __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
+                             : /* no outputs */
+                             : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+}
+
+static inline void _outw(u16 w, unsigned long addr)
+{
+        __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
+                             : /* no outputs */
+                             : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+}
+
+static inline void _outl(u32 l, unsigned long addr)
+{
+        __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
+                             : /* no outputs */
+                             : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+}
+
+#define inb(__addr)             (_inb((unsigned long)(__addr)))
+#define inw(__addr)             (_inw((unsigned long)(__addr)))
+#define inl(__addr)             (_inl((unsigned long)(__addr)))
+#define outb(__b, __addr)       (_outb((u8)(__b), (unsigned long)(__addr)))
+#define outw(__w, __addr)       (_outw((u16)(__w), (unsigned long)(__addr)))
+#define outl(__l, __addr)       (_outl((u32)(__l), (unsigned long)(__addr)))
+
+#define inb_p(__addr)           inb(__addr)
+#define outb_p(__b, __addr)     outb(__b, __addr)
+#define inw_p(__addr)           inw(__addr)
+#define outw_p(__w, __addr)     outw(__w, __addr)
+#define inl_p(__addr)           inl(__addr)
+#define outl_p(__l, __addr)     outl(__l, __addr)
+
+extern void outsb(unsigned long, const void *, unsigned long);
+extern void outsw(unsigned long, const void *, unsigned long);
+extern void outsl(unsigned long, const void *, unsigned long);
+extern void insb(unsigned long, void *, unsigned long);
+extern void insw(unsigned long, void *, unsigned long);
+extern void insl(unsigned long, void *, unsigned long);
+
+static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insb((unsigned long __force)port, buf, count);
+}
+static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insw((unsigned long __force)port, buf, count);
+}
+
+static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
+{
+        insl((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsb((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsw((unsigned long __force)port, buf, count);
+}
+
+static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
+{
+        outsl((unsigned long __force)port, buf, count);
+}
+
+/* Memory functions, same as I/O accesses on Ultra. */
+static inline u8 _readb(const volatile void __iomem *addr)
+{       u8 ret;
+
+        __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+        return ret;
+}
+
+static inline u16 _readw(const volatile void __iomem *addr)
+{       u16 ret;
+
+        __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+
+        return ret;
+}
+
+static inline u32 _readl(const volatile void __iomem *addr)
+{       u32 ret;
+
+        __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+
+        return ret;
+}
+
+static inline u64 _readq(const volatile void __iomem *addr)
+{       u64 ret;
+
+        __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+
+        return ret;
+}
+
+static inline void _writeb(u8 b, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
+                             : /* no outputs */
+                             : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+}
+
+static inline void _writew(u16 w, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
+                             : /* no outputs */
+                             : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+}
+
+static inline void _writel(u32 l, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
+                             : /* no outputs */
+                             : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+}
+
+static inline void _writeq(u64 q, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
+                             : /* no outputs */
+                             : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
+                             : "memory");
+}
+
+#define readb(__addr)           _readb(__addr)
+#define readw(__addr)           _readw(__addr)
+#define readl(__addr)           _readl(__addr)
+#define readq(__addr)           _readq(__addr)
+#define readb_relaxed(__addr)   _readb(__addr)
+#define readw_relaxed(__addr)   _readw(__addr)
+#define readl_relaxed(__addr)   _readl(__addr)
+#define readq_relaxed(__addr)   _readq(__addr)
+#define writeb(__b, __addr)     _writeb(__b, __addr)
+#define writew(__w, __addr)     _writew(__w, __addr)
+#define writel(__l, __addr)     _writel(__l, __addr)
+#define writeq(__q, __addr)     _writeq(__q, __addr)
+
+/* Now versions without byte-swapping. */
+static inline u8 _raw_readb(unsigned long addr)
+{
+        u8 ret;
+
+        __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline u16 _raw_readw(unsigned long addr)
+{
+        u16 ret;
+
+        __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline u32 _raw_readl(unsigned long addr)
+{
+        u32 ret;
+
+        __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline u64 _raw_readq(unsigned long addr)
+{
+        u64 ret;
+
+        __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline void _raw_writeb(u8 b, unsigned long addr)
+{
+        __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
+                             : /* no outputs */
+                             : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _raw_writew(u16 w, unsigned long addr)
+{
+        __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
+                             : /* no outputs */
+                             : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _raw_writel(u32 l, unsigned long addr)
+{
+        __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
+                             : /* no outputs */
+                             : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _raw_writeq(u64 q, unsigned long addr)
+{
+        __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
+                             : /* no outputs */
+                             : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+#define __raw_readb(__addr)             (_raw_readb((unsigned long)(__addr)))
+#define __raw_readw(__addr)             (_raw_readw((unsigned long)(__addr)))
+#define __raw_readl(__addr)             (_raw_readl((unsigned long)(__addr)))
+#define __raw_readq(__addr)             (_raw_readq((unsigned long)(__addr)))
+#define __raw_writeb(__b, __addr)       (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
+#define __raw_writew(__w, __addr)       (_raw_writew((u16)(__w), (unsigned long)(__addr)))
+#define __raw_writel(__l, __addr)       (_raw_writel((u32)(__l), (unsigned long)(__addr)))
+#define __raw_writeq(__q, __addr)       (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
+
+/* Valid I/O Space regions are anywhere, because each PCI bus supported
+ * can live in an arbitrary area of the physical address range.
+ */
+#define IO_SPACE_LIMIT 0xffffffffffffffffUL
+
+/* Now, SBUS variants, only difference from PCI is that we do
+ * not use little-endian ASIs.
+ */
+static inline u8 _sbus_readb(const volatile void __iomem *addr)
+{
+        u8 ret;
+
+        __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+
+        return ret;
+}
+
+static inline u16 _sbus_readw(const volatile void __iomem *addr)
+{
+        u16 ret;
+
+        __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+
+        return ret;
+}
+
+static inline u32 _sbus_readl(const volatile void __iomem *addr)
+{
+        u32 ret;
+
+        __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+
+        return ret;
+}
+
+static inline u64 _sbus_readq(const volatile void __iomem *addr)
+{
+        u64 ret;
+
+        __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+
+        return ret;
+}
+
+static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
+                             : /* no outputs */
+                             : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+}
+
+static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
+                             : /* no outputs */
+                             : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+}
+
+static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
+                             : /* no outputs */
+                             : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+}
+
+static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
+{
+        __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
+                             : /* no outputs */
+                             : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
+                             : "memory");
+}
+
+#define sbus_readb(__addr)              _sbus_readb(__addr)
+#define sbus_readw(__addr)              _sbus_readw(__addr)
+#define sbus_readl(__addr)              _sbus_readl(__addr)
+#define sbus_readq(__addr)              _sbus_readq(__addr)
+#define sbus_writeb(__b, __addr)        _sbus_writeb(__b, __addr)
+#define sbus_writew(__w, __addr)        _sbus_writew(__w, __addr)
+#define sbus_writel(__l, __addr)        _sbus_writel(__l, __addr)
+#define sbus_writeq(__l, __addr)        _sbus_writeq(__l, __addr)
+
+static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
+{
+        while(n--) {
+                sbus_writeb(c, dst);
+                dst++;
+        }
+}
+
+#define sbus_memset_io(d,c,sz)  _sbus_memset_io(d,c,sz)
+
+static inline void
+_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
+{
+        volatile void __iomem *d = dst;
+
+        while (n--) {
+                writeb(c, d);
+                d++;
+        }
+}
+
+#define memset_io(d,c,sz)       _memset_io(d,c,sz)
+
+static inline void
+_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
+{
+        char *d = dst;
+
+        while (n--) {
+                char tmp = readb(src);
+                *d++ = tmp;
+                src++;
+        }
+}
+
+#define memcpy_fromio(d,s,sz)   _memcpy_fromio(d,s,sz)
+
+static inline void
+_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
+{
+        const char *s = src;
+        volatile void __iomem *d = dst;
+
+        while (n--) {
+                char tmp = *s++;
+                writeb(tmp, d);
+                d++;
+        }
+}
+
+#define memcpy_toio(d,s,sz)     _memcpy_toio(d,s,sz)
+
+#define mmiowb()
+
+#ifdef __KERNEL__
+
+/* On sparc64 we have the whole physical IO address space accessible
+ * using physically addressed loads and stores, so this does nothing.
+ */
+static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
+{
+        return (void __iomem *)offset;
+}
+
+#define ioremap_nocache(X,Y)            ioremap((X),(Y))
+#define ioremap_wc(X,Y)                 ioremap((X),(Y))
+
+static inline void iounmap(volatile void __iomem *addr)
+{
+}
+
+#define ioread8(X)                      readb(X)
+#define ioread16(X)                     readw(X)
+#define ioread32(X)                     readl(X)
+#define iowrite8(val,X)                 writeb(val,X)
+#define iowrite16(val,X)                writew(val,X)
+#define iowrite32(val,X)                writel(val,X)
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+/* Similarly for SBUS. */
+#define sbus_ioremap(__res, __offset, __size, __name) \
+({      unsigned long __ret; \
+        __ret  = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
+        __ret += (unsigned long) (__offset); \
+        if (! request_region((__ret), (__size), (__name))) \
+                __ret = 0UL; \
+        (void __iomem *) __ret; \
+})
+
+#define sbus_iounmap(__addr, __size)    \
+        release_region((unsigned long)(__addr), (__size))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif
+
+#endif /* !(__SPARC64_IO_H) */
diff --git a/arch/sparc/include/asm/ioctl.h b/arch/sparc/include/asm/ioctl.h
new file mode 100644
index 000000000000..7d6bd51321b9
--- /dev/null
+++ b/arch/sparc/include/asm/ioctl.h
@@ -0,0 +1,67 @@
+#ifndef _SPARC_IOCTL_H
+#define _SPARC_IOCTL_H
+
+/*
+ * Our DIR and SIZE overlap in order to simulteneously provide
+ * a non-zero _IOC_NONE (for binary compatibility) and
+ * 14 bits of size as on i386. Here's the layout:
+ *
+ *   0xE0000000   DIR
+ *   0x80000000     DIR = WRITE
+ *   0x40000000     DIR = READ
+ *   0x20000000     DIR = NONE
+ *   0x3FFF0000   SIZE (overlaps NONE bit)
+ *   0x0000FF00   TYPE
+ *   0x000000FF   NR (CMD)
+ */
+
+#define _IOC_NRBITS      8
+#define _IOC_TYPEBITS    8
+#define _IOC_SIZEBITS   13      /* Actually 14, see below. */
+#define _IOC_DIRBITS     3
+
+#define _IOC_NRMASK      ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK    ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK    ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_XSIZEMASK   ((1 << (_IOC_SIZEBITS+1))-1)
+#define _IOC_DIRMASK     ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT     0
+#define _IOC_TYPESHIFT   (_IOC_NRSHIFT + _IOC_NRBITS)
+#define _IOC_SIZESHIFT   (_IOC_TYPESHIFT + _IOC_TYPEBITS)
+#define _IOC_DIRSHIFT    (_IOC_SIZESHIFT + _IOC_SIZEBITS)
+
+#define _IOC_NONE        1U
+#define _IOC_READ        2U
+#define _IOC_WRITE       4U
+
+#define _IOC(dir,type,nr,size) \
+        (((dir)  << _IOC_DIRSHIFT) | \
+         ((type) << _IOC_TYPESHIFT) | \
+         ((nr)   << _IOC_NRSHIFT) | \
+         ((size) << _IOC_SIZESHIFT))
+
+#define _IO(type,nr)        _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)  _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW(type,nr,size)  _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* Used to decode ioctl numbers in drivers despite the leading underscore... */
+#define _IOC_DIR(nr)    \
+ ( (((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) != 0)?   \
+                            (((nr) >> _IOC_DIRSHIFT) & (_IOC_WRITE|_IOC_READ)):  \
+                            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) )
+#define _IOC_TYPE(nr)       (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)         (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)   \
+ ((((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) == 0)?    \
+                         0: (((nr) >> _IOC_SIZESHIFT) & _IOC_XSIZEMASK))
+
+/* ...and for the PCMCIA and sound. */
+#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK    (_IOC_XSIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+
+#endif /* !(_SPARC_IOCTL_H) */
diff --git a/arch/sparc/include/asm/ioctls.h b/arch/sparc/include/asm/ioctls.h
new file mode 100644
index 000000000000..1fe6855c5c18
--- /dev/null
+++ b/arch/sparc/include/asm/ioctls.h
@@ -0,0 +1,136 @@
+#ifndef _ASM_SPARC_IOCTLS_H
+#define _ASM_SPARC_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+/* Big T */
+#define TCGETA          _IOR('T', 1, struct termio)
+#define TCSETA          _IOW('T', 2, struct termio)
+#define TCSETAW         _IOW('T', 3, struct termio)
+#define TCSETAF         _IOW('T', 4, struct termio)
+#define TCSBRK          _IO('T', 5)
+#define TCXONC          _IO('T', 6)
+#define TCFLSH          _IO('T', 7)
+#define TCGETS          _IOR('T', 8, struct termios)
+#define TCSETS          _IOW('T', 9, struct termios)
+#define TCSETSW         _IOW('T', 10, struct termios)
+#define TCSETSF         _IOW('T', 11, struct termios)
+#define TCGETS2         _IOR('T', 12, struct termios2)
+#define TCSETS2         _IOW('T', 13, struct termios2)
+#define TCSETSW2        _IOW('T', 14, struct termios2)
+#define TCSETSF2        _IOW('T', 15, struct termios2)
+
+/* Note that all the ioctls that are not available in Linux have a 
+ * double underscore on the front to: a) avoid some programs to
+ * think we support some ioctls under Linux (autoconfiguration stuff)
+ */
+/* Little t */
+#define TIOCGETD        _IOR('t', 0, int)
+#define TIOCSETD        _IOW('t', 1, int)
+#define __TIOCHPCL        _IO('t', 2) /* SunOS Specific */
+#define __TIOCMODG        _IOR('t', 3, int) /* SunOS Specific */
+#define __TIOCMODS        _IOW('t', 4, int) /* SunOS Specific */
+#define __TIOCGETP        _IOR('t', 8, struct sgttyb) /* SunOS Specific */
+#define __TIOCSETP        _IOW('t', 9, struct sgttyb) /* SunOS Specific */
+#define __TIOCSETN        _IOW('t', 10, struct sgttyb) /* SunOS Specific */
+#define TIOCEXCL        _IO('t', 13)
+#define TIOCNXCL        _IO('t', 14)
+#define __TIOCFLUSH       _IOW('t', 16, int) /* SunOS Specific */
+#define __TIOCSETC        _IOW('t', 17, struct tchars) /* SunOS Specific */
+#define __TIOCGETC        _IOR('t', 18, struct tchars) /* SunOS Specific */
+#define __TIOCTCNTL       _IOW('t', 32, int) /* SunOS Specific */
+#define __TIOCSIGNAL      _IOW('t', 33, int) /* SunOS Specific */
+#define __TIOCSETX        _IOW('t', 34, int) /* SunOS Specific */
+#define __TIOCGETX        _IOR('t', 35, int) /* SunOS Specific */
+#define TIOCCONS        _IO('t', 36)
+#define TIOCGSOFTCAR    _IOR('t', 100, int)
+#define TIOCSSOFTCAR    _IOW('t', 101, int)
+#define __TIOCUCNTL       _IOW('t', 102, int) /* SunOS Specific */
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
+#define __TIOCREMOTE      _IOW('t', 105, int) /* SunOS Specific */
+#define TIOCMGET        _IOR('t', 106, int)
+#define TIOCMBIC        _IOW('t', 107, int)
+#define TIOCMBIS        _IOW('t', 108, int)
+#define TIOCMSET        _IOW('t', 109, int)
+#define TIOCSTART       _IO('t', 110)
+#define TIOCSTOP        _IO('t', 111)
+#define TIOCPKT         _IOW('t', 112, int)
+#define TIOCNOTTY       _IO('t', 113)
+#define TIOCSTI         _IOW('t', 114, char)
+#define TIOCOUTQ        _IOR('t', 115, int)
+#define __TIOCGLTC        _IOR('t', 116, struct ltchars) /* SunOS Specific */
+#define __TIOCSLTC        _IOW('t', 117, struct ltchars) /* SunOS Specific */
+/* 118 is the non-posix setpgrp tty ioctl */
+/* 119 is the non-posix getpgrp tty ioctl */
+#define __TIOCCDTR        _IO('t', 120) /* SunOS Specific */
+#define __TIOCSDTR        _IO('t', 121) /* SunOS Specific */
+#define TIOCCBRK        _IO('t', 122)
+#define TIOCSBRK        _IO('t', 123)
+#define __TIOCLGET        _IOW('t', 124, int) /* SunOS Specific */
+#define __TIOCLSET        _IOW('t', 125, int) /* SunOS Specific */
+#define __TIOCLBIC        _IOW('t', 126, int) /* SunOS Specific */
+#define __TIOCLBIS        _IOW('t', 127, int) /* SunOS Specific */
+#define __TIOCISPACE      _IOR('t', 128, int) /* SunOS Specific */
+#define __TIOCISIZE       _IOR('t', 129, int) /* SunOS Specific */
+#define TIOCSPGRP       _IOW('t', 130, int)
+#define TIOCGPGRP       _IOR('t', 131, int)
+#define TIOCSCTTY       _IO('t', 132)
+#define TIOCGSID        _IOR('t', 133, int)
+/* Get minor device of a pty master's FD -- Solaris equiv is ISPTM */
+#define TIOCGPTN        _IOR('t', 134, unsigned int) /* Get Pty Number */
+#define TIOCSPTLCK      _IOW('t', 135, int) /* Lock/unlock PTY */
+
+/* Little f */
+#define FIOCLEX         _IO('f', 1)
+#define FIONCLEX        _IO('f', 2)
+#define FIOASYNC        _IOW('f', 125, int)
+#define FIONBIO         _IOW('f', 126, int)
+#define FIONREAD        _IOR('f', 127, int)
+#define TIOCINQ         FIONREAD
+#define FIOQSIZE        _IOR('f', 128, loff_t)
+
+/* SCARY Rutgers local SunOS kernel hackery, perhaps I will support it
+ * someday.  This is completely bogus, I know...
+ */
+#define __TCGETSTAT       _IO('T', 200) /* Rutgers specific */
+#define __TCSETSTAT       _IO('T', 201) /* Rutgers specific */
+
+/* Linux specific, no SunOS equivalent. */
+#define TIOCLINUX       0x541C
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TCSBRKP         0x5425
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
+#define TIOCSERGETLSR   0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+#define TIOCMIWAIT      0x545C /* Wait for change on serial input line(s) */
+#define TIOCGICOUNT     0x545D /* Read serial port inline interrupt counts */
+
+/* Kernel definitions */
+#ifdef __KERNEL__
+#define TIOCGETC __TIOCGETC
+#define TIOCGETP __TIOCGETP
+#define TIOCGLTC __TIOCGLTC
+#define TIOCSLTC __TIOCSLTC
+#define TIOCSETP __TIOCSETP
+#define TIOCSETN __TIOCSETN
+#define TIOCSETC __TIOCSETC
+#endif
+
+/* Used for packet mode */
+#define TIOCPKT_DATA             0
+#define TIOCPKT_FLUSHREAD        1
+#define TIOCPKT_FLUSHWRITE       2
+#define TIOCPKT_STOP             4
+#define TIOCPKT_START            8
+#define TIOCPKT_NOSTOP          16
+#define TIOCPKT_DOSTOP          32
+
+#endif /* !(_ASM_SPARC_IOCTLS_H) */
diff --git a/arch/sparc/include/asm/iommu.h b/arch/sparc/include/asm/iommu.h
new file mode 100644
index 000000000000..e650965b4a8d
--- /dev/null
+++ b/arch/sparc/include/asm/iommu.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_IOMMU_H
+#define ___ASM_SPARC_IOMMU_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/iommu_64.h>
+#else
+#include <asm/iommu_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/iommu_32.h b/arch/sparc/include/asm/iommu_32.h
new file mode 100644
index 000000000000..70c589c05a10
--- /dev/null
+++ b/arch/sparc/include/asm/iommu_32.h
@@ -0,0 +1,121 @@
+/* iommu.h: Definitions for the sun4m IOMMU.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_IOMMU_H
+#define _SPARC_IOMMU_H
+
+#include <asm/page.h>
+#include <asm/bitext.h>
+
+/* The iommu handles all virtual to physical address translations
+ * that occur between the SBUS and physical memory.  Access by
+ * the cpu to IO registers and similar go over the mbus so are
+ * translated by the on chip SRMMU.  The iommu and the srmmu do
+ * not need to have the same translations at all, in fact most
+ * of the time the translations they handle are a disjunct set.
+ * Basically the iommu handles all dvma sbus activity.
+ */
+
+/* The IOMMU registers occupy three pages in IO space. */
+struct iommu_regs {
+        /* First page */
+        volatile unsigned long control;    /* IOMMU control */
+        volatile unsigned long base;       /* Physical base of iopte page table */
+        volatile unsigned long _unused1[3];
+        volatile unsigned long tlbflush;   /* write only */
+        volatile unsigned long pageflush;  /* write only */
+        volatile unsigned long _unused2[1017];
+        /* Second page */
+        volatile unsigned long afsr;       /* Async-fault status register */
+        volatile unsigned long afar;       /* Async-fault physical address */
+        volatile unsigned long _unused3[2];
+        volatile unsigned long sbuscfg0;   /* SBUS configuration registers, per-slot */
+        volatile unsigned long sbuscfg1;
+        volatile unsigned long sbuscfg2;
+        volatile unsigned long sbuscfg3;
+        volatile unsigned long mfsr;       /* Memory-fault status register */
+        volatile unsigned long mfar;       /* Memory-fault physical address */
+        volatile unsigned long _unused4[1014];
+        /* Third page */
+        volatile unsigned long mid;        /* IOMMU module-id */
+};
+
+#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
+#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
+#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
+#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
+#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
+#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
+#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
+#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
+#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
+#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
+#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
+#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
+
+#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
+#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after transaction */
+#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than 12.8 us. */
+#define IOMMU_AFSR_BE       0x10000000 /* Write access received error acknowledge */
+#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
+#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
+#define IOMMU_AFSR_RESV     0x00f00000 /* Reserver, forced to 0x8 by hardware */
+#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
+#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
+#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
+
+#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
+#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
+#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
+#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
+                                          produced by this device as pure
+                                          physical. */
+
+#define IOMMU_MFSR_ERR      0x80000000 /* One or more of PERR1 or PERR0 */
+#define IOMMU_MFSR_S        0x01000000 /* Sparc was in supervisor mode */
+#define IOMMU_MFSR_CPU      0x00800000 /* CPU transaction caused parity error */
+#define IOMMU_MFSR_ME       0x00080000 /* Multiple parity errors occurred */
+#define IOMMU_MFSR_PERR     0x00006000 /* high bit indicates parity error occurred
+                                          on the even word of the access, low bit
+                                          indicated odd word caused the parity error */
+#define IOMMU_MFSR_BM       0x00001000 /* Error occurred while in boot mode */
+#define IOMMU_MFSR_C        0x00000800 /* Address causing error was marked cacheable */
+#define IOMMU_MFSR_RTYP     0x000000f0 /* Memory request transaction type */
+
+#define IOMMU_MID_SBAE      0x001f0000 /* SBus arbitration enable */
+#define IOMMU_MID_SE        0x00100000 /* Enables SCSI/ETHERNET arbitration */
+#define IOMMU_MID_SB3       0x00080000 /* Enable SBUS device 3 arbitration */
+#define IOMMU_MID_SB2       0x00040000 /* Enable SBUS device 2 arbitration */
+#define IOMMU_MID_SB1       0x00020000 /* Enable SBUS device 1 arbitration */
+#define IOMMU_MID_SB0       0x00010000 /* Enable SBUS device 0 arbitration */
+#define IOMMU_MID_MID       0x0000000f /* Module-id, hardcoded to 0x8 */
+
+/* The format of an iopte in the page tables */
+#define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
+#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
+#define IOPTE_WRITE         0x00000004 /* Writeable */
+#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
+#define IOPTE_WAZ           0x00000001 /* Write as zeros */
+
+struct iommu_struct {
+        struct iommu_regs *regs;
+        iopte_t *page_table;
+        /* For convenience */
+        unsigned long start; /* First managed virtual address */
+        unsigned long end;   /* Last managed virtual address */
+
+        struct bit_map usemap;
+};
+
+static inline void iommu_invalidate(struct iommu_regs *regs)
+{
+        regs->tlbflush = 0;
+}
+
+static inline void iommu_invalidate_page(struct iommu_regs *regs, unsigned long ba)
+{
+        regs->pageflush = (ba & PAGE_MASK);
+}
+
+#endif /* !(_SPARC_IOMMU_H) */
diff --git a/arch/sparc/include/asm/iommu_64.h b/arch/sparc/include/asm/iommu_64.h
new file mode 100644
index 000000000000..d7b9afcba08b
--- /dev/null
+++ b/arch/sparc/include/asm/iommu_64.h
@@ -0,0 +1,62 @@
+/* iommu.h: Definitions for the sun5 IOMMU.
+ *
+ * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
+ */
+#ifndef _SPARC64_IOMMU_H
+#define _SPARC64_IOMMU_H
+
+/* The format of an iopte in the page tables. */
+#define IOPTE_VALID   0x8000000000000000UL
+#define IOPTE_64K     0x2000000000000000UL
+#define IOPTE_STBUF   0x1000000000000000UL
+#define IOPTE_INTRA   0x0800000000000000UL
+#define IOPTE_CONTEXT 0x07ff800000000000UL
+#define IOPTE_PAGE    0x00007fffffffe000UL
+#define IOPTE_CACHE   0x0000000000000010UL
+#define IOPTE_WRITE   0x0000000000000002UL
+
+#define IOMMU_NUM_CTXS  4096
+
+struct iommu_arena {
+        unsigned long   *map;
+        unsigned int    hint;
+        unsigned int    limit;
+};
+
+struct iommu {
+        spinlock_t              lock;
+        struct iommu_arena      arena;
+        void                    (*flush_all)(struct iommu *);
+        iopte_t                 *page_table;
+        u32                     page_table_map_base;
+        unsigned long           iommu_control;
+        unsigned long           iommu_tsbbase;
+        unsigned long           iommu_flush;
+        unsigned long           iommu_flushinv;
+        unsigned long           iommu_tags;
+        unsigned long           iommu_ctxflush;
+        unsigned long           write_complete_reg;
+        unsigned long           dummy_page;
+        unsigned long           dummy_page_pa;
+        unsigned long           ctx_lowest_free;
+        DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
+        u32                     dma_addr_mask;
+};
+
+struct strbuf {
+        int                     strbuf_enabled;
+        unsigned long           strbuf_control;
+        unsigned long           strbuf_pflush;
+        unsigned long           strbuf_fsync;
+        unsigned long           strbuf_ctxflush;
+        unsigned long           strbuf_ctxmatch_base;
+        unsigned long           strbuf_flushflag_pa;
+        volatile unsigned long *strbuf_flushflag;
+        volatile unsigned long  __flushflag_buf[(64+(64-1)) / sizeof(long)];
+};
+
+extern int iommu_table_init(struct iommu *iommu, int tsbsize,
+                            u32 dma_offset, u32 dma_addr_mask,
+                            int numa_node);
+
+#endif /* !(_SPARC64_IOMMU_H) */
diff --git a/arch/sparc/include/asm/ipcbuf.h b/arch/sparc/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..17d6ef7b23a4
--- /dev/null
+++ b/arch/sparc/include/asm/ipcbuf.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_IPCBUF_H
+#define ___ASM_SPARC_IPCBUF_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/ipcbuf_64.h>
+#else
+#include <asm/ipcbuf_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/ipcbuf_32.h b/arch/sparc/include/asm/ipcbuf_32.h
new file mode 100644
index 000000000000..6387209518f2
--- /dev/null
+++ b/arch/sparc/include/asm/ipcbuf_32.h
@@ -0,0 +1,31 @@
+#ifndef _SPARC_IPCBUF_H
+#define _SPARC_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values (so that this structure matches
+ *                                  sparc64 ipc64_perm)
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid32_t        uid;
+        __kernel_gid32_t        gid;
+        __kernel_uid32_t        cuid;
+        __kernel_gid32_t        cgid;
+        unsigned short          __pad1;
+        __kernel_mode_t         mode;
+        unsigned short          __pad2;
+        unsigned short          seq;
+        unsigned long long      __unused1;
+        unsigned long long      __unused2;
+};
+
+#endif /* _SPARC_IPCBUF_H */
diff --git a/arch/sparc/include/asm/ipcbuf_64.h b/arch/sparc/include/asm/ipcbuf_64.h
new file mode 100644
index 000000000000..a44b855b98db
--- /dev/null
+++ b/arch/sparc/include/asm/ipcbuf_64.h
@@ -0,0 +1,28 @@
+#ifndef _SPARC64_IPCBUF_H
+#define _SPARC64_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for sparc64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+        __kernel_mode_t mode;
+        unsigned short  __pad1;
+        unsigned short  seq;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _SPARC64_IPCBUF_H */
diff --git a/arch/sparc/include/asm/irq.h b/arch/sparc/include/asm/irq.h
new file mode 100644
index 000000000000..3b44a6a14074
--- /dev/null
+++ b/arch/sparc/include/asm/irq.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_IRQ_H
+#define ___ASM_SPARC_IRQ_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/irq_64.h>
+#else
+#include <asm/irq_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/irq_32.h b/arch/sparc/include/asm/irq_32.h
new file mode 100644
index 000000000000..fe205cc444b8
--- /dev/null
+++ b/arch/sparc/include/asm/irq_32.h
@@ -0,0 +1,15 @@
+/* irq.h: IRQ registers on the Sparc.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC_IRQ_H
+#define _SPARC_IRQ_H
+
+#include <linux/interrupt.h>
+
+#define NR_IRQS    16
+
+#define irq_canonicalize(irq)   (irq)
+
+#endif
diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
new file mode 100644
index 000000000000..3473e25231d9
--- /dev/null
+++ b/arch/sparc/include/asm/irq_64.h
@@ -0,0 +1,96 @@
+/* irq.h: IRQ registers on the 64-bit Sparc.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+#ifndef _SPARC64_IRQ_H
+#define _SPARC64_IRQ_H
+
+#include <linux/linkage.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <asm/pil.h>
+#include <asm/ptrace.h>
+
+/* IMAP/ICLR register defines */
+#define IMAP_VALID              0x80000000UL    /* IRQ Enabled          */
+#define IMAP_TID_UPA            0x7c000000UL    /* UPA TargetID         */
+#define IMAP_TID_JBUS           0x7c000000UL    /* JBUS TargetID        */
+#define IMAP_TID_SHIFT          26
+#define IMAP_AID_SAFARI         0x7c000000UL    /* Safari AgentID       */
+#define IMAP_AID_SHIFT          26
+#define IMAP_NID_SAFARI         0x03e00000UL    /* Safari NodeID        */
+#define IMAP_NID_SHIFT          21
+#define IMAP_IGN                0x000007c0UL    /* IRQ Group Number     */
+#define IMAP_INO                0x0000003fUL    /* IRQ Number           */
+#define IMAP_INR                0x000007ffUL    /* Full interrupt number*/
+
+#define ICLR_IDLE               0x00000000UL    /* Idle state           */
+#define ICLR_TRANSMIT           0x00000001UL    /* Transmit state       */
+#define ICLR_PENDING            0x00000003UL    /* Pending state        */
+
+/* The largest number of unique interrupt sources we support.
+ * If this needs to ever be larger than 255, you need to change
+ * the type of ino_bucket->virt_irq as appropriate.
+ *
+ * ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
+ */
+#define NR_IRQS    255
+
+extern void irq_install_pre_handler(int virt_irq,
+                                    void (*func)(unsigned int, void *, void *),
+                                    void *arg1, void *arg2);
+#define irq_canonicalize(irq)   (irq)
+extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
+extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
+extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino);
+extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
+                                    unsigned int msi_devino_start,
+                                    unsigned int msi_devino_end);
+extern void sun4v_destroy_msi(unsigned int virt_irq);
+extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
+                                    unsigned int msi_devino_start,
+                                    unsigned int msi_devino_end,
+                                    unsigned long imap_base,
+                                    unsigned long iclr_base);
+extern void sun4u_destroy_msi(unsigned int virt_irq);
+extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
+
+extern unsigned char virt_irq_alloc(unsigned int dev_handle,
+                                    unsigned int dev_ino);
+#ifdef CONFIG_PCI_MSI
+extern void virt_irq_free(unsigned int virt_irq);
+#endif
+
+extern void __init init_IRQ(void);
+extern void fixup_irqs(void);
+
+static inline void set_softint(unsigned long bits)
+{
+        __asm__ __volatile__("wr        %0, 0x0, %%set_softint"
+                             : /* No outputs */
+                             : "r" (bits));
+}
+
+static inline void clear_softint(unsigned long bits)
+{
+        __asm__ __volatile__("wr        %0, 0x0, %%clear_softint"
+                             : /* No outputs */
+                             : "r" (bits));
+}
+
+static inline unsigned long get_softint(void)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__("rd        %%softint, %0"
+                             : "=r" (retval));
+        return retval;
+}
+
+void __trigger_all_cpu_backtrace(void);
+#define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
+
+#endif
diff --git a/arch/sparc/include/asm/irq_regs.h b/arch/sparc/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/sparc/include/asm/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/arch/sparc/include/asm/irqflags.h b/arch/sparc/include/asm/irqflags.h
new file mode 100644
index 000000000000..1e138632bd3f
--- /dev/null
+++ b/arch/sparc/include/asm/irqflags.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_IRQFLAGS_H
+#define ___ASM_SPARC_IRQFLAGS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/irqflags_64.h>
+#else
+#include <asm/irqflags_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/irqflags_32.h b/arch/sparc/include/asm/irqflags_32.h
new file mode 100644
index 000000000000..0fca9d97d44f
--- /dev/null
+++ b/arch/sparc/include/asm/irqflags_32.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm/irqflags.h
+ *
+ * IRQ flags handling
+ *
+ * This file gets included from lowlevel asm headers too, to provide
+ * wrapped versions of the local_irq_*() APIs, based on the
+ * raw_local_irq_*() functions from the lowlevel headers.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+extern void raw_local_irq_restore(unsigned long);
+extern unsigned long __raw_local_irq_save(void);
+extern void raw_local_irq_enable(void);
+
+static inline unsigned long getipl(void)
+{
+        unsigned long retval;
+
+        __asm__ __volatile__("rd        %%psr, %0" : "=r" (retval));
+        return retval;
+}
+
+#define raw_local_save_flags(flags) ((flags) = getipl())
+#define raw_local_irq_save(flags)   ((flags) = __raw_local_irq_save())
+#define raw_local_irq_disable()     ((void) __raw_local_irq_save())
+#define raw_irqs_disabled()         ((getipl() & PSR_PIL) != 0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return ((flags & PSR_PIL) != 0);
+}
+
+#endif /* (__ASSEMBLY__) */
+
+#endif /* !(_ASM_IRQFLAGS_H) */
diff --git a/arch/sparc/include/asm/irqflags_64.h b/arch/sparc/include/asm/irqflags_64.h
new file mode 100644
index 000000000000..bb42e59162aa
--- /dev/null
+++ b/arch/sparc/include/asm/irqflags_64.h
@@ -0,0 +1,89 @@
+/*
+ * include/asm/irqflags.h
+ *
+ * IRQ flags handling
+ *
+ * This file gets included from lowlevel asm headers too, to provide
+ * wrapped versions of the local_irq_*() APIs, based on the
+ * raw_local_irq_*() functions from the lowlevel headers.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+        unsigned long flags;
+
+        __asm__ __volatile__(
+                "rdpr   %%pil, %0"
+                : "=r" (flags)
+        );
+
+        return flags;
+}
+
+#define raw_local_save_flags(flags) \
+                do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        __asm__ __volatile__(
+                "wrpr   %0, %%pil"
+                : /* no output */
+                : "r" (flags)
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+        __asm__ __volatile__(
+                "wrpr   15, %%pil"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline void raw_local_irq_enable(void)
+{
+        __asm__ __volatile__(
+                "wrpr   0, %%pil"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory"
+        );
+}
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+        return (flags > 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        return raw_irqs_disabled_flags(flags);
+}
+
+/*
+ * For spinlocks, etc:
+ */
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags = __raw_local_save_flags();
+
+        raw_local_irq_disable();
+
+        return flags;
+}
+
+#define raw_local_irq_save(flags) \
+                do { (flags) = __raw_local_irq_save(); } while (0)
+
+#endif /* (__ASSEMBLY__) */
+
+#endif /* !(_ASM_IRQFLAGS_H) */
diff --git a/arch/sparc/include/asm/jsflash.h b/arch/sparc/include/asm/jsflash.h
new file mode 100644
index 000000000000..3457f29bd73b
--- /dev/null
+++ b/arch/sparc/include/asm/jsflash.h
@@ -0,0 +1,39 @@
+/*
+ * jsflash.h: OS Flash SIMM support for JavaStations.
+ *
+ * Copyright (C) 1999  Pete Zaitcev
+ */
+
+#ifndef _SPARC_JSFLASH_H
+#define _SPARC_JSFLASH_H
+
+#ifndef _SPARC_TYPES_H
+#include <asm/types.h>
+#endif
+
+/*
+ * Semantics of the offset is a full address.
+ * Hardcode it or get it from probe ioctl.
+ *
+ * We use full bus address, so that we would be
+ * automatically compatible with possible future systems.
+ */
+
+#define JSFLASH_IDENT   (('F'<<8)|54)
+struct jsflash_ident_arg {
+        __u64 off;                /* 0x20000000 is included */
+        __u32 size;
+        char name[32];          /* With trailing zero */
+};
+
+#define JSFLASH_ERASE   (('F'<<8)|55)
+/* Put 0 as argument, may be flags or sector number... */
+
+#define JSFLASH_PROGRAM (('F'<<8)|56)
+struct jsflash_program_arg {
+        __u64 data;             /* char* for sparc and sparc64 */
+        __u64 off;
+        __u32 size;
+};
+
+#endif /* _SPARC_JSFLASH_H */
diff --git a/arch/sparc/include/asm/kdebug.h b/arch/sparc/include/asm/kdebug.h
new file mode 100644
index 000000000000..8d12581ca386
--- /dev/null
+++ b/arch/sparc/include/asm/kdebug.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_KDEBUG_H
+#define ___ASM_SPARC_KDEBUG_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/kdebug_64.h>
+#else
+#include <asm/kdebug_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/kdebug_32.h b/arch/sparc/include/asm/kdebug_32.h
new file mode 100644
index 000000000000..f69fe7d84b3c
--- /dev/null
+++ b/arch/sparc/include/asm/kdebug_32.h
@@ -0,0 +1,73 @@
+/*
+ * kdebug.h:  Defines and definitions for debugging the Linux kernel
+ *            under various kernel debuggers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_KDEBUG_H
+#define _SPARC_KDEBUG_H
+
+#include <asm/openprom.h>
+#include <asm/vaddrs.h>
+
+/* Breakpoints are enter through trap table entry 126.  So in sparc assembly
+ * if you want to drop into the debugger you do:
+ *
+ * t DEBUG_BP_TRAP
+ */
+
+#define DEBUG_BP_TRAP     126
+
+#ifndef __ASSEMBLY__
+/* The debug vector is passed in %o1 at boot time.  It is a pointer to
+ * a structure in the debuggers address space.  Here is its format.
+ */
+
+typedef unsigned int (*debugger_funct)(void);
+
+struct kernel_debug {
+        /* First the entry point into the debugger.  You jump here
+         * to give control over to the debugger.
+         */
+        unsigned long kdebug_entry;
+        unsigned long kdebug_trapme;   /* Figure out later... */
+        /* The following is the number of pages that the debugger has
+         * taken from to total pool.
+         */
+        unsigned long *kdebug_stolen_pages;
+        /* Ok, after you remap yourself and/or change the trap table
+         * from what you were left with at boot time you have to call
+         * this synchronization function so the debugger can check out
+         * what you have done.
+         */
+        debugger_funct teach_debugger;
+}; /* I think that is it... */
+
+extern struct kernel_debug *linux_dbvec;
+
+/* Use this macro in C-code to enter the debugger. */
+static inline void sp_enter_debugger(void)
+{
+        __asm__ __volatile__("jmpl %0, %%o7\n\t"
+                             "nop\n\t" : :
+                             "r" (linux_dbvec) : "o7", "memory");
+}
+
+#define SP_ENTER_DEBUGGER do { \
+             if((linux_dbvec!=0) && ((*(short *)linux_dbvec)!=-1)) \
+               sp_enter_debugger(); \
+                       } while(0)
+
+enum die_val {
+        DIE_UNUSED,
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+/* Some nice offset defines for assembler code. */
+#define KDEBUG_ENTRY_OFF    0x0
+#define KDEBUG_DUNNO_OFF    0x4
+#define KDEBUG_DUNNO2_OFF   0x8
+#define KDEBUG_TEACH_OFF    0xc
+
+#endif /* !(_SPARC_KDEBUG_H) */
diff --git a/arch/sparc/include/asm/kdebug_64.h b/arch/sparc/include/asm/kdebug_64.h
new file mode 100644
index 000000000000..f905b773235a
--- /dev/null
+++ b/arch/sparc/include/asm/kdebug_64.h
@@ -0,0 +1,19 @@
+#ifndef _SPARC64_KDEBUG_H
+#define _SPARC64_KDEBUG_H
+
+struct pt_regs;
+
+extern void bad_trap(struct pt_regs *, long);
+
+/* Grossly misnamed. */
+enum die_val {
+        DIE_OOPS = 1,
+        DIE_DEBUG,      /* ta 0x70 */
+        DIE_DEBUG_2,    /* ta 0x71 */
+        DIE_DIE,
+        DIE_TRAP,
+        DIE_TRAP_TL1,
+        DIE_CALL,
+};
+
+#endif
diff --git a/arch/sparc/include/asm/kgdb.h b/arch/sparc/include/asm/kgdb.h
new file mode 100644
index 000000000000..b6ef301d05bf
--- /dev/null
+++ b/arch/sparc/include/asm/kgdb.h
@@ -0,0 +1,38 @@
+#ifndef _SPARC_KGDB_H
+#define _SPARC_KGDB_H
+
+#ifdef CONFIG_SPARC32
+#define BUFMAX                  2048
+#else
+#define BUFMAX                  4096
+#endif
+
+enum regnames {
+        GDB_G0, GDB_G1, GDB_G2, GDB_G3, GDB_G4, GDB_G5, GDB_G6, GDB_G7,
+        GDB_O0, GDB_O1, GDB_O2, GDB_O3, GDB_O4, GDB_O5, GDB_SP, GDB_O7,
+        GDB_L0, GDB_L1, GDB_L2, GDB_L3, GDB_L4, GDB_L5, GDB_L6, GDB_L7,
+        GDB_I0, GDB_I1, GDB_I2, GDB_I3, GDB_I4, GDB_I5, GDB_FP, GDB_I7,
+        GDB_F0,
+        GDB_F31 = GDB_F0 + 31,
+#ifdef CONFIG_SPARC32
+        GDB_Y, GDB_PSR, GDB_WIM, GDB_TBR, GDB_PC, GDB_NPC,
+        GDB_FSR, GDB_CSR,
+#else
+        GDB_F32 = GDB_F0 + 32,
+        GDB_F62 = GDB_F32 + 15,
+        GDB_PC, GDB_NPC, GDB_STATE, GDB_FSR, GDB_FPRS, GDB_Y,
+#endif
+};
+
+#ifdef CONFIG_SPARC32
+#define NUMREGBYTES             ((GDB_CSR + 1) * 4)
+#else
+#define NUMREGBYTES             ((GDB_Y + 1) * 8)
+#endif
+
+extern void arch_kgdb_breakpoint(void);
+
+#define BREAK_INSTR_SIZE        4
+#define CACHE_FLUSH_IS_SAFE     1
+
+#endif /* _SPARC_KGDB_H */
diff --git a/arch/sparc/include/asm/kmap_types.h b/arch/sparc/include/asm/kmap_types.h
new file mode 100644
index 000000000000..602f5e034f7a
--- /dev/null
+++ b/arch/sparc/include/asm/kmap_types.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+/* Dummy header just to define km_type.  None of this
+ * is actually used on sparc.  -DaveM
+ */
+
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
+        KM_TYPE_NR
+};
+
+#endif
diff --git a/arch/sparc/include/asm/kprobes.h b/arch/sparc/include/asm/kprobes.h
new file mode 100644
index 000000000000..5879d71afdaa
--- /dev/null
+++ b/arch/sparc/include/asm/kprobes.h
@@ -0,0 +1,49 @@
+#ifndef _SPARC64_KPROBES_H
+#define _SPARC64_KPROBES_H
+
+#include <linux/types.h>
+#include <linux/percpu.h>
+
+typedef u32 kprobe_opcode_t;
+
+#define BREAKPOINT_INSTRUCTION   0x91d02070 /* ta 0x70 */
+#define BREAKPOINT_INSTRUCTION_2 0x91d02071 /* ta 0x71 */
+#define MAX_INSN_SIZE 2
+
+#define kretprobe_blacklist_size 0
+
+#define arch_remove_kprobe(p)   do {} while (0)
+
+#define flush_insn_slot(p)              \
+do {    flushi(&(p)->ainsn.insn[0]);    \
+        flushi(&(p)->ainsn.insn[1]);    \
+} while (0)
+
+void kretprobe_trampoline(void);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the original instruction */
+        kprobe_opcode_t insn[MAX_INSN_SIZE];
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+        unsigned long orig_tnpc;
+        unsigned long orig_tstate_pil;
+};
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long kprobe_orig_tnpc;
+        unsigned long kprobe_orig_tstate_pil;
+        struct pt_regs jprobe_saved_regs;
+        struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
+#endif /* _SPARC64_KPROBES_H */
diff --git a/arch/sparc/include/asm/ldc.h b/arch/sparc/include/asm/ldc.h
new file mode 100644
index 000000000000..bdb524a7b814
--- /dev/null
+++ b/arch/sparc/include/asm/ldc.h
@@ -0,0 +1,138 @@
+#ifndef _SPARC64_LDC_H
+#define _SPARC64_LDC_H
+
+#include <asm/hypervisor.h>
+
+extern int ldom_domaining_enabled;
+extern void ldom_set_var(const char *var, const char *value);
+extern void ldom_reboot(const char *boot_command);
+extern void ldom_power_off(void);
+
+/* The event handler will be evoked when link state changes
+ * or data becomes available on the receive side.
+ *
+ * For non-RAW links, if the LDC_EVENT_RESET event arrives the
+ * driver should reset all of it's internal state and reinvoke
+ * ldc_connect() to try and bring the link up again.
+ *
+ * For RAW links, ldc_connect() is not used.  Instead the driver
+ * just waits for the LDC_EVENT_UP event.
+ */
+struct ldc_channel_config {
+        void (*event)(void *arg, int event);
+
+        u32                     mtu;
+        unsigned int            rx_irq;
+        unsigned int            tx_irq;
+        u8                      mode;
+#define LDC_MODE_RAW            0x00
+#define LDC_MODE_UNRELIABLE     0x01
+#define LDC_MODE_RESERVED       0x02
+#define LDC_MODE_STREAM         0x03
+
+        u8                      debug;
+#define LDC_DEBUG_HS            0x01
+#define LDC_DEBUG_STATE         0x02
+#define LDC_DEBUG_RX            0x04
+#define LDC_DEBUG_TX            0x08
+#define LDC_DEBUG_DATA          0x10
+};
+
+#define LDC_EVENT_RESET         0x01
+#define LDC_EVENT_UP            0x02
+#define LDC_EVENT_DATA_READY    0x04
+
+#define LDC_STATE_INVALID       0x00
+#define LDC_STATE_INIT          0x01
+#define LDC_STATE_BOUND         0x02
+#define LDC_STATE_READY         0x03
+#define LDC_STATE_CONNECTED     0x04
+
+struct ldc_channel;
+
+/* Allocate state for a channel.  */
+extern struct ldc_channel *ldc_alloc(unsigned long id,
+                                     const struct ldc_channel_config *cfgp,
+                                     void *event_arg);
+
+/* Shut down and free state for a channel.  */
+extern void ldc_free(struct ldc_channel *lp);
+
+/* Register TX and RX queues of the link with the hypervisor.  */
+extern int ldc_bind(struct ldc_channel *lp, const char *name);
+
+/* For non-RAW protocols we need to complete a handshake before
+ * communication can proceed.  ldc_connect() does that, if the
+ * handshake completes successfully, an LDC_EVENT_UP event will
+ * be sent up to the driver.
+ */
+extern int ldc_connect(struct ldc_channel *lp);
+extern int ldc_disconnect(struct ldc_channel *lp);
+
+extern int ldc_state(struct ldc_channel *lp);
+
+/* Read and write operations.  Only valid when the link is up.  */
+extern int ldc_write(struct ldc_channel *lp, const void *buf,
+                     unsigned int size);
+extern int ldc_read(struct ldc_channel *lp, void *buf, unsigned int size);
+
+#define LDC_MAP_SHADOW  0x01
+#define LDC_MAP_DIRECT  0x02
+#define LDC_MAP_IO      0x04
+#define LDC_MAP_R       0x08
+#define LDC_MAP_W       0x10
+#define LDC_MAP_X       0x20
+#define LDC_MAP_RW      (LDC_MAP_R | LDC_MAP_W)
+#define LDC_MAP_RWX     (LDC_MAP_R | LDC_MAP_W | LDC_MAP_X)
+#define LDC_MAP_ALL     0x03f
+
+struct ldc_trans_cookie {
+        u64                     cookie_addr;
+        u64                     cookie_size;
+};
+
+struct scatterlist;
+extern int ldc_map_sg(struct ldc_channel *lp,
+                      struct scatterlist *sg, int num_sg,
+                      struct ldc_trans_cookie *cookies, int ncookies,
+                      unsigned int map_perm);
+
+extern int ldc_map_single(struct ldc_channel *lp,
+                          void *buf, unsigned int len,
+                          struct ldc_trans_cookie *cookies, int ncookies,
+                          unsigned int map_perm);
+
+extern void ldc_unmap(struct ldc_channel *lp, struct ldc_trans_cookie *cookies,
+                      int ncookies);
+
+extern int ldc_copy(struct ldc_channel *lp, int copy_dir,
+                    void *buf, unsigned int len, unsigned long offset,
+                    struct ldc_trans_cookie *cookies, int ncookies);
+
+static inline int ldc_get_dring_entry(struct ldc_channel *lp,
+                                      void *buf, unsigned int len,
+                                      unsigned long offset,
+                                      struct ldc_trans_cookie *cookies,
+                                      int ncookies)
+{
+        return ldc_copy(lp, LDC_COPY_IN, buf, len, offset, cookies, ncookies);
+}
+
+static inline int ldc_put_dring_entry(struct ldc_channel *lp,
+                                      void *buf, unsigned int len,
+                                      unsigned long offset,
+                                      struct ldc_trans_cookie *cookies,
+                                      int ncookies)
+{
+        return ldc_copy(lp, LDC_COPY_OUT, buf, len, offset, cookies, ncookies);
+}
+
+extern void *ldc_alloc_exp_dring(struct ldc_channel *lp, unsigned int len,
+                                 struct ldc_trans_cookie *cookies,
+                                 int *ncookies, unsigned int map_perm);
+
+extern void ldc_free_exp_dring(struct ldc_channel *lp, void *buf,
+                               unsigned int len,
+                               struct ldc_trans_cookie *cookies, int ncookies);
+
+#endif /* _SPARC64_LDC_H */
diff --git a/arch/sparc/include/asm/linkage.h b/arch/sparc/include/asm/linkage.h
new file mode 100644
index 000000000000..291c2d01c44f
--- /dev/null
+++ b/arch/sparc/include/asm/linkage.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* Nothing to see here... */
+
+#endif
diff --git a/arch/sparc/include/asm/lmb.h b/arch/sparc/include/asm/lmb.h
new file mode 100644
index 000000000000..6a352cbcf520
--- /dev/null
+++ b/arch/sparc/include/asm/lmb.h
@@ -0,0 +1,10 @@
+#ifndef _SPARC64_LMB_H
+#define _SPARC64_LMB_H
+
+#include <asm/oplib.h>
+
+#define LMB_DBG(fmt...) prom_printf(fmt)
+
+#define LMB_REAL_LIMIT  0
+
+#endif /* !(_SPARC64_LMB_H) */
diff --git a/arch/sparc/include/asm/local.h b/arch/sparc/include/asm/local.h
new file mode 100644
index 000000000000..bc80815a435c
--- /dev/null
+++ b/arch/sparc/include/asm/local.h
@@ -0,0 +1,6 @@
+#ifndef _SPARC_LOCAL_H
+#define _SPARC_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif
diff --git a/arch/sparc/include/asm/lsu.h b/arch/sparc/include/asm/lsu.h
new file mode 100644
index 000000000000..7190f8de90a0
--- /dev/null
+++ b/arch/sparc/include/asm/lsu.h
@@ -0,0 +1,19 @@
+#ifndef _SPARC64_LSU_H
+#define _SPARC64_LSU_H
+
+#include <linux/const.h>
+
+/* LSU Control Register */
+#define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
+#define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
+#define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
+#define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
+#define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
+#define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
+#define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables.     */
+#define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable.         */
+#define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable.  */
+#define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable.       */
+#define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
+
+#endif /* !(_SPARC64_LSU_H) */
diff --git a/arch/sparc/include/asm/machines.h b/arch/sparc/include/asm/machines.h
new file mode 100644
index 000000000000..c28c2f248794
--- /dev/null
+++ b/arch/sparc/include/asm/machines.h
@@ -0,0 +1,67 @@
+/*
+ * machines.h:  Defines for taking apart the machine type value in the
+ *              idprom and determining the kind of machine we are on.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_MACHINES_H
+#define _SPARC_MACHINES_H
+
+struct Sun_Machine_Models {
+        char *name;
+        unsigned char id_machtype;
+};
+
+/* Current number of machines we know about that has an IDPROM
+ * machtype entry including one entry for the 0x80 OBP machines.
+ */
+#define NUM_SUN_MACHINES   15
+
+/* The machine type in the idprom area looks like this:
+ *
+ * ---------------
+ * | ARCH | MACH |
+ * ---------------
+ *  7    4 3    0
+ *
+ * The ARCH field determines the architecture line (sun4, sun4c, etc).
+ * The MACH field determines the machine make within that architecture.
+ */
+
+#define SM_ARCH_MASK  0xf0
+#define SM_SUN4       0x20
+#define SM_SUN4C      0x50
+#define SM_SUN4M      0x70
+#define SM_SUN4M_OBP  0x80
+
+#define SM_TYP_MASK   0x0f
+/* Sun4 machines */
+#define SM_4_260      0x01    /* Sun 4/200 series */
+#define SM_4_110      0x02    /* Sun 4/100 series */
+#define SM_4_330      0x03    /* Sun 4/300 series */
+#define SM_4_470      0x04    /* Sun 4/400 series */
+
+/* Sun4c machines                Full Name              - PROM NAME */
+#define SM_4C_SS1     0x01    /* Sun4c SparcStation 1   - Sun 4/60  */
+#define SM_4C_IPC     0x02    /* Sun4c SparcStation IPC - Sun 4/40  */
+#define SM_4C_SS1PLUS 0x03    /* Sun4c SparcStation 1+  - Sun 4/65  */
+#define SM_4C_SLC     0x04    /* Sun4c SparcStation SLC - Sun 4/20  */
+#define SM_4C_SS2     0x05    /* Sun4c SparcStation 2   - Sun 4/75  */
+#define SM_4C_ELC     0x06    /* Sun4c SparcStation ELC - Sun 4/25  */
+#define SM_4C_IPX     0x07    /* Sun4c SparcStation IPX - Sun 4/50  */
+
+/* Sun4m machines, these predate the OpenBoot.  These values only mean
+ * something if the value in the ARCH field is SM_SUN4M, if it is
+ * SM_SUN4M_OBP then you have the following situation:
+ * 1) You either have a sun4d, a sun4e, or a recently made sun4m.
+ * 2) You have to consult OpenBoot to determine which machine this is.
+ */
+#define SM_4M_SS60    0x01    /* Sun4m SparcSystem 600                  */
+#define SM_4M_SS50    0x02    /* Sun4m SparcStation 10                  */
+#define SM_4M_SS40    0x03    /* Sun4m SparcStation 5                   */
+
+/* Sun4d machines -- N/A */
+/* Sun4e machines -- N/A */
+/* Sun4u machines -- N/A */
+
+#endif /* !(_SPARC_MACHINES_H) */
diff --git a/arch/sparc/include/asm/mbus.h b/arch/sparc/include/asm/mbus.h
new file mode 100644
index 000000000000..69f07a022ee6
--- /dev/null
+++ b/arch/sparc/include/asm/mbus.h
@@ -0,0 +1,100 @@
+/*
+ * mbus.h:  Various defines for MBUS modules.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_MBUS_H
+#define _SPARC_MBUS_H
+
+#include <asm/ross.h>    /* HyperSparc stuff */
+#include <asm/cypress.h> /* Cypress Chips */
+#include <asm/viking.h>  /* Ugh, bug city... */
+
+enum mbus_module {
+        HyperSparc        = 0,
+        Cypress           = 1,
+        Cypress_vE        = 2,
+        Cypress_vD        = 3,
+        Swift_ok          = 4,
+        Swift_bad_c       = 5,
+        Swift_lots_o_bugs = 6,
+        Tsunami           = 7,
+        Viking_12         = 8,
+        Viking_2x         = 9,
+        Viking_30         = 10,
+        Viking_35         = 11,
+        Viking_new        = 12,
+        TurboSparc        = 13,
+        SRMMU_INVAL_MOD   = 14,
+};
+
+extern enum mbus_module srmmu_modtype;
+extern unsigned int viking_rev, swift_rev, cypress_rev;
+
+/* HW Mbus module bugs we have to deal with */
+#define HWBUG_COPYBACK_BROKEN        0x00000001
+#define HWBUG_ASIFLUSH_BROKEN        0x00000002
+#define HWBUG_VACFLUSH_BITROT        0x00000004
+#define HWBUG_KERN_ACCBROKEN         0x00000008
+#define HWBUG_KERN_CBITBROKEN        0x00000010
+#define HWBUG_MODIFIED_BITROT        0x00000020
+#define HWBUG_PC_BADFAULT_ADDR       0x00000040
+#define HWBUG_SUPERSCALAR_BAD        0x00000080
+#define HWBUG_PACINIT_BITROT         0x00000100
+
+/* First the module type values. To find out which you have, just load
+ * the mmu control register from ASI_M_MMUREG alternate address space and
+ * shift the value right 28 bits.
+ */
+/* IMPL field means the company which produced the chip. */
+#define MBUS_VIKING        0x4   /* bleech, Texas Instruments Module */
+#define MBUS_LSI           0x3   /* LSI Logics */
+#define MBUS_ROSS          0x1   /* Ross is nice */
+#define MBUS_FMI           0x0   /* Fujitsu Microelectronics/Swift */
+
+/* Ross Module versions */
+#define ROSS_604_REV_CDE        0x0   /* revisions c, d, and e */
+#define ROSS_604_REV_F          0x1   /* revision f */
+#define ROSS_605                0xf   /* revision a, a.1, and a.2 */
+#define ROSS_605_REV_B          0xe   /* revision b */
+
+/* TI Viking Module versions */
+#define VIKING_REV_12           0x1   /* Version 1.2 or SPARCclassic's CPU */
+#define VIKING_REV_2            0x2   /* Version 2.1, 2.2, 2.3, and 2.4 */
+#define VIKING_REV_30           0x3   /* Version 3.0 */
+#define VIKING_REV_35           0x4   /* Version 3.5 */
+
+/* LSI Logics. */
+#define LSI_L64815              0x0
+
+/* Fujitsu */
+#define FMI_AURORA              0x4   /* MB8690x, a Swift module... */
+#define FMI_TURBO               0x5   /* MB86907, a TurboSparc module... */
+
+/* For multiprocessor support we need to be able to obtain the CPU id and
+ * the MBUS Module id.
+ */
+
+/* The CPU ID is encoded in the trap base register, 20 bits to the left of
+ * bit zero, with 2 bits being significant.
+ */
+#define TBR_ID_SHIFT            20
+
+static inline int get_cpuid(void)
+{
+        register int retval;
+        __asm__ __volatile__("rd %%tbr, %0\n\t"
+                             "srl %0, %1, %0\n\t" :
+                             "=r" (retval) :
+                             "i" (TBR_ID_SHIFT));
+        return (retval & 3);
+}
+
+static inline int get_modid(void)
+{
+        return (get_cpuid() | 0x8);
+}
+
+        
+#endif /* !(_SPARC_MBUS_H) */
diff --git a/arch/sparc/include/asm/mc146818rtc.h b/arch/sparc/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..67ed9e3a0235
--- /dev/null
+++ b/arch/sparc/include/asm/mc146818rtc.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_MC146818RTC_H
+#define ___ASM_SPARC_MC146818RTC_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mc146818rtc_64.h>
+#else
+#include <asm/mc146818rtc_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/mc146818rtc_32.h b/arch/sparc/include/asm/mc146818rtc_32.h
new file mode 100644
index 000000000000..fa7eac926582
--- /dev/null
+++ b/arch/sparc/include/asm/mc146818rtc_32.h
@@ -0,0 +1,29 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_SPARC_MC146818RTC_H
+#define __ASM_SPARC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_ALWAYS_BCD  1       /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#define RTC_IRQ 8
+
+#endif /* __ASM_SPARC_MC146818RTC_H */
diff --git a/arch/sparc/include/asm/mc146818rtc_64.h b/arch/sparc/include/asm/mc146818rtc_64.h
new file mode 100644
index 000000000000..e9c0fcc25c6f
--- /dev/null
+++ b/arch/sparc/include/asm/mc146818rtc_64.h
@@ -0,0 +1,34 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_SPARC64_MC146818RTC_H
+#define __ASM_SPARC64_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#ifdef CONFIG_PCI
+extern unsigned long ds1287_regs;
+#else
+#define ds1287_regs (0UL)
+#endif
+#define RTC_PORT(x)     (ds1287_regs + (x))
+#define RTC_ALWAYS_BCD  0
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#define RTC_IRQ 8
+
+#endif /* __ASM_SPARC64_MC146818RTC_H */
diff --git a/arch/sparc/include/asm/mdesc.h b/arch/sparc/include/asm/mdesc.h
new file mode 100644
index 000000000000..1acc7272e537
--- /dev/null
+++ b/arch/sparc/include/asm/mdesc.h
@@ -0,0 +1,78 @@
+#ifndef _SPARC64_MDESC_H
+#define _SPARC64_MDESC_H
+
+#include <linux/types.h>
+#include <linux/cpumask.h>
+#include <asm/prom.h>
+
+struct mdesc_handle;
+
+/* Machine description operations are to be surrounded by grab and
+ * release calls.  The mdesc_handle returned from the grab is
+ * the first argument to all of the operational calls that work
+ * on mdescs.
+ */
+extern struct mdesc_handle *mdesc_grab(void);
+extern void mdesc_release(struct mdesc_handle *);
+
+#define MDESC_NODE_NULL         (~(u64)0)
+
+extern u64 mdesc_node_by_name(struct mdesc_handle *handle,
+                              u64 from_node, const char *name);
+#define mdesc_for_each_node_by_name(__hdl, __node, __name) \
+        for (__node = mdesc_node_by_name(__hdl, MDESC_NODE_NULL, __name); \
+             (__node) != MDESC_NODE_NULL; \
+             __node = mdesc_node_by_name(__hdl, __node, __name))
+
+/* Access to property values returned from mdesc_get_property() are
+ * only valid inside of a mdesc_grab()/mdesc_release() sequence.
+ * Once mdesc_release() is called, the memory backed up by these
+ * pointers may reference freed up memory.
+ *
+ * Therefore callers must make copies of any property values
+ * they need.
+ *
+ * These same rules apply to mdesc_node_name().
+ */
+extern const void *mdesc_get_property(struct mdesc_handle *handle,
+                                      u64 node, const char *name, int *lenp);
+extern const char *mdesc_node_name(struct mdesc_handle *hp, u64 node);
+
+/* MD arc iteration, the standard sequence is:
+ *
+ *      unsigned long arc;
+ *      mdesc_for_each_arc(arc, handle, node, MDESC_ARC_TYPE_{FWD,BACK}) {
+ *              unsigned long target = mdesc_arc_target(handle, arc);
+ *              ...
+ *      }
+ */
+
+#define MDESC_ARC_TYPE_FWD      "fwd"
+#define MDESC_ARC_TYPE_BACK     "back"
+
+extern u64 mdesc_next_arc(struct mdesc_handle *handle, u64 from,
+                          const char *arc_type);
+#define mdesc_for_each_arc(__arc, __hdl, __node, __type) \
+        for (__arc = mdesc_next_arc(__hdl, __node, __type); \
+             (__arc) != MDESC_NODE_NULL; \
+             __arc = mdesc_next_arc(__hdl, __arc, __type))
+
+extern u64 mdesc_arc_target(struct mdesc_handle *hp, u64 arc);
+
+extern void mdesc_update(void);
+
+struct mdesc_notifier_client {
+        void (*add)(struct mdesc_handle *handle, u64 node);
+        void (*remove)(struct mdesc_handle *handle, u64 node);
+
+        const char                      *node_name;
+        struct mdesc_notifier_client    *next;
+};
+
+extern void mdesc_register_notifier(struct mdesc_notifier_client *client);
+
+extern void mdesc_fill_in_cpu_data(cpumask_t mask);
+
+extern void sun4v_mdesc_init(void);
+
+#endif
diff --git a/arch/sparc/include/asm/memreg.h b/arch/sparc/include/asm/memreg.h
new file mode 100644
index 000000000000..845ad2b39183
--- /dev/null
+++ b/arch/sparc/include/asm/memreg.h
@@ -0,0 +1,51 @@
+#ifndef _SPARC_MEMREG_H
+#define _SPARC_MEMREG_H
+/* memreg.h:  Definitions of the values found in the synchronous
+ *            and asynchronous memory error registers when a fault
+ *            occurs on the sun4c.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* First the synchronous error codes, these are usually just
+ * normal page faults.
+ */
+
+#define SUN4C_SYNC_WDRESET   0x0001  /* watchdog reset */
+#define SUN4C_SYNC_SIZE      0x0002  /* bad access size? whuz this? */
+#define SUN4C_SYNC_PARITY    0x0008  /* bad ram chips caused a parity error */
+#define SUN4C_SYNC_SBUS      0x0010  /* the SBUS had some problems... */
+#define SUN4C_SYNC_NOMEM     0x0020  /* translation to non-existent ram */
+#define SUN4C_SYNC_PROT      0x0040  /* access violated pte protections */
+#define SUN4C_SYNC_NPRESENT  0x0080  /* pte said that page was not present */
+#define SUN4C_SYNC_BADWRITE  0x8000  /* while writing something went bogus */
+
+#define SUN4C_SYNC_BOLIXED  \
+        (SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \
+         SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY)
+
+/* Now the asynchronous error codes, these are almost always produced
+ * by the cache writing things back to memory and getting a bad translation.
+ * Bad DVMA transactions can cause these faults too.
+ */
+
+#define SUN4C_ASYNC_BADDVMA 0x0010  /* error during DVMA access */
+#define SUN4C_ASYNC_NOMEM   0x0020  /* write back pointed to bad phys addr */
+#define SUN4C_ASYNC_BADWB   0x0080  /* write back points to non-present page */
+
+/* Memory parity error register with associated bit constants. */
+#ifndef __ASSEMBLY__
+extern __volatile__ unsigned long __iomem *sun4c_memerr_reg;
+#endif
+
+#define SUN4C_MPE_ERROR 0x80    /* Parity error detected. (ro) */
+#define SUN4C_MPE_MULTI 0x40    /* Multiple parity errors detected. (ro) */
+#define SUN4C_MPE_TEST  0x20    /* Write inverse parity. (rw) */
+#define SUN4C_MPE_CHECK 0x10    /* Enable parity checking. (rw) */
+#define SUN4C_MPE_ERR00 0x08    /* Parity error in bits 0-7. (ro) */
+#define SUN4C_MPE_ERR08 0x04    /* Parity error in bits 8-15. (ro) */
+#define SUN4C_MPE_ERR16 0x02    /* Parity error in bits 16-23. (ro) */
+#define SUN4C_MPE_ERR24 0x01    /* Parity error in bits 24-31. (ro) */
+#define SUN4C_MPE_ERRS  0x0F    /* Bit mask for the error bits. (ro) */
+
+#endif /* !(_SPARC_MEMREG_H) */
diff --git a/arch/sparc/include/asm/mman.h b/arch/sparc/include/asm/mman.h
new file mode 100644
index 000000000000..fdfbbf0a4736
--- /dev/null
+++ b/arch/sparc/include/asm/mman.h
@@ -0,0 +1,31 @@
+#ifndef __SPARC_MMAN_H__
+#define __SPARC_MMAN_H__
+
+#include <asm-generic/mman.h>
+
+/* SunOS'ified... */
+
+#define MAP_RENAME      MAP_ANONYMOUS   /* In SunOS terminology */
+#define MAP_NORESERVE   0x40            /* don't reserve swap pages */
+#define MAP_INHERIT     0x80            /* SunOS doesn't do this, but... */
+#define MAP_LOCKED      0x100           /* lock the mapping */
+#define _MAP_NEW        0x80000000      /* Binary compatibility is fun... */
+
+#define MAP_GROWSDOWN   0x0200          /* stack-like segment */
+#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
+
+#define MCL_CURRENT     0x2000          /* lock all currently mapped pages */
+#define MCL_FUTURE      0x4000          /* lock all additions to address space */
+
+#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len)
+int sparc_mmap_check(unsigned long addr, unsigned long len);
+#endif
+#endif
+
+#endif /* __SPARC_MMAN_H__ */
diff --git a/arch/sparc/include/asm/mmu.h b/arch/sparc/include/asm/mmu.h
new file mode 100644
index 000000000000..88fa313887db
--- /dev/null
+++ b/arch/sparc/include/asm/mmu.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_MMU_H
+#define ___ASM_SPARC_MMU_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mmu_64.h>
+#else
+#include <asm/mmu_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/mmu_32.h b/arch/sparc/include/asm/mmu_32.h
new file mode 100644
index 000000000000..ccd36d26615a
--- /dev/null
+++ b/arch/sparc/include/asm/mmu_32.h
@@ -0,0 +1,7 @@
+#ifndef __MMU_H
+#define __MMU_H
+
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_t;
+
+#endif
diff --git a/arch/sparc/include/asm/mmu_64.h b/arch/sparc/include/asm/mmu_64.h
new file mode 100644
index 000000000000..9067dc500535
--- /dev/null
+++ b/arch/sparc/include/asm/mmu_64.h
@@ -0,0 +1,123 @@
+#ifndef __MMU_H
+#define __MMU_H
+
+#include <linux/const.h>
+#include <asm/page.h>
+#include <asm/hypervisor.h>
+
+#define CTX_NR_BITS             13
+
+#define TAG_CONTEXT_BITS        ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
+
+/* UltraSPARC-III+ and later have a feature whereby you can
+ * select what page size the various Data-TLB instances in the
+ * chip.  In order to gracefully support this, we put the version
+ * field in a spot outside of the areas of the context register
+ * where this parameter is specified.
+ */
+#define CTX_VERSION_SHIFT       22
+#define CTX_VERSION_MASK        ((~0UL) << CTX_VERSION_SHIFT)
+
+#define CTX_PGSZ_8KB            _AC(0x0,UL)
+#define CTX_PGSZ_64KB           _AC(0x1,UL)
+#define CTX_PGSZ_512KB          _AC(0x2,UL)
+#define CTX_PGSZ_4MB            _AC(0x3,UL)
+#define CTX_PGSZ_BITS           _AC(0x7,UL)
+#define CTX_PGSZ0_NUC_SHIFT     61
+#define CTX_PGSZ1_NUC_SHIFT     58
+#define CTX_PGSZ0_SHIFT         16
+#define CTX_PGSZ1_SHIFT         19
+#define CTX_PGSZ_MASK           ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
+                                 (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
+
+#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
+#define CTX_PGSZ_BASE   CTX_PGSZ_8KB
+#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
+#define CTX_PGSZ_BASE   CTX_PGSZ_64KB
+#else
+#error No page size specified in kernel configuration
+#endif
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define CTX_PGSZ_HUGE           CTX_PGSZ_4MB
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
+#define CTX_PGSZ_HUGE           CTX_PGSZ_512KB
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define CTX_PGSZ_HUGE           CTX_PGSZ_64KB
+#endif
+
+#define CTX_PGSZ_KERN   CTX_PGSZ_4MB
+
+/* Thus, when running on UltraSPARC-III+ and later, we use the following
+ * PRIMARY_CONTEXT register values for the kernel context.
+ */
+#define CTX_CHEETAH_PLUS_NUC \
+        ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
+         (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
+
+#define CTX_CHEETAH_PLUS_CTX0 \
+        ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
+         (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
+
+/* If you want "the TLB context number" use CTX_NR_MASK.  If you
+ * want "the bits I program into the context registers" use
+ * CTX_HW_MASK.
+ */
+#define CTX_NR_MASK             TAG_CONTEXT_BITS
+#define CTX_HW_MASK             (CTX_NR_MASK | CTX_PGSZ_MASK)
+
+#define CTX_FIRST_VERSION       ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
+#define CTX_VALID(__ctx)        \
+         (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
+#define CTX_HWBITS(__ctx)       ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
+#define CTX_NRBITS(__ctx)       ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
+
+#ifndef __ASSEMBLY__
+
+#define TSB_ENTRY_ALIGNMENT     16
+
+struct tsb {
+        unsigned long tag;
+        unsigned long pte;
+} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
+
+extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
+extern void tsb_flush(unsigned long ent, unsigned long tag);
+extern void tsb_init(struct tsb *tsb, unsigned long size);
+
+struct tsb_config {
+        struct tsb              *tsb;
+        unsigned long           tsb_rss_limit;
+        unsigned long           tsb_nentries;
+        unsigned long           tsb_reg_val;
+        unsigned long           tsb_map_vaddr;
+        unsigned long           tsb_map_pte;
+};
+
+#define MM_TSB_BASE     0
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define MM_TSB_HUGE     1
+#define MM_NUM_TSBS     2
+#else
+#define MM_NUM_TSBS     1
+#endif
+
+typedef struct {
+        spinlock_t              lock;
+        unsigned long           sparc64_ctx_val;
+        unsigned long           huge_pte_count;
+        struct tsb_config       tsb_block[MM_NUM_TSBS];
+        struct hv_tsb_descr     tsb_descr[MM_NUM_TSBS];
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#define TSB_CONFIG_TSB          0x00
+#define TSB_CONFIG_RSS_LIMIT    0x08
+#define TSB_CONFIG_NENTRIES     0x10
+#define TSB_CONFIG_REG_VAL      0x18
+#define TSB_CONFIG_MAP_VADDR    0x20
+#define TSB_CONFIG_MAP_PTE      0x28
+
+#endif /* __MMU_H */
diff --git a/arch/sparc/include/asm/mmu_context.h b/arch/sparc/include/asm/mmu_context.h
new file mode 100644
index 000000000000..5531346c64f9
--- /dev/null
+++ b/arch/sparc/include/asm/mmu_context.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_MMU_CONTEXT_H
+#define ___ASM_SPARC_MMU_CONTEXT_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mmu_context_64.h>
+#else
+#include <asm/mmu_context_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/mmu_context_32.h b/arch/sparc/include/asm/mmu_context_32.h
new file mode 100644
index 000000000000..671a997b9e69
--- /dev/null
+++ b/arch/sparc/include/asm/mmu_context_32.h
@@ -0,0 +1,42 @@
+#ifndef __SPARC_MMU_CONTEXT_H
+#define __SPARC_MMU_CONTEXT_H
+
+#include <asm/btfixup.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm-generic/mm_hooks.h>
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/*
+ * Initialize a new mmu context.  This is invoked when a new
+ * address space instance (unique or shared) is instantiated.
+ */
+#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
+
+/*
+ * Destroy a dead context.  This occurs when mmput drops the
+ * mm_users count to zero, the mmaps have been released, and
+ * all the page tables have been flushed.  Our job is to destroy
+ * any remaining processor-specific state.
+ */
+BTFIXUPDEF_CALL(void, destroy_context, struct mm_struct *)
+
+#define destroy_context(mm) BTFIXUP_CALL(destroy_context)(mm)
+
+/* Switch the current MM context. */
+BTFIXUPDEF_CALL(void, switch_mm, struct mm_struct *, struct mm_struct *, struct task_struct *)
+
+#define switch_mm(old_mm, mm, tsk) BTFIXUP_CALL(switch_mm)(old_mm, mm, tsk)
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+/* Activate a new MM instance for the current task. */
+#define activate_mm(active_mm, mm) switch_mm((active_mm), (mm), NULL)
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC_MMU_CONTEXT_H) */
diff --git a/arch/sparc/include/asm/mmu_context_64.h b/arch/sparc/include/asm/mmu_context_64.h
new file mode 100644
index 000000000000..5693ab482606
--- /dev/null
+++ b/arch/sparc/include/asm/mmu_context_64.h
@@ -0,0 +1,155 @@
+#ifndef __SPARC64_MMU_CONTEXT_H
+#define __SPARC64_MMU_CONTEXT_H
+
+/* Derived heavily from Linus's Alpha/AXP ASN code... */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/spinlock.h>
+#include <asm/system.h>
+#include <asm/spitfire.h>
+#include <asm-generic/mm_hooks.h>
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+extern spinlock_t ctx_alloc_lock;
+extern unsigned long tlb_context_cache;
+extern unsigned long mmu_context_bmap[];
+
+extern void get_new_mmu_context(struct mm_struct *mm);
+#ifdef CONFIG_SMP
+extern void smp_new_mmu_context_version(void);
+#else
+#define smp_new_mmu_context_version() do { } while (0)
+#endif
+
+extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
+extern void destroy_context(struct mm_struct *mm);
+
+extern void __tsb_context_switch(unsigned long pgd_pa,
+                                 struct tsb_config *tsb_base,
+                                 struct tsb_config *tsb_huge,
+                                 unsigned long tsb_descr_pa);
+
+static inline void tsb_context_switch(struct mm_struct *mm)
+{
+        __tsb_context_switch(__pa(mm->pgd),
+                             &mm->context.tsb_block[0],
+#ifdef CONFIG_HUGETLB_PAGE
+                             (mm->context.tsb_block[1].tsb ?
+                              &mm->context.tsb_block[1] :
+                              NULL)
+#else
+                             NULL
+#endif
+                             , __pa(&mm->context.tsb_descr[0]));
+}
+
+extern void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long mm_rss);
+#ifdef CONFIG_SMP
+extern void smp_tsb_sync(struct mm_struct *mm);
+#else
+#define smp_tsb_sync(__mm) do { } while (0)
+#endif
+
+/* Set MMU context in the actual hardware. */
+#define load_secondary_context(__mm) \
+        __asm__ __volatile__( \
+        "\n661: stxa            %0, [%1] %2\n" \
+        "       .section        .sun4v_1insn_patch, \"ax\"\n" \
+        "       .word           661b\n" \
+        "       stxa            %0, [%1] %3\n" \
+        "       .previous\n" \
+        "       flush           %%g6\n" \
+        : /* No outputs */ \
+        : "r" (CTX_HWBITS((__mm)->context)), \
+          "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
+
+extern void __flush_tlb_mm(unsigned long, unsigned long);
+
+/* Switch the current MM context.  Interrupts are disabled.  */
+static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
+{
+        unsigned long ctx_valid, flags;
+        int cpu;
+
+        if (unlikely(mm == &init_mm))
+                return;
+
+        spin_lock_irqsave(&mm->context.lock, flags);
+        ctx_valid = CTX_VALID(mm->context);
+        if (!ctx_valid)
+                get_new_mmu_context(mm);
+
+        /* We have to be extremely careful here or else we will miss
+         * a TSB grow if we switch back and forth between a kernel
+         * thread and an address space which has it's TSB size increased
+         * on another processor.
+         *
+         * It is possible to play some games in order to optimize the
+         * switch, but the safest thing to do is to unconditionally
+         * perform the secondary context load and the TSB context switch.
+         *
+         * For reference the bad case is, for address space "A":
+         *
+         *              CPU 0                   CPU 1
+         *      run address space A
+         *      set cpu0's bits in cpu_vm_mask
+         *      switch to kernel thread, borrow
+         *      address space A via entry_lazy_tlb
+         *                                      run address space A
+         *                                      set cpu1's bit in cpu_vm_mask
+         *                                      flush_tlb_pending()
+         *                                      reset cpu_vm_mask to just cpu1
+         *                                      TSB grow
+         *      run address space A
+         *      context was valid, so skip
+         *      TSB context switch
+         *
+         * At that point cpu0 continues to use a stale TSB, the one from
+         * before the TSB grow performed on cpu1.  cpu1 did not cross-call
+         * cpu0 to update it's TSB because at that point the cpu_vm_mask
+         * only had cpu1 set in it.
+         */
+        load_secondary_context(mm);
+        tsb_context_switch(mm);
+
+        /* Any time a processor runs a context on an address space
+         * for the first time, we must flush that context out of the
+         * local TLB.
+         */
+        cpu = smp_processor_id();
+        if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
+                cpu_set(cpu, mm->cpu_vm_mask);
+                __flush_tlb_mm(CTX_HWBITS(mm->context),
+                               SECONDARY_CONTEXT);
+        }
+        spin_unlock_irqrestore(&mm->context.lock, flags);
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+/* Activate a new MM instance for the current task. */
+static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
+{
+        unsigned long flags;
+        int cpu;
+
+        spin_lock_irqsave(&mm->context.lock, flags);
+        if (!CTX_VALID(mm->context))
+                get_new_mmu_context(mm);
+        cpu = smp_processor_id();
+        if (!cpu_isset(cpu, mm->cpu_vm_mask))
+                cpu_set(cpu, mm->cpu_vm_mask);
+
+        load_secondary_context(mm);
+        __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
+        tsb_context_switch(mm);
+        spin_unlock_irqrestore(&mm->context.lock, flags);
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_MMU_CONTEXT_H) */
diff --git a/arch/sparc/include/asm/mmzone.h b/arch/sparc/include/asm/mmzone.h
new file mode 100644
index 000000000000..ebf5986c12ed
--- /dev/null
+++ b/arch/sparc/include/asm/mmzone.h
@@ -0,0 +1,17 @@
+#ifndef _SPARC64_MMZONE_H
+#define _SPARC64_MMZONE_H
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+
+extern struct pglist_data *node_data[];
+
+#define NODE_DATA(nid)          (node_data[nid])
+#define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
+#define node_end_pfn(nid)       (NODE_DATA(nid)->node_end_pfn)
+
+extern int numa_cpu_lookup_table[];
+extern cpumask_t numa_cpumask_lookup_table[];
+
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
+#endif /* _SPARC64_MMZONE_H */
diff --git a/arch/sparc/include/asm/module.h b/arch/sparc/include/asm/module.h
new file mode 100644
index 000000000000..e82cf9a3e60e
--- /dev/null
+++ b/arch/sparc/include/asm/module.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_MODULE_H
+#define ___ASM_SPARC_MODULE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/module_64.h>
+#else
+#include <asm/module_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/module_32.h b/arch/sparc/include/asm/module_32.h
new file mode 100644
index 000000000000..cbd9e67b0c0b
--- /dev/null
+++ b/arch/sparc/include/asm/module_32.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_SPARC_MODULE_H
+#define _ASM_SPARC_MODULE_H
+struct mod_arch_specific { };
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+#endif /* _ASM_SPARC_MODULE_H */
diff --git a/arch/sparc/include/asm/module_64.h b/arch/sparc/include/asm/module_64.h
new file mode 100644
index 000000000000..3d77ba465783
--- /dev/null
+++ b/arch/sparc/include/asm/module_64.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_SPARC64_MODULE_H
+#define _ASM_SPARC64_MODULE_H
+struct mod_arch_specific { };
+#define Elf_Shdr Elf64_Shdr
+#define Elf_Sym Elf64_Sym
+#define Elf_Ehdr Elf64_Ehdr
+#endif /* _ASM_SPARC64_MODULE_H */
diff --git a/arch/sparc/include/asm/mostek.h b/arch/sparc/include/asm/mostek.h
new file mode 100644
index 000000000000..433be3e0a69b
--- /dev/null
+++ b/arch/sparc/include/asm/mostek.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_MOSTEK_H
+#define ___ASM_SPARC_MOSTEK_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/mostek_64.h>
+#else
+#include <asm/mostek_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/mostek_32.h b/arch/sparc/include/asm/mostek_32.h
new file mode 100644
index 000000000000..a99590c4c507
--- /dev/null
+++ b/arch/sparc/include/asm/mostek_32.h
@@ -0,0 +1,171 @@
+/*
+ * mostek.h:  Describes the various Mostek time of day clock registers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ * Added intersil code 05/25/98 Chris Davis (cdavis@cois.on.ca)
+ */
+
+#ifndef _SPARC_MOSTEK_H
+#define _SPARC_MOSTEK_H
+
+#include <asm/idprom.h>
+#include <asm/io.h>
+
+/*       M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
+ *
+ *                             Data
+ * Address                                                 Function
+ *        Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
+ *   7ff  -     -     -     -    -     -     -     -       Year 00-99
+ *   7fe  0     0     0     -    -     -     -     -      Month 01-12
+ *   7fd  0     0     -     -    -     -     -     -       Date 01-31
+ *   7fc  0     FT    0     0    0     -     -     -        Day 01-07
+ *   7fb  KS    0     -     -    -     -     -     -      Hours 00-23
+ *   7fa  0     -     -     -    -     -     -     -    Minutes 00-59
+ *   7f9  ST    -     -     -    -     -     -     -    Seconds 00-59
+ *   7f8  W     R     S     -    -     -     -     -    Control
+ *
+ *   * ST is STOP BIT
+ *   * W is WRITE BIT
+ *   * R is READ BIT
+ *   * S is SIGN BIT
+ *   * FT is FREQ TEST BIT
+ *   * KS is KICK START BIT
+ */
+
+/* The Mostek 48t02 real time clock and NVRAM chip. The registers
+ * other than the control register are in binary coded decimal. Some
+ * control bits also live outside the control register.
+ */
+#define mostek_read(_addr)              readb(_addr)
+#define mostek_write(_addr,_val)        writeb(_val, _addr)
+#define MOSTEK_EEPROM           0x0000UL
+#define MOSTEK_IDPROM           0x07d8UL
+#define MOSTEK_CREG             0x07f8UL
+#define MOSTEK_SEC              0x07f9UL
+#define MOSTEK_MIN              0x07faUL
+#define MOSTEK_HOUR             0x07fbUL
+#define MOSTEK_DOW              0x07fcUL
+#define MOSTEK_DOM              0x07fdUL
+#define MOSTEK_MONTH            0x07feUL
+#define MOSTEK_YEAR             0x07ffUL
+
+struct mostek48t02 {
+        volatile char eeprom[2008];     /* This is the eeprom, don't touch! */
+        struct idprom idprom;           /* The idprom lives here. */
+        volatile unsigned char creg;    /* Control register */
+        volatile unsigned char sec;     /* Seconds (0-59) */
+        volatile unsigned char min;     /* Minutes (0-59) */
+        volatile unsigned char hour;    /* Hour (0-23) */
+        volatile unsigned char dow;     /* Day of the week (1-7) */
+        volatile unsigned char dom;     /* Day of the month (1-31) */
+        volatile unsigned char month;   /* Month of year (1-12) */
+        volatile unsigned char year;    /* Year (0-99) */
+};
+
+extern spinlock_t mostek_lock;
+extern void __iomem *mstk48t02_regs;
+
+/* Control register values. */
+#define MSTK_CREG_WRITE 0x80    /* Must set this before placing values. */
+#define MSTK_CREG_READ  0x40    /* Stop updates to allow a clean read. */
+#define MSTK_CREG_SIGN  0x20    /* Slow/speed clock in calibration mode. */
+
+/* Control bits that live in the other registers. */
+#define MSTK_STOP       0x80    /* Stop the clock oscillator. (sec) */
+#define MSTK_KICK_START 0x80    /* Kick start the clock chip. (hour) */
+#define MSTK_FREQ_TEST  0x40    /* Frequency test mode. (day) */
+
+#define MSTK_YEAR_ZERO       1968   /* If year reg has zero, it is 1968. */
+#define MSTK_CVT_YEAR(yr)  ((yr) + MSTK_YEAR_ZERO)
+
+/* Masks that define how much space each value takes up. */
+#define MSTK_SEC_MASK   0x7f
+#define MSTK_MIN_MASK   0x7f
+#define MSTK_HOUR_MASK  0x3f
+#define MSTK_DOW_MASK   0x07
+#define MSTK_DOM_MASK   0x3f
+#define MSTK_MONTH_MASK 0x1f
+#define MSTK_YEAR_MASK  0xffU
+
+/* Binary coded decimal conversion macros. */
+#define MSTK_REGVAL_TO_DECIMAL(x)  (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
+#define MSTK_DECIMAL_TO_REGVAL(x)  ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
+
+/* Generic register set and get macros for internal use. */
+#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(((struct mostek48t02 *)regs)->var & MSTK_ ## mask ## _MASK))
+#define MSTK_SET(regs,var,value,mask) do { ((struct mostek48t02 *)regs)->var &= ~(MSTK_ ## mask ## _MASK); ((struct mostek48t02 *)regs)->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0)
+
+/* Macros to make register access easier on our fingers. These give you
+ * the decimal value of the register requested if applicable. You pass
+ * the a pointer to a 'struct mostek48t02'.
+ */
+#define MSTK_REG_CREG(regs)     (((struct mostek48t02 *)regs)->creg)
+#define MSTK_REG_SEC(regs)      MSTK_GET(regs,sec,SEC)
+#define MSTK_REG_MIN(regs)      MSTK_GET(regs,min,MIN)
+#define MSTK_REG_HOUR(regs)     MSTK_GET(regs,hour,HOUR)
+#define MSTK_REG_DOW(regs)      MSTK_GET(regs,dow,DOW)
+#define MSTK_REG_DOM(regs)      MSTK_GET(regs,dom,DOM)
+#define MSTK_REG_MONTH(regs)    MSTK_GET(regs,month,MONTH)
+#define MSTK_REG_YEAR(regs)     MSTK_GET(regs,year,YEAR)
+
+#define MSTK_SET_REG_SEC(regs,value)    MSTK_SET(regs,sec,value,SEC)
+#define MSTK_SET_REG_MIN(regs,value)    MSTK_SET(regs,min,value,MIN)
+#define MSTK_SET_REG_HOUR(regs,value)   MSTK_SET(regs,hour,value,HOUR)
+#define MSTK_SET_REG_DOW(regs,value)    MSTK_SET(regs,dow,value,DOW)
+#define MSTK_SET_REG_DOM(regs,value)    MSTK_SET(regs,dom,value,DOM)
+#define MSTK_SET_REG_MONTH(regs,value)  MSTK_SET(regs,month,value,MONTH)
+#define MSTK_SET_REG_YEAR(regs,value)   MSTK_SET(regs,year,value,YEAR)
+
+
+/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
+ * same (basically) layout of the 48t02 chip except for the extra
+ * NVRAM on board (8 KB against the 48t02's 2 KB).
+ */
+struct mostek48t08 {
+        char offset[6*1024];         /* Magic things may be here, who knows? */
+        struct mostek48t02 regs;     /* Here is what we are interested in.   */
+};
+
+#ifdef CONFIG_SUN4
+enum sparc_clock_type { MSTK48T02, MSTK48T08, \
+INTERSIL, MSTK_INVALID };
+#else
+enum sparc_clock_type { MSTK48T02, MSTK48T08, \
+MSTK_INVALID };
+#endif
+
+#ifdef CONFIG_SUN4
+/* intersil on a sun 4/260 code  data from harris doc */
+struct intersil_dt {
+        volatile unsigned char int_csec;
+        volatile unsigned char int_hour;
+        volatile unsigned char int_min;
+        volatile unsigned char int_sec;
+        volatile unsigned char int_month;
+        volatile unsigned char int_day;
+        volatile unsigned char int_year;
+        volatile unsigned char int_dow;
+};
+
+struct intersil {
+        struct intersil_dt clk;
+        struct intersil_dt cmp;
+        volatile unsigned char int_intr_reg;
+        volatile unsigned char int_cmd_reg;
+};
+
+#define INTERSIL_STOP        0x0
+#define INTERSIL_START       0x8
+#define INTERSIL_INTR_DISABLE   0x0
+#define INTERSIL_INTR_ENABLE   0x10
+#define INTERSIL_32K            0x0
+#define INTERSIL_NORMAL         0x0
+#define INTERSIL_24H            0x4
+#define INTERSIL_INT_100HZ      0x2
+
+/* end of intersil info */
+#endif
+
+#endif /* !(_SPARC_MOSTEK_H) */
diff --git a/arch/sparc/include/asm/mostek_64.h b/arch/sparc/include/asm/mostek_64.h
new file mode 100644
index 000000000000..c5652de2ace2
--- /dev/null
+++ b/arch/sparc/include/asm/mostek_64.h
@@ -0,0 +1,143 @@
+/* mostek.h:  Describes the various Mostek time of day clock registers.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ */
+
+#ifndef _SPARC64_MOSTEK_H
+#define _SPARC64_MOSTEK_H
+
+#include <asm/idprom.h>
+
+/*       M48T02 Register Map (adapted from Sun NVRAM/Hostid FAQ)
+ *
+ *                             Data
+ * Address                                                 Function
+ *        Bit 7 Bit 6 Bit 5 Bit 4Bit 3 Bit 2 Bit 1 Bit 0
+ *   7ff  -     -     -     -    -     -     -     -       Year 00-99
+ *   7fe  0     0     0     -    -     -     -     -      Month 01-12
+ *   7fd  0     0     -     -    -     -     -     -       Date 01-31
+ *   7fc  0     FT    0     0    0     -     -     -        Day 01-07
+ *   7fb  KS    0     -     -    -     -     -     -      Hours 00-23
+ *   7fa  0     -     -     -    -     -     -     -    Minutes 00-59
+ *   7f9  ST    -     -     -    -     -     -     -    Seconds 00-59
+ *   7f8  W     R     S     -    -     -     -     -    Control
+ *
+ *   * ST is STOP BIT
+ *   * W is WRITE BIT
+ *   * R is READ BIT
+ *   * S is SIGN BIT
+ *   * FT is FREQ TEST BIT
+ *   * KS is KICK START BIT
+ */
+
+/* The Mostek 48t02 real time clock and NVRAM chip. The registers
+ * other than the control register are in binary coded decimal. Some
+ * control bits also live outside the control register.
+ *
+ * We now deal with physical addresses for I/O to the chip. -DaveM
+ */
+static inline u8 mostek_read(void __iomem *addr)
+{
+        u8 ret;
+
+        __asm__ __volatile__("lduba     [%1] %2, %0"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+        return ret;
+}
+
+static inline void mostek_write(void __iomem *addr, u8 val)
+{
+        __asm__ __volatile__("stba      %0, [%1] %2"
+                             : /* no outputs */
+                             : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+#define MOSTEK_EEPROM           0x0000UL
+#define MOSTEK_IDPROM           0x07d8UL
+#define MOSTEK_CREG             0x07f8UL
+#define MOSTEK_SEC              0x07f9UL
+#define MOSTEK_MIN              0x07faUL
+#define MOSTEK_HOUR             0x07fbUL
+#define MOSTEK_DOW              0x07fcUL
+#define MOSTEK_DOM              0x07fdUL
+#define MOSTEK_MONTH            0x07feUL
+#define MOSTEK_YEAR             0x07ffUL
+
+extern spinlock_t mostek_lock;
+extern void __iomem *mstk48t02_regs;
+
+/* Control register values. */
+#define MSTK_CREG_WRITE 0x80    /* Must set this before placing values. */
+#define MSTK_CREG_READ  0x40    /* Stop updates to allow a clean read. */
+#define MSTK_CREG_SIGN  0x20    /* Slow/speed clock in calibration mode. */
+
+/* Control bits that live in the other registers. */
+#define MSTK_STOP       0x80    /* Stop the clock oscillator. (sec) */
+#define MSTK_KICK_START 0x80    /* Kick start the clock chip. (hour) */
+#define MSTK_FREQ_TEST  0x40    /* Frequency test mode. (day) */
+
+#define MSTK_YEAR_ZERO       1968   /* If year reg has zero, it is 1968. */
+#define MSTK_CVT_YEAR(yr)  ((yr) + MSTK_YEAR_ZERO)
+
+/* Masks that define how much space each value takes up. */
+#define MSTK_SEC_MASK   0x7f
+#define MSTK_MIN_MASK   0x7f
+#define MSTK_HOUR_MASK  0x3f
+#define MSTK_DOW_MASK   0x07
+#define MSTK_DOM_MASK   0x3f
+#define MSTK_MONTH_MASK 0x1f
+#define MSTK_YEAR_MASK  0xffU
+
+/* Binary coded decimal conversion macros. */
+#define MSTK_REGVAL_TO_DECIMAL(x)  (((x) & 0x0F) + 0x0A * ((x) >> 0x04))
+#define MSTK_DECIMAL_TO_REGVAL(x)  ((((x) / 0x0A) << 0x04) + ((x) % 0x0A))
+
+/* Generic register set and get macros for internal use. */
+#define MSTK_GET(regs,name)     \
+        (MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK))
+#define MSTK_SET(regs,name,value) \
+do {    u8 __val = mostek_read(regs + MOSTEK_ ## name); \
+        __val &= ~(MSTK_ ## name ## _MASK); \
+        __val |= (MSTK_DECIMAL_TO_REGVAL(value) & \
+                  (MSTK_ ## name ## _MASK)); \
+        mostek_write(regs + MOSTEK_ ## name, __val); \
+} while(0)
+
+/* Macros to make register access easier on our fingers. These give you
+ * the decimal value of the register requested if applicable. You pass
+ * the a pointer to a 'struct mostek48t02'.
+ */
+#define MSTK_REG_CREG(regs)     (mostek_read((regs) + MOSTEK_CREG))
+#define MSTK_REG_SEC(regs)      MSTK_GET(regs,SEC)
+#define MSTK_REG_MIN(regs)      MSTK_GET(regs,MIN)
+#define MSTK_REG_HOUR(regs)     MSTK_GET(regs,HOUR)
+#define MSTK_REG_DOW(regs)      MSTK_GET(regs,DOW)
+#define MSTK_REG_DOM(regs)      MSTK_GET(regs,DOM)
+#define MSTK_REG_MONTH(regs)    MSTK_GET(regs,MONTH)
+#define MSTK_REG_YEAR(regs)     MSTK_GET(regs,YEAR)
+
+#define MSTK_SET_REG_SEC(regs,value)    MSTK_SET(regs,SEC,value)
+#define MSTK_SET_REG_MIN(regs,value)    MSTK_SET(regs,MIN,value)
+#define MSTK_SET_REG_HOUR(regs,value)   MSTK_SET(regs,HOUR,value)
+#define MSTK_SET_REG_DOW(regs,value)    MSTK_SET(regs,DOW,value)
+#define MSTK_SET_REG_DOM(regs,value)    MSTK_SET(regs,DOM,value)
+#define MSTK_SET_REG_MONTH(regs,value)  MSTK_SET(regs,MONTH,value)
+#define MSTK_SET_REG_YEAR(regs,value)   MSTK_SET(regs,YEAR,value)
+
+
+/* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the
+ * same (basically) layout of the 48t02 chip except for the extra
+ * NVRAM on board (8 KB against the 48t02's 2 KB).
+ */
+#define MOSTEK_48T08_OFFSET     0x0000UL        /* Lower NVRAM portions */
+#define MOSTEK_48T08_48T02      0x1800UL        /* Offset to 48T02 chip */
+
+/* SUN5 systems usually have 48t59 model clock chipsets.  But we keep the older
+ * clock chip definitions around just in case.
+ */
+#define MOSTEK_48T59_OFFSET     0x0000UL        /* Lower NVRAM portions */
+#define MOSTEK_48T59_48T02      0x1800UL        /* Offset to 48T02 chip */
+
+#endif /* !(_SPARC64_MOSTEK_H) */
diff --git a/arch/sparc/include/asm/mpmbox.h b/arch/sparc/include/asm/mpmbox.h
new file mode 100644
index 000000000000..f8423039b242
--- /dev/null
+++ b/arch/sparc/include/asm/mpmbox.h
@@ -0,0 +1,67 @@
+/*
+ * mpmbox.h:  Interface and defines for the OpenProm mailbox
+ *               facilities for MP machines under Linux.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_MPMBOX_H
+#define _SPARC_MPMBOX_H
+
+/* The prom allocates, for each CPU on the machine an unsigned
+ * byte in physical ram.  You probe the device tree prom nodes
+ * for these values.  The purpose of this byte is to be able to
+ * pass messages from one cpu to another.
+ */
+
+/* These are the main message types we have to look for in our
+ * Cpu mailboxes, based upon these values we decide what course
+ * of action to take.
+ */
+
+/* The CPU is executing code in the kernel. */
+#define MAILBOX_ISRUNNING     0xf0
+
+/* Another CPU called romvec->pv_exit(), you should call
+ * prom_stopcpu() when you see this in your mailbox.
+ */
+#define MAILBOX_EXIT          0xfb
+
+/* Another CPU called romvec->pv_enter(), you should call
+ * prom_cpuidle() when this is seen.
+ */
+#define MAILBOX_GOSPIN        0xfc
+
+/* Another CPU has hit a breakpoint either into kadb or the prom
+ * itself.  Just like MAILBOX_GOSPIN, you should call prom_cpuidle()
+ * at this point.
+ */
+#define MAILBOX_BPT_SPIN      0xfd
+
+/* Oh geese, some other nitwit got a damn watchdog reset.  The party's
+ * over so go call prom_stopcpu().
+ */
+#define MAILBOX_WDOG_STOP     0xfe
+
+#ifndef __ASSEMBLY__
+
+/* Handy macro's to determine a cpu's state. */
+
+/* Is the cpu still in Power On Self Test? */
+#define MBOX_POST_P(letter)  ((letter) >= 0x00 && (letter) <= 0x7f)
+
+/* Is the cpu at the 'ok' prompt of the PROM? */
+#define MBOX_PROMPROMPT_P(letter) ((letter) >= 0x80 && (letter) <= 0x8f)
+
+/* Is the cpu spinning in the PROM? */
+#define MBOX_PROMSPIN_P(letter) ((letter) >= 0x90 && (letter) <= 0xef)
+
+/* Sanity check... This is junk mail, throw it out. */
+#define MBOX_BOGON_P(letter) ((letter) >= 0xf1 && (letter) <= 0xfa)
+
+/* Is the cpu actively running an application/kernel-code? */
+#define MBOX_RUNNING_P(letter) ((letter) == MAILBOX_ISRUNNING)
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_MPMBOX_H) */
diff --git a/arch/sparc/include/asm/msgbuf.h b/arch/sparc/include/asm/msgbuf.h
new file mode 100644
index 000000000000..efc7cbe9788f
--- /dev/null
+++ b/arch/sparc/include/asm/msgbuf.h
@@ -0,0 +1,38 @@
+#ifndef _SPARC_MSGBUF_H
+#define _SPARC_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for sparc64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        PADDING(__pad1)
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        PADDING(__pad2)
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        PADDING(__pad3)
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused1;
+        unsigned long  __unused2;
+};
+#undef PADDING
+#endif /* _SPARC_MSGBUF_H */
diff --git a/arch/sparc/include/asm/msi.h b/arch/sparc/include/asm/msi.h
new file mode 100644
index 000000000000..724ca5667052
--- /dev/null
+++ b/arch/sparc/include/asm/msi.h
@@ -0,0 +1,31 @@
+/*
+ * msi.h:  Defines specific to the MBus - Sbus - Interface.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996 Eddie C. Dost   (ecd@skynet.be)
+ */
+
+#ifndef _SPARC_MSI_H
+#define _SPARC_MSI_H
+
+/*
+ * Locations of MSI Registers.
+ */
+#define MSI_MBUS_ARBEN  0xe0001008      /* MBus Arbiter Enable register */
+
+/*
+ * Useful bits in the MSI Registers.
+ */
+#define MSI_ASYNC_MODE  0x80000000      /* Operate the MSI asynchronously */
+
+
+static inline void msi_set_sync(void)
+{
+        __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
+                              "andn %%g3, %2, %%g3\n\t"
+                              "sta %%g3, [%0] %1\n\t" : :
+                              "r" (MSI_MBUS_ARBEN),
+                              "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
+}
+
+#endif /* !(_SPARC_MSI_H) */
diff --git a/arch/sparc/include/asm/mutex.h b/arch/sparc/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/sparc/include/asm/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/sparc/include/asm/mxcc.h b/arch/sparc/include/asm/mxcc.h
new file mode 100644
index 000000000000..c0517bd05bde
--- /dev/null
+++ b/arch/sparc/include/asm/mxcc.h
@@ -0,0 +1,137 @@
+/*
+ * mxcc.h:  Definitions of the Viking MXCC registers
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_MXCC_H
+#define _SPARC_MXCC_H
+
+/* These registers are accessed through ASI 0x2. */
+#define MXCC_DATSTREAM       0x1C00000  /* Data stream register */
+#define MXCC_SRCSTREAM       0x1C00100  /* Source stream register */
+#define MXCC_DESSTREAM       0x1C00200  /* Destination stream register */
+#define MXCC_RMCOUNT         0x1C00300  /* Count of references and misses */
+#define MXCC_STEST           0x1C00804  /* Internal self-test */
+#define MXCC_CREG            0x1C00A04  /* Control register */
+#define MXCC_SREG            0x1C00B00  /* Status register */
+#define MXCC_RREG            0x1C00C04  /* Reset register */
+#define MXCC_EREG            0x1C00E00  /* Error code register */
+#define MXCC_PREG            0x1C00F04  /* Address port register */
+
+/* Some MXCC constants. */
+#define MXCC_STREAM_SIZE     0x20       /* Size in bytes of one stream r/w */
+
+/* The MXCC Control Register:
+ *
+ * ----------------------------------------------------------------------
+ * |                                   | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
+ * ----------------------------------------------------------------------
+ *  31                              10    9    8-6   5   4    3   2  1-0
+ *
+ * RRC: Controls what you read from MXCC_RMCOUNT reg.
+ *      0=Misses 1=References
+ * PRE: Prefetch enable
+ * MCE: Multiple Command Enable
+ * PARE: Parity enable
+ * ECE: External cache enable
+ */
+
+#define MXCC_CTL_RRC   0x00000200
+#define MXCC_CTL_PRE   0x00000020
+#define MXCC_CTL_MCE   0x00000010
+#define MXCC_CTL_PARE  0x00000008
+#define MXCC_CTL_ECE   0x00000004
+
+/* The MXCC Error Register:
+ *
+ * --------------------------------------------------------
+ * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
+ * --------------------------------------------------------
+ *  31   30 29  28  27  26  25 24-15  14-7   6  5-3   2-0
+ *
+ * ME: Multiple Errors have occurred
+ * CE: Cache consistency Error
+ * PEW: Parity Error during a Write operation
+ * PEE: Parity Error involving the External cache
+ * ASE: ASynchronous Error
+ * EIV: This register is toast
+ * MOPC: MXCC Operation Code for instance causing error
+ * ECODE: The Error CODE
+ * PRIV: A privileged mode error? 0=no 1=yes
+ * HPADDR: High PhysicalADDRess bits (35-32)
+ */
+
+#define MXCC_ERR_ME     0x80000000
+#define MXCC_ERR_CE     0x20000000
+#define MXCC_ERR_PEW    0x10000000
+#define MXCC_ERR_PEE    0x08000000
+#define MXCC_ERR_ASE    0x04000000
+#define MXCC_ERR_EIV    0x02000000
+#define MXCC_ERR_MOPC   0x01FF8000
+#define MXCC_ERR_ECODE  0x00007F80
+#define MXCC_ERR_PRIV   0x00000040
+#define MXCC_ERR_HPADDR 0x0000000f
+
+/* The MXCC Port register:
+ *
+ * -----------------------------------------------------
+ * |                | MID |                            |
+ * -----------------------------------------------------
+ *  31            21 20-18 17                         0
+ *
+ * MID: The moduleID of the cpu your read this from.
+ */
+
+#ifndef __ASSEMBLY__
+
+static inline void mxcc_set_stream_src(unsigned long *paddr)
+{
+        unsigned long data0 = paddr[0];
+        unsigned long data1 = paddr[1];
+
+        __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
+                              "or %%g0, %1, %%g3\n\t"
+                              "stda %%g2, [%2] %3\n\t" : :
+                              "r" (data0), "r" (data1),
+                              "r" (MXCC_SRCSTREAM),
+                              "i" (ASI_M_MXCC) : "g2", "g3");
+}
+
+static inline void mxcc_set_stream_dst(unsigned long *paddr)
+{
+        unsigned long data0 = paddr[0];
+        unsigned long data1 = paddr[1];
+
+        __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
+                              "or %%g0, %1, %%g3\n\t"
+                              "stda %%g2, [%2] %3\n\t" : :
+                              "r" (data0), "r" (data1),
+                              "r" (MXCC_DESSTREAM),
+                              "i" (ASI_M_MXCC) : "g2", "g3");
+}
+
+static inline unsigned long mxcc_get_creg(void)
+{
+        unsigned long mxcc_control;
+
+        __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
+                             "set 0xffffffff, %%g3\n\t"
+                             "stda %%g2, [%1] %2\n\t"
+                             "lda [%3] %2, %0\n\t" :
+                             "=r" (mxcc_control) :
+                             "r" (MXCC_EREG), "i" (ASI_M_MXCC),
+                             "r" (MXCC_CREG) : "g2", "g3");
+        return mxcc_control;
+}
+
+static inline void mxcc_set_creg(unsigned long mxcc_control)
+{
+        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+                             "r" (mxcc_control), "r" (MXCC_CREG),
+                             "i" (ASI_M_MXCC));
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_MXCC_H) */
diff --git a/arch/sparc/include/asm/ns87303.h b/arch/sparc/include/asm/ns87303.h
new file mode 100644
index 000000000000..686defe6aaa0
--- /dev/null
+++ b/arch/sparc/include/asm/ns87303.h
@@ -0,0 +1,118 @@
+/* ns87303.h: Configuration Register Description for the
+ *            National Semiconductor PC87303 (SuperIO).
+ *
+ * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
+ */
+
+#ifndef _SPARC_NS87303_H
+#define _SPARC_NS87303_H 1
+
+/*
+ * Control Register Index Values
+ */
+#define FER     0x00
+#define FAR     0x01
+#define PTR     0x02
+#define FCR     0x03
+#define PCR     0x04
+#define KRR     0x05
+#define PMC     0x06
+#define TUP     0x07
+#define SID     0x08
+#define ASC     0x09
+#define CS0CF0  0x0a
+#define CS0CF1  0x0b
+#define CS1CF0  0x0c
+#define CS1CF1  0x0d
+
+/* Function Enable Register (FER) bits */
+#define FER_EDM         0x10    /* Encoded Drive and Motor pin information   */
+
+/* Function Address Register (FAR) bits */
+#define FAR_LPT_MASK    0x03
+#define FAR_LPTB        0x00
+#define FAR_LPTA        0x01
+#define FAR_LPTC        0x02
+
+/* Power and Test Register (PTR) bits */
+#define PTR_LPTB_IRQ7   0x08
+#define PTR_LEVEL_IRQ   0x80    /* When not ECP/EPP: Use level IRQ           */
+#define PTR_LPT_REG_DIR 0x80    /* When ECP/EPP: LPT CTR controlls direction */
+                                /*               of the parallel port        */
+
+/* Function Control Register (FCR) bits */
+#define FCR_LDE         0x10    /* Logical Drive Exchange                    */
+#define FCR_ZWS_ENA     0x20    /* Enable short host read/write in ECP/EPP   */
+
+/* Printer Control Register (PCR) bits */
+#define PCR_EPP_ENABLE  0x01
+#define PCR_EPP_IEEE    0x02    /* Enable EPP Version 1.9 (IEEE 1284)        */
+#define PCR_ECP_ENABLE  0x04
+#define PCR_ECP_CLK_ENA 0x08    /* If 0 ECP Clock is stopped on Power down   */
+#define PCR_IRQ_POLAR   0x20    /* If 0 IRQ is level high or negative pulse, */
+                                /* if 1 polarity is inverted                 */
+#define PCR_IRQ_ODRAIN  0x40    /* If 1, IRQ is open drain                   */
+
+/* Tape UARTs and Parallel Port Config Register (TUP) bits */
+#define TUP_EPP_TIMO    0x02    /* Enable EPP timeout IRQ                    */
+
+/* Advanced SuperIO Config Register (ASC) bits */
+#define ASC_LPT_IRQ7    0x01    /* Always use IRQ7 for LPT                  */
+#define ASC_DRV2_SEL    0x02    /* Logical Drive Exchange controlled by TDR  */
+
+#define FER_RESERVED    0x00
+#define FAR_RESERVED    0x00
+#define PTR_RESERVED    0x73
+#define FCR_RESERVED    0xc4
+#define PCR_RESERVED    0x10
+#define KRR_RESERVED    0x00
+#define PMC_RESERVED    0x98
+#define TUP_RESERVED    0xfb
+#define SIP_RESERVED    0x00
+#define ASC_RESERVED    0x18
+#define CS0CF0_RESERVED 0x00
+#define CS0CF1_RESERVED 0x08
+#define CS1CF0_RESERVED 0x00
+#define CS1CF1_RESERVED 0x08
+
+#ifdef __KERNEL__
+
+#include <linux/spinlock.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+
+extern spinlock_t ns87303_lock;
+
+static inline int ns87303_modify(unsigned long port, unsigned int index,
+                                     unsigned char clr, unsigned char set)
+{
+        static unsigned char reserved[] = {
+                FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
+                PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
+                SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
+                CS1CF0_RESERVED, CS1CF1_RESERVED
+        };
+        unsigned long flags;
+        unsigned char value;
+
+        if (index > 0x0d)
+                return -EINVAL;
+
+        spin_lock_irqsave(&ns87303_lock, flags);
+
+        outb(index, port);
+        value = inb(port + 1);
+        value &= ~(reserved[index] | clr);
+        value |= set;
+        outb(value, port + 1);
+        outb(value, port + 1);
+
+        spin_unlock_irqrestore(&ns87303_lock, flags);
+
+        return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* !(_SPARC_NS87303_H) */
diff --git a/arch/sparc/include/asm/obio.h b/arch/sparc/include/asm/obio.h
new file mode 100644
index 000000000000..1a7544ceb574
--- /dev/null
+++ b/arch/sparc/include/asm/obio.h
@@ -0,0 +1,249 @@
+/*
+ * obio.h:  Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
+ *
+ * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
+ */
+
+#ifndef _SPARC_OBIO_H
+#define _SPARC_OBIO_H
+
+#include <asm/asi.h>
+
+/* This weird monster likes to use the very upper parts of
+   36bit PA for these things :) */
+   
+/* CSR space (for each XDBUS)
+ *  ------------------------------------------------------------------------
+ *  |   0xFE  |   DEVID    |                | XDBUS ID |                   |
+ *  ------------------------------------------------------------------------
+ *  35      28 27        20 19            10 9        8 7                 0
+ */
+   
+#define CSR_BASE_ADDR           0xe0000000
+#define CSR_CPU_SHIFT           (32 - 4 - 5)
+#define CSR_XDBUS_SHIFT         8
+
+#define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
+
+/* ECSR space (not for each XDBUS)
+ *  ------------------------------------------------------------------------
+ *  |   0xF  | DEVID[7:1] |                                                |
+ *  ------------------------------------------------------------------------
+ *  35     32 31        25 24                                             0
+ */
+   
+#define ECSR_BASE_ADDR          0x00000000
+#define ECSR_CPU_SHIFT          (32 - 5)
+#define ECSR_DEV_SHIFT          (32 - 8)
+
+#define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
+#define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT) 
+
+/* Bus Watcher */
+#define BW_LOCAL_BASE           0xfff00000
+
+#define BW_CID                  0x00000000
+#define BW_DBUS_CTRL            0x00000008
+#define BW_DBUS_DATA            0x00000010
+#define BW_CTRL                 0x00001000
+#define BW_INTR_TABLE           0x00001040
+#define BW_INTR_TABLE_CLEAR     0x00001080
+#define BW_PRESCALER            0x000010c0
+#define BW_PTIMER_LIMIT         0x00002000
+#define BW_PTIMER_COUNTER2      0x00002004
+#define BW_PTIMER_NDLIMIT       0x00002008
+#define BW_PTIMER_CTRL          0x0000200c
+#define BW_PTIMER_COUNTER       0x00002010
+#define BW_TIMER_LIMIT          0x00003000
+#define BW_TIMER_COUNTER2       0x00003004
+#define BW_TIMER_NDLIMIT        0x00003008
+#define BW_TIMER_CTRL           0x0000300c
+#define BW_TIMER_COUNTER        0x00003010
+
+/* BW Control */
+#define BW_CTRL_USER_TIMER      0x00000004      /* Is User Timer Free run enabled */
+
+/* Boot Bus */
+#define BB_LOCAL_BASE           0xf0000000
+
+#define BB_STAT1                0x00100000
+#define BB_STAT2                0x00120000
+#define BB_STAT3                0x00140000
+#define BB_LEDS                 0x002e0000
+
+/* Bits in BB_STAT2 */
+#define BB_STAT2_AC_INTR        0x04    /* Aiee! 5ms and power is gone... */
+#define BB_STAT2_TMP_INTR       0x10    /* My Penguins are burning. Are you able to smell it? */
+#define BB_STAT2_FAN_INTR       0x20    /* My fan refuses to work */
+#define BB_STAT2_PWR_INTR       0x40    /* On SC2000, one of the two ACs died. Ok, we go on... */
+#define BB_STAT2_MASK           (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
+
+/* Cache Controller */
+#define CC_BASE         0x1F00000
+#define CC_DATSTREAM    0x1F00000  /* Data stream register */
+#define CC_DATSIZE      0x1F0003F  /* Size */
+#define CC_SRCSTREAM    0x1F00100  /* Source stream register */
+#define CC_DESSTREAM    0x1F00200  /* Destination stream register */
+#define CC_RMCOUNT      0x1F00300  /* Count of references and misses */
+#define CC_IPEN         0x1F00406  /* Pending Interrupts */
+#define CC_IMSK         0x1F00506  /* Interrupt Mask */
+#define CC_ICLR         0x1F00606  /* Clear pending Interrupts */
+#define CC_IGEN         0x1F00704  /* Generate Interrupt register */
+#define CC_STEST        0x1F00804  /* Internal self-test */
+#define CC_CREG         0x1F00A04  /* Control register */
+#define CC_SREG         0x1F00B00  /* Status register */
+#define CC_RREG         0x1F00C04  /* Reset register */
+#define CC_EREG         0x1F00E00  /* Error code register */
+#define CC_CID          0x1F00F04  /* Component ID */
+
+#ifndef __ASSEMBLY__
+
+static inline int bw_get_intr_mask(int sbus_level)
+{
+        int mask;
+        
+        __asm__ __volatile__ ("lduha [%1] %2, %0" :
+                              "=r" (mask) :
+                              "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
+                              "i" (ASI_M_CTL));
+        return mask;
+}
+
+static inline void bw_clear_intr_mask(int sbus_level, int mask)
+{
+        __asm__ __volatile__ ("stha %0, [%1] %2" : :
+                              "r" (mask),
+                              "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
+                              "i" (ASI_M_CTL));
+}
+
+static inline unsigned bw_get_prof_limit(int cpu)
+{
+        unsigned limit;
+        
+        __asm__ __volatile__ ("lda [%1] %2, %0" :
+                              "=r" (limit) :
+                              "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
+                              "i" (ASI_M_CTL));
+        return limit;
+}
+
+static inline void bw_set_prof_limit(int cpu, unsigned limit)
+{
+        __asm__ __volatile__ ("sta %0, [%1] %2" : :
+                              "r" (limit),
+                              "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
+                              "i" (ASI_M_CTL));
+}
+
+static inline unsigned bw_get_ctrl(int cpu)
+{
+        unsigned ctrl;
+        
+        __asm__ __volatile__ ("lda [%1] %2, %0" :
+                              "=r" (ctrl) :
+                              "r" (CSR_BASE(cpu) + BW_CTRL),
+                              "i" (ASI_M_CTL));
+        return ctrl;
+}
+
+static inline void bw_set_ctrl(int cpu, unsigned ctrl)
+{
+        __asm__ __volatile__ ("sta %0, [%1] %2" : :
+                              "r" (ctrl),
+                              "r" (CSR_BASE(cpu) + BW_CTRL),
+                              "i" (ASI_M_CTL));
+}
+
+extern unsigned char cpu_leds[32];
+
+static inline void show_leds(int cpuid)
+{
+        cpuid &= 0x1e;
+        __asm__ __volatile__ ("stba %0, [%1] %2" : :
+                              "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
+                              "r" (ECSR_BASE(cpuid) | BB_LEDS),
+                              "i" (ASI_M_CTL));
+}
+
+static inline unsigned cc_get_ipen(void)
+{
+        unsigned pending;
+        
+        __asm__ __volatile__ ("lduha [%1] %2, %0" :
+                              "=r" (pending) :
+                              "r" (CC_IPEN),
+                              "i" (ASI_M_MXCC));
+        return pending;
+}
+
+static inline void cc_set_iclr(unsigned clear)
+{
+        __asm__ __volatile__ ("stha %0, [%1] %2" : :
+                              "r" (clear),
+                              "r" (CC_ICLR),
+                              "i" (ASI_M_MXCC));
+}
+
+static inline unsigned cc_get_imsk(void)
+{
+        unsigned mask;
+        
+        __asm__ __volatile__ ("lduha [%1] %2, %0" :
+                              "=r" (mask) :
+                              "r" (CC_IMSK),
+                              "i" (ASI_M_MXCC));
+        return mask;
+}
+
+static inline void cc_set_imsk(unsigned mask)
+{
+        __asm__ __volatile__ ("stha %0, [%1] %2" : :
+                              "r" (mask),
+                              "r" (CC_IMSK),
+                              "i" (ASI_M_MXCC));
+}
+
+static inline unsigned cc_get_imsk_other(int cpuid)
+{
+        unsigned mask;
+        
+        __asm__ __volatile__ ("lduha [%1] %2, %0" :
+                              "=r" (mask) :
+                              "r" (ECSR_BASE(cpuid) | CC_IMSK),
+                              "i" (ASI_M_CTL));
+        return mask;
+}
+
+static inline void cc_set_imsk_other(int cpuid, unsigned mask)
+{
+        __asm__ __volatile__ ("stha %0, [%1] %2" : :
+                              "r" (mask),
+                              "r" (ECSR_BASE(cpuid) | CC_IMSK),
+                              "i" (ASI_M_CTL));
+}
+
+static inline void cc_set_igen(unsigned gen)
+{
+        __asm__ __volatile__ ("sta %0, [%1] %2" : :
+                              "r" (gen),
+                              "r" (CC_IGEN),
+                              "i" (ASI_M_MXCC));
+}
+
+/* +-------+-------------+-----------+------------------------------------+
+ * | bcast |  devid      |   sid     |              levels mask           |
+ * +-------+-------------+-----------+------------------------------------+
+ *  31      30         23 22       15 14                                 0
+ */
+#define IGEN_MESSAGE(bcast, devid, sid, levels) \
+        (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
+            
+static inline void sun4d_send_ipi(int cpu, int level)
+{
+        cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_OBIO_H) */
diff --git a/arch/sparc/include/asm/of_device.h b/arch/sparc/include/asm/of_device.h
new file mode 100644
index 000000000000..e5f5aedc2293
--- /dev/null
+++ b/arch/sparc/include/asm/of_device.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_SPARC_OF_DEVICE_H
+#define _ASM_SPARC_OF_DEVICE_H
+#ifdef __KERNEL__
+
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/mod_devicetable.h>
+#include <asm/openprom.h>
+
+/*
+ * The of_device is a kind of "base class" that is a superset of
+ * struct device for use by devices attached to an OF node and
+ * probed using OF properties.
+ */
+struct of_device
+{
+        struct device_node              *node;
+        struct device                   dev;
+        struct resource                 resource[PROMREG_MAX];
+        unsigned int                    irqs[PROMINTR_MAX];
+        int                             num_irqs;
+
+        void                            *sysdata;
+
+        int                             slot;
+        int                             portid;
+        int                             clock_freq;
+};
+
+extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
+extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
+
+/* These are just here during the transition */
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_SPARC_OF_DEVICE_H */
diff --git a/arch/sparc/include/asm/of_platform.h b/arch/sparc/include/asm/of_platform.h
new file mode 100644
index 000000000000..93a262c44022
--- /dev/null
+++ b/arch/sparc/include/asm/of_platform.h
@@ -0,0 +1,24 @@
+#ifndef ___ASM_SPARC_OF_PLATFORM_H
+#define ___ASM_SPARC_OF_PLATFORM_H
+/*
+ *    Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
+ *                       <benh@kernel.crashing.org>
+ *    Modified for Sparc by merging parts of asm/of_device.h
+ *              by Stephen Rothwell
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+
+/* This is just here during the transition */
+#include <linux/of_platform.h>
+
+extern struct bus_type ebus_bus_type;
+extern struct bus_type sbus_bus_type;
+
+#define of_bus_type     of_platform_bus_type    /* for compatibility */
+
+#endif
diff --git a/arch/sparc/include/asm/openprom.h b/arch/sparc/include/asm/openprom.h
new file mode 100644
index 000000000000..aaeae905ed3f
--- /dev/null
+++ b/arch/sparc/include/asm/openprom.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_OPENPROM_H
+#define ___ASM_SPARC_OPENPROM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/openprom_64.h>
+#else
+#include <asm/openprom_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/openprom_32.h b/arch/sparc/include/asm/openprom_32.h
new file mode 100644
index 000000000000..8b1649f29ed9
--- /dev/null
+++ b/arch/sparc/include/asm/openprom_32.h
@@ -0,0 +1,255 @@
+#ifndef __SPARC_OPENPROM_H
+#define __SPARC_OPENPROM_H
+
+/* openprom.h:  Prom structures and defines for access to the OPENBOOT
+ *              prom routines and data areas.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* Empirical constants... */
+#define LINUX_OPPROM_MAGIC      0x10010407
+
+#ifndef __ASSEMBLY__
+/* V0 prom device operations. */
+struct linux_dev_v0_funcs {
+        int (*v0_devopen)(char *device_str);
+        int (*v0_devclose)(int dev_desc);
+        int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+        int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+        int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
+        int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
+        int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+        int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+        int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
+};
+
+/* V2 and later prom device operations. */
+struct linux_dev_v2_funcs {
+        int (*v2_inst2pkg)(int d);      /* Convert ihandle to phandle */
+        char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
+        void (*v2_dumb_mem_free)(char *va, unsigned sz);
+
+        /* To map devices into virtual I/O space. */
+        char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
+        void (*v2_dumb_munmap)(char *virta, unsigned size);
+
+        int (*v2_dev_open)(char *devpath);
+        void (*v2_dev_close)(int d);
+        int (*v2_dev_read)(int d, char *buf, int nbytes);
+        int (*v2_dev_write)(int d, char *buf, int nbytes);
+        int (*v2_dev_seek)(int d, int hi, int lo);
+
+        /* Never issued (multistage load support) */
+        void (*v2_wheee2)(void);
+        void (*v2_wheee3)(void);
+};
+
+struct linux_mlist_v0 {
+        struct linux_mlist_v0 *theres_more;
+        char *start_adr;
+        unsigned num_bytes;
+};
+
+struct linux_mem_v0 {
+        struct linux_mlist_v0 **v0_totphys;
+        struct linux_mlist_v0 **v0_prommap;
+        struct linux_mlist_v0 **v0_available; /* What we can use */
+};
+
+/* Arguments sent to the kernel from the boot prompt. */
+struct linux_arguments_v0 {
+        char *argv[8];
+        char args[100];
+        char boot_dev[2];
+        int boot_dev_ctrl;
+        int boot_dev_unit;
+        int dev_partition;
+        char *kernel_file_name;
+        void *aieee1;           /* XXX */
+};
+
+/* V2 and up boot things. */
+struct linux_bootargs_v2 {
+        char **bootpath;
+        char **bootargs;
+        int *fd_stdin;
+        int *fd_stdout;
+};
+
+/* The top level PROM vector. */
+struct linux_romvec {
+        /* Version numbers. */
+        unsigned int pv_magic_cookie;
+        unsigned int pv_romvers;
+        unsigned int pv_plugin_revision;
+        unsigned int pv_printrev;
+
+        /* Version 0 memory descriptors. */
+        struct linux_mem_v0 pv_v0mem;
+
+        /* Node operations. */
+        struct linux_nodeops *pv_nodeops;
+
+        char **pv_bootstr;
+        struct linux_dev_v0_funcs pv_v0devops;
+
+        char *pv_stdin;
+        char *pv_stdout;
+#define PROMDEV_KBD     0               /* input from keyboard */
+#define PROMDEV_SCREEN  0               /* output to screen */
+#define PROMDEV_TTYA    1               /* in/out to ttya */
+#define PROMDEV_TTYB    2               /* in/out to ttyb */
+
+        /* Blocking getchar/putchar.  NOT REENTRANT! (grr) */
+        int (*pv_getchar)(void);
+        void (*pv_putchar)(int ch);
+
+        /* Non-blocking variants. */
+        int (*pv_nbgetchar)(void);
+        int (*pv_nbputchar)(int ch);
+
+        void (*pv_putstr)(char *str, int len);
+
+        /* Miscellany. */
+        void (*pv_reboot)(char *bootstr);
+        void (*pv_printf)(__const__ char *fmt, ...);
+        void (*pv_abort)(void);
+        __volatile__ int *pv_ticks;
+        void (*pv_halt)(void);
+        void (**pv_synchook)(void);
+
+        /* Evaluate a forth string, not different proto for V0 and V2->up. */
+        union {
+                void (*v0_eval)(int len, char *str);
+                void (*v2_eval)(char *str);
+        } pv_fortheval;
+
+        struct linux_arguments_v0 **pv_v0bootargs;
+
+        /* Get ether address. */
+        unsigned int (*pv_enaddr)(int d, char *enaddr);
+
+        struct linux_bootargs_v2 pv_v2bootargs;
+        struct linux_dev_v2_funcs pv_v2devops;
+
+        int filler[15];
+
+        /* This one is sun4c/sun4 only. */
+        void (*pv_setctxt)(int ctxt, char *va, int pmeg);
+
+        /* Prom version 3 Multiprocessor routines. This stuff is crazy.
+         * No joke. Calling these when there is only one cpu probably
+         * crashes the machine, have to test this. :-)
+         */
+
+        /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
+         * 'thiscontext' executing at address 'prog_counter'
+         */
+        int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
+                           int thiscontext, char *prog_counter);
+
+        /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
+         * until a resume cpu call is made.
+         */
+        int (*v3_cpustop)(unsigned int whichcpu);
+
+        /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
+         * resume cpu call is made.
+         */
+        int (*v3_cpuidle)(unsigned int whichcpu);
+
+        /* v3_cpuresume() will resume processor 'whichcpu' executing
+         * starting with whatever 'pc' and 'npc' were left at the
+         * last 'idle' or 'stop' call.
+         */
+        int (*v3_cpuresume)(unsigned int whichcpu);
+};
+
+/* Routines for traversing the prom device tree. */
+struct linux_nodeops {
+        int (*no_nextnode)(int node);
+        int (*no_child)(int node);
+        int (*no_proplen)(int node, char *name);
+        int (*no_getprop)(int node, char *name, char *val);
+        int (*no_setprop)(int node, char *name, char *val, int len);
+        char * (*no_nextprop)(int node, char *name);
+};
+
+/* More fun PROM structures for device probing. */
+#define PROMREG_MAX     16
+#define PROMVADDR_MAX   16
+#define PROMINTR_MAX    15
+
+struct linux_prom_registers {
+        unsigned int which_io;         /* is this in OBIO space? */
+        unsigned int phys_addr;        /* The physical address of this register */
+        unsigned int reg_size;         /* How many bytes does this register take up? */
+};
+
+struct linux_prom_irqs {
+        int pri;    /* IRQ priority */
+        int vector; /* This is foobar, what does it do? */
+};
+
+/* Element of the "ranges" vector */
+struct linux_prom_ranges {
+        unsigned int ot_child_space;
+        unsigned int ot_child_base;             /* Bus feels this */
+        unsigned int ot_parent_space;
+        unsigned int ot_parent_base;            /* CPU looks from here */
+        unsigned int or_size;
+};
+
+/* Ranges and reg properties are a bit different for PCI. */
+struct linux_prom_pci_registers {
+        /*
+         * We don't know what information this field contain.
+         * We guess, PCI device function is in bits 15:8
+         * So, ...
+         */
+        unsigned int which_io;  /* Let it be which_io */
+
+        unsigned int phys_hi;
+        unsigned int phys_lo;
+
+        unsigned int size_hi;
+        unsigned int size_lo;
+};
+
+struct linux_prom_pci_ranges {
+        unsigned int child_phys_hi;     /* Only certain bits are encoded here. */
+        unsigned int child_phys_mid;
+        unsigned int child_phys_lo;
+
+        unsigned int parent_phys_hi;
+        unsigned int parent_phys_lo;
+
+        unsigned int size_hi;
+        unsigned int size_lo;
+};
+
+struct linux_prom_pci_assigned_addresses {
+        unsigned int which_io;
+
+        unsigned int phys_hi;
+        unsigned int phys_lo;
+
+        unsigned int size_hi;
+        unsigned int size_lo;
+};
+
+struct linux_prom_ebus_ranges {
+        unsigned int child_phys_hi;
+        unsigned int child_phys_lo;
+
+        unsigned int parent_phys_hi;
+        unsigned int parent_phys_mid;
+        unsigned int parent_phys_lo;
+
+        unsigned int size;
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC_OPENPROM_H) */
diff --git a/arch/sparc/include/asm/openprom_64.h b/arch/sparc/include/asm/openprom_64.h
new file mode 100644
index 000000000000..b69e4a8c9170
--- /dev/null
+++ b/arch/sparc/include/asm/openprom_64.h
@@ -0,0 +1,280 @@
+#ifndef __SPARC64_OPENPROM_H
+#define __SPARC64_OPENPROM_H
+
+/* openprom.h:  Prom structures and defines for access to the OPENBOOT
+ *              prom routines and data areas.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __ASSEMBLY__
+/* V0 prom device operations. */
+struct linux_dev_v0_funcs {
+        int (*v0_devopen)(char *device_str);
+        int (*v0_devclose)(int dev_desc);
+        int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+        int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+        int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
+        int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
+        int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+        int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+        int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
+};
+
+/* V2 and later prom device operations. */
+struct linux_dev_v2_funcs {
+        int (*v2_inst2pkg)(int d);      /* Convert ihandle to phandle */
+        char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
+        void (*v2_dumb_mem_free)(char *va, unsigned sz);
+
+        /* To map devices into virtual I/O space. */
+        char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
+        void (*v2_dumb_munmap)(char *virta, unsigned size);
+
+        int (*v2_dev_open)(char *devpath);
+        void (*v2_dev_close)(int d);
+        int (*v2_dev_read)(int d, char *buf, int nbytes);
+        int (*v2_dev_write)(int d, char *buf, int nbytes);
+        int (*v2_dev_seek)(int d, int hi, int lo);
+
+        /* Never issued (multistage load support) */
+        void (*v2_wheee2)(void);
+        void (*v2_wheee3)(void);
+};
+
+struct linux_mlist_v0 {
+        struct linux_mlist_v0 *theres_more;
+        unsigned start_adr;
+        unsigned num_bytes;
+};
+
+struct linux_mem_v0 {
+        struct linux_mlist_v0 **v0_totphys;
+        struct linux_mlist_v0 **v0_prommap;
+        struct linux_mlist_v0 **v0_available; /* What we can use */
+};
+
+/* Arguments sent to the kernel from the boot prompt. */
+struct linux_arguments_v0 {
+        char *argv[8];
+        char args[100];
+        char boot_dev[2];
+        int boot_dev_ctrl;
+        int boot_dev_unit;
+        int dev_partition;
+        char *kernel_file_name;
+        void *aieee1;           /* XXX */
+};
+
+/* V2 and up boot things. */
+struct linux_bootargs_v2 {
+        char **bootpath;
+        char **bootargs;
+        int *fd_stdin;
+        int *fd_stdout;
+};
+
+/* The top level PROM vector. */
+struct linux_romvec {
+        /* Version numbers. */
+        unsigned int pv_magic_cookie;
+        unsigned int pv_romvers;
+        unsigned int pv_plugin_revision;
+        unsigned int pv_printrev;
+
+        /* Version 0 memory descriptors. */
+        struct linux_mem_v0 pv_v0mem;
+
+        /* Node operations. */
+        struct linux_nodeops *pv_nodeops;
+
+        char **pv_bootstr;
+        struct linux_dev_v0_funcs pv_v0devops;
+
+        char *pv_stdin;
+        char *pv_stdout;
+#define PROMDEV_KBD     0               /* input from keyboard */
+#define PROMDEV_SCREEN  0               /* output to screen */
+#define PROMDEV_TTYA    1               /* in/out to ttya */
+#define PROMDEV_TTYB    2               /* in/out to ttyb */
+
+        /* Blocking getchar/putchar.  NOT REENTRANT! (grr) */
+        int (*pv_getchar)(void);
+        void (*pv_putchar)(int ch);
+
+        /* Non-blocking variants. */
+        int (*pv_nbgetchar)(void);
+        int (*pv_nbputchar)(int ch);
+
+        void (*pv_putstr)(char *str, int len);
+
+        /* Miscellany. */
+        void (*pv_reboot)(char *bootstr);
+        void (*pv_printf)(__const__ char *fmt, ...);
+        void (*pv_abort)(void);
+        __volatile__ int *pv_ticks;
+        void (*pv_halt)(void);
+        void (**pv_synchook)(void);
+
+        /* Evaluate a forth string, not different proto for V0 and V2->up. */
+        union {
+                void (*v0_eval)(int len, char *str);
+                void (*v2_eval)(char *str);
+        } pv_fortheval;
+
+        struct linux_arguments_v0 **pv_v0bootargs;
+
+        /* Get ether address. */
+        unsigned int (*pv_enaddr)(int d, char *enaddr);
+
+        struct linux_bootargs_v2 pv_v2bootargs;
+        struct linux_dev_v2_funcs pv_v2devops;
+
+        int filler[15];
+
+        /* This one is sun4c/sun4 only. */
+        void (*pv_setctxt)(int ctxt, char *va, int pmeg);
+
+        /* Prom version 3 Multiprocessor routines. This stuff is crazy.
+         * No joke. Calling these when there is only one cpu probably
+         * crashes the machine, have to test this. :-)
+         */
+
+        /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
+         * 'thiscontext' executing at address 'prog_counter'
+         */
+        int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
+                           int thiscontext, char *prog_counter);
+
+        /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
+         * until a resume cpu call is made.
+         */
+        int (*v3_cpustop)(unsigned int whichcpu);
+
+        /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
+         * resume cpu call is made.
+         */
+        int (*v3_cpuidle)(unsigned int whichcpu);
+
+        /* v3_cpuresume() will resume processor 'whichcpu' executing
+         * starting with whatever 'pc' and 'npc' were left at the
+         * last 'idle' or 'stop' call.
+         */
+        int (*v3_cpuresume)(unsigned int whichcpu);
+};
+
+/* Routines for traversing the prom device tree. */
+struct linux_nodeops {
+        int (*no_nextnode)(int node);
+        int (*no_child)(int node);
+        int (*no_proplen)(int node, char *name);
+        int (*no_getprop)(int node, char *name, char *val);
+        int (*no_setprop)(int node, char *name, char *val, int len);
+        char * (*no_nextprop)(int node, char *name);
+};
+
+/* More fun PROM structures for device probing. */
+#define PROMREG_MAX     24
+#define PROMVADDR_MAX   16
+#define PROMINTR_MAX    32
+
+struct linux_prom_registers {
+        unsigned which_io;      /* hi part of physical address                  */
+        unsigned phys_addr;     /* The physical address of this register        */
+        int reg_size;           /* How many bytes does this register take up?   */
+};
+
+struct linux_prom64_registers {
+        unsigned long phys_addr;
+        unsigned long reg_size;
+};
+
+struct linux_prom_irqs {
+        int pri;    /* IRQ priority */
+        int vector; /* This is foobar, what does it do? */
+};
+
+/* Element of the "ranges" vector */
+struct linux_prom_ranges {
+        unsigned int ot_child_space;
+        unsigned int ot_child_base;             /* Bus feels this */
+        unsigned int ot_parent_space;
+        unsigned int ot_parent_base;            /* CPU looks from here */
+        unsigned int or_size;
+};
+
+struct linux_prom64_ranges {
+        unsigned long ot_child_base;            /* Bus feels this */
+        unsigned long ot_parent_base;           /* CPU looks from here */
+        unsigned long or_size;
+};
+
+/* Ranges and reg properties are a bit different for PCI. */
+struct linux_prom_pci_registers {
+        unsigned int phys_hi;
+        unsigned int phys_mid;
+        unsigned int phys_lo;
+
+        unsigned int size_hi;
+        unsigned int size_lo;
+};
+
+struct linux_prom_pci_ranges {
+        unsigned int child_phys_hi;     /* Only certain bits are encoded here. */
+        unsigned int child_phys_mid;
+        unsigned int child_phys_lo;
+
+        unsigned int parent_phys_hi;
+        unsigned int parent_phys_lo;
+
+        unsigned int size_hi;
+        unsigned int size_lo;
+};
+
+struct linux_prom_pci_intmap {
+        unsigned int phys_hi;
+        unsigned int phys_mid;
+        unsigned int phys_lo;
+
+        unsigned int interrupt;
+
+        int          cnode;
+        unsigned int cinterrupt;
+};
+
+struct linux_prom_pci_intmask {
+        unsigned int phys_hi;
+        unsigned int phys_mid;
+        unsigned int phys_lo;
+        unsigned int interrupt;
+};
+
+struct linux_prom_ebus_ranges {
+        unsigned int child_phys_hi;
+        unsigned int child_phys_lo;
+
+        unsigned int parent_phys_hi;
+        unsigned int parent_phys_mid;
+        unsigned int parent_phys_lo;
+
+        unsigned int size;
+};
+
+struct linux_prom_ebus_intmap {
+        unsigned int phys_hi;
+        unsigned int phys_lo;
+
+        unsigned int interrupt;
+
+        int          cnode;
+        unsigned int cinterrupt;
+};
+
+struct linux_prom_ebus_intmask {
+        unsigned int phys_hi;
+        unsigned int phys_lo;
+        unsigned int interrupt;
+};
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_OPENPROM_H) */
diff --git a/arch/sparc/include/asm/openpromio.h b/arch/sparc/include/asm/openpromio.h
new file mode 100644
index 000000000000..917fb8e9c633
--- /dev/null
+++ b/arch/sparc/include/asm/openpromio.h
@@ -0,0 +1,69 @@
+#ifndef _SPARC_OPENPROMIO_H
+#define _SPARC_OPENPROMIO_H
+
+#include <linux/compiler.h>
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+/*
+ * SunOS and Solaris /dev/openprom definitions. The ioctl values
+ * were chosen to be exactly equal to the SunOS equivalents.
+ */
+
+struct openpromio
+{
+        u_int   oprom_size;             /* Actual size of the oprom_array. */
+        char    oprom_array[1];         /* Holds property names and values. */
+};
+
+#define OPROMMAXPARAM   4096            /* Maximum size of oprom_array. */
+
+#define OPROMGETOPT             0x20004F01
+#define OPROMSETOPT             0x20004F02
+#define OPROMNXTOPT             0x20004F03
+#define OPROMSETOPT2            0x20004F04
+#define OPROMNEXT               0x20004F05
+#define OPROMCHILD              0x20004F06
+#define OPROMGETPROP            0x20004F07
+#define OPROMNXTPROP            0x20004F08
+#define OPROMU2P                0x20004F09
+#define OPROMGETCONS            0x20004F0A
+#define OPROMGETFBNAME          0x20004F0B
+#define OPROMGETBOOTARGS        0x20004F0C
+/* Linux extensions */                          /* Arguments in oprom_array: */
+#define OPROMSETCUR             0x20004FF0      /* int node - Sets current node */
+#define OPROMPCI2NODE           0x20004FF1      /* int pci_bus, pci_devfn - Sets current node to PCI device's node */
+#define OPROMPATH2NODE          0x20004FF2      /* char path[] - Set current node from fully qualified PROM path */
+
+/*
+ * Return values from OPROMGETCONS:
+ */
+
+#define OPROMCONS_NOT_WSCONS    0
+#define OPROMCONS_STDIN_IS_KBD  0x1     /* stdin device is kbd */
+#define OPROMCONS_STDOUT_IS_FB  0x2     /* stdout is a framebuffer */
+#define OPROMCONS_OPENPROM      0x4     /* supports openboot */
+
+
+/*
+ *  NetBSD/OpenBSD /dev/openprom definitions.
+ */
+
+struct opiocdesc
+{
+        int     op_nodeid;              /* PROM Node ID (value-result) */
+        int     op_namelen;             /* Length of op_name. */
+        char    __user *op_name;        /* Pointer to the property name. */
+        int     op_buflen;              /* Length of op_buf (value-result) */
+        char    __user *op_buf;         /* Pointer to buffer. */
+};
+
+#define OPIOCGET        _IOWR('O', 1, struct opiocdesc)
+#define OPIOCSET        _IOW('O', 2, struct opiocdesc)
+#define OPIOCNEXTPROP   _IOWR('O', 3, struct opiocdesc)
+#define OPIOCGETOPTNODE _IOR('O', 4, int)
+#define OPIOCGETNEXT    _IOWR('O', 5, int)
+#define OPIOCGETCHILD   _IOWR('O', 6, int)
+
+#endif /* _SPARC_OPENPROMIO_H */
+
diff --git a/arch/sparc/include/asm/oplib.h b/arch/sparc/include/asm/oplib.h
new file mode 100644
index 000000000000..72e04e13a6b4
--- /dev/null
+++ b/arch/sparc/include/asm/oplib.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_OPLIB_H
+#define ___ASM_SPARC_OPLIB_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/oplib_64.h>
+#else
+#include <asm/oplib_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
new file mode 100644
index 000000000000..b2631da259e0
--- /dev/null
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -0,0 +1,272 @@
+/*
+ * oplib.h:  Describes the interface and available routines in the
+ *           Linux Prom library.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_OPLIB_H
+#define __SPARC_OPLIB_H
+
+#include <asm/openprom.h>
+#include <linux/spinlock.h>
+#include <linux/compiler.h>
+
+/* The master romvec pointer... */
+extern struct linux_romvec *romvec;
+
+/* Enumeration to describe the prom major version we have detected. */
+enum prom_major_version {
+        PROM_V0,      /* Original sun4c V0 prom */
+        PROM_V2,      /* sun4c and early sun4m V2 prom */
+        PROM_V3,      /* sun4m and later, up to sun4d/sun4e machines V3 */
+        PROM_P1275,   /* IEEE compliant ISA based Sun PROM, only sun4u */
+        PROM_SUN4,    /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */
+};
+
+extern enum prom_major_version prom_vers;
+/* Revision, and firmware revision. */
+extern unsigned int prom_rev, prom_prev;
+
+/* Root node of the prom device tree, this stays constant after
+ * initialization is complete.
+ */
+extern int prom_root_node;
+
+/* Pointer to prom structure containing the device tree traversal
+ * and usage utility functions.  Only prom-lib should use these,
+ * users use the interface defined by the library only!
+ */
+extern struct linux_nodeops *prom_nodeops;
+
+/* The functions... */
+
+/* You must call prom_init() before using any of the library services,
+ * preferably as early as possible.  Pass it the romvec pointer.
+ */
+extern void prom_init(struct linux_romvec *rom_ptr);
+
+/* Boot argument acquisition, returns the boot command line string. */
+extern char *prom_getbootargs(void);
+
+/* Device utilities. */
+
+/* Map and unmap devices in IO space at virtual addresses. Note that the
+ * virtual address you pass is a request and the prom may put your mappings
+ * somewhere else, so check your return value as that is where your new
+ * mappings really are!
+ *
+ * Another note, these are only available on V2 or higher proms!
+ */
+extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
+extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
+
+/* Device operations. */
+
+/* Open the device described by the passed string.  Note, that the format
+ * of the string is different on V0 vs. V2->higher proms.  The caller must
+ * know what he/she is doing!  Returns the device descriptor, an int.
+ */
+extern int prom_devopen(char *device_string);
+
+/* Close a previously opened device described by the passed integer
+ * descriptor.
+ */
+extern int prom_devclose(int device_handle);
+
+/* Do a seek operation on the device described by the passed integer
+ * descriptor.
+ */
+extern void prom_seek(int device_handle, unsigned int seek_hival,
+                      unsigned int seek_lowval);
+
+/* Miscellaneous routines, don't really fit in any category per se. */
+
+/* Reboot the machine with the command line passed. */
+extern void prom_reboot(char *boot_command);
+
+/* Evaluate the forth string passed. */
+extern void prom_feval(char *forth_string);
+
+/* Enter the prom, with possibility of continuation with the 'go'
+ * command in newer proms.
+ */
+extern void prom_cmdline(void);
+
+/* Enter the prom, with no chance of continuation for the stand-alone
+ * which calls this.
+ */
+extern void prom_halt(void) __attribute__ ((noreturn));
+
+/* Set the PROM 'sync' callback function to the passed function pointer.
+ * When the user gives the 'sync' command at the prom prompt while the
+ * kernel is still active, the prom will call this routine.
+ *
+ * XXX The arguments are different on V0 vs. V2->higher proms, grrr! XXX
+ */
+typedef void (*sync_func_t)(void);
+extern void prom_setsync(sync_func_t func_ptr);
+
+/* Acquire the IDPROM of the root node in the prom device tree.  This
+ * gets passed a buffer where you would like it stuffed.  The return value
+ * is the format type of this idprom or 0xff on error.
+ */
+extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
+
+/* Get the prom major version. */
+extern int prom_version(void);
+
+/* Get the prom plugin revision. */
+extern int prom_getrev(void);
+
+/* Get the prom firmware revision. */
+extern int prom_getprev(void);
+
+/* Character operations to/from the console.... */
+
+/* Non-blocking get character from console. */
+extern int prom_nbgetchar(void);
+
+/* Non-blocking put character to console. */
+extern int prom_nbputchar(char character);
+
+/* Blocking get character from console. */
+extern char prom_getchar(void);
+
+/* Blocking put character to console. */
+extern void prom_putchar(char character);
+
+/* Prom's internal routines, don't use in kernel/boot code. */
+extern void prom_printf(char *fmt, ...);
+extern void prom_write(const char *buf, unsigned int len);
+
+/* Multiprocessor operations... */
+
+/* Start the CPU with the given device tree node, context table, and context
+ * at the passed program counter.
+ */
+extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
+                         int context, char *program_counter);
+
+/* Stop the CPU with the passed device tree node. */
+extern int prom_stopcpu(int cpunode);
+
+/* Idle the CPU with the passed device tree node. */
+extern int prom_idlecpu(int cpunode);
+
+/* Re-Start the CPU with the passed device tree node. */
+extern int prom_restartcpu(int cpunode);
+
+/* PROM memory allocation facilities... */
+
+/* Allocated at possibly the given virtual address a chunk of the
+ * indicated size.
+ */
+extern char *prom_alloc(char *virt_hint, unsigned int size);
+
+/* Free a previously allocated chunk. */
+extern void prom_free(char *virt_addr, unsigned int size);
+
+/* Sun4/sun4c specific memory-management startup hook. */
+
+/* Map the passed segment in the given context at the passed
+ * virtual address.
+ */
+extern void prom_putsegment(int context, unsigned long virt_addr,
+                            int physical_segment);
+
+
+/* PROM device tree traversal functions... */
+
+#ifdef PROMLIB_INTERNAL
+
+/* Internal version of prom_getchild. */
+extern int __prom_getchild(int parent_node);
+
+/* Internal version of prom_getsibling. */
+extern int __prom_getsibling(int node);
+
+#endif
+
+
+/* Get the child node of the given node, or zero if no child exists. */
+extern int prom_getchild(int parent_node);
+
+/* Get the next sibling node of the given node, or zero if no further
+ * siblings exist.
+ */
+extern int prom_getsibling(int node);
+
+/* Get the length, at the passed node, of the given property type.
+ * Returns -1 on error (ie. no such property at this node).
+ */
+extern int prom_getproplen(int thisnode, char *property);
+
+/* Fetch the requested property using the given buffer.  Returns
+ * the number of bytes the prom put into your buffer or -1 on error.
+ */
+extern int __must_check prom_getproperty(int thisnode, char *property,
+                                         char *prop_buffer, int propbuf_size);
+
+/* Acquire an integer property. */
+extern int prom_getint(int node, char *property);
+
+/* Acquire an integer property, with a default value. */
+extern int prom_getintdefault(int node, char *property, int defval);
+
+/* Acquire a boolean property, 0=FALSE 1=TRUE. */
+extern int prom_getbool(int node, char *prop);
+
+/* Acquire a string property, null string on error. */
+extern void prom_getstring(int node, char *prop, char *buf, int bufsize);
+
+/* Does the passed node have the given "name"? YES=1 NO=0 */
+extern int prom_nodematch(int thisnode, char *name);
+
+/* Search all siblings starting at the passed node for "name" matching
+ * the given string.  Returns the node on success, zero on failure.
+ */
+extern int prom_searchsiblings(int node_start, char *name);
+
+/* Return the first property type, as a string, for the given node.
+ * Returns a null string on error.
+ */
+extern char *prom_firstprop(int node, char *buffer);
+
+/* Returns the next property after the passed property for the given
+ * node.  Returns null string on failure.
+ */
+extern char *prom_nextprop(int node, char *prev_property, char *buffer);
+
+/* Returns phandle of the path specified */
+extern int prom_finddevice(char *name);
+
+/* Returns 1 if the specified node has given property. */
+extern int prom_node_has_property(int node, char *property);
+
+/* Set the indicated property at the given node with the passed value.
+ * Returns the number of bytes of your value that the prom took.
+ */
+extern int prom_setprop(int node, char *prop_name, char *prop_value,
+                        int value_size);
+
+extern int prom_pathtoinode(char *path);
+extern int prom_inst2pkg(int);
+
+/* Dorking with Bus ranges... */
+
+/* Apply promlib probes OBIO ranges to registers. */
+extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
+
+/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
+extern void prom_apply_generic_ranges(int node, int parent,
+                                      struct linux_prom_registers *sbusregs, int nregs);
+
+/* CPU probing helpers.  */
+int cpu_find_by_instance(int instance, int *prom_node, int *mid);
+int cpu_find_by_mid(int mid, int *prom_node);
+int cpu_get_hwmid(int prom_node);
+
+extern spinlock_t prom_lock;
+
+#endif /* !(__SPARC_OPLIB_H) */
diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h
new file mode 100644
index 000000000000..6d2c2ca98039
--- /dev/null
+++ b/arch/sparc/include/asm/oplib_64.h
@@ -0,0 +1,322 @@
+/* oplib.h:  Describes the interface and available routines in the
+ *           Linux Prom library.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __SPARC64_OPLIB_H
+#define __SPARC64_OPLIB_H
+
+#include <asm/openprom.h>
+
+/* OBP version string. */
+extern char prom_version[];
+
+/* Root node of the prom device tree, this stays constant after
+ * initialization is complete.
+ */
+extern int prom_root_node;
+
+/* PROM stdin and stdout */
+extern int prom_stdin, prom_stdout;
+
+/* /chosen node of the prom device tree, this stays constant after
+ * initialization is complete.
+ */
+extern int prom_chosen_node;
+
+/* Helper values and strings in arch/sparc64/kernel/head.S */
+extern const char prom_peer_name[];
+extern const char prom_compatible_name[];
+extern const char prom_root_compatible[];
+extern const char prom_cpu_compatible[];
+extern const char prom_finddev_name[];
+extern const char prom_chosen_path[];
+extern const char prom_cpu_path[];
+extern const char prom_getprop_name[];
+extern const char prom_mmu_name[];
+extern const char prom_callmethod_name[];
+extern const char prom_translate_name[];
+extern const char prom_map_name[];
+extern const char prom_unmap_name[];
+extern int prom_mmu_ihandle_cache;
+extern unsigned int prom_boot_mapped_pc;
+extern unsigned int prom_boot_mapping_mode;
+extern unsigned long prom_boot_mapping_phys_high, prom_boot_mapping_phys_low;
+
+struct linux_mlist_p1275 {
+        struct linux_mlist_p1275 *theres_more;
+        unsigned long start_adr;
+        unsigned long num_bytes;
+};
+
+struct linux_mem_p1275 {
+        struct linux_mlist_p1275 **p1275_totphys;
+        struct linux_mlist_p1275 **p1275_prommap;
+        struct linux_mlist_p1275 **p1275_available; /* What we can use */
+};
+
+/* The functions... */
+
+/* You must call prom_init() before using any of the library services,
+ * preferably as early as possible.  Pass it the romvec pointer.
+ */
+extern void prom_init(void *cif_handler, void *cif_stack);
+
+/* Boot argument acquisition, returns the boot command line string. */
+extern char *prom_getbootargs(void);
+
+/* Device utilities. */
+
+/* Device operations. */
+
+/* Open the device described by the passed string.  Note, that the format
+ * of the string is different on V0 vs. V2->higher proms.  The caller must
+ * know what he/she is doing!  Returns the device descriptor, an int.
+ */
+extern int prom_devopen(const char *device_string);
+
+/* Close a previously opened device described by the passed integer
+ * descriptor.
+ */
+extern int prom_devclose(int device_handle);
+
+/* Do a seek operation on the device described by the passed integer
+ * descriptor.
+ */
+extern void prom_seek(int device_handle, unsigned int seek_hival,
+                      unsigned int seek_lowval);
+
+/* Miscellaneous routines, don't really fit in any category per se. */
+
+/* Reboot the machine with the command line passed. */
+extern void prom_reboot(const char *boot_command);
+
+/* Evaluate the forth string passed. */
+extern void prom_feval(const char *forth_string);
+
+/* Enter the prom, with possibility of continuation with the 'go'
+ * command in newer proms.
+ */
+extern void prom_cmdline(void);
+
+/* Enter the prom, with no chance of continuation for the stand-alone
+ * which calls this.
+ */
+extern void prom_halt(void) __attribute__ ((noreturn));
+
+/* Halt and power-off the machine. */
+extern void prom_halt_power_off(void) __attribute__ ((noreturn));
+
+/* Set the PROM 'sync' callback function to the passed function pointer.
+ * When the user gives the 'sync' command at the prom prompt while the
+ * kernel is still active, the prom will call this routine.
+ *
+ */
+typedef int (*callback_func_t)(long *cmd);
+extern void prom_setcallback(callback_func_t func_ptr);
+
+/* Acquire the IDPROM of the root node in the prom device tree.  This
+ * gets passed a buffer where you would like it stuffed.  The return value
+ * is the format type of this idprom or 0xff on error.
+ */
+extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
+
+/* Character operations to/from the console.... */
+
+/* Non-blocking get character from console. */
+extern int prom_nbgetchar(void);
+
+/* Non-blocking put character to console. */
+extern int prom_nbputchar(char character);
+
+/* Blocking get character from console. */
+extern char prom_getchar(void);
+
+/* Blocking put character to console. */
+extern void prom_putchar(char character);
+
+/* Prom's internal routines, don't use in kernel/boot code. */
+extern void prom_printf(const char *fmt, ...);
+extern void prom_write(const char *buf, unsigned int len);
+
+/* Multiprocessor operations... */
+#ifdef CONFIG_SMP
+/* Start the CPU with the given device tree node at the passed program
+ * counter with the given arg passed in via register %o0.
+ */
+extern void prom_startcpu(int cpunode, unsigned long pc, unsigned long arg);
+
+/* Start the CPU with the given cpu ID at the passed program
+ * counter with the given arg passed in via register %o0.
+ */
+extern void prom_startcpu_cpuid(int cpuid, unsigned long pc, unsigned long arg);
+
+/* Stop the CPU with the given cpu ID.  */
+extern void prom_stopcpu_cpuid(int cpuid);
+
+/* Stop the current CPU. */
+extern void prom_stopself(void);
+
+/* Idle the current CPU. */
+extern void prom_idleself(void);
+
+/* Resume the CPU with the passed device tree node. */
+extern void prom_resumecpu(int cpunode);
+#endif
+
+/* Power management interfaces. */
+
+/* Put the current CPU to sleep. */
+extern void prom_sleepself(void);
+
+/* Put the entire system to sleep. */
+extern int prom_sleepsystem(void);
+
+/* Initiate a wakeup event. */
+extern int prom_wakeupsystem(void);
+
+/* MMU and memory related OBP interfaces. */
+
+/* Get unique string identifying SIMM at given physical address. */
+extern int prom_getunumber(int syndrome_code,
+                           unsigned long phys_addr,
+                           char *buf, int buflen);
+
+/* Retain physical memory to the caller across soft resets. */
+extern unsigned long prom_retain(const char *name,
+                                 unsigned long pa_low, unsigned long pa_high,
+                                 long size, long align);
+
+/* Load explicit I/D TLB entries into the calling processor. */
+extern long prom_itlb_load(unsigned long index,
+                           unsigned long tte_data,
+                           unsigned long vaddr);
+
+extern long prom_dtlb_load(unsigned long index,
+                           unsigned long tte_data,
+                           unsigned long vaddr);
+
+/* Map/Unmap client program address ranges.  First the format of
+ * the mapping mode argument.
+ */
+#define PROM_MAP_WRITE  0x0001 /* Writable */
+#define PROM_MAP_READ   0x0002 /* Readable - sw */
+#define PROM_MAP_EXEC   0x0004 /* Executable - sw */
+#define PROM_MAP_LOCKED 0x0010 /* Locked, use i/dtlb load calls for this instead */
+#define PROM_MAP_CACHED 0x0020 /* Cacheable in both L1 and L2 caches */
+#define PROM_MAP_SE     0x0040 /* Side-Effects */
+#define PROM_MAP_GLOB   0x0080 /* Global */
+#define PROM_MAP_IE     0x0100 /* Invert-Endianness */
+#define PROM_MAP_DEFAULT (PROM_MAP_WRITE | PROM_MAP_READ | PROM_MAP_EXEC | PROM_MAP_CACHED)
+
+extern int prom_map(int mode, unsigned long size,
+                    unsigned long vaddr, unsigned long paddr);
+extern void prom_unmap(unsigned long size, unsigned long vaddr);
+
+
+/* PROM device tree traversal functions... */
+
+#ifdef PROMLIB_INTERNAL
+
+/* Internal version of prom_getchild. */
+extern int __prom_getchild(int parent_node);
+
+/* Internal version of prom_getsibling. */
+extern int __prom_getsibling(int node);
+
+#endif
+
+/* Get the child node of the given node, or zero if no child exists. */
+extern int prom_getchild(int parent_node);
+
+/* Get the next sibling node of the given node, or zero if no further
+ * siblings exist.
+ */
+extern int prom_getsibling(int node);
+
+/* Get the length, at the passed node, of the given property type.
+ * Returns -1 on error (ie. no such property at this node).
+ */
+extern int prom_getproplen(int thisnode, const char *property);
+
+/* Fetch the requested property using the given buffer.  Returns
+ * the number of bytes the prom put into your buffer or -1 on error.
+ */
+extern int prom_getproperty(int thisnode, const char *property,
+                            char *prop_buffer, int propbuf_size);
+
+/* Acquire an integer property. */
+extern int prom_getint(int node, const char *property);
+
+/* Acquire an integer property, with a default value. */
+extern int prom_getintdefault(int node, const char *property, int defval);
+
+/* Acquire a boolean property, 0=FALSE 1=TRUE. */
+extern int prom_getbool(int node, const char *prop);
+
+/* Acquire a string property, null string on error. */
+extern void prom_getstring(int node, const char *prop, char *buf, int bufsize);
+
+/* Does the passed node have the given "name"? YES=1 NO=0 */
+extern int prom_nodematch(int thisnode, const char *name);
+
+/* Search all siblings starting at the passed node for "name" matching
+ * the given string.  Returns the node on success, zero on failure.
+ */
+extern int prom_searchsiblings(int node_start, const char *name);
+
+/* Return the first property type, as a string, for the given node.
+ * Returns a null string on error. Buffer should be at least 32B long.
+ */
+extern char *prom_firstprop(int node, char *buffer);
+
+/* Returns the next property after the passed property for the given
+ * node.  Returns null string on failure. Buffer should be at least 32B long.
+ */
+extern char *prom_nextprop(int node, const char *prev_property, char *buffer);
+
+/* Returns 1 if the specified node has given property. */
+extern int prom_node_has_property(int node, const char *property);
+
+/* Returns phandle of the path specified */
+extern int prom_finddevice(const char *name);
+
+/* Set the indicated property at the given node with the passed value.
+ * Returns the number of bytes of your value that the prom took.
+ */
+extern int prom_setprop(int node, const char *prop_name, char *prop_value,
+                        int value_size);
+
+extern int prom_pathtoinode(const char *path);
+extern int prom_inst2pkg(int);
+extern int prom_service_exists(const char *service_name);
+extern void prom_sun4v_guest_soft_state(void);
+
+extern int prom_ihandle2path(int handle, char *buffer, int bufsize);
+
+/* Client interface level routines. */
+extern long p1275_cmd(const char *, long, ...);
+
+#if 0
+#define P1275_SIZE(x) ((((long)((x) / 32)) << 32) | (x))
+#else
+#define P1275_SIZE(x) x
+#endif
+
+/* We support at most 16 input and 1 output argument */
+#define P1275_ARG_NUMBER                0
+#define P1275_ARG_IN_STRING             1
+#define P1275_ARG_OUT_BUF               2
+#define P1275_ARG_OUT_32B               3
+#define P1275_ARG_IN_FUNCTION           4
+#define P1275_ARG_IN_BUF                5
+#define P1275_ARG_IN_64B                6
+
+#define P1275_IN(x) ((x) & 0xf)
+#define P1275_OUT(x) (((x) << 4) & 0xf0)
+#define P1275_INOUT(i,o) (P1275_IN(i)|P1275_OUT(o))
+#define P1275_ARG(n,x) ((x) << ((n)*3 + 8))
+
+#endif /* !(__SPARC64_OPLIB_H) */
diff --git a/arch/sparc/include/asm/page.h b/arch/sparc/include/asm/page.h
new file mode 100644
index 000000000000..f21de0349025
--- /dev/null
+++ b/arch/sparc/include/asm/page.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_PAGE_H
+#define ___ASM_SPARC_PAGE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/page_64.h>
+#else
+#include <asm/page_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
new file mode 100644
index 000000000000..cf5fb70ca1c1
--- /dev/null
+++ b/arch/sparc/include/asm/page_32.h
@@ -0,0 +1,160 @@
+/*
+ * page.h:  Various defines and such for MMU operations on the Sparc for
+ *          the Linux kernel.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_PAGE_H
+#define _SPARC_PAGE_H
+
+#ifdef CONFIG_SUN4
+#define PAGE_SHIFT   13
+#else
+#define PAGE_SHIFT   12
+#endif
+#ifndef __ASSEMBLY__
+/* I have my suspicions... -DaveM */
+#define PAGE_SIZE    (1UL << PAGE_SHIFT)
+#else
+#define PAGE_SIZE    (1 << PAGE_SHIFT)
+#endif
+#define PAGE_MASK    (~(PAGE_SIZE-1))
+
+#include <asm/btfixup.h>
+
+#ifndef __ASSEMBLY__
+
+#define clear_page(page)         memset((void *)(page), 0, PAGE_SIZE)
+#define copy_page(to,from)      memcpy((void *)(to), (void *)(from), PAGE_SIZE)
+#define clear_user_page(addr, vaddr, page)      \
+        do {    clear_page(addr);               \
+                sparc_flush_page_to_ram(page);  \
+        } while (0)
+#define copy_user_page(to, from, vaddr, page)   \
+        do {    copy_page(to, from);            \
+                sparc_flush_page_to_ram(page);  \
+        } while (0)
+
+/* The following structure is used to hold the physical
+ * memory configuration of the machine.  This is filled in
+ * prom_meminit() and is later used by mem_init() to set up
+ * mem_map[].  We statically allocate SPARC_PHYS_BANKS+1 of
+ * these structs, this is arbitrary.  The entry after the
+ * last valid one has num_bytes==0.
+ */
+struct sparc_phys_banks {
+  unsigned long base_addr;
+  unsigned long num_bytes;
+};
+
+#define SPARC_PHYS_BANKS 32
+
+extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
+
+/* Cache alias structure.  Entry is valid if context != -1. */
+struct cache_palias {
+        unsigned long vaddr;
+        int context;
+};
+
+/* passing structs on the Sparc slow us down tremendously... */
+
+/* #define STRICT_MM_TYPECHECKS */
+
+#ifdef STRICT_MM_TYPECHECKS
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long iopte; } iopte_t;
+typedef struct { unsigned long pmdv[16]; } pmd_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long ctxd; } ctxd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long iopgprot; } iopgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define iopte_val(x)    ((x).iopte)
+#define pmd_val(x)      ((x).pmdv[0])
+#define pgd_val(x)      ((x).pgd)
+#define ctxd_val(x)     ((x).ctxd)
+#define pgprot_val(x)   ((x).pgprot)
+#define iopgprot_val(x) ((x).iopgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __iopte(x)      ((iopte_t) { (x) } )
+/* #define __pmd(x)        ((pmd_t) { (x) } ) */ /* XXX procedure with loop */
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __ctxd(x)       ((ctxd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+#define __iopgprot(x)   ((iopgprot_t) { (x) } )
+
+#else
+/*
+ * .. while these make it easier on the compiler
+ */
+typedef unsigned long pte_t;
+typedef unsigned long iopte_t;
+typedef struct { unsigned long pmdv[16]; } pmd_t;
+typedef unsigned long pgd_t;
+typedef unsigned long ctxd_t;
+typedef unsigned long pgprot_t;
+typedef unsigned long iopgprot_t;
+
+#define pte_val(x)      (x)
+#define iopte_val(x)    (x)
+#define pmd_val(x)      ((x).pmdv[0])
+#define pgd_val(x)      (x)
+#define ctxd_val(x)     (x)
+#define pgprot_val(x)   (x)
+#define iopgprot_val(x) (x)
+
+#define __pte(x)        (x)
+#define __iopte(x)      (x)
+/* #define __pmd(x)        (x) */ /* XXX later */
+#define __pgd(x)        (x)
+#define __ctxd(x)       (x)
+#define __pgprot(x)     (x)
+#define __iopgprot(x)   (x)
+
+#endif
+
+typedef struct page *pgtable_t;
+
+extern unsigned long sparc_unmapped_base;
+
+BTFIXUPDEF_SETHI(sparc_unmapped_base)
+
+#define TASK_UNMAPPED_BASE      BTFIXUP_SETHI(sparc_unmapped_base)
+
+#else /* !(__ASSEMBLY__) */
+
+#define __pgprot(x)     (x)
+
+#endif /* !(__ASSEMBLY__) */
+
+#define PAGE_OFFSET     0xf0000000
+#ifndef __ASSEMBLY__
+extern unsigned long phys_base;
+extern unsigned long pfn_base;
+#endif
+#define __pa(x)                 ((unsigned long)(x) - PAGE_OFFSET + phys_base)
+#define __va(x)                 ((void *)((unsigned long) (x) - phys_base + PAGE_OFFSET))
+
+#define virt_to_phys            __pa
+#define phys_to_virt            __va
+
+#define ARCH_PFN_OFFSET         (pfn_base)
+#define virt_to_page(kaddr)     (mem_map + ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT)))
+
+#define pfn_valid(pfn)          (((pfn) >= (pfn_base)) && (((pfn)-(pfn_base)) < max_mapnr))
+#define virt_addr_valid(kaddr)  ((((unsigned long)(kaddr)-PAGE_OFFSET)>>PAGE_SHIFT) < max_mapnr)
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/page.h>
+
+#endif /* _SPARC_PAGE_H */
diff --git a/arch/sparc/include/asm/page_64.h b/arch/sparc/include/asm/page_64.h
new file mode 100644
index 000000000000..b579b910ef51
--- /dev/null
+++ b/arch/sparc/include/asm/page_64.h
@@ -0,0 +1,135 @@
+#ifndef _SPARC64_PAGE_H
+#define _SPARC64_PAGE_H
+
+#include <linux/const.h>
+
+#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
+#define PAGE_SHIFT   13
+#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
+#define PAGE_SHIFT   16
+#else
+#error No page size specified in kernel configuration
+#endif
+
+#define PAGE_SIZE    (_AC(1,UL) << PAGE_SHIFT)
+#define PAGE_MASK    (~(PAGE_SIZE-1))
+
+/* Flushing for D-cache alias handling is only needed if
+ * the page size is smaller than 16K.
+ */
+#if PAGE_SHIFT < 14
+#define DCACHE_ALIASING_POSSIBLE
+#endif
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define HPAGE_SHIFT             22
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
+#define HPAGE_SHIFT             19
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define HPAGE_SHIFT             16
+#endif
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define HPAGE_SIZE              (_AC(1,UL) << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE - 1UL))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+#endif
+
+#ifndef __ASSEMBLY__
+
+extern void _clear_page(void *page);
+#define clear_page(X)   _clear_page((void *)(X))
+struct page;
+extern void clear_user_page(void *addr, unsigned long vaddr, struct page *page);
+#define copy_page(X,Y)  memcpy((void *)(X), (void *)(Y), PAGE_SIZE)
+extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *topage);
+
+/* Unlike sparc32, sparc64's parameter passing API is more
+ * sane in that structures which as small enough are passed
+ * in registers instead of on the stack.  Thus, setting
+ * STRICT_MM_TYPECHECKS does not generate worse code so
+ * let's enable it to get the type checking.
+ */
+
+#define STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+/* These are used to make use of C type-checking.. */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long iopte; } iopte_t;
+typedef struct { unsigned int pmd; } pmd_t;
+typedef struct { unsigned int pgd; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define iopte_val(x)    ((x).iopte)
+#define pmd_val(x)      ((x).pmd)
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __iopte(x)      ((iopte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+#else
+/* .. while these make it easier on the compiler */
+typedef unsigned long pte_t;
+typedef unsigned long iopte_t;
+typedef unsigned int pmd_t;
+typedef unsigned int pgd_t;
+typedef unsigned long pgprot_t;
+
+#define pte_val(x)      (x)
+#define iopte_val(x)    (x)
+#define pmd_val(x)      (x)
+#define pgd_val(x)      (x)
+#define pgprot_val(x)   (x)
+
+#define __pte(x)        (x)
+#define __iopte(x)      (x)
+#define __pmd(x)        (x)
+#define __pgd(x)        (x)
+#define __pgprot(x)     (x)
+
+#endif /* (STRICT_MM_TYPECHECKS) */
+
+typedef struct page *pgtable_t;
+
+#define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_32BIT) ? \
+                                 (_AC(0x0000000070000000,UL)) : \
+                                 (_AC(0xfffff80000000000,UL) + (1UL << 32UL)))
+
+#include <asm-generic/memory_model.h>
+
+#endif /* !(__ASSEMBLY__) */
+
+/* We used to stick this into a hard-coded global register (%g4)
+ * but that does not make sense anymore.
+ */
+#define PAGE_OFFSET             _AC(0xFFFFF80000000000,UL)
+
+#ifndef __ASSEMBLY__
+
+#define __pa(x)                 ((unsigned long)(x) - PAGE_OFFSET)
+#define __va(x)                 ((void *)((unsigned long) (x) + PAGE_OFFSET))
+
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr)>>PAGE_SHIFT)
+
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+#define virt_to_phys __pa
+#define phys_to_virt __va
+
+#endif /* !(__ASSEMBLY__) */
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/page.h>
+
+#endif /* _SPARC64_PAGE_H */
diff --git a/arch/sparc/include/asm/param.h b/arch/sparc/include/asm/param.h
new file mode 100644
index 000000000000..9836d9a3cb9a
--- /dev/null
+++ b/arch/sparc/include/asm/param.h
@@ -0,0 +1,22 @@
+#ifndef _ASMSPARC_PARAM_H
+#define _ASMSPARC_PARAM_H
+
+#ifdef __KERNEL__
+# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
+# define USER_HZ        100     /* .. some user interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   8192    /* Thanks for sun4's we carry baggage... */
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif
diff --git a/arch/sparc/include/asm/parport.h b/arch/sparc/include/asm/parport.h
new file mode 100644
index 000000000000..7818b2523b8d
--- /dev/null
+++ b/arch/sparc/include/asm/parport.h
@@ -0,0 +1,246 @@
+/* parport.h: sparc64 specific parport initialization and dma.
+ *
+ * Copyright (C) 1999  Eddie C. Dost  (ecd@skynet.be)
+ */
+
+#ifndef _ASM_SPARC64_PARPORT_H
+#define _ASM_SPARC64_PARPORT_H 1
+
+#include <asm/ebus.h>
+#include <asm/ns87303.h>
+#include <asm/of_device.h>
+#include <asm/prom.h>
+
+#define PARPORT_PC_MAX_PORTS    PARPORT_MAX
+
+/*
+ * While sparc64 doesn't have an ISA DMA API, we provide something that looks
+ * close enough to make parport_pc happy
+ */
+#define HAS_DMA
+
+static DEFINE_SPINLOCK(dma_spin_lock);
+
+#define claim_dma_lock() \
+({      unsigned long flags; \
+        spin_lock_irqsave(&dma_spin_lock, flags); \
+        flags; \
+})
+
+#define release_dma_lock(__flags) \
+        spin_unlock_irqrestore(&dma_spin_lock, __flags);
+
+static struct sparc_ebus_info {
+        struct ebus_dma_info info;
+        unsigned int addr;
+        unsigned int count;
+        int lock;
+
+        struct parport *port;
+} sparc_ebus_dmas[PARPORT_PC_MAX_PORTS];
+
+static DECLARE_BITMAP(dma_slot_map, PARPORT_PC_MAX_PORTS);
+
+static inline int request_dma(unsigned int dmanr, const char *device_id)
+{
+        if (dmanr >= PARPORT_PC_MAX_PORTS)
+                return -EINVAL;
+        if (xchg(&sparc_ebus_dmas[dmanr].lock, 1) != 0)
+                return -EBUSY;
+        return 0;
+}
+
+static inline void free_dma(unsigned int dmanr)
+{
+        if (dmanr >= PARPORT_PC_MAX_PORTS) {
+                printk(KERN_WARNING "Trying to free DMA%d\n", dmanr);
+                return;
+        }
+        if (xchg(&sparc_ebus_dmas[dmanr].lock, 0) == 0) {
+                printk(KERN_WARNING "Trying to free free DMA%d\n", dmanr);
+                return;
+        }
+}
+
+static inline void enable_dma(unsigned int dmanr)
+{
+        ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 1);
+
+        if (ebus_dma_request(&sparc_ebus_dmas[dmanr].info,
+                             sparc_ebus_dmas[dmanr].addr,
+                             sparc_ebus_dmas[dmanr].count))
+                BUG();
+}
+
+static inline void disable_dma(unsigned int dmanr)
+{
+        ebus_dma_enable(&sparc_ebus_dmas[dmanr].info, 0);
+}
+
+static inline void clear_dma_ff(unsigned int dmanr)
+{
+        /* nothing */
+}
+
+static inline void set_dma_mode(unsigned int dmanr, char mode)
+{
+        ebus_dma_prepare(&sparc_ebus_dmas[dmanr].info, (mode != DMA_MODE_WRITE));
+}
+
+static inline void set_dma_addr(unsigned int dmanr, unsigned int addr)
+{
+        sparc_ebus_dmas[dmanr].addr = addr;
+}
+
+static inline void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        sparc_ebus_dmas[dmanr].count = count;
+}
+
+static inline unsigned int get_dma_residue(unsigned int dmanr)
+{
+        return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info);
+}
+
+static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id *match)
+{
+        unsigned long base = op->resource[0].start;
+        unsigned long config = op->resource[1].start;
+        unsigned long d_base = op->resource[2].start;
+        unsigned long d_len;
+        struct device_node *parent;
+        struct parport *p;
+        int slot, err;
+
+        parent = op->node->parent;
+        if (!strcmp(parent->name, "dma")) {
+                p = parport_pc_probe_port(base, base + 0x400,
+                                          op->irqs[0], PARPORT_DMA_NOFIFO,
+                                          op->dev.parent->parent);
+                if (!p)
+                        return -ENOMEM;
+                dev_set_drvdata(&op->dev, p);
+                return 0;
+        }
+
+        for (slot = 0; slot < PARPORT_PC_MAX_PORTS; slot++) {
+                if (!test_and_set_bit(slot, dma_slot_map))
+                        break;
+        }
+        err = -ENODEV;
+        if (slot >= PARPORT_PC_MAX_PORTS)
+                goto out_err;
+
+        spin_lock_init(&sparc_ebus_dmas[slot].info.lock);
+
+        d_len = (op->resource[2].end - d_base) + 1UL;
+        sparc_ebus_dmas[slot].info.regs =
+                of_ioremap(&op->resource[2], 0, d_len, "ECPP DMA");
+
+        if (!sparc_ebus_dmas[slot].info.regs)
+                goto out_clear_map;
+
+        sparc_ebus_dmas[slot].info.flags = 0;
+        sparc_ebus_dmas[slot].info.callback = NULL;
+        sparc_ebus_dmas[slot].info.client_cookie = NULL;
+        sparc_ebus_dmas[slot].info.irq = 0xdeadbeef;
+        strcpy(sparc_ebus_dmas[slot].info.name, "parport");
+        if (ebus_dma_register(&sparc_ebus_dmas[slot].info))
+                goto out_unmap_regs;
+
+        ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 1);
+
+        /* Configure IRQ to Push Pull, Level Low */
+        /* Enable ECP, set bit 2 of the CTR first */
+        outb(0x04, base + 0x02);
+        ns87303_modify(config, PCR,
+                       PCR_EPP_ENABLE |
+                       PCR_IRQ_ODRAIN,
+                       PCR_ECP_ENABLE |
+                       PCR_ECP_CLK_ENA |
+                       PCR_IRQ_POLAR);
+
+        /* CTR bit 5 controls direction of port */
+        ns87303_modify(config, PTR,
+                       0, PTR_LPT_REG_DIR);
+
+        p = parport_pc_probe_port(base, base + 0x400,
+                                  op->irqs[0],
+                                  slot,
+                                  op->dev.parent);
+        err = -ENOMEM;
+        if (!p)
+                goto out_disable_irq;
+
+        dev_set_drvdata(&op->dev, p);
+
+        return 0;
+
+out_disable_irq:
+        ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
+        ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
+
+out_unmap_regs:
+        of_iounmap(&op->resource[2], sparc_ebus_dmas[slot].info.regs, d_len);
+
+out_clear_map:
+        clear_bit(slot, dma_slot_map);
+
+out_err:
+        return err;
+}
+
+static int __devexit ecpp_remove(struct of_device *op)
+{
+        struct parport *p = dev_get_drvdata(&op->dev);
+        int slot = p->dma;
+
+        parport_pc_unregister_port(p);
+
+        if (slot != PARPORT_DMA_NOFIFO) {
+                unsigned long d_base = op->resource[2].start;
+                unsigned long d_len;
+
+                d_len = (op->resource[2].end - d_base) + 1UL;
+
+                ebus_dma_irq_enable(&sparc_ebus_dmas[slot].info, 0);
+                ebus_dma_unregister(&sparc_ebus_dmas[slot].info);
+                of_iounmap(&op->resource[2],
+                           sparc_ebus_dmas[slot].info.regs,
+                           d_len);
+                clear_bit(slot, dma_slot_map);
+        }
+
+        return 0;
+}
+
+static struct of_device_id ecpp_match[] = {
+        {
+                .name = "ecpp",
+        },
+        {
+                .name = "parallel",
+                .compatible = "ecpp",
+        },
+        {
+                .name = "parallel",
+                .compatible = "ns87317-ecpp",
+        },
+        {},
+};
+
+static struct of_platform_driver ecpp_driver = {
+        .name                   = "ecpp",
+        .match_table            = ecpp_match,
+        .probe                  = ecpp_probe,
+        .remove                 = __devexit_p(ecpp_remove),
+};
+
+static int parport_pc_find_nonpci_ports(int autoirq, int autodma)
+{
+        of_register_driver(&ecpp_driver, &of_bus_type);
+
+        return 0;
+}
+
+#endif /* !(_ASM_SPARC64_PARPORT_H */
diff --git a/arch/sparc/include/asm/pbm.h b/arch/sparc/include/asm/pbm.h
new file mode 100644
index 000000000000..458a4916d14d
--- /dev/null
+++ b/arch/sparc/include/asm/pbm.h
@@ -0,0 +1,47 @@
+/*
+ *
+ * pbm.h: PCI bus module pseudo driver software state
+ *        Adopted from sparc64 by V. Roganov and G. Raiko
+ *
+ * Original header:
+ * pbm.h: U2P PCI bus module pseudo driver software state.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * To put things into perspective, consider sparc64 with a few PCI controllers.
+ * Each type would have an own structure, with instances related one to one.
+ * We have only pcic on sparc, but we want to be compatible with sparc64 pbm.h.
+ * All three represent different abstractions.
+ *   pci_bus  - Linux PCI subsystem view of a PCI bus (including bridged buses)
+ *   pbm      - Arch-specific view of a PCI bus (sparc or sparc64)
+ *   pcic     - Chip-specific information for PCIC.
+ */
+
+#ifndef __SPARC_PBM_H
+#define __SPARC_PBM_H
+
+#include <linux/pci.h>
+#include <asm/oplib.h>
+#include <asm/prom.h>
+
+struct linux_pbm_info {
+        int             prom_node;
+        char            prom_name[64];
+        /* struct linux_prom_pci_ranges pbm_ranges[PROMREG_MAX]; */
+        /* int          num_pbm_ranges; */
+
+        /* Now things for the actual PCI bus probes. */
+        unsigned int    pci_first_busno;        /* Can it be nonzero? */
+        struct pci_bus  *pci_bus;               /* Was inline, MJ allocs now */
+};
+
+/* PCI devices which are not bridges have this placed in their pci_dev
+ * sysdata member.  This makes OBP aware PCI device drivers easier to
+ * code.
+ */
+struct pcidev_cookie {
+        struct linux_pbm_info           *pbm;
+        struct device_node              *prom_node;
+};
+
+#endif /* !(__SPARC_PBM_H) */
diff --git a/arch/sparc/include/asm/pci.h b/arch/sparc/include/asm/pci.h
new file mode 100644
index 000000000000..6e14fd179335
--- /dev/null
+++ b/arch/sparc/include/asm/pci.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_PCI_H
+#define ___ASM_SPARC_PCI_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/pci_64.h>
+#else
+#include <asm/pci_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
new file mode 100644
index 000000000000..0ee949d220c0
--- /dev/null
+++ b/arch/sparc/include/asm/pci_32.h
@@ -0,0 +1,171 @@
+#ifndef __SPARC_PCI_H
+#define __SPARC_PCI_H
+
+#ifdef __KERNEL__
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+ * already-configured bus numbers - to be used for buggy BIOSes
+ * or architectures with incomplete PCI setup by the loader.
+ */
+#define pcibios_assign_all_busses()     0
+#define pcibios_scan_all_fns(a, b)      0
+
+#define PCIBIOS_MIN_IO          0UL
+#define PCIBIOS_MIN_MEM         0UL
+
+#define PCI_IRQ_NONE            0xffffffff
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/* Dynamic DMA mapping stuff.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (0)
+
+#include <asm/scatterlist.h>
+
+struct pci_dev;
+
+/* Allocate and map kernel buffer using consistent mode DMA for a device.
+ * hwdev should be valid struct pci_dev pointer for PCI devices.
+ */
+extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
+
+/* Free and unmap a consistent DMA buffer.
+ * cpu_addr is what was returned from pci_alloc_consistent,
+ * size must be the same as what as passed into pci_alloc_consistent,
+ * and likewise dma_addr must be the same as what *dma_addrp was set to.
+ *
+ * References to the memory and mappings assosciated with cpu_addr/dma_addr
+ * past this call are illegal.
+ */
+extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
+
+/* Map a single buffer of the indicated size for DMA in streaming mode.
+ * The 32-bit bus address to use is returned.
+ *
+ * Once the device is given the dma address, the device owns this memory
+ * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
+ */
+extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
+
+/* Unmap a single streaming mode DMA translation.  The dma_addr and size
+ * must match what was provided for in a previous pci_map_single call.  All
+ * other usages are undefined.
+ *
+ * After this call, reads by the cpu to the buffer are guaranteed to see
+ * whatever the device wrote there.
+ */
+extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
+
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+
+/*
+ * Same as above, only with pages instead of mapped addresses.
+ */
+extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
+                        unsigned long offset, size_t size, int direction);
+extern void pci_unmap_page(struct pci_dev *hwdev,
+                        dma_addr_t dma_address, size_t size, int direction);
+
+/* Map a set of buffers described by scatterlist in streaming
+ * mode for DMA.  This is the scather-gather version of the
+ * above pci_map_single interface.  Here the scatter gather list
+ * elements are each tagged with the appropriate dma address
+ * and length.  They are obtained via sg_dma_{address,length}(SG).
+ *
+ * NOTE: An implementation may be able to use a smaller number of
+ *       DMA address/length pairs than there are SG table elements.
+ *       (for example via virtual mapping capabilities)
+ *       The routine returns the number of addr/length pairs actually
+ *       used, at most nents.
+ *
+ * Device ownership issues as mentioned above for pci_map_single are
+ * the same here.
+ */
+extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
+
+/* Unmap a set of streaming mode DMA translations.
+ * Again, cpu read rules concerning calls here are the same as for
+ * pci_unmap_single() above.
+ */
+extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
+
+/* Make physical memory consistent for a single
+ * streaming mode DMA translation after a transfer.
+ *
+ * If you perform a pci_map_single() but wish to interrogate the
+ * buffer using the cpu, yet do not wish to teardown the PCI dma
+ * mapping, you must call this function before doing so.  At the
+ * next point you give the PCI dma address back to the card, you
+ * must first perform a pci_dma_sync_for_device, and then the device
+ * again owns the buffer.
+ */
+extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
+extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
+
+/* Make physical memory consistent for a set of streaming
+ * mode DMA translations after a transfer.
+ *
+ * The same as pci_dma_sync_single_* but for a scatter-gather list,
+ * same rules and usage.
+ */
+extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
+extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
+
+/* Return whether the given PCI device DMA address mask can
+ * be supported properly.  For example, if your device can
+ * only drive the low 24-bits during PCI bus mastering, then
+ * you would pass 0x00ffffff as the mask to this function.
+ */
+static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
+{
+        return 1;
+}
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
+#define PCI_DMA_ERROR_CODE      (~(dma_addr_t)0x0)
+
+static inline int pci_dma_mapping_error(struct pci_dev *pdev,
+                                        dma_addr_t dma_addr)
+{
+        return (dma_addr == PCI_DMA_ERROR_CODE);
+}
+
+struct device_node;
+extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
+
+#endif /* __KERNEL__ */
+
+/* generic pci stuff */
+#include <asm-generic/pci.h>
+
+#endif /* __SPARC_PCI_H */
diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h
new file mode 100644
index 000000000000..4f79a54948f6
--- /dev/null
+++ b/arch/sparc/include/asm/pci_64.h
@@ -0,0 +1,210 @@
+#ifndef __SPARC64_PCI_H
+#define __SPARC64_PCI_H
+
+#ifdef __KERNEL__
+
+#include <linux/dma-mapping.h>
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+ * already-configured bus numbers - to be used for buggy BIOSes
+ * or architectures with incomplete PCI setup by the loader.
+ */
+#define pcibios_assign_all_busses()     0
+#define pcibios_scan_all_fns(a, b)      0
+
+#define PCIBIOS_MIN_IO          0UL
+#define PCIBIOS_MIN_MEM         0UL
+
+#define PCI_IRQ_NONE            0xffffffff
+
+#define PCI_CACHE_LINE_BYTES    64
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/* The PCI address space does not equal the physical memory
+ * address space.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (0)
+
+static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
+                                         dma_addr_t *dma_handle)
+{
+        return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
+}
+
+static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
+                                       void *vaddr, dma_addr_t dma_handle)
+{
+        return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
+}
+
+static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
+                                        size_t size, int direction)
+{
+        return dma_map_single(&pdev->dev, ptr, size,
+                              (enum dma_data_direction) direction);
+}
+
+static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
+                                    size_t size, int direction)
+{
+        dma_unmap_single(&pdev->dev, dma_addr, size,
+                         (enum dma_data_direction) direction);
+}
+
+#define pci_map_page(dev, page, off, size, dir) \
+        pci_map_single(dev, (page_address(page) + (off)), size, dir)
+#define pci_unmap_page(dev,addr,sz,dir) \
+        pci_unmap_single(dev,addr,sz,dir)
+
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
+        dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
+        __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)                  \
+        ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
+        (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)                    \
+        ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
+        (((PTR)->LEN_NAME) = (VAL))
+
+static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
+                             int nents, int direction)
+{
+        return dma_map_sg(&pdev->dev, sg, nents,
+                          (enum dma_data_direction) direction);
+}
+
+static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
+                                int nents, int direction)
+{
+        dma_unmap_sg(&pdev->dev, sg, nents,
+                     (enum dma_data_direction) direction);
+}
+
+static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
+                                               dma_addr_t dma_handle,
+                                               size_t size, int direction)
+{
+        dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
+                                (enum dma_data_direction) direction);
+}
+
+static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
+                                                  dma_addr_t dma_handle,
+                                                  size_t size, int direction)
+{
+        /* No flushing needed to sync cpu writes to the device.  */
+}
+
+static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
+                                           struct scatterlist *sg,
+                                           int nents, int direction)
+{
+        dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
+                            (enum dma_data_direction) direction);
+}
+
+static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
+                                              struct scatterlist *sg,
+                                              int nelems, int direction)
+{
+        /* No flushing needed to sync cpu writes to the device.  */
+}
+
+/* Return whether the given PCI device DMA address mask can
+ * be supported properly.  For example, if your device can
+ * only drive the low 24-bits during PCI bus mastering, then
+ * you would pass 0x00ffffff as the mask to this function.
+ */
+extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
+
+/* PCI IOMMU mapping bypass support. */
+
+/* PCI 64-bit addressing works for all slots on all controller
+ * types on sparc64.  However, it requires that the device
+ * can drive enough of the 64 bits.
+ */
+#define PCI64_REQUIRED_MASK     (~(dma64_addr_t)0)
+#define PCI64_ADDR_BASE         0xfffc000000000000UL
+
+static inline int pci_dma_mapping_error(struct pci_dev *pdev,
+                                        dma_addr_t dma_addr)
+{
+        return dma_mapping_error(&pdev->dev, dma_addr);
+}
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+        if (byte == 0)
+                cacheline_size = 1024;
+        else
+                cacheline_size = (int) byte * 4;
+
+        *strat = PCI_DMA_BURST_BOUNDARY;
+        *strategy_parameter = cacheline_size;
+}
+#endif
+
+/* Return the index of the PCI controller for device PDEV. */
+
+extern int pci_domain_nr(struct pci_bus *bus);
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        return 1;
+}
+
+/* Platform support for /proc/bus/pci/X/Y mmap()s. */
+
+#define HAVE_PCI_MMAP
+#define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
+#define get_pci_unmapped_area get_fb_unmapped_area
+
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+                               enum pci_mmap_state mmap_state,
+                               int write_combine);
+
+extern void
+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+                        struct resource *res);
+
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                        struct pci_bus_region *region);
+
+extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
+
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        return PCI_IRQ_NONE;
+}
+
+struct device_node;
+extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
+
+#define HAVE_ARCH_PCI_RESOURCE_TO_USER
+extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
+                                 const struct resource *rsrc,
+                                 resource_size_t *start, resource_size_t *end);
+#endif /* __KERNEL__ */
+
+#endif /* __SPARC64_PCI_H */
diff --git a/arch/sparc/include/asm/pcic.h b/arch/sparc/include/asm/pcic.h
new file mode 100644
index 000000000000..f20ef562b265
--- /dev/null
+++ b/arch/sparc/include/asm/pcic.h
@@ -0,0 +1,123 @@
+/*
+ * pcic.h: JavaEngine 1 specific PCI definitions.
+ *
+ * Copyright (C) 1998 V. Roganov and G. Raiko
+ */
+
+#ifndef __SPARC_PCIC_H
+#define __SPARC_PCIC_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <linux/smp.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <asm/pbm.h>
+
+struct linux_pcic {
+        void __iomem            *pcic_regs;
+        unsigned long           pcic_io;
+        void __iomem            *pcic_config_space_addr;
+        void __iomem            *pcic_config_space_data;
+        struct resource         pcic_res_regs;
+        struct resource         pcic_res_io;
+        struct resource         pcic_res_cfg_addr;
+        struct resource         pcic_res_cfg_data;
+        struct linux_pbm_info   pbm;
+        struct pcic_ca2irq      *pcic_imap;
+        int                     pcic_imdim;
+};
+
+extern int pcic_probe(void);
+/* Erm... MJ redefined pcibios_present() so that it does not work early. */
+extern int pcic_present(void);
+extern void sun4m_pci_init_IRQ(void);
+
+#endif
+
+/* Size of PCI I/O space which we relocate. */
+#define PCI_SPACE_SIZE                  0x1000000       /* 16 MB */
+
+/* PCIC Register Set. */
+#define PCI_DIAGNOSTIC_0                0x40    /* 32 bits */
+#define PCI_SIZE_0                      0x44    /* 32 bits */
+#define PCI_SIZE_1                      0x48    /* 32 bits */
+#define PCI_SIZE_2                      0x4c    /* 32 bits */
+#define PCI_SIZE_3                      0x50    /* 32 bits */
+#define PCI_SIZE_4                      0x54    /* 32 bits */
+#define PCI_SIZE_5                      0x58    /* 32 bits */
+#define PCI_PIO_CONTROL                 0x60    /* 8  bits */
+#define PCI_DVMA_CONTROL                0x62    /* 8  bits */
+#define  PCI_DVMA_CONTROL_INACTIVITY_REQ        (1<<0)
+#define  PCI_DVMA_CONTROL_IOTLB_ENABLE          (1<<0)
+#define  PCI_DVMA_CONTROL_IOTLB_DISABLE         0
+#define  PCI_DVMA_CONTROL_INACTIVITY_ACK        (1<<4)
+#define PCI_INTERRUPT_CONTROL           0x63    /* 8  bits */
+#define PCI_CPU_INTERRUPT_PENDING       0x64    /* 32 bits */
+#define PCI_DIAGNOSTIC_1                0x68    /* 16 bits */
+#define PCI_SOFTWARE_INT_CLEAR          0x6a    /* 16 bits */
+#define PCI_SOFTWARE_INT_SET            0x6e    /* 16 bits */
+#define PCI_SYS_INT_PENDING             0x70    /* 32 bits */
+#define  PCI_SYS_INT_PENDING_PIO                0x40000000
+#define  PCI_SYS_INT_PENDING_DMA                0x20000000
+#define  PCI_SYS_INT_PENDING_PCI                0x10000000
+#define  PCI_SYS_INT_PENDING_APSR               0x08000000
+#define PCI_SYS_INT_TARGET_MASK         0x74    /* 32 bits */
+#define PCI_SYS_INT_TARGET_MASK_CLEAR   0x78    /* 32 bits */
+#define PCI_SYS_INT_TARGET_MASK_SET     0x7c    /* 32 bits */
+#define PCI_SYS_INT_PENDING_CLEAR       0x83    /* 8  bits */
+#define  PCI_SYS_INT_PENDING_CLEAR_ALL          0x80
+#define  PCI_SYS_INT_PENDING_CLEAR_PIO          0x40
+#define  PCI_SYS_INT_PENDING_CLEAR_DMA          0x20
+#define  PCI_SYS_INT_PENDING_CLEAR_PCI          0x10
+#define PCI_IOTLB_CONTROL               0x84    /* 8  bits */
+#define PCI_INT_SELECT_LO               0x88    /* 16 bits */
+#define PCI_ARBITRATION_SELECT          0x8a    /* 16 bits */
+#define PCI_INT_SELECT_HI               0x8c    /* 16 bits */
+#define PCI_HW_INT_OUTPUT               0x8e    /* 16 bits */
+#define PCI_IOTLB_RAM_INPUT             0x90    /* 32 bits */
+#define PCI_IOTLB_CAM_INPUT             0x94    /* 32 bits */
+#define PCI_IOTLB_RAM_OUTPUT            0x98    /* 32 bits */
+#define PCI_IOTLB_CAM_OUTPUT            0x9c    /* 32 bits */
+#define PCI_SMBAR0                      0xa0    /* 8  bits */
+#define PCI_MSIZE0                      0xa1    /* 8  bits */
+#define PCI_PMBAR0                      0xa2    /* 8  bits */
+#define PCI_SMBAR1                      0xa4    /* 8  bits */
+#define PCI_MSIZE1                      0xa5    /* 8  bits */
+#define PCI_PMBAR1                      0xa6    /* 8  bits */
+#define PCI_SIBAR                       0xa8    /* 8  bits */
+#define   PCI_SIBAR_ADDRESS_MASK        0xf
+#define PCI_ISIZE                       0xa9    /* 8  bits */
+#define   PCI_ISIZE_16M                 0xf
+#define   PCI_ISIZE_32M                 0xe
+#define   PCI_ISIZE_64M                 0xc
+#define   PCI_ISIZE_128M                0x8
+#define   PCI_ISIZE_256M                0x0
+#define PCI_PIBAR                       0xaa    /* 8  bits */
+#define PCI_CPU_COUNTER_LIMIT_HI        0xac    /* 32 bits */
+#define PCI_CPU_COUNTER_LIMIT_LO        0xb0    /* 32 bits */
+#define PCI_CPU_COUNTER_LIMIT           0xb4    /* 32 bits */
+#define PCI_SYS_LIMIT                   0xb8    /* 32 bits */
+#define PCI_SYS_COUNTER                 0xbc    /* 32 bits */
+#define   PCI_SYS_COUNTER_OVERFLOW      (1<<31) /* Limit reached */
+#define PCI_SYS_LIMIT_PSEUDO            0xc0    /* 32 bits */
+#define PCI_USER_TIMER_CONTROL          0xc4    /* 8  bits */
+#define PCI_USER_TIMER_CONFIG           0xc5    /* 8  bits */
+#define PCI_COUNTER_IRQ                 0xc6    /* 8  bits */
+#define  PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq)  ((((sys_irq) & 0xf) << 4) | \
+                                                  ((cpu_irq) & 0xf))
+#define  PCI_COUNTER_IRQ_SYS(v)                 (((v) >> 4) & 0xf)
+#define  PCI_COUNTER_IRQ_CPU(v)                 ((v) & 0xf)
+#define PCI_PIO_ERROR_COMMAND           0xc7    /* 8  bits */
+#define PCI_PIO_ERROR_ADDRESS           0xc8    /* 32 bits */
+#define PCI_IOTLB_ERROR_ADDRESS         0xcc    /* 32 bits */
+#define PCI_SYS_STATUS                  0xd0    /* 8  bits */
+#define   PCI_SYS_STATUS_RESET_ENABLE           (1<<0)
+#define   PCI_SYS_STATUS_RESET                  (1<<1)
+#define   PCI_SYS_STATUS_WATCHDOG_RESET         (1<<4)
+#define   PCI_SYS_STATUS_PCI_RESET              (1<<5)
+#define   PCI_SYS_STATUS_PCI_RESET_ENABLE       (1<<6)
+#define   PCI_SYS_STATUS_PCI_SATTELITE_MODE     (1<<7)
+
+#endif /* !(__SPARC_PCIC_H) */
diff --git a/arch/sparc/include/asm/percpu.h b/arch/sparc/include/asm/percpu.h
new file mode 100644
index 000000000000..bfb1d19ff1bf
--- /dev/null
+++ b/arch/sparc/include/asm/percpu.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_PERCPU_H
+#define ___ASM_SPARC_PERCPU_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/percpu_64.h>
+#else
+#include <asm/percpu_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/percpu_32.h b/arch/sparc/include/asm/percpu_32.h
new file mode 100644
index 000000000000..06066a7aaec3
--- /dev/null
+++ b/arch/sparc/include/asm/percpu_32.h
@@ -0,0 +1,6 @@
+#ifndef __ARCH_SPARC_PERCPU__
+#define __ARCH_SPARC_PERCPU__
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_SPARC_PERCPU__ */
diff --git a/arch/sparc/include/asm/percpu_64.h b/arch/sparc/include/asm/percpu_64.h
new file mode 100644
index 000000000000..bee64593023e
--- /dev/null
+++ b/arch/sparc/include/asm/percpu_64.h
@@ -0,0 +1,28 @@
+#ifndef __ARCH_SPARC64_PERCPU__
+#define __ARCH_SPARC64_PERCPU__
+
+#include <linux/compiler.h>
+
+register unsigned long __local_per_cpu_offset asm("g5");
+
+#ifdef CONFIG_SMP
+
+extern void real_setup_per_cpu_areas(void);
+
+extern unsigned long __per_cpu_base;
+extern unsigned long __per_cpu_shift;
+#define __per_cpu_offset(__cpu) \
+        (__per_cpu_base + ((unsigned long)(__cpu) << __per_cpu_shift))
+#define per_cpu_offset(x) (__per_cpu_offset(x))
+
+#define __my_cpu_offset __local_per_cpu_offset
+
+#else /* ! SMP */
+
+#define real_setup_per_cpu_areas()              do { } while (0)
+
+#endif  /* SMP */
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_SPARC64_PERCPU__ */
diff --git a/arch/sparc/include/asm/perfctr.h b/arch/sparc/include/asm/perfctr.h
new file mode 100644
index 000000000000..836873002b75
--- /dev/null
+++ b/arch/sparc/include/asm/perfctr.h
@@ -0,0 +1,173 @@
+/*----------------------------------------
+  PERFORMANCE INSTRUMENTATION  
+  Guillaume Thouvenin           08/10/98
+  David S. Miller               10/06/98
+  ---------------------------------------*/
+#ifndef PERF_COUNTER_API
+#define PERF_COUNTER_API
+
+/* sys_perfctr() interface.  First arg is operation code
+ * from enumeration below.  The meaning of further arguments
+ * are determined by the operation code.
+ *
+ * int sys_perfctr(int opcode, unsigned long arg0,
+ *                 unsigned long arg1, unsigned long arg2)
+ *
+ * Pointers which are passed by the user are pointers to 64-bit
+ * integers.
+ *
+ * Once enabled, performance counter state is retained until the
+ * process either exits or performs an exec.  That is, performance
+ * counters remain enabled for fork/clone children.
+ */
+enum perfctr_opcode {
+        /* Enable UltraSparc performance counters, ARG0 is pointer
+         * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
+         * to 64-bit accumulator for D1 counter.  ARG2 is a pointer to
+         * the initial PCR register value to use.
+         */
+        PERFCTR_ON,
+
+        /* Disable UltraSparc performance counters.  The PCR is written
+         * with zero and the user counter accumulator pointers and
+         * working PCR register value are forgotten.
+         */
+        PERFCTR_OFF,
+
+        /* Add current D0 and D1 PIC values into user pointers given
+         * in PERFCTR_ON operation.  The PIC is cleared before returning.
+         */
+        PERFCTR_READ,
+
+        /* Clear the PIC register. */
+        PERFCTR_CLRPIC,
+
+        /* Begin using a new PCR value, the pointer to which is passed
+         * in ARG0.  The PIC is also cleared after the new PCR value is
+         * written.
+         */
+        PERFCTR_SETPCR,
+
+        /* Store in pointer given in ARG0 the current PCR register value
+         * being used.
+         */
+        PERFCTR_GETPCR
+};
+
+/* I don't want the kernel's namespace to be polluted with this
+ * stuff when this file is included.  --DaveM
+ */
+#ifndef __KERNEL__
+
+#define  PRIV 0x00000001
+#define  SYS  0x00000002
+#define  USR  0x00000004
+
+/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II  */
+#define  CYCLE_CNT            0x00000000
+#define  INSTR_CNT            0x00000010
+#define  DISPATCH0_IC_MISS    0x00000020
+#define  DISPATCH0_STOREBUF   0x00000030
+#define  IC_REF               0x00000080
+#define  DC_RD                0x00000090
+#define  DC_WR                0x000000A0
+#define  LOAD_USE             0x000000B0
+#define  EC_REF               0x000000C0
+#define  EC_WRITE_HIT_RDO     0x000000D0
+#define  EC_SNOOP_INV         0x000000E0
+#define  EC_RD_HIT            0x000000F0
+
+/* Pic.S0 Selection Bit Field Encoding, Ultra-III  */
+#define  US3_CYCLE_CNT          0x00000000
+#define  US3_INSTR_CNT          0x00000010
+#define  US3_DISPATCH0_IC_MISS  0x00000020
+#define  US3_DISPATCH0_BR_TGT   0x00000030
+#define  US3_DISPATCH0_2ND_BR   0x00000040
+#define  US3_RSTALL_STOREQ      0x00000050
+#define  US3_RSTALL_IU_USE      0x00000060
+#define  US3_IC_REF             0x00000080
+#define  US3_DC_RD              0x00000090
+#define  US3_DC_WR              0x000000a0
+#define  US3_EC_REF             0x000000c0
+#define  US3_EC_WR_HIT_RTO      0x000000d0
+#define  US3_EC_SNOOP_INV       0x000000e0
+#define  US3_EC_RD_MISS         0x000000f0
+#define  US3_PC_PORT0_RD        0x00000100
+#define  US3_SI_SNOOP           0x00000110
+#define  US3_SI_CIQ_FLOW        0x00000120
+#define  US3_SI_OWNED           0x00000130
+#define  US3_SW_COUNT_0         0x00000140
+#define  US3_IU_BR_MISS_TAKEN   0x00000150
+#define  US3_IU_BR_COUNT_TAKEN  0x00000160
+#define  US3_DISP_RS_MISPRED    0x00000170
+#define  US3_FA_PIPE_COMPL      0x00000180
+#define  US3_MC_READS_0         0x00000200
+#define  US3_MC_READS_1         0x00000210
+#define  US3_MC_READS_2         0x00000220
+#define  US3_MC_READS_3         0x00000230
+#define  US3_MC_STALLS_0        0x00000240
+#define  US3_MC_STALLS_2        0x00000250
+
+/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II  */
+#define  CYCLE_CNT_D1         0x00000000
+#define  INSTR_CNT_D1         0x00000800
+#define  DISPATCH0_IC_MISPRED 0x00001000
+#define  DISPATCH0_FP_USE     0x00001800
+#define  IC_HIT               0x00004000
+#define  DC_RD_HIT            0x00004800
+#define  DC_WR_HIT            0x00005000
+#define  LOAD_USE_RAW         0x00005800
+#define  EC_HIT               0x00006000
+#define  EC_WB                0x00006800
+#define  EC_SNOOP_CB          0x00007000
+#define  EC_IT_HIT            0x00007800
+
+/* Pic.S1 Selection Bit Field Encoding, Ultra-III  */
+#define  US3_CYCLE_CNT_D1       0x00000000
+#define  US3_INSTR_CNT_D1       0x00000800
+#define  US3_DISPATCH0_MISPRED  0x00001000
+#define  US3_IC_MISS_CANCELLED  0x00001800
+#define  US3_RE_ENDIAN_MISS     0x00002000
+#define  US3_RE_FPU_BYPASS      0x00002800
+#define  US3_RE_DC_MISS         0x00003000
+#define  US3_RE_EC_MISS         0x00003800
+#define  US3_IC_MISS            0x00004000
+#define  US3_DC_RD_MISS         0x00004800
+#define  US3_DC_WR_MISS         0x00005000
+#define  US3_RSTALL_FP_USE      0x00005800
+#define  US3_EC_MISSES          0x00006000
+#define  US3_EC_WB              0x00006800
+#define  US3_EC_SNOOP_CB        0x00007000
+#define  US3_EC_IC_MISS         0x00007800
+#define  US3_RE_PC_MISS         0x00008000
+#define  US3_ITLB_MISS          0x00008800
+#define  US3_DTLB_MISS          0x00009000
+#define  US3_WC_MISS            0x00009800
+#define  US3_WC_SNOOP_CB        0x0000a000
+#define  US3_WC_SCRUBBED        0x0000a800
+#define  US3_WC_WB_WO_READ      0x0000b000
+#define  US3_PC_SOFT_HIT        0x0000c000
+#define  US3_PC_SNOOP_INV       0x0000c800
+#define  US3_PC_HARD_HIT        0x0000d000
+#define  US3_PC_PORT1_RD        0x0000d800
+#define  US3_SW_COUNT_1         0x0000e000
+#define  US3_IU_STAT_BR_MIS_UNTAKEN     0x0000e800
+#define  US3_IU_STAT_BR_COUNT_UNTAKEN   0x0000f000
+#define  US3_PC_MS_MISSES       0x0000f800
+#define  US3_MC_WRITES_0        0x00010800
+#define  US3_MC_WRITES_1        0x00011000
+#define  US3_MC_WRITES_2        0x00011800
+#define  US3_MC_WRITES_3        0x00012000
+#define  US3_MC_STALLS_1        0x00012800
+#define  US3_MC_STALLS_3        0x00013000
+#define  US3_RE_RAW_MISS        0x00013800
+#define  US3_FM_PIPE_COMPLETION 0x00014000
+
+struct vcounter_struct {
+  unsigned long long vcnt0;
+  unsigned long long vcnt1;
+};
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(PERF_COUNTER_API) */
diff --git a/arch/sparc/include/asm/pgalloc.h b/arch/sparc/include/asm/pgalloc.h
new file mode 100644
index 000000000000..b6db1f7cdcab
--- /dev/null
+++ b/arch/sparc/include/asm/pgalloc.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_PGALLOC_H
+#define ___ASM_SPARC_PGALLOC_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/pgalloc_64.h>
+#else
+#include <asm/pgalloc_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/pgalloc_32.h b/arch/sparc/include/asm/pgalloc_32.h
new file mode 100644
index 000000000000..681582d26969
--- /dev/null
+++ b/arch/sparc/include/asm/pgalloc_32.h
@@ -0,0 +1,68 @@
+#ifndef _SPARC_PGALLOC_H
+#define _SPARC_PGALLOC_H
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+#include <asm/page.h>
+#include <asm/btfixup.h>
+
+struct page;
+
+extern struct pgtable_cache_struct {
+        unsigned long *pgd_cache;
+        unsigned long *pte_cache;
+        unsigned long pgtable_cache_sz;
+        unsigned long pgd_cache_sz;
+} pgt_quicklists;
+#define pgd_quicklist           (pgt_quicklists.pgd_cache)
+#define pmd_quicklist           ((unsigned long *)0)
+#define pte_quicklist           (pgt_quicklists.pte_cache)
+#define pgtable_cache_size      (pgt_quicklists.pgtable_cache_sz)
+#define pgd_cache_size          (pgt_quicklists.pgd_cache_sz)
+
+extern void check_pgt_cache(void);
+BTFIXUPDEF_CALL(void,    do_check_pgt_cache, int, int)
+#define do_check_pgt_cache(low,high) BTFIXUP_CALL(do_check_pgt_cache)(low,high)
+
+BTFIXUPDEF_CALL(pgd_t *, get_pgd_fast, void)
+#define get_pgd_fast()          BTFIXUP_CALL(get_pgd_fast)()
+
+BTFIXUPDEF_CALL(void, free_pgd_fast, pgd_t *)
+#define free_pgd_fast(pgd)      BTFIXUP_CALL(free_pgd_fast)(pgd)
+
+#define pgd_free(mm, pgd)       free_pgd_fast(pgd)
+#define pgd_alloc(mm)   get_pgd_fast()
+
+BTFIXUPDEF_CALL(void, pgd_set, pgd_t *, pmd_t *)
+#define pgd_set(pgdp,pmdp) BTFIXUP_CALL(pgd_set)(pgdp,pmdp)
+#define pgd_populate(MM, PGD, PMD)      pgd_set(PGD, PMD)
+
+BTFIXUPDEF_CALL(pmd_t *, pmd_alloc_one, struct mm_struct *, unsigned long)
+#define pmd_alloc_one(mm, address)      BTFIXUP_CALL(pmd_alloc_one)(mm, address)
+
+BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *)
+#define free_pmd_fast(pmd)      BTFIXUP_CALL(free_pmd_fast)(pmd)
+
+#define pmd_free(mm, pmd)       free_pmd_fast(pmd)
+#define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd)
+
+BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *)
+#define pmd_populate(MM, PMD, PTE)        BTFIXUP_CALL(pmd_populate)(PMD, PTE)
+#define pmd_pgtable(pmd) pmd_page(pmd)
+BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *)
+#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE)
+
+BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long)
+#define pte_alloc_one(mm, address)      BTFIXUP_CALL(pte_alloc_one)(mm, address)
+BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long)
+#define pte_alloc_one_kernel(mm, addr)  BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr)
+
+BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *)
+#define pte_free_kernel(mm, pte)        BTFIXUP_CALL(free_pte_fast)(pte)
+
+BTFIXUPDEF_CALL(void, pte_free, pgtable_t )
+#define pte_free(mm, pte)       BTFIXUP_CALL(pte_free)(pte)
+#define __pte_free_tlb(tlb, pte)        pte_free((tlb)->mm, pte)
+
+#endif /* _SPARC_PGALLOC_H */
diff --git a/arch/sparc/include/asm/pgalloc_64.h b/arch/sparc/include/asm/pgalloc_64.h
new file mode 100644
index 000000000000..5bdfa2c6e400
--- /dev/null
+++ b/arch/sparc/include/asm/pgalloc_64.h
@@ -0,0 +1,81 @@
+#ifndef _SPARC64_PGALLOC_H
+#define _SPARC64_PGALLOC_H
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/quicklist.h>
+
+#include <asm/spitfire.h>
+#include <asm/cpudata.h>
+#include <asm/cacheflush.h>
+#include <asm/page.h>
+
+/* Page table allocation/freeing. */
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        quicklist_free(0, NULL, pgd);
+}
+
+#define pud_populate(MM, PUD, PMD)      pud_set(PUD, PMD)
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+        quicklist_free(0, NULL, pmd);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long address)
+{
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+                                        unsigned long address)
+{
+        struct page *page;
+        void *pg;
+
+        pg = quicklist_alloc(0, GFP_KERNEL, NULL);
+        if (!pg)
+                return NULL;
+        page = virt_to_page(pg);
+        pgtable_page_ctor(page);
+        return page;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        quicklist_free(0, NULL, pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+        pgtable_page_dtor(ptepage);
+        quicklist_free_page(0, NULL, ptepage);
+}
+
+
+#define pmd_populate_kernel(MM, PMD, PTE)       pmd_set(PMD, PTE)
+#define pmd_populate(MM,PMD,PTE_PAGE)           \
+        pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+static inline void check_pgt_cache(void)
+{
+        quicklist_trim(0, NULL, 25, 16);
+}
+
+#endif /* _SPARC64_PGALLOC_H */
diff --git a/arch/sparc/include/asm/pgtable.h b/arch/sparc/include/asm/pgtable.h
new file mode 100644
index 000000000000..59ba6f620732
--- /dev/null
+++ b/arch/sparc/include/asm/pgtable.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_PGTABLE_H
+#define ___ASM_SPARC_PGTABLE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/pgtable_64.h>
+#else
+#include <asm/pgtable_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
new file mode 100644
index 000000000000..08237fda8874
--- /dev/null
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -0,0 +1,480 @@
+#ifndef _SPARC_PGTABLE_H
+#define _SPARC_PGTABLE_H
+
+/*  asm/pgtable.h:  Defines and functions used to work
+ *                        with Sparc page tables.
+ *
+ *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ *  Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __ASSEMBLY__
+#include <asm-generic/4level-fixup.h>
+
+#include <linux/spinlock.h>
+#include <linux/swap.h>
+#include <asm/types.h>
+#ifdef CONFIG_SUN4
+#include <asm/pgtsun4.h>
+#else
+#include <asm/pgtsun4c.h>
+#endif
+#include <asm/pgtsrmmu.h>
+#include <asm/vac-ops.h>
+#include <asm/oplib.h>
+#include <asm/btfixup.h>
+#include <asm/system.h>
+
+
+struct vm_area_struct;
+struct page;
+
+extern void load_mmu(void);
+extern unsigned long calc_highpages(void);
+
+BTFIXUPDEF_SIMM13(pgdir_shift)
+BTFIXUPDEF_SETHI(pgdir_size)
+BTFIXUPDEF_SETHI(pgdir_mask)
+
+BTFIXUPDEF_SIMM13(ptrs_per_pmd)
+BTFIXUPDEF_SIMM13(ptrs_per_pgd)
+BTFIXUPDEF_SIMM13(user_ptrs_per_pgd)
+
+#define pte_ERROR(e)   __builtin_trap()
+#define pmd_ERROR(e)   __builtin_trap()
+#define pgd_ERROR(e)   __builtin_trap()
+
+BTFIXUPDEF_INT(page_none)
+BTFIXUPDEF_INT(page_copy)
+BTFIXUPDEF_INT(page_readonly)
+BTFIXUPDEF_INT(page_kernel)
+
+#define PMD_SHIFT               SUN4C_PMD_SHIFT
+#define PMD_SIZE                (1UL << PMD_SHIFT)
+#define PMD_MASK                (~(PMD_SIZE-1))
+#define PMD_ALIGN(__addr)       (((__addr) + ~PMD_MASK) & PMD_MASK)
+#define PGDIR_SHIFT             BTFIXUP_SIMM13(pgdir_shift)
+#define PGDIR_SIZE              BTFIXUP_SETHI(pgdir_size)
+#define PGDIR_MASK              BTFIXUP_SETHI(pgdir_mask)
+#define PTRS_PER_PTE            1024
+#define PTRS_PER_PMD            BTFIXUP_SIMM13(ptrs_per_pmd)
+#define PTRS_PER_PGD            BTFIXUP_SIMM13(ptrs_per_pgd)
+#define USER_PTRS_PER_PGD       BTFIXUP_SIMM13(user_ptrs_per_pgd)
+#define FIRST_USER_ADDRESS      0
+#define PTE_SIZE                (PTRS_PER_PTE*4)
+
+#define PAGE_NONE      __pgprot(BTFIXUP_INT(page_none))
+extern pgprot_t PAGE_SHARED;
+#define PAGE_COPY      __pgprot(BTFIXUP_INT(page_copy))
+#define PAGE_READONLY  __pgprot(BTFIXUP_INT(page_readonly))
+
+extern unsigned long page_kernel;
+
+#ifdef MODULE
+#define PAGE_KERNEL     page_kernel
+#else
+#define PAGE_KERNEL    __pgprot(BTFIXUP_INT(page_kernel))
+#endif
+
+/* Top-level page directory */
+extern pgd_t swapper_pg_dir[1024];
+
+extern void paging_init(void);
+
+/* Page table for 0-4MB for everybody, on the Sparc this
+ * holds the same as on the i386.
+ */
+extern pte_t pg0[1024];
+extern pte_t pg1[1024];
+extern pte_t pg2[1024];
+extern pte_t pg3[1024];
+
+extern unsigned long ptr_in_current_pgd;
+
+/* Here is a trick, since mmap.c need the initializer elements for
+ * protection_map[] to be constant at compile time, I set the following
+ * to all zeros.  I set it to the real values after I link in the
+ * appropriate MMU page table routines at boot time.
+ */
+#define __P000  __pgprot(0)
+#define __P001  __pgprot(0)
+#define __P010  __pgprot(0)
+#define __P011  __pgprot(0)
+#define __P100  __pgprot(0)
+#define __P101  __pgprot(0)
+#define __P110  __pgprot(0)
+#define __P111  __pgprot(0)
+
+#define __S000  __pgprot(0)
+#define __S001  __pgprot(0)
+#define __S010  __pgprot(0)
+#define __S011  __pgprot(0)
+#define __S100  __pgprot(0)
+#define __S101  __pgprot(0)
+#define __S110  __pgprot(0)
+#define __S111  __pgprot(0)
+
+extern int num_contexts;
+
+/* First physical page can be anywhere, the following is needed so that
+ * va-->pa and vice versa conversions work properly without performance
+ * hit for all __pa()/__va() operations.
+ */
+extern unsigned long phys_base;
+extern unsigned long pfn_base;
+
+/*
+ * BAD_PAGETABLE is used when we need a bogus page-table, while
+ * BAD_PAGE is used for a bogus page.
+ *
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern pte_t * __bad_pagetable(void);
+extern pte_t __bad_page(void);
+extern unsigned long empty_zero_page;
+
+#define BAD_PAGETABLE __bad_pagetable()
+#define BAD_PAGE __bad_page()
+#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
+
+/*
+ */
+BTFIXUPDEF_CALL_CONST(struct page *, pmd_page, pmd_t)
+BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
+
+#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
+#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
+
+BTFIXUPDEF_SETHI(none_mask)
+BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
+BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
+
+static inline int pte_none(pte_t pte)
+{
+        return !(pte_val(pte) & ~BTFIXUP_SETHI(none_mask));
+}
+
+#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
+#define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte)
+
+BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t)
+BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t)
+BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
+
+static inline int pmd_none(pmd_t pmd)
+{
+        return !(pmd_val(pmd) & ~BTFIXUP_SETHI(none_mask));
+}
+
+#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)
+#define pmd_present(pmd) BTFIXUP_CALL(pmd_present)(pmd)
+#define pmd_clear(pmd) BTFIXUP_CALL(pmd_clear)(pmd)
+
+BTFIXUPDEF_CALL_CONST(int, pgd_none, pgd_t)
+BTFIXUPDEF_CALL_CONST(int, pgd_bad, pgd_t)
+BTFIXUPDEF_CALL_CONST(int, pgd_present, pgd_t)
+BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *)
+
+#define pgd_none(pgd) BTFIXUP_CALL(pgd_none)(pgd)
+#define pgd_bad(pgd) BTFIXUP_CALL(pgd_bad)(pgd)
+#define pgd_present(pgd) BTFIXUP_CALL(pgd_present)(pgd)
+#define pgd_clear(pgd) BTFIXUP_CALL(pgd_clear)(pgd)
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+BTFIXUPDEF_HALF(pte_writei)
+BTFIXUPDEF_HALF(pte_dirtyi)
+BTFIXUPDEF_HALF(pte_youngi)
+
+static int pte_write(pte_t pte) __attribute_const__;
+static inline int pte_write(pte_t pte)
+{
+        return pte_val(pte) & BTFIXUP_HALF(pte_writei);
+}
+
+static int pte_dirty(pte_t pte) __attribute_const__;
+static inline int pte_dirty(pte_t pte)
+{
+        return pte_val(pte) & BTFIXUP_HALF(pte_dirtyi);
+}
+
+static int pte_young(pte_t pte) __attribute_const__;
+static inline int pte_young(pte_t pte)
+{
+        return pte_val(pte) & BTFIXUP_HALF(pte_youngi);
+}
+
+/*
+ * The following only work if pte_present() is not true.
+ */
+BTFIXUPDEF_HALF(pte_filei)
+
+static int pte_file(pte_t pte) __attribute_const__;
+static inline int pte_file(pte_t pte)
+{
+        return pte_val(pte) & BTFIXUP_HALF(pte_filei);
+}
+
+static inline int pte_special(pte_t pte)
+{
+        return 0;
+}
+
+/*
+ */
+BTFIXUPDEF_HALF(pte_wrprotecti)
+BTFIXUPDEF_HALF(pte_mkcleani)
+BTFIXUPDEF_HALF(pte_mkoldi)
+
+static pte_t pte_wrprotect(pte_t pte) __attribute_const__;
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_wrprotecti));
+}
+
+static pte_t pte_mkclean(pte_t pte) __attribute_const__;
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkcleani));
+}
+
+static pte_t pte_mkold(pte_t pte) __attribute_const__;
+static inline pte_t pte_mkold(pte_t pte)
+{
+        return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkoldi));
+}
+
+BTFIXUPDEF_CALL_CONST(pte_t, pte_mkwrite, pte_t)
+BTFIXUPDEF_CALL_CONST(pte_t, pte_mkdirty, pte_t)
+BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
+
+#define pte_mkwrite(pte) BTFIXUP_CALL(pte_mkwrite)(pte)
+#define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
+#define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
+
+#define pte_mkspecial(pte)    (pte)
+
+#define pfn_pte(pfn, prot)              mk_pte(pfn_to_page(pfn), prot)
+
+BTFIXUPDEF_CALL(unsigned long,   pte_pfn, pte_t)
+#define pte_pfn(pte) BTFIXUP_CALL(pte_pfn)(pte)
+#define pte_page(pte)   pfn_to_page(pte_pfn(pte))
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+BTFIXUPDEF_CALL_CONST(pte_t, mk_pte, struct page *, pgprot_t)
+
+BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_phys, unsigned long, pgprot_t)
+BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_io, unsigned long, pgprot_t, int)
+BTFIXUPDEF_CALL_CONST(pgprot_t, pgprot_noncached, pgprot_t)
+
+#define mk_pte(page,pgprot) BTFIXUP_CALL(mk_pte)(page,pgprot)
+#define mk_pte_phys(page,pgprot) BTFIXUP_CALL(mk_pte_phys)(page,pgprot)
+#define mk_pte_io(page,pgprot,space) BTFIXUP_CALL(mk_pte_io)(page,pgprot,space)
+
+#define pgprot_noncached(pgprot) BTFIXUP_CALL(pgprot_noncached)(pgprot)
+
+BTFIXUPDEF_INT(pte_modify_mask)
+
+static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) |
+                pgprot_val(newprot));
+}
+
+#define pgd_index(address) ((address) >> PGDIR_SHIFT)
+
+/* to find an entry in a page-table-directory */
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* Find an entry in the second-level page table.. */
+BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long)
+#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)
+
+/* Find an entry in the third-level page table.. */
+BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long)
+#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)
+
+/*
+ * This shortcut works on sun4m (and sun4d) because the nocache area is static,
+ * and sun4c is guaranteed to have no highmem anyway.
+ */
+#define pte_offset_map(d, a)            pte_offset_kernel(d,a)
+#define pte_offset_map_nested(d, a)     pte_offset_kernel(d,a)
+
+#define pte_unmap(pte)          do{}while(0)
+#define pte_unmap_nested(pte)   do{}while(0)
+
+/* Certain architectures need to do special things when pte's
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+
+BTFIXUPDEF_CALL(void, set_pte, pte_t *, pte_t)
+
+#define set_pte(ptep,pteval) BTFIXUP_CALL(set_pte)(ptep,pteval)
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+struct seq_file;
+BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
+
+#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)
+
+/* Fault handler stuff... */
+#define FAULT_CODE_PROT     0x1
+#define FAULT_CODE_WRITE    0x2
+#define FAULT_CODE_USER     0x4
+
+BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t)
+
+#define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte)
+
+BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
+    unsigned long, unsigned int)
+BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
+#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
+#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)
+
+extern int invalid_segment;
+
+/* Encode and de-code a swap entry */
+BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
+BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
+BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)
+
+#define __swp_type(__x)                 BTFIXUP_CALL(__swp_type)(__x)
+#define __swp_offset(__x)               BTFIXUP_CALL(__swp_offset)(__x)
+#define __swp_entry(__type,__off)       BTFIXUP_CALL(__swp_entry)(__type,__off)
+
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
+
+/* file-offset-in-pte helpers */
+BTFIXUPDEF_CALL(unsigned long, pte_to_pgoff, pte_t pte);
+BTFIXUPDEF_CALL(pte_t, pgoff_to_pte, unsigned long pgoff);
+
+#define pte_to_pgoff(pte) BTFIXUP_CALL(pte_to_pgoff)(pte)
+#define pgoff_to_pte(off) BTFIXUP_CALL(pgoff_to_pte)(off)
+
+/*
+ * This is made a constant because mm/fremap.c required a constant.
+ * Note that layout of these bits is different between sun4c.c and srmmu.c.
+ */
+#define PTE_FILE_MAX_BITS 24
+
+/*
+ */
+struct ctx_list {
+        struct ctx_list *next;
+        struct ctx_list *prev;
+        unsigned int ctx_number;
+        struct mm_struct *ctx_mm;
+};
+
+extern struct ctx_list *ctx_list_pool;  /* Dynamically allocated */
+extern struct ctx_list ctx_free;        /* Head of free list */
+extern struct ctx_list ctx_used;        /* Head of used contexts list */
+
+#define NO_CONTEXT     -1
+
+static inline void remove_from_ctx_list(struct ctx_list *entry)
+{
+        entry->next->prev = entry->prev;
+        entry->prev->next = entry->next;
+}
+
+static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
+{
+        entry->next = head;
+        (entry->prev = head->prev)->next = entry;
+        head->prev = entry;
+}
+#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
+#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
+
+static inline unsigned long
+__get_phys (unsigned long addr)
+{
+        switch (sparc_cpu_model){
+        case sun4:
+        case sun4c:
+                return sun4c_get_pte (addr) << PAGE_SHIFT;
+        case sun4m:
+        case sun4d:
+                return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
+        default:
+                return 0;
+        }
+}
+
+static inline int
+__get_iospace (unsigned long addr)
+{
+        switch (sparc_cpu_model){
+        case sun4:
+        case sun4c:
+                return -1; /* Don't check iospace on sun4c */
+        case sun4m:
+        case sun4d:
+                return (srmmu_get_pte (addr) >> 28);
+        default:
+                return -1;
+        }
+}
+
+extern unsigned long *sparc_valid_addr_bitmap;
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr) \
+        (test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
+
+extern int io_remap_pfn_range(struct vm_area_struct *vma,
+                              unsigned long from, unsigned long pfn,
+                              unsigned long size, pgprot_t prot);
+
+/*
+ * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
+ * its high 4 bits.  These macros/functions put it there or get it from there.
+ */
+#define MK_IOSPACE_PFN(space, pfn)      (pfn | (space << (BITS_PER_LONG - 4)))
+#define GET_IOSPACE(pfn)                (pfn >> (BITS_PER_LONG - 4))
+#define GET_PFN(pfn)                    (pfn & 0x0fffffffUL)
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+({                                                                        \
+        int __changed = !pte_same(*(__ptep), __entry);                    \
+        if (__changed) {                                                  \
+                set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
+                flush_tlb_page(__vma, __address);                         \
+        }                                                                 \
+        (sparc_cpu_model == sun4c) || __changed;                          \
+})
+
+#include <asm-generic/pgtable.h>
+
+#endif /* !(__ASSEMBLY__) */
+
+#define VMALLOC_START           0xfe600000
+/* XXX Alter this when I get around to fixing sun4c - Anton */
+#define VMALLOC_END             0xffc00000
+
+
+/* We provide our own get_unmapped_area to cope with VA holes for userland */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+#endif /* !(_SPARC_PGTABLE_H) */
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
new file mode 100644
index 000000000000..bb9ec2cce355
--- /dev/null
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -0,0 +1,775 @@
+/*
+ * pgtable.h: SpitFire page table operations.
+ *
+ * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef _SPARC64_PGTABLE_H
+#define _SPARC64_PGTABLE_H
+
+/* This file contains the functions and defines necessary to modify and use
+ * the SpitFire page tables.
+ */
+
+#include <asm-generic/pgtable-nopud.h>
+
+#include <linux/compiler.h>
+#include <linux/const.h>
+#include <asm/types.h>
+#include <asm/spitfire.h>
+#include <asm/asi.h>
+#include <asm/system.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+
+/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
+ * The page copy blockops can use 0x6000000 to 0x8000000.
+ * The TSB is mapped in the 0x8000000 to 0xa000000 range.
+ * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
+ * The vmalloc area spans 0x100000000 to 0x200000000.
+ * Since modules need to be in the lowest 32-bits of the address space,
+ * we place them right before the OBP area from 0x10000000 to 0xf0000000.
+ * There is a single static kernel PMD which maps from 0x0 to address
+ * 0x400000000.
+ */
+#define TLBTEMP_BASE            _AC(0x0000000006000000,UL)
+#define TSBMAP_BASE             _AC(0x0000000008000000,UL)
+#define MODULES_VADDR           _AC(0x0000000010000000,UL)
+#define MODULES_LEN             _AC(0x00000000e0000000,UL)
+#define MODULES_END             _AC(0x00000000f0000000,UL)
+#define LOW_OBP_ADDRESS         _AC(0x00000000f0000000,UL)
+#define HI_OBP_ADDRESS          _AC(0x0000000100000000,UL)
+#define VMALLOC_START           _AC(0x0000000100000000,UL)
+#define VMALLOC_END             _AC(0x0000000200000000,UL)
+#define VMEMMAP_BASE            _AC(0x0000000200000000,UL)
+
+#define vmemmap                 ((struct page *)VMEMMAP_BASE)
+
+/* XXX All of this needs to be rethought so we can take advantage
+ * XXX cheetah's full 64-bit virtual address space, ie. no more hole
+ * XXX in the middle like on spitfire. -DaveM
+ */
+/*
+ * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
+ * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
+ * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
+ * table is a single page long). The next higher PMD_BITS determine pmd#
+ * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
+ * since the pmd entries are 4 bytes, and each pmd page is a single page
+ * long). Finally, the higher few bits determine pgde#.
+ */
+
+/* PMD_SHIFT determines the size of the area a second-level page
+ * table can map
+ */
+#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT-3))
+#define PMD_SIZE        (_AC(1,UL) << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+#define PMD_BITS        (PAGE_SHIFT - 2)
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
+#define PGDIR_SIZE      (_AC(1,UL) << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+#define PGDIR_BITS      (PAGE_SHIFT - 2)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sched.h>
+
+/* Entries per page directory level. */
+#define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-3))
+#define PTRS_PER_PMD    (1UL << PMD_BITS)
+#define PTRS_PER_PGD    (1UL << PGDIR_BITS)
+
+/* Kernel has a separate 44bit address space. */
+#define FIRST_USER_ADDRESS      0
+
+#define pte_ERROR(e)    __builtin_trap()
+#define pmd_ERROR(e)    __builtin_trap()
+#define pgd_ERROR(e)    __builtin_trap()
+
+#endif /* !(__ASSEMBLY__) */
+
+/* PTE bits which are the same in SUN4U and SUN4V format.  */
+#define _PAGE_VALID       _AC(0x8000000000000000,UL) /* Valid TTE            */
+#define _PAGE_R           _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
+
+/* SUN4U pte bits... */
+#define _PAGE_SZ4MB_4U    _AC(0x6000000000000000,UL) /* 4MB Page             */
+#define _PAGE_SZ512K_4U   _AC(0x4000000000000000,UL) /* 512K Page            */
+#define _PAGE_SZ64K_4U    _AC(0x2000000000000000,UL) /* 64K Page             */
+#define _PAGE_SZ8K_4U     _AC(0x0000000000000000,UL) /* 8K Page              */
+#define _PAGE_NFO_4U      _AC(0x1000000000000000,UL) /* No Fault Only        */
+#define _PAGE_IE_4U       _AC(0x0800000000000000,UL) /* Invert Endianness    */
+#define _PAGE_SOFT2_4U    _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
+#define _PAGE_RES1_4U     _AC(0x0002000000000000,UL) /* Reserved             */
+#define _PAGE_SZ32MB_4U   _AC(0x0001000000000000,UL) /* (Panther) 32MB page  */
+#define _PAGE_SZ256MB_4U  _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
+#define _PAGE_SZALL_4U    _AC(0x6001000000000000,UL) /* All pgsz bits        */
+#define _PAGE_SN_4U       _AC(0x0000800000000000,UL) /* (Cheetah) Snoop      */
+#define _PAGE_RES2_4U     _AC(0x0000780000000000,UL) /* Reserved             */
+#define _PAGE_PADDR_4U    _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13]  */
+#define _PAGE_SOFT_4U     _AC(0x0000000000001F80,UL) /* Software bits:       */
+#define _PAGE_EXEC_4U     _AC(0x0000000000001000,UL) /* Executable SW bit    */
+#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty)     */
+#define _PAGE_FILE_4U     _AC(0x0000000000000800,UL) /* Pagecache page       */
+#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd)     */
+#define _PAGE_READ_4U     _AC(0x0000000000000200,UL) /* Readable SW Bit      */
+#define _PAGE_WRITE_4U    _AC(0x0000000000000100,UL) /* Writable SW Bit      */
+#define _PAGE_PRESENT_4U  _AC(0x0000000000000080,UL) /* Present              */
+#define _PAGE_L_4U        _AC(0x0000000000000040,UL) /* Locked TTE           */
+#define _PAGE_CP_4U       _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
+#define _PAGE_CV_4U       _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
+#define _PAGE_E_4U        _AC(0x0000000000000008,UL) /* side-Effect          */
+#define _PAGE_P_4U        _AC(0x0000000000000004,UL) /* Privileged Page      */
+#define _PAGE_W_4U        _AC(0x0000000000000002,UL) /* Writable             */
+
+/* SUN4V pte bits... */
+#define _PAGE_NFO_4V      _AC(0x4000000000000000,UL) /* No Fault Only        */
+#define _PAGE_SOFT2_4V    _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
+#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty)     */
+#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd)     */
+#define _PAGE_READ_4V     _AC(0x0800000000000000,UL) /* Readable SW Bit      */
+#define _PAGE_WRITE_4V    _AC(0x0400000000000000,UL) /* Writable SW Bit      */
+#define _PAGE_PADDR_4V    _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13]         */
+#define _PAGE_IE_4V       _AC(0x0000000000001000,UL) /* Invert Endianness    */
+#define _PAGE_E_4V        _AC(0x0000000000000800,UL) /* side-Effect          */
+#define _PAGE_CP_4V       _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
+#define _PAGE_CV_4V       _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
+#define _PAGE_P_4V        _AC(0x0000000000000100,UL) /* Privileged Page      */
+#define _PAGE_EXEC_4V     _AC(0x0000000000000080,UL) /* Executable Page      */
+#define _PAGE_W_4V        _AC(0x0000000000000040,UL) /* Writable             */
+#define _PAGE_SOFT_4V     _AC(0x0000000000000030,UL) /* Software bits        */
+#define _PAGE_FILE_4V     _AC(0x0000000000000020,UL) /* Pagecache page       */
+#define _PAGE_PRESENT_4V  _AC(0x0000000000000010,UL) /* Present              */
+#define _PAGE_RESV_4V     _AC(0x0000000000000008,UL) /* Reserved             */
+#define _PAGE_SZ16GB_4V   _AC(0x0000000000000007,UL) /* 16GB Page            */
+#define _PAGE_SZ2GB_4V    _AC(0x0000000000000006,UL) /* 2GB Page             */
+#define _PAGE_SZ256MB_4V  _AC(0x0000000000000005,UL) /* 256MB Page           */
+#define _PAGE_SZ32MB_4V   _AC(0x0000000000000004,UL) /* 32MB Page            */
+#define _PAGE_SZ4MB_4V    _AC(0x0000000000000003,UL) /* 4MB Page             */
+#define _PAGE_SZ512K_4V   _AC(0x0000000000000002,UL) /* 512K Page            */
+#define _PAGE_SZ64K_4V    _AC(0x0000000000000001,UL) /* 64K Page             */
+#define _PAGE_SZ8K_4V     _AC(0x0000000000000000,UL) /* 8K Page              */
+#define _PAGE_SZALL_4V    _AC(0x0000000000000007,UL) /* All pgsz bits        */
+
+#if PAGE_SHIFT == 13
+#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
+#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
+#elif PAGE_SHIFT == 16
+#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
+#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
+#else
+#error Wrong PAGE_SHIFT specified
+#endif
+
+#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
+#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
+#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
+#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
+#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
+#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
+#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
+#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
+#endif
+
+/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
+#define __P000  __pgprot(0)
+#define __P001  __pgprot(0)
+#define __P010  __pgprot(0)
+#define __P011  __pgprot(0)
+#define __P100  __pgprot(0)
+#define __P101  __pgprot(0)
+#define __P110  __pgprot(0)
+#define __P111  __pgprot(0)
+
+#define __S000  __pgprot(0)
+#define __S001  __pgprot(0)
+#define __S010  __pgprot(0)
+#define __S011  __pgprot(0)
+#define __S100  __pgprot(0)
+#define __S101  __pgprot(0)
+#define __S110  __pgprot(0)
+#define __S111  __pgprot(0)
+
+#ifndef __ASSEMBLY__
+
+extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
+
+extern unsigned long pte_sz_bits(unsigned long size);
+
+extern pgprot_t PAGE_KERNEL;
+extern pgprot_t PAGE_KERNEL_LOCKED;
+extern pgprot_t PAGE_COPY;
+extern pgprot_t PAGE_SHARED;
+
+/* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
+extern unsigned long _PAGE_IE;
+extern unsigned long _PAGE_E;
+extern unsigned long _PAGE_CACHE;
+
+extern unsigned long pg_iobits;
+extern unsigned long _PAGE_ALL_SZ_BITS;
+extern unsigned long _PAGE_SZBITS;
+
+extern struct page *mem_map_zero;
+#define ZERO_PAGE(vaddr)        (mem_map_zero)
+
+/* PFNs are real physical page numbers.  However, mem_map only begins to record
+ * per-page information starting at pfn_base.  This is to handle systems where
+ * the first physical page in the machine is at some huge physical address,
+ * such as 4GB.   This is common on a partitioned E10000, for example.
+ */
+static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
+{
+        unsigned long paddr = pfn << PAGE_SHIFT;
+        unsigned long sz_bits;
+
+        sz_bits = 0UL;
+        if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
+                __asm__ __volatile__(
+                "\n661: sethi           %%uhi(%1), %0\n"
+                "       sllx            %0, 32, %0\n"
+                "       .section        .sun4v_2insn_patch, \"ax\"\n"
+                "       .word           661b\n"
+                "       mov             %2, %0\n"
+                "       nop\n"
+                "       .previous\n"
+                : "=r" (sz_bits)
+                : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
+        }
+        return __pte(paddr | sz_bits | pgprot_val(prot));
+}
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+/* This one can be done with two shifts.  */
+static inline unsigned long pte_pfn(pte_t pte)
+{
+        unsigned long ret;
+
+        __asm__ __volatile__(
+        "\n661: sllx            %1, %2, %0\n"
+        "       srlx            %0, %3, %0\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sllx            %1, %4, %0\n"
+        "       srlx            %0, %5, %0\n"
+        "       .previous\n"
+        : "=r" (ret)
+        : "r" (pte_val(pte)),
+          "i" (21), "i" (21 + PAGE_SHIFT),
+          "i" (8), "i" (8 + PAGE_SHIFT));
+
+        return ret;
+}
+#define pte_page(x) pfn_to_page(pte_pfn(x))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
+{
+        unsigned long mask, tmp;
+
+        /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
+         * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
+         *
+         * Even if we use negation tricks the result is still a 6
+         * instruction sequence, so don't try to play fancy and just
+         * do the most straightforward implementation.
+         *
+         * Note: We encode this into 3 sun4v 2-insn patch sequences.
+         */
+
+        __asm__ __volatile__(
+        "\n661: sethi           %%uhi(%2), %1\n"
+        "       sethi           %%hi(%2), %0\n"
+        "\n662: or              %1, %%ulo(%2), %1\n"
+        "       or              %0, %%lo(%2), %0\n"
+        "\n663: sllx            %1, 32, %1\n"
+        "       or              %0, %1, %0\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%3), %1\n"
+        "       sethi           %%hi(%3), %0\n"
+        "       .word           662b\n"
+        "       or              %1, %%ulo(%3), %1\n"
+        "       or              %0, %%lo(%3), %0\n"
+        "       .word           663b\n"
+        "       sllx            %1, 32, %1\n"
+        "       or              %0, %1, %0\n"
+        "       .previous\n"
+        : "=r" (mask), "=r" (tmp)
+        : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
+               _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
+               _PAGE_SZBITS_4U),
+          "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
+               _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
+               _PAGE_SZBITS_4V));
+
+        return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
+}
+
+static inline pte_t pgoff_to_pte(unsigned long off)
+{
+        off <<= PAGE_SHIFT;
+
+        __asm__ __volatile__(
+        "\n661: or              %0, %2, %0\n"
+        "       .section        .sun4v_1insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       or              %0, %3, %0\n"
+        "       .previous\n"
+        : "=r" (off)
+        : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
+
+        return __pte(off);
+}
+
+static inline pgprot_t pgprot_noncached(pgprot_t prot)
+{
+        unsigned long val = pgprot_val(prot);
+
+        __asm__ __volatile__(
+        "\n661: andn            %0, %2, %0\n"
+        "       or              %0, %3, %0\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       andn            %0, %4, %0\n"
+        "       or              %0, %5, %0\n"
+        "       .previous\n"
+        : "=r" (val)
+        : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
+                     "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
+
+        return __pgprot(val);
+}
+/* Various pieces of code check for platform support by ifdef testing
+ * on "pgprot_noncached".  That's broken and should be fixed, but for
+ * now...
+ */
+#define pgprot_noncached pgprot_noncached
+
+#ifdef CONFIG_HUGETLB_PAGE
+static inline pte_t pte_mkhuge(pte_t pte)
+{
+        unsigned long mask;
+
+        __asm__ __volatile__(
+        "\n661: sethi           %%uhi(%1), %0\n"
+        "       sllx            %0, 32, %0\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       mov             %2, %0\n"
+        "       nop\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
+
+        return __pte(pte_val(pte) | mask);
+}
+#endif
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        unsigned long val = pte_val(pte), tmp;
+
+        __asm__ __volatile__(
+        "\n661: or              %0, %3, %0\n"
+        "       nop\n"
+        "\n662: nop\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%4), %1\n"
+        "       sllx            %1, 32, %1\n"
+        "       .word           662b\n"
+        "       or              %1, %%lo(%4), %1\n"
+        "       or              %0, %1, %0\n"
+        "       .previous\n"
+        : "=r" (val), "=r" (tmp)
+        : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
+          "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
+
+        return __pte(val);
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        unsigned long val = pte_val(pte), tmp;
+
+        __asm__ __volatile__(
+        "\n661: andn            %0, %3, %0\n"
+        "       nop\n"
+        "\n662: nop\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%4), %1\n"
+        "       sllx            %1, 32, %1\n"
+        "       .word           662b\n"
+        "       or              %1, %%lo(%4), %1\n"
+        "       andn            %0, %1, %0\n"
+        "       .previous\n"
+        : "=r" (val), "=r" (tmp)
+        : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
+          "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
+
+        return __pte(val);
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        unsigned long val = pte_val(pte), mask;
+
+        __asm__ __volatile__(
+        "\n661: mov             %1, %0\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%2), %0\n"
+        "       sllx            %0, 32, %0\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
+
+        return __pte(val | mask);
+}
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        unsigned long val = pte_val(pte), tmp;
+
+        __asm__ __volatile__(
+        "\n661: andn            %0, %3, %0\n"
+        "       nop\n"
+        "\n662: nop\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%4), %1\n"
+        "       sllx            %1, 32, %1\n"
+        "       .word           662b\n"
+        "       or              %1, %%lo(%4), %1\n"
+        "       andn            %0, %1, %0\n"
+        "       .previous\n"
+        : "=r" (val), "=r" (tmp)
+        : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
+          "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
+
+        return __pte(val);
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        unsigned long mask;
+
+        __asm__ __volatile__(
+        "\n661: mov             %1, %0\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%2), %0\n"
+        "       sllx            %0, 32, %0\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
+
+        mask |= _PAGE_R;
+
+        return __pte(pte_val(pte) & ~mask);
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        unsigned long mask;
+
+        __asm__ __volatile__(
+        "\n661: mov             %1, %0\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%2), %0\n"
+        "       sllx            %0, 32, %0\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
+
+        mask |= _PAGE_R;
+
+        return __pte(pte_val(pte) | mask);
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+        return pte;
+}
+
+static inline unsigned long pte_young(pte_t pte)
+{
+        unsigned long mask;
+
+        __asm__ __volatile__(
+        "\n661: mov             %1, %0\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%2), %0\n"
+        "       sllx            %0, 32, %0\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
+
+        return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_dirty(pte_t pte)
+{
+        unsigned long mask;
+
+        __asm__ __volatile__(
+        "\n661: mov             %1, %0\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%2), %0\n"
+        "       sllx            %0, 32, %0\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
+
+        return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_write(pte_t pte)
+{
+        unsigned long mask;
+
+        __asm__ __volatile__(
+        "\n661: mov             %1, %0\n"
+        "       nop\n"
+        "       .section        .sun4v_2insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       sethi           %%uhi(%2), %0\n"
+        "       sllx            %0, 32, %0\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
+
+        return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_exec(pte_t pte)
+{
+        unsigned long mask;
+
+        __asm__ __volatile__(
+        "\n661: sethi           %%hi(%1), %0\n"
+        "       .section        .sun4v_1insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       mov             %2, %0\n"
+        "       .previous\n"
+        : "=r" (mask)
+        : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
+
+        return (pte_val(pte) & mask);
+}
+
+static inline unsigned long pte_file(pte_t pte)
+{
+        unsigned long val = pte_val(pte);
+
+        __asm__ __volatile__(
+        "\n661: and             %0, %2, %0\n"
+        "       .section        .sun4v_1insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       and             %0, %3, %0\n"
+        "       .previous\n"
+        : "=r" (val)
+        : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
+
+        return val;
+}
+
+static inline unsigned long pte_present(pte_t pte)
+{
+        unsigned long val = pte_val(pte);
+
+        __asm__ __volatile__(
+        "\n661: and             %0, %2, %0\n"
+        "       .section        .sun4v_1insn_patch, \"ax\"\n"
+        "       .word           661b\n"
+        "       and             %0, %3, %0\n"
+        "       .previous\n"
+        : "=r" (val)
+        : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
+
+        return val;
+}
+
+static inline int pte_special(pte_t pte)
+{
+        return 0;
+}
+
+#define pmd_set(pmdp, ptep)     \
+        (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
+#define pud_set(pudp, pmdp)     \
+        (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
+#define __pmd_page(pmd)         \
+        ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
+#define pmd_page(pmd)                   virt_to_page((void *)__pmd_page(pmd))
+#define pud_page_vaddr(pud)             \
+        ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
+#define pud_page(pud)                   virt_to_page((void *)pud_page_vaddr(pud))
+#define pmd_none(pmd)                   (!pmd_val(pmd))
+#define pmd_bad(pmd)                    (0)
+#define pmd_present(pmd)                (pmd_val(pmd) != 0U)
+#define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0U)
+#define pud_none(pud)                   (!pud_val(pud))
+#define pud_bad(pud)                    (0)
+#define pud_present(pud)                (pud_val(pud) != 0U)
+#define pud_clear(pudp)                 (pud_val(*(pudp)) = 0U)
+
+/* Same in both SUN4V and SUN4U.  */
+#define pte_none(pte)                   (!pte_val(pte))
+
+/* to find an entry in a page-table-directory. */
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* Find an entry in the second-level page table.. */
+#define pmd_offset(pudp, address)       \
+        ((pmd_t *) pud_page_vaddr(*(pudp)) + \
+         (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(dir, address) \
+        ((pte_t *) __pmd_page(*(dir)) + \
+         ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#define pte_offset_kernel               pte_index
+#define pte_offset_map                  pte_index
+#define pte_offset_map_nested           pte_index
+#define pte_unmap(pte)                  do { } while (0)
+#define pte_unmap_nested(pte)           do { } while (0)
+
+/* Actual page table PTE updates.  */
+extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
+{
+        pte_t orig = *ptep;
+
+        *ptep = pte;
+
+        /* It is more efficient to let flush_tlb_kernel_range()
+         * handle init_mm tlb flushes.
+         *
+         * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
+         *             and SUN4V pte layout, so this inline test is fine.
+         */
+        if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
+                tlb_batch_add(mm, addr, ptep, orig);
+}
+
+#define pte_clear(mm,addr,ptep)         \
+        set_pte_at((mm), (addr), (ptep), __pte(0UL))
+
+#ifdef DCACHE_ALIASING_POSSIBLE
+#define __HAVE_ARCH_MOVE_PTE
+#define move_pte(pte, prot, old_addr, new_addr)                         \
+({                                                                      \
+        pte_t newpte = (pte);                                           \
+        if (tlb_type != hypervisor && pte_present(pte)) {               \
+                unsigned long this_pfn = pte_pfn(pte);                  \
+                                                                        \
+                if (pfn_valid(this_pfn) &&                              \
+                    (((old_addr) ^ (new_addr)) & (1 << 13)))            \
+                        flush_dcache_page_all(current->mm,              \
+                                              pfn_to_page(this_pfn));   \
+        }                                                               \
+        newpte;                                                         \
+})
+#endif
+
+extern pgd_t swapper_pg_dir[2048];
+extern pmd_t swapper_low_pmd_dir[2048];
+
+extern void paging_init(void);
+extern unsigned long find_ecache_flush_span(unsigned long size);
+
+/* These do nothing with the way I have things setup. */
+#define mmu_lockarea(vaddr, len)                (vaddr)
+#define mmu_unlockarea(vaddr, len)              do { } while(0)
+
+struct vm_area_struct;
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+
+/* Encode and de-code a swap entry */
+#define __swp_type(entry)       (((entry).val >> PAGE_SHIFT) & 0xffUL)
+#define __swp_offset(entry)     ((entry).val >> (PAGE_SHIFT + 8UL))
+#define __swp_entry(type, offset)       \
+        ( (swp_entry_t) \
+          { \
+                (((long)(type) << PAGE_SHIFT) | \
+                 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
+          } )
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
+
+/* File offset in PTE support. */
+extern unsigned long pte_file(pte_t);
+#define pte_to_pgoff(pte)       (pte_val(pte) >> PAGE_SHIFT)
+extern pte_t pgoff_to_pte(unsigned long);
+#define PTE_FILE_MAX_BITS       (64UL - PAGE_SHIFT - 1UL)
+
+extern unsigned long *sparc64_valid_addr_bitmap;
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr)   \
+        (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
+
+extern int page_in_phys_avail(unsigned long paddr);
+
+extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
+                               unsigned long pfn,
+                               unsigned long size, pgprot_t prot);
+
+/*
+ * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
+ * its high 4 bits.  These macros/functions put it there or get it from there.
+ */
+#define MK_IOSPACE_PFN(space, pfn)      (pfn | (space << (BITS_PER_LONG - 4)))
+#define GET_IOSPACE(pfn)                (pfn >> (BITS_PER_LONG - 4))
+#define GET_PFN(pfn)                    (pfn & 0x0fffffffffffffffUL)
+
+#include <asm-generic/pgtable.h>
+
+/* We provide our own get_unmapped_area to cope with VA holes and
+ * SHM area cache aliasing for userland.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
+ * the largest alignment possible such that larget PTEs can be used.
+ */
+extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
+                                          unsigned long, unsigned long,
+                                          unsigned long);
+#define HAVE_ARCH_FB_UNMAPPED_AREA
+
+extern void pgtable_cache_init(void);
+extern void sun4v_register_fault_status(void);
+extern void sun4v_ktsb_register(void);
+extern void __init cheetah_ecache_flush_init(void);
+extern void sun4v_patch_tlb_handlers(void);
+
+extern unsigned long cmdline_memory_size;
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC64_PGTABLE_H) */
diff --git a/arch/sparc/include/asm/pgtsrmmu.h b/arch/sparc/include/asm/pgtsrmmu.h
new file mode 100644
index 000000000000..808555fc1d58
--- /dev/null
+++ b/arch/sparc/include/asm/pgtsrmmu.h
@@ -0,0 +1,298 @@
+/*
+ * pgtsrmmu.h:  SRMMU page table defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_PGTSRMMU_H
+#define _SPARC_PGTSRMMU_H
+
+#include <asm/page.h>
+
+#ifdef __ASSEMBLY__
+#include <asm/thread_info.h>    /* TI_UWINMASK for WINDOW_FLUSH */
+#endif
+
+/* Number of contexts is implementation-dependent; 64k is the most we support */
+#define SRMMU_MAX_CONTEXTS      65536
+
+/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
+#define SRMMU_REAL_PMD_SHIFT            18
+#define SRMMU_REAL_PMD_SIZE             (1UL << SRMMU_REAL_PMD_SHIFT)
+#define SRMMU_REAL_PMD_MASK             (~(SRMMU_REAL_PMD_SIZE-1))
+#define SRMMU_REAL_PMD_ALIGN(__addr)    (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SRMMU_PGDIR_SHIFT       24
+#define SRMMU_PGDIR_SIZE        (1UL << SRMMU_PGDIR_SHIFT)
+#define SRMMU_PGDIR_MASK        (~(SRMMU_PGDIR_SIZE-1))
+#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
+
+#define SRMMU_REAL_PTRS_PER_PTE 64
+#define SRMMU_REAL_PTRS_PER_PMD 64
+#define SRMMU_PTRS_PER_PGD      256
+
+#define SRMMU_REAL_PTE_TABLE_SIZE       (SRMMU_REAL_PTRS_PER_PTE*4)
+#define SRMMU_PMD_TABLE_SIZE            (SRMMU_REAL_PTRS_PER_PMD*4)
+#define SRMMU_PGD_TABLE_SIZE            (SRMMU_PTRS_PER_PGD*4)
+
+/*
+ * To support pagetables in highmem, Linux introduces APIs which
+ * return struct page* and generally manipulate page tables when
+ * they are not mapped into kernel space. Our hardware page tables
+ * are smaller than pages. We lump hardware tabes into big, page sized
+ * software tables.
+ *
+ * PMD_SHIFT determines the size of the area a second-level page table entry
+ * can map, and our pmd_t is 16 times larger than normal.  The values which
+ * were once defined here are now generic for 4c and srmmu, so they're
+ * found in pgtable.h.
+ */
+#define SRMMU_PTRS_PER_PMD      4
+
+/* Definition of the values in the ET field of PTD's and PTE's */
+#define SRMMU_ET_MASK         0x3
+#define SRMMU_ET_INVALID      0x0
+#define SRMMU_ET_PTD          0x1
+#define SRMMU_ET_PTE          0x2
+#define SRMMU_ET_REPTE        0x3 /* AIEEE, SuperSparc II reverse endian page! */
+
+/* Physical page extraction from PTP's and PTE's. */
+#define SRMMU_CTX_PMASK    0xfffffff0
+#define SRMMU_PTD_PMASK    0xfffffff0
+#define SRMMU_PTE_PMASK    0xffffff00
+
+/* The pte non-page bits.  Some notes:
+ * 1) cache, dirty, valid, and ref are frobbable
+ *    for both supervisor and user pages.
+ * 2) exec and write will only give the desired effect
+ *    on user pages
+ * 3) use priv and priv_readonly for changing the
+ *    characteristics of supervisor ptes
+ */
+#define SRMMU_CACHE        0x80
+#define SRMMU_DIRTY        0x40
+#define SRMMU_REF          0x20
+#define SRMMU_NOREAD       0x10
+#define SRMMU_EXEC         0x08
+#define SRMMU_WRITE        0x04
+#define SRMMU_VALID        0x02 /* SRMMU_ET_PTE */
+#define SRMMU_PRIV         0x1c
+#define SRMMU_PRIV_RDONLY  0x18
+
+#define SRMMU_FILE         0x40 /* Implemented in software */
+
+#define SRMMU_PTE_FILE_SHIFT     8      /* == 32-PTE_FILE_MAX_BITS */
+
+#define SRMMU_CHG_MASK    (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
+
+/* SRMMU swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset.  This gives us
+ * 32 swapfiles of 4GB each.  Encoding looks like:
+ *
+ * oooooooooooooooooootttttRRRRRRRR
+ * fedcba9876543210fedcba9876543210
+ *
+ * The bottom 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SRMMU_SWP_TYPE_MASK     0x1f
+#define SRMMU_SWP_TYPE_SHIFT    SRMMU_PTE_FILE_SHIFT
+#define SRMMU_SWP_OFF_MASK      0x7ffff
+#define SRMMU_SWP_OFF_SHIFT     (SRMMU_PTE_FILE_SHIFT + 5)
+
+/* Some day I will implement true fine grained access bits for
+ * user pages because the SRMMU gives us the capabilities to
+ * enforce all the protection levels that vma's can have.
+ * XXX But for now...
+ */
+#define SRMMU_PAGE_NONE    __pgprot(SRMMU_CACHE | \
+                                    SRMMU_PRIV | SRMMU_REF)
+#define SRMMU_PAGE_SHARED  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
+                                    SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
+#define SRMMU_PAGE_COPY    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
+                                    SRMMU_EXEC | SRMMU_REF)
+#define SRMMU_PAGE_RDONLY  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
+                                    SRMMU_EXEC | SRMMU_REF)
+#define SRMMU_PAGE_KERNEL  __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
+                                    SRMMU_DIRTY | SRMMU_REF)
+
+/* SRMMU Register addresses in ASI 0x4.  These are valid for all
+ * current SRMMU implementations that exist.
+ */
+#define SRMMU_CTRL_REG           0x00000000
+#define SRMMU_CTXTBL_PTR         0x00000100
+#define SRMMU_CTX_REG            0x00000200
+#define SRMMU_FAULT_STATUS       0x00000300
+#define SRMMU_FAULT_ADDR         0x00000400
+
+#define WINDOW_FLUSH(tmp1, tmp2)                                        \
+        mov     0, tmp1;                                                \
+98:     ld      [%g6 + TI_UWINMASK], tmp2;                              \
+        orcc    %g0, tmp2, %g0;                                         \
+        add     tmp1, 1, tmp1;                                          \
+        bne     98b;                                                    \
+         save   %sp, -64, %sp;                                          \
+99:     subcc   tmp1, 1, tmp1;                                          \
+        bne     99b;                                                    \
+         restore %g0, %g0, %g0;
+
+#ifndef __ASSEMBLY__
+
+/* This makes sense. Honest it does - Anton */
+/* XXX Yes but it's ugly as sin.  FIXME. -KMW */
+extern void *srmmu_nocache_pool;
+#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
+#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
+#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
+
+/* Accessing the MMU control register. */
+static inline unsigned int srmmu_get_mmureg(void)
+{
+        unsigned int retval;
+        __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
+                             "=r" (retval) :
+                             "i" (ASI_M_MMUREGS));
+        return retval;
+}
+
+static inline void srmmu_set_mmureg(unsigned long regval)
+{
+        __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
+                             "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
+
+}
+
+static inline void srmmu_set_ctable_ptr(unsigned long paddr)
+{
+        paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
+        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+                             "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
+                             "i" (ASI_M_MMUREGS) :
+                             "memory");
+}
+
+static inline unsigned long srmmu_get_ctable_ptr(void)
+{
+        unsigned int retval;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_CTXTBL_PTR),
+                             "i" (ASI_M_MMUREGS));
+        return (retval & SRMMU_CTX_PMASK) << 4;
+}
+
+static inline void srmmu_set_context(int context)
+{
+        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
+                             "r" (context), "r" (SRMMU_CTX_REG),
+                             "i" (ASI_M_MMUREGS) : "memory");
+}
+
+static inline int srmmu_get_context(void)
+{
+        register int retval;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_CTX_REG),
+                             "i" (ASI_M_MMUREGS));
+        return retval;
+}
+
+static inline unsigned int srmmu_get_fstatus(void)
+{
+        unsigned int retval;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
+        return retval;
+}
+
+static inline unsigned int srmmu_get_faddr(void)
+{
+        unsigned int retval;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
+        return retval;
+}
+
+/* This is guaranteed on all SRMMU's. */
+static inline void srmmu_flush_whole_tlb(void)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (0x400),        /* Flush entire TLB!! */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+/* These flush types are not available on all chips... */
+static inline void srmmu_flush_tlb_ctx(void)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (0x300),        /* Flush TLB ctx.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline void srmmu_flush_tlb_region(unsigned long addr)
+{
+        addr &= SRMMU_PGDIR_MASK;
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (addr | 0x200), /* Flush TLB region.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+
+static inline void srmmu_flush_tlb_segment(unsigned long addr)
+{
+        addr &= SRMMU_REAL_PMD_MASK;
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (addr | 0x100), /* Flush TLB segment.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline void srmmu_flush_tlb_page(unsigned long page)
+{
+        page &= PAGE_MASK;
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
+                             "r" (page),        /* Flush TLB page.. */
+                             "i" (ASI_M_FLUSH_PROBE) : "memory");
+
+}
+
+static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
+{
+        unsigned long retval;
+
+        vaddr &= PAGE_MASK;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
+
+        return retval;
+}
+
+static inline int
+srmmu_get_pte (unsigned long addr)
+{
+        register unsigned long entry;
+        
+        __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
+                                "=r" (entry):
+                                "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
+        return entry;
+}
+
+extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
+extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSRMMU_H) */
diff --git a/arch/sparc/include/asm/pgtsun4.h b/arch/sparc/include/asm/pgtsun4.h
new file mode 100644
index 000000000000..5a0d661fb82e
--- /dev/null
+++ b/arch/sparc/include/asm/pgtsun4.h
@@ -0,0 +1,171 @@
+/*
+ * pgtsun4.h:  Sun4 specific pgtable.h defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _SPARC_PGTSUN4C_H
+#define _SPARC_PGTSUN4C_H
+
+#include <asm/contregs.h>
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define SUN4C_PMD_SHIFT       23
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SUN4C_PGDIR_SHIFT       23
+#define SUN4C_PGDIR_SIZE        (1UL << SUN4C_PGDIR_SHIFT)
+#define SUN4C_PGDIR_MASK        (~(SUN4C_PGDIR_SIZE-1))
+#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
+
+/* To represent how the sun4c mmu really lays things out. */
+#define SUN4C_REAL_PGDIR_SHIFT       18
+#define SUN4C_REAL_PGDIR_SIZE        (1UL << SUN4C_REAL_PGDIR_SHIFT)
+#define SUN4C_REAL_PGDIR_MASK        (~(SUN4C_REAL_PGDIR_SIZE-1))
+#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
+
+/* 19 bit PFN on sun4 */
+#define SUN4C_PFN_MASK 0x7ffff
+ 
+/* Don't increase these unless the structures in sun4c.c are fixed */
+#define SUN4C_MAX_SEGMAPS 256
+#define SUN4C_MAX_CONTEXTS 16
+
+/*
+ * To be efficient, and not have to worry about allocating such
+ * a huge pgd, we make the kernel sun4c tables each hold 1024
+ * entries and the pgd similarly just like the i386 tables.
+ */
+#define SUN4C_PTRS_PER_PTE    1024
+#define SUN4C_PTRS_PER_PMD    1
+#define SUN4C_PTRS_PER_PGD    1024
+
+/*
+ * Sparc SUN4C pte fields.
+ */
+#define _SUN4C_PAGE_VALID        0x80000000
+#define _SUN4C_PAGE_SILENT_READ  0x80000000   /* synonym */
+#define _SUN4C_PAGE_DIRTY        0x40000000
+#define _SUN4C_PAGE_SILENT_WRITE 0x40000000   /* synonym */
+#define _SUN4C_PAGE_PRIV         0x20000000   /* privileged page */
+#define _SUN4C_PAGE_NOCACHE      0x10000000   /* non-cacheable page */
+#define _SUN4C_PAGE_PRESENT      0x08000000   /* implemented in software */
+#define _SUN4C_PAGE_IO           0x04000000   /* I/O page */
+#define _SUN4C_PAGE_FILE         0x02000000   /* implemented in software */
+#define _SUN4C_PAGE_READ         0x00800000   /* implemented in software */
+#define _SUN4C_PAGE_WRITE        0x00400000   /* implemented in software */
+#define _SUN4C_PAGE_ACCESSED     0x00200000   /* implemented in software */
+#define _SUN4C_PAGE_MODIFIED     0x00100000   /* implemented in software */
+
+#define _SUN4C_READABLE         (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
+                                 _SUN4C_PAGE_ACCESSED)
+#define _SUN4C_WRITEABLE        (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
+                                 _SUN4C_PAGE_MODIFIED)
+
+#define _SUN4C_PAGE_CHG_MASK    (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
+
+#define SUN4C_PAGE_NONE         __pgprot(_SUN4C_PAGE_PRESENT)
+#define SUN4C_PAGE_SHARED       __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
+                                         _SUN4C_PAGE_WRITE)
+#define SUN4C_PAGE_COPY         __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_READONLY     __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_KERNEL       __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
+                                         _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
+
+/* SUN4C swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset.  This gives us
+ * 32 swapfiles of 4GB each.  Encoding looks like:
+ *
+ * RRRRRRRRooooooooooooooooooottttt
+ * fedcba9876543210fedcba9876543210
+ *
+ * The top 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SUN4C_SWP_TYPE_MASK     0x1f
+#define SUN4C_SWP_OFF_MASK      0x7ffff
+#define SUN4C_SWP_OFF_SHIFT     5
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long sun4c_get_synchronous_error(void)
+{
+        unsigned long sync_err;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_err) :
+                             "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
+        return sync_err;
+}
+
+static inline unsigned long sun4c_get_synchronous_address(void)
+{
+        unsigned long sync_addr;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_addr) :
+                             "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
+        return sync_addr;
+}
+
+/* SUN4 pte, segmap, and context manipulation */
+static inline unsigned long sun4c_get_segmap(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_SEGMAP));
+  return entry;
+}
+
+static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
+{
+  __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), "r" (entry),
+                       "i" (ASI_SEGMAP)
+                       : "memory");
+}
+
+static inline unsigned long sun4c_get_pte(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_PTE));
+  return entry;
+}
+
+static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
+{
+  __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), 
+                       "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
+                       : "memory");
+}
+
+static inline int sun4c_get_context(void)
+{
+  register int ctx;
+
+  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
+                       "=r" (ctx) :
+                       "r" (AC_CONTEXT), "i" (ASI_CONTROL));
+
+  return ctx;
+}
+
+static inline int sun4c_set_context(int ctx)
+{
+  __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
+                       "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
+                       : "memory");
+
+  return ctx;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSUN4_H) */
diff --git a/arch/sparc/include/asm/pgtsun4c.h b/arch/sparc/include/asm/pgtsun4c.h
new file mode 100644
index 000000000000..aeb25e912179
--- /dev/null
+++ b/arch/sparc/include/asm/pgtsun4c.h
@@ -0,0 +1,172 @@
+/*
+ * pgtsun4c.h:  Sun4c specific pgtable.h defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_PGTSUN4C_H
+#define _SPARC_PGTSUN4C_H
+
+#include <asm/contregs.h>
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define SUN4C_PMD_SHIFT       22
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SUN4C_PGDIR_SHIFT       22
+#define SUN4C_PGDIR_SIZE        (1UL << SUN4C_PGDIR_SHIFT)
+#define SUN4C_PGDIR_MASK        (~(SUN4C_PGDIR_SIZE-1))
+#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
+
+/* To represent how the sun4c mmu really lays things out. */
+#define SUN4C_REAL_PGDIR_SHIFT       18
+#define SUN4C_REAL_PGDIR_SIZE        (1UL << SUN4C_REAL_PGDIR_SHIFT)
+#define SUN4C_REAL_PGDIR_MASK        (~(SUN4C_REAL_PGDIR_SIZE-1))
+#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
+
+/* 16 bit PFN on sun4c */
+#define SUN4C_PFN_MASK 0xffff
+
+/* Don't increase these unless the structures in sun4c.c are fixed */
+#define SUN4C_MAX_SEGMAPS 256
+#define SUN4C_MAX_CONTEXTS 16
+
+/*
+ * To be efficient, and not have to worry about allocating such
+ * a huge pgd, we make the kernel sun4c tables each hold 1024
+ * entries and the pgd similarly just like the i386 tables.
+ */
+#define SUN4C_PTRS_PER_PTE    1024
+#define SUN4C_PTRS_PER_PMD    1
+#define SUN4C_PTRS_PER_PGD    1024
+
+/*
+ * Sparc SUN4C pte fields.
+ */
+#define _SUN4C_PAGE_VALID        0x80000000
+#define _SUN4C_PAGE_SILENT_READ  0x80000000   /* synonym */
+#define _SUN4C_PAGE_DIRTY        0x40000000
+#define _SUN4C_PAGE_SILENT_WRITE 0x40000000   /* synonym */
+#define _SUN4C_PAGE_PRIV         0x20000000   /* privileged page */
+#define _SUN4C_PAGE_NOCACHE      0x10000000   /* non-cacheable page */
+#define _SUN4C_PAGE_PRESENT      0x08000000   /* implemented in software */
+#define _SUN4C_PAGE_IO           0x04000000   /* I/O page */
+#define _SUN4C_PAGE_FILE         0x02000000   /* implemented in software */
+#define _SUN4C_PAGE_READ         0x00800000   /* implemented in software */
+#define _SUN4C_PAGE_WRITE        0x00400000   /* implemented in software */
+#define _SUN4C_PAGE_ACCESSED     0x00200000   /* implemented in software */
+#define _SUN4C_PAGE_MODIFIED     0x00100000   /* implemented in software */
+
+#define _SUN4C_READABLE         (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
+                                 _SUN4C_PAGE_ACCESSED)
+#define _SUN4C_WRITEABLE        (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
+                                 _SUN4C_PAGE_MODIFIED)
+
+#define _SUN4C_PAGE_CHG_MASK    (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
+
+#define SUN4C_PAGE_NONE         __pgprot(_SUN4C_PAGE_PRESENT)
+#define SUN4C_PAGE_SHARED       __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
+                                         _SUN4C_PAGE_WRITE)
+#define SUN4C_PAGE_COPY         __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_READONLY     __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_KERNEL       __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
+                                         _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
+
+/* SUN4C swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset.  This gives us
+ * 32 swapfiles of 4GB each.  Encoding looks like:
+ *
+ * RRRRRRRRooooooooooooooooooottttt
+ * fedcba9876543210fedcba9876543210
+ *
+ * The top 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SUN4C_SWP_TYPE_MASK     0x1f
+#define SUN4C_SWP_OFF_MASK      0x7ffff
+#define SUN4C_SWP_OFF_SHIFT     5
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long sun4c_get_synchronous_error(void)
+{
+        unsigned long sync_err;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_err) :
+                             "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
+        return sync_err;
+}
+
+static inline unsigned long sun4c_get_synchronous_address(void)
+{
+        unsigned long sync_addr;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_addr) :
+                             "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
+        return sync_addr;
+}
+
+/* SUN4C pte, segmap, and context manipulation */
+static inline unsigned long sun4c_get_segmap(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_SEGMAP));
+
+  return entry;
+}
+
+static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
+{
+
+  __asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), "r" (entry),
+                       "i" (ASI_SEGMAP)
+                       : "memory");
+}
+
+static inline unsigned long sun4c_get_pte(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_PTE));
+  return entry;
+}
+
+static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
+{
+  __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), 
+                       "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
+                       : "memory");
+}
+
+static inline int sun4c_get_context(void)
+{
+  register int ctx;
+
+  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
+                       "=r" (ctx) :
+                       "r" (AC_CONTEXT), "i" (ASI_CONTROL));
+
+  return ctx;
+}
+
+static inline int sun4c_set_context(int ctx)
+{
+  __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
+                       "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
+                       : "memory");
+
+  return ctx;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSUN4C_H) */
diff --git a/arch/sparc/include/asm/pil.h b/arch/sparc/include/asm/pil.h
new file mode 100644
index 000000000000..71819bb943fc
--- /dev/null
+++ b/arch/sparc/include/asm/pil.h
@@ -0,0 +1,22 @@
+#ifndef _SPARC64_PIL_H
+#define _SPARC64_PIL_H
+
+/* To avoid some locking problems, we hard allocate certain PILs
+ * for SMP cross call messages that must do a etrap/rtrap.
+ *
+ * A local_irq_disable() does not block the cross call delivery, so
+ * when SMP locking is an issue we reschedule the event into a PIL
+ * interrupt which is blocked by local_irq_disable().
+ *
+ * In fact any XCALL which has to etrap/rtrap has a problem because
+ * it is difficult to prevent rtrap from running BH's, and that would
+ * need to be done if the XCALL arrived while %pil==15.
+ */
+#define PIL_SMP_CALL_FUNC       1
+#define PIL_SMP_RECEIVE_SIGNAL  2
+#define PIL_SMP_CAPTURE         3
+#define PIL_SMP_CTX_NEW_VERSION 4
+#define PIL_DEVICE_IRQ          5
+#define PIL_SMP_CALL_FUNC_SNGL  6
+
+#endif /* !(_SPARC64_PIL_H) */
diff --git a/arch/sparc/include/asm/poll.h b/arch/sparc/include/asm/poll.h
new file mode 100644
index 000000000000..091d3ad2e830
--- /dev/null
+++ b/arch/sparc/include/asm/poll.h
@@ -0,0 +1,12 @@
+#ifndef __SPARC_POLL_H
+#define __SPARC_POLL_H
+
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      256
+#define POLLMSG         512
+#define POLLREMOVE      1024
+#define POLLRDHUP       2048
+
+#include <asm-generic/poll.h>
+
+#endif
diff --git a/arch/sparc/include/asm/posix_types.h b/arch/sparc/include/asm/posix_types.h
new file mode 100644
index 000000000000..03a0e091a884
--- /dev/null
+++ b/arch/sparc/include/asm/posix_types.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_POSIX_TYPES_H
+#define ___ASM_SPARC_POSIX_TYPES_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/posix_types_64.h>
+#else
+#include <asm/posix_types_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/posix_types_32.h b/arch/sparc/include/asm/posix_types_32.h
new file mode 100644
index 000000000000..6bb6eb1ca0f2
--- /dev/null
+++ b/arch/sparc/include/asm/posix_types_32.h
@@ -0,0 +1,118 @@
+#ifndef __ARCH_SPARC_POSIX_TYPES_H
+#define __ARCH_SPARC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int           __kernel_size_t;
+typedef int                    __kernel_ssize_t;
+typedef long int               __kernel_ptrdiff_t;
+typedef long                   __kernel_time_t;
+typedef long                   __kernel_suseconds_t;
+typedef long                   __kernel_clock_t;
+typedef int                    __kernel_pid_t;
+typedef unsigned short         __kernel_ipc_pid_t;
+typedef unsigned short         __kernel_uid_t;
+typedef unsigned short         __kernel_gid_t;
+typedef unsigned long          __kernel_ino_t;
+typedef unsigned short         __kernel_mode_t;
+typedef unsigned short         __kernel_umode_t;
+typedef short                  __kernel_nlink_t;
+typedef long                   __kernel_daddr_t;
+typedef long                   __kernel_off_t;
+typedef char *                 __kernel_caddr_t;
+typedef unsigned short         __kernel_uid16_t;
+typedef unsigned short         __kernel_gid16_t;
+typedef unsigned int           __kernel_uid32_t;
+typedef unsigned int           __kernel_gid32_t;
+typedef unsigned short         __kernel_old_uid_t;
+typedef unsigned short         __kernel_old_gid_t;
+typedef unsigned short         __kernel_old_dev_t;
+typedef int                    __kernel_clockid_t;
+typedef int                    __kernel_timer_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant cases (8 or 32 longs,
+ * for 256 and 1024-bit fd_sets respectively)
+ */
+#undef __FD_ZERO
+static inline void __FD_ZERO(__kernel_fd_set *p)
+{
+        unsigned long *tmp = p->fds_bits;
+        int i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                        case 32:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+                          tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                          tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
+                          tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
+                          tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
+                          tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
+                          return;
+                        case 16:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+                          tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                          return;
+                        case 8:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          return;
+                        case 4:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          return;
+                }
+        }
+        i = __FDSET_LONGS;
+        while (i) {
+                i--;
+                *tmp = 0;
+                tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */
diff --git a/arch/sparc/include/asm/posix_types_64.h b/arch/sparc/include/asm/posix_types_64.h
new file mode 100644
index 000000000000..ba8f93295763
--- /dev/null
+++ b/arch/sparc/include/asm/posix_types_64.h
@@ -0,0 +1,122 @@
+#ifndef __ARCH_SPARC64_POSIX_TYPES_H
+#define __ARCH_SPARC64_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long          __kernel_size_t;
+typedef long                   __kernel_ssize_t;
+typedef long                   __kernel_ptrdiff_t;
+typedef long                   __kernel_time_t;
+typedef long                   __kernel_clock_t;
+typedef int                    __kernel_pid_t;
+typedef int                    __kernel_ipc_pid_t;
+typedef unsigned int           __kernel_uid_t;
+typedef unsigned int           __kernel_gid_t;
+typedef unsigned long          __kernel_ino_t;
+typedef unsigned int           __kernel_mode_t;
+typedef unsigned short         __kernel_umode_t;
+typedef unsigned int           __kernel_nlink_t;
+typedef int                    __kernel_daddr_t;
+typedef long                   __kernel_off_t;
+typedef char *                 __kernel_caddr_t;
+typedef unsigned short         __kernel_uid16_t;
+typedef unsigned short         __kernel_gid16_t;
+typedef int                    __kernel_clockid_t;
+typedef int                    __kernel_timer_t;
+
+typedef unsigned short         __kernel_old_uid_t;
+typedef unsigned short         __kernel_old_gid_t;
+typedef __kernel_uid_t         __kernel_uid32_t;
+typedef __kernel_gid_t         __kernel_gid32_t;
+
+typedef unsigned int           __kernel_old_dev_t;
+
+/* Note this piece of asymmetry from the v9 ABI.  */
+typedef int                    __kernel_suseconds_t;
+
+#ifdef __GNUC__
+typedef long long              __kernel_loff_t;
+#endif
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant cases (8 or 32 longs,
+ * for 256 and 1024-bit fd_sets respectively)
+ */
+#undef __FD_ZERO
+static inline void __FD_ZERO(__kernel_fd_set *p)
+{
+        unsigned long *tmp = p->fds_bits;
+        int i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                        case 32:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+                          tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                          tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
+                          tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
+                          tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
+                          tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
+                          return;
+                        case 16:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+                          tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                          return;
+                        case 8:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          return;
+                        case 4:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          return;
+                }
+        }
+        i = __FDSET_LONGS;
+        while (i) {
+                i--;
+                *tmp = 0;
+                tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */
diff --git a/arch/sparc/include/asm/processor.h b/arch/sparc/include/asm/processor.h
new file mode 100644
index 000000000000..9da9646bf6c6
--- /dev/null
+++ b/arch/sparc/include/asm/processor.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_PROCESSOR_H
+#define ___ASM_SPARC_PROCESSOR_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/processor_64.h>
+#else
+#include <asm/processor_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/processor_32.h b/arch/sparc/include/asm/processor_32.h
new file mode 100644
index 000000000000..2ae67a2e7f3a
--- /dev/null
+++ b/arch/sparc/include/asm/processor_32.h
@@ -0,0 +1,129 @@
+/* include/asm/processor.h
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __ASM_SPARC_PROCESSOR_H
+#define __ASM_SPARC_PROCESSOR_H
+
+/*
+ * Sparc32 implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ void *pc; __asm__("sethi %%hi(1f), %0; or %0, %%lo(1f), %0;\n1:" : "=r" (pc)); pc; })
+
+#include <asm/psr.h>
+#include <asm/ptrace.h>
+#include <asm/head.h>
+#include <asm/signal.h>
+#include <asm/btfixup.h>
+#include <asm/page.h>
+
+/*
+ * The sparc has no problems with write protection
+ */
+#define wp_works_ok 1
+#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
+
+/* Whee, this is STACK_TOP + PAGE_SIZE and the lowest kernel address too...
+ * That one page is used to protect kernel from intruders, so that
+ * we can make our access_ok test faster
+ */
+#define TASK_SIZE       PAGE_OFFSET
+#ifdef __KERNEL__
+#define STACK_TOP       (PAGE_OFFSET - PAGE_SIZE)
+#define STACK_TOP_MAX   STACK_TOP
+#endif /* __KERNEL__ */
+
+struct task_struct;
+
+#ifdef __KERNEL__
+struct fpq {
+        unsigned long *insn_addr;
+        unsigned long insn;
+};
+#endif
+
+typedef struct {
+        int seg;
+} mm_segment_t;
+
+/* The Sparc processor specific thread struct. */
+struct thread_struct {
+        struct pt_regs *kregs;
+        unsigned int _pad1;
+
+        /* Special child fork kpsr/kwim values. */
+        unsigned long fork_kpsr __attribute__ ((aligned (8)));
+        unsigned long fork_kwim;
+
+        /* Floating point regs */
+        unsigned long   float_regs[32] __attribute__ ((aligned (8)));
+        unsigned long   fsr;
+        unsigned long   fpqdepth;
+        struct fpq      fpqueue[16];
+        unsigned long flags;
+        mm_segment_t current_ds;
+};
+
+#define SPARC_FLAG_KTHREAD      0x1    /* task is a kernel thread */
+#define SPARC_FLAG_UNALIGNED    0x2    /* is allowed to do unaligned accesses */
+
+#define INIT_THREAD  { \
+        .flags = SPARC_FLAG_KTHREAD, \
+        .current_ds = KERNEL_DS, \
+}
+
+/* Return saved PC of a blocked thread. */
+extern unsigned long thread_saved_pc(struct task_struct *t);
+
+/* Do necessary setup to start up a newly executed thread. */
+static inline void start_thread(struct pt_regs * regs, unsigned long pc,
+                                    unsigned long sp)
+{
+        register unsigned long zero asm("g1");
+
+        regs->psr = (regs->psr & (PSR_CWP)) | PSR_S;
+        regs->pc = ((pc & (~3)) - 4);
+        regs->npc = regs->pc + 4;
+        regs->y = 0;
+        zero = 0;
+        __asm__ __volatile__("std\t%%g0, [%0 + %3 + 0x00]\n\t"
+                             "std\t%%g0, [%0 + %3 + 0x08]\n\t"
+                             "std\t%%g0, [%0 + %3 + 0x10]\n\t"
+                             "std\t%%g0, [%0 + %3 + 0x18]\n\t"
+                             "std\t%%g0, [%0 + %3 + 0x20]\n\t"
+                             "std\t%%g0, [%0 + %3 + 0x28]\n\t"
+                             "std\t%%g0, [%0 + %3 + 0x30]\n\t"
+                             "st\t%1, [%0 + %3 + 0x38]\n\t"
+                             "st\t%%g0, [%0 + %3 + 0x3c]"
+                             : /* no outputs */
+                             : "r" (regs),
+                               "r" (sp - sizeof(struct reg_window)),
+                               "r" (zero),
+                               "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))
+                             : "memory");
+}
+
+/* Free all resources held by a thread. */
+#define release_thread(tsk)             do { } while(0)
+extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+extern unsigned long get_wchan(struct task_struct *);
+
+#define task_pt_regs(tsk) ((tsk)->thread.kregs)
+#define KSTK_EIP(tsk)  ((tsk)->thread.kregs->pc)
+#define KSTK_ESP(tsk)  ((tsk)->thread.kregs->u_regs[UREG_FP])
+
+#ifdef __KERNEL__
+
+extern struct task_struct *last_task_used_math;
+
+#define cpu_relax()     barrier()
+
+#endif
+
+#endif /* __ASM_SPARC_PROCESSOR_H */
diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm/processor_64.h
new file mode 100644
index 000000000000..137a6bd72fc8
--- /dev/null
+++ b/arch/sparc/include/asm/processor_64.h
@@ -0,0 +1,237 @@
+/*
+ * include/asm/processor.h
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __ASM_SPARC64_PROCESSOR_H
+#define __ASM_SPARC64_PROCESSOR_H
+
+/*
+ * Sparc64 implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
+
+#include <asm/asi.h>
+#include <asm/pstate.h>
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/* The sparc has no problems with write protection */
+#define wp_works_ok 1
+#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
+
+/*
+ * User lives in his very own context, and cannot reference us. Note
+ * that TASK_SIZE is a misnomer, it really gives maximum user virtual
+ * address that the kernel will allocate out.
+ *
+ * XXX No longer using virtual page tables, kill this upper limit...
+ */
+#define VA_BITS         44
+#ifndef __ASSEMBLY__
+#define VPTE_SIZE       (1UL << (VA_BITS - PAGE_SHIFT + 3))
+#else
+#define VPTE_SIZE       (1 << (VA_BITS - PAGE_SHIFT + 3))
+#endif
+
+#define TASK_SIZE       ((unsigned long)-VPTE_SIZE)
+#define TASK_SIZE_OF(tsk) \
+        (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
+         (1UL << 32UL) : TASK_SIZE)
+#ifdef __KERNEL__
+
+#define STACK_TOP32     ((1UL << 32UL) - PAGE_SIZE)
+#define STACK_TOP64     (0x0000080000000000UL - (1UL << 32UL))
+
+#define STACK_TOP       (test_thread_flag(TIF_32BIT) ? \
+                         STACK_TOP32 : STACK_TOP64)
+
+#define STACK_TOP_MAX   STACK_TOP64
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned char seg;
+} mm_segment_t;
+
+/* The Sparc processor specific thread struct. */
+/* XXX This should die, everything can go into thread_info now. */
+struct thread_struct {
+#ifdef CONFIG_DEBUG_SPINLOCK
+        /* How many spinlocks held by this thread.
+         * Used with spin lock debugging to catch tasks
+         * sleeping illegally with locks held.
+         */
+        int smp_lock_count;
+        unsigned int smp_lock_pc;
+#else
+        int dummy; /* f'in gcc bug... */
+#endif
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+#ifndef CONFIG_DEBUG_SPINLOCK
+#define INIT_THREAD  {                  \
+        0,                              \
+}
+#else /* CONFIG_DEBUG_SPINLOCK */
+#define INIT_THREAD  {                                  \
+/* smp_lock_count, smp_lock_pc, */                      \
+   0,              0,                                   \
+}
+#endif /* !(CONFIG_DEBUG_SPINLOCK) */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+/* Return saved PC of a blocked thread. */
+struct task_struct;
+extern unsigned long thread_saved_pc(struct task_struct *);
+
+/* On Uniprocessor, even in RMO processes see TSO semantics */
+#ifdef CONFIG_SMP
+#define TSTATE_INITIAL_MM       TSTATE_TSO
+#else
+#define TSTATE_INITIAL_MM       TSTATE_RMO
+#endif
+
+/* Do necessary setup to start up a newly executed thread. */
+#define start_thread(regs, pc, sp) \
+do { \
+        unsigned long __asi = ASI_PNF; \
+        regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
+        regs->tpc = ((pc & (~3)) - 4); \
+        regs->tnpc = regs->tpc + 4; \
+        regs->y = 0; \
+        set_thread_wstate(1 << 3); \
+        if (current_thread_info()->utraps) { \
+                if (*(current_thread_info()->utraps) < 2) \
+                        kfree(current_thread_info()->utraps); \
+                else \
+                        (*(current_thread_info()->utraps))--; \
+                current_thread_info()->utraps = NULL; \
+        } \
+        __asm__ __volatile__( \
+        "stx            %%g0, [%0 + %2 + 0x00]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x08]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x10]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x18]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x20]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x28]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x30]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x38]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x40]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x48]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x50]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x58]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x60]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x68]\n\t" \
+        "stx            %1,   [%0 + %2 + 0x70]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x78]\n\t" \
+        "wrpr           %%g0, (1 << 3), %%wstate\n\t" \
+        : \
+        : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
+          "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
+} while (0)
+
+#define start_thread32(regs, pc, sp) \
+do { \
+        unsigned long __asi = ASI_PNF; \
+        pc &= 0x00000000ffffffffUL; \
+        sp &= 0x00000000ffffffffUL; \
+        regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
+        regs->tpc = ((pc & (~3)) - 4); \
+        regs->tnpc = regs->tpc + 4; \
+        regs->y = 0; \
+        set_thread_wstate(2 << 3); \
+        if (current_thread_info()->utraps) { \
+                if (*(current_thread_info()->utraps) < 2) \
+                        kfree(current_thread_info()->utraps); \
+                else \
+                        (*(current_thread_info()->utraps))--; \
+                current_thread_info()->utraps = NULL; \
+        } \
+        __asm__ __volatile__( \
+        "stx            %%g0, [%0 + %2 + 0x00]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x08]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x10]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x18]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x20]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x28]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x30]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x38]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x40]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x48]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x50]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x58]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x60]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x68]\n\t" \
+        "stx            %1,   [%0 + %2 + 0x70]\n\t" \
+        "stx            %%g0, [%0 + %2 + 0x78]\n\t" \
+        "wrpr           %%g0, (2 << 3), %%wstate\n\t" \
+        : \
+        : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
+          "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
+} while (0)
+
+/* Free all resources held by a thread. */
+#define release_thread(tsk)             do { } while (0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+extern unsigned long get_wchan(struct task_struct *task);
+
+#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
+#define KSTK_EIP(tsk)  (task_pt_regs(tsk)->tpc)
+#define KSTK_ESP(tsk)  (task_pt_regs(tsk)->u_regs[UREG_FP])
+
+#define cpu_relax()     barrier()
+
+/* Prefetch support.  This is tuned for UltraSPARC-III and later.
+ * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
+ * a shallower prefetch queue than later chips.
+ */
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+#define ARCH_HAS_SPINLOCK_PREFETCH
+
+static inline void prefetch(const void *x)
+{
+        /* We do not use the read prefetch mnemonic because that
+         * prefetches into the prefetch-cache which only is accessible
+         * by floating point operations in UltraSPARC-III and later.
+         * By contrast, "#one_write" prefetches into the L2 cache
+         * in shared state.
+         */
+        __asm__ __volatile__("prefetch [%0], #one_write"
+                             : /* no outputs */
+                             : "r" (x));
+}
+
+static inline void prefetchw(const void *x)
+{
+        /* The most optimal prefetch to use for writes is
+         * "#n_writes".  This brings the cacheline into the
+         * L2 cache in "owned" state.
+         */
+        __asm__ __volatile__("prefetch [%0], #n_writes"
+                             : /* no outputs */
+                             : "r" (x));
+}
+
+#define spin_lock_prefetch(x)   prefetchw(x)
+
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
new file mode 100644
index 000000000000..fd55522481cd
--- /dev/null
+++ b/arch/sparc/include/asm/prom.h
@@ -0,0 +1,108 @@
+#ifndef _SPARC_PROM_H
+#define _SPARC_PROM_H
+#ifdef __KERNEL__
+
+/*
+ * Definitions for talking to the Open Firmware PROM on
+ * Power Macintosh computers.
+ *
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
+ * Updates for SPARC by David S. Miller
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <asm/atomic.h>
+
+#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
+#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
+
+#define of_compat_cmp(s1, s2, l)        strncmp((s1), (s2), (l))
+#define of_prop_cmp(s1, s2)             strcasecmp((s1), (s2))
+#define of_node_cmp(s1, s2)             strcmp((s1), (s2))
+
+typedef u32 phandle;
+typedef u32 ihandle;
+
+struct property {
+        char    *name;
+        int     length;
+        void    *value;
+        struct property *next;
+        unsigned long _flags;
+        unsigned int unique_id;
+};
+
+struct of_irq_controller;
+struct device_node {
+        const char      *name;
+        const char      *type;
+        phandle node;
+        char    *path_component_name;
+        char    *full_name;
+
+        struct  property *properties;
+        struct  property *deadprops; /* removed properties */
+        struct  device_node *parent;
+        struct  device_node *child;
+        struct  device_node *sibling;
+        struct  device_node *next;      /* next device of same type */
+        struct  device_node *allnext;   /* next in list of all nodes */
+        struct  proc_dir_entry *pde;    /* this node's proc directory */
+        struct  kref kref;
+        unsigned long _flags;
+        void    *data;
+        unsigned int unique_id;
+
+        struct of_irq_controller *irq_trans;
+};
+
+struct of_irq_controller {
+        unsigned int    (*irq_build)(struct device_node *, unsigned int, void *);
+        void            *data;
+};
+
+#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
+#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
+
+extern struct device_node *of_find_node_by_cpuid(int cpuid);
+extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
+extern int of_getintprop_default(struct device_node *np,
+                                 const char *name,
+                                 int def);
+extern int of_find_in_proplist(const char *list, const char *match, int len);
+#ifdef CONFIG_NUMA
+extern int of_node_to_nid(struct device_node *dp);
+#else
+#define of_node_to_nid(dp)      (-1)
+#endif
+
+extern void prom_build_devicetree(void);
+
+/* Dummy ref counting routines - to be implemented later */
+static inline struct device_node *of_node_get(struct device_node *node)
+{
+        return node;
+}
+static inline void of_node_put(struct device_node *node)
+{
+}
+
+/*
+ * NB:  This is here while we transition from using asm/prom.h
+ * to linux/of.h
+ */
+#include <linux/of.h>
+
+extern struct device_node *of_console_device;
+extern char *of_console_path;
+extern char *of_console_options;
+
+#endif /* __KERNEL__ */
+#endif /* _SPARC_PROM_H */
diff --git a/arch/sparc/include/asm/psr.h b/arch/sparc/include/asm/psr.h
new file mode 100644
index 000000000000..b8c0e5f0a66b
--- /dev/null
+++ b/arch/sparc/include/asm/psr.h
@@ -0,0 +1,93 @@
+/*
+ * psr.h: This file holds the macros for masking off various parts of
+ *        the processor status register on the Sparc. This is valid
+ *        for Version 8. On the V9 this is renamed to the PSTATE
+ *        register and its members are accessed as fields like
+ *        PSTATE.PRIV for the current CPU privilege level.
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __LINUX_SPARC_PSR_H
+#define __LINUX_SPARC_PSR_H
+
+/* The Sparc PSR fields are laid out as the following:
+ *
+ *  ------------------------------------------------------------------------
+ *  | impl  | vers  | icc   | resv  | EC | EF | PIL  | S | PS | ET |  CWP  |
+ *  | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
+ *  ------------------------------------------------------------------------
+ */
+#define PSR_CWP     0x0000001f         /* current window pointer     */
+#define PSR_ET      0x00000020         /* enable traps field         */
+#define PSR_PS      0x00000040         /* previous privilege level   */
+#define PSR_S       0x00000080         /* current privilege level    */
+#define PSR_PIL     0x00000f00         /* processor interrupt level  */
+#define PSR_EF      0x00001000         /* enable floating point      */
+#define PSR_EC      0x00002000         /* enable co-processor        */
+#define PSR_SYSCALL 0x00004000         /* inside of a syscall        */
+#define PSR_LE      0x00008000         /* SuperSparcII little-endian */
+#define PSR_ICC     0x00f00000         /* integer condition codes    */
+#define PSR_C       0x00100000         /* carry bit                  */
+#define PSR_V       0x00200000         /* overflow bit               */
+#define PSR_Z       0x00400000         /* zero bit                   */
+#define PSR_N       0x00800000         /* negative bit               */
+#define PSR_VERS    0x0f000000         /* cpu-version field          */
+#define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+/* Get the %psr register. */
+static inline unsigned int get_psr(void)
+{
+        unsigned int psr;
+        __asm__ __volatile__(
+                "rd     %%psr, %0\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                "nop\n\t"
+        : "=r" (psr)
+        : /* no inputs */
+        : "memory");
+
+        return psr;
+}
+
+static inline void put_psr(unsigned int new_psr)
+{
+        __asm__ __volatile__(
+                "wr     %0, 0x0, %%psr\n\t"
+                "nop\n\t"
+                "nop\n\t"
+                "nop\n\t"
+        : /* no outputs */
+        : "r" (new_psr)
+        : "memory", "cc");
+}
+
+/* Get the %fsr register.  Be careful, make sure the floating point
+ * enable bit is set in the %psr when you execute this or you will
+ * incur a trap.
+ */
+
+extern unsigned int fsr_storage;
+
+static inline unsigned int get_fsr(void)
+{
+        unsigned int fsr = 0;
+
+        __asm__ __volatile__(
+                "st     %%fsr, %1\n\t"
+                "ld     %1, %0\n\t"
+        : "=r" (fsr)
+        : "m" (fsr_storage));
+
+        return fsr;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* (__KERNEL__) */
+
+#endif /* !(__LINUX_SPARC_PSR_H) */
diff --git a/arch/sparc/include/asm/psrcompat.h b/arch/sparc/include/asm/psrcompat.h
new file mode 100644
index 000000000000..44b6327dbbf5
--- /dev/null
+++ b/arch/sparc/include/asm/psrcompat.h
@@ -0,0 +1,45 @@
+#ifndef _SPARC64_PSRCOMPAT_H
+#define _SPARC64_PSRCOMPAT_H
+
+#include <asm/pstate.h>
+
+/* Old 32-bit PSR fields for the compatibility conversion code. */
+#define PSR_CWP     0x0000001f         /* current window pointer     */
+#define PSR_ET      0x00000020         /* enable traps field         */
+#define PSR_PS      0x00000040         /* previous privilege level   */
+#define PSR_S       0x00000080         /* current privilege level    */
+#define PSR_PIL     0x00000f00         /* processor interrupt level  */
+#define PSR_EF      0x00001000         /* enable floating point      */
+#define PSR_EC      0x00002000         /* enable co-processor        */
+#define PSR_SYSCALL 0x00004000         /* inside of a syscall        */
+#define PSR_LE      0x00008000         /* SuperSparcII little-endian */
+#define PSR_ICC     0x00f00000         /* integer condition codes    */
+#define PSR_C       0x00100000         /* carry bit                  */
+#define PSR_V       0x00200000         /* overflow bit               */
+#define PSR_Z       0x00400000         /* zero bit                   */
+#define PSR_N       0x00800000         /* negative bit               */
+#define PSR_VERS    0x0f000000         /* cpu-version field          */
+#define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
+
+#define PSR_V8PLUS  0xff000000         /* fake impl/ver, meaning a 64bit CPU is present */
+#define PSR_XCC     0x000f0000         /* if PSR_V8PLUS, this is %xcc */
+
+static inline unsigned int tstate_to_psr(unsigned long tstate)
+{
+        return ((tstate & TSTATE_CWP)                   |
+                PSR_S                                   |
+                ((tstate & TSTATE_ICC) >> 12)           |
+                ((tstate & TSTATE_XCC) >> 20)           |
+                ((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
+                PSR_V8PLUS);
+}
+
+static inline unsigned long psr_to_tstate_icc(unsigned int psr)
+{
+        unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
+        if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
+                tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
+        return tstate;
+}
+
+#endif /* !(_SPARC64_PSRCOMPAT_H) */
diff --git a/arch/sparc/include/asm/pstate.h b/arch/sparc/include/asm/pstate.h
new file mode 100644
index 000000000000..a26a53777bb0
--- /dev/null
+++ b/arch/sparc/include/asm/pstate.h
@@ -0,0 +1,91 @@
+#ifndef _SPARC64_PSTATE_H
+#define _SPARC64_PSTATE_H
+
+#include <linux/const.h>
+
+/* The V9 PSTATE Register (with SpitFire extensions).
+ *
+ * -----------------------------------------------------------------------
+ * | Resv | IG | MG | CLE | TLE |  MM  | RED | PEF | AM | PRIV | IE | AG |
+ * -----------------------------------------------------------------------
+ *  63  12  11   10    9     8    7   6   5     4     3     2     1    0
+ */
+#define PSTATE_IG   _AC(0x0000000000000800,UL) /* Interrupt Globals.    */
+#define PSTATE_MG   _AC(0x0000000000000400,UL) /* MMU Globals.          */
+#define PSTATE_CLE  _AC(0x0000000000000200,UL) /* Current Little Endian.*/
+#define PSTATE_TLE  _AC(0x0000000000000100,UL) /* Trap Little Endian.   */
+#define PSTATE_MM   _AC(0x00000000000000c0,UL) /* Memory Model.         */
+#define PSTATE_TSO  _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder   */
+#define PSTATE_PSO  _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
+#define PSTATE_RMO  _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
+#define PSTATE_RED  _AC(0x0000000000000020,UL) /* Reset Error Debug.    */
+#define PSTATE_PEF  _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
+#define PSTATE_AM   _AC(0x0000000000000008,UL) /* Address Mask.         */
+#define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege.            */
+#define PSTATE_IE   _AC(0x0000000000000002,UL) /* Interrupt Enable.     */
+#define PSTATE_AG   _AC(0x0000000000000001,UL) /* Alternate Globals.    */
+
+/* The V9 TSTATE Register (with SpitFire and Linux extensions).
+ *
+ * ---------------------------------------------------------------------
+ * |  Resv |  GL  |  CCR  |  ASI  |  %pil  |  PSTATE  |  Resv  |  CWP  |
+ * ---------------------------------------------------------------------
+ *  63   43 42  40 39   32 31   24 23    20 19       8 7      5 4     0
+ */
+#define TSTATE_GL       _AC(0x0000070000000000,UL) /* Global reg level  */
+#define TSTATE_CCR      _AC(0x000000ff00000000,UL) /* Condition Codes.  */
+#define TSTATE_XCC      _AC(0x000000f000000000,UL) /* Condition Codes.  */
+#define TSTATE_XNEG     _AC(0x0000008000000000,UL) /* %xcc Negative.    */
+#define TSTATE_XZERO    _AC(0x0000004000000000,UL) /* %xcc Zero.        */
+#define TSTATE_XOVFL    _AC(0x0000002000000000,UL) /* %xcc Overflow.    */
+#define TSTATE_XCARRY   _AC(0x0000001000000000,UL) /* %xcc Carry.       */
+#define TSTATE_ICC      _AC(0x0000000f00000000,UL) /* Condition Codes.  */
+#define TSTATE_INEG     _AC(0x0000000800000000,UL) /* %icc Negative.    */
+#define TSTATE_IZERO    _AC(0x0000000400000000,UL) /* %icc Zero.        */
+#define TSTATE_IOVFL    _AC(0x0000000200000000,UL) /* %icc Overflow.    */
+#define TSTATE_ICARRY   _AC(0x0000000100000000,UL) /* %icc Carry.       */
+#define TSTATE_ASI      _AC(0x00000000ff000000,UL) /* AddrSpace ID.     */
+#define TSTATE_PIL      _AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/
+#define TSTATE_PSTATE   _AC(0x00000000000fff00,UL) /* PSTATE.           */
+#define TSTATE_IG       _AC(0x0000000000080000,UL) /* Interrupt Globals.*/
+#define TSTATE_MG       _AC(0x0000000000040000,UL) /* MMU Globals.      */
+#define TSTATE_CLE      _AC(0x0000000000020000,UL) /* CurrLittleEndian. */
+#define TSTATE_TLE      _AC(0x0000000000010000,UL) /* TrapLittleEndian. */
+#define TSTATE_MM       _AC(0x000000000000c000,UL) /* Memory Model.     */
+#define TSTATE_TSO      _AC(0x0000000000000000,UL) /* MM: TSO           */
+#define TSTATE_PSO      _AC(0x0000000000004000,UL) /* MM: PSO           */
+#define TSTATE_RMO      _AC(0x0000000000008000,UL) /* MM: RMO           */
+#define TSTATE_RED      _AC(0x0000000000002000,UL) /* Reset Error Debug.*/
+#define TSTATE_PEF      _AC(0x0000000000001000,UL) /* FPU Enable.       */
+#define TSTATE_AM       _AC(0x0000000000000800,UL) /* Address Mask.     */
+#define TSTATE_PRIV     _AC(0x0000000000000400,UL) /* Privilege.        */
+#define TSTATE_IE       _AC(0x0000000000000200,UL) /* Interrupt Enable. */
+#define TSTATE_AG       _AC(0x0000000000000100,UL) /* Alternate Globals.*/
+#define TSTATE_SYSCALL  _AC(0x0000000000000020,UL) /* in syscall trap   */
+#define TSTATE_CWP      _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
+
+/* Floating-Point Registers State Register.
+ *
+ * --------------------------------
+ * |  Resv  |  FEF  |  DU  |  DL  |
+ * --------------------------------
+ *  63     3    2       1      0
+ */
+#define FPRS_FEF        _AC(0x0000000000000004,UL) /* FPU Enable.       */
+#define FPRS_DU         _AC(0x0000000000000002,UL) /* Dirty Upper.      */
+#define FPRS_DL         _AC(0x0000000000000001,UL) /* Dirty Lower.      */
+
+/* Version Register.
+ *
+ * ------------------------------------------------------
+ * | MANUF | IMPL | MASK | Resv | MAXTL | Resv | MAXWIN |
+ * ------------------------------------------------------
+ *  63   48 47  32 31  24 23  16 15    8 7    5 4      0
+ */
+#define VERS_MANUF      _AC(0xffff000000000000,UL) /* Manufacturer.     */
+#define VERS_IMPL       _AC(0x0000ffff00000000,UL) /* Implementation.   */
+#define VERS_MASK       _AC(0x00000000ff000000,UL) /* Mask Set Revision.*/
+#define VERS_MAXTL      _AC(0x000000000000ff00,UL) /* Max Trap Level.   */
+#define VERS_MAXWIN     _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
+
+#endif /* !(_SPARC64_PSTATE_H) */
diff --git a/arch/sparc/include/asm/ptrace.h b/arch/sparc/include/asm/ptrace.h
new file mode 100644
index 000000000000..6dcbe2eed2e2
--- /dev/null
+++ b/arch/sparc/include/asm/ptrace.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_PTRACE_H
+#define ___ASM_SPARC_PTRACE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/ptrace_64.h>
+#else
+#include <asm/ptrace_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/ptrace_32.h b/arch/sparc/include/asm/ptrace_32.h
new file mode 100644
index 000000000000..d409c4f21a5c
--- /dev/null
+++ b/arch/sparc/include/asm/ptrace_32.h
@@ -0,0 +1,176 @@
+#ifndef _SPARC_PTRACE_H
+#define _SPARC_PTRACE_H
+
+#include <asm/psr.h>
+
+/* This struct defines the way the registers are stored on the
+ * stack during a system call and basically all traps.
+ */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+struct pt_regs {
+        unsigned long psr;
+        unsigned long pc;
+        unsigned long npc;
+        unsigned long y;
+        unsigned long u_regs[16]; /* globals and ins */
+};
+
+#define UREG_G0        0
+#define UREG_G1        1
+#define UREG_G2        2
+#define UREG_G3        3
+#define UREG_G4        4
+#define UREG_G5        5
+#define UREG_G6        6
+#define UREG_G7        7
+#define UREG_I0        8
+#define UREG_I1        9
+#define UREG_I2        10
+#define UREG_I3        11
+#define UREG_I4        12
+#define UREG_I5        13
+#define UREG_I6        14
+#define UREG_I7        15
+#define UREG_WIM       UREG_G0
+#define UREG_FADDR     UREG_G0
+#define UREG_FP        UREG_I6
+#define UREG_RETPC     UREG_I7
+
+/* A register window */
+struct reg_window {
+        unsigned long locals[8];
+        unsigned long ins[8];
+};
+
+/* A Sparc stack frame */
+struct sparc_stackf {
+        unsigned long locals[8];
+        unsigned long ins[6];
+        struct sparc_stackf *fp;
+        unsigned long callers_pc;
+        char *structptr;
+        unsigned long xargs[6];
+        unsigned long xxargs[1];
+};
+
+#define TRACEREG_SZ   sizeof(struct pt_regs)
+#define STACKFRAME_SZ sizeof(struct sparc_stackf)
+
+#ifdef __KERNEL__
+
+static inline bool pt_regs_is_syscall(struct pt_regs *regs)
+{
+        return (regs->psr & PSR_SYSCALL);
+}
+
+static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
+{
+        return (regs->psr &= ~PSR_SYSCALL);
+}
+
+#define user_mode(regs) (!((regs)->psr & PSR_PS))
+#define instruction_pointer(regs) ((regs)->pc)
+#define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP])
+unsigned long profile_pc(struct pt_regs *);
+extern void show_regs(struct pt_regs *);
+#endif
+
+#else /* __ASSEMBLY__ */
+/* For assembly code. */
+#define TRACEREG_SZ       0x50
+#define STACKFRAME_SZ     0x60
+#endif
+
+/*
+ * The asm-offsets.h is a generated file, so we cannot include it.
+ * It may be OK for glibc headers, but it's utterly pointless for C code.
+ * The assembly code using those offsets has to include it explicitly.
+ */
+/* #include <asm/asm-offsets.h> */
+
+/* These are for pt_regs. */
+#define PT_PSR    0x0
+#define PT_PC     0x4
+#define PT_NPC    0x8
+#define PT_Y      0xc
+#define PT_G0     0x10
+#define PT_WIM    PT_G0
+#define PT_G1     0x14
+#define PT_G2     0x18
+#define PT_G3     0x1c
+#define PT_G4     0x20
+#define PT_G5     0x24
+#define PT_G6     0x28
+#define PT_G7     0x2c
+#define PT_I0     0x30
+#define PT_I1     0x34
+#define PT_I2     0x38
+#define PT_I3     0x3c
+#define PT_I4     0x40
+#define PT_I5     0x44
+#define PT_I6     0x48
+#define PT_FP     PT_I6
+#define PT_I7     0x4c
+
+/* Reg_window offsets */
+#define RW_L0     0x00
+#define RW_L1     0x04
+#define RW_L2     0x08
+#define RW_L3     0x0c
+#define RW_L4     0x10
+#define RW_L5     0x14
+#define RW_L6     0x18
+#define RW_L7     0x1c
+#define RW_I0     0x20
+#define RW_I1     0x24
+#define RW_I2     0x28
+#define RW_I3     0x2c
+#define RW_I4     0x30
+#define RW_I5     0x34
+#define RW_I6     0x38
+#define RW_I7     0x3c
+
+/* Stack_frame offsets */
+#define SF_L0     0x00
+#define SF_L1     0x04
+#define SF_L2     0x08
+#define SF_L3     0x0c
+#define SF_L4     0x10
+#define SF_L5     0x14
+#define SF_L6     0x18
+#define SF_L7     0x1c
+#define SF_I0     0x20
+#define SF_I1     0x24
+#define SF_I2     0x28
+#define SF_I3     0x2c
+#define SF_I4     0x30
+#define SF_I5     0x34
+#define SF_FP     0x38
+#define SF_PC     0x3c
+#define SF_RETP   0x40
+#define SF_XARG0  0x44
+#define SF_XARG1  0x48
+#define SF_XARG2  0x4c
+#define SF_XARG3  0x50
+#define SF_XARG4  0x54
+#define SF_XARG5  0x58
+#define SF_XXARG  0x5c
+
+/* Stuff for the ptrace system call */
+#define PTRACE_SPARC_DETACH       11
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13
+#define PTRACE_GETFPREGS          14
+#define PTRACE_SETFPREGS          15
+#define PTRACE_READDATA           16
+#define PTRACE_WRITEDATA          17
+#define PTRACE_READTEXT           18
+#define PTRACE_WRITETEXT          19
+#define PTRACE_GETFPAREGS         20
+#define PTRACE_SETFPAREGS         21
+
+#endif /* !(_SPARC_PTRACE_H) */
diff --git a/arch/sparc/include/asm/ptrace_64.h b/arch/sparc/include/asm/ptrace_64.h
new file mode 100644
index 000000000000..06e4914c13f4
--- /dev/null
+++ b/arch/sparc/include/asm/ptrace_64.h
@@ -0,0 +1,346 @@
+#ifndef _SPARC64_PTRACE_H
+#define _SPARC64_PTRACE_H
+
+#include <asm/pstate.h>
+
+/* This struct defines the way the registers are stored on the
+ * stack during a system call and basically all traps.
+ */
+
+/* This magic value must have the low 9 bits clear,
+ * as that is where we encode the %tt value, see below.
+ */
+#define PT_REGS_MAGIC 0x57ac6c00
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+struct pt_regs {
+        unsigned long u_regs[16]; /* globals and ins */
+        unsigned long tstate;
+        unsigned long tpc;
+        unsigned long tnpc;
+        unsigned int y;
+
+        /* We encode a magic number, PT_REGS_MAGIC, along
+         * with the %tt (trap type) register value at trap
+         * entry time.  The magic number allows us to identify
+         * accurately a trap stack frame in the stack
+         * unwinder, and the %tt value allows us to test
+         * things like "in a system call" etc. for an arbitray
+         * process.
+         *
+         * The PT_REGS_MAGIC is choosen such that it can be
+         * loaded completely using just a sethi instruction.
+         */
+        unsigned int magic;
+};
+
+struct pt_regs32 {
+        unsigned int psr;
+        unsigned int pc;
+        unsigned int npc;
+        unsigned int y;
+        unsigned int u_regs[16]; /* globals and ins */
+};
+
+#define UREG_G0        0
+#define UREG_G1        1
+#define UREG_G2        2
+#define UREG_G3        3
+#define UREG_G4        4
+#define UREG_G5        5
+#define UREG_G6        6
+#define UREG_G7        7
+#define UREG_I0        8
+#define UREG_I1        9
+#define UREG_I2        10
+#define UREG_I3        11
+#define UREG_I4        12
+#define UREG_I5        13
+#define UREG_I6        14
+#define UREG_I7        15
+#define UREG_FP        UREG_I6
+#define UREG_RETPC     UREG_I7
+
+/* A V9 register window */
+struct reg_window {
+        unsigned long locals[8];
+        unsigned long ins[8];
+};
+
+/* A 32-bit register window. */
+struct reg_window32 {
+        unsigned int locals[8];
+        unsigned int ins[8];
+};
+
+/* A V9 Sparc stack frame */
+struct sparc_stackf {
+        unsigned long locals[8];
+        unsigned long ins[6];
+        struct sparc_stackf *fp;
+        unsigned long callers_pc;
+        char *structptr;
+        unsigned long xargs[6];
+        unsigned long xxargs[1];
+};
+
+/* A 32-bit Sparc stack frame */
+struct sparc_stackf32 {
+        unsigned int locals[8];
+        unsigned int ins[6];
+        unsigned int fp;
+        unsigned int callers_pc;
+        unsigned int structptr;
+        unsigned int xargs[6];
+        unsigned int xxargs[1];
+};
+
+struct sparc_trapf {
+        unsigned long locals[8];
+        unsigned long ins[8];
+        unsigned long _unused;
+        struct pt_regs *regs;
+};
+
+#define TRACEREG_SZ     sizeof(struct pt_regs)
+#define STACKFRAME_SZ   sizeof(struct sparc_stackf)
+
+#define TRACEREG32_SZ   sizeof(struct pt_regs32)
+#define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
+
+#ifdef __KERNEL__
+
+static inline int pt_regs_trap_type(struct pt_regs *regs)
+{
+        return regs->magic & 0x1ff;
+}
+
+static inline bool pt_regs_is_syscall(struct pt_regs *regs)
+{
+        return (regs->tstate & TSTATE_SYSCALL);
+}
+
+static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
+{
+        return (regs->tstate &= ~TSTATE_SYSCALL);
+}
+
+struct global_reg_snapshot {
+        unsigned long           tstate;
+        unsigned long           tpc;
+        unsigned long           tnpc;
+        unsigned long           o7;
+        unsigned long           i7;
+        unsigned long           rpc;
+        struct thread_info      *thread;
+        unsigned long           pad1;
+};
+
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+
+#define force_successful_syscall_return()           \
+do {    current_thread_info()->syscall_noerror = 1; \
+} while (0)
+#define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
+#define instruction_pointer(regs) ((regs)->tpc)
+#define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP])
+#define regs_return_value(regs) ((regs)->u_regs[UREG_I0])
+#ifdef CONFIG_SMP
+extern unsigned long profile_pc(struct pt_regs *);
+#else
+#define profile_pc(regs) instruction_pointer(regs)
+#endif
+extern void show_regs(struct pt_regs *);
+#endif
+
+#else /* __ASSEMBLY__ */
+/* For assembly code. */
+#define TRACEREG_SZ             0xa0
+#define STACKFRAME_SZ           0xc0
+
+#define TRACEREG32_SZ           0x50
+#define STACKFRAME32_SZ         0x60
+#endif
+
+#ifdef __KERNEL__
+#define STACK_BIAS              2047
+#endif
+
+/* These are for pt_regs. */
+#define PT_V9_G0     0x00
+#define PT_V9_G1     0x08
+#define PT_V9_G2     0x10
+#define PT_V9_G3     0x18
+#define PT_V9_G4     0x20
+#define PT_V9_G5     0x28
+#define PT_V9_G6     0x30
+#define PT_V9_G7     0x38
+#define PT_V9_I0     0x40
+#define PT_V9_I1     0x48
+#define PT_V9_I2     0x50
+#define PT_V9_I3     0x58
+#define PT_V9_I4     0x60
+#define PT_V9_I5     0x68
+#define PT_V9_I6     0x70
+#define PT_V9_FP     PT_V9_I6
+#define PT_V9_I7     0x78
+#define PT_V9_TSTATE 0x80
+#define PT_V9_TPC    0x88
+#define PT_V9_TNPC   0x90
+#define PT_V9_Y      0x98
+#define PT_V9_MAGIC  0x9c
+#define PT_TSTATE       PT_V9_TSTATE
+#define PT_TPC          PT_V9_TPC
+#define PT_TNPC         PT_V9_TNPC
+
+/* These for pt_regs32. */
+#define PT_PSR    0x0
+#define PT_PC     0x4
+#define PT_NPC    0x8
+#define PT_Y      0xc
+#define PT_G0     0x10
+#define PT_WIM    PT_G0
+#define PT_G1     0x14
+#define PT_G2     0x18
+#define PT_G3     0x1c
+#define PT_G4     0x20
+#define PT_G5     0x24
+#define PT_G6     0x28
+#define PT_G7     0x2c
+#define PT_I0     0x30
+#define PT_I1     0x34
+#define PT_I2     0x38
+#define PT_I3     0x3c
+#define PT_I4     0x40
+#define PT_I5     0x44
+#define PT_I6     0x48
+#define PT_FP     PT_I6
+#define PT_I7     0x4c
+
+/* Reg_window offsets */
+#define RW_V9_L0     0x00
+#define RW_V9_L1     0x08
+#define RW_V9_L2     0x10
+#define RW_V9_L3     0x18
+#define RW_V9_L4     0x20
+#define RW_V9_L5     0x28
+#define RW_V9_L6     0x30
+#define RW_V9_L7     0x38
+#define RW_V9_I0     0x40
+#define RW_V9_I1     0x48
+#define RW_V9_I2     0x50
+#define RW_V9_I3     0x58
+#define RW_V9_I4     0x60
+#define RW_V9_I5     0x68
+#define RW_V9_I6     0x70
+#define RW_V9_I7     0x78
+
+#define RW_L0     0x00
+#define RW_L1     0x04
+#define RW_L2     0x08
+#define RW_L3     0x0c
+#define RW_L4     0x10
+#define RW_L5     0x14
+#define RW_L6     0x18
+#define RW_L7     0x1c
+#define RW_I0     0x20
+#define RW_I1     0x24
+#define RW_I2     0x28
+#define RW_I3     0x2c
+#define RW_I4     0x30
+#define RW_I5     0x34
+#define RW_I6     0x38
+#define RW_I7     0x3c
+
+/* Stack_frame offsets */
+#define SF_V9_L0     0x00
+#define SF_V9_L1     0x08
+#define SF_V9_L2     0x10
+#define SF_V9_L3     0x18
+#define SF_V9_L4     0x20
+#define SF_V9_L5     0x28
+#define SF_V9_L6     0x30
+#define SF_V9_L7     0x38
+#define SF_V9_I0     0x40
+#define SF_V9_I1     0x48
+#define SF_V9_I2     0x50
+#define SF_V9_I3     0x58
+#define SF_V9_I4     0x60
+#define SF_V9_I5     0x68
+#define SF_V9_FP     0x70
+#define SF_V9_PC     0x78
+#define SF_V9_RETP   0x80
+#define SF_V9_XARG0  0x88
+#define SF_V9_XARG1  0x90
+#define SF_V9_XARG2  0x98
+#define SF_V9_XARG3  0xa0
+#define SF_V9_XARG4  0xa8
+#define SF_V9_XARG5  0xb0
+#define SF_V9_XXARG  0xb8
+
+#define SF_L0     0x00
+#define SF_L1     0x04
+#define SF_L2     0x08
+#define SF_L3     0x0c
+#define SF_L4     0x10
+#define SF_L5     0x14
+#define SF_L6     0x18
+#define SF_L7     0x1c
+#define SF_I0     0x20
+#define SF_I1     0x24
+#define SF_I2     0x28
+#define SF_I3     0x2c
+#define SF_I4     0x30
+#define SF_I5     0x34
+#define SF_FP     0x38
+#define SF_PC     0x3c
+#define SF_RETP   0x40
+#define SF_XARG0  0x44
+#define SF_XARG1  0x48
+#define SF_XARG2  0x4c
+#define SF_XARG3  0x50
+#define SF_XARG4  0x54
+#define SF_XARG5  0x58
+#define SF_XXARG  0x5c
+
+#ifdef __KERNEL__
+
+/* global_reg_snapshot offsets */
+#define GR_SNAP_TSTATE  0x00
+#define GR_SNAP_TPC     0x08
+#define GR_SNAP_TNPC    0x10
+#define GR_SNAP_O7      0x18
+#define GR_SNAP_I7      0x20
+#define GR_SNAP_RPC     0x28
+#define GR_SNAP_THREAD  0x30
+#define GR_SNAP_PAD1    0x38
+
+#endif  /*  __KERNEL__  */
+
+/* Stuff for the ptrace system call */
+#define PTRACE_SPARC_DETACH       11
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13
+#define PTRACE_GETFPREGS          14
+#define PTRACE_SETFPREGS          15
+#define PTRACE_READDATA           16
+#define PTRACE_WRITEDATA          17
+#define PTRACE_READTEXT           18
+#define PTRACE_WRITETEXT          19
+#define PTRACE_GETFPAREGS         20
+#define PTRACE_SETFPAREGS         21
+
+/* There are for debugging 64-bit processes, either from a 32 or 64 bit
+ * parent.  Thus their complements are for debugging 32-bit processes only.
+ */
+
+#define PTRACE_GETREGS64          22
+#define PTRACE_SETREGS64          23
+/* PTRACE_SYSCALL is 24 */
+#define PTRACE_GETFPREGS64        25
+#define PTRACE_SETFPREGS64        26
+
+#endif /* !(_SPARC64_PTRACE_H) */
diff --git a/arch/sparc/include/asm/reboot.h b/arch/sparc/include/asm/reboot.h
new file mode 100644
index 000000000000..3f3f43f5be5e
--- /dev/null
+++ b/arch/sparc/include/asm/reboot.h
@@ -0,0 +1,6 @@
+#ifndef _SPARC64_REBOOT_H
+#define _SPARC64_REBOOT_H
+
+extern void machine_alt_power_off(void);
+
+#endif /* _SPARC64_REBOOT_H */
diff --git a/arch/sparc/include/asm/reg.h b/arch/sparc/include/asm/reg.h
new file mode 100644
index 000000000000..0c16e19cae4d
--- /dev/null
+++ b/arch/sparc/include/asm/reg.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_REG_H
+#define ___ASM_SPARC_REG_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/reg_64.h>
+#else
+#include <asm/reg_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/reg_32.h b/arch/sparc/include/asm/reg_32.h
new file mode 100644
index 000000000000..1efb056fb3d1
--- /dev/null
+++ b/arch/sparc/include/asm/reg_32.h
@@ -0,0 +1,79 @@
+/*
+ * linux/include/asm/reg.h
+ * Layout of the registers as expected by gdb on the Sparc
+ * we should replace the user.h definitions with those in
+ * this file, we don't even use the other
+ * -miguel
+ *
+ * The names of the structures, constants and aliases in this file
+ * have the same names as the sunos ones, some programs rely on these
+ * names (gdb for example).
+ *
+ */
+
+#ifndef __SPARC_REG_H
+#define __SPARC_REG_H
+
+struct regs {
+        int     r_psr;
+#define r_ps r_psr
+        int     r_pc;
+        int     r_npc;
+        int     r_y;
+        int     r_g1;
+        int     r_g2;
+        int     r_g3;
+        int     r_g4;
+        int     r_g5;
+        int     r_g6;
+        int     r_g7;
+        int     r_o0;
+        int     r_o1;
+        int     r_o2;
+        int     r_o3;
+        int     r_o4;
+        int     r_o5;
+        int     r_o6;
+        int     r_o7;
+};
+
+struct fpq {
+        unsigned long *addr;
+        unsigned long instr;
+};
+
+struct  fq {
+        union {
+                double  whole;
+                struct  fpq fpq;
+        } FQu;
+};
+
+#define FPU_REGS_TYPE unsigned int
+#define FPU_FSR_TYPE unsigned
+
+struct fp_status {
+        union {
+                FPU_REGS_TYPE Fpu_regs[32];
+                double  Fpu_dregs[16];
+        } fpu_fr;
+        FPU_FSR_TYPE Fpu_fsr;
+        unsigned Fpu_flags;
+        unsigned Fpu_extra;
+        unsigned Fpu_qcnt;
+        struct fq Fpu_q[16];
+};
+
+#define fpu_regs  f_fpstatus.fpu_fr.Fpu_regs
+#define fpu_dregs f_fpstatus.fpu_fr.Fpu_dregs
+#define fpu_fsr   f_fpstatus.Fpu_fsr
+#define fpu_flags f_fpstatus.Fpu_flags
+#define fpu_extra f_fpstatus.Fpu_extra
+#define fpu_q     f_fpstatus.Fpu_q
+#define fpu_qcnt  f_fpstatus.Fpu_qcnt
+
+struct fpu {
+        struct fp_status f_fpstatus;
+};
+
+#endif /* __SPARC_REG_H */
diff --git a/arch/sparc/include/asm/reg_64.h b/arch/sparc/include/asm/reg_64.h
new file mode 100644
index 000000000000..6f277d7c7d88
--- /dev/null
+++ b/arch/sparc/include/asm/reg_64.h
@@ -0,0 +1,56 @@
+/*
+ * linux/asm/reg.h
+ * Layout of the registers as expected by gdb on the Sparc
+ * we should replace the user.h definitions with those in
+ * this file, we don't even use the other
+ * -miguel
+ *
+ * The names of the structures, constants and aliases in this file
+ * have the same names as the sunos ones, some programs rely on these
+ * names (gdb for example).
+ *
+ */
+
+#ifndef __SPARC64_REG_H
+#define __SPARC64_REG_H
+
+struct regs {
+        unsigned long r_g1;
+        unsigned long r_g2;
+        unsigned long r_g3;
+        unsigned long r_g4;
+        unsigned long r_g5;
+        unsigned long r_g6;
+        unsigned long r_g7;
+        unsigned long r_o0;
+        unsigned long r_o1;
+        unsigned long r_o2;
+        unsigned long r_o3;
+        unsigned long r_o4;
+        unsigned long r_o5;
+        unsigned long r_o6;
+        unsigned long r_o7;
+        unsigned long __pad;
+        unsigned long r_tstate;
+        unsigned long r_tpc;
+        unsigned long r_tnpc;
+        unsigned int  r_y;
+        unsigned int  r_fprs;
+};
+
+#define FPU_REGS_TYPE unsigned int
+#define FPU_FSR_TYPE unsigned long
+
+struct fp_status {
+        unsigned long fpu_fr[32];
+        unsigned long Fpu_fsr;
+};
+
+struct fpu {
+        struct fp_status f_fpstatus;
+};
+
+#define fpu_regs  f_fpstatus.fpu_fr
+#define fpu_fsr   f_fpstatus.Fpu_fsr
+
+#endif /* __SPARC64_REG_H */
diff --git a/arch/sparc/include/asm/resource.h b/arch/sparc/include/asm/resource.h
new file mode 100644
index 000000000000..fe163cafb4c7
--- /dev/null
+++ b/arch/sparc/include/asm/resource.h
@@ -0,0 +1,30 @@
+/*
+ * resource.h: Resource definitions.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_RESOURCE_H
+#define _SPARC_RESOURCE_H
+
+/*
+ * These two resource limit IDs have a Sparc/Linux-specific ordering,
+ * the rest comes from the generic header:
+ */
+#define RLIMIT_NOFILE           6       /* max number of open files */
+#define RLIMIT_NPROC            7       /* max number of processes */
+
+#if defined(__sparc__) && defined(__arch64__)
+/* Use generic version */
+#else
+/*
+ * SuS says limits have to be unsigned.
+ * We make this unsigned, but keep the
+ * old value for compatibility:
+ */
+#define RLIM_INFINITY           0x7fffffff
+#endif
+
+#include <asm-generic/resource.h>
+
+#endif /* !(_SPARC_RESOURCE_H) */
diff --git a/arch/sparc/include/asm/ross.h b/arch/sparc/include/asm/ross.h
new file mode 100644
index 000000000000..ecb6e81786a6
--- /dev/null
+++ b/arch/sparc/include/asm/ross.h
@@ -0,0 +1,191 @@
+/*
+ * ross.h: Ross module specific definitions and defines.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_ROSS_H
+#define _SPARC_ROSS_H
+
+#include <asm/asi.h>
+#include <asm/page.h>
+
+/* Ross made Hypersparcs have a %psr 'impl' field of '0001'.  The 'vers'
+ * field has '1111'.
+ */
+
+/* The MMU control register fields on the HyperSparc.
+ *
+ * -----------------------------------------------------------------
+ * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
+ * -----------------------------------------------------------------
+ *  31    24 23-22 21  20  19 18-15 14 13 12 11 10  9   8 7-2  1  0
+ *
+ * Phew, lots of fields there ;-)
+ *
+ * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
+ * SE: Snoop Enable, turns on bus snooping for cache activity if one.
+ * WBE: Write Buffer Enable, one turns it on.
+ * MID: The ModuleID of the chip for MBus transactions.
+ * BM: Boot-Mode. One indicates the MMU is in boot mode.
+ * C: Indicates whether accesses are cachable while the MMU is
+ *    disabled.
+ * CS: Cache Size -- 0 = 128k, 1 = 256k
+ * MR: Memory Reflection, one indicates that the memory bus connected
+ *     to the MBus supports memory reflection.
+ * CM: Cache Mode -- 0 = write-through, 1 = copy-back
+ * CE: Cache Enable -- 0 = no caching, 1 = cache is on
+ * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
+ *                 1 = faults from supervisor mode do not generate traps
+ * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
+ */
+
+#define HYPERSPARC_CWENABLE   0x00200000
+#define HYPERSPARC_SBENABLE   0x00100000
+#define HYPERSPARC_WBENABLE   0x00080000
+#define HYPERSPARC_MIDMASK    0x00078000
+#define HYPERSPARC_BMODE      0x00004000
+#define HYPERSPARC_ACENABLE   0x00002000
+#define HYPERSPARC_CSIZE      0x00001000
+#define HYPERSPARC_MRFLCT     0x00000800
+#define HYPERSPARC_CMODE      0x00000400
+#define HYPERSPARC_CENABLE    0x00000100
+#define HYPERSPARC_NFAULT     0x00000002
+#define HYPERSPARC_MENABLE    0x00000001
+
+
+/* The ICCR instruction cache register on the HyperSparc.
+ *
+ * -----------------------------------------------
+ * |                                 | FTD | ICE |
+ * -----------------------------------------------
+ *  31                                  1     0
+ *
+ * This register is accessed using the V8 'wrasr' and 'rdasr'
+ * opcodes, since not all assemblers understand them and those
+ * that do use different semantics I will just hard code the
+ * instruction with a '.word' statement.
+ *
+ * FTD:  If set to one flush instructions executed during an
+ *       instruction cache hit occurs, the corresponding line
+ *       for said cache-hit is invalidated.  If FTD is zero,
+ *       an unimplemented 'flush' trap will occur when any
+ *       flush is executed by the processor.
+ *
+ * ICE:  If set to one, the instruction cache is enabled.  If
+ *       zero, the cache will not be used for instruction fetches.
+ *
+ * All other bits are read as zeros, and writes to them have no
+ * effect.
+ *
+ * Wheee, not many assemblers understand the %iccr register nor
+ * the generic asr r/w instructions.
+ *
+ *  1000 0011 0100 0111 1100 0000 0000 0000   ! rd %iccr, %g1
+ *
+ * 0x  8    3    4    7    c    0    0    0   ! 0x8347c000
+ *
+ *  1011 1111 1000 0000 0110 0000 0000 0000   ! wr %g1, 0x0, %iccr
+ *
+ * 0x  b    f    8    0    6    0    0    0   ! 0xbf806000
+ *
+ */
+
+#define HYPERSPARC_ICCR_FTD     0x00000002
+#define HYPERSPARC_ICCR_ICE     0x00000001
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned int get_ross_icr(void)
+{
+        unsigned int icreg;
+
+        __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
+                             "mov %%g1, %0\n\t"
+                             : "=r" (icreg)
+                             : /* no inputs */
+                             : "g1", "memory");
+
+        return icreg;
+}
+
+static inline void put_ross_icr(unsigned int icreg)
+{
+        __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
+                             ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
+                             "nop\n\t"
+                             "nop\n\t"
+                             "nop\n\t"
+                             : /* no outputs */
+                             : "r" (icreg)
+                             : "g1", "memory");
+
+        return;
+}
+
+/* HyperSparc specific cache flushing. */
+
+/* This is for the on-chip instruction cache. */
+static inline void hyper_flush_whole_icache(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+                             : /* no outputs */
+                             : "i" (ASI_M_FLUSH_IWHOLE)
+                             : "memory");
+        return;
+}
+
+extern int vac_cache_size;
+extern int vac_line_size;
+
+static inline void hyper_clear_all_tags(void)
+{
+        unsigned long addr;
+
+        for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
+                __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                                     : /* no outputs */
+                                     : "r" (addr), "i" (ASI_M_DATAC_TAG)
+                                     : "memory");
+}
+
+static inline void hyper_flush_unconditional_combined(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
+                __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                                     : /* no outputs */
+                                     : "r" (addr), "i" (ASI_M_FLUSH_CTX)
+                                     : "memory");
+}
+
+static inline void hyper_flush_cache_user(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
+                __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                                     : /* no outputs */
+                                     : "r" (addr), "i" (ASI_M_FLUSH_USER)
+                                     : "memory");
+}
+
+static inline void hyper_flush_cache_page(unsigned long page)
+{
+        unsigned long end;
+
+        page &= PAGE_MASK;
+        end = page + PAGE_SIZE;
+        while (page < end) {
+                __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                                     : /* no outputs */
+                                     : "r" (page), "i" (ASI_M_FLUSH_PAGE)
+                                     : "memory");
+                page += vac_line_size;
+        }
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_ROSS_H) */
diff --git a/arch/sparc/include/asm/rtc.h b/arch/sparc/include/asm/rtc.h
new file mode 100644
index 000000000000..f9ecb1fe2ecd
--- /dev/null
+++ b/arch/sparc/include/asm/rtc.h
@@ -0,0 +1,26 @@
+/*
+ * rtc.h: Definitions for access to the Mostek real time clock
+ *
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ */
+
+#ifndef _RTC_H
+#define _RTC_H
+
+#include <linux/ioctl.h>
+
+struct rtc_time
+{
+        int     sec;    /* Seconds (0-59) */
+        int     min;    /* Minutes (0-59) */
+        int     hour;   /* Hour (0-23) */
+        int     dow;    /* Day of the week (1-7) */
+        int     dom;    /* Day of the month (1-31) */
+        int     month;  /* Month of year (1-12) */
+        int     year;   /* Year (0-99) */
+};
+
+#define RTCGET _IOR('p', 20, struct rtc_time)
+#define RTCSET _IOW('p', 21, struct rtc_time)
+
+#endif
diff --git a/arch/sparc/include/asm/rwsem-const.h b/arch/sparc/include/asm/rwsem-const.h
new file mode 100644
index 000000000000..a303c9d64d84
--- /dev/null
+++ b/arch/sparc/include/asm/rwsem-const.h
@@ -0,0 +1,12 @@
+/* rwsem-const.h: RW semaphore counter constants.  */
+#ifndef _SPARC64_RWSEM_CONST_H
+#define _SPARC64_RWSEM_CONST_H
+
+#define RWSEM_UNLOCKED_VALUE            0x00000000
+#define RWSEM_ACTIVE_BIAS               0x00000001
+#define RWSEM_ACTIVE_MASK               0x0000ffff
+#define RWSEM_WAITING_BIAS              0xffff0000
+#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+
+#endif /* _SPARC64_RWSEM_CONST_H */
diff --git a/arch/sparc/include/asm/rwsem.h b/arch/sparc/include/asm/rwsem.h
new file mode 100644
index 000000000000..1dc129ac2feb
--- /dev/null
+++ b/arch/sparc/include/asm/rwsem.h
@@ -0,0 +1,84 @@
+/*
+ * rwsem.h: R/W semaphores implemented using CAS
+ *
+ * Written by David S. Miller (davem@redhat.com), 2001.
+ * Derived from asm-i386/rwsem.h
+ */
+#ifndef _SPARC64_RWSEM_H
+#define _SPARC64_RWSEM_H
+
+#ifndef _LINUX_RWSEM_H
+#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
+#endif
+
+#ifdef __KERNEL__
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <asm/rwsem-const.h>
+
+struct rwsem_waiter;
+
+struct rw_semaphore {
+        signed int count;
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
+  __RWSEM_DEP_MAP_INIT(name) }
+
+#define DECLARE_RWSEM(name) \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                                         \
+do {                                                            \
+        static struct lock_class_key __key;                     \
+                                                                \
+        __init_rwsem((sem), #sem, &__key);                      \
+} while (0)
+
+extern void __down_read(struct rw_semaphore *sem);
+extern int __down_read_trylock(struct rw_semaphore *sem);
+extern void __down_write(struct rw_semaphore *sem);
+extern int __down_write_trylock(struct rw_semaphore *sem);
+extern void __up_read(struct rw_semaphore *sem);
+extern void __up_write(struct rw_semaphore *sem);
+extern void __downgrade_write(struct rw_semaphore *sem);
+
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
+{
+        __down_write(sem);
+}
+
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+{
+        return atomic_add_return(delta, (atomic_t *)(&sem->count));
+}
+
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+{
+        atomic_add(delta, (atomic_t *)(&sem->count));
+}
+
+static inline int rwsem_is_locked(struct rw_semaphore *sem)
+{
+        return (sem->count != 0);
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _SPARC64_RWSEM_H */
diff --git a/arch/sparc/include/asm/sbi.h b/arch/sparc/include/asm/sbi.h
new file mode 100644
index 000000000000..5eb7f1965d33
--- /dev/null
+++ b/arch/sparc/include/asm/sbi.h
@@ -0,0 +1,115 @@
+/*
+ * sbi.h:  SBI (Sbus Interface on sun4d) definitions
+ *
+ * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
+ */
+
+#ifndef _SPARC_SBI_H
+#define _SPARC_SBI_H
+
+#include <asm/obio.h>
+
+/* SBI */
+struct sbi_regs {
+/* 0x0000 */    u32             cid;            /* Component ID */
+/* 0x0004 */    u32             ctl;            /* Control */
+/* 0x0008 */    u32             status;         /* Status */
+                u32             _unused1;
+                
+/* 0x0010 */    u32             cfg0;           /* Slot0 config reg */
+/* 0x0014 */    u32             cfg1;           /* Slot1 config reg */
+/* 0x0018 */    u32             cfg2;           /* Slot2 config reg */
+/* 0x001c */    u32             cfg3;           /* Slot3 config reg */
+
+/* 0x0020 */    u32             stb0;           /* Streaming buf control for slot 0 */
+/* 0x0024 */    u32             stb1;           /* Streaming buf control for slot 1 */
+/* 0x0028 */    u32             stb2;           /* Streaming buf control for slot 2 */
+/* 0x002c */    u32             stb3;           /* Streaming buf control for slot 3 */
+
+/* 0x0030 */    u32             intr_state;     /* Interrupt state */
+/* 0x0034 */    u32             intr_tid;       /* Interrupt target ID */
+/* 0x0038 */    u32             intr_diag;      /* Interrupt diagnostics */
+};
+
+#define SBI_CID                 0x02800000
+#define SBI_CTL                 0x02800004
+#define SBI_STATUS              0x02800008
+#define SBI_CFG0                0x02800010
+#define SBI_CFG1                0x02800014
+#define SBI_CFG2                0x02800018
+#define SBI_CFG3                0x0280001c
+#define SBI_STB0                0x02800020
+#define SBI_STB1                0x02800024
+#define SBI_STB2                0x02800028
+#define SBI_STB3                0x0280002c
+#define SBI_INTR_STATE          0x02800030
+#define SBI_INTR_TID            0x02800034
+#define SBI_INTR_DIAG           0x02800038
+
+/* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
+#define SBI_CFG_BURST_MASK      0x0000001e
+
+/* How to make devid from sbi no */
+#define SBI2DEVID(sbino) ((sbino<<4)|2)
+
+/* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
+ *
+ *                 +-------+-------+-------+-------+-------+-------+-------+-------+
+ *  SBUS IRQ LEVEL |   7   |   6   |   5   |   4   |   3   |   2   |   1   |       |
+ *                 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
+ *  SLOT #         |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|  ved  |
+ *                 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
+ *  Bits           31      27      23      19      15      11      7       3      0
+ */
+
+
+#ifndef __ASSEMBLY__
+
+static inline int acquire_sbi(int devid, int mask)
+{
+        __asm__ __volatile__ ("swapa [%2] %3, %0" :
+                              "=r" (mask) :
+                              "0" (mask),
+                              "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
+                              "i" (ASI_M_CTL));
+        return mask;
+}
+
+static inline void release_sbi(int devid, int mask)
+{
+        __asm__ __volatile__ ("sta %0, [%1] %2" : :
+                              "r" (mask),
+                              "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
+                              "i" (ASI_M_CTL));
+}
+
+static inline void set_sbi_tid(int devid, int targetid)
+{
+        __asm__ __volatile__ ("sta %0, [%1] %2" : :
+                              "r" (targetid),
+                              "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
+                              "i" (ASI_M_CTL));
+}
+
+static inline int get_sbi_ctl(int devid, int cfgno)
+{
+        int cfg;
+        
+        __asm__ __volatile__ ("lda [%1] %2, %0" :
+                              "=r" (cfg) :
+                              "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
+                              "i" (ASI_M_CTL));
+        return cfg;
+}
+
+static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
+{
+        __asm__ __volatile__ ("sta %0, [%1] %2" : :
+                              "r" (cfg),
+                              "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
+                              "i" (ASI_M_CTL));
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_SBI_H) */
diff --git a/arch/sparc/include/asm/sbus.h b/arch/sparc/include/asm/sbus.h
new file mode 100644
index 000000000000..f82481ab44db
--- /dev/null
+++ b/arch/sparc/include/asm/sbus.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SBUS_H
+#define ___ASM_SPARC_SBUS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sbus_64.h>
+#else
+#include <asm/sbus_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/sbus_32.h b/arch/sparc/include/asm/sbus_32.h
new file mode 100644
index 000000000000..77b5d3aadc99
--- /dev/null
+++ b/arch/sparc/include/asm/sbus_32.h
@@ -0,0 +1,153 @@
+/*
+ * sbus.h:  Defines for the Sun SBus.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SBUS_H
+#define _SPARC_SBUS_H
+
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+#include <asm/scatterlist.h>
+
+/* We scan which devices are on the SBus using the PROM node device
+ * tree.  SBus devices are described in two different ways.  You can
+ * either get an absolute address at which to access the device, or
+ * you can get a SBus 'slot' number and an offset within that slot.
+ */
+
+/* The base address at which to calculate device OBIO addresses. */
+#define SUN_SBUS_BVADDR        0xf8000000
+#define SBUS_OFF_MASK          0x01ffffff
+
+/* These routines are used to calculate device address from slot
+ * numbers + offsets, and vice versa.
+ */
+
+static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
+{
+  return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<25)+(offset));
+}
+
+static inline int sbus_dev_slot(unsigned long dev_addr)
+{
+  return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>25);
+}
+
+struct sbus_bus;
+
+/* Linux SBUS device tables */
+struct sbus_dev {
+        struct of_device        ofdev;
+        struct sbus_bus         *bus;
+        struct sbus_dev         *next;
+        struct sbus_dev         *child;
+        struct sbus_dev         *parent;
+        int prom_node;
+        char prom_name[64];
+        int slot;
+
+        struct resource resource[PROMREG_MAX];
+
+        struct linux_prom_registers reg_addrs[PROMREG_MAX];
+        int num_registers;
+
+        struct linux_prom_ranges device_ranges[PROMREG_MAX];
+        int num_device_ranges;
+
+        unsigned int irqs[4];
+        int num_irqs;
+};
+#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
+
+/* This struct describes the SBus(s) found on this machine. */
+struct sbus_bus {
+        struct of_device        ofdev;
+        struct sbus_dev         *devices;       /* Link to devices on this SBus */
+        struct sbus_bus         *next;          /* next SBus, if more than one SBus */
+        int                     prom_node;      /* PROM device tree node for this SBus */
+        char                    prom_name[64];  /* Usually "sbus" or "sbi" */
+        int                     clock_freq;
+
+        struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
+        int num_sbus_ranges;
+
+        int devid;
+        int board;
+};
+#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
+
+extern struct sbus_bus *sbus_root;
+
+static inline int
+sbus_is_slave(struct sbus_dev *dev)
+{
+        /* XXX Have to write this for sun4c's */
+        return 0;
+}
+
+/* Device probing routines could find these handy */
+#define for_each_sbus(bus) \
+        for((bus) = sbus_root; (bus); (bus)=(bus)->next)
+
+#define for_each_sbusdev(device, bus) \
+        for((device) = (bus)->devices; (device); (device)=(device)->next)
+
+#define for_all_sbusdev(device, bus) \
+        for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
+                for ((device) = (bus)->devices; (device); (device) = (device)->next)
+
+/* Driver DVMA interfaces. */
+#define sbus_can_dma_64bit(sdev)        (0) /* actually, sparc_cpu_model==sun4d */
+#define sbus_can_burst64(sdev)          (0) /* actually, sparc_cpu_model==sun4d */
+extern void sbus_set_sbus64(struct sbus_dev *, int);
+extern void sbus_fill_device_irq(struct sbus_dev *);
+
+/* These yield IOMMU mappings in consistent mode. */
+extern void *sbus_alloc_consistent(struct sbus_dev *, long, u32 *dma_addrp);
+extern void sbus_free_consistent(struct sbus_dev *, long, void *, u32);
+void prom_adjust_ranges(struct linux_prom_ranges *, int,
+                        struct linux_prom_ranges *, int);
+
+#define SBUS_DMA_BIDIRECTIONAL  DMA_BIDIRECTIONAL
+#define SBUS_DMA_TODEVICE       DMA_TO_DEVICE
+#define SBUS_DMA_FROMDEVICE     DMA_FROM_DEVICE
+#define SBUS_DMA_NONE           DMA_NONE
+
+/* All the rest use streaming mode mappings. */
+extern dma_addr_t sbus_map_single(struct sbus_dev *, void *, size_t, int);
+extern void sbus_unmap_single(struct sbus_dev *, dma_addr_t, size_t, int);
+extern int sbus_map_sg(struct sbus_dev *, struct scatterlist *, int, int);
+extern void sbus_unmap_sg(struct sbus_dev *, struct scatterlist *, int, int);
+
+/* Finally, allow explicit synchronization of streamable mappings. */
+extern void sbus_dma_sync_single_for_cpu(struct sbus_dev *, dma_addr_t, size_t, int);
+#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
+extern void sbus_dma_sync_single_for_device(struct sbus_dev *, dma_addr_t, size_t, int);
+extern void sbus_dma_sync_sg_for_cpu(struct sbus_dev *, struct scatterlist *, int, int);
+#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
+extern void sbus_dma_sync_sg_for_device(struct sbus_dev *, struct scatterlist *, int, int);
+
+/* Eric Brower (ebrower@usa.net)
+ * Translate SBus interrupt levels to ino values--
+ * this is used when converting sbus "interrupts" OBP
+ * node values to "intr" node values, and is platform
+ * dependent.  If only we could call OBP with
+ * "sbus-intr>cpu (sbint -- ino)" from kernel...
+ * See .../drivers/sbus/sbus.c for details.
+ */
+BTFIXUPDEF_CALL(unsigned int, sbint_to_irq, struct sbus_dev *sdev, unsigned int)
+#define sbint_to_irq(sdev, sbint) BTFIXUP_CALL(sbint_to_irq)(sdev, sbint)
+
+extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
+extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
+extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
+extern int sbus_arch_preinit(void);
+extern void sbus_arch_postinit(void);
+
+#endif /* !(_SPARC_SBUS_H) */
diff --git a/arch/sparc/include/asm/sbus_64.h b/arch/sparc/include/asm/sbus_64.h
new file mode 100644
index 000000000000..0e16b6dd7e96
--- /dev/null
+++ b/arch/sparc/include/asm/sbus_64.h
@@ -0,0 +1,190 @@
+/* sbus.h: Defines for the Sun SBus.
+ *
+ * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_SBUS_H
+#define _SPARC64_SBUS_H
+
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+
+#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
+#include <asm/iommu.h>
+#include <asm/scatterlist.h>
+
+/* We scan which devices are on the SBus using the PROM node device
+ * tree.  SBus devices are described in two different ways.  You can
+ * either get an absolute address at which to access the device, or
+ * you can get a SBus 'slot' number and an offset within that slot.
+ */
+
+/* The base address at which to calculate device OBIO addresses. */
+#define SUN_SBUS_BVADDR        0x00000000
+#define SBUS_OFF_MASK          0x0fffffff
+
+/* These routines are used to calculate device address from slot
+ * numbers + offsets, and vice versa.
+ */
+
+static inline unsigned long sbus_devaddr(int slotnum, unsigned long offset)
+{
+  return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset));
+}
+
+static inline int sbus_dev_slot(unsigned long dev_addr)
+{
+  return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28);
+}
+
+struct sbus_bus;
+
+/* Linux SBUS device tables */
+struct sbus_dev {
+        struct of_device        ofdev;
+        struct sbus_bus         *bus;
+        struct sbus_dev         *next;
+        struct sbus_dev         *child;
+        struct sbus_dev         *parent;
+        int prom_node;
+        char prom_name[64];
+        int slot;
+
+        struct resource resource[PROMREG_MAX];
+
+        struct linux_prom_registers reg_addrs[PROMREG_MAX];
+        int num_registers;
+
+        struct linux_prom_ranges device_ranges[PROMREG_MAX];
+        int num_device_ranges;
+
+        unsigned int irqs[4];
+        int num_irqs;
+};
+#define to_sbus_device(d) container_of(d, struct sbus_dev, ofdev.dev)
+
+/* This struct describes the SBus(s) found on this machine. */
+struct sbus_bus {
+        struct of_device        ofdev;
+        struct sbus_dev         *devices;       /* Tree of SBUS devices */
+        struct sbus_bus         *next;          /* Next SBUS in system  */
+        int                     prom_node;      /* OBP node of SBUS     */
+        char                    prom_name[64];  /* Usually "sbus" or "sbi" */
+        int                     clock_freq;
+
+        struct linux_prom_ranges sbus_ranges[PROMREG_MAX];
+        int num_sbus_ranges;
+
+        int portid;
+};
+#define to_sbus(d) container_of(d, struct sbus_bus, ofdev.dev)
+
+extern struct sbus_bus *sbus_root;
+
+/* Device probing routines could find these handy */
+#define for_each_sbus(bus) \
+        for((bus) = sbus_root; (bus); (bus)=(bus)->next)
+
+#define for_each_sbusdev(device, bus) \
+        for((device) = (bus)->devices; (device); (device)=(device)->next)
+
+#define for_all_sbusdev(device, bus) \
+        for ((bus) = sbus_root; (bus); (bus) = (bus)->next) \
+                for ((device) = (bus)->devices; (device); (device) = (device)->next)
+
+/* Driver DVMA interfaces. */
+#define sbus_can_dma_64bit(sdev)        (1)
+#define sbus_can_burst64(sdev)          (1)
+extern void sbus_set_sbus64(struct sbus_dev *, int);
+extern void sbus_fill_device_irq(struct sbus_dev *);
+
+static inline void *sbus_alloc_consistent(struct sbus_dev *sdev , size_t size,
+                                          dma_addr_t *dma_handle)
+{
+        return dma_alloc_coherent(&sdev->ofdev.dev, size,
+                                  dma_handle, GFP_ATOMIC);
+}
+
+static inline void sbus_free_consistent(struct sbus_dev *sdev, size_t size,
+                                        void *vaddr, dma_addr_t dma_handle)
+{
+        return dma_free_coherent(&sdev->ofdev.dev, size, vaddr, dma_handle);
+}
+
+#define SBUS_DMA_BIDIRECTIONAL  DMA_BIDIRECTIONAL
+#define SBUS_DMA_TODEVICE       DMA_TO_DEVICE
+#define SBUS_DMA_FROMDEVICE     DMA_FROM_DEVICE
+#define SBUS_DMA_NONE           DMA_NONE
+
+/* All the rest use streaming mode mappings. */
+static inline dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr,
+                                         size_t size, int direction)
+{
+        return dma_map_single(&sdev->ofdev.dev, ptr, size,
+                              (enum dma_data_direction) direction);
+}
+
+static inline void sbus_unmap_single(struct sbus_dev *sdev,
+                                     dma_addr_t dma_addr, size_t size,
+                                     int direction)
+{
+        dma_unmap_single(&sdev->ofdev.dev, dma_addr, size,
+                         (enum dma_data_direction) direction);
+}
+
+static inline int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg,
+                              int nents, int direction)
+{
+        return dma_map_sg(&sdev->ofdev.dev, sg, nents,
+                          (enum dma_data_direction) direction);
+}
+
+static inline void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg,
+                                 int nents, int direction)
+{
+        dma_unmap_sg(&sdev->ofdev.dev, sg, nents,
+                     (enum dma_data_direction) direction);
+}
+
+/* Finally, allow explicit synchronization of streamable mappings. */
+static inline void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev,
+                                                dma_addr_t dma_handle,
+                                                size_t size, int direction)
+{
+        dma_sync_single_for_cpu(&sdev->ofdev.dev, dma_handle, size,
+                                (enum dma_data_direction) direction);
+}
+#define sbus_dma_sync_single sbus_dma_sync_single_for_cpu
+
+static inline void sbus_dma_sync_single_for_device(struct sbus_dev *sdev,
+                                                   dma_addr_t dma_handle,
+                                                   size_t size, int direction)
+{
+        /* No flushing needed to sync cpu writes to the device.  */
+}
+
+static inline void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev,
+                                            struct scatterlist *sg,
+                                            int nents, int direction)
+{
+        dma_sync_sg_for_cpu(&sdev->ofdev.dev, sg, nents,
+                            (enum dma_data_direction) direction);
+}
+#define sbus_dma_sync_sg sbus_dma_sync_sg_for_cpu
+
+static inline void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev,
+                                               struct scatterlist *sg,
+                                               int nents, int direction)
+{
+        /* No flushing needed to sync cpu writes to the device.  */
+}
+
+extern void sbus_arch_bus_ranges_init(struct device_node *, struct sbus_bus *);
+extern void sbus_setup_iommu(struct sbus_bus *, struct device_node *);
+extern void sbus_setup_arch_props(struct sbus_bus *, struct device_node *);
+extern int sbus_arch_preinit(void);
+extern void sbus_arch_postinit(void);
+
+#endif /* !(_SPARC64_SBUS_H) */
diff --git a/arch/sparc/include/asm/scatterlist.h b/arch/sparc/include/asm/scatterlist.h
new file mode 100644
index 000000000000..ec21a4517641
--- /dev/null
+++ b/arch/sparc/include/asm/scatterlist.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SCATTERLIST_H
+#define ___ASM_SPARC_SCATTERLIST_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/scatterlist_64.h>
+#else
+#include <asm/scatterlist_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/scatterlist_32.h b/arch/sparc/include/asm/scatterlist_32.h
new file mode 100644
index 000000000000..c82609ca1d0f
--- /dev/null
+++ b/arch/sparc/include/asm/scatterlist_32.h
@@ -0,0 +1,26 @@
+#ifndef _SPARC_SCATTERLIST_H
+#define _SPARC_SCATTERLIST_H
+
+#include <linux/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+        unsigned long sg_magic;
+#endif
+        unsigned long page_link;
+        unsigned int offset;
+
+        unsigned int length;
+
+        __u32 dvma_address; /* A place to hang host-specific addresses at. */
+        __u32 dvma_length;
+};
+
+#define sg_dma_address(sg) ((sg)->dvma_address)
+#define sg_dma_len(sg)     ((sg)->dvma_length)
+
+#define ISA_DMA_THRESHOLD (~0UL)
+
+#define ARCH_HAS_SG_CHAIN
+
+#endif /* !(_SPARC_SCATTERLIST_H) */
diff --git a/arch/sparc/include/asm/scatterlist_64.h b/arch/sparc/include/asm/scatterlist_64.h
new file mode 100644
index 000000000000..81bd058f9382
--- /dev/null
+++ b/arch/sparc/include/asm/scatterlist_64.h
@@ -0,0 +1,27 @@
+#ifndef _SPARC64_SCATTERLIST_H
+#define _SPARC64_SCATTERLIST_H
+
+#include <asm/page.h>
+#include <asm/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+        unsigned long   sg_magic;
+#endif
+        unsigned long   page_link;
+        unsigned int    offset;
+
+        unsigned int    length;
+
+        dma_addr_t      dma_address;
+        __u32           dma_length;
+};
+
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->dma_length)
+
+#define ISA_DMA_THRESHOLD       (~0UL)
+
+#define ARCH_HAS_SG_CHAIN
+
+#endif /* !(_SPARC64_SCATTERLIST_H) */
diff --git a/arch/sparc/include/asm/scratchpad.h b/arch/sparc/include/asm/scratchpad.h
new file mode 100644
index 000000000000..5e8b01fb3343
--- /dev/null
+++ b/arch/sparc/include/asm/scratchpad.h
@@ -0,0 +1,14 @@
+#ifndef _SPARC64_SCRATCHPAD_H
+#define _SPARC64_SCRATCHPAD_H
+
+/* Sun4v scratchpad registers, accessed via ASI_SCRATCHPAD.  */
+
+#define SCRATCHPAD_MMU_MISS     0x00 /* Shared with OBP - set by OBP        */
+#define SCRATCHPAD_CPUID        0x08 /* Shared with OBP - set by hypervisor */
+#define SCRATCHPAD_UTSBREG1     0x10
+#define SCRATCHPAD_UTSBREG2     0x18
+        /* 0x20 and 0x28, hypervisor only... */
+#define SCRATCHPAD_UNUSED1      0x30
+#define SCRATCHPAD_UNUSED2      0x38 /* Reserved for OBP                    */
+
+#endif /* !(_SPARC64_SCRATCHPAD_H) */
diff --git a/arch/sparc/include/asm/seccomp.h b/arch/sparc/include/asm/seccomp.h
new file mode 100644
index 000000000000..7fcd9968192b
--- /dev/null
+++ b/arch/sparc/include/asm/seccomp.h
@@ -0,0 +1,21 @@
+#ifndef _ASM_SECCOMP_H
+
+#include <linux/thread_info.h> /* already defines TIF_32BIT */
+
+#ifndef TIF_32BIT
+#error "unexpected TIF_32BIT on sparc64"
+#endif
+
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+#define __NR_seccomp_read_32 __NR_read
+#define __NR_seccomp_write_32 __NR_write
+#define __NR_seccomp_exit_32 __NR_exit
+#define __NR_seccomp_sigreturn_32 __NR_sigreturn
+
+#endif /* _ASM_SECCOMP_H */
diff --git a/arch/sparc/include/asm/sections.h b/arch/sparc/include/asm/sections.h
new file mode 100644
index 000000000000..c7c69b00967f
--- /dev/null
+++ b/arch/sparc/include/asm/sections.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SECTIONS_H
+#define ___ASM_SPARC_SECTIONS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sections_64.h>
+#else
+#include <asm/sections_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/sections_32.h b/arch/sparc/include/asm/sections_32.h
new file mode 100644
index 000000000000..6832841df051
--- /dev/null
+++ b/arch/sparc/include/asm/sections_32.h
@@ -0,0 +1,6 @@
+#ifndef _SPARC_SECTIONS_H
+#define _SPARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/sparc/include/asm/sections_64.h b/arch/sparc/include/asm/sections_64.h
new file mode 100644
index 000000000000..3f4b9fdc28d0
--- /dev/null
+++ b/arch/sparc/include/asm/sections_64.h
@@ -0,0 +1,9 @@
+#ifndef _SPARC64_SECTIONS_H
+#define _SPARC64_SECTIONS_H
+
+/* nothing to see, move along */
+#include <asm-generic/sections.h>
+
+extern char _start[];
+
+#endif
diff --git a/arch/sparc/include/asm/sembuf.h b/arch/sparc/include/asm/sembuf.h
new file mode 100644
index 000000000000..faee1be08d67
--- /dev/null
+++ b/arch/sparc/include/asm/sembuf.h
@@ -0,0 +1,31 @@
+#ifndef _SPARC_SEMBUF_H
+#define _SPARC_SEMBUF_H
+
+/*
+ * The semid64_ds structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        PADDING(__pad1)
+        __kernel_time_t sem_otime;              /* last semop time */
+        PADDING(__pad2)
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+#undef PADDING
+
+#endif /* _SPARC64_SEMBUF_H */
diff --git a/arch/sparc/include/asm/setup.h b/arch/sparc/include/asm/setup.h
new file mode 100644
index 000000000000..2643c62f4ac0
--- /dev/null
+++ b/arch/sparc/include/asm/setup.h
@@ -0,0 +1,14 @@
+/*
+ *      Just a place holder. 
+ */
+
+#ifndef _SPARC_SETUP_H
+#define _SPARC_SETUP_H
+
+#if defined(__sparc__) && defined(__arch64__)
+# define COMMAND_LINE_SIZE 2048
+#else
+# define COMMAND_LINE_SIZE 256
+#endif
+
+#endif /* _SPARC_SETUP_H */
diff --git a/arch/sparc/include/asm/sfafsr.h b/arch/sparc/include/asm/sfafsr.h
new file mode 100644
index 000000000000..e96137b04a4f
--- /dev/null
+++ b/arch/sparc/include/asm/sfafsr.h
@@ -0,0 +1,82 @@
+#ifndef _SPARC64_SFAFSR_H
+#define _SPARC64_SFAFSR_H
+
+#include <linux/const.h>
+
+/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
+
+#define SFAFSR_ME               (_AC(1,UL) << SFAFSR_ME_SHIFT)
+#define SFAFSR_ME_SHIFT         32
+#define SFAFSR_PRIV             (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
+#define SFAFSR_PRIV_SHIFT       31
+#define SFAFSR_ISAP             (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
+#define SFAFSR_ISAP_SHIFT       30
+#define SFAFSR_ETP              (_AC(1,UL) << SFAFSR_ETP_SHIFT)
+#define SFAFSR_ETP_SHIFT        29
+#define SFAFSR_IVUE             (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
+#define SFAFSR_IVUE_SHIFT       28
+#define SFAFSR_TO               (_AC(1,UL) << SFAFSR_TO_SHIFT)
+#define SFAFSR_TO_SHIFT         27
+#define SFAFSR_BERR             (_AC(1,UL) << SFAFSR_BERR_SHIFT)
+#define SFAFSR_BERR_SHIFT       26
+#define SFAFSR_LDP              (_AC(1,UL) << SFAFSR_LDP_SHIFT)
+#define SFAFSR_LDP_SHIFT        25
+#define SFAFSR_CP               (_AC(1,UL) << SFAFSR_CP_SHIFT)
+#define SFAFSR_CP_SHIFT         24
+#define SFAFSR_WP               (_AC(1,UL) << SFAFSR_WP_SHIFT)
+#define SFAFSR_WP_SHIFT         23
+#define SFAFSR_EDP              (_AC(1,UL) << SFAFSR_EDP_SHIFT)
+#define SFAFSR_EDP_SHIFT        22
+#define SFAFSR_UE               (_AC(1,UL) << SFAFSR_UE_SHIFT)
+#define SFAFSR_UE_SHIFT         21
+#define SFAFSR_CE               (_AC(1,UL) << SFAFSR_CE_SHIFT)
+#define SFAFSR_CE_SHIFT         20
+#define SFAFSR_ETS              (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
+#define SFAFSR_ETS_SHIFT        16
+#define SFAFSR_PSYND            (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
+#define SFAFSR_PSYND_SHIFT      0
+
+/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read
+ *                     ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write
+ */
+
+#define UDBE_UE                 (_AC(1,UL) << 9)
+#define UDBE_CE                 (_AC(1,UL) << 8)
+#define UDBE_E_SYNDR            (_AC(0xff,UL) << 0)
+
+/* The trap handlers for asynchronous errors encode the AFSR and
+ * other pieces of information into a 64-bit argument for C code
+ * encoded as follows:
+ *
+ * -----------------------------------------------
+ * |  UDB_H  |  UDB_L  | TL>1  |  TT  |   AFSR   |
+ * -----------------------------------------------
+ *  63     54 53     44    42   41  33 32       0
+ *
+ * The AFAR is passed in unchanged.
+ */
+#define SFSTAT_UDBH_MASK        (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
+#define SFSTAT_UDBH_SHIFT       54
+#define SFSTAT_UDBL_MASK        (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
+#define SFSTAT_UDBL_SHIFT       44
+#define SFSTAT_TL_GT_ONE        (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
+#define SFSTAT_TL_GT_ONE_SHIFT  42
+#define SFSTAT_TRAP_TYPE        (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
+#define SFSTAT_TRAP_TYPE_SHIFT  33
+#define SFSTAT_AFSR_MASK        (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
+#define SFSTAT_AFSR_SHIFT       0
+
+/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */
+#define ESTATE_ERR_CE           0x1 /* Correctable errors                    */
+#define ESTATE_ERR_NCE          0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */
+#define ESTATE_ERR_ISAP         0x4 /* System address parity error           */
+#define ESTATE_ERR_ALL          (ESTATE_ERR_CE | \
+                                 ESTATE_ERR_NCE | \
+                                 ESTATE_ERR_ISAP)
+
+/* The various trap types that report using the above state. */
+#define TRAP_TYPE_IAE           0x09 /* Instruction Access Error             */
+#define TRAP_TYPE_DAE           0x32 /* Data Access Error                    */
+#define TRAP_TYPE_CEE           0x63 /* Correctable ECC Error                */
+
+#endif /* _SPARC64_SFAFSR_H */
diff --git a/arch/sparc/include/asm/sfp-machine.h b/arch/sparc/include/asm/sfp-machine.h
new file mode 100644
index 000000000000..4ebc3823ed4f
--- /dev/null
+++ b/arch/sparc/include/asm/sfp-machine.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SFP_MACHINE_H
+#define ___ASM_SPARC_SFP_MACHINE_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sfp-machine_64.h>
+#else
+#include <asm/sfp-machine_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/sfp-machine_32.h b/arch/sparc/include/asm/sfp-machine_32.h
new file mode 100644
index 000000000000..01d9c3b5a73b
--- /dev/null
+++ b/arch/sparc/include/asm/sfp-machine_32.h
@@ -0,0 +1,212 @@
+/* Machine-dependent software floating-point definitions.
+   Sparc userland (_Q_*) version.
+   Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Richard Henderson (rth@cygnus.com),
+                  Jakub Jelinek (jj@ultra.linux.cz),
+                  David S. Miller (davem@redhat.com) and
+                  Peter Maydell (pmaydell@chiark.greenend.org.uk).
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If
+   not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _SFP_MACHINE_H
+#define _SFP_MACHINE_H
+
+
+#define _FP_W_TYPE_SIZE         32
+#define _FP_W_TYPE              unsigned long
+#define _FP_WS_TYPE             signed long
+#define _FP_I_TYPE              long
+
+#define _FP_MUL_MEAT_S(R,X,Y)                                   \
+  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y)                                   \
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y)                                   \
+  _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_udiv(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S           ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D           ((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q           ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S           0
+#define _FP_NANSIGN_D           0
+#define _FP_NANSIGN_Q           0
+
+#define _FP_KEEPNANFRACP 1
+
+/* If one NaN is signaling and the other is not,
+ * we choose that one, otherwise we choose X.
+ */
+/* For _Qp_* and _Q_*, this should prefer X, for
+ * CPU instruction emulation this should prefer Y.
+ * (see SPAMv9 B.2.2 section).
+ */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
+  do {                                                          \
+    if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)          \
+        && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs))     \
+      {                                                         \
+        R##_s = X##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,X);                                \
+      }                                                         \
+    else                                                        \
+      {                                                         \
+        R##_s = Y##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,Y);                                \
+      }                                                         \
+    R##_c = FP_CLS_NAN;                                         \
+  } while (0)
+
+/* Some assembly to speed things up. */
+#define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0)                     \
+  __asm__ ("addcc %r7,%8,%2\n\t"                                        \
+           "addxcc %r5,%6,%1\n\t"                                       \
+           "addx %r3,%4,%0\n"                                           \
+           : "=r" ((USItype)(r2)),                                      \
+             "=&r" ((USItype)(r1)),                                     \
+             "=&r" ((USItype)(r0))                                      \
+           : "%rJ" ((USItype)(x2)),                                     \
+             "rI" ((USItype)(y2)),                                      \
+             "%rJ" ((USItype)(x1)),                                     \
+             "rI" ((USItype)(y1)),                                      \
+             "%rJ" ((USItype)(x0)),                                     \
+             "rI" ((USItype)(y0))                                       \
+           : "cc")
+
+#define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0)                     \
+  __asm__ ("subcc %r7,%8,%2\n\t"                                        \
+            "subxcc %r5,%6,%1\n\t"                                      \
+            "subx %r3,%4,%0\n"                                          \
+           : "=r" ((USItype)(r2)),                                      \
+             "=&r" ((USItype)(r1)),                                     \
+             "=&r" ((USItype)(r0))                                      \
+           : "%rJ" ((USItype)(x2)),                                     \
+             "rI" ((USItype)(y2)),                                      \
+             "%rJ" ((USItype)(x1)),                                     \
+             "rI" ((USItype)(y1)),                                      \
+             "%rJ" ((USItype)(x0)),                                     \
+             "rI" ((USItype)(y0))                                       \
+           : "cc")
+
+#define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0)            \
+  do {                                                                  \
+    /* We need to fool gcc,  as we need to pass more than 10            \
+       input/outputs.  */                                               \
+    register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2");            \
+    __asm__ __volatile__ (                                              \
+            "addcc %r8,%9,%1\n\t"                                       \
+            "addxcc %r6,%7,%0\n\t"                                      \
+            "addxcc %r4,%5,%%g2\n\t"                                    \
+            "addx %r2,%3,%%g1\n\t"                                      \
+           : "=&r" ((USItype)(r1)),                                     \
+             "=&r" ((USItype)(r0))                                      \
+           : "%rJ" ((USItype)(x3)),                                     \
+             "rI" ((USItype)(y3)),                                      \
+             "%rJ" ((USItype)(x2)),                                     \
+             "rI" ((USItype)(y2)),                                      \
+             "%rJ" ((USItype)(x1)),                                     \
+             "rI" ((USItype)(y1)),                                      \
+             "%rJ" ((USItype)(x0)),                                     \
+             "rI" ((USItype)(y0))                                       \
+           : "cc", "g1", "g2");                                         \
+    __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2));                 \
+    r3 = _t1; r2 = _t2;                                                 \
+  } while (0)
+
+#define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0)            \
+  do {                                                                  \
+    /* We need to fool gcc,  as we need to pass more than 10            \
+       input/outputs.  */                                               \
+    register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2");            \
+    __asm__ __volatile__ (                                              \
+            "subcc %r8,%9,%1\n\t"                                       \
+            "subxcc %r6,%7,%0\n\t"                                      \
+            "subxcc %r4,%5,%%g2\n\t"                                    \
+            "subx %r2,%3,%%g1\n\t"                                      \
+           : "=&r" ((USItype)(r1)),                                     \
+             "=&r" ((USItype)(r0))                                      \
+           : "%rJ" ((USItype)(x3)),                                     \
+             "rI" ((USItype)(y3)),                                      \
+             "%rJ" ((USItype)(x2)),                                     \
+             "rI" ((USItype)(y2)),                                      \
+             "%rJ" ((USItype)(x1)),                                     \
+             "rI" ((USItype)(y1)),                                      \
+             "%rJ" ((USItype)(x0)),                                     \
+             "rI" ((USItype)(y0))                                       \
+           : "cc", "g1", "g2");                                         \
+    __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2));                 \
+    r3 = _t1; r2 = _t2;                                                 \
+  } while (0)
+
+#define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
+
+#define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
+
+#define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i)                                 \
+  __asm__ ("addcc %3,%4,%3\n\t"                                         \
+           "addxcc %2,%%g0,%2\n\t"                                      \
+           "addxcc %1,%%g0,%1\n\t"                                      \
+           "addx %0,%%g0,%0\n\t"                                        \
+           : "=&r" ((USItype)(x3)),                                     \
+             "=&r" ((USItype)(x2)),                                     \
+             "=&r" ((USItype)(x1)),                                     \
+             "=&r" ((USItype)(x0))                                      \
+           : "rI" ((USItype)(i)),                                       \
+             "0" ((USItype)(x3)),                                       \
+             "1" ((USItype)(x2)),                                       \
+             "2" ((USItype)(x1)),                                       \
+             "3" ((USItype)(x0))                                        \
+           : "cc")
+
+#ifndef CONFIG_SMP
+extern struct task_struct *last_task_used_math;
+#endif
+
+/* Obtain the current rounding mode. */
+#ifndef FP_ROUNDMODE
+#ifdef CONFIG_SMP
+#define FP_ROUNDMODE    ((current->thread.fsr >> 30) & 0x3)
+#else
+#define FP_ROUNDMODE    ((last_task_used_math->thread.fsr >> 30) & 0x3)
+#endif
+#endif
+
+/* Exception flags. */
+#define FP_EX_INVALID           (1 << 4)
+#define FP_EX_OVERFLOW          (1 << 3)
+#define FP_EX_UNDERFLOW         (1 << 2)
+#define FP_EX_DIVZERO           (1 << 1)
+#define FP_EX_INEXACT           (1 << 0)
+
+#define FP_HANDLE_EXCEPTIONS return _fex
+
+#ifdef CONFIG_SMP
+#define FP_INHIBIT_RESULTS ((current->thread.fsr >> 23) & _fex)
+#else
+#define FP_INHIBIT_RESULTS ((last_task_used_math->thread.fsr >> 23) & _fex)
+#endif
+
+#ifdef CONFIG_SMP
+#define FP_TRAPPING_EXCEPTIONS ((current->thread.fsr >> 23) & 0x1f)
+#else
+#define FP_TRAPPING_EXCEPTIONS ((last_task_used_math->thread.fsr >> 23) & 0x1f)
+#endif
+
+#endif
diff --git a/arch/sparc/include/asm/sfp-machine_64.h b/arch/sparc/include/asm/sfp-machine_64.h
new file mode 100644
index 000000000000..ca913ef40bd5
--- /dev/null
+++ b/arch/sparc/include/asm/sfp-machine_64.h
@@ -0,0 +1,93 @@
+/* Machine-dependent software floating-point definitions.
+   Sparc64 kernel version.
+   Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Richard Henderson (rth@cygnus.com),
+                  Jakub Jelinek (jj@ultra.linux.cz) and
+                  David S. Miller (davem@redhat.com).
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If
+   not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _SFP_MACHINE_H
+#define _SFP_MACHINE_H
+
+#define _FP_W_TYPE_SIZE         64
+#define _FP_W_TYPE              unsigned long
+#define _FP_WS_TYPE             signed long
+#define _FP_I_TYPE              long
+
+#define _FP_MUL_MEAT_S(R,X,Y)                                   \
+  _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
+#define _FP_MUL_MEAT_D(R,X,Y)                                   \
+  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y)                                   \
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
+#define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S           ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D           ((_FP_QNANBIT_D << 1) - 1)
+#define _FP_NANFRAC_Q           ((_FP_QNANBIT_Q << 1) - 1), -1
+#define _FP_NANSIGN_S           0
+#define _FP_NANSIGN_D           0
+#define _FP_NANSIGN_Q           0
+
+#define _FP_KEEPNANFRACP 1
+
+/* If one NaN is signaling and the other is not,
+ * we choose that one, otherwise we choose X.
+ */
+/* For _Qp_* and _Q_*, this should prefer X, for
+ * CPU instruction emulation this should prefer Y.
+ * (see SPAMv9 B.2.2 section).
+ */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
+  do {                                                          \
+    if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)          \
+        && !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs))     \
+      {                                                         \
+        R##_s = X##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,X);                                \
+      }                                                         \
+    else                                                        \
+      {                                                         \
+        R##_s = Y##_s;                                          \
+        _FP_FRAC_COPY_##wc(R,Y);                                \
+      }                                                         \
+    R##_c = FP_CLS_NAN;                                         \
+  } while (0)
+
+/* Obtain the current rounding mode. */
+#ifndef FP_ROUNDMODE
+#define FP_ROUNDMODE    ((current_thread_info()->xfsr[0] >> 30) & 0x3)
+#endif
+
+/* Exception flags. */
+#define FP_EX_INVALID           (1 << 4)
+#define FP_EX_OVERFLOW          (1 << 3)
+#define FP_EX_UNDERFLOW         (1 << 2)
+#define FP_EX_DIVZERO           (1 << 1)
+#define FP_EX_INEXACT           (1 << 0)
+
+#define FP_HANDLE_EXCEPTIONS return _fex
+
+#define FP_INHIBIT_RESULTS ((current_thread_info()->xfsr[0] >> 23) & _fex)
+
+#define FP_TRAPPING_EXCEPTIONS ((current_thread_info()->xfsr[0] >> 23) & 0x1f)
+
+#endif
diff --git a/arch/sparc/include/asm/shmbuf.h b/arch/sparc/include/asm/shmbuf.h
new file mode 100644
index 000000000000..83a16055363f
--- /dev/null
+++ b/arch/sparc/include/asm/shmbuf.h
@@ -0,0 +1,50 @@
+#ifndef _SPARC_SHMBUF_H
+#define _SPARC_SHMBUF_H
+
+/* 
+ * The shmid64_ds structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        PADDING(__pad1)
+        __kernel_time_t         shm_atime;      /* last attach time */
+        PADDING(__pad2)
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        PADDING(__pad3)
+        __kernel_time_t         shm_ctime;      /* last change time */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#undef PADDING
+
+#endif /* _SPARC_SHMBUF_H */
diff --git a/arch/sparc/include/asm/shmparam.h b/arch/sparc/include/asm/shmparam.h
new file mode 100644
index 000000000000..8bf0cfe0694f
--- /dev/null
+++ b/arch/sparc/include/asm/shmparam.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SHMPARAM_H
+#define ___ASM_SPARC_SHMPARAM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/shmparam_64.h>
+#else
+#include <asm/shmparam_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/shmparam_32.h b/arch/sparc/include/asm/shmparam_32.h
new file mode 100644
index 000000000000..59a1243c12f3
--- /dev/null
+++ b/arch/sparc/include/asm/shmparam_32.h
@@ -0,0 +1,11 @@
+#ifndef _ASMSPARC_SHMPARAM_H
+#define _ASMSPARC_SHMPARAM_H
+
+#define __ARCH_FORCE_SHMLBA     1
+
+extern int vac_cache_size;
+#define SHMLBA (vac_cache_size ? vac_cache_size : \
+                (sparc_cpu_model == sun4c ? (64 * 1024) : \
+                 (sparc_cpu_model == sun4 ? (128 * 1024) : PAGE_SIZE)))
+
+#endif /* _ASMSPARC_SHMPARAM_H */
diff --git a/arch/sparc/include/asm/shmparam_64.h b/arch/sparc/include/asm/shmparam_64.h
new file mode 100644
index 000000000000..1ed0d6701a9b
--- /dev/null
+++ b/arch/sparc/include/asm/shmparam_64.h
@@ -0,0 +1,10 @@
+#ifndef _ASMSPARC64_SHMPARAM_H
+#define _ASMSPARC64_SHMPARAM_H
+
+#include <asm/spitfire.h>
+
+#define __ARCH_FORCE_SHMLBA     1
+/* attach addr a multiple of this */
+#define SHMLBA  ((PAGE_SIZE > L1DCACHE_SIZE) ? PAGE_SIZE : L1DCACHE_SIZE)
+
+#endif /* _ASMSPARC64_SHMPARAM_H */
diff --git a/arch/sparc/include/asm/sigcontext.h b/arch/sparc/include/asm/sigcontext.h
new file mode 100644
index 000000000000..e92de7e286b5
--- /dev/null
+++ b/arch/sparc/include/asm/sigcontext.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SIGCONTEXT_H
+#define ___ASM_SPARC_SIGCONTEXT_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/sigcontext_64.h>
+#else
+#include <asm/sigcontext_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/sigcontext_32.h b/arch/sparc/include/asm/sigcontext_32.h
new file mode 100644
index 000000000000..c5fb60dcbd75
--- /dev/null
+++ b/arch/sparc/include/asm/sigcontext_32.h
@@ -0,0 +1,62 @@
+#ifndef __SPARC_SIGCONTEXT_H
+#define __SPARC_SIGCONTEXT_H
+
+#ifdef __KERNEL__
+#include <asm/ptrace.h>
+
+#ifndef __ASSEMBLY__
+
+#define __SUNOS_MAXWIN   31
+
+/* This is what SunOS does, so shall I. */
+struct sigcontext {
+        int sigc_onstack;      /* state to restore */
+        int sigc_mask;         /* sigmask to restore */
+        int sigc_sp;           /* stack pointer */
+        int sigc_pc;           /* program counter */
+        int sigc_npc;          /* next program counter */
+        int sigc_psr;          /* for condition codes etc */
+        int sigc_g1;           /* User uses these two registers */
+        int sigc_o0;           /* within the trampoline code. */
+
+        /* Now comes information regarding the users window set
+         * at the time of the signal.
+         */
+        int sigc_oswins;       /* outstanding windows */
+
+        /* stack ptrs for each regwin buf */
+        char *sigc_spbuf[__SUNOS_MAXWIN];
+
+        /* Windows to restore after signal */
+        struct {
+                unsigned long   locals[8];
+                unsigned long   ins[8];
+        } sigc_wbuf[__SUNOS_MAXWIN];
+};
+
+typedef struct {
+        struct {
+                unsigned long psr;
+                unsigned long pc;
+                unsigned long npc;
+                unsigned long y;
+                unsigned long u_regs[16]; /* globals and ins */
+        }               si_regs;
+        int             si_mask;
+} __siginfo_t;
+
+typedef struct {
+        unsigned   long si_float_regs [32];
+        unsigned   long si_fsr;
+        unsigned   long si_fpqdepth;
+        struct {
+                unsigned long *insn_addr;
+                unsigned long insn;
+        } si_fpqueue [16];
+} __siginfo_fpu_t;
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* (__KERNEL__) */
+
+#endif /* !(__SPARC_SIGCONTEXT_H) */
diff --git a/arch/sparc/include/asm/sigcontext_64.h b/arch/sparc/include/asm/sigcontext_64.h
new file mode 100644
index 000000000000..1c868d680cfc
--- /dev/null
+++ b/arch/sparc/include/asm/sigcontext_64.h
@@ -0,0 +1,87 @@
+#ifndef __SPARC64_SIGCONTEXT_H
+#define __SPARC64_SIGCONTEXT_H
+
+#ifdef __KERNEL__
+#include <asm/ptrace.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifdef __KERNEL__
+
+#define __SUNOS_MAXWIN   31
+
+/* This is what SunOS does, so shall I unless we use new 32bit signals or rt signals. */
+struct sigcontext32 {
+        int sigc_onstack;      /* state to restore */
+        int sigc_mask;         /* sigmask to restore */
+        int sigc_sp;           /* stack pointer */
+        int sigc_pc;           /* program counter */
+        int sigc_npc;          /* next program counter */
+        int sigc_psr;          /* for condition codes etc */
+        int sigc_g1;           /* User uses these two registers */
+        int sigc_o0;           /* within the trampoline code. */
+
+        /* Now comes information regarding the users window set
+         * at the time of the signal.
+         */
+        int sigc_oswins;       /* outstanding windows */
+
+        /* stack ptrs for each regwin buf */
+        unsigned sigc_spbuf[__SUNOS_MAXWIN];
+
+        /* Windows to restore after signal */
+        struct reg_window32 sigc_wbuf[__SUNOS_MAXWIN];
+};
+
+#endif
+
+#ifdef __KERNEL__
+
+/* This is what we use for 32bit new non-rt signals. */
+
+typedef struct {
+        struct {
+                unsigned int psr;
+                unsigned int pc;
+                unsigned int npc;
+                unsigned int y;
+                unsigned int u_regs[16]; /* globals and ins */
+        }                       si_regs;
+        int                     si_mask;
+} __siginfo32_t;
+
+#endif
+
+typedef struct {
+        unsigned   int si_float_regs [64];
+        unsigned   long si_fsr;
+        unsigned   long si_gsr;
+        unsigned   long si_fprs;
+} __siginfo_fpu_t;
+
+/* This is what SunOS doesn't, so we have to write this alone
+   and do it properly. */
+struct sigcontext {
+        /* The size of this array has to match SI_MAX_SIZE from siginfo.h */
+        char                    sigc_info[128];
+        struct {
+                unsigned long   u_regs[16]; /* globals and ins */
+                unsigned long   tstate;
+                unsigned long   tpc;
+                unsigned long   tnpc;
+                unsigned int    y;
+                unsigned int    fprs;
+        }                       sigc_regs;
+        __siginfo_fpu_t *       sigc_fpu_save;
+        struct {
+                void    *       ss_sp;
+                int             ss_flags;
+                unsigned long   ss_size;
+        }                       sigc_stack;
+        unsigned long           sigc_mask;
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_SIGCONTEXT_H) */
diff --git a/arch/sparc/include/asm/siginfo.h b/arch/sparc/include/asm/siginfo.h
new file mode 100644
index 000000000000..bd81f8d7f5ce
--- /dev/null
+++ b/arch/sparc/include/asm/siginfo.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SIGINFO_H
+#define ___ASM_SPARC_SIGINFO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/siginfo_64.h>
+#else
+#include <asm/siginfo_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/siginfo_32.h b/arch/sparc/include/asm/siginfo_32.h
new file mode 100644
index 000000000000..3c71af135c52
--- /dev/null
+++ b/arch/sparc/include/asm/siginfo_32.h
@@ -0,0 +1,17 @@
+#ifndef _SPARC_SIGINFO_H
+#define _SPARC_SIGINFO_H
+
+#define __ARCH_SI_UID_T         unsigned int
+#define __ARCH_SI_TRAPNO
+
+#include <asm-generic/siginfo.h>
+
+#define SI_NOINFO       32767           /* no information in siginfo_t */
+
+/*
+ * SIGEMT si_codes
+ */
+#define EMT_TAGOVF      (__SI_FAULT|1)  /* tag overflow */
+#define NSIGEMT         1
+
+#endif /* !(_SPARC_SIGINFO_H) */
diff --git a/arch/sparc/include/asm/siginfo_64.h b/arch/sparc/include/asm/siginfo_64.h
new file mode 100644
index 000000000000..c96e6c30f8b0
--- /dev/null
+++ b/arch/sparc/include/asm/siginfo_64.h
@@ -0,0 +1,32 @@
+#ifndef _SPARC64_SIGINFO_H
+#define _SPARC64_SIGINFO_H
+
+#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
+
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#define __ARCH_SI_TRAPNO
+#define __ARCH_SI_BAND_T int
+
+#include <asm-generic/siginfo.h>
+
+#ifdef __KERNEL__
+
+#include <linux/compat.h>
+
+#ifdef CONFIG_COMPAT
+
+struct compat_siginfo;
+
+#endif /* CONFIG_COMPAT */
+
+#endif /* __KERNEL__ */
+
+#define SI_NOINFO       32767           /* no information in siginfo_t */
+
+/*
+ * SIGEMT si_codes
+ */
+#define EMT_TAGOVF      (__SI_FAULT|1)  /* tag overflow */
+#define NSIGEMT         1
+
+#endif
diff --git a/arch/sparc/include/asm/signal.h b/arch/sparc/include/asm/signal.h
new file mode 100644
index 000000000000..27ab05dc203e
--- /dev/null
+++ b/arch/sparc/include/asm/signal.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SIGNAL_H
+#define ___ASM_SPARC_SIGNAL_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/signal_64.h>
+#else
+#include <asm/signal_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/signal_32.h b/arch/sparc/include/asm/signal_32.h
new file mode 100644
index 000000000000..96a60ab03ca1
--- /dev/null
+++ b/arch/sparc/include/asm/signal_32.h
@@ -0,0 +1,207 @@
+#ifndef _ASMSPARC_SIGNAL_H
+#define _ASMSPARC_SIGNAL_H
+
+#include <asm/sigcontext.h>
+#include <linux/compiler.h>
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#include <linux/personality.h>
+#include <linux/types.h>
+#endif
+#endif
+
+/* On the Sparc the signal handlers get passed a 'sub-signal' code
+ * for certain signal types, which we document here.
+ */
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define    SUBSIG_STACK       0
+#define    SUBSIG_ILLINST     2
+#define    SUBSIG_PRIVINST    3
+#define    SUBSIG_BADTRAP(t)  (0x80 + (t))
+
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+
+#define SIGEMT           7
+#define    SUBSIG_TAG    10
+
+#define SIGFPE           8
+#define    SUBSIG_FPDISABLED     0x400
+#define    SUBSIG_FPERROR        0x404
+#define    SUBSIG_FPINTOVFL      0x001
+#define    SUBSIG_FPSTSIG        0x002
+#define    SUBSIG_IDIVZERO       0x014
+#define    SUBSIG_FPINEXACT      0x0c4
+#define    SUBSIG_FPDIVZERO      0x0c8
+#define    SUBSIG_FPUNFLOW       0x0cc
+#define    SUBSIG_FPOPERROR      0x0d0
+#define    SUBSIG_FPOVFLOW       0x0d4
+
+#define SIGKILL          9
+#define SIGBUS          10
+#define    SUBSIG_BUSTIMEOUT    1
+#define    SUBSIG_ALIGNMENT     2
+#define    SUBSIG_MISCERROR     5
+
+#define SIGSEGV         11
+#define    SUBSIG_NOMAPPING     3
+#define    SUBSIG_PROTECTION    4
+#define    SUBSIG_SEGERROR      5
+
+#define SIGSYS          12
+
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGURG          16
+
+/* SunOS values which deviate from the Linux/i386 ones */
+#define SIGSTOP         17
+#define SIGTSTP         18
+#define SIGCONT         19
+#define SIGCHLD         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGIO           23
+#define SIGPOLL         SIGIO   /* SysV name for SIGIO */
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGLOST         29
+#define SIGPWR          SIGLOST
+#define SIGUSR1         30
+#define SIGUSR2         31
+
+/* Most things should be clean enough to redefine this at will, if care
+ * is taken to make libc match.
+ */
+
+#define __OLD_NSIG      32
+#define __NEW_NSIG      64
+#define _NSIG_BPW       32
+#define _NSIG_WORDS     (__NEW_NSIG / _NSIG_BPW)
+
+#define SIGRTMIN        32
+#define SIGRTMAX        __NEW_NSIG
+
+#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
+#define _NSIG           __NEW_NSIG
+#define __new_sigset_t  sigset_t
+#define __new_sigaction sigaction
+#define __old_sigset_t  old_sigset_t
+#define __old_sigaction old_sigaction
+#else
+#define _NSIG           __OLD_NSIG
+#define __old_sigset_t  sigset_t
+#define __old_sigaction sigaction
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long __old_sigset_t;
+
+typedef struct {
+        unsigned long   sig[_NSIG_WORDS];
+} __new_sigset_t;
+
+
+#ifdef __KERNEL__
+/* A SunOS sigstack */
+struct sigstack {
+        char *the_stack;
+        int   cur_status;
+};
+#endif
+
+/* Sigvec flags */
+#define _SV_SSTACK    1u    /* This signal handler should use sig-stack */
+#define _SV_INTR      2u    /* Sig return should not restart system call */
+#define _SV_RESET     4u    /* Set handler to SIG_DFL upon taken signal */
+#define _SV_IGNCHILD  8u    /* Do not send SIGCHLD */
+
+/*
+ * sa_flags values: SA_STACK is not currently supported, but will allow the
+ * usage of signal stacks by using the (now obsolete) sa_restorer field in
+ * the sigaction structure as a stack pointer. This is now possible due to
+ * the changes in signal handling. LBT 010493.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ */
+#define SA_NOCLDSTOP    _SV_IGNCHILD
+#define SA_STACK        _SV_SSTACK
+#define SA_ONSTACK      _SV_SSTACK
+#define SA_RESTART      _SV_INTR
+#define SA_ONESHOT      _SV_RESET
+#define SA_NOMASK       0x20u
+#define SA_NOCLDWAIT    0x100u
+#define SA_SIGINFO      0x200u
+
+#define SIG_BLOCK          0x01 /* for blocking signals */
+#define SIG_UNBLOCK        0x02 /* for unblocking signals */
+#define SIG_SETMASK        0x04 /* for setting the signal mask */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     4096
+#define SIGSTKSZ        16384
+
+#ifdef __KERNEL__
+/*
+ * DJHR
+ * SA_STATIC_ALLOC is used for the SPARC system to indicate that this
+ * interrupt handler's irq structure should be statically allocated
+ * by the request_irq routine.
+ * The alternative is that arch/sparc/kernel/irq.c has carnal knowledge
+ * of interrupt usage and that sucks. Also without a flag like this
+ * it may be possible for the free_irq routine to attempt to free
+ * statically allocated data.. which is NOT GOOD.
+ *
+ */
+#define SA_STATIC_ALLOC         0x8000
+#endif
+
+#include <asm-generic/signal.h>
+
+#ifdef __KERNEL__
+struct __new_sigaction {
+        __sighandler_t  sa_handler;
+        unsigned long   sa_flags;
+        void            (*sa_restorer)(void);   /* Not used by Linux/SPARC */
+        __new_sigset_t  sa_mask;
+};
+
+struct k_sigaction {
+        struct __new_sigaction  sa;
+        void                    __user *ka_restorer;
+};
+
+struct __old_sigaction {
+        __sighandler_t  sa_handler;
+        __old_sigset_t  sa_mask;
+        unsigned long   sa_flags;
+        void            (*sa_restorer) (void);  /* not used by Linux/SPARC */
+};
+
+typedef struct sigaltstack {
+        void            __user *ss_sp;
+        int             ss_flags;
+        size_t          ss_size;
+} stack_t;
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_ASMSPARC_SIGNAL_H) */
diff --git a/arch/sparc/include/asm/signal_64.h b/arch/sparc/include/asm/signal_64.h
new file mode 100644
index 000000000000..ab1509a101c5
--- /dev/null
+++ b/arch/sparc/include/asm/signal_64.h
@@ -0,0 +1,194 @@
+#ifndef _ASMSPARC64_SIGNAL_H
+#define _ASMSPARC64_SIGNAL_H
+
+#include <asm/sigcontext.h>
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+#include <linux/personality.h>
+#include <linux/types.h>
+#endif
+#endif
+
+/* On the Sparc the signal handlers get passed a 'sub-signal' code
+ * for certain signal types, which we document here.
+ */
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define    SUBSIG_STACK       0
+#define    SUBSIG_ILLINST     2
+#define    SUBSIG_PRIVINST    3
+#define    SUBSIG_BADTRAP(t)  (0x80 + (t))
+
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+
+#define SIGEMT           7
+#define    SUBSIG_TAG    10
+
+#define SIGFPE           8
+#define    SUBSIG_FPDISABLED     0x400
+#define    SUBSIG_FPERROR        0x404
+#define    SUBSIG_FPINTOVFL      0x001
+#define    SUBSIG_FPSTSIG        0x002
+#define    SUBSIG_IDIVZERO       0x014
+#define    SUBSIG_FPINEXACT      0x0c4
+#define    SUBSIG_FPDIVZERO      0x0c8
+#define    SUBSIG_FPUNFLOW       0x0cc
+#define    SUBSIG_FPOPERROR      0x0d0
+#define    SUBSIG_FPOVFLOW       0x0d4
+
+#define SIGKILL          9
+#define SIGBUS          10
+#define    SUBSIG_BUSTIMEOUT    1
+#define    SUBSIG_ALIGNMENT     2
+#define    SUBSIG_MISCERROR     5
+
+#define SIGSEGV         11
+#define    SUBSIG_NOMAPPING     3
+#define    SUBSIG_PROTECTION    4
+#define    SUBSIG_SEGERROR      5
+
+#define SIGSYS          12
+
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGURG          16
+
+/* SunOS values which deviate from the Linux/i386 ones */
+#define SIGSTOP         17
+#define SIGTSTP         18
+#define SIGCONT         19
+#define SIGCHLD         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGIO           23
+#define SIGPOLL         SIGIO   /* SysV name for SIGIO */
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGLOST         29
+#define SIGPWR          SIGLOST
+#define SIGUSR1         30
+#define SIGUSR2         31
+
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define __OLD_NSIG      32
+#define __NEW_NSIG      64
+#define _NSIG_BPW       64
+#define _NSIG_WORDS     (__NEW_NSIG / _NSIG_BPW)
+
+#define SIGRTMIN       32
+#define SIGRTMAX       __NEW_NSIG
+
+#if defined(__KERNEL__) || defined(__WANT_POSIX1B_SIGNALS__)
+#define _NSIG                   __NEW_NSIG
+#define __new_sigset_t          sigset_t
+#define __new_sigaction         sigaction
+#define __new_sigaction32       sigaction32
+#define __old_sigset_t          old_sigset_t
+#define __old_sigaction         old_sigaction
+#define __old_sigaction32       old_sigaction32
+#else
+#define _NSIG                   __OLD_NSIG
+#define NSIG                    _NSIG
+#define __old_sigset_t          sigset_t
+#define __old_sigaction         sigaction
+#define __old_sigaction32       sigaction32
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long __old_sigset_t;            /* at least 32 bits */
+
+typedef struct {
+       unsigned long sig[_NSIG_WORDS];
+} __new_sigset_t;
+
+/* A SunOS sigstack */
+struct sigstack {
+        /* XXX 32-bit pointers pinhead XXX */
+        char *the_stack;
+        int   cur_status;
+};
+
+/* Sigvec flags */
+#define _SV_SSTACK    1u    /* This signal handler should use sig-stack */
+#define _SV_INTR      2u    /* Sig return should not restart system call */
+#define _SV_RESET     4u    /* Set handler to SIG_DFL upon taken signal */
+#define _SV_IGNCHILD  8u    /* Do not send SIGCHLD */
+
+/*
+ * sa_flags values: SA_STACK is not currently supported, but will allow the
+ * usage of signal stacks by using the (now obsolete) sa_restorer field in
+ * the sigaction structure as a stack pointer. This is now possible due to
+ * the changes in signal handling. LBT 010493.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ */
+#define SA_NOCLDSTOP    _SV_IGNCHILD
+#define SA_STACK        _SV_SSTACK
+#define SA_ONSTACK      _SV_SSTACK
+#define SA_RESTART      _SV_INTR
+#define SA_ONESHOT      _SV_RESET
+#define SA_NOMASK       0x20u
+#define SA_NOCLDWAIT    0x100u
+#define SA_SIGINFO      0x200u
+
+
+#define SIG_BLOCK          0x01 /* for blocking signals */
+#define SIG_UNBLOCK        0x02 /* for unblocking signals */
+#define SIG_SETMASK        0x04 /* for setting the signal mask */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     4096
+#define SIGSTKSZ        16384
+
+#include <asm-generic/signal.h>
+
+struct __new_sigaction {
+        __sighandler_t          sa_handler;
+        unsigned long           sa_flags;
+        __sigrestore_t          sa_restorer;  /* not used by Linux/SPARC yet */
+        __new_sigset_t          sa_mask;
+};
+
+struct __old_sigaction {
+        __sighandler_t          sa_handler;
+        __old_sigset_t          sa_mask;
+        unsigned long           sa_flags;
+        void                    (*sa_restorer)(void);     /* not used by Linux/SPARC yet */
+};
+
+typedef struct sigaltstack {
+        void                    __user *ss_sp;
+        int                     ss_flags;
+        size_t                  ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+
+struct k_sigaction {
+        struct __new_sigaction  sa;
+        void __user             *ka_restorer;
+};
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_ASMSPARC64_SIGNAL_H) */
diff --git a/arch/sparc/include/asm/smp.h b/arch/sparc/include/asm/smp.h
new file mode 100644
index 000000000000..b59672d0e19b
--- /dev/null
+++ b/arch/sparc/include/asm/smp.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SMP_H
+#define ___ASM_SPARC_SMP_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/smp_64.h>
+#else
+#include <asm/smp_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/smp_32.h b/arch/sparc/include/asm/smp_32.h
new file mode 100644
index 000000000000..7201752cf934
--- /dev/null
+++ b/arch/sparc/include/asm/smp_32.h
@@ -0,0 +1,173 @@
+/* smp.h: Sparc specific SMP stuff.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SMP_H
+#define _SPARC_SMP_H
+
+#include <linux/threads.h>
+#include <asm/head.h>
+#include <asm/btfixup.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/cpumask.h>
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_SMP
+
+#ifndef __ASSEMBLY__
+
+#include <asm/ptrace.h>
+#include <asm/asi.h>
+#include <asm/atomic.h>
+
+/*
+ *      Private routines/data
+ */
+
+extern unsigned char boot_cpu_id;
+extern cpumask_t phys_cpu_present_map;
+#define cpu_possible_map phys_cpu_present_map
+
+typedef void (*smpfunc_t)(unsigned long, unsigned long, unsigned long,
+                       unsigned long, unsigned long);
+
+/*
+ *      General functions that each host system must provide.
+ */
+
+void sun4m_init_smp(void);
+void sun4d_init_smp(void);
+
+void smp_callin(void);
+void smp_boot_cpus(void);
+void smp_store_cpu_info(int);
+
+struct seq_file;
+void smp_bogo(struct seq_file *);
+void smp_info(struct seq_file *);
+
+BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void)
+BTFIXUPDEF_BLACKBOX(hard_smp_processor_id)
+BTFIXUPDEF_BLACKBOX(load_current)
+
+#define smp_cross_call(func,arg1,arg2,arg3,arg4,arg5) BTFIXUP_CALL(smp_cross_call)(func,arg1,arg2,arg3,arg4,arg5)
+
+static inline void xc0(smpfunc_t func) { smp_cross_call(func, 0, 0, 0, 0, 0); }
+static inline void xc1(smpfunc_t func, unsigned long arg1)
+{ smp_cross_call(func, arg1, 0, 0, 0, 0); }
+static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2)
+{ smp_cross_call(func, arg1, arg2, 0, 0, 0); }
+static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+                           unsigned long arg3)
+{ smp_cross_call(func, arg1, arg2, arg3, 0, 0); }
+static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+                           unsigned long arg3, unsigned long arg4)
+{ smp_cross_call(func, arg1, arg2, arg3, arg4, 0); }
+static inline void xc5(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+                           unsigned long arg3, unsigned long arg4, unsigned long arg5)
+{ smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); }
+
+static inline int smp_call_function(void (*func)(void *info), void *info, int wait)
+{
+        xc1((smpfunc_t)func, (unsigned long)info);
+        return 0;
+}
+
+static inline int cpu_logical_map(int cpu)
+{
+        return cpu;
+}
+
+static inline int hard_smp4m_processor_id(void)
+{
+        int cpuid;
+
+        __asm__ __volatile__("rd %%tbr, %0\n\t"
+                             "srl %0, 12, %0\n\t"
+                             "and %0, 3, %0\n\t" :
+                             "=&r" (cpuid));
+        return cpuid;
+}
+
+static inline int hard_smp4d_processor_id(void)
+{
+        int cpuid;
+
+        __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
+                             "=&r" (cpuid) : "i" (ASI_M_VIKING_TMP1));
+        return cpuid;
+}
+
+#ifndef MODULE
+static inline int hard_smp_processor_id(void)
+{
+        int cpuid;
+
+        /* Black box - sun4m
+                __asm__ __volatile__("rd %%tbr, %0\n\t"
+                                     "srl %0, 12, %0\n\t"
+                                     "and %0, 3, %0\n\t" :
+                                     "=&r" (cpuid));
+                     - sun4d
+                __asm__ __volatile__("lda [%g0] ASI_M_VIKING_TMP1, %0\n\t"
+                                     "nop; nop" :
+                                     "=&r" (cpuid));
+           See btfixup.h and btfixupprep.c to understand how a blackbox works.
+         */
+        __asm__ __volatile__("sethi %%hi(___b_hard_smp_processor_id), %0\n\t"
+                             "sethi %%hi(boot_cpu_id), %0\n\t"
+                             "ldub [%0 + %%lo(boot_cpu_id)], %0\n\t" :
+                             "=&r" (cpuid));
+        return cpuid;
+}
+#else
+static inline int hard_smp_processor_id(void)
+{
+        int cpuid;
+
+        __asm__ __volatile__("mov %%o7, %%g1\n\t"
+                             "call ___f___hard_smp_processor_id\n\t"
+                             " nop\n\t"
+                             "mov %%g2, %0\n\t" : "=r"(cpuid) : : "g1", "g2");
+        return cpuid;
+}
+#endif
+
+#define raw_smp_processor_id()          (current_thread_info()->cpu)
+
+#define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
+#define prof_counter(__cpu)             cpu_data(__cpu).counter
+
+void smp_setup_cpu_possible_map(void);
+
+#endif /* !(__ASSEMBLY__) */
+
+/* Sparc specific messages. */
+#define MSG_CROSS_CALL         0x0005       /* run func on cpus */
+
+/* Empirical PROM processor mailbox constants.  If the per-cpu mailbox
+ * contains something other than one of these then the ipi is from
+ * Linux's active_kernel_processor.  This facility exists so that
+ * the boot monitor can capture all the other cpus when one catches
+ * a watchdog reset or the user enters the monitor using L1-A keys.
+ */
+#define MBOX_STOPCPU          0xFB
+#define MBOX_IDLECPU          0xFC
+#define MBOX_IDLECPU2         0xFD
+#define MBOX_STOPCPU2         0xFE
+
+#else /* SMP */
+
+#define hard_smp_processor_id()         0
+#define smp_setup_cpu_possible_map() do { } while (0)
+
+#endif /* !(SMP) */
+
+#define NO_PROC_ID            0xFF
+
+#endif /* !(_SPARC_SMP_H) */
diff --git a/arch/sparc/include/asm/smp_64.h b/arch/sparc/include/asm/smp_64.h
new file mode 100644
index 000000000000..57224dd37b3a
--- /dev/null
+++ b/arch/sparc/include/asm/smp_64.h
@@ -0,0 +1,67 @@
+/* smp.h: Sparc64 specific SMP stuff.
+ *
+ * Copyright (C) 1996, 2008 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_SMP_H
+#define _SPARC64_SMP_H
+
+#include <linux/threads.h>
+#include <asm/asi.h>
+#include <asm/starfire.h>
+#include <asm/spitfire.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/cpumask.h>
+#include <linux/cache.h>
+
+#endif /* !(__ASSEMBLY__) */
+
+#ifdef CONFIG_SMP
+
+#ifndef __ASSEMBLY__
+
+/*
+ *      Private routines/data
+ */
+
+#include <linux/bitops.h>
+#include <asm/atomic.h>
+#include <asm/percpu.h>
+
+DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
+extern cpumask_t cpu_core_map[NR_CPUS];
+extern int sparc64_multi_core;
+
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
+/*
+ *      General functions that each host system must provide.
+ */
+
+extern int hard_smp_processor_id(void);
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+extern void smp_fill_in_sib_core_maps(void);
+extern void cpu_play_dead(void);
+
+extern void smp_fetch_global_regs(void);
+
+#ifdef CONFIG_HOTPLUG_CPU
+extern int __cpu_disable(void);
+extern void __cpu_die(unsigned int cpu);
+#endif
+
+#endif /* !(__ASSEMBLY__) */
+
+#else
+
+#define hard_smp_processor_id()         0
+#define smp_fill_in_sib_core_maps() do { } while (0)
+#define smp_fetch_global_regs() do { } while (0)
+
+#endif /* !(CONFIG_SMP) */
+
+#endif /* !(_SPARC64_SMP_H) */
diff --git a/arch/sparc/include/asm/smpprim.h b/arch/sparc/include/asm/smpprim.h
new file mode 100644
index 000000000000..eb849d862c64
--- /dev/null
+++ b/arch/sparc/include/asm/smpprim.h
@@ -0,0 +1,54 @@
+/*
+ *  smpprim.h:  SMP locking primitives on the Sparc
+ *
+ *  God knows we won't be actually using this code for some time
+ *  but I thought I'd write it since I knew how.
+ *
+ *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_SMPPRIM_H
+#define __SPARC_SMPPRIM_H
+
+/* Test and set the unsigned byte at ADDR to 1.  Returns the previous
+ * value.  On the Sparc we use the ldstub instruction since it is
+ * atomic.
+ */
+
+static inline __volatile__ char test_and_set(void *addr)
+{
+        char state = 0;
+
+        __asm__ __volatile__("ldstub [%0], %1         ! test_and_set\n\t"
+                             "=r" (addr), "=r" (state) :
+                             "0" (addr), "1" (state) : "memory");
+
+        return state;
+}
+
+/* Initialize a spin-lock. */
+static inline __volatile__ smp_initlock(void *spinlock)
+{
+        /* Unset the lock. */
+        *((unsigned char *) spinlock) = 0;
+
+        return;
+}
+
+/* This routine spins until it acquires the lock at ADDR. */
+static inline __volatile__ smp_lock(void *addr)
+{
+        while(test_and_set(addr) == 0xff)
+                ;
+
+        /* We now have the lock */
+        return;
+}
+
+/* This routine releases the lock at ADDR. */
+static inline __volatile__ smp_unlock(void *addr)
+{
+        *((unsigned char *) addr) = 0;
+}
+
+#endif /* !(__SPARC_SMPPRIM_H) */
diff --git a/arch/sparc/include/asm/socket.h b/arch/sparc/include/asm/socket.h
new file mode 100644
index 000000000000..bf50d0c2d583
--- /dev/null
+++ b/arch/sparc/include/asm/socket.h
@@ -0,0 +1,58 @@
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      0xffff
+
+#define SO_DEBUG        0x0001
+#define SO_PASSCRED     0x0002
+#define SO_REUSEADDR    0x0004
+#define SO_KEEPALIVE    0x0008
+#define SO_DONTROUTE    0x0010
+#define SO_BROADCAST    0x0020
+#define SO_PEERCRED     0x0040
+#define SO_LINGER       0x0080
+#define SO_OOBINLINE    0x0100
+/* To add :#define SO_REUSEPORT 0x0200 */
+#define SO_BSDCOMPAT    0x0400
+#define SO_RCVLOWAT     0x0800
+#define SO_SNDLOWAT     0x1000
+#define SO_RCVTIMEO     0x2000
+#define SO_SNDTIMEO     0x4000
+#define SO_ACCEPTCONN   0x8000
+
+#define SO_SNDBUF       0x1001
+#define SO_RCVBUF       0x1002
+#define SO_SNDBUFFORCE  0x100a
+#define SO_RCVBUFFORCE  0x100b
+#define SO_ERROR        0x1007
+#define SO_TYPE         0x1008
+
+/* Linux specific, keep the same. */
+#define SO_NO_CHECK     0x000b
+#define SO_PRIORITY     0x000c
+
+#define SO_BINDTODEVICE 0x000d
+
+#define SO_ATTACH_FILTER        0x001a
+#define SO_DETACH_FILTER        0x001b
+
+#define SO_PEERNAME             0x001c
+#define SO_TIMESTAMP            0x001d
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_PEERSEC              0x001e
+#define SO_PASSSEC              0x001f
+#define SO_TIMESTAMPNS          0x0021
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 0x0022
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              0x5001
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        0x5002
+#define SO_SECURITY_ENCRYPTION_NETWORK          0x5004
+
+#endif /* _ASM_SOCKET_H */
diff --git a/arch/sparc/include/asm/sockios.h b/arch/sparc/include/asm/sockios.h
new file mode 100644
index 000000000000..990ea746486b
--- /dev/null
+++ b/arch/sparc/include/asm/sockios.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_SPARC_SOCKIOS_H
+#define _ASM_SPARC_SOCKIOS_H
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif /* !(_ASM_SPARC_SOCKIOS_H) */
+
diff --git a/arch/sparc/include/asm/sparsemem.h b/arch/sparc/include/asm/sparsemem.h
new file mode 100644
index 000000000000..b99d4e4b6d28
--- /dev/null
+++ b/arch/sparc/include/asm/sparsemem.h
@@ -0,0 +1,12 @@
+#ifndef _SPARC64_SPARSEMEM_H
+#define _SPARC64_SPARSEMEM_H
+
+#ifdef __KERNEL__
+
+#define SECTION_SIZE_BITS       30
+#define MAX_PHYSADDR_BITS       42
+#define MAX_PHYSMEM_BITS        42
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(_SPARC64_SPARSEMEM_H) */
diff --git a/arch/sparc/include/asm/spinlock.h b/arch/sparc/include/asm/spinlock.h
new file mode 100644
index 000000000000..f276b0036b2c
--- /dev/null
+++ b/arch/sparc/include/asm/spinlock.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SPINLOCK_H
+#define ___ASM_SPARC_SPINLOCK_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/spinlock_64.h>
+#else
+#include <asm/spinlock_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/spinlock_32.h b/arch/sparc/include/asm/spinlock_32.h
new file mode 100644
index 000000000000..de2249b267c6
--- /dev/null
+++ b/arch/sparc/include/asm/spinlock_32.h
@@ -0,0 +1,192 @@
+/* spinlock.h: 32-bit Sparc spinlock support.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_SPINLOCK_H
+#define __SPARC_SPINLOCK_H
+
+#include <linux/threads.h>      /* For NR_CPUS */
+
+#ifndef __ASSEMBLY__
+
+#include <asm/psr.h>
+
+#define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
+
+#define __raw_spin_unlock_wait(lock) \
+        do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+        __asm__ __volatile__(
+        "\n1:\n\t"
+        "ldstub [%0], %%g2\n\t"
+        "orcc   %%g2, 0x0, %%g0\n\t"
+        "bne,a  2f\n\t"
+        " ldub  [%0], %%g2\n\t"
+        ".subsection    2\n"
+        "2:\n\t"
+        "orcc   %%g2, 0x0, %%g0\n\t"
+        "bne,a  2b\n\t"
+        " ldub  [%0], %%g2\n\t"
+        "b,a    1b\n\t"
+        ".previous\n"
+        : /* no outputs */
+        : "r" (lock)
+        : "g2", "memory", "cc");
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+        unsigned int result;
+        __asm__ __volatile__("ldstub [%1], %0"
+                             : "=r" (result)
+                             : "r" (lock)
+                             : "memory");
+        return (result == 0);
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+        __asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
+}
+
+/* Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ *
+ * XXX This might create some problems with my dual spinlock
+ * XXX scheme, deadlocks etc. -DaveM
+ *
+ * Sort of like atomic_t's on Sparc, but even more clever.
+ *
+ *      ------------------------------------
+ *      | 24-bit counter           | wlock |  raw_rwlock_t
+ *      ------------------------------------
+ *       31                       8 7     0
+ *
+ * wlock signifies the one writer is in or somebody is updating
+ * counter. For a writer, if he successfully acquires the wlock,
+ * but counter is non-zero, he has to release the lock and wait,
+ * till both counter and wlock are zero.
+ *
+ * Unfortunately this scheme limits us to ~16,000,000 cpus.
+ */
+static inline void __read_lock(raw_rwlock_t *rw)
+{
+        register raw_rwlock_t *lp asm("g1");
+        lp = rw;
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___rw_read_enter\n\t"
+        " ldstub        [%%g1 + 3], %%g2\n"
+        : /* no outputs */
+        : "r" (lp)
+        : "g2", "g4", "memory", "cc");
+}
+
+#define __raw_read_lock(lock) \
+do {    unsigned long flags; \
+        local_irq_save(flags); \
+        __read_lock(lock); \
+        local_irq_restore(flags); \
+} while(0)
+
+static inline void __read_unlock(raw_rwlock_t *rw)
+{
+        register raw_rwlock_t *lp asm("g1");
+        lp = rw;
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___rw_read_exit\n\t"
+        " ldstub        [%%g1 + 3], %%g2\n"
+        : /* no outputs */
+        : "r" (lp)
+        : "g2", "g4", "memory", "cc");
+}
+
+#define __raw_read_unlock(lock) \
+do {    unsigned long flags; \
+        local_irq_save(flags); \
+        __read_unlock(lock); \
+        local_irq_restore(flags); \
+} while(0)
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+        register raw_rwlock_t *lp asm("g1");
+        lp = rw;
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___rw_write_enter\n\t"
+        " ldstub        [%%g1 + 3], %%g2\n"
+        : /* no outputs */
+        : "r" (lp)
+        : "g2", "g4", "memory", "cc");
+        *(volatile __u32 *)&lp->lock = ~0U;
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+        unsigned int val;
+
+        __asm__ __volatile__("ldstub [%1 + 3], %0"
+                             : "=r" (val)
+                             : "r" (&rw->lock)
+                             : "memory");
+
+        if (val == 0) {
+                val = rw->lock & ~0xff;
+                if (val)
+                        ((volatile u8*)&rw->lock)[3] = 0;
+                else
+                        *(volatile u32*)&rw->lock = ~0U;
+        }
+
+        return (val == 0);
+}
+
+static inline int __read_trylock(raw_rwlock_t *rw)
+{
+        register raw_rwlock_t *lp asm("g1");
+        register int res asm("o0");
+        lp = rw;
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___rw_read_try\n\t"
+        " ldstub        [%%g1 + 3], %%g2\n"
+        : "=r" (res)
+        : "r" (lp)
+        : "g2", "g4", "memory", "cc");
+        return res;
+}
+
+#define __raw_read_trylock(lock) \
+({      unsigned long flags; \
+        int res; \
+        local_irq_save(flags); \
+        res = __read_trylock(lock); \
+        local_irq_restore(flags); \
+        res; \
+})
+
+#define __raw_write_unlock(rw)  do { (rw)->lock = 0; } while(0)
+
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+
+#define _raw_spin_relax(lock)   cpu_relax()
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
+#define __raw_write_can_lock(rw) (!(rw)->lock)
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* __SPARC_SPINLOCK_H */
diff --git a/arch/sparc/include/asm/spinlock_64.h b/arch/sparc/include/asm/spinlock_64.h
new file mode 100644
index 000000000000..0006fe9f8c7a
--- /dev/null
+++ b/arch/sparc/include/asm/spinlock_64.h
@@ -0,0 +1,250 @@
+/* spinlock.h: 64-bit Sparc spinlock support.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC64_SPINLOCK_H
+#define __SPARC64_SPINLOCK_H
+
+#include <linux/threads.h>      /* For NR_CPUS */
+
+#ifndef __ASSEMBLY__
+
+/* To get debugging spinlocks which detect and catch
+ * deadlock situations, set CONFIG_DEBUG_SPINLOCK
+ * and rebuild your kernel.
+ */
+
+/* All of these locking primitives are expected to work properly
+ * even in an RMO memory model, which currently is what the kernel
+ * runs in.
+ *
+ * There is another issue.  Because we play games to save cycles
+ * in the non-contention case, we need to be extra careful about
+ * branch targets into the "spinning" code.  They live in their
+ * own section, but the newer V9 branches have a shorter range
+ * than the traditional 32-bit sparc branch variants.  The rule
+ * is that the branches that go into and out of the spinner sections
+ * must be pre-V9 branches.
+ */
+
+#define __raw_spin_is_locked(lp)        ((lp)->lock != 0)
+
+#define __raw_spin_unlock_wait(lp)      \
+        do {    rmb();                  \
+        } while((lp)->lock)
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__(
+"1:     ldstub          [%1], %0\n"
+"       membar          #StoreLoad | #StoreStore\n"
+"       brnz,pn         %0, 2f\n"
+"        nop\n"
+"       .subsection     2\n"
+"2:     ldub            [%1], %0\n"
+"       membar          #LoadLoad\n"
+"       brnz,pt         %0, 2b\n"
+"        nop\n"
+"       ba,a,pt         %%xcc, 1b\n"
+"       .previous"
+        : "=&r" (tmp)
+        : "r" (lock)
+        : "memory");
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+        unsigned long result;
+
+        __asm__ __volatile__(
+"       ldstub          [%1], %0\n"
+"       membar          #StoreLoad | #StoreStore"
+        : "=r" (result)
+        : "r" (lock)
+        : "memory");
+
+        return (result == 0UL);
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+        __asm__ __volatile__(
+"       membar          #StoreStore | #LoadStore\n"
+"       stb             %%g0, [%0]"
+        : /* No outputs */
+        : "r" (lock)
+        : "memory");
+}
+
+static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
+{
+        unsigned long tmp1, tmp2;
+
+        __asm__ __volatile__(
+"1:     ldstub          [%2], %0\n"
+"       membar          #StoreLoad | #StoreStore\n"
+"       brnz,pn         %0, 2f\n"
+"        nop\n"
+"       .subsection     2\n"
+"2:     rdpr            %%pil, %1\n"
+"       wrpr            %3, %%pil\n"
+"3:     ldub            [%2], %0\n"
+"       membar          #LoadLoad\n"
+"       brnz,pt         %0, 3b\n"
+"        nop\n"
+"       ba,pt           %%xcc, 1b\n"
+"        wrpr           %1, %%pil\n"
+"       .previous"
+        : "=&r" (tmp1), "=&r" (tmp2)
+        : "r"(lock), "r"(flags)
+        : "memory");
+}
+
+/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
+
+static void inline __read_lock(raw_rwlock_t *lock)
+{
+        unsigned long tmp1, tmp2;
+
+        __asm__ __volatile__ (
+"1:     ldsw            [%2], %0\n"
+"       brlz,pn         %0, 2f\n"
+"4:      add            %0, 1, %1\n"
+"       cas             [%2], %0, %1\n"
+"       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
+"       bne,pn          %%icc, 1b\n"
+"        nop\n"
+"       .subsection     2\n"
+"2:     ldsw            [%2], %0\n"
+"       membar          #LoadLoad\n"
+"       brlz,pt         %0, 2b\n"
+"        nop\n"
+"       ba,a,pt         %%xcc, 4b\n"
+"       .previous"
+        : "=&r" (tmp1), "=&r" (tmp2)
+        : "r" (lock)
+        : "memory");
+}
+
+static int inline __read_trylock(raw_rwlock_t *lock)
+{
+        int tmp1, tmp2;
+
+        __asm__ __volatile__ (
+"1:     ldsw            [%2], %0\n"
+"       brlz,a,pn       %0, 2f\n"
+"        mov            0, %0\n"
+"       add             %0, 1, %1\n"
+"       cas             [%2], %0, %1\n"
+"       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
+"       bne,pn          %%icc, 1b\n"
+"        mov            1, %0\n"
+"2:"
+        : "=&r" (tmp1), "=&r" (tmp2)
+        : "r" (lock)
+        : "memory");
+
+        return tmp1;
+}
+
+static void inline __read_unlock(raw_rwlock_t *lock)
+{
+        unsigned long tmp1, tmp2;
+
+        __asm__ __volatile__(
+"       membar  #StoreLoad | #LoadLoad\n"
+"1:     lduw    [%2], %0\n"
+"       sub     %0, 1, %1\n"
+"       cas     [%2], %0, %1\n"
+"       cmp     %0, %1\n"
+"       bne,pn  %%xcc, 1b\n"
+"        nop"
+        : "=&r" (tmp1), "=&r" (tmp2)
+        : "r" (lock)
+        : "memory");
+}
+
+static void inline __write_lock(raw_rwlock_t *lock)
+{
+        unsigned long mask, tmp1, tmp2;
+
+        mask = 0x80000000UL;
+
+        __asm__ __volatile__(
+"1:     lduw            [%2], %0\n"
+"       brnz,pn         %0, 2f\n"
+"4:      or             %0, %3, %1\n"
+"       cas             [%2], %0, %1\n"
+"       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
+"       bne,pn          %%icc, 1b\n"
+"        nop\n"
+"       .subsection     2\n"
+"2:     lduw            [%2], %0\n"
+"       membar          #LoadLoad\n"
+"       brnz,pt         %0, 2b\n"
+"        nop\n"
+"       ba,a,pt         %%xcc, 4b\n"
+"       .previous"
+        : "=&r" (tmp1), "=&r" (tmp2)
+        : "r" (lock), "r" (mask)
+        : "memory");
+}
+
+static void inline __write_unlock(raw_rwlock_t *lock)
+{
+        __asm__ __volatile__(
+"       membar          #LoadStore | #StoreStore\n"
+"       stw             %%g0, [%0]"
+        : /* no outputs */
+        : "r" (lock)
+        : "memory");
+}
+
+static int inline __write_trylock(raw_rwlock_t *lock)
+{
+        unsigned long mask, tmp1, tmp2, result;
+
+        mask = 0x80000000UL;
+
+        __asm__ __volatile__(
+"       mov             0, %2\n"
+"1:     lduw            [%3], %0\n"
+"       brnz,pn         %0, 2f\n"
+"        or             %0, %4, %1\n"
+"       cas             [%3], %0, %1\n"
+"       cmp             %0, %1\n"
+"       membar          #StoreLoad | #StoreStore\n"
+"       bne,pn          %%icc, 1b\n"
+"        nop\n"
+"       mov             1, %2\n"
+"2:"
+        : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result)
+        : "r" (lock), "r" (mask)
+        : "memory");
+
+        return result;
+}
+
+#define __raw_read_lock(p)      __read_lock(p)
+#define __raw_read_trylock(p)   __read_trylock(p)
+#define __raw_read_unlock(p)    __read_unlock(p)
+#define __raw_write_lock(p)     __write_lock(p)
+#define __raw_write_unlock(p)   __write_unlock(p)
+#define __raw_write_trylock(p)  __write_trylock(p)
+
+#define __raw_read_can_lock(rw)         (!((rw)->lock & 0x80000000UL))
+#define __raw_write_can_lock(rw)        (!(rw)->lock)
+
+#define _raw_spin_relax(lock)   cpu_relax()
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC64_SPINLOCK_H) */
diff --git a/arch/sparc/include/asm/spinlock_types.h b/arch/sparc/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..37cbe01c585b
--- /dev/null
+++ b/arch/sparc/include/asm/spinlock_types.h
@@ -0,0 +1,20 @@
+#ifndef __SPARC_SPINLOCK_TYPES_H
+#define __SPARC_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        volatile unsigned char lock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_rwlock_t;
+
+#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+
+#endif
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
new file mode 100644
index 000000000000..985ea7e31992
--- /dev/null
+++ b/arch/sparc/include/asm/spitfire.h
@@ -0,0 +1,342 @@
+/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_SPITFIRE_H
+#define _SPARC64_SPITFIRE_H
+
+#include <asm/asi.h>
+
+/* The following register addresses are accessible via ASI_DMMU
+ * and ASI_IMMU, that is there is a distinct and unique copy of
+ * each these registers for each TLB.
+ */
+#define TSB_TAG_TARGET          0x0000000000000000 /* All chips                         */
+#define TLB_SFSR                0x0000000000000018 /* All chips                         */
+#define TSB_REG                 0x0000000000000028 /* All chips                         */
+#define TLB_TAG_ACCESS          0x0000000000000030 /* All chips                         */
+#define VIRT_WATCHPOINT         0x0000000000000038 /* All chips                         */
+#define PHYS_WATCHPOINT         0x0000000000000040 /* All chips                         */
+#define TSB_EXTENSION_P         0x0000000000000048 /* Ultra-III and later               */
+#define TSB_EXTENSION_S         0x0000000000000050 /* Ultra-III and later, D-TLB only   */
+#define TSB_EXTENSION_N         0x0000000000000058 /* Ultra-III and later               */
+#define TLB_TAG_ACCESS_EXT      0x0000000000000060 /* Ultra-III+ and later              */
+
+/* These registers only exist as one entity, and are accessed
+ * via ASI_DMMU only.
+ */
+#define PRIMARY_CONTEXT         0x0000000000000008
+#define SECONDARY_CONTEXT       0x0000000000000010
+#define DMMU_SFAR               0x0000000000000020
+#define VIRT_WATCHPOINT         0x0000000000000038
+#define PHYS_WATCHPOINT         0x0000000000000040
+
+#define SPITFIRE_HIGHEST_LOCKED_TLBENT  (64 - 1)
+#define CHEETAH_HIGHEST_LOCKED_TLBENT   (16 - 1)
+
+#define L1DCACHE_SIZE           0x4000
+
+#define SUN4V_CHIP_INVALID      0x00
+#define SUN4V_CHIP_NIAGARA1     0x01
+#define SUN4V_CHIP_NIAGARA2     0x02
+#define SUN4V_CHIP_UNKNOWN      0xff
+
+#ifndef __ASSEMBLY__
+
+enum ultra_tlb_layout {
+        spitfire = 0,
+        cheetah = 1,
+        cheetah_plus = 2,
+        hypervisor = 3,
+};
+
+extern enum ultra_tlb_layout tlb_type;
+
+extern int sun4v_chip_type;
+
+extern int cheetah_pcache_forced_on;
+extern void cheetah_enable_pcache(void);
+
+#define sparc64_highest_locked_tlbent() \
+        (tlb_type == spitfire ? \
+         SPITFIRE_HIGHEST_LOCKED_TLBENT : \
+         CHEETAH_HIGHEST_LOCKED_TLBENT)
+
+extern int num_kernel_image_mappings;
+
+/* The data cache is write through, so this just invalidates the
+ * specified line.
+ */
+static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
+}
+
+/* The instruction cache lines are flushed with this, but note that
+ * this does not flush the pipeline.  It is possible for a line to
+ * get flushed but stale instructions to still be in the pipeline,
+ * a flush instruction (to any address) is sufficient to handle
+ * this issue after the line is invalidated.
+ */
+static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
+}
+
+static inline unsigned long spitfire_get_dtlb_data(int entry)
+{
+        unsigned long data;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (data)
+                             : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
+
+        /* Clear TTE diag bits. */
+        data &= ~0x0003fe0000000000UL;
+
+        return data;
+}
+
+static inline unsigned long spitfire_get_dtlb_tag(int entry)
+{
+        unsigned long tag;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (tag)
+                             : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
+        return tag;
+}
+
+static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (data), "r" (entry << 3),
+                               "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+static inline unsigned long spitfire_get_itlb_data(int entry)
+{
+        unsigned long data;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (data)
+                             : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
+
+        /* Clear TTE diag bits. */
+        data &= ~0x0003fe0000000000UL;
+
+        return data;
+}
+
+static inline unsigned long spitfire_get_itlb_tag(int entry)
+{
+        unsigned long tag;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (tag)
+                             : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
+        return tag;
+}
+
+static inline void spitfire_put_itlb_data(int entry, unsigned long data)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (data), "r" (entry << 3),
+                               "i" (ASI_ITLB_DATA_ACCESS));
+}
+
+static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
+{
+        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
+}
+
+static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
+{
+        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
+}
+
+/* Cheetah has "all non-locked" tlb flushes. */
+static inline void cheetah_flush_dtlb_all(void)
+{
+        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (0x80), "i" (ASI_DMMU_DEMAP));
+}
+
+static inline void cheetah_flush_itlb_all(void)
+{
+        __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (0x80), "i" (ASI_IMMU_DEMAP));
+}
+
+/* Cheetah has a 4-tlb layout so direct access is a bit different.
+ * The first two TLBs are fully assosciative, hold 16 entries, and are
+ * used only for locked and >8K sized translations.  One exists for
+ * data accesses and one for instruction accesses.
+ *
+ * The third TLB is for data accesses to 8K non-locked translations, is
+ * 2 way assosciative, and holds 512 entries.  The fourth TLB is for
+ * instruction accesses to 8K non-locked translations, is 2 way
+ * assosciative, and holds 128 entries.
+ *
+ * Cheetah has some bug where bogus data can be returned from
+ * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
+ * the problem for me. -DaveM
+ */
+static inline unsigned long cheetah_get_ldtlb_data(int entry)
+{
+        unsigned long data;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
+                             "ldxa      [%1] %2, %0"
+                             : "=r" (data)
+                             : "r" ((0 << 16) | (entry << 3)),
+                             "i" (ASI_DTLB_DATA_ACCESS));
+
+        return data;
+}
+
+static inline unsigned long cheetah_get_litlb_data(int entry)
+{
+        unsigned long data;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
+                             "ldxa      [%1] %2, %0"
+                             : "=r" (data)
+                             : "r" ((0 << 16) | (entry << 3)),
+                             "i" (ASI_ITLB_DATA_ACCESS));
+
+        return data;
+}
+
+static inline unsigned long cheetah_get_ldtlb_tag(int entry)
+{
+        unsigned long tag;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (tag)
+                             : "r" ((0 << 16) | (entry << 3)),
+                             "i" (ASI_DTLB_TAG_READ));
+
+        return tag;
+}
+
+static inline unsigned long cheetah_get_litlb_tag(int entry)
+{
+        unsigned long tag;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (tag)
+                             : "r" ((0 << 16) | (entry << 3)),
+                             "i" (ASI_ITLB_TAG_READ));
+
+        return tag;
+}
+
+static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (data),
+                               "r" ((0 << 16) | (entry << 3)),
+                               "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+static inline void cheetah_put_litlb_data(int entry, unsigned long data)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (data),
+                               "r" ((0 << 16) | (entry << 3)),
+                               "i" (ASI_ITLB_DATA_ACCESS));
+}
+
+static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
+{
+        unsigned long data;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
+                             "ldxa      [%1] %2, %0"
+                             : "=r" (data)
+                             : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
+
+        return data;
+}
+
+static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
+{
+        unsigned long tag;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (tag)
+                             : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
+        return tag;
+}
+
+static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (data),
+                               "r" ((tlb << 16) | (entry << 3)),
+                               "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+static inline unsigned long cheetah_get_itlb_data(int entry)
+{
+        unsigned long data;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
+                             "ldxa      [%1] %2, %0"
+                             : "=r" (data)
+                             : "r" ((2 << 16) | (entry << 3)),
+                               "i" (ASI_ITLB_DATA_ACCESS));
+
+        return data;
+}
+
+static inline unsigned long cheetah_get_itlb_tag(int entry)
+{
+        unsigned long tag;
+
+        __asm__ __volatile__("ldxa      [%1] %2, %0"
+                             : "=r" (tag)
+                             : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
+        return tag;
+}
+
+static inline void cheetah_put_itlb_data(int entry, unsigned long data)
+{
+        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
+                             "membar    #Sync"
+                             : /* No outputs */
+                             : "r" (data), "r" ((2 << 16) | (entry << 3)),
+                               "i" (ASI_ITLB_DATA_ACCESS));
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC64_SPITFIRE_H) */
diff --git a/arch/sparc/include/asm/sstate.h b/arch/sparc/include/asm/sstate.h
new file mode 100644
index 000000000000..a7c35dbcb281
--- /dev/null
+++ b/arch/sparc/include/asm/sstate.h
@@ -0,0 +1,13 @@
+#ifndef _SPARC64_SSTATE_H
+#define _SPARC64_SSTATE_H
+
+extern void sstate_booting(void);
+extern void sstate_running(void);
+extern void sstate_halt(void);
+extern void sstate_poweroff(void);
+extern void sstate_panic(void);
+extern void sstate_reboot(void);
+
+extern void sun4v_sstate_init(void);
+
+#endif /* _SPARC64_SSTATE_H */
diff --git a/arch/sparc/include/asm/stacktrace.h b/arch/sparc/include/asm/stacktrace.h
new file mode 100644
index 000000000000..6cee39adf6d6
--- /dev/null
+++ b/arch/sparc/include/asm/stacktrace.h
@@ -0,0 +1,6 @@
+#ifndef _SPARC64_STACKTRACE_H
+#define _SPARC64_STACKTRACE_H
+
+extern void stack_trace_flush(void);
+
+#endif /* _SPARC64_STACKTRACE_H */
diff --git a/arch/sparc/include/asm/starfire.h b/arch/sparc/include/asm/starfire.h
new file mode 100644
index 000000000000..07bafd31e33c
--- /dev/null
+++ b/arch/sparc/include/asm/starfire.h
@@ -0,0 +1,21 @@
+/*
+ * starfire.h: Group all starfire specific code together.
+ *
+ * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
+ */
+
+#ifndef _SPARC64_STARFIRE_H
+#define _SPARC64_STARFIRE_H
+
+#ifndef __ASSEMBLY__
+
+extern int this_is_starfire;
+
+extern void check_if_starfire(void);
+extern void starfire_cpu_setup(void);
+extern int starfire_hard_smp_processor_id(void);
+extern void starfire_hookup(int);
+extern unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
+
+#endif
+#endif
diff --git a/arch/sparc/include/asm/stat.h b/arch/sparc/include/asm/stat.h
new file mode 100644
index 000000000000..d8153013df72
--- /dev/null
+++ b/arch/sparc/include/asm/stat.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_STAT_H
+#define ___ASM_SPARC_STAT_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/stat_64.h>
+#else
+#include <asm/stat_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/stat_32.h b/arch/sparc/include/asm/stat_32.h
new file mode 100644
index 000000000000..2299e1d5d94c
--- /dev/null
+++ b/arch/sparc/include/asm/stat_32.h
@@ -0,0 +1,76 @@
+#ifndef _SPARC_STAT_H
+#define _SPARC_STAT_H
+
+#include <linux/types.h>
+
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+struct stat {
+        unsigned short  st_dev;
+        unsigned long   st_ino;
+        unsigned short  st_mode;
+        short           st_nlink;
+        unsigned short  st_uid;
+        unsigned short  st_gid;
+        unsigned short  st_rdev;
+        long            st_size;
+        long            st_atime;
+        unsigned long   st_atime_nsec;
+        long            st_mtime;
+        unsigned long   st_mtime_nsec;
+        long            st_ctime;
+        unsigned long   st_ctime_nsec;
+        long            st_blksize;
+        long            st_blocks;
+        unsigned long   __unused4[2];
+};
+
+#define STAT_HAVE_NSEC 1
+
+struct stat64 {
+        unsigned long long st_dev;
+
+        unsigned long long st_ino;
+
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned int    st_uid;
+        unsigned int    st_gid;
+
+        unsigned long long st_rdev;
+
+        unsigned char   __pad3[8];
+
+        long long       st_size;
+        unsigned int    st_blksize;
+
+        unsigned char   __pad4[8];
+        unsigned int    st_blocks;
+
+        unsigned int    st_atime;
+        unsigned int    st_atime_nsec;
+
+        unsigned int    st_mtime;
+        unsigned int    st_mtime_nsec;
+
+        unsigned int    st_ctime;
+        unsigned int    st_ctime_nsec;
+
+        unsigned int    __unused4;
+        unsigned int    __unused5;
+};
+
+#endif
diff --git a/arch/sparc/include/asm/stat_64.h b/arch/sparc/include/asm/stat_64.h
new file mode 100644
index 000000000000..9650fdea847f
--- /dev/null
+++ b/arch/sparc/include/asm/stat_64.h
@@ -0,0 +1,47 @@
+#ifndef _SPARC64_STAT_H
+#define _SPARC64_STAT_H
+
+#include <linux/types.h>
+
+struct stat {
+        unsigned   st_dev;
+        ino_t   st_ino;
+        mode_t  st_mode;
+        short   st_nlink;
+        uid_t   st_uid;
+        gid_t   st_gid;
+        unsigned   st_rdev;
+        off_t   st_size;
+        time_t  st_atime;
+        time_t  st_mtime;
+        time_t  st_ctime;
+        off_t   st_blksize;
+        off_t   st_blocks;
+        unsigned long  __unused4[2];
+};
+
+struct stat64 {
+        unsigned long   st_dev;
+        unsigned long   st_ino;
+        unsigned long   st_nlink;
+
+        unsigned int    st_mode;
+        unsigned int    st_uid;
+        unsigned int    st_gid;
+        unsigned int    __pad0;
+
+        unsigned long   st_rdev;
+        long            st_size;
+        long            st_blksize;
+        long            st_blocks;
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+        long            __unused[3];
+};
+
+#endif
diff --git a/arch/sparc/include/asm/statfs.h b/arch/sparc/include/asm/statfs.h
new file mode 100644
index 000000000000..5e937a73743d
--- /dev/null
+++ b/arch/sparc/include/asm/statfs.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_STATFS_H
+#define ___ASM_SPARC_STATFS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/statfs_64.h>
+#else
+#include <asm/statfs_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/statfs_32.h b/arch/sparc/include/asm/statfs_32.h
new file mode 100644
index 000000000000..304520fa8863
--- /dev/null
+++ b/arch/sparc/include/asm/statfs_32.h
@@ -0,0 +1,6 @@
+#ifndef _SPARC_STATFS_H
+#define _SPARC_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif
diff --git a/arch/sparc/include/asm/statfs_64.h b/arch/sparc/include/asm/statfs_64.h
new file mode 100644
index 000000000000..79b3c890a5fa
--- /dev/null
+++ b/arch/sparc/include/asm/statfs_64.h
@@ -0,0 +1,54 @@
+#ifndef _SPARC64_STATFS_H
+#define _SPARC64_STATFS_H
+
+#ifndef __KERNEL_STRICT_NAMES
+
+#include <linux/types.h>
+
+typedef __kernel_fsid_t fsid_t;
+
+#endif
+
+struct statfs {
+        long f_type;
+        long f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        long f_namelen;
+        long f_frsize;
+        long f_spare[5];
+};
+
+struct statfs64 {
+        long f_type;
+        long f_bsize;
+        long f_blocks;
+        long f_bfree;
+        long f_bavail;
+        long f_files;
+        long f_ffree;
+        __kernel_fsid_t f_fsid;
+        long f_namelen;
+        long f_frsize;
+        long f_spare[5];
+};
+
+struct compat_statfs64 {
+        __u32 f_type;
+        __u32 f_bsize;
+        __u64 f_blocks;
+        __u64 f_bfree;
+        __u64 f_bavail;
+        __u64 f_files;
+        __u64 f_ffree;
+        __kernel_fsid_t f_fsid;
+        __u32 f_namelen;
+        __u32 f_frsize;
+        __u32 f_spare[5];
+};
+
+#endif
diff --git a/arch/sparc/include/asm/string.h b/arch/sparc/include/asm/string.h
new file mode 100644
index 000000000000..98b72a0c8e6e
--- /dev/null
+++ b/arch/sparc/include/asm/string.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_STRING_H
+#define ___ASM_SPARC_STRING_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/string_64.h>
+#else
+#include <asm/string_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/string_32.h b/arch/sparc/include/asm/string_32.h
new file mode 100644
index 000000000000..6c5fddb7e6b5
--- /dev/null
+++ b/arch/sparc/include/asm/string_32.h
@@ -0,0 +1,205 @@
+/*
+ * string.h: External definitions for optimized assembly string
+ *           routines for the Linux Kernel.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __SPARC_STRING_H__
+#define __SPARC_STRING_H__
+
+#include <asm/page.h>
+
+/* Really, userland/ksyms should not see any of this stuff. */
+
+#ifdef __KERNEL__
+
+extern void __memmove(void *,const void *,__kernel_size_t);
+extern __kernel_size_t __memcpy(void *,const void *,__kernel_size_t);
+extern __kernel_size_t __memset(void *,int,__kernel_size_t);
+
+#ifndef EXPORT_SYMTAB_STROPS
+
+/* First the mem*() things. */
+#define __HAVE_ARCH_MEMMOVE
+#undef memmove
+#define memmove(_to, _from, _n) \
+({ \
+        void *_t = (_to); \
+        __memmove(_t, (_from), (_n)); \
+        _t; \
+})
+
+#define __HAVE_ARCH_MEMCPY
+
+static inline void *__constant_memcpy(void *to, const void *from, __kernel_size_t n)
+{
+        extern void __copy_1page(void *, const void *);
+
+        if(n <= 32) {
+                __builtin_memcpy(to, from, n);
+        } else if (((unsigned int) to & 7) != 0) {
+                /* Destination is not aligned on the double-word boundary */
+                __memcpy(to, from, n);
+        } else {
+                switch(n) {
+                case PAGE_SIZE:
+                        __copy_1page(to, from);
+                        break;
+                default:
+                        __memcpy(to, from, n);
+                        break;
+                }
+        }
+        return to;
+}
+
+static inline void *__nonconstant_memcpy(void *to, const void *from, __kernel_size_t n)
+{
+        __memcpy(to, from, n);
+        return to;
+}
+
+#undef memcpy
+#define memcpy(t, f, n) \
+(__builtin_constant_p(n) ? \
+ __constant_memcpy((t),(f),(n)) : \
+ __nonconstant_memcpy((t),(f),(n)))
+
+#define __HAVE_ARCH_MEMSET
+
+static inline void *__constant_c_and_count_memset(void *s, char c, __kernel_size_t count)
+{
+        extern void bzero_1page(void *);
+        extern __kernel_size_t __bzero(void *, __kernel_size_t);
+
+        if(!c) {
+                if(count == PAGE_SIZE)
+                        bzero_1page(s);
+                else
+                        __bzero(s, count);
+        } else {
+                __memset(s, c, count);
+        }
+        return s;
+}
+
+static inline void *__constant_c_memset(void *s, char c, __kernel_size_t count)
+{
+        extern __kernel_size_t __bzero(void *, __kernel_size_t);
+
+        if(!c)
+                __bzero(s, count);
+        else
+                __memset(s, c, count);
+        return s;
+}
+
+static inline void *__nonconstant_memset(void *s, char c, __kernel_size_t count)
+{
+        __memset(s, c, count);
+        return s;
+}
+
+#undef memset
+#define memset(s, c, count) \
+(__builtin_constant_p(c) ? (__builtin_constant_p(count) ? \
+                            __constant_c_and_count_memset((s), (c), (count)) : \
+                            __constant_c_memset((s), (c), (count))) \
+                          : __nonconstant_memset((s), (c), (count)))
+
+#define __HAVE_ARCH_MEMSCAN
+
+#undef memscan
+#define memscan(__arg0, __char, __arg2)                                         \
+({                                                                              \
+        extern void *__memscan_zero(void *, size_t);                            \
+        extern void *__memscan_generic(void *, int, size_t);                    \
+        void *__retval, *__addr = (__arg0);                                     \
+        size_t __size = (__arg2);                                               \
+                                                                                \
+        if(__builtin_constant_p(__char) && !(__char))                           \
+                __retval = __memscan_zero(__addr, __size);                      \
+        else                                                                    \
+                __retval = __memscan_generic(__addr, (__char), __size);         \
+                                                                                \
+        __retval;                                                               \
+})
+
+#define __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *,const void *,__kernel_size_t);
+
+/* Now the str*() stuff... */
+#define __HAVE_ARCH_STRLEN
+extern __kernel_size_t strlen(const char *);
+
+#define __HAVE_ARCH_STRNCMP
+
+extern int __strncmp(const char *, const char *, __kernel_size_t);
+
+static inline int __constant_strncmp(const char *src, const char *dest, __kernel_size_t count)
+{
+        register int retval;
+        switch(count) {
+        case 0: return 0;
+        case 1: return (src[0] - dest[0]);
+        case 2: retval = (src[0] - dest[0]);
+                if(!retval && src[0])
+                  retval = (src[1] - dest[1]);
+                return retval;
+        case 3: retval = (src[0] - dest[0]);
+                if(!retval && src[0]) {
+                  retval = (src[1] - dest[1]);
+                  if(!retval && src[1])
+                    retval = (src[2] - dest[2]);
+                }
+                return retval;
+        case 4: retval = (src[0] - dest[0]);
+                if(!retval && src[0]) {
+                  retval = (src[1] - dest[1]);
+                  if(!retval && src[1]) {
+                    retval = (src[2] - dest[2]);
+                    if (!retval && src[2])
+                      retval = (src[3] - dest[3]);
+                  }
+                }
+                return retval;
+        case 5: retval = (src[0] - dest[0]);
+                if(!retval && src[0]) {
+                  retval = (src[1] - dest[1]);
+                  if(!retval && src[1]) {
+                    retval = (src[2] - dest[2]);
+                    if (!retval && src[2]) {
+                      retval = (src[3] - dest[3]);
+                      if (!retval && src[3])
+                        retval = (src[4] - dest[4]);
+                    }
+                  }
+                }
+                return retval;
+        default:
+                retval = (src[0] - dest[0]);
+                if(!retval && src[0]) {
+                  retval = (src[1] - dest[1]);
+                  if(!retval && src[1]) {
+                    retval = (src[2] - dest[2]);
+                    if(!retval && src[2])
+                      retval = __strncmp(src+3,dest+3,count-3);
+                  }
+                }
+                return retval;
+        }
+}
+
+#undef strncmp
+#define strncmp(__arg0, __arg1, __arg2) \
+(__builtin_constant_p(__arg2) ? \
+ __constant_strncmp(__arg0, __arg1, __arg2) : \
+ __strncmp(__arg0, __arg1, __arg2))
+
+#endif /* !EXPORT_SYMTAB_STROPS */
+
+#endif /* __KERNEL__ */
+
+#endif /* !(__SPARC_STRING_H__) */
diff --git a/arch/sparc/include/asm/string_64.h b/arch/sparc/include/asm/string_64.h
new file mode 100644
index 000000000000..43161f2d17eb
--- /dev/null
+++ b/arch/sparc/include/asm/string_64.h
@@ -0,0 +1,83 @@
+/*
+ * string.h: External definitions for optimized assembly string
+ *           routines for the Linux Kernel.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996,1997,1999 Jakub Jelinek (jakub@redhat.com)
+ */
+
+#ifndef __SPARC64_STRING_H__
+#define __SPARC64_STRING_H__
+
+/* Really, userland/ksyms should not see any of this stuff. */
+
+#ifdef __KERNEL__
+
+#include <asm/asi.h>
+
+extern void *__memset(void *,int,__kernel_size_t);
+
+#ifndef EXPORT_SYMTAB_STROPS
+
+/* First the mem*() things. */
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *__builtin_memset(void *,int,__kernel_size_t);
+
+static inline void *__constant_memset(void *s, int c, __kernel_size_t count)
+{
+        extern __kernel_size_t __bzero(void *, __kernel_size_t);
+
+        if (!c) {
+                __bzero(s, count);
+                return s;
+        } else
+                return __memset(s, c, count);
+}
+
+#undef memset
+#define memset(s, c, count) \
+((__builtin_constant_p(count) && (count) <= 32) ? \
+ __builtin_memset((s), (c), (count)) : \
+ (__builtin_constant_p(c) ? \
+  __constant_memset((s), (c), (count)) : \
+  __memset((s), (c), (count))))
+
+#define __HAVE_ARCH_MEMSCAN
+
+#undef memscan
+#define memscan(__arg0, __char, __arg2)                                 \
+({                                                                      \
+        extern void *__memscan_zero(void *, size_t);                    \
+        extern void *__memscan_generic(void *, int, size_t);            \
+        void *__retval, *__addr = (__arg0);                             \
+        size_t __size = (__arg2);                                       \
+                                                                        \
+        if(__builtin_constant_p(__char) && !(__char))                   \
+                __retval = __memscan_zero(__addr, __size);              \
+        else                                                            \
+                __retval = __memscan_generic(__addr, (__char), __size); \
+                                                                        \
+        __retval;                                                       \
+})
+
+#define __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *,const void *,__kernel_size_t);
+
+/* Now the str*() stuff... */
+#define __HAVE_ARCH_STRLEN
+extern __kernel_size_t strlen(const char *);
+
+#define __HAVE_ARCH_STRNCMP
+extern int strncmp(const char *, const char *, __kernel_size_t);
+
+#endif /* !EXPORT_SYMTAB_STROPS */
+
+#endif /* __KERNEL__ */
+
+#endif /* !(__SPARC64_STRING_H__) */
diff --git a/arch/sparc/include/asm/sun4paddr.h b/arch/sparc/include/asm/sun4paddr.h
new file mode 100644
index 000000000000..d52985f19f42
--- /dev/null
+++ b/arch/sparc/include/asm/sun4paddr.h
@@ -0,0 +1,56 @@
+/*
+ * sun4paddr.h:  Various physical addresses on sun4 machines
+ *
+ * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
+ * Copyright (C) 1998 Chris Davis (cdavis@cois.on.ca)
+ * 
+ * Now supports more sun4's
+ */
+
+#ifndef _SPARC_SUN4PADDR_H
+#define _SPARC_SUN4PADDR_H
+
+#define SUN4_IE_PHYSADDR                0xf5000000
+#define SUN4_UNUSED_PHYSADDR            0
+
+/* these work for me */
+#define SUN4_200_MEMREG_PHYSADDR        0xf4000000
+#define SUN4_200_CLOCK_PHYSADDR         0xf3000000
+#define SUN4_200_BWTWO_PHYSADDR         0xfd000000
+#define SUN4_200_ETH_PHYSADDR           0xf6000000
+#define SUN4_200_SI_PHYSADDR            0xff200000
+
+/* these were here before */
+#define SUN4_300_MEMREG_PHYSADDR        0xf4000000
+#define SUN4_300_CLOCK_PHYSADDR         0xf2000000
+#define SUN4_300_TIMER_PHYSADDR         0xef000000
+#define SUN4_300_ETH_PHYSADDR           0xf9000000
+#define SUN4_300_BWTWO_PHYSADDR         0xfb400000
+#define SUN4_300_DMA_PHYSADDR           0xfa001000
+#define SUN4_300_ESP_PHYSADDR           0xfa000000
+
+/* Are these right? */
+#define SUN4_400_MEMREG_PHYSADDR        0xf4000000
+#define SUN4_400_CLOCK_PHYSADDR         0xf2000000
+#define SUN4_400_TIMER_PHYSADDR         0xef000000
+#define SUN4_400_ETH_PHYSADDR           0xf9000000
+#define SUN4_400_BWTWO_PHYSADDR         0xfb400000
+#define SUN4_400_DMA_PHYSADDR           0xfa001000
+#define SUN4_400_ESP_PHYSADDR           0xfa000000
+
+/* 
+        these are the actual values set and used in the code. Unused items set 
+        to SUN_UNUSED_PHYSADDR 
+ */
+
+extern int sun4_memreg_physaddr; /* memory register (ecc?) */
+extern int sun4_clock_physaddr;  /* system clock */
+extern int sun4_timer_physaddr;  /* timer, where applicable */
+extern int sun4_eth_physaddr;    /* onboard ethernet (ie/le) */
+extern int sun4_si_physaddr;     /* sun3 scsi adapter */
+extern int sun4_bwtwo_physaddr;  /* onboard bw2 */
+extern int sun4_dma_physaddr;    /* scsi dma */
+extern int sun4_esp_physaddr;    /* esp scsi */
+extern int sun4_ie_physaddr;     /* interrupt enable */
+
+#endif /* !(_SPARC_SUN4PADDR_H) */
diff --git a/arch/sparc/include/asm/sun4prom.h b/arch/sparc/include/asm/sun4prom.h
new file mode 100644
index 000000000000..9c8b4cbf629a
--- /dev/null
+++ b/arch/sparc/include/asm/sun4prom.h
@@ -0,0 +1,83 @@
+/*
+ * sun4prom.h -- interface to sun4 PROM monitor.  We don't use most of this,
+ *               so most of these are just placeholders.
+ */
+
+#ifndef _SUN4PROM_H_
+#define _SUN4PROM_H_
+
+/*
+ * Although this looks similar to an romvec for a OpenProm machine, it is 
+ * actually closer to what was used in the Sun2 and Sun3.
+ *
+ * V2 entries exist only in version 2 PROMs and later, V3 in version 3 and later.
+ * 
+ * Many of the function prototypes are guesses.  Some are certainly wrong.
+ * Use with care.
+ */
+
+typedef struct {
+        char            *initSP;                /* Initial system stack ptr */
+        void            (*startmon)(void);      /* Initial PC for hardware */
+        int             *diagberr;              /* Bus err handler for diags */
+        struct linux_arguments_v0 **bootParam; /* Info for bootstrapped pgm */
+        unsigned int    *memorysize;            /* Usable memory in bytes */
+        unsigned char   (*getchar)(void);       /* Get char from input device */ 
+        void            (*putchar)(char);       /* Put char to output device */
+        int             (*mayget)(void);        /* Maybe get char, or -1 */
+        int             (*mayput)(int);         /* Maybe put char, or -1 */
+        unsigned char   *echo;                  /* Should getchar echo? */
+        unsigned char   *insource;              /* Input source selector */
+        unsigned char   *outsink;               /* Output sink selector */
+        int             (*getkey)(void);        /* Get next key if one exists */
+        void            (*initgetkey)(void);    /* Initialize get key */
+        unsigned int    *translation;           /* Kbd translation selector */
+        unsigned char   *keybid;                /* Keyboard ID byte */
+        int             *screen_x;              /* V2: Screen x pos (r/o) */
+        int             *screen_y;              /* V2: Screen y pos (r/o) */
+        struct keybuf   *keybuf;                /* Up/down keycode buffer */
+        char            *monid;                 /* Monitor version ID */
+        void            (*fbwritechar)(char);   /* Write a character to FB */
+        int             *fbAddr;                /* Address of frame buffer */
+        char            **font;                 /* Font table for FB */
+        void            (*fbwritestr)(char *);  /* Write string to FB */
+        void            (*reboot)(char *);      /* e.g. reboot("sd()vmlinux") */
+        unsigned char   *linebuf;               /* The line input buffer */
+        unsigned char   **lineptr;              /* Cur pointer into linebuf */
+        int             *linesize;              /* length of line in linebuf */
+        void            (*getline)(char *);     /* Get line from user */
+        unsigned char   (*getnextchar)(void);   /* Get next char from linebuf */
+        unsigned char   (*peeknextchar)(void);  /* Peek at next char */
+        int             *fbthere;               /* =1 if frame buffer there */
+        int             (*getnum)(void);        /* Grab hex num from line */
+        int             (*printf)(char *, ...); /* See prom_printf() instead */ 
+        void            (*printhex)(int);       /* Format N digits in hex */
+        unsigned char   *leds;                  /* RAM copy of LED register */
+        void            (*setLEDs)(unsigned char *);    /* Sets LED's and RAM copy */
+        void            (*NMIaddr)(void *);     /* Addr for level 7 vector */
+        void            (*abortentry)(void);    /* Entry for keyboard abort */
+        int             *nmiclock;              /* Counts up in msec */
+        int             *FBtype;                /* Frame buffer type */
+        unsigned int    romvecversion;          /* Version number for this romvec */
+        struct globram  *globram;               /* monitor global variables ??? */
+        void *          kbdaddr;                /* Addr of keyboard in use */
+        int             *keyrinit;              /* ms before kbd repeat */
+        unsigned char   *keyrtick;              /* ms between repetitions */
+        unsigned int    *memoryavail;           /* V1: Main mem usable size */
+        long            *resetaddr;             /* where to jump on a reset */
+        long            *resetmap;              /* pgmap entry for resetaddr */
+        void            (*exittomon)(void);     /* Exit from user program */
+        unsigned char   **memorybitmap;         /* V1: &{0 or &bits} */
+        void            (*setcxsegmap)(int ctxt, char *va, int pmeg);   /* Set seg in any context */
+        void            (**vector_cmd)(void *); /* V2: Handler for 'v' cmd */
+        unsigned long   *expectedtrapsig;       /* V3: Location of the expected trap signal */
+        unsigned long   *trapvectorbasetable;   /* V3: Address of the trap vector table */
+        int             unused1;
+        int             unused2;
+        int             unused3;
+        int             unused4;
+} linux_sun4_romvec;
+
+extern linux_sun4_romvec *sun4_romvec;
+
+#endif /* _SUN4PROM_H_ */
diff --git a/arch/sparc/include/asm/sunbpp.h b/arch/sparc/include/asm/sunbpp.h
new file mode 100644
index 000000000000..d81a02eaf78b
--- /dev/null
+++ b/arch/sparc/include/asm/sunbpp.h
@@ -0,0 +1,80 @@
+/*
+ * include/asm/sunbpp.h
+ */
+
+#ifndef _ASM_SPARC_SUNBPP_H
+#define _ASM_SPARC_SUNBPP_H
+
+struct bpp_regs {
+  /* DMA registers */
+  __volatile__ __u32 p_csr;             /* DMA Control/Status Register */
+  __volatile__ __u32 p_addr;            /* Address Register */
+  __volatile__ __u32 p_bcnt;            /* Byte Count Register */
+  __volatile__ __u32 p_tst_csr;         /* Test Control/Status (DMA2 only) */
+  /* Parallel Port registers */
+  __volatile__ __u16 p_hcr;             /* Hardware Configuration Register */
+  __volatile__ __u16 p_ocr;             /* Operation Configuration Register */
+  __volatile__ __u8 p_dr;               /* Parallel Data Register */
+  __volatile__ __u8 p_tcr;              /* Transfer Control Register */
+  __volatile__ __u8 p_or;               /* Output Register */
+  __volatile__ __u8 p_ir;               /* Input Register */
+  __volatile__ __u16 p_icr;             /* Interrupt Control Register */
+};
+
+/* P_HCR. Time is in increments of SBus clock. */
+#define P_HCR_TEST      0x8000      /* Allows buried counters to be read */
+#define P_HCR_DSW       0x7f00      /* Data strobe width (in ticks) */
+#define P_HCR_DDS       0x007f      /* Data setup before strobe (in ticks) */
+
+/* P_OCR. */
+#define P_OCR_MEM_CLR   0x8000
+#define P_OCR_DATA_SRC  0x4000      /* )                  */
+#define P_OCR_DS_DSEL   0x2000      /* )  Bidirectional      */
+#define P_OCR_BUSY_DSEL 0x1000      /* )    selects            */
+#define P_OCR_ACK_DSEL  0x0800      /* )                  */
+#define P_OCR_EN_DIAG   0x0400
+#define P_OCR_BUSY_OP   0x0200      /* Busy operation */
+#define P_OCR_ACK_OP    0x0100      /* Ack operation */
+#define P_OCR_SRST      0x0080      /* Reset state machines. Not selfcleaning. */
+#define P_OCR_IDLE      0x0008      /* PP data transfer state machine is idle */
+#define P_OCR_V_ILCK    0x0002      /* Versatec faded. Zebra only. */
+#define P_OCR_EN_VER    0x0001      /* Enable Versatec (0 - enable). Zebra only. */
+
+/* P_TCR */
+#define P_TCR_DIR       0x08
+#define P_TCR_BUSY      0x04
+#define P_TCR_ACK       0x02
+#define P_TCR_DS        0x01        /* Strobe */
+
+/* P_OR */
+#define P_OR_V3         0x20        /* )                 */
+#define P_OR_V2         0x10        /* ) on Zebra only   */
+#define P_OR_V1         0x08        /* )                 */
+#define P_OR_INIT       0x04
+#define P_OR_AFXN       0x02        /* Auto Feed */
+#define P_OR_SLCT_IN    0x01
+
+/* P_IR */
+#define P_IR_PE         0x04
+#define P_IR_SLCT       0x02
+#define P_IR_ERR        0x01
+
+/* P_ICR */
+#define P_DS_IRQ        0x8000      /* RW1  */
+#define P_ACK_IRQ       0x4000      /* RW1  */
+#define P_BUSY_IRQ      0x2000      /* RW1  */
+#define P_PE_IRQ        0x1000      /* RW1  */
+#define P_SLCT_IRQ      0x0800      /* RW1  */
+#define P_ERR_IRQ       0x0400      /* RW1  */
+#define P_DS_IRQ_EN     0x0200      /* RW   Always on rising edge */
+#define P_ACK_IRQ_EN    0x0100      /* RW   Always on rising edge */
+#define P_BUSY_IRP      0x0080      /* RW   1= rising edge */
+#define P_BUSY_IRQ_EN   0x0040      /* RW   */
+#define P_PE_IRP        0x0020      /* RW   1= rising edge */
+#define P_PE_IRQ_EN     0x0010      /* RW   */
+#define P_SLCT_IRP      0x0008      /* RW   1= rising edge */
+#define P_SLCT_IRQ_EN   0x0004      /* RW   */
+#define P_ERR_IRP       0x0002      /* RW1  1= rising edge */
+#define P_ERR_IRQ_EN    0x0001      /* RW   */
+
+#endif /* !(_ASM_SPARC_SUNBPP_H) */
diff --git a/arch/sparc/include/asm/swift.h b/arch/sparc/include/asm/swift.h
new file mode 100644
index 000000000000..e535061bf755
--- /dev/null
+++ b/arch/sparc/include/asm/swift.h
@@ -0,0 +1,106 @@
+/* swift.h: Specific definitions for the _broken_ Swift SRMMU
+ *          MMU module.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SWIFT_H
+#define _SPARC_SWIFT_H
+
+/* Swift is so brain damaged, here is the mmu control register. */
+#define SWIFT_ST       0x00800000   /* SW tablewalk enable */
+#define SWIFT_WP       0x00400000   /* Watchpoint enable   */
+
+/* Branch folding (buggy, disable on production systems!)  */
+#define SWIFT_BF       0x00200000
+#define SWIFT_PMC      0x00180000   /* Page mode control   */
+#define SWIFT_PE       0x00040000   /* Parity enable       */
+#define SWIFT_PC       0x00020000   /* Parity control      */
+#define SWIFT_AP       0x00010000   /* Graphics page mode control (TCX/SX) */
+#define SWIFT_AC       0x00008000   /* Alternate Cacheability (see viking.h) */
+#define SWIFT_BM       0x00004000   /* Boot mode */
+#define SWIFT_RC       0x00003c00   /* DRAM refresh control */
+#define SWIFT_IE       0x00000200   /* Instruction cache enable */
+#define SWIFT_DE       0x00000100   /* Data cache enable */
+#define SWIFT_SA       0x00000080   /* Store Allocate */
+#define SWIFT_NF       0x00000002   /* No fault mode */
+#define SWIFT_EN       0x00000001   /* MMU enable */
+
+/* Bits [13:5] select one of 512 instruction cache tags */
+static inline void swift_inv_insn_tag(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (addr), "i" (ASI_M_TXTC_TAG)
+                             : "memory");
+}
+
+/* Bits [12:4] select one of 512 data cache tags */
+static inline void swift_inv_data_tag(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (addr), "i" (ASI_M_DATAC_TAG)
+                             : "memory");
+}
+
+static inline void swift_flush_dcache(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < 0x2000; addr += 0x10)
+                swift_inv_data_tag(addr);
+}
+
+static inline void swift_flush_icache(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < 0x4000; addr += 0x20)
+                swift_inv_insn_tag(addr);
+}
+
+static inline void swift_idflash_clear(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < 0x2000; addr += 0x10) {
+                swift_inv_insn_tag(addr<<1);
+                swift_inv_data_tag(addr);
+        }
+}
+
+/* Swift is so broken, it isn't even safe to use the following. */
+static inline void swift_flush_page(unsigned long page)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (page), "i" (ASI_M_FLUSH_PAGE)
+                             : "memory");
+}
+
+static inline void swift_flush_segment(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (addr), "i" (ASI_M_FLUSH_SEG)
+                             : "memory");
+}
+
+static inline void swift_flush_region(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (addr), "i" (ASI_M_FLUSH_REGION)
+                             : "memory");
+}
+
+static inline void swift_flush_context(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+                             : /* no outputs */
+                             : "i" (ASI_M_FLUSH_CTX)
+                             : "memory");
+}
+
+#endif /* !(_SPARC_SWIFT_H) */
diff --git a/arch/sparc/include/asm/syscall.h b/arch/sparc/include/asm/syscall.h
new file mode 100644
index 000000000000..7486c605e23c
--- /dev/null
+++ b/arch/sparc/include/asm/syscall.h
@@ -0,0 +1,120 @@
+#ifndef __ASM_SPARC_SYSCALL_H
+#define __ASM_SPARC_SYSCALL_H
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <asm/ptrace.h>
+
+/* The system call number is given by the user in %g1 */
+static inline long syscall_get_nr(struct task_struct *task,
+                                  struct pt_regs *regs)
+{
+        int syscall_p = pt_regs_is_syscall(regs);
+
+        return (syscall_p ? regs->u_regs[UREG_G1] : -1L);
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        /* XXX This needs some thought.  On Sparc we don't
+         * XXX save away the original %o0 value somewhere.
+         * XXX Instead we hold it in register %l5 at the top
+         * XXX level trap frame and pass this down to the signal
+         * XXX dispatch code which is the only place that value
+         * XXX ever was needed.
+         */
+}
+
+#ifdef CONFIG_SPARC32
+static inline bool syscall_has_error(struct pt_regs *regs)
+{
+        return (regs->psr & PSR_C) ? true : false;
+}
+static inline void syscall_set_error(struct pt_regs *regs)
+{
+        regs->psr |= PSR_C;
+}
+static inline void syscall_clear_error(struct pt_regs *regs)
+{
+        regs->psr &= ~PSR_C;
+}
+#else
+static inline bool syscall_has_error(struct pt_regs *regs)
+{
+        return (regs->tstate & (TSTATE_XCARRY | TSTATE_ICARRY)) ? true : false;
+}
+static inline void syscall_set_error(struct pt_regs *regs)
+{
+        regs->tstate |= (TSTATE_XCARRY | TSTATE_ICARRY);
+}
+static inline void syscall_clear_error(struct pt_regs *regs)
+{
+        regs->tstate &= ~(TSTATE_XCARRY | TSTATE_ICARRY);
+}
+#endif
+
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        long val = regs->u_regs[UREG_I0];
+
+        return (syscall_has_error(regs) ? -val : 0);
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        long val = regs->u_regs[UREG_I0];
+
+        return val;
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        if (error) {
+                syscall_set_error(regs);
+                regs->u_regs[UREG_I0] = -error;
+        } else {
+                syscall_clear_error(regs);
+                regs->u_regs[UREG_I0] = val;
+        }
+}
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+        int zero_extend = 0;
+        unsigned int j;
+
+#ifdef CONFIG_SPARC64
+        if (test_tsk_thread_flag(task, TIF_32BIT))
+                zero_extend = 1;
+#endif
+
+        for (j = 0; j < n; j++) {
+                unsigned long val = regs->u_regs[UREG_I0 + i + j];
+
+                if (zero_extend)
+                        args[j] = (u32) val;
+                else
+                        args[j] = val;
+        }
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        unsigned int j;
+
+        for (j = 0; j < n; j++)
+                regs->u_regs[UREG_I0 + i + j] = args[j];
+}
+
+#endif /* __ASM_SPARC_SYSCALL_H */
diff --git a/arch/sparc/include/asm/syscalls.h b/arch/sparc/include/asm/syscalls.h
new file mode 100644
index 000000000000..45a43f637a14
--- /dev/null
+++ b/arch/sparc/include/asm/syscalls.h
@@ -0,0 +1,13 @@
+#ifndef _SPARC64_SYSCALLS_H
+#define _SPARC64_SYSCALLS_H
+
+struct pt_regs;
+
+extern asmlinkage long sparc_do_fork(unsigned long clone_flags,
+                                     unsigned long stack_start,
+                                     struct pt_regs *regs,
+                                     unsigned long stack_size);
+
+extern asmlinkage int sparc_execve(struct pt_regs *regs);
+
+#endif /* _SPARC64_SYSCALLS_H */
diff --git a/arch/sparc/include/asm/sysen.h b/arch/sparc/include/asm/sysen.h
new file mode 100644
index 000000000000..6af34abde6e7
--- /dev/null
+++ b/arch/sparc/include/asm/sysen.h
@@ -0,0 +1,15 @@
+/*
+ * sysen.h:  Bit fields within the "System Enable" register accessed via
+ *           the ASI_CONTROL address space at address AC_SYSENABLE.
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SYSEN_H
+#define _SPARC_SYSEN_H
+
+#define SENABLE_DVMA   0x20   /* enable dvma transfers */
+#define SENABLE_CACHE  0x10   /* enable VAC cache */
+#define SENABLE_RESET  0x04   /* reset whole machine, danger Will Robinson */
+
+#endif /* _SPARC_SYSEN_H */
diff --git a/arch/sparc/include/asm/system.h b/arch/sparc/include/asm/system.h
new file mode 100644
index 000000000000..7944a7cfc996
--- /dev/null
+++ b/arch/sparc/include/asm/system.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SYSTEM_H
+#define ___ASM_SPARC_SYSTEM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/system_64.h>
+#else
+#include <asm/system_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/system_32.h b/arch/sparc/include/asm/system_32.h
new file mode 100644
index 000000000000..b4b024445fc9
--- /dev/null
+++ b/arch/sparc/include/asm/system_32.h
@@ -0,0 +1,288 @@
+#ifndef __SPARC_SYSTEM_H
+#define __SPARC_SYSTEM_H
+
+#include <linux/kernel.h>
+#include <linux/threads.h>      /* NR_CPUS */
+#include <linux/thread_info.h>
+
+#include <asm/page.h>
+#include <asm/psr.h>
+#include <asm/ptrace.h>
+#include <asm/btfixup.h>
+#include <asm/smp.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+
+/*
+ * Sparc (general) CPU types
+ */
+enum sparc_cpu {
+  sun4        = 0x00,
+  sun4c       = 0x01,
+  sun4m       = 0x02,
+  sun4d       = 0x03,
+  sun4e       = 0x04,
+  sun4u       = 0x05, /* V8 ploos ploos */
+  sun_unknown = 0x06,
+  ap1000      = 0x07, /* almost a sun4m */
+};
+
+/* Really, userland should not be looking at any of this... */
+#ifdef __KERNEL__
+
+extern enum sparc_cpu sparc_cpu_model;
+
+#ifndef CONFIG_SUN4
+#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
+#define ARCH_SUN4 0
+#else
+#define ARCH_SUN4C_SUN4 1
+#define ARCH_SUN4 1
+#endif
+
+#define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
+
+extern char reboot_command[];
+
+extern struct thread_info *current_set[NR_CPUS];
+
+extern unsigned long empty_bad_page;
+extern unsigned long empty_bad_page_table;
+extern unsigned long empty_zero_page;
+
+extern void sun_do_break(void);
+extern int serial_console;
+extern int stop_a_enabled;
+
+static inline int con_is_present(void)
+{
+        return serial_console ? 0 : 1;
+}
+
+/* When a context switch happens we must flush all user windows so that
+ * the windows of the current process are flushed onto its stack. This
+ * way the windows are all clean for the next process and the stack
+ * frames are up to date.
+ */
+extern void flush_user_windows(void);
+extern void kill_user_windows(void);
+extern void synchronize_user_stack(void);
+extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
+                   void *fpqueue, unsigned long *fpqdepth);
+
+#ifdef CONFIG_SMP
+#define SWITCH_ENTER(prv) \
+        do {                    \
+        if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
+                put_psr(get_psr() | PSR_EF); \
+                fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
+                       &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
+                clear_tsk_thread_flag(prv, TIF_USEDFPU); \
+                (prv)->thread.kregs->psr &= ~PSR_EF; \
+        } \
+        } while(0)
+
+#define SWITCH_DO_LAZY_FPU(next)        /* */
+#else
+#define SWITCH_ENTER(prv)               /* */
+#define SWITCH_DO_LAZY_FPU(nxt) \
+        do {                    \
+        if (last_task_used_math != (nxt))               \
+                (nxt)->thread.kregs->psr&=~PSR_EF;      \
+        } while(0)
+#endif
+
+extern void flushw_all(void);
+
+/*
+ * Flush windows so that the VM switch which follows
+ * would not pull the stack from under us.
+ *
+ * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
+ * XXX WTF is the above comment? Found in late teen 2.4.x.
+ */
+#define prepare_arch_switch(next) do { \
+        __asm__ __volatile__( \
+        ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
+        "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
+        "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
+        "save %sp, -0x40, %sp\n\t" \
+        "restore; restore; restore; restore; restore; restore; restore"); \
+} while(0)
+
+        /* Much care has gone into this code, do not touch it.
+         *
+         * We need to loadup regs l0/l1 for the newly forked child
+         * case because the trap return path relies on those registers
+         * holding certain values, gcc is told that they are clobbered.
+         * Gcc needs registers for 3 values in and 1 value out, so we
+         * clobber every non-fixed-usage register besides l2/l3/o4/o5.  -DaveM
+         *
+         * Hey Dave, that do not touch sign is too much of an incentive
+         * - Anton & Pete
+         */
+#define switch_to(prev, next, last) do {                                                \
+        SWITCH_ENTER(prev);                                                             \
+        SWITCH_DO_LAZY_FPU(next);                                                       \
+        cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask);                      \
+        __asm__ __volatile__(                                                           \
+        "sethi  %%hi(here - 0x8), %%o7\n\t"                                             \
+        "mov    %%g6, %%g3\n\t"                                                         \
+        "or     %%o7, %%lo(here - 0x8), %%o7\n\t"                                       \
+        "rd     %%psr, %%g4\n\t"                                                        \
+        "std    %%sp, [%%g6 + %4]\n\t"                                                  \
+        "rd     %%wim, %%g5\n\t"                                                        \
+        "wr     %%g4, 0x20, %%psr\n\t"                                                  \
+        "nop\n\t"                                                                       \
+        "std    %%g4, [%%g6 + %3]\n\t"                                                  \
+        "ldd    [%2 + %3], %%g4\n\t"                                                    \
+        "mov    %2, %%g6\n\t"                                                           \
+        ".globl patchme_store_new_current\n"                                            \
+"patchme_store_new_current:\n\t"                                                        \
+        "st     %2, [%1]\n\t"                                                           \
+        "wr     %%g4, 0x20, %%psr\n\t"                                                  \
+        "nop\n\t"                                                                       \
+        "nop\n\t"                                                                       \
+        "nop\n\t"       /* LEON needs all 3 nops: load to %sp depends on CWP. */                \
+        "ldd    [%%g6 + %4], %%sp\n\t"                                                  \
+        "wr     %%g5, 0x0, %%wim\n\t"                                                   \
+        "ldd    [%%sp + 0x00], %%l0\n\t"                                                \
+        "ldd    [%%sp + 0x38], %%i6\n\t"                                                \
+        "wr     %%g4, 0x0, %%psr\n\t"                                                   \
+        "nop\n\t"                                                                       \
+        "nop\n\t"                                                                       \
+        "jmpl   %%o7 + 0x8, %%g0\n\t"                                                   \
+        " ld    [%%g3 + %5], %0\n\t"                                                    \
+        "here:\n"                                                                       \
+        : "=&r" (last)                                                                  \
+        : "r" (&(current_set[hard_smp_processor_id()])),        \
+          "r" (task_thread_info(next)),                         \
+          "i" (TI_KPSR),                                        \
+          "i" (TI_KSP),                                         \
+          "i" (TI_TASK)                                         \
+        :       "g1", "g2", "g3", "g4", "g5",       "g7",       \
+          "l0", "l1",       "l3", "l4", "l5", "l6", "l7",       \
+          "i0", "i1", "i2", "i3", "i4", "i5",                   \
+          "o0", "o1", "o2", "o3",                   "o7");      \
+        } while(0)
+
+/* XXX Change this if we ever use a PSO mode kernel. */
+#define mb()    __asm__ __volatile__ ("" : : : "memory")
+#define rmb()   mb()
+#define wmb()   mb()
+#define read_barrier_depends()  do { } while(0)
+#define set_mb(__var, __value)  do { __var = __value; mb(); } while(0)
+#define smp_mb()        __asm__ __volatile__("":::"memory")
+#define smp_rmb()       __asm__ __volatile__("":::"memory")
+#define smp_wmb()       __asm__ __volatile__("":::"memory")
+#define smp_read_barrier_depends()      do { } while(0)
+
+#define nop() __asm__ __volatile__ ("nop")
+
+/* This has special calling conventions */
+#ifndef CONFIG_SMP
+BTFIXUPDEF_CALL(void, ___xchg32, void)
+#endif
+
+static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
+{
+#ifdef CONFIG_SMP
+        __asm__ __volatile__("swap [%2], %0"
+                             : "=&r" (val)
+                             : "0" (val), "r" (m)
+                             : "memory");
+        return val;
+#else
+        register unsigned long *ptr asm("g1");
+        register unsigned long ret asm("g2");
+
+        ptr = (unsigned long *) m;
+        ret = val;
+
+        /* Note: this is magic and the nop there is
+           really needed. */
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___f____xchg32\n\t"
+        " nop\n\t"
+        : "=&r" (ret)
+        : "0" (ret), "r" (ptr)
+        : "g3", "g4", "g7", "memory", "cc");
+
+        return ret;
+#endif
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
+{
+        switch (size) {
+        case 4:
+                return xchg_u32(ptr, x);
+        };
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+/* Emulate cmpxchg() the same way we emulate atomics,
+ * by hashing the object address and indexing into an array
+ * of spinlocks to get a bit of performance...
+ *
+ * See arch/sparc/lib/atomic32.c for implementation.
+ *
+ * Cribbed from <asm-parisc/atomic.h>
+ */
+#define __HAVE_ARCH_CMPXCHG     1
+
+/* bug catcher for when unsupported size is used - won't link */
+extern void __cmpxchg_called_with_bad_pointer(void);
+/* we only need to support cmpxchg of a u32 on sparc */
+extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
+
+/* don't worry...optimizer will get rid of most of this */
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
+        default:
+                __cmpxchg_called_with_bad_pointer();
+                break;
+        }
+        return old;
+}
+
+#define cmpxchg(ptr, o, n)                                              \
+({                                                                      \
+        __typeof__(*(ptr)) _o_ = (o);                                   \
+        __typeof__(*(ptr)) _n_ = (n);                                   \
+        (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,       \
+                        (unsigned long)_n_, sizeof(*(ptr)));            \
+})
+
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)                                               \
+        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+                        (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* !(__SPARC_SYSTEM_H) */
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
new file mode 100644
index 000000000000..db9e742a406a
--- /dev/null
+++ b/arch/sparc/include/asm/system_64.h
@@ -0,0 +1,355 @@
+#ifndef __SPARC64_SYSTEM_H
+#define __SPARC64_SYSTEM_H
+
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/visasm.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * Sparc (general) CPU types
+ */
+enum sparc_cpu {
+  sun4        = 0x00,
+  sun4c       = 0x01,
+  sun4m       = 0x02,
+  sun4d       = 0x03,
+  sun4e       = 0x04,
+  sun4u       = 0x05, /* V8 ploos ploos */
+  sun_unknown = 0x06,
+  ap1000      = 0x07, /* almost a sun4m */
+};
+
+#define sparc_cpu_model sun4u
+
+/* This cannot ever be a sun4c nor sun4 :) That's just history. */
+#define ARCH_SUN4C_SUN4 0
+#define ARCH_SUN4 0
+
+extern char reboot_command[];
+
+/* These are here in an effort to more fully work around Spitfire Errata
+ * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
+ * branch, the chip can stop executing instructions until a trap occurs.
+ * Therefore, if interrupts are disabled, the chip can hang forever.
+ *
+ * It used to be believed that the memory barrier had to be right in the
+ * delay slot, but a case has been traced recently wherein the memory barrier
+ * was one instruction after the branch delay slot and the chip still hung.
+ * The offending sequence was the following in sym_wakeup_done() of the
+ * sym53c8xx_2 driver:
+ *
+ *      call    sym_ccb_from_dsa, 0
+ *       movge  %icc, 0, %l0
+ *      brz,pn  %o0, .LL1303
+ *       mov    %o0, %l2
+ *      membar  #LoadLoad
+ *
+ * The branch has to be mispredicted for the bug to occur.  Therefore, we put
+ * the memory barrier explicitly into a "branch always, predicted taken"
+ * delay slot to avoid the problem case.
+ */
+#define membar_safe(type) \
+do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
+                             " membar   " type "\n" \
+                             "1:\n" \
+                             : : : "memory"); \
+} while (0)
+
+#define mb()    \
+        membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
+#define rmb()   \
+        membar_safe("#LoadLoad")
+#define wmb()   \
+        membar_safe("#StoreStore")
+#define membar_storeload() \
+        membar_safe("#StoreLoad")
+#define membar_storeload_storestore() \
+        membar_safe("#StoreLoad | #StoreStore")
+#define membar_storeload_loadload() \
+        membar_safe("#StoreLoad | #LoadLoad")
+#define membar_storestore_loadstore() \
+        membar_safe("#StoreStore | #LoadStore")
+
+#endif
+
+#define nop()           __asm__ __volatile__ ("nop")
+
+#define read_barrier_depends()          do { } while(0)
+#define set_mb(__var, __value) \
+        do { __var = __value; membar_storeload_storestore(); } while(0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        __asm__ __volatile__("":::"memory")
+#define smp_rmb()       __asm__ __volatile__("":::"memory")
+#define smp_wmb()       __asm__ __volatile__("":::"memory")
+#define smp_read_barrier_depends()      do { } while(0)
+#endif
+
+#define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
+
+#define flushw_all()    __asm__ __volatile__("flushw")
+
+/* Performance counter register access. */
+#define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
+#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
+#define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
+
+/* Blackbird errata workaround.  See commentary in
+ * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
+ * for more information.
+ */
+#define reset_pic()                                             \
+        __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
+                             ".align    64\n"                   \
+                          "99:wr        %g0, 0x0, %pic\n\t"     \
+                             "rd        %pic, %g0")
+
+#ifndef __ASSEMBLY__
+
+extern void sun_do_break(void);
+extern int stop_a_enabled;
+
+extern void fault_in_user_windows(void);
+extern void synchronize_user_stack(void);
+
+extern void __flushw_user(void);
+#define flushw_user() __flushw_user()
+
+#define flush_user_windows flushw_user
+#define flush_register_windows flushw_all
+
+/* Don't hold the runqueue lock over context switch */
+#define __ARCH_WANT_UNLOCKED_CTXSW
+#define prepare_arch_switch(next)               \
+do {                                            \
+        flushw_all();                           \
+} while (0)
+
+        /* See what happens when you design the chip correctly?
+         *
+         * We tell gcc we clobber all non-fixed-usage registers except
+         * for l0/l1.  It will use one for 'next' and the other to hold
+         * the output value of 'last'.  'next' is not referenced again
+         * past the invocation of switch_to in the scheduler, so we need
+         * not preserve it's value.  Hairy, but it lets us remove 2 loads
+         * and 2 stores in this critical code path.  -DaveM
+         */
+#define switch_to(prev, next, last)                                     \
+do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
+                unsigned long __tmp;                                    \
+                read_pcr(__tmp);                                        \
+                current_thread_info()->pcr_reg = __tmp;                 \
+                read_pic(__tmp);                                        \
+                current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
+                current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
+        }                                                               \
+        flush_tlb_pending();                                            \
+        save_and_clear_fpu();                                           \
+        /* If you are tempted to conditionalize the following */        \
+        /* so that ASI is only written if it changes, think again. */   \
+        __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
+        : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
+        trap_block[current_thread_info()->cpu].thread =                 \
+                task_thread_info(next);                                 \
+        __asm__ __volatile__(                                           \
+        "mov    %%g4, %%g7\n\t"                                         \
+        "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
+        "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
+        "rdpr   %%wstate, %%o5\n\t"                                     \
+        "stx    %%o6, [%%g6 + %6]\n\t"                                  \
+        "stb    %%o5, [%%g6 + %5]\n\t"                                  \
+        "rdpr   %%cwp, %%o5\n\t"                                        \
+        "stb    %%o5, [%%g6 + %8]\n\t"                                  \
+        "mov    %4, %%g6\n\t"                                           \
+        "ldub   [%4 + %8], %%g1\n\t"                                    \
+        "wrpr   %%g1, %%cwp\n\t"                                        \
+        "ldx    [%%g6 + %6], %%o6\n\t"                                  \
+        "ldub   [%%g6 + %5], %%o5\n\t"                                  \
+        "ldub   [%%g6 + %7], %%o7\n\t"                                  \
+        "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
+        "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
+        "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
+        "ldx    [%%g6 + %9], %%g4\n\t"                                  \
+        "brz,pt %%o7, switch_to_pc\n\t"                                 \
+        " mov   %%g7, %0\n\t"                                           \
+        "sethi  %%hi(ret_from_syscall), %%g1\n\t"                       \
+        "jmpl   %%g1 + %%lo(ret_from_syscall), %%g0\n\t"                \
+        " nop\n\t"                                                      \
+        ".globl switch_to_pc\n\t"                                       \
+        "switch_to_pc:\n\t"                                             \
+        : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
+          "=r" (__local_per_cpu_offset)                                 \
+        : "0" (task_thread_info(next)),                                 \
+          "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
+          "i" (TI_CWP), "i" (TI_TASK)                                   \
+        : "cc",                                                         \
+                "g1", "g2", "g3",                   "g7",               \
+                "l1", "l2", "l3", "l4", "l5", "l6", "l7",               \
+          "i0", "i1", "i2", "i3", "i4", "i5",                           \
+          "o0", "o1", "o2", "o3", "o4", "o5",       "o7");              \
+        /* If you fuck with this, update ret_from_syscall code too. */  \
+        if (test_thread_flag(TIF_PERFCTR)) {                            \
+                write_pcr(current_thread_info()->pcr_reg);              \
+                reset_pic();                                            \
+        }                                                               \
+} while(0)
+
+static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
+{
+        unsigned long tmp1, tmp2;
+
+        __asm__ __volatile__(
+"       membar          #StoreLoad | #LoadLoad\n"
+"       mov             %0, %1\n"
+"1:     lduw            [%4], %2\n"
+"       cas             [%4], %2, %0\n"
+"       cmp             %2, %0\n"
+"       bne,a,pn        %%icc, 1b\n"
+"        mov            %1, %0\n"
+"       membar          #StoreLoad | #StoreStore\n"
+        : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
+        : "0" (val), "r" (m)
+        : "cc", "memory");
+        return val;
+}
+
+static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
+{
+        unsigned long tmp1, tmp2;
+
+        __asm__ __volatile__(
+"       membar          #StoreLoad | #LoadLoad\n"
+"       mov             %0, %1\n"
+"1:     ldx             [%4], %2\n"
+"       casx            [%4], %2, %0\n"
+"       cmp             %2, %0\n"
+"       bne,a,pn        %%xcc, 1b\n"
+"        mov            %1, %0\n"
+"       membar          #StoreLoad | #StoreStore\n"
+        : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
+        : "0" (val), "r" (m)
+        : "cc", "memory");
+        return val;
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
+                                       int size)
+{
+        switch (size) {
+        case 4:
+                return xchg32(ptr, x);
+        case 8:
+                return xchg64(ptr, x);
+        };
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long
+__cmpxchg_u32(volatile int *m, int old, int new)
+{
+        __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
+                             "cas [%2], %3, %0\n\t"
+                             "membar #StoreLoad | #StoreStore"
+                             : "=&r" (new)
+                             : "0" (new), "r" (m), "r" (old)
+                             : "memory");
+
+        return new;
+}
+
+static inline unsigned long
+__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
+{
+        __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
+                             "casx [%2], %3, %0\n\t"
+                             "membar #StoreLoad | #StoreStore"
+                             : "=&r" (new)
+                             : "0" (new), "r" (m), "r" (old)
+                             : "memory");
+
+        return new;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid cmpxchg().  */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+{
+        switch (size) {
+                case 4:
+                        return __cmpxchg_u32(ptr, old, new);
+                case 8:
+                        return __cmpxchg_u64(ptr, old, new);
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)                                                 \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+                                      unsigned long old,
+                                      unsigned long new, int size)
+{
+        switch (size) {
+        case 4:
+        case 8: return __cmpxchg(ptr, old, new, size);
+        default:
+                return __cmpxchg_local_generic(ptr, old, new, size);
+        }
+
+        return old;
+}
+
+#define cmpxchg_local(ptr, o, n)                                        \
+        ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
+                        (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n)                                      \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg_local((ptr), (o), (n));                                 \
+  })
+
+#endif /* !(__ASSEMBLY__) */
+
+#define arch_align_stack(x) (x)
+
+#endif /* !(__SPARC64_SYSTEM_H) */
diff --git a/arch/sparc/include/asm/termbits.h b/arch/sparc/include/asm/termbits.h
new file mode 100644
index 000000000000..d6ca3e2754f5
--- /dev/null
+++ b/arch/sparc/include/asm/termbits.h
@@ -0,0 +1,266 @@
+#ifndef _SPARC_TERMBITS_H
+#define _SPARC_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+
+#if defined(__sparc__) && defined(__arch64__)
+typedef unsigned int    tcflag_t;
+#else
+typedef unsigned long   tcflag_t;
+#endif
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+#define NCCS 17
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+#ifdef __KERNEL__
+#define SIZEOF_USER_TERMIOS sizeof (struct termios) - (2*sizeof (cc_t))
+        cc_t _x_cc[2];                  /* We need them to hold vmin/vtime */
+#endif
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t _x_cc[2];                  /* padding to match ktermios */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t _x_cc[2];                  /* We need them to hold vmin/vtime */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR    0
+#define VQUIT    1
+#define VERASE   2
+#define VKILL    3
+#define VEOF     4
+#define VEOL     5
+#define VEOL2    6
+#define VSWTC    7
+#define VSTART   8
+#define VSTOP    9
+
+
+
+#define VSUSP    10
+#define VDSUSP   11  /* SunOS POSIX nicety I do believe... */
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE  14
+#define VLNEXT   15
+
+/* Kernel keeps vmin/vtime separated, user apps assume vmin/vtime is
+ * shared with eof/eol
+ */
+#ifdef __KERNEL__
+#define VMIN     16
+#define VTIME    17
+#else
+#define VMIN     VEOF
+#define VTIME    VEOL
+#endif
+
+/* c_iflag bits */
+#define IGNBRK  0x00000001
+#define BRKINT  0x00000002
+#define IGNPAR  0x00000004
+#define PARMRK  0x00000008
+#define INPCK   0x00000010
+#define ISTRIP  0x00000020
+#define INLCR   0x00000040
+#define IGNCR   0x00000080
+#define ICRNL   0x00000100
+#define IUCLC   0x00000200
+#define IXON    0x00000400
+#define IXANY   0x00000800
+#define IXOFF   0x00001000
+#define IMAXBEL 0x00002000
+#define IUTF8   0x00004000
+
+/* c_oflag bits */
+#define OPOST   0x00000001
+#define OLCUC   0x00000002
+#define ONLCR   0x00000004
+#define OCRNL   0x00000008
+#define ONOCR   0x00000010
+#define ONLRET  0x00000020
+#define OFILL   0x00000040
+#define OFDEL   0x00000080
+#define NLDLY   0x00000100
+#define   NL0   0x00000000
+#define   NL1   0x00000100
+#define CRDLY   0x00000600
+#define   CR0   0x00000000
+#define   CR1   0x00000200
+#define   CR2   0x00000400
+#define   CR3   0x00000600
+#define TABDLY  0x00001800
+#define   TAB0  0x00000000
+#define   TAB1  0x00000800
+#define   TAB2  0x00001000
+#define   TAB3  0x00001800
+#define   XTABS 0x00001800
+#define BSDLY   0x00002000
+#define   BS0   0x00000000
+#define   BS1   0x00002000
+#define VTDLY   0x00004000
+#define   VT0   0x00000000
+#define   VT1   0x00004000
+#define FFDLY   0x00008000
+#define   FF0   0x00000000
+#define   FF1   0x00008000
+#define PAGEOUT 0x00010000  /* SUNOS specific */
+#define WRAP    0x00020000  /* SUNOS specific */
+
+/* c_cflag bit meaning */
+#define CBAUD     0x0000100f
+#define  B0       0x00000000   /* hang up */
+#define  B50      0x00000001
+#define  B75      0x00000002
+#define  B110     0x00000003
+#define  B134     0x00000004
+#define  B150     0x00000005
+#define  B200     0x00000006
+#define  B300     0x00000007
+#define  B600     0x00000008
+#define  B1200    0x00000009
+#define  B1800    0x0000000a
+#define  B2400    0x0000000b
+#define  B4800    0x0000000c
+#define  B9600    0x0000000d
+#define  B19200   0x0000000e
+#define  B38400   0x0000000f
+#define EXTA      B19200
+#define EXTB      B38400
+#define  CSIZE    0x00000030
+#define   CS5     0x00000000
+#define   CS6     0x00000010
+#define   CS7     0x00000020
+#define   CS8     0x00000030
+#define CSTOPB    0x00000040
+#define CREAD     0x00000080
+#define PARENB    0x00000100
+#define PARODD    0x00000200
+#define HUPCL     0x00000400
+#define CLOCAL    0x00000800
+#define CBAUDEX   0x00001000
+/* We'll never see these speeds with the Zilogs, but for completeness... */
+#define  BOTHER   0x00001000
+#define  B57600   0x00001001
+#define  B115200  0x00001002
+#define  B230400  0x00001003
+#define  B460800  0x00001004
+/* This is what we can do with the Zilogs. */
+#define  B76800   0x00001005
+/* This is what we can do with the SAB82532. */
+#define  B153600  0x00001006
+#define  B307200  0x00001007
+#define  B614400  0x00001008
+#define  B921600  0x00001009
+/* And these are the rest... */
+#define  B500000  0x0000100a
+#define  B576000  0x0000100b
+#define B1000000  0x0000100c
+#define B1152000  0x0000100d
+#define B1500000  0x0000100e
+#define B2000000  0x0000100f
+/* These have totally bogus values and nobody uses them
+   so far. Later on we'd have to use say 0x10000x and
+   adjust CBAUD constant and drivers accordingly.
+#define B2500000  0x00001010
+#define B3000000  0x00001011
+#define B3500000  0x00001012
+#define B4000000  0x00001013  */
+#define CIBAUD    0x100f0000  /* input baud rate (not used) */
+#define CMSPAR    0x40000000  /* mark or space (stick) parity */
+#define CRTSCTS   0x80000000  /* flow control */
+
+#define IBSHIFT   16            /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0x00000001
+#define ICANON  0x00000002
+#define XCASE   0x00000004
+#define ECHO    0x00000008
+#define ECHOE   0x00000010
+#define ECHOK   0x00000020
+#define ECHONL  0x00000040
+#define NOFLSH  0x00000080
+#define TOSTOP  0x00000100
+#define ECHOCTL 0x00000200
+#define ECHOPRT 0x00000400
+#define ECHOKE  0x00000800
+#define DEFECHO 0x00001000  /* SUNOS thing, what is it? */
+#define FLUSHO  0x00002000
+#define PENDIN  0x00004000
+#define IEXTEN  0x00008000
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif /* !(_SPARC_TERMBITS_H) */
diff --git a/arch/sparc/include/asm/termios.h b/arch/sparc/include/asm/termios.h
new file mode 100644
index 000000000000..e8ba95399643
--- /dev/null
+++ b/arch/sparc/include/asm/termios.h
@@ -0,0 +1,186 @@
+#ifndef _SPARC_TERMIOS_H
+#define _SPARC_TERMIOS_H
+
+#include <asm/ioctls.h>
+#include <asm/termbits.h>
+
+#if defined(__KERNEL__) || defined(__DEFINE_BSD_TERMIOS)
+struct sgttyb {
+        char    sg_ispeed;
+        char    sg_ospeed;
+        char    sg_erase;
+        char    sg_kill;
+        short   sg_flags;
+};
+
+struct tchars {
+        char    t_intrc;
+        char    t_quitc;
+        char    t_startc;
+        char    t_stopc;
+        char    t_eofc;
+        char    t_brkc;
+};
+
+struct ltchars {
+        char    t_suspc;
+        char    t_dsuspc;
+        char    t_rprntc;
+        char    t_flushc;
+        char    t_werasc;
+        char    t_lnextc;
+};
+#endif /* __KERNEL__ */
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#ifdef __KERNEL__
+#include <linux/module.h>
+
+/*
+ * c_cc characters in the termio structure.  Oh, how I love being
+ * backwardly compatible.  Notice that character 4 and 5 are
+ * interpreted differently depending on whether ICANON is set in
+ * c_lflag.  If it's set, they are used as _VEOF and _VEOL, otherwise
+ * as _VMIN and V_TIME.  This is for compatibility with OSF/1 (which
+ * is compatible with sysV)...
+ */
+#define _VMIN   4
+#define _VTIME  5
+
+/*      intr=^C         quit=^\         erase=del       kill=^U
+        eof=^D          eol=\0          eol2=\0         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         dsusp=^Y
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        vmin=\1         vtime=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\000\000\000\021\023\032\031\022\025\027\026\001"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        unsigned short tmp; \
+        int err; \
+        err = get_user(tmp, &(termio)->c_iflag); \
+        (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
+        err |= get_user(tmp, &(termio)->c_oflag); \
+        (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
+        err |= get_user(tmp, &(termio)->c_cflag); \
+        (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
+        err |= get_user(tmp, &(termio)->c_lflag); \
+        (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
+        err |= copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+        err; \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ *
+ * Note the "fun" _VMIN overloading.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        int err; \
+        err  = put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        err |= put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        err |= put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        err |= put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        err |= put_user((termios)->c_line,  &(termio)->c_line); \
+        err |= copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+        if (!((termios)->c_lflag & ICANON)) { \
+                err |= put_user((termios)->c_cc[VMIN], &(termio)->c_cc[_VMIN]); \
+                err |= put_user((termios)->c_cc[VTIME], &(termio)->c_cc[_VTIME]); \
+        } \
+        err; \
+})
+
+#define user_termios_to_kernel_termios(k, u) \
+({ \
+        int err; \
+        err  = get_user((k)->c_iflag, &(u)->c_iflag); \
+        err |= get_user((k)->c_oflag, &(u)->c_oflag); \
+        err |= get_user((k)->c_cflag, &(u)->c_cflag); \
+        err |= get_user((k)->c_lflag, &(u)->c_lflag); \
+        err |= get_user((k)->c_line,  &(u)->c_line); \
+        err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
+        if ((k)->c_lflag & ICANON) { \
+                err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+                err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+        } else { \
+                err |= get_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
+                err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+        } \
+        err |= get_user((k)->c_ispeed,  &(u)->c_ispeed); \
+        err |= get_user((k)->c_ospeed,  &(u)->c_ospeed); \
+        err; \
+})
+
+#define kernel_termios_to_user_termios(u, k) \
+({ \
+        int err; \
+        err  = put_user((k)->c_iflag, &(u)->c_iflag); \
+        err |= put_user((k)->c_oflag, &(u)->c_oflag); \
+        err |= put_user((k)->c_cflag, &(u)->c_cflag); \
+        err |= put_user((k)->c_lflag, &(u)->c_lflag); \
+        err |= put_user((k)->c_line, &(u)->c_line); \
+        err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
+        if (!((k)->c_lflag & ICANON)) { \
+                err |= put_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
+                err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+        } else { \
+                err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+                err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+        } \
+        err |= put_user((k)->c_ispeed, &(u)->c_ispeed); \
+        err |= put_user((k)->c_ospeed, &(u)->c_ospeed); \
+        err; \
+})
+
+#define user_termios_to_kernel_termios_1(k, u) \
+({ \
+        int err; \
+        err  = get_user((k)->c_iflag, &(u)->c_iflag); \
+        err |= get_user((k)->c_oflag, &(u)->c_oflag); \
+        err |= get_user((k)->c_cflag, &(u)->c_cflag); \
+        err |= get_user((k)->c_lflag, &(u)->c_lflag); \
+        err |= get_user((k)->c_line,  &(u)->c_line); \
+        err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \
+        if ((k)->c_lflag & ICANON) { \
+                err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+                err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+        } else { \
+                err |= get_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
+                err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+        } \
+        err; \
+})
+
+#define kernel_termios_to_user_termios_1(u, k) \
+({ \
+        int err; \
+        err  = put_user((k)->c_iflag, &(u)->c_iflag); \
+        err |= put_user((k)->c_oflag, &(u)->c_oflag); \
+        err |= put_user((k)->c_cflag, &(u)->c_cflag); \
+        err |= put_user((k)->c_lflag, &(u)->c_lflag); \
+        err |= put_user((k)->c_line, &(u)->c_line); \
+        err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \
+        if (!((k)->c_lflag & ICANON)) { \
+                err |= put_user((k)->c_cc[VMIN],  &(u)->c_cc[_VMIN]); \
+                err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \
+        } else { \
+                err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \
+                err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \
+        } \
+        err; \
+})
+
+#endif  /* __KERNEL__ */
+
+#endif /* _SPARC_TERMIOS_H */
diff --git a/arch/sparc/include/asm/thread_info.h b/arch/sparc/include/asm/thread_info.h
new file mode 100644
index 000000000000..122d7acc07e6
--- /dev/null
+++ b/arch/sparc/include/asm/thread_info.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_THREAD_INFO_H
+#define ___ASM_SPARC_THREAD_INFO_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/thread_info_64.h>
+#else
+#include <asm/thread_info_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h
new file mode 100644
index 000000000000..cbb892d0dff0
--- /dev/null
+++ b/arch/sparc/include/asm/thread_info_32.h
@@ -0,0 +1,158 @@
+/*
+ * thread_info.h: sparc low-level thread information
+ * adapted from the ppc version by Pete Zaitcev, which was
+ * adapted from the i386 version by Paul Mackerras
+ *
+ * Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ * Copyright (c) 2002  Pete Zaitcev (zaitcev@yahoo.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#include <asm/btfixup.h>
+#include <asm/ptrace.h>
+#include <asm/page.h>
+
+/*
+ * Low level task data.
+ *
+ * If you change this, change the TI_* offsets below to match.
+ */
+#define NSWINS 8
+struct thread_info {
+        unsigned long           uwinmask;
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        int                     cpu;            /* cpu we're on */
+        int                     preempt_count;  /* 0 => preemptable,
+                                                   <0 => BUG */
+        int                     softirq_count;
+        int                     hardirq_count;
+
+        /* Context switch saved kernel state. */
+        unsigned long ksp;      /* ... ksp __attribute__ ((aligned (8))); */
+        unsigned long kpc;
+        unsigned long kpsr;
+        unsigned long kwim;
+
+        /* A place to store user windows and stack pointers
+         * when the stack needs inspection.
+         */
+        struct reg_window       reg_window[NSWINS];     /* align for ldd! */
+        unsigned long           rwbuf_stkptrs[NSWINS];
+        unsigned long           w_saved;
+
+        struct restart_block    restart_block;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#define INIT_THREAD_INFO(tsk)                           \
+{                                                       \
+        .uwinmask       =       0,                      \
+        .task           =       &tsk,                   \
+        .exec_domain    =       &default_exec_domain,   \
+        .flags          =       0,                      \
+        .cpu            =       0,                      \
+        .preempt_count  =       1,                      \
+        .restart_block  = {                             \
+                .fn     =       do_no_restart_syscall,  \
+        },                                              \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* how to get the thread information struct from C */
+register struct thread_info *current_thread_info_reg asm("g6");
+#define current_thread_info()   (current_thread_info_reg)
+
+/*
+ * thread information allocation
+ */
+#if PAGE_SHIFT == 13
+#define THREAD_INFO_ORDER  0
+#else /* PAGE_SHIFT */
+#define THREAD_INFO_ORDER  1
+#endif
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info, void)
+#define alloc_thread_info(tsk) BTFIXUP_CALL(alloc_thread_info)()
+
+BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
+#define free_thread_info(ti) BTFIXUP_CALL(free_thread_info)(ti)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Size of kernel stack for each process.
+ * Observe the order of get_free_pages() in alloc_thread_info().
+ * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste.
+ */
+#define THREAD_SIZE             8192
+
+/*
+ * Offsets in thread_info structure, used in assembly code
+ * The "#define REGWIN_SZ 0x40" was abolished, so no multiplications.
+ */
+#define TI_UWINMASK     0x00    /* uwinmask */
+#define TI_TASK         0x04
+#define TI_EXECDOMAIN   0x08    /* exec_domain */
+#define TI_FLAGS        0x0c
+#define TI_CPU          0x10
+#define TI_PREEMPT      0x14    /* preempt_count */
+#define TI_SOFTIRQ      0x18    /* softirq_count */
+#define TI_HARDIRQ      0x1c    /* hardirq_count */
+#define TI_KSP          0x20    /* ksp */
+#define TI_KPC          0x24    /* kpc (ldd'ed with kpc) */
+#define TI_KPSR         0x28    /* kpsr */
+#define TI_KWIM         0x2c    /* kwim (ldd'ed with kpsr) */
+#define TI_REG_WINDOW   0x30
+#define TI_RWIN_SPTRS   0x230
+#define TI_W_SAVED      0x250
+/* #define TI_RESTART_BLOCK 0x25n */ /* Nobody cares */
+
+#define PREEMPT_ACTIVE          0x4000000
+
+/*
+ * thread information flag bit numbers
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* callback before returning to user */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_RESTORE_SIGMASK     4       /* restore signal mask in do_signal() */
+#define TIF_USEDFPU             8       /* FPU was used by this task
+                                         * this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      9       /* true if poll_idle() is polling
+                                         * TIF_NEED_RESCHED */
+#define TIF_MEMDIE              10
+
+/* as above, but as bit values */
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+
+#define _TIF_DO_NOTIFY_RESUME_MASK      (_TIF_NOTIFY_RESUME | \
+                                         _TIF_SIGPENDING | \
+                                         _TIF_RESTORE_SIGMASK)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h
new file mode 100644
index 000000000000..c0a737d7292c
--- /dev/null
+++ b/arch/sparc/include/asm/thread_info_64.h
@@ -0,0 +1,281 @@
+/* thread_info.h: sparc64 low-level thread information
+ *
+ * Copyright (C) 2002  David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#define NSWINS          7
+
+#define TI_FLAG_BYTE_FAULT_CODE         0
+#define TI_FLAG_FAULT_CODE_SHIFT        56
+#define TI_FLAG_BYTE_WSTATE             1
+#define TI_FLAG_WSTATE_SHIFT            48
+#define TI_FLAG_BYTE_CWP                2
+#define TI_FLAG_CWP_SHIFT               40
+#define TI_FLAG_BYTE_CURRENT_DS         3
+#define TI_FLAG_CURRENT_DS_SHIFT        32
+#define TI_FLAG_BYTE_FPDEPTH            4
+#define TI_FLAG_FPDEPTH_SHIFT           24
+#define TI_FLAG_BYTE_WSAVED             5
+#define TI_FLAG_WSAVED_SHIFT            16
+
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+struct task_struct;
+struct exec_domain;
+
+struct thread_info {
+        /* D$ line 1 */
+        struct task_struct      *task;
+        unsigned long           flags;
+        __u8                    fpsaved[7];
+        __u8                    status;
+        unsigned long           ksp;
+
+        /* D$ line 2 */
+        unsigned long           fault_address;
+        struct pt_regs          *kregs;
+        struct exec_domain      *exec_domain;
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
+        __u8                    new_child;
+        __u8                    syscall_noerror;
+        __u16                   cpu;
+
+        unsigned long           *utraps;
+
+        struct reg_window       reg_window[NSWINS];
+        unsigned long           rwbuf_stkptrs[NSWINS];
+
+        unsigned long           gsr[7];
+        unsigned long           xfsr[7];
+
+        __u64                   __user *user_cntd0;
+        __u64                   __user *user_cntd1;
+        __u64                   kernel_cntd0, kernel_cntd1;
+        __u64                   pcr_reg;
+
+        struct restart_block    restart_block;
+
+        struct pt_regs          *kern_una_regs;
+        unsigned int            kern_una_insn;
+
+        unsigned long           fpregs[0] __attribute__ ((aligned(64)));
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+/* offsets into the thread_info struct for assembly code access */
+#define TI_TASK         0x00000000
+#define TI_FLAGS        0x00000008
+#define TI_FAULT_CODE   (TI_FLAGS + TI_FLAG_BYTE_FAULT_CODE)
+#define TI_WSTATE       (TI_FLAGS + TI_FLAG_BYTE_WSTATE)
+#define TI_CWP          (TI_FLAGS + TI_FLAG_BYTE_CWP)
+#define TI_CURRENT_DS   (TI_FLAGS + TI_FLAG_BYTE_CURRENT_DS)
+#define TI_FPDEPTH      (TI_FLAGS + TI_FLAG_BYTE_FPDEPTH)
+#define TI_WSAVED       (TI_FLAGS + TI_FLAG_BYTE_WSAVED)
+#define TI_FPSAVED      0x00000010
+#define TI_KSP          0x00000018
+#define TI_FAULT_ADDR   0x00000020
+#define TI_KREGS        0x00000028
+#define TI_EXEC_DOMAIN  0x00000030
+#define TI_PRE_COUNT    0x00000038
+#define TI_NEW_CHILD    0x0000003c
+#define TI_SYS_NOERROR  0x0000003d
+#define TI_CPU          0x0000003e
+#define TI_UTRAPS       0x00000040
+#define TI_REG_WINDOW   0x00000048
+#define TI_RWIN_SPTRS   0x000003c8
+#define TI_GSR          0x00000400
+#define TI_XFSR         0x00000438
+#define TI_USER_CNTD0   0x00000470
+#define TI_USER_CNTD1   0x00000478
+#define TI_KERN_CNTD0   0x00000480
+#define TI_KERN_CNTD1   0x00000488
+#define TI_PCR          0x00000490
+#define TI_RESTART_BLOCK 0x00000498
+#define TI_KUNA_REGS    0x000004c0
+#define TI_KUNA_INSN    0x000004c8
+#define TI_FPREGS       0x00000500
+
+/* We embed this in the uppermost byte of thread_info->flags */
+#define FAULT_CODE_WRITE        0x01    /* Write access, implies D-TLB     */
+#define FAULT_CODE_DTLB         0x02    /* Miss happened in D-TLB          */
+#define FAULT_CODE_ITLB         0x04    /* Miss happened in I-TLB          */
+#define FAULT_CODE_WINFIXUP     0x08    /* Miss happened during spill/fill */
+#define FAULT_CODE_BLKCOMMIT    0x10    /* Use blk-commit ASI in copy_page */
+
+#if PAGE_SHIFT == 13
+#define THREAD_SIZE (2*PAGE_SIZE)
+#define THREAD_SHIFT (PAGE_SHIFT + 1)
+#else /* PAGE_SHIFT == 13 */
+#define THREAD_SIZE PAGE_SIZE
+#define THREAD_SHIFT PAGE_SHIFT
+#endif /* PAGE_SHIFT == 13 */
+
+#define PREEMPT_ACTIVE          0x4000000
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#ifndef __ASSEMBLY__
+
+#define INIT_THREAD_INFO(tsk)                           \
+{                                                       \
+        .task           =       &tsk,                   \
+        .flags          = ((unsigned long)ASI_P) << TI_FLAG_CURRENT_DS_SHIFT,   \
+        .exec_domain    =       &default_exec_domain,   \
+        .preempt_count  =       1,                      \
+        .restart_block  = {                             \
+                .fn     =       do_no_restart_syscall,  \
+        },                                              \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* how to get the thread information struct from C */
+register struct thread_info *current_thread_info_reg asm("g6");
+#define current_thread_info()   (current_thread_info_reg)
+
+/* thread information allocation */
+#if PAGE_SHIFT == 13
+#define __THREAD_INFO_ORDER     1
+#else /* PAGE_SHIFT == 13 */
+#define __THREAD_INFO_ORDER     0
+#endif /* PAGE_SHIFT == 13 */
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(tsk)                                  \
+({                                                              \
+        struct thread_info *ret;                                \
+                                                                \
+        ret = (struct thread_info *)                            \
+          __get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER);    \
+        if (ret)                                                \
+                memset(ret, 0, PAGE_SIZE<<__THREAD_INFO_ORDER); \
+        ret;                                                    \
+})
+#else
+#define alloc_thread_info(tsk) \
+        ((struct thread_info *)__get_free_pages(GFP_KERNEL, __THREAD_INFO_ORDER))
+#endif
+
+#define free_thread_info(ti) \
+        free_pages((unsigned long)(ti),__THREAD_INFO_ORDER)
+
+#define __thread_flag_byte_ptr(ti)      \
+        ((unsigned char *)(&((ti)->flags)))
+#define __cur_thread_flag_byte_ptr      __thread_flag_byte_ptr(current_thread_info())
+
+#define get_thread_fault_code()         (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE])
+#define set_thread_fault_code(val)      (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FAULT_CODE] = (val))
+#define get_thread_wstate()             (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE])
+#define set_thread_wstate(val)          (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSTATE] = (val))
+#define get_thread_cwp()                (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP])
+#define set_thread_cwp(val)             (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CWP] = (val))
+#define get_thread_current_ds()         (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS])
+#define set_thread_current_ds(val)      (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_CURRENT_DS] = (val))
+#define get_thread_fpdepth()            (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH])
+#define set_thread_fpdepth(val)         (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH] = (val))
+#define get_thread_wsaved()             (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED])
+#define set_thread_wsaved(val)          (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED] = (val))
+
+#endif /* !(__ASSEMBLY__) */
+
+/*
+ * Thread information flags, only 16 bits are available as we encode
+ * other values into the upper 6 bytes.
+ *
+ * On trap return we need to test several values:
+ *
+ * user:        need_resched, notify_resume, sigpending, wsaved, perfctr
+ * kernel:      fpdepth
+ *
+ * So to check for work in the kernel case we simply load the fpdepth
+ * byte out of the flags and test it.  For the user case we encode the
+ * lower 3 bytes of flags as follows:
+ *      ----------------------------------------
+ *      | wsaved | flags byte 1 | flags byte 2 |
+ *      ----------------------------------------
+ * This optimizes the user test into:
+ *      ldx             [%g6 + TI_FLAGS], REG1
+ *      sethi           %hi(_TIF_USER_WORK_MASK), REG2
+ *      or              REG2, %lo(_TIF_USER_WORK_MASK), REG2
+ *      andcc           REG1, REG2, %g0
+ *      be,pt           no_work_to_do
+ *       nop
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* callback before returning to user */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_PERFCTR             4       /* performance counters active */
+#define TIF_UNALIGNED           5       /* allowed to do unaligned accesses */
+/* flag bit 6 is available */
+#define TIF_32BIT               7       /* 32-bit binary */
+/* flag bit 8 is available */
+#define TIF_SECCOMP             9       /* secure computing */
+#define TIF_SYSCALL_AUDIT       10      /* syscall auditing active */
+/* flag bit 11 is available */
+/* NOTE: Thread flags >= 12 should be ones we have no interest
+ *       in using in assembly, else we can't use the mask as
+ *       an immediate value in instructions such as andcc.
+ */
+#define TIF_ABI_PENDING         12
+#define TIF_MEMDIE              13
+#define TIF_POLLING_NRFLAG      14
+
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_PERFCTR            (1<<TIF_PERFCTR)
+#define _TIF_UNALIGNED          (1<<TIF_UNALIGNED)
+#define _TIF_32BIT              (1<<TIF_32BIT)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_ABI_PENDING        (1<<TIF_ABI_PENDING)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+
+#define _TIF_USER_WORK_MASK     ((0xff << TI_FLAG_WSAVED_SHIFT) | \
+                                 _TIF_DO_NOTIFY_RESUME_MASK | \
+                                 _TIF_NEED_RESCHED | _TIF_PERFCTR)
+#define _TIF_DO_NOTIFY_RESUME_MASK      (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING)
+
+/*
+ * Thread-synchronous status.
+ *
+ * This is different from the flags in that nobody else
+ * ever touches our thread-synchronous status, so we don't
+ * have to worry about atomic accesses.
+ *
+ * Note that there are only 8 bits available.
+ */
+#define TS_RESTORE_SIGMASK      0x0001  /* restore signal mask in do_signal() */
+
+#ifndef __ASSEMBLY__
+#define HAVE_SET_RESTORE_SIGMASK        1
+static inline void set_restore_sigmask(void)
+{
+        struct thread_info *ti = current_thread_info();
+        ti->status |= TS_RESTORE_SIGMASK;
+        set_bit(TIF_SIGPENDING, &ti->flags);
+}
+#endif  /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/sparc/include/asm/timer.h b/arch/sparc/include/asm/timer.h
new file mode 100644
index 000000000000..612fd2779d9e
--- /dev/null
+++ b/arch/sparc/include/asm/timer.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_TIMER_H
+#define ___ASM_SPARC_TIMER_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/timer_64.h>
+#else
+#include <asm/timer_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/timer_32.h b/arch/sparc/include/asm/timer_32.h
new file mode 100644
index 000000000000..361e53898dd7
--- /dev/null
+++ b/arch/sparc/include/asm/timer_32.h
@@ -0,0 +1,107 @@
+/*
+ * timer.h:  Definitions for the timer chips on the Sparc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+
+#ifndef _SPARC_TIMER_H
+#define _SPARC_TIMER_H
+
+#include <asm/system.h>  /* For SUN4M_NCPUS */
+#include <asm/sun4paddr.h>
+#include <asm/btfixup.h>
+
+/* Timer structures. The interrupt timer has two properties which
+ * are the counter (which is handled in do_timer in sched.c) and the limit.
+ * This limit is where the timer's counter 'wraps' around. Oddly enough,
+ * the sun4c timer when it hits the limit wraps back to 1 and not zero
+ * thus when calculating the value at which it will fire a microsecond you
+ * must adjust by one.  Thanks SUN for designing such great hardware ;(
+ */
+
+/* Note that I am only going to use the timer that interrupts at
+ * Sparc IRQ 10.  There is another one available that can fire at
+ * IRQ 14. Currently it is left untouched, we keep the PROM's limit
+ * register value and let the prom take these interrupts.  This allows
+ * L1-A to work.
+ */
+
+struct sun4c_timer_info {
+  __volatile__ unsigned int cur_count10;
+  __volatile__ unsigned int timer_limit10;
+  __volatile__ unsigned int cur_count14;
+  __volatile__ unsigned int timer_limit14;
+};
+
+#define SUN4C_TIMER_PHYSADDR   0xf3000000
+#ifdef CONFIG_SUN4
+#define SUN_TIMER_PHYSADDR SUN4_300_TIMER_PHYSADDR
+#else
+#define SUN_TIMER_PHYSADDR SUN4C_TIMER_PHYSADDR
+#endif
+
+/* A sun4m has two blocks of registers which are probably of the same
+ * structure. LSI Logic's L64851 is told to _decrement_ from the limit
+ * value. Aurora behaves similarly but its limit value is compacted in
+ * other fashion (it's wider). Documented fields are defined here.
+ */
+
+/* As with the interrupt register, we have two classes of timer registers
+ * which are per-cpu and master.  Per-cpu timers only hit that cpu and are
+ * only level 14 ticks, master timer hits all cpus and is level 10.
+ */
+
+#define SUN4M_PRM_CNT_L       0x80000000
+#define SUN4M_PRM_CNT_LVALUE  0x7FFFFC00
+
+struct sun4m_timer_percpu_info {
+  __volatile__ unsigned int l14_timer_limit;    /* Initial value is 0x009c4000 */
+  __volatile__ unsigned int l14_cur_count;
+
+  /* This register appears to be write only and/or inaccessible
+   * on Uni-Processor sun4m machines.
+   */
+  __volatile__ unsigned int l14_limit_noclear;  /* Data access error is here */
+
+  __volatile__ unsigned int cntrl;            /* =1 after POST on Aurora */
+  __volatile__ unsigned char space[PAGE_SIZE - 16];
+};
+
+struct sun4m_timer_regs {
+        struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
+        volatile unsigned int l10_timer_limit;
+        volatile unsigned int l10_cur_count;
+
+        /* Again, this appears to be write only and/or inaccessible
+         * on uni-processor sun4m machines.
+         */
+        volatile unsigned int l10_limit_noclear;
+
+        /* This register too, it must be magic. */
+        volatile unsigned int foobar;
+
+        volatile unsigned int cfg;     /* equals zero at boot time... */
+};
+
+#define SUN4D_PRM_CNT_L       0x80000000
+#define SUN4D_PRM_CNT_LVALUE  0x7FFFFC00
+
+struct sun4d_timer_regs {
+        volatile unsigned int l10_timer_limit;
+        volatile unsigned int l10_cur_countx;
+        volatile unsigned int l10_limit_noclear;
+        volatile unsigned int ctrl;
+        volatile unsigned int l10_cur_count;
+};
+
+extern struct sun4d_timer_regs *sun4d_timers;
+
+extern __volatile__ unsigned int *master_l10_counter;
+extern __volatile__ unsigned int *master_l10_limit;
+
+/* FIXME: Make do_[gs]ettimeofday btfixup calls */
+BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
+#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv)
+
+#endif /* !(_SPARC_TIMER_H) */
diff --git a/arch/sparc/include/asm/timer_64.h b/arch/sparc/include/asm/timer_64.h
new file mode 100644
index 000000000000..5b779fd1f788
--- /dev/null
+++ b/arch/sparc/include/asm/timer_64.h
@@ -0,0 +1,30 @@
+/* timer.h: System timer definitions for sun5.
+ *
+ * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
+ */
+
+#ifndef _SPARC64_TIMER_H
+#define _SPARC64_TIMER_H
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+struct sparc64_tick_ops {
+        unsigned long (*get_tick)(void);
+        int (*add_compare)(unsigned long);
+        unsigned long softint_mask;
+        void (*disable_irq)(void);
+
+        void (*init_tick)(void);
+        unsigned long (*add_tick)(unsigned long);
+
+        char *name;
+};
+
+extern struct sparc64_tick_ops *tick_ops;
+
+extern unsigned long sparc64_get_clock_tick(unsigned int cpu);
+extern void __devinit setup_sparc64_timer(void);
+extern void __init time_init(void);
+
+#endif /* _SPARC64_TIMER_H */
diff --git a/arch/sparc/include/asm/timex.h b/arch/sparc/include/asm/timex.h
new file mode 100644
index 000000000000..70cc37b73827
--- /dev/null
+++ b/arch/sparc/include/asm/timex.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_TIMEX_H
+#define ___ASM_SPARC_TIMEX_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/timex_64.h>
+#else
+#include <asm/timex_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/timex_32.h b/arch/sparc/include/asm/timex_32.h
new file mode 100644
index 000000000000..b6ccdb0d6f7d
--- /dev/null
+++ b/arch/sparc/include/asm/timex_32.h
@@ -0,0 +1,15 @@
+/*
+ * linux/include/asm/timex.h
+ *
+ * sparc architecture timex specifications
+ */
+#ifndef _ASMsparc_TIMEX_H
+#define _ASMsparc_TIMEX_H
+
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
+
+/* XXX Maybe do something better at some point... -DaveM */
+typedef unsigned long cycles_t;
+#define get_cycles()    (0)
+
+#endif
diff --git a/arch/sparc/include/asm/timex_64.h b/arch/sparc/include/asm/timex_64.h
new file mode 100644
index 000000000000..18b30bc9823b
--- /dev/null
+++ b/arch/sparc/include/asm/timex_64.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm/timex.h
+ *
+ * sparc64 architecture timex specifications
+ */
+#ifndef _ASMsparc64_TIMEX_H
+#define _ASMsparc64_TIMEX_H
+
+#include <asm/timer.h>
+
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
+
+/* Getting on the cycle counter on sparc64. */
+typedef unsigned long cycles_t;
+#define get_cycles()    tick_ops->get_tick()
+
+#define ARCH_HAS_READ_CURRENT_TIMER
+
+#endif
diff --git a/arch/sparc/include/asm/tlb.h b/arch/sparc/include/asm/tlb.h
new file mode 100644
index 000000000000..92d0393bbcdc
--- /dev/null
+++ b/arch/sparc/include/asm/tlb.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_TLB_H
+#define ___ASM_SPARC_TLB_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/tlb_64.h>
+#else
+#include <asm/tlb_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/tlb_32.h b/arch/sparc/include/asm/tlb_32.h
new file mode 100644
index 000000000000..6d02d1ce53f3
--- /dev/null
+++ b/arch/sparc/include/asm/tlb_32.h
@@ -0,0 +1,24 @@
+#ifndef _SPARC_TLB_H
+#define _SPARC_TLB_H
+
+#define tlb_start_vma(tlb, vma) \
+do {                                                            \
+        flush_cache_range(vma, vma->vm_start, vma->vm_end);     \
+} while (0)
+
+#define tlb_end_vma(tlb, vma) \
+do {                                                            \
+        flush_tlb_range(vma, vma->vm_start, vma->vm_end);       \
+} while (0)
+
+#define __tlb_remove_tlb_entry(tlb, pte, address) \
+        do { } while (0)
+
+#define tlb_flush(tlb) \
+do {                                                            \
+        flush_tlb_mm((tlb)->mm);                                \
+} while (0)
+
+#include <asm-generic/tlb.h>
+
+#endif /* _SPARC_TLB_H */
diff --git a/arch/sparc/include/asm/tlb_64.h b/arch/sparc/include/asm/tlb_64.h
new file mode 100644
index 000000000000..ec81cdedef2c
--- /dev/null
+++ b/arch/sparc/include/asm/tlb_64.h
@@ -0,0 +1,111 @@
+#ifndef _SPARC64_TLB_H
+#define _SPARC64_TLB_H
+
+#include <linux/swap.h>
+#include <linux/pagemap.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+#include <asm/mmu_context.h>
+
+#define TLB_BATCH_NR    192
+
+/*
+ * For UP we don't need to worry about TLB flush
+ * and page free order so much..
+ */
+#ifdef CONFIG_SMP
+  #define FREE_PTE_NR   506
+  #define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
+#else
+  #define FREE_PTE_NR   1
+  #define tlb_fast_mode(bp) 1
+#endif
+
+struct mmu_gather {
+        struct mm_struct *mm;
+        unsigned int pages_nr;
+        unsigned int need_flush;
+        unsigned int fullmm;
+        unsigned int tlb_nr;
+        unsigned long vaddrs[TLB_BATCH_NR];
+        struct page *pages[FREE_PTE_NR];
+};
+
+DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+#ifdef CONFIG_SMP
+extern void smp_flush_tlb_pending(struct mm_struct *,
+                                  unsigned long, unsigned long *);
+#endif
+
+extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
+extern void flush_tlb_pending(void);
+
+static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+{
+        struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
+
+        BUG_ON(mp->tlb_nr);
+
+        mp->mm = mm;
+        mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
+        mp->fullmm = full_mm_flush;
+
+        return mp;
+}
+
+
+static inline void tlb_flush_mmu(struct mmu_gather *mp)
+{
+        if (mp->need_flush) {
+                free_pages_and_swap_cache(mp->pages, mp->pages_nr);
+                mp->pages_nr = 0;
+                mp->need_flush = 0;
+        }
+
+}
+
+#ifdef CONFIG_SMP
+extern void smp_flush_tlb_mm(struct mm_struct *mm);
+#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
+#else
+#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
+#endif
+
+static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
+{
+        tlb_flush_mmu(mp);
+
+        if (mp->fullmm)
+                mp->fullmm = 0;
+        else
+                flush_tlb_pending();
+
+        /* keep the page table cache within bounds */
+        check_pgt_cache();
+
+        put_cpu_var(mmu_gathers);
+}
+
+static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
+{
+        if (tlb_fast_mode(mp)) {
+                free_page_and_swap_cache(page);
+                return;
+        }
+        mp->need_flush = 1;
+        mp->pages[mp->pages_nr++] = page;
+        if (mp->pages_nr >= FREE_PTE_NR)
+                tlb_flush_mmu(mp);
+}
+
+#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
+#define pte_free_tlb(mp, ptepage) pte_free((mp)->mm, ptepage)
+#define pmd_free_tlb(mp, pmdp) pmd_free((mp)->mm, pmdp)
+#define pud_free_tlb(tlb,pudp) __pud_free_tlb(tlb,pudp)
+
+#define tlb_migrate_finish(mm)  do { } while (0)
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma)   do { } while (0)
+
+#endif /* _SPARC64_TLB_H */
diff --git a/arch/sparc/include/asm/tlbflush.h b/arch/sparc/include/asm/tlbflush.h
new file mode 100644
index 000000000000..2c9629fad1e2
--- /dev/null
+++ b/arch/sparc/include/asm/tlbflush.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_TLBFLUSH_H
+#define ___ASM_SPARC_TLBFLUSH_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/tlbflush_64.h>
+#else
+#include <asm/tlbflush_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/tlbflush_32.h b/arch/sparc/include/asm/tlbflush_32.h
new file mode 100644
index 000000000000..fe0a71abc9bb
--- /dev/null
+++ b/arch/sparc/include/asm/tlbflush_32.h
@@ -0,0 +1,60 @@
+#ifndef _SPARC_TLBFLUSH_H
+#define _SPARC_TLBFLUSH_H
+
+#include <linux/mm.h>
+// #include <asm/processor.h>
+
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb() flushes the current mm struct TLBs    XXX Exists?
+ *  - flush_tlb_all() flushes all processes TLBs
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ */
+
+#ifdef CONFIG_SMP
+
+BTFIXUPDEF_CALL(void, local_flush_tlb_all, void)
+BTFIXUPDEF_CALL(void, local_flush_tlb_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, local_flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, local_flush_tlb_page, struct vm_area_struct *, unsigned long)
+
+#define local_flush_tlb_all() BTFIXUP_CALL(local_flush_tlb_all)()
+#define local_flush_tlb_mm(mm) BTFIXUP_CALL(local_flush_tlb_mm)(mm)
+#define local_flush_tlb_range(vma,start,end) BTFIXUP_CALL(local_flush_tlb_range)(vma,start,end)
+#define local_flush_tlb_page(vma,addr) BTFIXUP_CALL(local_flush_tlb_page)(vma,addr)
+
+extern void smp_flush_tlb_all(void);
+extern void smp_flush_tlb_mm(struct mm_struct *mm);
+extern void smp_flush_tlb_range(struct vm_area_struct *vma,
+                                  unsigned long start,
+                                  unsigned long end);
+extern void smp_flush_tlb_page(struct vm_area_struct *mm, unsigned long page);
+
+#endif /* CONFIG_SMP */
+
+BTFIXUPDEF_CALL(void, flush_tlb_all, void)
+BTFIXUPDEF_CALL(void, flush_tlb_mm, struct mm_struct *)
+BTFIXUPDEF_CALL(void, flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
+BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long)
+
+#define flush_tlb_all() BTFIXUP_CALL(flush_tlb_all)()
+#define flush_tlb_mm(mm) BTFIXUP_CALL(flush_tlb_mm)(mm)
+#define flush_tlb_range(vma,start,end) BTFIXUP_CALL(flush_tlb_range)(vma,start,end)
+#define flush_tlb_page(vma,addr) BTFIXUP_CALL(flush_tlb_page)(vma,addr)
+
+// #define flush_tlb() flush_tlb_mm(current->active_mm) /* XXX Sure? */
+
+/*
+ * This is a kludge, until I know better. --zaitcev XXX
+ */
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+        flush_tlb_all();
+}
+
+#endif /* _SPARC_TLBFLUSH_H */
diff --git a/arch/sparc/include/asm/tlbflush_64.h b/arch/sparc/include/asm/tlbflush_64.h
new file mode 100644
index 000000000000..fbb675dbe0c9
--- /dev/null
+++ b/arch/sparc/include/asm/tlbflush_64.h
@@ -0,0 +1,44 @@
+#ifndef _SPARC64_TLBFLUSH_H
+#define _SPARC64_TLBFLUSH_H
+
+#include <linux/mm.h>
+#include <asm/mmu_context.h>
+
+/* TSB flush operations. */
+struct mmu_gather;
+extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_tsb_user(struct mmu_gather *mp);
+
+/* TLB flush operations. */
+
+extern void flush_tlb_pending(void);
+
+#define flush_tlb_range(vma,start,end)  \
+        do { (void)(start); flush_tlb_pending(); } while (0)
+#define flush_tlb_page(vma,addr)        flush_tlb_pending()
+#define flush_tlb_mm(mm)                flush_tlb_pending()
+
+/* Local cpu only.  */
+extern void __flush_tlb_all(void);
+
+extern void __flush_tlb_kernel_range(unsigned long start, unsigned long end);
+
+#ifndef CONFIG_SMP
+
+#define flush_tlb_kernel_range(start,end) \
+do {    flush_tsb_kernel_range(start,end); \
+        __flush_tlb_kernel_range(start,end); \
+} while (0)
+
+#else /* CONFIG_SMP */
+
+extern void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end);
+
+#define flush_tlb_kernel_range(start, end) \
+do {    flush_tsb_kernel_range(start,end); \
+        smp_flush_tlb_kernel_range(start, end); \
+} while (0)
+
+#endif /* ! CONFIG_SMP */
+
+#endif /* _SPARC64_TLBFLUSH_H */
diff --git a/arch/sparc/include/asm/topology.h b/arch/sparc/include/asm/topology.h
new file mode 100644
index 000000000000..ee4f191d394a
--- /dev/null
+++ b/arch/sparc/include/asm/topology.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_TOPOLOGY_H
+#define ___ASM_SPARC_TOPOLOGY_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/topology_64.h>
+#else
+#include <asm/topology_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/topology_32.h b/arch/sparc/include/asm/topology_32.h
new file mode 100644
index 000000000000..ee5ac9c9da28
--- /dev/null
+++ b/arch/sparc/include/asm/topology_32.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_SPARC_TOPOLOGY_H
+#define _ASM_SPARC_TOPOLOGY_H
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_SPARC_TOPOLOGY_H */
diff --git a/arch/sparc/include/asm/topology_64.h b/arch/sparc/include/asm/topology_64.h
new file mode 100644
index 000000000000..001c04027c82
--- /dev/null
+++ b/arch/sparc/include/asm/topology_64.h
@@ -0,0 +1,86 @@
+#ifndef _ASM_SPARC64_TOPOLOGY_H
+#define _ASM_SPARC64_TOPOLOGY_H
+
+#ifdef CONFIG_NUMA
+
+#include <asm/mmzone.h>
+
+static inline int cpu_to_node(int cpu)
+{
+        return numa_cpu_lookup_table[cpu];
+}
+
+#define parent_node(node)       (node)
+
+static inline cpumask_t node_to_cpumask(int node)
+{
+        return numa_cpumask_lookup_table[node];
+}
+
+/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
+#define node_to_cpumask_ptr(v, node)            \
+                cpumask_t *v = &(numa_cpumask_lookup_table[node])
+
+#define node_to_cpumask_ptr_next(v, node)       \
+                           v = &(numa_cpumask_lookup_table[node])
+
+static inline int node_to_first_cpu(int node)
+{
+        cpumask_t tmp;
+        tmp = node_to_cpumask(node);
+        return first_cpu(tmp);
+}
+
+struct pci_bus;
+#ifdef CONFIG_PCI
+extern int pcibus_to_node(struct pci_bus *pbus);
+#else
+static inline int pcibus_to_node(struct pci_bus *pbus)
+{
+        return -1;
+}
+#endif
+
+#define pcibus_to_cpumask(bus)  \
+        (pcibus_to_node(bus) == -1 ? \
+         CPU_MASK_ALL : \
+         node_to_cpumask(pcibus_to_node(bus)))
+
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .min_interval           = 8,                    \
+        .max_interval           = 32,                   \
+        .busy_factor            = 32,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 2,                    \
+        .busy_idx               = 3,                    \
+        .idle_idx               = 2,                    \
+        .newidle_idx            = 0,                    \
+        .wake_idx               = 1,                    \
+        .forkexec_idx           = 1,                    \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_FORK       \
+                                | SD_BALANCE_EXEC       \
+                                | SD_SERIALIZE          \
+                                | SD_WAKE_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+}
+
+#else /* CONFIG_NUMA */
+
+#include <asm-generic/topology.h>
+
+#endif /* !(CONFIG_NUMA) */
+
+#ifdef CONFIG_SMP
+#define topology_physical_package_id(cpu)       (cpu_data(cpu).proc_id)
+#define topology_core_id(cpu)                   (cpu_data(cpu).core_id)
+#define topology_core_siblings(cpu)             (cpu_core_map[cpu])
+#define topology_thread_siblings(cpu)           (per_cpu(cpu_sibling_map, cpu))
+#define mc_capable()                            (sparc64_multi_core)
+#define smt_capable()                           (sparc64_multi_core)
+#endif /* CONFIG_SMP */
+
+#define cpu_coregroup_map(cpu)                  (cpu_core_map[cpu])
+
+#endif /* _ASM_SPARC64_TOPOLOGY_H */
diff --git a/arch/sparc/include/asm/traps.h b/arch/sparc/include/asm/traps.h
new file mode 100644
index 000000000000..bebdbf8f43a8
--- /dev/null
+++ b/arch/sparc/include/asm/traps.h
@@ -0,0 +1,140 @@
+/*
+ * traps.h:  Format of entries for the Sparc trap table.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_TRAPS_H
+#define _SPARC_TRAPS_H
+
+#define NUM_SPARC_TRAPS  255
+
+#ifndef __ASSEMBLY__
+
+/* This is for V8 compliant Sparc CPUS */
+struct tt_entry {
+        unsigned long inst_one;
+        unsigned long inst_two;
+        unsigned long inst_three;
+        unsigned long inst_four;
+};
+
+/* We set this to _start in system setup. */
+extern struct tt_entry *sparc_ttable;
+
+static inline unsigned long get_tbr(void)
+{
+        unsigned long tbr;
+
+        __asm__ __volatile__("rd %%tbr, %0\n\t" : "=r" (tbr));
+        return tbr;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+/* For patching the trap table at boot time, we need to know how to
+ * form various common Sparc instructions.  Thus these macros...
+ */
+
+#define SPARC_MOV_CONST_L3(const) (0xa6102000 | (const&0xfff))
+
+/* The following assumes that the branch lies before the place we
+ * are branching to.  This is the case for a trap vector...
+ * You have been warned.
+ */
+#define SPARC_BRANCH(dest_addr, inst_addr) \
+          (0x10800000 | (((dest_addr-inst_addr)>>2)&0x3fffff))
+
+#define SPARC_RD_PSR_L0  (0xa1480000)
+#define SPARC_RD_WIM_L3  (0xa7500000)
+#define SPARC_NOP (0x01000000)
+
+/* Various interesting trap levels. */
+/* First, hardware traps. */
+#define SP_TRAP_TFLT    0x1          /* Text fault */
+#define SP_TRAP_II      0x2          /* Illegal Instruction */
+#define SP_TRAP_PI      0x3          /* Privileged Instruction */
+#define SP_TRAP_FPD     0x4          /* Floating Point Disabled */
+#define SP_TRAP_WOVF    0x5          /* Window Overflow */
+#define SP_TRAP_WUNF    0x6          /* Window Underflow */
+#define SP_TRAP_MNA     0x7          /* Memory Address Unaligned */
+#define SP_TRAP_FPE     0x8          /* Floating Point Exception */
+#define SP_TRAP_DFLT    0x9          /* Data Fault */
+#define SP_TRAP_TOF     0xa          /* Tag Overflow */
+#define SP_TRAP_WDOG    0xb          /* Watchpoint Detected */
+#define SP_TRAP_IRQ1    0x11         /* IRQ level 1 */
+#define SP_TRAP_IRQ2    0x12         /* IRQ level 2 */
+#define SP_TRAP_IRQ3    0x13         /* IRQ level 3 */
+#define SP_TRAP_IRQ4    0x14         /* IRQ level 4 */
+#define SP_TRAP_IRQ5    0x15         /* IRQ level 5 */
+#define SP_TRAP_IRQ6    0x16         /* IRQ level 6 */
+#define SP_TRAP_IRQ7    0x17         /* IRQ level 7 */
+#define SP_TRAP_IRQ8    0x18         /* IRQ level 8 */
+#define SP_TRAP_IRQ9    0x19         /* IRQ level 9 */
+#define SP_TRAP_IRQ10   0x1a         /* IRQ level 10 */
+#define SP_TRAP_IRQ11   0x1b         /* IRQ level 11 */
+#define SP_TRAP_IRQ12   0x1c         /* IRQ level 12 */
+#define SP_TRAP_IRQ13   0x1d         /* IRQ level 13 */
+#define SP_TRAP_IRQ14   0x1e         /* IRQ level 14 */
+#define SP_TRAP_IRQ15   0x1f         /* IRQ level 15 Non-maskable */
+#define SP_TRAP_RACC    0x20         /* Register Access Error ??? */
+#define SP_TRAP_IACC    0x21         /* Instruction Access Error */
+#define SP_TRAP_CPDIS   0x24         /* Co-Processor Disabled */
+#define SP_TRAP_BADFL   0x25         /* Unimplemented Flush Instruction */
+#define SP_TRAP_CPEXP   0x28         /* Co-Processor Exception */
+#define SP_TRAP_DACC    0x29         /* Data Access Error */
+#define SP_TRAP_DIVZ    0x2a         /* Divide By Zero */
+#define SP_TRAP_DSTORE  0x2b         /* Data Store Error ??? */
+#define SP_TRAP_DMM     0x2c         /* Data Access MMU Miss ??? */
+#define SP_TRAP_IMM     0x3c         /* Instruction Access MMU Miss ??? */
+
+/* Now the Software Traps... */
+#define SP_TRAP_SUNOS   0x80         /* SunOS System Call */
+#define SP_TRAP_SBPT    0x81         /* Software Breakpoint */
+#define SP_TRAP_SDIVZ   0x82         /* Software Divide-by-Zero trap */
+#define SP_TRAP_FWIN    0x83         /* Flush Windows */
+#define SP_TRAP_CWIN    0x84         /* Clean Windows */
+#define SP_TRAP_RCHK    0x85         /* Range Check */
+#define SP_TRAP_FUNA    0x86         /* Fix Unaligned Access */
+#define SP_TRAP_IOWFL   0x87         /* Integer Overflow */
+#define SP_TRAP_SOLARIS 0x88         /* Solaris System Call */
+#define SP_TRAP_NETBSD  0x89         /* NetBSD System Call */
+#define SP_TRAP_LINUX   0x90         /* Linux System Call */
+
+/* Names used for compatibility with SunOS */
+#define ST_SYSCALL              0x00
+#define ST_BREAKPOINT           0x01
+#define ST_DIV0                 0x02
+#define ST_FLUSH_WINDOWS        0x03
+#define ST_CLEAN_WINDOWS        0x04
+#define ST_RANGE_CHECK          0x05
+#define ST_FIX_ALIGN            0x06
+#define ST_INT_OVERFLOW         0x07
+
+/* Special traps... */
+#define SP_TRAP_KBPT1   0xfe         /* KADB/PROM Breakpoint one */
+#define SP_TRAP_KBPT2   0xff         /* KADB/PROM Breakpoint two */
+
+/* Handy Macros */
+/* Is this a trap we never expect to get? */
+#define BAD_TRAP_P(level) \
+        ((level > SP_TRAP_WDOG && level < SP_TRAP_IRQ1) || \
+         (level > SP_TRAP_IACC && level < SP_TRAP_CPDIS) || \
+         (level > SP_TRAP_BADFL && level < SP_TRAP_CPEXP) || \
+         (level > SP_TRAP_DMM && level < SP_TRAP_IMM) || \
+         (level > SP_TRAP_IMM && level < SP_TRAP_SUNOS) || \
+         (level > SP_TRAP_LINUX && level < SP_TRAP_KBPT1))
+
+/* Is this a Hardware trap? */
+#define HW_TRAP_P(level) ((level > 0) && (level < SP_TRAP_SUNOS))
+
+/* Is this a Software trap? */
+#define SW_TRAP_P(level) ((level >= SP_TRAP_SUNOS) && (level <= SP_TRAP_KBPT2))
+
+/* Is this a system call for some OS we know about? */
+#define SCALL_TRAP_P(level) ((level == SP_TRAP_SUNOS) || \
+                             (level == SP_TRAP_SOLARIS) || \
+                             (level == SP_TRAP_NETBSD) || \
+                             (level == SP_TRAP_LINUX))
+
+#endif /* !(_SPARC_TRAPS_H) */
diff --git a/arch/sparc/include/asm/tsb.h b/arch/sparc/include/asm/tsb.h
new file mode 100644
index 000000000000..76e4299dd9bc
--- /dev/null
+++ b/arch/sparc/include/asm/tsb.h
@@ -0,0 +1,283 @@
+#ifndef _SPARC64_TSB_H
+#define _SPARC64_TSB_H
+
+/* The sparc64 TSB is similar to the powerpc hashtables.  It's a
+ * power-of-2 sized table of TAG/PTE pairs.  The cpu precomputes
+ * pointers into this table for 8K and 64K page sizes, and also a
+ * comparison TAG based upon the virtual address and context which
+ * faults.
+ *
+ * TLB miss trap handler software does the actual lookup via something
+ * of the form:
+ *
+ *      ldxa            [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
+ *      ldxa            [%g0] ASI_{D,I}MMU, %g6
+ *      sllx            %g6, 22, %g6
+ *      srlx            %g6, 22, %g6
+ *      ldda            [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
+ *      cmp             %g4, %g6
+ *      bne,pn  %xcc, tsb_miss_{d,i}tlb
+ *       mov            FAULT_CODE_{D,I}TLB, %g3
+ *      stxa            %g5, [%g0] ASI_{D,I}TLB_DATA_IN
+ *      retry
+ *
+ *
+ * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
+ * PTE.  The TAG is of the same layout as the TLB TAG TARGET mmu
+ * register which is:
+ *
+ * -------------------------------------------------
+ * |  -  |  CONTEXT |  -  |    VADDR bits 63:22    |
+ * -------------------------------------------------
+ *  63 61 60      48 47 42 41                     0
+ *
+ * But actually, since we use per-mm TSB's, we zero out the CONTEXT
+ * field.
+ *
+ * Like the powerpc hashtables we need to use locking in order to
+ * synchronize while we update the entries.  PTE updates need locking
+ * as well.
+ *
+ * We need to carefully choose a lock bits for the TSB entry.  We
+ * choose to use bit 47 in the tag.  Also, since we never map anything
+ * at page zero in context zero, we use zero as an invalid tag entry.
+ * When the lock bit is set, this forces a tag comparison failure.
+ */
+
+#define TSB_TAG_LOCK_BIT        47
+#define TSB_TAG_LOCK_HIGH       (1 << (TSB_TAG_LOCK_BIT - 32))
+
+#define TSB_TAG_INVALID_BIT     46
+#define TSB_TAG_INVALID_HIGH    (1 << (TSB_TAG_INVALID_BIT - 32))
+
+#define TSB_MEMBAR      membar  #StoreStore
+
+/* Some cpus support physical address quad loads.  We want to use
+ * those if possible so we don't need to hard-lock the TSB mapping
+ * into the TLB.  We encode some instruction patching in order to
+ * support this.
+ *
+ * The kernel TSB is locked into the TLB by virtue of being in the
+ * kernel image, so we don't play these games for swapper_tsb access.
+ */
+#ifndef __ASSEMBLY__
+struct tsb_ldquad_phys_patch_entry {
+        unsigned int    addr;
+        unsigned int    sun4u_insn;
+        unsigned int    sun4v_insn;
+};
+extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
+        __tsb_ldquad_phys_patch_end;
+
+struct tsb_phys_patch_entry {
+        unsigned int    addr;
+        unsigned int    insn;
+};
+extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
+#endif
+#define TSB_LOAD_QUAD(TSB, REG) \
+661:    ldda            [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
+        .section        .tsb_ldquad_phys_patch, "ax"; \
+        .word           661b; \
+        ldda            [TSB] ASI_QUAD_LDD_PHYS, REG; \
+        ldda            [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
+        .previous
+
+#define TSB_LOAD_TAG_HIGH(TSB, REG) \
+661:    lduwa           [TSB] ASI_N, REG; \
+        .section        .tsb_phys_patch, "ax"; \
+        .word           661b; \
+        lduwa           [TSB] ASI_PHYS_USE_EC, REG; \
+        .previous
+
+#define TSB_LOAD_TAG(TSB, REG) \
+661:    ldxa            [TSB] ASI_N, REG; \
+        .section        .tsb_phys_patch, "ax"; \
+        .word           661b; \
+        ldxa            [TSB] ASI_PHYS_USE_EC, REG; \
+        .previous
+
+#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
+661:    casa            [TSB] ASI_N, REG1, REG2; \
+        .section        .tsb_phys_patch, "ax"; \
+        .word           661b; \
+        casa            [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
+        .previous
+
+#define TSB_CAS_TAG(TSB, REG1, REG2) \
+661:    casxa           [TSB] ASI_N, REG1, REG2; \
+        .section        .tsb_phys_patch, "ax"; \
+        .word           661b; \
+        casxa           [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
+        .previous
+
+#define TSB_STORE(ADDR, VAL) \
+661:    stxa            VAL, [ADDR] ASI_N; \
+        .section        .tsb_phys_patch, "ax"; \
+        .word           661b; \
+        stxa            VAL, [ADDR] ASI_PHYS_USE_EC; \
+        .previous
+
+#define TSB_LOCK_TAG(TSB, REG1, REG2)   \
+99:     TSB_LOAD_TAG_HIGH(TSB, REG1);   \
+        sethi   %hi(TSB_TAG_LOCK_HIGH), REG2;\
+        andcc   REG1, REG2, %g0;        \
+        bne,pn  %icc, 99b;              \
+         nop;                           \
+        TSB_CAS_TAG_HIGH(TSB, REG1, REG2);      \
+        cmp     REG1, REG2;             \
+        bne,pn  %icc, 99b;              \
+         nop;                           \
+        TSB_MEMBAR
+
+#define TSB_WRITE(TSB, TTE, TAG) \
+        add     TSB, 0x8, TSB;   \
+        TSB_STORE(TSB, TTE);     \
+        sub     TSB, 0x8, TSB;   \
+        TSB_MEMBAR;              \
+        TSB_STORE(TSB, TAG);
+
+#define KTSB_LOAD_QUAD(TSB, REG) \
+        ldda            [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
+
+#define KTSB_STORE(ADDR, VAL) \
+        stxa            VAL, [ADDR] ASI_N;
+
+#define KTSB_LOCK_TAG(TSB, REG1, REG2)  \
+99:     lduwa   [TSB] ASI_N, REG1;      \
+        sethi   %hi(TSB_TAG_LOCK_HIGH), REG2;\
+        andcc   REG1, REG2, %g0;        \
+        bne,pn  %icc, 99b;              \
+         nop;                           \
+        casa    [TSB] ASI_N, REG1, REG2;\
+        cmp     REG1, REG2;             \
+        bne,pn  %icc, 99b;              \
+         nop;                           \
+        TSB_MEMBAR
+
+#define KTSB_WRITE(TSB, TTE, TAG) \
+        add     TSB, 0x8, TSB;   \
+        stxa    TTE, [TSB] ASI_N;     \
+        sub     TSB, 0x8, TSB;   \
+        TSB_MEMBAR;              \
+        stxa    TAG, [TSB] ASI_N;
+
+        /* Do a kernel page table walk.  Leaves physical PTE pointer in
+         * REG1.  Jumps to FAIL_LABEL on early page table walk termination.
+         * VADDR will not be clobbered, but REG2 will.
+         */
+#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL)        \
+        sethi           %hi(swapper_pg_dir), REG1; \
+        or              REG1, %lo(swapper_pg_dir), REG1; \
+        sllx            VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
+        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
+        andn            REG2, 0x3, REG2; \
+        lduw            [REG1 + REG2], REG1; \
+        brz,pn          REG1, FAIL_LABEL; \
+         sllx           VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
+        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
+        sllx            REG1, 11, REG1; \
+        andn            REG2, 0x3, REG2; \
+        lduwa           [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
+        brz,pn          REG1, FAIL_LABEL; \
+         sllx           VADDR, 64 - PMD_SHIFT, REG2; \
+        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
+        sllx            REG1, 11, REG1; \
+        andn            REG2, 0x7, REG2; \
+        add             REG1, REG2, REG1;
+
+        /* Do a user page table walk in MMU globals.  Leaves physical PTE
+         * pointer in REG1.  Jumps to FAIL_LABEL on early page table walk
+         * termination.  Physical base of page tables is in PHYS_PGD which
+         * will not be modified.
+         *
+         * VADDR will not be clobbered, but REG1 and REG2 will.
+         */
+#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL)  \
+        sllx            VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
+        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
+        andn            REG2, 0x3, REG2; \
+        lduwa           [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
+        brz,pn          REG1, FAIL_LABEL; \
+         sllx           VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
+        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
+        sllx            REG1, 11, REG1; \
+        andn            REG2, 0x3, REG2; \
+        lduwa           [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
+        brz,pn          REG1, FAIL_LABEL; \
+         sllx           VADDR, 64 - PMD_SHIFT, REG2; \
+        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
+        sllx            REG1, 11, REG1; \
+        andn            REG2, 0x7, REG2; \
+        add             REG1, REG2, REG1;
+
+/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
+ * If no entry is found, FAIL_LABEL will be branched to.  On success
+ * the resulting PTE value will be left in REG1.  VADDR is preserved
+ * by this routine.
+ */
+#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
+        sethi           %hi(prom_trans), REG1; \
+        or              REG1, %lo(prom_trans), REG1; \
+97:     ldx             [REG1 + 0x00], REG2; \
+        brz,pn          REG2, FAIL_LABEL; \
+         nop; \
+        ldx             [REG1 + 0x08], REG3; \
+        add             REG2, REG3, REG3; \
+        cmp             REG2, VADDR; \
+        bgu,pt          %xcc, 98f; \
+         cmp            VADDR, REG3; \
+        bgeu,pt         %xcc, 98f; \
+         ldx            [REG1 + 0x10], REG3; \
+        sub             VADDR, REG2, REG2; \
+        ba,pt           %xcc, 99f; \
+         add            REG3, REG2, REG1; \
+98:     ba,pt           %xcc, 97b; \
+         add            REG1, (3 * 8), REG1; \
+99:
+
+        /* We use a 32K TSB for the whole kernel, this allows to
+         * handle about 16MB of modules and vmalloc mappings without
+         * incurring many hash conflicts.
+         */
+#define KERNEL_TSB_SIZE_BYTES   (32 * 1024)
+#define KERNEL_TSB_NENTRIES     \
+        (KERNEL_TSB_SIZE_BYTES / 16)
+#define KERNEL_TSB4M_NENTRIES   4096
+
+        /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
+         * on TSB hit.  REG1, REG2, REG3, and REG4 are used as temporaries
+         * and the found TTE will be left in REG1.  REG3 and REG4 must
+         * be an even/odd pair of registers.
+         *
+         * VADDR and TAG will be preserved and not clobbered by this macro.
+         */
+#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
+        sethi           %hi(swapper_tsb), REG1; \
+        or              REG1, %lo(swapper_tsb), REG1; \
+        srlx            VADDR, PAGE_SHIFT, REG2; \
+        and             REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
+        sllx            REG2, 4, REG2; \
+        add             REG1, REG2, REG2; \
+        KTSB_LOAD_QUAD(REG2, REG3); \
+        cmp             REG3, TAG; \
+        be,a,pt         %xcc, OK_LABEL; \
+         mov            REG4, REG1;
+
+#ifndef CONFIG_DEBUG_PAGEALLOC
+        /* This version uses a trick, the TAG is already (VADDR >> 22) so
+         * we can make use of that for the index computation.
+         */
+#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
+        sethi           %hi(swapper_4m_tsb), REG1; \
+        or              REG1, %lo(swapper_4m_tsb), REG1; \
+        and             TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
+        sllx            REG2, 4, REG2; \
+        add             REG1, REG2, REG2; \
+        KTSB_LOAD_QUAD(REG2, REG3); \
+        cmp             REG3, TAG; \
+        be,a,pt         %xcc, OK_LABEL; \
+         mov            REG4, REG1;
+#endif
+
+#endif /* !(_SPARC64_TSB_H) */
diff --git a/arch/sparc/include/asm/tsunami.h b/arch/sparc/include/asm/tsunami.h
new file mode 100644
index 000000000000..5bbd1d523baa
--- /dev/null
+++ b/arch/sparc/include/asm/tsunami.h
@@ -0,0 +1,64 @@
+/*
+ * tsunami.h:  Module specific definitions for Tsunami V8 Sparcs
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_TSUNAMI_H
+#define _SPARC_TSUNAMI_H
+
+#include <asm/asi.h>
+
+/* The MMU control register on the Tsunami:
+ *
+ * -----------------------------------------------------------------------
+ * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
+ * -----------------------------------------------------------------------
+ *  31      24 23 22 21 20 19-18 17  16 14  13-12 11 10-9  8  7 6-2  1  0
+ *
+ * SW: Enable Software Table Walks  0=off 1=on
+ * AV: Address View bit
+ * DV: Data View bit
+ * MV: Memory View bit
+ * PC: Parity Control
+ * ITD: ITBR disable
+ * ALC: Alternate Cacheable
+ * PE: Parity Enable   0=off 1=on
+ * RC: Refresh Control
+ * IE: Instruction cache Enable  0=off 1=on
+ * DE: Data cache Enable  0=off 1=on
+ * NF: No Fault, same as all other SRMMUs
+ * ME: MMU Enable, same as all other SRMMUs
+ */
+
+#define TSUNAMI_SW        0x00800000
+#define TSUNAMI_AV        0x00400000
+#define TSUNAMI_DV        0x00200000
+#define TSUNAMI_MV        0x00100000
+#define TSUNAMI_PC        0x00020000
+#define TSUNAMI_ITD       0x00010000
+#define TSUNAMI_ALC       0x00008000
+#define TSUNAMI_PE        0x00001000
+#define TSUNAMI_RCMASK    0x00000C00
+#define TSUNAMI_IENAB     0x00000200
+#define TSUNAMI_DENAB     0x00000100
+#define TSUNAMI_NF        0x00000002
+#define TSUNAMI_ME        0x00000001
+
+static inline void tsunami_flush_icache(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+                             : /* no outputs */
+                             : "i" (ASI_M_IC_FLCLEAR)
+                             : "memory");
+}
+
+static inline void tsunami_flush_dcache(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+                             : /* no outputs */
+                             : "i" (ASI_M_DC_FLCLEAR)
+                             : "memory");
+}
+
+#endif /* !(_SPARC_TSUNAMI_H) */
diff --git a/arch/sparc/include/asm/ttable.h b/arch/sparc/include/asm/ttable.h
new file mode 100644
index 000000000000..5708ba2719fb
--- /dev/null
+++ b/arch/sparc/include/asm/ttable.h
@@ -0,0 +1,658 @@
+#ifndef _SPARC64_TTABLE_H
+#define _SPARC64_TTABLE_H
+
+#include <asm/utrap.h>
+
+#ifdef __ASSEMBLY__
+#include <asm/thread_info.h>
+#endif
+
+#define BOOT_KERNEL b sparc64_boot; nop; nop; nop; nop; nop; nop; nop;
+
+/* We need a "cleaned" instruction... */
+#define CLEAN_WINDOW                                                    \
+        rdpr    %cleanwin, %l0;         add     %l0, 1, %l0;            \
+        wrpr    %l0, 0x0, %cleanwin;                                    \
+        clr     %o0;    clr     %o1;    clr     %o2;    clr     %o3;    \
+        clr     %o4;    clr     %o5;    clr     %o6;    clr     %o7;    \
+        clr     %l0;    clr     %l1;    clr     %l2;    clr     %l3;    \
+        clr     %l4;    clr     %l5;    clr     %l6;    clr     %l7;    \
+        retry;                                                          \
+        nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
+
+#define TRAP(routine)                                   \
+        sethi   %hi(109f), %g7;                         \
+        ba,pt   %xcc, etrap;                            \
+109:     or     %g7, %lo(109b), %g7;                    \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o0;                   \
+        ba,pt   %xcc, rtrap;                            \
+         nop;                                           \
+        nop;
+
+#define TRAP_7INSNS(routine)                            \
+        sethi   %hi(109f), %g7;                         \
+        ba,pt   %xcc, etrap;                            \
+109:     or     %g7, %lo(109b), %g7;                    \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o0;                   \
+        ba,pt   %xcc, rtrap;                            \
+         nop;
+
+#define TRAP_SAVEFPU(routine)                           \
+        sethi   %hi(109f), %g7;                         \
+        ba,pt   %xcc, do_fptrap;                        \
+109:     or     %g7, %lo(109b), %g7;                    \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o0;                   \
+        ba,pt   %xcc, rtrap;                            \
+         nop;                                           \
+        nop;
+
+#define TRAP_NOSAVE(routine)                            \
+        ba,pt   %xcc, routine;                          \
+         nop;                                           \
+        nop; nop; nop; nop; nop; nop;
+
+#define TRAP_NOSAVE_7INSNS(routine)                     \
+        ba,pt   %xcc, routine;                          \
+         nop;                                           \
+        nop; nop; nop; nop; nop;
+
+#define TRAPTL1(routine)                                \
+        sethi   %hi(109f), %g7;                         \
+        ba,pt   %xcc, etraptl1;                         \
+109:     or     %g7, %lo(109b), %g7;                    \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o0;                   \
+        ba,pt   %xcc, rtrap;                            \
+         nop;                                           \
+        nop;
+
+#define TRAP_ARG(routine, arg)                          \
+        sethi   %hi(109f), %g7;                         \
+        ba,pt   %xcc, etrap;                            \
+109:     or     %g7, %lo(109b), %g7;                    \
+        add     %sp, PTREGS_OFF, %o0;                   \
+        call    routine;                                \
+         mov    arg, %o1;                               \
+        ba,pt   %xcc, rtrap;                            \
+         nop;
+
+#define TRAPTL1_ARG(routine, arg)                       \
+        sethi   %hi(109f), %g7;                         \
+        ba,pt   %xcc, etraptl1;                         \
+109:     or     %g7, %lo(109b), %g7;                    \
+        add     %sp, PTREGS_OFF, %o0;                   \
+        call    routine;                                \
+         mov    arg, %o1;                               \
+        ba,pt   %xcc, rtrap;                            \
+         nop;
+
+#define SYSCALL_TRAP(routine, systbl)                   \
+        rdpr    %pil, %g2;                              \
+        mov     TSTATE_SYSCALL, %g3;                    \
+        sethi   %hi(109f), %g7;                         \
+        ba,pt   %xcc, etrap_syscall;                    \
+109:     or     %g7, %lo(109b), %g7;                    \
+        sethi   %hi(systbl), %l7;                       \
+        ba,pt   %xcc, routine;                          \
+         or     %l7, %lo(systbl), %l7;
+
+#define TRAP_UTRAP(handler,lvl)                         \
+        mov     handler, %g3;                           \
+        ba,pt   %xcc, utrap_trap;                       \
+         mov    lvl, %g4;                               \
+        nop;                                            \
+        nop;                                            \
+        nop;                                            \
+        nop;                                            \
+        nop;
+
+#ifdef CONFIG_COMPAT
+#define LINUX_32BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sys_call_table32)
+#else
+#define LINUX_32BIT_SYSCALL_TRAP BTRAP(0x110)
+#endif
+#define LINUX_64BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall, sys_call_table64)
+#define GETCC_TRAP TRAP(getcc)
+#define SETCC_TRAP TRAP(setcc)
+#define BREAKPOINT_TRAP TRAP(breakpoint_trap)
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+
+#define TRAP_IRQ(routine, level)                        \
+        rdpr    %pil, %g2;                              \
+        wrpr    %g0, 15, %pil;                          \
+        sethi   %hi(1f-4), %g7;                         \
+        ba,pt   %xcc, etrap_irq;                        \
+         or     %g7, %lo(1f-4), %g7;                    \
+        nop;                                            \
+        nop;                                            \
+        nop;                                            \
+        .subsection     2;                              \
+1:      call    trace_hardirqs_off;                     \
+         nop;                                           \
+        mov     level, %o0;                             \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o1;                   \
+        ba,a,pt %xcc, rtrap_irq;                        \
+        .previous;
+
+#else
+
+#define TRAP_IRQ(routine, level)                        \
+        rdpr    %pil, %g2;                              \
+        wrpr    %g0, 15, %pil;                          \
+        ba,pt   %xcc, etrap_irq;                        \
+         rd     %pc, %g7;                               \
+        mov     level, %o0;                             \
+        call    routine;                                \
+         add    %sp, PTREGS_OFF, %o1;                   \
+        ba,a,pt %xcc, rtrap_irq;
+
+#endif
+
+#define TRAP_IVEC TRAP_NOSAVE(do_ivec)
+
+#define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)
+
+#define BTRAPTL1(lvl) TRAPTL1_ARG(bad_trap_tl1, lvl)
+
+#define FLUSH_WINDOW_TRAP                                               \
+        ba,pt   %xcc, etrap;                                            \
+         rd     %pc, %g7;                                               \
+        flushw;                                                         \
+        ldx     [%sp + PTREGS_OFF + PT_V9_TNPC], %l1;                   \
+        add     %l1, 4, %l2;                                            \
+        stx     %l1, [%sp + PTREGS_OFF + PT_V9_TPC];                    \
+        ba,pt   %xcc, rtrap;                                            \
+         stx    %l2, [%sp + PTREGS_OFF + PT_V9_TNPC];
+
+#ifdef CONFIG_KPROBES
+#define KPROBES_TRAP(lvl) TRAP_IRQ(kprobe_trap, lvl)
+#else
+#define KPROBES_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
+#endif
+
+#ifdef CONFIG_KGDB
+#define KGDB_TRAP(lvl) TRAP_IRQ(kgdb_trap, lvl)
+#else
+#define KGDB_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
+#endif
+
+#define SUN4V_ITSB_MISS                                 \
+        ldxa    [%g0] ASI_SCRATCHPAD, %g2;              \
+        ldx     [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4;    \
+        ldx     [%g2 + HV_FAULT_I_CTX_OFFSET], %g5;     \
+        srlx    %g4, 22, %g6;                           \
+        ba,pt   %xcc, sun4v_itsb_miss;                  \
+         nop;                                           \
+        nop;                                            \
+        nop;
+
+#define SUN4V_DTSB_MISS                                 \
+        ldxa    [%g0] ASI_SCRATCHPAD, %g2;              \
+        ldx     [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4;    \
+        ldx     [%g2 + HV_FAULT_D_CTX_OFFSET], %g5;     \
+        srlx    %g4, 22, %g6;                           \
+        ba,pt   %xcc, sun4v_dtsb_miss;                  \
+         nop;                                           \
+        nop;                                            \
+        nop;
+
+/* Before touching these macros, you owe it to yourself to go and
+ * see how arch/sparc64/kernel/winfixup.S works... -DaveM
+ *
+ * For the user cases we used to use the %asi register, but
+ * it turns out that the "wr xxx, %asi" costs ~5 cycles, so
+ * now we use immediate ASI loads and stores instead.  Kudos
+ * to Greg Onufer for pointing out this performance anomaly.
+ *
+ * Further note that we cannot use the g2, g4, g5, and g7 alternate
+ * globals in the spill routines, check out the save instruction in
+ * arch/sparc64/kernel/etrap.S to see what I mean about g2, and
+ * g4/g5 are the globals which are preserved by etrap processing
+ * for the caller of it.  The g7 register is the return pc for
+ * etrap.  Finally, g6 is the current thread register so we cannot
+ * us it in the spill handlers either.  Most of these rules do not
+ * apply to fill processing, only g6 is not usable.
+ */
+
+/* Normal kernel spill */
+#define SPILL_0_NORMAL                                  \
+        stx     %l0, [%sp + STACK_BIAS + 0x00];         \
+        stx     %l1, [%sp + STACK_BIAS + 0x08];         \
+        stx     %l2, [%sp + STACK_BIAS + 0x10];         \
+        stx     %l3, [%sp + STACK_BIAS + 0x18];         \
+        stx     %l4, [%sp + STACK_BIAS + 0x20];         \
+        stx     %l5, [%sp + STACK_BIAS + 0x28];         \
+        stx     %l6, [%sp + STACK_BIAS + 0x30];         \
+        stx     %l7, [%sp + STACK_BIAS + 0x38];         \
+        stx     %i0, [%sp + STACK_BIAS + 0x40];         \
+        stx     %i1, [%sp + STACK_BIAS + 0x48];         \
+        stx     %i2, [%sp + STACK_BIAS + 0x50];         \
+        stx     %i3, [%sp + STACK_BIAS + 0x58];         \
+        stx     %i4, [%sp + STACK_BIAS + 0x60];         \
+        stx     %i5, [%sp + STACK_BIAS + 0x68];         \
+        stx     %i6, [%sp + STACK_BIAS + 0x70];         \
+        stx     %i7, [%sp + STACK_BIAS + 0x78];         \
+        saved; retry; nop; nop; nop; nop; nop; nop;     \
+        nop; nop; nop; nop; nop; nop; nop; nop;
+
+#define SPILL_0_NORMAL_ETRAP                            \
+etrap_kernel_spill:                                     \
+        stx     %l0, [%sp + STACK_BIAS + 0x00];         \
+        stx     %l1, [%sp + STACK_BIAS + 0x08];         \
+        stx     %l2, [%sp + STACK_BIAS + 0x10];         \
+        stx     %l3, [%sp + STACK_BIAS + 0x18];         \
+        stx     %l4, [%sp + STACK_BIAS + 0x20];         \
+        stx     %l5, [%sp + STACK_BIAS + 0x28];         \
+        stx     %l6, [%sp + STACK_BIAS + 0x30];         \
+        stx     %l7, [%sp + STACK_BIAS + 0x38];         \
+        stx     %i0, [%sp + STACK_BIAS + 0x40];         \
+        stx     %i1, [%sp + STACK_BIAS + 0x48];         \
+        stx     %i2, [%sp + STACK_BIAS + 0x50];         \
+        stx     %i3, [%sp + STACK_BIAS + 0x58];         \
+        stx     %i4, [%sp + STACK_BIAS + 0x60];         \
+        stx     %i5, [%sp + STACK_BIAS + 0x68];         \
+        stx     %i6, [%sp + STACK_BIAS + 0x70];         \
+        stx     %i7, [%sp + STACK_BIAS + 0x78];         \
+        saved;                                          \
+        sub     %g1, 2, %g1;                            \
+        ba,pt   %xcc, etrap_save;                       \
+        wrpr    %g1, %cwp;                              \
+        nop; nop; nop; nop; nop; nop; nop; nop;         \
+        nop; nop; nop; nop;
+
+/* Normal 64bit spill */
+#define SPILL_1_GENERIC(ASI)                            \
+        add     %sp, STACK_BIAS + 0x00, %g1;            \
+        stxa    %l0, [%g1 + %g0] ASI;                   \
+        mov     0x08, %g3;                              \
+        stxa    %l1, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x10, %g1;                         \
+        stxa    %l2, [%g1 + %g0] ASI;                   \
+        stxa    %l3, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x10, %g1;                         \
+        stxa    %l4, [%g1 + %g0] ASI;                   \
+        stxa    %l5, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x10, %g1;                         \
+        stxa    %l6, [%g1 + %g0] ASI;                   \
+        stxa    %l7, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x10, %g1;                         \
+        stxa    %i0, [%g1 + %g0] ASI;                   \
+        stxa    %i1, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x10, %g1;                         \
+        stxa    %i2, [%g1 + %g0] ASI;                   \
+        stxa    %i3, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x10, %g1;                         \
+        stxa    %i4, [%g1 + %g0] ASI;                   \
+        stxa    %i5, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x10, %g1;                         \
+        stxa    %i6, [%g1 + %g0] ASI;                   \
+        stxa    %i7, [%g1 + %g3] ASI;                   \
+        saved;                                          \
+        retry; nop; nop;                                \
+        b,a,pt  %xcc, spill_fixup_dax;                  \
+        b,a,pt  %xcc, spill_fixup_mna;                  \
+        b,a,pt  %xcc, spill_fixup;
+
+#define SPILL_1_GENERIC_ETRAP                           \
+etrap_user_spill_64bit:                                 \
+        stxa    %l0, [%sp + STACK_BIAS + 0x00] %asi;    \
+        stxa    %l1, [%sp + STACK_BIAS + 0x08] %asi;    \
+        stxa    %l2, [%sp + STACK_BIAS + 0x10] %asi;    \
+        stxa    %l3, [%sp + STACK_BIAS + 0x18] %asi;    \
+        stxa    %l4, [%sp + STACK_BIAS + 0x20] %asi;    \
+        stxa    %l5, [%sp + STACK_BIAS + 0x28] %asi;    \
+        stxa    %l6, [%sp + STACK_BIAS + 0x30] %asi;    \
+        stxa    %l7, [%sp + STACK_BIAS + 0x38] %asi;    \
+        stxa    %i0, [%sp + STACK_BIAS + 0x40] %asi;    \
+        stxa    %i1, [%sp + STACK_BIAS + 0x48] %asi;    \
+        stxa    %i2, [%sp + STACK_BIAS + 0x50] %asi;    \
+        stxa    %i3, [%sp + STACK_BIAS + 0x58] %asi;    \
+        stxa    %i4, [%sp + STACK_BIAS + 0x60] %asi;    \
+        stxa    %i5, [%sp + STACK_BIAS + 0x68] %asi;    \
+        stxa    %i6, [%sp + STACK_BIAS + 0x70] %asi;    \
+        stxa    %i7, [%sp + STACK_BIAS + 0x78] %asi;    \
+        saved;                                          \
+        sub     %g1, 2, %g1;                            \
+        ba,pt   %xcc, etrap_save;                       \
+         wrpr   %g1, %cwp;                              \
+        nop; nop; nop; nop; nop;                        \
+        nop; nop; nop; nop;                             \
+        ba,a,pt %xcc, etrap_spill_fixup_64bit;          \
+        ba,a,pt %xcc, etrap_spill_fixup_64bit;          \
+        ba,a,pt %xcc, etrap_spill_fixup_64bit;
+
+#define SPILL_1_GENERIC_ETRAP_FIXUP                     \
+etrap_spill_fixup_64bit:                                \
+        ldub    [%g6 + TI_WSAVED], %g1;                 \
+        sll     %g1, 3, %g3;                            \
+        add     %g6, %g3, %g3;                          \
+        stx     %sp, [%g3 + TI_RWIN_SPTRS];             \
+        sll     %g1, 7, %g3;                            \
+        add     %g6, %g3, %g3;                          \
+        stx     %l0, [%g3 + TI_REG_WINDOW + 0x00];      \
+        stx     %l1, [%g3 + TI_REG_WINDOW + 0x08];      \
+        stx     %l2, [%g3 + TI_REG_WINDOW + 0x10];      \
+        stx     %l3, [%g3 + TI_REG_WINDOW + 0x18];      \
+        stx     %l4, [%g3 + TI_REG_WINDOW + 0x20];      \
+        stx     %l5, [%g3 + TI_REG_WINDOW + 0x28];      \
+        stx     %l6, [%g3 + TI_REG_WINDOW + 0x30];      \
+        stx     %l7, [%g3 + TI_REG_WINDOW + 0x38];      \
+        stx     %i0, [%g3 + TI_REG_WINDOW + 0x40];      \
+        stx     %i1, [%g3 + TI_REG_WINDOW + 0x48];      \
+        stx     %i2, [%g3 + TI_REG_WINDOW + 0x50];      \
+        stx     %i3, [%g3 + TI_REG_WINDOW + 0x58];      \
+        stx     %i4, [%g3 + TI_REG_WINDOW + 0x60];      \
+        stx     %i5, [%g3 + TI_REG_WINDOW + 0x68];      \
+        stx     %i6, [%g3 + TI_REG_WINDOW + 0x70];      \
+        stx     %i7, [%g3 + TI_REG_WINDOW + 0x78];      \
+        add     %g1, 1, %g1;                            \
+        stb     %g1, [%g6 + TI_WSAVED];                 \
+        saved;                                          \
+        rdpr    %cwp, %g1;                              \
+        sub     %g1, 2, %g1;                            \
+        ba,pt   %xcc, etrap_save;                       \
+         wrpr   %g1, %cwp;                              \
+        nop; nop; nop
+
+/* Normal 32bit spill */
+#define SPILL_2_GENERIC(ASI)                            \
+        srl     %sp, 0, %sp;                            \
+        stwa    %l0, [%sp + %g0] ASI;                   \
+        mov     0x04, %g3;                              \
+        stwa    %l1, [%sp + %g3] ASI;                   \
+        add     %sp, 0x08, %g1;                         \
+        stwa    %l2, [%g1 + %g0] ASI;                   \
+        stwa    %l3, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x08, %g1;                         \
+        stwa    %l4, [%g1 + %g0] ASI;                   \
+        stwa    %l5, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x08, %g1;                         \
+        stwa    %l6, [%g1 + %g0] ASI;                   \
+        stwa    %l7, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x08, %g1;                         \
+        stwa    %i0, [%g1 + %g0] ASI;                   \
+        stwa    %i1, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x08, %g1;                         \
+        stwa    %i2, [%g1 + %g0] ASI;                   \
+        stwa    %i3, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x08, %g1;                         \
+        stwa    %i4, [%g1 + %g0] ASI;                   \
+        stwa    %i5, [%g1 + %g3] ASI;                   \
+        add     %g1, 0x08, %g1;                         \
+        stwa    %i6, [%g1 + %g0] ASI;                   \
+        stwa    %i7, [%g1 + %g3] ASI;                   \
+        saved;                                          \
+        retry; nop; nop;                                \
+        b,a,pt  %xcc, spill_fixup_dax;                  \
+        b,a,pt  %xcc, spill_fixup_mna;                  \
+        b,a,pt  %xcc, spill_fixup;
+
+#define SPILL_2_GENERIC_ETRAP           \
+etrap_user_spill_32bit:                 \
+        srl     %sp, 0, %sp;            \
+        stwa    %l0, [%sp + 0x00] %asi; \
+        stwa    %l1, [%sp + 0x04] %asi; \
+        stwa    %l2, [%sp + 0x08] %asi; \
+        stwa    %l3, [%sp + 0x0c] %asi; \
+        stwa    %l4, [%sp + 0x10] %asi; \
+        stwa    %l5, [%sp + 0x14] %asi; \
+        stwa    %l6, [%sp + 0x18] %asi; \
+        stwa    %l7, [%sp + 0x1c] %asi; \
+        stwa    %i0, [%sp + 0x20] %asi; \
+        stwa    %i1, [%sp + 0x24] %asi; \
+        stwa    %i2, [%sp + 0x28] %asi; \
+        stwa    %i3, [%sp + 0x2c] %asi; \
+        stwa    %i4, [%sp + 0x30] %asi; \
+        stwa    %i5, [%sp + 0x34] %asi; \
+        stwa    %i6, [%sp + 0x38] %asi; \
+        stwa    %i7, [%sp + 0x3c] %asi; \
+        saved;                          \
+        sub     %g1, 2, %g1;            \
+        ba,pt   %xcc, etrap_save;       \
+         wrpr   %g1, %cwp;              \
+        nop; nop; nop; nop;             \
+        nop; nop; nop; nop;             \
+        ba,a,pt %xcc, etrap_spill_fixup_32bit; \
+        ba,a,pt %xcc, etrap_spill_fixup_32bit; \
+        ba,a,pt %xcc, etrap_spill_fixup_32bit;
+
+#define SPILL_2_GENERIC_ETRAP_FIXUP                     \
+etrap_spill_fixup_32bit:                                \
+        ldub    [%g6 + TI_WSAVED], %g1;                 \
+        sll     %g1, 3, %g3;                            \
+        add     %g6, %g3, %g3;                          \
+        stx     %sp, [%g3 + TI_RWIN_SPTRS];             \
+        sll     %g1, 7, %g3;                            \
+        add     %g6, %g3, %g3;                          \
+        stw     %l0, [%g3 + TI_REG_WINDOW + 0x00];      \
+        stw     %l1, [%g3 + TI_REG_WINDOW + 0x04];      \
+        stw     %l2, [%g3 + TI_REG_WINDOW + 0x08];      \
+        stw     %l3, [%g3 + TI_REG_WINDOW + 0x0c];      \
+        stw     %l4, [%g3 + TI_REG_WINDOW + 0x10];      \
+        stw     %l5, [%g3 + TI_REG_WINDOW + 0x14];      \
+        stw     %l6, [%g3 + TI_REG_WINDOW + 0x18];      \
+        stw     %l7, [%g3 + TI_REG_WINDOW + 0x1c];      \
+        stw     %i0, [%g3 + TI_REG_WINDOW + 0x20];      \
+        stw     %i1, [%g3 + TI_REG_WINDOW + 0x24];      \
+        stw     %i2, [%g3 + TI_REG_WINDOW + 0x28];      \
+        stw     %i3, [%g3 + TI_REG_WINDOW + 0x2c];      \
+        stw     %i4, [%g3 + TI_REG_WINDOW + 0x30];      \
+        stw     %i5, [%g3 + TI_REG_WINDOW + 0x34];      \
+        stw     %i6, [%g3 + TI_REG_WINDOW + 0x38];      \
+        stw     %i7, [%g3 + TI_REG_WINDOW + 0x3c];      \
+        add     %g1, 1, %g1;                            \
+        stb     %g1, [%g6 + TI_WSAVED];                 \
+        saved;                                          \
+        rdpr    %cwp, %g1;                              \
+        sub     %g1, 2, %g1;                            \
+        ba,pt   %xcc, etrap_save;                       \
+         wrpr   %g1, %cwp;                              \
+        nop; nop; nop
+
+#define SPILL_1_NORMAL SPILL_1_GENERIC(ASI_AIUP)
+#define SPILL_2_NORMAL SPILL_2_GENERIC(ASI_AIUP)
+#define SPILL_3_NORMAL SPILL_0_NORMAL
+#define SPILL_4_NORMAL SPILL_0_NORMAL
+#define SPILL_5_NORMAL SPILL_0_NORMAL
+#define SPILL_6_NORMAL SPILL_0_NORMAL
+#define SPILL_7_NORMAL SPILL_0_NORMAL
+
+#define SPILL_0_OTHER SPILL_0_NORMAL
+#define SPILL_1_OTHER SPILL_1_GENERIC(ASI_AIUS)
+#define SPILL_2_OTHER SPILL_2_GENERIC(ASI_AIUS)
+#define SPILL_3_OTHER SPILL_3_NORMAL
+#define SPILL_4_OTHER SPILL_4_NORMAL
+#define SPILL_5_OTHER SPILL_5_NORMAL
+#define SPILL_6_OTHER SPILL_6_NORMAL
+#define SPILL_7_OTHER SPILL_7_NORMAL
+
+/* Normal kernel fill */
+#define FILL_0_NORMAL                                   \
+        ldx     [%sp + STACK_BIAS + 0x00], %l0;         \
+        ldx     [%sp + STACK_BIAS + 0x08], %l1;         \
+        ldx     [%sp + STACK_BIAS + 0x10], %l2;         \
+        ldx     [%sp + STACK_BIAS + 0x18], %l3;         \
+        ldx     [%sp + STACK_BIAS + 0x20], %l4;         \
+        ldx     [%sp + STACK_BIAS + 0x28], %l5;         \
+        ldx     [%sp + STACK_BIAS + 0x30], %l6;         \
+        ldx     [%sp + STACK_BIAS + 0x38], %l7;         \
+        ldx     [%sp + STACK_BIAS + 0x40], %i0;         \
+        ldx     [%sp + STACK_BIAS + 0x48], %i1;         \
+        ldx     [%sp + STACK_BIAS + 0x50], %i2;         \
+        ldx     [%sp + STACK_BIAS + 0x58], %i3;         \
+        ldx     [%sp + STACK_BIAS + 0x60], %i4;         \
+        ldx     [%sp + STACK_BIAS + 0x68], %i5;         \
+        ldx     [%sp + STACK_BIAS + 0x70], %i6;         \
+        ldx     [%sp + STACK_BIAS + 0x78], %i7;         \
+        restored; retry; nop; nop; nop; nop; nop; nop;  \
+        nop; nop; nop; nop; nop; nop; nop; nop;
+
+#define FILL_0_NORMAL_RTRAP                             \
+kern_rtt_fill:                                          \
+        rdpr    %cwp, %g1;                              \
+        sub     %g1, 1, %g1;                            \
+        wrpr    %g1, %cwp;                              \
+        ldx     [%sp + STACK_BIAS + 0x00], %l0;         \
+        ldx     [%sp + STACK_BIAS + 0x08], %l1;         \
+        ldx     [%sp + STACK_BIAS + 0x10], %l2;         \
+        ldx     [%sp + STACK_BIAS + 0x18], %l3;         \
+        ldx     [%sp + STACK_BIAS + 0x20], %l4;         \
+        ldx     [%sp + STACK_BIAS + 0x28], %l5;         \
+        ldx     [%sp + STACK_BIAS + 0x30], %l6;         \
+        ldx     [%sp + STACK_BIAS + 0x38], %l7;         \
+        ldx     [%sp + STACK_BIAS + 0x40], %i0;         \
+        ldx     [%sp + STACK_BIAS + 0x48], %i1;         \
+        ldx     [%sp + STACK_BIAS + 0x50], %i2;         \
+        ldx     [%sp + STACK_BIAS + 0x58], %i3;         \
+        ldx     [%sp + STACK_BIAS + 0x60], %i4;         \
+        ldx     [%sp + STACK_BIAS + 0x68], %i5;         \
+        ldx     [%sp + STACK_BIAS + 0x70], %i6;         \
+        ldx     [%sp + STACK_BIAS + 0x78], %i7;         \
+        restored;                                       \
+        add     %g1, 1, %g1;                            \
+        ba,pt   %xcc, kern_rtt_restore;                 \
+         wrpr   %g1, %cwp;                              \
+        nop; nop; nop; nop; nop;                        \
+        nop; nop; nop; nop;
+
+
+/* Normal 64bit fill */
+#define FILL_1_GENERIC(ASI)                             \
+        add     %sp, STACK_BIAS + 0x00, %g1;            \
+        ldxa    [%g1 + %g0] ASI, %l0;                   \
+        mov     0x08, %g2;                              \
+        mov     0x10, %g3;                              \
+        ldxa    [%g1 + %g2] ASI, %l1;                   \
+        mov     0x18, %g5;                              \
+        ldxa    [%g1 + %g3] ASI, %l2;                   \
+        ldxa    [%g1 + %g5] ASI, %l3;                   \
+        add     %g1, 0x20, %g1;                         \
+        ldxa    [%g1 + %g0] ASI, %l4;                   \
+        ldxa    [%g1 + %g2] ASI, %l5;                   \
+        ldxa    [%g1 + %g3] ASI, %l6;                   \
+        ldxa    [%g1 + %g5] ASI, %l7;                   \
+        add     %g1, 0x20, %g1;                         \
+        ldxa    [%g1 + %g0] ASI, %i0;                   \
+        ldxa    [%g1 + %g2] ASI, %i1;                   \
+        ldxa    [%g1 + %g3] ASI, %i2;                   \
+        ldxa    [%g1 + %g5] ASI, %i3;                   \
+        add     %g1, 0x20, %g1;                         \
+        ldxa    [%g1 + %g0] ASI, %i4;                   \
+        ldxa    [%g1 + %g2] ASI, %i5;                   \
+        ldxa    [%g1 + %g3] ASI, %i6;                   \
+        ldxa    [%g1 + %g5] ASI, %i7;                   \
+        restored;                                       \
+        retry; nop; nop; nop; nop;                      \
+        b,a,pt  %xcc, fill_fixup_dax;                   \
+        b,a,pt  %xcc, fill_fixup_mna;                   \
+        b,a,pt  %xcc, fill_fixup;
+
+#define FILL_1_GENERIC_RTRAP                            \
+user_rtt_fill_64bit:                                    \
+        ldxa    [%sp + STACK_BIAS + 0x00] %asi, %l0;    \
+        ldxa    [%sp + STACK_BIAS + 0x08] %asi, %l1;    \
+        ldxa    [%sp + STACK_BIAS + 0x10] %asi, %l2;    \
+        ldxa    [%sp + STACK_BIAS + 0x18] %asi, %l3;    \
+        ldxa    [%sp + STACK_BIAS + 0x20] %asi, %l4;    \
+        ldxa    [%sp + STACK_BIAS + 0x28] %asi, %l5;    \
+        ldxa    [%sp + STACK_BIAS + 0x30] %asi, %l6;    \
+        ldxa    [%sp + STACK_BIAS + 0x38] %asi, %l7;    \
+        ldxa    [%sp + STACK_BIAS + 0x40] %asi, %i0;    \
+        ldxa    [%sp + STACK_BIAS + 0x48] %asi, %i1;    \
+        ldxa    [%sp + STACK_BIAS + 0x50] %asi, %i2;    \
+        ldxa    [%sp + STACK_BIAS + 0x58] %asi, %i3;    \
+        ldxa    [%sp + STACK_BIAS + 0x60] %asi, %i4;    \
+        ldxa    [%sp + STACK_BIAS + 0x68] %asi, %i5;    \
+        ldxa    [%sp + STACK_BIAS + 0x70] %asi, %i6;    \
+        ldxa    [%sp + STACK_BIAS + 0x78] %asi, %i7;    \
+        ba,pt   %xcc, user_rtt_pre_restore;             \
+         restored;                                      \
+        nop; nop; nop; nop; nop; nop;                   \
+        nop; nop; nop; nop; nop;                        \
+        ba,a,pt %xcc, user_rtt_fill_fixup;              \
+        ba,a,pt %xcc, user_rtt_fill_fixup;              \
+        ba,a,pt %xcc, user_rtt_fill_fixup;
+
+
+/* Normal 32bit fill */
+#define FILL_2_GENERIC(ASI)                             \
+        srl     %sp, 0, %sp;                            \
+        lduwa   [%sp + %g0] ASI, %l0;                   \
+        mov     0x04, %g2;                              \
+        mov     0x08, %g3;                              \
+        lduwa   [%sp + %g2] ASI, %l1;                   \
+        mov     0x0c, %g5;                              \
+        lduwa   [%sp + %g3] ASI, %l2;                   \
+        lduwa   [%sp + %g5] ASI, %l3;                   \
+        add     %sp, 0x10, %g1;                         \
+        lduwa   [%g1 + %g0] ASI, %l4;                   \
+        lduwa   [%g1 + %g2] ASI, %l5;                   \
+        lduwa   [%g1 + %g3] ASI, %l6;                   \
+        lduwa   [%g1 + %g5] ASI, %l7;                   \
+        add     %g1, 0x10, %g1;                         \
+        lduwa   [%g1 + %g0] ASI, %i0;                   \
+        lduwa   [%g1 + %g2] ASI, %i1;                   \
+        lduwa   [%g1 + %g3] ASI, %i2;                   \
+        lduwa   [%g1 + %g5] ASI, %i3;                   \
+        add     %g1, 0x10, %g1;                         \
+        lduwa   [%g1 + %g0] ASI, %i4;                   \
+        lduwa   [%g1 + %g2] ASI, %i5;                   \
+        lduwa   [%g1 + %g3] ASI, %i6;                   \
+        lduwa   [%g1 + %g5] ASI, %i7;                   \
+        restored;                                       \
+        retry; nop; nop; nop; nop;                      \
+        b,a,pt  %xcc, fill_fixup_dax;                   \
+        b,a,pt  %xcc, fill_fixup_mna;                   \
+        b,a,pt  %xcc, fill_fixup;
+
+#define FILL_2_GENERIC_RTRAP                            \
+user_rtt_fill_32bit:                                    \
+        srl     %sp, 0, %sp;                            \
+        lduwa   [%sp + 0x00] %asi, %l0;                 \
+        lduwa   [%sp + 0x04] %asi, %l1;                 \
+        lduwa   [%sp + 0x08] %asi, %l2;                 \
+        lduwa   [%sp + 0x0c] %asi, %l3;                 \
+        lduwa   [%sp + 0x10] %asi, %l4;                 \
+        lduwa   [%sp + 0x14] %asi, %l5;                 \
+        lduwa   [%sp + 0x18] %asi, %l6;                 \
+        lduwa   [%sp + 0x1c] %asi, %l7;                 \
+        lduwa   [%sp + 0x20] %asi, %i0;                 \
+        lduwa   [%sp + 0x24] %asi, %i1;                 \
+        lduwa   [%sp + 0x28] %asi, %i2;                 \
+        lduwa   [%sp + 0x2c] %asi, %i3;                 \
+        lduwa   [%sp + 0x30] %asi, %i4;                 \
+        lduwa   [%sp + 0x34] %asi, %i5;                 \
+        lduwa   [%sp + 0x38] %asi, %i6;                 \
+        lduwa   [%sp + 0x3c] %asi, %i7;                 \
+        ba,pt   %xcc, user_rtt_pre_restore;             \
+         restored;                                      \
+        nop; nop; nop; nop; nop;                        \
+        nop; nop; nop; nop; nop;                        \
+        ba,a,pt %xcc, user_rtt_fill_fixup;              \
+        ba,a,pt %xcc, user_rtt_fill_fixup;              \
+        ba,a,pt %xcc, user_rtt_fill_fixup;
+
+
+#define FILL_1_NORMAL FILL_1_GENERIC(ASI_AIUP)
+#define FILL_2_NORMAL FILL_2_GENERIC(ASI_AIUP)
+#define FILL_3_NORMAL FILL_0_NORMAL
+#define FILL_4_NORMAL FILL_0_NORMAL
+#define FILL_5_NORMAL FILL_0_NORMAL
+#define FILL_6_NORMAL FILL_0_NORMAL
+#define FILL_7_NORMAL FILL_0_NORMAL
+
+#define FILL_0_OTHER FILL_0_NORMAL
+#define FILL_1_OTHER FILL_1_GENERIC(ASI_AIUS)
+#define FILL_2_OTHER FILL_2_GENERIC(ASI_AIUS)
+#define FILL_3_OTHER FILL_3_NORMAL
+#define FILL_4_OTHER FILL_4_NORMAL
+#define FILL_5_OTHER FILL_5_NORMAL
+#define FILL_6_OTHER FILL_6_NORMAL
+#define FILL_7_OTHER FILL_7_NORMAL
+
+#endif /* !(_SPARC64_TTABLE_H) */
diff --git a/arch/sparc/include/asm/turbosparc.h b/arch/sparc/include/asm/turbosparc.h
new file mode 100644
index 000000000000..17c73282db0a
--- /dev/null
+++ b/arch/sparc/include/asm/turbosparc.h
@@ -0,0 +1,125 @@
+/*
+ * turbosparc.h:  Defines specific to the TurboSparc module.
+ *            This is SRMMU stuff.
+ *
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _SPARC_TURBOSPARC_H
+#define _SPARC_TURBOSPARC_H
+
+#include <asm/asi.h>
+#include <asm/pgtsrmmu.h>
+
+/* Bits in the SRMMU control register for TurboSparc modules.
+ *
+ * -------------------------------------------------------------------
+ * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
+ * -------------------------------------------------------------------
+ *  31    24 23-21 20-19 18 17 16-15 14 13-10  9  8  7  6-3   2  1  0
+ *
+ * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
+ *
+ * This indicates whether the TurboSparc is in boot-mode or not.
+ *
+ * IC: Instruction Cache -- 0 = off, 1 = on
+ * DC: Data Cache -- 0 = off, 1 = 0n
+ *
+ * These bits enable the on-cpu TurboSparc split I/D caches.
+ *
+ * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
+ * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
+ * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
+ *
+ */
+
+#define TURBOSPARC_MMUENABLE    0x00000001
+#define TURBOSPARC_NOFAULT      0x00000002
+#define TURBOSPARC_ICSNOOP      0x00000004
+#define TURBOSPARC_PSO          0x00000080
+#define TURBOSPARC_DCENABLE     0x00000100   /* Enable data cache */
+#define TURBOSPARC_ICENABLE     0x00000200   /* Enable instruction cache */
+#define TURBOSPARC_BMODE        0x00004000   
+#define TURBOSPARC_PARITYODD    0x00020000   /* Parity odd, if enabled */
+#define TURBOSPARC_PCENABLE     0x00040000   /* Enable parity checking */
+
+/* Bits in the CPU configuration register for TurboSparc modules.
+ *
+ * -------------------------------------------------------
+ * |IOClk|SNP|AXClk| RAH |  WS |  RSV  |SBC|WT|uS2|SE|SCC|
+ * -------------------------------------------------------
+ *    31   30 29-28 27-26 25-23   22-8  7-6  5  4   3 2-0
+ *
+ */
+
+#define TURBOSPARC_SCENABLE 0x00000008   /* Secondary cache enable */
+#define TURBOSPARC_uS2      0x00000010   /* Swift compatibility mode */
+#define TURBOSPARC_WTENABLE 0x00000020   /* Write thru for dcache */
+#define TURBOSPARC_SNENABLE 0x40000000   /* DVMA snoop enable */
+
+#ifndef __ASSEMBLY__
+
+/* Bits [13:5] select one of 512 instruction cache tags */
+static inline void turbosparc_inv_insn_tag(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (addr), "i" (ASI_M_TXTC_TAG)
+                             : "memory");
+}
+
+/* Bits [13:5] select one of 512 data cache tags */
+static inline void turbosparc_inv_data_tag(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (addr), "i" (ASI_M_DATAC_TAG)
+                             : "memory");
+}
+
+static inline void turbosparc_flush_icache(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < 0x4000; addr += 0x20)
+                turbosparc_inv_insn_tag(addr);
+}
+
+static inline void turbosparc_flush_dcache(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < 0x4000; addr += 0x20)
+                turbosparc_inv_data_tag(addr);
+}
+
+static inline void turbosparc_idflash_clear(void)
+{
+        unsigned long addr;
+
+        for (addr = 0; addr < 0x4000; addr += 0x20) {
+                turbosparc_inv_insn_tag(addr);
+                turbosparc_inv_data_tag(addr);
+        }
+}
+
+static inline void turbosparc_set_ccreg(unsigned long regval)
+{
+        __asm__ __volatile__("sta %0, [%1] %2\n\t"
+                             : /* no outputs */
+                             : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
+                             : "memory");
+}
+
+static inline unsigned long turbosparc_get_ccreg(void)
+{
+        unsigned long regval;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t"
+                             : "=r" (regval)
+                             : "r" (0x600), "i" (ASI_M_MMUREGS));
+        return regval;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_TURBOSPARC_H) */
diff --git a/arch/sparc/include/asm/types.h b/arch/sparc/include/asm/types.h
new file mode 100644
index 000000000000..8c28fde5eaa2
--- /dev/null
+++ b/arch/sparc/include/asm/types.h
@@ -0,0 +1,62 @@
+#ifndef _SPARC_TYPES_H
+#define _SPARC_TYPES_H
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+
+/*** SPARC 64 bit ***/
+#include <asm-generic/int-l64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 64
+
+#ifndef __ASSEMBLY__
+
+/* Dma addresses come in generic and 64-bit flavours.  */
+
+typedef u32 dma_addr_t;
+typedef u64 dma64_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#else
+
+/*** SPARC 32 bit ***/
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef u32 dma_addr_t;
+typedef u32 dma64_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* defined(__sparc__) && defined(__arch64__) */
+
+#endif /* defined(_SPARC_TYPES_H) */
diff --git a/arch/sparc/include/asm/uaccess.h b/arch/sparc/include/asm/uaccess.h
new file mode 100644
index 000000000000..e88fbe5c0457
--- /dev/null
+++ b/arch/sparc/include/asm/uaccess.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_UACCESS_H
+#define ___ASM_SPARC_UACCESS_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/uaccess_64.h>
+#else
+#include <asm/uaccess_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h
new file mode 100644
index 000000000000..47d5619d43fa
--- /dev/null
+++ b/arch/sparc/include/asm/uaccess_32.h
@@ -0,0 +1,336 @@
+/*
+ * uaccess.h: User space memore access functions.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+#ifdef __KERNEL__
+#include <linux/compiler.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <asm/vac-ops.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+/* Sparc is not segmented, however we need to be able to fool access_ok()
+ * when doing system calls from kernel mode legitimately.
+ *
+ * "For historical reasons, these macros are grossly misnamed." -Linus
+ */
+
+#define KERNEL_DS   ((mm_segment_t) { 0 })
+#define USER_DS     ((mm_segment_t) { -1 })
+
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current->thread.current_ds)
+#define set_fs(val)     ((current->thread.current_ds) = (val))
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+/* We have there a nice not-mapped page at PAGE_OFFSET - PAGE_SIZE, so that this test
+ * can be fairly lightweight.
+ * No one can read/write anything from userland in the kernel space by setting
+ * large size and address near to PAGE_OFFSET - a fault will break his intentions.
+ */
+#define __user_ok(addr, size) ({ (void)(size); (addr) < STACK_TOP; })
+#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
+#define __access_ok(addr,size) (__user_ok((addr) & get_fs().seg,(size)))
+#define access_ok(type, addr, size)                                     \
+        ({ (void)(type); __access_ok((unsigned long)(addr), size); })
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ *
+ * There is a special way how to put a range of potentially faulting
+ * insns (like twenty ldd/std's with now intervening other instructions)
+ * You specify address of first in insn and 0 in fixup and in the next
+ * exception_table_entry you specify last potentially faulting insn + 1
+ * and in fixup the routine which should handle the fault.
+ * That fixup code will get
+ * (faulting_insn_address - first_insn_in_the_range_address)/4
+ * in %g2 (ie. index of the faulting instruction in the range).
+ */
+
+struct exception_table_entry
+{
+        unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_extables_range(unsigned long addr, unsigned long *g2);
+
+extern void __ret_efault(void);
+
+/* Uh, these should become the main single-value transfer routines..
+ * They automatically use the right size if we just have the right
+ * pointer type..
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ */
+#define put_user(x,ptr) ({ \
+unsigned long __pu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__put_user_check((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
+
+#define get_user(x,ptr) ({ \
+unsigned long __gu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__get_user_check((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
+
+/*
+ * The "__xxx" versions do not do address space checking, useful when
+ * doing multiple accesses to the same area (the user has to do the
+ * checks by hand with "access_ok()")
+ */
+#define __put_user(x,ptr) __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
+#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr)),__typeof__(*(ptr)))
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) ((struct __large_struct __user *)(x))
+
+#define __put_user_check(x,addr,size) ({ \
+register int __pu_ret; \
+if (__access_ok(addr,size)) { \
+switch (size) { \
+case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
+case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
+case 4: __put_user_asm(x,,addr,__pu_ret); break; \
+case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
+default: __pu_ret = __put_user_bad(); break; \
+} } else { __pu_ret = -EFAULT; } __pu_ret; })
+
+#define __put_user_nocheck(x,addr,size) ({ \
+register int __pu_ret; \
+switch (size) { \
+case 1: __put_user_asm(x,b,addr,__pu_ret); break; \
+case 2: __put_user_asm(x,h,addr,__pu_ret); break; \
+case 4: __put_user_asm(x,,addr,__pu_ret); break; \
+case 8: __put_user_asm(x,d,addr,__pu_ret); break; \
+default: __pu_ret = __put_user_bad(); break; \
+} __pu_ret; })
+
+#define __put_user_asm(x,size,addr,ret)                                 \
+__asm__ __volatile__(                                                   \
+        "/* Put user asm, inline. */\n"                                 \
+"1:\t"  "st"#size " %1, %2\n\t"                                         \
+        "clr    %0\n"                                                   \
+"2:\n\n\t"                                                              \
+        ".section .fixup,#alloc,#execinstr\n\t"                         \
+        ".align 4\n"                                                    \
+"3:\n\t"                                                                \
+        "b      2b\n\t"                                                 \
+        " mov   %3, %0\n\t"                                             \
+        ".previous\n\n\t"                                               \
+        ".section __ex_table,#alloc\n\t"                                \
+        ".align 4\n\t"                                                  \
+        ".word  1b, 3b\n\t"                                             \
+        ".previous\n\n\t"                                               \
+       : "=&r" (ret) : "r" (x), "m" (*__m(addr)),                       \
+         "i" (-EFAULT))
+
+extern int __put_user_bad(void);
+
+#define __get_user_check(x,addr,size,type) ({ \
+register int __gu_ret; \
+register unsigned long __gu_val; \
+if (__access_ok(addr,size)) { \
+switch (size) { \
+case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
+case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
+case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
+case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
+default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
+} } else { __gu_val = 0; __gu_ret = -EFAULT; } x = (type) __gu_val; __gu_ret; })
+
+#define __get_user_check_ret(x,addr,size,type,retval) ({ \
+register unsigned long __gu_val __asm__ ("l1"); \
+if (__access_ok(addr,size)) { \
+switch (size) { \
+case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
+case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
+case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
+case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
+default: if (__get_user_bad()) return retval; \
+} x = (type) __gu_val; } else return retval; })
+
+#define __get_user_nocheck(x,addr,size,type) ({ \
+register int __gu_ret; \
+register unsigned long __gu_val; \
+switch (size) { \
+case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
+case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
+case 4: __get_user_asm(__gu_val,,addr,__gu_ret); break; \
+case 8: __get_user_asm(__gu_val,d,addr,__gu_ret); break; \
+default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
+} x = (type) __gu_val; __gu_ret; })
+
+#define __get_user_nocheck_ret(x,addr,size,type,retval) ({ \
+register unsigned long __gu_val __asm__ ("l1"); \
+switch (size) { \
+case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
+case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
+case 4: __get_user_asm_ret(__gu_val,,addr,retval); break; \
+case 8: __get_user_asm_ret(__gu_val,d,addr,retval); break; \
+default: if (__get_user_bad()) return retval; \
+} x = (type) __gu_val; })
+
+#define __get_user_asm(x,size,addr,ret)                                 \
+__asm__ __volatile__(                                                   \
+        "/* Get user asm, inline. */\n"                                 \
+"1:\t"  "ld"#size " %2, %1\n\t"                                         \
+        "clr    %0\n"                                                   \
+"2:\n\n\t"                                                              \
+        ".section .fixup,#alloc,#execinstr\n\t"                         \
+        ".align 4\n"                                                    \
+"3:\n\t"                                                                \
+        "clr    %1\n\t"                                                 \
+        "b      2b\n\t"                                                 \
+        " mov   %3, %0\n\n\t"                                           \
+        ".previous\n\t"                                                 \
+        ".section __ex_table,#alloc\n\t"                                \
+        ".align 4\n\t"                                                  \
+        ".word  1b, 3b\n\n\t"                                           \
+        ".previous\n\t"                                                 \
+       : "=&r" (ret), "=&r" (x) : "m" (*__m(addr)),                     \
+         "i" (-EFAULT))
+
+#define __get_user_asm_ret(x,size,addr,retval)                          \
+if (__builtin_constant_p(retval) && retval == -EFAULT)                  \
+__asm__ __volatile__(                                                   \
+        "/* Get user asm ret, inline. */\n"                             \
+"1:\t"  "ld"#size " %1, %0\n\n\t"                                       \
+        ".section __ex_table,#alloc\n\t"                                \
+        ".align 4\n\t"                                                  \
+        ".word  1b,__ret_efault\n\n\t"                                  \
+        ".previous\n\t"                                                 \
+       : "=&r" (x) : "m" (*__m(addr)));                                 \
+else                                                                    \
+__asm__ __volatile__(                                                   \
+        "/* Get user asm ret, inline. */\n"                             \
+"1:\t"  "ld"#size " %1, %0\n\n\t"                                       \
+        ".section .fixup,#alloc,#execinstr\n\t"                         \
+        ".align 4\n"                                                    \
+"3:\n\t"                                                                \
+        "ret\n\t"                                                       \
+        " restore %%g0, %2, %%o0\n\n\t"                                 \
+        ".previous\n\t"                                                 \
+        ".section __ex_table,#alloc\n\t"                                \
+        ".align 4\n\t"                                                  \
+        ".word  1b, 3b\n\n\t"                                           \
+        ".previous\n\t"                                                 \
+       : "=&r" (x) : "m" (*__m(addr)), "i" (retval))
+
+extern int __get_user_bad(void);
+
+extern unsigned long __copy_user(void __user *to, const void __user *from, unsigned long size);
+
+static inline unsigned long copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        if (n && __access_ok((unsigned long) to, n))
+                return __copy_user(to, (__force void __user *) from, n);
+        else
+                return n;
+}
+
+static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        return __copy_user(to, (__force void __user *) from, n);
+}
+
+static inline unsigned long copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        if (n && __access_ok((unsigned long) from, n))
+                return __copy_user((__force void __user *) to, from, n);
+        else
+                return n;
+}
+
+static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        return __copy_user((__force void __user *) to, from, n);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+static inline unsigned long __clear_user(void __user *addr, unsigned long size)
+{
+        unsigned long ret;
+
+        __asm__ __volatile__ (
+                ".section __ex_table,#alloc\n\t"
+                ".align 4\n\t"
+                ".word 1f,3\n\t"
+                ".previous\n\t"
+                "mov %2, %%o1\n"
+                "1:\n\t"
+                "call __bzero\n\t"
+                " mov %1, %%o0\n\t"
+                "mov %%o0, %0\n"
+                : "=r" (ret) : "r" (addr), "r" (size) :
+                "o0", "o1", "o2", "o3", "o4", "o5", "o7",
+                "g1", "g2", "g3", "g4", "g5", "g7", "cc");
+
+        return ret;
+}
+
+static inline unsigned long clear_user(void __user *addr, unsigned long n)
+{
+        if (n && __access_ok((unsigned long) addr, n))
+                return __clear_user(addr, n);
+        else
+                return n;
+}
+
+extern long __strncpy_from_user(char *dest, const char __user *src, long count);
+
+static inline long strncpy_from_user(char *dest, const char __user *src, long count)
+{
+        if (__access_ok((unsigned long) src, count))
+                return __strncpy_from_user(dest, src, count);
+        else
+                return -EFAULT;
+}
+
+extern long __strlen_user(const char __user *);
+extern long __strnlen_user(const char __user *, long len);
+
+static inline long strlen_user(const char __user *str)
+{
+        if (!access_ok(VERIFY_READ, str, 0))
+                return 0;
+        else
+                return __strlen_user(str);
+}
+
+static inline long strnlen_user(const char __user *str, long len)
+{
+        if (!access_ok(VERIFY_READ, str, 0))
+                return 0;
+        else
+                return __strnlen_user(str, len);
+}
+
+#endif  /* __ASSEMBLY__ */
+
+#endif /* _ASM_UACCESS_H */
diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h
new file mode 100644
index 000000000000..296ef30e05c8
--- /dev/null
+++ b/arch/sparc/include/asm/uaccess_64.h
@@ -0,0 +1,273 @@
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+
+#ifdef __KERNEL__
+#include <linux/compiler.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <asm/asi.h>
+#include <asm/system.h>
+#include <asm/spitfire.h>
+#include <asm-generic/uaccess.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Sparc64 is segmented, though more like the M68K than the I386.
+ * We use the secondary ASI to address user memory, which references a
+ * completely different VM map, thus there is zero chance of the user
+ * doing something queer and tricking us into poking kernel memory.
+ *
+ * What is left here is basically what is needed for the other parts of
+ * the kernel that expect to be able to manipulate, erum, "segments".
+ * Or perhaps more properly, permissions.
+ *
+ * "For historical reasons, these macros are grossly misnamed." -Linus
+ */
+
+#define KERNEL_DS   ((mm_segment_t) { ASI_P })
+#define USER_DS     ((mm_segment_t) { ASI_AIUS })       /* har har har */
+
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+
+#define get_fs() ((mm_segment_t) { get_thread_current_ds() })
+#define get_ds() (KERNEL_DS)
+
+#define segment_eq(a,b)  ((a).seg == (b).seg)
+
+#define set_fs(val)                                                             \
+do {                                                                            \
+        set_thread_current_ds((val).seg);                                       \
+        __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" ((val).seg));        \
+} while(0)
+
+static inline int __access_ok(const void __user * addr, unsigned long size)
+{
+        return 1;
+}
+
+static inline int access_ok(int type, const void __user * addr, unsigned long size)
+{
+        return 1;
+}
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+        unsigned int insn, fixup;
+};
+
+extern void __ret_efault(void);
+extern void __retl_efault(void);
+
+/* Uh, these should become the main single-value transfer routines..
+ * They automatically use the right size if we just have the right
+ * pointer type..
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ */
+#define put_user(x,ptr) ({ \
+unsigned long __pu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__put_user_nocheck((__typeof__(*(ptr)))(x),__pu_addr,sizeof(*(ptr))); })
+
+#define get_user(x,ptr) ({ \
+unsigned long __gu_addr = (unsigned long)(ptr); \
+__chk_user_ptr(ptr); \
+__get_user_nocheck((x),__gu_addr,sizeof(*(ptr)),__typeof__(*(ptr))); })
+
+#define __put_user(x,ptr) put_user(x,ptr)
+#define __get_user(x,ptr) get_user(x,ptr)
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) ((struct __large_struct *)(x))
+
+#define __put_user_nocheck(data,addr,size) ({ \
+register int __pu_ret; \
+switch (size) { \
+case 1: __put_user_asm(data,b,addr,__pu_ret); break; \
+case 2: __put_user_asm(data,h,addr,__pu_ret); break; \
+case 4: __put_user_asm(data,w,addr,__pu_ret); break; \
+case 8: __put_user_asm(data,x,addr,__pu_ret); break; \
+default: __pu_ret = __put_user_bad(); break; \
+} __pu_ret; })
+
+#define __put_user_asm(x,size,addr,ret)                                 \
+__asm__ __volatile__(                                                   \
+        "/* Put user asm, inline. */\n"                                 \
+"1:\t"  "st"#size "a %1, [%2] %%asi\n\t"                                \
+        "clr    %0\n"                                                   \
+"2:\n\n\t"                                                              \
+        ".section .fixup,#alloc,#execinstr\n\t"                         \
+        ".align 4\n"                                                    \
+"3:\n\t"                                                                \
+        "sethi  %%hi(2b), %0\n\t"                                       \
+        "jmpl   %0 + %%lo(2b), %%g0\n\t"                                \
+        " mov   %3, %0\n\n\t"                                           \
+        ".previous\n\t"                                                 \
+        ".section __ex_table,\"a\"\n\t"                                 \
+        ".align 4\n\t"                                                  \
+        ".word  1b, 3b\n\t"                                             \
+        ".previous\n\n\t"                                               \
+       : "=r" (ret) : "r" (x), "r" (__m(addr)),                         \
+         "i" (-EFAULT))
+
+extern int __put_user_bad(void);
+
+#define __get_user_nocheck(data,addr,size,type) ({ \
+register int __gu_ret; \
+register unsigned long __gu_val; \
+switch (size) { \
+case 1: __get_user_asm(__gu_val,ub,addr,__gu_ret); break; \
+case 2: __get_user_asm(__gu_val,uh,addr,__gu_ret); break; \
+case 4: __get_user_asm(__gu_val,uw,addr,__gu_ret); break; \
+case 8: __get_user_asm(__gu_val,x,addr,__gu_ret); break; \
+default: __gu_val = 0; __gu_ret = __get_user_bad(); break; \
+} data = (type) __gu_val; __gu_ret; })
+
+#define __get_user_nocheck_ret(data,addr,size,type,retval) ({ \
+register unsigned long __gu_val __asm__ ("l1"); \
+switch (size) { \
+case 1: __get_user_asm_ret(__gu_val,ub,addr,retval); break; \
+case 2: __get_user_asm_ret(__gu_val,uh,addr,retval); break; \
+case 4: __get_user_asm_ret(__gu_val,uw,addr,retval); break; \
+case 8: __get_user_asm_ret(__gu_val,x,addr,retval); break; \
+default: if (__get_user_bad()) return retval; \
+} data = (type) __gu_val; })
+
+#define __get_user_asm(x,size,addr,ret)                                 \
+__asm__ __volatile__(                                                   \
+        "/* Get user asm, inline. */\n"                                 \
+"1:\t"  "ld"#size "a [%2] %%asi, %1\n\t"                                \
+        "clr    %0\n"                                                   \
+"2:\n\n\t"                                                              \
+        ".section .fixup,#alloc,#execinstr\n\t"                         \
+        ".align 4\n"                                                    \
+"3:\n\t"                                                                \
+        "sethi  %%hi(2b), %0\n\t"                                       \
+        "clr    %1\n\t"                                                 \
+        "jmpl   %0 + %%lo(2b), %%g0\n\t"                                \
+        " mov   %3, %0\n\n\t"                                           \
+        ".previous\n\t"                                                 \
+        ".section __ex_table,\"a\"\n\t"                                 \
+        ".align 4\n\t"                                                  \
+        ".word  1b, 3b\n\n\t"                                           \
+        ".previous\n\t"                                                 \
+       : "=r" (ret), "=r" (x) : "r" (__m(addr)),                        \
+         "i" (-EFAULT))
+
+#define __get_user_asm_ret(x,size,addr,retval)                          \
+if (__builtin_constant_p(retval) && retval == -EFAULT)                  \
+__asm__ __volatile__(                                                   \
+        "/* Get user asm ret, inline. */\n"                             \
+"1:\t"  "ld"#size "a [%1] %%asi, %0\n\n\t"                              \
+        ".section __ex_table,\"a\"\n\t"                                 \
+        ".align 4\n\t"                                                  \
+        ".word  1b,__ret_efault\n\n\t"                                  \
+        ".previous\n\t"                                                 \
+       : "=r" (x) : "r" (__m(addr)));                                   \
+else                                                                    \
+__asm__ __volatile__(                                                   \
+        "/* Get user asm ret, inline. */\n"                             \
+"1:\t"  "ld"#size "a [%1] %%asi, %0\n\n\t"                              \
+        ".section .fixup,#alloc,#execinstr\n\t"                         \
+        ".align 4\n"                                                    \
+"3:\n\t"                                                                \
+        "ret\n\t"                                                       \
+        " restore %%g0, %2, %%o0\n\n\t"                                 \
+        ".previous\n\t"                                                 \
+        ".section __ex_table,\"a\"\n\t"                                 \
+        ".align 4\n\t"                                                  \
+        ".word  1b, 3b\n\n\t"                                           \
+        ".previous\n\t"                                                 \
+       : "=r" (x) : "r" (__m(addr)), "i" (retval))
+
+extern int __get_user_bad(void);
+
+extern unsigned long __must_check ___copy_from_user(void *to,
+                                                    const void __user *from,
+                                                    unsigned long size);
+extern unsigned long copy_from_user_fixup(void *to, const void __user *from,
+                                          unsigned long size);
+static inline unsigned long __must_check
+copy_from_user(void *to, const void __user *from, unsigned long size)
+{
+        unsigned long ret = ___copy_from_user(to, from, size);
+
+        if (unlikely(ret))
+                ret = copy_from_user_fixup(to, from, size);
+        return ret;
+}
+#define __copy_from_user copy_from_user
+
+extern unsigned long __must_check ___copy_to_user(void __user *to,
+                                                  const void *from,
+                                                  unsigned long size);
+extern unsigned long copy_to_user_fixup(void __user *to, const void *from,
+                                        unsigned long size);
+static inline unsigned long __must_check
+copy_to_user(void __user *to, const void *from, unsigned long size)
+{
+        unsigned long ret = ___copy_to_user(to, from, size);
+
+        if (unlikely(ret))
+                ret = copy_to_user_fixup(to, from, size);
+        return ret;
+}
+#define __copy_to_user copy_to_user
+
+extern unsigned long __must_check ___copy_in_user(void __user *to,
+                                                  const void __user *from,
+                                                  unsigned long size);
+extern unsigned long copy_in_user_fixup(void __user *to, void __user *from,
+                                        unsigned long size);
+static inline unsigned long __must_check
+copy_in_user(void __user *to, void __user *from, unsigned long size)
+{
+        unsigned long ret = ___copy_in_user(to, from, size);
+
+        if (unlikely(ret))
+                ret = copy_in_user_fixup(to, from, size);
+        return ret;
+}
+#define __copy_in_user copy_in_user
+
+extern unsigned long __must_check __clear_user(void __user *, unsigned long);
+
+#define clear_user __clear_user
+
+extern long __must_check __strncpy_from_user(char *dest, const char __user *src, long count);
+
+#define strncpy_from_user __strncpy_from_user
+
+extern long __strlen_user(const char __user *);
+extern long __strnlen_user(const char __user *, long len);
+
+#define strlen_user __strlen_user
+#define strnlen_user __strnlen_user
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+#endif  /* __ASSEMBLY__ */
+
+#endif /* _ASM_UACCESS_H */
diff --git a/arch/sparc/include/asm/uctx.h b/arch/sparc/include/asm/uctx.h
new file mode 100644
index 000000000000..dc937c75ffdd
--- /dev/null
+++ b/arch/sparc/include/asm/uctx.h
@@ -0,0 +1,71 @@
+/*
+ * uctx.h: Sparc64 {set,get}context() register state layouts.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC64_UCTX_H
+#define __SPARC64_UCTX_H
+
+#define MC_TSTATE       0
+#define MC_PC           1
+#define MC_NPC          2
+#define MC_Y            3
+#define MC_G1           4
+#define MC_G2           5
+#define MC_G3           6
+#define MC_G4           7
+#define MC_G5           8
+#define MC_G6           9
+#define MC_G7           10
+#define MC_O0           11
+#define MC_O1           12
+#define MC_O2           13
+#define MC_O3           14
+#define MC_O4           15
+#define MC_O5           16
+#define MC_O6           17
+#define MC_O7           18
+#define MC_NGREG        19
+
+typedef unsigned long mc_greg_t;
+typedef mc_greg_t mc_gregset_t[MC_NGREG];
+
+#define MC_MAXFPQ       16
+struct mc_fq {
+        unsigned long   *mcfq_addr;
+        unsigned int    mcfq_insn;
+};
+
+struct mc_fpu {
+        union {
+                unsigned int    sregs[32];
+                unsigned long   dregs[32];
+                long double     qregs[16];
+        } mcfpu_fregs;
+        unsigned long   mcfpu_fsr;
+        unsigned long   mcfpu_fprs;
+        unsigned long   mcfpu_gsr;
+        struct mc_fq    *mcfpu_fq;
+        unsigned char   mcfpu_qcnt;
+        unsigned char   mcfpu_qentsz;
+        unsigned char   mcfpu_enab;
+};
+typedef struct mc_fpu mc_fpu_t;
+
+typedef struct {
+        mc_gregset_t    mc_gregs;
+        mc_greg_t       mc_fp;
+        mc_greg_t       mc_i7;
+        mc_fpu_t        mc_fpregs;
+} mcontext_t;
+
+struct ucontext {
+        struct ucontext         *uc_link;
+        unsigned long           uc_flags;
+        sigset_t                uc_sigmask;
+        mcontext_t              uc_mcontext;
+};
+typedef struct ucontext ucontext_t;
+
+#endif /* __SPARC64_UCTX_H */
diff --git a/arch/sparc/include/asm/unaligned.h b/arch/sparc/include/asm/unaligned.h
new file mode 100644
index 000000000000..11d2d5fb5902
--- /dev/null
+++ b/arch/sparc/include/asm/unaligned.h
@@ -0,0 +1,10 @@
+#ifndef _ASM_SPARC_UNALIGNED_H
+#define _ASM_SPARC_UNALIGNED_H
+
+#include <linux/unaligned/be_struct.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/generic.h>
+#define get_unaligned   __get_unaligned_be
+#define put_unaligned   __put_unaligned_be
+
+#endif /* _ASM_SPARC_UNALIGNED_H */
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
new file mode 100644
index 000000000000..4207fb362da0
--- /dev/null
+++ b/arch/sparc/include/asm/unistd.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_UNISTD_H
+#define ___ASM_SPARC_UNISTD_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/unistd_64.h>
+#else
+#include <asm/unistd_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/unistd_32.h b/arch/sparc/include/asm/unistd_32.h
new file mode 100644
index 000000000000..648643a9f139
--- /dev/null
+++ b/arch/sparc/include/asm/unistd_32.h
@@ -0,0 +1,384 @@
+#ifndef _SPARC_UNISTD_H
+#define _SPARC_UNISTD_H
+
+/*
+ * System calls under the Sparc.
+ *
+ * Don't be scared by the ugly clobbers, it is the only way I can
+ * think of right now to force the arguments into fixed registers
+ * before the trap into the system call with gcc 'asm' statements.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ *
+ * SunOS compatibility based upon preliminary work which is:
+ *
+ * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
+ */
+
+#define __NR_restart_syscall      0 /* Linux Specific                              */
+#define __NR_exit                 1 /* Common                                      */
+#define __NR_fork                 2 /* Common                                      */
+#define __NR_read                 3 /* Common                                      */
+#define __NR_write                4 /* Common                                      */
+#define __NR_open                 5 /* Common                                      */
+#define __NR_close                6 /* Common                                      */
+#define __NR_wait4                7 /* Common                                      */
+#define __NR_creat                8 /* Common                                      */
+#define __NR_link                 9 /* Common                                      */
+#define __NR_unlink              10 /* Common                                      */
+#define __NR_execv               11 /* SunOS Specific                              */
+#define __NR_chdir               12 /* Common                                      */
+#define __NR_chown               13 /* Common                                      */
+#define __NR_mknod               14 /* Common                                      */
+#define __NR_chmod               15 /* Common                                      */
+#define __NR_lchown              16 /* Common                                      */
+#define __NR_brk                 17 /* Common                                      */
+#define __NR_perfctr             18 /* Performance counter operations              */
+#define __NR_lseek               19 /* Common                                      */
+#define __NR_getpid              20 /* Common                                      */
+#define __NR_capget              21 /* Linux Specific                              */
+#define __NR_capset              22 /* Linux Specific                              */
+#define __NR_setuid              23 /* Implemented via setreuid in SunOS           */
+#define __NR_getuid              24 /* Common                                      */
+#define __NR_vmsplice            25 /* ENOSYS under SunOS                          */
+#define __NR_ptrace              26 /* Common                                      */
+#define __NR_alarm               27 /* Implemented via setitimer in SunOS          */
+#define __NR_sigaltstack         28 /* Common                                      */
+#define __NR_pause               29 /* Is sigblock(0)->sigpause() in SunOS         */
+#define __NR_utime               30 /* Implemented via utimes() under SunOS        */
+#define __NR_lchown32            31 /* Linux sparc32 specific                      */
+#define __NR_fchown32            32 /* Linux sparc32 specific                      */
+#define __NR_access              33 /* Common                                      */
+#define __NR_nice                34 /* Implemented via get/setpriority() in SunOS  */
+#define __NR_chown32             35 /* Linux sparc32 specific                      */
+#define __NR_sync                36 /* Common                                      */
+#define __NR_kill                37 /* Common                                      */
+#define __NR_stat                38 /* Common                                      */
+#define __NR_sendfile            39 /* Linux Specific                              */
+#define __NR_lstat               40 /* Common                                      */
+#define __NR_dup                 41 /* Common                                      */
+#define __NR_pipe                42 /* Common                                      */
+#define __NR_times               43 /* Implemented via getrusage() in SunOS        */
+#define __NR_getuid32            44 /* Linux sparc32 specific                      */
+#define __NR_umount2             45 /* Linux Specific                              */
+#define __NR_setgid              46 /* Implemented via setregid() in SunOS         */
+#define __NR_getgid              47 /* Common                                      */
+#define __NR_signal              48 /* Implemented via sigvec() in SunOS           */
+#define __NR_geteuid             49 /* SunOS calls getuid()                        */
+#define __NR_getegid             50 /* SunOS calls getgid()                        */
+#define __NR_acct                51 /* Common                                      */
+/* #define __NR_memory_ordering  52    Linux sparc64 specific                      */
+#define __NR_getgid32            53 /* Linux sparc32 specific                      */
+#define __NR_ioctl               54 /* Common                                      */
+#define __NR_reboot              55 /* Common                                      */
+#define __NR_mmap2               56 /* Linux sparc32 Specific                      */
+#define __NR_symlink             57 /* Common                                      */
+#define __NR_readlink            58 /* Common                                      */
+#define __NR_execve              59 /* Common                                      */
+#define __NR_umask               60 /* Common                                      */
+#define __NR_chroot              61 /* Common                                      */
+#define __NR_fstat               62 /* Common                                      */
+#define __NR_fstat64             63 /* Linux Specific                              */
+#define __NR_getpagesize         64 /* Common                                      */
+#define __NR_msync               65 /* Common in newer 1.3.x revs...               */
+#define __NR_vfork               66 /* Common                                      */
+#define __NR_pread64             67 /* Linux Specific                              */
+#define __NR_pwrite64            68 /* Linux Specific                              */
+#define __NR_geteuid32           69 /* Linux sparc32, sbrk under SunOS             */
+#define __NR_getegid32           70 /* Linux sparc32, sstk under SunOS             */
+#define __NR_mmap                71 /* Common                                      */
+#define __NR_setreuid32          72 /* Linux sparc32, vadvise under SunOS          */
+#define __NR_munmap              73 /* Common                                      */
+#define __NR_mprotect            74 /* Common                                      */
+#define __NR_madvise             75 /* Common                                      */
+#define __NR_vhangup             76 /* Common                                      */
+#define __NR_truncate64          77 /* Linux sparc32 Specific                      */
+#define __NR_mincore             78 /* Common                                      */
+#define __NR_getgroups           79 /* Common                                      */
+#define __NR_setgroups           80 /* Common                                      */
+#define __NR_getpgrp             81 /* Common                                      */
+#define __NR_setgroups32         82 /* Linux sparc32, setpgrp under SunOS          */
+#define __NR_setitimer           83 /* Common                                      */
+#define __NR_ftruncate64         84 /* Linux sparc32 Specific                      */
+#define __NR_swapon              85 /* Common                                      */
+#define __NR_getitimer           86 /* Common                                      */
+#define __NR_setuid32            87 /* Linux sparc32, gethostname under SunOS      */
+#define __NR_sethostname         88 /* Common                                      */
+#define __NR_setgid32            89 /* Linux sparc32, getdtablesize under SunOS    */
+#define __NR_dup2                90 /* Common                                      */
+#define __NR_setfsuid32          91 /* Linux sparc32, getdopt under SunOS          */
+#define __NR_fcntl               92 /* Common                                      */
+#define __NR_select              93 /* Common                                      */
+#define __NR_setfsgid32          94 /* Linux sparc32, setdopt under SunOS          */
+#define __NR_fsync               95 /* Common                                      */
+#define __NR_setpriority         96 /* Common                                      */
+#define __NR_socket              97 /* Common                                      */
+#define __NR_connect             98 /* Common                                      */
+#define __NR_accept              99 /* Common                                      */
+#define __NR_getpriority        100 /* Common                                      */
+#define __NR_rt_sigreturn       101 /* Linux Specific                              */
+#define __NR_rt_sigaction       102 /* Linux Specific                              */
+#define __NR_rt_sigprocmask     103 /* Linux Specific                              */
+#define __NR_rt_sigpending      104 /* Linux Specific                              */
+#define __NR_rt_sigtimedwait    105 /* Linux Specific                              */
+#define __NR_rt_sigqueueinfo    106 /* Linux Specific                              */
+#define __NR_rt_sigsuspend      107 /* Linux Specific                              */
+#define __NR_setresuid32        108 /* Linux Specific, sigvec under SunOS          */
+#define __NR_getresuid32        109 /* Linux Specific, sigblock under SunOS        */
+#define __NR_setresgid32        110 /* Linux Specific, sigsetmask under SunOS      */
+#define __NR_getresgid32        111 /* Linux Specific, sigpause under SunOS        */
+#define __NR_setregid32         112 /* Linux sparc32, sigstack under SunOS         */
+#define __NR_recvmsg            113 /* Common                                      */
+#define __NR_sendmsg            114 /* Common                                      */
+#define __NR_getgroups32        115 /* Linux sparc32, vtrace under SunOS           */
+#define __NR_gettimeofday       116 /* Common                                      */
+#define __NR_getrusage          117 /* Common                                      */
+#define __NR_getsockopt         118 /* Common                                      */
+#define __NR_getcwd             119 /* Linux Specific                              */
+#define __NR_readv              120 /* Common                                      */
+#define __NR_writev             121 /* Common                                      */
+#define __NR_settimeofday       122 /* Common                                      */
+#define __NR_fchown             123 /* Common                                      */
+#define __NR_fchmod             124 /* Common                                      */
+#define __NR_recvfrom           125 /* Common                                      */
+#define __NR_setreuid           126 /* Common                                      */
+#define __NR_setregid           127 /* Common                                      */
+#define __NR_rename             128 /* Common                                      */
+#define __NR_truncate           129 /* Common                                      */
+#define __NR_ftruncate          130 /* Common                                      */
+#define __NR_flock              131 /* Common                                      */
+#define __NR_lstat64            132 /* Linux Specific                              */
+#define __NR_sendto             133 /* Common                                      */
+#define __NR_shutdown           134 /* Common                                      */
+#define __NR_socketpair         135 /* Common                                      */
+#define __NR_mkdir              136 /* Common                                      */
+#define __NR_rmdir              137 /* Common                                      */
+#define __NR_utimes             138 /* SunOS Specific                              */
+#define __NR_stat64             139 /* Linux Specific                              */
+#define __NR_sendfile64         140 /* adjtime under SunOS                         */
+#define __NR_getpeername        141 /* Common                                      */
+#define __NR_futex              142 /* gethostid under SunOS                       */
+#define __NR_gettid             143 /* ENOSYS under SunOS                          */
+#define __NR_getrlimit          144 /* Common                                      */
+#define __NR_setrlimit          145 /* Common                                      */
+#define __NR_pivot_root         146 /* Linux Specific, killpg under SunOS          */
+#define __NR_prctl              147 /* ENOSYS under SunOS                          */
+#define __NR_pciconfig_read     148 /* ENOSYS under SunOS                          */
+#define __NR_pciconfig_write    149 /* ENOSYS under SunOS                          */
+#define __NR_getsockname        150 /* Common                                      */
+#define __NR_inotify_init       151 /* Linux specific                              */
+#define __NR_inotify_add_watch  152 /* Linux specific                              */
+#define __NR_poll               153 /* Common                                      */
+#define __NR_getdents64         154 /* Linux specific                              */
+#define __NR_fcntl64            155 /* Linux sparc32 Specific                      */
+#define __NR_inotify_rm_watch   156 /* Linux specific                              */
+#define __NR_statfs             157 /* Common                                      */
+#define __NR_fstatfs            158 /* Common                                      */
+#define __NR_umount             159 /* Common                                      */
+#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS    */
+#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS           */
+#define __NR_getdomainname      162 /* SunOS Specific                              */
+#define __NR_setdomainname      163 /* Common                                      */
+/* #define __NR_utrap_install   164    Linux sparc64 specific                      */
+#define __NR_quotactl           165 /* Common                                      */
+#define __NR_set_tid_address    166 /* Linux specific, exportfs under SunOS        */
+#define __NR_mount              167 /* Common                                      */
+#define __NR_ustat              168 /* Common                                      */
+#define __NR_setxattr           169 /* SunOS: semsys                               */
+#define __NR_lsetxattr          170 /* SunOS: msgsys                               */
+#define __NR_fsetxattr          171 /* SunOS: shmsys                               */
+#define __NR_getxattr           172 /* SunOS: auditsys                             */
+#define __NR_lgetxattr          173 /* SunOS: rfssys                               */
+#define __NR_getdents           174 /* Common                                      */
+#define __NR_setsid             175 /* Common                                      */
+#define __NR_fchdir             176 /* Common                                      */
+#define __NR_fgetxattr          177 /* SunOS: fchroot                              */
+#define __NR_listxattr          178 /* SunOS: vpixsys                              */
+#define __NR_llistxattr         179 /* SunOS: aioread                              */
+#define __NR_flistxattr         180 /* SunOS: aiowrite                             */
+#define __NR_removexattr        181 /* SunOS: aiowait                              */
+#define __NR_lremovexattr       182 /* SunOS: aiocancel                            */
+#define __NR_sigpending         183 /* Common                                      */
+#define __NR_query_module       184 /* Linux Specific                              */
+#define __NR_setpgid            185 /* Common                                      */
+#define __NR_fremovexattr       186 /* SunOS: pathconf                             */
+#define __NR_tkill              187 /* SunOS: fpathconf                            */
+#define __NR_exit_group         188 /* Linux specific, sysconf undef SunOS         */
+#define __NR_uname              189 /* Linux Specific                              */
+#define __NR_init_module        190 /* Linux Specific                              */
+#define __NR_personality        191 /* Linux Specific                              */
+#define __NR_remap_file_pages   192 /* Linux Specific                              */
+#define __NR_epoll_create       193 /* Linux Specific                              */
+#define __NR_epoll_ctl          194 /* Linux Specific                              */
+#define __NR_epoll_wait         195 /* Linux Specific                              */
+#define __NR_ioprio_set         196 /* Linux Specific                              */
+#define __NR_getppid            197 /* Linux Specific                              */
+#define __NR_sigaction          198 /* Linux Specific                              */
+#define __NR_sgetmask           199 /* Linux Specific                              */
+#define __NR_ssetmask           200 /* Linux Specific                              */
+#define __NR_sigsuspend         201 /* Linux Specific                              */
+#define __NR_oldlstat           202 /* Linux Specific                              */
+#define __NR_uselib             203 /* Linux Specific                              */
+#define __NR_readdir            204 /* Linux Specific                              */
+#define __NR_readahead          205 /* Linux Specific                              */
+#define __NR_socketcall         206 /* Linux Specific                              */
+#define __NR_syslog             207 /* Linux Specific                              */
+#define __NR_lookup_dcookie     208 /* Linux Specific                              */
+#define __NR_fadvise64          209 /* Linux Specific                              */
+#define __NR_fadvise64_64       210 /* Linux Specific                              */
+#define __NR_tgkill             211 /* Linux Specific                              */
+#define __NR_waitpid            212 /* Linux Specific                              */
+#define __NR_swapoff            213 /* Linux Specific                              */
+#define __NR_sysinfo            214 /* Linux Specific                              */
+#define __NR_ipc                215 /* Linux Specific                              */
+#define __NR_sigreturn          216 /* Linux Specific                              */
+#define __NR_clone              217 /* Linux Specific                              */
+#define __NR_ioprio_get         218 /* Linux Specific                              */
+#define __NR_adjtimex           219 /* Linux Specific                              */
+#define __NR_sigprocmask        220 /* Linux Specific                              */
+#define __NR_create_module      221 /* Linux Specific                              */
+#define __NR_delete_module      222 /* Linux Specific                              */
+#define __NR_get_kernel_syms    223 /* Linux Specific                              */
+#define __NR_getpgid            224 /* Linux Specific                              */
+#define __NR_bdflush            225 /* Linux Specific                              */
+#define __NR_sysfs              226 /* Linux Specific                              */
+#define __NR_afs_syscall        227 /* Linux Specific                              */
+#define __NR_setfsuid           228 /* Linux Specific                              */
+#define __NR_setfsgid           229 /* Linux Specific                              */
+#define __NR__newselect         230 /* Linux Specific                              */
+#define __NR_time               231 /* Linux Specific                              */
+#define __NR_splice             232 /* Linux Specific                              */
+#define __NR_stime              233 /* Linux Specific                              */
+#define __NR_statfs64           234 /* Linux Specific                              */
+#define __NR_fstatfs64          235 /* Linux Specific                              */
+#define __NR__llseek            236 /* Linux Specific                              */
+#define __NR_mlock              237
+#define __NR_munlock            238
+#define __NR_mlockall           239
+#define __NR_munlockall         240
+#define __NR_sched_setparam     241
+#define __NR_sched_getparam     242
+#define __NR_sched_setscheduler 243
+#define __NR_sched_getscheduler 244
+#define __NR_sched_yield        245
+#define __NR_sched_get_priority_max 246
+#define __NR_sched_get_priority_min 247
+#define __NR_sched_rr_get_interval  248
+#define __NR_nanosleep          249
+#define __NR_mremap             250
+#define __NR__sysctl            251
+#define __NR_getsid             252
+#define __NR_fdatasync          253
+#define __NR_nfsservctl         254
+#define __NR_sync_file_range    255
+#define __NR_clock_settime      256
+#define __NR_clock_gettime      257
+#define __NR_clock_getres       258
+#define __NR_clock_nanosleep    259
+#define __NR_sched_getaffinity  260
+#define __NR_sched_setaffinity  261
+#define __NR_timer_settime      262
+#define __NR_timer_gettime      263
+#define __NR_timer_getoverrun   264
+#define __NR_timer_delete       265
+#define __NR_timer_create       266
+/* #define __NR_vserver         267 Reserved for VSERVER */
+#define __NR_io_setup           268
+#define __NR_io_destroy         269
+#define __NR_io_submit          270
+#define __NR_io_cancel          271
+#define __NR_io_getevents       272
+#define __NR_mq_open            273
+#define __NR_mq_unlink          274
+#define __NR_mq_timedsend       275
+#define __NR_mq_timedreceive    276
+#define __NR_mq_notify          277
+#define __NR_mq_getsetattr      278
+#define __NR_waitid             279
+#define __NR_tee                280
+#define __NR_add_key            281
+#define __NR_request_key        282
+#define __NR_keyctl             283
+#define __NR_openat             284
+#define __NR_mkdirat            285
+#define __NR_mknodat            286
+#define __NR_fchownat           287
+#define __NR_futimesat          288
+#define __NR_fstatat64          289
+#define __NR_unlinkat           290
+#define __NR_renameat           291
+#define __NR_linkat             292
+#define __NR_symlinkat          293
+#define __NR_readlinkat         294
+#define __NR_fchmodat           295
+#define __NR_faccessat          296
+#define __NR_pselect6           297
+#define __NR_ppoll              298
+#define __NR_unshare            299
+#define __NR_set_robust_list    300
+#define __NR_get_robust_list    301
+#define __NR_migrate_pages      302
+#define __NR_mbind              303
+#define __NR_get_mempolicy      304
+#define __NR_set_mempolicy      305
+#define __NR_kexec_load         306
+#define __NR_move_pages         307
+#define __NR_getcpu             308
+#define __NR_epoll_pwait        309
+#define __NR_utimensat          310
+#define __NR_signalfd           311
+#define __NR_timerfd_create     312
+#define __NR_eventfd            313
+#define __NR_fallocate          314
+#define __NR_timerfd_settime    315
+#define __NR_timerfd_gettime    316
+#define __NR_signalfd4          317
+#define __NR_eventfd2           318
+#define __NR_epoll_create1      319
+#define __NR_dup3               320
+#define __NR_pipe2              321
+#define __NR_inotify_init1      322
+
+#define NR_SYSCALLS             323
+
+/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
+ * it never had the plain ones and there is no value to adding those
+ * old versions into the syscall table.
+ */
+#define __IGNORE_setresuid
+#define __IGNORE_getresuid
+#define __IGNORE_setresgid
+#define __IGNORE_getresgid
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+
+#endif /* __KERNEL__ */
+#endif /* _SPARC_UNISTD_H */
diff --git a/arch/sparc/include/asm/unistd_64.h b/arch/sparc/include/asm/unistd_64.h
new file mode 100644
index 000000000000..c5cc0e052321
--- /dev/null
+++ b/arch/sparc/include/asm/unistd_64.h
@@ -0,0 +1,379 @@
+#ifndef _SPARC64_UNISTD_H
+#define _SPARC64_UNISTD_H
+
+/*
+ * System calls under the Sparc.
+ *
+ * Don't be scared by the ugly clobbers, it is the only way I can
+ * think of right now to force the arguments into fixed registers
+ * before the trap into the system call with gcc 'asm' statements.
+ *
+ * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
+ *
+ * SunOS compatibility based upon preliminary work which is:
+ *
+ * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
+ */
+
+#define __NR_restart_syscall      0 /* Linux Specific                              */
+#define __NR_exit                 1 /* Common                                      */
+#define __NR_fork                 2 /* Common                                      */
+#define __NR_read                 3 /* Common                                      */
+#define __NR_write                4 /* Common                                      */
+#define __NR_open                 5 /* Common                                      */
+#define __NR_close                6 /* Common                                      */
+#define __NR_wait4                7 /* Common                                      */
+#define __NR_creat                8 /* Common                                      */
+#define __NR_link                 9 /* Common                                      */
+#define __NR_unlink              10 /* Common                                      */
+#define __NR_execv               11 /* SunOS Specific                              */
+#define __NR_chdir               12 /* Common                                      */
+#define __NR_chown               13 /* Common                                      */
+#define __NR_mknod               14 /* Common                                      */
+#define __NR_chmod               15 /* Common                                      */
+#define __NR_lchown              16 /* Common                                      */
+#define __NR_brk                 17 /* Common                                      */
+#define __NR_perfctr             18 /* Performance counter operations              */
+#define __NR_lseek               19 /* Common                                      */
+#define __NR_getpid              20 /* Common                                      */
+#define __NR_capget              21 /* Linux Specific                              */
+#define __NR_capset              22 /* Linux Specific                              */
+#define __NR_setuid              23 /* Implemented via setreuid in SunOS           */
+#define __NR_getuid              24 /* Common                                      */
+#define __NR_vmsplice            25 /* ENOSYS under SunOS                          */
+#define __NR_ptrace              26 /* Common                                      */
+#define __NR_alarm               27 /* Implemented via setitimer in SunOS          */
+#define __NR_sigaltstack         28 /* Common                                      */
+#define __NR_pause               29 /* Is sigblock(0)->sigpause() in SunOS         */
+#define __NR_utime               30 /* Implemented via utimes() under SunOS        */
+/* #define __NR_lchown32         31    Linux sparc32 specific                      */
+/* #define __NR_fchown32         32    Linux sparc32 specific                      */
+#define __NR_access              33 /* Common                                      */
+#define __NR_nice                34 /* Implemented via get/setpriority() in SunOS  */
+/* #define __NR_chown32          35    Linux sparc32 specific                      */
+#define __NR_sync                36 /* Common                                      */
+#define __NR_kill                37 /* Common                                      */
+#define __NR_stat                38 /* Common                                      */
+#define __NR_sendfile            39 /* Linux Specific                              */
+#define __NR_lstat               40 /* Common                                      */
+#define __NR_dup                 41 /* Common                                      */
+#define __NR_pipe                42 /* Common                                      */
+#define __NR_times               43 /* Implemented via getrusage() in SunOS        */
+/* #define __NR_getuid32         44    Linux sparc32 specific                      */
+#define __NR_umount2             45 /* Linux Specific                              */
+#define __NR_setgid              46 /* Implemented via setregid() in SunOS         */
+#define __NR_getgid              47 /* Common                                      */
+#define __NR_signal              48 /* Implemented via sigvec() in SunOS           */
+#define __NR_geteuid             49 /* SunOS calls getuid()                        */
+#define __NR_getegid             50 /* SunOS calls getgid()                        */
+#define __NR_acct                51 /* Common                                      */
+#define __NR_memory_ordering     52 /* Linux Specific                              */
+/* #define __NR_getgid32         53    Linux sparc32 specific                      */
+#define __NR_ioctl               54 /* Common                                      */
+#define __NR_reboot              55 /* Common                                      */
+/* #define __NR_mmap2            56    Linux sparc32 Specific                      */
+#define __NR_symlink             57 /* Common                                      */
+#define __NR_readlink            58 /* Common                                      */
+#define __NR_execve              59 /* Common                                      */
+#define __NR_umask               60 /* Common                                      */
+#define __NR_chroot              61 /* Common                                      */
+#define __NR_fstat               62 /* Common                                      */
+#define __NR_fstat64             63 /* Linux Specific                              */
+#define __NR_getpagesize         64 /* Common                                      */
+#define __NR_msync               65 /* Common in newer 1.3.x revs...               */
+#define __NR_vfork               66 /* Common                                      */
+#define __NR_pread64             67 /* Linux Specific                              */
+#define __NR_pwrite64            68 /* Linux Specific                              */
+/* #define __NR_geteuid32        69    Linux sparc32, sbrk under SunOS             */
+/* #define __NR_getegid32        70    Linux sparc32, sstk under SunOS             */
+#define __NR_mmap                71 /* Common                                      */
+/* #define __NR_setreuid32       72    Linux sparc32, vadvise under SunOS          */
+#define __NR_munmap              73 /* Common                                      */
+#define __NR_mprotect            74 /* Common                                      */
+#define __NR_madvise             75 /* Common                                      */
+#define __NR_vhangup             76 /* Common                                      */
+/* #define __NR_truncate64       77    Linux sparc32 Specific                      */
+#define __NR_mincore             78 /* Common                                      */
+#define __NR_getgroups           79 /* Common                                      */
+#define __NR_setgroups           80 /* Common                                      */
+#define __NR_getpgrp             81 /* Common                                      */
+/* #define __NR_setgroups32      82    Linux sparc32, setpgrp under SunOS          */
+#define __NR_setitimer           83 /* Common                                      */
+/* #define __NR_ftruncate64      84    Linux sparc32 Specific                      */
+#define __NR_swapon              85 /* Common                                      */
+#define __NR_getitimer           86 /* Common                                      */
+/* #define __NR_setuid32         87    Linux sparc32, gethostname under SunOS      */
+#define __NR_sethostname         88 /* Common                                      */
+/* #define __NR_setgid32         89    Linux sparc32, getdtablesize under SunOS    */
+#define __NR_dup2                90 /* Common                                      */
+/* #define __NR_setfsuid32       91    Linux sparc32, getdopt under SunOS          */
+#define __NR_fcntl               92 /* Common                                      */
+#define __NR_select              93 /* Common                                      */
+/* #define __NR_setfsgid32       94    Linux sparc32, setdopt under SunOS          */
+#define __NR_fsync               95 /* Common                                      */
+#define __NR_setpriority         96 /* Common                                      */
+#define __NR_socket              97 /* Common                                      */
+#define __NR_connect             98 /* Common                                      */
+#define __NR_accept              99 /* Common                                      */
+#define __NR_getpriority        100 /* Common                                      */
+#define __NR_rt_sigreturn       101 /* Linux Specific                              */
+#define __NR_rt_sigaction       102 /* Linux Specific                              */
+#define __NR_rt_sigprocmask     103 /* Linux Specific                              */
+#define __NR_rt_sigpending      104 /* Linux Specific                              */
+#define __NR_rt_sigtimedwait    105 /* Linux Specific                              */
+#define __NR_rt_sigqueueinfo    106 /* Linux Specific                              */
+#define __NR_rt_sigsuspend      107 /* Linux Specific                              */
+#define __NR_setresuid          108 /* Linux Specific, sigvec under SunOS          */
+#define __NR_getresuid          109 /* Linux Specific, sigblock under SunOS        */
+#define __NR_setresgid          110 /* Linux Specific, sigsetmask under SunOS      */
+#define __NR_getresgid          111 /* Linux Specific, sigpause under SunOS        */
+/* #define __NR_setregid32       75    Linux sparc32, sigstack under SunOS         */
+#define __NR_recvmsg            113 /* Common                                      */
+#define __NR_sendmsg            114 /* Common                                      */
+/* #define __NR_getgroups32     115    Linux sparc32, vtrace under SunOS           */
+#define __NR_gettimeofday       116 /* Common                                      */
+#define __NR_getrusage          117 /* Common                                      */
+#define __NR_getsockopt         118 /* Common                                      */
+#define __NR_getcwd             119 /* Linux Specific                              */
+#define __NR_readv              120 /* Common                                      */
+#define __NR_writev             121 /* Common                                      */
+#define __NR_settimeofday       122 /* Common                                      */
+#define __NR_fchown             123 /* Common                                      */
+#define __NR_fchmod             124 /* Common                                      */
+#define __NR_recvfrom           125 /* Common                                      */
+#define __NR_setreuid           126 /* Common                                      */
+#define __NR_setregid           127 /* Common                                      */
+#define __NR_rename             128 /* Common                                      */
+#define __NR_truncate           129 /* Common                                      */
+#define __NR_ftruncate          130 /* Common                                      */
+#define __NR_flock              131 /* Common                                      */
+#define __NR_lstat64            132 /* Linux Specific                              */
+#define __NR_sendto             133 /* Common                                      */
+#define __NR_shutdown           134 /* Common                                      */
+#define __NR_socketpair         135 /* Common                                      */
+#define __NR_mkdir              136 /* Common                                      */
+#define __NR_rmdir              137 /* Common                                      */
+#define __NR_utimes             138 /* SunOS Specific                              */
+#define __NR_stat64             139 /* Linux Specific                              */
+#define __NR_sendfile64         140 /* adjtime under SunOS                         */
+#define __NR_getpeername        141 /* Common                                      */
+#define __NR_futex              142 /* gethostid under SunOS                       */
+#define __NR_gettid             143 /* ENOSYS under SunOS                          */
+#define __NR_getrlimit          144 /* Common                                      */
+#define __NR_setrlimit          145 /* Common                                      */
+#define __NR_pivot_root         146 /* Linux Specific, killpg under SunOS          */
+#define __NR_prctl              147 /* ENOSYS under SunOS                          */
+#define __NR_pciconfig_read     148 /* ENOSYS under SunOS                          */
+#define __NR_pciconfig_write    149 /* ENOSYS under SunOS                          */
+#define __NR_getsockname        150 /* Common                                      */
+#define __NR_inotify_init       151 /* Linux specific                              */
+#define __NR_inotify_add_watch  152 /* Linux specific                              */
+#define __NR_poll               153 /* Common                                      */
+#define __NR_getdents64         154 /* Linux specific                              */
+/* #define __NR_fcntl64         155    Linux sparc32 Specific                      */
+#define __NR_inotify_rm_watch   156 /* Linux specific                              */
+#define __NR_statfs             157 /* Common                                      */
+#define __NR_fstatfs            158 /* Common                                      */
+#define __NR_umount             159 /* Common                                      */
+#define __NR_sched_set_affinity 160 /* Linux specific, async_daemon under SunOS    */
+#define __NR_sched_get_affinity 161 /* Linux specific, getfh under SunOS           */
+#define __NR_getdomainname      162 /* SunOS Specific                              */
+#define __NR_setdomainname      163 /* Common                                      */
+#define __NR_utrap_install      164 /* SYSV ABI/v9 required                        */
+#define __NR_quotactl           165 /* Common                                      */
+#define __NR_set_tid_address    166 /* Linux specific, exportfs under SunOS        */
+#define __NR_mount              167 /* Common                                      */
+#define __NR_ustat              168 /* Common                                      */
+#define __NR_setxattr           169 /* SunOS: semsys                               */
+#define __NR_lsetxattr          170 /* SunOS: msgsys                               */
+#define __NR_fsetxattr          171 /* SunOS: shmsys                               */
+#define __NR_getxattr           172 /* SunOS: auditsys                             */
+#define __NR_lgetxattr          173 /* SunOS: rfssys                               */
+#define __NR_getdents           174 /* Common                                      */
+#define __NR_setsid             175 /* Common                                      */
+#define __NR_fchdir             176 /* Common                                      */
+#define __NR_fgetxattr          177 /* SunOS: fchroot                              */
+#define __NR_listxattr          178 /* SunOS: vpixsys                              */
+#define __NR_llistxattr         179 /* SunOS: aioread                              */
+#define __NR_flistxattr         180 /* SunOS: aiowrite                             */
+#define __NR_removexattr        181 /* SunOS: aiowait                              */
+#define __NR_lremovexattr       182 /* SunOS: aiocancel                            */
+#define __NR_sigpending         183 /* Common                                      */
+#define __NR_query_module       184 /* Linux Specific                              */
+#define __NR_setpgid            185 /* Common                                      */
+#define __NR_fremovexattr       186 /* SunOS: pathconf                             */
+#define __NR_tkill              187 /* SunOS: fpathconf                            */
+#define __NR_exit_group         188 /* Linux specific, sysconf undef SunOS         */
+#define __NR_uname              189 /* Linux Specific                              */
+#define __NR_init_module        190 /* Linux Specific                              */
+#define __NR_personality        191 /* Linux Specific                              */
+#define __NR_remap_file_pages   192 /* Linux Specific                              */
+#define __NR_epoll_create       193 /* Linux Specific                              */
+#define __NR_epoll_ctl          194 /* Linux Specific                              */
+#define __NR_epoll_wait         195 /* Linux Specific                              */
+#define __NR_ioprio_set         196 /* Linux Specific                              */
+#define __NR_getppid            197 /* Linux Specific                              */
+#define __NR_sigaction          198 /* Linux Specific                              */
+#define __NR_sgetmask           199 /* Linux Specific                              */
+#define __NR_ssetmask           200 /* Linux Specific                              */
+#define __NR_sigsuspend         201 /* Linux Specific                              */
+#define __NR_oldlstat           202 /* Linux Specific                              */
+#define __NR_uselib             203 /* Linux Specific                              */
+#define __NR_readdir            204 /* Linux Specific                              */
+#define __NR_readahead          205 /* Linux Specific                              */
+#define __NR_socketcall         206 /* Linux Specific                              */
+#define __NR_syslog             207 /* Linux Specific                              */
+#define __NR_lookup_dcookie     208 /* Linux Specific                              */
+#define __NR_fadvise64          209 /* Linux Specific                              */
+#define __NR_fadvise64_64       210 /* Linux Specific                              */
+#define __NR_tgkill             211 /* Linux Specific                              */
+#define __NR_waitpid            212 /* Linux Specific                              */
+#define __NR_swapoff            213 /* Linux Specific                              */
+#define __NR_sysinfo            214 /* Linux Specific                              */
+#define __NR_ipc                215 /* Linux Specific                              */
+#define __NR_sigreturn          216 /* Linux Specific                              */
+#define __NR_clone              217 /* Linux Specific                              */
+#define __NR_ioprio_get         218 /* Linux Specific                              */
+#define __NR_adjtimex           219 /* Linux Specific                              */
+#define __NR_sigprocmask        220 /* Linux Specific                              */
+#define __NR_create_module      221 /* Linux Specific                              */
+#define __NR_delete_module      222 /* Linux Specific                              */
+#define __NR_get_kernel_syms    223 /* Linux Specific                              */
+#define __NR_getpgid            224 /* Linux Specific                              */
+#define __NR_bdflush            225 /* Linux Specific                              */
+#define __NR_sysfs              226 /* Linux Specific                              */
+#define __NR_afs_syscall        227 /* Linux Specific                              */
+#define __NR_setfsuid           228 /* Linux Specific                              */
+#define __NR_setfsgid           229 /* Linux Specific                              */
+#define __NR__newselect         230 /* Linux Specific                              */
+#ifdef __KERNEL__
+#define __NR_time               231 /* Linux sparc32                               */
+#endif
+#define __NR_splice             232 /* Linux Specific                              */
+#define __NR_stime              233 /* Linux Specific                              */
+#define __NR_statfs64           234 /* Linux Specific                              */
+#define __NR_fstatfs64          235 /* Linux Specific                              */
+#define __NR__llseek            236 /* Linux Specific                              */
+#define __NR_mlock              237
+#define __NR_munlock            238
+#define __NR_mlockall           239
+#define __NR_munlockall         240
+#define __NR_sched_setparam     241
+#define __NR_sched_getparam     242
+#define __NR_sched_setscheduler 243
+#define __NR_sched_getscheduler 244
+#define __NR_sched_yield        245
+#define __NR_sched_get_priority_max 246
+#define __NR_sched_get_priority_min 247
+#define __NR_sched_rr_get_interval  248
+#define __NR_nanosleep          249
+#define __NR_mremap             250
+#define __NR__sysctl            251
+#define __NR_getsid             252
+#define __NR_fdatasync          253
+#define __NR_nfsservctl         254
+#define __NR_sync_file_range    255
+#define __NR_clock_settime      256
+#define __NR_clock_gettime      257
+#define __NR_clock_getres       258
+#define __NR_clock_nanosleep    259
+#define __NR_sched_getaffinity  260
+#define __NR_sched_setaffinity  261
+#define __NR_timer_settime      262
+#define __NR_timer_gettime      263
+#define __NR_timer_getoverrun   264
+#define __NR_timer_delete       265
+#define __NR_timer_create       266
+/* #define __NR_vserver         267 Reserved for VSERVER */
+#define __NR_io_setup           268
+#define __NR_io_destroy         269
+#define __NR_io_submit          270
+#define __NR_io_cancel          271
+#define __NR_io_getevents       272
+#define __NR_mq_open            273
+#define __NR_mq_unlink          274
+#define __NR_mq_timedsend       275
+#define __NR_mq_timedreceive    276
+#define __NR_mq_notify          277
+#define __NR_mq_getsetattr      278
+#define __NR_waitid             279
+#define __NR_tee                280
+#define __NR_add_key            281
+#define __NR_request_key        282
+#define __NR_keyctl             283
+#define __NR_openat             284
+#define __NR_mkdirat            285
+#define __NR_mknodat            286
+#define __NR_fchownat           287
+#define __NR_futimesat          288
+#define __NR_fstatat64          289
+#define __NR_unlinkat           290
+#define __NR_renameat           291
+#define __NR_linkat             292
+#define __NR_symlinkat          293
+#define __NR_readlinkat         294
+#define __NR_fchmodat           295
+#define __NR_faccessat          296
+#define __NR_pselect6           297
+#define __NR_ppoll              298
+#define __NR_unshare            299
+#define __NR_set_robust_list    300
+#define __NR_get_robust_list    301
+#define __NR_migrate_pages      302
+#define __NR_mbind              303
+#define __NR_get_mempolicy      304
+#define __NR_set_mempolicy      305
+#define __NR_kexec_load         306
+#define __NR_move_pages         307
+#define __NR_getcpu             308
+#define __NR_epoll_pwait        309
+#define __NR_utimensat          310
+#define __NR_signalfd           311
+#define __NR_timerfd_create     312
+#define __NR_eventfd            313
+#define __NR_fallocate          314
+#define __NR_timerfd_settime    315
+#define __NR_timerfd_gettime    316
+#define __NR_signalfd4          317
+#define __NR_eventfd2           318
+#define __NR_epoll_create1      319
+#define __NR_dup3               320
+#define __NR_pipe2              321
+#define __NR_inotify_init1      322
+
+#define NR_SYSCALLS             323
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_COMPAT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+
+#endif /* __KERNEL__ */
+#endif /* _SPARC64_UNISTD_H */
diff --git a/arch/sparc/include/asm/upa.h b/arch/sparc/include/asm/upa.h
new file mode 100644
index 000000000000..5b1633223f92
--- /dev/null
+++ b/arch/sparc/include/asm/upa.h
@@ -0,0 +1,109 @@
+#ifndef _SPARC64_UPA_H
+#define _SPARC64_UPA_H
+
+#include <asm/asi.h>
+
+/* UPA level registers and defines. */
+
+/* UPA Config Register */
+#define UPA_CONFIG_RESV         0xffffffffc0000000 /* Reserved.                    */
+#define UPA_CONFIG_PCON         0x000000003fc00000 /* Depth of various sys queues. */
+#define UPA_CONFIG_MID          0x00000000003e0000 /* Module ID.                   */
+#define UPA_CONFIG_PCAP         0x000000000001ffff /* Port Capabilities.           */
+
+/* UPA Port ID Register */
+#define UPA_PORTID_FNP          0xff00000000000000 /* Hardcoded to 0xfc on ultra.  */
+#define UPA_PORTID_RESV         0x00fffff800000000 /* Reserved.                    */
+#define UPA_PORTID_ECCVALID     0x0000000400000000 /* Zero if mod can generate ECC */
+#define UPA_PORTID_ONEREAD      0x0000000200000000 /* Set if mod generates P_RASB  */
+#define UPA_PORTID_PINTRDQ      0x0000000180000000 /* # outstanding P_INT_REQ's    */
+#define UPA_PORTID_PREQDQ       0x000000007e000000 /* slave-wr's to mod supported  */
+#define UPA_PORTID_PREQRD       0x0000000001e00000 /* # incoming P_REQ's supported */
+#define UPA_PORTID_UPACAP       0x00000000001f0000 /* UPA capabilities of mod      */
+#define UPA_PORTID_ID           0x000000000000ffff /* Module Identification bits  */
+
+/* UPA I/O space accessors */
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+static inline unsigned char _upa_readb(unsigned long addr)
+{
+        unsigned char ret;
+
+        __asm__ __volatile__("lduba\t[%1] %2, %0\t/* upa_readb */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline unsigned short _upa_readw(unsigned long addr)
+{
+        unsigned short ret;
+
+        __asm__ __volatile__("lduha\t[%1] %2, %0\t/* upa_readw */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline unsigned int _upa_readl(unsigned long addr)
+{
+        unsigned int ret;
+
+        __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* upa_readl */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline unsigned long _upa_readq(unsigned long addr)
+{
+        unsigned long ret;
+
+        __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* upa_readq */"
+                             : "=r" (ret)
+                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+
+        return ret;
+}
+
+static inline void _upa_writeb(unsigned char b, unsigned long addr)
+{
+        __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */"
+                             : /* no outputs */
+                             : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _upa_writew(unsigned short w, unsigned long addr)
+{
+        __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */"
+                             : /* no outputs */
+                             : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _upa_writel(unsigned int l, unsigned long addr)
+{
+        __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */"
+                             : /* no outputs */
+                             : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+static inline void _upa_writeq(unsigned long q, unsigned long addr)
+{
+        __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */"
+                             : /* no outputs */
+                             : "r" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
+}
+
+#define upa_readb(__addr)               (_upa_readb((unsigned long)(__addr)))
+#define upa_readw(__addr)               (_upa_readw((unsigned long)(__addr)))
+#define upa_readl(__addr)               (_upa_readl((unsigned long)(__addr)))
+#define upa_readq(__addr)               (_upa_readq((unsigned long)(__addr)))
+#define upa_writeb(__b, __addr)         (_upa_writeb((__b), (unsigned long)(__addr)))
+#define upa_writew(__w, __addr)         (_upa_writew((__w), (unsigned long)(__addr)))
+#define upa_writel(__l, __addr)         (_upa_writel((__l), (unsigned long)(__addr)))
+#define upa_writeq(__q, __addr)         (_upa_writeq((__q), (unsigned long)(__addr)))
+#endif /* __KERNEL__ && !__ASSEMBLY__ */
+
+#endif /* !(_SPARC64_UPA_H) */
diff --git a/arch/sparc/include/asm/user.h b/arch/sparc/include/asm/user.h
new file mode 100644
index 000000000000..3400ea87f148
--- /dev/null
+++ b/arch/sparc/include/asm/user.h
@@ -0,0 +1,6 @@
+#ifndef _SPARC_USER_H
+#define _SPARC_USER_H
+
+/* Nothing to define.  */
+
+#endif /* !(_SPARC_USER_H) */
diff --git a/arch/sparc/include/asm/utrap.h b/arch/sparc/include/asm/utrap.h
new file mode 100644
index 000000000000..b10e527c22d9
--- /dev/null
+++ b/arch/sparc/include/asm/utrap.h
@@ -0,0 +1,51 @@
+/*
+ * include/asm/utrap.h
+ *
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __ASM_SPARC64_UTRAP_H
+#define __ASM_SPARC64_UTRAP_H
+
+#define UT_INSTRUCTION_EXCEPTION                1
+#define UT_INSTRUCTION_ERROR                    2
+#define UT_INSTRUCTION_PROTECTION               3
+#define UT_ILLTRAP_INSTRUCTION                  4
+#define UT_ILLEGAL_INSTRUCTION                  5
+#define UT_PRIVILEGED_OPCODE                    6
+#define UT_FP_DISABLED                          7
+#define UT_FP_EXCEPTION_IEEE_754                8
+#define UT_FP_EXCEPTION_OTHER                   9
+#define UT_TAG_OVERVIEW                         10
+#define UT_DIVISION_BY_ZERO                     11
+#define UT_DATA_EXCEPTION                       12
+#define UT_DATA_ERROR                           13
+#define UT_DATA_PROTECTION                      14
+#define UT_MEM_ADDRESS_NOT_ALIGNED              15
+#define UT_PRIVILEGED_ACTION                    16
+#define UT_ASYNC_DATA_ERROR                     17
+#define UT_TRAP_INSTRUCTION_16                  18
+#define UT_TRAP_INSTRUCTION_17                  19
+#define UT_TRAP_INSTRUCTION_18                  20
+#define UT_TRAP_INSTRUCTION_19                  21
+#define UT_TRAP_INSTRUCTION_20                  22
+#define UT_TRAP_INSTRUCTION_21                  23
+#define UT_TRAP_INSTRUCTION_22                  24
+#define UT_TRAP_INSTRUCTION_23                  25
+#define UT_TRAP_INSTRUCTION_24                  26
+#define UT_TRAP_INSTRUCTION_25                  27
+#define UT_TRAP_INSTRUCTION_26                  28
+#define UT_TRAP_INSTRUCTION_27                  29
+#define UT_TRAP_INSTRUCTION_28                  30
+#define UT_TRAP_INSTRUCTION_29                  31
+#define UT_TRAP_INSTRUCTION_30                  32
+#define UT_TRAP_INSTRUCTION_31                  33
+
+#define UTH_NOCHANGE                            (-1)
+
+#ifndef __ASSEMBLY__
+typedef int utrap_entry_t;
+typedef void *utrap_handler_t;
+#endif /* __ASSEMBLY__ */
+
+#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
diff --git a/arch/sparc/include/asm/vac-ops.h b/arch/sparc/include/asm/vac-ops.h
new file mode 100644
index 000000000000..d10527611f11
--- /dev/null
+++ b/arch/sparc/include/asm/vac-ops.h
@@ -0,0 +1,134 @@
+#ifndef _SPARC_VAC_OPS_H
+#define _SPARC_VAC_OPS_H
+
+/* vac-ops.h: Inline assembly routines to do operations on the Sparc
+ *            VAC (virtual address cache) for the sun4c.
+ *
+ * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#include <asm/sysen.h>
+#include <asm/contregs.h>
+#include <asm/asi.h>
+
+/* The SUN4C models have a virtually addressed write-through
+ * cache.
+ *
+ * The cache tags are directly accessible through an ASI and
+ * each have the form:
+ *
+ * ------------------------------------------------------------
+ * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ |
+ * ------------------------------------------------------------
+ *  31 25  24   22     21     20     19    18 16  15   2  1  0
+ *
+ * MBZ: These bits are either unused and/or reserved and should
+ *      be written as zeroes.
+ *
+ * CONTEXT: Records the context to which this cache line belongs.
+ *
+ * WRITE: A copy of the writable bit from the mmu pte access bits.
+ *
+ * PRIV: A copy of the privileged bit from the pte access bits.
+ *
+ * VALID: If set, this line is valid, else invalid.
+ *
+ * TagID: Fourteen bits of tag ID.
+ *
+ * Every virtual address is seen by the cache like this:
+ *
+ * ----------------------------------------
+ * |  RESV  | TagID | LINE | BYTE-in-LINE |
+ * ----------------------------------------
+ *  31    30 29   16 15   4 3            0
+ *
+ * RESV: Unused/reserved.
+ *
+ * TagID: Used to match the Tag-ID in that vac tags.
+ *
+ * LINE: Which line within the cache
+ *
+ * BYTE-in-LINE: Which byte within the cache line.
+ */
+
+/* Sun4c VAC Tags */
+#define S4CVACTAG_CID      0x01c00000
+#define S4CVACTAG_W        0x00200000
+#define S4CVACTAG_P        0x00100000
+#define S4CVACTAG_V        0x00080000
+#define S4CVACTAG_TID      0x0000fffc
+
+/* Sun4c VAC Virtual Address */
+/* These aren't used, why bother? (Anton) */
+#if 0
+#define S4CVACVA_TID       0x3fff0000
+#define S4CVACVA_LINE      0x0000fff0
+#define S4CVACVA_BIL       0x0000000f
+#endif
+
+/* The indexing of cache lines creates a problem.  Because the line
+ * field of a virtual address extends past the page offset within
+ * the virtual address it is possible to have what are called
+ * 'bad aliases' which will create inconsistencies.  So we must make
+ * sure that within a context that if a physical page is mapped
+ * more than once, that 'extra' line bits are the same.  If this is
+ * not the case, and thus is a 'bad alias' we must turn off the
+ * cacheable bit in the pte's of all such pages.
+ */
+
+#ifdef CONFIG_SUN4
+#define S4CVAC_BADBITS     0x0001e000
+#else
+#define S4CVAC_BADBITS    0x0000f000
+#endif
+
+/* The following is true if vaddr1 and vaddr2 would cause
+ * a 'bad alias'.
+ */
+#define S4CVAC_BADALIAS(vaddr1, vaddr2) \
+        ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \
+         (S4CVAC_BADBITS))
+
+/* The following structure describes the characteristics of a sun4c
+ * VAC as probed from the prom during boot time.
+ */
+struct sun4c_vac_props {
+        unsigned int num_bytes;     /* Size of the cache */
+        unsigned int num_lines;     /* Number of cache lines */
+        unsigned int do_hwflushes;  /* Hardware flushing available? */
+        enum { VAC_NONE, VAC_WRITE_THROUGH,
+            VAC_WRITE_BACK } type;  /* What type of VAC? */
+        unsigned int linesize;      /* Size of each line in bytes */
+        unsigned int log2lsize;     /* log2(linesize) */
+        unsigned int on;            /* VAC is enabled */
+};
+
+extern struct sun4c_vac_props sun4c_vacinfo;
+
+/* sun4c_enable_vac() enables the sun4c virtual address cache. */
+static inline void sun4c_enable_vac(void)
+{
+        __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
+                             "or    %%g1, %2, %%g1\n\t"
+                             "stba  %%g1, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" ((unsigned int) AC_SENABLE),
+                             "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
+                             : "g1", "memory");
+        sun4c_vacinfo.on = 1;
+}
+
+/* sun4c_disable_vac() disables the virtual address cache. */
+static inline void sun4c_disable_vac(void)
+{
+        __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
+                             "andn  %%g1, %2, %%g1\n\t"
+                             "stba  %%g1, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" ((unsigned int) AC_SENABLE),
+                             "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
+                             : "g1", "memory");
+        sun4c_vacinfo.on = 0;
+}
+
+#endif /* !(_SPARC_VAC_OPS_H) */
diff --git a/arch/sparc/include/asm/vaddrs.h b/arch/sparc/include/asm/vaddrs.h
new file mode 100644
index 000000000000..541e13755cec
--- /dev/null
+++ b/arch/sparc/include/asm/vaddrs.h
@@ -0,0 +1,64 @@
+#ifndef _SPARC_VADDRS_H
+#define _SPARC_VADDRS_H
+
+#include <asm/head.h>
+
+/*
+ * asm/vaddrs.h:  Here we define the virtual addresses at
+ *                      which important things will be mapped.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 2000 Anton Blanchard (anton@samba.org)
+ */
+
+#define SRMMU_MAXMEM            0x0c000000
+
+#define SRMMU_NOCACHE_VADDR     (KERNBASE + SRMMU_MAXMEM)
+                                /* = 0x0fc000000 */
+/* XXX Empiricals - this needs to go away - KMW */
+#define SRMMU_MIN_NOCACHE_PAGES (550)
+#define SRMMU_MAX_NOCACHE_PAGES (1280)
+
+/* The following constant is used in mm/srmmu.c::srmmu_nocache_calcsize()
+ * to determine the amount of memory that will be reserved as nocache:
+ *
+ * 256 pages will be taken as nocache per each
+ * SRMMU_NOCACHE_ALCRATIO MB of system memory.
+ *
+ * limits enforced:     nocache minimum = 256 pages
+ *                      nocache maximum = 1280 pages
+ */
+#define SRMMU_NOCACHE_ALCRATIO  64      /* 256 pages per 64MB of system RAM */
+
+#define SUN4M_IOBASE_VADDR      0xfd000000 /* Base for mapping pages */
+#define IOBASE_VADDR            0xfe000000
+#define IOBASE_END              0xfe600000
+
+/*
+ * On the sun4/4c we need a place
+ * to reliably map locked down kernel data.  This includes the
+ * task_struct and kernel stack pages of each process plus the
+ * scsi buffers during dvma IO transfers, also the floppy buffers
+ * during pseudo dma which runs with traps off (no faults allowed).
+ * Some quick calculations yield:
+ *       NR_TASKS <512> * (3 * PAGE_SIZE) == 0x600000
+ * Subtract this from 0xc00000 and you get 0x927C0 of vm left
+ * over to map SCSI dvma + floppy pseudo-dma buffers.  So be
+ * careful if you change NR_TASKS or else there won't be enough
+ * room for it all.
+ */
+#define SUN4C_LOCK_VADDR        0xff000000
+#define SUN4C_LOCK_END          0xffc00000
+
+#define KADB_DEBUGGER_BEGVM     0xffc00000 /* Where kern debugger is in virt-mem */
+#define KADB_DEBUGGER_ENDVM     0xffd00000
+#define DEBUG_FIRSTVADDR        KADB_DEBUGGER_BEGVM
+#define DEBUG_LASTVADDR         KADB_DEBUGGER_ENDVM
+
+#define LINUX_OPPROM_BEGVM      0xffd00000
+#define LINUX_OPPROM_ENDVM      0xfff00000
+
+#define DVMA_VADDR              0xfff00000 /* Base area of the DVMA on suns */
+#define DVMA_END                0xfffc0000
+
+#endif /* !(_SPARC_VADDRS_H) */
diff --git a/arch/sparc/include/asm/vfc_ioctls.h b/arch/sparc/include/asm/vfc_ioctls.h
new file mode 100644
index 000000000000..af8b69007b22
--- /dev/null
+++ b/arch/sparc/include/asm/vfc_ioctls.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 1996 by Manish Vachharajani */
+
+#ifndef _LINUX_VFC_IOCTLS_H_
+#define _LINUX_VFC_IOCTLS_H_
+
+        /* IOCTLs */
+#define VFC_IOCTL(a)          (('j' << 8) | a)
+#define VFCGCTRL        (VFC_IOCTL (0))         /* get vfc attributes */
+#define VFCSCTRL        (VFC_IOCTL (1))         /* set vfc attributes */
+#define VFCGVID         (VFC_IOCTL (2))         /* get video decoder attributes */
+#define VFCSVID         (VFC_IOCTL (3))         /* set video decoder attributes */
+#define VFCHUE          (VFC_IOCTL (4))         /* set hue */
+#define VFCPORTCHG      (VFC_IOCTL (5))         /* change port */
+#define VFCRDINFO       (VFC_IOCTL (6))         /* read info */
+
+        /* Options for setting the vfc attributes and status */
+#define MEMPRST         0x1     /* reset FIFO ptr. */
+#define CAPTRCMD        0x2     /* start capture and wait */
+#define DIAGMODE        0x3     /* diag mode */
+#define NORMMODE        0x4     /* normal mode */
+#define CAPTRSTR        0x5     /* start capture */
+#define CAPTRWAIT       0x6     /* wait for capture to finish */
+
+
+        /* Options for the decoder */
+#define STD_NTSC        0x1     /* NTSC mode */
+#define STD_PAL         0x2     /* PAL mode */
+#define COLOR_ON        0x3     /* force color ON */
+#define MONO            0x4     /* force color OFF */
+
+        /* Values returned by ioctl 2 */
+
+#define NO_LOCK         1
+#define NTSC_COLOR      2
+#define NTSC_NOCOLOR    3
+#define PAL_COLOR       4
+#define PAL_NOCOLOR     5
+
+/* Not too sure what this does yet */
+        /* Options for setting Field number */
+#define ODD_FIELD       0x1
+#define EVEN_FIELD      0x0
+#define ACTIVE_ONLY     0x2
+#define NON_ACTIVE      0x0
+
+/* Debug options */
+#define VFC_I2C_SEND 0
+#define VFC_I2C_RECV 1
+
+struct vfc_debug_inout
+{
+        unsigned long addr;
+        unsigned long ret;
+        unsigned long len;
+        unsigned char __user *buffer;
+};
+
+#endif /* _LINUX_VFC_IOCTLS_H_ */
diff --git a/arch/sparc/include/asm/vga.h b/arch/sparc/include/asm/vga.h
new file mode 100644
index 000000000000..c69d5b2ba19a
--- /dev/null
+++ b/arch/sparc/include/asm/vga.h
@@ -0,0 +1,33 @@
+/*
+ *      Access to VGA videoram
+ *
+ *      (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+
+#ifndef _LINUX_ASM_VGA_H_
+#define _LINUX_ASM_VGA_H_
+
+#include <asm/types.h>
+
+#define VT_BUF_HAVE_RW
+
+#undef scr_writew
+#undef scr_readw
+
+static inline void scr_writew(u16 val, u16 *addr)
+{
+        BUG_ON((long) addr >= 0);
+
+        *addr = val;
+}
+
+static inline u16 scr_readw(const u16 *addr)
+{
+        BUG_ON((long) addr >= 0);
+
+        return *addr;
+}
+
+#define VGA_MAP_MEM(x,s) (x)
+
+#endif
diff --git a/arch/sparc/include/asm/viking.h b/arch/sparc/include/asm/viking.h
new file mode 100644
index 000000000000..989930aeb093
--- /dev/null
+++ b/arch/sparc/include/asm/viking.h
@@ -0,0 +1,253 @@
+/*
+ * viking.h:  Defines specific to the GNU/Viking MBUS module.
+ *            This is SRMMU stuff.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_VIKING_H
+#define _SPARC_VIKING_H
+
+#include <asm/asi.h>
+#include <asm/mxcc.h>
+#include <asm/pgtsrmmu.h>
+
+/* Bits in the SRMMU control register for GNU/Viking modules.
+ *
+ * -----------------------------------------------------------
+ * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
+ * -----------------------------------------------------------
+ *  31     24 23-17 16 15 14 13 12 11  10  9  8  7  6-2  1  0
+ *
+ * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
+ *                            1 = Twalks are cacheable in E-cache
+ *
+ * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
+ * and never caches them internally (or so states the docs).  Therefore
+ * for machines lacking an E-cache (ie. in MBUS mode) this bit must
+ * remain cleared.
+ *
+ * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
+ *                            1 = Passthru physical accesses cacheable
+ *
+ * This indicates whether accesses are cacheable when no cachable bit
+ * is present in the pte when the processor is in boot-mode or the
+ * access does not need pte's for translation (ie. pass-thru ASI's).
+ * "Cachable" is only referring to E-cache (if present) and not the
+ * on chip split I/D caches of the GNU/Viking.
+ *
+ * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
+ *
+ * This enables snooping on the GNU/Viking bus.  This must be on
+ * for the hardware cache consistency mechanisms of the GNU/Viking
+ * to work at all.  On non-mxcc GNU/Viking modules the split I/D
+ * caches will snoop regardless of whether they are enabled, this
+ * takes care of the case where the I or D or both caches are turned
+ * off yet still contain valid data.  Note also that this bit does
+ * not affect GNU/Viking store-buffer snoops, those happen if the
+ * store-buffer is enabled no matter what.
+ *
+ * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
+ *
+ * This indicates whether the GNU/Viking is in boot-mode or not,
+ * if it is then all instruction fetch physical addresses are
+ * computed as 0xff0000000 + low 28 bits of requested address.
+ * GNU/Viking boot-mode does not affect data accesses.  Also,
+ * in boot mode instruction accesses bypass the split on chip I/D
+ * caches, they may be cached by the GNU/MXCC if present and enabled.
+ *
+ * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
+ *
+ * This indicated the GNU/Viking configuration present.  If in
+ * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache.  If it is
+ * not then the GNU/Viking is on a module VBUS connected directly
+ * to a GNU/MXCC cache controller.  The GNU/MXCC can be thus connected
+ * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
+ *
+ * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
+ *
+ * The GNU/Viking store buffer allows the chip to continue execution
+ * after a store even if the data cannot be placed in one of the
+ * caches during that cycle.  If disabled, all stores operations
+ * occur synchronously.
+ *
+ * IC: Instruction Cache -- 0 = off, 1 = on
+ * DC: Data Cache -- 0 = off, 1 = 0n
+ *
+ * These bits enable the on-cpu GNU/Viking split I/D caches.  Note,
+ * as mentioned above, these caches will snoop the bus in GNU/MBUS
+ * configurations even when disabled to avoid data corruption.
+ *
+ * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
+ * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
+ *
+ */
+
+#define VIKING_MMUENABLE    0x00000001
+#define VIKING_NOFAULT      0x00000002
+#define VIKING_PSO          0x00000080
+#define VIKING_DCENABLE     0x00000100   /* Enable data cache */
+#define VIKING_ICENABLE     0x00000200   /* Enable instruction cache */
+#define VIKING_SBENABLE     0x00000400   /* Enable store buffer */
+#define VIKING_MMODE        0x00000800   /* MBUS mode */
+#define VIKING_PCENABLE     0x00001000   /* Enable parity checking */
+#define VIKING_BMODE        0x00002000   
+#define VIKING_SPENABLE     0x00004000   /* Enable bus cache snooping */
+#define VIKING_ACENABLE     0x00008000   /* Enable alternate caching */
+#define VIKING_TCENABLE     0x00010000   /* Enable table-walks to be cached */
+#define VIKING_DPENABLE     0x00040000   /* Enable the data prefetcher */
+
+/*
+ * GNU/Viking Breakpoint Action Register fields.
+ */
+#define VIKING_ACTION_MIX   0x00001000   /* Enable multiple instructions */
+
+/*
+ * GNU/Viking Cache Tags.
+ */
+#define VIKING_PTAG_VALID   0x01000000   /* Cache block is valid */
+#define VIKING_PTAG_DIRTY   0x00010000   /* Block has been modified */
+#define VIKING_PTAG_SHARED  0x00000100   /* Shared with some other cache */
+
+#ifndef __ASSEMBLY__
+
+static inline void viking_flush_icache(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+                             : /* no outputs */
+                             : "i" (ASI_M_IC_FLCLEAR)
+                             : "memory");
+}
+
+static inline void viking_flush_dcache(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
+                             : /* no outputs */
+                             : "i" (ASI_M_DC_FLCLEAR)
+                             : "memory");
+}
+
+static inline void viking_unlock_icache(void)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
+                             : "memory");
+}
+
+static inline void viking_unlock_dcache(void)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
+                             : "memory");
+}
+
+static inline void viking_set_bpreg(unsigned long regval)
+{
+        __asm__ __volatile__("sta %0, [%%g0] %1\n\t"
+                             : /* no outputs */
+                             : "r" (regval), "i" (ASI_M_ACTION)
+                             : "memory");
+}
+
+static inline unsigned long viking_get_bpreg(void)
+{
+        unsigned long regval;
+
+        __asm__ __volatile__("lda [%%g0] %1, %0\n\t"
+                             : "=r" (regval)
+                             : "i" (ASI_M_ACTION));
+        return regval;
+}
+
+static inline void viking_get_dcache_ptag(int set, int block,
+                                              unsigned long *data)
+{
+        unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
+                             0x80000000;
+        unsigned long info, page;
+
+        __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
+                              "or %%g0, %%g2, %0\n\t"
+                              "or %%g0, %%g3, %1\n\t"
+                              : "=r" (info), "=r" (page)
+                              : "r" (ptag), "i" (ASI_M_DATAC_TAG)
+                              : "g2", "g3");
+        data[0] = info;
+        data[1] = page;
+}
+
+static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
+                                                   unsigned long *mxcc_cregp)
+{
+        unsigned long mreg = *mregp;
+        unsigned long mxcc_creg = *mxcc_cregp;
+
+        mreg &= ~(VIKING_PCENABLE);
+        mxcc_creg &= ~(MXCC_CTL_PARE);
+
+        __asm__ __volatile__ ("set 1f, %%g2\n\t"
+                              "andcc %%g2, 4, %%g0\n\t"
+                              "bne 2f\n\t"
+                              " nop\n"
+                              "1:\n\t"
+                              "sta %0, [%%g0] %3\n\t"
+                              "sta %1, [%2] %4\n\t"
+                              "b 1f\n\t"
+                              " nop\n\t"
+                              "nop\n"
+                              "2:\n\t"
+                              "sta %0, [%%g0] %3\n\t"
+                              "sta %1, [%2] %4\n"
+                              "1:\n\t"
+                              : /* no output */
+                              : "r" (mreg), "r" (mxcc_creg),
+                                "r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
+                                "i" (ASI_M_MXCC)
+                              : "g2", "memory", "cc");
+        *mregp = mreg;
+        *mxcc_cregp = mxcc_creg;
+}
+
+static inline unsigned long viking_hwprobe(unsigned long vaddr)
+{
+        unsigned long val;
+
+        vaddr &= PAGE_MASK;
+        /* Probe all MMU entries. */
+        __asm__ __volatile__("lda [%1] %2, %0\n\t"
+                             : "=r" (val)
+                             : "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
+        if (!val)
+                return 0;
+
+        /* Probe region. */
+        __asm__ __volatile__("lda [%1] %2, %0\n\t"
+                             : "=r" (val)
+                             : "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
+        if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
+                vaddr &= ~SRMMU_PGDIR_MASK;
+                vaddr >>= PAGE_SHIFT;
+                return val | (vaddr << 8);
+        }
+
+        /* Probe segment. */
+        __asm__ __volatile__("lda [%1] %2, %0\n\t"
+                             : "=r" (val)
+                             : "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
+        if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
+                vaddr &= ~SRMMU_REAL_PMD_MASK;
+                vaddr >>= PAGE_SHIFT;
+                return val | (vaddr << 8);
+        }
+
+        /* Probe page. */
+        __asm__ __volatile__("lda [%1] %2, %0\n\t"
+                             : "=r" (val)
+                             : "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
+        return val;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !(_SPARC_VIKING_H) */
diff --git a/arch/sparc/include/asm/vio.h b/arch/sparc/include/asm/vio.h
new file mode 100644
index 000000000000..d4de32f0f8af
--- /dev/null
+++ b/arch/sparc/include/asm/vio.h
@@ -0,0 +1,406 @@
+#ifndef _SPARC64_VIO_H
+#define _SPARC64_VIO_H
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/list.h>
+#include <linux/log2.h>
+
+#include <asm/ldc.h>
+#include <asm/mdesc.h>
+
+struct vio_msg_tag {
+        u8                      type;
+#define VIO_TYPE_CTRL           0x01
+#define VIO_TYPE_DATA           0x02
+#define VIO_TYPE_ERR            0x04
+
+        u8                      stype;
+#define VIO_SUBTYPE_INFO        0x01
+#define VIO_SUBTYPE_ACK         0x02
+#define VIO_SUBTYPE_NACK        0x04
+
+        u16                     stype_env;
+#define VIO_VER_INFO            0x0001
+#define VIO_ATTR_INFO           0x0002
+#define VIO_DRING_REG           0x0003
+#define VIO_DRING_UNREG         0x0004
+#define VIO_RDX                 0x0005
+#define VIO_PKT_DATA            0x0040
+#define VIO_DESC_DATA           0x0041
+#define VIO_DRING_DATA          0x0042
+#define VNET_MCAST_INFO         0x0101
+
+        u32             sid;
+};
+
+struct vio_rdx {
+        struct vio_msg_tag      tag;
+        u64                     resv[6];
+};
+
+struct vio_ver_info {
+        struct vio_msg_tag      tag;
+        u16                     major;
+        u16                     minor;
+        u8                      dev_class;
+#define VDEV_NETWORK            0x01
+#define VDEV_NETWORK_SWITCH     0x02
+#define VDEV_DISK               0x03
+#define VDEV_DISK_SERVER        0x04
+
+        u8                      resv1[3];
+        u64                     resv2[5];
+};
+
+struct vio_dring_register {
+        struct vio_msg_tag      tag;
+        u64                     dring_ident;
+        u32                     num_descr;
+        u32                     descr_size;
+        u16                     options;
+#define VIO_TX_DRING            0x0001
+#define VIO_RX_DRING            0x0002
+        u16                     resv;
+        u32                     num_cookies;
+        struct ldc_trans_cookie cookies[0];
+};
+
+struct vio_dring_unregister {
+        struct vio_msg_tag      tag;
+        u64                     dring_ident;
+        u64                     resv[5];
+};
+
+/* Data transfer modes */
+#define VIO_PKT_MODE            0x01 /* Packet based transfer   */
+#define VIO_DESC_MODE           0x02 /* In-band descriptors     */
+#define VIO_DRING_MODE          0x03 /* Descriptor rings        */
+
+struct vio_dring_data {
+        struct vio_msg_tag      tag;
+        u64                     seq;
+        u64                     dring_ident;
+        u32                     start_idx;
+        u32                     end_idx;
+        u8                      state;
+#define VIO_DRING_ACTIVE        0x01
+#define VIO_DRING_STOPPED       0x02
+
+        u8                      __pad1;
+        u16                     __pad2;
+        u32                     __pad3;
+        u64                     __par4[2];
+};
+
+struct vio_dring_hdr {
+        u8                      state;
+#define VIO_DESC_FREE           0x01
+#define VIO_DESC_READY          0x02
+#define VIO_DESC_ACCEPTED       0x03
+#define VIO_DESC_DONE           0x04
+        u8                      ack;
+#define VIO_ACK_ENABLE          0x01
+#define VIO_ACK_DISABLE         0x00
+
+        u16                     __pad1;
+        u32                     __pad2;
+};
+
+/* VIO disk specific structures and defines */
+struct vio_disk_attr_info {
+        struct vio_msg_tag      tag;
+        u8                      xfer_mode;
+        u8                      vdisk_type;
+#define VD_DISK_TYPE_SLICE      0x01 /* Slice in block device   */
+#define VD_DISK_TYPE_DISK       0x02 /* Entire block device     */
+        u16                     resv1;
+        u32                     vdisk_block_size;
+        u64                     operations;
+        u64                     vdisk_size;
+        u64                     max_xfer_size;
+        u64                     resv2[2];
+};
+
+struct vio_disk_desc {
+        struct vio_dring_hdr    hdr;
+        u64                     req_id;
+        u8                      operation;
+#define VD_OP_BREAD             0x01 /* Block read                      */
+#define VD_OP_BWRITE            0x02 /* Block write                     */
+#define VD_OP_FLUSH             0x03 /* Flush disk contents             */
+#define VD_OP_GET_WCE           0x04 /* Get write-cache status          */
+#define VD_OP_SET_WCE           0x05 /* Enable/disable write-cache      */
+#define VD_OP_GET_VTOC          0x06 /* Get VTOC                        */
+#define VD_OP_SET_VTOC          0x07 /* Set VTOC                        */
+#define VD_OP_GET_DISKGEOM      0x08 /* Get disk geometry               */
+#define VD_OP_SET_DISKGEOM      0x09 /* Set disk geometry               */
+#define VD_OP_SCSICMD           0x0a /* SCSI control command            */
+#define VD_OP_GET_DEVID         0x0b /* Get device ID                   */
+#define VD_OP_GET_EFI           0x0c /* Get EFI                         */
+#define VD_OP_SET_EFI           0x0d /* Set EFI                         */
+        u8                      slice;
+        u16                     resv1;
+        u32                     status;
+        u64                     offset;
+        u64                     size;
+        u32                     ncookies;
+        u32                     resv2;
+        struct ldc_trans_cookie cookies[0];
+};
+
+#define VIO_DISK_VNAME_LEN      8
+#define VIO_DISK_ALABEL_LEN     128
+#define VIO_DISK_NUM_PART       8
+
+struct vio_disk_vtoc {
+        u8                      volume_name[VIO_DISK_VNAME_LEN];
+        u16                     sector_size;
+        u16                     num_partitions;
+        u8                      ascii_label[VIO_DISK_ALABEL_LEN];
+        struct {
+                u16             id;
+                u16             perm_flags;
+                u32             resv;
+                u64             start_block;
+                u64             num_blocks;
+        } partitions[VIO_DISK_NUM_PART];
+};
+
+struct vio_disk_geom {
+        u16                     num_cyl; /* Num data cylinders          */
+        u16                     alt_cyl; /* Num alternate cylinders     */
+        u16                     beg_cyl; /* Cyl off of fixed head area  */
+        u16                     num_hd;  /* Num heads                   */
+        u16                     num_sec; /* Num sectors                 */
+        u16                     ifact;   /* Interleave factor           */
+        u16                     apc;     /* Alts per cylinder (SCSI)    */
+        u16                     rpm;     /* Revolutions per minute      */
+        u16                     phy_cyl; /* Num physical cylinders      */
+        u16                     wr_skip; /* Num sects to skip, writes   */
+        u16                     rd_skip; /* Num sects to skip, writes   */
+};
+
+struct vio_disk_devid {
+        u16                     resv;
+        u16                     type;
+        u32                     len;
+        char                    id[0];
+};
+
+struct vio_disk_efi {
+        u64                     lba;
+        u64                     len;
+        char                    data[0];
+};
+
+/* VIO net specific structures and defines */
+struct vio_net_attr_info {
+        struct vio_msg_tag      tag;
+        u8                      xfer_mode;
+        u8                      addr_type;
+#define VNET_ADDR_ETHERMAC      0x01
+        u16                     ack_freq;
+        u32                     resv1;
+        u64                     addr;
+        u64                     mtu;
+        u64                     resv2[3];
+};
+
+#define VNET_NUM_MCAST          7
+
+struct vio_net_mcast_info {
+        struct vio_msg_tag      tag;
+        u8                      set;
+        u8                      count;
+        u8                      mcast_addr[VNET_NUM_MCAST * 6];
+        u32                     resv;
+};
+
+struct vio_net_desc {
+        struct vio_dring_hdr    hdr;
+        u32                     size;
+        u32                     ncookies;
+        struct ldc_trans_cookie cookies[0];
+};
+
+#define VIO_MAX_RING_COOKIES    24
+
+struct vio_dring_state {
+        u64                     ident;
+        void                    *base;
+        u64                     snd_nxt;
+        u64                     rcv_nxt;
+        u32                     entry_size;
+        u32                     num_entries;
+        u32                     prod;
+        u32                     cons;
+        u32                     pending;
+        int                     ncookies;
+        struct ldc_trans_cookie cookies[VIO_MAX_RING_COOKIES];
+};
+
+static inline void *vio_dring_cur(struct vio_dring_state *dr)
+{
+        return dr->base + (dr->entry_size * dr->prod);
+}
+
+static inline void *vio_dring_entry(struct vio_dring_state *dr,
+                                    unsigned int index)
+{
+        return dr->base + (dr->entry_size * index);
+}
+
+static inline u32 vio_dring_avail(struct vio_dring_state *dr,
+                                  unsigned int ring_size)
+{
+        BUILD_BUG_ON(!is_power_of_2(ring_size));
+
+        return (dr->pending -
+                ((dr->prod - dr->cons) & (ring_size - 1)));
+}
+
+#define VIO_MAX_TYPE_LEN        32
+#define VIO_MAX_COMPAT_LEN      64
+
+struct vio_dev {
+        u64                     mp;
+        struct device_node      *dp;
+
+        char                    type[VIO_MAX_TYPE_LEN];
+        char                    compat[VIO_MAX_COMPAT_LEN];
+        int                     compat_len;
+
+        u64                     dev_no;
+
+        unsigned long           channel_id;
+
+        unsigned int            tx_irq;
+        unsigned int            rx_irq;
+
+        struct device           dev;
+};
+
+struct vio_driver {
+        struct list_head                node;
+        const struct vio_device_id      *id_table;
+        int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
+        int (*remove)(struct vio_dev *dev);
+        void (*shutdown)(struct vio_dev *dev);
+        unsigned long                   driver_data;
+        struct device_driver            driver;
+};
+
+struct vio_version {
+        u16             major;
+        u16             minor;
+};
+
+struct vio_driver_state;
+struct vio_driver_ops {
+        int     (*send_attr)(struct vio_driver_state *vio);
+        int     (*handle_attr)(struct vio_driver_state *vio, void *pkt);
+        void    (*handshake_complete)(struct vio_driver_state *vio);
+};
+
+struct vio_completion {
+        struct completion       com;
+        int                     err;
+        int                     waiting_for;
+};
+
+struct vio_driver_state {
+        /* Protects VIO handshake and, optionally, driver private state.  */
+        spinlock_t              lock;
+
+        struct ldc_channel      *lp;
+
+        u32                     _peer_sid;
+        u32                     _local_sid;
+        struct vio_dring_state  drings[2];
+#define VIO_DRIVER_TX_RING      0
+#define VIO_DRIVER_RX_RING      1
+
+        u8                      hs_state;
+#define VIO_HS_INVALID          0x00
+#define VIO_HS_GOTVERS          0x01
+#define VIO_HS_GOT_ATTR         0x04
+#define VIO_HS_SENT_DREG        0x08
+#define VIO_HS_SENT_RDX         0x10
+#define VIO_HS_GOT_RDX_ACK      0x20
+#define VIO_HS_GOT_RDX          0x40
+#define VIO_HS_SENT_RDX_ACK     0x80
+#define VIO_HS_COMPLETE         (VIO_HS_GOT_RDX_ACK | VIO_HS_SENT_RDX_ACK)
+
+        u8                      dev_class;
+
+        u8                      dr_state;
+#define VIO_DR_STATE_TXREG      0x01
+#define VIO_DR_STATE_RXREG      0x02
+#define VIO_DR_STATE_TXREQ      0x10
+#define VIO_DR_STATE_RXREQ      0x20
+
+        u8                      debug;
+#define VIO_DEBUG_HS            0x01
+#define VIO_DEBUG_DATA          0x02
+
+        void                    *desc_buf;
+        unsigned int            desc_buf_len;
+
+        struct vio_completion   *cmp;
+
+        struct vio_dev          *vdev;
+
+        struct timer_list       timer;
+
+        struct vio_version      ver;
+
+        struct vio_version      *ver_table;
+        int                     ver_table_entries;
+
+        char                    *name;
+
+        struct vio_driver_ops   *ops;
+};
+
+#define viodbg(TYPE, f, a...) \
+do {    if (vio->debug & VIO_DEBUG_##TYPE) \
+                printk(KERN_INFO "vio: ID[%lu] " f, \
+                       vio->vdev->channel_id, ## a); \
+} while (0)
+
+extern int vio_register_driver(struct vio_driver *drv);
+extern void vio_unregister_driver(struct vio_driver *drv);
+
+static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
+{
+        return container_of(drv, struct vio_driver, driver);
+}
+
+static inline struct vio_dev *to_vio_dev(struct device *dev)
+{
+        return container_of(dev, struct vio_dev, dev);
+}
+
+extern int vio_ldc_send(struct vio_driver_state *vio, void *data, int len);
+extern void vio_link_state_change(struct vio_driver_state *vio, int event);
+extern void vio_conn_reset(struct vio_driver_state *vio);
+extern int vio_control_pkt_engine(struct vio_driver_state *vio, void *pkt);
+extern int vio_validate_sid(struct vio_driver_state *vio,
+                            struct vio_msg_tag *tp);
+extern u32 vio_send_sid(struct vio_driver_state *vio);
+extern int vio_ldc_alloc(struct vio_driver_state *vio,
+                         struct ldc_channel_config *base_cfg, void *event_arg);
+extern void vio_ldc_free(struct vio_driver_state *vio);
+extern int vio_driver_init(struct vio_driver_state *vio, struct vio_dev *vdev,
+                           u8 dev_class, struct vio_version *ver_table,
+                           int ver_table_size, struct vio_driver_ops *ops,
+                           char *name);
+
+extern void vio_port_up(struct vio_driver_state *vio);
+
+#endif /* _SPARC64_VIO_H */
diff --git a/arch/sparc/include/asm/visasm.h b/arch/sparc/include/asm/visasm.h
new file mode 100644
index 000000000000..de797b9bf552
--- /dev/null
+++ b/arch/sparc/include/asm/visasm.h
@@ -0,0 +1,62 @@
+#ifndef _SPARC64_VISASM_H
+#define _SPARC64_VISASM_H
+
+/* visasm.h:  FPU saving macros for VIS routines
+ *
+ * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+#include <asm/pstate.h>
+#include <asm/ptrace.h>
+
+/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
+
+#define VISEntry                                        \
+        rd              %fprs, %o5;                     \
+        andcc           %o5, (FPRS_FEF|FPRS_DU), %g0;   \
+        be,pt           %icc, 297f;                     \
+         sethi          %hi(297f), %g7;                 \
+        sethi           %hi(VISenter), %g1;             \
+        jmpl            %g1 + %lo(VISenter), %g0;       \
+         or             %g7, %lo(297f), %g7;            \
+297:    wr              %g0, FPRS_FEF, %fprs;           \
+
+#define VISExit                                         \
+        wr              %g0, 0, %fprs;
+
+/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
+ * Must preserve %o5 between VISEntryHalf and VISExitHalf */
+
+#define VISEntryHalf                                    \
+        rd              %fprs, %o5;                     \
+        andcc           %o5, FPRS_FEF, %g0;             \
+        be,pt           %icc, 297f;                     \
+         sethi          %hi(298f), %g7;                 \
+        sethi           %hi(VISenterhalf), %g1;         \
+        jmpl            %g1 + %lo(VISenterhalf), %g0;   \
+         or             %g7, %lo(298f), %g7;            \
+        clr             %o5;                            \
+297:    wr              %o5, FPRS_FEF, %fprs;           \
+298:
+
+#define VISExitHalf                                     \
+        wr              %o5, 0, %fprs;
+
+#ifndef __ASSEMBLY__
+static inline void save_and_clear_fpu(void) {
+        __asm__ __volatile__ (
+"               rd %%fprs, %%o5\n"
+"               andcc %%o5, %0, %%g0\n"
+"               be,pt %%icc, 299f\n"
+"                sethi %%hi(298f), %%g7\n"
+"               sethi %%hi(VISenter), %%g1\n"
+"               jmpl %%g1 + %%lo(VISenter), %%g0\n"
+"                or %%g7, %%lo(298f), %%g7\n"
+"       298:    wr %%g0, 0, %%fprs\n"
+"       299:\n"
+"               " : : "i" (FPRS_FEF|FPRS_DU) :
+                "o5", "g1", "g2", "g3", "g7", "cc");
+}
+#endif
+
+#endif /* _SPARC64_ASI_H */
diff --git a/arch/sparc/include/asm/watchdog.h b/arch/sparc/include/asm/watchdog.h
new file mode 100644
index 000000000000..5baf2d3919cf
--- /dev/null
+++ b/arch/sparc/include/asm/watchdog.h
@@ -0,0 +1,31 @@
+/*
+ *
+ * watchdog - Driver interface for the hardware watchdog timers
+ * present on Sun Microsystems boardsets
+ *
+ * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
+ *
+ */
+
+#ifndef _SPARC64_WATCHDOG_H
+#define _SPARC64_WATCHDOG_H
+
+#include <linux/watchdog.h>
+
+/* Solaris compatibility ioctls--
+ * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
+ */
+#define WIOCSTART _IO (WATCHDOG_IOCTL_BASE, 10)         /* Start Timer          */
+#define WIOCSTOP  _IO (WATCHDOG_IOCTL_BASE, 11)         /* Stop Timer           */
+#define WIOCGSTAT _IOR(WATCHDOG_IOCTL_BASE, 12, int)/* Get Timer Status */
+
+/* Status flags from WIOCGSTAT ioctl
+ */
+#define WD_FREERUN      0x01    /* timer is running, interrupts disabled        */
+#define WD_EXPIRED      0x02    /* timer has expired                                            */
+#define WD_RUNNING      0x04    /* timer is running, interrupts enabled         */
+#define WD_STOPPED      0x08    /* timer has not been started                           */
+#define WD_SERVICED 0x10        /* timer interrupt was serviced                         */
+
+#endif /* ifndef _SPARC64_WATCHDOG_H */
+
diff --git a/arch/sparc/include/asm/winmacro.h b/arch/sparc/include/asm/winmacro.h
new file mode 100644
index 000000000000..5b0a06dc3bcb
--- /dev/null
+++ b/arch/sparc/include/asm/winmacro.h
@@ -0,0 +1,135 @@
+/*
+ * winmacro.h: Window loading-unloading macros.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_WINMACRO_H
+#define _SPARC_WINMACRO_H
+
+#include <asm/ptrace.h>
+
+/* Store the register window onto the 8-byte aligned area starting
+ * at %reg.  It might be %sp, it might not, we don't care.
+ */
+#define STORE_WINDOW(reg) \
+        std     %l0, [%reg + RW_L0]; \
+        std     %l2, [%reg + RW_L2]; \
+        std     %l4, [%reg + RW_L4]; \
+        std     %l6, [%reg + RW_L6]; \
+        std     %i0, [%reg + RW_I0]; \
+        std     %i2, [%reg + RW_I2]; \
+        std     %i4, [%reg + RW_I4]; \
+        std     %i6, [%reg + RW_I6];
+
+/* Load a register window from the area beginning at %reg. */
+#define LOAD_WINDOW(reg) \
+        ldd     [%reg + RW_L0], %l0; \
+        ldd     [%reg + RW_L2], %l2; \
+        ldd     [%reg + RW_L4], %l4; \
+        ldd     [%reg + RW_L6], %l6; \
+        ldd     [%reg + RW_I0], %i0; \
+        ldd     [%reg + RW_I2], %i2; \
+        ldd     [%reg + RW_I4], %i4; \
+        ldd     [%reg + RW_I6], %i6;
+
+/* Loading and storing struct pt_reg trap frames. */
+#define LOAD_PT_INS(base_reg) \
+        ldd     [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
+        ldd     [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
+        ldd     [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
+        ldd     [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
+
+#define LOAD_PT_GLOBALS(base_reg) \
+        ld      [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
+        ldd     [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
+        ldd     [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
+        ldd     [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
+
+#define LOAD_PT_YREG(base_reg, scratch) \
+        ld      [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \
+        wr      %scratch, 0x0, %y;
+
+#define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
+        ld      [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \
+        ld      [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \
+        ld      [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc;
+
+#define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
+        LOAD_PT_YREG(base_reg, scratch) \
+        LOAD_PT_INS(base_reg) \
+        LOAD_PT_GLOBALS(base_reg) \
+        LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
+
+#define STORE_PT_INS(base_reg) \
+        std     %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
+        std     %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \
+        std     %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \
+        std     %i6, [%base_reg + STACKFRAME_SZ + PT_I6];
+
+#define STORE_PT_GLOBALS(base_reg) \
+        st      %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \
+        std     %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \
+        std     %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
+        std     %g6, [%base_reg + STACKFRAME_SZ + PT_G6];
+
+#define STORE_PT_YREG(base_reg, scratch) \
+        rd      %y, %scratch; \
+        st      %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];
+
+#define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
+        st      %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \
+        st      %pt_pc,  [%base_reg + STACKFRAME_SZ + PT_PC]; \
+        st      %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC];
+
+#define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
+        STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
+        STORE_PT_GLOBALS(base_reg) \
+        STORE_PT_YREG(base_reg, g_scratch) \
+        STORE_PT_INS(base_reg)
+
+#define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \
+        ld       [%cur_reg + TI_W_SAVED], %scratch; \
+        sll      %scratch, 2, %scratch; \
+        add      %scratch, %cur_reg, %scratch; \
+        st       %sp, [%scratch + TI_RWIN_SPTRS]; \
+        sub      %scratch, %cur_reg, %scratch; \
+        sll      %scratch, 4, %scratch; \
+        add      %scratch, %cur_reg, %scratch; \
+        STORE_WINDOW(scratch + TI_REG_WINDOW); \
+        sub      %scratch, %cur_reg, %scratch; \
+        srl      %scratch, 6, %scratch; \
+        add      %scratch, 1, %scratch; \
+        st       %scratch, [%cur_reg + TI_W_SAVED];
+
+#ifdef CONFIG_SMP
+#define LOAD_CURRENT4M(dest_reg, idreg) \
+        rd       %tbr, %idreg; \
+        sethi    %hi(current_set), %dest_reg; \
+        srl      %idreg, 10, %idreg; \
+        or       %dest_reg, %lo(current_set), %dest_reg; \
+        and      %idreg, 0xc, %idreg; \
+        ld       [%idreg + %dest_reg], %dest_reg;
+
+#define LOAD_CURRENT4D(dest_reg, idreg) \
+        lda      [%g0] ASI_M_VIKING_TMP1, %idreg; \
+        sethi   %hi(C_LABEL(current_set)), %dest_reg; \
+        sll     %idreg, 2, %idreg; \
+        or      %dest_reg, %lo(C_LABEL(current_set)), %dest_reg; \
+        ld      [%idreg + %dest_reg], %dest_reg;
+
+/* Blackbox - take care with this... - check smp4m and smp4d before changing this. */
+#define LOAD_CURRENT(dest_reg, idreg)                                   \
+        sethi    %hi(___b_load_current), %idreg;                        \
+        sethi    %hi(current_set), %dest_reg;                   \
+        sethi    %hi(boot_cpu_id4), %idreg;                     \
+        or       %dest_reg, %lo(current_set), %dest_reg;        \
+        ldub     [%idreg + %lo(boot_cpu_id4)], %idreg;          \
+        ld       [%idreg + %dest_reg], %dest_reg;
+#else
+#define LOAD_CURRENT(dest_reg, idreg) \
+        sethi    %hi(current_set), %idreg; \
+        ld       [%idreg + %lo(current_set)], %dest_reg;
+#endif
+
+#endif /* !(_SPARC_WINMACRO_H) */
diff --git a/arch/sparc/include/asm/xor.h b/arch/sparc/include/asm/xor.h
new file mode 100644
index 000000000000..8ed591c7db2d
--- /dev/null
+++ b/arch/sparc/include/asm/xor.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_XOR_H
+#define ___ASM_SPARC_XOR_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/xor_64.h>
+#else
+#include <asm/xor_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/xor_32.h b/arch/sparc/include/asm/xor_32.h
new file mode 100644
index 000000000000..44bfa0787f3f
--- /dev/null
+++ b/arch/sparc/include/asm/xor_32.h
@@ -0,0 +1,269 @@
+/*
+ * include/asm/xor.h
+ *
+ * Optimized RAID-5 checksumming functions for 32-bit Sparc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * (for example /usr/src/linux/COPYING); if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * High speed xor_block operation for RAID4/5 utilizing the
+ * ldd/std SPARC instructions.
+ *
+ * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
+ */
+
+static void
+sparc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
+{
+        int lines = bytes / (sizeof (long)) / 8;
+
+        do {
+                __asm__ __volatile__(
+                  "ldd [%0 + 0x00], %%g2\n\t"
+                  "ldd [%0 + 0x08], %%g4\n\t"
+                  "ldd [%0 + 0x10], %%o0\n\t"
+                  "ldd [%0 + 0x18], %%o2\n\t"
+                  "ldd [%1 + 0x00], %%o4\n\t"
+                  "ldd [%1 + 0x08], %%l0\n\t"
+                  "ldd [%1 + 0x10], %%l2\n\t"
+                  "ldd [%1 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "std %%g2, [%0 + 0x00]\n\t"
+                  "std %%g4, [%0 + 0x08]\n\t"
+                  "std %%o0, [%0 + 0x10]\n\t"
+                  "std %%o2, [%0 + 0x18]\n"
+                :
+                : "r" (p1), "r" (p2)
+                : "g2", "g3", "g4", "g5",
+                  "o0", "o1", "o2", "o3", "o4", "o5",
+                  "l0", "l1", "l2", "l3", "l4", "l5");
+                p1 += 8;
+                p2 += 8;
+        } while (--lines > 0);
+}
+
+static void
+sparc_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+        unsigned long *p3)
+{
+        int lines = bytes / (sizeof (long)) / 8;
+
+        do {
+                __asm__ __volatile__(
+                  "ldd [%0 + 0x00], %%g2\n\t"
+                  "ldd [%0 + 0x08], %%g4\n\t"
+                  "ldd [%0 + 0x10], %%o0\n\t"
+                  "ldd [%0 + 0x18], %%o2\n\t"
+                  "ldd [%1 + 0x00], %%o4\n\t"
+                  "ldd [%1 + 0x08], %%l0\n\t"
+                  "ldd [%1 + 0x10], %%l2\n\t"
+                  "ldd [%1 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "ldd [%2 + 0x00], %%o4\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "ldd [%2 + 0x08], %%l0\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "ldd [%2 + 0x10], %%l2\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "ldd [%2 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "std %%g2, [%0 + 0x00]\n\t"
+                  "std %%g4, [%0 + 0x08]\n\t"
+                  "std %%o0, [%0 + 0x10]\n\t"
+                  "std %%o2, [%0 + 0x18]\n"
+                :
+                : "r" (p1), "r" (p2), "r" (p3)
+                : "g2", "g3", "g4", "g5",
+                  "o0", "o1", "o2", "o3", "o4", "o5",
+                  "l0", "l1", "l2", "l3", "l4", "l5");
+                p1 += 8;
+                p2 += 8;
+                p3 += 8;
+        } while (--lines > 0);
+}
+
+static void
+sparc_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+        unsigned long *p3, unsigned long *p4)
+{
+        int lines = bytes / (sizeof (long)) / 8;
+
+        do {
+                __asm__ __volatile__(
+                  "ldd [%0 + 0x00], %%g2\n\t"
+                  "ldd [%0 + 0x08], %%g4\n\t"
+                  "ldd [%0 + 0x10], %%o0\n\t"
+                  "ldd [%0 + 0x18], %%o2\n\t"
+                  "ldd [%1 + 0x00], %%o4\n\t"
+                  "ldd [%1 + 0x08], %%l0\n\t"
+                  "ldd [%1 + 0x10], %%l2\n\t"
+                  "ldd [%1 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "ldd [%2 + 0x00], %%o4\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "ldd [%2 + 0x08], %%l0\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "ldd [%2 + 0x10], %%l2\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "ldd [%2 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "ldd [%3 + 0x00], %%o4\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "ldd [%3 + 0x08], %%l0\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "ldd [%3 + 0x10], %%l2\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "ldd [%3 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "std %%g2, [%0 + 0x00]\n\t"
+                  "std %%g4, [%0 + 0x08]\n\t"
+                  "std %%o0, [%0 + 0x10]\n\t"
+                  "std %%o2, [%0 + 0x18]\n"
+                :
+                : "r" (p1), "r" (p2), "r" (p3), "r" (p4)
+                : "g2", "g3", "g4", "g5",
+                  "o0", "o1", "o2", "o3", "o4", "o5",
+                  "l0", "l1", "l2", "l3", "l4", "l5");
+                p1 += 8;
+                p2 += 8;
+                p3 += 8;
+                p4 += 8;
+        } while (--lines > 0);
+}
+
+static void
+sparc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+        unsigned long *p3, unsigned long *p4, unsigned long *p5)
+{
+        int lines = bytes / (sizeof (long)) / 8;
+
+        do {
+                __asm__ __volatile__(
+                  "ldd [%0 + 0x00], %%g2\n\t"
+                  "ldd [%0 + 0x08], %%g4\n\t"
+                  "ldd [%0 + 0x10], %%o0\n\t"
+                  "ldd [%0 + 0x18], %%o2\n\t"
+                  "ldd [%1 + 0x00], %%o4\n\t"
+                  "ldd [%1 + 0x08], %%l0\n\t"
+                  "ldd [%1 + 0x10], %%l2\n\t"
+                  "ldd [%1 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "ldd [%2 + 0x00], %%o4\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "ldd [%2 + 0x08], %%l0\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "ldd [%2 + 0x10], %%l2\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "ldd [%2 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "ldd [%3 + 0x00], %%o4\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "ldd [%3 + 0x08], %%l0\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "ldd [%3 + 0x10], %%l2\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "ldd [%3 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "ldd [%4 + 0x00], %%o4\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "ldd [%4 + 0x08], %%l0\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "ldd [%4 + 0x10], %%l2\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "ldd [%4 + 0x18], %%l4\n\t"
+                  "xor %%g2, %%o4, %%g2\n\t"
+                  "xor %%g3, %%o5, %%g3\n\t"
+                  "xor %%g4, %%l0, %%g4\n\t"
+                  "xor %%g5, %%l1, %%g5\n\t"
+                  "xor %%o0, %%l2, %%o0\n\t"
+                  "xor %%o1, %%l3, %%o1\n\t"
+                  "xor %%o2, %%l4, %%o2\n\t"
+                  "xor %%o3, %%l5, %%o3\n\t"
+                  "std %%g2, [%0 + 0x00]\n\t"
+                  "std %%g4, [%0 + 0x08]\n\t"
+                  "std %%o0, [%0 + 0x10]\n\t"
+                  "std %%o2, [%0 + 0x18]\n"
+                :
+                : "r" (p1), "r" (p2), "r" (p3), "r" (p4), "r" (p5)
+                : "g2", "g3", "g4", "g5",
+                  "o0", "o1", "o2", "o3", "o4", "o5",
+                  "l0", "l1", "l2", "l3", "l4", "l5");
+                p1 += 8;
+                p2 += 8;
+                p3 += 8;
+                p4 += 8;
+                p5 += 8;
+        } while (--lines > 0);
+}
+
+static struct xor_block_template xor_block_SPARC = {
+        .name   = "SPARC",
+        .do_2   = sparc_2,
+        .do_3   = sparc_3,
+        .do_4   = sparc_4,
+        .do_5   = sparc_5,
+};
+
+/* For grins, also test the generic routines.  */
+#include <asm-generic/xor.h>
+
+#undef XOR_TRY_TEMPLATES
+#define XOR_TRY_TEMPLATES                               \
+        do {                                            \
+                xor_speed(&xor_block_8regs);            \
+                xor_speed(&xor_block_32regs);           \
+                xor_speed(&xor_block_SPARC);            \
+        } while (0)
diff --git a/arch/sparc/include/asm/xor_64.h b/arch/sparc/include/asm/xor_64.h
new file mode 100644
index 000000000000..bee4bf4be3af
--- /dev/null
+++ b/arch/sparc/include/asm/xor_64.h
@@ -0,0 +1,70 @@
+/*
+ * include/asm/xor.h
+ *
+ * High speed xor_block operation for RAID4/5 utilizing the
+ * UltraSparc Visual Instruction Set and Niagara block-init
+ * twin-load instructions.
+ *
+ * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
+ * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * (for example /usr/src/linux/COPYING); if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/spitfire.h>
+
+extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
+extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
+                      unsigned long *);
+extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *,
+                      unsigned long *, unsigned long *);
+extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *,
+                      unsigned long *, unsigned long *, unsigned long *);
+
+/* XXX Ugh, write cheetah versions... -DaveM */
+
+static struct xor_block_template xor_block_VIS = {
+        .name   = "VIS",
+        .do_2   = xor_vis_2,
+        .do_3   = xor_vis_3,
+        .do_4   = xor_vis_4,
+        .do_5   = xor_vis_5,
+};
+
+extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *);
+extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *,
+                          unsigned long *);
+extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *,
+                          unsigned long *, unsigned long *);
+extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *,
+                          unsigned long *, unsigned long *, unsigned long *);
+
+static struct xor_block_template xor_block_niagara = {
+        .name   = "Niagara",
+        .do_2   = xor_niagara_2,
+        .do_3   = xor_niagara_3,
+        .do_4   = xor_niagara_4,
+        .do_5   = xor_niagara_5,
+};
+
+#undef XOR_TRY_TEMPLATES
+#define XOR_TRY_TEMPLATES                               \
+        do {                                            \
+                xor_speed(&xor_block_VIS);              \
+                xor_speed(&xor_block_niagara);          \
+        } while (0)
+
+/* For VIS for everything except Niagara.  */
+#define XOR_SELECT_TEMPLATE(FASTEST) \
+        ((tlb_type == hypervisor && \
+          (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
+           sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \
+         &xor_block_niagara : \
+         &xor_block_VIS)
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 2f96256dc515..e8cdf715a546 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -1196,8 +1196,9 @@ sys_rt_sigreturn:
         be      1f
          nop
 
+        add     %sp, STACKFRAME_SZ, %o0
         call    syscall_trace
-         nop
+         mov    1, %o1
 
 1:
         /* We are returning to a signal handler. */
@@ -1287,8 +1288,12 @@ linux_fast_syscall:
          mov    %i3, %o3
 
 linux_syscall_trace:
+        add     %sp, STACKFRAME_SZ, %o0
         call    syscall_trace
-         nop
+         mov    0, %o1
+        cmp     %o0, 0
+        bne     3f
+         mov    -ENOSYS, %o0
         mov     %i0, %o0
         mov     %i1, %o1
         mov     %i2, %o2
@@ -1337,6 +1342,7 @@ syscall_is_too_hard:
         call    %l7
          mov    %i5, %o5
 
+3:
         st      %o0, [%sp + STACKFRAME_SZ + PT_I0]
 
 ret_sys_call:
@@ -1374,6 +1380,8 @@ ret_sys_call:
          st     %l2, [%sp + STACKFRAME_SZ + PT_NPC]
 
 linux_syscall_trace2:
+        add     %sp, STACKFRAME_SZ, %o0
+        mov     1, %o1
         call    syscall_trace
          add    %l1, 0x4, %l2                   /* npc = npc+4 */
         st      %l1, [%sp + STACKFRAME_SZ + PT_PC]
diff --git a/arch/sparc/kernel/ptrace.c b/arch/sparc/kernel/ptrace.c
index 81f3b929743f..20699c701412 100644
--- a/arch/sparc/kernel/ptrace.c
+++ b/arch/sparc/kernel/ptrace.c
@@ -21,6 +21,7 @@
 #include <linux/signal.h>
 #include <linux/regset.h>
 #include <linux/elf.h>
+#include <linux/tracehook.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -450,21 +451,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         return ret;
 }
 
-asmlinkage void syscall_trace(void)
+asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p)
 {
-        if (!test_thread_flag(TIF_SYSCALL_TRACE))
-                return;
-        if (!(current->ptrace & PT_PTRACED))
-                return;
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                 ? 0x80 : 0));
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig (current->exit_code, current, 1);
-                current->exit_code = 0;
+        int ret = 0;
+
+        if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+                if (syscall_exit_p)
+                        tracehook_report_syscall_exit(regs, 0);
+                else
+                        ret = tracehook_report_syscall_entry(regs);
         }
+
+        return ret;
 }
diff --git a/arch/sparc/kernel/rtrap.S b/arch/sparc/kernel/rtrap.S
index 891f460b7b96..4da2e1f66290 100644
--- a/arch/sparc/kernel/rtrap.S
+++ b/arch/sparc/kernel/rtrap.S
@@ -69,12 +69,13 @@ ret_trap_lockless_ipi:
 
         ld      [%curptr + TI_FLAGS], %g2
 signal_p:
-        andcc   %g2, (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK), %g0
+        andcc   %g2, _TIF_DO_NOTIFY_RESUME_MASK, %g0
         bz,a    ret_trap_continue
          ld     [%sp + STACKFRAME_SZ + PT_PSR], %t_psr
 
+        mov     %g2, %o2
         mov     %l5, %o1
-        call    do_signal
+        call    do_notify_resume
          add    %sp, STACKFRAME_SZ, %o0 ! pt_regs ptr
 
         /* Fall through. */
diff --git a/arch/sparc/kernel/signal.c b/arch/sparc/kernel/signal.c
index 3fd1df9f9ba7..c94f91c8b6e0 100644
--- a/arch/sparc/kernel/signal.c
+++ b/arch/sparc/kernel/signal.c
@@ -18,6 +18,7 @@
 #include <linux/smp.h>
 #include <linux/binfmts.h>      /* do_coredum */
 #include <linux/bitops.h>
+#include <linux/tracehook.h>
 
 #include <asm/uaccess.h>
 #include <asm/ptrace.h>
@@ -513,7 +514,7 @@ static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs,
  * want to handle. Thus you cannot kill init even with a SIGKILL even by
  * mistake.
  */
-asmlinkage void do_signal(struct pt_regs * regs, unsigned long orig_i0)
+static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
 {
         struct k_sigaction ka;
         int restart_syscall;
@@ -552,6 +553,8 @@ asmlinkage void do_signal(struct pt_regs * regs, unsigned long orig_i0)
                  */
                 if (test_thread_flag(TIF_RESTORE_SIGMASK))
                         clear_thread_flag(TIF_RESTORE_SIGMASK);
+
+                tracehook_signal_handler(signr, &info, &ka, regs, 0);
                 return;
         }
         if (restart_syscall &&
@@ -579,6 +582,17 @@ asmlinkage void do_signal(struct pt_regs * regs, unsigned long orig_i0)
         }
 }
 
+void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0,
+                      unsigned long thread_info_flags)
+{
+        if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
+                do_signal(regs, orig_i0);
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+        }
+}
+
 asmlinkage int
 do_sys_sigstack(struct sigstack __user *ssptr, struct sigstack __user *ossptr,
                 unsigned long sp)
diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig
index 7c88263256af..923a98959fa7 100644
--- a/arch/sparc64/Kconfig
+++ b/arch/sparc64/Kconfig
@@ -17,6 +17,7 @@ config SPARC64
         select HAVE_LMB
         select HAVE_ARCH_KGDB
         select USE_GENERIC_SMP_HELPERS if SMP
+        select HAVE_ARCH_TRACEHOOK
 
 config GENERIC_TIME
         bool
diff --git a/arch/sparc64/kernel/compat_audit.c b/arch/sparc64/kernel/compat_audit.c
index c1979482aa92..c831b0a4e660 100644
--- a/arch/sparc64/kernel/compat_audit.c
+++ b/arch/sparc64/kernel/compat_audit.c
@@ -1,4 +1,4 @@
-#include <asm-sparc/unistd.h>
+#include <asm/unistd_32.h>
 
 unsigned sparc32_dir_class[] = {
 #include <asm-generic/audit_dir_write.h>
diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h
index 32fbab620852..fc294a292899 100644
--- a/arch/sparc64/kernel/entry.h
+++ b/arch/sparc64/kernel/entry.h
@@ -22,8 +22,7 @@ extern void do_notify_resume(struct pt_regs *regs,
                              unsigned long orig_i0,
                              unsigned long thread_info_flags);
 
-extern asmlinkage void syscall_trace(struct pt_regs *regs,
-                                     int syscall_exit_p);
+extern asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p);
 
 extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
 
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index c481673d249c..ba43d85e8dde 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -915,12 +915,18 @@ static void __init sun4v_init_mondo_queues(void)
                 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
                                tb->nonresum_qmask);
+        }
+}
+
+static void __init init_send_mondo_info(void)
+{
+        int cpu;
+
+        for_each_possible_cpu(cpu) {
+                struct trap_per_cpu *tb = &trap_block[cpu];
 
                 init_cpu_send_mondo_info(tb);
         }
-
-        /* Load up the boot cpu's entries.  */
-        sun4v_register_mondo_queues(hard_smp_processor_id());
 }
 
 static struct irqaction timer_irq_action = {
@@ -949,6 +955,13 @@ void __init init_IRQ(void)
         if (tlb_type == hypervisor)
                 sun4v_init_mondo_queues();
 
+        init_send_mondo_info();
+
+        if (tlb_type == hypervisor) {
+                /* Load up the boot cpu's entries.  */
+                sun4v_register_mondo_queues(hard_smp_processor_id());
+        }
+
         /* We need to clear any IRQ's pending in the soft interrupt
          * registers, a spurious one could be left around from the
          * PROM timer which we just disabled.
diff --git a/arch/sparc64/kernel/of_device.c b/arch/sparc64/kernel/of_device.c
index 4fd48ab7dda4..f8b50cbf4bf7 100644
--- a/arch/sparc64/kernel/of_device.c
+++ b/arch/sparc64/kernel/of_device.c
@@ -56,9 +56,6 @@ struct of_device *of_find_device_by_node(struct device_node *dp)
 EXPORT_SYMBOL(of_find_device_by_node);
 
 #ifdef CONFIG_PCI
-struct bus_type isa_bus_type;
-EXPORT_SYMBOL(isa_bus_type);
-
 struct bus_type ebus_bus_type;
 EXPORT_SYMBOL(ebus_bus_type);
 #endif
@@ -842,8 +839,6 @@ static int __init of_bus_driver_init(void)
         err = of_bus_type_init(&of_platform_bus_type, "of");
 #ifdef CONFIG_PCI
         if (!err)
-                err = of_bus_type_init(&isa_bus_type, "isa");
-        if (!err)
                 err = of_bus_type_init(&ebus_bus_type, "ebus");
 #endif
 #ifdef CONFIG_SBUS
diff --git a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
index 8a9cd3e165b9..7f5debdc5fed 100644
--- a/arch/sparc64/kernel/process.c
+++ b/arch/sparc64/kernel/process.c
@@ -52,8 +52,6 @@
 #include <asm/irq_regs.h>
 #include <asm/smp.h>
 
-/* #define VERBOSE_SHOWREGS */
-
 static void sparc64_yield(int cpu)
 {
         if (tlb_type != hypervisor)
@@ -213,22 +211,8 @@ static void show_regwindow(struct pt_regs *regs)
                 printk("I7: <%pS>\n", (void *) rwk->ins[7]);
 }
 
-#ifdef CONFIG_SMP
-static DEFINE_SPINLOCK(regdump_lock);
-#endif
-
-void __show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
-#ifdef CONFIG_SMP
-        unsigned long flags;
-
-        /* Protect against xcall ipis which might lead to livelock on the lock */
-        __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
-                             "wrpr      %0, %1, %%pstate"
-                             : "=r" (flags)
-                             : "i" (PSTATE_IE));
-        spin_lock(&regdump_lock);
-#endif
         printk("TSTATE: %016lx TPC: %016lx TNPC: %016lx Y: %08x    %s\n", regs->tstate,
                regs->tpc, regs->tnpc, regs->y, print_tainted());
         printk("TPC: <%pS>\n", (void *) regs->tpc);
@@ -246,64 +230,24 @@ void __show_regs(struct pt_regs * regs)
                regs->u_regs[15]);
         printk("RPC: <%pS>\n", (void *) regs->u_regs[15]);
         show_regwindow(regs);
-#ifdef CONFIG_SMP
-        spin_unlock(&regdump_lock);
-        __asm__ __volatile__("wrpr      %0, 0, %%pstate"
-                             : : "r" (flags));
-#endif
 }
 
-#ifdef VERBOSE_SHOWREGS
-static void idump_from_user (unsigned int *pc)
-{
-        int i;
-        int code;
-        
-        if((((unsigned long) pc) & 3))
-                return;
-        
-        pc -= 3;
-        for(i = -3; i < 6; i++) {
-                get_user(code, pc);
-                printk("%c%08x%c",i?' ':'<',code,i?' ':'>');
-                pc++;
-        }
-        printk("\n");
-}
-#endif
+struct global_reg_snapshot global_reg_snapshot[NR_CPUS];
+static DEFINE_SPINLOCK(global_reg_snapshot_lock);
 
-void show_regs(struct pt_regs *regs)
+static bool kstack_valid(struct thread_info *tp, struct reg_window *rw)
 {
-#ifdef VERBOSE_SHOWREGS
-        extern long etrap, etraptl1;
-#endif
-        __show_regs(regs);
-#if 0
-#ifdef CONFIG_SMP
-        {
-                extern void smp_report_regs(void);
+        unsigned long thread_base, fp;
 
-                smp_report_regs();
-        }
-#endif
-#endif
+        thread_base = (unsigned long) tp;
+        fp = (unsigned long) rw;
 
-#ifdef VERBOSE_SHOWREGS 
-        if (regs->tpc >= &etrap && regs->tpc < &etraptl1 &&
-            regs->u_regs[14] >= (long)current - PAGE_SIZE &&
-            regs->u_regs[14] < (long)current + 6 * PAGE_SIZE) {
-                printk ("*********parent**********\n");
-                __show_regs((struct pt_regs *)(regs->u_regs[14] + PTREGS_OFF));
-                idump_from_user(((struct pt_regs *)(regs->u_regs[14] + PTREGS_OFF))->tpc);
-                printk ("*********endpar**********\n");
-        }
-#endif
+        if (fp < (thread_base + sizeof(struct thread_info)) ||
+            fp >= (thread_base + THREAD_SIZE))
+                return false;
+        return true;
 }
 
-#ifdef CONFIG_MAGIC_SYSRQ
-struct global_reg_snapshot global_reg_snapshot[NR_CPUS];
-static DEFINE_SPINLOCK(global_reg_snapshot_lock);
-
 static void __global_reg_self(struct thread_info *tp, struct pt_regs *regs,
                               int this_cpu)
 {
@@ -315,14 +259,22 @@ static void __global_reg_self(struct thread_info *tp, struct pt_regs *regs,
         global_reg_snapshot[this_cpu].o7 = regs->u_regs[UREG_I7];
 
         if (regs->tstate & TSTATE_PRIV) {
+                struct thread_info *tp = current_thread_info();
                 struct reg_window *rw;
 
                 rw = (struct reg_window *)
                         (regs->u_regs[UREG_FP] + STACK_BIAS);
-                global_reg_snapshot[this_cpu].i7 = rw->ins[6];
-        } else
+                if (kstack_valid(tp, rw)) {
+                        global_reg_snapshot[this_cpu].i7 = rw->ins[7];
+                        rw = (struct reg_window *)
+                                (rw->ins[6] + STACK_BIAS);
+                        if (kstack_valid(tp, rw))
+                                global_reg_snapshot[this_cpu].rpc = rw->ins[7];
+                }
+        } else {
                 global_reg_snapshot[this_cpu].i7 = 0;
-
+                global_reg_snapshot[this_cpu].rpc = 0;
+        }
         global_reg_snapshot[this_cpu].thread = tp;
 }
 
@@ -341,7 +293,7 @@ static void __global_reg_poll(struct global_reg_snapshot *gp)
         }
 }
 
-static void sysrq_handle_globreg(int key, struct tty_struct *tty)
+void __trigger_all_cpu_backtrace(void)
 {
         struct thread_info *tp = current_thread_info();
         struct pt_regs *regs = get_irq_regs();
@@ -375,13 +327,14 @@ static void sysrq_handle_globreg(int key, struct tty_struct *tty)
                        ((tp && tp->task) ? tp->task->pid : -1));
 
                 if (gp->tstate & TSTATE_PRIV) {
-                        printk("             TPC[%pS] O7[%pS] I7[%pS]\n",
+                        printk("             TPC[%pS] O7[%pS] I7[%pS] RPC[%pS]\n",
                                (void *) gp->tpc,
                                (void *) gp->o7,
-                               (void *) gp->i7);
+                               (void *) gp->i7,
+                               (void *) gp->rpc);
                 } else {
-                        printk("             TPC[%lx] O7[%lx] I7[%lx]\n",
-                               gp->tpc, gp->o7, gp->i7);
+                        printk("             TPC[%lx] O7[%lx] I7[%lx] RPC[%lx]\n",
+                               gp->tpc, gp->o7, gp->i7, gp->rpc);
                 }
         }
 
@@ -390,6 +343,13 @@ static void sysrq_handle_globreg(int key, struct tty_struct *tty)
         spin_unlock_irqrestore(&global_reg_snapshot_lock, flags);
 }
 
+#ifdef CONFIG_MAGIC_SYSRQ
+
+static void sysrq_handle_globreg(int key, struct tty_struct *tty)
+{
+        __trigger_all_cpu_backtrace();
+}
+
 static struct sysrq_key_op sparc_globalreg_op = {
         .handler        = sysrq_handle_globreg,
         .help_msg       = "Globalregs",
diff --git a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c
index f6c9fc92921d..bd578cc4856d 100644
--- a/arch/sparc64/kernel/ptrace.c
+++ b/arch/sparc64/kernel/ptrace.c
@@ -23,6 +23,7 @@
 #include <linux/audit.h>
 #include <linux/signal.h>
 #include <linux/regset.h>
+#include <linux/tracehook.h>
 #include <linux/compat.h>
 #include <linux/elf.h>
 
@@ -1049,8 +1050,10 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         return ret;
 }
 
-asmlinkage void syscall_trace(struct pt_regs *regs, int syscall_exit_p)
+asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p)
 {
+        int ret = 0;
+
         /* do the secure computing check first */
         secure_computing(regs->u_regs[UREG_G1]);
 
@@ -1064,27 +1067,14 @@ asmlinkage void syscall_trace(struct pt_regs *regs, int syscall_exit_p)
                 audit_syscall_exit(result, regs->u_regs[UREG_I0]);
         }
 
-        if (!(current->ptrace & PT_PTRACED))
-                goto out;
-
-        if (!test_thread_flag(TIF_SYSCALL_TRACE))
-                goto out;
-
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                 ? 0x80 : 0));
-
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
+        if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+                if (syscall_exit_p)
+                        tracehook_report_syscall_exit(regs, 0);
+                else
+                        ret = tracehook_report_syscall_entry(regs);
         }
 
-out:
-        if (unlikely(current->audit_context) && !syscall_exit_p)
+        if (unlikely(current->audit_context) && !syscall_exit_p && !ret)
                 audit_syscall_entry((test_thread_flag(TIF_32BIT) ?
                                      AUDIT_ARCH_SPARC :
                                      AUDIT_ARCH_SPARC64),
@@ -1093,4 +1083,6 @@ out:
                                     regs->u_regs[UREG_I1],
                                     regs->u_regs[UREG_I2],
                                     regs->u_regs[UREG_I3]);
+
+        return ret;
 }
diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index c6fc695fe1fe..97a993c1f7f3 100644
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -46,7 +46,7 @@ __handle_user_windows:
                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
                 ldx                     [%g6 + TI_FLAGS], %l0
 
-1:              andcc                   %l0, _TIF_SIGPENDING, %g0
+1:              andcc                   %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
                 be,pt                   %xcc, __handle_user_windows_continue
                  nop
                 mov                     %l5, %o1
@@ -86,7 +86,7 @@ __handle_perfctrs:
                  wrpr                   %g0, RTRAP_PSTATE, %pstate
                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
                 ldx                     [%g6 + TI_FLAGS], %l0
-1:              andcc                   %l0, _TIF_SIGPENDING, %g0
+1:              andcc                   %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
 
                 be,pt                   %xcc, __handle_perfctrs_continue
                  sethi                  %hi(TSTATE_PEF), %o0
@@ -195,7 +195,7 @@ __handle_preemption_continue:
                  andcc                  %l1, %o0, %g0
                 andcc                   %l0, _TIF_NEED_RESCHED, %g0
                 bne,pn                  %xcc, __handle_preemption
-                 andcc                  %l0, _TIF_SIGPENDING, %g0
+                 andcc                  %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
                 bne,pn                  %xcc, __handle_signal
 __handle_signal_continue:
                  ldub                   [%g6 + TI_WSAVED], %o2
diff --git a/arch/sparc64/kernel/signal.c b/arch/sparc64/kernel/signal.c
index 9667e96fd513..ec82d76dc6f2 100644
--- a/arch/sparc64/kernel/signal.c
+++ b/arch/sparc64/kernel/signal.c
@@ -2,7 +2,7 @@
  *  arch/sparc64/kernel/signal.c
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
- *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ *  Copyright (C) 1995, 2008 David S. Miller (davem@davemloft.net)
  *  Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
  *  Copyright (C) 1997 Eddie C. Dost   (ecd@skynet.be)
  *  Copyright (C) 1997,1998 Jakub Jelinek   (jj@sunsite.mff.cuni.cz)
@@ -17,6 +17,7 @@
 #include <linux/errno.h>
 #include <linux/wait.h>
 #include <linux/ptrace.h>
+#include <linux/tracehook.h>
 #include <linux/unistd.h>
 #include <linux/mm.h>
 #include <linux/tty.h>
@@ -89,7 +90,9 @@ asmlinkage void sparc64_set_context(struct pt_regs *regs)
         err |= __get_user(regs->u_regs[UREG_G4], (&(*grp)[MC_G4]));
         err |= __get_user(regs->u_regs[UREG_G5], (&(*grp)[MC_G5]));
         err |= __get_user(regs->u_regs[UREG_G6], (&(*grp)[MC_G6]));
-        err |= __get_user(regs->u_regs[UREG_G7], (&(*grp)[MC_G7]));
+
+        /* Skip %g7 as that's the thread register in userspace.  */
+
         err |= __get_user(regs->u_regs[UREG_I0], (&(*grp)[MC_O0]));
         err |= __get_user(regs->u_regs[UREG_I1], (&(*grp)[MC_O1]));
         err |= __get_user(regs->u_regs[UREG_I2], (&(*grp)[MC_O2]));
@@ -574,6 +577,8 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
                  * clear the TS_RESTORE_SIGMASK flag.
                  */
                 current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+
+                tracehook_signal_handler(signr, &info, &ka, regs, 0);
                 return;
         }
         if (restart_syscall &&
@@ -605,4 +610,8 @@ void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0, unsigned long
 {
         if (thread_info_flags & _TIF_SIGPENDING)
                 do_signal(regs, orig_i0);
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+        }
 }
diff --git a/arch/sparc64/kernel/signal32.c b/arch/sparc64/kernel/signal32.c
index 97cdd1bf4a10..ba5b09ad6666 100644
--- a/arch/sparc64/kernel/signal32.c
+++ b/arch/sparc64/kernel/signal32.c
@@ -19,6 +19,7 @@
 #include <linux/binfmts.h>
 #include <linux/compat.h>
 #include <linux/bitops.h>
+#include <linux/tracehook.h>
 
 #include <asm/uaccess.h>
 #include <asm/ptrace.h>
@@ -794,6 +795,8 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
                  * clear the TS_RESTORE_SIGMASK flag.
                  */
                 current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
+
+                tracehook_signal_handler(signr, &info, &ka, regs, 0);
                 return;
         }
         if (restart_syscall &&
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 7cf72b4bb108..27b81775a4de 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -459,27 +459,35 @@ again:
         }
 }
 
-static inline void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
+static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 {
+        u64 *mondo, data0, data1, data2;
+        u16 *cpu_list;
         u64 pstate;
         int i;
 
         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
-        for_each_cpu_mask(i, mask)
-                spitfire_xcall_helper(data0, data1, data2, pstate, i);
+        cpu_list = __va(tb->cpu_list_pa);
+        mondo = __va(tb->cpu_mondo_block_pa);
+        data0 = mondo[0];
+        data1 = mondo[1];
+        data2 = mondo[2];
+        for (i = 0; i < cnt; i++)
+                spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
 }
 
 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
  * packet, but we have no use for that.  However we do take advantage of
  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
  */
-static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
+static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 {
-        u64 pstate, ver, busy_mask;
         int nack_busy_id, is_jbus, need_more;
+        u64 *mondo, pstate, ver, busy_mask;
+        u16 *cpu_list;
 
-        if (cpus_empty(mask))
-                return;
+        cpu_list = __va(tb->cpu_list_pa);
+        mondo = __va(tb->cpu_mondo_block_pa);
 
         /* Unfortunately, someone at Sun had the brilliant idea to make the
          * busy/nack fields hard-coded by ITID number for this Ultra-III
@@ -502,7 +510,7 @@ retry:
                              "stxa      %2, [%5] %6\n\t"
                              "membar    #Sync\n\t"
                              : /* no outputs */
-                             : "r" (data0), "r" (data1), "r" (data2),
+                             : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
                                "r" (0x40), "r" (0x50), "r" (0x60),
                                "i" (ASI_INTR_W));
 
@@ -511,11 +519,16 @@ retry:
         {
                 int i;
 
-                for_each_cpu_mask(i, mask) {
-                        u64 target = (i << 14) | 0x70;
+                for (i = 0; i < cnt; i++) {
+                        u64 target, nr;
 
+                        nr = cpu_list[i];
+                        if (nr == 0xffff)
+                                continue;
+
+                        target = (nr << 14) | 0x70;
                         if (is_jbus) {
-                                busy_mask |= (0x1UL << (i * 2));
+                                busy_mask |= (0x1UL << (nr * 2));
                         } else {
                                 target |= (nack_busy_id << 24);
                                 busy_mask |= (0x1UL <<
@@ -549,11 +562,13 @@ retry:
                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
                                                      : : "r" (pstate));
                                 if (unlikely(need_more)) {
-                                        int i, cnt = 0;
-                                        for_each_cpu_mask(i, mask) {
-                                                cpu_clear(i, mask);
-                                                cnt++;
-                                                if (cnt == 32)
+                                        int i, this_cnt = 0;
+                                        for (i = 0; i < cnt; i++) {
+                                                if (cpu_list[i] == 0xffff)
+                                                        continue;
+                                                cpu_list[i] = 0xffff;
+                                                this_cnt++;
+                                                if (this_cnt == 32)
                                                         break;
                                         }
                                         goto retry;
@@ -584,16 +599,20 @@ retry:
                         /* Clear out the mask bits for cpus which did not
                          * NACK us.
                          */
-                        for_each_cpu_mask(i, mask) {
-                                u64 check_mask;
+                        for (i = 0; i < cnt; i++) {
+                                u64 check_mask, nr;
+
+                                nr = cpu_list[i];
+                                if (nr == 0xffff)
+                                        continue;
 
                                 if (is_jbus)
-                                        check_mask = (0x2UL << (2*i));
+                                        check_mask = (0x2UL << (2*nr));
                                 else
                                         check_mask = (0x2UL <<
                                                       this_busy_nack);
                                 if ((dispatch_stat & check_mask) == 0)
-                                        cpu_clear(i, mask);
+                                        cpu_list[i] = 0xffff;
                                 this_busy_nack += 2;
                                 if (this_busy_nack == 64)
                                         break;
@@ -605,47 +624,17 @@ retry:
 }
 
 /* Multi-cpu list version.  */
-static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
+static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 {
-        struct trap_per_cpu *tb;
+        int retries, this_cpu, prev_sent, i, saw_cpu_error;
+        unsigned long status;
         u16 *cpu_list;
-        u64 *mondo;
-        cpumask_t error_mask;
-        unsigned long flags, status;
-        int cnt, retries, this_cpu, prev_sent, i;
-
-        if (cpus_empty(mask))
-                return;
-
-        /* We have to do this whole thing with interrupts fully disabled.
-         * Otherwise if we send an xcall from interrupt context it will
-         * corrupt both our mondo block and cpu list state.
-         *
-         * One consequence of this is that we cannot use timeout mechanisms
-         * that depend upon interrupts being delivered locally.  So, for
-         * example, we cannot sample jiffies and expect it to advance.
-         *
-         * Fortunately, udelay() uses %stick/%tick so we can use that.
-         */
-        local_irq_save(flags);
 
         this_cpu = smp_processor_id();
-        tb = &trap_block[this_cpu];
-
-        mondo = __va(tb->cpu_mondo_block_pa);
-        mondo[0] = data0;
-        mondo[1] = data1;
-        mondo[2] = data2;
-        wmb();
 
         cpu_list = __va(tb->cpu_list_pa);
 
-        /* Setup the initial cpu list.  */
-        cnt = 0;
-        for_each_cpu_mask(i, mask)
-                cpu_list[cnt++] = i;
-
-        cpus_clear(error_mask);
+        saw_cpu_error = 0;
         retries = 0;
         prev_sent = 0;
         do {
@@ -690,10 +679,9 @@ static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t
                                         continue;
 
                                 err = sun4v_cpu_state(cpu);
-                                if (err >= 0 &&
-                                    err == HV_CPU_STATE_ERROR) {
+                                if (err == HV_CPU_STATE_ERROR) {
+                                        saw_cpu_error = (cpu + 1);
                                         cpu_list[i] = 0xffff;
-                                        cpu_set(cpu, error_mask);
                                 }
                         }
                 } else if (unlikely(status != HV_EWOULDBLOCK))
@@ -717,32 +705,24 @@ static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t
                 }
         } while (1);
 
-        local_irq_restore(flags);
-
-        if (unlikely(!cpus_empty(error_mask)))
+        if (unlikely(saw_cpu_error))
                 goto fatal_mondo_cpu_error;
 
         return;
 
 fatal_mondo_cpu_error:
         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
-               "were in error state\n",
-               this_cpu);
-        printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
-        for_each_cpu_mask(i, error_mask)
-                printk("%d ", i);
-        printk("]\n");
+               "(including %d) were in error state\n",
+               this_cpu, saw_cpu_error - 1);
         return;
 
 fatal_mondo_timeout:
-        local_irq_restore(flags);
         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
                " progress after %d retries.\n",
                this_cpu, retries);
         goto dump_cpu_list_and_out;
 
 fatal_mondo_error:
-        local_irq_restore(flags);
         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
                this_cpu, status);
         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
@@ -756,58 +736,93 @@ dump_cpu_list_and_out:
         printk("]\n");
 }
 
-/* Send cross call to all processors mentioned in MASK
- * except self.
+static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
+
+static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
+{
+        struct trap_per_cpu *tb;
+        int this_cpu, i, cnt;
+        unsigned long flags;
+        u16 *cpu_list;
+        u64 *mondo;
+
+        /* We have to do this whole thing with interrupts fully disabled.
+         * Otherwise if we send an xcall from interrupt context it will
+         * corrupt both our mondo block and cpu list state.
+         *
+         * One consequence of this is that we cannot use timeout mechanisms
+         * that depend upon interrupts being delivered locally.  So, for
+         * example, we cannot sample jiffies and expect it to advance.
+         *
+         * Fortunately, udelay() uses %stick/%tick so we can use that.
+         */
+        local_irq_save(flags);
+
+        this_cpu = smp_processor_id();
+        tb = &trap_block[this_cpu];
+
+        mondo = __va(tb->cpu_mondo_block_pa);
+        mondo[0] = data0;
+        mondo[1] = data1;
+        mondo[2] = data2;
+        wmb();
+
+        cpu_list = __va(tb->cpu_list_pa);
+
+        /* Setup the initial cpu list.  */
+        cnt = 0;
+        for_each_cpu_mask_nr(i, *mask) {
+                if (i == this_cpu || !cpu_online(i))
+                        continue;
+                cpu_list[cnt++] = i;
+        }
+
+        if (cnt)
+                xcall_deliver_impl(tb, cnt);
+
+        local_irq_restore(flags);
+}
+
+/* Send cross call to all processors mentioned in MASK_P
+ * except self.  Really, there are only two cases currently,
+ * "&cpu_online_map" and "&mm->cpu_vm_mask".
  */
-static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
+static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
 {
         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
-        int this_cpu = get_cpu();
-
-        cpus_and(mask, mask, cpu_online_map);
-        cpu_clear(this_cpu, mask);
 
-        if (tlb_type == spitfire)
-                spitfire_xcall_deliver(data0, data1, data2, mask);
-        else if (tlb_type == cheetah || tlb_type == cheetah_plus)
-                cheetah_xcall_deliver(data0, data1, data2, mask);
-        else
-                hypervisor_xcall_deliver(data0, data1, data2, mask);
-        /* NOTE: Caller runs local copy on master. */
+        xcall_deliver(data0, data1, data2, mask);
+}
 
-        put_cpu();
+/* Send cross call to all processors except self. */
+static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
+{
+        smp_cross_call_masked(func, ctx, data1, data2, &cpu_online_map);
 }
 
 extern unsigned long xcall_sync_tick;
 
 static void smp_start_sync_tick_client(int cpu)
 {
-        cpumask_t mask = cpumask_of_cpu(cpu);
-
-        smp_cross_call_masked(&xcall_sync_tick,
-                              0, 0, 0, mask);
+        xcall_deliver((u64) &xcall_sync_tick, 0, 0,
+                      &cpumask_of_cpu(cpu));
 }
 
 extern unsigned long xcall_call_function;
 
 void arch_send_call_function_ipi(cpumask_t mask)
 {
-        smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
+        xcall_deliver((u64) &xcall_call_function, 0, 0, &mask);
 }
 
 extern unsigned long xcall_call_function_single;
 
 void arch_send_call_function_single_ipi(int cpu)
 {
-        cpumask_t mask = cpumask_of_cpu(cpu);
-
-        smp_cross_call_masked(&xcall_call_function_single, 0, 0, 0, mask);
+        xcall_deliver((u64) &xcall_call_function_single, 0, 0,
+                      &cpumask_of_cpu(cpu));
 }
 
-/* Send cross call to all processors except self. */
-#define smp_cross_call(func, ctx, data1, data2) \
-        smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
-
 void smp_call_function_client(int irq, struct pt_regs *regs)
 {
         clear_softint(1 << irq);
@@ -843,7 +858,6 @@ void smp_tsb_sync(struct mm_struct *mm)
 extern unsigned long xcall_flush_tlb_mm;
 extern unsigned long xcall_flush_tlb_pending;
 extern unsigned long xcall_flush_tlb_kernel_range;
-extern unsigned long xcall_report_regs;
 #ifdef CONFIG_MAGIC_SYSRQ
 extern unsigned long xcall_fetch_glob_regs;
 #endif
@@ -878,7 +892,6 @@ static inline void __local_flush_dcache_page(struct page *page)
 
 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 {
-        cpumask_t mask = cpumask_of_cpu(cpu);
         int this_cpu;
 
         if (tlb_type == hypervisor)
@@ -894,29 +907,24 @@ void smp_flush_dcache_page_impl(struct page *page, int cpu)
                 __local_flush_dcache_page(page);
         } else if (cpu_online(cpu)) {
                 void *pg_addr = page_address(page);
-                u64 data0;
+                u64 data0 = 0;
 
                 if (tlb_type == spitfire) {
-                        data0 =
-                                ((u64)&xcall_flush_dcache_page_spitfire);
+                        data0 = ((u64)&xcall_flush_dcache_page_spitfire);
                         if (page_mapping(page) != NULL)
                                 data0 |= ((u64)1 << 32);
-                        spitfire_xcall_deliver(data0,
-                                               __pa(pg_addr),
-                                               (u64) pg_addr,
-                                               mask);
                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 #ifdef DCACHE_ALIASING_POSSIBLE
-                        data0 =
-                                ((u64)&xcall_flush_dcache_page_cheetah);
-                        cheetah_xcall_deliver(data0,
-                                              __pa(pg_addr),
-                                              0, mask);
+                        data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 #endif
                 }
+                if (data0) {
+                        xcall_deliver(data0, __pa(pg_addr),
+                                      (u64) pg_addr, &cpumask_of_cpu(cpu));
 #ifdef CONFIG_DEBUG_DCFLUSH
-                atomic_inc(&dcpage_flushes_xcall);
+                        atomic_inc(&dcpage_flushes_xcall);
 #endif
+                }
         }
 
         put_cpu();
@@ -924,66 +932,41 @@ void smp_flush_dcache_page_impl(struct page *page, int cpu)
 
 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 {
-        void *pg_addr = page_address(page);
-        cpumask_t mask = cpu_online_map;
-        u64 data0;
+        void *pg_addr;
         int this_cpu;
+        u64 data0;
 
         if (tlb_type == hypervisor)
                 return;
 
         this_cpu = get_cpu();
 
-        cpu_clear(this_cpu, mask);
-
 #ifdef CONFIG_DEBUG_DCFLUSH
         atomic_inc(&dcpage_flushes);
 #endif
-        if (cpus_empty(mask))
-                goto flush_self;
+        data0 = 0;
+        pg_addr = page_address(page);
         if (tlb_type == spitfire) {
                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
                 if (page_mapping(page) != NULL)
                         data0 |= ((u64)1 << 32);
-                spitfire_xcall_deliver(data0,
-                                       __pa(pg_addr),
-                                       (u64) pg_addr,
-                                       mask);
         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 #ifdef DCACHE_ALIASING_POSSIBLE
                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
-                cheetah_xcall_deliver(data0,
-                                      __pa(pg_addr),
-                                      0, mask);
 #endif
         }
+        if (data0) {
+                xcall_deliver(data0, __pa(pg_addr),
+                              (u64) pg_addr, &cpu_online_map);
 #ifdef CONFIG_DEBUG_DCFLUSH
-        atomic_inc(&dcpage_flushes_xcall);
+                atomic_inc(&dcpage_flushes_xcall);
 #endif
- flush_self:
+        }
         __local_flush_dcache_page(page);
 
         put_cpu();
 }
 
-static void __smp_receive_signal_mask(cpumask_t mask)
-{
-        smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
-}
-
-void smp_receive_signal(int cpu)
-{
-        cpumask_t mask = cpumask_of_cpu(cpu);
-
-        if (cpu_online(cpu))
-                __smp_receive_signal_mask(mask);
-}
-
-void smp_receive_signal_client(int irq, struct pt_regs *regs)
-{
-        clear_softint(1 << irq);
-}
-
 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 {
         struct mm_struct *mm;
@@ -1022,11 +1005,6 @@ void kgdb_roundup_cpus(unsigned long flags)
 }
 #endif
 
-void smp_report_regs(void)
-{
-        smp_cross_call(&xcall_report_regs, 0, 0, 0);
-}
-
 #ifdef CONFIG_MAGIC_SYSRQ
 void smp_fetch_global_regs(void)
 {
@@ -1089,7 +1067,7 @@ void smp_flush_tlb_mm(struct mm_struct *mm)
 
         smp_cross_call_masked(&xcall_flush_tlb_mm,
                               ctx, 0, 0,
-                              mm->cpu_vm_mask);
+                              &mm->cpu_vm_mask);
 
 local_flush_and_out:
         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
@@ -1107,7 +1085,7 @@ void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long
         else
                 smp_cross_call_masked(&xcall_flush_tlb_pending,
                                       ctx, nr, (unsigned long) vaddrs,
-                                      mm->cpu_vm_mask);
+                                      &mm->cpu_vm_mask);
 
         __flush_tlb_pending(ctx, nr, vaddrs);
 
@@ -1208,6 +1186,16 @@ void __devinit smp_prepare_boot_cpu(void)
 {
 }
 
+void __init smp_setup_processor_id(void)
+{
+        if (tlb_type == spitfire)
+                xcall_deliver_impl = spitfire_xcall_deliver;
+        else if (tlb_type == cheetah || tlb_type == cheetah_plus)
+                xcall_deliver_impl = cheetah_xcall_deliver;
+        else
+                xcall_deliver_impl = hypervisor_xcall_deliver;
+}
+
 void __devinit smp_fill_in_sib_core_maps(void)
 {
         unsigned int i;
@@ -1376,7 +1364,13 @@ void __init smp_cpus_done(unsigned int max_cpus)
 
 void smp_send_reschedule(int cpu)
 {
-        smp_receive_signal(cpu);
+        xcall_deliver((u64) &xcall_receive_signal, 0, 0,
+                      &cpumask_of_cpu(cpu));
+}
+
+void smp_receive_signal_client(int irq, struct pt_regs *regs)
+{
+        clear_softint(1 << irq);
 }
 
 /* This is a nop because we capture all other cpus
diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
index 504e678ee128..0804f71df6cb 100644
--- a/arch/sparc64/kernel/sparc64_ksyms.c
+++ b/arch/sparc64/kernel/sparc64_ksyms.c
@@ -68,7 +68,6 @@ extern void *__memscan_zero(void *, size_t);
 extern void *__memscan_generic(void *, int, size_t);
 extern int __memcmp(const void *, const void *, __kernel_size_t);
 extern __kernel_size_t strlen(const char *);
-extern void show_regs(struct pt_regs *);
 extern void syscall_trace(struct pt_regs *, int);
 extern void sys_sigsuspend(void);
 extern int compat_sys_ioctl(unsigned int fd, unsigned int cmd, u32 arg);
diff --git a/arch/sparc64/kernel/syscalls.S b/arch/sparc64/kernel/syscalls.S
index db19ed67acf6..a2f24270ed8a 100644
--- a/arch/sparc64/kernel/syscalls.S
+++ b/arch/sparc64/kernel/syscalls.S
@@ -162,6 +162,8 @@ linux_syscall_trace32:
         add     %sp, PTREGS_OFF, %o0
         call    syscall_trace
          clr    %o1
+        brnz,pn %o0, 3f
+         mov    -ENOSYS, %o0
         srl     %i0, 0, %o0
         srl     %i4, 0, %o4
         srl     %i1, 0, %o1
@@ -173,6 +175,8 @@ linux_syscall_trace:
         add     %sp, PTREGS_OFF, %o0
         call    syscall_trace
          clr    %o1
+        brnz,pn %o0, 3f
+         mov    -ENOSYS, %o0
         mov     %i0, %o0
         mov     %i1, %o1
         mov     %i2, %o2
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index bd30ecba5630..404e8561e2d0 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -1777,7 +1777,7 @@ static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent,
                pfx,
                ent->err_raddr, ent->err_size, ent->err_cpu);
 
-        __show_regs(regs);
+        show_regs(regs);
 
         if ((cnt = atomic_read(ocnt)) != 0) {
                 atomic_set(ocnt, 0);
@@ -2177,7 +2177,6 @@ static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
 void die_if_kernel(char *str, struct pt_regs *regs)
 {
         static int die_counter;
-        extern void smp_report_regs(void);
         int count = 0;
         
         /* Amuse the user. */
@@ -2190,7 +2189,7 @@ void die_if_kernel(char *str, struct pt_regs *regs)
         printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
         notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
         __asm__ __volatile__("flushw");
-        __show_regs(regs);
+        show_regs(regs);
         add_taint(TAINT_DIE);
         if (regs->tstate & TSTATE_PRIV) {
                 struct reg_window *rw = (struct reg_window *)
@@ -2215,11 +2214,6 @@ void die_if_kernel(char *str, struct pt_regs *regs)
                 }
                 user_instruction_dump ((unsigned int __user *) regs->tpc);
         }
-#if 0
-#ifdef CONFIG_SMP
-        smp_report_regs();
-#endif
-#endif                                                  
         if (regs->tstate & TSTATE_PRIV)
                 do_exit(SIGKILL);
         do_exit(SIGSEGV);
diff --git a/arch/sparc64/mm/tsb.c b/arch/sparc64/mm/tsb.c
index 3547937b17a2..587f8efb2e05 100644
--- a/arch/sparc64/mm/tsb.c
+++ b/arch/sparc64/mm/tsb.c
@@ -1,9 +1,10 @@
 /* arch/sparc64/mm/tsb.c
  *
- * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
+ * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net>
  */
 
 #include <linux/kernel.h>
+#include <linux/preempt.h>
 #include <asm/system.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -415,7 +416,9 @@ retry_tsb_alloc:
                 tsb_context_switch(mm);
 
                 /* Now force other processors to do the same.  */
+                preempt_disable();
                 smp_tsb_sync(mm);
+                preempt_enable();
 
                 /* Now it is safe to free the old tsb.  */
                 kmem_cache_free(tsb_caches[old_cache_index], old_tsb);
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 4c8ca131ffaf..ff1dc44d363e 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -480,41 +480,6 @@ xcall_sync_tick:
         b               rtrap_xcall
          ldx            [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 
-        /* NOTE: This is SPECIAL!!  We do etrap/rtrap however
-         *       we choose to deal with the "BH's run with
-         *       %pil==15" problem (described in asm/pil.h)
-         *       by just invoking rtrap directly past where
-         *       BH's are checked for.
-         *
-         *       We do it like this because we do not want %pil==15
-         *       lockups to prevent regs being reported.
-         */
-        .globl          xcall_report_regs
-xcall_report_regs:
-
-661:    rdpr            %pstate, %g2
-        wrpr            %g2, PSTATE_IG | PSTATE_AG, %pstate
-        .section        .sun4v_2insn_patch, "ax"
-        .word           661b
-        nop
-        nop
-        .previous
-
-        rdpr            %pil, %g2
-        wrpr            %g0, 15, %pil
-        sethi           %hi(109f), %g7
-        b,pt            %xcc, etrap_irq
-109:     or             %g7, %lo(109b), %g7
-#ifdef CONFIG_TRACE_IRQFLAGS
-        call            trace_hardirqs_off
-         nop
-#endif
-        call            __show_regs
-         add            %sp, PTREGS_OFF, %o0
-        /* Has to be a non-v9 branch due to the large distance. */
-        b               rtrap_xcall
-         ldx            [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
-
 #ifdef CONFIG_MAGIC_SYSRQ
         .globl          xcall_fetch_glob_regs
 xcall_fetch_glob_regs:
@@ -531,6 +496,13 @@ xcall_fetch_glob_regs:
         stx             %g7, [%g1 + GR_SNAP_TNPC]
         stx             %o7, [%g1 + GR_SNAP_O7]
         stx             %i7, [%g1 + GR_SNAP_I7]
+        /* Don't try this at home kids... */
+        rdpr            %cwp, %g2
+        sub             %g2, 1, %g7
+        wrpr            %g7, %cwp
+        mov             %i7, %g7
+        wrpr            %g2, %cwp
+        stx             %g7, [%g1 + GR_SNAP_RPC]
         sethi           %hi(trap_block), %g7
         or              %g7, %lo(trap_block), %g7
         sllx            %g2, TRAP_BLOCK_SZ_SHIFT, %g2
diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c
index 5047490fc299..d741f35d7b3a 100644
--- a/arch/um/drivers/line.c
+++ b/arch/um/drivers/line.c
@@ -362,19 +362,7 @@ static irqreturn_t line_write_interrupt(int irq, void *data)
         if (tty == NULL)
                 return IRQ_NONE;
 
-        if (test_bit(TTY_DO_WRITE_WAKEUP, &tty->flags) &&
-           (tty->ldisc.write_wakeup != NULL))
-                (tty->ldisc.write_wakeup)(tty);
-
-        /*
-         * BLOCKING mode
-         * In blocking mode, everything sleeps on tty->write_wait.
-         * Sleeping in the console driver would break non-blocking
-         * writes.
-         */
-
-        if (waitqueue_active(&tty->write_wait))
-                wake_up_interruptible(&tty->write_wait);
+        tty_wakeup(tty);
         return IRQ_HANDLED;
 }
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b6fa2877b173..3d0f2b6a5a16 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -30,6 +30,7 @@ config X86
         select HAVE_FTRACE
         select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64)
         select HAVE_ARCH_KGDB if !X86_VOYAGER
+        select HAVE_GENERIC_DMA_COHERENT if X86_32
         select HAVE_EFFICIENT_UNALIGNED_ACCESS
 
 config ARCH_DEFCONFIG
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 9220cf46aa10..c2502eb9aa83 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -73,7 +73,6 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
         struct cpuinfo_x86 *c = &cpu_data(cpu);
 
         cpumask_t saved_mask;
-        cpumask_of_cpu_ptr(new_mask, cpu);
         int retval;
         unsigned int eax, ebx, ecx, edx;
         unsigned int edx_part;
@@ -92,7 +91,7 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
 
         /* Make sure we are running on right CPU */
         saved_mask = current->cpus_allowed;
-        retval = set_cpus_allowed_ptr(current, new_mask);
+        retval = set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (retval)
                 return -1;
 
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 74697408576f..22d7d050905d 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -29,9 +29,6 @@
 
 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
 
-#define to_pages(addr, size) \
-         (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
-
 #define EXIT_LOOP_COUNT 10000000
 
 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
@@ -185,7 +182,7 @@ static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
                 u64 address, size_t size)
 {
         int s = 0;
-        unsigned pages = to_pages(address, size);
+        unsigned pages = iommu_num_pages(address, size);
 
         address &= PAGE_MASK;
 
@@ -557,8 +554,8 @@ static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
         if (iommu->exclusion_start &&
             iommu->exclusion_start < dma_dom->aperture_size) {
                 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
-                int pages = to_pages(iommu->exclusion_start,
-                                iommu->exclusion_length);
+                int pages = iommu_num_pages(iommu->exclusion_start,
+                                            iommu->exclusion_length);
                 dma_ops_reserve_addresses(dma_dom, startpage, pages);
         }
 
@@ -767,7 +764,7 @@ static dma_addr_t __map_single(struct device *dev,
         unsigned int pages;
         int i;
 
-        pages = to_pages(paddr, size);
+        pages = iommu_num_pages(paddr, size);
         paddr &= PAGE_MASK;
 
         address = dma_ops_alloc_addresses(dev, dma_dom, pages);
@@ -802,7 +799,7 @@ static void __unmap_single(struct amd_iommu *iommu,
         if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
                 return;
 
-        pages = to_pages(dma_addr, size);
+        pages = iommu_num_pages(dma_addr, size);
         dma_addr &= PAGE_MASK;
         start = dma_addr;
 
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index ff2fff56f0a8..dd097b835839 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -200,12 +200,10 @@ static void drv_read(struct drv_cmd *cmd)
 static void drv_write(struct drv_cmd *cmd)
 {
         cpumask_t saved_mask = current->cpus_allowed;
-        cpumask_of_cpu_ptr_declare(cpu_mask);
         unsigned int i;
 
         for_each_cpu_mask_nr(i, cmd->mask) {
-                cpumask_of_cpu_ptr_next(cpu_mask, i);
-                set_cpus_allowed_ptr(current, cpu_mask);
+                set_cpus_allowed_ptr(current, &cpumask_of_cpu(i));
                 do_drv_write(cmd);
         }
 
@@ -269,12 +267,11 @@ static unsigned int get_measured_perf(unsigned int cpu)
         } aperf_cur, mperf_cur;
 
         cpumask_t saved_mask;
-        cpumask_of_cpu_ptr(cpu_mask, cpu);
         unsigned int perf_percent;
         unsigned int retval;
 
         saved_mask = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, cpu_mask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (get_cpu() != cpu) {
                 /* We were not able to run on requested processor */
                 put_cpu();
@@ -340,7 +337,6 @@ static unsigned int get_measured_perf(unsigned int cpu)
 
 static unsigned int get_cur_freq_on_cpu(unsigned int cpu)
 {
-        cpumask_of_cpu_ptr(cpu_mask, cpu);
         struct acpi_cpufreq_data *data = per_cpu(drv_data, cpu);
         unsigned int freq;
         unsigned int cached_freq;
@@ -353,7 +349,7 @@ static unsigned int get_cur_freq_on_cpu(unsigned int cpu)
         }
 
         cached_freq = data->freq_table[data->acpi_data->state].frequency;
-        freq = extract_freq(get_cur_val(cpu_mask), data);
+        freq = extract_freq(get_cur_val(&cpumask_of_cpu(cpu)), data);
         if (freq != cached_freq) {
                 /*
                  * The dreaded BIOS frequency change behind our back.
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 53c7b6936973..c45ca6d4dce1 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -479,12 +479,11 @@ static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvi
 static int check_supported_cpu(unsigned int cpu)
 {
         cpumask_t oldmask;
-        cpumask_of_cpu_ptr(cpu_mask, cpu);
         u32 eax, ebx, ecx, edx;
         unsigned int rc = 0;
 
         oldmask = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, cpu_mask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
 
         if (smp_processor_id() != cpu) {
                 printk(KERN_ERR PFX "limiting to cpu %u failed\n", cpu);
@@ -1017,7 +1016,6 @@ static int transition_frequency_pstate(struct powernow_k8_data *data, unsigned i
 static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsigned relation)
 {
         cpumask_t oldmask;
-        cpumask_of_cpu_ptr(cpu_mask, pol->cpu);
         struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu);
         u32 checkfid;
         u32 checkvid;
@@ -1032,7 +1030,7 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
 
         /* only run on specific CPU from here on */
         oldmask = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, cpu_mask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu));
 
         if (smp_processor_id() != pol->cpu) {
                 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
@@ -1107,7 +1105,6 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
 {
         struct powernow_k8_data *data;
         cpumask_t oldmask;
-        cpumask_of_cpu_ptr_declare(newmask);
         int rc;
 
         if (!cpu_online(pol->cpu))
@@ -1159,8 +1156,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
 
         /* only run on specific CPU from here on */
         oldmask = current->cpus_allowed;
-        cpumask_of_cpu_ptr_next(newmask, pol->cpu);
-        set_cpus_allowed_ptr(current, newmask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu));
 
         if (smp_processor_id() != pol->cpu) {
                 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
@@ -1182,7 +1178,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
         set_cpus_allowed_ptr(current, &oldmask);
 
         if (cpu_family == CPU_HW_PSTATE)
-                pol->cpus = *newmask;
+                pol->cpus = cpumask_of_cpu(pol->cpu);
         else
                 pol->cpus = per_cpu(cpu_core_map, pol->cpu);
         data->available_cores = &(pol->cpus);
@@ -1248,7 +1244,6 @@ static unsigned int powernowk8_get (unsigned int cpu)
 {
         struct powernow_k8_data *data;
         cpumask_t oldmask = current->cpus_allowed;
-        cpumask_of_cpu_ptr(newmask, cpu);
         unsigned int khz = 0;
         unsigned int first;
 
@@ -1258,7 +1253,7 @@ static unsigned int powernowk8_get (unsigned int cpu)
         if (!data)
                 return -EINVAL;
 
-        set_cpus_allowed_ptr(current, newmask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (smp_processor_id() != cpu) {
                 printk(KERN_ERR PFX
                         "limiting to CPU %d failed in powernowk8_get\n", cpu);
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
index ca2ac13b7af2..15e13c01cc36 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -324,10 +324,9 @@ static unsigned int get_cur_freq(unsigned int cpu)
         unsigned l, h;
         unsigned clock_freq;
         cpumask_t saved_mask;
-        cpumask_of_cpu_ptr(new_mask, cpu);
 
         saved_mask = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, new_mask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (smp_processor_id() != cpu)
                 return 0;
 
@@ -585,15 +584,12 @@ static int centrino_target (struct cpufreq_policy *policy,
                  * Best effort undo..
                  */
 
-                if (!cpus_empty(*covered_cpus)) {
-                        cpumask_of_cpu_ptr_declare(new_mask);
-
+                if (!cpus_empty(*covered_cpus))
                         for_each_cpu_mask_nr(j, *covered_cpus) {
-                                cpumask_of_cpu_ptr_next(new_mask, j);
-                                set_cpus_allowed_ptr(current, new_mask);
+                                set_cpus_allowed_ptr(current,
+                                                     &cpumask_of_cpu(j));
                                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
                         }
-                }
 
                 tmp = freqs.new;
                 freqs.new = freqs.old;
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
index 2f3728dc24f6..191f7263c61d 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
@@ -244,8 +244,7 @@ static unsigned int _speedstep_get(const cpumask_t *cpus)
 
 static unsigned int speedstep_get(unsigned int cpu)
 {
-        cpumask_of_cpu_ptr(newmask, cpu);
-        return _speedstep_get(newmask);
+        return _speedstep_get(&cpumask_of_cpu(cpu));
 }
 
 /**
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 650d40f7912b..6b0a10b002f1 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -516,7 +516,6 @@ static int __cpuinit detect_cache_attributes(unsigned int cpu)
         unsigned long           j;
         int                     retval;
         cpumask_t               oldmask;
-        cpumask_of_cpu_ptr(newmask, cpu);
 
         if (num_cache_leaves == 0)
                 return -ENOENT;
@@ -527,7 +526,7 @@ static int __cpuinit detect_cache_attributes(unsigned int cpu)
                 return -ENOMEM;
 
         oldmask = current->cpus_allowed;
-        retval = set_cpus_allowed_ptr(current, newmask);
+        retval = set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         if (retval)
                 goto out;
 
diff --git a/arch/x86/kernel/genapic_64.c b/arch/x86/kernel/genapic_64.c
index 1fa8be5bd217..eaff0bbb1444 100644
--- a/arch/x86/kernel/genapic_64.c
+++ b/arch/x86/kernel/genapic_64.c
@@ -99,3 +99,4 @@ int is_uv_system(void)
 {
         return uv_system_type != UV_NONE;
 }
+EXPORT_SYMBOL_GPL(is_uv_system);
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index 3fee2aa50f3f..b68e21f06f4f 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -62,12 +62,10 @@ static int alloc_ldt(mm_context_t *pc, int mincount, int reload)
 
         if (reload) {
 #ifdef CONFIG_SMP
-                cpumask_of_cpu_ptr_declare(mask);
-
                 preempt_disable();
                 load_LDT(pc);
-                cpumask_of_cpu_ptr_next(mask, smp_processor_id());
-                if (!cpus_equal(current->mm->cpu_vm_mask, *mask))
+                if (!cpus_equal(current->mm->cpu_vm_mask,
+                                cpumask_of_cpu(smp_processor_id())))
                         smp_call_function(flush_ldt, current->mm, 1);
                 preempt_enable();
 #else
diff --git a/arch/x86/kernel/microcode.c b/arch/x86/kernel/microcode.c
index 6994c751590e..652fa5c38ebe 100644
--- a/arch/x86/kernel/microcode.c
+++ b/arch/x86/kernel/microcode.c
@@ -388,7 +388,6 @@ static int do_microcode_update (void)
         void *new_mc = NULL;
         int cpu;
         cpumask_t old;
-        cpumask_of_cpu_ptr_declare(newmask);
 
         old = current->cpus_allowed;
 
@@ -405,8 +404,7 @@ static int do_microcode_update (void)
 
                         if (!uci->valid)
                                 continue;
-                        cpumask_of_cpu_ptr_next(newmask, cpu);
-                        set_cpus_allowed_ptr(current, newmask);
+                        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
                         error = get_maching_microcode(new_mc, cpu);
                         if (error < 0)
                                 goto out;
@@ -576,7 +574,6 @@ static int apply_microcode_check_cpu(int cpu)
         struct cpuinfo_x86 *c = &cpu_data(cpu);
         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
         cpumask_t old;
-        cpumask_of_cpu_ptr(newmask, cpu);
         unsigned int val[2];
         int err = 0;
 
@@ -585,7 +582,7 @@ static int apply_microcode_check_cpu(int cpu)
                 return 0;
 
         old = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, newmask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
 
         /* Check if the microcode we have in memory matches the CPU */
         if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
@@ -623,12 +620,11 @@ static int apply_microcode_check_cpu(int cpu)
 static void microcode_init_cpu(int cpu, int resume)
 {
         cpumask_t old;
-        cpumask_of_cpu_ptr(newmask, cpu);
         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
 
         old = current->cpus_allowed;
 
-        set_cpus_allowed_ptr(current, newmask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
         mutex_lock(&microcode_mutex);
         collect_cpu_info(cpu);
         if (uci->valid && system_state == SYSTEM_RUNNING && !resume)
@@ -661,13 +657,10 @@ static ssize_t reload_store(struct sys_device *dev,
         if (end == buf)
                 return -EINVAL;
         if (val == 1) {
-                cpumask_t old;
-                cpumask_of_cpu_ptr(newmask, cpu);
-
-                old = current->cpus_allowed;
+                cpumask_t old = current->cpus_allowed;
 
                 get_online_cpus();
-                set_cpus_allowed_ptr(current, newmask);
+                set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
 
                 mutex_lock(&microcode_mutex);
                 if (uci->valid)
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 37544123896d..87d4d6964ec2 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -123,6 +123,14 @@ void __init pci_iommu_alloc(void)
 
         pci_swiotlb_init();
 }
+
+unsigned long iommu_num_pages(unsigned long addr, unsigned long len)
+{
+        unsigned long size = roundup((addr & ~PAGE_MASK) + len, PAGE_SIZE);
+
+        return size >> PAGE_SHIFT;
+}
+EXPORT_SYMBOL(iommu_num_pages);
 #endif
 
 /*
@@ -192,124 +200,6 @@ static __init int iommu_setup(char *p)
 }
 early_param("iommu", iommu_setup);
 
-#ifdef CONFIG_X86_32
-int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
-                                dma_addr_t device_addr, size_t size, int flags)
-{
-        void __iomem *mem_base = NULL;
-        int pages = size >> PAGE_SHIFT;
-        int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
-
-        if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
-                goto out;
-        if (!size)
-                goto out;
-        if (dev->dma_mem)
-                goto out;
-
-        /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
-
-        mem_base = ioremap(bus_addr, size);
-        if (!mem_base)
-                goto out;
-
-        dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
-        if (!dev->dma_mem)
-                goto out;
-        dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-        if (!dev->dma_mem->bitmap)
-                goto free1_out;
-
-        dev->dma_mem->virt_base = mem_base;
-        dev->dma_mem->device_base = device_addr;
-        dev->dma_mem->size = pages;
-        dev->dma_mem->flags = flags;
-
-        if (flags & DMA_MEMORY_MAP)
-                return DMA_MEMORY_MAP;
-
-        return DMA_MEMORY_IO;
-
- free1_out:
-        kfree(dev->dma_mem);
- out:
-        if (mem_base)
-                iounmap(mem_base);
-        return 0;
-}
-EXPORT_SYMBOL(dma_declare_coherent_memory);
-
-void dma_release_declared_memory(struct device *dev)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-
-        if (!mem)
-                return;
-        dev->dma_mem = NULL;
-        iounmap(mem->virt_base);
-        kfree(mem->bitmap);
-        kfree(mem);
-}
-EXPORT_SYMBOL(dma_release_declared_memory);
-
-void *dma_mark_declared_memory_occupied(struct device *dev,
-                                        dma_addr_t device_addr, size_t size)
-{
-        struct dma_coherent_mem *mem = dev->dma_mem;
-        int pos, err;
-        int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1);
-
-        pages >>= PAGE_SHIFT;
-
-        if (!mem)
-                return ERR_PTR(-EINVAL);
-
-        pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
-        err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
-        if (err != 0)
-                return ERR_PTR(err);
-        return mem->virt_base + (pos << PAGE_SHIFT);
-}
-EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
-
-static int dma_alloc_from_coherent_mem(struct device *dev, ssize_t size,
-                                       dma_addr_t *dma_handle, void **ret)
-{
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
-        int order = get_order(size);
-
-        if (mem) {
-                int page = bitmap_find_free_region(mem->bitmap, mem->size,
-                                                     order);
-                if (page >= 0) {
-                        *dma_handle = mem->device_base + (page << PAGE_SHIFT);
-                        *ret = mem->virt_base + (page << PAGE_SHIFT);
-                        memset(*ret, 0, size);
-                }
-                if (mem->flags & DMA_MEMORY_EXCLUSIVE)
-                        *ret = NULL;
-        }
-        return (mem != NULL);
-}
-
-static int dma_release_coherent(struct device *dev, int order, void *vaddr)
-{
-        struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
-
-        if (mem && vaddr >= mem->virt_base && vaddr <
-                   (mem->virt_base + (mem->size << PAGE_SHIFT))) {
-                int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
-
-                bitmap_release_region(mem->bitmap, page, order);
-                return 1;
-        }
-        return 0;
-}
-#else
-#define dma_alloc_from_coherent_mem(dev, size, handle, ret) (0)
-#define dma_release_coherent(dev, order, vaddr) (0)
-#endif /* CONFIG_X86_32 */
-
 int dma_supported(struct device *dev, u64 mask)
 {
         struct dma_mapping_ops *ops = get_dma_ops(dev);
@@ -379,7 +269,7 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
         /* ignore region specifiers */
         gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
 
-        if (dma_alloc_from_coherent_mem(dev, size, dma_handle, &memory))
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
                 return memory;
 
         if (!dev) {
@@ -484,7 +374,7 @@ void dma_free_coherent(struct device *dev, size_t size,
 
         int order = get_order(size);
         WARN_ON(irqs_disabled());       /* for portability */
-        if (dma_release_coherent(dev, order, vaddr))
+        if (dma_release_from_coherent(dev, order, vaddr))
                 return;
         if (ops->unmap_single)
                 ops->unmap_single(dev, bus, size, 0);
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 744126e64950..49285f8fd4d5 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -67,9 +67,6 @@ static u32 gart_unmapped_entry;
         (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
 
-#define to_pages(addr, size) \
-        (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
-
 #define EMERGENCY_PAGES 32 /* = 128KB */
 
 #ifdef CONFIG_AGP
@@ -241,7 +238,7 @@ nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
                                 size_t size, int dir)
 {
-        unsigned long npages = to_pages(phys_mem, size);
+        unsigned long npages = iommu_num_pages(phys_mem, size);
         unsigned long iommu_page = alloc_iommu(dev, npages);
         int i;
 
@@ -304,7 +301,7 @@ static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
                 return;
 
         iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
-        npages = to_pages(dma_addr, size);
+        npages = iommu_num_pages(dma_addr, size);
         for (i = 0; i < npages; i++) {
                 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
                 CLEAR_LEAK(iommu_page + i);
@@ -387,7 +384,7 @@ static int __dma_map_cont(struct device *dev, struct scatterlist *start,
                 }
 
                 addr = phys_addr;
-                pages = to_pages(s->offset, s->length);
+                pages = iommu_num_pages(s->offset, s->length);
                 while (pages--) {
                         iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
                         SET_LEAK(iommu_page);
@@ -470,7 +467,7 @@ gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
 
                 seg_size += s->length;
                 need = nextneed;
-                pages += to_pages(s->offset, s->length);
+                pages += iommu_num_pages(s->offset, s->length);
                 ps = s;
         }
         if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 06a9f643817e..724adfc63cb9 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -414,25 +414,20 @@ void native_machine_shutdown(void)
 
         /* The boot cpu is always logical cpu 0 */
         int reboot_cpu_id = 0;
-        cpumask_of_cpu_ptr(newmask, reboot_cpu_id);
 
 #ifdef CONFIG_X86_32
         /* See if there has been given a command line override */
         if ((reboot_cpu != -1) && (reboot_cpu < NR_CPUS) &&
-                cpu_online(reboot_cpu)) {
+                cpu_online(reboot_cpu))
                 reboot_cpu_id = reboot_cpu;
-                cpumask_of_cpu_ptr_next(newmask, reboot_cpu_id);
-        }
 #endif
 
         /* Make certain the cpu I'm about to reboot on is online */
-        if (!cpu_online(reboot_cpu_id)) {
+        if (!cpu_online(reboot_cpu_id))
                 reboot_cpu_id = smp_processor_id();
-                cpumask_of_cpu_ptr_next(newmask, reboot_cpu_id);
-        }
 
         /* Make certain I only run on the appropriate processor */
-        set_cpus_allowed_ptr(current, newmask);
+        set_cpus_allowed_ptr(current, &cpumask_of_cpu(reboot_cpu_id));
 
         /* O.K Now that I'm on the appropriate processor,
          * stop all of the others.
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index b520dae02bf4..2d888586385d 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -788,10 +788,6 @@ void __init setup_arch(char **cmdline_p)
 
         initmem_init(0, max_pfn);
 
-#ifdef CONFIG_X86_64
-        dma32_reserve_bootmem();
-#endif
-
 #ifdef CONFIG_ACPI_SLEEP
         /*
          * Reserve low memory region for sleep support.
@@ -806,6 +802,15 @@ void __init setup_arch(char **cmdline_p)
 #endif
         reserve_crashkernel();
 
+#ifdef CONFIG_X86_64
+        /*
+         * dma32_reserve_bootmem() allocates bootmem which may conflict
+         * with the crashkernel command line, so do that after
+         * reserve_crashkernel()
+         */
+        dma32_reserve_bootmem();
+#endif
+
         reserve_ibft_region();
 
 #ifdef CONFIG_KVM_CLOCK
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index f7745f94c006..76e305e064f9 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -80,24 +80,6 @@ static void __init setup_per_cpu_maps(void)
 #endif
 }
 
-#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
-cpumask_t *cpumask_of_cpu_map __read_mostly;
-EXPORT_SYMBOL(cpumask_of_cpu_map);
-
-/* requires nr_cpu_ids to be initialized */
-static void __init setup_cpumask_of_cpu(void)
-{
-        int i;
-
-        /* alloc_bootmem zeroes memory */
-        cpumask_of_cpu_map = alloc_bootmem_low(sizeof(cpumask_t) * nr_cpu_ids);
-        for (i = 0; i < nr_cpu_ids; i++)
-                cpu_set(i, cpumask_of_cpu_map[i]);
-}
-#else
-static inline void setup_cpumask_of_cpu(void) { }
-#endif
-
 #ifdef CONFIG_X86_32
 /*
  * Great future not-so-futuristic plan: make i386 and x86_64 do it
@@ -197,9 +179,6 @@ void __init setup_per_cpu_areas(void)
 
         /* Setup node to cpumask map */
         setup_node_to_cpumask_map();
-
-        /* Setup cpumask_of_cpu map */
-        setup_cpumask_of_cpu();
 }
 
 #endif
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 8d45fabc5f3b..ce3251ce5504 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -21,6 +21,7 @@ config KVM
         tristate "Kernel-based Virtual Machine (KVM) support"
         depends on HAVE_KVM
         select PREEMPT_NOTIFIERS
+        select MMU_NOTIFIER
         select ANON_INODES
         ---help---
           Support hosting fully virtualized guest machines using hardware
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 2fa231923cf7..0bfe2bd305eb 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -653,6 +653,84 @@ static void rmap_write_protect(struct kvm *kvm, u64 gfn)
         account_shadowed(kvm, gfn);
 }
 
+static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp)
+{
+        u64 *spte;
+        int need_tlb_flush = 0;
+
+        while ((spte = rmap_next(kvm, rmapp, NULL))) {
+                BUG_ON(!(*spte & PT_PRESENT_MASK));
+                rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
+                rmap_remove(kvm, spte);
+                set_shadow_pte(spte, shadow_trap_nonpresent_pte);
+                need_tlb_flush = 1;
+        }
+        return need_tlb_flush;
+}
+
+static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
+                          int (*handler)(struct kvm *kvm, unsigned long *rmapp))
+{
+        int i;
+        int retval = 0;
+
+        /*
+         * If mmap_sem isn't taken, we can look the memslots with only
+         * the mmu_lock by skipping over the slots with userspace_addr == 0.
+         */
+        for (i = 0; i < kvm->nmemslots; i++) {
+                struct kvm_memory_slot *memslot = &kvm->memslots[i];
+                unsigned long start = memslot->userspace_addr;
+                unsigned long end;
+
+                /* mmu_lock protects userspace_addr */
+                if (!start)
+                        continue;
+
+                end = start + (memslot->npages << PAGE_SHIFT);
+                if (hva >= start && hva < end) {
+                        gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
+                        retval |= handler(kvm, &memslot->rmap[gfn_offset]);
+                        retval |= handler(kvm,
+                                          &memslot->lpage_info[
+                                                  gfn_offset /
+                                                  KVM_PAGES_PER_HPAGE].rmap_pde);
+                }
+        }
+
+        return retval;
+}
+
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
+{
+        return kvm_handle_hva(kvm, hva, kvm_unmap_rmapp);
+}
+
+static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp)
+{
+        u64 *spte;
+        int young = 0;
+
+        spte = rmap_next(kvm, rmapp, NULL);
+        while (spte) {
+                int _young;
+                u64 _spte = *spte;
+                BUG_ON(!(_spte & PT_PRESENT_MASK));
+                _young = _spte & PT_ACCESSED_MASK;
+                if (_young) {
+                        young = 1;
+                        clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
+                }
+                spte = rmap_next(kvm, rmapp, spte);
+        }
+        return young;
+}
+
+int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return kvm_handle_hva(kvm, hva, kvm_age_rmapp);
+}
+
 #ifdef MMU_DEBUG
 static int is_empty_shadow_page(u64 *spt)
 {
@@ -1203,6 +1281,7 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
         int r;
         int largepage = 0;
         pfn_t pfn;
+        unsigned long mmu_seq;
 
         down_read(&current->mm->mmap_sem);
         if (is_largepage_backed(vcpu, gfn & ~(KVM_PAGES_PER_HPAGE-1))) {
@@ -1210,6 +1289,8 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
                 largepage = 1;
         }
 
+        mmu_seq = vcpu->kvm->mmu_notifier_seq;
+        /* implicit mb(), we'll read before PT lock is unlocked */
         pfn = gfn_to_pfn(vcpu->kvm, gfn);
         up_read(&current->mm->mmap_sem);
 
@@ -1220,6 +1301,8 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
         }
 
         spin_lock(&vcpu->kvm->mmu_lock);
+        if (mmu_notifier_retry(vcpu, mmu_seq))
+                goto out_unlock;
         kvm_mmu_free_some_pages(vcpu);
         r = __direct_map(vcpu, v, write, largepage, gfn, pfn,
                          PT32E_ROOT_LEVEL);
@@ -1227,6 +1310,11 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
 
 
         return r;
+
+out_unlock:
+        spin_unlock(&vcpu->kvm->mmu_lock);
+        kvm_release_pfn_clean(pfn);
+        return 0;
 }
 
 
@@ -1345,6 +1433,7 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
         int r;
         int largepage = 0;
         gfn_t gfn = gpa >> PAGE_SHIFT;
+        unsigned long mmu_seq;
 
         ASSERT(vcpu);
         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
@@ -1358,6 +1447,8 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
                 gfn &= ~(KVM_PAGES_PER_HPAGE-1);
                 largepage = 1;
         }
+        mmu_seq = vcpu->kvm->mmu_notifier_seq;
+        /* implicit mb(), we'll read before PT lock is unlocked */
         pfn = gfn_to_pfn(vcpu->kvm, gfn);
         up_read(&current->mm->mmap_sem);
         if (is_error_pfn(pfn)) {
@@ -1365,12 +1456,19 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
                 return 1;
         }
         spin_lock(&vcpu->kvm->mmu_lock);
+        if (mmu_notifier_retry(vcpu, mmu_seq))
+                goto out_unlock;
         kvm_mmu_free_some_pages(vcpu);
         r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
                          largepage, gfn, pfn, kvm_x86_ops->get_tdp_level());
         spin_unlock(&vcpu->kvm->mmu_lock);
 
         return r;
+
+out_unlock:
+        spin_unlock(&vcpu->kvm->mmu_lock);
+        kvm_release_pfn_clean(pfn);
+        return 0;
 }
 
 static void nonpaging_free(struct kvm_vcpu *vcpu)
@@ -1670,6 +1768,8 @@ static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
                 gfn &= ~(KVM_PAGES_PER_HPAGE-1);
                 vcpu->arch.update_pte.largepage = 1;
         }
+        vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
+        /* implicit mb(), we'll read before PT lock is unlocked */
         pfn = gfn_to_pfn(vcpu->kvm, gfn);
         up_read(&current->mm->mmap_sem);
 
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 4d918220baeb..f72ac1fa35f0 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -263,6 +263,8 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
         pfn = vcpu->arch.update_pte.pfn;
         if (is_error_pfn(pfn))
                 return;
+        if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
+                return;
         kvm_get_pfn(pfn);
         mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
                      gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
@@ -380,6 +382,7 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
         int r;
         pfn_t pfn;
         int largepage = 0;
+        unsigned long mmu_seq;
 
         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
         kvm_mmu_audit(vcpu, "pre page fault");
@@ -413,6 +416,8 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
                         largepage = 1;
                 }
         }
+        mmu_seq = vcpu->kvm->mmu_notifier_seq;
+        /* implicit mb(), we'll read before PT lock is unlocked */
         pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
         up_read(&current->mm->mmap_sem);
 
@@ -424,6 +429,8 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
         }
 
         spin_lock(&vcpu->kvm->mmu_lock);
+        if (mmu_notifier_retry(vcpu, mmu_seq))
+                goto out_unlock;
         kvm_mmu_free_some_pages(vcpu);
         shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
                                   largepage, &write_pt, pfn);
@@ -439,6 +446,11 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
         spin_unlock(&vcpu->kvm->mmu_lock);
 
         return write_pt;
+
+out_unlock:
+        spin_unlock(&vcpu->kvm->mmu_lock);
+        kvm_release_pfn_clean(pfn);
+        return 0;
 }
 
 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 5916191420c7..0d682fc6aeb3 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -883,6 +883,7 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_PIT:
         case KVM_CAP_NOP_IO_DELAY:
         case KVM_CAP_MP_STATE:
+        case KVM_CAP_SYNC_MMU:
                 r = 1;
                 break;
         case KVM_CAP_COALESCED_MMIO:
@@ -1495,6 +1496,7 @@ static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
                 goto out;
 
         down_write(&kvm->slots_lock);
+        spin_lock(&kvm->mmu_lock);
 
         p = &kvm->arch.aliases[alias->slot];
         p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
@@ -1506,6 +1508,7 @@ static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
                         break;
         kvm->arch.naliases = n;
 
+        spin_unlock(&kvm->mmu_lock);
         kvm_mmu_zap_all(kvm);
 
         up_write(&kvm->slots_lock);
@@ -3972,16 +3975,23 @@ int kvm_arch_set_memory_region(struct kvm *kvm,
          */
         if (!user_alloc) {
                 if (npages && !old.rmap) {
+                        unsigned long userspace_addr;
+
                         down_write(&current->mm->mmap_sem);
-                        memslot->userspace_addr = do_mmap(NULL, 0,
-                                                     npages * PAGE_SIZE,
-                                                     PROT_READ | PROT_WRITE,
-                                                     MAP_SHARED | MAP_ANONYMOUS,
-                                                     0);
+                        userspace_addr = do_mmap(NULL, 0,
+                                                 npages * PAGE_SIZE,
+                                                 PROT_READ | PROT_WRITE,
+                                                 MAP_SHARED | MAP_ANONYMOUS,
+                                                 0);
                         up_write(&current->mm->mmap_sem);
 
-                        if (IS_ERR((void *)memslot->userspace_addr))
-                                return PTR_ERR((void *)memslot->userspace_addr);
+                        if (IS_ERR((void *)userspace_addr))
+                                return PTR_ERR((void *)userspace_addr);
+
+                        /* set userspace_addr atomically for kvm_hva_to_rmapp */
+                        spin_lock(&kvm->mmu_lock);
+                        memslot->userspace_addr = userspace_addr;
+                        spin_unlock(&kvm->mmu_lock);
                 } else {
                         if (!old.user_alloc && old.rmap) {
                                 int ret;
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 0313a5eec412..d9249a882aa5 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -1014,6 +1014,9 @@ __init void lguest_init(void)
         init_pg_tables_start = __pa(pg0);
         init_pg_tables_end = __pa(pg0);
 
+        /* As described in head_32.S, we map the first 128M of memory. */
+        max_pfn_mapped = (128*1024*1024) >> PAGE_SHIFT;
+
         /* Load the %fs segment register (the per-cpu segment register) with
          * the normal data segment to get through booting. */
         asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_DS) : "memory");
diff --git a/arch/x86/lib/copy_user_64.S b/arch/x86/lib/copy_user_64.S
index dfdf428975c0..f118c110af32 100644
--- a/arch/x86/lib/copy_user_64.S
+++ b/arch/x86/lib/copy_user_64.S
@@ -52,7 +52,7 @@
         jnz 100b
 102:
         .section .fixup,"ax"
-103:    addl %r8d,%edx                  /* ecx is zerorest also */
+103:    addl %ecx,%edx                  /* ecx is zerorest also */
         jmp copy_user_handle_tail
         .previous
 
diff --git a/arch/x86/lib/copy_user_nocache_64.S b/arch/x86/lib/copy_user_nocache_64.S
index 40e0e309d27e..cb0c112386fb 100644
--- a/arch/x86/lib/copy_user_nocache_64.S
+++ b/arch/x86/lib/copy_user_nocache_64.S
@@ -32,7 +32,7 @@
         jnz 100b
 102:
         .section .fixup,"ax"
-103:    addl %r8d,%edx                  /* ecx is zerorest also */
+103:    addl %ecx,%edx                  /* ecx is zerorest also */
         jmp copy_user_handle_tail
         .previous
 
@@ -108,7 +108,6 @@ ENTRY(__copy_user_nocache)
         jmp 60f
 50:     movl %ecx,%edx
 60:     sfence
-        movl %r8d,%ecx
         jmp copy_user_handle_tail
         .previous
 
diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c
index 3085f25b4355..007bb06c7504 100644
--- a/arch/x86/mm/gup.c
+++ b/arch/x86/mm/gup.c
@@ -223,14 +223,17 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
                         struct page **pages)
 {
         struct mm_struct *mm = current->mm;
-        unsigned long end = start + (nr_pages << PAGE_SHIFT);
-        unsigned long addr = start;
+        unsigned long addr, len, end;
         unsigned long next;
         pgd_t *pgdp;
         int nr = 0;
 
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+        end = start + len;
         if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
-                                        start, nr_pages*PAGE_SIZE)))
+                                        start, len)))
                 goto slow_irqon;
 
         /*
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index ff3a6a336342..4bdaa590375d 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -23,7 +23,8 @@ static void __devinit pci_fixup_i450nx(struct pci_dev *d)
                 pci_read_config_byte(d, reg++, &busno);
                 pci_read_config_byte(d, reg++, &suba);
                 pci_read_config_byte(d, reg++, &subb);
-                DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
+                dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
+                        suba, subb);
                 if (busno)
                         pci_scan_bus_with_sysdata(busno);       /* Bus A */
                 if (suba < subb)
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index a09505806b82..5807d1bc73f7 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -128,10 +128,8 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
                                 pr = pci_find_parent_resource(dev, r);
                                 if (!r->start || !pr ||
                                     request_resource(pr, r) < 0) {
-                                        printk(KERN_ERR "PCI: Cannot allocate "
-                                                "resource region %d "
-                                                "of bridge %s\n",
-                                                idx, pci_name(dev));
+                                        dev_err(&dev->dev, "BAR %d: can't "
+                                                "allocate resource\n", idx);
                                         /*
                                          * Something is wrong with the region.
                                          * Invalidate the resource to prevent
@@ -166,15 +164,15 @@ static void __init pcibios_allocate_resources(int pass)
                         else
                                 disabled = !(command & PCI_COMMAND_MEMORY);
                         if (pass == disabled) {
-                                DBG("PCI: Resource %08lx-%08lx "
-                                    "(f=%lx, d=%d, p=%d)\n",
-                                    r->start, r->end, r->flags, disabled, pass);
+                                dev_dbg(&dev->dev, "resource %#08llx-%#08llx "
+                                        "(f=%lx, d=%d, p=%d)\n",
+                                        (unsigned long long) r->start,
+                                        (unsigned long long) r->end,
+                                        r->flags, disabled, pass);
                                 pr = pci_find_parent_resource(dev, r);
                                 if (!pr || request_resource(pr, r) < 0) {
-                                        printk(KERN_ERR "PCI: Cannot allocate "
-                                                "resource region %d "
-                                                "of device %s\n",
-                                                idx, pci_name(dev));
+                                        dev_err(&dev->dev, "BAR %d: can't "
+                                                "allocate resource\n", idx);
                                         /* We'll assign a new address later */
                                         r->end -= r->start;
                                         r->start = 0;
@@ -187,8 +185,7 @@ static void __init pcibios_allocate_resources(int pass)
                                 /* Turn the ROM off, leave the resource region,
                                  * but keep it unregistered. */
                                 u32 reg;
-                                DBG("PCI: Switching off ROM of %s\n",
-                                        pci_name(dev));
+                                dev_dbg(&dev->dev, "disabling ROM\n");
                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
                                 pci_read_config_dword(dev,
                                                 dev->rom_base_reg, &reg);
@@ -257,8 +254,7 @@ void pcibios_set_master(struct pci_dev *dev)
                 lat = pcibios_max_latency;
         else
                 return;
-        printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
-                pci_name(dev), lat);
+        dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 }
 
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 6a06a2eb0597..fec0123b33a9 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -436,7 +436,7 @@ static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
 {
         WARN_ON_ONCE(pirq >= 9);
         if (pirq > 8) {
-                printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
+                dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
                 return 0;
         }
         return read_config_nybble(router, 0x74, pirq-1);
@@ -446,7 +446,7 @@ static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
 {
         WARN_ON_ONCE(pirq >= 9);
         if (pirq > 8) {
-                printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
+                dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
                 return 0;
         }
         write_config_nybble(router, 0x74, pirq-1, irq);
@@ -492,15 +492,17 @@ static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq
         irq = 0;
         if (pirq <= 4)
                 irq = read_config_nybble(router, 0x56, pirq - 1);
-        printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
-                dev->vendor, dev->device, pirq, irq);
+        dev_info(&dev->dev,
+                 "AMD756: dev [%04x/%04x], router PIRQ %d get IRQ %d\n",
+                 dev->vendor, dev->device, pirq, irq);
         return irq;
 }
 
 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
 {
-        printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
-                dev->vendor, dev->device, pirq, irq);
+        dev_info(&dev->dev,
+                 "AMD756: dev [%04x/%04x], router PIRQ %d set IRQ %d\n",
+                 dev->vendor, dev->device, pirq, irq);
         if (pirq <= 4)
                 write_config_nybble(router, 0x56, pirq - 1, irq);
         return 1;
@@ -730,7 +732,6 @@ static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router,
         switch (device) {
         case PCI_DEVICE_ID_AL_M1533:
         case PCI_DEVICE_ID_AL_M1563:
-                printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n");
                 r->name = "ALI";
                 r->get = pirq_ali_get;
                 r->set = pirq_ali_set;
@@ -840,11 +841,9 @@ static void __init pirq_find_router(struct irq_router *r)
                         h->probe(r, pirq_router_dev, pirq_router_dev->device))
                         break;
         }
-        printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
-                pirq_router.name,
-                pirq_router_dev->vendor,
-                pirq_router_dev->device,
-                pci_name(pirq_router_dev));
+        dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x/%04x]\n",
+                 pirq_router.name,
+                 pirq_router_dev->vendor, pirq_router_dev->device);
 
         /* The device remains referenced for the kernel lifetime */
 }
@@ -877,7 +876,7 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
         /* Find IRQ pin */
         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
         if (!pin) {
-                DBG(KERN_DEBUG " -> no interrupt pin\n");
+                dev_dbg(&dev->dev, "no interrupt pin\n");
                 return 0;
         }
         pin = pin - 1;
@@ -887,20 +886,20 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
         if (!pirq_table)
                 return 0;
 
-        DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin);
         info = pirq_get_info(dev);
         if (!info) {
-                DBG(" -> not found in routing table\n" KERN_DEBUG);
+                dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
+                        'A' + pin);
                 return 0;
         }
         pirq = info->irq[pin].link;
         mask = info->irq[pin].bitmap;
         if (!pirq) {
-                DBG(" -> not routed\n" KERN_DEBUG);
+                dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin);
                 return 0;
         }
-        DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask,
-                pirq_table->exclusive_irqs);
+        dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
+                'A' + pin, pirq, mask, pirq_table->exclusive_irqs);
         mask &= pcibios_irq_mask;
 
         /* Work around broken HP Pavilion Notebooks which assign USB to
@@ -930,10 +929,8 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
                 if (pci_probe & PCI_USE_PIRQ_MASK)
                         newirq = 0;
                 else
-                        printk("\n" KERN_WARNING
-                                "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n"
-                                KERN_DEBUG, newirq,
-                                pci_name(dev));
+                        dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
+                                 "%#x; try pci=usepirqmask\n", newirq, mask);
         }
         if (!newirq && assign) {
                 for (i = 0; i < 16; i++) {
@@ -944,39 +941,35 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
                                 newirq = i;
                 }
         }
-        DBG(" -> newirq=%d", newirq);
+        dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin, newirq);
 
         /* Check if it is hardcoded */
         if ((pirq & 0xf0) == 0xf0) {
                 irq = pirq & 0xf;
-                DBG(" -> hardcoded IRQ %d\n", irq);
-                msg = "Hardcoded";
+                msg = "hardcoded";
         } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
         ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
-                DBG(" -> got IRQ %d\n", irq);
-                msg = "Found";
+                msg = "found";
                 eisa_set_level_irq(irq);
         } else if (newirq && r->set &&
                 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
-                DBG(" -> assigning IRQ %d", newirq);
                 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
                         eisa_set_level_irq(newirq);
-                        DBG(" ... OK\n");
-                        msg = "Assigned";
+                        msg = "assigned";
                         irq = newirq;
                 }
         }
 
         if (!irq) {
-                DBG(" ... failed\n");
                 if (newirq && mask == (1 << newirq)) {
-                        msg = "Guessed";
+                        msg = "guessed";
                         irq = newirq;
-                } else
+                } else {
+                        dev_dbg(&dev->dev, "can't route interrupt\n");
                         return 0;
+                }
         }
-        printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq,
-                pci_name(dev));
+        dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin, irq);
 
         /* Update IRQ for all devices with the same pirq value */
         while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
@@ -996,17 +989,17 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
                         (!(pci_probe & PCI_USE_PIRQ_MASK) || \
                         ((1 << dev2->irq) & mask))) {
 #ifndef CONFIG_PCI_MSI
-                                printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
-                                       pci_name(dev2), dev2->irq, irq);
+                                dev_info(&dev2->dev, "IRQ routing conflict: "
+                                         "have IRQ %d, want IRQ %d\n",
+                                         dev2->irq, irq);
 #endif
                                 continue;
                         }
                         dev2->irq = irq;
                         pirq_penalty[irq]++;
                         if (dev != dev2)
-                                printk(KERN_INFO
-                                        "PCI: Sharing IRQ %d with %s\n",
-                                        irq, pci_name(dev2));
+                                dev_info(&dev->dev, "sharing IRQ %d with %s\n",
+                                         irq, pci_name(dev2));
                 }
         }
         return 1;
@@ -1025,8 +1018,7 @@ static void __init pcibios_fixup_irqs(void)
                  * already in use.
                  */
                 if (dev->irq >= 16) {
-                        DBG(KERN_DEBUG "%s: ignoring bogus IRQ %d\n",
-                                pci_name(dev), dev->irq);
+                        dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
                         dev->irq = 0;
                 }
                 /*
@@ -1070,12 +1062,12 @@ static void __init pcibios_fixup_irqs(void)
                                         irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
                                                         PCI_SLOT(bridge->devfn), pin);
                                         if (irq >= 0)
-                                                printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
-                                                        pci_name(bridge), 'A' + pin, irq);
+                                                dev_warn(&dev->dev, "using bridge %s INT %c to get IRQ %d\n",
+                                                         pci_name(bridge),
+                                                         'A' + pin, irq);
                                 }
                                 if (irq >= 0) {
-                                        printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
-                                                pci_name(dev), 'A' + pin, irq);
+                                        dev_info(&dev->dev, "PCI->APIC IRQ transform: INT %c -> IRQ %d\n", 'A' + pin, irq);
                                         dev->irq = irq;
                                 }
                         }
@@ -1231,25 +1223,24 @@ static int pirq_enable_irq(struct pci_dev *dev)
                                 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
                                                 PCI_SLOT(bridge->devfn), pin);
                                 if (irq >= 0)
-                                        printk(KERN_WARNING
-                                                "PCI: using PPB %s[%c] to get irq %d\n",
-                                                pci_name(bridge),
-                                                'A' + pin, irq);
+                                        dev_warn(&dev->dev, "using bridge %s "
+                                                 "INT %c to get IRQ %d\n",
+                                                 pci_name(bridge), 'A' + pin,
+                                                 irq);
                                 dev = bridge;
                         }
                         dev = temp_dev;
                         if (irq >= 0) {
-                                printk(KERN_INFO
-                                        "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
-                                        pci_name(dev), 'A' + pin, irq);
+                                dev_info(&dev->dev, "PCI->APIC IRQ transform: "
+                                         "INT %c -> IRQ %d\n", 'A' + pin, irq);
                                 dev->irq = irq;
                                 return 0;
                         } else
-                                msg = " Probably buggy MP table.";
+                                msg = "; probably buggy MP table";
                 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
                         msg = "";
                 else
-                        msg = " Please try using pci=biosirq.";
+                        msg = "; please try using pci=biosirq";
 
                 /*
                  * With IDE legacy devices the IRQ lookup failure is not
@@ -1259,9 +1250,8 @@ static int pirq_enable_irq(struct pci_dev *dev)
                                 !(dev->class & 0x5))
                         return 0;
 
-                printk(KERN_WARNING
-                        "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
-                        'A' + pin, pci_name(dev), msg);
+                dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
+                         'A' + pin, msg);
         }
         return 0;
 }
diff --git a/arch/x86/pci/numaq_32.c b/arch/x86/pci/numaq_32.c
index f4b16dc11dad..1177845d3186 100644
--- a/arch/x86/pci/numaq_32.c
+++ b/arch/x86/pci/numaq_32.c
@@ -131,13 +131,14 @@ static void __devinit pci_fixup_i450nx(struct pci_dev *d)
         u8 busno, suba, subb;
         int quad = BUS2QUAD(d->bus->number);
 
-        printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
+        dev_info(&d->dev, "searching for i450NX host bridges\n");
         reg = 0xd0;
         for(pxb=0; pxb<2; pxb++) {
                 pci_read_config_byte(d, reg++, &busno);
                 pci_read_config_byte(d, reg++, &suba);
                 pci_read_config_byte(d, reg++, &subb);
-                DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
+                dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
+                        pxb, busno, suba, subb);
                 if (busno) {
                         /* Bus A */
                         pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
diff --git a/arch/xtensa/kernel/xtensa_ksyms.c b/arch/xtensa/kernel/xtensa_ksyms.c
index 6e52cdd6166f..c9a7c5b74a0d 100644
--- a/arch/xtensa/kernel/xtensa_ksyms.c
+++ b/arch/xtensa/kernel/xtensa_ksyms.c
@@ -18,7 +18,6 @@
 #include <linux/interrupt.h>
 #include <asm/irq.h>
 #include <linux/in6.h>
-#include <linux/ide.h>
 
 #include <asm/uaccess.h>
 #include <asm/checksum.h>