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authorPaul Mackerras <paulus@samba.org>2008-04-17 23:34:30 -0400
committerPaul Mackerras <paulus@samba.org>2008-04-17 23:34:30 -0400
commit11a55f2274bf0d719e4dd05f4ac5e89a15740211 (patch)
tree0886a988b43e280fe00e529155f8cd796e7edcc8 /arch
parent858c52d15f186e055dc33a1872f5b45a66d42296 (diff)
parent1a9ebc0cd2b3bb4450834e564722630fbc40611b (diff)
Merge branch 'powerpc-next' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/Kconfig5
-rw-r--r--arch/powerpc/Kconfig.debug2
-rw-r--r--arch/powerpc/boot/cpm-serial.c117
-rw-r--r--arch/powerpc/boot/cuboot-pq2.c27
-rw-r--r--arch/powerpc/boot/devtree.c20
-rw-r--r--arch/powerpc/boot/dts/ep8248e.dts5
-rw-r--r--arch/powerpc/boot/dts/ep88xc.dts73
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts83
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts83
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts97
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts132
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts7
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts173
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts161
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts299
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts289
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts161
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts209
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts291
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts383
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts58
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts77
-rw-r--r--arch/powerpc/boot/dts/pq2fads.dts126
-rw-r--r--arch/powerpc/boot/dts/sbc8641d.dts352
-rw-r--r--arch/powerpc/boot/mpc52xx-psc.c9
-rw-r--r--arch/powerpc/boot/ns16550.c10
-rw-r--r--arch/powerpc/boot/ops.h1
-rw-r--r--arch/powerpc/configs/83xx/mpc8313_rdb_defconfig (renamed from arch/powerpc/configs/mpc8313_rdb_defconfig)8
-rw-r--r--arch/powerpc/configs/83xx/mpc8315_rdb_defconfig (renamed from arch/powerpc/configs/mpc8315_rdb_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc832x_mds_defconfig (renamed from arch/powerpc/configs/mpc832x_mds_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc832x_rdb_defconfig (renamed from arch/powerpc/configs/mpc832x_rdb_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc834x_itx_defconfig (renamed from arch/powerpc/configs/mpc834x_itx_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig (renamed from arch/powerpc/configs/mpc834x_itxgp_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc834x_mds_defconfig (renamed from arch/powerpc/configs/mpc834x_mds_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc836x_mds_defconfig (renamed from arch/powerpc/configs/mpc836x_mds_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc837x_mds_defconfig (renamed from arch/powerpc/configs/mpc837x_mds_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/mpc837x_rdb_defconfig (renamed from arch/powerpc/configs/mpc837x_rdb_defconfig)0
-rw-r--r--arch/powerpc/configs/83xx/sbc834x_defconfig (renamed from arch/powerpc/configs/sbc834x_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/ksi8560_defconfig (renamed from arch/powerpc/configs/ksi8560_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/mpc8540_ads_defconfig (renamed from arch/powerpc/configs/mpc8540_ads_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/mpc8544_ds_defconfig (renamed from arch/powerpc/configs/mpc8544_ds_defconfig)17
-rw-r--r--arch/powerpc/configs/85xx/mpc8560_ads_defconfig (renamed from arch/powerpc/configs/mpc8560_ads_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/mpc8568mds_defconfig (renamed from arch/powerpc/configs/mpc8568mds_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/mpc8572_ds_defconfig (renamed from arch/powerpc/configs/mpc8572_ds_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/mpc85xx_cds_defconfig (renamed from arch/powerpc/configs/mpc85xx_cds_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/sbc8548_defconfig (renamed from arch/powerpc/configs/sbc8548_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/sbc8560_defconfig (renamed from arch/powerpc/configs/sbc8560_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/stx_gp3_defconfig (renamed from arch/powerpc/configs/stx_gp3_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/tqm8540_defconfig (renamed from arch/powerpc/configs/tqm8540_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/tqm8541_defconfig (renamed from arch/powerpc/configs/tqm8541_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/tqm8555_defconfig (renamed from arch/powerpc/configs/tqm8555_defconfig)0
-rw-r--r--arch/powerpc/configs/85xx/tqm8560_defconfig (renamed from arch/powerpc/configs/tqm8560_defconfig)0
-rw-r--r--arch/powerpc/configs/mpc83xx_defconfig164
-rw-r--r--arch/powerpc/configs/sbc8641d_defconfig1342
-rw-r--r--arch/powerpc/kernel/entry_32.S30
-rw-r--r--arch/powerpc/kernel/head_44x.S4
-rw-r--r--arch/powerpc/kernel/head_booke.h33
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S10
-rw-r--r--arch/powerpc/lib/rheap.c4
-rw-r--r--arch/powerpc/platforms/82xx/Kconfig3
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_rdb.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h2
-rw-r--r--arch/powerpc/platforms/83xx/usb.c12
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig8
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c2
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c13
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig8
-rw-r--r--arch/powerpc/platforms/86xx/Makefile1
-rw-r--r--arch/powerpc/platforms/86xx/mpc8610_hpcd.c4
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c14
-rw-r--r--arch/powerpc/platforms/86xx/sbc8641d.c164
-rw-r--r--arch/powerpc/platforms/8xx/Kconfig4
-rw-r--r--arch/powerpc/platforms/Kconfig8
-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/cpm1.c112
-rw-r--r--arch/powerpc/sysdev/cpm2.c103
-rw-r--r--arch/powerpc/sysdev/cpm_common.c3
-rw-r--r--arch/powerpc/sysdev/fsl_lbc.c129
-rw-r--r--arch/powerpc/sysdev/fsl_soc.c611
-rw-r--r--arch/powerpc/sysdev/fsl_soc.h1
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe.c13
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_io.c5
85 files changed, 3816 insertions, 2278 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index d1fe425cfb58..7f2f126d1c2b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -520,6 +520,11 @@ config FSL_PCI
520config 4xx_SOC 520config 4xx_SOC
521 bool 521 bool
522 522
523config FSL_LBC
524 bool
525 help
526 Freescale Localbus support
527
523# Yes MCA RS/6000s exist but Linux-PPC does not currently support any 528# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
524config MCA 529config MCA
525 bool 530 bool
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index db7cc34c24d4..a86d8d853214 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -269,7 +269,7 @@ config PPC_EARLY_DEBUG_CPM_ADDR
269 hex "CPM UART early debug transmit descriptor address" 269 hex "CPM UART early debug transmit descriptor address"
270 depends on PPC_EARLY_DEBUG_CPM 270 depends on PPC_EARLY_DEBUG_CPM
271 default "0xfa202008" if PPC_EP88XC 271 default "0xfa202008" if PPC_EP88XC
272 default "0xf0000008" if CPM2 272 default "0xf0001ff8" if CPM2
273 default "0xff002008" if CPM1 273 default "0xff002008" if CPM1
274 help 274 help
275 This specifies the address of the transmit descriptor 275 This specifies the address of the transmit descriptor
diff --git a/arch/powerpc/boot/cpm-serial.c b/arch/powerpc/boot/cpm-serial.c
index 28296facb2ae..19dc15abe43d 100644
--- a/arch/powerpc/boot/cpm-serial.c
+++ b/arch/powerpc/boot/cpm-serial.c
@@ -11,6 +11,7 @@
11#include "types.h" 11#include "types.h"
12#include "io.h" 12#include "io.h"
13#include "ops.h" 13#include "ops.h"
14#include "page.h"
14 15
15struct cpm_scc { 16struct cpm_scc {
16 u32 gsmrl; 17 u32 gsmrl;
@@ -42,6 +43,22 @@ struct cpm_param {
42 u16 tbase; 43 u16 tbase;
43 u8 rfcr; 44 u8 rfcr;
44 u8 tfcr; 45 u8 tfcr;
46 u16 mrblr;
47 u32 rstate;
48 u8 res1[4];
49 u16 rbptr;
50 u8 res2[6];
51 u32 tstate;
52 u8 res3[4];
53 u16 tbptr;
54 u8 res4[6];
55 u16 maxidl;
56 u16 idlc;
57 u16 brkln;
58 u16 brkec;
59 u16 brkcr;
60 u16 rmask;
61 u8 res5[4];
45}; 62};
46 63
47struct cpm_bd { 64struct cpm_bd {
@@ -54,10 +71,10 @@ static void *cpcr;
54static struct cpm_param *param; 71static struct cpm_param *param;
55static struct cpm_smc *smc; 72static struct cpm_smc *smc;
56static struct cpm_scc *scc; 73static struct cpm_scc *scc;
57struct cpm_bd *tbdf, *rbdf; 74static struct cpm_bd *tbdf, *rbdf;
58static u32 cpm_cmd; 75static u32 cpm_cmd;
59static u8 *muram_start; 76static void *cbd_addr;
60static u32 muram_offset; 77static u32 cbd_offset;
61 78
62static void (*do_cmd)(int op); 79static void (*do_cmd)(int op);
63static void (*enable_port)(void); 80static void (*enable_port)(void);
@@ -119,20 +136,25 @@ static int cpm_serial_open(void)
119 136
120 out_8(&param->rfcr, 0x10); 137 out_8(&param->rfcr, 0x10);
121 out_8(&param->tfcr, 0x10); 138 out_8(&param->tfcr, 0x10);
122 139 out_be16(&param->mrblr, 1);
123 rbdf = (struct cpm_bd *)muram_start; 140 out_be16(&param->maxidl, 0);
124 rbdf->addr = (u8 *)(rbdf + 2); 141 out_be16(&param->brkec, 0);
142 out_be16(&param->brkln, 0);
143 out_be16(&param->brkcr, 0);
144
145 rbdf = cbd_addr;
146 rbdf->addr = (u8 *)rbdf - 1;
125 rbdf->sc = 0xa000; 147 rbdf->sc = 0xa000;
126 rbdf->len = 1; 148 rbdf->len = 1;
127 149
128 tbdf = rbdf + 1; 150 tbdf = rbdf + 1;
129 tbdf->addr = (u8 *)(rbdf + 2) + 1; 151 tbdf->addr = (u8 *)rbdf - 2;
130 tbdf->sc = 0x2000; 152 tbdf->sc = 0x2000;
131 tbdf->len = 1; 153 tbdf->len = 1;
132 154
133 sync(); 155 sync();
134 out_be16(&param->rbase, muram_offset); 156 out_be16(&param->rbase, cbd_offset);
135 out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd)); 157 out_be16(&param->tbase, cbd_offset + sizeof(struct cpm_bd));
136 158
137 do_cmd(CPM_CMD_INIT_RX_TX); 159 do_cmd(CPM_CMD_INIT_RX_TX);
138 160
@@ -175,10 +197,12 @@ static unsigned char cpm_serial_getc(void)
175 197
176int cpm_console_init(void *devp, struct serial_console_data *scdp) 198int cpm_console_init(void *devp, struct serial_console_data *scdp)
177{ 199{
178 void *reg_virt[2]; 200 void *vreg[2];
179 int is_smc = 0, is_cpm2 = 0, n; 201 u32 reg[2];
180 unsigned long reg_phys; 202 int is_smc = 0, is_cpm2 = 0;
181 void *parent, *muram; 203 void *parent, *muram;
204 void *muram_addr;
205 unsigned long muram_offset, muram_size;
182 206
183 if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) { 207 if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
184 is_smc = 1; 208 is_smc = 1;
@@ -202,63 +226,64 @@ int cpm_console_init(void *devp, struct serial_console_data *scdp)
202 else 226 else
203 do_cmd = cpm1_cmd; 227 do_cmd = cpm1_cmd;
204 228
205 n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4); 229 if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
206 if (n < 4)
207 return -1; 230 return -1;
208 231
209 n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt)); 232 if (dt_get_virtual_reg(devp, vreg, 2) < 2)
210 if (n < (int)sizeof(reg_virt)) { 233 return -1;
211 for (n = 0; n < 2; n++) {
212 if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
213 return -1;
214
215 reg_virt[n] = (void *)reg_phys;
216 }
217 }
218 234
219 if (is_smc) 235 if (is_smc)
220 smc = reg_virt[0]; 236 smc = vreg[0];
221 else 237 else
222 scc = reg_virt[0]; 238 scc = vreg[0];
223 239
224 param = reg_virt[1]; 240 param = vreg[1];
225 241
226 parent = get_parent(devp); 242 parent = get_parent(devp);
227 if (!parent) 243 if (!parent)
228 return -1; 244 return -1;
229 245
230 n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt)); 246 if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
231 if (n < (int)sizeof(reg_virt)) { 247 return -1;
232 if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
233 return -1;
234
235 reg_virt[0] = (void *)reg_phys;
236 }
237
238 cpcr = reg_virt[0];
239 248
240 muram = finddevice("/soc/cpm/muram/data"); 249 muram = finddevice("/soc/cpm/muram/data");
241 if (!muram) 250 if (!muram)
242 return -1; 251 return -1;
243 252
244 /* For bootwrapper-compatible device trees, we assume that the first 253 /* For bootwrapper-compatible device trees, we assume that the first
245 * entry has at least 18 bytes, and that #address-cells/#data-cells 254 * entry has at least 128 bytes, and that #address-cells/#data-cells
246 * is one for both parent and child. 255 * is one for both parent and child.
247 */ 256 */
248 257
249 n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt)); 258 if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
250 if (n < (int)sizeof(reg_virt)) { 259 return -1;
251 if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
252 return -1;
253 260
254 reg_virt[0] = (void *)reg_phys; 261 if (getprop(muram, "reg", reg, 8) < 8)
255 } 262 return -1;
256 263
257 muram_start = reg_virt[0]; 264 muram_offset = reg[0];
265 muram_size = reg[1];
258 266
259 n = getprop(muram, "reg", &muram_offset, 4); 267 /* Store the buffer descriptors at the end of the first muram chunk.
260 if (n < 4) 268 * For SMC ports on CPM2-based platforms, relocate the parameter RAM
261 return -1; 269 * just before the buffer descriptors.
270 */
271
272 cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
273
274 if (is_cpm2 && is_smc) {
275 u16 *smc_base = (u16 *)param;
276 u16 pram_offset;
277
278 pram_offset = cbd_offset - 64;
279 pram_offset = _ALIGN_DOWN(pram_offset, 64);
280
281 disable_port();
282 out_be16(smc_base, pram_offset);
283 param = muram_addr - muram_offset + pram_offset;
284 }
285
286 cbd_addr = muram_addr - muram_offset + cbd_offset;
262 287
263 scdp->open = cpm_serial_open; 288 scdp->open = cpm_serial_open;
264 scdp->putc = cpm_serial_putc; 289 scdp->putc = cpm_serial_putc;
diff --git a/arch/powerpc/boot/cuboot-pq2.c b/arch/powerpc/boot/cuboot-pq2.c
index f56ac6cae9f3..9c7d13428293 100644
--- a/arch/powerpc/boot/cuboot-pq2.c
+++ b/arch/powerpc/boot/cuboot-pq2.c
@@ -128,7 +128,7 @@ static void fixup_pci(void)
128 u8 *soc_regs; 128 u8 *soc_regs;
129 int i, len; 129 int i, len;
130 void *node, *parent_node; 130 void *node, *parent_node;
131 u32 naddr, nsize, mem_log2; 131 u32 naddr, nsize, mem_pow2, mem_mask;
132 132
133 node = finddevice("/pci"); 133 node = finddevice("/pci");
134 if (!node || !dt_is_compatible(node, "fsl,pq2-pci")) 134 if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
@@ -141,7 +141,7 @@ static void fixup_pci(void)
141 141
142 soc_regs = (u8 *)fsl_get_immr(); 142 soc_regs = (u8 *)fsl_get_immr();
143 if (!soc_regs) 143 if (!soc_regs)
144 goto err; 144 goto unhandled;
145 145
146 dt_get_reg_format(node, &naddr, &nsize); 146 dt_get_reg_format(node, &naddr, &nsize);
147 if (naddr != 3 || nsize != 2) 147 if (naddr != 3 || nsize != 2)
@@ -153,7 +153,7 @@ static void fixup_pci(void)
153 153
154 dt_get_reg_format(parent_node, &naddr, &nsize); 154 dt_get_reg_format(parent_node, &naddr, &nsize);
155 if (naddr != 1 || nsize != 1) 155 if (naddr != 1 || nsize != 1)
156 goto err; 156 goto unhandled;
157 157
158 len = getprop(node, "ranges", pci_ranges_buf, 158 len = getprop(node, "ranges", pci_ranges_buf,
159 sizeof(pci_ranges_buf)); 159 sizeof(pci_ranges_buf));
@@ -170,14 +170,20 @@ static void fixup_pci(void)
170 } 170 }
171 171
172 if (!mem || !mmio || !io) 172 if (!mem || !mmio || !io)
173 goto err; 173 goto unhandled;
174 if (mem->size[1] != mmio->size[1])
175 goto unhandled;
176 if (mem->size[1] & (mem->size[1] - 1))
177 goto unhandled;
178 if (io->size[1] & (io->size[1] - 1))
179 goto unhandled;
174 180
175 if (mem->phys_addr + mem->size[1] == mmio->phys_addr) 181 if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
176 mem_base = mem; 182 mem_base = mem;
177 else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr) 183 else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
178 mem_base = mmio; 184 mem_base = mmio;
179 else 185 else
180 goto err; 186 goto unhandled;
181 187
182 out_be32(&pci_regs[1][0], mem_base->phys_addr | 1); 188 out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
183 out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1)); 189 out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
@@ -201,8 +207,9 @@ static void fixup_pci(void)
201 out_le32(&pci_regs[0][58], 0); 207 out_le32(&pci_regs[0][58], 0);
202 out_le32(&pci_regs[0][60], 0); 208 out_le32(&pci_regs[0][60], 0);
203 209
204 mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1); 210 mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
205 out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1)); 211 mem_mask = ~(mem_pow2 - 1) >> 12;
212 out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
206 213
207 /* If PCI is disabled, drive RST high to enable. */ 214 /* If PCI is disabled, drive RST high to enable. */
208 if (!(in_le32(&pci_regs[0][32]) & 1)) { 215 if (!(in_le32(&pci_regs[0][32]) & 1)) {
@@ -228,7 +235,11 @@ static void fixup_pci(void)
228 return; 235 return;
229 236
230err: 237err:
231 printf("Bad PCI node\r\n"); 238 printf("Bad PCI node -- using existing firmware setup.\r\n");
239 return;
240
241unhandled:
242 printf("Unsupported PCI node -- using existing firmware setup.\r\n");
232} 243}
233 244
234static void pq2_platform_fixups(void) 245static void pq2_platform_fixups(void)
diff --git a/arch/powerpc/boot/devtree.c b/arch/powerpc/boot/devtree.c
index 60f561e307a9..5d12336dc360 100644
--- a/arch/powerpc/boot/devtree.c
+++ b/arch/powerpc/boot/devtree.c
@@ -350,3 +350,23 @@ int dt_is_compatible(void *node, const char *compat)
350 350
351 return 0; 351 return 0;
352} 352}
353
354int dt_get_virtual_reg(void *node, void **addr, int nres)
355{
356 unsigned long xaddr;
357 int n;
358
359 n = getprop(node, "virtual-reg", addr, nres * 4);
360 if (n > 0)
361 return n / 4;
362
363 for (n = 0; n < nres; n++) {
364 if (!dt_xlate_reg(node, n, &xaddr, NULL))
365 break;
366
367 addr[n] = (void *)xaddr;
368 }
369
370 return n;
371}
372
diff --git a/arch/powerpc/boot/dts/ep8248e.dts b/arch/powerpc/boot/dts/ep8248e.dts
index 5d2fb76a72c1..756758fb5b7b 100644
--- a/arch/powerpc/boot/dts/ep8248e.dts
+++ b/arch/powerpc/boot/dts/ep8248e.dts
@@ -121,8 +121,7 @@
121 121
122 data@0 { 122 data@0 {
123 compatible = "fsl,cpm-muram-data"; 123 compatible = "fsl,cpm-muram-data";
124 reg = <0 0x1100 0x1140 124 reg = <0 0x2000 0x9800 0x800>;
125 0xec0 0x9800 0x800>;
126 }; 125 };
127 }; 126 };
128 127
@@ -138,7 +137,7 @@
138 device_type = "serial"; 137 device_type = "serial";
139 compatible = "fsl,mpc8248-smc-uart", 138 compatible = "fsl,mpc8248-smc-uart",
140 "fsl,cpm2-smc-uart"; 139 "fsl,cpm2-smc-uart";
141 reg = <0x11a80 0x20 0x1100 0x40>; 140 reg = <0x11a80 0x20 0x87fc 2>;
142 interrupts = <4 8>; 141 interrupts = <4 8>;
143 interrupt-parent = <&PIC>; 142 interrupt-parent = <&PIC>;
144 fsl,cpm-brg = <7>; 143 fsl,cpm-brg = <7>;
diff --git a/arch/powerpc/boot/dts/ep88xc.dts b/arch/powerpc/boot/dts/ep88xc.dts
index 02705f299790..ae57d6240120 100644
--- a/arch/powerpc/boot/dts/ep88xc.dts
+++ b/arch/powerpc/boot/dts/ep88xc.dts
@@ -2,7 +2,7 @@
2 * EP88xC Device Tree Source 2 * EP88xC Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2007 Freescale Semiconductor, Inc. 5 * Copyright 2007,2008 Freescale Semiconductor, Inc.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -10,6 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
13 14
14/ { 15/ {
15 model = "EP88xC"; 16 model = "EP88xC";
@@ -23,44 +24,44 @@
23 24
24 PowerPC,885@0 { 25 PowerPC,885@0 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 reg = <0>; 27 reg = <0x0>;
27 d-cache-line-size = <d#16>; 28 d-cache-line-size = <16>;
28 i-cache-line-size = <d#16>; 29 i-cache-line-size = <16>;
29 d-cache-size = <d#8192>; 30 d-cache-size = <8192>;
30 i-cache-size = <d#8192>; 31 i-cache-size = <8192>;
31 timebase-frequency = <0>; 32 timebase-frequency = <0>;
32 bus-frequency = <0>; 33 bus-frequency = <0>;
33 clock-frequency = <0>; 34 clock-frequency = <0>;
34 interrupts = <f 2>; // decrementer interrupt 35 interrupts = <15 2>; // decrementer interrupt
35 interrupt-parent = <&PIC>; 36 interrupt-parent = <&PIC>;
36 }; 37 };
37 }; 38 };
38 39
39 memory { 40 memory {
40 device_type = "memory"; 41 device_type = "memory";
41 reg = <0 0>; 42 reg = <0x0 0x0>;
42 }; 43 };
43 44
44 localbus@fa200100 { 45 localbus@fa200100 {
45 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; 46 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
46 #address-cells = <2>; 47 #address-cells = <2>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 reg = <fa200100 40>; 49 reg = <0xfa200100 0x40>;
49 50
50 ranges = < 51 ranges = <
51 0 0 fc000000 04000000 52 0x0 0x0 0xfc000000 0x4000000
52 3 0 fa000000 01000000 53 0x3 0x0 0xfa000000 0x1000000
53 >; 54 >;
54 55
55 flash@0,2000000 { 56 flash@0,2000000 {
56 compatible = "cfi-flash"; 57 compatible = "cfi-flash";
57 reg = <0 2000000 2000000>; 58 reg = <0x0 0x2000000 0x2000000>;
58 bank-width = <4>; 59 bank-width = <4>;
59 device-width = <2>; 60 device-width = <2>;
60 }; 61 };
61 62
62 board-control@3,400000 { 63 board-control@3,400000 {
63 reg = <3 400000 10>; 64 reg = <0x3 0x400000 0x10>;
64 compatible = "fsl,ep88xc-bcsr"; 65 compatible = "fsl,ep88xc-bcsr";
65 }; 66 };
66 }; 67 };
@@ -70,25 +71,25 @@
70 #address-cells = <1>; 71 #address-cells = <1>;
71 #size-cells = <1>; 72 #size-cells = <1>;
72 device_type = "soc"; 73 device_type = "soc";
73 ranges = <0 fa200000 00004000>; 74 ranges = <0x0 0xfa200000 0x4000>;
74 bus-frequency = <0>; 75 bus-frequency = <0>;
75 76
76 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 77 // Temporary -- will go away once kernel uses ranges for get_immrbase().
77 reg = <fa200000 4000>; 78 reg = <0xfa200000 0x4000>;
78 79
79 mdio@e00 { 80 mdio@e00 {
80 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; 81 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
81 reg = <e00 188>; 82 reg = <0xe00 0x188>;
82 #address-cells = <1>; 83 #address-cells = <1>;
83 #size-cells = <0>; 84 #size-cells = <0>;
84 85
85 PHY0: ethernet-phy@0 { 86 PHY0: ethernet-phy@0 {
86 reg = <0>; 87 reg = <0x0>;
87 device_type = "ethernet-phy"; 88 device_type = "ethernet-phy";
88 }; 89 };
89 90
90 PHY1: ethernet-phy@1 { 91 PHY1: ethernet-phy@1 {
91 reg = <1>; 92 reg = <0x1>;
92 device_type = "ethernet-phy"; 93 device_type = "ethernet-phy";
93 }; 94 };
94 }; 95 };
@@ -97,7 +98,7 @@
97 device_type = "network"; 98 device_type = "network";
98 compatible = "fsl,mpc885-fec-enet", 99 compatible = "fsl,mpc885-fec-enet",
99 "fsl,pq1-fec-enet"; 100 "fsl,pq1-fec-enet";
100 reg = <e00 188>; 101 reg = <0xe00 0x188>;
101 local-mac-address = [ 00 00 00 00 00 00 ]; 102 local-mac-address = [ 00 00 00 00 00 00 ];
102 interrupts = <3 1>; 103 interrupts = <3 1>;
103 interrupt-parent = <&PIC>; 104 interrupt-parent = <&PIC>;
@@ -109,7 +110,7 @@
109 device_type = "network"; 110 device_type = "network";
110 compatible = "fsl,mpc885-fec-enet", 111 compatible = "fsl,mpc885-fec-enet",
111 "fsl,pq1-fec-enet"; 112 "fsl,pq1-fec-enet";
112 reg = <1e00 188>; 113 reg = <0x1e00 0x188>;
113 local-mac-address = [ 00 00 00 00 00 00 ]; 114 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <7 1>; 115 interrupts = <7 1>;
115 interrupt-parent = <&PIC>; 116 interrupt-parent = <&PIC>;
@@ -120,7 +121,7 @@
120 PIC: interrupt-controller@0 { 121 PIC: interrupt-controller@0 {
121 interrupt-controller; 122 interrupt-controller;
122 #interrupt-cells = <2>; 123 #interrupt-cells = <2>;
123 reg = <0 24>; 124 reg = <0x0 0x24>;
124 compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; 125 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
125 }; 126 };
126 127
@@ -130,29 +131,29 @@
130 #size-cells = <2>; 131 #size-cells = <2>;
131 compatible = "fsl,pq-pcmcia"; 132 compatible = "fsl,pq-pcmcia";
132 device_type = "pcmcia"; 133 device_type = "pcmcia";
133 reg = <80 80>; 134 reg = <0x80 0x80>;
134 interrupt-parent = <&PIC>; 135 interrupt-parent = <&PIC>;
135 interrupts = <d 1>; 136 interrupts = <13 1>;
136 }; 137 };
137 138
138 cpm@9c0 { 139 cpm@9c0 {
139 #address-cells = <1>; 140 #address-cells = <1>;
140 #size-cells = <1>; 141 #size-cells = <1>;
141 compatible = "fsl,mpc885-cpm", "fsl,cpm1"; 142 compatible = "fsl,mpc885-cpm", "fsl,cpm1";
142 command-proc = <9c0>; 143 command-proc = <0x9c0>;
143 interrupts = <0>; // cpm error interrupt 144 interrupts = <0>; // cpm error interrupt
144 interrupt-parent = <&CPM_PIC>; 145 interrupt-parent = <&CPM_PIC>;
145 reg = <9c0 40>; 146 reg = <0x9c0 0x40>;
146 ranges; 147 ranges;
147 148
148 muram@2000 { 149 muram@2000 {
149 #address-cells = <1>; 150 #address-cells = <1>;
150 #size-cells = <1>; 151 #size-cells = <1>;
151 ranges = <0 2000 2000>; 152 ranges = <0x0 0x2000 0x2000>;
152 153
153 data@0 { 154 data@0 {
154 compatible = "fsl,cpm-muram-data"; 155 compatible = "fsl,cpm-muram-data";
155 reg = <0 1c00>; 156 reg = <0x0 0x1c00>;
156 }; 157 };
157 }; 158 };
158 159
@@ -160,7 +161,7 @@
160 compatible = "fsl,mpc885-brg", 161 compatible = "fsl,mpc885-brg",
161 "fsl,cpm1-brg", 162 "fsl,cpm1-brg",
162 "fsl,cpm-brg"; 163 "fsl,cpm-brg";
163 reg = <9f0 10>; 164 reg = <0x9f0 0x10>;
164 }; 165 };
165 166
166 CPM_PIC: interrupt-controller@930 { 167 CPM_PIC: interrupt-controller@930 {
@@ -168,7 +169,7 @@
168 #interrupt-cells = <1>; 169 #interrupt-cells = <1>;
169 interrupts = <5 2 0 2>; 170 interrupts = <5 2 0 2>;
170 interrupt-parent = <&PIC>; 171 interrupt-parent = <&PIC>;
171 reg = <930 20>; 172 reg = <0x930 0x20>;
172 compatible = "fsl,mpc885-cpm-pic", 173 compatible = "fsl,mpc885-cpm-pic",
173 "fsl,cpm1-pic"; 174 "fsl,cpm1-pic";
174 }; 175 };
@@ -178,11 +179,11 @@
178 device_type = "serial"; 179 device_type = "serial";
179 compatible = "fsl,mpc885-smc-uart", 180 compatible = "fsl,mpc885-smc-uart",
180 "fsl,cpm1-smc-uart"; 181 "fsl,cpm1-smc-uart";
181 reg = <a80 10 3e80 40>; 182 reg = <0xa80 0x10 0x3e80 0x40>;
182 interrupts = <4>; 183 interrupts = <4>;
183 interrupt-parent = <&CPM_PIC>; 184 interrupt-parent = <&CPM_PIC>;
184 fsl,cpm-brg = <1>; 185 fsl,cpm-brg = <1>;
185 fsl,cpm-command = <0090>; 186 fsl,cpm-command = <0x90>;
186 linux,planetcore-label = "SMC1"; 187 linux,planetcore-label = "SMC1";
187 }; 188 };
188 189
@@ -191,11 +192,11 @@
191 device_type = "serial"; 192 device_type = "serial";
192 compatible = "fsl,mpc885-scc-uart", 193 compatible = "fsl,mpc885-scc-uart",
193 "fsl,cpm1-scc-uart"; 194 "fsl,cpm1-scc-uart";
194 reg = <a20 20 3d00 80>; 195 reg = <0xa20 0x20 0x3d00 0x80>;
195 interrupts = <1d>; 196 interrupts = <29>;
196 interrupt-parent = <&CPM_PIC>; 197 interrupt-parent = <&CPM_PIC>;
197 fsl,cpm-brg = <2>; 198 fsl,cpm-brg = <2>;
198 fsl,cpm-command = <0040>; 199 fsl,cpm-command = <0x40>;
199 linux,planetcore-label = "SCC2"; 200 linux,planetcore-label = "SCC2";
200 }; 201 };
201 202
@@ -204,9 +205,9 @@
204 #size-cells = <0>; 205 #size-cells = <0>;
205 compatible = "fsl,mpc885-usb", 206 compatible = "fsl,mpc885-usb",
206 "fsl,cpm1-usb"; 207 "fsl,cpm1-usb";
207 reg = <a00 18 1c00 80>; 208 reg = <0xa00 0x18 0x1c00 0x80>;
208 interrupt-parent = <&CPM_PIC>; 209 interrupt-parent = <&CPM_PIC>;
209 interrupts = <1e>; 210 interrupts = <30>;
210 fsl,cpm-command = <0000>; 211 fsl,cpm-command = <0000>;
211 }; 212 };
212 }; 213 };
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 446958854519..2e5a1a1812b6 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -7,6 +7,7 @@
7 * Based on sandpoint.dts 7 * Based on sandpoint.dts
8 * 8 *
9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> 9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
10 * Copyright 2008 Freescale Semiconductor, Inc.
10 * 11 *
11 * This file is licensed under 12 * This file is licensed under
12 * the terms of the GNU General Public License version 2. This program 13 * the terms of the GNU General Public License version 2. This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
17 18
18 */ 19 */
19 20
21/dts-v1/;
22
20/ { 23/ {
21 model = "KuroboxHD"; 24 model = "KuroboxHD";
22 compatible = "linkstation"; 25 compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
35 38
36 PowerPC,603e { /* Really 8241 */ 39 PowerPC,603e { /* Really 8241 */
37 device_type = "cpu"; 40 device_type = "cpu";
38 reg = <0>; 41 reg = <0x0>;
39 clock-frequency = <bebc200>; /* Fixed by bootloader */ 42 clock-frequency = <200000000>; /* Fixed by bootloader */
40 timebase-frequency = <1743000>; /* Fixed by bootloader */ 43 timebase-frequency = <24391680>; /* Fixed by bootloader */
41 bus-frequency = <0>; /* Fixed by bootloader */ 44 bus-frequency = <0>; /* Fixed by bootloader */
42 /* Following required by dtc but not used */ 45 /* Following required by dtc but not used */
43 i-cache-size = <4000>; 46 i-cache-size = <0x4000>;
44 d-cache-size = <4000>; 47 d-cache-size = <0x4000>;
45 }; 48 };
46 }; 49 };
47 50
48 memory { 51 memory {
49 device_type = "memory"; 52 device_type = "memory";
50 reg = <00000000 04000000>; 53 reg = <0x0 0x4000000>;
51 }; 54 };
52 55
53 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 56 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
56 device_type = "soc"; 59 device_type = "soc";
57 compatible = "mpc10x"; 60 compatible = "mpc10x";
58 store-gathering = <0>; /* 0 == off, !0 == on */ 61 store-gathering = <0>; /* 0 == off, !0 == on */
59 reg = <80000000 00100000>; 62 reg = <0x80000000 0x100000>;
60 ranges = <80000000 80000000 70000000 /* pci mem space */ 63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
61 fc000000 fc000000 00100000 /* EUMB */ 64 0xfc000000 0xfc000000 0x100000 /* EUMB */
62 fe000000 fe000000 00c00000 /* pci i/o space */ 65 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
63 fec00000 fec00000 00300000 /* pci cfg regs */ 66 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
64 fef00000 fef00000 00100000>; /* pci iack */ 67 0xfef00000 0xfef00000 0x100000>; /* pci iack */
65 68
66 i2c@80003000 { 69 i2c@80003000 {
67 #address-cells = <1>; 70 #address-cells = <1>;
68 #size-cells = <0>; 71 #size-cells = <0>;
69 cell-index = <0>; 72 cell-index = <0>;
70 compatible = "fsl-i2c"; 73 compatible = "fsl-i2c";
71 reg = <80003000 1000>; 74 reg = <0x80003000 0x1000>;
72 interrupts = <5 2>; 75 interrupts = <5 2>;
73 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
74 77
75 rtc@32 { 78 rtc@32 {
76 device_type = "rtc"; 79 device_type = "rtc";
77 compatible = "ricoh,rs5c372a"; 80 compatible = "ricoh,rs5c372a";
78 reg = <32>; 81 reg = <0x32>;
79 }; 82 };
80 }; 83 };
81 84
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
83 cell-index = <0>; 86 cell-index = <0>;
84 device_type = "serial"; 87 device_type = "serial";
85 compatible = "ns16550"; 88 compatible = "ns16550";
86 reg = <80004500 8>; 89 reg = <0x80004500 0x8>;
87 clock-frequency = <5d08d88>; 90 clock-frequency = <97553800>;
88 current-speed = <2580>; 91 current-speed = <9600>;
89 interrupts = <9 0>; 92 interrupts = <9 0>;
90 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
91 }; 94 };
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
94 cell-index = <1>; 97 cell-index = <1>;
95 device_type = "serial"; 98 device_type = "serial";
96 compatible = "ns16550"; 99 compatible = "ns16550";
97 reg = <80004600 8>; 100 reg = <0x80004600 0x8>;
98 clock-frequency = <5d08d88>; 101 clock-frequency = <97553800>;
99 current-speed = <e100>; 102 current-speed = <57600>;
100 interrupts = <a 0>; 103 interrupts = <10 0>;
101 interrupt-parent = <&mpic>; 104 interrupt-parent = <&mpic>;
102 }; 105 };
103 106
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
107 device_type = "open-pic"; 110 device_type = "open-pic";
108 compatible = "chrp,open-pic"; 111 compatible = "chrp,open-pic";
109 interrupt-controller; 112 interrupt-controller;
110 reg = <80040000 40000>; 113 reg = <0x80040000 0x40000>;
111 }; 114 };
112 115
113 pci0: pci@fec00000 { 116 pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
116 #interrupt-cells = <1>; 119 #interrupt-cells = <1>;
117 device_type = "pci"; 120 device_type = "pci";
118 compatible = "mpc10x-pci"; 121 compatible = "mpc10x-pci";
119 reg = <fec00000 400000>; 122 reg = <0xfec00000 0x400000>;
120 ranges = <01000000 0 0 fe000000 0 00c00000 123 ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
121 02000000 0 80000000 80000000 0 70000000>; 124 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
122 bus-range = <0 ff>; 125 bus-range = <0 255>;
123 clock-frequency = <7f28155>; 126 clock-frequency = <133333333>;
124 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
125 interrupt-map-mask = <f800 0 0 7>; 128 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
126 interrupt-map = < 129 interrupt-map = <
127 /* IDSEL 11 - IRQ0 ETH */ 130 /* IDSEL 11 - IRQ0 ETH */
128 5800 0 0 1 &mpic 0 1 131 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
129 5800 0 0 2 &mpic 1 1 132 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
130 5800 0 0 3 &mpic 2 1 133 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
131 5800 0 0 4 &mpic 3 1 134 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
132 /* IDSEL 12 - IRQ1 IDE0 */ 135 /* IDSEL 12 - IRQ1 IDE0 */
133 6000 0 0 1 &mpic 1 1 136 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
134 6000 0 0 2 &mpic 2 1 137 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
135 6000 0 0 3 &mpic 3 1 138 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
136 6000 0 0 4 &mpic 0 1 139 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
137 /* IDSEL 14 - IRQ3 USB2.0 */ 140 /* IDSEL 14 - IRQ3 USB2.0 */
138 7000 0 0 1 &mpic 3 1 141 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
139 7000 0 0 2 &mpic 3 1 142 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
140 7000 0 0 3 &mpic 3 1 143 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
141 7000 0 0 4 &mpic 3 1 144 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
142 >; 145 >;
143 }; 146 };
144 }; 147 };
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index 8443c85b7b30..e4916e69ad31 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -7,6 +7,7 @@
7 * Based on sandpoint.dts 7 * Based on sandpoint.dts
8 * 8 *
9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> 9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
10 * Copyright 2008 Freescale Semiconductor, Inc.
10 * 11 *
11 * This file is licensed under 12 * This file is licensed under
12 * the terms of the GNU General Public License version 2. This program 13 * the terms of the GNU General Public License version 2. This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
17 18
18 */ 19 */
19 20
21/dts-v1/;
22
20/ { 23/ {
21 model = "KuroboxHG"; 24 model = "KuroboxHG";
22 compatible = "linkstation"; 25 compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
35 38
36 PowerPC,603e { /* Really 8241 */ 39 PowerPC,603e { /* Really 8241 */
37 device_type = "cpu"; 40 device_type = "cpu";
38 reg = <0>; 41 reg = <0x0>;
39 clock-frequency = <fdad680>; /* Fixed by bootloader */ 42 clock-frequency = <266000000>; /* Fixed by bootloader */
40 timebase-frequency = <1F04000>; /* Fixed by bootloader */ 43 timebase-frequency = <32522240>; /* Fixed by bootloader */
41 bus-frequency = <0>; /* Fixed by bootloader */ 44 bus-frequency = <0>; /* Fixed by bootloader */
42 /* Following required by dtc but not used */ 45 /* Following required by dtc but not used */
43 i-cache-size = <4000>; 46 i-cache-size = <0x4000>;
44 d-cache-size = <4000>; 47 d-cache-size = <0x4000>;
45 }; 48 };
46 }; 49 };
47 50
48 memory { 51 memory {
49 device_type = "memory"; 52 device_type = "memory";
50 reg = <00000000 08000000>; 53 reg = <0x0 0x8000000>;
51 }; 54 };
52 55
53 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 56 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
56 device_type = "soc"; 59 device_type = "soc";
57 compatible = "mpc10x"; 60 compatible = "mpc10x";
58 store-gathering = <0>; /* 0 == off, !0 == on */ 61 store-gathering = <0>; /* 0 == off, !0 == on */
59 reg = <80000000 00100000>; 62 reg = <0x80000000 0x100000>;
60 ranges = <80000000 80000000 70000000 /* pci mem space */ 63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
61 fc000000 fc000000 00100000 /* EUMB */ 64 0xfc000000 0xfc000000 0x100000 /* EUMB */
62 fe000000 fe000000 00c00000 /* pci i/o space */ 65 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
63 fec00000 fec00000 00300000 /* pci cfg regs */ 66 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
64 fef00000 fef00000 00100000>; /* pci iack */ 67 0xfef00000 0xfef00000 0x100000>; /* pci iack */
65 68
66 i2c@80003000 { 69 i2c@80003000 {
67 #address-cells = <1>; 70 #address-cells = <1>;
68 #size-cells = <0>; 71 #size-cells = <0>;
69 cell-index = <0>; 72 cell-index = <0>;
70 compatible = "fsl-i2c"; 73 compatible = "fsl-i2c";
71 reg = <80003000 1000>; 74 reg = <0x80003000 0x1000>;
72 interrupts = <5 2>; 75 interrupts = <5 2>;
73 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
74 77
75 rtc@32 { 78 rtc@32 {
76 device_type = "rtc"; 79 device_type = "rtc";
77 compatible = "ricoh,rs5c372a"; 80 compatible = "ricoh,rs5c372a";
78 reg = <32>; 81 reg = <0x32>;
79 }; 82 };
80 }; 83 };
81 84
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
83 cell-index = <0>; 86 cell-index = <0>;
84 device_type = "serial"; 87 device_type = "serial";
85 compatible = "ns16550"; 88 compatible = "ns16550";
86 reg = <80004500 8>; 89 reg = <0x80004500 0x8>;
87 clock-frequency = <7c044a8>; 90 clock-frequency = <130041000>;
88 current-speed = <2580>; 91 current-speed = <9600>;
89 interrupts = <9 0>; 92 interrupts = <9 0>;
90 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
91 }; 94 };
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
94 cell-index = <1>; 97 cell-index = <1>;
95 device_type = "serial"; 98 device_type = "serial";
96 compatible = "ns16550"; 99 compatible = "ns16550";
97 reg = <80004600 8>; 100 reg = <0x80004600 0x8>;
98 clock-frequency = <7c044a8>; 101 clock-frequency = <130041000>;
99 current-speed = <e100>; 102 current-speed = <57600>;
100 interrupts = <a 0>; 103 interrupts = <10 0>;
101 interrupt-parent = <&mpic>; 104 interrupt-parent = <&mpic>;
102 }; 105 };
103 106
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
107 device_type = "open-pic"; 110 device_type = "open-pic";
108 compatible = "chrp,open-pic"; 111 compatible = "chrp,open-pic";
109 interrupt-controller; 112 interrupt-controller;
110 reg = <80040000 40000>; 113 reg = <0x80040000 0x40000>;
111 }; 114 };
112 115
113 pci0: pci@fec00000 { 116 pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
116 #interrupt-cells = <1>; 119 #interrupt-cells = <1>;
117 device_type = "pci"; 120 device_type = "pci";
118 compatible = "mpc10x-pci"; 121 compatible = "mpc10x-pci";
119 reg = <fec00000 400000>; 122 reg = <0xfec00000 0x400000>;
120 ranges = <01000000 0 0 fe000000 0 00c00000 123 ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
121 02000000 0 80000000 80000000 0 70000000>; 124 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
122 bus-range = <0 ff>; 125 bus-range = <0 255>;
123 clock-frequency = <7f28155>; 126 clock-frequency = <133333333>;
124 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
125 interrupt-map-mask = <f800 0 0 7>; 128 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
126 interrupt-map = < 129 interrupt-map = <
127 /* IDSEL 11 - IRQ0 ETH */ 130 /* IDSEL 11 - IRQ0 ETH */
128 5800 0 0 1 &mpic 0 1 131 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
129 5800 0 0 2 &mpic 1 1 132 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
130 5800 0 0 3 &mpic 2 1 133 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
131 5800 0 0 4 &mpic 3 1 134 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
132 /* IDSEL 12 - IRQ1 IDE0 */ 135 /* IDSEL 12 - IRQ1 IDE0 */
133 6000 0 0 1 &mpic 1 1 136 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
134 6000 0 0 2 &mpic 2 1 137 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
135 6000 0 0 3 &mpic 3 1 138 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
136 6000 0 0 4 &mpic 0 1 139 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
137 /* IDSEL 14 - IRQ3 USB2.0 */ 140 /* IDSEL 14 - IRQ3 USB2.0 */
138 7000 0 0 1 &mpic 3 1 141 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
139 7000 0 0 2 &mpic 3 1 142 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
140 7000 0 0 3 &mpic 3 1 143 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
141 7000 0 0 4 &mpic 3 1 144 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
142 >; 145 >;
143 }; 146 };
144 }; 147 };
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index 8fb542387436..4936349b87cd 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC7448HPC2 (Taiga) board Device Tree Source 2 * MPC7448HPC2 (Taiga) board Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 2006 Roy Zang <Roy Zang at freescale.com>. 5 * 2006 Roy Zang <Roy Zang at freescale.com>.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -10,6 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
13 14
14/ { 15/ {
15 model = "mpc7448hpc2"; 16 model = "mpc7448hpc2";
@@ -23,11 +24,11 @@
23 24
24 PowerPC,7448@0 { 25 PowerPC,7448@0 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 reg = <0>; 27 reg = <0x0>;
27 d-cache-line-size = <20>; // 32 bytes 28 d-cache-line-size = <32>; // 32 bytes
28 i-cache-line-size = <20>; // 32 bytes 29 i-cache-line-size = <32>; // 32 bytes
29 d-cache-size = <8000>; // L1, 32K bytes 30 d-cache-size = <0x8000>; // L1, 32K bytes
30 i-cache-size = <8000>; // L1, 32K bytes 31 i-cache-size = <0x8000>; // L1, 32K bytes
31 timebase-frequency = <0>; // 33 MHz, from uboot 32 timebase-frequency = <0>; // 33 MHz, from uboot
32 clock-frequency = <0>; // From U-Boot 33 clock-frequency = <0>; // From U-Boot
33 bus-frequency = <0>; // From U-Boot 34 bus-frequency = <0>; // From U-Boot
@@ -36,7 +37,7 @@
36 37
37 memory { 38 memory {
38 device_type = "memory"; 39 device_type = "memory";
39 reg = <00000000 20000000 // DDR2 512M at 0 40 reg = <0x0 0x20000000 // DDR2 512M at 0
40 >; 41 >;
41 }; 42 };
42 43
@@ -44,14 +45,14 @@
44 #address-cells = <1>; 45 #address-cells = <1>;
45 #size-cells = <1>; 46 #size-cells = <1>;
46 device_type = "tsi-bridge"; 47 device_type = "tsi-bridge";
47 ranges = <00000000 c0000000 00010000>; 48 ranges = <0x0 0xc0000000 0x10000>;
48 reg = <c0000000 00010000>; 49 reg = <0xc0000000 0x10000>;
49 bus-frequency = <0>; 50 bus-frequency = <0>;
50 51
51 i2c@7000 { 52 i2c@7000 {
52 interrupt-parent = <&mpic>; 53 interrupt-parent = <&mpic>;
53 interrupts = <E 0>; 54 interrupts = <14 0>;
54 reg = <7000 400>; 55 reg = <0x7000 0x400>;
55 device_type = "i2c"; 56 device_type = "i2c";
56 compatible = "tsi108-i2c"; 57 compatible = "tsi108-i2c";
57 }; 58 };
@@ -59,20 +60,20 @@
59 MDIO: mdio@6000 { 60 MDIO: mdio@6000 {
60 device_type = "mdio"; 61 device_type = "mdio";
61 compatible = "tsi108-mdio"; 62 compatible = "tsi108-mdio";
62 reg = <6000 50>; 63 reg = <0x6000 0x50>;
63 #address-cells = <1>; 64 #address-cells = <1>;
64 #size-cells = <0>; 65 #size-cells = <0>;
65 66
66 phy8: ethernet-phy@8 { 67 phy8: ethernet-phy@8 {
67 interrupt-parent = <&mpic>; 68 interrupt-parent = <&mpic>;
68 interrupts = <2 1>; 69 interrupts = <2 1>;
69 reg = <8>; 70 reg = <0x8>;
70 }; 71 };
71 72
72 phy9: ethernet-phy@9 { 73 phy9: ethernet-phy@9 {
73 interrupt-parent = <&mpic>; 74 interrupt-parent = <&mpic>;
74 interrupts = <2 1>; 75 interrupts = <2 1>;
75 reg = <9>; 76 reg = <0x9>;
76 }; 77 };
77 78
78 }; 79 };
@@ -82,9 +83,9 @@
82 #size-cells = <0>; 83 #size-cells = <0>;
83 device_type = "network"; 84 device_type = "network";
84 compatible = "tsi108-ethernet"; 85 compatible = "tsi108-ethernet";
85 reg = <6000 200>; 86 reg = <0x6000 0x200>;
86 address = [ 00 06 D2 00 00 01 ]; 87 address = [ 00 06 D2 00 00 01 ];
87 interrupts = <10 2>; 88 interrupts = <16 2>;
88 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
89 mdio-handle = <&MDIO>; 90 mdio-handle = <&MDIO>;
90 phy-handle = <&phy8>; 91 phy-handle = <&phy8>;
@@ -96,9 +97,9 @@
96 #size-cells = <0>; 97 #size-cells = <0>;
97 device_type = "network"; 98 device_type = "network";
98 compatible = "tsi108-ethernet"; 99 compatible = "tsi108-ethernet";
99 reg = <6400 200>; 100 reg = <0x6400 0x200>;
100 address = [ 00 06 D2 00 00 02 ]; 101 address = [ 00 06 D2 00 00 02 ];
101 interrupts = <11 2>; 102 interrupts = <17 2>;
102 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
103 mdio-handle = <&MDIO>; 104 mdio-handle = <&MDIO>;
104 phy-handle = <&phy9>; 105 phy-handle = <&phy9>;
@@ -107,18 +108,18 @@
107 serial@7808 { 108 serial@7808 {
108 device_type = "serial"; 109 device_type = "serial";
109 compatible = "ns16550"; 110 compatible = "ns16550";
110 reg = <7808 200>; 111 reg = <0x7808 0x200>;
111 clock-frequency = <3f6b5a00>; 112 clock-frequency = <1064000000>;
112 interrupts = <c 0>; 113 interrupts = <12 0>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 }; 115 };
115 116
116 serial@7c08 { 117 serial@7c08 {
117 device_type = "serial"; 118 device_type = "serial";
118 compatible = "ns16550"; 119 compatible = "ns16550";
119 reg = <7c08 200>; 120 reg = <0x7c08 0x200>;
120 clock-frequency = <3f6b5a00>; 121 clock-frequency = <1064000000>;
121 interrupts = <d 0>; 122 interrupts = <13 0>;
122 interrupt-parent = <&mpic>; 123 interrupt-parent = <&mpic>;
123 }; 124 };
124 125
@@ -127,7 +128,7 @@
127 interrupt-controller; 128 interrupt-controller;
128 #address-cells = <0>; 129 #address-cells = <0>;
129 #interrupt-cells = <2>; 130 #interrupt-cells = <2>;
130 reg = <7400 400>; 131 reg = <0x7400 0x400>;
131 compatible = "chrp,open-pic"; 132 compatible = "chrp,open-pic";
132 device_type = "open-pic"; 133 device_type = "open-pic";
133 big-endian; 134 big-endian;
@@ -138,39 +139,39 @@
138 #interrupt-cells = <1>; 139 #interrupt-cells = <1>;
139 #size-cells = <2>; 140 #size-cells = <2>;
140 #address-cells = <3>; 141 #address-cells = <3>;
141 reg = <1000 1000>; 142 reg = <0x1000 0x1000>;
142 bus-range = <0 0>; 143 bus-range = <0 0>;
143 ranges = <02000000 0 e0000000 e0000000 0 1A000000 144 ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
144 01000000 0 00000000 fa000000 0 00010000>; 145 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
145 clock-frequency = <7f28154>; 146 clock-frequency = <133333332>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 interrupts = <17 2>; 148 interrupts = <23 2>;
148 interrupt-map-mask = <f800 0 0 7>; 149 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
149 interrupt-map = < 150 interrupt-map = <
150 151
151 /* IDSEL 0x11 */ 152 /* IDSEL 0x11 */
152 0800 0 0 1 &RT0 24 0 153 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
153 0800 0 0 2 &RT0 25 0 154 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
154 0800 0 0 3 &RT0 26 0 155 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
155 0800 0 0 4 &RT0 27 0 156 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
156 157
157 /* IDSEL 0x12 */ 158 /* IDSEL 0x12 */
158 1000 0 0 1 &RT0 25 0 159 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
159 1000 0 0 2 &RT0 26 0 160 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
160 1000 0 0 3 &RT0 27 0 161 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
161 1000 0 0 4 &RT0 24 0 162 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
162 163
163 /* IDSEL 0x13 */ 164 /* IDSEL 0x13 */
164 1800 0 0 1 &RT0 26 0 165 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
165 1800 0 0 2 &RT0 27 0 166 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
166 1800 0 0 3 &RT0 24 0 167 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
167 1800 0 0 4 &RT0 25 0 168 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
168 169
169 /* IDSEL 0x14 */ 170 /* IDSEL 0x14 */
170 2000 0 0 1 &RT0 27 0 171 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
171 2000 0 0 2 &RT0 24 0 172 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
172 2000 0 0 3 &RT0 25 0 173 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
173 2000 0 0 4 &RT0 26 0 174 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
174 >; 175 >;
175 176
176 RT0: router@1180 { 177 RT0: router@1180 {
@@ -180,7 +181,7 @@
180 #address-cells = <0>; 181 #address-cells = <0>;
181 #interrupt-cells = <2>; 182 #interrupt-cells = <2>;
182 big-endian; 183 big-endian;
183 interrupts = <17 2>; 184 interrupts = <23 2>;
184 interrupt-parent = <&mpic>; 185 interrupt-parent = <&mpic>;
185 }; 186 };
186 }; 187 };
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 7285ca1325fd..46e2da30c3dd 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8272 ADS Device Tree Source 2 * MPC8272 ADS Device Tree Source
3 * 3 *
4 * Copyright 2005 Freescale Semiconductor Inc. 4 * Copyright 2005,2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8272ADS"; 15 model = "MPC8272ADS";
14 compatible = "fsl,mpc8272ads"; 16 compatible = "fsl,mpc8272ads";
@@ -21,11 +23,11 @@
21 23
22 PowerPC,8272@0 { 24 PowerPC,8272@0 {
23 device_type = "cpu"; 25 device_type = "cpu";
24 reg = <0>; 26 reg = <0x0>;
25 d-cache-line-size = <d#32>; 27 d-cache-line-size = <32>;
26 i-cache-line-size = <d#32>; 28 i-cache-line-size = <32>;
27 d-cache-size = <d#16384>; 29 d-cache-size = <16384>;
28 i-cache-size = <d#16384>; 30 i-cache-size = <16384>;
29 timebase-frequency = <0>; 31 timebase-frequency = <0>;
30 bus-frequency = <0>; 32 bus-frequency = <0>;
31 clock-frequency = <0>; 33 clock-frequency = <0>;
@@ -34,7 +36,7 @@
34 36
35 memory { 37 memory {
36 device_type = "memory"; 38 device_type = "memory";
37 reg = <0 0>; 39 reg = <0x0 0x0>;
38 }; 40 };
39 41
40 localbus@f0010100 { 42 localbus@f0010100 {
@@ -42,21 +44,21 @@
42 "fsl,pq2-localbus"; 44 "fsl,pq2-localbus";
43 #address-cells = <2>; 45 #address-cells = <2>;
44 #size-cells = <1>; 46 #size-cells = <1>;
45 reg = <f0010100 40>; 47 reg = <0xf0010100 0x40>;
46 48
47 ranges = <0 0 fe000000 02000000 49 ranges = <0x0 0x0 0xfe000000 0x2000000
48 1 0 f4500000 00008000 50 0x1 0x0 0xf4500000 0x8000
49 3 0 f8200000 00008000>; 51 0x3 0x0 0xf8200000 0x8000>;
50 52
51 flash@0,0 { 53 flash@0,0 {
52 compatible = "jedec-flash"; 54 compatible = "jedec-flash";
53 reg = <0 0 2000000>; 55 reg = <0x0 0x0 0x2000000>;
54 bank-width = <4>; 56 bank-width = <4>;
55 device-width = <1>; 57 device-width = <1>;
56 }; 58 };
57 59
58 board-control@1,0 { 60 board-control@1,0 {
59 reg = <1 0 20>; 61 reg = <0x1 0x0 0x20>;
60 compatible = "fsl,mpc8272ads-bcsr"; 62 compatible = "fsl,mpc8272ads-bcsr";
61 }; 63 };
62 64
@@ -65,46 +67,46 @@
65 "fsl,pq2ads-pci-pic"; 67 "fsl,pq2ads-pci-pic";
66 #interrupt-cells = <1>; 68 #interrupt-cells = <1>;
67 interrupt-controller; 69 interrupt-controller;
68 reg = <3 0 8>; 70 reg = <0x3 0x0 0x8>;
69 interrupt-parent = <&PIC>; 71 interrupt-parent = <&PIC>;
70 interrupts = <14 8>; 72 interrupts = <20 8>;
71 }; 73 };
72 }; 74 };
73 75
74 76
75 pci@f0010800 { 77 pci@f0010800 {
76 device_type = "pci"; 78 device_type = "pci";
77 reg = <f0010800 10c f00101ac 8 f00101c4 8>; 79 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
78 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci"; 80 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
79 #interrupt-cells = <1>; 81 #interrupt-cells = <1>;
80 #size-cells = <2>; 82 #size-cells = <2>;
81 #address-cells = <3>; 83 #address-cells = <3>;
82 clock-frequency = <d#66666666>; 84 clock-frequency = <66666666>;
83 interrupt-map-mask = <f800 0 0 7>; 85 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
84 interrupt-map = < 86 interrupt-map = <
85 /* IDSEL 0x16 */ 87 /* IDSEL 0x16 */
86 b000 0 0 1 &PCI_PIC 0 88 0xb000 0x0 0x0 0x1 &PCI_PIC 0
87 b000 0 0 2 &PCI_PIC 1 89 0xb000 0x0 0x0 0x2 &PCI_PIC 1
88 b000 0 0 3 &PCI_PIC 2 90 0xb000 0x0 0x0 0x3 &PCI_PIC 2
89 b000 0 0 4 &PCI_PIC 3 91 0xb000 0x0 0x0 0x4 &PCI_PIC 3
90 92
91 /* IDSEL 0x17 */ 93 /* IDSEL 0x17 */
92 b800 0 0 1 &PCI_PIC 4 94 0xb800 0x0 0x0 0x1 &PCI_PIC 4
93 b800 0 0 2 &PCI_PIC 5 95 0xb800 0x0 0x0 0x2 &PCI_PIC 5
94 b800 0 0 3 &PCI_PIC 6 96 0xb800 0x0 0x0 0x3 &PCI_PIC 6
95 b800 0 0 4 &PCI_PIC 7 97 0xb800 0x0 0x0 0x4 &PCI_PIC 7
96 98
97 /* IDSEL 0x18 */ 99 /* IDSEL 0x18 */
98 c000 0 0 1 &PCI_PIC 8 100 0xc000 0x0 0x0 0x1 &PCI_PIC 8
99 c000 0 0 2 &PCI_PIC 9 101 0xc000 0x0 0x0 0x2 &PCI_PIC 9
100 c000 0 0 3 &PCI_PIC a 102 0xc000 0x0 0x0 0x3 &PCI_PIC 10
101 c000 0 0 4 &PCI_PIC b>; 103 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
102 104
103 interrupt-parent = <&PIC>; 105 interrupt-parent = <&PIC>;
104 interrupts = <12 8>; 106 interrupts = <18 8>;
105 ranges = <42000000 0 80000000 80000000 0 20000000 107 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
106 02000000 0 a0000000 a0000000 0 20000000 108 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
107 01000000 0 00000000 f6000000 0 02000000>; 109 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
108 }; 110 };
109 111
110 soc@f0000000 { 112 soc@f0000000 {
@@ -112,26 +114,26 @@
112 #size-cells = <1>; 114 #size-cells = <1>;
113 device_type = "soc"; 115 device_type = "soc";
114 compatible = "fsl,mpc8272", "fsl,pq2-soc"; 116 compatible = "fsl,mpc8272", "fsl,pq2-soc";
115 ranges = <00000000 f0000000 00053000>; 117 ranges = <0x0 0xf0000000 0x53000>;
116 118
117 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 119 // Temporary -- will go away once kernel uses ranges for get_immrbase().
118 reg = <f0000000 00053000>; 120 reg = <0xf0000000 0x53000>;
119 121
120 cpm@119c0 { 122 cpm@119c0 {
121 #address-cells = <1>; 123 #address-cells = <1>;
122 #size-cells = <1>; 124 #size-cells = <1>;
123 compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; 125 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
124 reg = <119c0 30>; 126 reg = <0x119c0 0x30>;
125 ranges; 127 ranges;
126 128
127 muram@0 { 129 muram@0 {
128 #address-cells = <1>; 130 #address-cells = <1>;
129 #size-cells = <1>; 131 #size-cells = <1>;
130 ranges = <0 0 10000>; 132 ranges = <0x0 0x0 0x10000>;
131 133
132 data@0 { 134 data@0 {
133 compatible = "fsl,cpm-muram-data"; 135 compatible = "fsl,cpm-muram-data";
134 reg = <0 2000 9800 800>; 136 reg = <0x0 0x2000 0x9800 0x800>;
135 }; 137 };
136 }; 138 };
137 139
@@ -139,29 +141,29 @@
139 compatible = "fsl,mpc8272-brg", 141 compatible = "fsl,mpc8272-brg",
140 "fsl,cpm2-brg", 142 "fsl,cpm2-brg",
141 "fsl,cpm-brg"; 143 "fsl,cpm-brg";
142 reg = <119f0 10 115f0 10>; 144 reg = <0x119f0 0x10 0x115f0 0x10>;
143 }; 145 };
144 146
145 serial@11a00 { 147 serial@11a00 {
146 device_type = "serial"; 148 device_type = "serial";
147 compatible = "fsl,mpc8272-scc-uart", 149 compatible = "fsl,mpc8272-scc-uart",
148 "fsl,cpm2-scc-uart"; 150 "fsl,cpm2-scc-uart";
149 reg = <11a00 20 8000 100>; 151 reg = <0x11a00 0x20 0x8000 0x100>;
150 interrupts = <28 8>; 152 interrupts = <40 8>;
151 interrupt-parent = <&PIC>; 153 interrupt-parent = <&PIC>;
152 fsl,cpm-brg = <1>; 154 fsl,cpm-brg = <1>;
153 fsl,cpm-command = <00800000>; 155 fsl,cpm-command = <0x800000>;
154 }; 156 };
155 157
156 serial@11a60 { 158 serial@11a60 {
157 device_type = "serial"; 159 device_type = "serial";
158 compatible = "fsl,mpc8272-scc-uart", 160 compatible = "fsl,mpc8272-scc-uart",
159 "fsl,cpm2-scc-uart"; 161 "fsl,cpm2-scc-uart";
160 reg = <11a60 20 8300 100>; 162 reg = <0x11a60 0x20 0x8300 0x100>;
161 interrupts = <2b 8>; 163 interrupts = <43 8>;
162 interrupt-parent = <&PIC>; 164 interrupt-parent = <&PIC>;
163 fsl,cpm-brg = <4>; 165 fsl,cpm-brg = <4>;
164 fsl,cpm-command = <0ce00000>; 166 fsl,cpm-command = <0xce00000>;
165 }; 167 };
166 168
167 mdio@10d40 { 169 mdio@10d40 {
@@ -169,23 +171,23 @@
169 compatible = "fsl,mpc8272ads-mdio-bitbang", 171 compatible = "fsl,mpc8272ads-mdio-bitbang",
170 "fsl,mpc8272-mdio-bitbang", 172 "fsl,mpc8272-mdio-bitbang",
171 "fsl,cpm2-mdio-bitbang"; 173 "fsl,cpm2-mdio-bitbang";
172 reg = <10d40 14>; 174 reg = <0x10d40 0x14>;
173 #address-cells = <1>; 175 #address-cells = <1>;
174 #size-cells = <0>; 176 #size-cells = <0>;
175 fsl,mdio-pin = <12>; 177 fsl,mdio-pin = <18>;
176 fsl,mdc-pin = <13>; 178 fsl,mdc-pin = <19>;
177 179
178 PHY0: ethernet-phy@0 { 180 PHY0: ethernet-phy@0 {
179 interrupt-parent = <&PIC>; 181 interrupt-parent = <&PIC>;
180 interrupts = <17 8>; 182 interrupts = <23 8>;
181 reg = <0>; 183 reg = <0x0>;
182 device_type = "ethernet-phy"; 184 device_type = "ethernet-phy";
183 }; 185 };
184 186
185 PHY1: ethernet-phy@1 { 187 PHY1: ethernet-phy@1 {
186 interrupt-parent = <&PIC>; 188 interrupt-parent = <&PIC>;
187 interrupts = <17 8>; 189 interrupts = <23 8>;
188 reg = <3>; 190 reg = <0x3>;
189 device_type = "ethernet-phy"; 191 device_type = "ethernet-phy";
190 }; 192 };
191 }; 193 };
@@ -194,33 +196,33 @@
194 device_type = "network"; 196 device_type = "network";
195 compatible = "fsl,mpc8272-fcc-enet", 197 compatible = "fsl,mpc8272-fcc-enet",
196 "fsl,cpm2-fcc-enet"; 198 "fsl,cpm2-fcc-enet";
197 reg = <11300 20 8400 100 11390 1>; 199 reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
198 local-mac-address = [ 00 00 00 00 00 00 ]; 200 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <20 8>; 201 interrupts = <32 8>;
200 interrupt-parent = <&PIC>; 202 interrupt-parent = <&PIC>;
201 phy-handle = <&PHY0>; 203 phy-handle = <&PHY0>;
202 linux,network-index = <0>; 204 linux,network-index = <0>;
203 fsl,cpm-command = <12000300>; 205 fsl,cpm-command = <0x12000300>;
204 }; 206 };
205 207
206 ethernet@11320 { 208 ethernet@11320 {
207 device_type = "network"; 209 device_type = "network";
208 compatible = "fsl,mpc8272-fcc-enet", 210 compatible = "fsl,mpc8272-fcc-enet",
209 "fsl,cpm2-fcc-enet"; 211 "fsl,cpm2-fcc-enet";
210 reg = <11320 20 8500 100 113b0 1>; 212 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
211 local-mac-address = [ 00 00 00 00 00 00 ]; 213 local-mac-address = [ 00 00 00 00 00 00 ];
212 interrupts = <21 8>; 214 interrupts = <33 8>;
213 interrupt-parent = <&PIC>; 215 interrupt-parent = <&PIC>;
214 phy-handle = <&PHY1>; 216 phy-handle = <&PHY1>;
215 linux,network-index = <1>; 217 linux,network-index = <1>;
216 fsl,cpm-command = <16200300>; 218 fsl,cpm-command = <0x16200300>;
217 }; 219 };
218 }; 220 };
219 221
220 PIC: interrupt-controller@10c00 { 222 PIC: interrupt-controller@10c00 {
221 #interrupt-cells = <2>; 223 #interrupt-cells = <2>;
222 interrupt-controller; 224 interrupt-controller;
223 reg = <10c00 80>; 225 reg = <0x10c00 0x80>;
224 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; 226 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
225 }; 227 };
226 228
@@ -232,14 +234,14 @@
232 "fsl,talitos-sec2", 234 "fsl,talitos-sec2",
233 "fsl,talitos", 235 "fsl,talitos",
234 "talitos"; 236 "talitos";
235 reg = <30000 10000>; 237 reg = <0x30000 0x10000>;
236 interrupts = <b 8>; 238 interrupts = <11 8>;
237 interrupt-parent = <&PIC>; 239 interrupt-parent = <&PIC>;
238 num-channels = <4>; 240 num-channels = <4>;
239 channel-fifo-len = <18>; 241 channel-fifo-len = <24>;
240 exec-units-mask = <0000007e>; 242 exec-units-mask = <0x7e>;
241/* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 243/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
242 descriptor-types-mask = <01010ebf>; 244 descriptor-types-mask = <0x1010ebf>;
243 }; 245 };
244 }; 246 };
245 247
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 9bb408371bcd..539e02fb3526 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -255,9 +255,7 @@
255 enet0: ucc@2200 { 255 enet0: ucc@2200 {
256 device_type = "network"; 256 device_type = "network";
257 compatible = "ucc_geth"; 257 compatible = "ucc_geth";
258 model = "UCC";
259 cell-index = <3>; 258 cell-index = <3>;
260 device-id = <3>;
261 reg = <0x2200 0x200>; 259 reg = <0x2200 0x200>;
262 interrupts = <34>; 260 interrupts = <34>;
263 interrupt-parent = <&qeic>; 261 interrupt-parent = <&qeic>;
@@ -271,9 +269,7 @@
271 enet1: ucc@3200 { 269 enet1: ucc@3200 {
272 device_type = "network"; 270 device_type = "network";
273 compatible = "ucc_geth"; 271 compatible = "ucc_geth";
274 model = "UCC";
275 cell-index = <4>; 272 cell-index = <4>;
276 device-id = <4>;
277 reg = <0x3200 0x200>; 273 reg = <0x3200 0x200>;
278 interrupts = <35>; 274 interrupts = <35>;
279 interrupt-parent = <&qeic>; 275 interrupt-parent = <&qeic>;
@@ -287,8 +283,7 @@
287 ucc@2400 { 283 ucc@2400 {
288 device_type = "serial"; 284 device_type = "serial";
289 compatible = "ucc_uart"; 285 compatible = "ucc_uart";
290 model = "UCC"; 286 cell-index = <5>; /* The UCC number, 1-7*/
291 device-id = <5>; /* The UCC number, 1-7*/
292 port-number = <0>; /* Which ttyQEx device */ 287 port-number = <0>; /* Which ttyQEx device */
293 soft-uart; /* We need Soft-UART */ 288 soft-uart; /* We need Soft-UART */
294 reg = <0x2400 0x200>; 289 reg = <0x2400 0x200>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 94f93d209de8..179c81c6a7ac 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -208,9 +208,7 @@
208 enet0: ucc@3000 { 208 enet0: ucc@3000 {
209 device_type = "network"; 209 device_type = "network";
210 compatible = "ucc_geth"; 210 compatible = "ucc_geth";
211 model = "UCC";
212 cell-index = <2>; 211 cell-index = <2>;
213 device-id = <2>;
214 reg = <0x3000 0x200>; 212 reg = <0x3000 0x200>;
215 interrupts = <33>; 213 interrupts = <33>;
216 interrupt-parent = <&qeic>; 214 interrupt-parent = <&qeic>;
@@ -224,9 +222,7 @@
224 enet1: ucc@2200 { 222 enet1: ucc@2200 {
225 device_type = "network"; 223 device_type = "network";
226 compatible = "ucc_geth"; 224 compatible = "ucc_geth";
227 model = "UCC";
228 cell-index = <3>; 225 cell-index = <3>;
229 device-id = <3>;
230 reg = <0x2200 0x200>; 226 reg = <0x2200 0x200>;
231 interrupts = <34>; 227 interrupts = <34>;
232 interrupt-parent = <&qeic>; 228 interrupt-parent = <&qeic>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 55f03e8dc97f..8160ff24e87e 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -257,9 +257,7 @@
257 enet0: ucc@2000 { 257 enet0: ucc@2000 {
258 device_type = "network"; 258 device_type = "network";
259 compatible = "ucc_geth"; 259 compatible = "ucc_geth";
260 model = "UCC";
261 cell-index = <1>; 260 cell-index = <1>;
262 device-id = <1>;
263 reg = <0x2000 0x200>; 261 reg = <0x2000 0x200>;
264 interrupts = <32>; 262 interrupts = <32>;
265 interrupt-parent = <&qeic>; 263 interrupt-parent = <&qeic>;
@@ -274,9 +272,7 @@
274 enet1: ucc@3000 { 272 enet1: ucc@3000 {
275 device_type = "network"; 273 device_type = "network";
276 compatible = "ucc_geth"; 274 compatible = "ucc_geth";
277 model = "UCC";
278 cell-index = <2>; 275 cell-index = <2>;
279 device-id = <2>;
280 reg = <0x3000 0x200>; 276 reg = <0x3000 0x200>;
281 interrupts = <33>; 277 interrupts = <33>;
282 interrupt-parent = <&qeic>; 278 interrupt-parent = <&qeic>;
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 975248491b7b..18033ed0b535 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8540 ADS Device Tree Source 2 * MPC8540 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8540ADS"; 15 model = "MPC8540ADS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8540@0 { 33 PowerPC,8540@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8540@e0000000 { 51 soc8540@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00100000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x100000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,8540-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,24 +87,24 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 phy3: ethernet-phy@3 { 104 phy3: ethernet-phy@3 {
104 interrupt-parent = <&mpic>; 105 interrupt-parent = <&mpic>;
105 interrupts = <7 1>; 106 interrupts = <7 1>;
106 reg = <3>; 107 reg = <0x3>;
107 device_type = "ethernet-phy"; 108 device_type = "ethernet-phy";
108 }; 109 };
109 }; 110 };
@@ -113,9 +114,9 @@
113 device_type = "network"; 114 device_type = "network";
114 model = "TSEC"; 115 model = "TSEC";
115 compatible = "gianfar"; 116 compatible = "gianfar";
116 reg = <24000 1000>; 117 reg = <0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ]; 118 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <1d 2 1e 2 22 2>; 119 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>; 120 interrupt-parent = <&mpic>;
120 phy-handle = <&phy0>; 121 phy-handle = <&phy0>;
121 }; 122 };
@@ -125,9 +126,9 @@
125 device_type = "network"; 126 device_type = "network";
126 model = "TSEC"; 127 model = "TSEC";
127 compatible = "gianfar"; 128 compatible = "gianfar";
128 reg = <25000 1000>; 129 reg = <0x25000 0x1000>;
129 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
130 interrupts = <23 2 24 2 28 2>; 131 interrupts = <35 2 36 2 40 2>;
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 phy-handle = <&phy1>; 133 phy-handle = <&phy1>;
133 }; 134 };
@@ -137,9 +138,9 @@
137 device_type = "network"; 138 device_type = "network";
138 model = "FEC"; 139 model = "FEC";
139 compatible = "gianfar"; 140 compatible = "gianfar";
140 reg = <26000 1000>; 141 reg = <0x26000 0x1000>;
141 local-mac-address = [ 00 00 00 00 00 00 ]; 142 local-mac-address = [ 00 00 00 00 00 00 ];
142 interrupts = <29 2>; 143 interrupts = <41 2>;
143 interrupt-parent = <&mpic>; 144 interrupt-parent = <&mpic>;
144 phy-handle = <&phy3>; 145 phy-handle = <&phy3>;
145 }; 146 };
@@ -148,9 +149,9 @@
148 cell-index = <0>; 149 cell-index = <0>;
149 device_type = "serial"; 150 device_type = "serial";
150 compatible = "ns16550"; 151 compatible = "ns16550";
151 reg = <4500 100>; // reg base, size 152 reg = <0x4500 0x100>; // reg base, size
152 clock-frequency = <0>; // should we fill in in uboot? 153 clock-frequency = <0>; // should we fill in in uboot?
153 interrupts = <2a 2>; 154 interrupts = <42 2>;
154 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
155 }; 156 };
156 157
@@ -158,9 +159,9 @@
158 cell-index = <1>; 159 cell-index = <1>;
159 device_type = "serial"; 160 device_type = "serial";
160 compatible = "ns16550"; 161 compatible = "ns16550";
161 reg = <4600 100>; // reg base, size 162 reg = <0x4600 0x100>; // reg base, size
162 clock-frequency = <0>; // should we fill in in uboot? 163 clock-frequency = <0>; // should we fill in in uboot?
163 interrupts = <2a 2>; 164 interrupts = <42 2>;
164 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>;
165 }; 166 };
166 mpic: pic@40000 { 167 mpic: pic@40000 {
@@ -168,7 +169,7 @@
168 interrupt-controller; 169 interrupt-controller;
169 #address-cells = <0>; 170 #address-cells = <0>;
170 #interrupt-cells = <2>; 171 #interrupt-cells = <2>;
171 reg = <40000 40000>; 172 reg = <0x40000 0x40000>;
172 compatible = "chrp,open-pic"; 173 compatible = "chrp,open-pic";
173 device_type = "open-pic"; 174 device_type = "open-pic";
174 big-endian; 175 big-endian;
@@ -177,90 +178,90 @@
177 178
178 pci0: pci@e0008000 { 179 pci0: pci@e0008000 {
179 cell-index = <0>; 180 cell-index = <0>;
180 interrupt-map-mask = <f800 0 0 7>; 181 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
181 interrupt-map = < 182 interrupt-map = <
182 183
183 /* IDSEL 0x02 */ 184 /* IDSEL 0x02 */
184 1000 0 0 1 &mpic 1 1 185 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
185 1000 0 0 2 &mpic 2 1 186 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
186 1000 0 0 3 &mpic 3 1 187 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
187 1000 0 0 4 &mpic 4 1 188 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
188 189
189 /* IDSEL 0x03 */ 190 /* IDSEL 0x03 */
190 1800 0 0 1 &mpic 4 1 191 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
191 1800 0 0 2 &mpic 1 1 192 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
192 1800 0 0 3 &mpic 2 1 193 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
193 1800 0 0 4 &mpic 3 1 194 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
194 195
195 /* IDSEL 0x04 */ 196 /* IDSEL 0x04 */
196 2000 0 0 1 &mpic 3 1 197 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
197 2000 0 0 2 &mpic 4 1 198 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
198 2000 0 0 3 &mpic 1 1 199 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
199 2000 0 0 4 &mpic 2 1 200 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
200 201
201 /* IDSEL 0x05 */ 202 /* IDSEL 0x05 */
202 2800 0 0 1 &mpic 2 1 203 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
203 2800 0 0 2 &mpic 3 1 204 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
204 2800 0 0 3 &mpic 4 1 205 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
205 2800 0 0 4 &mpic 1 1 206 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
206 207
207 /* IDSEL 0x0c */ 208 /* IDSEL 0x0c */
208 6000 0 0 1 &mpic 1 1 209 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
209 6000 0 0 2 &mpic 2 1 210 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
210 6000 0 0 3 &mpic 3 1 211 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
211 6000 0 0 4 &mpic 4 1 212 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
212 213
213 /* IDSEL 0x0d */ 214 /* IDSEL 0x0d */
214 6800 0 0 1 &mpic 4 1 215 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
215 6800 0 0 2 &mpic 1 1 216 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
216 6800 0 0 3 &mpic 2 1 217 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
217 6800 0 0 4 &mpic 3 1 218 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
218 219
219 /* IDSEL 0x0e */ 220 /* IDSEL 0x0e */
220 7000 0 0 1 &mpic 3 1 221 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
221 7000 0 0 2 &mpic 4 1 222 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
222 7000 0 0 3 &mpic 1 1 223 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
223 7000 0 0 4 &mpic 2 1 224 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
224 225
225 /* IDSEL 0x0f */ 226 /* IDSEL 0x0f */
226 7800 0 0 1 &mpic 2 1 227 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
227 7800 0 0 2 &mpic 3 1 228 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
228 7800 0 0 3 &mpic 4 1 229 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
229 7800 0 0 4 &mpic 1 1 230 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
230 231
231 /* IDSEL 0x12 */ 232 /* IDSEL 0x12 */
232 9000 0 0 1 &mpic 1 1 233 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
233 9000 0 0 2 &mpic 2 1 234 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
234 9000 0 0 3 &mpic 3 1 235 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
235 9000 0 0 4 &mpic 4 1 236 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
236 237
237 /* IDSEL 0x13 */ 238 /* IDSEL 0x13 */
238 9800 0 0 1 &mpic 4 1 239 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
239 9800 0 0 2 &mpic 1 1 240 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
240 9800 0 0 3 &mpic 2 1 241 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
241 9800 0 0 4 &mpic 3 1 242 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
242 243
243 /* IDSEL 0x14 */ 244 /* IDSEL 0x14 */
244 a000 0 0 1 &mpic 3 1 245 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
245 a000 0 0 2 &mpic 4 1 246 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
246 a000 0 0 3 &mpic 1 1 247 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
247 a000 0 0 4 &mpic 2 1 248 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
248 249
249 /* IDSEL 0x15 */ 250 /* IDSEL 0x15 */
250 a800 0 0 1 &mpic 2 1 251 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
251 a800 0 0 2 &mpic 3 1 252 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
252 a800 0 0 3 &mpic 4 1 253 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
253 a800 0 0 4 &mpic 1 1>; 254 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
254 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
255 interrupts = <18 2>; 256 interrupts = <24 2>;
256 bus-range = <0 0>; 257 bus-range = <0 0>;
257 ranges = <02000000 0 80000000 80000000 0 20000000 258 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
258 01000000 0 00000000 e2000000 0 00100000>; 259 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
259 clock-frequency = <3f940aa>; 260 clock-frequency = <66666666>;
260 #interrupt-cells = <1>; 261 #interrupt-cells = <1>;
261 #size-cells = <2>; 262 #size-cells = <2>;
262 #address-cells = <3>; 263 #address-cells = <3>;
263 reg = <e0008000 1000>; 264 reg = <0xe0008000 0x1000>;
264 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
265 device_type = "pci"; 266 device_type = "pci";
266 }; 267 };
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fa8d9aaad157..663c7c50ca45 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8541 CDS Device Tree Source 2 * MPC8541 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8541CDS"; 15 model = "MPC8541CDS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8541@0 { 33 PowerPC,8541@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8541@e0000000 { 51 soc8541@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00001000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8541-memory-controller"; 60 compatible = "fsl,8541-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8541-l2-cache-controller"; 67 compatible = "fsl,8541-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,18 +87,18 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 }; 104 };
@@ -107,9 +108,9 @@
107 device_type = "network"; 108 device_type = "network";
108 model = "TSEC"; 109 model = "TSEC";
109 compatible = "gianfar"; 110 compatible = "gianfar";
110 reg = <24000 1000>; 111 reg = <0x24000 0x1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>; 113 interrupts = <29 2 30 2 34 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>; 115 phy-handle = <&phy0>;
115 }; 116 };
@@ -119,9 +120,9 @@
119 device_type = "network"; 120 device_type = "network";
120 model = "TSEC"; 121 model = "TSEC";
121 compatible = "gianfar"; 122 compatible = "gianfar";
122 reg = <25000 1000>; 123 reg = <0x25000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 124 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <23 2 24 2 28 2>; 125 interrupts = <35 2 36 2 40 2>;
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 phy-handle = <&phy1>; 127 phy-handle = <&phy1>;
127 }; 128 };
@@ -130,9 +131,9 @@
130 cell-index = <0>; 131 cell-index = <0>;
131 device_type = "serial"; 132 device_type = "serial";
132 compatible = "ns16550"; 133 compatible = "ns16550";
133 reg = <4500 100>; // reg base, size 134 reg = <0x4500 0x100>; // reg base, size
134 clock-frequency = <0>; // should we fill in in uboot? 135 clock-frequency = <0>; // should we fill in in uboot?
135 interrupts = <2a 2>; 136 interrupts = <42 2>;
136 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
137 }; 138 };
138 139
@@ -140,9 +141,9 @@
140 cell-index = <1>; 141 cell-index = <1>;
141 device_type = "serial"; 142 device_type = "serial";
142 compatible = "ns16550"; 143 compatible = "ns16550";
143 reg = <4600 100>; // reg base, size 144 reg = <0x4600 0x100>; // reg base, size
144 clock-frequency = <0>; // should we fill in in uboot? 145 clock-frequency = <0>; // should we fill in in uboot?
145 interrupts = <2a 2>; 146 interrupts = <42 2>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 }; 148 };
148 149
@@ -151,7 +152,7 @@
151 interrupt-controller; 152 interrupt-controller;
152 #address-cells = <0>; 153 #address-cells = <0>;
153 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
154 reg = <40000 40000>; 155 reg = <0x40000 0x40000>;
155 compatible = "chrp,open-pic"; 156 compatible = "chrp,open-pic";
156 device_type = "open-pic"; 157 device_type = "open-pic";
157 big-endian; 158 big-endian;
@@ -161,17 +162,17 @@
161 #address-cells = <1>; 162 #address-cells = <1>;
162 #size-cells = <1>; 163 #size-cells = <1>;
163 compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; 164 compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
164 reg = <919c0 30>; 165 reg = <0x919c0 0x30>;
165 ranges; 166 ranges;
166 167
167 muram@80000 { 168 muram@80000 {
168 #address-cells = <1>; 169 #address-cells = <1>;
169 #size-cells = <1>; 170 #size-cells = <1>;
170 ranges = <0 80000 10000>; 171 ranges = <0x0 0x80000 0x10000>;
171 172
172 data@0 { 173 data@0 {
173 compatible = "fsl,cpm-muram-data"; 174 compatible = "fsl,cpm-muram-data";
174 reg = <0 2000 9000 1000>; 175 reg = <0x0 0x2000 0x9000 0x1000>;
175 }; 176 };
176 }; 177 };
177 178
@@ -179,16 +180,16 @@
179 compatible = "fsl,mpc8541-brg", 180 compatible = "fsl,mpc8541-brg",
180 "fsl,cpm2-brg", 181 "fsl,cpm2-brg",
181 "fsl,cpm-brg"; 182 "fsl,cpm-brg";
182 reg = <919f0 10 915f0 10>; 183 reg = <0x919f0 0x10 0x915f0 0x10>;
183 }; 184 };
184 185
185 cpmpic: pic@90c00 { 186 cpmpic: pic@90c00 {
186 interrupt-controller; 187 interrupt-controller;
187 #address-cells = <0>; 188 #address-cells = <0>;
188 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
189 interrupts = <2e 2>; 190 interrupts = <46 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 reg = <90c00 80>; 192 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 193 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
193 }; 194 };
194 }; 195 };
@@ -196,68 +197,68 @@
196 197
197 pci0: pci@e0008000 { 198 pci0: pci@e0008000 {
198 cell-index = <0>; 199 cell-index = <0>;
199 interrupt-map-mask = <1f800 0 0 7>; 200 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
200 interrupt-map = < 201 interrupt-map = <
201 202
202 /* IDSEL 0x10 */ 203 /* IDSEL 0x10 */
203 08000 0 0 1 &mpic 0 1 204 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 08000 0 0 2 &mpic 1 1 205 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 08000 0 0 3 &mpic 2 1 206 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 08000 0 0 4 &mpic 3 1 207 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
207 208
208 /* IDSEL 0x11 */ 209 /* IDSEL 0x11 */
209 08800 0 0 1 &mpic 0 1 210 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 08800 0 0 2 &mpic 1 1 211 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 08800 0 0 3 &mpic 2 1 212 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 08800 0 0 4 &mpic 3 1 213 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
213 214
214 /* IDSEL 0x12 (Slot 1) */ 215 /* IDSEL 0x12 (Slot 1) */
215 09000 0 0 1 &mpic 0 1 216 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 09000 0 0 2 &mpic 1 1 217 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 09000 0 0 3 &mpic 2 1 218 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 09000 0 0 4 &mpic 3 1 219 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
219 220
220 /* IDSEL 0x13 (Slot 2) */ 221 /* IDSEL 0x13 (Slot 2) */
221 09800 0 0 1 &mpic 1 1 222 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 09800 0 0 2 &mpic 2 1 223 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 09800 0 0 3 &mpic 3 1 224 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 09800 0 0 4 &mpic 0 1 225 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
225 226
226 /* IDSEL 0x14 (Slot 3) */ 227 /* IDSEL 0x14 (Slot 3) */
227 0a000 0 0 1 &mpic 2 1 228 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0a000 0 0 2 &mpic 3 1 229 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0a000 0 0 3 &mpic 0 1 230 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0a000 0 0 4 &mpic 1 1 231 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
231 232
232 /* IDSEL 0x15 (Slot 4) */ 233 /* IDSEL 0x15 (Slot 4) */
233 0a800 0 0 1 &mpic 3 1 234 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0a800 0 0 2 &mpic 0 1 235 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0a800 0 0 3 &mpic 1 1 236 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0a800 0 0 4 &mpic 2 1 237 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
237 238
238 /* Bus 1 (Tundra Bridge) */ 239 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */ 240 /* IDSEL 0x12 (ISA bridge) */
240 19000 0 0 1 &mpic 0 1 241 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 19000 0 0 2 &mpic 1 1 242 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 19000 0 0 3 &mpic 2 1 243 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 19000 0 0 4 &mpic 3 1>; 244 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 0>; 247 bus-range = <0 0>;
247 ranges = <02000000 0 80000000 80000000 0 20000000 248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 01000000 0 00000000 e2000000 0 00100000>; 249 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci"; 255 compatible = "fsl,mpc8540-pci";
255 device_type = "pci"; 256 device_type = "pci";
256 257
257 i8259@19000 { 258 i8259@19000 {
258 interrupt-controller; 259 interrupt-controller;
259 device_type = "interrupt-controller"; 260 device_type = "interrupt-controller";
260 reg = <19000 0 0 0 1>; 261 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>; 262 #address-cells = <0>;
262 #interrupt-cells = <2>; 263 #interrupt-cells = <2>;
263 compatible = "chrp,iic"; 264 compatible = "chrp,iic";
@@ -268,24 +269,24 @@
268 269
269 pci1: pci@e0009000 { 270 pci1: pci@e0009000 {
270 cell-index = <1>; 271 cell-index = <1>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
272 interrupt-map = < 273 interrupt-map = <
273 274
274 /* IDSEL 0x15 */ 275 /* IDSEL 0x15 */
275 a800 0 0 1 &mpic b 1 276 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 a800 0 0 2 &mpic b 1 277 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 a800 0 0 3 &mpic b 1 278 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 a800 0 0 4 &mpic b 1>; 279 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>; 280 interrupt-parent = <&mpic>;
280 interrupts = <19 2>; 281 interrupts = <25 2>;
281 bus-range = <0 0>; 282 bus-range = <0 0>;
282 ranges = <02000000 0 a0000000 a0000000 0 20000000 283 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 01000000 0 00000000 e3000000 0 00100000>; 284 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <3f940aa>; 285 clock-frequency = <66666666>;
285 #interrupt-cells = <1>; 286 #interrupt-cells = <1>;
286 #size-cells = <2>; 287 #size-cells = <2>;
287 #address-cells = <3>; 288 #address-cells = <3>;
288 reg = <e0009000 1000>; 289 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci"; 290 compatible = "fsl,mpc8540-pci";
290 device_type = "pci"; 291 device_type = "pci";
291 }; 292 };
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 688af9d06382..6a0d8db96d97 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8544 DS Device Tree Source 2 * MPC8544 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "MPC8544DS"; 14 model = "MPC8544DS";
14 compatible = "MPC8544DS", "MPC85xxDS"; 15 compatible = "MPC8544DS", "MPC85xxDS";
@@ -27,17 +28,16 @@
27 }; 28 };
28 29
29 cpus { 30 cpus {
30 #cpus = <1>;
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 33
34 PowerPC,8544@0 { 34 PowerPC,8544@0 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 reg = <0>; 36 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 41 timebase-frequency = <0>;
42 bus-frequency = <0>; 42 bus-frequency = <0>;
43 clock-frequency = <0>; 43 clock-frequency = <0>;
@@ -46,7 +46,7 @@
46 46
47 memory { 47 memory {
48 device_type = "memory"; 48 device_type = "memory";
49 reg = <00000000 00000000>; // Filled by U-Boot 49 reg = <0x0 0x0>; // Filled by U-Boot
50 }; 50 };
51 51
52 soc8544@e0000000 { 52 soc8544@e0000000 {
@@ -54,24 +54,24 @@
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc"; 55 device_type = "soc";
56 56
57 ranges = <00000000 e0000000 00100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <e0000000 00001000>; // CCSRBAR 1M 58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
59 bus-frequency = <0>; // Filled out by uboot. 59 bus-frequency = <0>; // Filled out by uboot.
60 60
61 memory-controller@2000 { 61 memory-controller@2000 {
62 compatible = "fsl,8544-memory-controller"; 62 compatible = "fsl,8544-memory-controller";
63 reg = <2000 1000>; 63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>; 64 interrupt-parent = <&mpic>;
65 interrupts = <12 2>; 65 interrupts = <18 2>;
66 }; 66 };
67 67
68 l2-cache-controller@20000 { 68 l2-cache-controller@20000 {
69 compatible = "fsl,8544-l2-cache-controller"; 69 compatible = "fsl,8544-l2-cache-controller";
70 reg = <20000 1000>; 70 reg = <0x20000 0x1000>;
71 cache-line-size = <20>; // 32 bytes 71 cache-line-size = <32>; // 32 bytes
72 cache-size = <40000>; // L2, 256K 72 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>; 73 interrupt-parent = <&mpic>;
74 interrupts = <10 2>; 74 interrupts = <16 2>;
75 }; 75 };
76 76
77 i2c@3000 { 77 i2c@3000 {
@@ -79,8 +79,8 @@
79 #size-cells = <0>; 79 #size-cells = <0>;
80 cell-index = <0>; 80 cell-index = <0>;
81 compatible = "fsl-i2c"; 81 compatible = "fsl-i2c";
82 reg = <3000 100>; 82 reg = <0x3000 0x100>;
83 interrupts = <2b 2>; 83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>; 84 interrupt-parent = <&mpic>;
85 dfsrr; 85 dfsrr;
86 }; 86 };
@@ -90,8 +90,8 @@
90 #size-cells = <0>; 90 #size-cells = <0>;
91 cell-index = <1>; 91 cell-index = <1>;
92 compatible = "fsl-i2c"; 92 compatible = "fsl-i2c";
93 reg = <3100 100>; 93 reg = <0x3100 0x100>;
94 interrupts = <2b 2>; 94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>;
96 dfsrr; 96 dfsrr;
97 }; 97 };
@@ -100,30 +100,71 @@
100 #address-cells = <1>; 100 #address-cells = <1>;
101 #size-cells = <0>; 101 #size-cells = <0>;
102 compatible = "fsl,gianfar-mdio"; 102 compatible = "fsl,gianfar-mdio";
103 reg = <24520 20>; 103 reg = <0x24520 0x20>;
104 104
105 phy0: ethernet-phy@0 { 105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>; 106 interrupt-parent = <&mpic>;
107 interrupts = <a 1>; 107 interrupts = <10 1>;
108 reg = <0>; 108 reg = <0x0>;
109 device_type = "ethernet-phy"; 109 device_type = "ethernet-phy";
110 }; 110 };
111 phy1: ethernet-phy@1 { 111 phy1: ethernet-phy@1 {
112 interrupt-parent = <&mpic>; 112 interrupt-parent = <&mpic>;
113 interrupts = <a 1>; 113 interrupts = <10 1>;
114 reg = <1>; 114 reg = <0x1>;
115 device_type = "ethernet-phy"; 115 device_type = "ethernet-phy";
116 }; 116 };
117 }; 117 };
118 118
119 dma@21300 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
123 reg = <0x21300 0x4>;
124 ranges = <0x0 0x21100 0x200>;
125 cell-index = <0>;
126 dma-channel@0 {
127 compatible = "fsl,mpc8544-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x0 0x80>;
130 cell-index = <0>;
131 interrupt-parent = <&mpic>;
132 interrupts = <20 2>;
133 };
134 dma-channel@80 {
135 compatible = "fsl,mpc8544-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x80 0x80>;
138 cell-index = <1>;
139 interrupt-parent = <&mpic>;
140 interrupts = <21 2>;
141 };
142 dma-channel@100 {
143 compatible = "fsl,mpc8544-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x100 0x80>;
146 cell-index = <2>;
147 interrupt-parent = <&mpic>;
148 interrupts = <22 2>;
149 };
150 dma-channel@180 {
151 compatible = "fsl,mpc8544-dma-channel",
152 "fsl,eloplus-dma-channel";
153 reg = <0x180 0x80>;
154 cell-index = <3>;
155 interrupt-parent = <&mpic>;
156 interrupts = <23 2>;
157 };
158 };
159
119 enet0: ethernet@24000 { 160 enet0: ethernet@24000 {
120 cell-index = <0>; 161 cell-index = <0>;
121 device_type = "network"; 162 device_type = "network";
122 model = "TSEC"; 163 model = "TSEC";
123 compatible = "gianfar"; 164 compatible = "gianfar";
124 reg = <24000 1000>; 165 reg = <0x24000 0x1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ]; 166 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <1d 2 1e 2 22 2>; 167 interrupts = <29 2 30 2 34 2>;
127 interrupt-parent = <&mpic>; 168 interrupt-parent = <&mpic>;
128 phy-handle = <&phy0>; 169 phy-handle = <&phy0>;
129 phy-connection-type = "rgmii-id"; 170 phy-connection-type = "rgmii-id";
@@ -134,9 +175,9 @@
134 device_type = "network"; 175 device_type = "network";
135 model = "TSEC"; 176 model = "TSEC";
136 compatible = "gianfar"; 177 compatible = "gianfar";
137 reg = <26000 1000>; 178 reg = <0x26000 0x1000>;
138 local-mac-address = [ 00 00 00 00 00 00 ]; 179 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <1f 2 20 2 21 2>; 180 interrupts = <31 2 32 2 33 2>;
140 interrupt-parent = <&mpic>; 181 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>; 182 phy-handle = <&phy1>;
142 phy-connection-type = "rgmii-id"; 183 phy-connection-type = "rgmii-id";
@@ -146,9 +187,9 @@
146 cell-index = <0>; 187 cell-index = <0>;
147 device_type = "serial"; 188 device_type = "serial";
148 compatible = "ns16550"; 189 compatible = "ns16550";
149 reg = <4500 100>; 190 reg = <0x4500 0x100>;
150 clock-frequency = <0>; 191 clock-frequency = <0>;
151 interrupts = <2a 2>; 192 interrupts = <42 2>;
152 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
153 }; 194 };
154 195
@@ -156,15 +197,15 @@
156 cell-index = <1>; 197 cell-index = <1>;
157 device_type = "serial"; 198 device_type = "serial";
158 compatible = "ns16550"; 199 compatible = "ns16550";
159 reg = <4600 100>; 200 reg = <0x4600 0x100>;
160 clock-frequency = <0>; 201 clock-frequency = <0>;
161 interrupts = <2a 2>; 202 interrupts = <42 2>;
162 interrupt-parent = <&mpic>; 203 interrupt-parent = <&mpic>;
163 }; 204 };
164 205
165 global-utilities@e0000 { //global utilities block 206 global-utilities@e0000 { //global utilities block
166 compatible = "fsl,mpc8548-guts"; 207 compatible = "fsl,mpc8548-guts";
167 reg = <e0000 1000>; 208 reg = <0xe0000 0x1000>;
168 fsl,has-rstcr; 209 fsl,has-rstcr;
169 }; 210 };
170 211
@@ -173,7 +214,7 @@
173 interrupt-controller; 214 interrupt-controller;
174 #address-cells = <0>; 215 #address-cells = <0>;
175 #interrupt-cells = <2>; 216 #interrupt-cells = <2>;
176 reg = <40000 40000>; 217 reg = <0x40000 0x40000>;
177 compatible = "chrp,open-pic"; 218 compatible = "chrp,open-pic";
178 device_type = "open-pic"; 219 device_type = "open-pic";
179 big-endian; 220 big-endian;
@@ -184,32 +225,32 @@
184 cell-index = <0>; 225 cell-index = <0>;
185 compatible = "fsl,mpc8540-pci"; 226 compatible = "fsl,mpc8540-pci";
186 device_type = "pci"; 227 device_type = "pci";
187 interrupt-map-mask = <f800 0 0 7>; 228 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
188 interrupt-map = < 229 interrupt-map = <
189 230
190 /* IDSEL 0x11 J17 Slot 1 */ 231 /* IDSEL 0x11 J17 Slot 1 */
191 8800 0 0 1 &mpic 2 1 232 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
192 8800 0 0 2 &mpic 3 1 233 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
193 8800 0 0 3 &mpic 4 1 234 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
194 8800 0 0 4 &mpic 1 1 235 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
195 236
196 /* IDSEL 0x12 J16 Slot 2 */ 237 /* IDSEL 0x12 J16 Slot 2 */
197 238
198 9000 0 0 1 &mpic 3 1 239 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
199 9000 0 0 2 &mpic 4 1 240 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
200 9000 0 0 3 &mpic 2 1 241 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
201 9000 0 0 4 &mpic 1 1>; 242 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
202 243
203 interrupt-parent = <&mpic>; 244 interrupt-parent = <&mpic>;
204 interrupts = <18 2>; 245 interrupts = <24 2>;
205 bus-range = <0 ff>; 246 bus-range = <0 255>;
206 ranges = <02000000 0 c0000000 c0000000 0 20000000 247 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
207 01000000 0 00000000 e1000000 0 00010000>; 248 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
208 clock-frequency = <3f940aa>; 249 clock-frequency = <66666666>;
209 #interrupt-cells = <1>; 250 #interrupt-cells = <1>;
210 #size-cells = <2>; 251 #size-cells = <2>;
211 #address-cells = <3>; 252 #address-cells = <3>;
212 reg = <e0008000 1000>; 253 reg = <0xe0008000 0x1000>;
213 }; 254 };
214 255
215 pci1: pcie@e0009000 { 256 pci1: pcie@e0009000 {
@@ -219,33 +260,33 @@
219 #interrupt-cells = <1>; 260 #interrupt-cells = <1>;
220 #size-cells = <2>; 261 #size-cells = <2>;
221 #address-cells = <3>; 262 #address-cells = <3>;
222 reg = <e0009000 1000>; 263 reg = <0xe0009000 0x1000>;
223 bus-range = <0 ff>; 264 bus-range = <0 255>;
224 ranges = <02000000 0 80000000 80000000 0 20000000 265 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
225 01000000 0 00000000 e1010000 0 00010000>; 266 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
226 clock-frequency = <1fca055>; 267 clock-frequency = <33333333>;
227 interrupt-parent = <&mpic>; 268 interrupt-parent = <&mpic>;
228 interrupts = <1a 2>; 269 interrupts = <26 2>;
229 interrupt-map-mask = <f800 0 0 7>; 270 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
230 interrupt-map = < 271 interrupt-map = <
231 /* IDSEL 0x0 */ 272 /* IDSEL 0x0 */
232 0000 0 0 1 &mpic 4 1 273 0000 0x0 0x0 0x1 &mpic 0x4 0x1
233 0000 0 0 2 &mpic 5 1 274 0000 0x0 0x0 0x2 &mpic 0x5 0x1
234 0000 0 0 3 &mpic 6 1 275 0000 0x0 0x0 0x3 &mpic 0x6 0x1
235 0000 0 0 4 &mpic 7 1 276 0000 0x0 0x0 0x4 &mpic 0x7 0x1
236 >; 277 >;
237 pcie@0 { 278 pcie@0 {
238 reg = <0 0 0 0 0>; 279 reg = <0x0 0x0 0x0 0x0 0x0>;
239 #size-cells = <2>; 280 #size-cells = <2>;
240 #address-cells = <3>; 281 #address-cells = <3>;
241 device_type = "pci"; 282 device_type = "pci";
242 ranges = <02000000 0 80000000 283 ranges = <0x2000000 0x0 0x80000000
243 02000000 0 80000000 284 0x2000000 0x0 0x80000000
244 0 20000000 285 0x0 0x20000000
245 286
246 01000000 0 00000000 287 0x1000000 0x0 0x0
247 01000000 0 00000000 288 0x1000000 0x0 0x0
248 0 00010000>; 289 0x0 0x10000>;
249 }; 290 };
250 }; 291 };
251 292
@@ -256,33 +297,33 @@
256 #interrupt-cells = <1>; 297 #interrupt-cells = <1>;
257 #size-cells = <2>; 298 #size-cells = <2>;
258 #address-cells = <3>; 299 #address-cells = <3>;
259 reg = <e000a000 1000>; 300 reg = <0xe000a000 0x1000>;
260 bus-range = <0 ff>; 301 bus-range = <0 255>;
261 ranges = <02000000 0 a0000000 a0000000 0 10000000 302 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
262 01000000 0 00000000 e1020000 0 00010000>; 303 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
263 clock-frequency = <1fca055>; 304 clock-frequency = <33333333>;
264 interrupt-parent = <&mpic>; 305 interrupt-parent = <&mpic>;
265 interrupts = <19 2>; 306 interrupts = <25 2>;
266 interrupt-map-mask = <f800 0 0 7>; 307 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
267 interrupt-map = < 308 interrupt-map = <
268 /* IDSEL 0x0 */ 309 /* IDSEL 0x0 */
269 0000 0 0 1 &mpic 0 1 310 0000 0x0 0x0 0x1 &mpic 0x0 0x1
270 0000 0 0 2 &mpic 1 1 311 0000 0x0 0x0 0x2 &mpic 0x1 0x1
271 0000 0 0 3 &mpic 2 1 312 0000 0x0 0x0 0x3 &mpic 0x2 0x1
272 0000 0 0 4 &mpic 3 1 313 0000 0x0 0x0 0x4 &mpic 0x3 0x1
273 >; 314 >;
274 pcie@0 { 315 pcie@0 {
275 reg = <0 0 0 0 0>; 316 reg = <0x0 0x0 0x0 0x0 0x0>;
276 #size-cells = <2>; 317 #size-cells = <2>;
277 #address-cells = <3>; 318 #address-cells = <3>;
278 device_type = "pci"; 319 device_type = "pci";
279 ranges = <02000000 0 a0000000 320 ranges = <0x2000000 0x0 0xa0000000
280 02000000 0 a0000000 321 0x2000000 0x0 0xa0000000
281 0 10000000 322 0x0 0x10000000
282 323
283 01000000 0 00000000 324 0x1000000 0x0 0x0
284 01000000 0 00000000 325 0x1000000 0x0 0x0
285 0 00010000>; 326 0x0 0x10000>;
286 }; 327 };
287 }; 328 };
288 329
@@ -293,72 +334,72 @@
293 #interrupt-cells = <1>; 334 #interrupt-cells = <1>;
294 #size-cells = <2>; 335 #size-cells = <2>;
295 #address-cells = <3>; 336 #address-cells = <3>;
296 reg = <e000b000 1000>; 337 reg = <0xe000b000 0x1000>;
297 bus-range = <0 ff>; 338 bus-range = <0 255>;
298 ranges = <02000000 0 b0000000 b0000000 0 00100000 339 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
299 01000000 0 00000000 b0100000 0 00100000>; 340 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
300 clock-frequency = <1fca055>; 341 clock-frequency = <33333333>;
301 interrupt-parent = <&mpic>; 342 interrupt-parent = <&mpic>;
302 interrupts = <1b 2>; 343 interrupts = <27 2>;
303 interrupt-map-mask = <ff00 0 0 1>; 344 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
304 interrupt-map = < 345 interrupt-map = <
305 // IDSEL 0x1c USB 346 // IDSEL 0x1c USB
306 e000 0 0 1 &i8259 c 2 347 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
307 e100 0 0 2 &i8259 9 2 348 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
308 e200 0 0 3 &i8259 a 2 349 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
309 e300 0 0 4 &i8259 b 2 350 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
310 351
311 // IDSEL 0x1d Audio 352 // IDSEL 0x1d Audio
312 e800 0 0 1 &i8259 6 2 353 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
313 354
314 // IDSEL 0x1e Legacy 355 // IDSEL 0x1e Legacy
315 f000 0 0 1 &i8259 7 2 356 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
316 f100 0 0 1 &i8259 7 2 357 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
317 358
318 // IDSEL 0x1f IDE/SATA 359 // IDSEL 0x1f IDE/SATA
319 f800 0 0 1 &i8259 e 2 360 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
320 f900 0 0 1 &i8259 5 2 361 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
321 >; 362 >;
322 363
323 pcie@0 { 364 pcie@0 {
324 reg = <0 0 0 0 0>; 365 reg = <0x0 0x0 0x0 0x0 0x0>;
325 #size-cells = <2>; 366 #size-cells = <2>;
326 #address-cells = <3>; 367 #address-cells = <3>;
327 device_type = "pci"; 368 device_type = "pci";
328 ranges = <02000000 0 b0000000 369 ranges = <0x2000000 0x0 0xb0000000
329 02000000 0 b0000000 370 0x2000000 0x0 0xb0000000
330 0 00100000 371 0x0 0x100000
331 372
332 01000000 0 00000000 373 0x1000000 0x0 0x0
333 01000000 0 00000000 374 0x1000000 0x0 0x0
334 0 00100000>; 375 0x0 0x100000>;
335 376
336 uli1575@0 { 377 uli1575@0 {
337 reg = <0 0 0 0 0>; 378 reg = <0x0 0x0 0x0 0x0 0x0>;
338 #size-cells = <2>; 379 #size-cells = <2>;
339 #address-cells = <3>; 380 #address-cells = <3>;
340 ranges = <02000000 0 b0000000 381 ranges = <0x2000000 0x0 0xb0000000
341 02000000 0 b0000000 382 0x2000000 0x0 0xb0000000
342 0 00100000 383 0x0 0x100000
343 384
344 01000000 0 00000000 385 0x1000000 0x0 0x0
345 01000000 0 00000000 386 0x1000000 0x0 0x0
346 0 00100000>; 387 0x0 0x100000>;
347 isa@1e { 388 isa@1e {
348 device_type = "isa"; 389 device_type = "isa";
349 #interrupt-cells = <2>; 390 #interrupt-cells = <2>;
350 #size-cells = <1>; 391 #size-cells = <1>;
351 #address-cells = <2>; 392 #address-cells = <2>;
352 reg = <f000 0 0 0 0>; 393 reg = <0xf000 0x0 0x0 0x0 0x0>;
353 ranges = <1 0 394 ranges = <0x1 0x0
354 01000000 0 0 395 0x1000000 0x0 0x0
355 00001000>; 396 0x1000>;
356 interrupt-parent = <&i8259>; 397 interrupt-parent = <&i8259>;
357 398
358 i8259: interrupt-controller@20 { 399 i8259: interrupt-controller@20 {
359 reg = <1 20 2 400 reg = <0x1 0x20 0x2
360 1 a0 2 401 0x1 0xa0 0x2
361 1 4d0 2>; 402 0x1 0x4d0 0x2>;
362 interrupt-controller; 403 interrupt-controller;
363 device_type = "interrupt-controller"; 404 device_type = "interrupt-controller";
364 #address-cells = <0>; 405 #address-cells = <0>;
@@ -371,28 +412,28 @@
371 i8042@60 { 412 i8042@60 {
372 #size-cells = <0>; 413 #size-cells = <0>;
373 #address-cells = <1>; 414 #address-cells = <1>;
374 reg = <1 60 1 1 64 1>; 415 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
375 interrupts = <1 3 c 3>; 416 interrupts = <1 3 12 3>;
376 interrupt-parent = <&i8259>; 417 interrupt-parent = <&i8259>;
377 418
378 keyboard@0 { 419 keyboard@0 {
379 reg = <0>; 420 reg = <0x0>;
380 compatible = "pnpPNP,303"; 421 compatible = "pnpPNP,303";
381 }; 422 };
382 423
383 mouse@1 { 424 mouse@1 {
384 reg = <1>; 425 reg = <0x1>;
385 compatible = "pnpPNP,f03"; 426 compatible = "pnpPNP,f03";
386 }; 427 };
387 }; 428 };
388 429
389 rtc@70 { 430 rtc@70 {
390 compatible = "pnpPNP,b00"; 431 compatible = "pnpPNP,b00";
391 reg = <1 70 2>; 432 reg = <0x1 0x70 0x2>;
392 }; 433 };
393 434
394 gpio@400 { 435 gpio@400 {
395 reg = <1 400 80>; 436 reg = <0x1 0x400 0x80>;
396 }; 437 };
397 }; 438 };
398 }; 439 };
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 1f470c6a1c63..fa298a8c81cc 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8548 CDS Device Tree Source 2 * MPC8548 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8548CDS"; 15 model = "MPC8548CDS";
@@ -36,11 +37,11 @@
36 37
37 PowerPC,8548@0 { 38 PowerPC,8548@0 {
38 device_type = "cpu"; 39 device_type = "cpu";
39 reg = <0>; 40 reg = <0x0>;
40 d-cache-line-size = <20>; // 32 bytes 41 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <20>; // 32 bytes 42 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <8000>; // L1, 32K 43 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <8000>; // L1, 32K 44 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>; // 33 MHz, from uboot 45 timebase-frequency = <0>; // 33 MHz, from uboot
45 bus-frequency = <0>; // 166 MHz 46 bus-frequency = <0>; // 166 MHz
46 clock-frequency = <0>; // 825 MHz, from uboot 47 clock-frequency = <0>; // 825 MHz, from uboot
@@ -49,31 +50,31 @@
49 50
50 memory { 51 memory {
51 device_type = "memory"; 52 device_type = "memory";
52 reg = <00000000 08000000>; // 128M at 0x0 53 reg = <0x0 0x8000000>; // 128M at 0x0
53 }; 54 };
54 55
55 soc8548@e0000000 { 56 soc8548@e0000000 {
56 #address-cells = <1>; 57 #address-cells = <1>;
57 #size-cells = <1>; 58 #size-cells = <1>;
58 device_type = "soc"; 59 device_type = "soc";
59 ranges = <00000000 e0000000 00100000>; 60 ranges = <0x0 0xe0000000 0x100000>;
60 reg = <e0000000 00001000>; // CCSRBAR 61 reg = <0xe0000000 0x1000>; // CCSRBAR
61 bus-frequency = <0>; 62 bus-frequency = <0>;
62 63
63 memory-controller@2000 { 64 memory-controller@2000 {
64 compatible = "fsl,8548-memory-controller"; 65 compatible = "fsl,8548-memory-controller";
65 reg = <2000 1000>; 66 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>; 67 interrupt-parent = <&mpic>;
67 interrupts = <12 2>; 68 interrupts = <18 2>;
68 }; 69 };
69 70
70 l2-cache-controller@20000 { 71 l2-cache-controller@20000 {
71 compatible = "fsl,8548-l2-cache-controller"; 72 compatible = "fsl,8548-l2-cache-controller";
72 reg = <20000 1000>; 73 reg = <0x20000 0x1000>;
73 cache-line-size = <20>; // 32 bytes 74 cache-line-size = <32>; // 32 bytes
74 cache-size = <80000>; // L2, 512K 75 cache-size = <0x80000>; // L2, 512K
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <10 2>; 77 interrupts = <16 2>;
77 }; 78 };
78 79
79 i2c@3000 { 80 i2c@3000 {
@@ -81,8 +82,8 @@
81 #size-cells = <0>; 82 #size-cells = <0>;
82 cell-index = <0>; 83 cell-index = <0>;
83 compatible = "fsl-i2c"; 84 compatible = "fsl-i2c";
84 reg = <3000 100>; 85 reg = <0x3000 0x100>;
85 interrupts = <2b 2>; 86 interrupts = <43 2>;
86 interrupt-parent = <&mpic>; 87 interrupt-parent = <&mpic>;
87 dfsrr; 88 dfsrr;
88 }; 89 };
@@ -92,8 +93,8 @@
92 #size-cells = <0>; 93 #size-cells = <0>;
93 cell-index = <1>; 94 cell-index = <1>;
94 compatible = "fsl-i2c"; 95 compatible = "fsl-i2c";
95 reg = <3100 100>; 96 reg = <0x3100 0x100>;
96 interrupts = <2b 2>; 97 interrupts = <43 2>;
97 interrupt-parent = <&mpic>; 98 interrupt-parent = <&mpic>;
98 dfsrr; 99 dfsrr;
99 }; 100 };
@@ -102,30 +103,30 @@
102 #address-cells = <1>; 103 #address-cells = <1>;
103 #size-cells = <0>; 104 #size-cells = <0>;
104 compatible = "fsl,gianfar-mdio"; 105 compatible = "fsl,gianfar-mdio";
105 reg = <24520 20>; 106 reg = <0x24520 0x20>;
106 107
107 phy0: ethernet-phy@0 { 108 phy0: ethernet-phy@0 {
108 interrupt-parent = <&mpic>; 109 interrupt-parent = <&mpic>;
109 interrupts = <5 1>; 110 interrupts = <5 1>;
110 reg = <0>; 111 reg = <0x0>;
111 device_type = "ethernet-phy"; 112 device_type = "ethernet-phy";
112 }; 113 };
113 phy1: ethernet-phy@1 { 114 phy1: ethernet-phy@1 {
114 interrupt-parent = <&mpic>; 115 interrupt-parent = <&mpic>;
115 interrupts = <5 1>; 116 interrupts = <5 1>;
116 reg = <1>; 117 reg = <0x1>;
117 device_type = "ethernet-phy"; 118 device_type = "ethernet-phy";
118 }; 119 };
119 phy2: ethernet-phy@2 { 120 phy2: ethernet-phy@2 {
120 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>;
121 interrupts = <5 1>; 122 interrupts = <5 1>;
122 reg = <2>; 123 reg = <0x2>;
123 device_type = "ethernet-phy"; 124 device_type = "ethernet-phy";
124 }; 125 };
125 phy3: ethernet-phy@3 { 126 phy3: ethernet-phy@3 {
126 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
127 interrupts = <5 1>; 128 interrupts = <5 1>;
128 reg = <3>; 129 reg = <0x3>;
129 device_type = "ethernet-phy"; 130 device_type = "ethernet-phy";
130 }; 131 };
131 }; 132 };
@@ -135,9 +136,9 @@
135 device_type = "network"; 136 device_type = "network";
136 model = "eTSEC"; 137 model = "eTSEC";
137 compatible = "gianfar"; 138 compatible = "gianfar";
138 reg = <24000 1000>; 139 reg = <0x24000 0x1000>;
139 local-mac-address = [ 00 00 00 00 00 00 ]; 140 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupts = <1d 2 1e 2 22 2>; 141 interrupts = <29 2 30 2 34 2>;
141 interrupt-parent = <&mpic>; 142 interrupt-parent = <&mpic>;
142 phy-handle = <&phy0>; 143 phy-handle = <&phy0>;
143 }; 144 };
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <25000 1000>; 151 reg = <0x25000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <23 2 24 2 28 2>; 153 interrupts = <35 2 36 2 40 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy1>; 155 phy-handle = <&phy1>;
155 }; 156 };
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <26000 1000>; 164 reg = <0x26000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <1f 2 20 2 21 2>; 166 interrupts = <31 2 32 2 33 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy2>; 168 phy-handle = <&phy2>;
168 }; 169 };
@@ -172,9 +173,9 @@
172 device_type = "network"; 173 device_type = "network";
173 model = "eTSEC"; 174 model = "eTSEC";
174 compatible = "gianfar"; 175 compatible = "gianfar";
175 reg = <27000 1000>; 176 reg = <0x27000 0x1000>;
176 local-mac-address = [ 00 00 00 00 00 00 ]; 177 local-mac-address = [ 00 00 00 00 00 00 ];
177 interrupts = <25 2 26 2 27 2>; 178 interrupts = <37 2 38 2 39 2>;
178 interrupt-parent = <&mpic>; 179 interrupt-parent = <&mpic>;
179 phy-handle = <&phy3>; 180 phy-handle = <&phy3>;
180 }; 181 };
@@ -184,9 +185,9 @@
184 cell-index = <0>; 185 cell-index = <0>;
185 device_type = "serial"; 186 device_type = "serial";
186 compatible = "ns16550"; 187 compatible = "ns16550";
187 reg = <4500 100>; // reg base, size 188 reg = <0x4500 0x100>; // reg base, size
188 clock-frequency = <0>; // should we fill in in uboot? 189 clock-frequency = <0>; // should we fill in in uboot?
189 interrupts = <2a 2>; 190 interrupts = <42 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 }; 192 };
192 193
@@ -194,15 +195,15 @@
194 cell-index = <1>; 195 cell-index = <1>;
195 device_type = "serial"; 196 device_type = "serial";
196 compatible = "ns16550"; 197 compatible = "ns16550";
197 reg = <4600 100>; // reg base, size 198 reg = <0x4600 0x100>; // reg base, size
198 clock-frequency = <0>; // should we fill in in uboot? 199 clock-frequency = <0>; // should we fill in in uboot?
199 interrupts = <2a 2>; 200 interrupts = <42 2>;
200 interrupt-parent = <&mpic>; 201 interrupt-parent = <&mpic>;
201 }; 202 };
202 203
203 global-utilities@e0000 { //global utilities reg 204 global-utilities@e0000 { //global utilities reg
204 compatible = "fsl,mpc8548-guts"; 205 compatible = "fsl,mpc8548-guts";
205 reg = <e0000 1000>; 206 reg = <0xe0000 0x1000>;
206 fsl,has-rstcr; 207 fsl,has-rstcr;
207 }; 208 };
208 209
@@ -211,7 +212,7 @@
211 interrupt-controller; 212 interrupt-controller;
212 #address-cells = <0>; 213 #address-cells = <0>;
213 #interrupt-cells = <2>; 214 #interrupt-cells = <2>;
214 reg = <40000 40000>; 215 reg = <0x40000 0x40000>;
215 compatible = "chrp,open-pic"; 216 compatible = "chrp,open-pic";
216 device_type = "open-pic"; 217 device_type = "open-pic";
217 big-endian; 218 big-endian;
@@ -220,139 +221,139 @@
220 221
221 pci0: pci@e0008000 { 222 pci0: pci@e0008000 {
222 cell-index = <0>; 223 cell-index = <0>;
223 interrupt-map-mask = <f800 0 0 7>; 224 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
224 interrupt-map = < 225 interrupt-map = <
225 /* IDSEL 0x4 (PCIX Slot 2) */ 226 /* IDSEL 0x4 (PCIX Slot 2) */
226 02000 0 0 1 &mpic 0 1 227 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
227 02000 0 0 2 &mpic 1 1 228 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
228 02000 0 0 3 &mpic 2 1 229 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
229 02000 0 0 4 &mpic 3 1 230 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
230 231
231 /* IDSEL 0x5 (PCIX Slot 3) */ 232 /* IDSEL 0x5 (PCIX Slot 3) */
232 02800 0 0 1 &mpic 1 1 233 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
233 02800 0 0 2 &mpic 2 1 234 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
234 02800 0 0 3 &mpic 3 1 235 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
235 02800 0 0 4 &mpic 0 1 236 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
236 237
237 /* IDSEL 0x6 (PCIX Slot 4) */ 238 /* IDSEL 0x6 (PCIX Slot 4) */
238 03000 0 0 1 &mpic 2 1 239 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
239 03000 0 0 2 &mpic 3 1 240 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
240 03000 0 0 3 &mpic 0 1 241 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
241 03000 0 0 4 &mpic 1 1 242 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
242 243
243 /* IDSEL 0x8 (PCIX Slot 5) */ 244 /* IDSEL 0x8 (PCIX Slot 5) */
244 04000 0 0 1 &mpic 0 1 245 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
245 04000 0 0 2 &mpic 1 1 246 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
246 04000 0 0 3 &mpic 2 1 247 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
247 04000 0 0 4 &mpic 3 1 248 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
248 249
249 /* IDSEL 0xC (Tsi310 bridge) */ 250 /* IDSEL 0xC (Tsi310 bridge) */
250 06000 0 0 1 &mpic 0 1 251 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
251 06000 0 0 2 &mpic 1 1 252 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
252 06000 0 0 3 &mpic 2 1 253 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
253 06000 0 0 4 &mpic 3 1 254 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
254 255
255 /* IDSEL 0x14 (Slot 2) */ 256 /* IDSEL 0x14 (Slot 2) */
256 0a000 0 0 1 &mpic 0 1 257 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
257 0a000 0 0 2 &mpic 1 1 258 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
258 0a000 0 0 3 &mpic 2 1 259 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
259 0a000 0 0 4 &mpic 3 1 260 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
260 261
261 /* IDSEL 0x15 (Slot 3) */ 262 /* IDSEL 0x15 (Slot 3) */
262 0a800 0 0 1 &mpic 1 1 263 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
263 0a800 0 0 2 &mpic 2 1 264 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
264 0a800 0 0 3 &mpic 3 1 265 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
265 0a800 0 0 4 &mpic 0 1 266 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
266 267
267 /* IDSEL 0x16 (Slot 4) */ 268 /* IDSEL 0x16 (Slot 4) */
268 0b000 0 0 1 &mpic 2 1 269 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
269 0b000 0 0 2 &mpic 3 1 270 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
270 0b000 0 0 3 &mpic 0 1 271 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
271 0b000 0 0 4 &mpic 1 1 272 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
272 273
273 /* IDSEL 0x18 (Slot 5) */ 274 /* IDSEL 0x18 (Slot 5) */
274 0c000 0 0 1 &mpic 0 1 275 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
275 0c000 0 0 2 &mpic 1 1 276 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
276 0c000 0 0 3 &mpic 2 1 277 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
277 0c000 0 0 4 &mpic 3 1 278 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
278 279
279 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 280 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
280 0E000 0 0 1 &mpic 0 1 281 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
281 0E000 0 0 2 &mpic 1 1 282 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
282 0E000 0 0 3 &mpic 2 1 283 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
283 0E000 0 0 4 &mpic 3 1>; 284 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
284 285
285 interrupt-parent = <&mpic>; 286 interrupt-parent = <&mpic>;
286 interrupts = <18 2>; 287 interrupts = <24 2>;
287 bus-range = <0 0>; 288 bus-range = <0 0>;
288 ranges = <02000000 0 80000000 80000000 0 10000000 289 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
289 01000000 0 00000000 e2000000 0 00800000>; 290 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
290 clock-frequency = <3f940aa>; 291 clock-frequency = <66666666>;
291 #interrupt-cells = <1>; 292 #interrupt-cells = <1>;
292 #size-cells = <2>; 293 #size-cells = <2>;
293 #address-cells = <3>; 294 #address-cells = <3>;
294 reg = <e0008000 1000>; 295 reg = <0xe0008000 0x1000>;
295 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 296 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
296 device_type = "pci"; 297 device_type = "pci";
297 298
298 pci_bridge@1c { 299 pci_bridge@1c {
299 interrupt-map-mask = <f800 0 0 7>; 300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
300 interrupt-map = < 301 interrupt-map = <
301 302
302 /* IDSEL 0x00 (PrPMC Site) */ 303 /* IDSEL 0x00 (PrPMC Site) */
303 0000 0 0 1 &mpic 0 1 304 0000 0x0 0x0 0x1 &mpic 0x0 0x1
304 0000 0 0 2 &mpic 1 1 305 0000 0x0 0x0 0x2 &mpic 0x1 0x1
305 0000 0 0 3 &mpic 2 1 306 0000 0x0 0x0 0x3 &mpic 0x2 0x1
306 0000 0 0 4 &mpic 3 1 307 0000 0x0 0x0 0x4 &mpic 0x3 0x1
307 308
308 /* IDSEL 0x04 (VIA chip) */ 309 /* IDSEL 0x04 (VIA chip) */
309 2000 0 0 1 &mpic 0 1 310 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
310 2000 0 0 2 &mpic 1 1 311 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
311 2000 0 0 3 &mpic 2 1 312 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
312 2000 0 0 4 &mpic 3 1 313 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
313 314
314 /* IDSEL 0x05 (8139) */ 315 /* IDSEL 0x05 (8139) */
315 2800 0 0 1 &mpic 1 1 316 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
316 317
317 /* IDSEL 0x06 (Slot 6) */ 318 /* IDSEL 0x06 (Slot 6) */
318 3000 0 0 1 &mpic 2 1 319 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
319 3000 0 0 2 &mpic 3 1 320 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
320 3000 0 0 3 &mpic 0 1 321 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
321 3000 0 0 4 &mpic 1 1 322 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
322 323
323 /* IDESL 0x07 (Slot 7) */ 324 /* IDESL 0x07 (Slot 7) */
324 3800 0 0 1 &mpic 3 1 325 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
325 3800 0 0 2 &mpic 0 1 326 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
326 3800 0 0 3 &mpic 1 1 327 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
327 3800 0 0 4 &mpic 2 1>; 328 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
328 329
329 reg = <e000 0 0 0 0>; 330 reg = <0xe000 0x0 0x0 0x0 0x0>;
330 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
331 #size-cells = <2>; 332 #size-cells = <2>;
332 #address-cells = <3>; 333 #address-cells = <3>;
333 ranges = <02000000 0 80000000 334 ranges = <0x2000000 0x0 0x80000000
334 02000000 0 80000000 335 0x2000000 0x0 0x80000000
335 0 20000000 336 0x0 0x20000000
336 01000000 0 00000000 337 0x1000000 0x0 0x0
337 01000000 0 00000000 338 0x1000000 0x0 0x0
338 0 00080000>; 339 0x0 0x80000>;
339 clock-frequency = <1fca055>; 340 clock-frequency = <33333333>;
340 341
341 isa@4 { 342 isa@4 {
342 device_type = "isa"; 343 device_type = "isa";
343 #interrupt-cells = <2>; 344 #interrupt-cells = <2>;
344 #size-cells = <1>; 345 #size-cells = <1>;
345 #address-cells = <2>; 346 #address-cells = <2>;
346 reg = <2000 0 0 0 0>; 347 reg = <0x2000 0x0 0x0 0x0 0x0>;
347 ranges = <1 0 01000000 0 0 00001000>; 348 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
348 interrupt-parent = <&i8259>; 349 interrupt-parent = <&i8259>;
349 350
350 i8259: interrupt-controller@20 { 351 i8259: interrupt-controller@20 {
351 interrupt-controller; 352 interrupt-controller;
352 device_type = "interrupt-controller"; 353 device_type = "interrupt-controller";
353 reg = <1 20 2 354 reg = <0x1 0x20 0x2
354 1 a0 2 355 0x1 0xa0 0x2
355 1 4d0 2>; 356 0x1 0x4d0 0x2>;
356 #address-cells = <0>; 357 #address-cells = <0>;
357 #interrupt-cells = <2>; 358 #interrupt-cells = <2>;
358 compatible = "chrp,iic"; 359 compatible = "chrp,iic";
@@ -362,7 +363,7 @@
362 363
363 rtc@70 { 364 rtc@70 {
364 compatible = "pnpPNP,b00"; 365 compatible = "pnpPNP,b00";
365 reg = <1 70 2>; 366 reg = <0x1 0x70 0x2>;
366 }; 367 };
367 }; 368 };
368 }; 369 };
@@ -370,64 +371,64 @@
370 371
371 pci1: pci@e0009000 { 372 pci1: pci@e0009000 {
372 cell-index = <1>; 373 cell-index = <1>;
373 interrupt-map-mask = <f800 0 0 7>; 374 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
374 interrupt-map = < 375 interrupt-map = <
375 376
376 /* IDSEL 0x15 */ 377 /* IDSEL 0x15 */
377 a800 0 0 1 &mpic b 1 378 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
378 a800 0 0 2 &mpic 1 1 379 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
379 a800 0 0 3 &mpic 2 1 380 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
380 a800 0 0 4 &mpic 3 1>; 381 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
381 382
382 interrupt-parent = <&mpic>; 383 interrupt-parent = <&mpic>;
383 interrupts = <19 2>; 384 interrupts = <25 2>;
384 bus-range = <0 0>; 385 bus-range = <0 0>;
385 ranges = <02000000 0 90000000 90000000 0 10000000 386 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
386 01000000 0 00000000 e2800000 0 00800000>; 387 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
387 clock-frequency = <3f940aa>; 388 clock-frequency = <66666666>;
388 #interrupt-cells = <1>; 389 #interrupt-cells = <1>;
389 #size-cells = <2>; 390 #size-cells = <2>;
390 #address-cells = <3>; 391 #address-cells = <3>;
391 reg = <e0009000 1000>; 392 reg = <0xe0009000 0x1000>;
392 compatible = "fsl,mpc8540-pci"; 393 compatible = "fsl,mpc8540-pci";
393 device_type = "pci"; 394 device_type = "pci";
394 }; 395 };
395 396
396 pci2: pcie@e000a000 { 397 pci2: pcie@e000a000 {
397 cell-index = <2>; 398 cell-index = <2>;
398 interrupt-map-mask = <f800 0 0 7>; 399 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = < 400 interrupt-map = <
400 401
401 /* IDSEL 0x0 (PEX) */ 402 /* IDSEL 0x0 (PEX) */
402 00000 0 0 1 &mpic 0 1 403 00000 0x0 0x0 0x1 &mpic 0x0 0x1
403 00000 0 0 2 &mpic 1 1 404 00000 0x0 0x0 0x2 &mpic 0x1 0x1
404 00000 0 0 3 &mpic 2 1 405 00000 0x0 0x0 0x3 &mpic 0x2 0x1
405 00000 0 0 4 &mpic 3 1>; 406 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
406 407
407 interrupt-parent = <&mpic>; 408 interrupt-parent = <&mpic>;
408 interrupts = <1a 2>; 409 interrupts = <26 2>;
409 bus-range = <0 ff>; 410 bus-range = <0 255>;
410 ranges = <02000000 0 a0000000 a0000000 0 20000000 411 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
411 01000000 0 00000000 e3000000 0 08000000>; 412 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
412 clock-frequency = <1fca055>; 413 clock-frequency = <33333333>;
413 #interrupt-cells = <1>; 414 #interrupt-cells = <1>;
414 #size-cells = <2>; 415 #size-cells = <2>;
415 #address-cells = <3>; 416 #address-cells = <3>;
416 reg = <e000a000 1000>; 417 reg = <0xe000a000 0x1000>;
417 compatible = "fsl,mpc8548-pcie"; 418 compatible = "fsl,mpc8548-pcie";
418 device_type = "pci"; 419 device_type = "pci";
419 pcie@0 { 420 pcie@0 {
420 reg = <0 0 0 0 0>; 421 reg = <0x0 0x0 0x0 0x0 0x0>;
421 #size-cells = <2>; 422 #size-cells = <2>;
422 #address-cells = <3>; 423 #address-cells = <3>;
423 device_type = "pci"; 424 device_type = "pci";
424 ranges = <02000000 0 a0000000 425 ranges = <0x2000000 0x0 0xa0000000
425 02000000 0 a0000000 426 0x2000000 0x0 0xa0000000
426 0 20000000 427 0x0 0x20000000
427 428
428 01000000 0 00000000 429 0x1000000 0x0 0x0
429 01000000 0 00000000 430 0x1000000 0x0 0x0
430 0 08000000>; 431 0x0 0x8000000>;
431 }; 432 };
432 }; 433 };
433}; 434};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 4538f3c38862..b025c566c10d 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8555 CDS Device Tree Source 2 * MPC8555 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8555CDS"; 15 model = "MPC8555CDS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8555@0 { 33 PowerPC,8555@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8555@e0000000 { 51 soc8555@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00001000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8555-memory-controller"; 60 compatible = "fsl,8555-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8555-l2-cache-controller"; 67 compatible = "fsl,8555-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,18 +87,18 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 }; 104 };
@@ -107,9 +108,9 @@
107 device_type = "network"; 108 device_type = "network";
108 model = "TSEC"; 109 model = "TSEC";
109 compatible = "gianfar"; 110 compatible = "gianfar";
110 reg = <24000 1000>; 111 reg = <0x24000 0x1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>; 113 interrupts = <29 2 30 2 34 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>; 115 phy-handle = <&phy0>;
115 }; 116 };
@@ -119,9 +120,9 @@
119 device_type = "network"; 120 device_type = "network";
120 model = "TSEC"; 121 model = "TSEC";
121 compatible = "gianfar"; 122 compatible = "gianfar";
122 reg = <25000 1000>; 123 reg = <0x25000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 124 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <23 2 24 2 28 2>; 125 interrupts = <35 2 36 2 40 2>;
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 phy-handle = <&phy1>; 127 phy-handle = <&phy1>;
127 }; 128 };
@@ -130,9 +131,9 @@
130 cell-index = <0>; 131 cell-index = <0>;
131 device_type = "serial"; 132 device_type = "serial";
132 compatible = "ns16550"; 133 compatible = "ns16550";
133 reg = <4500 100>; // reg base, size 134 reg = <0x4500 0x100>; // reg base, size
134 clock-frequency = <0>; // should we fill in in uboot? 135 clock-frequency = <0>; // should we fill in in uboot?
135 interrupts = <2a 2>; 136 interrupts = <42 2>;
136 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
137 }; 138 };
138 139
@@ -140,9 +141,9 @@
140 cell-index = <1>; 141 cell-index = <1>;
141 device_type = "serial"; 142 device_type = "serial";
142 compatible = "ns16550"; 143 compatible = "ns16550";
143 reg = <4600 100>; // reg base, size 144 reg = <0x4600 0x100>; // reg base, size
144 clock-frequency = <0>; // should we fill in in uboot? 145 clock-frequency = <0>; // should we fill in in uboot?
145 interrupts = <2a 2>; 146 interrupts = <42 2>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 }; 148 };
148 149
@@ -151,7 +152,7 @@
151 interrupt-controller; 152 interrupt-controller;
152 #address-cells = <0>; 153 #address-cells = <0>;
153 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
154 reg = <40000 40000>; 155 reg = <0x40000 0x40000>;
155 compatible = "chrp,open-pic"; 156 compatible = "chrp,open-pic";
156 device_type = "open-pic"; 157 device_type = "open-pic";
157 big-endian; 158 big-endian;
@@ -161,17 +162,17 @@
161 #address-cells = <1>; 162 #address-cells = <1>;
162 #size-cells = <1>; 163 #size-cells = <1>;
163 compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; 164 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
164 reg = <919c0 30>; 165 reg = <0x919c0 0x30>;
165 ranges; 166 ranges;
166 167
167 muram@80000 { 168 muram@80000 {
168 #address-cells = <1>; 169 #address-cells = <1>;
169 #size-cells = <1>; 170 #size-cells = <1>;
170 ranges = <0 80000 10000>; 171 ranges = <0x0 0x80000 0x10000>;
171 172
172 data@0 { 173 data@0 {
173 compatible = "fsl,cpm-muram-data"; 174 compatible = "fsl,cpm-muram-data";
174 reg = <0 2000 9000 1000>; 175 reg = <0x0 0x2000 0x9000 0x1000>;
175 }; 176 };
176 }; 177 };
177 178
@@ -179,16 +180,16 @@
179 compatible = "fsl,mpc8555-brg", 180 compatible = "fsl,mpc8555-brg",
180 "fsl,cpm2-brg", 181 "fsl,cpm2-brg",
181 "fsl,cpm-brg"; 182 "fsl,cpm-brg";
182 reg = <919f0 10 915f0 10>; 183 reg = <0x919f0 0x10 0x915f0 0x10>;
183 }; 184 };
184 185
185 cpmpic: pic@90c00 { 186 cpmpic: pic@90c00 {
186 interrupt-controller; 187 interrupt-controller;
187 #address-cells = <0>; 188 #address-cells = <0>;
188 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
189 interrupts = <2e 2>; 190 interrupts = <46 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 reg = <90c00 80>; 192 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; 193 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
193 }; 194 };
194 }; 195 };
@@ -196,68 +197,68 @@
196 197
197 pci0: pci@e0008000 { 198 pci0: pci@e0008000 {
198 cell-index = <0>; 199 cell-index = <0>;
199 interrupt-map-mask = <1f800 0 0 7>; 200 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
200 interrupt-map = < 201 interrupt-map = <
201 202
202 /* IDSEL 0x10 */ 203 /* IDSEL 0x10 */
203 08000 0 0 1 &mpic 0 1 204 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 08000 0 0 2 &mpic 1 1 205 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 08000 0 0 3 &mpic 2 1 206 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 08000 0 0 4 &mpic 3 1 207 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
207 208
208 /* IDSEL 0x11 */ 209 /* IDSEL 0x11 */
209 08800 0 0 1 &mpic 0 1 210 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 08800 0 0 2 &mpic 1 1 211 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 08800 0 0 3 &mpic 2 1 212 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 08800 0 0 4 &mpic 3 1 213 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
213 214
214 /* IDSEL 0x12 (Slot 1) */ 215 /* IDSEL 0x12 (Slot 1) */
215 09000 0 0 1 &mpic 0 1 216 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 09000 0 0 2 &mpic 1 1 217 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 09000 0 0 3 &mpic 2 1 218 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 09000 0 0 4 &mpic 3 1 219 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
219 220
220 /* IDSEL 0x13 (Slot 2) */ 221 /* IDSEL 0x13 (Slot 2) */
221 09800 0 0 1 &mpic 1 1 222 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 09800 0 0 2 &mpic 2 1 223 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 09800 0 0 3 &mpic 3 1 224 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 09800 0 0 4 &mpic 0 1 225 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
225 226
226 /* IDSEL 0x14 (Slot 3) */ 227 /* IDSEL 0x14 (Slot 3) */
227 0a000 0 0 1 &mpic 2 1 228 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0a000 0 0 2 &mpic 3 1 229 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0a000 0 0 3 &mpic 0 1 230 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0a000 0 0 4 &mpic 1 1 231 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
231 232
232 /* IDSEL 0x15 (Slot 4) */ 233 /* IDSEL 0x15 (Slot 4) */
233 0a800 0 0 1 &mpic 3 1 234 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0a800 0 0 2 &mpic 0 1 235 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0a800 0 0 3 &mpic 1 1 236 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0a800 0 0 4 &mpic 2 1 237 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
237 238
238 /* Bus 1 (Tundra Bridge) */ 239 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */ 240 /* IDSEL 0x12 (ISA bridge) */
240 19000 0 0 1 &mpic 0 1 241 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 19000 0 0 2 &mpic 1 1 242 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 19000 0 0 3 &mpic 2 1 243 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 19000 0 0 4 &mpic 3 1>; 244 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 0>; 247 bus-range = <0 0>;
247 ranges = <02000000 0 80000000 80000000 0 20000000 248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 01000000 0 00000000 e2000000 0 00100000>; 249 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci"; 255 compatible = "fsl,mpc8540-pci";
255 device_type = "pci"; 256 device_type = "pci";
256 257
257 i8259@19000 { 258 i8259@19000 {
258 interrupt-controller; 259 interrupt-controller;
259 device_type = "interrupt-controller"; 260 device_type = "interrupt-controller";
260 reg = <19000 0 0 0 1>; 261 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>; 262 #address-cells = <0>;
262 #interrupt-cells = <2>; 263 #interrupt-cells = <2>;
263 compatible = "chrp,iic"; 264 compatible = "chrp,iic";
@@ -268,24 +269,24 @@
268 269
269 pci1: pci@e0009000 { 270 pci1: pci@e0009000 {
270 cell-index = <1>; 271 cell-index = <1>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
272 interrupt-map = < 273 interrupt-map = <
273 274
274 /* IDSEL 0x15 */ 275 /* IDSEL 0x15 */
275 a800 0 0 1 &mpic b 1 276 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 a800 0 0 2 &mpic b 1 277 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 a800 0 0 3 &mpic b 1 278 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 a800 0 0 4 &mpic b 1>; 279 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>; 280 interrupt-parent = <&mpic>;
280 interrupts = <19 2>; 281 interrupts = <25 2>;
281 bus-range = <0 0>; 282 bus-range = <0 0>;
282 ranges = <02000000 0 a0000000 a0000000 0 20000000 283 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 01000000 0 00000000 e3000000 0 00100000>; 284 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <3f940aa>; 285 clock-frequency = <66666666>;
285 #interrupt-cells = <1>; 286 #interrupt-cells = <1>;
286 #size-cells = <2>; 287 #size-cells = <2>;
287 #address-cells = <3>; 288 #address-cells = <3>;
288 reg = <e0009000 1000>; 289 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci"; 290 compatible = "fsl,mpc8540-pci";
290 device_type = "pci"; 291 device_type = "pci";
291 }; 292 };
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 639ce8a709a6..0cc16ab305d1 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8560 ADS Device Tree Source 2 * MPC8560 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8560ADS"; 15 model = "MPC8560ADS";
@@ -32,74 +33,74 @@
32 33
33 PowerPC,8560@0 { 34 PowerPC,8560@0 {
34 device_type = "cpu"; 35 device_type = "cpu";
35 reg = <0>; 36 reg = <0x0>;
36 d-cache-line-size = <20>; // 32 bytes 37 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <20>; // 32 bytes 38 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <8000>; // L1, 32K 39 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <8000>; // L1, 32K 40 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <04ead9a0>; 41 timebase-frequency = <82500000>;
41 bus-frequency = <13ab6680>; 42 bus-frequency = <330000000>;
42 clock-frequency = <312c8040>; 43 clock-frequency = <825000000>;
43 }; 44 };
44 }; 45 };
45 46
46 memory { 47 memory {
47 device_type = "memory"; 48 device_type = "memory";
48 reg = <00000000 10000000>; 49 reg = <0x0 0x10000000>;
49 }; 50 };
50 51
51 soc8560@e0000000 { 52 soc8560@e0000000 {
52 #address-cells = <1>; 53 #address-cells = <1>;
53 #size-cells = <1>; 54 #size-cells = <1>;
54 device_type = "soc"; 55 device_type = "soc";
55 ranges = <0 e0000000 00100000>; 56 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <e0000000 00000200>; 57 reg = <0xe0000000 0x200>;
57 bus-frequency = <13ab6680>; 58 bus-frequency = <330000000>;
58 59
59 memory-controller@2000 { 60 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,8540-memory-controller";
61 reg = <2000 1000>; 62 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
63 interrupts = <12 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <20000 1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <20>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
70 cache-size = <40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
71 interrupt-parent = <&mpic>; 72 interrupt-parent = <&mpic>;
72 interrupts = <10 2>; 73 interrupts = <16 2>;
73 }; 74 };
74 75
75 mdio@24520 { 76 mdio@24520 {
76 #address-cells = <1>; 77 #address-cells = <1>;
77 #size-cells = <0>; 78 #size-cells = <0>;
78 compatible = "fsl,gianfar-mdio"; 79 compatible = "fsl,gianfar-mdio";
79 reg = <24520 20>; 80 reg = <0x24520 0x20>;
80 81
81 phy0: ethernet-phy@0 { 82 phy0: ethernet-phy@0 {
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 interrupts = <5 1>; 84 interrupts = <5 1>;
84 reg = <0>; 85 reg = <0x0>;
85 device_type = "ethernet-phy"; 86 device_type = "ethernet-phy";
86 }; 87 };
87 phy1: ethernet-phy@1 { 88 phy1: ethernet-phy@1 {
88 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
89 interrupts = <5 1>; 90 interrupts = <5 1>;
90 reg = <1>; 91 reg = <0x1>;
91 device_type = "ethernet-phy"; 92 device_type = "ethernet-phy";
92 }; 93 };
93 phy2: ethernet-phy@2 { 94 phy2: ethernet-phy@2 {
94 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>;
95 interrupts = <7 1>; 96 interrupts = <7 1>;
96 reg = <2>; 97 reg = <0x2>;
97 device_type = "ethernet-phy"; 98 device_type = "ethernet-phy";
98 }; 99 };
99 phy3: ethernet-phy@3 { 100 phy3: ethernet-phy@3 {
100 interrupt-parent = <&mpic>; 101 interrupt-parent = <&mpic>;
101 interrupts = <7 1>; 102 interrupts = <7 1>;
102 reg = <3>; 103 reg = <0x3>;
103 device_type = "ethernet-phy"; 104 device_type = "ethernet-phy";
104 }; 105 };
105 }; 106 };
@@ -109,9 +110,9 @@
109 device_type = "network"; 110 device_type = "network";
110 model = "TSEC"; 111 model = "TSEC";
111 compatible = "gianfar"; 112 compatible = "gianfar";
112 reg = <24000 1000>; 113 reg = <0x24000 0x1000>;
113 local-mac-address = [ 00 00 00 00 00 00 ]; 114 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <1d 2 1e 2 22 2>; 115 interrupts = <29 2 30 2 34 2>;
115 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
116 phy-handle = <&phy0>; 117 phy-handle = <&phy0>;
117 }; 118 };
@@ -121,9 +122,9 @@
121 device_type = "network"; 122 device_type = "network";
122 model = "TSEC"; 123 model = "TSEC";
123 compatible = "gianfar"; 124 compatible = "gianfar";
124 reg = <25000 1000>; 125 reg = <0x25000 0x1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ]; 126 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <23 2 24 2 28 2>; 127 interrupts = <35 2 36 2 40 2>;
127 interrupt-parent = <&mpic>; 128 interrupt-parent = <&mpic>;
128 phy-handle = <&phy1>; 129 phy-handle = <&phy1>;
129 }; 130 };
@@ -132,7 +133,7 @@
132 interrupt-controller; 133 interrupt-controller;
133 #address-cells = <0>; 134 #address-cells = <0>;
134 #interrupt-cells = <2>; 135 #interrupt-cells = <2>;
135 reg = <40000 40000>; 136 reg = <0x40000 0x40000>;
136 device_type = "open-pic"; 137 device_type = "open-pic";
137 }; 138 };
138 139
@@ -140,17 +141,17 @@
140 #address-cells = <1>; 141 #address-cells = <1>;
141 #size-cells = <1>; 142 #size-cells = <1>;
142 compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; 143 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
143 reg = <919c0 30>; 144 reg = <0x919c0 0x30>;
144 ranges; 145 ranges;
145 146
146 muram@80000 { 147 muram@80000 {
147 #address-cells = <1>; 148 #address-cells = <1>;
148 #size-cells = <1>; 149 #size-cells = <1>;
149 ranges = <0 80000 10000>; 150 ranges = <0x0 0x80000 0x10000>;
150 151
151 data@0 { 152 data@0 {
152 compatible = "fsl,cpm-muram-data"; 153 compatible = "fsl,cpm-muram-data";
153 reg = <0 4000 9000 2000>; 154 reg = <0x0 0x4000 0x9000 0x2000>;
154 }; 155 };
155 }; 156 };
156 157
@@ -158,17 +159,17 @@
158 compatible = "fsl,mpc8560-brg", 159 compatible = "fsl,mpc8560-brg",
159 "fsl,cpm2-brg", 160 "fsl,cpm2-brg",
160 "fsl,cpm-brg"; 161 "fsl,cpm-brg";
161 reg = <919f0 10 915f0 10>; 162 reg = <0x919f0 0x10 0x915f0 0x10>;
162 clock-frequency = <d#165000000>; 163 clock-frequency = <165000000>;
163 }; 164 };
164 165
165 cpmpic: pic@90c00 { 166 cpmpic: pic@90c00 {
166 interrupt-controller; 167 interrupt-controller;
167 #address-cells = <0>; 168 #address-cells = <0>;
168 #interrupt-cells = <2>; 169 #interrupt-cells = <2>;
169 interrupts = <2e 2>; 170 interrupts = <46 2>;
170 interrupt-parent = <&mpic>; 171 interrupt-parent = <&mpic>;
171 reg = <90c00 80>; 172 reg = <0x90c00 0x80>;
172 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 173 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
173 }; 174 };
174 175
@@ -176,11 +177,11 @@
176 device_type = "serial"; 177 device_type = "serial";
177 compatible = "fsl,mpc8560-scc-uart", 178 compatible = "fsl,mpc8560-scc-uart",
178 "fsl,cpm2-scc-uart"; 179 "fsl,cpm2-scc-uart";
179 reg = <91a00 20 88000 100>; 180 reg = <0x91a00 0x20 0x88000 0x100>;
180 fsl,cpm-brg = <1>; 181 fsl,cpm-brg = <1>;
181 fsl,cpm-command = <00800000>; 182 fsl,cpm-command = <0x800000>;
182 current-speed = <1c200>; 183 current-speed = <115200>;
183 interrupts = <28 8>; 184 interrupts = <40 8>;
184 interrupt-parent = <&cpmpic>; 185 interrupt-parent = <&cpmpic>;
185 }; 186 };
186 187
@@ -188,11 +189,11 @@
188 device_type = "serial"; 189 device_type = "serial";
189 compatible = "fsl,mpc8560-scc-uart", 190 compatible = "fsl,mpc8560-scc-uart",
190 "fsl,cpm2-scc-uart"; 191 "fsl,cpm2-scc-uart";
191 reg = <91a20 20 88100 100>; 192 reg = <0x91a20 0x20 0x88100 0x100>;
192 fsl,cpm-brg = <2>; 193 fsl,cpm-brg = <2>;
193 fsl,cpm-command = <04a00000>; 194 fsl,cpm-command = <0x4a00000>;
194 current-speed = <1c200>; 195 current-speed = <115200>;
195 interrupts = <29 8>; 196 interrupts = <41 8>;
196 interrupt-parent = <&cpmpic>; 197 interrupt-parent = <&cpmpic>;
197 }; 198 };
198 199
@@ -200,10 +201,10 @@
200 device_type = "network"; 201 device_type = "network";
201 compatible = "fsl,mpc8560-fcc-enet", 202 compatible = "fsl,mpc8560-fcc-enet",
202 "fsl,cpm2-fcc-enet"; 203 "fsl,cpm2-fcc-enet";
203 reg = <91320 20 88500 100 913b0 1>; 204 reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
204 local-mac-address = [ 00 00 00 00 00 00 ]; 205 local-mac-address = [ 00 00 00 00 00 00 ];
205 fsl,cpm-command = <16200300>; 206 fsl,cpm-command = <0x16200300>;
206 interrupts = <21 8>; 207 interrupts = <33 8>;
207 interrupt-parent = <&cpmpic>; 208 interrupt-parent = <&cpmpic>;
208 phy-handle = <&phy2>; 209 phy-handle = <&phy2>;
209 }; 210 };
@@ -212,10 +213,10 @@
212 device_type = "network"; 213 device_type = "network";
213 compatible = "fsl,mpc8560-fcc-enet", 214 compatible = "fsl,mpc8560-fcc-enet",
214 "fsl,cpm2-fcc-enet"; 215 "fsl,cpm2-fcc-enet";
215 reg = <91340 20 88600 100 913d0 1>; 216 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
216 local-mac-address = [ 00 00 00 00 00 00 ]; 217 local-mac-address = [ 00 00 00 00 00 00 ];
217 fsl,cpm-command = <1a400300>; 218 fsl,cpm-command = <0x1a400300>;
218 interrupts = <22 8>; 219 interrupts = <34 8>;
219 interrupt-parent = <&cpmpic>; 220 interrupt-parent = <&cpmpic>;
220 phy-handle = <&phy3>; 221 phy-handle = <&phy3>;
221 }; 222 };
@@ -229,87 +230,87 @@
229 #address-cells = <3>; 230 #address-cells = <3>;
230 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 231 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
231 device_type = "pci"; 232 device_type = "pci";
232 reg = <e0008000 1000>; 233 reg = <0xe0008000 0x1000>;
233 clock-frequency = <3f940aa>; 234 clock-frequency = <66666666>;
234 interrupt-map-mask = <f800 0 0 7>; 235 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
235 interrupt-map = < 236 interrupt-map = <
236 237
237 /* IDSEL 0x2 */ 238 /* IDSEL 0x2 */
238 1000 0 0 1 &mpic 1 1 239 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
239 1000 0 0 2 &mpic 2 1 240 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
240 1000 0 0 3 &mpic 3 1 241 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
241 1000 0 0 4 &mpic 4 1 242 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
242 243
243 /* IDSEL 0x3 */ 244 /* IDSEL 0x3 */
244 1800 0 0 1 &mpic 4 1 245 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
245 1800 0 0 2 &mpic 1 1 246 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
246 1800 0 0 3 &mpic 2 1 247 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
247 1800 0 0 4 &mpic 3 1 248 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
248 249
249 /* IDSEL 0x4 */ 250 /* IDSEL 0x4 */
250 2000 0 0 1 &mpic 3 1 251 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
251 2000 0 0 2 &mpic 4 1 252 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
252 2000 0 0 3 &mpic 1 1 253 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
253 2000 0 0 4 &mpic 2 1 254 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
254 255
255 /* IDSEL 0x5 */ 256 /* IDSEL 0x5 */
256 2800 0 0 1 &mpic 2 1 257 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
257 2800 0 0 2 &mpic 3 1 258 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
258 2800 0 0 3 &mpic 4 1 259 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
259 2800 0 0 4 &mpic 1 1 260 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
260 261
261 /* IDSEL 12 */ 262 /* IDSEL 12 */
262 6000 0 0 1 &mpic 1 1 263 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
263 6000 0 0 2 &mpic 2 1 264 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
264 6000 0 0 3 &mpic 3 1 265 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
265 6000 0 0 4 &mpic 4 1 266 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
266 267
267 /* IDSEL 13 */ 268 /* IDSEL 13 */
268 6800 0 0 1 &mpic 4 1 269 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
269 6800 0 0 2 &mpic 1 1 270 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
270 6800 0 0 3 &mpic 2 1 271 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
271 6800 0 0 4 &mpic 3 1 272 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
272 273
273 /* IDSEL 14*/ 274 /* IDSEL 14*/
274 7000 0 0 1 &mpic 3 1 275 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
275 7000 0 0 2 &mpic 4 1 276 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
276 7000 0 0 3 &mpic 1 1 277 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
277 7000 0 0 4 &mpic 2 1 278 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
278 279
279 /* IDSEL 15 */ 280 /* IDSEL 15 */
280 7800 0 0 1 &mpic 2 1 281 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
281 7800 0 0 2 &mpic 3 1 282 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
282 7800 0 0 3 &mpic 4 1 283 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
283 7800 0 0 4 &mpic 1 1 284 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
284 285
285 /* IDSEL 18 */ 286 /* IDSEL 18 */
286 9000 0 0 1 &mpic 1 1 287 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
287 9000 0 0 2 &mpic 2 1 288 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
288 9000 0 0 3 &mpic 3 1 289 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
289 9000 0 0 4 &mpic 4 1 290 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
290 291
291 /* IDSEL 19 */ 292 /* IDSEL 19 */
292 9800 0 0 1 &mpic 4 1 293 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
293 9800 0 0 2 &mpic 1 1 294 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
294 9800 0 0 3 &mpic 2 1 295 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
295 9800 0 0 4 &mpic 3 1 296 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
296 297
297 /* IDSEL 20 */ 298 /* IDSEL 20 */
298 a000 0 0 1 &mpic 3 1 299 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
299 a000 0 0 2 &mpic 4 1 300 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
300 a000 0 0 3 &mpic 1 1 301 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
301 a000 0 0 4 &mpic 2 1 302 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
302 303
303 /* IDSEL 21 */ 304 /* IDSEL 21 */
304 a800 0 0 1 &mpic 2 1 305 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
305 a800 0 0 2 &mpic 3 1 306 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
306 a800 0 0 3 &mpic 4 1 307 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
307 a800 0 0 4 &mpic 1 1>; 308 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
308 309
309 interrupt-parent = <&mpic>; 310 interrupt-parent = <&mpic>;
310 interrupts = <18 2>; 311 interrupts = <24 2>;
311 bus-range = <0 0>; 312 bus-range = <0 0>;
312 ranges = <02000000 0 80000000 80000000 0 20000000 313 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
313 01000000 0 00000000 e2000000 0 01000000>; 314 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
314 }; 315 };
315}; 316};
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 97bc048f2158..a025a8ededc5 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8568E MDS Device Tree Source 2 * MPC8568E MDS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,10 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12 12/dts-v1/;
13/*
14/memreserve/ 00000000 1000000;
15*/
16 13
17/ { 14/ {
18 model = "MPC8568EMDS"; 15 model = "MPC8568EMDS";
@@ -37,11 +34,11 @@
37 34
38 PowerPC,8568@0 { 35 PowerPC,8568@0 {
39 device_type = "cpu"; 36 device_type = "cpu";
40 reg = <0>; 37 reg = <0x0>;
41 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; 42 timebase-frequency = <0>;
46 bus-frequency = <0>; 43 bus-frequency = <0>;
47 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -50,36 +47,36 @@
50 47
51 memory { 48 memory {
52 device_type = "memory"; 49 device_type = "memory";
53 reg = <00000000 10000000>; 50 reg = <0x0 0x10000000>;
54 }; 51 };
55 52
56 bcsr@f8000000 { 53 bcsr@f8000000 {
57 device_type = "board-control"; 54 device_type = "board-control";
58 reg = <f8000000 8000>; 55 reg = <0xf8000000 0x8000>;
59 }; 56 };
60 57
61 soc8568@e0000000 { 58 soc8568@e0000000 {
62 #address-cells = <1>; 59 #address-cells = <1>;
63 #size-cells = <1>; 60 #size-cells = <1>;
64 device_type = "soc"; 61 device_type = "soc";
65 ranges = <0 e0000000 00100000>; 62 ranges = <0x0 0xe0000000 0x100000>;
66 reg = <e0000000 00001000>; 63 reg = <0xe0000000 0x1000>;
67 bus-frequency = <0>; 64 bus-frequency = <0>;
68 65
69 memory-controller@2000 { 66 memory-controller@2000 {
70 compatible = "fsl,8568-memory-controller"; 67 compatible = "fsl,8568-memory-controller";
71 reg = <2000 1000>; 68 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>; 69 interrupt-parent = <&mpic>;
73 interrupts = <12 2>; 70 interrupts = <18 2>;
74 }; 71 };
75 72
76 l2-cache-controller@20000 { 73 l2-cache-controller@20000 {
77 compatible = "fsl,8568-l2-cache-controller"; 74 compatible = "fsl,8568-l2-cache-controller";
78 reg = <20000 1000>; 75 reg = <0x20000 0x1000>;
79 cache-line-size = <20>; // 32 bytes 76 cache-line-size = <32>; // 32 bytes
80 cache-size = <80000>; // L2, 512K 77 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>;
82 interrupts = <10 2>; 79 interrupts = <16 2>;
83 }; 80 };
84 81
85 i2c@3000 { 82 i2c@3000 {
@@ -87,14 +84,14 @@
87 #size-cells = <0>; 84 #size-cells = <0>;
88 cell-index = <0>; 85 cell-index = <0>;
89 compatible = "fsl-i2c"; 86 compatible = "fsl-i2c";
90 reg = <3000 100>; 87 reg = <0x3000 0x100>;
91 interrupts = <2b 2>; 88 interrupts = <43 2>;
92 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
93 dfsrr; 90 dfsrr;
94 91
95 rtc@68 { 92 rtc@68 {
96 compatible = "dallas,ds1374"; 93 compatible = "dallas,ds1374";
97 reg = <68>; 94 reg = <0x68>;
98 }; 95 };
99 }; 96 };
100 97
@@ -103,8 +100,8 @@
103 #size-cells = <0>; 100 #size-cells = <0>;
104 cell-index = <1>; 101 cell-index = <1>;
105 compatible = "fsl-i2c"; 102 compatible = "fsl-i2c";
106 reg = <3100 100>; 103 reg = <0x3100 0x100>;
107 interrupts = <2b 2>; 104 interrupts = <43 2>;
108 interrupt-parent = <&mpic>; 105 interrupt-parent = <&mpic>;
109 dfsrr; 106 dfsrr;
110 }; 107 };
@@ -113,30 +110,30 @@
113 #address-cells = <1>; 110 #address-cells = <1>;
114 #size-cells = <0>; 111 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio"; 112 compatible = "fsl,gianfar-mdio";
116 reg = <24520 20>; 113 reg = <0x24520 0x20>;
117 114
118 phy0: ethernet-phy@7 { 115 phy0: ethernet-phy@7 {
119 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
120 interrupts = <1 1>; 117 interrupts = <1 1>;
121 reg = <7>; 118 reg = <0x7>;
122 device_type = "ethernet-phy"; 119 device_type = "ethernet-phy";
123 }; 120 };
124 phy1: ethernet-phy@1 { 121 phy1: ethernet-phy@1 {
125 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>;
126 interrupts = <2 1>; 123 interrupts = <2 1>;
127 reg = <1>; 124 reg = <0x1>;
128 device_type = "ethernet-phy"; 125 device_type = "ethernet-phy";
129 }; 126 };
130 phy2: ethernet-phy@2 { 127 phy2: ethernet-phy@2 {
131 interrupt-parent = <&mpic>; 128 interrupt-parent = <&mpic>;
132 interrupts = <1 1>; 129 interrupts = <1 1>;
133 reg = <2>; 130 reg = <0x2>;
134 device_type = "ethernet-phy"; 131 device_type = "ethernet-phy";
135 }; 132 };
136 phy3: ethernet-phy@3 { 133 phy3: ethernet-phy@3 {
137 interrupt-parent = <&mpic>; 134 interrupt-parent = <&mpic>;
138 interrupts = <2 1>; 135 interrupts = <2 1>;
139 reg = <3>; 136 reg = <0x3>;
140 device_type = "ethernet-phy"; 137 device_type = "ethernet-phy";
141 }; 138 };
142 }; 139 };
@@ -146,9 +143,9 @@
146 device_type = "network"; 143 device_type = "network";
147 model = "eTSEC"; 144 model = "eTSEC";
148 compatible = "gianfar"; 145 compatible = "gianfar";
149 reg = <24000 1000>; 146 reg = <0x24000 0x1000>;
150 local-mac-address = [ 00 00 00 00 00 00 ]; 147 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <1d 2 1e 2 22 2>; 148 interrupts = <29 2 30 2 34 2>;
152 interrupt-parent = <&mpic>; 149 interrupt-parent = <&mpic>;
153 phy-handle = <&phy2>; 150 phy-handle = <&phy2>;
154 }; 151 };
@@ -158,9 +155,9 @@
158 device_type = "network"; 155 device_type = "network";
159 model = "eTSEC"; 156 model = "eTSEC";
160 compatible = "gianfar"; 157 compatible = "gianfar";
161 reg = <25000 1000>; 158 reg = <0x25000 0x1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ]; 159 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <23 2 24 2 28 2>; 160 interrupts = <35 2 36 2 40 2>;
164 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>;
165 phy-handle = <&phy3>; 162 phy-handle = <&phy3>;
166 }; 163 };
@@ -169,15 +166,15 @@
169 cell-index = <0>; 166 cell-index = <0>;
170 device_type = "serial"; 167 device_type = "serial";
171 compatible = "ns16550"; 168 compatible = "ns16550";
172 reg = <4500 100>; 169 reg = <0x4500 0x100>;
173 clock-frequency = <0>; 170 clock-frequency = <0>;
174 interrupts = <2a 2>; 171 interrupts = <42 2>;
175 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>;
176 }; 173 };
177 174
178 global-utilities@e0000 { //global utilities block 175 global-utilities@e0000 { //global utilities block
179 compatible = "fsl,mpc8548-guts"; 176 compatible = "fsl,mpc8548-guts";
180 reg = <e0000 1000>; 177 reg = <0xe0000 0x1000>;
181 fsl,has-rstcr; 178 fsl,has-rstcr;
182 }; 179 };
183 180
@@ -185,9 +182,9 @@
185 cell-index = <1>; 182 cell-index = <1>;
186 device_type = "serial"; 183 device_type = "serial";
187 compatible = "ns16550"; 184 compatible = "ns16550";
188 reg = <4600 100>; 185 reg = <0x4600 0x100>;
189 clock-frequency = <0>; 186 clock-frequency = <0>;
190 interrupts = <2a 2>; 187 interrupts = <42 2>;
191 interrupt-parent = <&mpic>; 188 interrupt-parent = <&mpic>;
192 }; 189 };
193 190
@@ -195,13 +192,13 @@
195 device_type = "crypto"; 192 device_type = "crypto";
196 model = "SEC2"; 193 model = "SEC2";
197 compatible = "talitos"; 194 compatible = "talitos";
198 reg = <30000 f000>; 195 reg = <0x30000 0xf000>;
199 interrupts = <2d 2>; 196 interrupts = <45 2>;
200 interrupt-parent = <&mpic>; 197 interrupt-parent = <&mpic>;
201 num-channels = <4>; 198 num-channels = <4>;
202 channel-fifo-len = <18>; 199 channel-fifo-len = <24>;
203 exec-units-mask = <000000fe>; 200 exec-units-mask = <0xfe>;
204 descriptor-types-mask = <012b0ebf>; 201 descriptor-types-mask = <0x12b0ebf>;
205 }; 202 };
206 203
207 mpic: pic@40000 { 204 mpic: pic@40000 {
@@ -209,73 +206,73 @@
209 interrupt-controller; 206 interrupt-controller;
210 #address-cells = <0>; 207 #address-cells = <0>;
211 #interrupt-cells = <2>; 208 #interrupt-cells = <2>;
212 reg = <40000 40000>; 209 reg = <0x40000 0x40000>;
213 compatible = "chrp,open-pic"; 210 compatible = "chrp,open-pic";
214 device_type = "open-pic"; 211 device_type = "open-pic";
215 big-endian; 212 big-endian;
216 }; 213 };
217 214
218 par_io@e0100 { 215 par_io@e0100 {
219 reg = <e0100 100>; 216 reg = <0xe0100 0x100>;
220 device_type = "par_io"; 217 device_type = "par_io";
221 num-ports = <7>; 218 num-ports = <7>;
222 219
223 pio1: ucc_pin@01 { 220 pio1: ucc_pin@01 {
224 pio-map = < 221 pio-map = <
225 /* port pin dir open_drain assignment has_irq */ 222 /* port pin dir open_drain assignment has_irq */
226 4 0a 1 0 2 0 /* TxD0 */ 223 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
227 4 09 1 0 2 0 /* TxD1 */ 224 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
228 4 08 1 0 2 0 /* TxD2 */ 225 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
229 4 07 1 0 2 0 /* TxD3 */ 226 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
230 4 17 1 0 2 0 /* TxD4 */ 227 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
231 4 16 1 0 2 0 /* TxD5 */ 228 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
232 4 15 1 0 2 0 /* TxD6 */ 229 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
233 4 14 1 0 2 0 /* TxD7 */ 230 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
234 4 0f 2 0 2 0 /* RxD0 */ 231 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
235 4 0e 2 0 2 0 /* RxD1 */ 232 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
236 4 0d 2 0 2 0 /* RxD2 */ 233 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
237 4 0c 2 0 2 0 /* RxD3 */ 234 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
238 4 1d 2 0 2 0 /* RxD4 */ 235 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
239 4 1c 2 0 2 0 /* RxD5 */ 236 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
240 4 1b 2 0 2 0 /* RxD6 */ 237 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
241 4 1a 2 0 2 0 /* RxD7 */ 238 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
242 4 0b 1 0 2 0 /* TX_EN */ 239 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
243 4 18 1 0 2 0 /* TX_ER */ 240 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
244 4 10 2 0 2 0 /* RX_DV */ 241 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
245 4 1e 2 0 2 0 /* RX_ER */ 242 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
246 4 11 2 0 2 0 /* RX_CLK */ 243 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
247 4 13 1 0 2 0 /* GTX_CLK */ 244 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
248 1 1f 2 0 3 0>; /* GTX125 */ 245 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
249 }; 246 };
250 247
251 pio2: ucc_pin@02 { 248 pio2: ucc_pin@02 {
252 pio-map = < 249 pio-map = <
253 /* port pin dir open_drain assignment has_irq */ 250 /* port pin dir open_drain assignment has_irq */
254 5 0a 1 0 2 0 /* TxD0 */ 251 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
255 5 09 1 0 2 0 /* TxD1 */ 252 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
256 5 08 1 0 2 0 /* TxD2 */ 253 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
257 5 07 1 0 2 0 /* TxD3 */ 254 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
258 5 17 1 0 2 0 /* TxD4 */ 255 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
259 5 16 1 0 2 0 /* TxD5 */ 256 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
260 5 15 1 0 2 0 /* TxD6 */ 257 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
261 5 14 1 0 2 0 /* TxD7 */ 258 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
262 5 0f 2 0 2 0 /* RxD0 */ 259 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
263 5 0e 2 0 2 0 /* RxD1 */ 260 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
264 5 0d 2 0 2 0 /* RxD2 */ 261 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
265 5 0c 2 0 2 0 /* RxD3 */ 262 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
266 5 1d 2 0 2 0 /* RxD4 */ 263 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
267 5 1c 2 0 2 0 /* RxD5 */ 264 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
268 5 1b 2 0 2 0 /* RxD6 */ 265 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
269 5 1a 2 0 2 0 /* RxD7 */ 266 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
270 5 0b 1 0 2 0 /* TX_EN */ 267 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
271 5 18 1 0 2 0 /* TX_ER */ 268 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
272 5 10 2 0 2 0 /* RX_DV */ 269 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
273 5 1e 2 0 2 0 /* RX_ER */ 270 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
274 5 11 2 0 2 0 /* RX_CLK */ 271 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
275 5 13 1 0 2 0 /* GTX_CLK */ 272 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
276 1 1f 2 0 3 0 /* GTX125 */ 273 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
277 4 06 3 0 2 0 /* MDIO */ 274 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
278 4 05 1 0 2 0>; /* MDC */ 275 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
279 }; 276 };
280 }; 277 };
281 }; 278 };
@@ -285,28 +282,28 @@
285 #size-cells = <1>; 282 #size-cells = <1>;
286 device_type = "qe"; 283 device_type = "qe";
287 compatible = "fsl,qe"; 284 compatible = "fsl,qe";
288 ranges = <0 e0080000 00040000>; 285 ranges = <0x0 0xe0080000 0x40000>;
289 reg = <e0080000 480>; 286 reg = <0xe0080000 0x480>;
290 brg-frequency = <0>; 287 brg-frequency = <0>;
291 bus-frequency = <179A7B00>; 288 bus-frequency = <396000000>;
292 289
293 muram@10000 { 290 muram@10000 {
294 #address-cells = <1>; 291 #address-cells = <1>;
295 #size-cells = <1>; 292 #size-cells = <1>;
296 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 293 compatible = "fsl,qe-muram", "fsl,cpm-muram";
297 ranges = <0 00010000 0000c000>; 294 ranges = <0x0 0x10000 0x10000>;
298 295
299 data-only@0 { 296 data-only@0 {
300 compatible = "fsl,qe-muram-data", 297 compatible = "fsl,qe-muram-data",
301 "fsl,cpm-muram-data"; 298 "fsl,cpm-muram-data";
302 reg = <0 c000>; 299 reg = <0x0 0x10000>;
303 }; 300 };
304 }; 301 };
305 302
306 spi@4c0 { 303 spi@4c0 {
307 cell-index = <0>; 304 cell-index = <0>;
308 compatible = "fsl,spi"; 305 compatible = "fsl,spi";
309 reg = <4c0 40>; 306 reg = <0x4c0 0x40>;
310 interrupts = <2>; 307 interrupts = <2>;
311 interrupt-parent = <&qeic>; 308 interrupt-parent = <&qeic>;
312 mode = "cpu"; 309 mode = "cpu";
@@ -315,7 +312,7 @@
315 spi@500 { 312 spi@500 {
316 cell-index = <1>; 313 cell-index = <1>;
317 compatible = "fsl,spi"; 314 compatible = "fsl,spi";
318 reg = <500 40>; 315 reg = <0x500 0x40>;
319 interrupts = <1>; 316 interrupts = <1>;
320 interrupt-parent = <&qeic>; 317 interrupt-parent = <&qeic>;
321 mode = "cpu"; 318 mode = "cpu";
@@ -324,11 +321,9 @@
324 enet2: ucc@2000 { 321 enet2: ucc@2000 {
325 device_type = "network"; 322 device_type = "network";
326 compatible = "ucc_geth"; 323 compatible = "ucc_geth";
327 model = "UCC";
328 cell-index = <1>; 324 cell-index = <1>;
329 device-id = <1>; 325 reg = <0x2000 0x200>;
330 reg = <2000 200>; 326 interrupts = <32>;
331 interrupts = <20>;
332 interrupt-parent = <&qeic>; 327 interrupt-parent = <&qeic>;
333 local-mac-address = [ 00 00 00 00 00 00 ]; 328 local-mac-address = [ 00 00 00 00 00 00 ];
334 rx-clock-name = "none"; 329 rx-clock-name = "none";
@@ -341,11 +336,9 @@
341 enet3: ucc@3000 { 336 enet3: ucc@3000 {
342 device_type = "network"; 337 device_type = "network";
343 compatible = "ucc_geth"; 338 compatible = "ucc_geth";
344 model = "UCC";
345 cell-index = <2>; 339 cell-index = <2>;
346 device-id = <2>; 340 reg = <0x3000 0x200>;
347 reg = <3000 200>; 341 interrupts = <33>;
348 interrupts = <21>;
349 interrupt-parent = <&qeic>; 342 interrupt-parent = <&qeic>;
350 local-mac-address = [ 00 00 00 00 00 00 ]; 343 local-mac-address = [ 00 00 00 00 00 00 ];
351 rx-clock-name = "none"; 344 rx-clock-name = "none";
@@ -358,7 +351,7 @@
358 mdio@2120 { 351 mdio@2120 {
359 #address-cells = <1>; 352 #address-cells = <1>;
360 #size-cells = <0>; 353 #size-cells = <0>;
361 reg = <2120 18>; 354 reg = <0x2120 0x18>;
362 compatible = "fsl,ucc-mdio"; 355 compatible = "fsl,ucc-mdio";
363 356
364 /* These are the same PHYs as on 357 /* These are the same PHYs as on
@@ -366,25 +359,25 @@
366 qe_phy0: ethernet-phy@07 { 359 qe_phy0: ethernet-phy@07 {
367 interrupt-parent = <&mpic>; 360 interrupt-parent = <&mpic>;
368 interrupts = <1 1>; 361 interrupts = <1 1>;
369 reg = <7>; 362 reg = <0x7>;
370 device_type = "ethernet-phy"; 363 device_type = "ethernet-phy";
371 }; 364 };
372 qe_phy1: ethernet-phy@01 { 365 qe_phy1: ethernet-phy@01 {
373 interrupt-parent = <&mpic>; 366 interrupt-parent = <&mpic>;
374 interrupts = <2 1>; 367 interrupts = <2 1>;
375 reg = <1>; 368 reg = <0x1>;
376 device_type = "ethernet-phy"; 369 device_type = "ethernet-phy";
377 }; 370 };
378 qe_phy2: ethernet-phy@02 { 371 qe_phy2: ethernet-phy@02 {
379 interrupt-parent = <&mpic>; 372 interrupt-parent = <&mpic>;
380 interrupts = <1 1>; 373 interrupts = <1 1>;
381 reg = <2>; 374 reg = <0x2>;
382 device_type = "ethernet-phy"; 375 device_type = "ethernet-phy";
383 }; 376 };
384 qe_phy3: ethernet-phy@03 { 377 qe_phy3: ethernet-phy@03 {
385 interrupt-parent = <&mpic>; 378 interrupt-parent = <&mpic>;
386 interrupts = <2 1>; 379 interrupts = <2 1>;
387 reg = <3>; 380 reg = <0x3>;
388 device_type = "ethernet-phy"; 381 device_type = "ethernet-phy";
389 }; 382 };
390 }; 383 };
@@ -394,9 +387,9 @@
394 compatible = "fsl,qe-ic"; 387 compatible = "fsl,qe-ic";
395 #address-cells = <0>; 388 #address-cells = <0>;
396 #interrupt-cells = <1>; 389 #interrupt-cells = <1>;
397 reg = <80 80>; 390 reg = <0x80 0x80>;
398 big-endian; 391 big-endian;
399 interrupts = <2e 2 2e 2>; //high:30 low:30 392 interrupts = <46 2 46 2>; //high:30 low:30
400 interrupt-parent = <&mpic>; 393 interrupt-parent = <&mpic>;
401 }; 394 };
402 395
@@ -404,30 +397,30 @@
404 397
405 pci0: pci@e0008000 { 398 pci0: pci@e0008000 {
406 cell-index = <0>; 399 cell-index = <0>;
407 interrupt-map-mask = <f800 0 0 7>; 400 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
408 interrupt-map = < 401 interrupt-map = <
409 /* IDSEL 0x12 AD18 */ 402 /* IDSEL 0x12 AD18 */
410 9000 0 0 1 &mpic 5 1 403 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
411 9000 0 0 2 &mpic 6 1 404 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
412 9000 0 0 3 &mpic 7 1 405 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
413 9000 0 0 4 &mpic 4 1 406 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
414 407
415 /* IDSEL 0x13 AD19 */ 408 /* IDSEL 0x13 AD19 */
416 9800 0 0 1 &mpic 6 1 409 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
417 9800 0 0 2 &mpic 7 1 410 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
418 9800 0 0 3 &mpic 4 1 411 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
419 9800 0 0 4 &mpic 5 1>; 412 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
420 413
421 interrupt-parent = <&mpic>; 414 interrupt-parent = <&mpic>;
422 interrupts = <18 2>; 415 interrupts = <24 2>;
423 bus-range = <0 ff>; 416 bus-range = <0 255>;
424 ranges = <02000000 0 80000000 80000000 0 20000000 417 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
425 01000000 0 00000000 e2000000 0 00800000>; 418 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
426 clock-frequency = <3f940aa>; 419 clock-frequency = <66666666>;
427 #interrupt-cells = <1>; 420 #interrupt-cells = <1>;
428 #size-cells = <2>; 421 #size-cells = <2>;
429 #address-cells = <3>; 422 #address-cells = <3>;
430 reg = <e0008000 1000>; 423 reg = <0xe0008000 0x1000>;
431 compatible = "fsl,mpc8540-pci"; 424 compatible = "fsl,mpc8540-pci";
432 device_type = "pci"; 425 device_type = "pci";
433 }; 426 };
@@ -435,39 +428,39 @@
435 /* PCI Express */ 428 /* PCI Express */
436 pci1: pcie@e000a000 { 429 pci1: pcie@e000a000 {
437 cell-index = <2>; 430 cell-index = <2>;
438 interrupt-map-mask = <f800 0 0 7>; 431 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
439 interrupt-map = < 432 interrupt-map = <
440 433
441 /* IDSEL 0x0 (PEX) */ 434 /* IDSEL 0x0 (PEX) */
442 00000 0 0 1 &mpic 0 1 435 00000 0x0 0x0 0x1 &mpic 0x0 0x1
443 00000 0 0 2 &mpic 1 1 436 00000 0x0 0x0 0x2 &mpic 0x1 0x1
444 00000 0 0 3 &mpic 2 1 437 00000 0x0 0x0 0x3 &mpic 0x2 0x1
445 00000 0 0 4 &mpic 3 1>; 438 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
446 439
447 interrupt-parent = <&mpic>; 440 interrupt-parent = <&mpic>;
448 interrupts = <1a 2>; 441 interrupts = <26 2>;
449 bus-range = <0 ff>; 442 bus-range = <0 255>;
450 ranges = <02000000 0 a0000000 a0000000 0 10000000 443 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
451 01000000 0 00000000 e2800000 0 00800000>; 444 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
452 clock-frequency = <1fca055>; 445 clock-frequency = <33333333>;
453 #interrupt-cells = <1>; 446 #interrupt-cells = <1>;
454 #size-cells = <2>; 447 #size-cells = <2>;
455 #address-cells = <3>; 448 #address-cells = <3>;
456 reg = <e000a000 1000>; 449 reg = <0xe000a000 0x1000>;
457 compatible = "fsl,mpc8548-pcie"; 450 compatible = "fsl,mpc8548-pcie";
458 device_type = "pci"; 451 device_type = "pci";
459 pcie@0 { 452 pcie@0 {
460 reg = <0 0 0 0 0>; 453 reg = <0x0 0x0 0x0 0x0 0x0>;
461 #size-cells = <2>; 454 #size-cells = <2>;
462 #address-cells = <3>; 455 #address-cells = <3>;
463 device_type = "pci"; 456 device_type = "pci";
464 ranges = <02000000 0 a0000000 457 ranges = <0x2000000 0x0 0xa0000000
465 02000000 0 a0000000 458 0x2000000 0x0 0xa0000000
466 0 10000000 459 0x0 0x10000000
467 460
468 01000000 0 00000000 461 0x1000000 0x0 0x0
469 01000000 0 00000000 462 0x1000000 0x0 0x0
470 0 00800000>; 463 0x0 0x800000>;
471 }; 464 };
472 }; 465 };
473}; 466};
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index db37214aee37..66f27ab613a2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "fsl,MPC8572DS"; 14 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS"; 15 compatible = "fsl,MPC8572DS";
@@ -33,11 +34,11 @@
33 34
34 PowerPC,8572@0 { 35 PowerPC,8572@0 {
35 device_type = "cpu"; 36 device_type = "cpu";
36 reg = <0>; 37 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 42 timebase-frequency = <0>;
42 bus-frequency = <0>; 43 bus-frequency = <0>;
43 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -45,11 +46,11 @@
45 46
46 PowerPC,8572@1 { 47 PowerPC,8572@1 {
47 device_type = "cpu"; 48 device_type = "cpu";
48 reg = <1>; 49 reg = <0x1>;
49 d-cache-line-size = <20>; // 32 bytes 50 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <20>; // 32 bytes 51 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <8000>; // L1, 32K 52 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <8000>; // L1, 32K 53 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>; 54 timebase-frequency = <0>;
54 bus-frequency = <0>; 55 bus-frequency = <0>;
55 clock-frequency = <0>; 56 clock-frequency = <0>;
@@ -58,38 +59,38 @@
58 59
59 memory { 60 memory {
60 device_type = "memory"; 61 device_type = "memory";
61 reg = <00000000 00000000>; // Filled by U-Boot 62 reg = <0x0 0x0>; // Filled by U-Boot
62 }; 63 };
63 64
64 soc8572@ffe00000 { 65 soc8572@ffe00000 {
65 #address-cells = <1>; 66 #address-cells = <1>;
66 #size-cells = <1>; 67 #size-cells = <1>;
67 device_type = "soc"; 68 device_type = "soc";
68 ranges = <00000000 ffe00000 00100000>; 69 ranges = <0x0 0xffe00000 0x100000>;
69 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed 70 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
70 bus-frequency = <0>; // Filled out by uboot. 71 bus-frequency = <0>; // Filled out by uboot.
71 72
72 memory-controller@2000 { 73 memory-controller@2000 {
73 compatible = "fsl,mpc8572-memory-controller"; 74 compatible = "fsl,mpc8572-memory-controller";
74 reg = <2000 1000>; 75 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <12 2>; 77 interrupts = <18 2>;
77 }; 78 };
78 79
79 memory-controller@6000 { 80 memory-controller@6000 {
80 compatible = "fsl,mpc8572-memory-controller"; 81 compatible = "fsl,mpc8572-memory-controller";
81 reg = <6000 1000>; 82 reg = <0x6000 0x1000>;
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 interrupts = <12 2>; 84 interrupts = <18 2>;
84 }; 85 };
85 86
86 l2-cache-controller@20000 { 87 l2-cache-controller@20000 {
87 compatible = "fsl,mpc8572-l2-cache-controller"; 88 compatible = "fsl,mpc8572-l2-cache-controller";
88 reg = <20000 1000>; 89 reg = <0x20000 0x1000>;
89 cache-line-size = <20>; // 32 bytes 90 cache-line-size = <32>; // 32 bytes
90 cache-size = <80000>; // L2, 512K 91 cache-size = <0x80000>; // L2, 512K
91 interrupt-parent = <&mpic>; 92 interrupt-parent = <&mpic>;
92 interrupts = <10 2>; 93 interrupts = <16 2>;
93 }; 94 };
94 95
95 i2c@3000 { 96 i2c@3000 {
@@ -97,8 +98,8 @@
97 #size-cells = <0>; 98 #size-cells = <0>;
98 cell-index = <0>; 99 cell-index = <0>;
99 compatible = "fsl-i2c"; 100 compatible = "fsl-i2c";
100 reg = <3000 100>; 101 reg = <0x3000 0x100>;
101 interrupts = <2b 2>; 102 interrupts = <43 2>;
102 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
103 dfsrr; 104 dfsrr;
104 }; 105 };
@@ -108,8 +109,8 @@
108 #size-cells = <0>; 109 #size-cells = <0>;
109 cell-index = <1>; 110 cell-index = <1>;
110 compatible = "fsl-i2c"; 111 compatible = "fsl-i2c";
111 reg = <3100 100>; 112 reg = <0x3100 0x100>;
112 interrupts = <2b 2>; 113 interrupts = <43 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 dfsrr; 115 dfsrr;
115 }; 116 };
@@ -118,27 +119,27 @@
118 #address-cells = <1>; 119 #address-cells = <1>;
119 #size-cells = <0>; 120 #size-cells = <0>;
120 compatible = "fsl,gianfar-mdio"; 121 compatible = "fsl,gianfar-mdio";
121 reg = <24520 20>; 122 reg = <0x24520 0x20>;
122 123
123 phy0: ethernet-phy@0 { 124 phy0: ethernet-phy@0 {
124 interrupt-parent = <&mpic>; 125 interrupt-parent = <&mpic>;
125 interrupts = <a 1>; 126 interrupts = <10 1>;
126 reg = <0>; 127 reg = <0x0>;
127 }; 128 };
128 phy1: ethernet-phy@1 { 129 phy1: ethernet-phy@1 {
129 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>;
130 interrupts = <a 1>; 131 interrupts = <10 1>;
131 reg = <1>; 132 reg = <0x1>;
132 }; 133 };
133 phy2: ethernet-phy@2 { 134 phy2: ethernet-phy@2 {
134 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
135 interrupts = <a 1>; 136 interrupts = <10 1>;
136 reg = <2>; 137 reg = <0x2>;
137 }; 138 };
138 phy3: ethernet-phy@3 { 139 phy3: ethernet-phy@3 {
139 interrupt-parent = <&mpic>; 140 interrupt-parent = <&mpic>;
140 interrupts = <a 1>; 141 interrupts = <10 1>;
141 reg = <3>; 142 reg = <0x3>;
142 }; 143 };
143 }; 144 };
144 145
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <24000 1000>; 151 reg = <0x24000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <1d 2 1e 2 22 2>; 153 interrupts = <29 2 30 2 34 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy0>; 155 phy-handle = <&phy0>;
155 phy-connection-type = "rgmii-id"; 156 phy-connection-type = "rgmii-id";
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <25000 1000>; 164 reg = <0x25000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <23 2 24 2 28 2>; 166 interrupts = <35 2 36 2 40 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy1>; 168 phy-handle = <&phy1>;
168 phy-connection-type = "rgmii-id"; 169 phy-connection-type = "rgmii-id";
@@ -173,9 +174,9 @@
173 device_type = "network"; 174 device_type = "network";
174 model = "eTSEC"; 175 model = "eTSEC";
175 compatible = "gianfar"; 176 compatible = "gianfar";
176 reg = <26000 1000>; 177 reg = <0x26000 0x1000>;
177 local-mac-address = [ 00 00 00 00 00 00 ]; 178 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupts = <1f 2 20 2 21 2>; 179 interrupts = <31 2 32 2 33 2>;
179 interrupt-parent = <&mpic>; 180 interrupt-parent = <&mpic>;
180 phy-handle = <&phy2>; 181 phy-handle = <&phy2>;
181 phy-connection-type = "rgmii-id"; 182 phy-connection-type = "rgmii-id";
@@ -186,9 +187,9 @@
186 device_type = "network"; 187 device_type = "network";
187 model = "eTSEC"; 188 model = "eTSEC";
188 compatible = "gianfar"; 189 compatible = "gianfar";
189 reg = <27000 1000>; 190 reg = <0x27000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ]; 191 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <25 2 26 2 27 2>; 192 interrupts = <37 2 38 2 39 2>;
192 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
193 phy-handle = <&phy3>; 194 phy-handle = <&phy3>;
194 phy-connection-type = "rgmii-id"; 195 phy-connection-type = "rgmii-id";
@@ -198,9 +199,9 @@
198 cell-index = <0>; 199 cell-index = <0>;
199 device_type = "serial"; 200 device_type = "serial";
200 compatible = "ns16550"; 201 compatible = "ns16550";
201 reg = <4500 100>; 202 reg = <0x4500 0x100>;
202 clock-frequency = <0>; 203 clock-frequency = <0>;
203 interrupts = <2a 2>; 204 interrupts = <42 2>;
204 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
205 }; 206 };
206 207
@@ -208,15 +209,15 @@
208 cell-index = <1>; 209 cell-index = <1>;
209 device_type = "serial"; 210 device_type = "serial";
210 compatible = "ns16550"; 211 compatible = "ns16550";
211 reg = <4600 100>; 212 reg = <0x4600 0x100>;
212 clock-frequency = <0>; 213 clock-frequency = <0>;
213 interrupts = <2a 2>; 214 interrupts = <42 2>;
214 interrupt-parent = <&mpic>; 215 interrupt-parent = <&mpic>;
215 }; 216 };
216 217
217 global-utilities@e0000 { //global utilities block 218 global-utilities@e0000 { //global utilities block
218 compatible = "fsl,mpc8572-guts"; 219 compatible = "fsl,mpc8572-guts";
219 reg = <e0000 1000>; 220 reg = <0xe0000 0x1000>;
220 fsl,has-rstcr; 221 fsl,has-rstcr;
221 }; 222 };
222 223
@@ -225,7 +226,7 @@
225 interrupt-controller; 226 interrupt-controller;
226 #address-cells = <0>; 227 #address-cells = <0>;
227 #interrupt-cells = <2>; 228 #interrupt-cells = <2>;
228 reg = <40000 40000>; 229 reg = <0x40000 0x40000>;
229 compatible = "chrp,open-pic"; 230 compatible = "chrp,open-pic";
230 device_type = "open-pic"; 231 device_type = "open-pic";
231 big-endian; 232 big-endian;
@@ -239,167 +240,167 @@
239 #interrupt-cells = <1>; 240 #interrupt-cells = <1>;
240 #size-cells = <2>; 241 #size-cells = <2>;
241 #address-cells = <3>; 242 #address-cells = <3>;
242 reg = <ffe08000 1000>; 243 reg = <0xffe08000 0x1000>;
243 bus-range = <0 ff>; 244 bus-range = <0 255>;
244 ranges = <02000000 0 80000000 80000000 0 20000000 245 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
245 01000000 0 00000000 ffc00000 0 00010000>; 246 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
246 clock-frequency = <1fca055>; 247 clock-frequency = <33333333>;
247 interrupt-parent = <&mpic>; 248 interrupt-parent = <&mpic>;
248 interrupts = <18 2>; 249 interrupts = <24 2>;
249 interrupt-map-mask = <ff00 0 0 7>; 250 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
250 interrupt-map = < 251 interrupt-map = <
251 /* IDSEL 0x11 func 0 - PCI slot 1 */ 252 /* IDSEL 0x11 func 0 - PCI slot 1 */
252 8800 0 0 1 &mpic 2 1 253 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
253 8800 0 0 2 &mpic 3 1 254 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
254 8800 0 0 3 &mpic 4 1 255 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
255 8800 0 0 4 &mpic 1 1 256 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
256 257
257 /* IDSEL 0x11 func 1 - PCI slot 1 */ 258 /* IDSEL 0x11 func 1 - PCI slot 1 */
258 8900 0 0 1 &mpic 2 1 259 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
259 8900 0 0 2 &mpic 3 1 260 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
260 8900 0 0 3 &mpic 4 1 261 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
261 8900 0 0 4 &mpic 1 1 262 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
262 263
263 /* IDSEL 0x11 func 2 - PCI slot 1 */ 264 /* IDSEL 0x11 func 2 - PCI slot 1 */
264 8a00 0 0 1 &mpic 2 1 265 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
265 8a00 0 0 2 &mpic 3 1 266 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
266 8a00 0 0 3 &mpic 4 1 267 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
267 8a00 0 0 4 &mpic 1 1 268 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
268 269
269 /* IDSEL 0x11 func 3 - PCI slot 1 */ 270 /* IDSEL 0x11 func 3 - PCI slot 1 */
270 8b00 0 0 1 &mpic 2 1 271 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
271 8b00 0 0 2 &mpic 3 1 272 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
272 8b00 0 0 3 &mpic 4 1 273 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
273 8b00 0 0 4 &mpic 1 1 274 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
274 275
275 /* IDSEL 0x11 func 4 - PCI slot 1 */ 276 /* IDSEL 0x11 func 4 - PCI slot 1 */
276 8c00 0 0 1 &mpic 2 1 277 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
277 8c00 0 0 2 &mpic 3 1 278 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
278 8c00 0 0 3 &mpic 4 1 279 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
279 8c00 0 0 4 &mpic 1 1 280 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
280 281
281 /* IDSEL 0x11 func 5 - PCI slot 1 */ 282 /* IDSEL 0x11 func 5 - PCI slot 1 */
282 8d00 0 0 1 &mpic 2 1 283 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
283 8d00 0 0 2 &mpic 3 1 284 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
284 8d00 0 0 3 &mpic 4 1 285 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
285 8d00 0 0 4 &mpic 1 1 286 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
286 287
287 /* IDSEL 0x11 func 6 - PCI slot 1 */ 288 /* IDSEL 0x11 func 6 - PCI slot 1 */
288 8e00 0 0 1 &mpic 2 1 289 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
289 8e00 0 0 2 &mpic 3 1 290 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
290 8e00 0 0 3 &mpic 4 1 291 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
291 8e00 0 0 4 &mpic 1 1 292 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
292 293
293 /* IDSEL 0x11 func 7 - PCI slot 1 */ 294 /* IDSEL 0x11 func 7 - PCI slot 1 */
294 8f00 0 0 1 &mpic 2 1 295 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
295 8f00 0 0 2 &mpic 3 1 296 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
296 8f00 0 0 3 &mpic 4 1 297 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
297 8f00 0 0 4 &mpic 1 1 298 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
298 299
299 /* IDSEL 0x12 func 0 - PCI slot 2 */ 300 /* IDSEL 0x12 func 0 - PCI slot 2 */
300 9000 0 0 1 &mpic 3 1 301 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
301 9000 0 0 2 &mpic 4 1 302 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
302 9000 0 0 3 &mpic 1 1 303 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
303 9000 0 0 4 &mpic 2 1 304 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
304 305
305 /* IDSEL 0x12 func 1 - PCI slot 2 */ 306 /* IDSEL 0x12 func 1 - PCI slot 2 */
306 9100 0 0 1 &mpic 3 1 307 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
307 9100 0 0 2 &mpic 4 1 308 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
308 9100 0 0 3 &mpic 1 1 309 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
309 9100 0 0 4 &mpic 2 1 310 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
310 311
311 /* IDSEL 0x12 func 2 - PCI slot 2 */ 312 /* IDSEL 0x12 func 2 - PCI slot 2 */
312 9200 0 0 1 &mpic 3 1 313 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
313 9200 0 0 2 &mpic 4 1 314 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
314 9200 0 0 3 &mpic 1 1 315 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
315 9200 0 0 4 &mpic 2 1 316 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
316 317
317 /* IDSEL 0x12 func 3 - PCI slot 2 */ 318 /* IDSEL 0x12 func 3 - PCI slot 2 */
318 9300 0 0 1 &mpic 3 1 319 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
319 9300 0 0 2 &mpic 4 1 320 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
320 9300 0 0 3 &mpic 1 1 321 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
321 9300 0 0 4 &mpic 2 1 322 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
322 323
323 /* IDSEL 0x12 func 4 - PCI slot 2 */ 324 /* IDSEL 0x12 func 4 - PCI slot 2 */
324 9400 0 0 1 &mpic 3 1 325 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
325 9400 0 0 2 &mpic 4 1 326 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
326 9400 0 0 3 &mpic 1 1 327 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
327 9400 0 0 4 &mpic 2 1 328 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
328 329
329 /* IDSEL 0x12 func 5 - PCI slot 2 */ 330 /* IDSEL 0x12 func 5 - PCI slot 2 */
330 9500 0 0 1 &mpic 3 1 331 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
331 9500 0 0 2 &mpic 4 1 332 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
332 9500 0 0 3 &mpic 1 1 333 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
333 9500 0 0 4 &mpic 2 1 334 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
334 335
335 /* IDSEL 0x12 func 6 - PCI slot 2 */ 336 /* IDSEL 0x12 func 6 - PCI slot 2 */
336 9600 0 0 1 &mpic 3 1 337 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
337 9600 0 0 2 &mpic 4 1 338 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
338 9600 0 0 3 &mpic 1 1 339 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
339 9600 0 0 4 &mpic 2 1 340 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
340 341
341 /* IDSEL 0x12 func 7 - PCI slot 2 */ 342 /* IDSEL 0x12 func 7 - PCI slot 2 */
342 9700 0 0 1 &mpic 3 1 343 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
343 9700 0 0 2 &mpic 4 1 344 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
344 9700 0 0 3 &mpic 1 1 345 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
345 9700 0 0 4 &mpic 2 1 346 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
346 347
347 // IDSEL 0x1c USB 348 // IDSEL 0x1c USB
348 e000 0 0 1 &i8259 c 2 349 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
349 e100 0 0 2 &i8259 9 2 350 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
350 e200 0 0 3 &i8259 a 2 351 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
351 e300 0 0 4 &i8259 b 2 352 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
352 353
353 // IDSEL 0x1d Audio 354 // IDSEL 0x1d Audio
354 e800 0 0 1 &i8259 6 2 355 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
355 356
356 // IDSEL 0x1e Legacy 357 // IDSEL 0x1e Legacy
357 f000 0 0 1 &i8259 7 2 358 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
358 f100 0 0 1 &i8259 7 2 359 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
359 360
360 // IDSEL 0x1f IDE/SATA 361 // IDSEL 0x1f IDE/SATA
361 f800 0 0 1 &i8259 e 2 362 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
362 f900 0 0 1 &i8259 5 2 363 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
363 364
364 >; 365 >;
365 366
366 pcie@0 { 367 pcie@0 {
367 reg = <0 0 0 0 0>; 368 reg = <0x0 0x0 0x0 0x0 0x0>;
368 #size-cells = <2>; 369 #size-cells = <2>;
369 #address-cells = <3>; 370 #address-cells = <3>;
370 device_type = "pci"; 371 device_type = "pci";
371 ranges = <02000000 0 80000000 372 ranges = <0x2000000 0x0 0x80000000
372 02000000 0 80000000 373 0x2000000 0x0 0x80000000
373 0 20000000 374 0x0 0x20000000
374 375
375 01000000 0 00000000 376 0x1000000 0x0 0x0
376 01000000 0 00000000 377 0x1000000 0x0 0x0
377 0 00100000>; 378 0x0 0x100000>;
378 uli1575@0 { 379 uli1575@0 {
379 reg = <0 0 0 0 0>; 380 reg = <0x0 0x0 0x0 0x0 0x0>;
380 #size-cells = <2>; 381 #size-cells = <2>;
381 #address-cells = <3>; 382 #address-cells = <3>;
382 ranges = <02000000 0 80000000 383 ranges = <0x2000000 0x0 0x80000000
383 02000000 0 80000000 384 0x2000000 0x0 0x80000000
384 0 20000000 385 0x0 0x20000000
385 386
386 01000000 0 00000000 387 0x1000000 0x0 0x0
387 01000000 0 00000000 388 0x1000000 0x0 0x0
388 0 00100000>; 389 0x0 0x100000>;
389 isa@1e { 390 isa@1e {
390 device_type = "isa"; 391 device_type = "isa";
391 #interrupt-cells = <2>; 392 #interrupt-cells = <2>;
392 #size-cells = <1>; 393 #size-cells = <1>;
393 #address-cells = <2>; 394 #address-cells = <2>;
394 reg = <f000 0 0 0 0>; 395 reg = <0xf000 0x0 0x0 0x0 0x0>;
395 ranges = <1 0 01000000 0 0 396 ranges = <0x1 0x0 0x1000000 0x0 0x0
396 00001000>; 397 0x1000>;
397 interrupt-parent = <&i8259>; 398 interrupt-parent = <&i8259>;
398 399
399 i8259: interrupt-controller@20 { 400 i8259: interrupt-controller@20 {
400 reg = <1 20 2 401 reg = <0x1 0x20 0x2
401 1 a0 2 402 0x1 0xa0 0x2
402 1 4d0 2>; 403 0x1 0x4d0 0x2>;
403 interrupt-controller; 404 interrupt-controller;
404 device_type = "interrupt-controller"; 405 device_type = "interrupt-controller";
405 #address-cells = <0>; 406 #address-cells = <0>;
@@ -412,29 +413,29 @@
412 i8042@60 { 413 i8042@60 {
413 #size-cells = <0>; 414 #size-cells = <0>;
414 #address-cells = <1>; 415 #address-cells = <1>;
415 reg = <1 60 1 1 64 1>; 416 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
416 interrupts = <1 3 c 3>; 417 interrupts = <1 3 12 3>;
417 interrupt-parent = 418 interrupt-parent =
418 <&i8259>; 419 <&i8259>;
419 420
420 keyboard@0 { 421 keyboard@0 {
421 reg = <0>; 422 reg = <0x0>;
422 compatible = "pnpPNP,303"; 423 compatible = "pnpPNP,303";
423 }; 424 };
424 425
425 mouse@1 { 426 mouse@1 {
426 reg = <1>; 427 reg = <0x1>;
427 compatible = "pnpPNP,f03"; 428 compatible = "pnpPNP,f03";
428 }; 429 };
429 }; 430 };
430 431
431 rtc@70 { 432 rtc@70 {
432 compatible = "pnpPNP,b00"; 433 compatible = "pnpPNP,b00";
433 reg = <1 70 2>; 434 reg = <0x1 0x70 0x2>;
434 }; 435 };
435 436
436 gpio@400 { 437 gpio@400 {
437 reg = <1 400 80>; 438 reg = <0x1 0x400 0x80>;
438 }; 439 };
439 }; 440 };
440 }; 441 };
@@ -449,33 +450,33 @@
449 #interrupt-cells = <1>; 450 #interrupt-cells = <1>;
450 #size-cells = <2>; 451 #size-cells = <2>;
451 #address-cells = <3>; 452 #address-cells = <3>;
452 reg = <ffe09000 1000>; 453 reg = <0xffe09000 0x1000>;
453 bus-range = <0 ff>; 454 bus-range = <0 255>;
454 ranges = <02000000 0 a0000000 a0000000 0 20000000 455 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
455 01000000 0 00000000 ffc10000 0 00010000>; 456 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
456 clock-frequency = <1fca055>; 457 clock-frequency = <33333333>;
457 interrupt-parent = <&mpic>; 458 interrupt-parent = <&mpic>;
458 interrupts = <1a 2>; 459 interrupts = <26 2>;
459 interrupt-map-mask = <f800 0 0 7>; 460 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
460 interrupt-map = < 461 interrupt-map = <
461 /* IDSEL 0x0 */ 462 /* IDSEL 0x0 */
462 0000 0 0 1 &mpic 4 1 463 0000 0x0 0x0 0x1 &mpic 0x4 0x1
463 0000 0 0 2 &mpic 5 1 464 0000 0x0 0x0 0x2 &mpic 0x5 0x1
464 0000 0 0 3 &mpic 6 1 465 0000 0x0 0x0 0x3 &mpic 0x6 0x1
465 0000 0 0 4 &mpic 7 1 466 0000 0x0 0x0 0x4 &mpic 0x7 0x1
466 >; 467 >;
467 pcie@0 { 468 pcie@0 {
468 reg = <0 0 0 0 0>; 469 reg = <0x0 0x0 0x0 0x0 0x0>;
469 #size-cells = <2>; 470 #size-cells = <2>;
470 #address-cells = <3>; 471 #address-cells = <3>;
471 device_type = "pci"; 472 device_type = "pci";
472 ranges = <02000000 0 a0000000 473 ranges = <0x2000000 0x0 0xa0000000
473 02000000 0 a0000000 474 0x2000000 0x0 0xa0000000
474 0 20000000 475 0x0 0x20000000
475 476
476 01000000 0 00000000 477 0x1000000 0x0 0x0
477 01000000 0 00000000 478 0x1000000 0x0 0x0
478 0 00100000>; 479 0x0 0x100000>;
479 }; 480 };
480 }; 481 };
481 482
@@ -486,33 +487,33 @@
486 #interrupt-cells = <1>; 487 #interrupt-cells = <1>;
487 #size-cells = <2>; 488 #size-cells = <2>;
488 #address-cells = <3>; 489 #address-cells = <3>;
489 reg = <ffe0a000 1000>; 490 reg = <0xffe0a000 0x1000>;
490 bus-range = <0 ff>; 491 bus-range = <0 255>;
491 ranges = <02000000 0 c0000000 c0000000 0 20000000 492 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
492 01000000 0 00000000 ffc20000 0 00010000>; 493 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
493 clock-frequency = <1fca055>; 494 clock-frequency = <33333333>;
494 interrupt-parent = <&mpic>; 495 interrupt-parent = <&mpic>;
495 interrupts = <1b 2>; 496 interrupts = <27 2>;
496 interrupt-map-mask = <f800 0 0 7>; 497 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
497 interrupt-map = < 498 interrupt-map = <
498 /* IDSEL 0x0 */ 499 /* IDSEL 0x0 */
499 0000 0 0 1 &mpic 0 1 500 0000 0x0 0x0 0x1 &mpic 0x0 0x1
500 0000 0 0 2 &mpic 1 1 501 0000 0x0 0x0 0x2 &mpic 0x1 0x1
501 0000 0 0 3 &mpic 2 1 502 0000 0x0 0x0 0x3 &mpic 0x2 0x1
502 0000 0 0 4 &mpic 3 1 503 0000 0x0 0x0 0x4 &mpic 0x3 0x1
503 >; 504 >;
504 pcie@0 { 505 pcie@0 {
505 reg = <0 0 0 0 0>; 506 reg = <0x0 0x0 0x0 0x0 0x0>;
506 #size-cells = <2>; 507 #size-cells = <2>;
507 #address-cells = <3>; 508 #address-cells = <3>;
508 device_type = "pci"; 509 device_type = "pci";
509 ranges = <02000000 0 c0000000 510 ranges = <0x2000000 0x0 0xc0000000
510 02000000 0 c0000000 511 0x2000000 0x0 0xc0000000
511 0 20000000 512 0x0 0x20000000
512 513
513 01000000 0 00000000 514 0x1000000 0x0 0x0
514 01000000 0 00000000 515 0x1000000 0x0 0x0
515 0 00100000>; 516 0x0 0x100000>;
516 }; 517 };
517 }; 518 };
518}; 519};
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 79385bcd5c5f..7f9b999843ce 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -13,7 +13,7 @@
13 13
14/ { 14/ {
15 model = "MPC8641HPCN"; 15 model = "MPC8641HPCN";
16 compatible = "mpc86xx"; 16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index daf9433e906b..765e43c997da 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -2,6 +2,7 @@
2 * MPC866 ADS Device Tree Source 2 * MPC866 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2008 Freescale Semiconductor, Inc.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -9,6 +10,7 @@
9 * option) any later version. 10 * option) any later version.
10 */ 11 */
11 12
13/dts-v1/;
12 14
13/ { 15/ {
14 model = "MPC866ADS"; 16 model = "MPC866ADS";
@@ -22,37 +24,37 @@
22 24
23 PowerPC,866@0 { 25 PowerPC,866@0 {
24 device_type = "cpu"; 26 device_type = "cpu";
25 reg = <0>; 27 reg = <0x0>;
26 d-cache-line-size = <10>; // 16 bytes 28 d-cache-line-size = <16>; // 16 bytes
27 i-cache-line-size = <10>; // 16 bytes 29 i-cache-line-size = <16>; // 16 bytes
28 d-cache-size = <2000>; // L1, 8K 30 d-cache-size = <0x2000>; // L1, 8K
29 i-cache-size = <4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; 32 timebase-frequency = <0>;
31 bus-frequency = <0>; 33 bus-frequency = <0>;
32 clock-frequency = <0>; 34 clock-frequency = <0>;
33 interrupts = <f 2>; // decrementer interrupt 35 interrupts = <15 2>; // decrementer interrupt
34 interrupt-parent = <&PIC>; 36 interrupt-parent = <&PIC>;
35 }; 37 };
36 }; 38 };
37 39
38 memory { 40 memory {
39 device_type = "memory"; 41 device_type = "memory";
40 reg = <00000000 800000>; 42 reg = <0x0 0x800000>;
41 }; 43 };
42 44
43 localbus@ff000100 { 45 localbus@ff000100 {
44 compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus"; 46 compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
45 #address-cells = <2>; 47 #address-cells = <2>;
46 #size-cells = <1>; 48 #size-cells = <1>;
47 reg = <ff000100 40>; 49 reg = <0xff000100 0x40>;
48 50
49 ranges = < 51 ranges = <
50 1 0 ff080000 00008000 52 0x1 0x0 0xff080000 0x8000
51 5 0 ff0a0000 00008000 53 0x5 0x0 0xff0a0000 0x8000
52 >; 54 >;
53 55
54 board-control@1,0 { 56 board-control@1,0 {
55 reg = <1 0 20 5 300 4>; 57 reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
56 compatible = "fsl,mpc866ads-bcsr"; 58 compatible = "fsl,mpc866ads-bcsr";
57 }; 59 };
58 }; 60 };
@@ -61,17 +63,17 @@
61 #address-cells = <1>; 63 #address-cells = <1>;
62 #size-cells = <1>; 64 #size-cells = <1>;
63 device_type = "soc"; 65 device_type = "soc";
64 ranges = <0 ff000000 00100000>; 66 ranges = <0x0 0xff000000 0x100000>;
65 reg = <ff000000 00000200>; 67 reg = <0xff000000 0x200>;
66 bus-frequency = <0>; 68 bus-frequency = <0>;
67 69
68 mdio@e00 { 70 mdio@e00 {
69 compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio"; 71 compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
70 reg = <e00 188>; 72 reg = <0xe00 0x188>;
71 #address-cells = <1>; 73 #address-cells = <1>;
72 #size-cells = <0>; 74 #size-cells = <0>;
73 PHY: ethernet-phy@f { 75 PHY: ethernet-phy@f {
74 reg = <f>; 76 reg = <0xf>;
75 device_type = "ethernet-phy"; 77 device_type = "ethernet-phy";
76 }; 78 };
77 }; 79 };
@@ -80,7 +82,7 @@
80 device_type = "network"; 82 device_type = "network";
81 compatible = "fsl,mpc866-fec-enet", 83 compatible = "fsl,mpc866-fec-enet",
82 "fsl,pq1-fec-enet"; 84 "fsl,pq1-fec-enet";
83 reg = <e00 188>; 85 reg = <0xe00 0x188>;
84 local-mac-address = [ 00 00 00 00 00 00 ]; 86 local-mac-address = [ 00 00 00 00 00 00 ];
85 interrupts = <3 1>; 87 interrupts = <3 1>;
86 interrupt-parent = <&PIC>; 88 interrupt-parent = <&PIC>;
@@ -91,7 +93,7 @@
91 PIC: pic@0 { 93 PIC: pic@0 {
92 interrupt-controller; 94 interrupt-controller;
93 #interrupt-cells = <2>; 95 #interrupt-cells = <2>;
94 reg = <0 24>; 96 reg = <0x0 0x24>;
95 compatible = "fsl,mpc866-pic", "fsl,pq1-pic"; 97 compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
96 }; 98 };
97 99
@@ -100,7 +102,7 @@
100 #size-cells = <1>; 102 #size-cells = <1>;
101 compatible = "fsl,mpc866-cpm", "fsl,cpm1"; 103 compatible = "fsl,mpc866-cpm", "fsl,cpm1";
102 ranges; 104 ranges;
103 reg = <9c0 40>; 105 reg = <0x9c0 0x40>;
104 brg-frequency = <0>; 106 brg-frequency = <0>;
105 interrupts = <0 2>; // cpm error interrupt 107 interrupts = <0 2>; // cpm error interrupt
106 interrupt-parent = <&CPM_PIC>; 108 interrupt-parent = <&CPM_PIC>;
@@ -108,11 +110,11 @@
108 muram@2000 { 110 muram@2000 {
109 #address-cells = <1>; 111 #address-cells = <1>;
110 #size-cells = <1>; 112 #size-cells = <1>;
111 ranges = <0 2000 2000>; 113 ranges = <0x0 0x2000 0x2000>;
112 114
113 data@0 { 115 data@0 {
114 compatible = "fsl,cpm-muram-data"; 116 compatible = "fsl,cpm-muram-data";
115 reg = <0 1c00>; 117 reg = <0x0 0x1c00>;
116 }; 118 };
117 }; 119 };
118 120
@@ -120,7 +122,7 @@
120 compatible = "fsl,mpc866-brg", 122 compatible = "fsl,mpc866-brg",
121 "fsl,cpm1-brg", 123 "fsl,cpm1-brg",
122 "fsl,cpm-brg"; 124 "fsl,cpm-brg";
123 reg = <9f0 10>; 125 reg = <0x9f0 0x10>;
124 clock-frequency = <0>; 126 clock-frequency = <0>;
125 }; 127 };
126 128
@@ -130,7 +132,7 @@
130 #interrupt-cells = <1>; 132 #interrupt-cells = <1>;
131 interrupts = <5 2 0 2>; 133 interrupts = <5 2 0 2>;
132 interrupt-parent = <&PIC>; 134 interrupt-parent = <&PIC>;
133 reg = <930 20>; 135 reg = <0x930 0x20>;
134 compatible = "fsl,mpc866-cpm-pic", 136 compatible = "fsl,mpc866-cpm-pic",
135 "fsl,cpm1-pic"; 137 "fsl,cpm1-pic";
136 }; 138 };
@@ -140,31 +142,31 @@
140 device_type = "serial"; 142 device_type = "serial";
141 compatible = "fsl,mpc866-smc-uart", 143 compatible = "fsl,mpc866-smc-uart",
142 "fsl,cpm1-smc-uart"; 144 "fsl,cpm1-smc-uart";
143 reg = <a80 10 3e80 40>; 145 reg = <0xa80 0x10 0x3e80 0x40>;
144 interrupts = <4>; 146 interrupts = <4>;
145 interrupt-parent = <&CPM_PIC>; 147 interrupt-parent = <&CPM_PIC>;
146 fsl,cpm-brg = <1>; 148 fsl,cpm-brg = <1>;
147 fsl,cpm-command = <0090>; 149 fsl,cpm-command = <0x90>;
148 }; 150 };
149 151
150 serial@a90 { 152 serial@a90 {
151 device_type = "serial"; 153 device_type = "serial";
152 compatible = "fsl,mpc866-smc-uart", 154 compatible = "fsl,mpc866-smc-uart",
153 "fsl,cpm1-smc-uart"; 155 "fsl,cpm1-smc-uart";
154 reg = <a90 10 3f80 40>; 156 reg = <0xa90 0x10 0x3f80 0x40>;
155 interrupts = <3>; 157 interrupts = <3>;
156 interrupt-parent = <&CPM_PIC>; 158 interrupt-parent = <&CPM_PIC>;
157 fsl,cpm-brg = <2>; 159 fsl,cpm-brg = <2>;
158 fsl,cpm-command = <00d0>; 160 fsl,cpm-command = <0xd0>;
159 }; 161 };
160 162
161 ethernet@a00 { 163 ethernet@a00 {
162 device_type = "network"; 164 device_type = "network";
163 compatible = "fsl,mpc866-scc-enet", 165 compatible = "fsl,mpc866-scc-enet",
164 "fsl,cpm1-scc-enet"; 166 "fsl,cpm1-scc-enet";
165 reg = <a00 18 3c00 100>; 167 reg = <0xa00 0x18 0x3c00 0x100>;
166 local-mac-address = [ 00 00 00 00 00 00 ]; 168 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <1e>; 169 interrupts = <30>;
168 interrupt-parent = <&CPM_PIC>; 170 interrupt-parent = <&CPM_PIC>;
169 fsl,cpm-command = <0000>; 171 fsl,cpm-command = <0000>;
170 linux,network-index = <1>; 172 linux,network-index = <1>;
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index d84a012c2aaf..9895043722b9 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -2,7 +2,7 @@
2 * MPC885 ADS Device Tree Source 2 * MPC885 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2007 Freescale Semiconductor, Inc. 5 * Copyright 2007,2008 Freescale Semiconductor, Inc.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -10,6 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
13 14
14/ { 15/ {
15 model = "MPC885ADS"; 16 model = "MPC885ADS";
@@ -23,45 +24,45 @@
23 24
24 PowerPC,885@0 { 25 PowerPC,885@0 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 reg = <0>; 27 reg = <0x0>;
27 d-cache-line-size = <d#16>; 28 d-cache-line-size = <16>;
28 i-cache-line-size = <d#16>; 29 i-cache-line-size = <16>;
29 d-cache-size = <d#8192>; 30 d-cache-size = <8192>;
30 i-cache-size = <d#8192>; 31 i-cache-size = <8192>;
31 timebase-frequency = <0>; 32 timebase-frequency = <0>;
32 bus-frequency = <0>; 33 bus-frequency = <0>;
33 clock-frequency = <0>; 34 clock-frequency = <0>;
34 interrupts = <f 2>; // decrementer interrupt 35 interrupts = <15 2>; // decrementer interrupt
35 interrupt-parent = <&PIC>; 36 interrupt-parent = <&PIC>;
36 }; 37 };
37 }; 38 };
38 39
39 memory { 40 memory {
40 device_type = "memory"; 41 device_type = "memory";
41 reg = <0 0>; 42 reg = <0x0 0x0>;
42 }; 43 };
43 44
44 localbus@ff000100 { 45 localbus@ff000100 {
45 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; 46 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
46 #address-cells = <2>; 47 #address-cells = <2>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 reg = <ff000100 40>; 49 reg = <0xff000100 0x40>;
49 50
50 ranges = < 51 ranges = <
51 0 0 fe000000 00800000 52 0x0 0x0 0xfe000000 0x800000
52 1 0 ff080000 00008000 53 0x1 0x0 0xff080000 0x8000
53 5 0 ff0a0000 00008000 54 0x5 0x0 0xff0a0000 0x8000
54 >; 55 >;
55 56
56 flash@0,0 { 57 flash@0,0 {
57 compatible = "jedec-flash"; 58 compatible = "jedec-flash";
58 reg = <0 0 800000>; 59 reg = <0x0 0x0 0x800000>;
59 bank-width = <4>; 60 bank-width = <4>;
60 device-width = <1>; 61 device-width = <1>;
61 }; 62 };
62 63
63 board-control@1,0 { 64 board-control@1,0 {
64 reg = <1 0 20 5 300 4>; 65 reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
65 compatible = "fsl,mpc885ads-bcsr"; 66 compatible = "fsl,mpc885ads-bcsr";
66 }; 67 };
67 }; 68 };
@@ -71,30 +72,30 @@
71 #address-cells = <1>; 72 #address-cells = <1>;
72 #size-cells = <1>; 73 #size-cells = <1>;
73 device_type = "soc"; 74 device_type = "soc";
74 ranges = <0 ff000000 00004000>; 75 ranges = <0x0 0xff000000 0x4000>;
75 bus-frequency = <0>; 76 bus-frequency = <0>;
76 77
77 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 78 // Temporary -- will go away once kernel uses ranges for get_immrbase().
78 reg = <ff000000 4000>; 79 reg = <0xff000000 0x4000>;
79 80
80 mdio@e00 { 81 mdio@e00 {
81 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; 82 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
82 reg = <e00 188>; 83 reg = <0xe00 0x188>;
83 #address-cells = <1>; 84 #address-cells = <1>;
84 #size-cells = <0>; 85 #size-cells = <0>;
85 86
86 PHY0: ethernet-phy@0 { 87 PHY0: ethernet-phy@0 {
87 reg = <0>; 88 reg = <0x0>;
88 device_type = "ethernet-phy"; 89 device_type = "ethernet-phy";
89 }; 90 };
90 91
91 PHY1: ethernet-phy@1 { 92 PHY1: ethernet-phy@1 {
92 reg = <1>; 93 reg = <0x1>;
93 device_type = "ethernet-phy"; 94 device_type = "ethernet-phy";
94 }; 95 };
95 96
96 PHY2: ethernet-phy@2 { 97 PHY2: ethernet-phy@2 {
97 reg = <2>; 98 reg = <0x2>;
98 device_type = "ethernet-phy"; 99 device_type = "ethernet-phy";
99 }; 100 };
100 }; 101 };
@@ -103,7 +104,7 @@
103 device_type = "network"; 104 device_type = "network";
104 compatible = "fsl,mpc885-fec-enet", 105 compatible = "fsl,mpc885-fec-enet",
105 "fsl,pq1-fec-enet"; 106 "fsl,pq1-fec-enet";
106 reg = <e00 188>; 107 reg = <0xe00 0x188>;
107 local-mac-address = [ 00 00 00 00 00 00 ]; 108 local-mac-address = [ 00 00 00 00 00 00 ];
108 interrupts = <3 1>; 109 interrupts = <3 1>;
109 interrupt-parent = <&PIC>; 110 interrupt-parent = <&PIC>;
@@ -115,7 +116,7 @@
115 device_type = "network"; 116 device_type = "network";
116 compatible = "fsl,mpc885-fec-enet", 117 compatible = "fsl,mpc885-fec-enet",
117 "fsl,pq1-fec-enet"; 118 "fsl,pq1-fec-enet";
118 reg = <1e00 188>; 119 reg = <0x1e00 0x188>;
119 local-mac-address = [ 00 00 00 00 00 00 ]; 120 local-mac-address = [ 00 00 00 00 00 00 ];
120 interrupts = <7 1>; 121 interrupts = <7 1>;
121 interrupt-parent = <&PIC>; 122 interrupt-parent = <&PIC>;
@@ -126,7 +127,7 @@
126 PIC: interrupt-controller@0 { 127 PIC: interrupt-controller@0 {
127 interrupt-controller; 128 interrupt-controller;
128 #interrupt-cells = <2>; 129 #interrupt-cells = <2>;
129 reg = <0 24>; 130 reg = <0x0 0x24>;
130 compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; 131 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
131 }; 132 };
132 133
@@ -136,29 +137,29 @@
136 #size-cells = <2>; 137 #size-cells = <2>;
137 compatible = "fsl,pq-pcmcia"; 138 compatible = "fsl,pq-pcmcia";
138 device_type = "pcmcia"; 139 device_type = "pcmcia";
139 reg = <80 80>; 140 reg = <0x80 0x80>;
140 interrupt-parent = <&PIC>; 141 interrupt-parent = <&PIC>;
141 interrupts = <d 1>; 142 interrupts = <13 1>;
142 }; 143 };
143 144
144 cpm@9c0 { 145 cpm@9c0 {
145 #address-cells = <1>; 146 #address-cells = <1>;
146 #size-cells = <1>; 147 #size-cells = <1>;
147 compatible = "fsl,mpc885-cpm", "fsl,cpm1"; 148 compatible = "fsl,mpc885-cpm", "fsl,cpm1";
148 command-proc = <9c0>; 149 command-proc = <0x9c0>;
149 interrupts = <0>; // cpm error interrupt 150 interrupts = <0>; // cpm error interrupt
150 interrupt-parent = <&CPM_PIC>; 151 interrupt-parent = <&CPM_PIC>;
151 reg = <9c0 40>; 152 reg = <0x9c0 0x40>;
152 ranges; 153 ranges;
153 154
154 muram@2000 { 155 muram@2000 {
155 #address-cells = <1>; 156 #address-cells = <1>;
156 #size-cells = <1>; 157 #size-cells = <1>;
157 ranges = <0 2000 2000>; 158 ranges = <0x0 0x2000 0x2000>;
158 159
159 data@0 { 160 data@0 {
160 compatible = "fsl,cpm-muram-data"; 161 compatible = "fsl,cpm-muram-data";
161 reg = <0 1c00>; 162 reg = <0x0 0x1c00>;
162 }; 163 };
163 }; 164 };
164 165
@@ -167,7 +168,7 @@
167 "fsl,cpm1-brg", 168 "fsl,cpm1-brg",
168 "fsl,cpm-brg"; 169 "fsl,cpm-brg";
169 clock-frequency = <0>; 170 clock-frequency = <0>;
170 reg = <9f0 10>; 171 reg = <0x9f0 0x10>;
171 }; 172 };
172 173
173 CPM_PIC: interrupt-controller@930 { 174 CPM_PIC: interrupt-controller@930 {
@@ -175,7 +176,7 @@
175 #interrupt-cells = <1>; 176 #interrupt-cells = <1>;
176 interrupts = <5 2 0 2>; 177 interrupts = <5 2 0 2>;
177 interrupt-parent = <&PIC>; 178 interrupt-parent = <&PIC>;
178 reg = <930 20>; 179 reg = <0x930 0x20>;
179 compatible = "fsl,mpc885-cpm-pic", 180 compatible = "fsl,mpc885-cpm-pic",
180 "fsl,cpm1-pic"; 181 "fsl,cpm1-pic";
181 }; 182 };
@@ -184,34 +185,34 @@
184 device_type = "serial"; 185 device_type = "serial";
185 compatible = "fsl,mpc885-smc-uart", 186 compatible = "fsl,mpc885-smc-uart",
186 "fsl,cpm1-smc-uart"; 187 "fsl,cpm1-smc-uart";
187 reg = <a80 10 3e80 40>; 188 reg = <0xa80 0x10 0x3e80 0x40>;
188 interrupts = <4>; 189 interrupts = <4>;
189 interrupt-parent = <&CPM_PIC>; 190 interrupt-parent = <&CPM_PIC>;
190 fsl,cpm-brg = <1>; 191 fsl,cpm-brg = <1>;
191 fsl,cpm-command = <0090>; 192 fsl,cpm-command = <0x90>;
192 }; 193 };
193 194
194 serial@a90 { 195 serial@a90 {
195 device_type = "serial"; 196 device_type = "serial";
196 compatible = "fsl,mpc885-smc-uart", 197 compatible = "fsl,mpc885-smc-uart",
197 "fsl,cpm1-smc-uart"; 198 "fsl,cpm1-smc-uart";
198 reg = <a90 10 3f80 40>; 199 reg = <0xa90 0x10 0x3f80 0x40>;
199 interrupts = <3>; 200 interrupts = <3>;
200 interrupt-parent = <&CPM_PIC>; 201 interrupt-parent = <&CPM_PIC>;
201 fsl,cpm-brg = <2>; 202 fsl,cpm-brg = <2>;
202 fsl,cpm-command = <00d0>; 203 fsl,cpm-command = <0xd0>;
203 }; 204 };
204 205
205 ethernet@a40 { 206 ethernet@a40 {
206 device_type = "network"; 207 device_type = "network";
207 compatible = "fsl,mpc885-scc-enet", 208 compatible = "fsl,mpc885-scc-enet",
208 "fsl,cpm1-scc-enet"; 209 "fsl,cpm1-scc-enet";
209 reg = <a40 18 3e00 100>; 210 reg = <0xa40 0x18 0x3e00 0x100>;
210 local-mac-address = [ 00 00 00 00 00 00 ]; 211 local-mac-address = [ 00 00 00 00 00 00 ];
211 interrupts = <1c>; 212 interrupts = <28>;
212 interrupt-parent = <&CPM_PIC>; 213 interrupt-parent = <&CPM_PIC>;
213 phy-handle = <&PHY2>; 214 phy-handle = <&PHY2>;
214 fsl,cpm-command = <0080>; 215 fsl,cpm-command = <0x80>;
215 linux,network-index = <2>; 216 linux,network-index = <2>;
216 }; 217 };
217 }; 218 };
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
index 2d564921897a..b2d61091b36d 100644
--- a/arch/powerpc/boot/dts/pq2fads.dts
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip. 2 * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007,2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "pq2fads"; 15 model = "pq2fads";
14 compatible = "fsl,pq2fads"; 16 compatible = "fsl,pq2fads";
@@ -21,11 +23,11 @@
21 23
22 cpu@0 { 24 cpu@0 {
23 device_type = "cpu"; 25 device_type = "cpu";
24 reg = <0>; 26 reg = <0x0>;
25 d-cache-line-size = <d#32>; 27 d-cache-line-size = <32>;
26 i-cache-line-size = <d#32>; 28 i-cache-line-size = <32>;
27 d-cache-size = <d#16384>; 29 d-cache-size = <16384>;
28 i-cache-size = <d#16384>; 30 i-cache-size = <16384>;
29 timebase-frequency = <0>; 31 timebase-frequency = <0>;
30 clock-frequency = <0>; 32 clock-frequency = <0>;
31 }; 33 };
@@ -33,7 +35,7 @@
33 35
34 memory { 36 memory {
35 device_type = "memory"; 37 device_type = "memory";
36 reg = <0 0>; 38 reg = <0x0 0x0>;
37 }; 39 };
38 40
39 localbus@f0010100 { 41 localbus@f0010100 {
@@ -41,67 +43,67 @@
41 "fsl,pq2-localbus"; 43 "fsl,pq2-localbus";
42 #address-cells = <2>; 44 #address-cells = <2>;
43 #size-cells = <1>; 45 #size-cells = <1>;
44 reg = <f0010100 60>; 46 reg = <0xf0010100 0x60>;
45 47
46 ranges = <0 0 fe000000 00800000 48 ranges = <0x0 0x0 0xfe000000 0x800000
47 1 0 f4500000 00008000 49 0x1 0x0 0xf4500000 0x8000
48 8 0 f8200000 00008000>; 50 0x8 0x0 0xf8200000 0x8000>;
49 51
50 flash@0,0 { 52 flash@0,0 {
51 compatible = "jedec-flash"; 53 compatible = "jedec-flash";
52 reg = <0 0 800000>; 54 reg = <0x0 0x0 0x800000>;
53 bank-width = <4>; 55 bank-width = <4>;
54 device-width = <1>; 56 device-width = <1>;
55 }; 57 };
56 58
57 bcsr@1,0 { 59 bcsr@1,0 {
58 reg = <1 0 20>; 60 reg = <0x1 0x0 0x20>;
59 compatible = "fsl,pq2fads-bcsr"; 61 compatible = "fsl,pq2fads-bcsr";
60 }; 62 };
61 63
62 PCI_PIC: pic@8,0 { 64 PCI_PIC: pic@8,0 {
63 #interrupt-cells = <1>; 65 #interrupt-cells = <1>;
64 interrupt-controller; 66 interrupt-controller;
65 reg = <8 0 8>; 67 reg = <0x8 0x0 0x8>;
66 compatible = "fsl,pq2ads-pci-pic"; 68 compatible = "fsl,pq2ads-pci-pic";
67 interrupt-parent = <&PIC>; 69 interrupt-parent = <&PIC>;
68 interrupts = <18 8>; 70 interrupts = <24 8>;
69 }; 71 };
70 }; 72 };
71 73
72 pci@f0010800 { 74 pci@f0010800 {
73 device_type = "pci"; 75 device_type = "pci";
74 reg = <f0010800 10c f00101ac 8 f00101c4 8>; 76 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
75 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; 77 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
76 #interrupt-cells = <1>; 78 #interrupt-cells = <1>;
77 #size-cells = <2>; 79 #size-cells = <2>;
78 #address-cells = <3>; 80 #address-cells = <3>;
79 clock-frequency = <d#66000000>; 81 clock-frequency = <66000000>;
80 interrupt-map-mask = <f800 0 0 7>; 82 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
81 interrupt-map = < 83 interrupt-map = <
82 /* IDSEL 0x16 */ 84 /* IDSEL 0x16 */
83 b000 0 0 1 &PCI_PIC 0 85 0xb000 0x0 0x0 0x1 &PCI_PIC 0
84 b000 0 0 2 &PCI_PIC 1 86 0xb000 0x0 0x0 0x2 &PCI_PIC 1
85 b000 0 0 3 &PCI_PIC 2 87 0xb000 0x0 0x0 0x3 &PCI_PIC 2
86 b000 0 0 4 &PCI_PIC 3 88 0xb000 0x0 0x0 0x4 &PCI_PIC 3
87 89
88 /* IDSEL 0x17 */ 90 /* IDSEL 0x17 */
89 b800 0 0 1 &PCI_PIC 4 91 0xb800 0x0 0x0 0x1 &PCI_PIC 4
90 b800 0 0 2 &PCI_PIC 5 92 0xb800 0x0 0x0 0x2 &PCI_PIC 5
91 b800 0 0 3 &PCI_PIC 6 93 0xb800 0x0 0x0 0x3 &PCI_PIC 6
92 b800 0 0 4 &PCI_PIC 7 94 0xb800 0x0 0x0 0x4 &PCI_PIC 7
93 95
94 /* IDSEL 0x18 */ 96 /* IDSEL 0x18 */
95 c000 0 0 1 &PCI_PIC 8 97 0xc000 0x0 0x0 0x1 &PCI_PIC 8
96 c000 0 0 2 &PCI_PIC 9 98 0xc000 0x0 0x0 0x2 &PCI_PIC 9
97 c000 0 0 3 &PCI_PIC a 99 0xc000 0x0 0x0 0x3 &PCI_PIC 10
98 c000 0 0 4 &PCI_PIC b>; 100 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
99 101
100 interrupt-parent = <&PIC>; 102 interrupt-parent = <&PIC>;
101 interrupts = <12 8>; 103 interrupts = <18 8>;
102 ranges = <42000000 0 80000000 80000000 0 20000000 104 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
103 02000000 0 a0000000 a0000000 0 20000000 105 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
104 01000000 0 00000000 f6000000 0 02000000>; 106 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
105 }; 107 };
106 108
107 soc@f0000000 { 109 soc@f0000000 {
@@ -109,27 +111,27 @@
109 #size-cells = <1>; 111 #size-cells = <1>;
110 device_type = "soc"; 112 device_type = "soc";
111 compatible = "fsl,mpc8280", "fsl,pq2-soc"; 113 compatible = "fsl,mpc8280", "fsl,pq2-soc";
112 ranges = <00000000 f0000000 00053000>; 114 ranges = <0x0 0xf0000000 0x53000>;
113 115
114 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 116 // Temporary -- will go away once kernel uses ranges for get_immrbase().
115 reg = <f0000000 00053000>; 117 reg = <0xf0000000 0x53000>;
116 118
117 cpm@119c0 { 119 cpm@119c0 {
118 #address-cells = <1>; 120 #address-cells = <1>;
119 #size-cells = <1>; 121 #size-cells = <1>;
120 #interrupt-cells = <2>; 122 #interrupt-cells = <2>;
121 compatible = "fsl,mpc8280-cpm", "fsl,cpm2"; 123 compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
122 reg = <119c0 30>; 124 reg = <0x119c0 0x30>;
123 ranges; 125 ranges;
124 126
125 muram@0 { 127 muram@0 {
126 #address-cells = <1>; 128 #address-cells = <1>;
127 #size-cells = <1>; 129 #size-cells = <1>;
128 ranges = <0 0 10000>; 130 ranges = <0x0 0x0 0x10000>;
129 131
130 data@0 { 132 data@0 {
131 compatible = "fsl,cpm-muram-data"; 133 compatible = "fsl,cpm-muram-data";
132 reg = <0 2000 9800 800>; 134 reg = <0x0 0x2000 0x9800 0x800>;
133 }; 135 };
134 }; 136 };
135 137
@@ -137,53 +139,53 @@
137 compatible = "fsl,mpc8280-brg", 139 compatible = "fsl,mpc8280-brg",
138 "fsl,cpm2-brg", 140 "fsl,cpm2-brg",
139 "fsl,cpm-brg"; 141 "fsl,cpm-brg";
140 reg = <119f0 10 115f0 10>; 142 reg = <0x119f0 0x10 0x115f0 0x10>;
141 }; 143 };
142 144
143 serial@11a00 { 145 serial@11a00 {
144 device_type = "serial"; 146 device_type = "serial";
145 compatible = "fsl,mpc8280-scc-uart", 147 compatible = "fsl,mpc8280-scc-uart",
146 "fsl,cpm2-scc-uart"; 148 "fsl,cpm2-scc-uart";
147 reg = <11a00 20 8000 100>; 149 reg = <0x11a00 0x20 0x8000 0x100>;
148 interrupts = <28 8>; 150 interrupts = <40 8>;
149 interrupt-parent = <&PIC>; 151 interrupt-parent = <&PIC>;
150 fsl,cpm-brg = <1>; 152 fsl,cpm-brg = <1>;
151 fsl,cpm-command = <00800000>; 153 fsl,cpm-command = <0x800000>;
152 }; 154 };
153 155
154 serial@11a20 { 156 serial@11a20 {
155 device_type = "serial"; 157 device_type = "serial";
156 compatible = "fsl,mpc8280-scc-uart", 158 compatible = "fsl,mpc8280-scc-uart",
157 "fsl,cpm2-scc-uart"; 159 "fsl,cpm2-scc-uart";
158 reg = <11a20 20 8100 100>; 160 reg = <0x11a20 0x20 0x8100 0x100>;
159 interrupts = <29 8>; 161 interrupts = <41 8>;
160 interrupt-parent = <&PIC>; 162 interrupt-parent = <&PIC>;
161 fsl,cpm-brg = <2>; 163 fsl,cpm-brg = <2>;
162 fsl,cpm-command = <04a00000>; 164 fsl,cpm-command = <0x4a00000>;
163 }; 165 };
164 166
165 ethernet@11320 { 167 ethernet@11320 {
166 device_type = "network"; 168 device_type = "network";
167 compatible = "fsl,mpc8280-fcc-enet", 169 compatible = "fsl,mpc8280-fcc-enet",
168 "fsl,cpm2-fcc-enet"; 170 "fsl,cpm2-fcc-enet";
169 reg = <11320 20 8500 100 113b0 1>; 171 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
170 interrupts = <21 8>; 172 interrupts = <33 8>;
171 interrupt-parent = <&PIC>; 173 interrupt-parent = <&PIC>;
172 phy-handle = <&PHY0>; 174 phy-handle = <&PHY0>;
173 linux,network-index = <0>; 175 linux,network-index = <0>;
174 fsl,cpm-command = <16200300>; 176 fsl,cpm-command = <0x16200300>;
175 }; 177 };
176 178
177 ethernet@11340 { 179 ethernet@11340 {
178 device_type = "network"; 180 device_type = "network";
179 compatible = "fsl,mpc8280-fcc-enet", 181 compatible = "fsl,mpc8280-fcc-enet",
180 "fsl,cpm2-fcc-enet"; 182 "fsl,cpm2-fcc-enet";
181 reg = <11340 20 8600 100 113d0 1>; 183 reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
182 interrupts = <22 8>; 184 interrupts = <34 8>;
183 interrupt-parent = <&PIC>; 185 interrupt-parent = <&PIC>;
184 phy-handle = <&PHY1>; 186 phy-handle = <&PHY1>;
185 linux,network-index = <1>; 187 linux,network-index = <1>;
186 fsl,cpm-command = <1a400300>; 188 fsl,cpm-command = <0x1a400300>;
187 local-mac-address = [00 e0 0c 00 79 01]; 189 local-mac-address = [00 e0 0c 00 79 01];
188 }; 190 };
189 191
@@ -194,21 +196,21 @@
194 "fsl,cpm2-mdio-bitbang"; 196 "fsl,cpm2-mdio-bitbang";
195 #address-cells = <1>; 197 #address-cells = <1>;
196 #size-cells = <0>; 198 #size-cells = <0>;
197 reg = <10d40 14>; 199 reg = <0x10d40 0x14>;
198 fsl,mdio-pin = <9>; 200 fsl,mdio-pin = <9>;
199 fsl,mdc-pin = <a>; 201 fsl,mdc-pin = <10>;
200 202
201 PHY0: ethernet-phy@0 { 203 PHY0: ethernet-phy@0 {
202 interrupt-parent = <&PIC>; 204 interrupt-parent = <&PIC>;
203 interrupts = <19 2>; 205 interrupts = <25 2>;
204 reg = <0>; 206 reg = <0x0>;
205 device_type = "ethernet-phy"; 207 device_type = "ethernet-phy";
206 }; 208 };
207 209
208 PHY1: ethernet-phy@1 { 210 PHY1: ethernet-phy@1 {
209 interrupt-parent = <&PIC>; 211 interrupt-parent = <&PIC>;
210 interrupts = <19 2>; 212 interrupts = <25 2>;
211 reg = <3>; 213 reg = <0x3>;
212 device_type = "ethernet-phy"; 214 device_type = "ethernet-phy";
213 }; 215 };
214 }; 216 };
@@ -218,17 +220,17 @@
218 #size-cells = <0>; 220 #size-cells = <0>;
219 compatible = "fsl,mpc8280-usb", 221 compatible = "fsl,mpc8280-usb",
220 "fsl,cpm2-usb"; 222 "fsl,cpm2-usb";
221 reg = <11b60 18 8b00 100>; 223 reg = <0x11b60 0x18 0x8b00 0x100>;
222 interrupt-parent = <&PIC>; 224 interrupt-parent = <&PIC>;
223 interrupts = <b 8>; 225 interrupts = <11 8>;
224 fsl,cpm-command = <2e600000>; 226 fsl,cpm-command = <0x2e600000>;
225 }; 227 };
226 }; 228 };
227 229
228 PIC: interrupt-controller@10c00 { 230 PIC: interrupt-controller@10c00 {
229 #interrupt-cells = <2>; 231 #interrupt-cells = <2>;
230 interrupt-controller; 232 interrupt-controller;
231 reg = <10c00 80>; 233 reg = <0x10c00 0x80>;
232 compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic"; 234 compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
233 }; 235 };
234 236
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
new file mode 100644
index 000000000000..3eebeec157b3
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -0,0 +1,352 @@
1/*
2 * SBC8641D Device Tree Source
3 *
4 * Copyright 2008 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/dts-v1/;
17
18/ {
19 model = "SBC8641D";
20 compatible = "wind,sbc8641";
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 ethernet3 = &enet3;
29 serial0 = &serial0;
30 serial1 = &serial1;
31 pci0 = &pci0;
32 pci1 = &pci1;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 PowerPC,8641@0 {
40 device_type = "cpu";
41 reg = <0>;
42 d-cache-line-size = <32>;
43 i-cache-line-size = <32>;
44 d-cache-size = <32768>; // L1
45 i-cache-size = <32768>; // L1
46 timebase-frequency = <0>; // From uboot
47 bus-frequency = <0>; // From uboot
48 clock-frequency = <0>; // From uboot
49 };
50 PowerPC,8641@1 {
51 device_type = "cpu";
52 reg = <1>;
53 d-cache-line-size = <32>;
54 i-cache-line-size = <32>;
55 d-cache-size = <32768>;
56 i-cache-size = <32768>;
57 timebase-frequency = <0>; // From uboot
58 bus-frequency = <0>; // From uboot
59 clock-frequency = <0>; // From uboot
60 };
61 };
62
63 memory {
64 device_type = "memory";
65 reg = <0x00000000 0x20000000>; // 512M at 0x0
66 };
67
68 localbus@f8005000 {
69 #address-cells = <2>;
70 #size-cells = <1>;
71 compatible = "fsl,mpc8641-localbus", "simple-bus";
72 reg = <0xf8005000 0x1000>;
73 interrupts = <19 2>;
74 interrupt-parent = <&mpic>;
75
76 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
77 1 0 0xf0000000 0x00010000 // 64KB EEPROM
78 2 0 0xf1000000 0x00100000 // EPLD (1MB)
79 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
80 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
81 6 0 0xf4000000 0x00100000 // LCD display (1MB)
82 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
83
84 flash@0,0 {
85 compatible = "cfi-flash";
86 reg = <0 0 0x01000000>;
87 bank-width = <2>;
88 device-width = <2>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 partition@0 {
92 label = "dtb";
93 reg = <0x00000000 0x00100000>;
94 read-only;
95 };
96 partition@300000 {
97 label = "kernel";
98 reg = <0x00100000 0x00400000>;
99 read-only;
100 };
101 partition@400000 {
102 label = "fs";
103 reg = <0x00500000 0x00a00000>;
104 };
105 partition@700000 {
106 label = "firmware";
107 reg = <0x00f00000 0x00100000>;
108 read-only;
109 };
110 };
111
112 epld@2,0 {
113 compatible = "wrs,epld-localbus";
114 #address-cells = <2>;
115 #size-cells = <1>;
116 reg = <2 0 0x100000>;
117 ranges = <0 0 5 0 1 // User switches
118 1 0 5 1 1 // Board ID/Rev
119 3 0 5 3 1>; // LEDs
120 };
121 };
122
123 soc@f8000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 device_type = "soc";
127 compatible = "simple-bus";
128 ranges = <0x00000000 0xf8000000 0x00100000>;
129 reg = <0xf8000000 0x00001000>; // CCSRBAR
130 bus-frequency = <0>;
131
132 i2c@3000 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 cell-index = <0>;
136 compatible = "fsl-i2c";
137 reg = <0x3000 0x100>;
138 interrupts = <43 2>;
139 interrupt-parent = <&mpic>;
140 dfsrr;
141 };
142
143 i2c@3100 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <1>;
147 compatible = "fsl-i2c";
148 reg = <0x3100 0x100>;
149 interrupts = <43 2>;
150 interrupt-parent = <&mpic>;
151 dfsrr;
152 };
153
154 mdio@24520 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,gianfar-mdio";
158 reg = <0x24520 0x20>;
159
160 phy0: ethernet-phy@1f {
161 interrupt-parent = <&mpic>;
162 interrupts = <10 1>;
163 reg = <0x1f>;
164 device_type = "ethernet-phy";
165 };
166 phy1: ethernet-phy@0 {
167 interrupt-parent = <&mpic>;
168 interrupts = <10 1>;
169 reg = <0>;
170 device_type = "ethernet-phy";
171 };
172 phy2: ethernet-phy@1 {
173 interrupt-parent = <&mpic>;
174 interrupts = <10 1>;
175 reg = <1>;
176 device_type = "ethernet-phy";
177 };
178 phy3: ethernet-phy@2 {
179 interrupt-parent = <&mpic>;
180 interrupts = <10 1>;
181 reg = <2>;
182 device_type = "ethernet-phy";
183 };
184 };
185
186 enet0: ethernet@24000 {
187 cell-index = <0>;
188 device_type = "network";
189 model = "TSEC";
190 compatible = "gianfar";
191 reg = <0x24000 0x1000>;
192 local-mac-address = [ 00 00 00 00 00 00 ];
193 interrupts = <29 2 30 2 34 2>;
194 interrupt-parent = <&mpic>;
195 phy-handle = <&phy0>;
196 phy-connection-type = "rgmii-id";
197 };
198
199 enet1: ethernet@25000 {
200 cell-index = <1>;
201 device_type = "network";
202 model = "TSEC";
203 compatible = "gianfar";
204 reg = <0x25000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <35 2 36 2 40 2>;
207 interrupt-parent = <&mpic>;
208 phy-handle = <&phy1>;
209 phy-connection-type = "rgmii-id";
210 };
211
212 enet2: ethernet@26000 {
213 cell-index = <2>;
214 device_type = "network";
215 model = "TSEC";
216 compatible = "gianfar";
217 reg = <0x26000 0x1000>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <31 2 32 2 33 2>;
220 interrupt-parent = <&mpic>;
221 phy-handle = <&phy2>;
222 phy-connection-type = "rgmii-id";
223 };
224
225 enet3: ethernet@27000 {
226 cell-index = <3>;
227 device_type = "network";
228 model = "TSEC";
229 compatible = "gianfar";
230 reg = <0x27000 0x1000>;
231 local-mac-address = [ 00 00 00 00 00 00 ];
232 interrupts = <37 2 38 2 39 2>;
233 interrupt-parent = <&mpic>;
234 phy-handle = <&phy3>;
235 phy-connection-type = "rgmii-id";
236 };
237
238 serial0: serial@4500 {
239 cell-index = <0>;
240 device_type = "serial";
241 compatible = "ns16550";
242 reg = <0x4500 0x100>;
243 clock-frequency = <0>;
244 interrupts = <42 2>;
245 interrupt-parent = <&mpic>;
246 };
247
248 serial1: serial@4600 {
249 cell-index = <1>;
250 device_type = "serial";
251 compatible = "ns16550";
252 reg = <0x4600 0x100>;
253 clock-frequency = <0>;
254 interrupts = <28 2>;
255 interrupt-parent = <&mpic>;
256 };
257
258 mpic: pic@40000 {
259 clock-frequency = <0>;
260 interrupt-controller;
261 #address-cells = <0>;
262 #interrupt-cells = <2>;
263 reg = <0x40000 0x40000>;
264 compatible = "chrp,open-pic";
265 device_type = "open-pic";
266 big-endian;
267 };
268
269 global-utilities@e0000 {
270 compatible = "fsl,mpc8641-guts";
271 reg = <0xe0000 0x1000>;
272 fsl,has-rstcr;
273 };
274 };
275
276 pci0: pcie@f8008000 {
277 cell-index = <0>;
278 compatible = "fsl,mpc8641-pcie";
279 device_type = "pci";
280 #interrupt-cells = <1>;
281 #size-cells = <2>;
282 #address-cells = <3>;
283 reg = <0xf8008000 0x1000>;
284 bus-range = <0x0 0xff>;
285 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
286 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
287 clock-frequency = <33333333>;
288 interrupt-parent = <&mpic>;
289 interrupts = <24 2>;
290 interrupt-map-mask = <0xff00 0 0 7>;
291 interrupt-map = <
292 /* IDSEL 0x0 */
293 0x0000 0 0 1 &mpic 0 1
294 0x0000 0 0 2 &mpic 1 1
295 0x0000 0 0 3 &mpic 2 1
296 0x0000 0 0 4 &mpic 3 1
297 >;
298
299 pcie@0 {
300 reg = <0 0 0 0 0>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 device_type = "pci";
304 ranges = <0x02000000 0x0 0x80000000
305 0x02000000 0x0 0x80000000
306 0x0 0x20000000
307
308 0x01000000 0x0 0x00000000
309 0x01000000 0x0 0x00000000
310 0x0 0x00100000>;
311 };
312
313 };
314
315 pci1: pcie@f8009000 {
316 cell-index = <1>;
317 compatible = "fsl,mpc8641-pcie";
318 device_type = "pci";
319 #interrupt-cells = <1>;
320 #size-cells = <2>;
321 #address-cells = <3>;
322 reg = <0xf8009000 0x1000>;
323 bus-range = <0 0xff>;
324 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
325 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
326 clock-frequency = <33333333>;
327 interrupt-parent = <&mpic>;
328 interrupts = <25 2>;
329 interrupt-map-mask = <0xf800 0 0 7>;
330 interrupt-map = <
331 /* IDSEL 0x0 */
332 0x0000 0 0 1 &mpic 4 1
333 0x0000 0 0 2 &mpic 5 1
334 0x0000 0 0 3 &mpic 6 1
335 0x0000 0 0 4 &mpic 7 1
336 >;
337
338 pcie@0 {
339 reg = <0 0 0 0 0>;
340 #size-cells = <2>;
341 #address-cells = <3>;
342 device_type = "pci";
343 ranges = <0x02000000 0x0 0xa0000000
344 0x02000000 0x0 0xa0000000
345 0x0 0x20000000
346
347 0x01000000 0x0 0x00000000
348 0x01000000 0x0 0x00000000
349 0x0 0x00100000>;
350 };
351 };
352};
diff --git a/arch/powerpc/boot/mpc52xx-psc.c b/arch/powerpc/boot/mpc52xx-psc.c
index 1074626e6a37..d4cb4e4e0938 100644
--- a/arch/powerpc/boot/mpc52xx-psc.c
+++ b/arch/powerpc/boot/mpc52xx-psc.c
@@ -51,14 +51,9 @@ static unsigned char psc_getc(void)
51 51
52int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp) 52int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
53{ 53{
54 int n;
55
56 /* Get the base address of the psc registers */ 54 /* Get the base address of the psc registers */
57 n = getprop(devp, "virtual-reg", &psc, sizeof(psc)); 55 if (dt_get_virtual_reg(devp, &psc, 1) < 1)
58 if (n != sizeof(psc)) { 56 return -1;
59 if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
60 return -1;
61 }
62 57
63 scdp->open = psc_open; 58 scdp->open = psc_open;
64 scdp->putc = psc_putc; 59 scdp->putc = psc_putc;
diff --git a/arch/powerpc/boot/ns16550.c b/arch/powerpc/boot/ns16550.c
index f8f1b2f31412..aef3bdc89160 100644
--- a/arch/powerpc/boot/ns16550.c
+++ b/arch/powerpc/boot/ns16550.c
@@ -55,15 +55,9 @@ static u8 ns16550_tstc(void)
55int ns16550_console_init(void *devp, struct serial_console_data *scdp) 55int ns16550_console_init(void *devp, struct serial_console_data *scdp)
56{ 56{
57 int n; 57 int n;
58 unsigned long reg_phys;
59 58
60 n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base)); 59 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1)
61 if (n != sizeof(reg_base)) { 60 return -1;
62 if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
63 return -1;
64
65 reg_base = (void *)reg_phys;
66 }
67 61
68 n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift)); 62 n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift));
69 if (n != sizeof(reg_shift)) 63 if (n != sizeof(reg_shift))
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index 4b0544b03c64..321e2f5afe71 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -95,6 +95,7 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
95int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr); 95int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
96int dt_is_compatible(void *node, const char *compat); 96int dt_is_compatible(void *node, const char *compat);
97void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize); 97void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
98int dt_get_virtual_reg(void *node, void **addr, int nres);
98 99
99static inline void *finddevice(const char *name) 100static inline void *finddevice(const char *name)
100{ 101{
diff --git a/arch/powerpc/configs/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
index 7a862a6e3be8..7d18440e398f 100644
--- a/arch/powerpc/configs/mpc8313_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc6
4# Mon Mar 24 08:48:14 2008 4# Fri Apr 11 11:10:09 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -196,6 +196,7 @@ CONFIG_PREEMPT_NONE=y
196# CONFIG_PREEMPT is not set 196# CONFIG_PREEMPT is not set
197CONFIG_BINFMT_ELF=y 197CONFIG_BINFMT_ELF=y
198# CONFIG_BINFMT_MISC is not set 198# CONFIG_BINFMT_MISC is not set
199CONFIG_FORCE_MAX_ZONEORDER=11
199# CONFIG_IOMMU_HELPER is not set 200# CONFIG_IOMMU_HELPER is not set
200CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 201CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
201CONFIG_ARCH_HAS_WALK_MEMORY=y 202CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -360,7 +361,7 @@ CONFIG_MTD=y
360CONFIG_MTD_PARTITIONS=y 361CONFIG_MTD_PARTITIONS=y
361# CONFIG_MTD_REDBOOT_PARTS is not set 362# CONFIG_MTD_REDBOOT_PARTS is not set
362# CONFIG_MTD_CMDLINE_PARTS is not set 363# CONFIG_MTD_CMDLINE_PARTS is not set
363# CONFIG_MTD_OF_PARTS is not set 364CONFIG_MTD_OF_PARTS=y
364 365
365# 366#
366# User Modules And Translation Layers 367# User Modules And Translation Layers
@@ -436,7 +437,7 @@ CONFIG_MTD_NAND_IDS=y
436# CONFIG_MTD_NAND_NANDSIM is not set 437# CONFIG_MTD_NAND_NANDSIM is not set
437# CONFIG_MTD_NAND_PLATFORM is not set 438# CONFIG_MTD_NAND_PLATFORM is not set
438# CONFIG_MTD_ALAUDA is not set 439# CONFIG_MTD_ALAUDA is not set
439# CONFIG_MTD_NAND_FSL_ELBC is not set 440CONFIG_MTD_NAND_FSL_ELBC=y
440# CONFIG_MTD_ONENAND is not set 441# CONFIG_MTD_ONENAND is not set
441 442
442# 443#
@@ -1293,6 +1294,7 @@ CONFIG_PLIST=y
1293CONFIG_HAS_IOMEM=y 1294CONFIG_HAS_IOMEM=y
1294CONFIG_HAS_IOPORT=y 1295CONFIG_HAS_IOPORT=y
1295CONFIG_HAS_DMA=y 1296CONFIG_HAS_DMA=y
1297CONFIG_HAVE_LMB=y
1296 1298
1297# 1299#
1298# Kernel hacking 1300# Kernel hacking
diff --git a/arch/powerpc/configs/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
index 1f57456dd81e..1f57456dd81e 100644
--- a/arch/powerpc/configs/mpc8315_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
diff --git a/arch/powerpc/configs/mpc832x_mds_defconfig b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig
index 50cceda8994f..50cceda8994f 100644
--- a/arch/powerpc/configs/mpc832x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc832x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc832x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
index ac913025713e..ac913025713e 100644
--- a/arch/powerpc/configs/mpc832x_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
diff --git a/arch/powerpc/configs/mpc834x_itx_defconfig b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig
index e1de399a7bdd..e1de399a7bdd 100644
--- a/arch/powerpc/configs/mpc834x_itx_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_itx_defconfig
diff --git a/arch/powerpc/configs/mpc834x_itxgp_defconfig b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
index b4e39cf82a8c..b4e39cf82a8c 100644
--- a/arch/powerpc/configs/mpc834x_itxgp_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
diff --git a/arch/powerpc/configs/mpc834x_mds_defconfig b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig
index b4e82c0e2be7..b4e82c0e2be7 100644
--- a/arch/powerpc/configs/mpc834x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc834x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc836x_mds_defconfig b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
index d50a96eddcdc..d50a96eddcdc 100644
--- a/arch/powerpc/configs/mpc836x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc837x_mds_defconfig b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig
index f377cde785b0..f377cde785b0 100644
--- a/arch/powerpc/configs/mpc837x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc837x_mds_defconfig
diff --git a/arch/powerpc/configs/mpc837x_rdb_defconfig b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
index a6331769d88f..a6331769d88f 100644
--- a/arch/powerpc/configs/mpc837x_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
diff --git a/arch/powerpc/configs/sbc834x_defconfig b/arch/powerpc/configs/83xx/sbc834x_defconfig
index 1f1518229f6d..1f1518229f6d 100644
--- a/arch/powerpc/configs/sbc834x_defconfig
+++ b/arch/powerpc/configs/83xx/sbc834x_defconfig
diff --git a/arch/powerpc/configs/ksi8560_defconfig b/arch/powerpc/configs/85xx/ksi8560_defconfig
index 2d0debcefdbf..2d0debcefdbf 100644
--- a/arch/powerpc/configs/ksi8560_defconfig
+++ b/arch/powerpc/configs/85xx/ksi8560_defconfig
diff --git a/arch/powerpc/configs/mpc8540_ads_defconfig b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
index b998539da86e..b998539da86e 100644
--- a/arch/powerpc/configs/mpc8540_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
diff --git a/arch/powerpc/configs/mpc8544_ds_defconfig b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig
index 418bcdb5f919..a9f113b243ae 100644
--- a/arch/powerpc/configs/mpc8544_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8544_ds_defconfig
@@ -162,6 +162,7 @@ CONFIG_MPC85xx=y
162# CONFIG_MPC85xx_CDS is not set 162# CONFIG_MPC85xx_CDS is not set
163# CONFIG_MPC85xx_MDS is not set 163# CONFIG_MPC85xx_MDS is not set
164CONFIG_MPC85xx_DS=y 164CONFIG_MPC85xx_DS=y
165# CONFIG_KSI8560 is not set
165# CONFIG_STX_GP3 is not set 166# CONFIG_STX_GP3 is not set
166# CONFIG_TQM8540 is not set 167# CONFIG_TQM8540 is not set
167# CONFIG_TQM8541 is not set 168# CONFIG_TQM8541 is not set
@@ -202,6 +203,7 @@ CONFIG_PREEMPT_NONE=y
202# CONFIG_PREEMPT is not set 203# CONFIG_PREEMPT is not set
203CONFIG_BINFMT_ELF=y 204CONFIG_BINFMT_ELF=y
204CONFIG_BINFMT_MISC=m 205CONFIG_BINFMT_MISC=m
206CONFIG_FORCE_MAX_ZONEORDER=11
205CONFIG_MATH_EMULATION=y 207CONFIG_MATH_EMULATION=y
206# CONFIG_IOMMU_HELPER is not set 208# CONFIG_IOMMU_HELPER is not set
207CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 209CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@@ -1255,7 +1257,19 @@ CONFIG_RTC_DRV_CMOS=y
1255# 1257#
1256# on-CPU RTC drivers 1258# on-CPU RTC drivers
1257# 1259#
1258# CONFIG_DMADEVICES is not set 1260CONFIG_DMADEVICES=y
1261
1262#
1263# DMA Devices
1264#
1265CONFIG_FSL_DMA=y
1266# CONFIG_FSL_DMA_SELFTEST is not set
1267CONFIG_DMA_ENGINE=y
1268
1269#
1270# DMA Clients
1271#
1272# CONFIG_NET_DMA is not set
1259 1273
1260# 1274#
1261# Userspace I/O 1275# Userspace I/O
@@ -1447,6 +1461,7 @@ CONFIG_PLIST=y
1447CONFIG_HAS_IOMEM=y 1461CONFIG_HAS_IOMEM=y
1448CONFIG_HAS_IOPORT=y 1462CONFIG_HAS_IOPORT=y
1449CONFIG_HAS_DMA=y 1463CONFIG_HAS_DMA=y
1464CONFIG_HAVE_LMB=y
1450 1465
1451# 1466#
1452# Kernel hacking 1467# Kernel hacking
diff --git a/arch/powerpc/configs/mpc8560_ads_defconfig b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
index 851ac9115617..851ac9115617 100644
--- a/arch/powerpc/configs/mpc8560_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
diff --git a/arch/powerpc/configs/mpc8568mds_defconfig b/arch/powerpc/configs/85xx/mpc8568mds_defconfig
index 2b866b385607..2b866b385607 100644
--- a/arch/powerpc/configs/mpc8568mds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8568mds_defconfig
diff --git a/arch/powerpc/configs/mpc8572_ds_defconfig b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
index 53aa6f3173a5..53aa6f3173a5 100644
--- a/arch/powerpc/configs/mpc8572_ds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8572_ds_defconfig
diff --git a/arch/powerpc/configs/mpc85xx_cds_defconfig b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
index a469fe918816..a469fe918816 100644
--- a/arch/powerpc/configs/mpc85xx_cds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
diff --git a/arch/powerpc/configs/sbc8548_defconfig b/arch/powerpc/configs/85xx/sbc8548_defconfig
index 67f67978c742..67f67978c742 100644
--- a/arch/powerpc/configs/sbc8548_defconfig
+++ b/arch/powerpc/configs/85xx/sbc8548_defconfig
diff --git a/arch/powerpc/configs/sbc8560_defconfig b/arch/powerpc/configs/85xx/sbc8560_defconfig
index fef605579e29..fef605579e29 100644
--- a/arch/powerpc/configs/sbc8560_defconfig
+++ b/arch/powerpc/configs/85xx/sbc8560_defconfig
diff --git a/arch/powerpc/configs/stx_gp3_defconfig b/arch/powerpc/configs/85xx/stx_gp3_defconfig
index 1d303c49bb0c..1d303c49bb0c 100644
--- a/arch/powerpc/configs/stx_gp3_defconfig
+++ b/arch/powerpc/configs/85xx/stx_gp3_defconfig
diff --git a/arch/powerpc/configs/tqm8540_defconfig b/arch/powerpc/configs/85xx/tqm8540_defconfig
index d39ee3b35bfc..d39ee3b35bfc 100644
--- a/arch/powerpc/configs/tqm8540_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8540_defconfig
diff --git a/arch/powerpc/configs/tqm8541_defconfig b/arch/powerpc/configs/85xx/tqm8541_defconfig
index cbf6ad2d71da..cbf6ad2d71da 100644
--- a/arch/powerpc/configs/tqm8541_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8541_defconfig
diff --git a/arch/powerpc/configs/tqm8555_defconfig b/arch/powerpc/configs/85xx/tqm8555_defconfig
index bbff962c8472..bbff962c8472 100644
--- a/arch/powerpc/configs/tqm8555_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8555_defconfig
diff --git a/arch/powerpc/configs/tqm8560_defconfig b/arch/powerpc/configs/85xx/tqm8560_defconfig
index 63c5ec8b6515..63c5ec8b6515 100644
--- a/arch/powerpc/configs/tqm8560_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8560_defconfig
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 029d2dab7deb..9e0dd8201691 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc9
4# Mon Mar 24 08:48:25 2008 4# Tue Apr 15 18:07:36 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -201,6 +201,7 @@ CONFIG_PREEMPT_NONE=y
201# CONFIG_PREEMPT is not set 201# CONFIG_PREEMPT is not set
202CONFIG_BINFMT_ELF=y 202CONFIG_BINFMT_ELF=y
203# CONFIG_BINFMT_MISC is not set 203# CONFIG_BINFMT_MISC is not set
204CONFIG_FORCE_MAX_ZONEORDER=11
204CONFIG_MATH_EMULATION=y 205CONFIG_MATH_EMULATION=y
205# CONFIG_IOMMU_HELPER is not set 206# CONFIG_IOMMU_HELPER is not set
206CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 207CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@@ -353,7 +354,90 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
353# CONFIG_FW_LOADER is not set 354# CONFIG_FW_LOADER is not set
354# CONFIG_SYS_HYPERVISOR is not set 355# CONFIG_SYS_HYPERVISOR is not set
355# CONFIG_CONNECTOR is not set 356# CONFIG_CONNECTOR is not set
356# CONFIG_MTD is not set 357CONFIG_MTD=y
358# CONFIG_MTD_DEBUG is not set
359# CONFIG_MTD_CONCAT is not set
360CONFIG_MTD_PARTITIONS=y
361# CONFIG_MTD_REDBOOT_PARTS is not set
362# CONFIG_MTD_CMDLINE_PARTS is not set
363CONFIG_MTD_OF_PARTS=y
364
365#
366# User Modules And Translation Layers
367#
368CONFIG_MTD_CHAR=y
369CONFIG_MTD_BLKDEVS=y
370CONFIG_MTD_BLOCK=y
371# CONFIG_FTL is not set
372# CONFIG_NFTL is not set
373# CONFIG_INFTL is not set
374# CONFIG_RFD_FTL is not set
375# CONFIG_SSFDC is not set
376# CONFIG_MTD_OOPS is not set
377
378#
379# RAM/ROM/Flash chip drivers
380#
381CONFIG_MTD_CFI=y
382# CONFIG_MTD_JEDECPROBE is not set
383CONFIG_MTD_GEN_PROBE=y
384# CONFIG_MTD_CFI_ADV_OPTIONS is not set
385CONFIG_MTD_MAP_BANK_WIDTH_1=y
386CONFIG_MTD_MAP_BANK_WIDTH_2=y
387CONFIG_MTD_MAP_BANK_WIDTH_4=y
388# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
389# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
390# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
391CONFIG_MTD_CFI_I1=y
392CONFIG_MTD_CFI_I2=y
393# CONFIG_MTD_CFI_I4 is not set
394# CONFIG_MTD_CFI_I8 is not set
395# CONFIG_MTD_CFI_INTELEXT is not set
396CONFIG_MTD_CFI_AMDSTD=y
397# CONFIG_MTD_CFI_STAA is not set
398CONFIG_MTD_CFI_UTIL=y
399# CONFIG_MTD_RAM is not set
400# CONFIG_MTD_ROM is not set
401# CONFIG_MTD_ABSENT is not set
402
403#
404# Mapping drivers for chip access
405#
406# CONFIG_MTD_COMPLEX_MAPPINGS is not set
407# CONFIG_MTD_PHYSMAP is not set
408CONFIG_MTD_PHYSMAP_OF=y
409# CONFIG_MTD_PLATRAM is not set
410
411#
412# Self-contained MTD device drivers
413#
414# CONFIG_MTD_SLRAM is not set
415# CONFIG_MTD_PHRAM is not set
416# CONFIG_MTD_MTDRAM is not set
417# CONFIG_MTD_BLOCK2MTD is not set
418
419#
420# Disk-On-Chip Device Drivers
421#
422# CONFIG_MTD_DOC2000 is not set
423# CONFIG_MTD_DOC2001 is not set
424# CONFIG_MTD_DOC2001PLUS is not set
425CONFIG_MTD_NAND=y
426CONFIG_MTD_NAND_VERIFY_WRITE=y
427# CONFIG_MTD_NAND_ECC_SMC is not set
428# CONFIG_MTD_NAND_MUSEUM_IDS is not set
429CONFIG_MTD_NAND_IDS=y
430# CONFIG_MTD_NAND_DISKONCHIP is not set
431# CONFIG_MTD_NAND_NANDSIM is not set
432# CONFIG_MTD_NAND_PLATFORM is not set
433# CONFIG_MTD_ALAUDA is not set
434CONFIG_MTD_NAND_FSL_ELBC=y
435# CONFIG_MTD_ONENAND is not set
436
437#
438# UBI - Unsorted block images
439#
440# CONFIG_MTD_UBI is not set
357CONFIG_OF_DEVICE=y 441CONFIG_OF_DEVICE=y
358# CONFIG_PARPORT is not set 442# CONFIG_PARPORT is not set
359CONFIG_BLK_DEV=y 443CONFIG_BLK_DEV=y
@@ -362,6 +446,7 @@ CONFIG_BLK_DEV=y
362CONFIG_BLK_DEV_LOOP=y 446CONFIG_BLK_DEV_LOOP=y
363# CONFIG_BLK_DEV_CRYPTOLOOP is not set 447# CONFIG_BLK_DEV_CRYPTOLOOP is not set
364# CONFIG_BLK_DEV_NBD is not set 448# CONFIG_BLK_DEV_NBD is not set
449# CONFIG_BLK_DEV_UB is not set
365CONFIG_BLK_DEV_RAM=y 450CONFIG_BLK_DEV_RAM=y
366CONFIG_BLK_DEV_RAM_COUNT=16 451CONFIG_BLK_DEV_RAM_COUNT=16
367CONFIG_BLK_DEV_RAM_SIZE=32768 452CONFIG_BLK_DEV_RAM_SIZE=32768
@@ -469,6 +554,15 @@ CONFIG_NETDEV_10000=y
469# 554#
470# CONFIG_WLAN_PRE80211 is not set 555# CONFIG_WLAN_PRE80211 is not set
471# CONFIG_WLAN_80211 is not set 556# CONFIG_WLAN_80211 is not set
557
558#
559# USB Network Adapters
560#
561# CONFIG_USB_CATC is not set
562# CONFIG_USB_KAWETH is not set
563# CONFIG_USB_PEGASUS is not set
564# CONFIG_USB_RTL8150 is not set
565# CONFIG_USB_USBNET is not set
472# CONFIG_WAN is not set 566# CONFIG_WAN is not set
473# CONFIG_PPP is not set 567# CONFIG_PPP is not set
474# CONFIG_SLIP is not set 568# CONFIG_SLIP is not set
@@ -563,6 +657,7 @@ CONFIG_I2C_MPC=y
563# CONFIG_I2C_SIMTEC is not set 657# CONFIG_I2C_SIMTEC is not set
564# CONFIG_I2C_TAOS_EVM is not set 658# CONFIG_I2C_TAOS_EVM is not set
565# CONFIG_I2C_STUB is not set 659# CONFIG_I2C_STUB is not set
660# CONFIG_I2C_TINY_USB is not set
566 661
567# 662#
568# Miscellaneous I2C Chip support 663# Miscellaneous I2C Chip support
@@ -648,6 +743,11 @@ CONFIG_WATCHDOG=y
648CONFIG_83xx_WDT=y 743CONFIG_83xx_WDT=y
649 744
650# 745#
746# USB-based Watchdog Cards
747#
748# CONFIG_USBPCWATCHDOG is not set
749
750#
651# Sonics Silicon Backplane 751# Sonics Silicon Backplane
652# 752#
653CONFIG_SSB_POSSIBLE=y 753CONFIG_SSB_POSSIBLE=y
@@ -664,6 +764,7 @@ CONFIG_SSB_POSSIBLE=y
664# CONFIG_VIDEO_DEV is not set 764# CONFIG_VIDEO_DEV is not set
665# CONFIG_DVB_CORE is not set 765# CONFIG_DVB_CORE is not set
666CONFIG_DAB=y 766CONFIG_DAB=y
767# CONFIG_USB_DABUSB is not set
667 768
668# 769#
669# Graphics support 770# Graphics support
@@ -686,6 +787,14 @@ CONFIG_HID_SUPPORT=y
686CONFIG_HID=y 787CONFIG_HID=y
687# CONFIG_HID_DEBUG is not set 788# CONFIG_HID_DEBUG is not set
688# CONFIG_HIDRAW is not set 789# CONFIG_HIDRAW is not set
790
791#
792# USB Input Devices
793#
794CONFIG_USB_HID=y
795# CONFIG_USB_HIDINPUT_POWERBOOK is not set
796# CONFIG_HID_FF is not set
797# CONFIG_USB_HIDDEV is not set
689CONFIG_USB_SUPPORT=y 798CONFIG_USB_SUPPORT=y
690CONFIG_USB_ARCH_HAS_HCD=y 799CONFIG_USB_ARCH_HAS_HCD=y
691# CONFIG_USB_ARCH_HAS_OHCI is not set 800# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -715,8 +824,55 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
715# CONFIG_USB_R8A66597_HCD is not set 824# CONFIG_USB_R8A66597_HCD is not set
716 825
717# 826#
827# USB Device Class drivers
828#
829# CONFIG_USB_ACM is not set
830# CONFIG_USB_PRINTER is not set
831
832#
718# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 833# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
719# 834#
835
836#
837# may also be needed; see USB_STORAGE Help for more information
838#
839# CONFIG_USB_STORAGE is not set
840# CONFIG_USB_LIBUSUAL is not set
841
842#
843# USB Imaging devices
844#
845# CONFIG_USB_MDC800 is not set
846# CONFIG_USB_MICROTEK is not set
847CONFIG_USB_MON=y
848
849#
850# USB port drivers
851#
852# CONFIG_USB_SERIAL is not set
853
854#
855# USB Miscellaneous drivers
856#
857# CONFIG_USB_EMI62 is not set
858# CONFIG_USB_EMI26 is not set
859# CONFIG_USB_ADUTUX is not set
860# CONFIG_USB_AUERSWALD is not set
861# CONFIG_USB_RIO500 is not set
862# CONFIG_USB_LEGOTOWER is not set
863# CONFIG_USB_LCD is not set
864# CONFIG_USB_BERRY_CHARGE is not set
865# CONFIG_USB_LED is not set
866# CONFIG_USB_CYPRESS_CY7C63 is not set
867# CONFIG_USB_CYTHERM is not set
868# CONFIG_USB_PHIDGET is not set
869# CONFIG_USB_IDMOUSE is not set
870# CONFIG_USB_FTDI_ELAN is not set
871# CONFIG_USB_APPLEDISPLAY is not set
872# CONFIG_USB_SISUSBVGA is not set
873# CONFIG_USB_LD is not set
874# CONFIG_USB_TRANCEVIBRATOR is not set
875# CONFIG_USB_IOWARRIOR is not set
720# CONFIG_USB_GADGET is not set 876# CONFIG_USB_GADGET is not set
721# CONFIG_MMC is not set 877# CONFIG_MMC is not set
722# CONFIG_MEMSTICK is not set 878# CONFIG_MEMSTICK is not set
@@ -792,6 +948,7 @@ CONFIG_TMPFS=y
792# CONFIG_BEFS_FS is not set 948# CONFIG_BEFS_FS is not set
793# CONFIG_BFS_FS is not set 949# CONFIG_BFS_FS is not set
794# CONFIG_EFS_FS is not set 950# CONFIG_EFS_FS is not set
951# CONFIG_JFFS2_FS is not set
795# CONFIG_CRAMFS is not set 952# CONFIG_CRAMFS is not set
796# CONFIG_VXFS_FS is not set 953# CONFIG_VXFS_FS is not set
797# CONFIG_MINIX_FS is not set 954# CONFIG_MINIX_FS is not set
@@ -862,6 +1019,7 @@ CONFIG_PLIST=y
862CONFIG_HAS_IOMEM=y 1019CONFIG_HAS_IOMEM=y
863CONFIG_HAS_IOPORT=y 1020CONFIG_HAS_IOPORT=y
864CONFIG_HAS_DMA=y 1021CONFIG_HAS_DMA=y
1022CONFIG_HAVE_LMB=y
865 1023
866# 1024#
867# Kernel hacking 1025# Kernel hacking
diff --git a/arch/powerpc/configs/sbc8641d_defconfig b/arch/powerpc/configs/sbc8641d_defconfig
new file mode 100644
index 000000000000..3180125aa6c4
--- /dev/null
+++ b/arch/powerpc/configs/sbc8641d_defconfig
@@ -0,0 +1,1342 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6
4# Thu Apr 10 18:03:25 2008
5#
6# CONFIG_PPC64 is not set
7
8#
9# Processor support
10#
11CONFIG_6xx=y
12# CONFIG_PPC_85xx is not set
13# CONFIG_PPC_8xx is not set
14# CONFIG_40x is not set
15# CONFIG_44x is not set
16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y
18CONFIG_ALTIVEC=y
19CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set
22CONFIG_SMP=y
23CONFIG_NR_CPUS=2
24CONFIG_PPC32=y
25CONFIG_WORD_SIZE=32
26CONFIG_PPC_MERGE=y
27CONFIG_MMU=y
28CONFIG_GENERIC_CMOS_UPDATE=y
29CONFIG_GENERIC_TIME=y
30CONFIG_GENERIC_TIME_VSYSCALL=y
31CONFIG_GENERIC_CLOCKEVENTS=y
32CONFIG_GENERIC_HARDIRQS=y
33# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
34CONFIG_IRQ_PER_CPU=y
35CONFIG_RWSEM_XCHGADD_ALGORITHM=y
36CONFIG_GENERIC_LOCKBREAK=y
37CONFIG_ARCH_HAS_ILOG2_U32=y
38CONFIG_GENERIC_HWEIGHT=y
39CONFIG_GENERIC_CALIBRATE_DELAY=y
40CONFIG_GENERIC_FIND_NEXT_BIT=y
41# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
42CONFIG_PPC=y
43CONFIG_EARLY_PRINTK=y
44CONFIG_GENERIC_NVRAM=y
45CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
46CONFIG_ARCH_MAY_HAVE_PC_FDC=y
47CONFIG_PPC_OF=y
48CONFIG_OF=y
49CONFIG_PPC_UDBG_16550=y
50CONFIG_GENERIC_TBSYNC=y
51CONFIG_AUDIT_ARCH=y
52CONFIG_GENERIC_BUG=y
53CONFIG_DEFAULT_UIMAGE=y
54# CONFIG_PPC_DCR_NATIVE is not set
55# CONFIG_PPC_DCR_MMIO is not set
56CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
57
58#
59# General setup
60#
61CONFIG_EXPERIMENTAL=y
62CONFIG_LOCK_KERNEL=y
63CONFIG_INIT_ENV_ARG_LIMIT=32
64CONFIG_LOCALVERSION=""
65CONFIG_LOCALVERSION_AUTO=y
66CONFIG_SWAP=y
67CONFIG_SYSVIPC=y
68CONFIG_SYSVIPC_SYSCTL=y
69CONFIG_POSIX_MQUEUE=y
70CONFIG_BSD_PROCESS_ACCT=y
71CONFIG_BSD_PROCESS_ACCT_V3=y
72# CONFIG_TASKSTATS is not set
73# CONFIG_AUDIT is not set
74CONFIG_IKCONFIG=y
75CONFIG_IKCONFIG_PROC=y
76CONFIG_LOG_BUF_SHIFT=14
77# CONFIG_CGROUPS is not set
78CONFIG_GROUP_SCHED=y
79CONFIG_FAIR_GROUP_SCHED=y
80# CONFIG_RT_GROUP_SCHED is not set
81CONFIG_USER_SCHED=y
82# CONFIG_CGROUP_SCHED is not set
83CONFIG_SYSFS_DEPRECATED=y
84CONFIG_SYSFS_DEPRECATED_V2=y
85CONFIG_RELAY=y
86# CONFIG_NAMESPACES is not set
87CONFIG_BLK_DEV_INITRD=y
88CONFIG_INITRAMFS_SOURCE=""
89# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
90CONFIG_SYSCTL=y
91CONFIG_EMBEDDED=y
92CONFIG_SYSCTL_SYSCALL=y
93CONFIG_KALLSYMS=y
94# CONFIG_KALLSYMS_ALL is not set
95# CONFIG_KALLSYMS_EXTRA_PASS is not set
96CONFIG_HOTPLUG=y
97CONFIG_PRINTK=y
98CONFIG_BUG=y
99CONFIG_ELF_CORE=y
100CONFIG_COMPAT_BRK=y
101CONFIG_BASE_FULL=y
102CONFIG_FUTEX=y
103CONFIG_ANON_INODES=y
104CONFIG_EPOLL=y
105CONFIG_SIGNALFD=y
106CONFIG_TIMERFD=y
107CONFIG_EVENTFD=y
108CONFIG_SHMEM=y
109CONFIG_VM_EVENT_COUNTERS=y
110CONFIG_SLAB=y
111# CONFIG_SLUB is not set
112# CONFIG_SLOB is not set
113# CONFIG_PROFILING is not set
114# CONFIG_MARKERS is not set
115CONFIG_HAVE_OPROFILE=y
116# CONFIG_KPROBES is not set
117CONFIG_HAVE_KPROBES=y
118CONFIG_HAVE_KRETPROBES=y
119CONFIG_PROC_PAGE_MONITOR=y
120CONFIG_SLABINFO=y
121CONFIG_RT_MUTEXES=y
122# CONFIG_TINY_SHMEM is not set
123CONFIG_BASE_SMALL=0
124CONFIG_MODULES=y
125CONFIG_MODULE_UNLOAD=y
126# CONFIG_MODULE_FORCE_UNLOAD is not set
127# CONFIG_MODVERSIONS is not set
128# CONFIG_MODULE_SRCVERSION_ALL is not set
129CONFIG_KMOD=y
130CONFIG_STOP_MACHINE=y
131CONFIG_BLOCK=y
132# CONFIG_LBD is not set
133# CONFIG_BLK_DEV_IO_TRACE is not set
134# CONFIG_LSF is not set
135# CONFIG_BLK_DEV_BSG is not set
136
137#
138# IO Schedulers
139#
140CONFIG_IOSCHED_NOOP=y
141CONFIG_IOSCHED_AS=y
142CONFIG_IOSCHED_DEADLINE=y
143CONFIG_IOSCHED_CFQ=y
144# CONFIG_DEFAULT_AS is not set
145# CONFIG_DEFAULT_DEADLINE is not set
146CONFIG_DEFAULT_CFQ=y
147# CONFIG_DEFAULT_NOOP is not set
148CONFIG_DEFAULT_IOSCHED="cfq"
149CONFIG_CLASSIC_RCU=y
150
151#
152# Platform support
153#
154# CONFIG_PPC_MULTIPLATFORM is not set
155# CONFIG_PPC_82xx is not set
156# CONFIG_PPC_83xx is not set
157CONFIG_PPC_86xx=y
158# CONFIG_PPC_MPC512x is not set
159# CONFIG_PPC_MPC5121 is not set
160# CONFIG_PPC_CELL is not set
161# CONFIG_PPC_CELL_NATIVE is not set
162# CONFIG_PQ2ADS is not set
163# CONFIG_MPC8641_HPCN is not set
164CONFIG_SBC8641D=y
165# CONFIG_MPC8610_HPCD is not set
166CONFIG_MPC8641=y
167# CONFIG_IPIC is not set
168CONFIG_MPIC=y
169# CONFIG_MPIC_WEIRD is not set
170# CONFIG_PPC_I8259 is not set
171# CONFIG_PPC_RTAS is not set
172# CONFIG_MMIO_NVRAM is not set
173# CONFIG_PPC_MPC106 is not set
174# CONFIG_PPC_970_NAP is not set
175# CONFIG_PPC_INDIRECT_IO is not set
176# CONFIG_GENERIC_IOMAP is not set
177# CONFIG_CPU_FREQ is not set
178# CONFIG_FSL_ULI1575 is not set
179
180#
181# Kernel options
182#
183# CONFIG_HIGHMEM is not set
184CONFIG_TICK_ONESHOT=y
185# CONFIG_NO_HZ is not set
186CONFIG_HIGH_RES_TIMERS=y
187CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
188# CONFIG_HZ_100 is not set
189CONFIG_HZ_250=y
190# CONFIG_HZ_300 is not set
191# CONFIG_HZ_1000 is not set
192CONFIG_HZ=250
193# CONFIG_SCHED_HRTICK is not set
194# CONFIG_PREEMPT_NONE is not set
195# CONFIG_PREEMPT_VOLUNTARY is not set
196CONFIG_PREEMPT=y
197# CONFIG_PREEMPT_RCU is not set
198CONFIG_BINFMT_ELF=y
199CONFIG_BINFMT_MISC=m
200CONFIG_FORCE_MAX_ZONEORDER=11
201# CONFIG_IOMMU_HELPER is not set
202CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
203CONFIG_ARCH_HAS_WALK_MEMORY=y
204CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
205CONFIG_IRQ_ALL_CPUS=y
206CONFIG_ARCH_FLATMEM_ENABLE=y
207CONFIG_ARCH_POPULATES_NODE_MAP=y
208CONFIG_SELECT_MEMORY_MODEL=y
209CONFIG_FLATMEM_MANUAL=y
210# CONFIG_DISCONTIGMEM_MANUAL is not set
211# CONFIG_SPARSEMEM_MANUAL is not set
212CONFIG_FLATMEM=y
213CONFIG_FLAT_NODE_MEM_MAP=y
214# CONFIG_SPARSEMEM_STATIC is not set
215# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
216CONFIG_SPLIT_PTLOCK_CPUS=4
217# CONFIG_RESOURCES_64BIT is not set
218CONFIG_ZONE_DMA_FLAG=1
219CONFIG_BOUNCE=y
220CONFIG_VIRT_TO_BUS=y
221# CONFIG_PROC_DEVICETREE is not set
222# CONFIG_CMDLINE_BOOL is not set
223# CONFIG_PM is not set
224CONFIG_SECCOMP=y
225CONFIG_ISA_DMA_API=y
226
227#
228# Bus options
229#
230CONFIG_ZONE_DMA=y
231CONFIG_GENERIC_ISA_DMA=y
232CONFIG_PPC_INDIRECT_PCI=y
233CONFIG_FSL_SOC=y
234CONFIG_FSL_PCI=y
235CONFIG_PCI=y
236CONFIG_PCI_DOMAINS=y
237CONFIG_PCI_SYSCALL=y
238CONFIG_PCIEPORTBUS=y
239CONFIG_PCIEAER=y
240CONFIG_ARCH_SUPPORTS_MSI=y
241# CONFIG_PCI_MSI is not set
242CONFIG_PCI_LEGACY=y
243# CONFIG_PCI_DEBUG is not set
244# CONFIG_PCCARD is not set
245# CONFIG_HOTPLUG_PCI is not set
246
247#
248# Advanced setup
249#
250# CONFIG_ADVANCED_OPTIONS is not set
251
252#
253# Default settings for advanced configuration options are used
254#
255CONFIG_HIGHMEM_START=0xfe000000
256CONFIG_LOWMEM_SIZE=0x30000000
257CONFIG_KERNEL_START=0xc0000000
258CONFIG_TASK_SIZE=0xc0000000
259CONFIG_BOOT_LOAD=0x00800000
260
261#
262# Networking
263#
264CONFIG_NET=y
265
266#
267# Networking options
268#
269CONFIG_PACKET=y
270CONFIG_PACKET_MMAP=y
271CONFIG_UNIX=y
272CONFIG_XFRM=y
273CONFIG_XFRM_USER=m
274# CONFIG_XFRM_SUB_POLICY is not set
275# CONFIG_XFRM_MIGRATE is not set
276# CONFIG_XFRM_STATISTICS is not set
277CONFIG_NET_KEY=m
278# CONFIG_NET_KEY_MIGRATE is not set
279CONFIG_INET=y
280CONFIG_IP_MULTICAST=y
281CONFIG_IP_ADVANCED_ROUTER=y
282CONFIG_ASK_IP_FIB_HASH=y
283# CONFIG_IP_FIB_TRIE is not set
284CONFIG_IP_FIB_HASH=y
285CONFIG_IP_MULTIPLE_TABLES=y
286CONFIG_IP_ROUTE_MULTIPATH=y
287CONFIG_IP_ROUTE_VERBOSE=y
288CONFIG_IP_PNP=y
289CONFIG_IP_PNP_DHCP=y
290CONFIG_IP_PNP_BOOTP=y
291CONFIG_IP_PNP_RARP=y
292CONFIG_NET_IPIP=m
293CONFIG_NET_IPGRE=m
294CONFIG_NET_IPGRE_BROADCAST=y
295CONFIG_IP_MROUTE=y
296CONFIG_IP_PIMSM_V1=y
297CONFIG_IP_PIMSM_V2=y
298# CONFIG_ARPD is not set
299CONFIG_SYN_COOKIES=y
300CONFIG_INET_AH=m
301CONFIG_INET_ESP=m
302CONFIG_INET_IPCOMP=m
303CONFIG_INET_XFRM_TUNNEL=m
304CONFIG_INET_TUNNEL=m
305CONFIG_INET_XFRM_MODE_TRANSPORT=y
306CONFIG_INET_XFRM_MODE_TUNNEL=y
307CONFIG_INET_XFRM_MODE_BEET=y
308# CONFIG_INET_LRO is not set
309CONFIG_INET_DIAG=y
310CONFIG_INET_TCP_DIAG=y
311# CONFIG_TCP_CONG_ADVANCED is not set
312CONFIG_TCP_CONG_CUBIC=y
313CONFIG_DEFAULT_TCP_CONG="cubic"
314# CONFIG_TCP_MD5SIG is not set
315# CONFIG_IP_VS is not set
316CONFIG_IPV6=m
317# CONFIG_IPV6_PRIVACY is not set
318# CONFIG_IPV6_ROUTER_PREF is not set
319# CONFIG_IPV6_OPTIMISTIC_DAD is not set
320CONFIG_INET6_AH=m
321CONFIG_INET6_ESP=m
322CONFIG_INET6_IPCOMP=m
323# CONFIG_IPV6_MIP6 is not set
324CONFIG_INET6_XFRM_TUNNEL=m
325CONFIG_INET6_TUNNEL=m
326CONFIG_INET6_XFRM_MODE_TRANSPORT=m
327CONFIG_INET6_XFRM_MODE_TUNNEL=m
328CONFIG_INET6_XFRM_MODE_BEET=m
329# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
330CONFIG_IPV6_SIT=m
331CONFIG_IPV6_TUNNEL=m
332# CONFIG_IPV6_MULTIPLE_TABLES is not set
333# CONFIG_NETLABEL is not set
334# CONFIG_NETWORK_SECMARK is not set
335CONFIG_NETFILTER=y
336# CONFIG_NETFILTER_DEBUG is not set
337CONFIG_NETFILTER_ADVANCED=y
338CONFIG_BRIDGE_NETFILTER=y
339
340#
341# Core Netfilter Configuration
342#
343# CONFIG_NETFILTER_NETLINK_QUEUE is not set
344# CONFIG_NETFILTER_NETLINK_LOG is not set
345# CONFIG_NF_CONNTRACK is not set
346CONFIG_NETFILTER_XTABLES=m
347# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
348# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
349# CONFIG_NETFILTER_XT_TARGET_MARK is not set
350# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
351# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
352# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
353# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
354# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
355# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
356# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
357# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
358# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
359# CONFIG_NETFILTER_XT_MATCH_ESP is not set
360# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
361# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
362# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
363# CONFIG_NETFILTER_XT_MATCH_MAC is not set
364# CONFIG_NETFILTER_XT_MATCH_MARK is not set
365# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
366# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
367# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
368# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
369# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
370# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
371# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
372# CONFIG_NETFILTER_XT_MATCH_REALM is not set
373# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
374# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
375# CONFIG_NETFILTER_XT_MATCH_STRING is not set
376# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
377# CONFIG_NETFILTER_XT_MATCH_TIME is not set
378# CONFIG_NETFILTER_XT_MATCH_U32 is not set
379# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
380
381#
382# IP: Netfilter Configuration
383#
384CONFIG_IP_NF_QUEUE=m
385CONFIG_IP_NF_IPTABLES=m
386CONFIG_IP_NF_MATCH_RECENT=m
387CONFIG_IP_NF_MATCH_ECN=m
388# CONFIG_IP_NF_MATCH_AH is not set
389CONFIG_IP_NF_MATCH_TTL=m
390CONFIG_IP_NF_MATCH_ADDRTYPE=m
391CONFIG_IP_NF_FILTER=m
392CONFIG_IP_NF_TARGET_REJECT=m
393CONFIG_IP_NF_TARGET_LOG=m
394CONFIG_IP_NF_TARGET_ULOG=m
395CONFIG_IP_NF_MANGLE=m
396CONFIG_IP_NF_TARGET_ECN=m
397# CONFIG_IP_NF_TARGET_TTL is not set
398CONFIG_IP_NF_RAW=m
399CONFIG_IP_NF_ARPTABLES=m
400CONFIG_IP_NF_ARPFILTER=m
401CONFIG_IP_NF_ARP_MANGLE=m
402
403#
404# IPv6: Netfilter Configuration
405#
406CONFIG_IP6_NF_QUEUE=m
407CONFIG_IP6_NF_IPTABLES=m
408CONFIG_IP6_NF_MATCH_RT=m
409CONFIG_IP6_NF_MATCH_OPTS=m
410CONFIG_IP6_NF_MATCH_FRAG=m
411CONFIG_IP6_NF_MATCH_HL=m
412CONFIG_IP6_NF_MATCH_IPV6HEADER=m
413# CONFIG_IP6_NF_MATCH_AH is not set
414# CONFIG_IP6_NF_MATCH_MH is not set
415CONFIG_IP6_NF_MATCH_EUI64=m
416CONFIG_IP6_NF_FILTER=m
417CONFIG_IP6_NF_TARGET_LOG=m
418# CONFIG_IP6_NF_TARGET_REJECT is not set
419CONFIG_IP6_NF_MANGLE=m
420# CONFIG_IP6_NF_TARGET_HL is not set
421CONFIG_IP6_NF_RAW=m
422
423#
424# Bridge: Netfilter Configuration
425#
426# CONFIG_BRIDGE_NF_EBTABLES is not set
427# CONFIG_IP_DCCP is not set
428CONFIG_IP_SCTP=m
429# CONFIG_SCTP_DBG_MSG is not set
430# CONFIG_SCTP_DBG_OBJCNT is not set
431# CONFIG_SCTP_HMAC_NONE is not set
432# CONFIG_SCTP_HMAC_SHA1 is not set
433CONFIG_SCTP_HMAC_MD5=y
434CONFIG_TIPC=m
435# CONFIG_TIPC_ADVANCED is not set
436# CONFIG_TIPC_DEBUG is not set
437CONFIG_ATM=m
438CONFIG_ATM_CLIP=m
439# CONFIG_ATM_CLIP_NO_ICMP is not set
440CONFIG_ATM_LANE=m
441CONFIG_ATM_MPOA=m
442CONFIG_ATM_BR2684=m
443# CONFIG_ATM_BR2684_IPFILTER is not set
444CONFIG_BRIDGE=m
445CONFIG_VLAN_8021Q=m
446# CONFIG_DECNET is not set
447CONFIG_LLC=m
448# CONFIG_LLC2 is not set
449# CONFIG_IPX is not set
450# CONFIG_ATALK is not set
451# CONFIG_X25 is not set
452# CONFIG_LAPB is not set
453# CONFIG_ECONET is not set
454CONFIG_WAN_ROUTER=m
455CONFIG_NET_SCHED=y
456
457#
458# Queueing/Scheduling
459#
460CONFIG_NET_SCH_CBQ=m
461CONFIG_NET_SCH_HTB=m
462CONFIG_NET_SCH_HFSC=m
463CONFIG_NET_SCH_ATM=m
464CONFIG_NET_SCH_PRIO=m
465# CONFIG_NET_SCH_RR is not set
466CONFIG_NET_SCH_RED=m
467CONFIG_NET_SCH_SFQ=m
468CONFIG_NET_SCH_TEQL=m
469CONFIG_NET_SCH_TBF=m
470CONFIG_NET_SCH_GRED=m
471CONFIG_NET_SCH_DSMARK=m
472CONFIG_NET_SCH_NETEM=m
473
474#
475# Classification
476#
477CONFIG_NET_CLS=y
478# CONFIG_NET_CLS_BASIC is not set
479CONFIG_NET_CLS_TCINDEX=m
480CONFIG_NET_CLS_ROUTE4=m
481CONFIG_NET_CLS_ROUTE=y
482CONFIG_NET_CLS_FW=m
483CONFIG_NET_CLS_U32=m
484# CONFIG_CLS_U32_PERF is not set
485# CONFIG_CLS_U32_MARK is not set
486CONFIG_NET_CLS_RSVP=m
487CONFIG_NET_CLS_RSVP6=m
488# CONFIG_NET_CLS_FLOW is not set
489# CONFIG_NET_EMATCH is not set
490# CONFIG_NET_CLS_ACT is not set
491# CONFIG_NET_CLS_IND is not set
492CONFIG_NET_SCH_FIFO=y
493
494#
495# Network testing
496#
497CONFIG_NET_PKTGEN=m
498# CONFIG_HAMRADIO is not set
499# CONFIG_CAN is not set
500# CONFIG_IRDA is not set
501# CONFIG_BT is not set
502# CONFIG_AF_RXRPC is not set
503CONFIG_FIB_RULES=y
504
505#
506# Wireless
507#
508# CONFIG_CFG80211 is not set
509# CONFIG_WIRELESS_EXT is not set
510# CONFIG_MAC80211 is not set
511# CONFIG_IEEE80211 is not set
512# CONFIG_RFKILL is not set
513# CONFIG_NET_9P is not set
514
515#
516# Device Drivers
517#
518
519#
520# Generic Driver Options
521#
522CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
523CONFIG_STANDALONE=y
524CONFIG_PREVENT_FIRMWARE_BUILD=y
525# CONFIG_FW_LOADER is not set
526# CONFIG_DEBUG_DRIVER is not set
527# CONFIG_DEBUG_DEVRES is not set
528# CONFIG_SYS_HYPERVISOR is not set
529# CONFIG_CONNECTOR is not set
530CONFIG_MTD=y
531# CONFIG_MTD_DEBUG is not set
532CONFIG_MTD_CONCAT=y
533CONFIG_MTD_PARTITIONS=y
534# CONFIG_MTD_REDBOOT_PARTS is not set
535# CONFIG_MTD_CMDLINE_PARTS is not set
536# CONFIG_MTD_OF_PARTS is not set
537
538#
539# User Modules And Translation Layers
540#
541CONFIG_MTD_CHAR=y
542CONFIG_MTD_BLKDEVS=y
543CONFIG_MTD_BLOCK=y
544# CONFIG_FTL is not set
545# CONFIG_NFTL is not set
546# CONFIG_INFTL is not set
547# CONFIG_RFD_FTL is not set
548# CONFIG_SSFDC is not set
549# CONFIG_MTD_OOPS is not set
550
551#
552# RAM/ROM/Flash chip drivers
553#
554CONFIG_MTD_CFI=y
555# CONFIG_MTD_JEDECPROBE is not set
556CONFIG_MTD_GEN_PROBE=y
557CONFIG_MTD_CFI_ADV_OPTIONS=y
558# CONFIG_MTD_CFI_NOSWAP is not set
559# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
560CONFIG_MTD_CFI_LE_BYTE_SWAP=y
561# CONFIG_MTD_CFI_GEOMETRY is not set
562CONFIG_MTD_MAP_BANK_WIDTH_1=y
563CONFIG_MTD_MAP_BANK_WIDTH_2=y
564CONFIG_MTD_MAP_BANK_WIDTH_4=y
565# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
566# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
567# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
568CONFIG_MTD_CFI_I1=y
569CONFIG_MTD_CFI_I2=y
570# CONFIG_MTD_CFI_I4 is not set
571# CONFIG_MTD_CFI_I8 is not set
572# CONFIG_MTD_OTP is not set
573CONFIG_MTD_CFI_INTELEXT=y
574# CONFIG_MTD_CFI_AMDSTD is not set
575# CONFIG_MTD_CFI_STAA is not set
576CONFIG_MTD_CFI_UTIL=y
577# CONFIG_MTD_RAM is not set
578# CONFIG_MTD_ROM is not set
579# CONFIG_MTD_ABSENT is not set
580
581#
582# Mapping drivers for chip access
583#
584# CONFIG_MTD_COMPLEX_MAPPINGS is not set
585# CONFIG_MTD_PHYSMAP is not set
586CONFIG_MTD_PHYSMAP_OF=y
587# CONFIG_MTD_INTEL_VR_NOR is not set
588# CONFIG_MTD_PLATRAM is not set
589
590#
591# Self-contained MTD device drivers
592#
593# CONFIG_MTD_PMC551 is not set
594# CONFIG_MTD_SLRAM is not set
595# CONFIG_MTD_PHRAM is not set
596# CONFIG_MTD_MTDRAM is not set
597# CONFIG_MTD_BLOCK2MTD is not set
598
599#
600# Disk-On-Chip Device Drivers
601#
602# CONFIG_MTD_DOC2000 is not set
603# CONFIG_MTD_DOC2001 is not set
604# CONFIG_MTD_DOC2001PLUS is not set
605# CONFIG_MTD_NAND is not set
606# CONFIG_MTD_ONENAND is not set
607
608#
609# UBI - Unsorted block images
610#
611# CONFIG_MTD_UBI is not set
612CONFIG_OF_DEVICE=y
613# CONFIG_PARPORT is not set
614CONFIG_BLK_DEV=y
615# CONFIG_BLK_DEV_FD is not set
616# CONFIG_BLK_CPQ_DA is not set
617# CONFIG_BLK_CPQ_CISS_DA is not set
618# CONFIG_BLK_DEV_DAC960 is not set
619# CONFIG_BLK_DEV_UMEM is not set
620# CONFIG_BLK_DEV_COW_COMMON is not set
621CONFIG_BLK_DEV_LOOP=m
622CONFIG_BLK_DEV_CRYPTOLOOP=m
623CONFIG_BLK_DEV_NBD=m
624# CONFIG_BLK_DEV_SX8 is not set
625CONFIG_BLK_DEV_RAM=y
626CONFIG_BLK_DEV_RAM_COUNT=16
627CONFIG_BLK_DEV_RAM_SIZE=4096
628# CONFIG_BLK_DEV_XIP is not set
629# CONFIG_CDROM_PKTCDVD is not set
630# CONFIG_ATA_OVER_ETH is not set
631CONFIG_MISC_DEVICES=y
632# CONFIG_PHANTOM is not set
633# CONFIG_EEPROM_93CX6 is not set
634# CONFIG_SGI_IOC4 is not set
635# CONFIG_TIFM_CORE is not set
636# CONFIG_ENCLOSURE_SERVICES is not set
637CONFIG_HAVE_IDE=y
638# CONFIG_IDE is not set
639
640#
641# SCSI device support
642#
643# CONFIG_RAID_ATTRS is not set
644# CONFIG_SCSI is not set
645# CONFIG_SCSI_DMA is not set
646# CONFIG_SCSI_NETLINK is not set
647# CONFIG_ATA is not set
648CONFIG_MD=y
649CONFIG_BLK_DEV_MD=y
650CONFIG_MD_LINEAR=y
651CONFIG_MD_RAID0=y
652CONFIG_MD_RAID1=y
653CONFIG_MD_RAID10=y
654# CONFIG_MD_RAID456 is not set
655CONFIG_MD_MULTIPATH=y
656CONFIG_MD_FAULTY=y
657CONFIG_BLK_DEV_DM=y
658# CONFIG_DM_DEBUG is not set
659CONFIG_DM_CRYPT=y
660CONFIG_DM_SNAPSHOT=y
661CONFIG_DM_MIRROR=y
662CONFIG_DM_ZERO=y
663# CONFIG_DM_MULTIPATH is not set
664# CONFIG_DM_DELAY is not set
665# CONFIG_DM_UEVENT is not set
666# CONFIG_FUSION is not set
667
668#
669# IEEE 1394 (FireWire) support
670#
671# CONFIG_FIREWIRE is not set
672# CONFIG_IEEE1394 is not set
673# CONFIG_I2O is not set
674# CONFIG_MACINTOSH_DRIVERS is not set
675CONFIG_NETDEVICES=y
676# CONFIG_NETDEVICES_MULTIQUEUE is not set
677CONFIG_DUMMY=m
678CONFIG_BONDING=m
679# CONFIG_MACVLAN is not set
680# CONFIG_EQUALIZER is not set
681CONFIG_TUN=m
682# CONFIG_VETH is not set
683# CONFIG_ARCNET is not set
684CONFIG_PHYLIB=y
685
686#
687# MII PHY device drivers
688#
689# CONFIG_MARVELL_PHY is not set
690# CONFIG_DAVICOM_PHY is not set
691# CONFIG_QSEMI_PHY is not set
692# CONFIG_LXT_PHY is not set
693# CONFIG_CICADA_PHY is not set
694# CONFIG_VITESSE_PHY is not set
695# CONFIG_SMSC_PHY is not set
696CONFIG_BROADCOM_PHY=y
697# CONFIG_ICPLUS_PHY is not set
698# CONFIG_REALTEK_PHY is not set
699# CONFIG_FIXED_PHY is not set
700# CONFIG_MDIO_BITBANG is not set
701CONFIG_NET_ETHERNET=y
702CONFIG_MII=y
703# CONFIG_HAPPYMEAL is not set
704# CONFIG_SUNGEM is not set
705# CONFIG_CASSINI is not set
706# CONFIG_NET_VENDOR_3COM is not set
707# CONFIG_NET_TULIP is not set
708# CONFIG_HP100 is not set
709# CONFIG_IBM_NEW_EMAC_ZMII is not set
710# CONFIG_IBM_NEW_EMAC_RGMII is not set
711# CONFIG_IBM_NEW_EMAC_TAH is not set
712# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
713# CONFIG_NET_PCI is not set
714# CONFIG_B44 is not set
715CONFIG_NETDEV_1000=y
716# CONFIG_ACENIC is not set
717# CONFIG_DL2K is not set
718# CONFIG_E1000 is not set
719# CONFIG_E1000E is not set
720# CONFIG_E1000E_ENABLED is not set
721# CONFIG_IP1000 is not set
722# CONFIG_IGB is not set
723# CONFIG_NS83820 is not set
724# CONFIG_HAMACHI is not set
725# CONFIG_YELLOWFIN is not set
726# CONFIG_R8169 is not set
727# CONFIG_SIS190 is not set
728# CONFIG_SKGE is not set
729# CONFIG_SKY2 is not set
730# CONFIG_SK98LIN is not set
731# CONFIG_VIA_VELOCITY is not set
732# CONFIG_TIGON3 is not set
733# CONFIG_BNX2 is not set
734CONFIG_GIANFAR=y
735# CONFIG_GFAR_NAPI is not set
736# CONFIG_QLA3XXX is not set
737# CONFIG_ATL1 is not set
738# CONFIG_NETDEV_10000 is not set
739# CONFIG_TR is not set
740
741#
742# Wireless LAN
743#
744# CONFIG_WLAN_PRE80211 is not set
745# CONFIG_WLAN_80211 is not set
746# CONFIG_WAN is not set
747CONFIG_ATM_DRIVERS=y
748# CONFIG_ATM_DUMMY is not set
749# CONFIG_ATM_TCP is not set
750# CONFIG_ATM_LANAI is not set
751# CONFIG_ATM_ENI is not set
752# CONFIG_ATM_FIRESTREAM is not set
753# CONFIG_ATM_ZATM is not set
754# CONFIG_ATM_NICSTAR is not set
755# CONFIG_ATM_IDT77252 is not set
756# CONFIG_ATM_AMBASSADOR is not set
757# CONFIG_ATM_HORIZON is not set
758# CONFIG_ATM_IA is not set
759# CONFIG_ATM_FORE200E_MAYBE is not set
760# CONFIG_ATM_HE is not set
761# CONFIG_FDDI is not set
762# CONFIG_HIPPI is not set
763CONFIG_PPP=m
764CONFIG_PPP_MULTILINK=y
765CONFIG_PPP_FILTER=y
766CONFIG_PPP_ASYNC=m
767CONFIG_PPP_SYNC_TTY=m
768CONFIG_PPP_DEFLATE=m
769CONFIG_PPP_BSDCOMP=m
770# CONFIG_PPP_MPPE is not set
771CONFIG_PPPOE=m
772CONFIG_PPPOATM=m
773# CONFIG_PPPOL2TP is not set
774CONFIG_SLIP=m
775CONFIG_SLIP_COMPRESSED=y
776CONFIG_SLHC=m
777CONFIG_SLIP_SMART=y
778CONFIG_SLIP_MODE_SLIP6=y
779CONFIG_NETCONSOLE=y
780# CONFIG_NETCONSOLE_DYNAMIC is not set
781CONFIG_NETPOLL=y
782CONFIG_NETPOLL_TRAP=y
783CONFIG_NET_POLL_CONTROLLER=y
784# CONFIG_ISDN is not set
785# CONFIG_PHONE is not set
786
787#
788# Input device support
789#
790CONFIG_INPUT=y
791# CONFIG_INPUT_FF_MEMLESS is not set
792# CONFIG_INPUT_POLLDEV is not set
793
794#
795# Userland interfaces
796#
797CONFIG_INPUT_MOUSEDEV=y
798CONFIG_INPUT_MOUSEDEV_PSAUX=y
799CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
800CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
801# CONFIG_INPUT_JOYDEV is not set
802# CONFIG_INPUT_EVDEV is not set
803# CONFIG_INPUT_EVBUG is not set
804
805#
806# Input Device Drivers
807#
808# CONFIG_INPUT_KEYBOARD is not set
809# CONFIG_INPUT_MOUSE is not set
810# CONFIG_INPUT_JOYSTICK is not set
811# CONFIG_INPUT_TABLET is not set
812# CONFIG_INPUT_TOUCHSCREEN is not set
813# CONFIG_INPUT_MISC is not set
814
815#
816# Hardware I/O ports
817#
818# CONFIG_SERIO is not set
819# CONFIG_GAMEPORT is not set
820
821#
822# Character devices
823#
824CONFIG_VT=y
825CONFIG_VT_CONSOLE=y
826CONFIG_HW_CONSOLE=y
827# CONFIG_VT_HW_CONSOLE_BINDING is not set
828# CONFIG_SERIAL_NONSTANDARD is not set
829# CONFIG_NOZOMI is not set
830
831#
832# Serial drivers
833#
834CONFIG_SERIAL_8250=y
835CONFIG_SERIAL_8250_CONSOLE=y
836# CONFIG_SERIAL_8250_PCI is not set
837CONFIG_SERIAL_8250_NR_UARTS=2
838CONFIG_SERIAL_8250_RUNTIME_UARTS=2
839# CONFIG_SERIAL_8250_EXTENDED is not set
840
841#
842# Non-8250 serial port support
843#
844# CONFIG_SERIAL_UARTLITE is not set
845CONFIG_SERIAL_CORE=y
846CONFIG_SERIAL_CORE_CONSOLE=y
847# CONFIG_SERIAL_JSM is not set
848# CONFIG_SERIAL_OF_PLATFORM is not set
849CONFIG_UNIX98_PTYS=y
850CONFIG_LEGACY_PTYS=y
851CONFIG_LEGACY_PTY_COUNT=256
852# CONFIG_IPMI_HANDLER is not set
853CONFIG_HW_RANDOM=m
854# CONFIG_NVRAM is not set
855# CONFIG_GEN_RTC is not set
856# CONFIG_R3964 is not set
857# CONFIG_APPLICOM is not set
858# CONFIG_RAW_DRIVER is not set
859# CONFIG_TCG_TPM is not set
860CONFIG_DEVPORT=y
861CONFIG_I2C=y
862CONFIG_I2C_BOARDINFO=y
863CONFIG_I2C_CHARDEV=y
864
865#
866# I2C Algorithms
867#
868# CONFIG_I2C_ALGOBIT is not set
869# CONFIG_I2C_ALGOPCF is not set
870# CONFIG_I2C_ALGOPCA is not set
871
872#
873# I2C Hardware Bus support
874#
875# CONFIG_I2C_ALI1535 is not set
876# CONFIG_I2C_ALI1563 is not set
877# CONFIG_I2C_ALI15X3 is not set
878# CONFIG_I2C_AMD756 is not set
879# CONFIG_I2C_AMD8111 is not set
880# CONFIG_I2C_I801 is not set
881# CONFIG_I2C_I810 is not set
882# CONFIG_I2C_PIIX4 is not set
883CONFIG_I2C_MPC=y
884# CONFIG_I2C_NFORCE2 is not set
885# CONFIG_I2C_OCORES is not set
886# CONFIG_I2C_PARPORT_LIGHT is not set
887# CONFIG_I2C_PROSAVAGE is not set
888# CONFIG_I2C_SAVAGE4 is not set
889# CONFIG_I2C_SIMTEC is not set
890# CONFIG_I2C_SIS5595 is not set
891# CONFIG_I2C_SIS630 is not set
892# CONFIG_I2C_SIS96X is not set
893# CONFIG_I2C_TAOS_EVM is not set
894# CONFIG_I2C_STUB is not set
895# CONFIG_I2C_VIA is not set
896# CONFIG_I2C_VIAPRO is not set
897# CONFIG_I2C_VOODOO3 is not set
898
899#
900# Miscellaneous I2C Chip support
901#
902# CONFIG_DS1682 is not set
903# CONFIG_SENSORS_EEPROM is not set
904# CONFIG_SENSORS_PCF8574 is not set
905# CONFIG_PCF8575 is not set
906# CONFIG_SENSORS_PCF8591 is not set
907# CONFIG_TPS65010 is not set
908# CONFIG_SENSORS_MAX6875 is not set
909# CONFIG_SENSORS_TSL2550 is not set
910# CONFIG_I2C_DEBUG_CORE is not set
911# CONFIG_I2C_DEBUG_ALGO is not set
912# CONFIG_I2C_DEBUG_BUS is not set
913# CONFIG_I2C_DEBUG_CHIP is not set
914
915#
916# SPI support
917#
918# CONFIG_SPI is not set
919# CONFIG_SPI_MASTER is not set
920# CONFIG_W1 is not set
921# CONFIG_POWER_SUPPLY is not set
922CONFIG_HWMON=y
923# CONFIG_HWMON_VID is not set
924# CONFIG_SENSORS_AD7418 is not set
925# CONFIG_SENSORS_ADM1021 is not set
926# CONFIG_SENSORS_ADM1025 is not set
927# CONFIG_SENSORS_ADM1026 is not set
928# CONFIG_SENSORS_ADM1029 is not set
929# CONFIG_SENSORS_ADM1031 is not set
930# CONFIG_SENSORS_ADM9240 is not set
931# CONFIG_SENSORS_ADT7470 is not set
932# CONFIG_SENSORS_ADT7473 is not set
933# CONFIG_SENSORS_ATXP1 is not set
934# CONFIG_SENSORS_DS1621 is not set
935# CONFIG_SENSORS_I5K_AMB is not set
936# CONFIG_SENSORS_F71805F is not set
937# CONFIG_SENSORS_F71882FG is not set
938# CONFIG_SENSORS_F75375S is not set
939# CONFIG_SENSORS_GL518SM is not set
940# CONFIG_SENSORS_GL520SM is not set
941# CONFIG_SENSORS_IT87 is not set
942# CONFIG_SENSORS_LM63 is not set
943# CONFIG_SENSORS_LM75 is not set
944# CONFIG_SENSORS_LM77 is not set
945# CONFIG_SENSORS_LM78 is not set
946# CONFIG_SENSORS_LM80 is not set
947# CONFIG_SENSORS_LM83 is not set
948# CONFIG_SENSORS_LM85 is not set
949# CONFIG_SENSORS_LM87 is not set
950# CONFIG_SENSORS_LM90 is not set
951# CONFIG_SENSORS_LM92 is not set
952# CONFIG_SENSORS_LM93 is not set
953# CONFIG_SENSORS_MAX1619 is not set
954# CONFIG_SENSORS_MAX6650 is not set
955# CONFIG_SENSORS_PC87360 is not set
956# CONFIG_SENSORS_PC87427 is not set
957# CONFIG_SENSORS_SIS5595 is not set
958# CONFIG_SENSORS_DME1737 is not set
959# CONFIG_SENSORS_SMSC47M1 is not set
960# CONFIG_SENSORS_SMSC47M192 is not set
961# CONFIG_SENSORS_SMSC47B397 is not set
962# CONFIG_SENSORS_ADS7828 is not set
963# CONFIG_SENSORS_THMC50 is not set
964# CONFIG_SENSORS_VIA686A is not set
965# CONFIG_SENSORS_VT1211 is not set
966# CONFIG_SENSORS_VT8231 is not set
967# CONFIG_SENSORS_W83781D is not set
968# CONFIG_SENSORS_W83791D is not set
969# CONFIG_SENSORS_W83792D is not set
970# CONFIG_SENSORS_W83793 is not set
971# CONFIG_SENSORS_W83L785TS is not set
972# CONFIG_SENSORS_W83L786NG is not set
973# CONFIG_SENSORS_W83627HF is not set
974# CONFIG_SENSORS_W83627EHF is not set
975# CONFIG_HWMON_DEBUG_CHIP is not set
976# CONFIG_THERMAL is not set
977CONFIG_WATCHDOG=y
978# CONFIG_WATCHDOG_NOWAYOUT is not set
979
980#
981# Watchdog Device Drivers
982#
983CONFIG_SOFT_WATCHDOG=m
984
985#
986# PCI-based Watchdog Cards
987#
988# CONFIG_PCIPCWATCHDOG is not set
989# CONFIG_WDTPCI is not set
990
991#
992# Sonics Silicon Backplane
993#
994CONFIG_SSB_POSSIBLE=y
995# CONFIG_SSB is not set
996
997#
998# Multifunction device drivers
999#
1000# CONFIG_MFD_SM501 is not set
1001
1002#
1003# Multimedia devices
1004#
1005# CONFIG_VIDEO_DEV is not set
1006# CONFIG_DVB_CORE is not set
1007CONFIG_DAB=y
1008
1009#
1010# Graphics support
1011#
1012# CONFIG_AGP is not set
1013# CONFIG_DRM is not set
1014# CONFIG_VGASTATE is not set
1015CONFIG_VIDEO_OUTPUT_CONTROL=m
1016# CONFIG_FB is not set
1017# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1018
1019#
1020# Display device support
1021#
1022# CONFIG_DISPLAY_SUPPORT is not set
1023
1024#
1025# Console display driver support
1026#
1027CONFIG_VGA_CONSOLE=y
1028# CONFIG_VGACON_SOFT_SCROLLBACK is not set
1029CONFIG_DUMMY_CONSOLE=y
1030
1031#
1032# Sound
1033#
1034# CONFIG_SOUND is not set
1035CONFIG_HID_SUPPORT=y
1036CONFIG_HID=y
1037# CONFIG_HID_DEBUG is not set
1038# CONFIG_HIDRAW is not set
1039CONFIG_USB_SUPPORT=y
1040CONFIG_USB_ARCH_HAS_HCD=y
1041CONFIG_USB_ARCH_HAS_OHCI=y
1042CONFIG_USB_ARCH_HAS_EHCI=y
1043# CONFIG_USB is not set
1044
1045#
1046# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1047#
1048# CONFIG_USB_GADGET is not set
1049# CONFIG_MMC is not set
1050# CONFIG_MEMSTICK is not set
1051# CONFIG_NEW_LEDS is not set
1052# CONFIG_INFINIBAND is not set
1053# CONFIG_EDAC is not set
1054# CONFIG_RTC_CLASS is not set
1055# CONFIG_DMADEVICES is not set
1056
1057#
1058# Userspace I/O
1059#
1060# CONFIG_UIO is not set
1061
1062#
1063# File systems
1064#
1065CONFIG_EXT2_FS=y
1066CONFIG_EXT2_FS_XATTR=y
1067CONFIG_EXT2_FS_POSIX_ACL=y
1068# CONFIG_EXT2_FS_SECURITY is not set
1069# CONFIG_EXT2_FS_XIP is not set
1070CONFIG_EXT3_FS=y
1071CONFIG_EXT3_FS_XATTR=y
1072CONFIG_EXT3_FS_POSIX_ACL=y
1073# CONFIG_EXT3_FS_SECURITY is not set
1074# CONFIG_EXT4DEV_FS is not set
1075CONFIG_JBD=y
1076# CONFIG_JBD_DEBUG is not set
1077CONFIG_FS_MBCACHE=y
1078CONFIG_REISERFS_FS=m
1079# CONFIG_REISERFS_CHECK is not set
1080# CONFIG_REISERFS_PROC_INFO is not set
1081CONFIG_REISERFS_FS_XATTR=y
1082CONFIG_REISERFS_FS_POSIX_ACL=y
1083# CONFIG_REISERFS_FS_SECURITY is not set
1084# CONFIG_JFS_FS is not set
1085CONFIG_FS_POSIX_ACL=y
1086# CONFIG_XFS_FS is not set
1087# CONFIG_GFS2_FS is not set
1088CONFIG_OCFS2_FS=m
1089CONFIG_OCFS2_DEBUG_MASKLOG=y
1090# CONFIG_OCFS2_DEBUG_FS is not set
1091CONFIG_DNOTIFY=y
1092CONFIG_INOTIFY=y
1093CONFIG_INOTIFY_USER=y
1094# CONFIG_QUOTA is not set
1095CONFIG_AUTOFS_FS=m
1096CONFIG_AUTOFS4_FS=m
1097# CONFIG_FUSE_FS is not set
1098
1099#
1100# CD-ROM/DVD Filesystems
1101#
1102# CONFIG_ISO9660_FS is not set
1103# CONFIG_UDF_FS is not set
1104
1105#
1106# DOS/FAT/NT Filesystems
1107#
1108# CONFIG_MSDOS_FS is not set
1109# CONFIG_VFAT_FS is not set
1110# CONFIG_NTFS_FS is not set
1111
1112#
1113# Pseudo filesystems
1114#
1115CONFIG_PROC_FS=y
1116CONFIG_PROC_KCORE=y
1117CONFIG_PROC_SYSCTL=y
1118CONFIG_SYSFS=y
1119CONFIG_TMPFS=y
1120# CONFIG_TMPFS_POSIX_ACL is not set
1121# CONFIG_HUGETLB_PAGE is not set
1122CONFIG_CONFIGFS_FS=m
1123
1124#
1125# Miscellaneous filesystems
1126#
1127# CONFIG_ADFS_FS is not set
1128# CONFIG_AFFS_FS is not set
1129# CONFIG_HFS_FS is not set
1130# CONFIG_HFSPLUS_FS is not set
1131# CONFIG_BEFS_FS is not set
1132# CONFIG_BFS_FS is not set
1133# CONFIG_EFS_FS is not set
1134# CONFIG_JFFS2_FS is not set
1135# CONFIG_CRAMFS is not set
1136# CONFIG_VXFS_FS is not set
1137CONFIG_MINIX_FS=m
1138# CONFIG_HPFS_FS is not set
1139# CONFIG_QNX4FS_FS is not set
1140CONFIG_ROMFS_FS=m
1141# CONFIG_SYSV_FS is not set
1142# CONFIG_UFS_FS is not set
1143CONFIG_NETWORK_FILESYSTEMS=y
1144CONFIG_NFS_FS=y
1145CONFIG_NFS_V3=y
1146# CONFIG_NFS_V3_ACL is not set
1147CONFIG_NFS_V4=y
1148CONFIG_NFS_DIRECTIO=y
1149# CONFIG_NFSD is not set
1150CONFIG_ROOT_NFS=y
1151CONFIG_LOCKD=y
1152CONFIG_LOCKD_V4=y
1153CONFIG_NFS_COMMON=y
1154CONFIG_SUNRPC=y
1155CONFIG_SUNRPC_GSS=y
1156# CONFIG_SUNRPC_BIND34 is not set
1157CONFIG_RPCSEC_GSS_KRB5=y
1158# CONFIG_RPCSEC_GSS_SPKM3 is not set
1159CONFIG_SMB_FS=m
1160CONFIG_SMB_NLS_DEFAULT=y
1161CONFIG_SMB_NLS_REMOTE="cp437"
1162CONFIG_CIFS=m
1163# CONFIG_CIFS_STATS is not set
1164# CONFIG_CIFS_WEAK_PW_HASH is not set
1165CONFIG_CIFS_XATTR=y
1166CONFIG_CIFS_POSIX=y
1167# CONFIG_CIFS_DEBUG2 is not set
1168# CONFIG_CIFS_EXPERIMENTAL is not set
1169# CONFIG_NCP_FS is not set
1170# CONFIG_CODA_FS is not set
1171# CONFIG_AFS_FS is not set
1172
1173#
1174# Partition Types
1175#
1176# CONFIG_PARTITION_ADVANCED is not set
1177CONFIG_MSDOS_PARTITION=y
1178CONFIG_NLS=m
1179CONFIG_NLS_DEFAULT="iso8859-1"
1180CONFIG_NLS_CODEPAGE_437=m
1181CONFIG_NLS_CODEPAGE_737=m
1182CONFIG_NLS_CODEPAGE_775=m
1183CONFIG_NLS_CODEPAGE_850=m
1184CONFIG_NLS_CODEPAGE_852=m
1185CONFIG_NLS_CODEPAGE_855=m
1186CONFIG_NLS_CODEPAGE_857=m
1187CONFIG_NLS_CODEPAGE_860=m
1188CONFIG_NLS_CODEPAGE_861=m
1189CONFIG_NLS_CODEPAGE_862=m
1190CONFIG_NLS_CODEPAGE_863=m
1191CONFIG_NLS_CODEPAGE_864=m
1192CONFIG_NLS_CODEPAGE_865=m
1193CONFIG_NLS_CODEPAGE_866=m
1194CONFIG_NLS_CODEPAGE_869=m
1195CONFIG_NLS_CODEPAGE_936=m
1196CONFIG_NLS_CODEPAGE_950=m
1197CONFIG_NLS_CODEPAGE_932=m
1198CONFIG_NLS_CODEPAGE_949=m
1199CONFIG_NLS_CODEPAGE_874=m
1200CONFIG_NLS_ISO8859_8=m
1201CONFIG_NLS_CODEPAGE_1250=m
1202CONFIG_NLS_CODEPAGE_1251=m
1203CONFIG_NLS_ASCII=m
1204CONFIG_NLS_ISO8859_1=m
1205CONFIG_NLS_ISO8859_2=m
1206CONFIG_NLS_ISO8859_3=m
1207CONFIG_NLS_ISO8859_4=m
1208CONFIG_NLS_ISO8859_5=m
1209CONFIG_NLS_ISO8859_6=m
1210CONFIG_NLS_ISO8859_7=m
1211CONFIG_NLS_ISO8859_9=m
1212CONFIG_NLS_ISO8859_13=m
1213CONFIG_NLS_ISO8859_14=m
1214CONFIG_NLS_ISO8859_15=m
1215CONFIG_NLS_KOI8_R=m
1216CONFIG_NLS_KOI8_U=m
1217CONFIG_NLS_UTF8=m
1218# CONFIG_DLM is not set
1219
1220#
1221# Library routines
1222#
1223CONFIG_BITREVERSE=y
1224CONFIG_CRC_CCITT=m
1225# CONFIG_CRC16 is not set
1226# CONFIG_CRC_ITU_T is not set
1227CONFIG_CRC32=y
1228# CONFIG_CRC7 is not set
1229CONFIG_LIBCRC32C=m
1230CONFIG_ZLIB_INFLATE=m
1231CONFIG_ZLIB_DEFLATE=m
1232CONFIG_PLIST=y
1233CONFIG_HAS_IOMEM=y
1234CONFIG_HAS_IOPORT=y
1235CONFIG_HAS_DMA=y
1236CONFIG_HAVE_LMB=y
1237
1238#
1239# Kernel hacking
1240#
1241# CONFIG_PRINTK_TIME is not set
1242CONFIG_ENABLE_WARN_DEPRECATED=y
1243CONFIG_ENABLE_MUST_CHECK=y
1244CONFIG_MAGIC_SYSRQ=y
1245# CONFIG_UNUSED_SYMBOLS is not set
1246CONFIG_DEBUG_FS=y
1247# CONFIG_HEADERS_CHECK is not set
1248CONFIG_DEBUG_KERNEL=y
1249# CONFIG_DEBUG_SHIRQ is not set
1250CONFIG_DETECT_SOFTLOCKUP=y
1251CONFIG_SCHED_DEBUG=y
1252# CONFIG_SCHEDSTATS is not set
1253# CONFIG_TIMER_STATS is not set
1254# CONFIG_DEBUG_SLAB is not set
1255# CONFIG_DEBUG_RT_MUTEXES is not set
1256# CONFIG_RT_MUTEX_TESTER is not set
1257# CONFIG_DEBUG_SPINLOCK is not set
1258# CONFIG_DEBUG_MUTEXES is not set
1259# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1260# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1261# CONFIG_DEBUG_KOBJECT is not set
1262# CONFIG_DEBUG_BUGVERBOSE is not set
1263CONFIG_DEBUG_INFO=y
1264# CONFIG_DEBUG_VM is not set
1265# CONFIG_DEBUG_LIST is not set
1266# CONFIG_DEBUG_SG is not set
1267# CONFIG_BOOT_PRINTK_DELAY is not set
1268# CONFIG_RCU_TORTURE_TEST is not set
1269# CONFIG_BACKTRACE_SELF_TEST is not set
1270# CONFIG_FAULT_INJECTION is not set
1271# CONFIG_SAMPLES is not set
1272# CONFIG_DEBUG_STACKOVERFLOW is not set
1273# CONFIG_DEBUG_STACK_USAGE is not set
1274# CONFIG_DEBUG_PAGEALLOC is not set
1275CONFIG_DEBUGGER=y
1276# CONFIG_XMON is not set
1277# CONFIG_VIRQ_DEBUG is not set
1278# CONFIG_BDI_SWITCH is not set
1279# CONFIG_PPC_EARLY_DEBUG is not set
1280
1281#
1282# Security options
1283#
1284# CONFIG_KEYS is not set
1285CONFIG_SECURITY=y
1286CONFIG_SECURITY_NETWORK=y
1287# CONFIG_SECURITY_NETWORK_XFRM is not set
1288CONFIG_SECURITY_CAPABILITIES=y
1289# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1290CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1291CONFIG_CRYPTO=y
1292CONFIG_CRYPTO_ALGAPI=y
1293CONFIG_CRYPTO_AEAD=m
1294CONFIG_CRYPTO_BLKCIPHER=y
1295# CONFIG_CRYPTO_SEQIV is not set
1296CONFIG_CRYPTO_HASH=y
1297CONFIG_CRYPTO_MANAGER=y
1298CONFIG_CRYPTO_HMAC=y
1299# CONFIG_CRYPTO_XCBC is not set
1300CONFIG_CRYPTO_NULL=m
1301CONFIG_CRYPTO_MD4=m
1302CONFIG_CRYPTO_MD5=y
1303CONFIG_CRYPTO_SHA1=m
1304CONFIG_CRYPTO_SHA256=m
1305CONFIG_CRYPTO_SHA512=m
1306CONFIG_CRYPTO_WP512=m
1307# CONFIG_CRYPTO_TGR192 is not set
1308# CONFIG_CRYPTO_GF128MUL is not set
1309CONFIG_CRYPTO_ECB=m
1310CONFIG_CRYPTO_CBC=y
1311CONFIG_CRYPTO_PCBC=m
1312# CONFIG_CRYPTO_LRW is not set
1313# CONFIG_CRYPTO_XTS is not set
1314# CONFIG_CRYPTO_CTR is not set
1315# CONFIG_CRYPTO_GCM is not set
1316# CONFIG_CRYPTO_CCM is not set
1317# CONFIG_CRYPTO_CRYPTD is not set
1318CONFIG_CRYPTO_DES=y
1319# CONFIG_CRYPTO_FCRYPT is not set
1320CONFIG_CRYPTO_BLOWFISH=m
1321CONFIG_CRYPTO_TWOFISH=m
1322CONFIG_CRYPTO_TWOFISH_COMMON=m
1323CONFIG_CRYPTO_SERPENT=m
1324CONFIG_CRYPTO_AES=m
1325CONFIG_CRYPTO_CAST5=m
1326CONFIG_CRYPTO_CAST6=m
1327CONFIG_CRYPTO_TEA=m
1328CONFIG_CRYPTO_ARC4=m
1329CONFIG_CRYPTO_KHAZAD=m
1330CONFIG_CRYPTO_ANUBIS=m
1331# CONFIG_CRYPTO_SEED is not set
1332# CONFIG_CRYPTO_SALSA20 is not set
1333CONFIG_CRYPTO_DEFLATE=m
1334CONFIG_CRYPTO_MICHAEL_MIC=m
1335CONFIG_CRYPTO_CRC32C=m
1336# CONFIG_CRYPTO_CAMELLIA is not set
1337CONFIG_CRYPTO_TEST=m
1338CONFIG_CRYPTO_AUTHENC=m
1339# CONFIG_CRYPTO_LZO is not set
1340CONFIG_CRYPTO_HW=y
1341# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1342# CONFIG_PPC_CLOCK is not set
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 69a91bd46115..84c868633068 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -110,9 +110,9 @@ transfer_to_handler:
110 stw r11,PT_REGS(r12) 110 stw r11,PT_REGS(r12)
111#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 111#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
112 /* Check to see if the dbcr0 register is set up to debug. Use the 112 /* Check to see if the dbcr0 register is set up to debug. Use the
113 single-step bit to do this. */ 113 internal debug mode bit to do this. */
114 lwz r12,THREAD_DBCR0(r12) 114 lwz r12,THREAD_DBCR0(r12)
115 andis. r12,r12,DBCR0_IC@h 115 andis. r12,r12,DBCR0_IDM@h
116 beq+ 3f 116 beq+ 3f
117 /* From user and task is ptraced - load up global dbcr0 */ 117 /* From user and task is ptraced - load up global dbcr0 */
118 li r12,-1 /* clear all pending debug events */ 118 li r12,-1 /* clear all pending debug events */
@@ -120,6 +120,12 @@ transfer_to_handler:
120 lis r11,global_dbcr0@ha 120 lis r11,global_dbcr0@ha
121 tophys(r11,r11) 121 tophys(r11,r11)
122 addi r11,r11,global_dbcr0@l 122 addi r11,r11,global_dbcr0@l
123#ifdef CONFIG_SMP
124 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
125 lwz r9,TI_CPU(r9)
126 slwi r9,r9,3
127 add r11,r11,r9
128#endif
123 lwz r12,0(r11) 129 lwz r12,0(r11)
124 mtspr SPRN_DBCR0,r12 130 mtspr SPRN_DBCR0,r12
125 lwz r12,4(r11) 131 lwz r12,4(r11)
@@ -238,10 +244,10 @@ ret_from_syscall:
238 stw r11,_CCR(r1) 244 stw r11,_CCR(r1)
239syscall_exit_cont: 245syscall_exit_cont:
240#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 246#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
241 /* If the process has its own DBCR0 value, load it up. The single 247 /* If the process has its own DBCR0 value, load it up. The internal
242 step bit tells us that dbcr0 should be loaded. */ 248 debug mode bit tells us that dbcr0 should be loaded. */
243 lwz r0,THREAD+THREAD_DBCR0(r2) 249 lwz r0,THREAD+THREAD_DBCR0(r2)
244 andis. r10,r0,DBCR0_IC@h 250 andis. r10,r0,DBCR0_IDM@h
245 bnel- load_dbcr0 251 bnel- load_dbcr0
246#endif 252#endif
247#ifdef CONFIG_44x 253#ifdef CONFIG_44x
@@ -666,10 +672,10 @@ user_exc_return: /* r10 contains MSR_KERNEL here */
666 672
667restore_user: 673restore_user:
668#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 674#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
669 /* Check whether this process has its own DBCR0 value. The single 675 /* Check whether this process has its own DBCR0 value. The internal
670 step bit tells us that dbcr0 should be loaded. */ 676 debug mode bit tells us that dbcr0 should be loaded. */
671 lwz r0,THREAD+THREAD_DBCR0(r2) 677 lwz r0,THREAD+THREAD_DBCR0(r2)
672 andis. r10,r0,DBCR0_IC@h 678 andis. r10,r0,DBCR0_IDM@h
673 bnel- load_dbcr0 679 bnel- load_dbcr0
674#endif 680#endif
675 681
@@ -879,6 +885,12 @@ load_dbcr0:
879 mfspr r10,SPRN_DBCR0 885 mfspr r10,SPRN_DBCR0
880 lis r11,global_dbcr0@ha 886 lis r11,global_dbcr0@ha
881 addi r11,r11,global_dbcr0@l 887 addi r11,r11,global_dbcr0@l
888#ifdef CONFIG_SMP
889 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
890 lwz r9,TI_CPU(r9)
891 slwi r9,r9,3
892 add r11,r11,r9
893#endif
882 stw r10,0(r11) 894 stw r10,0(r11)
883 mtspr SPRN_DBCR0,r0 895 mtspr SPRN_DBCR0,r0
884 lwz r10,4(r11) 896 lwz r10,4(r11)
@@ -891,7 +903,7 @@ load_dbcr0:
891 .section .bss 903 .section .bss
892 .align 4 904 .align 4
893global_dbcr0: 905global_dbcr0:
894 .space 8 906 .space 8*NR_CPUS
895 .previous 907 .previous
896#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ 908#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
897 909
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index ad071a146a8d..b84ec6a2fc94 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -211,7 +211,7 @@ skpinv: addi r4,r4,1 /* Increment */
211 SET_IVOR(12, WatchdogTimer); 211 SET_IVOR(12, WatchdogTimer);
212 SET_IVOR(13, DataTLBError); 212 SET_IVOR(13, DataTLBError);
213 SET_IVOR(14, InstructionTLBError); 213 SET_IVOR(14, InstructionTLBError);
214 SET_IVOR(15, Debug); 214 SET_IVOR(15, DebugCrit);
215 215
216 /* Establish the interrupt vector base */ 216 /* Establish the interrupt vector base */
217 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 217 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
@@ -578,7 +578,7 @@ interrupt_base:
578 b InstructionStorage 578 b InstructionStorage
579 579
580 /* Debug Interrupt */ 580 /* Debug Interrupt */
581 DEBUG_EXCEPTION 581 DEBUG_CRIT_EXCEPTION
582 582
583/* 583/*
584 * Local functions 584 * Local functions
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index ba9393f8e77a..aefafc6330c9 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -56,8 +56,17 @@
56 * is necessary since the MMU is always on, for Book-E parts, and the stacks 56 * is necessary since the MMU is always on, for Book-E parts, and the stacks
57 * are offset from KERNELBASE. 57 * are offset from KERNELBASE.
58 * 58 *
59 * There is some space optimization to be had here if desired. However
60 * to allow for a common kernel with support for debug exceptions either
61 * going to critical or their own debug level we aren't currently
62 * providing configurations that micro-optimize space usage.
59 */ 63 */
60#define BOOKE_EXCEPTION_STACK_SIZE (8192) 64#ifdef CONFIG_44x
65#define NUM_EXCEPTION_LVLS 2
66#else
67#define NUM_EXCEPTION_LVLS 3
68#endif
69#define BOOKE_EXCEPTION_STACK_SIZE (4096 * NUM_EXCEPTION_LVLS)
61 70
62/* CRIT_SPRG only used in critical exception handling */ 71/* CRIT_SPRG only used in critical exception handling */
63#define CRIT_SPRG SPRN_SPRG2 72#define CRIT_SPRG SPRN_SPRG2
@@ -68,7 +77,7 @@
68#define CRIT_STACK_TOP (exception_stack_top) 77#define CRIT_STACK_TOP (exception_stack_top)
69 78
70/* only on e200 for now */ 79/* only on e200 for now */
71#define DEBUG_STACK_TOP (exception_stack_top - 4096) 80#define DEBUG_STACK_TOP (exception_stack_top - 8192)
72#define DEBUG_SPRG SPRN_SPRG6W 81#define DEBUG_SPRG SPRN_SPRG6W
73 82
74#ifdef CONFIG_SMP 83#ifdef CONFIG_SMP
@@ -212,9 +221,8 @@ label:
212 * save (and later restore) the MSR via SPRN_CSRR1, which will still have 221 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
213 * the MSR_DE bit set. 222 * the MSR_DE bit set.
214 */ 223 */
215#ifdef CONFIG_E200 224#define DEBUG_DEBUG_EXCEPTION \
216#define DEBUG_EXCEPTION \ 225 START_EXCEPTION(DebugDebug); \
217 START_EXCEPTION(Debug); \
218 DEBUG_EXCEPTION_PROLOG; \ 226 DEBUG_EXCEPTION_PROLOG; \
219 \ 227 \
220 /* \ 228 /* \
@@ -234,8 +242,8 @@ label:
234 cmplw r12,r10; \ 242 cmplw r12,r10; \
235 blt+ 2f; /* addr below exception vectors */ \ 243 blt+ 2f; /* addr below exception vectors */ \
236 \ 244 \
237 lis r10,Debug@h; \ 245 lis r10,DebugDebug@h; \
238 ori r10,r10,Debug@l; \ 246 ori r10,r10,DebugDebug@l; \
239 cmplw r12,r10; \ 247 cmplw r12,r10; \
240 bgt+ 2f; /* addr above exception vectors */ \ 248 bgt+ 2f; /* addr above exception vectors */ \
241 \ 249 \
@@ -265,9 +273,9 @@ label:
2652: mfspr r4,SPRN_DBSR; \ 2732: mfspr r4,SPRN_DBSR; \
266 addi r3,r1,STACK_FRAME_OVERHEAD; \ 274 addi r3,r1,STACK_FRAME_OVERHEAD; \
267 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) 275 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
268#else 276
269#define DEBUG_EXCEPTION \ 277#define DEBUG_CRIT_EXCEPTION \
270 START_EXCEPTION(Debug); \ 278 START_EXCEPTION(DebugCrit); \
271 CRITICAL_EXCEPTION_PROLOG; \ 279 CRITICAL_EXCEPTION_PROLOG; \
272 \ 280 \
273 /* \ 281 /* \
@@ -287,8 +295,8 @@ label:
287 cmplw r12,r10; \ 295 cmplw r12,r10; \
288 blt+ 2f; /* addr below exception vectors */ \ 296 blt+ 2f; /* addr below exception vectors */ \
289 \ 297 \
290 lis r10,Debug@h; \ 298 lis r10,DebugCrit@h; \
291 ori r10,r10,Debug@l; \ 299 ori r10,r10,DebugCrit@l; \
292 cmplw r12,r10; \ 300 cmplw r12,r10; \
293 bgt+ 2f; /* addr above exception vectors */ \ 301 bgt+ 2f; /* addr above exception vectors */ \
294 \ 302 \
@@ -318,7 +326,6 @@ label:
3182: mfspr r4,SPRN_DBSR; \ 3262: mfspr r4,SPRN_DBSR; \
319 addi r3,r1,STACK_FRAME_OVERHEAD; \ 327 addi r3,r1,STACK_FRAME_OVERHEAD; \
320 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) 328 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
321#endif
322 329
323#define INSTRUCTION_STORAGE_EXCEPTION \ 330#define INSTRUCTION_STORAGE_EXCEPTION \
324 START_EXCEPTION(InstructionStorage) \ 331 START_EXCEPTION(InstructionStorage) \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 9f40b3e77100..4ff744143566 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -303,7 +303,10 @@ skpinv: addi r6,r6,1 /* Increment */
303 SET_IVOR(12, WatchdogTimer); 303 SET_IVOR(12, WatchdogTimer);
304 SET_IVOR(13, DataTLBError); 304 SET_IVOR(13, DataTLBError);
305 SET_IVOR(14, InstructionTLBError); 305 SET_IVOR(14, InstructionTLBError);
306 SET_IVOR(15, Debug); 306 SET_IVOR(15, DebugDebug);
307#if defined(CONFIG_E500)
308 SET_IVOR(15, DebugCrit);
309#endif
307 SET_IVOR(32, SPEUnavailable); 310 SET_IVOR(32, SPEUnavailable);
308 SET_IVOR(33, SPEFloatingPointData); 311 SET_IVOR(33, SPEFloatingPointData);
309 SET_IVOR(34, SPEFloatingPointRound); 312 SET_IVOR(34, SPEFloatingPointRound);
@@ -738,7 +741,10 @@ interrupt_base:
738 741
739 742
740 /* Debug Interrupt */ 743 /* Debug Interrupt */
741 DEBUG_EXCEPTION 744 DEBUG_DEBUG_EXCEPTION
745#if defined(CONFIG_E500)
746 DEBUG_CRIT_EXCEPTION
747#endif
742 748
743/* 749/*
744 * Local functions 750 * Local functions
diff --git a/arch/powerpc/lib/rheap.c b/arch/powerpc/lib/rheap.c
index 22c3b4f53de7..29b2941cada0 100644
--- a/arch/powerpc/lib/rheap.c
+++ b/arch/powerpc/lib/rheap.c
@@ -54,7 +54,7 @@ static int grow(rh_info_t * info, int max_blocks)
54 54
55 new_blocks = max_blocks - info->max_blocks; 55 new_blocks = max_blocks - info->max_blocks;
56 56
57 block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_KERNEL); 57 block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_ATOMIC);
58 if (block == NULL) 58 if (block == NULL)
59 return -ENOMEM; 59 return -ENOMEM;
60 60
@@ -258,7 +258,7 @@ rh_info_t *rh_create(unsigned int alignment)
258 if ((alignment & (alignment - 1)) != 0) 258 if ((alignment & (alignment - 1)) != 0)
259 return ERR_PTR(-EINVAL); 259 return ERR_PTR(-EINVAL);
260 260
261 info = kmalloc(sizeof(*info), GFP_KERNEL); 261 info = kmalloc(sizeof(*info), GFP_ATOMIC);
262 if (info == NULL) 262 if (info == NULL)
263 return ERR_PTR(-ENOMEM); 263 return ERR_PTR(-ENOMEM);
264 264
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
index 4fad6c7bf9f1..917ac8891555 100644
--- a/arch/powerpc/platforms/82xx/Kconfig
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -11,7 +11,6 @@ config MPC8272_ADS
11 select 8260 11 select 8260
12 select FSL_SOC 12 select FSL_SOC
13 select PQ2_ADS_PCI_PIC if PCI 13 select PQ2_ADS_PCI_PIC if PCI
14 select PPC_CPM_NEW_BINDING
15 help 14 help
16 This option enables support for the MPC8272 ADS board 15 This option enables support for the MPC8272 ADS board
17 16
@@ -22,7 +21,6 @@ config PQ2FADS
22 select 8260 21 select 8260
23 select FSL_SOC 22 select FSL_SOC
24 select PQ2_ADS_PCI_PIC if PCI 23 select PQ2_ADS_PCI_PIC if PCI
25 select PPC_CPM_NEW_BINDING
26 help 24 help
27 This option enables support for the PQ2FADS board 25 This option enables support for the PQ2FADS board
28 26
@@ -31,7 +29,6 @@ config EP8248E
31 select 8272 29 select 8272
32 select 8260 30 select 8260
33 select FSL_SOC 31 select FSL_SOC
34 select PPC_CPM_NEW_BINDING
35 select MDIO_BITBANG 32 select MDIO_BITBANG
36 help 33 help
37 This enables support for the Embedded Planet EP8248E board. 34 This enables support for the Embedded Planet EP8248E board.
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 2293ae51383d..c00356bdb1dd 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -46,6 +46,7 @@ static void __init mpc837x_rdb_setup_arch(void)
46static struct of_device_id mpc837x_ids[] = { 46static struct of_device_id mpc837x_ids[] = {
47 { .type = "soc", }, 47 { .type = "soc", },
48 { .compatible = "soc", }, 48 { .compatible = "soc", },
49 { .compatible = "simple-bus", },
49 {}, 50 {},
50}; 51};
51 52
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 68065e62fc3d..88a3b5cabb18 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -16,6 +16,7 @@
16#define MPC83XX_SCCR_USB_DRCM_10 0x00200000 16#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
17#define MPC8315_SCCR_USB_MASK 0x00c00000 17#define MPC8315_SCCR_USB_MASK 0x00c00000
18#define MPC8315_SCCR_USB_DRCM_11 0x00c00000 18#define MPC8315_SCCR_USB_DRCM_11 0x00c00000
19#define MPC8315_SCCR_USB_DRCM_01 0x00400000
19#define MPC837X_SCCR_USB_DRCM_11 0x00c00000 20#define MPC837X_SCCR_USB_DRCM_11 0x00c00000
20 21
21/* system i/o configuration register low */ 22/* system i/o configuration register low */
@@ -37,6 +38,7 @@
37/* USB Control Register */ 38/* USB Control Register */
38#define FSL_USB2_CONTROL_OFFS 0x500 39#define FSL_USB2_CONTROL_OFFS 0x500
39#define CONTROL_UTMI_PHY_EN 0x00000200 40#define CONTROL_UTMI_PHY_EN 0x00000200
41#define CONTROL_REFSEL_24MHZ 0x00000040
40#define CONTROL_REFSEL_48MHZ 0x00000080 42#define CONTROL_REFSEL_48MHZ 0x00000080
41#define CONTROL_PHY_CLK_SEL_ULPI 0x00000400 43#define CONTROL_PHY_CLK_SEL_ULPI 0x00000400
42#define CONTROL_OTG_PORT 0x00000020 44#define CONTROL_OTG_PORT 0x00000020
diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c
index 471fdd8f4108..64bcf0a33c71 100644
--- a/arch/powerpc/platforms/83xx/usb.c
+++ b/arch/powerpc/platforms/83xx/usb.c
@@ -129,7 +129,7 @@ int mpc831x_usb_cfg(void)
129 if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) 129 if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
130 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, 130 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
131 MPC8315_SCCR_USB_MASK, 131 MPC8315_SCCR_USB_MASK,
132 MPC8315_SCCR_USB_DRCM_11); 132 MPC8315_SCCR_USB_DRCM_01);
133 else 133 else
134 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, 134 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
135 MPC83XX_SCCR_USB_MASK, 135 MPC83XX_SCCR_USB_MASK,
@@ -164,9 +164,15 @@ int mpc831x_usb_cfg(void)
164 /* Using on-chip PHY */ 164 /* Using on-chip PHY */
165 if (prop && (!strcmp(prop, "utmi_wide") || 165 if (prop && (!strcmp(prop, "utmi_wide") ||
166 !strcmp(prop, "utmi"))) { 166 !strcmp(prop, "utmi"))) {
167 /* Set UTMI_PHY_EN, REFSEL to 48MHZ */ 167 u32 refsel;
168
169 if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
170 refsel = CONTROL_REFSEL_24MHZ;
171 else
172 refsel = CONTROL_REFSEL_48MHZ;
173 /* Set UTMI_PHY_EN and REFSEL */
168 out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, 174 out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
169 CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ); 175 CONTROL_UTMI_PHY_EN | refsel);
170 /* Using external UPLI PHY */ 176 /* Using external UPLI PHY */
171 } else if (prop && !strcmp(prop, "ulpi")) { 177 } else if (prop && !strcmp(prop, "ulpi")) {
172 /* Set PHY_CLK_SEL to ULPI */ 178 /* Set PHY_CLK_SEL to ULPI */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 28bc6e58a970..7ff29d53dc2d 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -19,7 +19,6 @@ config MPC8540_ADS
19config MPC8560_ADS 19config MPC8560_ADS
20 bool "Freescale MPC8560 ADS" 20 bool "Freescale MPC8560 ADS"
21 select DEFAULT_UIMAGE 21 select DEFAULT_UIMAGE
22 select PPC_CPM_NEW_BINDING
23 select CPM2 22 select CPM2
24 help 23 help
25 This option enables support for the MPC 8560 ADS board 24 This option enables support for the MPC 8560 ADS board
@@ -48,7 +47,6 @@ config MPC85xx_DS
48 47
49config KSI8560 48config KSI8560
50 bool "Emerson KSI8560" 49 bool "Emerson KSI8560"
51 select PPC_CPM_NEW_BINDING
52 select DEFAULT_UIMAGE 50 select DEFAULT_UIMAGE
53 help 51 help
54 This option enables support for the Emerson KSI8560 board 52 This option enables support for the Emerson KSI8560 board
@@ -60,14 +58,12 @@ config STX_GP3
60 board. 58 board.
61 select CPM2 59 select CPM2
62 select DEFAULT_UIMAGE 60 select DEFAULT_UIMAGE
63 select PPC_CPM_NEW_BINDING
64 61
65config TQM8540 62config TQM8540
66 bool "TQ Components TQM8540" 63 bool "TQ Components TQM8540"
67 help 64 help
68 This option enables support for the TQ Components TQM8540 board. 65 This option enables support for the TQ Components TQM8540 board.
69 select DEFAULT_UIMAGE 66 select DEFAULT_UIMAGE
70 select PPC_CPM_NEW_BINDING
71 select TQM85xx 67 select TQM85xx
72 68
73config TQM8541 69config TQM8541
@@ -75,7 +71,6 @@ config TQM8541
75 help 71 help
76 This option enables support for the TQ Components TQM8541 board. 72 This option enables support for the TQ Components TQM8541 board.
77 select DEFAULT_UIMAGE 73 select DEFAULT_UIMAGE
78 select PPC_CPM_NEW_BINDING
79 select TQM85xx 74 select TQM85xx
80 select CPM2 75 select CPM2
81 76
@@ -84,7 +79,6 @@ config TQM8555
84 help 79 help
85 This option enables support for the TQ Components TQM8555 board. 80 This option enables support for the TQ Components TQM8555 board.
86 select DEFAULT_UIMAGE 81 select DEFAULT_UIMAGE
87 select PPC_CPM_NEW_BINDING
88 select TQM85xx 82 select TQM85xx
89 select CPM2 83 select CPM2
90 84
@@ -93,7 +87,6 @@ config TQM8560
93 help 87 help
94 This option enables support for the TQ Components TQM8560 board. 88 This option enables support for the TQ Components TQM8560 board.
95 select DEFAULT_UIMAGE 89 select DEFAULT_UIMAGE
96 select PPC_CPM_NEW_BINDING
97 select TQM85xx 90 select TQM85xx
98 select CPM2 91 select CPM2
99 92
@@ -106,7 +99,6 @@ config SBC8548
106config SBC8560 99config SBC8560
107 bool "Wind River SBC8560" 100 bool "Wind River SBC8560"
108 select DEFAULT_UIMAGE 101 select DEFAULT_UIMAGE
109 select PPC_CPM_NEW_BINDING if CPM2
110 help 102 help
111 This option enables support for the Wind River SBC8560 board 103 This option enables support for the Wind River SBC8560 board
112 104
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 4e0305096114..3582c841844b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -165,7 +165,7 @@ static void __init init_ioports(void)
165 int i; 165 int i;
166 166
167 for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) { 167 for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
168 struct cpm_pin *pin = &mpc8560_ads_pins[i]; 168 const struct cpm_pin *pin = &mpc8560_ads_pins[i];
169 cpm2_set_pin(pin->port, pin->pin, pin->flags); 169 cpm2_set_pin(pin->port, pin->pin, pin->flags);
170 } 170 }
171 171
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 2865d019afc3..dfd8b4ad9b28 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -19,6 +19,7 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/seq_file.h> 20#include <linux/seq_file.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/of_platform.h>
22 23
23#include <asm/system.h> 24#include <asm/system.h>
24#include <asm/time.h> 25#include <asm/time.h>
@@ -183,6 +184,18 @@ static int __init mpc8544_ds_probe(void)
183 } 184 }
184} 185}
185 186
187static struct of_device_id mpc85xxds_ids[] = {
188 { .type = "soc", },
189 { .compatible = "soc", },
190 {},
191};
192
193static int __init mpc85xxds_publish_devices(void)
194{
195 return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
196}
197machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
198
186/* 199/*
187 * Called very early, device-tree isn't unflattened 200 * Called very early, device-tree isn't unflattened
188 */ 201 */
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 21d113536b86..7442c58d44f5 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -11,6 +11,12 @@ config MPC8641_HPCN
11 help 11 help
12 This option enables support for the MPC8641 HPCN board. 12 This option enables support for the MPC8641 HPCN board.
13 13
14config SBC8641D
15 bool "Wind River SBC8641D"
16 select DEFAULT_UIMAGE
17 help
18 This option enables support for the WRS SBC8641D board.
19
14config MPC8610_HPCD 20config MPC8610_HPCD
15 bool "Freescale MPC8610 HPCD" 21 bool "Freescale MPC8610 HPCD"
16 select DEFAULT_UIMAGE 22 select DEFAULT_UIMAGE
@@ -24,7 +30,7 @@ config MPC8641
24 select FSL_PCI if PCI 30 select FSL_PCI if PCI
25 select PPC_UDBG_16550 31 select PPC_UDBG_16550
26 select MPIC 32 select MPIC
27 default y if MPC8641_HPCN 33 default y if MPC8641_HPCN || SBC8641D
28 34
29config MPC8610 35config MPC8610
30 bool 36 bool
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index c96706327eaa..1b9b4a9b2525 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -4,4 +4,5 @@
4 4
5obj-$(CONFIG_SMP) += mpc86xx_smp.o 5obj-$(CONFIG_SMP) += mpc86xx_smp.o
6obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o 6obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
7obj-$(CONFIG_SBC8641D) += sbc8641d.o
7obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o 8obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 0b07485641fe..18b8ebe930d5 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -52,7 +52,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
52} 52}
53machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices); 53machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
54 54
55void __init 55static void __init
56mpc86xx_hpcd_init_irq(void) 56mpc86xx_hpcd_init_irq(void)
57{ 57{
58 struct mpic *mpic1; 58 struct mpic *mpic1;
@@ -200,7 +200,7 @@ static int __init mpc86xx_hpcd_probe(void)
200 return 0; 200 return 0;
201} 201}
202 202
203long __init 203static long __init
204mpc86xx_time_init(void) 204mpc86xx_time_init(void)
205{ 205{
206 unsigned int temp; 206 unsigned int temp;
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index cfbe8c52e263..f947f555fd46 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -55,7 +55,7 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
55} 55}
56#endif /* CONFIG_PCI */ 56#endif /* CONFIG_PCI */
57 57
58void __init 58static void __init
59mpc86xx_hpcn_init_irq(void) 59mpc86xx_hpcn_init_irq(void)
60{ 60{
61 struct mpic *mpic1; 61 struct mpic *mpic1;
@@ -162,7 +162,7 @@ mpc86xx_hpcn_setup_arch(void)
162} 162}
163 163
164 164
165void 165static void
166mpc86xx_hpcn_show_cpuinfo(struct seq_file *m) 166mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
167{ 167{
168 struct device_node *root; 168 struct device_node *root;
@@ -190,13 +190,19 @@ static int __init mpc86xx_hpcn_probe(void)
190{ 190{
191 unsigned long root = of_get_flat_dt_root(); 191 unsigned long root = of_get_flat_dt_root();
192 192
193 if (of_flat_dt_is_compatible(root, "mpc86xx")) 193 if (of_flat_dt_is_compatible(root, "fsl,mpc8641hpcn"))
194 return 1; /* Looks good */ 194 return 1; /* Looks good */
195 195
196 /* Be nice and don't give silent boot death. Delete this in 2.6.27 */
197 if (of_flat_dt_is_compatible(root, "mpc86xx")) {
198 pr_warning("WARNING: your dts/dtb is old. You must update before the next kernel release\n");
199 return 1;
200 }
201
196 return 0; 202 return 0;
197} 203}
198 204
199long __init 205static long __init
200mpc86xx_time_init(void) 206mpc86xx_time_init(void)
201{ 207{
202 unsigned int temp; 208 unsigned int temp;
diff --git a/arch/powerpc/platforms/86xx/sbc8641d.c b/arch/powerpc/platforms/86xx/sbc8641d.c
new file mode 100644
index 000000000000..510a06ef0b55
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/sbc8641d.c
@@ -0,0 +1,164 @@
1/*
2 * SBC8641D board specific routines
3 *
4 * Copyright 2008 Wind River Systems Inc.
5 *
6 * By Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * Based largely on the 8641 HPCN support by Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/delay.h>
21#include <linux/seq_file.h>
22#include <linux/of_platform.h>
23
24#include <asm/system.h>
25#include <asm/time.h>
26#include <asm/machdep.h>
27#include <asm/pci-bridge.h>
28#include <asm/mpc86xx.h>
29#include <asm/prom.h>
30#include <mm/mmu_decl.h>
31#include <asm/udbg.h>
32
33#include <asm/mpic.h>
34
35#include <sysdev/fsl_pci.h>
36#include <sysdev/fsl_soc.h>
37
38#include "mpc86xx.h"
39
40static void __init
41sbc8641_init_irq(void)
42{
43 struct mpic *mpic1;
44 struct device_node *np;
45 struct resource res;
46
47 /* Determine PIC address. */
48 np = of_find_node_by_type(NULL, "open-pic");
49 if (np == NULL)
50 return;
51 of_address_to_resource(np, 0, &res);
52
53 /* Alloc mpic structure and per isu has 16 INT entries. */
54 mpic1 = mpic_alloc(np, res.start,
55 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
56 0, 256, " MPIC ");
57 of_node_put(np);
58 BUG_ON(mpic1 == NULL);
59
60 mpic_init(mpic1);
61}
62
63static void __init
64sbc8641_setup_arch(void)
65{
66#ifdef CONFIG_PCI
67 struct device_node *np;
68#endif
69
70 if (ppc_md.progress)
71 ppc_md.progress("sbc8641_setup_arch()", 0);
72
73#ifdef CONFIG_PCI
74 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie")
75 fsl_add_bridge(np, 0);
76#endif
77
78 printk("SBC8641 board from Wind River\n");
79
80#ifdef CONFIG_SMP
81 mpc86xx_smp_init();
82#endif
83}
84
85
86static void
87sbc8641_show_cpuinfo(struct seq_file *m)
88{
89 struct device_node *root;
90 uint memsize = total_memory;
91 const char *model = "";
92 uint svid = mfspr(SPRN_SVR);
93
94 seq_printf(m, "Vendor\t\t: Wind River Systems\n");
95
96 root = of_find_node_by_path("/");
97 if (root)
98 model = of_get_property(root, "model", NULL);
99 seq_printf(m, "Machine\t\t: %s\n", model);
100 of_node_put(root);
101
102 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
103 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
104}
105
106
107/*
108 * Called very early, device-tree isn't unflattened
109 */
110static int __init sbc8641_probe(void)
111{
112 unsigned long root = of_get_flat_dt_root();
113
114 if (of_flat_dt_is_compatible(root, "wind,sbc8641"))
115 return 1; /* Looks good */
116
117 return 0;
118}
119
120static long __init
121mpc86xx_time_init(void)
122{
123 unsigned int temp;
124
125 /* Set the time base to zero */
126 mtspr(SPRN_TBWL, 0);
127 mtspr(SPRN_TBWU, 0);
128
129 temp = mfspr(SPRN_HID0);
130 temp |= HID0_TBEN;
131 mtspr(SPRN_HID0, temp);
132 asm volatile("isync");
133
134 return 0;
135}
136
137static __initdata struct of_device_id of_bus_ids[] = {
138 { .compatible = "simple-bus", },
139 {},
140};
141
142static int __init declare_of_platform_devices(void)
143{
144 of_platform_bus_probe(NULL, of_bus_ids, NULL);
145
146 return 0;
147}
148machine_device_initcall(sbc8641, declare_of_platform_devices);
149
150define_machine(sbc8641) {
151 .name = "SBC8641D",
152 .probe = sbc8641_probe,
153 .setup_arch = sbc8641_setup_arch,
154 .init_IRQ = sbc8641_init_irq,
155 .show_cpuinfo = sbc8641_show_cpuinfo,
156 .get_irq = mpic_get_irq,
157 .restart = fsl_rstcr_restart,
158 .time_init = mpc86xx_time_init,
159 .calibrate_decr = generic_calibrate_decr,
160 .progress = udbg_progress,
161#ifdef CONFIG_PCI
162 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
163#endif
164};
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 7fd224ca233d..6fc849e51e48 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -18,7 +18,6 @@ config MPC8XXFADS
18config MPC86XADS 18config MPC86XADS
19 bool "MPC86XADS" 19 bool "MPC86XADS"
20 select CPM1 20 select CPM1
21 select PPC_CPM_NEW_BINDING
22 help 21 help
23 MPC86x Application Development System by Freescale Semiconductor. 22 MPC86x Application Development System by Freescale Semiconductor.
24 The MPC86xADS is meant to serve as a platform for s/w and h/w 23 The MPC86xADS is meant to serve as a platform for s/w and h/w
@@ -27,7 +26,6 @@ config MPC86XADS
27config MPC885ADS 26config MPC885ADS
28 bool "MPC885ADS" 27 bool "MPC885ADS"
29 select CPM1 28 select CPM1
30 select PPC_CPM_NEW_BINDING
31 help 29 help
32 Freescale Semiconductor MPC885 Application Development System (ADS). 30 Freescale Semiconductor MPC885 Application Development System (ADS).
33 Also known as DUET. 31 Also known as DUET.
@@ -37,7 +35,6 @@ config MPC885ADS
37config PPC_EP88XC 35config PPC_EP88XC
38 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)" 36 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
39 select CPM1 37 select CPM1
40 select PPC_CPM_NEW_BINDING
41 help 38 help
42 This enables support for the Embedded Planet EP88xC board. 39 This enables support for the Embedded Planet EP88xC board.
43 40
@@ -47,7 +44,6 @@ config PPC_EP88XC
47config PPC_ADDER875 44config PPC_ADDER875
48 bool "Analogue & Micro Adder 875" 45 bool "Analogue & Micro Adder 875"
49 select CPM1 46 select CPM1
50 select PPC_CPM_NEW_BINDING
51 select REDBOOT 47 select REDBOOT
52 help 48 help
53 This enables support for the Analogue & Micro Adder 875 49 This enables support for the Analogue & Micro Adder 875
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index a578b966ecbc..f38c50b4ce56 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -290,13 +290,7 @@ config CPM2
290config PPC_CPM_NEW_BINDING 290config PPC_CPM_NEW_BINDING
291 bool 291 bool
292 depends on CPM1 || CPM2 292 depends on CPM1 || CPM2
293 help 293 default y
294 Select this if your board has been converted to use the new
295 device tree bindings for CPM, and no longer needs the
296 ioport callbacks or the platform device glue code.
297
298 The fs_enet and cpm_uart drivers will be built as
299 of_platform devices.
300 294
301config AXON_RAM 295config AXON_RAM
302 tristate "Axon DDR2 memory device driver" 296 tristate "Axon DDR2 memory device driver"
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 851a0be71947..6d386d0071a0 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
12obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 12obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
13obj-$(CONFIG_FSL_SOC) += fsl_soc.o 13obj-$(CONFIG_FSL_SOC) += fsl_soc.o
14obj-$(CONFIG_FSL_PCI) += fsl_pci.o 14obj-$(CONFIG_FSL_PCI) += fsl_pci.o
15obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
15obj-$(CONFIG_RAPIDIO) += fsl_rio.o 16obj-$(CONFIG_RAPIDIO) += fsl_rio.o
16obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 17obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
17obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 18obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 3eceeb5f3ee7..58292a086c16 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -44,9 +44,6 @@
44 44
45#define CPM_MAP_SIZE (0x4000) 45#define CPM_MAP_SIZE (0x4000)
46 46
47#ifndef CONFIG_PPC_CPM_NEW_BINDING
48static void m8xx_cpm_dpinit(void);
49#endif
50cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ 47cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
51immap_t __iomem *mpc8xx_immr; 48immap_t __iomem *mpc8xx_immr;
52static cpic8xx_t __iomem *cpic_reg; 49static cpic8xx_t __iomem *cpic_reg;
@@ -229,12 +226,7 @@ void __init cpm_reset(void)
229 out_be32(&siu_conf->sc_sdcr, 1); 226 out_be32(&siu_conf->sc_sdcr, 1);
230 immr_unmap(siu_conf); 227 immr_unmap(siu_conf);
231 228
232#ifdef CONFIG_PPC_CPM_NEW_BINDING
233 cpm_muram_init(); 229 cpm_muram_init();
234#else
235 /* Reclaim the DP memory for our use. */
236 m8xx_cpm_dpinit();
237#endif
238} 230}
239 231
240static DEFINE_SPINLOCK(cmd_lock); 232static DEFINE_SPINLOCK(cmd_lock);
@@ -293,110 +285,6 @@ cpm_setbrg(uint brg, uint rate)
293 CPM_BRG_EN | CPM_BRG_DIV16); 285 CPM_BRG_EN | CPM_BRG_DIV16);
294} 286}
295 287
296#ifndef CONFIG_PPC_CPM_NEW_BINDING
297/*
298 * dpalloc / dpfree bits.
299 */
300static spinlock_t cpm_dpmem_lock;
301/*
302 * 16 blocks should be enough to satisfy all requests
303 * until the memory subsystem goes up...
304 */
305static rh_block_t cpm_boot_dpmem_rh_block[16];
306static rh_info_t cpm_dpmem_info;
307
308#define CPM_DPMEM_ALIGNMENT 8
309static u8 __iomem *dpram_vbase;
310static phys_addr_t dpram_pbase;
311
312static void m8xx_cpm_dpinit(void)
313{
314 spin_lock_init(&cpm_dpmem_lock);
315
316 dpram_vbase = cpmp->cp_dpmem;
317 dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
318
319 /* Initialize the info header */
320 rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
321 sizeof(cpm_boot_dpmem_rh_block) /
322 sizeof(cpm_boot_dpmem_rh_block[0]),
323 cpm_boot_dpmem_rh_block);
324
325 /*
326 * Attach the usable dpmem area.
327 * XXX: This is actually crap. CPM_DATAONLY_BASE and
328 * CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
329 * with the processor and the microcode patches applied / activated.
330 * But the following should be at least safe.
331 */
332 rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
333}
334
335/*
336 * Allocate the requested size worth of DP memory.
337 * This function returns an offset into the DPRAM area.
338 * Use cpm_dpram_addr() to get the virtual address of the area.
339 */
340unsigned long cpm_dpalloc(uint size, uint align)
341{
342 unsigned long start;
343 unsigned long flags;
344
345 spin_lock_irqsave(&cpm_dpmem_lock, flags);
346 cpm_dpmem_info.alignment = align;
347 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
348 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
349
350 return (uint)start;
351}
352EXPORT_SYMBOL(cpm_dpalloc);
353
354int cpm_dpfree(unsigned long offset)
355{
356 int ret;
357 unsigned long flags;
358
359 spin_lock_irqsave(&cpm_dpmem_lock, flags);
360 ret = rh_free(&cpm_dpmem_info, offset);
361 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
362
363 return ret;
364}
365EXPORT_SYMBOL(cpm_dpfree);
366
367unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
368{
369 unsigned long start;
370 unsigned long flags;
371
372 spin_lock_irqsave(&cpm_dpmem_lock, flags);
373 cpm_dpmem_info.alignment = align;
374 start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
375 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
376
377 return start;
378}
379EXPORT_SYMBOL(cpm_dpalloc_fixed);
380
381void cpm_dpdump(void)
382{
383 rh_dump(&cpm_dpmem_info);
384}
385EXPORT_SYMBOL(cpm_dpdump);
386
387void *cpm_dpram_addr(unsigned long offset)
388{
389 return (void *)(dpram_vbase + offset);
390}
391EXPORT_SYMBOL(cpm_dpram_addr);
392
393uint cpm_dpram_phys(u8 *addr)
394{
395 return (dpram_pbase + (uint)(addr - dpram_vbase));
396}
397EXPORT_SYMBOL(cpm_dpram_phys);
398#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
399
400struct cpm_ioport16 { 288struct cpm_ioport16 {
401 __be16 dir, par, odr_sor, dat, intr; 289 __be16 dir, par, odr_sor, dat, intr;
402 __be16 res[3]; 290 __be16 res[3];
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index fa70ee31349e..5a6c5dfc53ef 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -46,10 +46,6 @@
46 46
47#include <sysdev/fsl_soc.h> 47#include <sysdev/fsl_soc.h>
48 48
49#ifndef CONFIG_PPC_CPM_NEW_BINDING
50static void cpm2_dpinit(void);
51#endif
52
53cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */ 49cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
54 50
55/* We allocate this here because it is used almost exclusively for 51/* We allocate this here because it is used almost exclusively for
@@ -71,15 +67,17 @@ void __init cpm2_reset(void)
71 67
72 /* Reclaim the DP memory for our use. 68 /* Reclaim the DP memory for our use.
73 */ 69 */
74#ifdef CONFIG_PPC_CPM_NEW_BINDING
75 cpm_muram_init(); 70 cpm_muram_init();
76#else
77 cpm2_dpinit();
78#endif
79 71
80 /* Tell everyone where the comm processor resides. 72 /* Tell everyone where the comm processor resides.
81 */ 73 */
82 cpmp = &cpm2_immr->im_cpm; 74 cpmp = &cpm2_immr->im_cpm;
75
76#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
77 /* Reset the CPM.
78 */
79 cpm_command(CPM_CR_RST, 0);
80#endif
83} 81}
84 82
85static DEFINE_SPINLOCK(cmd_lock); 83static DEFINE_SPINLOCK(cmd_lock);
@@ -347,95 +345,6 @@ int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
347 return ret; 345 return ret;
348} 346}
349 347
350#ifndef CONFIG_PPC_CPM_NEW_BINDING
351/*
352 * dpalloc / dpfree bits.
353 */
354static spinlock_t cpm_dpmem_lock;
355/* 16 blocks should be enough to satisfy all requests
356 * until the memory subsystem goes up... */
357static rh_block_t cpm_boot_dpmem_rh_block[16];
358static rh_info_t cpm_dpmem_info;
359static u8 __iomem *im_dprambase;
360
361static void cpm2_dpinit(void)
362{
363 spin_lock_init(&cpm_dpmem_lock);
364
365 /* initialize the info header */
366 rh_init(&cpm_dpmem_info, 1,
367 sizeof(cpm_boot_dpmem_rh_block) /
368 sizeof(cpm_boot_dpmem_rh_block[0]),
369 cpm_boot_dpmem_rh_block);
370
371 im_dprambase = cpm2_immr;
372
373 /* Attach the usable dpmem area */
374 /* XXX: This is actually crap. CPM_DATAONLY_BASE and
375 * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
376 * varies with the processor and the microcode patches activated.
377 * But the following should be at least safe.
378 */
379 rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
380}
381
382/* This function returns an index into the DPRAM area.
383 */
384unsigned long cpm_dpalloc(uint size, uint align)
385{
386 unsigned long start;
387 unsigned long flags;
388
389 spin_lock_irqsave(&cpm_dpmem_lock, flags);
390 cpm_dpmem_info.alignment = align;
391 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
392 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
393
394 return (uint)start;
395}
396EXPORT_SYMBOL(cpm_dpalloc);
397
398int cpm_dpfree(unsigned long offset)
399{
400 int ret;
401 unsigned long flags;
402
403 spin_lock_irqsave(&cpm_dpmem_lock, flags);
404 ret = rh_free(&cpm_dpmem_info, offset);
405 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
406
407 return ret;
408}
409EXPORT_SYMBOL(cpm_dpfree);
410
411/* not sure if this is ever needed */
412unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
413{
414 unsigned long start;
415 unsigned long flags;
416
417 spin_lock_irqsave(&cpm_dpmem_lock, flags);
418 cpm_dpmem_info.alignment = align;
419 start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
420 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
421
422 return start;
423}
424EXPORT_SYMBOL(cpm_dpalloc_fixed);
425
426void cpm_dpdump(void)
427{
428 rh_dump(&cpm_dpmem_info);
429}
430EXPORT_SYMBOL(cpm_dpdump);
431
432void *cpm_dpram_addr(unsigned long offset)
433{
434 return (void *)(im_dprambase + offset);
435}
436EXPORT_SYMBOL(cpm_dpram_addr);
437#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
438
439struct cpm2_ioports { 348struct cpm2_ioports {
440 u32 dir, par, sor, odr, dat; 349 u32 dir, par, sor, odr, dat;
441 u32 res[3]; 350 u32 res[3];
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 165981c87786..cb7df2dce44f 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -58,7 +58,6 @@ void __init udbg_init_cpm(void)
58} 58}
59#endif 59#endif
60 60
61#ifdef CONFIG_PPC_CPM_NEW_BINDING
62static spinlock_t cpm_muram_lock; 61static spinlock_t cpm_muram_lock;
63static rh_block_t cpm_boot_muram_rh_block[16]; 62static rh_block_t cpm_boot_muram_rh_block[16];
64static rh_info_t cpm_muram_info; 63static rh_info_t cpm_muram_info;
@@ -199,5 +198,3 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
199 return muram_pbase + ((u8 __iomem *)addr - muram_vbase); 198 return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
200} 199}
201EXPORT_SYMBOL(cpm_muram_dma); 200EXPORT_SYMBOL(cpm_muram_dma);
202
203#endif /* CONFIG_PPC_CPM_NEW_BINDING */
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
new file mode 100644
index 000000000000..422c8faef593
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -0,0 +1,129 @@
1/*
2 * Freescale LBC and UPM routines.
3 *
4 * Copyright (c) 2007-2008 MontaVista Software, Inc.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/of.h>
16#include <asm/fsl_lbc.h>
17
18spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
19
20struct fsl_lbc_regs __iomem *fsl_lbc_regs;
21EXPORT_SYMBOL(fsl_lbc_regs);
22
23static char __initdata *compat_lbc[] = {
24 "fsl,pq2-localbus",
25 "fsl,pq2pro-localbus",
26 "fsl,pq3-localbus",
27 "fsl,elbc",
28};
29
30static int __init fsl_lbc_init(void)
31{
32 struct device_node *lbus;
33 int i;
34
35 for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
36 lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
37 if (lbus)
38 goto found;
39 }
40 return -ENODEV;
41
42found:
43 fsl_lbc_regs = of_iomap(lbus, 0);
44 of_node_put(lbus);
45 if (!fsl_lbc_regs)
46 return -ENOMEM;
47 return 0;
48}
49arch_initcall(fsl_lbc_init);
50
51/**
52 * fsl_lbc_find - find Localbus bank
53 * @addr_base: base address of the memory bank
54 *
55 * This function walks LBC banks comparing "Base address" field of the BR
56 * registers with the supplied addr_base argument. When bases match this
57 * function returns bank number (starting with 0), otherwise it returns
58 * appropriate errno value.
59 */
60int fsl_lbc_find(phys_addr_t addr_base)
61{
62 int i;
63
64 if (!fsl_lbc_regs)
65 return -ENODEV;
66
67 for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
68 __be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
69 __be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
70
71 if (br & BR_V && (br & or & BR_BA) == addr_base)
72 return i;
73 }
74
75 return -ENOENT;
76}
77EXPORT_SYMBOL(fsl_lbc_find);
78
79/**
80 * fsl_upm_find - find pre-programmed UPM via base address
81 * @addr_base: base address of the memory bank controlled by the UPM
82 * @upm: pointer to the allocated fsl_upm structure
83 *
84 * This function fills fsl_upm structure so you can use it with the rest of
85 * UPM API. On success this function returns 0, otherwise it returns
86 * appropriate errno value.
87 */
88int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
89{
90 int bank;
91 __be32 br;
92
93 bank = fsl_lbc_find(addr_base);
94 if (bank < 0)
95 return bank;
96
97 br = in_be32(&fsl_lbc_regs->bank[bank].br);
98
99 switch (br & BR_MSEL) {
100 case BR_MS_UPMA:
101 upm->mxmr = &fsl_lbc_regs->mamr;
102 break;
103 case BR_MS_UPMB:
104 upm->mxmr = &fsl_lbc_regs->mbmr;
105 break;
106 case BR_MS_UPMC:
107 upm->mxmr = &fsl_lbc_regs->mcmr;
108 break;
109 default:
110 return -EINVAL;
111 }
112
113 switch (br & BR_PS) {
114 case BR_PS_8:
115 upm->width = 8;
116 break;
117 case BR_PS_16:
118 upm->width = 16;
119 break;
120 case BR_PS_32:
121 upm->width = 32;
122 break;
123 default:
124 return -EINVAL;
125 }
126
127 return 0;
128}
129EXPORT_SYMBOL(fsl_upm_find);
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 2c5388ce902a..b6d6bdae95f2 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -75,6 +75,33 @@ phys_addr_t get_immrbase(void)
75 75
76EXPORT_SYMBOL(get_immrbase); 76EXPORT_SYMBOL(get_immrbase);
77 77
78static u32 sysfreq = -1;
79
80u32 fsl_get_sys_freq(void)
81{
82 struct device_node *soc;
83 const u32 *prop;
84 int size;
85
86 if (sysfreq != -1)
87 return sysfreq;
88
89 soc = of_find_node_by_type(NULL, "soc");
90 if (!soc)
91 return -1;
92
93 prop = of_get_property(soc, "clock-frequency", &size);
94 if (!prop || size != sizeof(*prop) || *prop == 0)
95 prop = of_get_property(soc, "bus-frequency", &size);
96
97 if (prop && size == sizeof(*prop))
98 sysfreq = *prop;
99
100 of_node_put(soc);
101 return sysfreq;
102}
103EXPORT_SYMBOL(fsl_get_sys_freq);
104
78#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx) 105#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
79 106
80static u32 brgfreq = -1; 107static u32 brgfreq = -1;
@@ -516,9 +543,9 @@ arch_initcall(fsl_i2c_of_init);
516static int __init mpc83xx_wdt_init(void) 543static int __init mpc83xx_wdt_init(void)
517{ 544{
518 struct resource r; 545 struct resource r;
519 struct device_node *soc, *np; 546 struct device_node *np;
520 struct platform_device *dev; 547 struct platform_device *dev;
521 const unsigned int *freq; 548 u32 freq = fsl_get_sys_freq();
522 int ret; 549 int ret;
523 550
524 np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt"); 551 np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
@@ -528,19 +555,6 @@ static int __init mpc83xx_wdt_init(void)
528 goto nodev; 555 goto nodev;
529 } 556 }
530 557
531 soc = of_find_node_by_type(NULL, "soc");
532
533 if (!soc) {
534 ret = -ENODEV;
535 goto nosoc;
536 }
537
538 freq = of_get_property(soc, "bus-frequency", NULL);
539 if (!freq) {
540 ret = -ENODEV;
541 goto err;
542 }
543
544 memset(&r, 0, sizeof(r)); 558 memset(&r, 0, sizeof(r));
545 559
546 ret = of_address_to_resource(np, 0, &r); 560 ret = of_address_to_resource(np, 0, &r);
@@ -553,20 +567,16 @@ static int __init mpc83xx_wdt_init(void)
553 goto err; 567 goto err;
554 } 568 }
555 569
556 ret = platform_device_add_data(dev, freq, sizeof(int)); 570 ret = platform_device_add_data(dev, &freq, sizeof(freq));
557 if (ret) 571 if (ret)
558 goto unreg; 572 goto unreg;
559 573
560 of_node_put(soc);
561 of_node_put(np); 574 of_node_put(np);
562
563 return 0; 575 return 0;
564 576
565unreg: 577unreg:
566 platform_device_unregister(dev); 578 platform_device_unregister(dev);
567err: 579err:
568 of_node_put(soc);
569nosoc:
570 of_node_put(np); 580 of_node_put(np);
571nodev: 581nodev:
572 return ret; 582 return ret;
@@ -735,547 +745,6 @@ err:
735 745
736arch_initcall(fsl_usb_of_init); 746arch_initcall(fsl_usb_of_init);
737 747
738#ifndef CONFIG_PPC_CPM_NEW_BINDING
739#ifdef CONFIG_CPM2
740
741extern void init_scc_ioports(struct fs_uart_platform_info*);
742
743static const char fcc_regs[] = "fcc_regs";
744static const char fcc_regs_c[] = "fcc_regs_c";
745static const char fcc_pram[] = "fcc_pram";
746static char bus_id[9][BUS_ID_SIZE];
747
748static int __init fs_enet_of_init(void)
749{
750 struct device_node *np;
751 unsigned int i;
752 struct platform_device *fs_enet_dev;
753 struct resource res;
754 int ret;
755
756 for (np = NULL, i = 0;
757 (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
758 i++) {
759 struct resource r[4];
760 struct device_node *phy, *mdio;
761 struct fs_platform_info fs_enet_data;
762 const unsigned int *id, *phy_addr, *phy_irq;
763 const void *mac_addr;
764 const phandle *ph;
765 const char *model;
766
767 memset(r, 0, sizeof(r));
768 memset(&fs_enet_data, 0, sizeof(fs_enet_data));
769
770 ret = of_address_to_resource(np, 0, &r[0]);
771 if (ret)
772 goto err;
773 r[0].name = fcc_regs;
774
775 ret = of_address_to_resource(np, 1, &r[1]);
776 if (ret)
777 goto err;
778 r[1].name = fcc_pram;
779
780 ret = of_address_to_resource(np, 2, &r[2]);
781 if (ret)
782 goto err;
783 r[2].name = fcc_regs_c;
784 fs_enet_data.fcc_regs_c = r[2].start;
785
786 of_irq_to_resource(np, 0, &r[3]);
787
788 fs_enet_dev =
789 platform_device_register_simple("fsl-cpm-fcc", i, &r[0], 4);
790
791 if (IS_ERR(fs_enet_dev)) {
792 ret = PTR_ERR(fs_enet_dev);
793 goto err;
794 }
795
796 model = of_get_property(np, "model", NULL);
797 if (model == NULL) {
798 ret = -ENODEV;
799 goto unreg;
800 }
801
802 mac_addr = of_get_mac_address(np);
803 if (mac_addr)
804 memcpy(fs_enet_data.macaddr, mac_addr, 6);
805
806 ph = of_get_property(np, "phy-handle", NULL);
807 phy = of_find_node_by_phandle(*ph);
808
809 if (phy == NULL) {
810 ret = -ENODEV;
811 goto unreg;
812 }
813
814 phy_addr = of_get_property(phy, "reg", NULL);
815 fs_enet_data.phy_addr = *phy_addr;
816
817 phy_irq = of_get_property(phy, "interrupts", NULL);
818
819 id = of_get_property(np, "device-id", NULL);
820 fs_enet_data.fs_no = *id;
821 strcpy(fs_enet_data.fs_type, model);
822
823 mdio = of_get_parent(phy);
824 ret = of_address_to_resource(mdio, 0, &res);
825 if (ret) {
826 of_node_put(phy);
827 of_node_put(mdio);
828 goto unreg;
829 }
830
831 fs_enet_data.clk_rx = *((u32 *)of_get_property(np,
832 "rx-clock", NULL));
833 fs_enet_data.clk_tx = *((u32 *)of_get_property(np,
834 "tx-clock", NULL));
835
836 if (strstr(model, "FCC")) {
837 int fcc_index = *id - 1;
838 const unsigned char *mdio_bb_prop;
839
840 fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
841 fs_enet_data.rx_ring = 32;
842 fs_enet_data.tx_ring = 32;
843 fs_enet_data.rx_copybreak = 240;
844 fs_enet_data.use_napi = 0;
845 fs_enet_data.napi_weight = 17;
846 fs_enet_data.mem_offset = FCC_MEM_OFFSET(fcc_index);
847 fs_enet_data.cp_page = CPM_CR_FCC_PAGE(fcc_index);
848 fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
849
850 snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
851 (u32)res.start, fs_enet_data.phy_addr);
852 fs_enet_data.bus_id = (char*)&bus_id[(*id)];
853 fs_enet_data.init_ioports = init_fcc_ioports;
854
855 mdio_bb_prop = of_get_property(phy, "bitbang", NULL);
856 if (mdio_bb_prop) {
857 struct platform_device *fs_enet_mdio_bb_dev;
858 struct fs_mii_bb_platform_info fs_enet_mdio_bb_data;
859
860 fs_enet_mdio_bb_dev =
861 platform_device_register_simple("fsl-bb-mdio",
862 i, NULL, 0);
863 memset(&fs_enet_mdio_bb_data, 0,
864 sizeof(struct fs_mii_bb_platform_info));
865 fs_enet_mdio_bb_data.mdio_dat.bit =
866 mdio_bb_prop[0];
867 fs_enet_mdio_bb_data.mdio_dir.bit =
868 mdio_bb_prop[1];
869 fs_enet_mdio_bb_data.mdc_dat.bit =
870 mdio_bb_prop[2];
871 fs_enet_mdio_bb_data.mdio_port =
872 mdio_bb_prop[3];
873 fs_enet_mdio_bb_data.mdc_port =
874 mdio_bb_prop[4];
875 fs_enet_mdio_bb_data.delay =
876 mdio_bb_prop[5];
877
878 fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
879 fs_enet_mdio_bb_data.irq[1] = -1;
880 fs_enet_mdio_bb_data.irq[2] = -1;
881 fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
882 fs_enet_mdio_bb_data.irq[31] = -1;
883
884 fs_enet_mdio_bb_data.mdio_dat.offset =
885 (u32)&cpm2_immr->im_ioport.iop_pdatc;
886 fs_enet_mdio_bb_data.mdio_dir.offset =
887 (u32)&cpm2_immr->im_ioport.iop_pdirc;
888 fs_enet_mdio_bb_data.mdc_dat.offset =
889 (u32)&cpm2_immr->im_ioport.iop_pdatc;
890
891 ret = platform_device_add_data(
892 fs_enet_mdio_bb_dev,
893 &fs_enet_mdio_bb_data,
894 sizeof(struct fs_mii_bb_platform_info));
895 if (ret)
896 goto unreg;
897 }
898
899 of_node_put(phy);
900 of_node_put(mdio);
901
902 ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
903 sizeof(struct
904 fs_platform_info));
905 if (ret)
906 goto unreg;
907 }
908 }
909 return 0;
910
911unreg:
912 platform_device_unregister(fs_enet_dev);
913err:
914 return ret;
915}
916
917arch_initcall(fs_enet_of_init);
918
919static const char scc_regs[] = "regs";
920static const char scc_pram[] = "pram";
921
922static int __init cpm_uart_of_init(void)
923{
924 struct device_node *np;
925 unsigned int i;
926 struct platform_device *cpm_uart_dev;
927 int ret;
928
929 for (np = NULL, i = 0;
930 (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
931 i++) {
932 struct resource r[3];
933 struct fs_uart_platform_info cpm_uart_data;
934 const int *id;
935 const char *model;
936
937 memset(r, 0, sizeof(r));
938 memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
939
940 ret = of_address_to_resource(np, 0, &r[0]);
941 if (ret)
942 goto err;
943
944 r[0].name = scc_regs;
945
946 ret = of_address_to_resource(np, 1, &r[1]);
947 if (ret)
948 goto err;
949 r[1].name = scc_pram;
950
951 of_irq_to_resource(np, 0, &r[2]);
952
953 cpm_uart_dev =
954 platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
955
956 if (IS_ERR(cpm_uart_dev)) {
957 ret = PTR_ERR(cpm_uart_dev);
958 goto err;
959 }
960
961 id = of_get_property(np, "device-id", NULL);
962 cpm_uart_data.fs_no = *id;
963
964 model = of_get_property(np, "model", NULL);
965 strcpy(cpm_uart_data.fs_type, model);
966
967 cpm_uart_data.uart_clk = ppc_proc_freq;
968
969 cpm_uart_data.tx_num_fifo = 4;
970 cpm_uart_data.tx_buf_size = 32;
971 cpm_uart_data.rx_num_fifo = 4;
972 cpm_uart_data.rx_buf_size = 32;
973 cpm_uart_data.clk_rx = *((u32 *)of_get_property(np,
974 "rx-clock", NULL));
975 cpm_uart_data.clk_tx = *((u32 *)of_get_property(np,
976 "tx-clock", NULL));
977
978 ret =
979 platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
980 sizeof(struct
981 fs_uart_platform_info));
982 if (ret)
983 goto unreg;
984 }
985
986 return 0;
987
988unreg:
989 platform_device_unregister(cpm_uart_dev);
990err:
991 return ret;
992}
993
994arch_initcall(cpm_uart_of_init);
995#endif /* CONFIG_CPM2 */
996
997#ifdef CONFIG_8xx
998
999extern void init_scc_ioports(struct fs_platform_info*);
1000extern int platform_device_skip(const char *model, int id);
1001
1002static int __init fs_enet_mdio_of_init(void)
1003{
1004 struct device_node *np;
1005 unsigned int i;
1006 struct platform_device *mdio_dev;
1007 struct resource res;
1008 int ret;
1009
1010 for (np = NULL, i = 0;
1011 (np = of_find_compatible_node(np, "mdio", "fs_enet")) != NULL;
1012 i++) {
1013 struct fs_mii_fec_platform_info mdio_data;
1014
1015 memset(&res, 0, sizeof(res));
1016 memset(&mdio_data, 0, sizeof(mdio_data));
1017
1018 ret = of_address_to_resource(np, 0, &res);
1019 if (ret)
1020 goto err;
1021
1022 mdio_dev =
1023 platform_device_register_simple("fsl-cpm-fec-mdio",
1024 res.start, &res, 1);
1025 if (IS_ERR(mdio_dev)) {
1026 ret = PTR_ERR(mdio_dev);
1027 goto err;
1028 }
1029
1030 mdio_data.mii_speed = ((((ppc_proc_freq + 4999999) / 2500000) / 2) & 0x3F) << 1;
1031
1032 ret =
1033 platform_device_add_data(mdio_dev, &mdio_data,
1034 sizeof(struct fs_mii_fec_platform_info));
1035 if (ret)
1036 goto unreg;
1037 }
1038 return 0;
1039
1040unreg:
1041 platform_device_unregister(mdio_dev);
1042err:
1043 return ret;
1044}
1045
1046arch_initcall(fs_enet_mdio_of_init);
1047
1048static const char *enet_regs = "regs";
1049static const char *enet_pram = "pram";
1050static const char *enet_irq = "interrupt";
1051static char bus_id[9][BUS_ID_SIZE];
1052
1053static int __init fs_enet_of_init(void)
1054{
1055 struct device_node *np;
1056 unsigned int i;
1057 struct platform_device *fs_enet_dev = NULL;
1058 struct resource res;
1059 int ret;
1060
1061 for (np = NULL, i = 0;
1062 (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
1063 i++) {
1064 struct resource r[4];
1065 struct device_node *phy = NULL, *mdio = NULL;
1066 struct fs_platform_info fs_enet_data;
1067 const unsigned int *id;
1068 const unsigned int *phy_addr;
1069 const void *mac_addr;
1070 const phandle *ph;
1071 const char *model;
1072
1073 memset(r, 0, sizeof(r));
1074 memset(&fs_enet_data, 0, sizeof(fs_enet_data));
1075
1076 model = of_get_property(np, "model", NULL);
1077 if (model == NULL) {
1078 ret = -ENODEV;
1079 goto unreg;
1080 }
1081
1082 id = of_get_property(np, "device-id", NULL);
1083 fs_enet_data.fs_no = *id;
1084
1085 if (platform_device_skip(model, *id))
1086 continue;
1087
1088 ret = of_address_to_resource(np, 0, &r[0]);
1089 if (ret)
1090 goto err;
1091 r[0].name = enet_regs;
1092
1093 mac_addr = of_get_mac_address(np);
1094 if (mac_addr)
1095 memcpy(fs_enet_data.macaddr, mac_addr, 6);
1096
1097 ph = of_get_property(np, "phy-handle", NULL);
1098 if (ph != NULL)
1099 phy = of_find_node_by_phandle(*ph);
1100
1101 if (phy != NULL) {
1102 phy_addr = of_get_property(phy, "reg", NULL);
1103 fs_enet_data.phy_addr = *phy_addr;
1104 fs_enet_data.has_phy = 1;
1105
1106 mdio = of_get_parent(phy);
1107 ret = of_address_to_resource(mdio, 0, &res);
1108 if (ret) {
1109 of_node_put(phy);
1110 of_node_put(mdio);
1111 goto unreg;
1112 }
1113 }
1114
1115 model = of_get_property(np, "model", NULL);
1116 strcpy(fs_enet_data.fs_type, model);
1117
1118 if (strstr(model, "FEC")) {
1119 r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
1120 r[1].flags = IORESOURCE_IRQ;
1121 r[1].name = enet_irq;
1122
1123 fs_enet_dev =
1124 platform_device_register_simple("fsl-cpm-fec", i, &r[0], 2);
1125
1126 if (IS_ERR(fs_enet_dev)) {
1127 ret = PTR_ERR(fs_enet_dev);
1128 goto err;
1129 }
1130
1131 fs_enet_data.rx_ring = 128;
1132 fs_enet_data.tx_ring = 16;
1133 fs_enet_data.rx_copybreak = 240;
1134 fs_enet_data.use_napi = 1;
1135 fs_enet_data.napi_weight = 17;
1136
1137 snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%x:%02x",
1138 (u32)res.start, fs_enet_data.phy_addr);
1139 fs_enet_data.bus_id = (char*)&bus_id[i];
1140 fs_enet_data.init_ioports = init_fec_ioports;
1141 }
1142 if (strstr(model, "SCC")) {
1143 ret = of_address_to_resource(np, 1, &r[1]);
1144 if (ret)
1145 goto err;
1146 r[1].name = enet_pram;
1147
1148 r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
1149 r[2].flags = IORESOURCE_IRQ;
1150 r[2].name = enet_irq;
1151
1152 fs_enet_dev =
1153 platform_device_register_simple("fsl-cpm-scc", i, &r[0], 3);
1154
1155 if (IS_ERR(fs_enet_dev)) {
1156 ret = PTR_ERR(fs_enet_dev);
1157 goto err;
1158 }
1159
1160 fs_enet_data.rx_ring = 64;
1161 fs_enet_data.tx_ring = 8;
1162 fs_enet_data.rx_copybreak = 240;
1163 fs_enet_data.use_napi = 1;
1164 fs_enet_data.napi_weight = 17;
1165
1166 snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%s", "fixed@10:1");
1167 fs_enet_data.bus_id = (char*)&bus_id[i];
1168 fs_enet_data.init_ioports = init_scc_ioports;
1169 }
1170
1171 of_node_put(phy);
1172 of_node_put(mdio);
1173
1174 ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
1175 sizeof(struct
1176 fs_platform_info));
1177 if (ret)
1178 goto unreg;
1179 }
1180 return 0;
1181
1182unreg:
1183 platform_device_unregister(fs_enet_dev);
1184err:
1185 return ret;
1186}
1187
1188arch_initcall(fs_enet_of_init);
1189
1190static int __init fsl_pcmcia_of_init(void)
1191{
1192 struct device_node *np;
1193 /*
1194 * Register all the devices which type is "pcmcia"
1195 */
1196 for_each_compatible_node(np, "pcmcia", "fsl,pq-pcmcia")
1197 of_platform_device_create(np, "m8xx-pcmcia", NULL);
1198 return 0;
1199}
1200
1201arch_initcall(fsl_pcmcia_of_init);
1202
1203static const char *smc_regs = "regs";
1204static const char *smc_pram = "pram";
1205
1206static int __init cpm_smc_uart_of_init(void)
1207{
1208 struct device_node *np;
1209 unsigned int i;
1210 struct platform_device *cpm_uart_dev;
1211 int ret;
1212
1213 for (np = NULL, i = 0;
1214 (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
1215 i++) {
1216 struct resource r[3];
1217 struct fs_uart_platform_info cpm_uart_data;
1218 const int *id;
1219 const char *model;
1220
1221 memset(r, 0, sizeof(r));
1222 memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
1223
1224 ret = of_address_to_resource(np, 0, &r[0]);
1225 if (ret)
1226 goto err;
1227
1228 r[0].name = smc_regs;
1229
1230 ret = of_address_to_resource(np, 1, &r[1]);
1231 if (ret)
1232 goto err;
1233 r[1].name = smc_pram;
1234
1235 r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
1236 r[2].flags = IORESOURCE_IRQ;
1237
1238 cpm_uart_dev =
1239 platform_device_register_simple("fsl-cpm-smc:uart", i, &r[0], 3);
1240
1241 if (IS_ERR(cpm_uart_dev)) {
1242 ret = PTR_ERR(cpm_uart_dev);
1243 goto err;
1244 }
1245
1246 model = of_get_property(np, "model", NULL);
1247 strcpy(cpm_uart_data.fs_type, model);
1248
1249 id = of_get_property(np, "device-id", NULL);
1250 cpm_uart_data.fs_no = *id;
1251 cpm_uart_data.uart_clk = ppc_proc_freq;
1252
1253 cpm_uart_data.tx_num_fifo = 4;
1254 cpm_uart_data.tx_buf_size = 32;
1255 cpm_uart_data.rx_num_fifo = 4;
1256 cpm_uart_data.rx_buf_size = 32;
1257
1258 ret =
1259 platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
1260 sizeof(struct
1261 fs_uart_platform_info));
1262 if (ret)
1263 goto unreg;
1264 }
1265
1266 return 0;
1267
1268unreg:
1269 platform_device_unregister(cpm_uart_dev);
1270err:
1271 return ret;
1272}
1273
1274arch_initcall(cpm_smc_uart_of_init);
1275
1276#endif /* CONFIG_8xx */
1277#endif /* CONFIG_PPC_CPM_NEW_BINDING */
1278
1279static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk, 748static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
1280 struct spi_board_info *board_infos, 749 struct spi_board_info *board_infos,
1281 unsigned int num_board_infos, 750 unsigned int num_board_infos,
@@ -1371,25 +840,9 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
1371 sysclk = get_brgfreq(); 840 sysclk = get_brgfreq();
1372#endif 841#endif
1373 if (sysclk == -1) { 842 if (sysclk == -1) {
1374 struct device_node *np; 843 sysclk = fsl_get_sys_freq();
1375 const u32 *freq; 844 if (sysclk == -1)
1376 int size;
1377
1378 np = of_find_node_by_type(NULL, "soc");
1379 if (!np)
1380 return -ENODEV; 845 return -ENODEV;
1381
1382 freq = of_get_property(np, "clock-frequency", &size);
1383 if (!freq || size != sizeof(*freq) || *freq == 0) {
1384 freq = of_get_property(np, "bus-frequency", &size);
1385 if (!freq || size != sizeof(*freq) || *freq == 0) {
1386 of_node_put(np);
1387 return -ENODEV;
1388 }
1389 }
1390
1391 sysclk = *freq;
1392 of_node_put(np);
1393 } 846 }
1394 847
1395 ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos, 848 ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 63e7db30a4cd..74c4a9657b33 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -7,6 +7,7 @@
7extern phys_addr_t get_immrbase(void); 7extern phys_addr_t get_immrbase(void);
8extern u32 get_brgfreq(void); 8extern u32 get_brgfreq(void);
9extern u32 get_baudrate(void); 9extern u32 get_baudrate(void);
10extern u32 fsl_get_sys_freq(void);
10 11
11struct spi_board_info; 12struct spi_board_info;
12 13
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index cc81fd1141b0..cff550eec7e8 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -55,7 +55,7 @@ struct qe_snum {
55/* We allocate this here because it is used almost exclusively for 55/* We allocate this here because it is used almost exclusively for
56 * the communication processor devices. 56 * the communication processor devices.
57 */ 57 */
58struct qe_immap *qe_immr = NULL; 58struct qe_immap __iomem *qe_immr;
59EXPORT_SYMBOL(qe_immr); 59EXPORT_SYMBOL(qe_immr);
60 60
61static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */ 61static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
@@ -156,7 +156,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
156 */ 156 */
157static unsigned int brg_clk = 0; 157static unsigned int brg_clk = 0;
158 158
159unsigned int get_brg_clk(void) 159unsigned int qe_get_brg_clk(void)
160{ 160{
161 struct device_node *qe; 161 struct device_node *qe;
162 unsigned int size; 162 unsigned int size;
@@ -180,6 +180,7 @@ unsigned int get_brg_clk(void)
180 180
181 return brg_clk; 181 return brg_clk;
182} 182}
183EXPORT_SYMBOL(qe_get_brg_clk);
183 184
184/* Program the BRG to the given sampling rate and multiplier 185/* Program the BRG to the given sampling rate and multiplier
185 * 186 *
@@ -197,7 +198,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
197 if ((brg < QE_BRG1) || (brg > QE_BRG16)) 198 if ((brg < QE_BRG1) || (brg > QE_BRG16))
198 return -EINVAL; 199 return -EINVAL;
199 200
200 divisor = get_brg_clk() / (rate * multiplier); 201 divisor = qe_get_brg_clk() / (rate * multiplier);
201 202
202 if (divisor > QE_BRGC_DIVISOR_MAX + 1) { 203 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
203 div16 = QE_BRGC_DIV16; 204 div16 = QE_BRGC_DIV16;
@@ -415,12 +416,6 @@ void qe_muram_dump(void)
415} 416}
416EXPORT_SYMBOL(qe_muram_dump); 417EXPORT_SYMBOL(qe_muram_dump);
417 418
418void *qe_muram_addr(unsigned long offset)
419{
420 return (void *)&qe_immr->muram[offset];
421}
422EXPORT_SYMBOL(qe_muram_addr);
423
424/* The maximum number of RISCs we support */ 419/* The maximum number of RISCs we support */
425#define MAX_QE_RISC 2 420#define MAX_QE_RISC 2
426 421
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index 736c1fcc9503..93916a48afec 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -22,6 +22,7 @@
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/qe.h>
25#include <asm/prom.h> 26#include <asm/prom.h>
26#include <sysdev/fsl_soc.h> 27#include <sysdev/fsl_soc.h>
27 28
@@ -41,7 +42,7 @@ struct port_regs {
41#endif 42#endif
42}; 43};
43 44
44static struct port_regs *par_io = NULL; 45static struct port_regs __iomem *par_io;
45static int num_par_io_ports = 0; 46static int num_par_io_ports = 0;
46 47
47int par_io_init(struct device_node *np) 48int par_io_init(struct device_node *np)
@@ -165,7 +166,7 @@ int par_io_of_config(struct device_node *np)
165 } 166 }
166 167
167 ph = of_get_property(np, "pio-handle", NULL); 168 ph = of_get_property(np, "pio-handle", NULL);
168 if (ph == 0) { 169 if (ph == NULL) {
169 printk(KERN_ERR "pio-handle not available \n"); 170 printk(KERN_ERR "pio-handle not available \n");
170 return -1; 171 return -1;
171 } 172 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 18:01:21 -0500