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authorJongpill Lee <boyko.lee@samsung.com>2010-05-17 03:56:26 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-20 01:21:21 -0400
commit0df04f820b7ca5204329d1c235e509648fa8008d (patch)
treedbef433228009bdb1e1fc2ae6c361a8d57f07407 /arch
parent504d36e91ac12ccdb0e1193cee7bef9831a1c99e (diff)
ARM: S5PV210: Add IRQ_EINT interrupt support.
Add support for external interrupts on S5PV210. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Pannaga Bhushan <p.bhushan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> [ben-linux@fluff.org: Ext => IRQ_EINT in title] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-s5pv210/Kconfig1
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h31
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-gpio.h44
-rw-r--r--arch/arm/plat-s5p/Kconfig5
-rw-r--r--arch/arm/plat-s5p/Makefile2
-rw-r--r--arch/arm/plat-s5p/irq-eint.c213
6 files changed, 276 insertions, 20 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 7601c28e240b..8b9566e0cc51 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -13,6 +13,7 @@ config CPU_S5PV210
13 bool 13 bool
14 select PLAT_S5P 14 select PLAT_S5P
15 select S3C_PL330_DMA 15 select S3C_PL330_DMA
16 select S5P_EXT_INT
16 help 17 help
17 Enable S5PV210 CPU support 18 Enable S5PV210 CPU support
18 19
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 62c5175ef291..3a9e42e7734b 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -17,22 +17,6 @@
17 17
18/* VIC0: System, DMA, Timer */ 18/* VIC0: System, DMA, Timer */
19 19
20#define IRQ_EINT0 S5P_IRQ_VIC0(0)
21#define IRQ_EINT1 S5P_IRQ_VIC0(1)
22#define IRQ_EINT2 S5P_IRQ_VIC0(2)
23#define IRQ_EINT3 S5P_IRQ_VIC0(3)
24#define IRQ_EINT4 S5P_IRQ_VIC0(4)
25#define IRQ_EINT5 S5P_IRQ_VIC0(5)
26#define IRQ_EINT6 S5P_IRQ_VIC0(6)
27#define IRQ_EINT7 S5P_IRQ_VIC0(7)
28#define IRQ_EINT8 S5P_IRQ_VIC0(8)
29#define IRQ_EINT9 S5P_IRQ_VIC0(9)
30#define IRQ_EINT10 S5P_IRQ_VIC0(10)
31#define IRQ_EINT11 S5P_IRQ_VIC0(11)
32#define IRQ_EINT12 S5P_IRQ_VIC0(12)
33#define IRQ_EINT13 S5P_IRQ_VIC0(13)
34#define IRQ_EINT14 S5P_IRQ_VIC0(14)
35#define IRQ_EINT15 S5P_IRQ_VIC0(15)
36#define IRQ_EINT16_31 S5P_IRQ_VIC0(16) 20#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
37#define IRQ_BATF S5P_IRQ_VIC0(17) 21#define IRQ_BATF S5P_IRQ_VIC0(17)
38#define IRQ_MDMA S5P_IRQ_VIC0(18) 22#define IRQ_MDMA S5P_IRQ_VIC0(18)
@@ -134,13 +118,20 @@
134#define IRQ_MDNIE3 S5P_IRQ_VIC3(8) 118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
135#define IRQ_VIC_END S5P_IRQ_VIC3(31) 119#define IRQ_VIC_END S5P_IRQ_VIC3(31)
136 120
137#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) 121#define S5P_EINT_16_31_BASE (IRQ_VIC_END + 1)
138 122
139#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) 123#define EINT_MODE S3C_GPIO_SFN(0xf)
140#define IRQ_EINT(x) S5P_EINT(x) 124
125#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_IRQ_VIC0(0)) \
126 : ((x) + S5P_EINT_16_31_BASE))
141 127
142/* Set the default NR_IRQS */ 128/* Set the default NR_IRQS */
143 129
144#define NR_IRQS (IRQ_EINT(31) + 1) 130#define NR_IRQS (IRQ_EINT(31) + 1)
131
132#define EINT_GPIO_0(x) S5PV210_GPH0(x)
133#define EINT_GPIO_1(x) S5PV210_GPH1(x)
134#define EINT_GPIO_2(x) S5PV210_GPH2(x)
135#define EINT_GPIO_3(x) S5PV210_GPH3(x)
145 136
146#endif /* ASM_ARCH_IRQS_H */ 137#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..6d068091c36c
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
@@ -0,0 +1,44 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV210 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18#define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00)
19#define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4))
20
21#define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
22#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4))
23
24#define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00)
25#define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4))
26
27#define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40)
28#define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4))
29
30#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) \
31 : ((irq) - S5P_EINT_16_31_BASE))
32
33#define EINT_REG_NR(x) (eint_offset(x) >> 3)
34
35#define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7))
36
37/* values for S5P_EXTINT0 */
38#define S5P_EXTINT_LOWLEV (0x00)
39#define S5P_EXTINT_HILEV (0x01)
40#define S5P_EXTINT_FALLEDGE (0x02)
41#define S5P_EXTINT_RISEEDGE (0x03)
42#define S5P_EXTINT_BOTHEDGE (0x04)
43
44#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 92bd75607b43..c2361132d867 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -24,3 +24,8 @@ config PLAT_S5P
24 select SAMSUNG_IRQ_UART 24 select SAMSUNG_IRQ_UART
25 help 25 help
26 Base platform code for Samsung's S5P series SoC. 26 Base platform code for Samsung's S5P series SoC.
27
28config S5P_EXT_INT
29 bool
30 help
31 Use the external interrupts (other than GPIO interrupts.)
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 0ec09a9c36bd..25941a5d3bf6 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -16,3 +16,5 @@ obj-y += dev-uart.o
16obj-y += cpu.o 16obj-y += cpu.o
17obj-y += clock.o 17obj-y += clock.o
18obj-y += irq.o 18obj-y += irq.o
19obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
20obj-y += setup-i2c0.o
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
new file mode 100644
index 000000000000..eaa70aa0127b
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -0,0 +1,213 @@
1/* linux/arch/arm/plat-s5p/irq-eint.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <asm/hardware/vic.h>
21
22#include <plat/regs-irqtype.h>
23
24#include <mach/map.h>
25#include <plat/cpu.h>
26#include <plat/pm.h>
27
28#include <plat/gpio-cfg.h>
29#include <mach/regs-gpio.h>
30
31static inline void s5p_irq_eint_mask(unsigned int irq)
32{
33 u32 mask;
34
35 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
36 mask |= eint_irq_to_bit(irq);
37 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
38}
39
40static void s5p_irq_eint_unmask(unsigned int irq)
41{
42 u32 mask;
43
44 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
45 mask &= ~(eint_irq_to_bit(irq));
46 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
47}
48
49static inline void s5p_irq_eint_ack(unsigned int irq)
50{
51 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
52}
53
54static void s5p_irq_eint_maskack(unsigned int irq)
55{
56 /* compiler should in-line these */
57 s5p_irq_eint_mask(irq);
58 s5p_irq_eint_ack(irq);
59}
60
61static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
62{
63 int offs = eint_offset(irq);
64 int shift;
65 u32 ctrl, mask;
66 u32 newvalue = 0;
67
68 switch (type) {
69 case IRQ_TYPE_EDGE_RISING:
70 newvalue = S5P_EXTINT_RISEEDGE;
71 break;
72
73 case IRQ_TYPE_EDGE_FALLING:
74 newvalue = S5P_EXTINT_RISEEDGE;
75 break;
76
77 case IRQ_TYPE_EDGE_BOTH:
78 newvalue = S5P_EXTINT_BOTHEDGE;
79 break;
80
81 case IRQ_TYPE_LEVEL_LOW:
82 newvalue = S5P_EXTINT_LOWLEV;
83 break;
84
85 case IRQ_TYPE_LEVEL_HIGH:
86 newvalue = S5P_EXTINT_HILEV;
87 break;
88
89 default:
90 printk(KERN_ERR "No such irq type %d", type);
91 return -EINVAL;
92 }
93
94 shift = (offs & 0x7) * 4;
95 mask = 0x7 << shift;
96
97 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
98 ctrl &= ~mask;
99 ctrl |= newvalue << shift;
100 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
101
102 if ((0 <= offs) && (offs < 8))
103 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
104
105 else if ((8 <= offs) && (offs < 16))
106 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
107
108 else if ((16 <= offs) && (offs < 24))
109 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
110
111 else if ((24 <= offs) && (offs < 32))
112 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
113
114 else
115 printk(KERN_ERR "No such irq number %d", offs);
116
117 return 0;
118}
119
120static struct irq_chip s5p_irq_eint = {
121 .name = "s5p-eint",
122 .mask = s5p_irq_eint_mask,
123 .unmask = s5p_irq_eint_unmask,
124 .mask_ack = s5p_irq_eint_maskack,
125 .ack = s5p_irq_eint_ack,
126 .set_type = s5p_irq_eint_set_type,
127#ifdef CONFIG_PM
128 .set_wake = s3c_irqext_wake,
129#endif
130};
131
132/* s5p_irq_demux_eint
133 *
134 * This function demuxes the IRQ from the group0 external interrupts,
135 * from EINTs 16 to 31. It is designed to be inlined into the specific
136 * handler s5p_irq_demux_eintX_Y.
137 *
138 * Each EINT pend/mask registers handle eight of them.
139 */
140static inline void s5p_irq_demux_eint(unsigned int start)
141{
142 u32 status;
143 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
144 unsigned int irq;
145
146 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
147 status &= ~mask;
148 status &= 0xff;
149
150 while (status) {
151 irq = fls(status);
152 generic_handle_irq(irq - 1 + start);
153 status &= ~(1 << irq);
154 }
155}
156
157static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
158{
159 s5p_irq_demux_eint(IRQ_EINT(16));
160 s5p_irq_demux_eint(IRQ_EINT(24));
161}
162
163static inline void s5p_irq_vic_eint_mask(unsigned int irq)
164{
165 s5p_irq_eint_mask(irq);
166}
167
168static void s5p_irq_vic_eint_unmask(unsigned int irq)
169{
170 s5p_irq_eint_unmask(irq);
171}
172
173static inline void s5p_irq_vic_eint_ack(unsigned int irq)
174{
175 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
176}
177
178static void s5p_irq_vic_eint_maskack(unsigned int irq)
179{
180 s5p_irq_vic_eint_mask(irq);
181 s5p_irq_vic_eint_ack(irq);
182}
183
184static struct irq_chip s5p_irq_vic_eint = {
185 .name = "s5p_vic_eint",
186 .mask = s5p_irq_vic_eint_mask,
187 .unmask = s5p_irq_vic_eint_unmask,
188 .mask_ack = s5p_irq_vic_eint_maskack,
189 .ack = s5p_irq_vic_eint_ack,
190 .set_type = s5p_irq_eint_set_type,
191#ifdef CONFIG_PM
192 .set_wake = s3c_irqext_wake,
193#endif
194};
195
196int __init s5p_init_irq_eint(void)
197{
198 int irq;
199
200 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
201 set_irq_chip(irq, &s5p_irq_vic_eint);
202
203 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
204 set_irq_chip(irq, &s5p_irq_eint);
205 set_irq_handler(irq, handle_level_irq);
206 set_irq_flags(irq, IRQF_VALID);
207 }
208
209 set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
210 return 0;
211}
212
213arch_initcall(s5p_init_irq_eint);
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