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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-18 12:51:47 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-20 09:38:21 -0400
commit94a4c32939dede9328c6e4face335eb8441fc18d (patch)
tree0ac510bf3b90cb79fe94112b95dd77d96c190bf9 /arch
parent255033a9bb900a06c9a7798908ce12557d24fb66 (diff)
[MIPS] TXx9: Add 64-bit support
SYS_SUPPORTS_64BIT_KERNEL is enabled for RBTX4927/RBTX4938, but actually it was broken for long time (or from the beginning). Now it should work. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/txx9/generic/Makefile4
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c2
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c2
-rw-r--r--arch/mips/txx9/generic/setup.c16
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c194
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c259
-rw-r--r--arch/mips/txx9/jmr3927/setup.c8
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c12
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c89
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c218
10 files changed, 510 insertions, 294 deletions
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index ab274ede9a70..9c120771e65f 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -4,8 +4,8 @@
4 4
5obj-y += setup.o 5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o 6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o 7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o irq_tx4938.o 8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o 10obj-$(CONFIG_KGDB) += dbgio.o
11 11
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index 6377bd8a9050..cbea1fdde82b 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -31,7 +31,7 @@
31void __init tx4927_irq_init(void) 31void __init tx4927_irq_init(void)
32{ 32{
33 mips_cpu_irq_init(); 33 mips_cpu_irq_init();
34 txx9_irq_init(TX4927_IRC_REG); 34 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
36 handle_simple_irq); 36 handle_simple_irq);
37} 37}
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index 5fc86c9c9d2f..6eac684bf190 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -19,7 +19,7 @@
19void __init tx4938_irq_init(void) 19void __init tx4938_irq_init(void)
20{ 20{
21 mips_cpu_irq_init(); 21 mips_cpu_irq_init();
22 txx9_irq_init(TX4938_IRC_REG); 22 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
24 handle_simple_irq); 24 handle_simple_irq);
25} 25}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8caef07701bb..3715a8f5ea44 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -30,6 +30,7 @@ struct resource txx9_ce_res[8];
30static char txx9_ce_res_name[8][4]; /* "CEn" */ 30static char txx9_ce_res_name[8][4]; /* "CEn" */
31 31
32/* pcode, internal register */ 32/* pcode, internal register */
33unsigned int txx9_pcode;
33char txx9_pcode_str[8]; 34char txx9_pcode_str[8];
34static struct resource txx9_reg_res = { 35static struct resource txx9_reg_res = {
35 .name = txx9_pcode_str, 36 .name = txx9_pcode_str,
@@ -59,15 +60,16 @@ unsigned int txx9_master_clock;
59unsigned int txx9_cpu_clock; 60unsigned int txx9_cpu_clock;
60unsigned int txx9_gbus_clock; 61unsigned int txx9_gbus_clock;
61 62
63int txx9_ccfg_toeon __initdata = 1;
62 64
63/* Minimum CLK support */ 65/* Minimum CLK support */
64 66
65struct clk *clk_get(struct device *dev, const char *id) 67struct clk *clk_get(struct device *dev, const char *id)
66{ 68{
67 if (!strcmp(id, "spi-baseclk")) 69 if (!strcmp(id, "spi-baseclk"))
68 return (struct clk *)(txx9_gbus_clock / 2 / 4); 70 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4);
69 if (!strcmp(id, "imbus_clk")) 71 if (!strcmp(id, "imbus_clk"))
70 return (struct clk *)(txx9_gbus_clock / 2); 72 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
71 return ERR_PTR(-ENOENT); 73 return ERR_PTR(-ENOENT);
72} 74}
73EXPORT_SYMBOL(clk_get); 75EXPORT_SYMBOL(clk_get);
@@ -123,6 +125,12 @@ void __init prom_init_cmdline(void)
123 int argc = (int)fw_arg0; 125 int argc = (int)fw_arg0;
124 char **argv = (char **)fw_arg1; 126 char **argv = (char **)fw_arg1;
125 int i; /* Always ignore the "-c" at argv[0] */ 127 int i; /* Always ignore the "-c" at argv[0] */
128#ifdef CONFIG_64BIT
129 char *fixed_argv[32];
130 for (i = 0; i < argc; i++)
131 fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));
132 argv = fixed_argv;
133#endif
126 134
127 /* ignore all built-in args if any f/w args given */ 135 /* ignore all built-in args if any f/w args given */
128 if (argc > 1) 136 if (argc > 1)
@@ -180,6 +188,10 @@ char * __init prom_getcmdline(void)
180/* wrappers */ 188/* wrappers */
181void __init plat_mem_setup(void) 189void __init plat_mem_setup(void)
182{ 190{
191 ioport_resource.start = 0;
192 ioport_resource.end = ~0UL; /* no limit */
193 iomem_resource.start = 0;
194 iomem_resource.end = ~0UL; /* no limit */
183 txx9_board_vec->mem_setup(); 195 txx9_board_vec->mem_setup();
184} 196}
185 197
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
new file mode 100644
index 000000000000..89d6e28add93
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -0,0 +1,194 @@
1/*
2 * TX4927 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4927.h>
23
24void __init tx4927_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4927_ccfg_set(TX4927_CCFG_WR);
30}
31
32static struct resource tx4927_sdram_resource[4];
33
34void __init tx4927_setup(void)
35{
36 int i;
37 __u32 divmode;
38 int cpuclk = 0;
39 u64 ccfg;
40
41 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
42 TX4927_REG_SIZE);
43
44 /* SDRAMC,EBUSC are configured by PROM */
45 for (i = 0; i < 8; i++) {
46 if (!(TX4927_EBUSC_CR(i) & 0x8))
47 continue; /* disabled */
48 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
49 txx9_ce_res[i].end =
50 txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
51 request_resource(&iomem_resource, &txx9_ce_res[i]);
52 }
53
54 /* clocks */
55 ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
56 if (txx9_master_clock) {
57 /* calculate gbus_clock and cpu_clock from master_clock */
58 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
59 switch (divmode) {
60 case TX4927_CCFG_DIVMODE_8:
61 case TX4927_CCFG_DIVMODE_10:
62 case TX4927_CCFG_DIVMODE_12:
63 case TX4927_CCFG_DIVMODE_16:
64 txx9_gbus_clock = txx9_master_clock * 4; break;
65 default:
66 txx9_gbus_clock = txx9_master_clock;
67 }
68 switch (divmode) {
69 case TX4927_CCFG_DIVMODE_2:
70 case TX4927_CCFG_DIVMODE_8:
71 cpuclk = txx9_gbus_clock * 2; break;
72 case TX4927_CCFG_DIVMODE_2_5:
73 case TX4927_CCFG_DIVMODE_10:
74 cpuclk = txx9_gbus_clock * 5 / 2; break;
75 case TX4927_CCFG_DIVMODE_3:
76 case TX4927_CCFG_DIVMODE_12:
77 cpuclk = txx9_gbus_clock * 3; break;
78 case TX4927_CCFG_DIVMODE_4:
79 case TX4927_CCFG_DIVMODE_16:
80 cpuclk = txx9_gbus_clock * 4; break;
81 }
82 txx9_cpu_clock = cpuclk;
83 } else {
84 if (txx9_cpu_clock == 0)
85 txx9_cpu_clock = 200000000; /* 200MHz */
86 /* calculate gbus_clock and master_clock from cpu_clock */
87 cpuclk = txx9_cpu_clock;
88 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
89 switch (divmode) {
90 case TX4927_CCFG_DIVMODE_2:
91 case TX4927_CCFG_DIVMODE_8:
92 txx9_gbus_clock = cpuclk / 2; break;
93 case TX4927_CCFG_DIVMODE_2_5:
94 case TX4927_CCFG_DIVMODE_10:
95 txx9_gbus_clock = cpuclk * 2 / 5; break;
96 case TX4927_CCFG_DIVMODE_3:
97 case TX4927_CCFG_DIVMODE_12:
98 txx9_gbus_clock = cpuclk / 3; break;
99 case TX4927_CCFG_DIVMODE_4:
100 case TX4927_CCFG_DIVMODE_16:
101 txx9_gbus_clock = cpuclk / 4; break;
102 }
103 switch (divmode) {
104 case TX4927_CCFG_DIVMODE_8:
105 case TX4927_CCFG_DIVMODE_10:
106 case TX4927_CCFG_DIVMODE_12:
107 case TX4927_CCFG_DIVMODE_16:
108 txx9_master_clock = txx9_gbus_clock / 4; break;
109 default:
110 txx9_master_clock = txx9_gbus_clock;
111 }
112 }
113 /* change default value to udelay/mdelay take reasonable time */
114 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
115
116 /* CCFG */
117 tx4927_wdr_init();
118 /* clear BusErrorOnWrite flag (W1C) */
119 tx4927_ccfg_set(TX4927_CCFG_BEOW);
120 /* enable Timeout BusError */
121 if (txx9_ccfg_toeon)
122 tx4927_ccfg_set(TX4927_CCFG_TOE);
123
124 /* DMA selection */
125 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
126
127 /* Use external clock for external arbiter */
128 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
129 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
130
131 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
132 txx9_pcode_str,
133 (cpuclk + 500000) / 1000000,
134 (txx9_master_clock + 500000) / 1000000,
135 (__u32)____raw_readq(&tx4927_ccfgptr->crir),
136 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
137 (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
138
139 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
140 for (i = 0; i < 4; i++) {
141 __u64 cr = TX4927_SDRAMC_CR(i);
142 unsigned long base, size;
143 if (!((__u32)cr & 0x00000400))
144 continue; /* disabled */
145 base = (unsigned long)(cr >> 49) << 21;
146 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
147 printk(" CR%d:%016llx", i, (unsigned long long)cr);
148 tx4927_sdram_resource[i].name = "SDRAM";
149 tx4927_sdram_resource[i].start = base;
150 tx4927_sdram_resource[i].end = base + size - 1;
151 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
152 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
153 }
154 printk(" TR:%09llx\n",
155 (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
156
157 /* TMR */
158 /* disable all timers */
159 for (i = 0; i < TX4927_NR_TMR; i++)
160 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
161
162 /* PIO */
163 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
164 __raw_writel(0, &tx4927_pioptr->maskcpu);
165 __raw_writel(0, &tx4927_pioptr->maskext);
166}
167
168void __init tx4927_time_init(unsigned int tmrnr)
169{
170 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
171 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
172 TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
173 TXX9_IMCLK);
174}
175
176void __init tx4927_setup_serial(void)
177{
178#ifdef CONFIG_SERIAL_TXX9
179 int i;
180 struct uart_port req;
181
182 for (i = 0; i < 2; i++) {
183 memset(&req, 0, sizeof(req));
184 req.line = i;
185 req.iotype = UPIO_MEM;
186 req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
187 req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
188 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
189 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
190 req.uartclk = TXX9_IMCLK;
191 early_serial_txx9_setup(&req);
192 }
193#endif /* CONFIG_SERIAL_TXX9 */
194}
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
new file mode 100644
index 000000000000..317378d8579d
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -0,0 +1,259 @@
1/*
2 * TX4938/4937 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4938.h>
23
24void __init tx4938_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4938_ccfg_set(TX4938_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4938_ccfg_set(TX4938_CCFG_WR);
30}
31
32static struct resource tx4938_sdram_resource[4];
33static struct resource tx4938_sram_resource;
34
35#define TX4938_SRAM_SIZE 0x800
36
37void __init tx4938_setup(void)
38{
39 int i;
40 __u32 divmode;
41 int cpuclk = 0;
42 u64 ccfg;
43
44 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
45 TX4938_REG_SIZE);
46
47 /* SDRAMC,EBUSC are configured by PROM */
48 for (i = 0; i < 8; i++) {
49 if (!(TX4938_EBUSC_CR(i) & 0x8))
50 continue; /* disabled */
51 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
52 txx9_ce_res[i].end =
53 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
54 request_resource(&iomem_resource, &txx9_ce_res[i]);
55 }
56
57 /* clocks */
58 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
59 if (txx9_master_clock) {
60 /* calculate gbus_clock and cpu_clock from master_clock */
61 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
62 switch (divmode) {
63 case TX4938_CCFG_DIVMODE_8:
64 case TX4938_CCFG_DIVMODE_10:
65 case TX4938_CCFG_DIVMODE_12:
66 case TX4938_CCFG_DIVMODE_16:
67 case TX4938_CCFG_DIVMODE_18:
68 txx9_gbus_clock = txx9_master_clock * 4; break;
69 default:
70 txx9_gbus_clock = txx9_master_clock;
71 }
72 switch (divmode) {
73 case TX4938_CCFG_DIVMODE_2:
74 case TX4938_CCFG_DIVMODE_8:
75 cpuclk = txx9_gbus_clock * 2; break;
76 case TX4938_CCFG_DIVMODE_2_5:
77 case TX4938_CCFG_DIVMODE_10:
78 cpuclk = txx9_gbus_clock * 5 / 2; break;
79 case TX4938_CCFG_DIVMODE_3:
80 case TX4938_CCFG_DIVMODE_12:
81 cpuclk = txx9_gbus_clock * 3; break;
82 case TX4938_CCFG_DIVMODE_4:
83 case TX4938_CCFG_DIVMODE_16:
84 cpuclk = txx9_gbus_clock * 4; break;
85 case TX4938_CCFG_DIVMODE_4_5:
86 case TX4938_CCFG_DIVMODE_18:
87 cpuclk = txx9_gbus_clock * 9 / 2; break;
88 }
89 txx9_cpu_clock = cpuclk;
90 } else {
91 if (txx9_cpu_clock == 0)
92 txx9_cpu_clock = 300000000; /* 300MHz */
93 /* calculate gbus_clock and master_clock from cpu_clock */
94 cpuclk = txx9_cpu_clock;
95 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
96 switch (divmode) {
97 case TX4938_CCFG_DIVMODE_2:
98 case TX4938_CCFG_DIVMODE_8:
99 txx9_gbus_clock = cpuclk / 2; break;
100 case TX4938_CCFG_DIVMODE_2_5:
101 case TX4938_CCFG_DIVMODE_10:
102 txx9_gbus_clock = cpuclk * 2 / 5; break;
103 case TX4938_CCFG_DIVMODE_3:
104 case TX4938_CCFG_DIVMODE_12:
105 txx9_gbus_clock = cpuclk / 3; break;
106 case TX4938_CCFG_DIVMODE_4:
107 case TX4938_CCFG_DIVMODE_16:
108 txx9_gbus_clock = cpuclk / 4; break;
109 case TX4938_CCFG_DIVMODE_4_5:
110 case TX4938_CCFG_DIVMODE_18:
111 txx9_gbus_clock = cpuclk * 2 / 9; break;
112 }
113 switch (divmode) {
114 case TX4938_CCFG_DIVMODE_8:
115 case TX4938_CCFG_DIVMODE_10:
116 case TX4938_CCFG_DIVMODE_12:
117 case TX4938_CCFG_DIVMODE_16:
118 case TX4938_CCFG_DIVMODE_18:
119 txx9_master_clock = txx9_gbus_clock / 4; break;
120 default:
121 txx9_master_clock = txx9_gbus_clock;
122 }
123 }
124 /* change default value to udelay/mdelay take reasonable time */
125 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
126
127 /* CCFG */
128 tx4938_wdr_init();
129 /* clear BusErrorOnWrite flag (W1C) */
130 tx4938_ccfg_set(TX4938_CCFG_BEOW);
131 /* enable Timeout BusError */
132 if (txx9_ccfg_toeon)
133 tx4938_ccfg_set(TX4938_CCFG_TOE);
134
135 /* DMA selection */
136 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
137
138 /* Use external clock for external arbiter */
139 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
140 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
141
142 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
143 txx9_pcode_str,
144 (cpuclk + 500000) / 1000000,
145 (txx9_master_clock + 500000) / 1000000,
146 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
147 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
148 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
149
150 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
151 for (i = 0; i < 4; i++) {
152 __u64 cr = TX4938_SDRAMC_CR(i);
153 unsigned long base, size;
154 if (!((__u32)cr & 0x00000400))
155 continue; /* disabled */
156 base = (unsigned long)(cr >> 49) << 21;
157 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
158 printk(" CR%d:%016llx", i, (unsigned long long)cr);
159 tx4938_sdram_resource[i].name = "SDRAM";
160 tx4938_sdram_resource[i].start = base;
161 tx4938_sdram_resource[i].end = base + size - 1;
162 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
163 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
164 }
165 printk(" TR:%09llx\n",
166 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
167
168 /* SRAM */
169 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
170 unsigned int size = TX4938_SRAM_SIZE;
171 tx4938_sram_resource.name = "SRAM";
172 tx4938_sram_resource.start =
173 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
174 & ~(size - 1);
175 tx4938_sram_resource.end =
176 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
177 tx4938_sram_resource.flags = IORESOURCE_MEM;
178 request_resource(&iomem_resource, &tx4938_sram_resource);
179 }
180
181 /* TMR */
182 /* disable all timers */
183 for (i = 0; i < TX4938_NR_TMR; i++)
184 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
185
186 /* DMA */
187 for (i = 0; i < 2; i++)
188 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
189 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
190
191 /* PIO */
192 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
193 __raw_writel(0, &tx4938_pioptr->maskcpu);
194 __raw_writel(0, &tx4938_pioptr->maskext);
195
196 if (txx9_pcode == 0x4938) {
197 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
198 /* set PCIC1 reset */
199 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
200 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
201 mdelay(1); /* at least 128 cpu clock */
202 /* clear PCIC1 reset */
203 txx9_clear64(&tx4938_ccfgptr->clkctr,
204 TX4938_CLKCTR_PCIC1RST);
205 } else {
206 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
207 /* stop PCIC1 */
208 txx9_set64(&tx4938_ccfgptr->clkctr,
209 TX4938_CLKCTR_PCIC1CKD);
210 }
211 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
212 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
213 txx9_set64(&tx4938_ccfgptr->clkctr,
214 TX4938_CLKCTR_ETH0RST);
215 txx9_set64(&tx4938_ccfgptr->clkctr,
216 TX4938_CLKCTR_ETH0CKD);
217 }
218 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
219 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
220 txx9_set64(&tx4938_ccfgptr->clkctr,
221 TX4938_CLKCTR_ETH1RST);
222 txx9_set64(&tx4938_ccfgptr->clkctr,
223 TX4938_CLKCTR_ETH1CKD);
224 }
225 }
226}
227
228void __init tx4938_time_init(unsigned int tmrnr)
229{
230 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
231 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
232 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
233 TXX9_IMCLK);
234}
235
236void __init tx4938_setup_serial(void)
237{
238#ifdef CONFIG_SERIAL_TXX9
239 int i;
240 struct uart_port req;
241 unsigned int ch_mask = 0;
242
243 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
244 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
245 for (i = 0; i < 2; i++) {
246 if ((1 << i) & ch_mask)
247 continue;
248 memset(&req, 0, sizeof(req));
249 req.line = i;
250 req.iotype = UPIO_MEM;
251 req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i);
252 req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL;
253 req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i);
254 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
255 req.uartclk = TXX9_IMCLK;
256 early_serial_txx9_setup(&req);
257 }
258#endif /* CONFIG_SERIAL_TXX9 */
259}
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 5e35ef73c5a5..03647ebe4130 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -105,14 +105,6 @@ static void __init jmr3927_mem_setup(void)
105 _machine_halt = jmr3927_machine_halt; 105 _machine_halt = jmr3927_machine_halt;
106 pm_power_off = jmr3927_machine_power_off; 106 pm_power_off = jmr3927_machine_power_off;
107 107
108 /*
109 * IO/MEM resources.
110 */
111 ioport_resource.start = 0;
112 ioport_resource.end = 0xffffffff;
113 iomem_resource.start = 0;
114 iomem_resource.end = 0xffffffff;
115
116 /* Reboot on panic */ 108 /* Reboot on panic */
117 panic_timeout = 180; 109 panic_timeout = 180;
118 110
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 70f13211bc2a..cd748a930328 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -126,14 +126,12 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
126 .mask_ack = toshiba_rbtx4927_irq_ioc_disable, 126 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
127 .unmask = toshiba_rbtx4927_irq_ioc_enable, 127 .unmask = toshiba_rbtx4927_irq_ioc_enable,
128}; 128};
129#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
130#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
131 129
132static int toshiba_rbtx4927_irq_nested(int sw_irq) 130static int toshiba_rbtx4927_irq_nested(int sw_irq)
133{ 131{
134 u8 level3; 132 u8 level3;
135 133
136 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 134 level3 = readb(rbtx4927_imstat_addr) & 0x1f;
137 if (level3) 135 if (level3)
138 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; 136 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
139 return (sw_irq); 137 return (sw_irq);
@@ -154,18 +152,18 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
154{ 152{
155 unsigned char v; 153 unsigned char v;
156 154
157 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 155 v = readb(rbtx4927_imask_addr);
158 v |= (1 << (irq - RBTX4927_IRQ_IOC)); 156 v |= (1 << (irq - RBTX4927_IRQ_IOC));
159 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); 157 writeb(v, rbtx4927_imask_addr);
160} 158}
161 159
162static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 160static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
163{ 161{
164 unsigned char v; 162 unsigned char v;
165 163
166 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 164 v = readb(rbtx4927_imask_addr);
167 v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); 165 v &= ~(1 << (irq - RBTX4927_IRQ_IOC));
168 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); 166 writeb(v, rbtx4927_imask_addr);
169 mmiowb(); 167 mmiowb();
170} 168}
171 169
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 1657fd935da8..3da20ea3e55c 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -53,17 +53,10 @@
53#include <asm/io.h> 53#include <asm/io.h>
54#include <asm/processor.h> 54#include <asm/processor.h>
55#include <asm/reboot.h> 55#include <asm/reboot.h>
56#include <asm/time.h>
57#include <asm/txx9tmr.h>
58#include <asm/txx9/generic.h> 56#include <asm/txx9/generic.h>
59#include <asm/txx9/pci.h> 57#include <asm/txx9/pci.h>
60#include <asm/txx9/rbtx4927.h> 58#include <asm/txx9/rbtx4927.h>
61#include <asm/txx9/tx4938.h> /* for TX4937 */ 59#include <asm/txx9/tx4938.h> /* for TX4937 */
62#ifdef CONFIG_SERIAL_TXX9
63#include <linux/serial_core.h>
64#endif
65
66static int tx4927_ccfg_toeon = 1;
67 60
68#ifdef CONFIG_PCI 61#ifdef CONFIG_PCI
69static void __init tx4927_pci_setup(void) 62static void __init tx4927_pci_setup(void)
@@ -184,14 +177,14 @@ static void toshiba_rbtx4927_restart(char *command)
184 printk(KERN_NOTICE "System Rebooting...\n"); 177 printk(KERN_NOTICE "System Rebooting...\n");
185 178
186 /* enable the s/w reset register */ 179 /* enable the s/w reset register */
187 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); 180 writeb(1, rbtx4927_softresetlock_addr);
188 181
189 /* wait for enable to be seen */ 182 /* wait for enable to be seen */
190 while ((readb(RBTX4927_SW_RESET_ENABLE) & 183 while (!(readb(rbtx4927_softresetlock_addr) & 1))
191 RBTX4927_SW_RESET_ENABLE_SET) == 0x00); 184 ;
192 185
193 /* do a s/w reset */ 186 /* do a s/w reset */
194 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); 187 writeb(1, rbtx4927_softreset_addr);
195 188
196 /* do something passive while waiting for reset */ 189 /* do something passive while waiting for reset */
197 local_irq_disable(); 190 local_irq_disable();
@@ -213,9 +206,11 @@ static void toshiba_rbtx4927_power_off(void)
213 /* no return */ 206 /* no return */
214} 207}
215 208
209static void __init rbtx4927_clock_init(void);
210static void __init rbtx4937_clock_init(void);
211
216static void __init rbtx4927_mem_setup(void) 212static void __init rbtx4927_mem_setup(void)
217{ 213{
218 int i;
219 u32 cp0_config; 214 u32 cp0_config;
220 char *argptr; 215 char *argptr;
221 216
@@ -227,16 +222,18 @@ static void __init rbtx4927_mem_setup(void)
227 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 222 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
228 write_c0_config(cp0_config); 223 write_c0_config(cp0_config);
229 224
230 ioport_resource.end = 0xffffffff; 225 if (TX4927_REV_PCODE() == 0x4927) {
231 iomem_resource.end = 0xffffffff; 226 rbtx4927_clock_init();
227 tx4927_setup();
228 } else {
229 rbtx4937_clock_init();
230 tx4938_setup();
231 }
232 232
233 _machine_restart = toshiba_rbtx4927_restart; 233 _machine_restart = toshiba_rbtx4927_restart;
234 _machine_halt = toshiba_rbtx4927_halt; 234 _machine_halt = toshiba_rbtx4927_halt;
235 pm_power_off = toshiba_rbtx4927_power_off; 235 pm_power_off = toshiba_rbtx4927_power_off;
236 236
237 for (i = 0; i < TX4927_NR_TMR; i++)
238 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
239
240#ifdef CONFIG_PCI 237#ifdef CONFIG_PCI
241 txx9_alloc_pci_controller(&txx9_primary_pcic, 238 txx9_alloc_pci_controller(&txx9_primary_pcic,
242 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, 239 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
@@ -245,36 +242,13 @@ static void __init rbtx4927_mem_setup(void)
245 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 242 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
246#endif 243#endif
247 244
248 /* CCFG */ 245 tx4927_setup_serial();
249 /* do reset on watchdog */
250 tx4927_ccfg_set(TX4927_CCFG_WR);
251 /* enable Timeout BusError */
252 if (tx4927_ccfg_toeon)
253 tx4927_ccfg_set(TX4927_CCFG_TOE);
254
255#ifdef CONFIG_SERIAL_TXX9
256 {
257 extern int early_serial_txx9_setup(struct uart_port *port);
258 struct uart_port req;
259 for(i = 0; i < 2; i++) {
260 memset(&req, 0, sizeof(req));
261 req.line = i;
262 req.iotype = UPIO_MEM;
263 req.membase = (char *)(0xff1ff300 + i * 0x100);
264 req.mapbase = 0xff1ff300 + i * 0x100;
265 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
266 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
267 req.uartclk = 50000000;
268 early_serial_txx9_setup(&req);
269 }
270 }
271#ifdef CONFIG_SERIAL_TXX9_CONSOLE 246#ifdef CONFIG_SERIAL_TXX9_CONSOLE
272 argptr = prom_getcmdline(); 247 argptr = prom_getcmdline();
273 if (strstr(argptr, "console=") == NULL) { 248 if (strstr(argptr, "console=") == NULL) {
274 strcat(argptr, " console=ttyS0,38400"); 249 strcat(argptr, " console=ttyS0,38400");
275 } 250 }
276#endif 251#endif
277#endif
278 252
279#ifdef CONFIG_ROOT_NFS 253#ifdef CONFIG_ROOT_NFS
280 argptr = prom_getcmdline(); 254 argptr = prom_getcmdline();
@@ -291,19 +265,7 @@ static void __init rbtx4927_mem_setup(void)
291#endif 265#endif
292} 266}
293 267
294static void __init rbtx49x7_common_time_init(void) 268static void __init rbtx4927_clock_init(void)
295{
296 /* change default value to udelay/mdelay take reasonable time */
297 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
298
299 mips_hpt_frequency = txx9_cpu_clock / 2;
300 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
301 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
302 TXX9_IRQ_BASE + 17,
303 50000000);
304}
305
306static void __init rbtx4927_time_init(void)
307{ 269{
308 /* 270 /*
309 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 271 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
@@ -325,11 +287,9 @@ static void __init rbtx4927_time_init(void)
325 default: 287 default:
326 txx9_cpu_clock = 200000000; /* 200MHz */ 288 txx9_cpu_clock = 200000000; /* 200MHz */
327 } 289 }
328
329 rbtx49x7_common_time_init();
330} 290}
331 291
332static void __init rbtx4937_time_init(void) 292static void __init rbtx4937_clock_init(void)
333{ 293{
334 /* 294 /*
335 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 295 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
@@ -357,15 +317,18 @@ static void __init rbtx4937_time_init(void)
357 default: 317 default:
358 txx9_cpu_clock = 333333333; /* 333MHz */ 318 txx9_cpu_clock = 333333333; /* 333MHz */
359 } 319 }
320}
360 321
361 rbtx49x7_common_time_init(); 322static void __init rbtx4927_time_init(void)
323{
324 tx4927_time_init(0);
362} 325}
363 326
364static int __init toshiba_rbtx4927_rtc_init(void) 327static int __init toshiba_rbtx4927_rtc_init(void)
365{ 328{
366 static struct resource __initdata res = { 329 struct resource res = {
367 .start = 0x1c010000, 330 .start = RBTX4927_BRAMRTC_BASE - IO_BASE,
368 .end = 0x1c010000 + 0x800 - 1, 331 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
369 .flags = IORESOURCE_MEM, 332 .flags = IORESOURCE_MEM,
370 }; 333 };
371 struct platform_device *dev = 334 struct platform_device *dev =
@@ -375,7 +338,7 @@ static int __init toshiba_rbtx4927_rtc_init(void)
375 338
376static int __init rbtx4927_ne_init(void) 339static int __init rbtx4927_ne_init(void)
377{ 340{
378 static struct resource __initdata res[] = { 341 struct resource res[] = {
379 { 342 {
380 .start = RBTX4927_RTL_8019_BASE, 343 .start = RBTX4927_RTL_8019_BASE,
381 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, 344 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
@@ -434,7 +397,7 @@ struct txx9_board_vec rbtx4937_vec __initdata = {
434 .prom_init = rbtx4927_prom_init, 397 .prom_init = rbtx4927_prom_init,
435 .mem_setup = rbtx4927_mem_setup, 398 .mem_setup = rbtx4927_mem_setup,
436 .irq_setup = rbtx4927_irq_setup, 399 .irq_setup = rbtx4927_irq_setup,
437 .time_init = rbtx4937_time_init, 400 .time_init = rbtx4927_time_init,
438 .device_init = rbtx4927_device_init, 401 .device_init = rbtx4927_device_init,
439 .arch_init = rbtx4937_arch_init, 402 .arch_init = rbtx4937_arch_init,
440#ifdef CONFIG_PCI 403#ifdef CONFIG_PCI
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index c1e076c7b2d2..6c2b99bb8af6 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -20,21 +20,14 @@
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21 21
22#include <asm/reboot.h> 22#include <asm/reboot.h>
23#include <asm/time.h>
24#include <asm/txx9tmr.h>
25#include <asm/io.h> 23#include <asm/io.h>
26#include <asm/txx9/generic.h> 24#include <asm/txx9/generic.h>
27#include <asm/txx9/pci.h> 25#include <asm/txx9/pci.h>
28#include <asm/txx9/rbtx4938.h> 26#include <asm/txx9/rbtx4938.h>
29#ifdef CONFIG_SERIAL_TXX9
30#include <linux/serial_core.h>
31#endif
32#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
33#include <asm/txx9/spi.h> 28#include <asm/txx9/spi.h>
34#include <asm/txx9pio.h> 29#include <asm/txx9pio.h>
35 30
36static int tx4938_ccfg_toeon = 1;
37
38static void rbtx4938_machine_halt(void) 31static void rbtx4938_machine_halt(void)
39{ 32{
40 printk(KERN_NOTICE "System Halted\n"); 33 printk(KERN_NOTICE "System Halted\n");
@@ -182,189 +175,10 @@ static void __init rbtx4938_spi_setup(void)
182} 175}
183 176
184static struct resource rbtx4938_fpga_resource; 177static struct resource rbtx4938_fpga_resource;
185static struct resource tx4938_sdram_resource[4];
186static struct resource tx4938_sram_resource;
187
188void __init tx4938_board_setup(void)
189{
190 int i;
191 unsigned long divmode;
192 int cpuclk = 0;
193 unsigned long pcode = TX4938_REV_PCODE();
194
195 ioport_resource.start = 0;
196 ioport_resource.end = 0xffffffff;
197 iomem_resource.start = 0;
198 iomem_resource.end = 0xffffffff; /* expand to 4GB */
199
200 txx9_reg_res_init(pcode, TX4938_REG_BASE,
201 TX4938_REG_SIZE);
202 /* SDRAMC,EBUSC are configured by PROM */
203 for (i = 0; i < 8; i++) {
204 if (!(TX4938_EBUSC_CR(i) & 0x8))
205 continue; /* disabled */
206 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
207 txx9_ce_res[i].end =
208 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
209 request_resource(&iomem_resource, &txx9_ce_res[i]);
210 }
211
212 /* clocks */
213 if (txx9_master_clock) {
214 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
215 /* calculate gbus_clock and cpu_clock_freq from master_clock */
216 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
217 switch (divmode) {
218 case TX4938_CCFG_DIVMODE_8:
219 case TX4938_CCFG_DIVMODE_10:
220 case TX4938_CCFG_DIVMODE_12:
221 case TX4938_CCFG_DIVMODE_16:
222 case TX4938_CCFG_DIVMODE_18:
223 txx9_gbus_clock = txx9_master_clock * 4; break;
224 default:
225 txx9_gbus_clock = txx9_master_clock;
226 }
227 switch (divmode) {
228 case TX4938_CCFG_DIVMODE_2:
229 case TX4938_CCFG_DIVMODE_8:
230 cpuclk = txx9_gbus_clock * 2; break;
231 case TX4938_CCFG_DIVMODE_2_5:
232 case TX4938_CCFG_DIVMODE_10:
233 cpuclk = txx9_gbus_clock * 5 / 2; break;
234 case TX4938_CCFG_DIVMODE_3:
235 case TX4938_CCFG_DIVMODE_12:
236 cpuclk = txx9_gbus_clock * 3; break;
237 case TX4938_CCFG_DIVMODE_4:
238 case TX4938_CCFG_DIVMODE_16:
239 cpuclk = txx9_gbus_clock * 4; break;
240 case TX4938_CCFG_DIVMODE_4_5:
241 case TX4938_CCFG_DIVMODE_18:
242 cpuclk = txx9_gbus_clock * 9 / 2; break;
243 }
244 txx9_cpu_clock = cpuclk;
245 } else {
246 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
247 if (txx9_cpu_clock == 0) {
248 txx9_cpu_clock = 300000000; /* 300MHz */
249 }
250 /* calculate gbus_clock and master_clock from cpu_clock_freq */
251 cpuclk = txx9_cpu_clock;
252 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
253 switch (divmode) {
254 case TX4938_CCFG_DIVMODE_2:
255 case TX4938_CCFG_DIVMODE_8:
256 txx9_gbus_clock = cpuclk / 2; break;
257 case TX4938_CCFG_DIVMODE_2_5:
258 case TX4938_CCFG_DIVMODE_10:
259 txx9_gbus_clock = cpuclk * 2 / 5; break;
260 case TX4938_CCFG_DIVMODE_3:
261 case TX4938_CCFG_DIVMODE_12:
262 txx9_gbus_clock = cpuclk / 3; break;
263 case TX4938_CCFG_DIVMODE_4:
264 case TX4938_CCFG_DIVMODE_16:
265 txx9_gbus_clock = cpuclk / 4; break;
266 case TX4938_CCFG_DIVMODE_4_5:
267 case TX4938_CCFG_DIVMODE_18:
268 txx9_gbus_clock = cpuclk * 2 / 9; break;
269 }
270 switch (divmode) {
271 case TX4938_CCFG_DIVMODE_8:
272 case TX4938_CCFG_DIVMODE_10:
273 case TX4938_CCFG_DIVMODE_12:
274 case TX4938_CCFG_DIVMODE_16:
275 case TX4938_CCFG_DIVMODE_18:
276 txx9_master_clock = txx9_gbus_clock / 4; break;
277 default:
278 txx9_master_clock = txx9_gbus_clock;
279 }
280 }
281 /* change default value to udelay/mdelay take reasonable time */
282 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
283
284 /* CCFG */
285 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
286 tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
287 /* do reset on watchdog */
288 tx4938_ccfg_set(TX4938_CCFG_WR);
289 /* clear PCIC1 reset */
290 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
291
292 /* enable Timeout BusError */
293 if (tx4938_ccfg_toeon)
294 tx4938_ccfg_set(TX4938_CCFG_TOE);
295
296 /* DMA selection */
297 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
298
299 /* Use external clock for external arbiter */
300 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
301 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
302
303 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
304 txx9_pcode_str,
305 (cpuclk + 500000) / 1000000,
306 (txx9_master_clock + 500000) / 1000000,
307 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
308 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
309 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
310
311 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
312 for (i = 0; i < 4; i++) {
313 u64 cr = TX4938_SDRAMC_CR(i);
314 unsigned long ram_base, ram_size;
315 if (!((unsigned long)cr & 0x00000400))
316 continue; /* disabled */
317 ram_base = (unsigned long)(cr >> 49) << 21;
318 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
319 if (ram_base >= 0x20000000)
320 continue; /* high memory (ignore) */
321 printk(KERN_CONT " CR%d:%016llx", i, cr);
322 tx4938_sdram_resource[i].name = "SDRAM";
323 tx4938_sdram_resource[i].start = ram_base;
324 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
325 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
326 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
327 }
328 printk(KERN_CONT " TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr));
329
330 /* SRAM */
331 if (____raw_readq(&tx4938_sramcptr->cr) & 1) {
332 unsigned int size = 0x800;
333 unsigned long base =
334 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
335 & ~(size - 1);
336 tx4938_sram_resource.name = "SRAM";
337 tx4938_sram_resource.start = base;
338 tx4938_sram_resource.end = base + size - 1;
339 tx4938_sram_resource.flags = IORESOURCE_MEM;
340 request_resource(&iomem_resource, &tx4938_sram_resource);
341 }
342
343 /* TMR */
344 for (i = 0; i < TX4938_NR_TMR; i++)
345 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
346
347 /* enable DMA */
348 for (i = 0; i < 2; i++)
349 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
350 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
351
352 /* PIO */
353 __raw_writel(0, &tx4938_pioptr->maskcpu);
354 __raw_writel(0, &tx4938_pioptr->maskext);
355
356#ifdef CONFIG_PCI
357 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
358#endif
359}
360 178
361static void __init rbtx4938_time_init(void) 179static void __init rbtx4938_time_init(void)
362{ 180{
363 mips_hpt_frequency = txx9_cpu_clock / 2; 181 tx4938_time_init(0);
364 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
365 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
366 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
367 txx9_gbus_clock / 2);
368} 182}
369 183
370static void __init rbtx4938_mem_setup(void) 184static void __init rbtx4938_mem_setup(void)
@@ -372,39 +186,24 @@ static void __init rbtx4938_mem_setup(void)
372 unsigned long long pcfg; 186 unsigned long long pcfg;
373 char *argptr; 187 char *argptr;
374 188
375 iomem_resource.end = 0xffffffff; /* 4GB */
376
377 if (txx9_master_clock == 0) 189 if (txx9_master_clock == 0)
378 txx9_master_clock = 25000000; /* 25MHz */ 190 txx9_master_clock = 25000000; /* 25MHz */
379 tx4938_board_setup(); 191
380#ifndef CONFIG_PCI 192 tx4938_setup();
193
194#ifdef CONFIG_PCI
195 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
196#else
381 set_io_port_base(RBTX4938_ETHER_BASE); 197 set_io_port_base(RBTX4938_ETHER_BASE);
382#endif 198#endif
383 199
384#ifdef CONFIG_SERIAL_TXX9 200 tx4938_setup_serial();
385 {
386 extern int early_serial_txx9_setup(struct uart_port *port);
387 int i;
388 struct uart_port req;
389 for(i = 0; i < 2; i++) {
390 memset(&req, 0, sizeof(req));
391 req.line = i;
392 req.iotype = UPIO_MEM;
393 req.membase = (char *)(0xff1ff300 + i * 0x100);
394 req.mapbase = 0xff1ff300 + i * 0x100;
395 req.irq = RBTX4938_IRQ_IRC_SIO(i);
396 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
397 req.uartclk = 50000000;
398 early_serial_txx9_setup(&req);
399 }
400 }
401#ifdef CONFIG_SERIAL_TXX9_CONSOLE 201#ifdef CONFIG_SERIAL_TXX9_CONSOLE
402 argptr = prom_getcmdline(); 202 argptr = prom_getcmdline();
403 if (strstr(argptr, "console=") == NULL) { 203 if (strstr(argptr, "console=") == NULL) {
404 strcat(argptr, " console=ttyS0,38400"); 204 strcat(argptr, " console=ttyS0,38400");
405 } 205 }
406#endif 206#endif
407#endif
408 207
409#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 208#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
410 printk("PIOSEL: disabling both ata and nand selection\n"); 209 printk("PIOSEL: disabling both ata and nand selection\n");
@@ -568,7 +367,6 @@ static int __init rbtx4938_spi_init(void)
568 367
569static void __init rbtx4938_arch_init(void) 368static void __init rbtx4938_arch_init(void)
570{ 369{
571 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
572 gpiochip_add(&rbtx4938_spi_gpio_chip); 370 gpiochip_add(&rbtx4938_spi_gpio_chip);
573 rbtx4938_pci_setup(); 371 rbtx4938_pci_setup();
574 rbtx4938_spi_init(); 372 rbtx4938_spi_init();
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 01:28:43 -0500