diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2009-11-10 04:20:30 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-11-18 04:40:44 -0500 |
commit | e676756fa43e04166111e4729c62bb4fdf477255 (patch) | |
tree | 2334b7f48d5b20b9315908b50d4a8b18ac29a6ba /arch | |
parent | f73a42f7054b4ec7fab373789b7dae1e309f81a7 (diff) |
imx: reorder mx3x.h
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx3x.h | 45 |
1 files changed, 23 insertions, 22 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 009f4440276b..3e07d3da104d 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h | |||
@@ -34,21 +34,6 @@ | |||
34 | * C0000000 64M PCMCIA/CF | 34 | * C0000000 64M PCMCIA/CF |
35 | */ | 35 | */ |
36 | 36 | ||
37 | #define CS0_BASE_ADDR 0xA0000000 | ||
38 | #define CS1_BASE_ADDR 0xA8000000 | ||
39 | #define CS2_BASE_ADDR 0xB0000000 | ||
40 | #define CS3_BASE_ADDR 0xB2000000 | ||
41 | |||
42 | #define CS4_BASE_ADDR 0xB4000000 | ||
43 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
44 | #define CS4_SIZE SZ_32M | ||
45 | |||
46 | #define CS5_BASE_ADDR 0xB6000000 | ||
47 | #define CS5_BASE_ADDR_VIRT 0xF6000000 | ||
48 | #define CS5_SIZE SZ_32M | ||
49 | |||
50 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
51 | |||
52 | /* | 37 | /* |
53 | * L2CC | 38 | * L2CC |
54 | */ | 39 | */ |
@@ -101,6 +86,7 @@ | |||
101 | #define AIPS2_BASE_ADDR 0x53F00000 | 86 | #define AIPS2_BASE_ADDR 0x53F00000 |
102 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 | 87 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 |
103 | #define AIPS2_SIZE SZ_1M | 88 | #define AIPS2_SIZE SZ_1M |
89 | |||
104 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) | 90 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) |
105 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) | 91 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) |
106 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) | 92 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) |
@@ -130,6 +116,27 @@ | |||
130 | #define AVIC_SIZE SZ_1M | 116 | #define AVIC_SIZE SZ_1M |
131 | 117 | ||
132 | /* | 118 | /* |
119 | * Memory regions and CS | ||
120 | */ | ||
121 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
122 | #define CSD0_BASE_ADDR 0x80000000 | ||
123 | #define CSD1_BASE_ADDR 0x90000000 | ||
124 | |||
125 | #define CS0_BASE_ADDR 0xA0000000 | ||
126 | #define CS1_BASE_ADDR 0xA8000000 | ||
127 | #define CS2_BASE_ADDR 0xB0000000 | ||
128 | #define CS3_BASE_ADDR 0xB2000000 | ||
129 | |||
130 | #define CS4_BASE_ADDR 0xB4000000 | ||
131 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
132 | #define CS4_SIZE SZ_32M | ||
133 | |||
134 | #define CS5_BASE_ADDR 0xB6000000 | ||
135 | #define CS5_BASE_ADDR_VIRT 0xF6000000 | ||
136 | #define CS5_SIZE SZ_32M | ||
137 | |||
138 | |||
139 | /* | ||
133 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 140 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
134 | */ | 141 | */ |
135 | #define X_MEMC_BASE_ADDR 0xB8000000 | 142 | #define X_MEMC_BASE_ADDR 0xB8000000 |
@@ -142,12 +149,7 @@ | |||
142 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | 149 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) |
143 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR | 150 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR |
144 | 151 | ||
145 | /* | 152 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 |
146 | * Memory regions and CS | ||
147 | */ | ||
148 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
149 | #define CSD0_BASE_ADDR 0x80000000 | ||
150 | #define CSD1_BASE_ADDR 0x90000000 | ||
151 | 153 | ||
152 | /*! | 154 | /*! |
153 | * This macro defines the physical to virtual address mapping for all the | 155 | * This macro defines the physical to virtual address mapping for all the |
@@ -272,4 +274,3 @@ static inline int mx31_revision(void) | |||
272 | #endif | 274 | #endif |
273 | 275 | ||
274 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | 276 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ |
275 | |||