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authorErik Gilling <konkers@android.com>2010-01-21 19:53:02 -0500
committerErik Gilling <konkers@android.com>2010-08-05 17:51:42 -0400
commitc5f800656bc985b448b1d848d309648826536543 (patch)
treeefac337e79b73bf24ce639840e41f77bcd46d707 /arch
parentcdd854bc42b5e6c79bbbc40c6600d995ffe6e747 (diff)
[ARM] tegra: initial tegra support
v2: Fixes from Mike Rapoport - remove unused header files (mach/dma.h and mach/nand.h) - remove tegra 1 references from Makefile.boot v2: fixes from Russell King - remove mach/io.h include from mach/iomap.h - fix whitespace in Kconfig v2: from Colin Cross - fix invalid immediate in debug-macro.S v3: - allow selection of multiple boards Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig13
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-tegra/Kconfig49
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/Makefile.boot3
-rw-r--r--arch/arm/mach-tegra/board.h32
-rw-r--r--arch/arm/mach-tegra/common.c44
-rw-r--r--arch/arm/mach-tegra/include/mach/barriers.h30
-rw-r--r--arch/arm/mach-tegra/include/mach/debug-macro.S46
-rw-r--r--arch/arm/mach-tegra/include/mach/entry-macro.S118
-rw-r--r--arch/arm/mach-tegra/include/mach/hardware.h24
-rw-r--r--arch/arm/mach-tegra/include/mach/io.h79
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h203
-rw-r--r--arch/arm/mach-tegra/include/mach/memory.h28
-rw-r--r--arch/arm/mach-tegra/include/mach/system.h39
-rw-r--r--arch/arm/mach-tegra/include/mach/timex.h26
-rw-r--r--arch/arm/mach-tegra/include/mach/uncompress.h78
-rw-r--r--arch/arm/mach-tegra/include/mach/vmalloc.h28
-rw-r--r--arch/arm/mach-tegra/io.c78
-rw-r--r--arch/arm/mm/Kconfig3
20 files changed, 923 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e39caa8b0c93..56d2c4291e43 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -562,6 +562,17 @@ config ARCH_NUC93X
562 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a 562 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
563 low-power and high performance MPEG-4/JPEG multimedia controller chip. 563 low-power and high performance MPEG-4/JPEG multimedia controller chip.
564 564
565config ARCH_TEGRA
566 bool "NVIDIA Tegra"
567 select GENERIC_TIME
568 select GENERIC_CLOCKEVENTS
569 select GENERIC_GPIO
570 select HAVE_CLK
571 select ARCH_HAS_BARRIERS if CACHE_L2X0
572 help
573 This enables support for NVIDIA Tegra based systems (Tegra APX,
574 Tegra 6xx and Tegra 2 series).
575
565config ARCH_PNX4008 576config ARCH_PNX4008
566 bool "Philips Nexperia PNX4008 Mobile" 577 bool "Philips Nexperia PNX4008 Mobile"
567 select CPU_ARM926T 578 select CPU_ARM926T
@@ -911,6 +922,8 @@ source "arch/arm/mach-shmobile/Kconfig"
911 922
912source "arch/arm/plat-stmp3xxx/Kconfig" 923source "arch/arm/plat-stmp3xxx/Kconfig"
913 924
925source "arch/arm/mach-tegra/Kconfig"
926
914source "arch/arm/mach-u300/Kconfig" 927source "arch/arm/mach-u300/Kconfig"
915 928
916source "arch/arm/mach-ux500/Kconfig" 929source "arch/arm/mach-ux500/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 63d998e8c672..a8d4dca9da35 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -179,6 +179,7 @@ machine-$(CONFIG_ARCH_SHARK) := shark
179machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 179machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
180machine-$(CONFIG_ARCH_STMP378X) := stmp378x 180machine-$(CONFIG_ARCH_STMP378X) := stmp378x
181machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx 181machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
182machine-$(CONFIG_ARCH_TEGRA) := tegra
182machine-$(CONFIG_ARCH_U300) := u300 183machine-$(CONFIG_ARCH_U300) := u300
183machine-$(CONFIG_ARCH_U8500) := ux500 184machine-$(CONFIG_ARCH_U8500) := ux500
184machine-$(CONFIG_ARCH_VERSATILE) := versatile 185machine-$(CONFIG_ARCH_VERSATILE) := versatile
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
new file mode 100644
index 000000000000..bcbda96ec84c
--- /dev/null
+++ b/arch/arm/mach-tegra/Kconfig
@@ -0,0 +1,49 @@
1if ARCH_TEGRA
2
3comment "NVIDIA Tegra options"
4
5choice
6 prompt "Select Tegra processor family for target system"
7
8config ARCH_TEGRA_2x_SOC
9 bool "Tegra 2 family"
10 select CPU_V7
11 select ARM_GIC
12 help
13 Support for NVIDIA Tegra AP20 and T20 processors, based on the
14 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
15
16endchoice
17
18comment "Tegra board type"
19
20config MACH_HARMONY
21 bool "Harmony board"
22 help
23 Support for nVidia Harmony development platform
24
25choice
26 prompt "Low-level debug console UART"
27 default TEGRA_DEBUG_UART_NONE
28
29config TEGRA_DEBUG_UART_NONE
30 bool "None"
31
32config TEGRA_DEBUG_UARTA
33 bool "UART-A"
34
35config TEGRA_DEBUG_UARTB
36 bool "UART-B"
37
38config TEGRA_DEBUG_UARTC
39 bool "UART-C"
40
41config TEGRA_DEBUG_UARTD
42 bool "UART-D"
43
44config TEGRA_DEBUG_UARTE
45 bool "UART-E"
46
47endchoice
48
49endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
new file mode 100644
index 000000000000..81f003dcb26c
--- /dev/null
+++ b/arch/arm/mach-tegra/Makefile
@@ -0,0 +1,2 @@
1obj-y += common.o
2obj-y += io.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
new file mode 100644
index 000000000000..db52d61a7386
--- /dev/null
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -0,0 +1,3 @@
1zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00008000
2params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
new file mode 100644
index 000000000000..3d06354136f2
--- /dev/null
+++ b/arch/arm/mach-tegra/board.h
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-tegra/board.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_BOARD_H
22#define __MACH_TEGRA_BOARD_H
23
24#include <linux/types.h>
25
26void __init tegra_common_init(void);
27void __init tegra_map_common_io(void);
28void __init tegra_init_irq(void);
29void __init tegra_init_clock(void);
30
31extern struct sys_timer tegra_timer;
32#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
new file mode 100644
index 000000000000..20875ee8f039
--- /dev/null
+++ b/arch/arm/mach-tegra/common.c
@@ -0,0 +1,44 @@
1/*
2 * arch/arm/mach-tegra/board-harmony.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/init.h>
21#include <linux/io.h>
22
23#include <asm/hardware/cache-l2x0.h>
24
25#include <mach/iomap.h>
26
27#include "board.h"
28
29void __init tegra_init_cache(void)
30{
31#ifdef CONFIG_CACHE_L2X0
32 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
33
34 writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
35 writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
36
37 l2x0_init(p, 0x6C080001, 0x8200c3fe);
38#endif
39}
40
41void __init tegra_common_init(void)
42{
43 tegra_init_cache();
44}
diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h
new file mode 100644
index 000000000000..cc115174899b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/barriers.h
@@ -0,0 +1,30 @@
1/*
2 * arch/arm/mach-realview/include/mach/barriers.h
3 *
4 * Copyright (C) 2010 ARM Ltd.
5 * Written by Catalin Marinas <catalin.marinas@arm.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __MACH_BARRIERS_H
22#define __MACH_BARRIERS_H
23
24#include <asm/outercache.h>
25
26#define rmb() dmb()
27#define wmb() do { dsb(); outer_sync(); } while (0)
28#define mb() wmb()
29
30#endif /* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
new file mode 100644
index 000000000000..55a39564b43c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-tegra/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <mach/io.h>
22
23 .macro addruart,rx, tmp
24 mrc p15, 0, \rx, c1, c0
25 tst \rx, #1 @ MMU enabled?
26 ldreq \rx, =IO_APB_PHYS @ physical
27 ldrne \rx, =IO_APB_VIRT @ virtual
28#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
29#error "A debug UART must be selected in the kernel config to use DEBUG_LL"
30#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
31 orr \rx, \rx, #0x6000
32#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
33 ldr \tmp, =0x6040
34 orr \rx, \rx, \tmp
35#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
36 orr \rx, \rx, #0x6200
37#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
38 orr \rx, \rx, #0x6300
39#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
40 orr \rx, \rx, #0x6400
41#endif
42 .endm
43
44#define UART_SHIFT 2
45#include <asm/hardware/debug-8250.S>
46
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
new file mode 100644
index 000000000000..2ba9e5c9d2f6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -0,0 +1,118 @@
1/* arch/arm/mach-tegra/include/mach/entry-macro.S
2 *
3 * Copyright (C) 2009 Palm, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15#include <mach/iomap.h>
16#include <mach/io.h>
17
18#if defined(CONFIG_ARM_GIC)
19
20#include <asm/hardware/gic.h>
21
22 /* Uses the GIC interrupt controller built into the cpu */
23#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
24
25 .macro disable_fiq
26 .endm
27
28 .macro get_irqnr_preamble, base, tmp
29 movw \base, #(ICTRL_BASE & 0x0000ffff)
30 movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
35
36 /*
37 * The interrupt numbering scheme is defined in the
38 * interrupt controller spec. To wit:
39 *
40 * Interrupts 0-15 are IPI
41 * 16-28 are reserved
42 * 29-31 are local. We allow 30 to be used for the watchdog.
43 * 32-1020 are global
44 * 1021-1022 are reserved
45 * 1023 is "spurious" (no interrupt)
46 *
47 * For now, we ignore all local interrupts so only return an interrupt
48 * if it's between 30 and 1020. The test_for_ipi routine below will
49 * pick up on IPIs.
50 *
51 * A simple read from the controller will tell us the number of the
52 * highest priority enabled interrupt. We then just need to check
53 * whether it is in the valid range for an IRQ (30-1020 inclusive).
54 */
55
56 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
57
58 /* bits 12-10 = src CPU, 9-0 = int # */
59 ldr \irqstat, [\base, #GIC_CPU_INTACK]
60
61 ldr \tmp, =1021
62
63 bic \irqnr, \irqstat, #0x1c00
64
65 cmp \irqnr, #29
66 cmpcc \irqnr, \irqnr
67 cmpne \irqnr, \tmp
68 cmpcs \irqnr, \irqnr
69
70 .endm
71
72 /* We assume that irqstat (the raw value of the IRQ acknowledge
73 * register) is preserved from the macro above.
74 * If there is an IPI, we immediately signal end of interrupt on the
75 * controller, since this requires the original irqstat value which
76 * we won't easily be able to recreate later.
77 */
78
79 .macro test_for_ipi, irqnr, irqstat, base, tmp
80 bic \irqnr, \irqstat, #0x1c00
81 cmp \irqnr, #16
82 strcc \irqstat, [\base, #GIC_CPU_EOI]
83 cmpcs \irqnr, \irqnr
84 .endm
85
86 /* As above, this assumes that irqstat and base are preserved.. */
87
88 .macro test_for_ltirq, irqnr, irqstat, base, tmp
89 bic \irqnr, \irqstat, #0x1c00
90 mov \tmp, #0
91 cmp \irqnr, #29
92 moveq \tmp, #1
93 streq \irqstat, [\base, #GIC_CPU_EOI]
94 cmp \tmp, #0
95 .endm
96
97#else
98 /* legacy interrupt controller for AP16 */
99 .macro disable_fiq
100 .endm
101
102 .macro get_irqnr_preamble, base, tmp
103 @ enable imprecise aborts
104 cpsie a
105 @ EVP base at 0xf010f000
106 mov \base, #0xf0000000
107 orr \base, #0x00100000
108 orr \base, #0x0000f000
109 .endm
110
111 .macro arch_ret_to_user, tmp1, tmp2
112 .endm
113
114 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
115 ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS
116 cmp \irqnr, #0x80
117 .endm
118#endif
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
new file mode 100644
index 000000000000..6014edf60d93
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/hardware.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-tegra/include/mach/hardware.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_HARDWARE_H
22#define __MACH_TEGRA_HARDWARE_H
23
24#endif
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
new file mode 100644
index 000000000000..35edfc32ffc9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -0,0 +1,79 @@
1/*
2 * arch/arm/mach-tegra/include/mach/io.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IO_H
22#define __MACH_TEGRA_IO_H
23
24#define IO_SPACE_LIMIT 0xffffffff
25
26/* On TEGRA, many peripherals are very closely packed in
27 * two 256MB io windows (that actually only use about 64KB
28 * at the start of each).
29 *
30 * We will just map the first 1MB of each window (to minimize
31 * pt entries needed) and provide a macro to transform physical
32 * io addresses to an appropriate void __iomem *.
33 *
34 */
35
36#define IO_CPU_PHYS 0x50040000
37#define IO_CPU_VIRT 0xFE000000
38#define IO_CPU_SIZE SZ_16K
39
40#define IO_PPSB_PHYS 0x60000000
41#define IO_PPSB_VIRT 0xFE200000
42#define IO_PPSB_SIZE SZ_1M
43
44#define IO_APB_PHYS 0x70000000
45#define IO_APB_VIRT 0xFE300000
46#define IO_APB_SIZE SZ_1M
47
48#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
49#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
50
51#define IO_TO_VIRT(n) ( \
52 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
53 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
54 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
55 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
56 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
57 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
58 0)
59
60#ifndef __ASSEMBLER__
61
62#define __arch_ioremap(p, s, t) tegra_ioremap(p, s, t)
63#define __arch_iounmap(v) tegra_iounmap(v)
64
65void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
66void tegra_iounmap(volatile void __iomem *addr);
67
68#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
69
70static inline void __iomem *__io(unsigned long addr)
71{
72 return (void __iomem *)addr;
73}
74#define __io(a) __io(a)
75#define __mem_pci(a) (a)
76
77#endif
78
79#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
new file mode 100644
index 000000000000..1741f7dd7a9b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -0,0 +1,203 @@
1/*
2 * arch/arm/mach-tegra/include/mach/iomap.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IOMAP_H
22#define __MACH_TEGRA_IOMAP_H
23
24#include <asm/sizes.h>
25
26#define TEGRA_ARM_PERIF_BASE 0x50040000
27#define TEGRA_ARM_PERIF_SIZE SZ_8K
28
29#define TEGRA_ARM_INT_DIST_BASE 0x50041000
30#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
31
32#define TEGRA_DISPLAY_BASE 0x54200000
33#define TEGRA_DISPLAY_SIZE SZ_256K
34
35#define TEGRA_DISPLAY2_BASE 0x54240000
36#define TEGRA_DISPLAY2_SIZE SZ_256K
37
38#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
39#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
40
41#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
42#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
43
44#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
45#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
46
47#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
48#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
49
50#define TEGRA_TMR1_BASE 0x60005000
51#define TEGRA_TMR1_SIZE SZ_8
52
53#define TEGRA_TMR2_BASE 0x60005008
54#define TEGRA_TMR2_SIZE SZ_8
55
56#define TEGRA_TMRUS_BASE 0x60005010
57#define TEGRA_TMRUS_SIZE SZ_64
58
59#define TEGRA_TMR3_BASE 0x60005050
60#define TEGRA_TMR3_SIZE SZ_8
61
62#define TEGRA_TMR4_BASE 0x60005058
63#define TEGRA_TMR4_SIZE SZ_8
64
65#define TEGRA_CLK_RESET_BASE 0x60006000
66#define TEGRA_CLK_RESET_SIZE SZ_4K
67
68#define TEGRA_FLOW_CTRL_BASE 0x60007000
69#define TEGRA_FLOW_CTRL_SIZE 20
70
71#define TEGRA_STATMON_BASE 0x6000C4000
72#define TEGRA_STATMON_SIZE SZ_1K
73
74#define TEGRA_GPIO_BASE 0x6000D000
75#define TEGRA_GPIO_SIZE SZ_4K
76
77#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
78#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
79
80#define TEGRA_APB_MISC_BASE 0x70000000
81#define TEGRA_APB_MISC_SIZE SZ_4K
82
83#define TEGRA_AC97_BASE 0x70002000
84#define TEGRA_AC97_SIZE SZ_512
85
86#define TEGRA_SPDIF_BASE 0x70002400
87#define TEGRA_SPDIF_SIZE SZ_512
88
89#define TEGRA_I2S1_BASE 0x70002800
90#define TEGRA_I2S1_SIZE SZ_256
91
92#define TEGRA_I2S2_BASE 0x70002A00
93#define TEGRA_I2S2_SIZE SZ_256
94
95#define TEGRA_UARTA_BASE 0x70006000
96#define TEGRA_UARTA_SIZE SZ_64
97
98#define TEGRA_UARTB_BASE 0x70006040
99#define TEGRA_UARTB_SIZE SZ_64
100
101#define TEGRA_UARTC_BASE 0x70006200
102#define TEGRA_UARTC_SIZE SZ_256
103
104#define TEGRA_UARTD_BASE 0x70006300
105#define TEGRA_UARTD_SIZE SZ_256
106
107#define TEGRA_UARTE_BASE 0x70006400
108#define TEGRA_UARTE_SIZE SZ_256
109
110#define TEGRA_NAND_BASE 0x70008000
111#define TEGRA_NAND_SIZE SZ_256
112
113#define TEGRA_HSMMC_BASE 0x70008500
114#define TEGRA_HSMMC_SIZE SZ_256
115
116#define TEGRA_SNOR_BASE 0x70009000
117#define TEGRA_SNOR_SIZE SZ_4K
118
119#define TEGRA_PWFM_BASE 0x7000A000
120#define TEGRA_PWFM_SIZE SZ_256
121
122#define TEGRA_MIPI_BASE 0x7000B000
123#define TEGRA_MIPI_SIZE SZ_256
124
125#define TEGRA_I2C_BASE 0x7000C000
126#define TEGRA_I2C_SIZE SZ_256
127
128#define TEGRA_TWC_BASE 0x7000C100
129#define TEGRA_TWC_SIZE SZ_256
130
131#define TEGRA_SPI_BASE 0x7000C380
132#define TEGRA_SPI_SIZE 48
133
134#define TEGRA_I2C2_BASE 0x7000C400
135#define TEGRA_I2C2_SIZE SZ_256
136
137#define TEGRA_I2C3_BASE 0x7000C500
138#define TEGRA_I2C3_SIZE SZ_256
139
140#define TEGRA_OWR_BASE 0x7000D000
141#define TEGRA_OWR_SIZE 80
142
143#define TEGRA_DVC_BASE 0x7000D000
144#define TEGRA_DVC_SIZE SZ_512
145
146#define TEGRA_SPI1_BASE 0x7000D400
147#define TEGRA_SPI1_SIZE SZ_512
148
149#define TEGRA_SPI2_BASE 0x7000D600
150#define TEGRA_SPI2_SIZE SZ_512
151
152#define TEGRA_SPI3_BASE 0x7000D800
153#define TEGRA_SPI3_SIZE SZ_512
154
155#define TEGRA_SPI4_BASE 0x7000DA00
156#define TEGRA_SPI4_SIZE SZ_512
157
158#define TEGRA_RTC_BASE 0x7000E000
159#define TEGRA_RTC_SIZE SZ_256
160
161#define TEGRA_KBC_BASE 0x7000E200
162#define TEGRA_KBC_SIZE SZ_256
163
164#define TEGRA_PMC_BASE 0x7000E400
165#define TEGRA_PMC_SIZE SZ_256
166
167#define TEGRA_MC_BASE 0x7000F000
168#define TEGRA_MC_SIZE SZ_1K
169
170#define TEGRA_EMC_BASE 0x7000F400
171#define TEGRA_EMC_SIZE SZ_1K
172
173#define TEGRA_FUSE_BASE 0x7000F800
174#define TEGRA_FUSE_SIZE SZ_1K
175
176#define TEGRA_KFUSE_BASE 0x7000FC00
177#define TEGRA_KFUSE_SIZE SZ_1K
178
179#define TEGRA_CSITE_BASE 0x70040000
180#define TEGRA_CSITE_SIZE SZ_256K
181
182#define TEGRA_USB_BASE 0xC5000000
183#define TEGRA_USB_SIZE SZ_16K
184
185#define TEGRA_USB1_BASE 0xC5004000
186#define TEGRA_USB1_SIZE SZ_16K
187
188#define TEGRA_USB2_BASE 0xC5008000
189#define TEGRA_USB2_SIZE SZ_16K
190
191#define TEGRA_SDMMC1_BASE 0xC8000000
192#define TEGRA_SDMMC1_SIZE SZ_512
193
194#define TEGRA_SDMMC2_BASE 0xC8000200
195#define TEGRA_SDMMC2_SIZE SZ_512
196
197#define TEGRA_SDMMC3_BASE 0xC8000400
198#define TEGRA_SDMMC3_SIZE SZ_512
199
200#define TEGRA_SDMMC4_BASE 0xC8000600
201#define TEGRA_SDMMC4_SIZE SZ_512
202
203#endif
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
new file mode 100644
index 000000000000..6151bab62af2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/memory.h
@@ -0,0 +1,28 @@
1/*
2 * arch/arm/mach-tegra/include/mach/memory.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_MEMORY_H
22#define __MACH_TEGRA_MEMORY_H
23
24/* physical offset of RAM */
25#define PHYS_OFFSET UL(0)
26
27#endif
28
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
new file mode 100644
index 000000000000..84d5d46113f7
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-tegra/include/mach/system.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_SYSTEM_H
22#define __MACH_TEGRA_SYSTEM_H
23
24#include <mach/hardware.h>
25#include <mach/iomap.h>
26
27static inline void arch_idle(void)
28{
29}
30
31static inline void arch_reset(char mode, const char *cmd)
32{
33 void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
34 u32 reg = readl(reset);
35 reg |= 0x04;
36 writel(reg, reset);
37}
38
39#endif
diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h
new file mode 100644
index 000000000000..a44ccbdb7dbf
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/timex.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-tegra/include/mach/timex.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_TIMEX_H
22#define __MACH_TEGRA_TIMEX_H
23
24#define CLOCK_TICK_RATE 1000000
25
26#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
new file mode 100644
index 000000000000..6c4dd815abd7
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -0,0 +1,78 @@
1/*
2 * arch/arm/mach-tegra/include/mach/uncompress.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_UNCOMPRESS_H
22#define __MACH_TEGRA_UNCOMPRESS_H
23
24#include <linux/types.h>
25#include <linux/serial_reg.h>
26
27#include <mach/iomap.h>
28
29#if defined(CONFIG_TEGRA_DEBUG_UARTA)
30#define DEBUG_UART_BASE TEGRA_UARTA_BASE
31#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
32#define DEBUG_UART_BASE TEGRA_UARTB_BASE
33#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
34#define DEBUG_UART_BASE TEGRA_UARTC_BASE
35#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
36#define DEBUG_UART_BASE TEGRA_UARTD_BASE
37#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
38#define DEBUG_UART_BASE TEGRA_UARTE_BASE
39#else
40#define DEBUG_UART_BASE NULL
41#endif
42
43static void putc(int c)
44{
45 volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
46 int shift = 2;
47
48 if (uart == NULL)
49 return;
50
51 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
52 barrier();
53 uart[UART_TX << shift] = c;
54}
55
56static inline void flush(void)
57{
58}
59
60static inline void arch_decomp_setup(void)
61{
62 volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
63 int shift = 2;
64
65 if (uart == NULL)
66 return;
67
68 uart[UART_LCR << shift] |= UART_LCR_DLAB;
69 uart[UART_DLL << shift] = 0x75;
70 uart[UART_DLM << shift] = 0x0;
71 uart[UART_LCR << shift] = 3;
72}
73
74static inline void arch_decomp_wdog(void)
75{
76}
77
78#endif
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
new file mode 100644
index 000000000000..267a141730d9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -0,0 +1,28 @@
1/*
2 * arch/arm/mach-tegra/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_VMALLOC_H
22#define __MACH_TEGRA_VMALLOC_H
23
24#include <asm/sizes.h>
25
26#define VMALLOC_END 0xFE000000
27
28#endif
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
new file mode 100644
index 000000000000..9fe2c5c683d4
--- /dev/null
+++ b/arch/arm/mach-tegra/io.c
@@ -0,0 +1,78 @@
1/*
2 * arch/arm/mach-tegra/io.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <asm/page.h>
29#include <asm/mach/map.h>
30
31#include "board.h"
32
33static struct map_desc tegra_io_desc[] __initdata = {
34 {
35 .virtual = IO_PPSB_VIRT,
36 .pfn = __phys_to_pfn(IO_PPSB_PHYS),
37 .length = IO_PPSB_SIZE,
38 .type = MT_DEVICE,
39 },
40 {
41 .virtual = IO_APB_VIRT,
42 .pfn = __phys_to_pfn(IO_APB_PHYS),
43 .length = IO_APB_SIZE,
44 .type = MT_DEVICE,
45 },
46 {
47 .virtual = IO_CPU_VIRT,
48 .pfn = __phys_to_pfn(IO_CPU_PHYS),
49 .length = IO_CPU_SIZE,
50 .type = MT_DEVICE,
51 },
52};
53
54void __init tegra_map_common_io(void)
55{
56 iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
57}
58
59/*
60 * Intercept ioremap() requests for addresses in our fixed mapping regions.
61 */
62void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
63{
64 void __iomem *v = IO_ADDRESS(p);
65 if (v == NULL)
66 v = __arm_ioremap(p, size, type);
67 return v;
68}
69EXPORT_SYMBOL(tegra_ioremap);
70
71void tegra_iounmap(volatile void __iomem *addr)
72{
73 unsigned long virt = (unsigned long)addr;
74
75 if (virt >= VMALLOC_START && virt < VMALLOC_END)
76 __iounmap(addr);
77}
78EXPORT_SYMBOL(tegra_iounmap);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 87ec141fcaa6..e1fd98fff8fa 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -771,7 +771,8 @@ config CACHE_L2X0
771 bool "Enable the L2x0 outer cache controller" 771 bool "Enable the L2x0 outer cache controller"
772 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 772 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
773 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ 773 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
774 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 774 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
775 ARCH_TEGRA
775 default y 776 default y
776 select OUTER_CACHE 777 select OUTER_CACHE
777 select OUTER_CACHE_SYNC 778 select OUTER_CACHE_SYNC
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 15:29:07 -0500