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authorHaojian Zhuang <haojian.zhuang@linaro.org>2013-12-11 02:54:51 -0500
committerKevin Hilman <khilman@linaro.org>2013-12-17 19:43:32 -0500
commitfa8962a8bb84cad2902cc7e2f3682cbc7450ab86 (patch)
tree2dede6e2c563ca71450605c90fdaa34410f98189 /arch
parent2c7268c70fc1099ce4aac83c194675efd927e90f (diff)
ARM: dts: enable hi4511 with device tree
Enable Hisilicon Hi4511 development platform with device tree support. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/hi3620.dtsi518
-rw-r--r--arch/arm/boot/dts/hi4511.dts648
3 files changed, 1167 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a65b24f..a4c771fff734 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
66 exynos5420-smdk5420.dtb \ 66 exynos5420-smdk5420.dtb \
67 exynos5440-sd5v1.dtb \ 67 exynos5440-sd5v1.dtb \
68 exynos5440-ssdk5440.dtb 68 exynos5440-ssdk5440.dtb
69dtb-$(CONFIG_ARCH_HI3xxx) += hi4511.dtb
69dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 70dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
70 ecx-2000.dtb 71 ecx-2000.dtb
71dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 72dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
new file mode 100644
index 000000000000..b9d86795ed5a
--- /dev/null
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -0,0 +1,518 @@
1/*
2 * Hisilicon Ltd. Hi3620 SoC
3 *
4 * Copyright (C) 2012-2013 Hisilicon Ltd.
5 * Copyright (C) 2012-2013 Linaro Ltd.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * publishhed by the Free Software Foundation.
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 aliases {
18 serial0 = &uart0;
19 serial1 = &uart1;
20 serial2 = &uart2;
21 serial3 = &uart3;
22 serial4 = &uart4;
23 };
24
25 pclk: clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0x0>;
40 next-level-cache = <&L2>;
41 };
42 };
43
44 amba {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "arm,amba-bus";
48 interrupt-parent = <&gic>;
49 ranges = <0 0xfc000000 0x2000000>;
50
51 L2: l2-cache {
52 compatible = "arm,pl310-cache";
53 reg = <0xfc10000 0x100000>;
54 interrupts = <0 15 4>;
55 cache-unified;
56 cache-level = <2>;
57 };
58
59 gic: interrupt-controller@1000 {
60 compatible = "arm,cortex-a9-gic";
61 #interrupt-cells = <3>;
62 #address-cells = <0>;
63 interrupt-controller;
64 /* gic dist base, gic cpu base */
65 reg = <0x1000 0x1000>, <0x100 0x100>;
66 };
67
68 dual_timer0: dual_timer@800000 {
69 compatible = "arm,sp804", "arm,primecell";
70 reg = <0x800000 0x1000>;
71 /* timer00 & timer01 */
72 interrupts = <0 0 4>, <0 1 4>;
73 clocks = <&pclk>;
74 clock-names = "apb_pclk";
75 status = "disabled";
76 };
77
78 dual_timer1: dual_timer@801000 {
79 compatible = "arm,sp804", "arm,primecell";
80 reg = <0x801000 0x1000>;
81 /* timer10 & timer11 */
82 interrupts = <0 2 4>, <0 3 4>;
83 clocks = <&pclk>;
84 clock-names = "apb_pclk";
85 status = "disabled";
86 };
87
88 dual_timer2: dual_timer@a01000 {
89 compatible = "arm,sp804", "arm,primecell";
90 reg = <0xa01000 0x1000>;
91 /* timer20 & timer21 */
92 interrupts = <0 4 4>, <0 5 4>;
93 clocks = <&pclk>;
94 clock-names = "apb_pclk";
95 status = "disabled";
96 };
97
98 dual_timer3: dual_timer@a02000 {
99 compatible = "arm,sp804", "arm,primecell";
100 reg = <0xa02000 0x1000>;
101 /* timer30 & timer31 */
102 interrupts = <0 6 4>, <0 7 4>;
103 clocks = <&pclk>;
104 clock-names = "apb_pclk";
105 status = "disabled";
106 };
107
108 dual_timer4: dual_timer@a03000 {
109 compatible = "arm,sp804", "arm,primecell";
110 reg = <0xa03000 0x1000>;
111 /* timer40 & timer41 */
112 interrupts = <0 96 4>, <0 97 4>;
113 clocks = <&pclk>;
114 clock-names = "apb_pclk";
115 status = "disabled";
116 };
117
118 uart0: uart@b00000 {
119 compatible = "arm,pl011", "arm,primecell";
120 reg = <0xb00000 0x1000>;
121 interrupts = <0 20 4>;
122 clocks = <&pclk>;
123 clock-names = "apb_pclk";
124 status = "disabled";
125 };
126
127 uart1: uart@b01000 {
128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0xb01000 0x1000>;
130 interrupts = <0 21 4>;
131 clocks = <&pclk>;
132 clock-names = "apb_pclk";
133 status = "disabled";
134 };
135
136 uart2: uart@b02000 {
137 compatible = "arm,pl011", "arm,primecell";
138 reg = <0xb02000 0x1000>;
139 interrupts = <0 22 4>;
140 clocks = <&pclk>;
141 clock-names = "apb_pclk";
142 status = "disabled";
143 };
144
145 uart3: uart@b03000 {
146 compatible = "arm,pl011", "arm,primecell";
147 reg = <0xb03000 0x1000>;
148 interrupts = <0 23 4>;
149 clocks = <&pclk>;
150 clock-names = "apb_pclk";
151 status = "disabled";
152 };
153
154 uart4: uart@b04000 {
155 compatible = "arm,pl011", "arm,primecell";
156 reg = <0xb04000 0x1000>;
157 interrupts = <0 24 4>;
158 clocks = <&pclk>;
159 clock-names = "apb_pclk";
160 status = "disabled";
161 };
162
163 gpio0: gpio@806000 {
164 compatible = "arm,pl061", "arm,primecell";
165 reg = <0x806000 0x1000>;
166 interrupts = <0 64 0x4>;
167 gpio-controller;
168 #gpio-cells = <2>;
169 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
170 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 clocks = <&pclk>;
174 clock-names = "apb_pclk";
175 };
176
177 gpio1: gpio@807000 {
178 compatible = "arm,pl061", "arm,primecell";
179 reg = <0x807000 0x1000>;
180 interrupts = <0 65 0x4>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
184 &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
185 &pmx0 6 5 1 &pmx0 7 6 1>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 clocks = <&pclk>;
189 clock-names = "apb_pclk";
190 };
191
192 gpio2: gpio@808000 {
193 compatible = "arm,pl061", "arm,primecell";
194 reg = <0x808000 0x1000>;
195 interrupts = <0 66 0x4>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
199 &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
200 &pmx0 6 3 1 &pmx0 7 3 1>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 clocks = <&pclk>;
204 clock-names = "apb_pclk";
205 };
206
207 gpio3: gpio@809000 {
208 compatible = "arm,pl061", "arm,primecell";
209 reg = <0x809000 0x1000>;
210 interrupts = <0 67 0x4>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
214 &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
215 &pmx0 6 11 1 &pmx0 7 11 1>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 clocks = <&pclk>;
219 clock-names = "apb_pclk";
220 };
221
222 gpio4: gpio@80a000 {
223 compatible = "arm,pl061", "arm,primecell";
224 reg = <0x80a000 0x1000>;
225 interrupts = <0 68 0x4>;
226 gpio-controller;
227 #gpio-cells = <2>;
228 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
229 &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
230 &pmx0 6 13 1 &pmx0 7 13 1>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
233 clocks = <&pclk>;
234 clock-names = "apb_pclk";
235 };
236
237 gpio5: gpio@80b000 {
238 compatible = "arm,pl061", "arm,primecell";
239 reg = <0x80b000 0x1000>;
240 interrupts = <0 69 0x4>;
241 gpio-controller;
242 #gpio-cells = <2>;
243 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
244 &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
245 &pmx0 6 16 1 &pmx0 7 16 1>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 clocks = <&pclk>;
249 clock-names = "apb_pclk";
250 };
251
252 gpio6: gpio@80c000 {
253 compatible = "arm,pl061", "arm,primecell";
254 reg = <0x80c000 0x1000>;
255 interrupts = <0 70 0x4>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
259 &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
260 &pmx0 6 18 1 &pmx0 7 19 1>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 clocks = <&pclk>;
264 clock-names = "apb_pclk";
265 };
266
267 gpio7: gpio@80d000 {
268 compatible = "arm,pl061", "arm,primecell";
269 reg = <0x80d000 0x1000>;
270 interrupts = <0 71 0x4>;
271 gpio-controller;
272 #gpio-cells = <2>;
273 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
274 &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
275 &pmx0 6 25 1 &pmx0 7 26 1>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 clocks = <&pclk>;
279 clock-names = "apb_pclk";
280 };
281
282 gpio8: gpio@80e000 {
283 compatible = "arm,pl061", "arm,primecell";
284 reg = <0x80e000 0x1000>;
285 interrupts = <0 72 0x4>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
289 &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
290 &pmx0 6 33 1 &pmx0 7 34 1>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
293 clocks = <&pclk>;
294 clock-names = "apb_pclk";
295 };
296
297 gpio9: gpio@80f000 {
298 compatible = "arm,pl061", "arm,primecell";
299 reg = <0x80f000 0x1000>;
300 interrupts = <0 73 0x4>;
301 gpio-controller;
302 #gpio-cells = <2>;
303 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
304 &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
305 &pmx0 6 41 1>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 clocks = <&pclk>;
309 clock-names = "apb_pclk";
310 };
311
312 gpio10: gpio@810000 {
313 compatible = "arm,pl061", "arm,primecell";
314 reg = <0x810000 0x1000>;
315 interrupts = <0 74 0x4>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
319 &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 clocks = <&pclk>;
323 clock-names = "apb_pclk";
324 };
325
326 gpio11: gpio@811000 {
327 compatible = "arm,pl061", "arm,primecell";
328 reg = <0x811000 0x1000>;
329 interrupts = <0 75 0x4>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
333 &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
334 &pmx0 6 49 1 &pmx0 7 49 1>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 clocks = <&pclk>;
338 clock-names = "apb_pclk";
339 };
340
341 gpio12: gpio@812000 {
342 compatible = "arm,pl061", "arm,primecell";
343 reg = <0x812000 0x1000>;
344 interrupts = <0 76 0x4>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
348 &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
349 &pmx0 6 51 1 &pmx0 7 52 1>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 clocks = <&pclk>;
353 clock-names = "apb_pclk";
354 };
355
356 gpio13: gpio@813000 {
357 compatible = "arm,pl061", "arm,primecell";
358 reg = <0x813000 0x1000>;
359 interrupts = <0 77 0x4>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
363 &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
364 &pmx0 6 55 1 &pmx0 7 56 1>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
367 clocks = <&pclk>;
368 clock-names = "apb_pclk";
369 };
370
371 gpio14: gpio@814000 {
372 compatible = "arm,pl061", "arm,primecell";
373 reg = <0x814000 0x1000>;
374 interrupts = <0 78 0x4>;
375 gpio-controller;
376 #gpio-cells = <2>;
377 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
378 &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
379 &pmx0 6 60 1 &pmx0 7 61 1>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 clocks = <&pclk>;
383 clock-names = "apb_pclk";
384 };
385
386 gpio15: gpio@815000 {
387 compatible = "arm,pl061", "arm,primecell";
388 reg = <0x815000 0x1000>;
389 interrupts = <0 79 0x4>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
393 &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
394 &pmx0 6 64 1 &pmx0 7 65 1>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 clocks = <&pclk>;
398 clock-names = "apb_pclk";
399 };
400
401 gpio16: gpio@816000 {
402 compatible = "arm,pl061", "arm,primecell";
403 reg = <0x816000 0x1000>;
404 interrupts = <0 80 0x4>;
405 gpio-controller;
406 #gpio-cells = <2>;
407 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
408 &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
409 &pmx0 6 72 1 &pmx0 7 73 1>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 clocks = <&pclk>;
413 clock-names = "apb_pclk";
414 };
415
416 gpio17: gpio@817000 {
417 compatible = "arm,pl061", "arm,primecell";
418 reg = <0x817000 0x1000>;
419 interrupts = <0 81 0x4>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
423 &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
424 &pmx0 6 80 1 &pmx0 7 81 1>;
425 interrupt-controller;
426 #interrupt-cells = <2>;
427 clocks = <&pclk>;
428 clock-names = "apb_pclk";
429 };
430
431 gpio18: gpio@818000 {
432 compatible = "arm,pl061", "arm,primecell";
433 reg = <0x818000 0x1000>;
434 interrupts = <0 82 0x4>;
435 gpio-controller;
436 #gpio-cells = <2>;
437 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
438 &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
439 &pmx0 6 86 1 &pmx0 7 87 1>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 clocks = <&pclk>;
443 clock-names = "apb_pclk";
444 };
445
446 gpio19: gpio@819000 {
447 compatible = "arm,pl061", "arm,primecell";
448 reg = <0x819000 0x1000>;
449 interrupts = <0 83 0x4>;
450 gpio-controller;
451 #gpio-cells = <2>;
452 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
453 &pmx0 3 88 1>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 clocks = <&pclk>;
457 clock-names = "apb_pclk";
458 };
459
460 gpio20: gpio@81a000 {
461 compatible = "arm,pl061", "arm,primecell";
462 reg = <0x81a000 0x1000>;
463 interrupts = <0 84 0x4>;
464 gpio-controller;
465 #gpio-cells = <2>;
466 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
467 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 clocks = <&pclk>;
471 clock-names = "apb_pclk";
472 };
473
474 gpio21: gpio@81b000 {
475 compatible = "arm,pl061", "arm,primecell";
476 reg = <0x81b000 0x1000>;
477 interrupts = <0 85 0x4>;
478 gpio-controller;
479 #gpio-cells = <2>;
480 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 clocks = <&pclk>;
484 clock-names = "apb_pclk";
485 };
486
487 pmx0: pinmux@803000 {
488 compatible = "pinctrl-single";
489 reg = <0x803000 0x188>;
490 #address-cells = <1>;
491 #size-cells = <1>;
492 #gpio-range-cells = <3>;
493 ranges;
494
495 pinctrl-single,register-width = <32>;
496 pinctrl-single,function-mask = <7>;
497 /* pin base, nr pins & gpio function */
498 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
499 &range 12 1 0 &range 13 29 1
500 &range 43 1 0 &range 44 49 1
501 &range 94 1 1 &range 96 2 1>;
502
503 range: gpio-range {
504 #pinctrl-single,gpio-range-cells = <3>;
505 };
506 };
507
508 pmx1: pinmux@803800 {
509 compatible = "pinconf-single";
510 reg = <0x803800 0x2dc>;
511 #address-cells = <1>;
512 #size-cells = <1>;
513 ranges;
514
515 pinctrl-single,register-width = <32>;
516 };
517 };
518};
diff --git a/arch/arm/boot/dts/hi4511.dts b/arch/arm/boot/dts/hi4511.dts
new file mode 100644
index 000000000000..96e69abfcdaa
--- /dev/null
+++ b/arch/arm/boot/dts/hi4511.dts
@@ -0,0 +1,648 @@
1/*
2 * Copyright (C) 2012-2013 Linaro Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "hi3620.dtsi"
12
13/ {
14 model = "Hisilicon Hi4511 Development Board";
15 compatible = "hisilicon,hi3620-hi4511";
16
17 chosen {
18 bootargs = "console=ttyAMA0,115200 root=/dev/ram0 earlyprintk";
19 };
20
21 memory {
22 device_type = "memory";
23 reg = <0x40000000 0x20000000>;
24 };
25
26 amba {
27 dual_timer0: dual_timer@800000 {
28 status = "ok";
29 };
30
31 uart0: uart@b00000 { /* console */
32 pinctrl-names = "default", "idle";
33 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
34 pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
35 status = "ok";
36 };
37
38 uart1: uart@b01000 { /* modem */
39 pinctrl-names = "default", "idle";
40 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
41 pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
42 status = "ok";
43 };
44
45 uart2: uart@b02000 { /* audience */
46 pinctrl-names = "default", "idle";
47 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
48 pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
49 status = "ok";
50 };
51
52 uart3: uart@b03000 {
53 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
55 pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
56 status = "ok";
57 };
58
59 uart4: uart@b04000 {
60 pinctrl-names = "default", "idle";
61 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
62 pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
63 status = "ok";
64 };
65
66 pmx0: pinmux@803000 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&board_pmx_pins>;
69
70 board_pmx_pins: board_pmx_pins {
71 pinctrl-single,pins = <
72 0x008 0x0 /* GPIO -- eFUSE_DOUT */
73 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */
74 >;
75 };
76 uart0_pmx_func: uart0_pmx_func {
77 pinctrl-single,pins = <
78 0x0f0 0x0
79 0x0f4 0x0 /* UART0_RX & UART0_TX */
80 >;
81 };
82 uart0_pmx_idle: uart0_pmx_idle {
83 pinctrl-single,pins = <
84 /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */
85 0x0f4 0x1 /* UART0_RX & UART0_TX */
86 >;
87 };
88 uart1_pmx_func: uart1_pmx_func {
89 pinctrl-single,pins = <
90 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */
91 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */
92 >;
93 };
94 uart1_pmx_idle: uart1_pmx_idle {
95 pinctrl-single,pins = <
96 0x0f8 0x1 /* GPIO (IOMG61) */
97 0x0fc 0x1 /* GPIO (IOMG62) */
98 >;
99 };
100 uart2_pmx_func: uart2_pmx_func {
101 pinctrl-single,pins = <
102 0x104 0x2 /* UART2_RXD (IOMG96) */
103 0x108 0x2 /* UART2_TXD (IOMG64) */
104 >;
105 };
106 uart2_pmx_idle: uart2_pmx_idle {
107 pinctrl-single,pins = <
108 0x104 0x1 /* GPIO (IOMG96) */
109 0x108 0x1 /* GPIO (IOMG64) */
110 >;
111 };
112 uart3_pmx_func: uart3_pmx_func {
113 pinctrl-single,pins = <
114 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */
115 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */
116 >;
117 };
118 uart3_pmx_idle: uart3_pmx_idle {
119 pinctrl-single,pins = <
120 0x160 0x1 /* GPIO (IOMG85) */
121 0x164 0x1 /* GPIO (IOMG86) */
122 >;
123 };
124 uart4_pmx_func: uart4_pmx_func {
125 pinctrl-single,pins = <
126 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */
127 0x16c 0x0 /* UART4_RXD (IOMG88) */
128 0x170 0x0 /* UART4_TXD (IOMG93) */
129 >;
130 };
131 uart4_pmx_idle: uart4_pmx_idle {
132 pinctrl-single,pins = <
133 0x168 0x1 /* GPIO (IOMG87) */
134 0x16c 0x1 /* GPIO (IOMG88) */
135 0x170 0x1 /* GPIO (IOMG93) */
136 >;
137 };
138 i2c0_pmx_func: i2c0_pmx_func {
139 pinctrl-single,pins = <
140 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */
141 >;
142 };
143 i2c0_pmx_idle: i2c0_pmx_idle {
144 pinctrl-single,pins = <
145 0x0b4 0x1 /* GPIO (IOMG45) */
146 >;
147 };
148 i2c1_pmx_func: i2c1_pmx_func {
149 pinctrl-single,pins = <
150 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */
151 >;
152 };
153 i2c1_pmx_idle: i2c1_pmx_idle {
154 pinctrl-single,pins = <
155 0x0b8 0x1 /* GPIO (IOMG46) */
156 >;
157 };
158 i2c2_pmx_func: i2c2_pmx_func {
159 pinctrl-single,pins = <
160 0x068 0x0 /* I2C2_SCL (IOMG26) */
161 0x06c 0x0 /* I2C2_SDA (IOMG27) */
162 >;
163 };
164 i2c2_pmx_idle: i2c2_pmx_idle {
165 pinctrl-single,pins = <
166 0x068 0x1 /* GPIO (IOMG26) */
167 0x06c 0x1 /* GPIO (IOMG27) */
168 >;
169 };
170 i2c3_pmx_func: i2c3_pmx_func {
171 pinctrl-single,pins = <
172 0x050 0x2 /* I2C3_SCL (IOMG20) */
173 0x054 0x2 /* I2C3_SDA (IOMG21) */
174 >;
175 };
176 i2c3_pmx_idle: i2c3_pmx_idle {
177 pinctrl-single,pins = <
178 0x050 0x1 /* GPIO (IOMG20) */
179 0x054 0x1 /* GPIO (IOMG21) */
180 >;
181 };
182 spi0_pmx_func: spi0_pmx_func {
183 pinctrl-single,pins = <
184 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */
185 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */
186 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */
187 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */
188 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */
189 >;
190 };
191 spi0_pmx_idle: spi0_pmx_idle {
192 pinctrl-single,pins = <
193 0x0d4 0x1 /* GPIO (IOMG53) */
194 0x0d8 0x1 /* GPIO (IOMG54) */
195 0x0dc 0x1 /* GPIO (IOMG55) */
196 0x0e0 0x1 /* GPIO (IOMG56) */
197 0x0e4 0x1 /* GPIO (IOMG57) */
198 >;
199 };
200 spi1_pmx_func: spi1_pmx_func {
201 pinctrl-single,pins = <
202 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */
203 0x0e8 0x0 /* SPI1_DO (IOMG58) */
204 0x0ec 0x0 /* SPI1_CS (IOMG95) */
205 >;
206 };
207 spi1_pmx_idle: spi1_pmx_idle {
208 pinctrl-single,pins = <
209 0x184 0x1 /* GPIO (IOMG98) */
210 0x0e8 0x1 /* GPIO (IOMG58) */
211 0x0ec 0x1 /* GPIO (IOMG95) */
212 >;
213 };
214 kpc_pmx_func: kpc_pmx_func {
215 pinctrl-single,pins = <
216 0x12c 0x0 /* KEY_IN0 (IOMG73) */
217 0x130 0x0 /* KEY_IN1 (IOMG74) */
218 0x134 0x0 /* KEY_IN2 (IOMG75) */
219 0x10c 0x0 /* KEY_OUT0 (IOMG65) */
220 0x110 0x0 /* KEY_OUT1 (IOMG66) */
221 0x114 0x0 /* KEY_OUT2 (IOMG67) */
222 >;
223 };
224 kpc_pmx_idle: kpc_pmx_idle {
225 pinctrl-single,pins = <
226 0x12c 0x1 /* GPIO (IOMG73) */
227 0x130 0x1 /* GPIO (IOMG74) */
228 0x134 0x1 /* GPIO (IOMG75) */
229 0x10c 0x1 /* GPIO (IOMG65) */
230 0x110 0x1 /* GPIO (IOMG66) */
231 0x114 0x1 /* GPIO (IOMG67) */
232 >;
233 };
234 gpio_key_func: gpio_key_func {
235 pinctrl-single,pins = <
236 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */
237 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */
238 >;
239 };
240 emmc_pmx_func: emmc_pmx_func {
241 pinctrl-single,pins = <
242 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */
243 0x018 0x0 /* NAND_CS3_N (IOMG6) */
244 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
245 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
246 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */
247 >;
248 };
249 emmc_pmx_idle: emmc_pmx_idle {
250 pinctrl-single,pins = <
251 0x030 0x0 /* GPIO (IOMG12) */
252 0x018 0x1 /* GPIO (IOMG6) */
253 0x024 0x1 /* GPIO (IOMG8) */
254 0x028 0x1 /* GPIO (IOMG9) */
255 0x02c 0x1 /* GPIO (IOMG10) */
256 >;
257 };
258 sd_pmx_func: sd_pmx_func {
259 pinctrl-single,pins = <
260 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */
261 0x0c0 0x0 /* SD_DATA3 (IOMG48) */
262 >;
263 };
264 sd_pmx_idle: sd_pmx_idle {
265 pinctrl-single,pins = <
266 0x0bc 0x1 /* GPIO (IOMG47) */
267 0x0c0 0x1 /* GPIO (IOMG48) */
268 >;
269 };
270 nand_pmx_func: nand_pmx_func {
271 pinctrl-single,pins = <
272 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */
273 0x010 0x0 /* NAND_CS1_N (IOMG4) */
274 0x014 0x0 /* NAND_CS2_N (IOMG5) */
275 0x018 0x0 /* NAND_CS3_N (IOMG6) */
276 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */
277 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */
278 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
279 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
280 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */
281 >;
282 };
283 nand_pmx_idle: nand_pmx_idle {
284 pinctrl-single,pins = <
285 0x00c 0x1 /* GPIO (IOMG3) */
286 0x010 0x1 /* GPIO (IOMG4) */
287 0x014 0x1 /* GPIO (IOMG5) */
288 0x018 0x1 /* GPIO (IOMG6) */
289 0x01c 0x1 /* GPIO (IOMG94) */
290 0x020 0x1 /* GPIO (IOMG7) */
291 0x024 0x1 /* GPIO (IOMG8) */
292 0x028 0x1 /* GPIO (IOMG9) */
293 0x02c 0x1 /* GPIO (IOMG10) */
294 >;
295 };
296 sdio_pmx_func: sdio_pmx_func {
297 pinctrl-single,pins = <
298 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */
299 >;
300 };
301 sdio_pmx_idle: sdio_pmx_idle {
302 pinctrl-single,pins = <
303 0x0c4 0x1 /* GPIO (IOMG49) */
304 >;
305 };
306 audio_out_pmx_func: audio_out_pmx_func {
307 pinctrl-single,pins = <
308 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */
309 >;
310 };
311 };
312
313 pmx1: pinmux@803800 {
314 pinctrl-names = "default";
315 pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins
316 &board_np_pins &board_ps_pins &kpc_cfg_func
317 &audio_out_cfg_func>;
318 board_pu_pins: board_pu_pins {
319 pinctrl-single,pins = <
320 0x014 0 /* GPIO_158 (IOCFG2) */
321 0x018 0 /* GPIO_159 (IOCFG3) */
322 0x01c 0 /* BOOT_MODE0 (IOCFG4) */
323 0x020 0 /* BOOT_MODE1 (IOCFG5) */
324 >;
325 pinctrl-single,bias-pulldown = <0 2 0 2>;
326 pinctrl-single,bias-pullup = <1 1 0 1>;
327 };
328 board_pd_pins: board_pd_pins {
329 pinctrl-single,pins = <
330 0x038 0 /* eFUSE_DOUT (IOCFG11) */
331 0x150 0 /* ISP_GPIO8 (IOCFG93) */
332 0x154 0 /* ISP_GPIO9 (IOCFG94) */
333 >;
334 pinctrl-single,bias-pulldown = <2 2 0 2>;
335 pinctrl-single,bias-pullup = <0 1 0 1>;
336 };
337 board_pd_ps_pins: board_pd_ps_pins {
338 pinctrl-single,pins = <
339 0x2d8 0 /* CLK_OUT0 (IOCFG190) */
340 0x004 0 /* PMU_SPI_DATA (IOCFG192) */
341 >;
342 pinctrl-single,bias-pulldown = <2 2 0 2>;
343 pinctrl-single,bias-pullup = <0 1 0 1>;
344 pinctrl-single,drive-strength = <0x30 0xf0>;
345 };
346 board_np_pins: board_np_pins {
347 pinctrl-single,pins = <
348 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */
349 >;
350 pinctrl-single,bias-pulldown = <0 2 0 2>;
351 pinctrl-single,bias-pullup = <0 1 0 1>;
352 };
353 board_ps_pins: board_ps_pins {
354 pinctrl-single,pins = <
355 0x000 0 /* PMU_SPI_CLK (IOCFG191) */
356 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */
357 >;
358 pinctrl-single,drive-strength = <0x30 0xf0>;
359 };
360 uart0_cfg_func: uart0_cfg_func {
361 pinctrl-single,pins = <
362 0x208 0 /* UART0_RXD (IOCFG138) */
363 0x20c 0 /* UART0_TXD (IOCFG139) */
364 >;
365 pinctrl-single,bias-pulldown = <0 2 0 2>;
366 pinctrl-single,bias-pullup = <0 1 0 1>;
367 };
368 uart0_cfg_idle: uart0_cfg_idle {
369 pinctrl-single,pins = <
370 0x208 0 /* UART0_RXD (IOCFG138) */
371 0x20c 0 /* UART0_TXD (IOCFG139) */
372 >;
373 pinctrl-single,bias-pulldown = <2 2 0 2>;
374 pinctrl-single,bias-pullup = <0 1 0 1>;
375 };
376 uart1_cfg_func: uart1_cfg_func {
377 pinctrl-single,pins = <
378 0x210 0 /* UART1_CTS (IOCFG140) */
379 0x214 0 /* UART1_RTS (IOCFG141) */
380 0x218 0 /* UART1_RXD (IOCFG142) */
381 0x21c 0 /* UART1_TXD (IOCFG143) */
382 >;
383 pinctrl-single,bias-pulldown = <0 2 0 2>;
384 pinctrl-single,bias-pullup = <0 1 0 1>;
385 };
386 uart1_cfg_idle: uart1_cfg_idle {
387 pinctrl-single,pins = <
388 0x210 0 /* UART1_CTS (IOCFG140) */
389 0x214 0 /* UART1_RTS (IOCFG141) */
390 0x218 0 /* UART1_RXD (IOCFG142) */
391 0x21c 0 /* UART1_TXD (IOCFG143) */
392 >;
393 pinctrl-single,bias-pulldown = <2 2 0 2>;
394 pinctrl-single,bias-pullup = <0 1 0 1>;
395 };
396 uart2_cfg_func: uart2_cfg_func {
397 pinctrl-single,pins = <
398 0x220 0 /* UART2_CTS (IOCFG144) */
399 0x224 0 /* UART2_RTS (IOCFG145) */
400 0x228 0 /* UART2_RXD (IOCFG146) */
401 0x22c 0 /* UART2_TXD (IOCFG147) */
402 >;
403 pinctrl-single,bias-pulldown = <0 2 0 2>;
404 pinctrl-single,bias-pullup = <0 1 0 1>;
405 };
406 uart2_cfg_idle: uart2_cfg_idle {
407 pinctrl-single,pins = <
408 0x220 0 /* GPIO (IOCFG144) */
409 0x224 0 /* GPIO (IOCFG145) */
410 0x228 0 /* GPIO (IOCFG146) */
411 0x22c 0 /* GPIO (IOCFG147) */
412 >;
413 pinctrl-single,bias-pulldown = <2 2 0 2>;
414 pinctrl-single,bias-pullup = <0 1 0 1>;
415 };
416 uart3_cfg_func: uart3_cfg_func {
417 pinctrl-single,pins = <
418 0x294 0 /* UART3_CTS (IOCFG173) */
419 0x298 0 /* UART3_RTS (IOCFG174) */
420 0x29c 0 /* UART3_RXD (IOCFG175) */
421 0x2a0 0 /* UART3_TXD (IOCFG176) */
422 >;
423 pinctrl-single,bias-pulldown = <0 2 0 2>;
424 pinctrl-single,bias-pullup = <0 1 0 1>;
425 };
426 uart3_cfg_idle: uart3_cfg_idle {
427 pinctrl-single,pins = <
428 0x294 0 /* UART3_CTS (IOCFG173) */
429 0x298 0 /* UART3_RTS (IOCFG174) */
430 0x29c 0 /* UART3_RXD (IOCFG175) */
431 0x2a0 0 /* UART3_TXD (IOCFG176) */
432 >;
433 pinctrl-single,bias-pulldown = <2 2 0 2>;
434 pinctrl-single,bias-pullup = <0 1 0 1>;
435 };
436 uart4_cfg_func: uart4_cfg_func {
437 pinctrl-single,pins = <
438 0x2a4 0 /* UART4_CTS (IOCFG177) */
439 0x2a8 0 /* UART4_RTS (IOCFG178) */
440 0x2ac 0 /* UART4_RXD (IOCFG179) */
441 0x2b0 0 /* UART4_TXD (IOCFG180) */
442 >;
443 pinctrl-single,bias-pulldown = <0 2 0 2>;
444 pinctrl-single,bias-pullup = <0 1 0 1>;
445 };
446 i2c0_cfg_func: i2c0_cfg_func {
447 pinctrl-single,pins = <
448 0x17c 0 /* I2C0_SCL (IOCFG103) */
449 0x180 0 /* I2C0_SDA (IOCFG104) */
450 >;
451 pinctrl-single,bias-pulldown = <0 2 0 2>;
452 pinctrl-single,bias-pullup = <0 1 0 1>;
453 pinctrl-single,drive-strength = <0x30 0xf0>;
454 };
455 i2c1_cfg_func: i2c1_cfg_func {
456 pinctrl-single,pins = <
457 0x184 0 /* I2C1_SCL (IOCFG105) */
458 0x188 0 /* I2C1_SDA (IOCFG106) */
459 >;
460 pinctrl-single,bias-pulldown = <0 2 0 2>;
461 pinctrl-single,bias-pullup = <0 1 0 1>;
462 pinctrl-single,drive-strength = <0x30 0xf0>;
463 };
464 i2c2_cfg_func: i2c2_cfg_func {
465 pinctrl-single,pins = <
466 0x118 0 /* I2C2_SCL (IOCFG79) */
467 0x11c 0 /* I2C2_SDA (IOCFG80) */
468 >;
469 pinctrl-single,bias-pulldown = <0 2 0 2>;
470 pinctrl-single,bias-pullup = <0 1 0 1>;
471 pinctrl-single,drive-strength = <0x30 0xf0>;
472 };
473 i2c3_cfg_func: i2c3_cfg_func {
474 pinctrl-single,pins = <
475 0x100 0 /* I2C3_SCL (IOCFG73) */
476 0x104 0 /* I2C3_SDA (IOCFG74) */
477 >;
478 pinctrl-single,bias-pulldown = <0 2 0 2>;
479 pinctrl-single,bias-pullup = <0 1 0 1>;
480 pinctrl-single,drive-strength = <0x30 0xf0>;
481 };
482 spi0_cfg_func1: spi0_cfg_func1 {
483 pinctrl-single,pins = <
484 0x1d4 0 /* SPI0_CLK (IOCFG125) */
485 0x1d8 0 /* SPI0_DI (IOCFG126) */
486 0x1dc 0 /* SPI0_DO (IOCFG127) */
487 >;
488 pinctrl-single,bias-pulldown = <2 2 0 2>;
489 pinctrl-single,bias-pullup = <0 1 0 1>;
490 pinctrl-single,drive-strength = <0x30 0xf0>;
491 };
492 spi0_cfg_func2: spi0_cfg_func2 {
493 pinctrl-single,pins = <
494 0x1e0 0 /* SPI0_CS0 (IOCFG128) */
495 0x1e4 0 /* SPI0_CS1 (IOCFG129) */
496 0x1e8 0 /* SPI0_CS2 (IOCFG130 */
497 0x1ec 0 /* SPI0_CS3 (IOCFG131) */
498 >;
499 pinctrl-single,bias-pulldown = <0 2 0 2>;
500 pinctrl-single,bias-pullup = <1 1 0 1>;
501 pinctrl-single,drive-strength = <0x30 0xf0>;
502 };
503 spi1_cfg_func1: spi1_cfg_func1 {
504 pinctrl-single,pins = <
505 0x1f0 0 /* SPI1_CLK (IOCFG132) */
506 0x1f4 0 /* SPI1_DI (IOCFG133) */
507 0x1f8 0 /* SPI1_DO (IOCFG134) */
508 >;
509 pinctrl-single,bias-pulldown = <2 2 0 2>;
510 pinctrl-single,bias-pullup = <0 1 0 1>;
511 pinctrl-single,drive-strength = <0x30 0xf0>;
512 };
513 spi1_cfg_func2: spi1_cfg_func2 {
514 pinctrl-single,pins = <
515 0x1fc 0 /* SPI1_CS (IOCFG135) */
516 >;
517 pinctrl-single,bias-pulldown = <0 2 0 2>;
518 pinctrl-single,bias-pullup = <1 1 0 1>;
519 pinctrl-single,drive-strength = <0x30 0xf0>;
520 };
521 kpc_cfg_func: kpc_cfg_func {
522 pinctrl-single,pins = <
523 0x250 0 /* KEY_IN0 (IOCFG156) */
524 0x254 0 /* KEY_IN1 (IOCFG157) */
525 0x258 0 /* KEY_IN2 (IOCFG158) */
526 0x230 0 /* KEY_OUT0 (IOCFG148) */
527 0x234 0 /* KEY_OUT1 (IOCFG149) */
528 0x238 0 /* KEY_OUT2 (IOCFG150) */
529 >;
530 pinctrl-single,bias-pulldown = <2 2 0 2>;
531 pinctrl-single,bias-pullup = <0 1 0 1>;
532 };
533 emmc_cfg_func: emmc_cfg_func {
534 pinctrl-single,pins = <
535 0x0ac 0 /* eMMC_CMD (IOCFG40) */
536 0x0b0 0 /* eMMC_CLK (IOCFG41) */
537 0x058 0 /* NAND_CS3_N (IOCFG19) */
538 0x064 0 /* NAND_BUSY2_N (IOCFG22) */
539 0x068 0 /* NAND_BUSY3_N (IOCFG23) */
540 0x08c 0 /* NAND_DATA8 (IOCFG32) */
541 0x090 0 /* NAND_DATA9 (IOCFG33) */
542 0x094 0 /* NAND_DATA10 (IOCFG34) */
543 0x098 0 /* NAND_DATA11 (IOCFG35) */
544 0x09c 0 /* NAND_DATA12 (IOCFG36) */
545 0x0a0 0 /* NAND_DATA13 (IOCFG37) */
546 0x0a4 0 /* NAND_DATA14 (IOCFG38) */
547 0x0a8 0 /* NAND_DATA15 (IOCFG39) */
548 >;
549 pinctrl-single,bias-pulldown = <0 2 0 2>;
550 pinctrl-single,bias-pullup = <1 1 0 1>;
551 pinctrl-single,drive-strength = <0x30 0xf0>;
552 };
553 sd_cfg_func1: sd_cfg_func1 {
554 pinctrl-single,pins = <
555 0x18c 0 /* SD_CLK (IOCFG107) */
556 0x190 0 /* SD_CMD (IOCFG108) */
557 >;
558 pinctrl-single,bias-pulldown = <2 2 0 2>;
559 pinctrl-single,bias-pullup = <0 1 0 1>;
560 pinctrl-single,drive-strength = <0x30 0xf0>;
561 };
562 sd_cfg_func2: sd_cfg_func2 {
563 pinctrl-single,pins = <
564 0x194 0 /* SD_DATA0 (IOCFG109) */
565 0x198 0 /* SD_DATA1 (IOCFG110) */
566 0x19c 0 /* SD_DATA2 (IOCFG111) */
567 0x1a0 0 /* SD_DATA3 (IOCFG112) */
568 >;
569 pinctrl-single,bias-pulldown = <2 2 0 2>;
570 pinctrl-single,bias-pullup = <0 1 0 1>;
571 pinctrl-single,drive-strength = <0x70 0xf0>;
572 };
573 nand_cfg_func1: nand_cfg_func1 {
574 pinctrl-single,pins = <
575 0x03c 0 /* NAND_ALE (IOCFG12) */
576 0x040 0 /* NAND_CLE (IOCFG13) */
577 0x06c 0 /* NAND_DATA0 (IOCFG24) */
578 0x070 0 /* NAND_DATA1 (IOCFG25) */
579 0x074 0 /* NAND_DATA2 (IOCFG26) */
580 0x078 0 /* NAND_DATA3 (IOCFG27) */
581 0x07c 0 /* NAND_DATA4 (IOCFG28) */
582 0x080 0 /* NAND_DATA5 (IOCFG29) */
583 0x084 0 /* NAND_DATA6 (IOCFG30) */
584 0x088 0 /* NAND_DATA7 (IOCFG31) */
585 0x08c 0 /* NAND_DATA8 (IOCFG32) */
586 0x090 0 /* NAND_DATA9 (IOCFG33) */
587 0x094 0 /* NAND_DATA10 (IOCFG34) */
588 0x098 0 /* NAND_DATA11 (IOCFG35) */
589 0x09c 0 /* NAND_DATA12 (IOCFG36) */
590 0x0a0 0 /* NAND_DATA13 (IOCFG37) */
591 0x0a4 0 /* NAND_DATA14 (IOCFG38) */
592 0x0a8 0 /* NAND_DATA15 (IOCFG39) */
593 >;
594 pinctrl-single,bias-pulldown = <2 2 0 2>;
595 pinctrl-single,bias-pullup = <0 1 0 1>;
596 pinctrl-single,drive-strength = <0x30 0xf0>;
597 };
598 nand_cfg_func2: nand_cfg_func2 {
599 pinctrl-single,pins = <
600 0x044 0 /* NAND_RE_N (IOCFG14) */
601 0x048 0 /* NAND_WE_N (IOCFG15) */
602 0x04c 0 /* NAND_CS0_N (IOCFG16) */
603 0x050 0 /* NAND_CS1_N (IOCFG17) */
604 0x054 0 /* NAND_CS2_N (IOCFG18) */
605 0x058 0 /* NAND_CS3_N (IOCFG19) */
606 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */
607 0x060 0 /* NAND_BUSY1_N (IOCFG21) */
608 0x064 0 /* NAND_BUSY2_N (IOCFG22) */
609 0x068 0 /* NAND_BUSY3_N (IOCFG23) */
610 >;
611 pinctrl-single,bias-pulldown = <0 2 0 2>;
612 pinctrl-single,bias-pullup = <1 1 0 1>;
613 pinctrl-single,drive-strength = <0x30 0xf0>;
614 };
615 sdio_cfg_func: sdio_cfg_func {
616 pinctrl-single,pins = <
617 0x1a4 0 /* SDIO0_CLK (IOCG113) */
618 0x1a8 0 /* SDIO0_CMD (IOCG114) */
619 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */
620 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */
621 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */
622 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */
623 >;
624 pinctrl-single,bias-pulldown = <2 2 0 2>;
625 pinctrl-single,bias-pullup = <0 1 0 1>;
626 pinctrl-single,drive-strength = <0x30 0xf0>;
627 };
628 audio_out_cfg_func: audio_out_cfg_func {
629 pinctrl-single,pins = <
630 0x200 0 /* GPIO (IOCFG136) */
631 0x204 0 /* GPIO (IOCFG137) */
632 >;
633 pinctrl-single,bias-pulldown = <2 2 0 2>;
634 pinctrl-single,bias-pullup = <0 1 0 1>;
635 };
636 };
637 };
638
639 gpio-keys {
640 compatible = "gpio-keys";
641
642 call {
643 label = "call";
644 gpios = <&gpio17 2 0>;
645 linux,code = <169>; /* KEY_PHONE */
646 };
647 };
648};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 20:53:56 -0500