diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-11-21 05:36:03 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-16 05:01:23 -0500 |
commit | b09bcdd4c2f52b54115895c4d62ad82918f71431 (patch) | |
tree | d6e7e39a0f31c98403af4362fb97bfa9345883dc /arch | |
parent | 44539a711217898358ae456fc0f81f5f4652abd5 (diff) |
[ARM] S3C64XX: Update TCFG for new timer divider settings.
The S3C64XX series has a new TCFG divider setting to allow the clock
directly through, which means that we need to update the pwm-clock
code to cope with this.
Add <mach/pwm-clock.h> containing the specific code to deal with the
TCFG divider settings and provide any other per-arch data that the
pwm-clock driver needs to function.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-s3c6400/include/mach/pwm-clock.h | 56 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/regs-timer.h | 8 | ||||
-rw-r--r-- | arch/arm/plat-s3c/pwm-clock.c | 39 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | 55 |
4 files changed, 129 insertions, 29 deletions
diff --git a/arch/arm/mach-s3c6400/include/mach/pwm-clock.h b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h new file mode 100644 index 000000000000..b25bedee0d52 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64xx - pwm clock and timer support | ||
9 | */ | ||
10 | |||
11 | /** | ||
12 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
13 | * @tcfg: The timer TCFG1 register bits shifted down to 0. | ||
14 | * | ||
15 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
16 | * any of the TDIV clocks. | ||
17 | */ | ||
18 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
19 | { | ||
20 | return tcfg >= S3C64XX_TCFG1_MUX_TCLK; | ||
21 | } | ||
22 | |||
23 | /** | ||
24 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
25 | * @tcfg1: The tcfg1 setting, shifted down. | ||
26 | * | ||
27 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
28 | * caller has already checked to see if this is not a TCLK source. | ||
29 | */ | ||
30 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
31 | { | ||
32 | return 1 << tcfg1; | ||
33 | } | ||
34 | |||
35 | /** | ||
36 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
37 | * | ||
38 | * Return true if we have a /1 in the tdiv setting. | ||
39 | */ | ||
40 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
41 | { | ||
42 | return 1; | ||
43 | } | ||
44 | |||
45 | /** | ||
46 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
47 | * @div: The divisor to calculate the bit information for. | ||
48 | * | ||
49 | * Turn a divisor into the necessary bit field for TCFG1. | ||
50 | */ | ||
51 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
52 | { | ||
53 | return ilog2(div); | ||
54 | } | ||
55 | |||
56 | #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK | ||
diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h index 086ce2685836..d097d92f8cc7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ b/arch/arm/plat-s3c/include/plat/regs-timer.h | |||
@@ -73,6 +73,14 @@ | |||
73 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) | 73 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) |
74 | #define S3C2410_TCFG1_MUX_MASK (15<<0) | 74 | #define S3C2410_TCFG1_MUX_MASK (15<<0) |
75 | 75 | ||
76 | #define S3C64XX_TCFG1_MUX_DIV1 (0<<0) | ||
77 | #define S3C64XX_TCFG1_MUX_DIV2 (1<<0) | ||
78 | #define S3C64XX_TCFG1_MUX_DIV4 (2<<0) | ||
79 | #define S3C64XX_TCFG1_MUX_DIV8 (3<<0) | ||
80 | #define S3C64XX_TCFG1_MUX_DIV16 (4<<0) | ||
81 | #define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ | ||
82 | #define S3C64XX_TCFG1_MUX_MASK (15<<0) | ||
83 | |||
76 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) | 84 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) |
77 | 85 | ||
78 | /* for each timer, we have an count buffer, an compare buffer and | 86 | /* for each timer, we have an count buffer, an compare buffer and |
diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c index 5242fb0afcca..988c0cd7ade2 100644 --- a/arch/arm/plat-s3c/pwm-clock.c +++ b/arch/arm/plat-s3c/pwm-clock.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
15 | #include <linux/list.h> | 15 | #include <linux/list.h> |
16 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
17 | #include <linux/log2.h> | ||
17 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
18 | #include <linux/err.h> | 19 | #include <linux/err.h> |
19 | #include <linux/io.h> | 20 | #include <linux/io.h> |
@@ -26,6 +27,7 @@ | |||
26 | #include <plat/cpu.h> | 27 | #include <plat/cpu.h> |
27 | 28 | ||
28 | #include <plat/regs-timer.h> | 29 | #include <plat/regs-timer.h> |
30 | #include <mach/pwm-clock.h> | ||
29 | 31 | ||
30 | /* Each of the timers 0 through 5 go through the following | 32 | /* Each of the timers 0 through 5 go through the following |
31 | * clock tree, with the inputs depending on the timers. | 33 | * clock tree, with the inputs depending on the timers. |
@@ -166,11 +168,6 @@ static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk) | |||
166 | return container_of(clk, struct pwm_tdiv_clk, clk); | 168 | return container_of(clk, struct pwm_tdiv_clk, clk); |
167 | } | 169 | } |
168 | 170 | ||
169 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
170 | { | ||
171 | return 1 << (1 + tcfg1); | ||
172 | } | ||
173 | |||
174 | static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) | 171 | static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) |
175 | { | 172 | { |
176 | unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); | 173 | unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); |
@@ -179,7 +176,7 @@ static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) | |||
179 | tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); | 176 | tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); |
180 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; | 177 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; |
181 | 178 | ||
182 | if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) | 179 | if (pwm_cfg_src_is_tclk(tcfg1)) |
183 | divisor = to_tdiv(clk)->divisor; | 180 | divisor = to_tdiv(clk)->divisor; |
184 | else | 181 | else |
185 | divisor = tcfg_to_divisor(tcfg1); | 182 | divisor = tcfg_to_divisor(tcfg1); |
@@ -196,7 +193,9 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, | |||
196 | parent_rate = clk_get_rate(clk->parent); | 193 | parent_rate = clk_get_rate(clk->parent); |
197 | divisor = parent_rate / rate; | 194 | divisor = parent_rate / rate; |
198 | 195 | ||
199 | if (divisor <= 2) | 196 | if (divisor <= 1 && pwm_tdiv_has_div1()) |
197 | divisor = 1; | ||
198 | else if (divisor <= 2) | ||
200 | divisor = 2; | 199 | divisor = 2; |
201 | else if (divisor <= 4) | 200 | else if (divisor <= 4) |
202 | divisor = 4; | 201 | divisor = 4; |
@@ -210,25 +209,7 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, | |||
210 | 209 | ||
211 | static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) | 210 | static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) |
212 | { | 211 | { |
213 | unsigned long bits; | 212 | return pwm_tdiv_div_bits(divclk->divisor); |
214 | |||
215 | switch (divclk->divisor) { | ||
216 | case 2: | ||
217 | bits = S3C2410_TCFG1_MUX_DIV2; | ||
218 | break; | ||
219 | case 4: | ||
220 | bits = S3C2410_TCFG1_MUX_DIV4; | ||
221 | break; | ||
222 | case 8: | ||
223 | bits = S3C2410_TCFG1_MUX_DIV8; | ||
224 | break; | ||
225 | case 16: | ||
226 | default: | ||
227 | bits = S3C2410_TCFG1_MUX_DIV16; | ||
228 | break; | ||
229 | } | ||
230 | |||
231 | return bits; | ||
232 | } | 213 | } |
233 | 214 | ||
234 | static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) | 215 | static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) |
@@ -269,7 +250,7 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) | |||
269 | /* Update the current MUX settings if we are currently | 250 | /* Update the current MUX settings if we are currently |
270 | * selected as the clock source for this clock. */ | 251 | * selected as the clock source for this clock. */ |
271 | 252 | ||
272 | if (tcfg1 != S3C2410_TCFG1_MUX_TCLK) | 253 | if (!pwm_cfg_src_is_tclk(tcfg1)) |
273 | clk_pwm_tdiv_update(divclk); | 254 | clk_pwm_tdiv_update(divclk); |
274 | 255 | ||
275 | return 0; | 256 | return 0; |
@@ -356,7 +337,7 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) | |||
356 | unsigned long shift = S3C2410_TCFG1_SHIFT(id); | 337 | unsigned long shift = S3C2410_TCFG1_SHIFT(id); |
357 | 338 | ||
358 | if (parent == s3c24xx_pwmclk_tclk(id)) | 339 | if (parent == s3c24xx_pwmclk_tclk(id)) |
359 | bits = S3C2410_TCFG1_MUX_TCLK << shift; | 340 | bits = S3C_TCFG1_MUX_TCLK << shift; |
360 | else if (parent == s3c24xx_pwmclk_tdiv(id)) | 341 | else if (parent == s3c24xx_pwmclk_tdiv(id)) |
361 | bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; | 342 | bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; |
362 | else | 343 | else |
@@ -418,7 +399,7 @@ static __init int clk_pwm_tin_register(struct clk *pwm) | |||
418 | tcfg1 >>= S3C2410_TCFG1_SHIFT(id); | 399 | tcfg1 >>= S3C2410_TCFG1_SHIFT(id); |
419 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; | 400 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; |
420 | 401 | ||
421 | if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) | 402 | if (pwm_cfg_src_is_tclk(tcfg1)) |
422 | parent = s3c24xx_pwmclk_tclk(id); | 403 | parent = s3c24xx_pwmclk_tclk(id); |
423 | else | 404 | else |
424 | parent = s3c24xx_pwmclk_tdiv(id); | 405 | parent = s3c24xx_pwmclk_tdiv(id); |
diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h new file mode 100644 index 000000000000..a087de21bc20 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | |||
@@ -0,0 +1,55 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C24xx - pwm clock and timer support | ||
8 | */ | ||
9 | |||
10 | /** | ||
11 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
12 | * @cfg: The timer TCFG1 register bits shifted down to 0. | ||
13 | * | ||
14 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
15 | * any of the TDIV clocks. | ||
16 | */ | ||
17 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
18 | { | ||
19 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | ||
20 | } | ||
21 | |||
22 | /** | ||
23 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
24 | * @tcfg1: The tcfg1 setting, shifted down. | ||
25 | * | ||
26 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
27 | * caller has already checked to see if this is not a TCLK source. | ||
28 | */ | ||
29 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
30 | { | ||
31 | return 1 << (1 + tcfg1); | ||
32 | } | ||
33 | |||
34 | /** | ||
35 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
36 | * | ||
37 | * Return true if we have a /1 in the tdiv setting. | ||
38 | */ | ||
39 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
40 | { | ||
41 | return 0; | ||
42 | } | ||
43 | |||
44 | /** | ||
45 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
46 | * @div: The divisor to calculate the bit information for. | ||
47 | * | ||
48 | * Turn a divisor into the necessary bit field for TCFG1. | ||
49 | */ | ||
50 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
51 | { | ||
52 | return ilog2(div) - 1; | ||
53 | } | ||
54 | |||
55 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | ||