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authorLinus Torvalds <torvalds@linux-foundation.org>2013-06-11 14:16:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-06-11 14:16:43 -0400
commitaf180b81a3f4ea925fae88878f367e676e99bf73 (patch)
tree4082893c231312169d9e0e984dc72e036c0d728e /arch
parent34376a50fb1fa095b9d0636fa41ed2e73125f214 (diff)
parent7c11c0ccc7ba186433b2102cf3775ce6b2445453 (diff)
Merge branch 'fixes' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm bugfixes from Gleb Natapov: "There is one more fix for MIPS KVM ABI here, MIPS and PPC build breakage fixes and a couple of PPC bug fixes" * 'fixes' of git://git.kernel.org/pub/scm/virt/kvm/kvm: kvm/ppc/booke64: Fix lazy ee handling in kvmppc_handle_exit() kvm/ppc/booke: Hold srcu lock when calling gfn functions kvm/ppc/booke64: Disable e6500 support kvm/ppc/booke64: Fix AltiVec interrupt numbers and build breakage mips/kvm: Use KVM_REG_MIPS and proper size indicators for *_ONE_REG kvm: Add definition of KVM_REG_MIPS KVM: add kvm_para_available to asm-generic/kvm_para.h
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/uapi/asm/kvm.h81
-rw-r--r--arch/mips/kvm/kvm_mips.c83
-rw-r--r--arch/powerpc/include/asm/kvm_asm.h16
-rw-r--r--arch/powerpc/kvm/44x_tlb.c5
-rw-r--r--arch/powerpc/kvm/booke.c18
-rw-r--r--arch/powerpc/kvm/e500_mmu.c5
-rw-r--r--arch/powerpc/kvm/e500mc.c2
7 files changed, 131 insertions, 79 deletions
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index 3f424f5217da..f09ff5ae2059 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -58,56 +58,53 @@ struct kvm_fpu {
58 * bits[2..0] - Register 'sel' index. 58 * bits[2..0] - Register 'sel' index.
59 * bits[7..3] - Register 'rd' index. 59 * bits[7..3] - Register 'rd' index.
60 * bits[15..8] - Must be zero. 60 * bits[15..8] - Must be zero.
61 * bits[63..16] - 1 -> CP0 registers. 61 * bits[31..16] - 1 -> CP0 registers.
62 * bits[51..32] - Must be zero.
63 * bits[63..52] - As per linux/kvm.h
62 * 64 *
63 * Other sets registers may be added in the future. Each set would 65 * Other sets registers may be added in the future. Each set would
64 * have its own identifier in bits[63..16]. 66 * have its own identifier in bits[31..16].
65 *
66 * The addr field of struct kvm_one_reg must point to an aligned
67 * 64-bit wide location. For registers that are narrower than
68 * 64-bits, the value is stored in the low order bits of the location,
69 * and sign extended to 64-bits.
70 * 67 *
71 * The registers defined in struct kvm_regs are also accessible, the 68 * The registers defined in struct kvm_regs are also accessible, the
72 * id values for these are below. 69 * id values for these are below.
73 */ 70 */
74 71
75#define KVM_REG_MIPS_R0 0 72#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
76#define KVM_REG_MIPS_R1 1 73#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
77#define KVM_REG_MIPS_R2 2 74#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
78#define KVM_REG_MIPS_R3 3 75#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
79#define KVM_REG_MIPS_R4 4 76#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
80#define KVM_REG_MIPS_R5 5 77#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
81#define KVM_REG_MIPS_R6 6 78#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
82#define KVM_REG_MIPS_R7 7 79#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
83#define KVM_REG_MIPS_R8 8 80#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
84#define KVM_REG_MIPS_R9 9 81#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
85#define KVM_REG_MIPS_R10 10 82#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
86#define KVM_REG_MIPS_R11 11 83#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
87#define KVM_REG_MIPS_R12 12 84#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
88#define KVM_REG_MIPS_R13 13 85#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
89#define KVM_REG_MIPS_R14 14 86#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
90#define KVM_REG_MIPS_R15 15 87#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
91#define KVM_REG_MIPS_R16 16 88#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
92#define KVM_REG_MIPS_R17 17 89#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
93#define KVM_REG_MIPS_R18 18 90#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
94#define KVM_REG_MIPS_R19 19 91#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
95#define KVM_REG_MIPS_R20 20 92#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
96#define KVM_REG_MIPS_R21 21 93#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
97#define KVM_REG_MIPS_R22 22 94#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
98#define KVM_REG_MIPS_R23 23 95#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
99#define KVM_REG_MIPS_R24 24 96#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
100#define KVM_REG_MIPS_R25 25 97#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
101#define KVM_REG_MIPS_R26 26 98#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
102#define KVM_REG_MIPS_R27 27 99#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
103#define KVM_REG_MIPS_R28 28 100#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
104#define KVM_REG_MIPS_R29 29 101#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
105#define KVM_REG_MIPS_R30 30 102#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
106#define KVM_REG_MIPS_R31 31 103#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
107 104
108#define KVM_REG_MIPS_HI 32 105#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
109#define KVM_REG_MIPS_LO 33 106#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
110#define KVM_REG_MIPS_PC 34 107#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
111 108
112/* 109/*
113 * KVM MIPS specific structures and definitions 110 * KVM MIPS specific structures and definitions
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index d934b017f479..dd203e59e6fd 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -485,29 +485,35 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
485 return -ENOIOCTLCMD; 485 return -ENOIOCTLCMD;
486} 486}
487 487
488#define KVM_REG_MIPS_CP0_INDEX (0x10000 + 8 * 0 + 0) 488#define MIPS_CP0_32(_R, _S) \
489#define KVM_REG_MIPS_CP0_ENTRYLO0 (0x10000 + 8 * 2 + 0) 489 (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
490#define KVM_REG_MIPS_CP0_ENTRYLO1 (0x10000 + 8 * 3 + 0) 490
491#define KVM_REG_MIPS_CP0_CONTEXT (0x10000 + 8 * 4 + 0) 491#define MIPS_CP0_64(_R, _S) \
492#define KVM_REG_MIPS_CP0_USERLOCAL (0x10000 + 8 * 4 + 2) 492 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
493#define KVM_REG_MIPS_CP0_PAGEMASK (0x10000 + 8 * 5 + 0) 493
494#define KVM_REG_MIPS_CP0_PAGEGRAIN (0x10000 + 8 * 5 + 1) 494#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
495#define KVM_REG_MIPS_CP0_WIRED (0x10000 + 8 * 6 + 0) 495#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
496#define KVM_REG_MIPS_CP0_HWRENA (0x10000 + 8 * 7 + 0) 496#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
497#define KVM_REG_MIPS_CP0_BADVADDR (0x10000 + 8 * 8 + 0) 497#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
498#define KVM_REG_MIPS_CP0_COUNT (0x10000 + 8 * 9 + 0) 498#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
499#define KVM_REG_MIPS_CP0_ENTRYHI (0x10000 + 8 * 10 + 0) 499#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
500#define KVM_REG_MIPS_CP0_COMPARE (0x10000 + 8 * 11 + 0) 500#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
501#define KVM_REG_MIPS_CP0_STATUS (0x10000 + 8 * 12 + 0) 501#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
502#define KVM_REG_MIPS_CP0_CAUSE (0x10000 + 8 * 13 + 0) 502#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
503#define KVM_REG_MIPS_CP0_EBASE (0x10000 + 8 * 15 + 1) 503#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
504#define KVM_REG_MIPS_CP0_CONFIG (0x10000 + 8 * 16 + 0) 504#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
505#define KVM_REG_MIPS_CP0_CONFIG1 (0x10000 + 8 * 16 + 1) 505#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
506#define KVM_REG_MIPS_CP0_CONFIG2 (0x10000 + 8 * 16 + 2) 506#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
507#define KVM_REG_MIPS_CP0_CONFIG3 (0x10000 + 8 * 16 + 3) 507#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
508#define KVM_REG_MIPS_CP0_CONFIG7 (0x10000 + 8 * 16 + 7) 508#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
509#define KVM_REG_MIPS_CP0_XCONTEXT (0x10000 + 8 * 20 + 0) 509#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
510#define KVM_REG_MIPS_CP0_ERROREPC (0x10000 + 8 * 30 + 0) 510#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
511#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
512#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
513#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
514#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
515#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
516#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
511 517
512static u64 kvm_mips_get_one_regs[] = { 518static u64 kvm_mips_get_one_regs[] = {
513 KVM_REG_MIPS_R0, 519 KVM_REG_MIPS_R0,
@@ -567,8 +573,6 @@ static u64 kvm_mips_get_one_regs[] = {
567static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 573static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
568 const struct kvm_one_reg *reg) 574 const struct kvm_one_reg *reg)
569{ 575{
570 u64 __user *uaddr = (u64 __user *)(long)reg->addr;
571
572 struct mips_coproc *cop0 = vcpu->arch.cop0; 576 struct mips_coproc *cop0 = vcpu->arch.cop0;
573 s64 v; 577 s64 v;
574 578
@@ -631,18 +635,39 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
631 default: 635 default:
632 return -EINVAL; 636 return -EINVAL;
633 } 637 }
634 return put_user(v, uaddr); 638 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
639 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
640 return put_user(v, uaddr64);
641 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
642 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
643 u32 v32 = (u32)v;
644 return put_user(v32, uaddr32);
645 } else {
646 return -EINVAL;
647 }
635} 648}
636 649
637static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 650static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
638 const struct kvm_one_reg *reg) 651 const struct kvm_one_reg *reg)
639{ 652{
640 u64 __user *uaddr = (u64 __user *)(long)reg->addr;
641 struct mips_coproc *cop0 = vcpu->arch.cop0; 653 struct mips_coproc *cop0 = vcpu->arch.cop0;
642 u64 v; 654 u64 v;
643 655
644 if (get_user(v, uaddr) != 0) 656 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
645 return -EFAULT; 657 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
658
659 if (get_user(v, uaddr64) != 0)
660 return -EFAULT;
661 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
662 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
663 s32 v32;
664
665 if (get_user(v32, uaddr32) != 0)
666 return -EFAULT;
667 v = (s64)v32;
668 } else {
669 return -EINVAL;
670 }
646 671
647 switch (reg->id) { 672 switch (reg->id) {
648 case KVM_REG_MIPS_R0: 673 case KVM_REG_MIPS_R0:
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index b9dd382cb349..851bac7afa4b 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -54,8 +54,16 @@
54#define BOOKE_INTERRUPT_DEBUG 15 54#define BOOKE_INTERRUPT_DEBUG 15
55 55
56/* E500 */ 56/* E500 */
57#define BOOKE_INTERRUPT_SPE_UNAVAIL 32 57#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32
58#define BOOKE_INTERRUPT_SPE_FP_DATA 33 58#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33
59/*
60 * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines
61 */
62#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
63#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
64#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
65#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \
66 BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
59#define BOOKE_INTERRUPT_SPE_FP_ROUND 34 67#define BOOKE_INTERRUPT_SPE_FP_ROUND 34
60#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35 68#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
61#define BOOKE_INTERRUPT_DOORBELL 36 69#define BOOKE_INTERRUPT_DOORBELL 36
@@ -67,10 +75,6 @@
67#define BOOKE_INTERRUPT_HV_SYSCALL 40 75#define BOOKE_INTERRUPT_HV_SYSCALL 40
68#define BOOKE_INTERRUPT_HV_PRIV 41 76#define BOOKE_INTERRUPT_HV_PRIV 41
69 77
70/* altivec */
71#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
72#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
73
74/* book3s */ 78/* book3s */
75 79
76#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100 80#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 5dd3ab469976..ed0385448148 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
441 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu); 441 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
442 struct kvmppc_44x_tlbe *tlbe; 442 struct kvmppc_44x_tlbe *tlbe;
443 unsigned int gtlb_index; 443 unsigned int gtlb_index;
444 int idx;
444 445
445 gtlb_index = kvmppc_get_gpr(vcpu, ra); 446 gtlb_index = kvmppc_get_gpr(vcpu, ra);
446 if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) { 447 if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
@@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
473 return EMULATE_FAIL; 474 return EMULATE_FAIL;
474 } 475 }
475 476
477 idx = srcu_read_lock(&vcpu->kvm->srcu);
478
476 if (tlbe_is_host_safe(vcpu, tlbe)) { 479 if (tlbe_is_host_safe(vcpu, tlbe)) {
477 gva_t eaddr; 480 gva_t eaddr;
478 gpa_t gpaddr; 481 gpa_t gpaddr;
@@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
489 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); 492 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
490 } 493 }
491 494
495 srcu_read_unlock(&vcpu->kvm->srcu, idx);
496
492 trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1, 497 trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
493 tlbe->word2); 498 tlbe->word2);
494 499
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 1020119226db..5cd7ad0c1176 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -832,6 +832,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
832{ 832{
833 int r = RESUME_HOST; 833 int r = RESUME_HOST;
834 int s; 834 int s;
835 int idx;
836
837#ifdef CONFIG_PPC64
838 WARN_ON(local_paca->irq_happened != 0);
839#endif
840
841 /*
842 * We enter with interrupts disabled in hardware, but
843 * we need to call hard_irq_disable anyway to ensure that
844 * the software state is kept in sync.
845 */
846 hard_irq_disable();
835 847
836 /* update before a new last_exit_type is rewritten */ 848 /* update before a new last_exit_type is rewritten */
837 kvmppc_update_timing_stats(vcpu); 849 kvmppc_update_timing_stats(vcpu);
@@ -1053,6 +1065,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1053 break; 1065 break;
1054 } 1066 }
1055 1067
1068 idx = srcu_read_lock(&vcpu->kvm->srcu);
1069
1056 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); 1070 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1057 gfn = gpaddr >> PAGE_SHIFT; 1071 gfn = gpaddr >> PAGE_SHIFT;
1058 1072
@@ -1075,6 +1089,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1075 kvmppc_account_exit(vcpu, MMIO_EXITS); 1089 kvmppc_account_exit(vcpu, MMIO_EXITS);
1076 } 1090 }
1077 1091
1092 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1078 break; 1093 break;
1079 } 1094 }
1080 1095
@@ -1098,6 +1113,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1098 1113
1099 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); 1114 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
1100 1115
1116 idx = srcu_read_lock(&vcpu->kvm->srcu);
1117
1101 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); 1118 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1102 gfn = gpaddr >> PAGE_SHIFT; 1119 gfn = gpaddr >> PAGE_SHIFT;
1103 1120
@@ -1114,6 +1131,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1114 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); 1131 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
1115 } 1132 }
1116 1133
1134 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1117 break; 1135 break;
1118 } 1136 }
1119 1137
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index c41a5a96b558..6d6f153b6c1d 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -396,6 +396,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
396 struct kvm_book3e_206_tlb_entry *gtlbe; 396 struct kvm_book3e_206_tlb_entry *gtlbe;
397 int tlbsel, esel; 397 int tlbsel, esel;
398 int recal = 0; 398 int recal = 0;
399 int idx;
399 400
400 tlbsel = get_tlb_tlbsel(vcpu); 401 tlbsel = get_tlb_tlbsel(vcpu);
401 esel = get_tlb_esel(vcpu, tlbsel); 402 esel = get_tlb_esel(vcpu, tlbsel);
@@ -430,6 +431,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
430 kvmppc_set_tlb1map_range(vcpu, gtlbe); 431 kvmppc_set_tlb1map_range(vcpu, gtlbe);
431 } 432 }
432 433
434 idx = srcu_read_lock(&vcpu->kvm->srcu);
435
433 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */ 436 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
434 if (tlbe_is_host_safe(vcpu, gtlbe)) { 437 if (tlbe_is_host_safe(vcpu, gtlbe)) {
435 u64 eaddr = get_tlb_eaddr(gtlbe); 438 u64 eaddr = get_tlb_eaddr(gtlbe);
@@ -444,6 +447,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
444 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel)); 447 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel));
445 } 448 }
446 449
450 srcu_read_unlock(&vcpu->kvm->srcu, idx);
451
447 kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS); 452 kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
448 return EMULATE_DONE; 453 return EMULATE_DONE;
449} 454}
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 753cc99eff2b..19c8379575f7 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -177,8 +177,6 @@ int kvmppc_core_check_processor_compat(void)
177 r = 0; 177 r = 0;
178 else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0) 178 else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
179 r = 0; 179 r = 0;
180 else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
181 r = 0;
182 else 180 else
183 r = -ENOTSUPP; 181 r = -ENOTSUPP;
184 182