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authorRalf Baechle <ralf@linux-mips.org>2014-03-31 12:17:33 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-03-31 12:17:33 -0400
commitade63aada79c61bcd5f51cbd310f237399892268 (patch)
tree4f8605528bfd9b6261679883974b9ac4870223dd /arch
parent9a1724c7506bfa7d3d9dcab13f83e9e6446929f9 (diff)
parentc14af233fbe279d0e561ecf84f1208b1bae087ef (diff)
Merge branch '3.14-fixes' into mips-for-linux-next
Diffstat (limited to 'arch')
-rw-r--r--arch/arc/mm/cache_arc700.c4
-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/boot/compressed/.gitignore1
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi2
-rw-r--r--arch/arm/boot/dts/keystone-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dts2
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts2
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts2
-rw-r--r--arch/arm/boot/dts/sama5d36.dtsi2
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi2
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi2
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi2
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi12
-rw-r--r--arch/arm/configs/tegra_defconfig3
-rw-r--r--arch/arm/include/asm/memory.h9
-rw-r--r--arch/arm/kernel/head-common.S12
-rw-r--r--arch/arm/kernel/head.S2
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c8
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c92
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c20
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c9
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c21
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c4
-rw-r--r--arch/arm/mach-sa1100/include/mach/collie.h2
-rw-r--r--arch/arm/mm/dump.c3
-rw-r--r--arch/c6x/include/asm/cache.h1
-rw-r--r--arch/cris/include/asm/bitops.h2
-rw-r--r--arch/ia64/kernel/uncached.c2
-rw-r--r--arch/mips/Kconfig29
-rw-r--r--arch/mips/Kconfig.debug10
-rw-r--r--arch/mips/alchemy/board-gpr.c4
-rw-r--r--arch/mips/alchemy/board-mtx1.c4
-rw-r--r--arch/mips/bcm47xx/board.c1
-rw-r--r--arch/mips/bcm47xx/nvram.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c22
-rw-r--r--arch/mips/include/asm/asmmacro.h15
-rw-r--r--arch/mips/include/asm/fpu.h2
-rw-r--r--arch/mips/include/asm/ftrace.h20
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h12
-rw-r--r--arch/mips/include/asm/syscall.h10
-rw-r--r--arch/mips/include/uapi/asm/inst.h4
-rw-r--r--arch/mips/kernel/ftrace.c5
-rw-r--r--arch/mips/kernel/r4k_fpu.S16
-rw-r--r--arch/mips/kernel/rtlx-cmp.c3
-rw-r--r--arch/mips/kernel/rtlx-mt.c3
-rw-r--r--arch/mips/math-emu/cp1emu.c6
-rw-r--r--arch/mips/mti-malta/malta-amon.c2
-rw-r--r--arch/mips/mti-malta/malta-int.c4
-rw-r--r--arch/mips/pci/msi-octeon.c1
-rw-r--r--arch/mips/power/hibernate.S1
-rw-r--r--arch/parisc/include/asm/page.h11
-rw-r--r--arch/parisc/include/asm/spinlock.h4
-rw-r--r--arch/parisc/include/uapi/asm/unistd.h4
-rw-r--r--arch/parisc/kernel/cache.c64
-rw-r--r--arch/parisc/kernel/syscall_table.S1
-rw-r--r--arch/powerpc/kernel/process.c9
-rw-r--r--arch/powerpc/kernel/reloc_64.S1
-rw-r--r--arch/powerpc/kvm/book3s_hv_rmhandlers.S71
-rw-r--r--arch/powerpc/platforms/cell/ras.c3
-rw-r--r--arch/sh/include/cpu-sh2/cpu/cache.h2
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/cache.h4
-rw-r--r--arch/sh/include/cpu-sh3/cpu/cache.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/cache.h2
-rw-r--r--arch/sh/kernel/cpu/init.c4
-rw-r--r--arch/sh/mm/cache-debugfs.c2
-rw-r--r--arch/sh/mm/cache-sh2.c4
-rw-r--r--arch/sh/mm/cache-sh2a.c6
-rw-r--r--arch/sh/mm/cache-sh4.c4
-rw-r--r--arch/sh/mm/cache-shx3.c4
-rw-r--r--arch/sh/mm/cache.c4
-rw-r--r--arch/sparc/kernel/process_64.c4
-rw-r--r--arch/sparc/kernel/syscalls.S4
-rw-r--r--arch/sparc/mm/tsb.c2
-rw-r--r--arch/x86/Kconfig.cpu4
-rw-r--r--arch/x86/include/asm/barrier.h8
-rw-r--r--arch/x86/include/asm/efi.h1
-rw-r--r--arch/x86/include/asm/io.h2
-rw-r--r--arch/x86/include/asm/spinlock.h5
-rw-r--r--arch/x86/kernel/aperture_64.c20
-rw-r--r--arch/x86/kernel/cpu/centaur.c272
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.c3
-rw-r--r--arch/x86/kernel/head_32.S7
-rw-r--r--arch/x86/kernel/head_64.S6
-rw-r--r--arch/x86/kernel/i387.c15
-rw-r--r--arch/x86/kernel/quirks.c2
-rw-r--r--arch/x86/kernel/setup.c10
-rw-r--r--arch/x86/kvm/svm.c6
-rw-r--r--arch/x86/mm/fault.c47
-rw-r--r--arch/x86/net/bpf_jit.S2
-rw-r--r--arch/x86/platform/efi/efi.c20
-rw-r--r--arch/x86/um/asm/barrier.h4
92 files changed, 401 insertions, 655 deletions
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 6b58c1de7577..400c663b21c2 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -282,7 +282,7 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
282#else 282#else
283 /* if V-P const for loop, PTAG can be written once outside loop */ 283 /* if V-P const for loop, PTAG can be written once outside loop */
284 if (full_page_op) 284 if (full_page_op)
285 write_aux_reg(ARC_REG_DC_PTAG, paddr); 285 write_aux_reg(aux_tag, paddr);
286#endif 286#endif
287 287
288 while (num_lines-- > 0) { 288 while (num_lines-- > 0) {
@@ -296,7 +296,7 @@ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
296 write_aux_reg(aux_cmd, vaddr); 296 write_aux_reg(aux_cmd, vaddr);
297 vaddr += L1_CACHE_BYTES; 297 vaddr += L1_CACHE_BYTES;
298#else 298#else
299 write_aux_reg(aux, paddr); 299 write_aux_reg(aux_cmd, paddr);
300 paddr += L1_CACHE_BYTES; 300 paddr += L1_CACHE_BYTES;
301#endif 301#endif
302 } 302 }
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e25419817791..15949459611f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1578,6 +1578,7 @@ config BL_SWITCHER_DUMMY_IF
1578 1578
1579choice 1579choice
1580 prompt "Memory split" 1580 prompt "Memory split"
1581 depends on MMU
1581 default VMSPLIT_3G 1582 default VMSPLIT_3G
1582 help 1583 help
1583 Select the desired split between kernel and user memory. 1584 Select the desired split between kernel and user memory.
@@ -1595,6 +1596,7 @@ endchoice
1595 1596
1596config PAGE_OFFSET 1597config PAGE_OFFSET
1597 hex 1598 hex
1599 default PHYS_OFFSET if !MMU
1598 default 0x40000000 if VMSPLIT_1G 1600 default 0x40000000 if VMSPLIT_1G
1599 default 0x80000000 if VMSPLIT_2G 1601 default 0x80000000 if VMSPLIT_2G
1600 default 0xC0000000 1602 default 0xC0000000
@@ -1903,6 +1905,7 @@ config XEN
1903 depends on ARM && AEABI && OF 1905 depends on ARM && AEABI && OF
1904 depends on CPU_V7 && !CPU_V6 1906 depends on CPU_V7 && !CPU_V6
1905 depends on !GENERIC_ATOMIC64 1907 depends on !GENERIC_ATOMIC64
1908 depends on MMU
1906 select ARM_PSCI 1909 select ARM_PSCI
1907 select SWIOTLB_XEN 1910 select SWIOTLB_XEN
1908 select ARCH_DMA_ADDR_T_64BIT 1911 select ARCH_DMA_ADDR_T_64BIT
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index 47279aa96a6a..0714e0334e33 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,4 +1,5 @@
1ashldi3.S 1ashldi3.S
2bswapsdi2.S
2font.c 3font.c
3lib1funcs.S 4lib1funcs.S
4hyp-stub.S 5hyp-stub.S
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index e491b82f8d67..792fde1b7f75 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -147,7 +147,7 @@
147 }; 147 };
148 148
149 pinctrl@35004800 { 149 pinctrl@35004800 {
150 compatible = "brcm,capri-pinctrl"; 150 compatible = "brcm,bcm11351-pinctrl";
151 reg = <0x35004800 0x430>; 151 reg = <0x35004800 0x430>;
152 }; 152 };
153 153
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index 2363593e1050..ef58d1c24313 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -612,7 +612,7 @@ clocks {
612 compatible = "ti,keystone,psc-clock"; 612 compatible = "ti,keystone,psc-clock";
613 clocks = <&chipclk13>; 613 clocks = <&chipclk13>;
614 clock-output-names = "vcp-3"; 614 clock-output-names = "vcp-3";
615 reg = <0x0235000a8 0xb00>, <0x02350060 0x400>; 615 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
616 reg-names = "control", "domain"; 616 reg-names = "control", "domain";
617 domain-id = <24>; 617 domain-id = <24>;
618 }; 618 };
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
index c551e4af4d83..d3b253bbc885 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -13,7 +13,7 @@
13 13
14/ { 14/ {
15 model = "OMAP3 GTA04"; 15 model = "OMAP3 GTA04";
16 compatible = "ti,omap3-gta04", "ti,omap3"; 16 compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3";
17 17
18 cpus { 18 cpus {
19 cpu@0 { 19 cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 25a2b5f652fd..f2779ac75872 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "IGEPv2 (TI OMAP AM/DM37x)"; 16 model = "IGEPv2 (TI OMAP AM/DM37x)";
17 compatible = "isee,omap3-igep0020", "ti,omap3"; 17 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
18 18
19 leds { 19 leds {
20 pinctrl-names = "default"; 20 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 145c58cfc8ac..2793749eb1ba 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -13,7 +13,7 @@
13 13
14/ { 14/ {
15 model = "IGEP COM MODULE (TI OMAP AM/DM37x)"; 15 model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030", "ti,omap3"; 16 compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
17 17
18 leds { 18 leds {
19 pinctrl-names = "default"; 19 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi
index 6c31c26e6cc0..db58cad6acd3 100644
--- a/arch/arm/boot/dts/sama5d36.dtsi
+++ b/arch/arm/boot/dts/sama5d36.dtsi
@@ -8,8 +8,8 @@
8 */ 8 */
9#include "sama5d3.dtsi" 9#include "sama5d3.dtsi"
10#include "sama5d3_can.dtsi" 10#include "sama5d3_can.dtsi"
11#include "sama5d3_emac.dtsi"
12#include "sama5d3_gmac.dtsi" 11#include "sama5d3_gmac.dtsi"
12#include "sama5d3_emac.dtsi"
13#include "sama5d3_lcd.dtsi" 13#include "sama5d3_lcd.dtsi"
14#include "sama5d3_mci2.dtsi" 14#include "sama5d3_mci2.dtsi"
15#include "sama5d3_tcb1.dtsi" 15#include "sama5d3_tcb1.dtsi"
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 10666ca8aee1..d4d2763f4794 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -426,7 +426,7 @@
426 }; 426 };
427 427
428 rtp: rtp@01c25000 { 428 rtp: rtp@01c25000 {
429 compatible = "allwinner,sun4i-ts"; 429 compatible = "allwinner,sun4i-a10-ts";
430 reg = <0x01c25000 0x100>; 430 reg = <0x01c25000 0x100>;
431 interrupts = <29>; 431 interrupts = <29>;
432 }; 432 };
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 64961595e8d6..79fd412005b0 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -383,7 +383,7 @@
383 }; 383 };
384 384
385 rtp: rtp@01c25000 { 385 rtp: rtp@01c25000 {
386 compatible = "allwinner,sun4i-ts"; 386 compatible = "allwinner,sun4i-a10-ts";
387 reg = <0x01c25000 0x100>; 387 reg = <0x01c25000 0x100>;
388 interrupts = <29>; 388 interrupts = <29>;
389 }; 389 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 320335abfccd..c463fd730c91 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -346,7 +346,7 @@
346 }; 346 };
347 347
348 rtp: rtp@01c25000 { 348 rtp: rtp@01c25000 {
349 compatible = "allwinner,sun4i-ts"; 349 compatible = "allwinner,sun4i-a10-ts";
350 reg = <0x01c25000 0x100>; 350 reg = <0x01c25000 0x100>;
351 interrupts = <29>; 351 interrupts = <29>;
352 }; 352 };
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9ff09484847b..6f25cf559ad0 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -454,7 +454,7 @@
454 rtc: rtc@01c20d00 { 454 rtc: rtc@01c20d00 {
455 compatible = "allwinner,sun7i-a20-rtc"; 455 compatible = "allwinner,sun7i-a20-rtc";
456 reg = <0x01c20d00 0x20>; 456 reg = <0x01c20d00 0x20>;
457 interrupts = <0 24 1>; 457 interrupts = <0 24 4>;
458 }; 458 };
459 459
460 sid: eeprom@01c23800 { 460 sid: eeprom@01c23800 {
@@ -463,7 +463,7 @@
463 }; 463 };
464 464
465 rtp: rtp@01c25000 { 465 rtp: rtp@01c25000 {
466 compatible = "allwinner,sun4i-ts"; 466 compatible = "allwinner,sun4i-a10-ts";
467 reg = <0x01c25000 0x100>; 467 reg = <0x01c25000 0x100>;
468 interrupts = <0 29 4>; 468 interrupts = <0 29 4>;
469 }; 469 };
@@ -596,10 +596,10 @@
596 hstimer@01c60000 { 596 hstimer@01c60000 {
597 compatible = "allwinner,sun7i-a20-hstimer"; 597 compatible = "allwinner,sun7i-a20-hstimer";
598 reg = <0x01c60000 0x1000>; 598 reg = <0x01c60000 0x1000>;
599 interrupts = <0 81 1>, 599 interrupts = <0 81 4>,
600 <0 82 1>, 600 <0 82 4>,
601 <0 83 1>, 601 <0 83 4>,
602 <0 84 1>; 602 <0 84 4>;
603 clocks = <&ahb_gates 28>; 603 clocks = <&ahb_gates 28>;
604 }; 604 };
605 605
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 00fe9e9710fd..27d69b558c5d 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -204,7 +204,10 @@ CONFIG_MMC_BLOCK_MINORS=16
204CONFIG_MMC_SDHCI=y 204CONFIG_MMC_SDHCI=y
205CONFIG_MMC_SDHCI_PLTFM=y 205CONFIG_MMC_SDHCI_PLTFM=y
206CONFIG_MMC_SDHCI_TEGRA=y 206CONFIG_MMC_SDHCI_TEGRA=y
207CONFIG_NEW_LEDS=y
208CONFIG_LEDS_CLASS=y
207CONFIG_LEDS_GPIO=y 209CONFIG_LEDS_GPIO=y
210CONFIG_LEDS_TRIGGERS=y
208CONFIG_LEDS_TRIGGER_TIMER=y 211CONFIG_LEDS_TRIGGER_TIMER=y
209CONFIG_LEDS_TRIGGER_ONESHOT=y 212CONFIG_LEDS_TRIGGER_ONESHOT=y
210CONFIG_LEDS_TRIGGER_HEARTBEAT=y 213CONFIG_LEDS_TRIGGER_HEARTBEAT=y
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 8756e4bcdba0..4afb376d9c7c 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -30,14 +30,15 @@
30 */ 30 */
31#define UL(x) _AC(x, UL) 31#define UL(x) _AC(x, UL)
32 32
33/* PAGE_OFFSET - the virtual address of the start of the kernel image */
34#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
35
33#ifdef CONFIG_MMU 36#ifdef CONFIG_MMU
34 37
35/* 38/*
36 * PAGE_OFFSET - the virtual address of the start of the kernel image
37 * TASK_SIZE - the maximum size of a user space task. 39 * TASK_SIZE - the maximum size of a user space task.
38 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area 40 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
39 */ 41 */
40#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)
41#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M)) 42#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M))
42#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M) 43#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M)
43 44
@@ -104,10 +105,6 @@
104#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE) 105#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
105#endif 106#endif
106 107
107#ifndef PAGE_OFFSET
108#define PAGE_OFFSET PLAT_PHYS_OFFSET
109#endif
110
111/* 108/*
112 * The module can be at any place in ram in nommu mode. 109 * The module can be at any place in ram in nommu mode.
113 */ 110 */
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 47cd974e57ea..c96ecacb2021 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -177,6 +177,18 @@ __lookup_processor_type_data:
177 .long __proc_info_end 177 .long __proc_info_end
178 .size __lookup_processor_type_data, . - __lookup_processor_type_data 178 .size __lookup_processor_type_data, . - __lookup_processor_type_data
179 179
180__error_lpae:
181#ifdef CONFIG_DEBUG_LL
182 adr r0, str_lpae
183 bl printascii
184 b __error
185str_lpae: .asciz "\nError: Kernel with LPAE support, but CPU does not support LPAE.\n"
186#else
187 b __error
188#endif
189 .align
190ENDPROC(__error_lpae)
191
180__error_p: 192__error_p:
181#ifdef CONFIG_DEBUG_LL 193#ifdef CONFIG_DEBUG_LL
182 adr r0, str_p1 194 adr r0, str_p1
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 914616e0bdcd..f5f381d91556 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -102,7 +102,7 @@ ENTRY(stext)
102 and r3, r3, #0xf @ extract VMSA support 102 and r3, r3, #0xf @ extract VMSA support
103 cmp r3, #5 @ long-descriptor translation table format? 103 cmp r3, #5 @ long-descriptor translation table format?
104 THUMB( it lo ) @ force fixup-able long branch encoding 104 THUMB( it lo ) @ force fixup-able long branch encoding
105 blo __error_p @ only classic page table format 105 blo __error_lpae @ only classic page table format
106#endif 106#endif
107 107
108#ifndef CONFIG_XIP_KERNEL 108#ifndef CONFIG_XIP_KERNEL
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 3b05aea56d1f..11ed9152e665 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -433,7 +433,9 @@ static const struct clk_ops dpll4_m5x2_ck_ops = {
433 .enable = &omap2_dflt_clk_enable, 433 .enable = &omap2_dflt_clk_enable,
434 .disable = &omap2_dflt_clk_disable, 434 .disable = &omap2_dflt_clk_disable,
435 .is_enabled = &omap2_dflt_clk_is_enabled, 435 .is_enabled = &omap2_dflt_clk_is_enabled,
436 .set_rate = &omap3_clkoutx2_set_rate,
436 .recalc_rate = &omap3_clkoutx2_recalc, 437 .recalc_rate = &omap3_clkoutx2_recalc,
438 .round_rate = &omap3_clkoutx2_round_rate,
437}; 439};
438 440
439static const struct clk_ops dpll4_m5x2_ck_3630_ops = { 441static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4c158c838d40..01fc710c8181 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -23,6 +23,8 @@
23#include "prm.h" 23#include "prm.h"
24#include "clockdomain.h" 24#include "clockdomain.h"
25 25
26#define MAX_CPUS 2
27
26/* Machine specific information */ 28/* Machine specific information */
27struct idle_statedata { 29struct idle_statedata {
28 u32 cpu_state; 30 u32 cpu_state;
@@ -48,11 +50,11 @@ static struct idle_statedata omap4_idle_data[] = {
48 }, 50 },
49}; 51};
50 52
51static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS]; 53static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
52static struct clockdomain *cpu_clkdm[NR_CPUS]; 54static struct clockdomain *cpu_clkdm[MAX_CPUS];
53 55
54static atomic_t abort_barrier; 56static atomic_t abort_barrier;
55static bool cpu_done[NR_CPUS]; 57static bool cpu_done[MAX_CPUS];
56static struct idle_statedata *state_ptr = &omap4_idle_data[0]; 58static struct idle_statedata *state_ptr = &omap4_idle_data[0];
57 59
58/* Private functions */ 60/* Private functions */
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3185ced807c9..3c418ea54bbe 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -623,6 +623,32 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
623 623
624/* Clock control for DPLL outputs */ 624/* Clock control for DPLL outputs */
625 625
626/* Find the parent DPLL for the given clkoutx2 clock */
627static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
628{
629 struct clk_hw_omap *pclk = NULL;
630 struct clk *parent;
631
632 /* Walk up the parents of clk, looking for a DPLL */
633 do {
634 do {
635 parent = __clk_get_parent(hw->clk);
636 hw = __clk_get_hw(parent);
637 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
638 if (!hw)
639 break;
640 pclk = to_clk_hw_omap(hw);
641 } while (pclk && !pclk->dpll_data);
642
643 /* clk does not have a DPLL as a parent? error in the clock data */
644 if (!pclk) {
645 WARN_ON(1);
646 return NULL;
647 }
648
649 return pclk;
650}
651
626/** 652/**
627 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate 653 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
628 * @clk: DPLL output struct clk 654 * @clk: DPLL output struct clk
@@ -637,27 +663,14 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
637 unsigned long rate; 663 unsigned long rate;
638 u32 v; 664 u32 v;
639 struct clk_hw_omap *pclk = NULL; 665 struct clk_hw_omap *pclk = NULL;
640 struct clk *parent;
641 666
642 if (!parent_rate) 667 if (!parent_rate)
643 return 0; 668 return 0;
644 669
645 /* Walk up the parents of clk, looking for a DPLL */ 670 pclk = omap3_find_clkoutx2_dpll(hw);
646 do {
647 do {
648 parent = __clk_get_parent(hw->clk);
649 hw = __clk_get_hw(parent);
650 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
651 if (!hw)
652 break;
653 pclk = to_clk_hw_omap(hw);
654 } while (pclk && !pclk->dpll_data);
655 671
656 /* clk does not have a DPLL as a parent? error in the clock data */ 672 if (!pclk)
657 if (!pclk) {
658 WARN_ON(1);
659 return 0; 673 return 0;
660 }
661 674
662 dd = pclk->dpll_data; 675 dd = pclk->dpll_data;
663 676
@@ -672,6 +685,55 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
672 return rate; 685 return rate;
673} 686}
674 687
688int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
689 unsigned long parent_rate)
690{
691 return 0;
692}
693
694long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
695 unsigned long *prate)
696{
697 const struct dpll_data *dd;
698 u32 v;
699 struct clk_hw_omap *pclk = NULL;
700
701 if (!*prate)
702 return 0;
703
704 pclk = omap3_find_clkoutx2_dpll(hw);
705
706 if (!pclk)
707 return 0;
708
709 dd = pclk->dpll_data;
710
711 /* TYPE J does not have a clkoutx2 */
712 if (dd->flags & DPLL_J_TYPE) {
713 *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);
714 return *prate;
715 }
716
717 WARN_ON(!dd->enable_mask);
718
719 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
720 v >>= __ffs(dd->enable_mask);
721
722 /* If in bypass, the rate is fixed to the bypass rate*/
723 if (v != OMAP3XXX_EN_DPLL_LOCKED)
724 return *prate;
725
726 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
727 unsigned long best_parent;
728
729 best_parent = (rate / 2);
730 *prate = __clk_round_rate(__clk_get_parent(hw->clk),
731 best_parent);
732 }
733
734 return *prate * 2;
735}
736
675/* OMAP3/4 non-CORE DPLL clkops */ 737/* OMAP3/4 non-CORE DPLL clkops */
676const struct clk_hw_omap_ops clkhwops_omap3_dpll = { 738const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
677 .allow_idle = omap3_dpll_allow_idle, 739 .allow_idle = omap3_dpll_allow_idle,
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 42d81885c700..1f33f5db10d5 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1947,29 +1947,31 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1947 goto dis_opt_clks; 1947 goto dis_opt_clks;
1948 1948
1949 _write_sysconfig(v, oh); 1949 _write_sysconfig(v, oh);
1950 ret = _clear_softreset(oh, &v);
1951 if (ret)
1952 goto dis_opt_clks;
1953
1954 _write_sysconfig(v, oh);
1955 1950
1956 if (oh->class->sysc->srst_udelay) 1951 if (oh->class->sysc->srst_udelay)
1957 udelay(oh->class->sysc->srst_udelay); 1952 udelay(oh->class->sysc->srst_udelay);
1958 1953
1959 c = _wait_softreset_complete(oh); 1954 c = _wait_softreset_complete(oh);
1960 if (c == MAX_MODULE_SOFTRESET_WAIT) 1955 if (c == MAX_MODULE_SOFTRESET_WAIT) {
1961 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", 1956 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1962 oh->name, MAX_MODULE_SOFTRESET_WAIT); 1957 oh->name, MAX_MODULE_SOFTRESET_WAIT);
1963 else 1958 ret = -ETIMEDOUT;
1959 goto dis_opt_clks;
1960 } else {
1964 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); 1961 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
1962 }
1963
1964 ret = _clear_softreset(oh, &v);
1965 if (ret)
1966 goto dis_opt_clks;
1967
1968 _write_sysconfig(v, oh);
1965 1969
1966 /* 1970 /*
1967 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from 1971 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
1968 * _wait_target_ready() or _reset() 1972 * _wait_target_ready() or _reset()
1969 */ 1973 */
1970 1974
1971 ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
1972
1973dis_opt_clks: 1975dis_opt_clks:
1974 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) 1976 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1975 _disable_optional_clocks(oh); 1977 _disable_optional_clocks(oh);
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 18f333c440db..810c205d668b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1365,11 +1365,10 @@ static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365 .rev_offs = 0x0000, 1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010, 1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014, 1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1369 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1369 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1370 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1370 SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1372 SIDLE_SMART_WKUP),
1373 .sysc_fields = &omap_hwmod_sysc_type1, 1372 .sysc_fields = &omap_hwmod_sysc_type1,
1374}; 1373};
1375 1374
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 3d5b24dcd9a4..c33e07e2f0d4 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -22,6 +22,8 @@
22#include "common-board-devices.h" 22#include "common-board-devices.h"
23#include "dss-common.h" 23#include "dss-common.h"
24#include "control.h" 24#include "control.h"
25#include "omap-secure.h"
26#include "soc.h"
25 27
26struct pdata_init { 28struct pdata_init {
27 const char *compatible; 29 const char *compatible;
@@ -169,6 +171,22 @@ static void __init am3517_evm_legacy_init(void)
169 omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); 171 omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
170 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ 172 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
171} 173}
174
175static void __init nokia_n900_legacy_init(void)
176{
177 hsmmc2_internal_input_clk();
178
179 if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
180 if (IS_ENABLED(CONFIG_ARM_ERRATA_430973)) {
181 pr_info("RX-51: Enabling ARM errata 430973 workaround\n");
182 /* set IBE to 1 */
183 rx51_secure_update_aux_cr(BIT(6), 0);
184 } else {
185 pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n");
186 pr_warning("Thumb binaries may crash randomly without this workaround\n");
187 }
188 }
189}
172#endif /* CONFIG_ARCH_OMAP3 */ 190#endif /* CONFIG_ARCH_OMAP3 */
173 191
174#ifdef CONFIG_ARCH_OMAP4 192#ifdef CONFIG_ARCH_OMAP4
@@ -239,6 +257,7 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
239#endif 257#endif
240#ifdef CONFIG_ARCH_OMAP3 258#ifdef CONFIG_ARCH_OMAP3
241 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), 259 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
260 OF_DEV_AUXDATA("ti,omap3-padconf", 0x480025a0, "480025a0.pinmux", &pcs_pdata),
242 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), 261 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
243 /* Only on am3517 */ 262 /* Only on am3517 */
244 OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), 263 OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
@@ -259,7 +278,7 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
259static struct pdata_init pdata_quirks[] __initdata = { 278static struct pdata_init pdata_quirks[] __initdata = {
260#ifdef CONFIG_ARCH_OMAP3 279#ifdef CONFIG_ARCH_OMAP3
261 { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, }, 280 { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, },
262 { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, 281 { "nokia,omap3-n900", nokia_n900_legacy_init, },
263 { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, 282 { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
264 { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, 283 { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
265 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, 284 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 6334b96b4097..280f3c58abe5 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -183,11 +183,11 @@ void omap4_prminst_global_warm_sw_reset(void)
183 OMAP4_PRM_RSTCTRL_OFFSET); 183 OMAP4_PRM_RSTCTRL_OFFSET);
184 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 184 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
185 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 185 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
186 OMAP4430_PRM_DEVICE_INST, 186 dev_inst,
187 OMAP4_PRM_RSTCTRL_OFFSET); 187 OMAP4_PRM_RSTCTRL_OFFSET);
188 188
189 /* OCP barrier */ 189 /* OCP barrier */
190 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 190 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
191 OMAP4430_PRM_DEVICE_INST, 191 dev_inst,
192 OMAP4_PRM_RSTCTRL_OFFSET); 192 OMAP4_PRM_RSTCTRL_OFFSET);
193} 193}
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index f33679d2d3ee..50e1d850ee2e 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_COLLIE_H 13#ifndef __ASM_ARCH_COLLIE_H
14#define __ASM_ARCH_COLLIE_H 14#define __ASM_ARCH_COLLIE_H
15 15
16#include "hardware.h" /* Gives GPIO_MAX */
17
16extern void locomolcd_power(int on); 18extern void locomolcd_power(int on);
17 19
18#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) 20#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 2b3a56414271..ef69152f9b52 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -264,6 +264,9 @@ static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
264 note_page(st, addr, 3, pmd_val(*pmd)); 264 note_page(st, addr, 3, pmd_val(*pmd));
265 else 265 else
266 walk_pte(st, pmd, addr); 266 walk_pte(st, pmd, addr);
267
268 if (SECTION_SIZE < PMD_SIZE && pmd_large(pmd[1]))
269 note_page(st, addr + SECTION_SIZE, 3, pmd_val(pmd[1]));
267 } 270 }
268} 271}
269 272
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
index 09c5a0f5f4d1..86648c083bb4 100644
--- a/arch/c6x/include/asm/cache.h
+++ b/arch/c6x/include/asm/cache.h
@@ -12,6 +12,7 @@
12#define _ASM_C6X_CACHE_H 12#define _ASM_C6X_CACHE_H
13 13
14#include <linux/irqflags.h> 14#include <linux/irqflags.h>
15#include <linux/init.h>
15 16
16/* 17/*
17 * Cache line size 18 * Cache line size
diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h
index 184066ceb1f6..053c17b36559 100644
--- a/arch/cris/include/asm/bitops.h
+++ b/arch/cris/include/asm/bitops.h
@@ -144,7 +144,7 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
144 * definition, which doesn't have the same semantics. We don't want to 144 * definition, which doesn't have the same semantics. We don't want to
145 * use -fno-builtin, so just hide the name ffs. 145 * use -fno-builtin, so just hide the name ffs.
146 */ 146 */
147#define ffs kernel_ffs 147#define ffs(x) kernel_ffs(x)
148 148
149#include <asm-generic/bitops/fls.h> 149#include <asm-generic/bitops/fls.h>
150#include <asm-generic/bitops/__fls.h> 150#include <asm-generic/bitops/__fls.h>
diff --git a/arch/ia64/kernel/uncached.c b/arch/ia64/kernel/uncached.c
index a96bcf83a735..20e8a9b21d75 100644
--- a/arch/ia64/kernel/uncached.c
+++ b/arch/ia64/kernel/uncached.c
@@ -98,7 +98,7 @@ static int uncached_add_chunk(struct uncached_pool *uc_pool, int nid)
98 /* attempt to allocate a granule's worth of cached memory pages */ 98 /* attempt to allocate a granule's worth of cached memory pages */
99 99
100 page = alloc_pages_exact_node(nid, 100 page = alloc_pages_exact_node(nid,
101 GFP_KERNEL | __GFP_ZERO | GFP_THISNODE, 101 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE,
102 IA64_GRANULE_SHIFT-PAGE_SHIFT); 102 IA64_GRANULE_SHIFT-PAGE_SHIFT);
103 if (!page) { 103 if (!page) {
104 mutex_unlock(&uc_pool->add_chunk_mutex); 104 mutex_unlock(&uc_pool->add_chunk_mutex);
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 14aeb174e00f..fc9be7c8c5aa 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -125,7 +125,7 @@ config BCM47XX
125 select SYS_SUPPORTS_32BIT_KERNEL 125 select SYS_SUPPORTS_32BIT_KERNEL
126 select SYS_SUPPORTS_LITTLE_ENDIAN 126 select SYS_SUPPORTS_LITTLE_ENDIAN
127 select SYS_HAS_EARLY_PRINTK 127 select SYS_HAS_EARLY_PRINTK
128 select EARLY_PRINTK_8250 if EARLY_PRINTK 128 select USE_GENERIC_EARLY_PRINTK_8250
129 help 129 help
130 Support for BCM47XX based boards 130 Support for BCM47XX based boards
131 131
@@ -152,7 +152,6 @@ config MIPS_COBALT
152 select CSRC_R4K 152 select CSRC_R4K
153 select CEVT_GT641XX 153 select CEVT_GT641XX
154 select DMA_NONCOHERENT 154 select DMA_NONCOHERENT
155 select EARLY_PRINTK_8250 if EARLY_PRINTK
156 select HW_HAS_PCI 155 select HW_HAS_PCI
157 select I8253 156 select I8253
158 select I8259 157 select I8259
@@ -165,6 +164,7 @@ config MIPS_COBALT
165 select SYS_SUPPORTS_32BIT_KERNEL 164 select SYS_SUPPORTS_32BIT_KERNEL
166 select SYS_SUPPORTS_64BIT_KERNEL 165 select SYS_SUPPORTS_64BIT_KERNEL
167 select SYS_SUPPORTS_LITTLE_ENDIAN 166 select SYS_SUPPORTS_LITTLE_ENDIAN
167 select USE_GENERIC_EARLY_PRINTK_8250
168 168
169config MACH_DECSTATION 169config MACH_DECSTATION
170 bool "DECstations" 170 bool "DECstations"
@@ -677,6 +677,7 @@ config SNI_RM
677 select SYS_SUPPORTS_BIG_ENDIAN 677 select SYS_SUPPORTS_BIG_ENDIAN
678 select SYS_SUPPORTS_HIGHMEM 678 select SYS_SUPPORTS_HIGHMEM
679 select SYS_SUPPORTS_LITTLE_ENDIAN 679 select SYS_SUPPORTS_LITTLE_ENDIAN
680 select USE_GENERIC_EARLY_PRINTK_8250
680 help 681 help
681 The SNI RM200/300/400 are MIPS-based machines manufactured by 682 The SNI RM200/300/400 are MIPS-based machines manufactured by
682 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid 683 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -1824,12 +1825,12 @@ endchoice
1824 1825
1825config FORCE_MAX_ZONEORDER 1826config FORCE_MAX_ZONEORDER
1826 int "Maximum zone order" 1827 int "Maximum zone order"
1827 range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB 1828 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1828 default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB 1829 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1829 range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB 1830 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1830 default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB 1831 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1831 range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB 1832 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1832 default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB 1833 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1833 range 11 64 1834 range 11 64
1834 default "11" 1835 default "11"
1835 help 1836 help
@@ -2456,9 +2457,8 @@ config SECCOMP
2456 If unsure, say Y. Only embedded should say N here. 2457 If unsure, say Y. Only embedded should say N here.
2457 2458
2458config MIPS_O32_FP64_SUPPORT 2459config MIPS_O32_FP64_SUPPORT
2459 bool "Support for O32 binaries using 64-bit FP" 2460 bool "Support for O32 binaries using 64-bit FP (EXPERIMENTAL)"
2460 depends on 32BIT || MIPS32_O32 2461 depends on 32BIT || MIPS32_O32
2461 default y
2462 help 2462 help
2463 When this is enabled, the kernel will support use of 64-bit floating 2463 When this is enabled, the kernel will support use of 64-bit floating
2464 point registers with binaries using the O32 ABI along with the 2464 point registers with binaries using the O32 ABI along with the
@@ -2470,7 +2470,14 @@ config MIPS_O32_FP64_SUPPORT
2470 of your kernel & potentially improve FP emulation performance by 2470 of your kernel & potentially improve FP emulation performance by
2471 saying N here. 2471 saying N here.
2472 2472
2473 If unsure, say Y. 2473 Although binutils currently supports use of this flag the details
2474 concerning its effect upon the O32 ABI in userland are still being
2475 worked on. In order to avoid userland becoming dependant upon current
2476 behaviour before the details have been finalised, this option should
2477 be considered experimental and only enabled by those working upon
2478 said details.
2479
2480 If unsure, say N.
2474 2481
2475config USE_OF 2482config USE_OF
2476 bool 2483 bool
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index b147e7038ff0..25de29211d76 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -21,13 +21,17 @@ config EARLY_PRINTK
21 unless you want to debug such a crash. 21 unless you want to debug such a crash.
22 22
23config EARLY_PRINTK_8250 23config EARLY_PRINTK_8250
24 bool "8250/16550 and compatible serial early printk driver" 24 bool
25 depends on EARLY_PRINTK 25 depends on EARLY_PRINTK && USE_GENERIC_EARLY_PRINTK_8250
26 default n 26 default y
27 help 27 help
28 "8250/16550 and compatible serial early printk driver"
28 If you say Y here, it will be possible to use a 8250/16550 serial 29 If you say Y here, it will be possible to use a 8250/16550 serial
29 port as the boot console. 30 port as the boot console.
30 31
32config USE_GENERIC_EARLY_PRINTK_8250
33 bool
34
31config CMDLINE_BOOL 35config CMDLINE_BOOL
32 bool "Built-in kernel command line" 36 bool "Built-in kernel command line"
33 default n 37 default n
diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
index 9edc35ff8cf1..acf9a2a37f5a 100644
--- a/arch/mips/alchemy/board-gpr.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -53,10 +53,8 @@ void __init prom_init(void)
53 prom_init_cmdline(); 53 prom_init_cmdline();
54 54
55 memsize_str = prom_getenv("memsize"); 55 memsize_str = prom_getenv("memsize");
56 if (!memsize_str) 56 if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
57 memsize = 0x04000000; 57 memsize = 0x04000000;
58 else
59 strict_strtoul(memsize_str, 0, &memsize);
60 add_memory_region(0, memsize, BOOT_MEM_RAM); 58 add_memory_region(0, memsize, BOOT_MEM_RAM);
61} 59}
62 60
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 9969dbab19e3..25a59a23547e 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -52,10 +52,8 @@ void __init prom_init(void)
52 prom_init_cmdline(); 52 prom_init_cmdline();
53 53
54 memsize_str = prom_getenv("memsize"); 54 memsize_str = prom_getenv("memsize");
55 if (!memsize_str) 55 if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
56 memsize = 0x04000000; 56 memsize = 0x04000000;
57 else
58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 58}
61 59
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
index adf1ca83f800..44ab1be68c3c 100644
--- a/arch/mips/bcm47xx/board.c
+++ b/arch/mips/bcm47xx/board.c
@@ -1,3 +1,4 @@
1#include <linux/errno.h>
1#include <linux/export.h> 2#include <linux/export.h>
2#include <linux/string.h> 3#include <linux/string.h>
3#include <bcm47xx_board.h> 4#include <bcm47xx_board.h>
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index 6decb27cf48b..2bed73a684ae 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -196,7 +196,7 @@ int bcm47xx_nvram_gpio_pin(const char *name)
196 char nvram_var[10]; 196 char nvram_var[10];
197 char buf[30]; 197 char buf[30];
198 198
199 for (i = 0; i < 16; i++) { 199 for (i = 0; i < 32; i++) {
200 err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i); 200 err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
201 if (err <= 0) 201 if (err <= 0)
202 continue; 202 continue;
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 25fbfae06c1f..c2bb4f896ce7 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -975,10 +975,6 @@ static int octeon_irq_ciu_xlat(struct irq_domain *d,
975 if (ciu > 1 || bit > 63) 975 if (ciu > 1 || bit > 63)
976 return -EINVAL; 976 return -EINVAL;
977 977
978 /* These are the GPIO lines */
979 if (ciu == 0 && bit >= 16 && bit < 32)
980 return -EINVAL;
981
982 *out_hwirq = (ciu << 6) | bit; 978 *out_hwirq = (ciu << 6) | bit;
983 *out_type = 0; 979 *out_type = 0;
984 980
@@ -1007,6 +1003,10 @@ static int octeon_irq_ciu_map(struct irq_domain *d,
1007 if (!octeon_irq_virq_in_range(virq)) 1003 if (!octeon_irq_virq_in_range(virq))
1008 return -EINVAL; 1004 return -EINVAL;
1009 1005
1006 /* Don't map irq if it is reserved for GPIO. */
1007 if (line == 0 && bit >= 16 && bit <32)
1008 return 0;
1009
1010 if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) 1010 if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
1011 return -EINVAL; 1011 return -EINVAL;
1012 1012
@@ -1525,10 +1525,6 @@ static int octeon_irq_ciu2_xlat(struct irq_domain *d,
1525 ciu = intspec[0]; 1525 ciu = intspec[0];
1526 bit = intspec[1]; 1526 bit = intspec[1];
1527 1527
1528 /* Line 7 are the GPIO lines */
1529 if (ciu > 6 || bit > 63)
1530 return -EINVAL;
1531
1532 *out_hwirq = (ciu << 6) | bit; 1528 *out_hwirq = (ciu << 6) | bit;
1533 *out_type = 0; 1529 *out_type = 0;
1534 1530
@@ -1570,8 +1566,14 @@ static int octeon_irq_ciu2_map(struct irq_domain *d,
1570 if (!octeon_irq_virq_in_range(virq)) 1566 if (!octeon_irq_virq_in_range(virq))
1571 return -EINVAL; 1567 return -EINVAL;
1572 1568
1573 /* Line 7 are the GPIO lines */ 1569 /*
1574 if (line > 6 || octeon_irq_ciu_to_irq[line][bit] != 0) 1570 * Don't map irq if it is reserved for GPIO.
1571 * (Line 7 are the GPIO lines.)
1572 */
1573 if (line == 7)
1574 return 0;
1575
1576 if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)
1575 return -EINVAL; 1577 return -EINVAL;
1576 1578
1577 if (octeon_irq_ciu2_is_edge(line, bit)) 1579 if (octeon_irq_ciu2_is_edge(line, bit))
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index fe3b03c793e5..b464b8b1147a 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -9,6 +9,7 @@
9#define _ASM_ASMMACRO_H 9#define _ASM_ASMMACRO_H
10 10
11#include <asm/hazards.h> 11#include <asm/hazards.h>
12#include <asm/asm-offsets.h>
12 13
13#ifdef CONFIG_32BIT 14#ifdef CONFIG_32BIT
14#include <asm/asmmacro-32.h> 15#include <asm/asmmacro-32.h>
@@ -54,11 +55,21 @@
54 .endm 55 .endm
55 56
56 .macro local_irq_disable reg=t0 57 .macro local_irq_disable reg=t0
58#ifdef CONFIG_PREEMPT
59 lw \reg, TI_PRE_COUNT($28)
60 addi \reg, \reg, 1
61 sw \reg, TI_PRE_COUNT($28)
62#endif
57 mfc0 \reg, CP0_STATUS 63 mfc0 \reg, CP0_STATUS
58 ori \reg, \reg, 1 64 ori \reg, \reg, 1
59 xori \reg, \reg, 1 65 xori \reg, \reg, 1
60 mtc0 \reg, CP0_STATUS 66 mtc0 \reg, CP0_STATUS
61 irq_disable_hazard 67 irq_disable_hazard
68#ifdef CONFIG_PREEMPT
69 lw \reg, TI_PRE_COUNT($28)
70 addi \reg, \reg, -1
71 sw \reg, TI_PRE_COUNT($28)
72#endif
62 .endm 73 .endm
63#endif /* CONFIG_MIPS_MT_SMTC */ 74#endif /* CONFIG_MIPS_MT_SMTC */
64 75
@@ -106,7 +117,7 @@
106 .endm 117 .endm
107 118
108 .macro fpu_save_double thread status tmp 119 .macro fpu_save_double thread status tmp
109#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 120#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
110 sll \tmp, \status, 5 121 sll \tmp, \status, 5
111 bgez \tmp, 10f 122 bgez \tmp, 10f
112 fpu_save_16odd \thread 123 fpu_save_16odd \thread
@@ -159,7 +170,7 @@
159 .endm 170 .endm
160 171
161 .macro fpu_restore_double thread status tmp 172 .macro fpu_restore_double thread status tmp
162#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 173#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
163 sll \tmp, \status, 5 174 sll \tmp, \status, 5
164 bgez \tmp, 10f # 16 register mode? 175 bgez \tmp, 10f # 16 register mode?
165 176
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3d61f0017f..4d86b72750c7 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -57,7 +57,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
57 return 0; 57 return 0;
58 58
59 case FPU_64BIT: 59 case FPU_64BIT:
60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64)) 60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
61 /* we only have a 32-bit FPU */ 61 /* we only have a 32-bit FPU */
62 return SIGFPE; 62 return SIGFPE;
63#endif 63#endif
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index ce35c9af0c28..992aaba603b5 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -22,12 +22,12 @@ extern void _mcount(void);
22#define safe_load(load, src, dst, error) \ 22#define safe_load(load, src, dst, error) \
23do { \ 23do { \
24 asm volatile ( \ 24 asm volatile ( \
25 "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\ 25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
26 " li %[" STR(error) "], 0\n" \ 26 " li %[tmp_err], 0\n" \
27 "2:\n" \ 27 "2:\n" \
28 \ 28 \
29 ".section .fixup, \"ax\"\n" \ 29 ".section .fixup, \"ax\"\n" \
30 "3: li %[" STR(error) "], 1\n" \ 30 "3: li %[tmp_err], 1\n" \
31 " j 2b\n" \ 31 " j 2b\n" \
32 ".previous\n" \ 32 ".previous\n" \
33 \ 33 \
@@ -35,8 +35,8 @@ do { \
35 STR(PTR) "\t1b, 3b\n\t" \ 35 STR(PTR) "\t1b, 3b\n\t" \
36 ".previous\n" \ 36 ".previous\n" \
37 \ 37 \
38 : [dst] "=&r" (dst), [error] "=r" (error)\ 38 : [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
39 : [src] "r" (src) \ 39 : [tmp_src] "r" (src) \
40 : "memory" \ 40 : "memory" \
41 ); \ 41 ); \
42} while (0) 42} while (0)
@@ -44,12 +44,12 @@ do { \
44#define safe_store(store, src, dst, error) \ 44#define safe_store(store, src, dst, error) \
45do { \ 45do { \
46 asm volatile ( \ 46 asm volatile ( \
47 "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\ 47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
48 " li %[" STR(error) "], 0\n" \ 48 " li %[tmp_err], 0\n" \
49 "2:\n" \ 49 "2:\n" \
50 \ 50 \
51 ".section .fixup, \"ax\"\n" \ 51 ".section .fixup, \"ax\"\n" \
52 "3: li %[" STR(error) "], 1\n" \ 52 "3: li %[tmp_err], 1\n" \
53 " j 2b\n" \ 53 " j 2b\n" \
54 ".previous\n" \ 54 ".previous\n" \
55 \ 55 \
@@ -57,8 +57,8 @@ do { \
57 STR(PTR) "\t1b, 3b\n\t" \ 57 STR(PTR) "\t1b, 3b\n\t" \
58 ".previous\n" \ 58 ".previous\n" \
59 \ 59 \
60 : [error] "=r" (error) \ 60 : [tmp_err] "=r" (error) \
61 : [dst] "r" (dst), [src] "r" (src)\ 61 : [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
62 : "memory" \ 62 : "memory" \
63 ); \ 63 ); \
64} while (0) 64} while (0)
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 54f9e84db8ac..b4c3ecb17d48 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -1161,18 +1161,6 @@ enum soc_au1200_ints {
1161#define MAC_RX_BUFF3_STATUS 0x30 1161#define MAC_RX_BUFF3_STATUS 0x30
1162#define MAC_RX_BUFF3_ADDR 0x34 1162#define MAC_RX_BUFF3_ADDR 0x34
1163 1163
1164#define UART_RX 0 /* Receive buffer */
1165#define UART_TX 4 /* Transmit buffer */
1166#define UART_IER 8 /* Interrupt Enable Register */
1167#define UART_IIR 0xC /* Interrupt ID Register */
1168#define UART_FCR 0x10 /* FIFO Control Register */
1169#define UART_LCR 0x14 /* Line Control Register */
1170#define UART_MCR 0x18 /* Modem Control Register */
1171#define UART_LSR 0x1C /* Line Status Register */
1172#define UART_MSR 0x20 /* Modem Status Register */
1173#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1174#define UART_MOD_CNTRL 0x100 /* Module Control */
1175
1176/* SSIO */ 1164/* SSIO */
1177#define SSI0_STATUS 0xB1600000 1165#define SSI0_STATUS 0xB1600000
1178# define SSI_STATUS_BF (1 << 4) 1166# define SSI_STATUS_BF (1 << 4)
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 9031745cec1b..6c488c85d791 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -13,6 +13,7 @@
13#ifndef __ASM_MIPS_SYSCALL_H 13#ifndef __ASM_MIPS_SYSCALL_H
14#define __ASM_MIPS_SYSCALL_H 14#define __ASM_MIPS_SYSCALL_H
15 15
16#include <linux/compiler.h>
16#include <linux/audit.h> 17#include <linux/audit.h>
17#include <linux/elf-em.h> 18#include <linux/elf-em.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -50,14 +51,14 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
50 51
51#ifdef CONFIG_32BIT 52#ifdef CONFIG_32BIT
52 case 4: case 5: case 6: case 7: 53 case 4: case 5: case 6: case 7:
53 return get_user(*arg, (int *)usp + 4 * n); 54 return get_user(*arg, (int *)usp + n);
54#endif 55#endif
55 56
56#ifdef CONFIG_64BIT 57#ifdef CONFIG_64BIT
57 case 4: case 5: case 6: case 7: 58 case 4: case 5: case 6: case 7:
58#ifdef CONFIG_MIPS32_O32 59#ifdef CONFIG_MIPS32_O32
59 if (test_thread_flag(TIF_32BIT_REGS)) 60 if (test_thread_flag(TIF_32BIT_REGS))
60 return get_user(*arg, (int *)usp + 4 * n); 61 return get_user(*arg, (int *)usp + n);
61 else 62 else
62#endif 63#endif
63 *arg = regs->regs[4 + n]; 64 *arg = regs->regs[4 + n];
@@ -68,6 +69,8 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
68 default: 69 default:
69 BUG(); 70 BUG();
70 } 71 }
72
73 unreachable();
71} 74}
72 75
73static inline long syscall_get_return_value(struct task_struct *task, 76static inline long syscall_get_return_value(struct task_struct *task,
@@ -100,7 +103,6 @@ static inline void syscall_get_arguments(struct task_struct *task,
100 unsigned int i, unsigned int n, 103 unsigned int i, unsigned int n,
101 unsigned long *args) 104 unsigned long *args)
102{ 105{
103 unsigned long arg;
104 int ret; 106 int ret;
105 /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */ 107 /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
106 if ((config_enabled(CONFIG_32BIT) || 108 if ((config_enabled(CONFIG_32BIT) ||
@@ -111,7 +113,7 @@ static inline void syscall_get_arguments(struct task_struct *task,
111 } 113 }
112 114
113 while (n--) 115 while (n--)
114 ret |= mips_get_syscall_arg(&arg, task, regs, i++); 116 ret |= mips_get_syscall_arg(args++, task, regs, i++);
115 117
116 /* 118 /*
117 * No way to communicate an error because this is a void function. 119 * No way to communicate an error because this is a void function.
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 1a44c5ac6f4f..df6e775f3fef 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -170,8 +170,8 @@ enum cop1_sdw_func {
170 */ 170 */
171enum cop1x_func { 171enum cop1x_func {
172 lwxc1_op = 0x00, ldxc1_op = 0x01, 172 lwxc1_op = 0x00, ldxc1_op = 0x01,
173 pfetch_op = 0x07, swxc1_op = 0x08, 173 swxc1_op = 0x08, sdxc1_op = 0x09,
174 sdxc1_op = 0x09, madd_s_op = 0x20, 174 pfetch_op = 0x0f, madd_s_op = 0x20,
175 madd_d_op = 0x21, madd_e_op = 0x22, 175 madd_d_op = 0x21, madd_e_op = 0x22,
176 msub_s_op = 0x28, msub_d_op = 0x29, 176 msub_s_op = 0x28, msub_d_op = 0x29,
177 msub_e_op = 0x2a, nmadd_s_op = 0x30, 177 msub_e_op = 0x2a, nmadd_s_op = 0x30,
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index ddcc3500248d..74fe73506d8f 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -115,11 +115,10 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
115 safe_store_code(new_code1, ip, faulted); 115 safe_store_code(new_code1, ip, faulted);
116 if (unlikely(faulted)) 116 if (unlikely(faulted))
117 return -EFAULT; 117 return -EFAULT;
118 ip += 4; 118 safe_store_code(new_code2, ip + 4, faulted);
119 safe_store_code(new_code2, ip, faulted);
120 if (unlikely(faulted)) 119 if (unlikely(faulted))
121 return -EFAULT; 120 return -EFAULT;
122 flush_icache_range(ip, ip + 8); /* original ip + 12 */ 121 flush_icache_range(ip, ip + 8);
123 return 0; 122 return 0;
124} 123}
125#endif 124#endif
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 0cfa7a56a153..71814272d148 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -36,9 +36,9 @@
36LEAF(_save_fp_context) 36LEAF(_save_fp_context)
37 cfc1 t1, fcr31 37 cfc1 t1, fcr31
38 38
39#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) 39#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
40 .set push 40 .set push
41#ifdef CONFIG_MIPS32_R2 41#ifdef CONFIG_CPU_MIPS32_R2
42 .set mips64r2 42 .set mips64r2
43 mfc0 t0, CP0_STATUS 43 mfc0 t0, CP0_STATUS
44 sll t0, t0, 5 44 sll t0, t0, 5
@@ -147,11 +147,11 @@ LEAF(_save_fp_context32)
147 * - cp1 status/control register 147 * - cp1 status/control register
148 */ 148 */
149LEAF(_restore_fp_context) 149LEAF(_restore_fp_context)
150 EX lw t0, SC_FPC_CSR(a0) 150 EX lw t1, SC_FPC_CSR(a0)
151 151
152#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) 152#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
153 .set push 153 .set push
154#ifdef CONFIG_MIPS32_R2 154#ifdef CONFIG_CPU_MIPS32_R2
155 .set mips64r2 155 .set mips64r2
156 mfc0 t0, CP0_STATUS 156 mfc0 t0, CP0_STATUS
157 sll t0, t0, 5 157 sll t0, t0, 5
@@ -192,7 +192,7 @@ LEAF(_restore_fp_context)
192 EX ldc1 $f26, SC_FPREGS+208(a0) 192 EX ldc1 $f26, SC_FPREGS+208(a0)
193 EX ldc1 $f28, SC_FPREGS+224(a0) 193 EX ldc1 $f28, SC_FPREGS+224(a0)
194 EX ldc1 $f30, SC_FPREGS+240(a0) 194 EX ldc1 $f30, SC_FPREGS+240(a0)
195 ctc1 t0, fcr31 195 ctc1 t1, fcr31
196 jr ra 196 jr ra
197 li v0, 0 # success 197 li v0, 0 # success
198 END(_restore_fp_context) 198 END(_restore_fp_context)
@@ -200,7 +200,7 @@ LEAF(_restore_fp_context)
200#ifdef CONFIG_MIPS32_COMPAT 200#ifdef CONFIG_MIPS32_COMPAT
201LEAF(_restore_fp_context32) 201LEAF(_restore_fp_context32)
202 /* Restore an o32 sigcontext. */ 202 /* Restore an o32 sigcontext. */
203 EX lw t0, SC32_FPC_CSR(a0) 203 EX lw t1, SC32_FPC_CSR(a0)
204 204
205 mfc0 t0, CP0_STATUS 205 mfc0 t0, CP0_STATUS
206 sll t0, t0, 5 206 sll t0, t0, 5
@@ -240,7 +240,7 @@ LEAF(_restore_fp_context32)
240 EX ldc1 $f26, SC32_FPREGS+208(a0) 240 EX ldc1 $f26, SC32_FPREGS+208(a0)
241 EX ldc1 $f28, SC32_FPREGS+224(a0) 241 EX ldc1 $f28, SC32_FPREGS+224(a0)
242 EX ldc1 $f30, SC32_FPREGS+240(a0) 242 EX ldc1 $f30, SC32_FPREGS+240(a0)
243 ctc1 t0, fcr31 243 ctc1 t1, fcr31
244 jr ra 244 jr ra
245 li v0, 0 # success 245 li v0, 0 # success
246 END(_restore_fp_context32) 246 END(_restore_fp_context32)
diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c
index 56dc69635153..758fb3cd2326 100644
--- a/arch/mips/kernel/rtlx-cmp.c
+++ b/arch/mips/kernel/rtlx-cmp.c
@@ -112,5 +112,8 @@ void __exit rtlx_module_exit(void)
112 112
113 for (i = 0; i < RTLX_CHANNELS; i++) 113 for (i = 0; i < RTLX_CHANNELS; i++)
114 device_destroy(mt_class, MKDEV(major, i)); 114 device_destroy(mt_class, MKDEV(major, i));
115
115 unregister_chrdev(major, RTLX_MODULE_NAME); 116 unregister_chrdev(major, RTLX_MODULE_NAME);
117
118 aprp_hook = NULL;
116} 119}
diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c
index 91d61ba422b4..9c1aca00fd54 100644
--- a/arch/mips/kernel/rtlx-mt.c
+++ b/arch/mips/kernel/rtlx-mt.c
@@ -144,5 +144,8 @@ void __exit rtlx_module_exit(void)
144 144
145 for (i = 0; i < RTLX_CHANNELS; i++) 145 for (i = 0; i < RTLX_CHANNELS; i++)
146 device_destroy(mt_class, MKDEV(major, i)); 146 device_destroy(mt_class, MKDEV(major, i));
147
147 unregister_chrdev(major, RTLX_MODULE_NAME); 148 unregister_chrdev(major, RTLX_MODULE_NAME);
149
150 aprp_hook = NULL;
148} 151}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 71a697c9d385..7b3c9acae689 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1561,10 +1561,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1561 break; 1561 break;
1562 } 1562 }
1563 1563
1564 case 0x7: /* 7 */ 1564 case 0x3:
1565 if (MIPSInst_FUNC(ir) != pfetch_op) { 1565 if (MIPSInst_FUNC(ir) != pfetch_op)
1566 return SIGILL; 1566 return SIGILL;
1567 } 1567
1568 /* ignore prefx operation */ 1568 /* ignore prefx operation */
1569 break; 1569 break;
1570 1570
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 592ac0427426..84ac523b0ce0 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -72,7 +72,7 @@ int amon_cpu_start(int cpu,
72 return 0; 72 return 0;
73} 73}
74 74
75#ifdef CONFIG_MIPS_VPE_LOADER 75#ifdef CONFIG_MIPS_VPE_LOADER_CMP
76int vpe_run(struct vpe *v) 76int vpe_run(struct vpe *v)
77{ 77{
78 struct vpe_notifications *n; 78 struct vpe_notifications *n;
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index c6cbfebcac9b..b71ee809191a 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -117,7 +117,7 @@ static void malta_hw0_irqdispatch(void)
117 117
118 do_IRQ(MALTA_INT_BASE + irq); 118 do_IRQ(MALTA_INT_BASE + irq);
119 119
120#ifdef MIPS_VPE_APSP_API 120#ifdef CONFIG_MIPS_VPE_APSP_API_MT
121 if (aprp_hook) 121 if (aprp_hook)
122 aprp_hook(); 122 aprp_hook();
123#endif 123#endif
@@ -311,7 +311,7 @@ static void ipi_call_dispatch(void)
311 311
312static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 312static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
313{ 313{
314#ifdef MIPS_VPE_APSP_API 314#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
315 if (aprp_hook) 315 if (aprp_hook)
316 aprp_hook(); 316 aprp_hook();
317#endif 317#endif
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index d37be36dc659..2b91b0e61566 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -150,6 +150,7 @@ msi_irq_allocated:
150 msg.address_lo = 150 msg.address_lo =
151 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff; 151 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
152 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32; 152 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
153 break;
153 case OCTEON_DMA_BAR_TYPE_BIG: 154 case OCTEON_DMA_BAR_TYPE_BIG:
154 /* When using big bar, Bar 0 is based at 0 */ 155 /* When using big bar, Bar 0 is based at 0 */
155 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff; 156 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 7e0277a1048f..32a7c828f073 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -43,6 +43,7 @@ LEAF(swsusp_arch_resume)
43 bne t1, t3, 1b 43 bne t1, t3, 1b
44 PTR_L t0, PBE_NEXT(t0) 44 PTR_L t0, PBE_NEXT(t0)
45 bnez t0, 0b 45 bnez t0, 0b
46 jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
46 PTR_LA t0, saved_regs 47 PTR_LA t0, saved_regs
47 PTR_L ra, PT_R31(t0) 48 PTR_L ra, PT_R31(t0)
48 PTR_L sp, PT_R29(t0) 49 PTR_L sp, PT_R29(t0)
diff --git a/arch/parisc/include/asm/page.h b/arch/parisc/include/asm/page.h
index 637fe031aa84..60d5d174dfe4 100644
--- a/arch/parisc/include/asm/page.h
+++ b/arch/parisc/include/asm/page.h
@@ -32,17 +32,6 @@ void copy_page_asm(void *to, void *from);
32void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, 32void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
33 struct page *pg); 33 struct page *pg);
34 34
35/* #define CONFIG_PARISC_TMPALIAS */
36
37#ifdef CONFIG_PARISC_TMPALIAS
38void clear_user_highpage(struct page *page, unsigned long vaddr);
39#define clear_user_highpage clear_user_highpage
40struct vm_area_struct;
41void copy_user_highpage(struct page *to, struct page *from,
42 unsigned long vaddr, struct vm_area_struct *vma);
43#define __HAVE_ARCH_COPY_USER_HIGHPAGE
44#endif
45
46/* 35/*
47 * These are used to make use of C type-checking.. 36 * These are used to make use of C type-checking..
48 */ 37 */
diff --git a/arch/parisc/include/asm/spinlock.h b/arch/parisc/include/asm/spinlock.h
index 3516e0b27044..64f2992e439f 100644
--- a/arch/parisc/include/asm/spinlock.h
+++ b/arch/parisc/include/asm/spinlock.h
@@ -191,8 +191,4 @@ static __inline__ int arch_write_can_lock(arch_rwlock_t *rw)
191#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) 191#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
192#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) 192#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
193 193
194#define arch_spin_relax(lock) cpu_relax()
195#define arch_read_relax(lock) cpu_relax()
196#define arch_write_relax(lock) cpu_relax()
197
198#endif /* __ASM_SPINLOCK_H */ 194#endif /* __ASM_SPINLOCK_H */
diff --git a/arch/parisc/include/uapi/asm/unistd.h b/arch/parisc/include/uapi/asm/unistd.h
index 42706794a36f..265ae5190b0a 100644
--- a/arch/parisc/include/uapi/asm/unistd.h
+++ b/arch/parisc/include/uapi/asm/unistd.h
@@ -828,13 +828,13 @@
828#define __NR_finit_module (__NR_Linux + 333) 828#define __NR_finit_module (__NR_Linux + 333)
829#define __NR_sched_setattr (__NR_Linux + 334) 829#define __NR_sched_setattr (__NR_Linux + 334)
830#define __NR_sched_getattr (__NR_Linux + 335) 830#define __NR_sched_getattr (__NR_Linux + 335)
831#define __NR_utimes (__NR_Linux + 336)
831 832
832#define __NR_Linux_syscalls (__NR_sched_getattr + 1) 833#define __NR_Linux_syscalls (__NR_utimes + 1)
833 834
834 835
835#define __IGNORE_select /* newselect */ 836#define __IGNORE_select /* newselect */
836#define __IGNORE_fadvise64 /* fadvise64_64 */ 837#define __IGNORE_fadvise64 /* fadvise64_64 */
837#define __IGNORE_utimes /* utime */
838 838
839 839
840#define HPUX_GATEWAY_ADDR 0xC0000004 840#define HPUX_GATEWAY_ADDR 0xC0000004
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index ac87a40502e6..a6ffc775a9f8 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -581,67 +581,3 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
581 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn)); 581 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
582 } 582 }
583} 583}
584
585#ifdef CONFIG_PARISC_TMPALIAS
586
587void clear_user_highpage(struct page *page, unsigned long vaddr)
588{
589 void *vto;
590 unsigned long flags;
591
592 /* Clear using TMPALIAS region. The page doesn't need to
593 be flushed but the kernel mapping needs to be purged. */
594
595 vto = kmap_atomic(page);
596
597 /* The PA-RISC 2.0 Architecture book states on page F-6:
598 "Before a write-capable translation is enabled, *all*
599 non-equivalently-aliased translations must be removed
600 from the page table and purged from the TLB. (Note
601 that the caches are not required to be flushed at this
602 time.) Before any non-equivalent aliased translation
603 is re-enabled, the virtual address range for the writeable
604 page (the entire page) must be flushed from the cache,
605 and the write-capable translation removed from the page
606 table and purged from the TLB." */
607
608 purge_kernel_dcache_page_asm((unsigned long)vto);
609 purge_tlb_start(flags);
610 pdtlb_kernel(vto);
611 purge_tlb_end(flags);
612 preempt_disable();
613 clear_user_page_asm(vto, vaddr);
614 preempt_enable();
615
616 pagefault_enable(); /* kunmap_atomic(addr, KM_USER0); */
617}
618
619void copy_user_highpage(struct page *to, struct page *from,
620 unsigned long vaddr, struct vm_area_struct *vma)
621{
622 void *vfrom, *vto;
623 unsigned long flags;
624
625 /* Copy using TMPALIAS region. This has the advantage
626 that the `from' page doesn't need to be flushed. However,
627 the `to' page must be flushed in copy_user_page_asm since
628 it can be used to bring in executable code. */
629
630 vfrom = kmap_atomic(from);
631 vto = kmap_atomic(to);
632
633 purge_kernel_dcache_page_asm((unsigned long)vto);
634 purge_tlb_start(flags);
635 pdtlb_kernel(vto);
636 pdtlb_kernel(vfrom);
637 purge_tlb_end(flags);
638 preempt_disable();
639 copy_user_page_asm(vto, vfrom, vaddr);
640 flush_dcache_page_asm(__pa(vto), vaddr);
641 preempt_enable();
642
643 pagefault_enable(); /* kunmap_atomic(addr, KM_USER1); */
644 pagefault_enable(); /* kunmap_atomic(addr, KM_USER0); */
645}
646
647#endif /* CONFIG_PARISC_TMPALIAS */
diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S
index 8fa3fbb3e4d3..80e5dd248934 100644
--- a/arch/parisc/kernel/syscall_table.S
+++ b/arch/parisc/kernel/syscall_table.S
@@ -431,6 +431,7 @@
431 ENTRY_SAME(finit_module) 431 ENTRY_SAME(finit_module)
432 ENTRY_SAME(sched_setattr) 432 ENTRY_SAME(sched_setattr)
433 ENTRY_SAME(sched_getattr) /* 335 */ 433 ENTRY_SAME(sched_getattr) /* 335 */
434 ENTRY_COMP(utimes)
434 435
435 /* Nothing yet */ 436 /* Nothing yet */
436 437
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 8d4c247f1738..af064d28b365 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1048,6 +1048,15 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1048 flush_altivec_to_thread(src); 1048 flush_altivec_to_thread(src);
1049 flush_vsx_to_thread(src); 1049 flush_vsx_to_thread(src);
1050 flush_spe_to_thread(src); 1050 flush_spe_to_thread(src);
1051 /*
1052 * Flush TM state out so we can copy it. __switch_to_tm() does this
1053 * flush but it removes the checkpointed state from the current CPU and
1054 * transitions the CPU out of TM mode. Hence we need to call
1055 * tm_recheckpoint_new_task() (on the same task) to restore the
1056 * checkpointed state back and the TM mode.
1057 */
1058 __switch_to_tm(src);
1059 tm_recheckpoint_new_task(src);
1051 1060
1052 *dst = *src; 1061 *dst = *src;
1053 1062
diff --git a/arch/powerpc/kernel/reloc_64.S b/arch/powerpc/kernel/reloc_64.S
index 1482327cfeba..d88736fbece6 100644
--- a/arch/powerpc/kernel/reloc_64.S
+++ b/arch/powerpc/kernel/reloc_64.S
@@ -81,6 +81,7 @@ _GLOBAL(relocate)
81 81
826: blr 826: blr
83 83
84.balign 8
84p_dyn: .llong __dynamic_start - 0b 85p_dyn: .llong __dynamic_start - 0b
85p_rela: .llong __rela_dyn_start - 0b 86p_rela: .llong __rela_dyn_start - 0b
86p_st: .llong _stext - 0b 87p_st: .llong _stext - 0b
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index e66d4ec04d95..818dce344e82 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1504,73 +1504,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
15041: addi r8,r8,16 15041: addi r8,r8,16
1505 .endr 1505 .endr
1506 1506
1507 /* Save DEC */
1508 mfspr r5,SPRN_DEC
1509 mftb r6
1510 extsw r5,r5
1511 add r5,r5,r6
1512 std r5,VCPU_DEC_EXPIRES(r9)
1513
1514BEGIN_FTR_SECTION
1515 b 8f
1516END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1517 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
1518 mfmsr r8
1519 li r0, 1
1520 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1521 mtmsrd r8
1522
1523 /* Save POWER8-specific registers */
1524 mfspr r5, SPRN_IAMR
1525 mfspr r6, SPRN_PSPB
1526 mfspr r7, SPRN_FSCR
1527 std r5, VCPU_IAMR(r9)
1528 stw r6, VCPU_PSPB(r9)
1529 std r7, VCPU_FSCR(r9)
1530 mfspr r5, SPRN_IC
1531 mfspr r6, SPRN_VTB
1532 mfspr r7, SPRN_TAR
1533 std r5, VCPU_IC(r9)
1534 std r6, VCPU_VTB(r9)
1535 std r7, VCPU_TAR(r9)
1536#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1537 mfspr r5, SPRN_TFHAR
1538 mfspr r6, SPRN_TFIAR
1539 mfspr r7, SPRN_TEXASR
1540 std r5, VCPU_TFHAR(r9)
1541 std r6, VCPU_TFIAR(r9)
1542 std r7, VCPU_TEXASR(r9)
1543#endif
1544 mfspr r8, SPRN_EBBHR
1545 std r8, VCPU_EBBHR(r9)
1546 mfspr r5, SPRN_EBBRR
1547 mfspr r6, SPRN_BESCR
1548 mfspr r7, SPRN_CSIGR
1549 mfspr r8, SPRN_TACR
1550 std r5, VCPU_EBBRR(r9)
1551 std r6, VCPU_BESCR(r9)
1552 std r7, VCPU_CSIGR(r9)
1553 std r8, VCPU_TACR(r9)
1554 mfspr r5, SPRN_TCSCR
1555 mfspr r6, SPRN_ACOP
1556 mfspr r7, SPRN_PID
1557 mfspr r8, SPRN_WORT
1558 std r5, VCPU_TCSCR(r9)
1559 std r6, VCPU_ACOP(r9)
1560 stw r7, VCPU_GUEST_PID(r9)
1561 std r8, VCPU_WORT(r9)
15628:
1563
1564 /* Save and reset AMR and UAMOR before turning on the MMU */
1565BEGIN_FTR_SECTION
1566 mfspr r5,SPRN_AMR
1567 mfspr r6,SPRN_UAMOR
1568 std r5,VCPU_AMR(r9)
1569 std r6,VCPU_UAMOR(r9)
1570 li r6,0
1571 mtspr SPRN_AMR,r6
1572END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1573
1574 /* Unset guest mode */ 1507 /* Unset guest mode */
1575 li r0, KVM_GUEST_MODE_NONE 1508 li r0, KVM_GUEST_MODE_NONE
1576 stb r0, HSTATE_IN_GUEST(r13) 1509 stb r0, HSTATE_IN_GUEST(r13)
@@ -2203,7 +2136,7 @@ BEGIN_FTR_SECTION
2203END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 2136END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2204#endif 2137#endif
2205 mfspr r6,SPRN_VRSAVE 2138 mfspr r6,SPRN_VRSAVE
2206 stw r6,VCPU_VRSAVE(r3) 2139 stw r6,VCPU_VRSAVE(r31)
2207 mtlr r30 2140 mtlr r30
2208 mtmsrd r5 2141 mtmsrd r5
2209 isync 2142 isync
@@ -2240,7 +2173,7 @@ BEGIN_FTR_SECTION
2240 bl .load_vr_state 2173 bl .load_vr_state
2241END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 2174END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2242#endif 2175#endif
2243 lwz r7,VCPU_VRSAVE(r4) 2176 lwz r7,VCPU_VRSAVE(r31)
2244 mtspr SPRN_VRSAVE,r7 2177 mtspr SPRN_VRSAVE,r7
2245 mtlr r30 2178 mtlr r30
2246 mr r4,r31 2179 mr r4,r31
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index 5ec1e47a0d77..e865d748179b 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -123,7 +123,8 @@ static int __init cbe_ptcal_enable_on_node(int nid, int order)
123 123
124 area->nid = nid; 124 area->nid = nid;
125 area->order = order; 125 area->order = order;
126 area->pages = alloc_pages_exact_node(area->nid, GFP_KERNEL|GFP_THISNODE, 126 area->pages = alloc_pages_exact_node(area->nid,
127 GFP_KERNEL|__GFP_THISNODE,
127 area->order); 128 area->order);
128 129
129 if (!area->pages) { 130 if (!area->pages) {
diff --git a/arch/sh/include/cpu-sh2/cpu/cache.h b/arch/sh/include/cpu-sh2/cpu/cache.h
index 673515bc4135..aa1b2b9088a7 100644
--- a/arch/sh/include/cpu-sh2/cpu/cache.h
+++ b/arch/sh/include/cpu-sh2/cpu/cache.h
@@ -18,7 +18,7 @@
18#define SH_CACHE_ASSOC 8 18#define SH_CACHE_ASSOC 8
19 19
20#if defined(CONFIG_CPU_SUBTYPE_SH7619) 20#if defined(CONFIG_CPU_SUBTYPE_SH7619)
21#define CCR 0xffffffec 21#define SH_CCR 0xffffffec
22 22
23#define CCR_CACHE_CE 0x01 /* Cache enable */ 23#define CCR_CACHE_CE 0x01 /* Cache enable */
24#define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */ 24#define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */
diff --git a/arch/sh/include/cpu-sh2a/cpu/cache.h b/arch/sh/include/cpu-sh2a/cpu/cache.h
index defb0baa5a06..b27ce92cb600 100644
--- a/arch/sh/include/cpu-sh2a/cpu/cache.h
+++ b/arch/sh/include/cpu-sh2a/cpu/cache.h
@@ -17,8 +17,8 @@
17#define SH_CACHE_COMBINED 4 17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8 18#define SH_CACHE_ASSOC 8
19 19
20#define CCR 0xfffc1000 /* CCR1 */ 20#define SH_CCR 0xfffc1000 /* CCR1 */
21#define CCR2 0xfffc1004 21#define SH_CCR2 0xfffc1004
22 22
23/* 23/*
24 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not 24 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
diff --git a/arch/sh/include/cpu-sh3/cpu/cache.h b/arch/sh/include/cpu-sh3/cpu/cache.h
index bee2d81c56bf..29700fd88c75 100644
--- a/arch/sh/include/cpu-sh3/cpu/cache.h
+++ b/arch/sh/include/cpu-sh3/cpu/cache.h
@@ -17,7 +17,7 @@
17#define SH_CACHE_COMBINED 4 17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8 18#define SH_CACHE_ASSOC 8
19 19
20#define CCR 0xffffffec /* Address of Cache Control Register */ 20#define SH_CCR 0xffffffec /* Address of Cache Control Register */
21 21
22#define CCR_CACHE_CE 0x01 /* Cache Enable */ 22#define CCR_CACHE_CE 0x01 /* Cache Enable */
23#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ 23#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h
index 7bfb9e8b069c..92c4cd119b66 100644
--- a/arch/sh/include/cpu-sh4/cpu/cache.h
+++ b/arch/sh/include/cpu-sh4/cpu/cache.h
@@ -17,7 +17,7 @@
17#define SH_CACHE_COMBINED 4 17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8 18#define SH_CACHE_ASSOC 8
19 19
20#define CCR 0xff00001c /* Address of Cache Control Register */ 20#define SH_CCR 0xff00001c /* Address of Cache Control Register */
21#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ 21#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
22#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ 22#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
23#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ 23#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index ecf83cd158dc..0d7360d549c1 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -112,7 +112,7 @@ static void cache_init(void)
112 unsigned long ccr, flags; 112 unsigned long ccr, flags;
113 113
114 jump_to_uncached(); 114 jump_to_uncached();
115 ccr = __raw_readl(CCR); 115 ccr = __raw_readl(SH_CCR);
116 116
117 /* 117 /*
118 * At this point we don't know whether the cache is enabled or not - a 118 * At this point we don't know whether the cache is enabled or not - a
@@ -189,7 +189,7 @@ static void cache_init(void)
189 189
190 l2_cache_init(); 190 l2_cache_init();
191 191
192 __raw_writel(flags, CCR); 192 __raw_writel(flags, SH_CCR);
193 back_to_cached(); 193 back_to_cached();
194} 194}
195#else 195#else
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 115725198038..777e50f33c00 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -36,7 +36,7 @@ static int cache_seq_show(struct seq_file *file, void *iter)
36 */ 36 */
37 jump_to_uncached(); 37 jump_to_uncached();
38 38
39 ccr = __raw_readl(CCR); 39 ccr = __raw_readl(SH_CCR);
40 if ((ccr & CCR_CACHE_ENABLE) == 0) { 40 if ((ccr & CCR_CACHE_ENABLE) == 0) {
41 back_to_cached(); 41 back_to_cached();
42 42
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index defcf719f2e8..a74259f2f981 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -63,9 +63,9 @@ static void sh2__flush_invalidate_region(void *start, int size)
63 local_irq_save(flags); 63 local_irq_save(flags);
64 jump_to_uncached(); 64 jump_to_uncached();
65 65
66 ccr = __raw_readl(CCR); 66 ccr = __raw_readl(SH_CCR);
67 ccr |= CCR_CACHE_INVALIDATE; 67 ccr |= CCR_CACHE_INVALIDATE;
68 __raw_writel(ccr, CCR); 68 __raw_writel(ccr, SH_CCR);
69 69
70 back_to_cached(); 70 back_to_cached();
71 local_irq_restore(flags); 71 local_irq_restore(flags);
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 949e2d3138a0..ee87d081259b 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -134,7 +134,8 @@ static void sh2a__flush_invalidate_region(void *start, int size)
134 134
135 /* If there are too many pages then just blow the cache */ 135 /* If there are too many pages then just blow the cache */
136 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) { 136 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
137 __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR); 137 __raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
138 SH_CCR);
138 } else { 139 } else {
139 for (v = begin; v < end; v += L1_CACHE_BYTES) 140 for (v = begin; v < end; v += L1_CACHE_BYTES)
140 sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v); 141 sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
@@ -167,7 +168,8 @@ static void sh2a_flush_icache_range(void *args)
167 /* I-Cache invalidate */ 168 /* I-Cache invalidate */
168 /* If there are too many pages then just blow the cache */ 169 /* If there are too many pages then just blow the cache */
169 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { 170 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
170 __raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR); 171 __raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
172 SH_CCR);
171 } else { 173 } else {
172 for (v = start; v < end; v += L1_CACHE_BYTES) 174 for (v = start; v < end; v += L1_CACHE_BYTES)
173 sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v); 175 sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 0e529285b28d..51d8f7f31d1d 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -133,9 +133,9 @@ static void flush_icache_all(void)
133 jump_to_uncached(); 133 jump_to_uncached();
134 134
135 /* Flush I-cache */ 135 /* Flush I-cache */
136 ccr = __raw_readl(CCR); 136 ccr = __raw_readl(SH_CCR);
137 ccr |= CCR_CACHE_ICI; 137 ccr |= CCR_CACHE_ICI;
138 __raw_writel(ccr, CCR); 138 __raw_writel(ccr, SH_CCR);
139 139
140 /* 140 /*
141 * back_to_cached() will take care of the barrier for us, don't add 141 * back_to_cached() will take care of the barrier for us, don't add
diff --git a/arch/sh/mm/cache-shx3.c b/arch/sh/mm/cache-shx3.c
index c0adbee97b5f..24c58b7dc022 100644
--- a/arch/sh/mm/cache-shx3.c
+++ b/arch/sh/mm/cache-shx3.c
@@ -19,7 +19,7 @@ void __init shx3_cache_init(void)
19{ 19{
20 unsigned int ccr; 20 unsigned int ccr;
21 21
22 ccr = __raw_readl(CCR); 22 ccr = __raw_readl(SH_CCR);
23 23
24 /* 24 /*
25 * If we've got cache aliases, resolve them in hardware. 25 * If we've got cache aliases, resolve them in hardware.
@@ -40,5 +40,5 @@ void __init shx3_cache_init(void)
40 ccr |= CCR_CACHE_IBE; 40 ccr |= CCR_CACHE_IBE;
41#endif 41#endif
42 42
43 writel_uncached(ccr, CCR); 43 writel_uncached(ccr, SH_CCR);
44} 44}
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 616966a96cba..097c2cdd117f 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -285,8 +285,8 @@ void __init cpu_cache_init(void)
285{ 285{
286 unsigned int cache_disabled = 0; 286 unsigned int cache_disabled = 0;
287 287
288#ifdef CCR 288#ifdef SH_CCR
289 cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE); 289 cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
290#endif 290#endif
291 291
292 compute_alias(&boot_cpu_data.icache); 292 compute_alias(&boot_cpu_data.icache);
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index 32a280ec38c1..d7b4967f8fa6 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -58,9 +58,12 @@ void arch_cpu_idle(void)
58{ 58{
59 if (tlb_type != hypervisor) { 59 if (tlb_type != hypervisor) {
60 touch_nmi_watchdog(); 60 touch_nmi_watchdog();
61 local_irq_enable();
61 } else { 62 } else {
62 unsigned long pstate; 63 unsigned long pstate;
63 64
65 local_irq_enable();
66
64 /* The sun4v sleeping code requires that we have PSTATE.IE cleared over 67 /* The sun4v sleeping code requires that we have PSTATE.IE cleared over
65 * the cpu sleep hypervisor call. 68 * the cpu sleep hypervisor call.
66 */ 69 */
@@ -82,7 +85,6 @@ void arch_cpu_idle(void)
82 : "=&r" (pstate) 85 : "=&r" (pstate)
83 : "i" (PSTATE_IE)); 86 : "i" (PSTATE_IE));
84 } 87 }
85 local_irq_enable();
86} 88}
87 89
88#ifdef CONFIG_HOTPLUG_CPU 90#ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/sparc/kernel/syscalls.S b/arch/sparc/kernel/syscalls.S
index 87729fff13b9..33a17e7b3ccd 100644
--- a/arch/sparc/kernel/syscalls.S
+++ b/arch/sparc/kernel/syscalls.S
@@ -189,7 +189,8 @@ linux_sparc_syscall32:
189 mov %i0, %l5 ! IEU1 189 mov %i0, %l5 ! IEU1
1905: call %l7 ! CTI Group brk forced 1905: call %l7 ! CTI Group brk forced
191 srl %i5, 0, %o5 ! IEU1 191 srl %i5, 0, %o5 ! IEU1
192 ba,a,pt %xcc, 3f 192 ba,pt %xcc, 3f
193 sra %o0, 0, %o0
193 194
194 /* Linux native system calls enter here... */ 195 /* Linux native system calls enter here... */
195 .align 32 196 .align 32
@@ -217,7 +218,6 @@ linux_sparc_syscall:
2173: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] 2183: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
218ret_sys_call: 219ret_sys_call:
219 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3 220 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
220 sra %o0, 0, %o0
221 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2 221 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
222 sllx %g2, 32, %g2 222 sllx %g2, 32, %g2
223 223
diff --git a/arch/sparc/mm/tsb.c b/arch/sparc/mm/tsb.c
index 3b3a360b429a..f5d506fdddad 100644
--- a/arch/sparc/mm/tsb.c
+++ b/arch/sparc/mm/tsb.c
@@ -273,7 +273,7 @@ void __init pgtable_cache_init(void)
273 prom_halt(); 273 prom_halt();
274 } 274 }
275 275
276 for (i = 0; i < 8; i++) { 276 for (i = 0; i < ARRAY_SIZE(tsb_cache_names); i++) {
277 unsigned long size = 8192 << i; 277 unsigned long size = 8192 << i;
278 const char *name = tsb_cache_names[i]; 278 const char *name = tsb_cache_names[i];
279 279
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index c026cca5602c..f3aaf231b4e5 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -341,10 +341,6 @@ config X86_USE_3DNOW
341 def_bool y 341 def_bool y
342 depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML 342 depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
343 343
344config X86_OOSTORE
345 def_bool y
346 depends on (MWINCHIP3D || MWINCHIPC6) && MTRR
347
348# 344#
349# P6_NOPs are a relatively minor optimization that require a family >= 345# P6_NOPs are a relatively minor optimization that require a family >=
350# 6 processor, except that it is broken on certain VIA chips. 346# 6 processor, except that it is broken on certain VIA chips.
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
index 04a48903b2eb..69bbb4845020 100644
--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -85,11 +85,7 @@
85#else 85#else
86# define smp_rmb() barrier() 86# define smp_rmb() barrier()
87#endif 87#endif
88#ifdef CONFIG_X86_OOSTORE 88#define smp_wmb() barrier()
89# define smp_wmb() wmb()
90#else
91# define smp_wmb() barrier()
92#endif
93#define smp_read_barrier_depends() read_barrier_depends() 89#define smp_read_barrier_depends() read_barrier_depends()
94#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) 90#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
95#else /* !SMP */ 91#else /* !SMP */
@@ -100,7 +96,7 @@
100#define set_mb(var, value) do { var = value; barrier(); } while (0) 96#define set_mb(var, value) do { var = value; barrier(); } while (0)
101#endif /* SMP */ 97#endif /* SMP */
102 98
103#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE) 99#if defined(CONFIG_X86_PPRO_FENCE)
104 100
105/* 101/*
106 * For either of these options x86 doesn't have a strong TSO memory 102 * For either of these options x86 doesn't have a strong TSO memory
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 3d6b9f81cc68..acd86c850414 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -134,6 +134,7 @@ extern void efi_setup_page_tables(void);
134extern void __init old_map_region(efi_memory_desc_t *md); 134extern void __init old_map_region(efi_memory_desc_t *md);
135extern void __init runtime_code_page_mkexec(void); 135extern void __init runtime_code_page_mkexec(void);
136extern void __init efi_runtime_mkexec(void); 136extern void __init efi_runtime_mkexec(void);
137extern void __init efi_apply_memmap_quirks(void);
137 138
138struct efi_setup_data { 139struct efi_setup_data {
139 u64 fw_vendor; 140 u64 fw_vendor;
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 34f69cb9350a..91d9c69a629e 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -237,7 +237,7 @@ memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
237 237
238static inline void flush_write_buffers(void) 238static inline void flush_write_buffers(void)
239{ 239{
240#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE) 240#if defined(CONFIG_X86_PPRO_FENCE)
241 asm volatile("lock; addl $0,0(%%esp)": : :"memory"); 241 asm volatile("lock; addl $0,0(%%esp)": : :"memory");
242#endif 242#endif
243} 243}
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index bf156ded74b5..0f62f5482d91 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -26,10 +26,9 @@
26# define LOCK_PTR_REG "D" 26# define LOCK_PTR_REG "D"
27#endif 27#endif
28 28
29#if defined(CONFIG_X86_32) && \ 29#if defined(CONFIG_X86_32) && (defined(CONFIG_X86_PPRO_FENCE))
30 (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
31/* 30/*
32 * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock 31 * On PPro SMP, we use a locked operation to unlock
33 * (PPro errata 66, 92) 32 * (PPro errata 66, 92)
34 */ 33 */
35# define UNLOCK_LOCK_PREFIX LOCK_PREFIX 34# define UNLOCK_LOCK_PREFIX LOCK_PREFIX
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index fd972a3e4cbb..9fa8aa051f54 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -18,7 +18,6 @@
18#include <linux/pci_ids.h> 18#include <linux/pci_ids.h>
19#include <linux/pci.h> 19#include <linux/pci.h>
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21#include <linux/ioport.h>
22#include <linux/suspend.h> 21#include <linux/suspend.h>
23#include <asm/e820.h> 22#include <asm/e820.h>
24#include <asm/io.h> 23#include <asm/io.h>
@@ -54,18 +53,6 @@ int fallback_aper_force __initdata;
54 53
55int fix_aperture __initdata = 1; 54int fix_aperture __initdata = 1;
56 55
57static struct resource gart_resource = {
58 .name = "GART",
59 .flags = IORESOURCE_MEM,
60};
61
62static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
63{
64 gart_resource.start = aper_base;
65 gart_resource.end = aper_base + aper_size - 1;
66 insert_resource(&iomem_resource, &gart_resource);
67}
68
69/* This code runs before the PCI subsystem is initialized, so just 56/* This code runs before the PCI subsystem is initialized, so just
70 access the northbridge directly. */ 57 access the northbridge directly. */
71 58
@@ -96,7 +83,6 @@ static u32 __init allocate_aperture(void)
96 memblock_reserve(addr, aper_size); 83 memblock_reserve(addr, aper_size);
97 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", 84 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
98 aper_size >> 10, addr); 85 aper_size >> 10, addr);
99 insert_aperture_resource((u32)addr, aper_size);
100 register_nosave_region(addr >> PAGE_SHIFT, 86 register_nosave_region(addr >> PAGE_SHIFT,
101 (addr+aper_size) >> PAGE_SHIFT); 87 (addr+aper_size) >> PAGE_SHIFT);
102 88
@@ -444,12 +430,8 @@ int __init gart_iommu_hole_init(void)
444 430
445out: 431out:
446 if (!fix && !fallback_aper_force) { 432 if (!fix && !fallback_aper_force) {
447 if (last_aper_base) { 433 if (last_aper_base)
448 unsigned long n = (32 * 1024 * 1024) << last_aper_order;
449
450 insert_aperture_resource((u32)last_aper_base, n);
451 return 1; 434 return 1;
452 }
453 return 0; 435 return 0;
454 } 436 }
455 437
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 8779edab684e..d8fba5c15fbd 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -8,236 +8,6 @@
8 8
9#include "cpu.h" 9#include "cpu.h"
10 10
11#ifdef CONFIG_X86_OOSTORE
12
13static u32 power2(u32 x)
14{
15 u32 s = 1;
16
17 while (s <= x)
18 s <<= 1;
19
20 return s >>= 1;
21}
22
23
24/*
25 * Set up an actual MCR
26 */
27static void centaur_mcr_insert(int reg, u32 base, u32 size, int key)
28{
29 u32 lo, hi;
30
31 hi = base & ~0xFFF;
32 lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
33 lo &= ~0xFFF; /* Remove the ctrl value bits */
34 lo |= key; /* Attribute we wish to set */
35 wrmsr(reg+MSR_IDT_MCR0, lo, hi);
36 mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
37}
38
39/*
40 * Figure what we can cover with MCR's
41 *
42 * Shortcut: We know you can't put 4Gig of RAM on a winchip
43 */
44static u32 ramtop(void)
45{
46 u32 clip = 0xFFFFFFFFUL;
47 u32 top = 0;
48 int i;
49
50 for (i = 0; i < e820.nr_map; i++) {
51 unsigned long start, end;
52
53 if (e820.map[i].addr > 0xFFFFFFFFUL)
54 continue;
55 /*
56 * Don't MCR over reserved space. Ignore the ISA hole
57 * we frob around that catastrophe already
58 */
59 if (e820.map[i].type == E820_RESERVED) {
60 if (e820.map[i].addr >= 0x100000UL &&
61 e820.map[i].addr < clip)
62 clip = e820.map[i].addr;
63 continue;
64 }
65 start = e820.map[i].addr;
66 end = e820.map[i].addr + e820.map[i].size;
67 if (start >= end)
68 continue;
69 if (end > top)
70 top = end;
71 }
72 /*
73 * Everything below 'top' should be RAM except for the ISA hole.
74 * Because of the limited MCR's we want to map NV/ACPI into our
75 * MCR range for gunk in RAM
76 *
77 * Clip might cause us to MCR insufficient RAM but that is an
78 * acceptable failure mode and should only bite obscure boxes with
79 * a VESA hole at 15Mb
80 *
81 * The second case Clip sometimes kicks in is when the EBDA is marked
82 * as reserved. Again we fail safe with reasonable results
83 */
84 if (top > clip)
85 top = clip;
86
87 return top;
88}
89
90/*
91 * Compute a set of MCR's to give maximum coverage
92 */
93static int centaur_mcr_compute(int nr, int key)
94{
95 u32 mem = ramtop();
96 u32 root = power2(mem);
97 u32 base = root;
98 u32 top = root;
99 u32 floor = 0;
100 int ct = 0;
101
102 while (ct < nr) {
103 u32 fspace = 0;
104 u32 high;
105 u32 low;
106
107 /*
108 * Find the largest block we will fill going upwards
109 */
110 high = power2(mem-top);
111
112 /*
113 * Find the largest block we will fill going downwards
114 */
115 low = base/2;
116
117 /*
118 * Don't fill below 1Mb going downwards as there
119 * is an ISA hole in the way.
120 */
121 if (base <= 1024*1024)
122 low = 0;
123
124 /*
125 * See how much space we could cover by filling below
126 * the ISA hole
127 */
128
129 if (floor == 0)
130 fspace = 512*1024;
131 else if (floor == 512*1024)
132 fspace = 128*1024;
133
134 /* And forget ROM space */
135
136 /*
137 * Now install the largest coverage we get
138 */
139 if (fspace > high && fspace > low) {
140 centaur_mcr_insert(ct, floor, fspace, key);
141 floor += fspace;
142 } else if (high > low) {
143 centaur_mcr_insert(ct, top, high, key);
144 top += high;
145 } else if (low > 0) {
146 base -= low;
147 centaur_mcr_insert(ct, base, low, key);
148 } else
149 break;
150 ct++;
151 }
152 /*
153 * We loaded ct values. We now need to set the mask. The caller
154 * must do this bit.
155 */
156 return ct;
157}
158
159static void centaur_create_optimal_mcr(void)
160{
161 int used;
162 int i;
163
164 /*
165 * Allocate up to 6 mcrs to mark as much of ram as possible
166 * as write combining and weak write ordered.
167 *
168 * To experiment with: Linux never uses stack operations for
169 * mmio spaces so we could globally enable stack operation wc
170 *
171 * Load the registers with type 31 - full write combining, all
172 * writes weakly ordered.
173 */
174 used = centaur_mcr_compute(6, 31);
175
176 /*
177 * Wipe unused MCRs
178 */
179 for (i = used; i < 8; i++)
180 wrmsr(MSR_IDT_MCR0+i, 0, 0);
181}
182
183static void winchip2_create_optimal_mcr(void)
184{
185 u32 lo, hi;
186 int used;
187 int i;
188
189 /*
190 * Allocate up to 6 mcrs to mark as much of ram as possible
191 * as write combining, weak store ordered.
192 *
193 * Load the registers with type 25
194 * 8 - weak write ordering
195 * 16 - weak read ordering
196 * 1 - write combining
197 */
198 used = centaur_mcr_compute(6, 25);
199
200 /*
201 * Mark the registers we are using.
202 */
203 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
204 for (i = 0; i < used; i++)
205 lo |= 1<<(9+i);
206 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
207
208 /*
209 * Wipe unused MCRs
210 */
211
212 for (i = used; i < 8; i++)
213 wrmsr(MSR_IDT_MCR0+i, 0, 0);
214}
215
216/*
217 * Handle the MCR key on the Winchip 2.
218 */
219static void winchip2_unprotect_mcr(void)
220{
221 u32 lo, hi;
222 u32 key;
223
224 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
225 lo &= ~0x1C0; /* blank bits 8-6 */
226 key = (lo>>17) & 7;
227 lo |= key<<6; /* replace with unlock key */
228 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
229}
230
231static void winchip2_protect_mcr(void)
232{
233 u32 lo, hi;
234
235 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
236 lo &= ~0x1C0; /* blank bits 8-6 */
237 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
238}
239#endif /* CONFIG_X86_OOSTORE */
240
241#define ACE_PRESENT (1 << 6) 11#define ACE_PRESENT (1 << 6)
242#define ACE_ENABLED (1 << 7) 12#define ACE_ENABLED (1 << 7)
243#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ 13#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
@@ -362,20 +132,6 @@ static void init_centaur(struct cpuinfo_x86 *c)
362 fcr_clr = DPDC; 132 fcr_clr = DPDC;
363 printk(KERN_NOTICE "Disabling bugged TSC.\n"); 133 printk(KERN_NOTICE "Disabling bugged TSC.\n");
364 clear_cpu_cap(c, X86_FEATURE_TSC); 134 clear_cpu_cap(c, X86_FEATURE_TSC);
365#ifdef CONFIG_X86_OOSTORE
366 centaur_create_optimal_mcr();
367 /*
368 * Enable:
369 * write combining on non-stack, non-string
370 * write combining on string, all types
371 * weak write ordering
372 *
373 * The C6 original lacks weak read order
374 *
375 * Note 0x120 is write only on Winchip 1
376 */
377 wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
378#endif
379 break; 135 break;
380 case 8: 136 case 8:
381 switch (c->x86_mask) { 137 switch (c->x86_mask) {
@@ -392,40 +148,12 @@ static void init_centaur(struct cpuinfo_x86 *c)
392 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 148 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
393 E2MMX|EAMD3D; 149 E2MMX|EAMD3D;
394 fcr_clr = DPDC; 150 fcr_clr = DPDC;
395#ifdef CONFIG_X86_OOSTORE
396 winchip2_unprotect_mcr();
397 winchip2_create_optimal_mcr();
398 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
399 /*
400 * Enable:
401 * write combining on non-stack, non-string
402 * write combining on string, all types
403 * weak write ordering
404 */
405 lo |= 31;
406 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
407 winchip2_protect_mcr();
408#endif
409 break; 151 break;
410 case 9: 152 case 9:
411 name = "3"; 153 name = "3";
412 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
413 E2MMX|EAMD3D; 155 E2MMX|EAMD3D;
414 fcr_clr = DPDC; 156 fcr_clr = DPDC;
415#ifdef CONFIG_X86_OOSTORE
416 winchip2_unprotect_mcr();
417 winchip2_create_optimal_mcr();
418 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
419 /*
420 * Enable:
421 * write combining on non-stack, non-string
422 * write combining on string, all types
423 * weak write ordering
424 */
425 lo |= 31;
426 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
427 winchip2_protect_mcr();
428#endif
429 break; 157 break;
430 default: 158 default:
431 name = "??"; 159 name = "??";
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index c88f7f4b03ee..047f540cf3f7 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -3334,6 +3334,8 @@ static int __init uncore_type_init(struct intel_uncore_type *type)
3334 if (!pmus) 3334 if (!pmus)
3335 return -ENOMEM; 3335 return -ENOMEM;
3336 3336
3337 type->pmus = pmus;
3338
3337 type->unconstrainted = (struct event_constraint) 3339 type->unconstrainted = (struct event_constraint)
3338 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1, 3340 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
3339 0, type->num_counters, 0, 0); 3341 0, type->num_counters, 0, 0);
@@ -3369,7 +3371,6 @@ static int __init uncore_type_init(struct intel_uncore_type *type)
3369 } 3371 }
3370 3372
3371 type->pmu_group = &uncore_pmu_attr_group; 3373 type->pmu_group = &uncore_pmu_attr_group;
3372 type->pmus = pmus;
3373 return 0; 3374 return 0;
3374fail: 3375fail:
3375 uncore_type_exit(type); 3376 uncore_type_exit(type);
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index 81ba27679f18..f36bd42d6f0c 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -544,6 +544,10 @@ ENDPROC(early_idt_handlers)
544 /* This is global to keep gas from relaxing the jumps */ 544 /* This is global to keep gas from relaxing the jumps */
545ENTRY(early_idt_handler) 545ENTRY(early_idt_handler)
546 cld 546 cld
547
548 cmpl $2,(%esp) # X86_TRAP_NMI
549 je is_nmi # Ignore NMI
550
547 cmpl $2,%ss:early_recursion_flag 551 cmpl $2,%ss:early_recursion_flag
548 je hlt_loop 552 je hlt_loop
549 incl %ss:early_recursion_flag 553 incl %ss:early_recursion_flag
@@ -594,8 +598,9 @@ ex_entry:
594 pop %edx 598 pop %edx
595 pop %ecx 599 pop %ecx
596 pop %eax 600 pop %eax
597 addl $8,%esp /* drop vector number and error code */
598 decl %ss:early_recursion_flag 601 decl %ss:early_recursion_flag
602is_nmi:
603 addl $8,%esp /* drop vector number and error code */
599 iret 604 iret
600ENDPROC(early_idt_handler) 605ENDPROC(early_idt_handler)
601 606
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index e1aabdb314c8..a468c0a65c42 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -343,6 +343,9 @@ early_idt_handlers:
343ENTRY(early_idt_handler) 343ENTRY(early_idt_handler)
344 cld 344 cld
345 345
346 cmpl $2,(%rsp) # X86_TRAP_NMI
347 je is_nmi # Ignore NMI
348
346 cmpl $2,early_recursion_flag(%rip) 349 cmpl $2,early_recursion_flag(%rip)
347 jz 1f 350 jz 1f
348 incl early_recursion_flag(%rip) 351 incl early_recursion_flag(%rip)
@@ -405,8 +408,9 @@ ENTRY(early_idt_handler)
405 popq %rdx 408 popq %rdx
406 popq %rcx 409 popq %rcx
407 popq %rax 410 popq %rax
408 addq $16,%rsp # drop vector number and error code
409 decl early_recursion_flag(%rip) 411 decl early_recursion_flag(%rip)
412is_nmi:
413 addq $16,%rsp # drop vector number and error code
410 INTERRUPT_RETURN 414 INTERRUPT_RETURN
411ENDPROC(early_idt_handler) 415ENDPROC(early_idt_handler)
412 416
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index e8368c6dd2a2..d5dd80814419 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -86,10 +86,19 @@ EXPORT_SYMBOL(__kernel_fpu_begin);
86 86
87void __kernel_fpu_end(void) 87void __kernel_fpu_end(void)
88{ 88{
89 if (use_eager_fpu()) 89 if (use_eager_fpu()) {
90 math_state_restore(); 90 /*
91 else 91 * For eager fpu, most the time, tsk_used_math() is true.
92 * Restore the user math as we are done with the kernel usage.
93 * At few instances during thread exit, signal handling etc,
94 * tsk_used_math() is false. Those few places will take proper
95 * actions, so we don't need to restore the math here.
96 */
97 if (likely(tsk_used_math(current)))
98 math_state_restore();
99 } else {
92 stts(); 100 stts();
101 }
93} 102}
94EXPORT_SYMBOL(__kernel_fpu_end); 103EXPORT_SYMBOL(__kernel_fpu_end);
95 104
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 7c6acd4b8995..ff898bbf579d 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -529,7 +529,7 @@ static void quirk_amd_nb_node(struct pci_dev *dev)
529 return; 529 return;
530 530
531 pci_read_config_dword(nb_ht, 0x60, &val); 531 pci_read_config_dword(nb_ht, 0x60, &val);
532 node = val & 7; 532 node = pcibus_to_node(dev->bus) | (val & 7);
533 /* 533 /*
534 * Some hardware may return an invalid node ID, 534 * Some hardware may return an invalid node ID,
535 * so check it first: 535 * so check it first:
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 06853e670354..ce72964b2f46 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1239,14 +1239,8 @@ void __init setup_arch(char **cmdline_p)
1239 register_refined_jiffies(CLOCK_TICK_RATE); 1239 register_refined_jiffies(CLOCK_TICK_RATE);
1240 1240
1241#ifdef CONFIG_EFI 1241#ifdef CONFIG_EFI
1242 /* Once setup is done above, unmap the EFI memory map on 1242 if (efi_enabled(EFI_BOOT))
1243 * mismatched firmware/kernel archtectures since there is no 1243 efi_apply_memmap_quirks();
1244 * support for runtime services.
1245 */
1246 if (efi_enabled(EFI_BOOT) && !efi_is_native()) {
1247 pr_info("efi: Setup done, disabling due to 32/64-bit mismatch\n");
1248 efi_unmap_memmap();
1249 }
1250#endif 1244#endif
1251} 1245}
1252 1246
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index e81df8fce027..2de1bc09a8d4 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -3002,10 +3002,8 @@ static int cr8_write_interception(struct vcpu_svm *svm)
3002 u8 cr8_prev = kvm_get_cr8(&svm->vcpu); 3002 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3003 /* instruction emulation calls kvm_set_cr8() */ 3003 /* instruction emulation calls kvm_set_cr8() */
3004 r = cr_interception(svm); 3004 r = cr_interception(svm);
3005 if (irqchip_in_kernel(svm->vcpu.kvm)) { 3005 if (irqchip_in_kernel(svm->vcpu.kvm))
3006 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3007 return r; 3006 return r;
3008 }
3009 if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) 3007 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3010 return r; 3008 return r;
3011 kvm_run->exit_reason = KVM_EXIT_SET_TPR; 3009 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
@@ -3567,6 +3565,8 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3567 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) 3565 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3568 return; 3566 return;
3569 3567
3568 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3569
3570 if (irr == -1) 3570 if (irr == -1)
3571 return; 3571 return;
3572 3572
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 6dea040cc3a1..a10c8c792161 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -1020,13 +1020,17 @@ static inline bool smap_violation(int error_code, struct pt_regs *regs)
1020 * This routine handles page faults. It determines the address, 1020 * This routine handles page faults. It determines the address,
1021 * and the problem, and then passes it off to one of the appropriate 1021 * and the problem, and then passes it off to one of the appropriate
1022 * routines. 1022 * routines.
1023 *
1024 * This function must have noinline because both callers
1025 * {,trace_}do_page_fault() have notrace on. Having this an actual function
1026 * guarantees there's a function trace entry.
1023 */ 1027 */
1024static void __kprobes 1028static void __kprobes noinline
1025__do_page_fault(struct pt_regs *regs, unsigned long error_code) 1029__do_page_fault(struct pt_regs *regs, unsigned long error_code,
1030 unsigned long address)
1026{ 1031{
1027 struct vm_area_struct *vma; 1032 struct vm_area_struct *vma;
1028 struct task_struct *tsk; 1033 struct task_struct *tsk;
1029 unsigned long address;
1030 struct mm_struct *mm; 1034 struct mm_struct *mm;
1031 int fault; 1035 int fault;
1032 unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; 1036 unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
@@ -1034,9 +1038,6 @@ __do_page_fault(struct pt_regs *regs, unsigned long error_code)
1034 tsk = current; 1038 tsk = current;
1035 mm = tsk->mm; 1039 mm = tsk->mm;
1036 1040
1037 /* Get the faulting address: */
1038 address = read_cr2();
1039
1040 /* 1041 /*
1041 * Detect and handle instructions that would cause a page fault for 1042 * Detect and handle instructions that would cause a page fault for
1042 * both a tracked kernel page and a userspace page. 1043 * both a tracked kernel page and a userspace page.
@@ -1248,32 +1249,50 @@ good_area:
1248 up_read(&mm->mmap_sem); 1249 up_read(&mm->mmap_sem);
1249} 1250}
1250 1251
1251dotraplinkage void __kprobes 1252dotraplinkage void __kprobes notrace
1252do_page_fault(struct pt_regs *regs, unsigned long error_code) 1253do_page_fault(struct pt_regs *regs, unsigned long error_code)
1253{ 1254{
1255 unsigned long address = read_cr2(); /* Get the faulting address */
1254 enum ctx_state prev_state; 1256 enum ctx_state prev_state;
1255 1257
1258 /*
1259 * We must have this function tagged with __kprobes, notrace and call
1260 * read_cr2() before calling anything else. To avoid calling any kind
1261 * of tracing machinery before we've observed the CR2 value.
1262 *
1263 * exception_{enter,exit}() contain all sorts of tracepoints.
1264 */
1265
1256 prev_state = exception_enter(); 1266 prev_state = exception_enter();
1257 __do_page_fault(regs, error_code); 1267 __do_page_fault(regs, error_code, address);
1258 exception_exit(prev_state); 1268 exception_exit(prev_state);
1259} 1269}
1260 1270
1261static void trace_page_fault_entries(struct pt_regs *regs, 1271#ifdef CONFIG_TRACING
1272static void trace_page_fault_entries(unsigned long address, struct pt_regs *regs,
1262 unsigned long error_code) 1273 unsigned long error_code)
1263{ 1274{
1264 if (user_mode(regs)) 1275 if (user_mode(regs))
1265 trace_page_fault_user(read_cr2(), regs, error_code); 1276 trace_page_fault_user(address, regs, error_code);
1266 else 1277 else
1267 trace_page_fault_kernel(read_cr2(), regs, error_code); 1278 trace_page_fault_kernel(address, regs, error_code);
1268} 1279}
1269 1280
1270dotraplinkage void __kprobes 1281dotraplinkage void __kprobes notrace
1271trace_do_page_fault(struct pt_regs *regs, unsigned long error_code) 1282trace_do_page_fault(struct pt_regs *regs, unsigned long error_code)
1272{ 1283{
1284 /*
1285 * The exception_enter and tracepoint processing could
1286 * trigger another page faults (user space callchain
1287 * reading) and destroy the original cr2 value, so read
1288 * the faulting address now.
1289 */
1290 unsigned long address = read_cr2();
1273 enum ctx_state prev_state; 1291 enum ctx_state prev_state;
1274 1292
1275 prev_state = exception_enter(); 1293 prev_state = exception_enter();
1276 trace_page_fault_entries(regs, error_code); 1294 trace_page_fault_entries(address, regs, error_code);
1277 __do_page_fault(regs, error_code); 1295 __do_page_fault(regs, error_code, address);
1278 exception_exit(prev_state); 1296 exception_exit(prev_state);
1279} 1297}
1298#endif /* CONFIG_TRACING */
diff --git a/arch/x86/net/bpf_jit.S b/arch/x86/net/bpf_jit.S
index 877b9a1b2152..01495755701b 100644
--- a/arch/x86/net/bpf_jit.S
+++ b/arch/x86/net/bpf_jit.S
@@ -140,7 +140,7 @@ bpf_slow_path_byte_msh:
140 push %r9; \ 140 push %r9; \
141 push SKBDATA; \ 141 push SKBDATA; \
142/* rsi already has offset */ \ 142/* rsi already has offset */ \
143 mov $SIZE,%ecx; /* size */ \ 143 mov $SIZE,%edx; /* size */ \
144 call bpf_internal_load_pointer_neg_helper; \ 144 call bpf_internal_load_pointer_neg_helper; \
145 test %rax,%rax; \ 145 test %rax,%rax; \
146 pop SKBDATA; \ 146 pop SKBDATA; \
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 1a201ac7cef8..b97acecf3fd9 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -52,6 +52,7 @@
52#include <asm/tlbflush.h> 52#include <asm/tlbflush.h>
53#include <asm/x86_init.h> 53#include <asm/x86_init.h>
54#include <asm/rtc.h> 54#include <asm/rtc.h>
55#include <asm/uv/uv.h>
55 56
56#define EFI_DEBUG 57#define EFI_DEBUG
57 58
@@ -1210,3 +1211,22 @@ static int __init parse_efi_cmdline(char *str)
1210 return 0; 1211 return 0;
1211} 1212}
1212early_param("efi", parse_efi_cmdline); 1213early_param("efi", parse_efi_cmdline);
1214
1215void __init efi_apply_memmap_quirks(void)
1216{
1217 /*
1218 * Once setup is done earlier, unmap the EFI memory map on mismatched
1219 * firmware/kernel architectures since there is no support for runtime
1220 * services.
1221 */
1222 if (!efi_is_native()) {
1223 pr_info("efi: Setup done, disabling due to 32/64-bit mismatch\n");
1224 efi_unmap_memmap();
1225 }
1226
1227 /*
1228 * UV doesn't support the new EFI pagetable mapping yet.
1229 */
1230 if (is_uv_system())
1231 set_bit(EFI_OLD_MEMMAP, &x86_efi_facility);
1232}
diff --git a/arch/x86/um/asm/barrier.h b/arch/x86/um/asm/barrier.h
index 7d01b8c56c00..cc04e67bfd05 100644
--- a/arch/x86/um/asm/barrier.h
+++ b/arch/x86/um/asm/barrier.h
@@ -40,11 +40,7 @@
40#define smp_rmb() barrier() 40#define smp_rmb() barrier()
41#endif /* CONFIG_X86_PPRO_FENCE */ 41#endif /* CONFIG_X86_PPRO_FENCE */
42 42
43#ifdef CONFIG_X86_OOSTORE
44#define smp_wmb() wmb()
45#else /* CONFIG_X86_OOSTORE */
46#define smp_wmb() barrier() 43#define smp_wmb() barrier()
47#endif /* CONFIG_X86_OOSTORE */
48 44
49#define smp_read_barrier_depends() read_barrier_depends() 45#define smp_read_barrier_depends() read_barrier_depends()
50#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) 46#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 03:49:02 -0500