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authorGabor Juhos <juhosg@openwrt.org>2013-02-04 05:56:53 -0500
committerJohn Crispin <blogic@openwrt.org>2013-02-16 19:25:35 -0500
commitad4ce92e919f7ad5561a2060deb58899de58b40c (patch)
treeafdb8e34ae87d800095b901b21b822b31b7578da /arch
parentfb167e891d5cc6386840dd092af2d461b38eb802 (diff)
MIPS: ath79: move global PCI defines into a common header
The constants will be used by a subsequent patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4907/ Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h24
-rw-r--r--arch/mips/pci/pci-ar71xx.c16
-rw-r--r--arch/mips/pci/pci-ar724x.c8
3 files changed, 24 insertions, 24 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 7d44b5d5f609..7c87bfe6e4ff 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -41,11 +41,35 @@
41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
42#define AR71XX_RESET_SIZE 0x100 42#define AR71XX_RESET_SIZE 0x100
43 43
44#define AR71XX_PCI_MEM_BASE 0x10000000
45#define AR71XX_PCI_MEM_SIZE 0x07000000
46
47#define AR71XX_PCI_WIN0_OFFS 0x10000000
48#define AR71XX_PCI_WIN1_OFFS 0x11000000
49#define AR71XX_PCI_WIN2_OFFS 0x12000000
50#define AR71XX_PCI_WIN3_OFFS 0x13000000
51#define AR71XX_PCI_WIN4_OFFS 0x14000000
52#define AR71XX_PCI_WIN5_OFFS 0x15000000
53#define AR71XX_PCI_WIN6_OFFS 0x16000000
54#define AR71XX_PCI_WIN7_OFFS 0x07000000
55
56#define AR71XX_PCI_CFG_BASE \
57 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
58#define AR71XX_PCI_CFG_SIZE 0x100
59
44#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 60#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
45#define AR7240_USB_CTRL_SIZE 0x100 61#define AR7240_USB_CTRL_SIZE 0x100
46#define AR7240_OHCI_BASE 0x1b000000 62#define AR7240_OHCI_BASE 0x1b000000
47#define AR7240_OHCI_SIZE 0x1000 63#define AR7240_OHCI_SIZE 0x1000
48 64
65#define AR724X_PCI_MEM_BASE 0x10000000
66#define AR724X_PCI_MEM_SIZE 0x04000000
67
68#define AR724X_PCI_CFG_BASE 0x14000000
69#define AR724X_PCI_CFG_SIZE 0x1000
70#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
71#define AR724X_PCI_CTRL_SIZE 0x100
72
49#define AR724X_EHCI_BASE 0x1b000000 73#define AR724X_EHCI_BASE 0x1b000000
50#define AR724X_EHCI_SIZE 0x1000 74#define AR724X_EHCI_SIZE 0x1000
51 75
diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c
index 0d8412fc5047..35ee23450d87 100644
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -25,22 +25,6 @@
25#include <asm/mach-ath79/ath79.h> 25#include <asm/mach-ath79/ath79.h>
26#include <asm/mach-ath79/pci.h> 26#include <asm/mach-ath79/pci.h>
27 27
28#define AR71XX_PCI_MEM_BASE 0x10000000
29#define AR71XX_PCI_MEM_SIZE 0x07000000
30
31#define AR71XX_PCI_WIN0_OFFS 0x10000000
32#define AR71XX_PCI_WIN1_OFFS 0x11000000
33#define AR71XX_PCI_WIN2_OFFS 0x12000000
34#define AR71XX_PCI_WIN3_OFFS 0x13000000
35#define AR71XX_PCI_WIN4_OFFS 0x14000000
36#define AR71XX_PCI_WIN5_OFFS 0x15000000
37#define AR71XX_PCI_WIN6_OFFS 0x16000000
38#define AR71XX_PCI_WIN7_OFFS 0x07000000
39
40#define AR71XX_PCI_CFG_BASE \
41 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
42#define AR71XX_PCI_CFG_SIZE 0x100
43
44#define AR71XX_PCI_REG_CRP_AD_CBE 0x00 28#define AR71XX_PCI_REG_CRP_AD_CBE 0x00
45#define AR71XX_PCI_REG_CRP_WRDATA 0x04 29#define AR71XX_PCI_REG_CRP_WRDATA 0x04
46#define AR71XX_PCI_REG_CRP_RDDATA 0x08 30#define AR71XX_PCI_REG_CRP_RDDATA 0x08
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index e7aca88ba0c0..b3f9d093c066 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -17,14 +17,6 @@
17#include <asm/mach-ath79/ar71xx_regs.h> 17#include <asm/mach-ath79/ar71xx_regs.h>
18#include <asm/mach-ath79/pci.h> 18#include <asm/mach-ath79/pci.h>
19 19
20#define AR724X_PCI_CFG_BASE 0x14000000
21#define AR724X_PCI_CFG_SIZE 0x1000
22#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
23#define AR724X_PCI_CTRL_SIZE 0x100
24
25#define AR724X_PCI_MEM_BASE 0x10000000
26#define AR724X_PCI_MEM_SIZE 0x04000000
27
28#define AR724X_PCI_REG_RESET 0x18 20#define AR724X_PCI_REG_RESET 0x18
29#define AR724X_PCI_REG_INT_STATUS 0x4c 21#define AR724X_PCI_REG_INT_STATUS 0x4c
30#define AR724X_PCI_REG_INT_MASK 0x50 22#define AR724X_PCI_REG_INT_MASK 0x50