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authorNicolas Ferre <nicolas.ferre@atmel.com>2014-09-15 12:15:56 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-09-22 08:42:38 -0400
commit7c661394c56c9fcd98734bb762fb4191e4ff0ecc (patch)
tree484554d98ac25d41dc8f237326d0bff039b4f1f5 /arch
parent726d32bf79ef4042004535c9af9c8ea543abe46f (diff)
ARM: at91: dt: add device tree file for SAMA5D4 SoC
Add SAMA5D4 SoC DT file. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi1240
1 files changed, 1240 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
new file mode 100644
index 000000000000..e0157b0f075c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -0,0 +1,1240 @@
1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This library is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/pinctrl/at91.h>
49#include <dt-bindings/interrupt-controller/irq.h>
50#include <dt-bindings/gpio/gpio.h>
51
52/ {
53 model = "Atmel SAMA5D4 family SoC";
54 compatible = "atmel,sama5d4";
55 interrupt-parent = <&aic>;
56
57 aliases {
58 serial0 = &usart3;
59 serial1 = &usart4;
60 serial2 = &usart2;
61 gpio0 = &pioA;
62 gpio1 = &pioB;
63 gpio2 = &pioC;
64 gpio4 = &pioE;
65 tcb0 = &tcb0;
66 tcb1 = &tcb1;
67 i2c2 = &i2c2;
68 };
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu@0 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a5";
76 reg = <0>;
77 next-level-cache = <&L2>;
78 };
79 };
80
81 memory {
82 reg = <0x20000000 0x20000000>;
83 };
84
85 clocks {
86 slow_xtal: slow_xtal {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <0>;
90 };
91
92 main_xtal: main_xtal {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <0>;
96 };
97
98 adc_op_clk: adc_op_clk{
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <1000000>;
102 };
103 };
104
105 ahb {
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 usb0: gadget@00400000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "atmel,at91sam9rl-udc";
115 reg = <0x00400000 0x100000
116 0xfc02c000 0x4000>;
117 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
118 clocks = <&udphs_clk>, <&utmi>;
119 clock-names = "pclk", "hclk";
120 status = "disabled";
121
122 ep0 {
123 reg = <0>;
124 atmel,fifo-size = <64>;
125 atmel,nb-banks = <1>;
126 };
127
128 ep1 {
129 reg = <1>;
130 atmel,fifo-size = <1024>;
131 atmel,nb-banks = <3>;
132 atmel,can-dma;
133 atmel,can-isoc;
134 };
135
136 ep2 {
137 reg = <2>;
138 atmel,fifo-size = <1024>;
139 atmel,nb-banks = <3>;
140 atmel,can-dma;
141 atmel,can-isoc;
142 };
143
144 ep3 {
145 reg = <3>;
146 atmel,fifo-size = <1024>;
147 atmel,nb-banks = <2>;
148 atmel,can-dma;
149 atmel,can-isoc;
150 };
151
152 ep4 {
153 reg = <4>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <2>;
156 atmel,can-dma;
157 atmel,can-isoc;
158 };
159
160 ep5 {
161 reg = <5>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <2>;
164 atmel,can-dma;
165 atmel,can-isoc;
166 };
167
168 ep6 {
169 reg = <6>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
172 atmel,can-dma;
173 atmel,can-isoc;
174 };
175
176 ep7 {
177 reg = <7>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
180 atmel,can-dma;
181 atmel,can-isoc;
182 };
183
184 ep8 {
185 reg = <8>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
188 atmel,can-isoc;
189 };
190
191 ep9 {
192 reg = <9>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
195 atmel,can-isoc;
196 };
197
198 ep10 {
199 reg = <10>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
202 atmel,can-isoc;
203 };
204
205 ep11 {
206 reg = <11>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
209 atmel,can-isoc;
210 };
211
212 ep12 {
213 reg = <12>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
216 atmel,can-isoc;
217 };
218
219 ep13 {
220 reg = <13>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
223 atmel,can-isoc;
224 };
225
226 ep14 {
227 reg = <14>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
230 atmel,can-isoc;
231 };
232
233 ep15 {
234 reg = <15>;
235 atmel,fifo-size = <1024>;
236 atmel,nb-banks = <2>;
237 atmel,can-isoc;
238 };
239 };
240
241 usb1: ohci@00500000 {
242 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
243 reg = <0x00500000 0x100000>;
244 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
245 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
246 <&uhpck>;
247 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
248 status = "disabled";
249 };
250
251 usb2: ehci@00600000 {
252 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
253 reg = <0x00600000 0x100000>;
254 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
255 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
256 clock-names = "usb_clk", "ehci_clk", "uhpck";
257 status = "disabled";
258 };
259
260 L2: cache-controller@00a00000 {
261 compatible = "arm,pl310-cache";
262 reg = <0x00a00000 0x1000>;
263 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
264 cache-unified;
265 cache-level = <2>;
266 };
267
268 nand0: nand@80000000 {
269 compatible = "atmel,at91rm9200-nand";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 ranges;
273 reg = < 0x80000000 0x08000000 /* EBI CS3 */
274 0xfc05c070 0x00000490 /* SMC PMECC regs */
275 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
276 >;
277 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
278 atmel,nand-addr-offset = <21>;
279 atmel,nand-cmd-offset = <22>;
280 atmel,nand-has-dma;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_nand>;
283 status = "disabled";
284
285 nfc@90000000 {
286 compatible = "atmel,sama5d3-nfc";
287 #address-cells = <1>;
288 #size-cells = <1>;
289 reg = <
290 0x90000000 0x10000000 /* NFC Command Registers */
291 0xfc05c000 0x00000070 /* NFC HSMC regs */
292 0x00100000 0x00100000 /* NFC SRAM banks */
293 >;
294 clocks = <&hsmc_clk>;
295 atmel,write-by-sram;
296 };
297 };
298
299 apb {
300 compatible = "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges;
304
305 ramc0: ramc@f0010000 {
306 compatible = "atmel,sama5d3-ddramc";
307 reg = <0xf0010000 0x200>;
308 clocks = <&ddrck>, <&mpddr_clk>;
309 clock-names = "ddrck", "mpddr";
310 };
311
312 pmc: pmc@f0018000 {
313 compatible = "atmel,sama5d3-pmc";
314 reg = <0xf0018000 0x120>;
315 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
316 interrupt-controller;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 #interrupt-cells = <1>;
320
321 main_rc_osc: main_rc_osc {
322 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
323 #clock-cells = <0>;
324 interrupt-parent = <&pmc>;
325 interrupts = <AT91_PMC_MOSCRCS>;
326 clock-frequency = <12000000>;
327 clock-accuracy = <100000000>;
328 };
329
330 main_osc: main_osc {
331 compatible = "atmel,at91rm9200-clk-main-osc";
332 #clock-cells = <0>;
333 interrupt-parent = <&pmc>;
334 interrupts = <AT91_PMC_MOSCS>;
335 clocks = <&main_xtal>;
336 };
337
338 main: mainck {
339 compatible = "atmel,at91sam9x5-clk-main";
340 #clock-cells = <0>;
341 interrupt-parent = <&pmc>;
342 interrupts = <AT91_PMC_MOSCSELS>;
343 clocks = <&main_rc_osc &main_osc>;
344 };
345
346 plla: pllack {
347 compatible = "atmel,sama5d3-clk-pll";
348 #clock-cells = <0>;
349 interrupt-parent = <&pmc>;
350 interrupts = <AT91_PMC_LOCKA>;
351 clocks = <&main>;
352 reg = <0>;
353 atmel,clk-input-range = <12000000 12000000>;
354 #atmel,pll-clk-output-range-cells = <4>;
355 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
356 };
357
358 plladiv: plladivck {
359 compatible = "atmel,at91sam9x5-clk-plldiv";
360 #clock-cells = <0>;
361 clocks = <&plla>;
362 };
363
364 utmi: utmick {
365 compatible = "atmel,at91sam9x5-clk-utmi";
366 #clock-cells = <0>;
367 interrupt-parent = <&pmc>;
368 interrupts = <AT91_PMC_LOCKU>;
369 clocks = <&main>;
370 };
371
372 mck: masterck {
373 compatible = "atmel,at91sam9x5-clk-master";
374 #clock-cells = <0>;
375 interrupt-parent = <&pmc>;
376 interrupts = <AT91_PMC_MCKRDY>;
377 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
378 atmel,clk-output-range = <125000000 177000000>;
379 atmel,clk-divisors = <1 2 4 3>;
380 };
381
382 h32ck: h32mxck {
383 #clock-cells = <0>;
384 compatible = "atmel,sama5d4-clk-h32mx";
385 clocks = <&mck>;
386 };
387
388 usb: usbck {
389 compatible = "atmel,at91sam9x5-clk-usb";
390 #clock-cells = <0>;
391 clocks = <&plladiv>, <&utmi>;
392 };
393
394 prog: progck {
395 compatible = "atmel,at91sam9x5-clk-programmable";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 interrupt-parent = <&pmc>;
399 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
400
401 prog0: prog0 {
402 #clock-cells = <0>;
403 reg = <0>;
404 interrupts = <AT91_PMC_PCKRDY(0)>;
405 };
406
407 prog1: prog1 {
408 #clock-cells = <0>;
409 reg = <1>;
410 interrupts = <AT91_PMC_PCKRDY(1)>;
411 };
412
413 prog2: prog2 {
414 #clock-cells = <0>;
415 reg = <2>;
416 interrupts = <AT91_PMC_PCKRDY(2)>;
417 };
418 };
419
420 smd: smdclk {
421 compatible = "atmel,at91sam9x5-clk-smd";
422 #clock-cells = <0>;
423 clocks = <&plladiv>, <&utmi>;
424 };
425
426 systemck {
427 compatible = "atmel,at91rm9200-clk-system";
428 #address-cells = <1>;
429 #size-cells = <0>;
430
431 ddrck: ddrck {
432 #clock-cells = <0>;
433 reg = <2>;
434 clocks = <&mck>;
435 };
436
437 lcdck: lcdck {
438 #clock-cells = <0>;
439 reg = <4>;
440 clocks = <&smd>;
441 };
442
443 smdck: smdck {
444 #clock-cells = <0>;
445 reg = <4>;
446 clocks = <&smd>;
447 };
448
449 uhpck: uhpck {
450 #clock-cells = <0>;
451 reg = <6>;
452 clocks = <&usb>;
453 };
454
455 udpck: udpck {
456 #clock-cells = <0>;
457 reg = <7>;
458 clocks = <&usb>;
459 };
460
461 pck0: pck0 {
462 #clock-cells = <0>;
463 reg = <8>;
464 clocks = <&prog0>;
465 };
466
467 pck1: pck1 {
468 #clock-cells = <0>;
469 reg = <9>;
470 clocks = <&prog1>;
471 };
472
473 pck2: pck2 {
474 #clock-cells = <0>;
475 reg = <10>;
476 clocks = <&prog2>;
477 };
478 };
479
480 periph32ck {
481 compatible = "atmel,at91sam9x5-clk-peripheral";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clocks = <&h32ck>;
485
486 pioD_clk: pioD_clk {
487 #clock-cells = <0>;
488 reg = <5>;
489 };
490
491 usart0_clk: usart0_clk {
492 #clock-cells = <0>;
493 reg = <6>;
494 };
495
496 usart1_clk: usart1_clk {
497 #clock-cells = <0>;
498 reg = <7>;
499 };
500
501 icm_clk: icm_clk {
502 #clock-cells = <0>;
503 reg = <9>;
504 };
505
506 aes_clk: aes_clk {
507 #clock-cells = <0>;
508 reg = <12>;
509 };
510
511 tdes_clk: tdes_clk {
512 #clock-cells = <0>;
513 reg = <14>;
514 };
515
516 sha_clk: sha_clk {
517 #clock-cells = <0>;
518 reg = <15>;
519 };
520
521 matrix1_clk: matrix1_clk {
522 #clock-cells = <0>;
523 reg = <17>;
524 };
525
526 hsmc_clk: hsmc_clk {
527 #clock-cells = <0>;
528 reg = <22>;
529 };
530
531 pioA_clk: pioA_clk {
532 #clock-cells = <0>;
533 reg = <23>;
534 };
535
536 pioB_clk: pioB_clk {
537 #clock-cells = <0>;
538 reg = <24>;
539 };
540
541 pioC_clk: pioC_clk {
542 #clock-cells = <0>;
543 reg = <25>;
544 };
545
546 pioE_clk: pioE_clk {
547 #clock-cells = <0>;
548 reg = <26>;
549 };
550
551 uart0_clk: uart0_clk {
552 #clock-cells = <0>;
553 reg = <27>;
554 };
555
556 uart1_clk: uart1_clk {
557 #clock-cells = <0>;
558 reg = <28>;
559 };
560
561 usart2_clk: usart2_clk {
562 #clock-cells = <0>;
563 reg = <29>;
564 };
565
566 usart3_clk: usart3_clk {
567 #clock-cells = <0>;
568 reg = <30>;
569 };
570
571 usart4_clk: usart4_clk {
572 #clock-cells = <0>;
573 reg = <31>;
574 };
575
576 twi0_clk: twi0_clk {
577 reg = <32>;
578 #clock-cells = <0>;
579 };
580
581 twi1_clk: twi1_clk {
582 #clock-cells = <0>;
583 reg = <33>;
584 };
585
586 twi2_clk: twi2_clk {
587 #clock-cells = <0>;
588 reg = <34>;
589 };
590
591 mci0_clk: mci0_clk {
592 #clock-cells = <0>;
593 reg = <35>;
594 };
595
596 mci1_clk: mci1_clk {
597 #clock-cells = <0>;
598 reg = <36>;
599 };
600
601 spi0_clk: spi0_clk {
602 #clock-cells = <0>;
603 reg = <37>;
604 };
605
606 spi1_clk: spi1_clk {
607 #clock-cells = <0>;
608 reg = <38>;
609 };
610
611 spi2_clk: spi2_clk {
612 #clock-cells = <0>;
613 reg = <39>;
614 };
615
616 tcb0_clk: tcb0_clk {
617 #clock-cells = <0>;
618 reg = <40>;
619 };
620
621 tcb1_clk: tcb1_clk {
622 #clock-cells = <0>;
623 reg = <41>;
624 };
625
626 tcb2_clk: tcb2_clk {
627 #clock-cells = <0>;
628 reg = <42>;
629 };
630
631 pwm_clk: pwm_clk {
632 #clock-cells = <0>;
633 reg = <43>;
634 };
635
636 adc_clk: adc_clk {
637 #clock-cells = <0>;
638 reg = <44>;
639 };
640
641 dbgu_clk: dbgu_clk {
642 #clock-cells = <0>;
643 reg = <45>;
644 };
645
646 uhphs_clk: uhphs_clk {
647 #clock-cells = <0>;
648 reg = <46>;
649 };
650
651 udphs_clk: udphs_clk {
652 #clock-cells = <0>;
653 reg = <47>;
654 };
655
656 ssc0_clk: ssc0_clk {
657 #clock-cells = <0>;
658 reg = <48>;
659 };
660
661 ssc1_clk: ssc1_clk {
662 #clock-cells = <0>;
663 reg = <49>;
664 };
665
666 trng_clk: trng_clk {
667 #clock-cells = <0>;
668 reg = <53>;
669 };
670
671 macb0_clk: macb0_clk {
672 #clock-cells = <0>;
673 reg = <54>;
674 };
675
676 macb1_clk: macb1_clk {
677 #clock-cells = <0>;
678 reg = <55>;
679 };
680
681 fuse_clk: fuse_clk {
682 #clock-cells = <0>;
683 reg = <57>;
684 };
685
686 securam_clk: securam_clk {
687 #clock-cells = <0>;
688 reg = <59>;
689 };
690
691 smd_clk: smd_clk {
692 #clock-cells = <0>;
693 reg = <61>;
694 };
695
696 twi3_clk: twi3_clk {
697 #clock-cells = <0>;
698 reg = <62>;
699 };
700
701 catb_clk: catb_clk {
702 #clock-cells = <0>;
703 reg = <63>;
704 };
705 };
706
707 periph64ck {
708 compatible = "atmel,at91sam9x5-clk-peripheral";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 clocks = <&mck>;
712
713 dma0_clk: dma0_clk {
714 #clock-cells = <0>;
715 reg = <8>;
716 };
717
718 cpkcc_clk: cpkcc_clk {
719 #clock-cells = <0>;
720 reg = <10>;
721 };
722
723 aesb_clk: aesb_clk {
724 #clock-cells = <0>;
725 reg = <13>;
726 };
727
728 mpddr_clk: mpddr_clk {
729 #clock-cells = <0>;
730 reg = <16>;
731 };
732
733 matrix0_clk: matrix0_clk {
734 #clock-cells = <0>;
735 reg = <18>;
736 };
737
738 vdec_clk: vdec_clk {
739 #clock-cells = <0>;
740 reg = <19>;
741 };
742
743 dma1_clk: dma1_clk {
744 #clock-cells = <0>;
745 reg = <50>;
746 };
747
748 lcd_clk: lcd_clk {
749 #clock-cells = <0>;
750 reg = <51>;
751 };
752
753 isi_clk: isi_clk {
754 #clock-cells = <0>;
755 reg = <52>;
756 };
757 };
758 };
759
760 mmc0: mmc@f8000000 {
761 compatible = "atmel,hsmci";
762 reg = <0xf8000000 0x600>;
763 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
766 status = "disabled";
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&mci0_clk>;
770 clock-names = "mci_clk";
771 };
772
773 spi0: spi@f8010000 {
774 #address-cells = <1>;
775 #size-cells = <0>;
776 compatible = "atmel,at91rm9200-spi";
777 reg = <0xf8010000 0x100>;
778 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&pinctrl_spi0>;
781 clocks = <&spi0_clk>;
782 clock-names = "spi_clk";
783 status = "disabled";
784 };
785
786 i2c0: i2c@f8014000 {
787 compatible = "atmel,at91sam9x5-i2c";
788 reg = <0xf8014000 0x4000>;
789 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&pinctrl_i2c0>;
792 #address-cells = <1>;
793 #size-cells = <0>;
794 clocks = <&twi0_clk>;
795 status = "disabled";
796 };
797
798 tcb0: timer@f801c000 {
799 compatible = "atmel,at91sam9x5-tcb";
800 reg = <0xf801c000 0x100>;
801 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
802 clocks = <&tcb0_clk>;
803 clock-names = "t0_clk";
804 };
805
806 macb0: ethernet@f8020000 {
807 compatible = "atmel,sama5d4-gem";
808 reg = <0xf8020000 0x100>;
809 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_macb0_rmii>;
812 clocks = <&macb0_clk>, <&macb0_clk>;
813 clock-names = "hclk", "pclk";
814 status = "disabled";
815 };
816
817 i2c2: i2c@f8024000 {
818 compatible = "atmel,at91sam9x5-i2c";
819 reg = <0xf8024000 0x4000>;
820 interrupts = <34 4 6>;
821 pinctrl-names = "default";
822 pinctrl-0 = <&pinctrl_i2c2>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&twi2_clk>;
826 status = "disabled";
827 };
828
829 mmc1: mmc@fc000000 {
830 compatible = "atmel,hsmci";
831 reg = <0xfc000000 0x600>;
832 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
835 status = "disabled";
836 #address-cells = <1>;
837 #size-cells = <0>;
838 clocks = <&mci1_clk>;
839 clock-names = "mci_clk";
840 };
841
842 usart2: serial@fc008000 {
843 compatible = "atmel,at91sam9260-usart";
844 reg = <0xfc008000 0x100>;
845 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
848 clocks = <&usart2_clk>;
849 clock-names = "usart";
850 status = "disabled";
851 };
852
853 usart3: serial@fc00c000 {
854 compatible = "atmel,at91sam9260-usart";
855 reg = <0xfc00c000 0x100>;
856 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&pinctrl_usart3>;
859 clocks = <&usart3_clk>;
860 clock-names = "usart";
861 status = "disabled";
862 };
863
864 usart4: serial@fc010000 {
865 compatible = "atmel,at91sam9260-usart";
866 reg = <0xfc010000 0x100>;
867 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&pinctrl_usart4>;
870 clocks = <&usart4_clk>;
871 clock-names = "usart";
872 status = "disabled";
873 };
874
875 tcb1: timer@fc020000 {
876 compatible = "atmel,at91sam9x5-tcb";
877 reg = <0xfc020000 0x100>;
878 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&tcb1_clk>;
880 clock-names = "t0_clk";
881 };
882
883 adc0: adc@fc034000 {
884 compatible = "atmel,at91sam9x5-adc";
885 reg = <0xfc034000 0x100>;
886 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
887 pinctrl-names = "default";
888 pinctrl-0 = <
889 /* external trigger is conflict with USBA_VBUS */
890 &pinctrl_adc0_ad0
891 &pinctrl_adc0_ad1
892 &pinctrl_adc0_ad2
893 &pinctrl_adc0_ad3
894 &pinctrl_adc0_ad4
895 >;
896 clocks = <&adc_clk>,
897 <&adc_op_clk>;
898 clock-names = "adc_clk", "adc_op_clk";
899 atmel,adc-channels-used = <0x01f>;
900 atmel,adc-startup-time = <40>;
901 atmel,adc-use-external;
902 atmel,adc-vref = <3000>;
903 atmel,adc-res = <8 10>;
904 atmel,adc-sample-hold-time = <11>;
905 atmel,adc-res-names = "lowres", "highres";
906 atmel,adc-ts-pressure-threshold = <10000>;
907 status = "disabled";
908
909 trigger@0 {
910 trigger-name = "external-rising";
911 trigger-value = <0x1>;
912 trigger-external;
913 };
914 trigger@1 {
915 trigger-name = "external-falling";
916 trigger-value = <0x2>;
917 trigger-external;
918 };
919 trigger@2 {
920 trigger-name = "external-any";
921 trigger-value = <0x3>;
922 trigger-external;
923 };
924 trigger@3 {
925 trigger-name = "continuous";
926 trigger-value = <0x6>;
927 };
928 };
929
930 rstc@fc068600 {
931 compatible = "atmel,at91sam9g45-rstc";
932 reg = <0xfc068600 0x10>;
933 };
934
935 shdwc@fc068610 {
936 compatible = "atmel,at91sam9x5-shdwc";
937 reg = <0xfc068610 0x10>;
938 };
939
940 pit: timer@fc068630 {
941 compatible = "atmel,at91sam9260-pit";
942 reg = <0xfc068630 0xf>;
943 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
944 clocks = <&h32ck>;
945 };
946
947 watchdog@fc068640 {
948 compatible = "atmel,at91sam9260-wdt";
949 reg = <0xfc068640 0x10>;
950 status = "disabled";
951 };
952
953 sckc@fc068650 {
954 compatible = "atmel,at91sam9x5-sckc";
955 reg = <0xfc068650 0x4>;
956
957 slow_rc_osc: slow_rc_osc {
958 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
959 #clock-cells = <0>;
960 clock-frequency = <32768>;
961 clock-accuracy = <250000000>;
962 atmel,startup-time-usec = <75>;
963 };
964
965 slow_osc: slow_osc {
966 compatible = "atmel,at91sam9x5-clk-slow-osc";
967 #clock-cells = <0>;
968 clocks = <&slow_xtal>;
969 atmel,startup-time-usec = <1200000>;
970 };
971
972 clk32k: slowck {
973 compatible = "atmel,at91sam9x5-clk-slow";
974 #clock-cells = <0>;
975 clocks = <&slow_rc_osc &slow_osc>;
976 };
977 };
978
979 rtc@fc0686b0 {
980 compatible = "atmel,at91rm9200-rtc";
981 reg = <0xfc0686b0 0x30>;
982 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
983 };
984
985 dbgu: serial@fc069000 {
986 compatible = "atmel,at91sam9260-usart";
987 reg = <0xfc069000 0x200>;
988 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&pinctrl_dbgu>;
991 clocks = <&dbgu_clk>;
992 clock-names = "usart";
993 status = "disabled";
994 };
995
996
997 pinctrl@fc06a000 {
998 #address-cells = <1>;
999 #size-cells = <1>;
1000 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1001 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1002 /* WARNING: revisit as pin spec has changed */
1003 atmel,mux-mask = <
1004 /* A B C */
1005 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1006 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1007 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1008 0x00000000 0x00000000 0x00000000 /* pioD */
1009 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1010 >;
1011
1012 pioA: gpio@fc06a000 {
1013 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1014 reg = <0xfc06a000 0x100>;
1015 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1016 #gpio-cells = <2>;
1017 gpio-controller;
1018 interrupt-controller;
1019 #interrupt-cells = <2>;
1020 clocks = <&pioA_clk>;
1021 };
1022
1023 pioB: gpio@fc06b000 {
1024 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1025 reg = <0xfc06b000 0x100>;
1026 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1027 #gpio-cells = <2>;
1028 gpio-controller;
1029 interrupt-controller;
1030 #interrupt-cells = <2>;
1031 clocks = <&pioB_clk>;
1032 };
1033
1034 pioC: gpio@fc06c000 {
1035 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1036 reg = <0xfc06c000 0x100>;
1037 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1038 #gpio-cells = <2>;
1039 gpio-controller;
1040 interrupt-controller;
1041 #interrupt-cells = <2>;
1042 clocks = <&pioC_clk>;
1043 };
1044
1045 pioE: gpio@fc06d000 {
1046 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1047 reg = <0xfc06d000 0x100>;
1048 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1049 #gpio-cells = <2>;
1050 gpio-controller;
1051 interrupt-controller;
1052 #interrupt-cells = <2>;
1053 clocks = <&pioE_clk>;
1054 };
1055
1056 /* pinctrl pin settings */
1057 adc0 {
1058 pinctrl_adc0_adtrg: adc0_adtrg {
1059 atmel,pins =
1060 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1061 };
1062 pinctrl_adc0_ad0: adc0_ad0 {
1063 atmel,pins =
1064 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1065 };
1066 pinctrl_adc0_ad1: adc0_ad1 {
1067 atmel,pins =
1068 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1069 };
1070 pinctrl_adc0_ad2: adc0_ad2 {
1071 atmel,pins =
1072 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1073 };
1074 pinctrl_adc0_ad3: adc0_ad3 {
1075 atmel,pins =
1076 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1077 };
1078 pinctrl_adc0_ad4: adc0_ad4 {
1079 atmel,pins =
1080 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1081 };
1082 };
1083
1084 dbgu {
1085 pinctrl_dbgu: dbgu-0 {
1086 atmel,pins =
1087 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1088 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1089 };
1090 };
1091
1092 i2c0 {
1093 pinctrl_i2c0: i2c0-0 {
1094 atmel,pins =
1095 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1096 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1097 };
1098 };
1099
1100 i2c2 {
1101 pinctrl_i2c2: i2c2-0 {
1102 atmel,pins =
1103 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1104 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1105 };
1106 };
1107
1108 macb0 {
1109 pinctrl_macb0_rmii: macb0_rmii-0 {
1110 atmel,pins =
1111 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1112 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1113 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1114 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1115 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1116 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1117 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1118 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1119 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1120 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1121 >;
1122 };
1123 };
1124
1125 mmc0 {
1126 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1127 atmel,pins =
1128 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1129 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1130 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1131 >;
1132 };
1133 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1134 atmel,pins =
1135 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1136 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1137 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1138 >;
1139 };
1140 };
1141
1142 mmc1 {
1143 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1144 atmel,pins =
1145 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1146 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1147 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1148 >;
1149 };
1150 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1151 atmel,pins =
1152 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1153 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1154 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1155 >;
1156 };
1157 };
1158
1159 nand0 {
1160 pinctrl_nand: nand-0 {
1161 atmel,pins =
1162 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1163 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1164
1165 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1166 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1167
1168 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1169 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1170 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1171 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1172 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1173 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1174 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1175 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1176 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1177 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1178 };
1179 };
1180
1181 spi0 {
1182 pinctrl_spi0: spi0-0 {
1183 atmel,pins =
1184 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1185 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1186 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1187 >;
1188 };
1189 };
1190
1191 usart2 {
1192 pinctrl_usart2: usart2-0 {
1193 atmel,pins =
1194 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1195 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1196 >;
1197 };
1198 pinctrl_usart2_rts: usart2_rts-0 {
1199 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1200 };
1201 pinctrl_usart2_cts: usart2_cts-0 {
1202 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1203 };
1204 };
1205
1206 usart3 {
1207 pinctrl_usart3: usart3-0 {
1208 atmel,pins =
1209 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1210 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1211 >;
1212 };
1213 };
1214
1215 usart4 {
1216 pinctrl_usart4: usart4-0 {
1217 atmel,pins =
1218 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1219 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1220 >;
1221 };
1222 pinctrl_usart4_rts: usart4_rts-0 {
1223 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1224 };
1225 pinctrl_usart4_cts: usart4_cts-0 {
1226 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1227 };
1228 };
1229 };
1230
1231 aic: interrupt-controller@fc06e000 {
1232 #interrupt-cells = <3>;
1233 compatible = "atmel,sama5d4-aic";
1234 interrupt-controller;
1235 reg = <0xfc06e000 0x200>;
1236 atmel,external-irqs = <56>;
1237 };
1238 };
1239 };
1240};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 17:48:24 -0500