aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorJayachandran C <jchandra@broadcom.com>2012-10-31 08:01:36 -0400
committerJohn Crispin <blogic@openwrt.org>2012-11-09 05:37:19 -0500
commit7143246e9ace7f6b50aad217289dd64b7a44dd2c (patch)
treee520ce0957d5aab7f9f056f73da323f23d1bc73a /arch
parentfeddaf7d89d554b705e7eb14a9202c4946e57c8e (diff)
MIPS: Netlogic: Update PIC access functions
Remove unused and trivial PIC accesss functions, update nlm_pic_send_ipi() and nlm_set_irt_to_cpu() to use similar logic, and use correct type for reg in nlm_pic_disable_irt(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4463 Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h40
1 files changed, 7 insertions, 33 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 49ee15c19771..061e0710607a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -273,36 +273,16 @@ nlm_pic_read_irt(uint64_t base, int irt_index)
273 return nlm_read_pic_reg(base, PIC_IRT(irt_index)); 273 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
274} 274}
275 275
276static inline uint64_t
277nlm_pic_read_control(uint64_t base)
278{
279 return nlm_read_pic_reg(base, PIC_CTRL);
280}
281
282static inline void
283nlm_pic_write_control(uint64_t base, uint64_t control)
284{
285 nlm_write_pic_reg(base, PIC_CTRL, control);
286}
287
288static inline void
289nlm_pic_update_control(uint64_t base, uint64_t control)
290{
291 uint64_t val;
292
293 val = nlm_read_pic_reg(base, PIC_CTRL);
294 nlm_write_pic_reg(base, PIC_CTRL, control | val);
295}
296
297static inline void 276static inline void
298nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 277nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
299{ 278{
300 uint64_t val; 279 uint64_t val;
301 280
302 val = nlm_read_pic_reg(base, PIC_IRT(irt)); 281 val = nlm_read_pic_reg(base, PIC_IRT(irt));
303 val |= cpu & 0xf; 282 /* clear cpuset and mask */
304 if (cpu > 15) 283 val &= ~((0x7ull << 16) | 0xffff);
305 val |= 1 << 16; 284 /* set DB, cpuset and cpumask */
285 val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
306 nlm_write_pic_reg(base, PIC_IRT(irt), val); 286 nlm_write_pic_reg(base, PIC_IRT(irt), val);
307} 287}
308 288
@@ -369,7 +349,7 @@ nlm_pic_enable_irt(uint64_t base, int irt)
369static inline void 349static inline void
370nlm_pic_disable_irt(uint64_t base, int irt) 350nlm_pic_disable_irt(uint64_t base, int irt)
371{ 351{
372 uint32_t reg; 352 uint64_t reg;
373 353
374 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 354 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
375 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); 355 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
@@ -379,15 +359,9 @@ static inline void
379nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) 359nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
380{ 360{
381 uint64_t ipi; 361 uint64_t ipi;
382 int node, ncpu;
383
384 node = hwt / 32;
385 ncpu = hwt & 0x1f;
386 ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
387 (1 << (ncpu & 0xf));
388 if (ncpu > 15)
389 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
390 362
363 ipi = (nmi << 31) | (irq << 20);
364 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
391 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 365 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
392} 366}
393 367