arm64: Remove asm/pgtable-*level-hwdef.h files

The macros in these files can easily be computed based on PAGE_SHIFT and VA_BITS, so just remove them and add the corresponding macros to asm/pgtable-hwdef.h Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
author: Catalin Marinas <catalin.marinas@arm.com> 2014-07-15 11:35:38 -0400
committer: Catalin Marinas <catalin.marinas@arm.com> 2014-07-23 10:27:51 -0400
commit: 6b4fee241dd7c4b11cae4432bfa899a386d71f26 (patch)
tree: 6f49796ecbc00a9a25bd53b1885eeecd1dd6e730 /arch
parent: abe669d7e1a8f9163eb7e8e153e7257d38c1ba3e (diff)
4 files changed, 36 insertions, 149 deletions
diff --git a/arch/arm64/include/asm/pgtable-2level-hwdef.h b/arch/arm64/include/asm/pgtable-2level-hwdef.h
deleted file mode 100644
index 2593b490c56a..000000000000
--- a/arch/arm64/include/asm/pgtable-2level-hwdef.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __ASM_PGTABLE_2LEVEL_HWDEF_H
-#define __ASM_PGTABLE_2LEVEL_HWDEF_H
-/*
- * With LPAE and 64KB pages, there are 2 levels of page tables. Each level has
- * 8192 entries of 8 bytes each, occupying a 64KB page. Levels 0 and 1 are not
- * used. The 2nd level table (PGD for Linux) can cover a range of 4TB, each
- * entry representing 512MB. The user and kernel address spaces are limited to
- * 4TB in the 64KB page configuration.
- */
-#define PTRS_PER_PTE            8192
-#define PTRS_PER_PGD            8192
-/*
- * PGDIR_SHIFT determines the size a top-level page table entry can map.
- */
-#define PGDIR_SHIFT             29
-#define PGDIR_SIZE              (_AC(1, UL) << PGDIR_SHIFT)
-#define PGDIR_MASK              (~(PGDIR_SIZE-1))
-/*
- * section address mask and size definitions.
- */
-#define SECTION_SHIFT           29
-#define SECTION_SIZE            (_AC(1, UL) << SECTION_SHIFT)
-#define SECTION_MASK            (~(SECTION_SIZE-1))
-#endif
diff --git a/arch/arm64/include/asm/pgtable-3level-hwdef.h b/arch/arm64/include/asm/pgtable-3level-hwdef.h
deleted file mode 100644
index 3dbf941d7767..000000000000
--- a/arch/arm64/include/asm/pgtable-3level-hwdef.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __ASM_PGTABLE_3LEVEL_HWDEF_H
-#define __ASM_PGTABLE_3LEVEL_HWDEF_H
-/*
- * With LPAE and 4KB pages, there are 3 levels of page tables. Each level has
- * 512 entries of 8 bytes each, occupying a 4K page. The first level table
- * covers a range of 512GB, each entry representing 1GB. The user and kernel
- * address spaces are limited to 512GB each.
- */
-#define PTRS_PER_PTE            512
-#define PTRS_PER_PMD            512
-#define PTRS_PER_PGD            512
-/*
- * PGDIR_SHIFT determines the size a top-level page table entry can map.
- */
-#define PGDIR_SHIFT             30
-#define PGDIR_SIZE              (_AC(1, UL) << PGDIR_SHIFT)
-#define PGDIR_MASK              (~(PGDIR_SIZE-1))
-/*
- * PMD_SHIFT determines the size a middle-level page table entry can map.
- */
-#define PMD_SHIFT               21
-#define PMD_SIZE                (_AC(1, UL) << PMD_SHIFT)
-#define PMD_MASK                (~(PMD_SIZE-1))
-/*
- * section address mask and size definitions.
- */
-#define SECTION_SHIFT           21
-#define SECTION_SIZE            (_AC(1, UL) << SECTION_SHIFT)
-#define SECTION_MASK            (~(SECTION_SIZE-1))
-#endif
diff --git a/arch/arm64/include/asm/pgtable-4level-hwdef.h b/arch/arm64/include/asm/pgtable-4level-hwdef.h
deleted file mode 100644
index 0ec84e2274a3..000000000000
--- a/arch/arm64/include/asm/pgtable-4level-hwdef.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __ASM_PGTABLE_4LEVEL_HWDEF_H
-#define __ASM_PGTABLE_4LEVEL_HWDEF_H
-#define PTRS_PER_PTE            512
-#define PTRS_PER_PMD            512
-#define PTRS_PER_PUD            512
-#define PTRS_PER_PGD            512
-/*
- * PGDIR_SHIFT determines the size a top-level page table entry can map.
- */
-#define PGDIR_SHIFT             39
-#define PGDIR_SIZE              (_AC(1, UL) << PGDIR_SHIFT)
-#define PGDIR_MASK              (~(PGDIR_SIZE-1))
-/*
- * PUD_SHIFT determines the size the second level page table entry can map.
- */
-#define PUD_SHIFT               30
-#define PUD_SIZE                (_AC(1, UL) << PUD_SHIFT)
-#define PUD_MASK                (~(PUD_SIZE-1))
-/*
- * PMD_SHIFT determines the size the third level page table entry can map.
- */
-#define PMD_SHIFT               21
-#define PMD_SIZE                (_AC(1, UL) << PMD_SHIFT)
-#define PMD_MASK                (~(PMD_SIZE-1))
-/*
- * section address mask and size definitions.
- */
-#define SECTION_SHIFT           21
-#define SECTION_SIZE            (_AC(1, UL) << SECTION_SHIFT)
-#define SECTION_MASK            (~(SECTION_SIZE-1))
-#endif
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index d453e8bfef06..88174e0bfafe 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -16,15 +16,45 @@
 #ifndef __ASM_PGTABLE_HWDEF_H
 #define __ASM_PGTABLE_HWDEF_H
-#if CONFIG_ARM64_PGTABLE_LEVELS == 2
+#define PTRS_PER_PTE            (1 << (PAGE_SHIFT - 3))
-#include <asm/pgtable-2level-hwdef.h>
-#elif CONFIG_ARM64_PGTABLE_LEVELS == 3
+/*
-#include <asm/pgtable-3level-hwdef.h>
+ * PMD_SHIFT determines the size a level 2 page table entry can map.
-#else
+ */
-#include <asm/pgtable-4level-hwdef.h>
+#if CONFIG_ARM64_PGTABLE_LEVELS > 2
+#define PMD_SHIFT               ((PAGE_SHIFT - 3) * 2 + 3)
+#define PMD_SIZE                (_AC(1, UL) << PMD_SHIFT)
+#define PMD_MASK                (~(PMD_SIZE-1))
+#define PTRS_PER_PMD            PTRS_PER_PTE
+#endif
+/*
+ * PUD_SHIFT determines the size a level 1 page table entry can map.
+ */
+#if CONFIG_ARM64_PGTABLE_LEVELS > 3
+#define PUD_SHIFT               ((PAGE_SHIFT - 3) * 3 + 3)
+#define PUD_SIZE                (_AC(1, UL) << PUD_SHIFT)
+#define PUD_MASK                (~(PUD_SIZE-1))
+#define PTRS_PER_PUD            PTRS_PER_PTE
 #endif
 /*
+ * PGDIR_SHIFT determines the size a top-level page table entry can map
+ * (depending on the configuration, this level can be 0, 1 or 2).
+ */
+#define PGDIR_SHIFT             ((PAGE_SHIFT - 3) * CONFIG_ARM64_PGTABLE_LEVELS + 3)
+#define PGDIR_SIZE              (_AC(1, UL) << PGDIR_SHIFT)
+#define PGDIR_MASK              (~(PGDIR_SIZE-1))
+#define PTRS_PER_PGD            (1 << (VA_BITS - PGDIR_SHIFT))
+/*
+ * Section address mask and size definitions.
+ */
+#define SECTION_SHIFT           PMD_SHIFT
+#define SECTION_SIZE            (_AC(1, UL) << SECTION_SHIFT)
+#define SECTION_MASK            (~(SECTION_SIZE-1))
+/*
 * Hardware page table definitions.
 *
 * Level 1 descriptor (PUD).
author	Catalin Marinas <catalin.marinas@arm.com>	2014-07-15 11:35:38 -0400
committer	Catalin Marinas <catalin.marinas@arm.com>	2014-07-23 10:27:51 -0400
commit	6b4fee241dd7c4b11cae4432bfa899a386d71f26 (patch)
tree	6f49796ecbc00a9a25bd53b1885eeecd1dd6e730 /arch
parent	abe669d7e1a8f9163eb7e8e153e7257d38c1ba3e (diff)

diff --git a/arch/arm64/include/asm/pgtable-2level-hwdef.h b/arch/arm64/include/asm/pgtable-2level-hwdef.h deleted file mode 100644 index 2593b490c56a..000000000000 --- a/arch/arm64/include/asm/pgtable-2level-hwdef.h +++ /dev/null
@@ -1,43 +0,0 @@
1	/*
2	* Copyright (C) 2012 ARM Ltd.
3	*
4	* This program is free software; you can redistribute it and/or modify
5	* it under the terms of the GNU General Public License version 2 as
6	* published by the Free Software Foundation.
7	*
8	* This program is distributed in the hope that it will be useful,
9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11	* GNU General Public License for more details.
12	*
13	* You should have received a copy of the GNU General Public License
14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
15	*/
16	#ifndef __ASM_PGTABLE_2LEVEL_HWDEF_H
17	#define __ASM_PGTABLE_2LEVEL_HWDEF_H
18
19	/*
20	* With LPAE and 64KB pages, there are 2 levels of page tables. Each level has
21	* 8192 entries of 8 bytes each, occupying a 64KB page. Levels 0 and 1 are not
22	* used. The 2nd level table (PGD for Linux) can cover a range of 4TB, each
23	* entry representing 512MB. The user and kernel address spaces are limited to
24	* 4TB in the 64KB page configuration.
25	*/
26	#define PTRS_PER_PTE 8192
27	#define PTRS_PER_PGD 8192
28
29	/*
30	* PGDIR_SHIFT determines the size a top-level page table entry can map.
31	*/
32	#define PGDIR_SHIFT 29
33	#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
34	#define PGDIR_MASK (~(PGDIR_SIZE-1))
35
36	/*
37	* section address mask and size definitions.
38	*/
39	#define SECTION_SHIFT 29
40	#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
41	#define SECTION_MASK (~(SECTION_SIZE-1))
42
43	#endif


diff --git a/arch/arm64/include/asm/pgtable-3level-hwdef.h b/arch/arm64/include/asm/pgtable-3level-hwdef.h deleted file mode 100644 index 3dbf941d7767..000000000000 --- a/arch/arm64/include/asm/pgtable-3level-hwdef.h +++ /dev/null
@@ -1,50 +0,0 @@
1	/*
2	* Copyright (C) 2012 ARM Ltd.
3	*
4	* This program is free software; you can redistribute it and/or modify
5	* it under the terms of the GNU General Public License version 2 as
6	* published by the Free Software Foundation.
7	*
8	* This program is distributed in the hope that it will be useful,
9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11	* GNU General Public License for more details.
12	*
13	* You should have received a copy of the GNU General Public License
14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
15	*/
16	#ifndef __ASM_PGTABLE_3LEVEL_HWDEF_H
17	#define __ASM_PGTABLE_3LEVEL_HWDEF_H
18
19	/*
20	* With LPAE and 4KB pages, there are 3 levels of page tables. Each level has
21	* 512 entries of 8 bytes each, occupying a 4K page. The first level table
22	* covers a range of 512GB, each entry representing 1GB. The user and kernel
23	* address spaces are limited to 512GB each.
24	*/
25	#define PTRS_PER_PTE 512
26	#define PTRS_PER_PMD 512
27	#define PTRS_PER_PGD 512
28
29	/*
30	* PGDIR_SHIFT determines the size a top-level page table entry can map.
31	*/
32	#define PGDIR_SHIFT 30
33	#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
34	#define PGDIR_MASK (~(PGDIR_SIZE-1))
35
36	/*
37	* PMD_SHIFT determines the size a middle-level page table entry can map.
38	*/
39	#define PMD_SHIFT 21
40	#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
41	#define PMD_MASK (~(PMD_SIZE-1))
42
43	/*
44	* section address mask and size definitions.
45	*/
46	#define SECTION_SHIFT 21
47	#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
48	#define SECTION_MASK (~(SECTION_SIZE-1))
49
50	#endif


diff --git a/arch/arm64/include/asm/pgtable-4level-hwdef.h b/arch/arm64/include/asm/pgtable-4level-hwdef.h deleted file mode 100644 index 0ec84e2274a3..000000000000 --- a/arch/arm64/include/asm/pgtable-4level-hwdef.h +++ /dev/null
@@ -1,50 +0,0 @@
1	/*
2	* This program is free software; you can redistribute it and/or modify
3	* it under the terms of the GNU General Public License version 2 as
4	* published by the Free Software Foundation.
5	*
6	* This program is distributed in the hope that it will be useful,
7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9	* GNU General Public License for more details.
10	*
11	* You should have received a copy of the GNU General Public License
12	* along with this program. If not, see <http://www.gnu.org/licenses/>.
13	*/
14	#ifndef __ASM_PGTABLE_4LEVEL_HWDEF_H
15	#define __ASM_PGTABLE_4LEVEL_HWDEF_H
16
17	#define PTRS_PER_PTE 512
18	#define PTRS_PER_PMD 512
19	#define PTRS_PER_PUD 512
20	#define PTRS_PER_PGD 512
21
22	/*
23	* PGDIR_SHIFT determines the size a top-level page table entry can map.
24	*/
25	#define PGDIR_SHIFT 39
26	#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
27	#define PGDIR_MASK (~(PGDIR_SIZE-1))
28
29	/*
30	* PUD_SHIFT determines the size the second level page table entry can map.
31	*/
32	#define PUD_SHIFT 30
33	#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
34	#define PUD_MASK (~(PUD_SIZE-1))
35
36	/*
37	* PMD_SHIFT determines the size the third level page table entry can map.
38	*/
39	#define PMD_SHIFT 21
40	#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
41	#define PMD_MASK (~(PMD_SIZE-1))
42
43	/*
44	* section address mask and size definitions.
45	*/
46	#define SECTION_SHIFT 21
47	#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
48	#define SECTION_MASK (~(SECTION_SIZE-1))
49
50	#endif


diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index d453e8bfef06..88174e0bfafe 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -16,15 +16,45 @@
16	#ifndef __ASM_PGTABLE_HWDEF_H	16	#ifndef __ASM_PGTABLE_HWDEF_H
17	#define __ASM_PGTABLE_HWDEF_H	17	#define __ASM_PGTABLE_HWDEF_H
18		18
19	#if CONFIG_ARM64_PGTABLE_LEVELS == 2	19	#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
20	#include <asm/pgtable-2level-hwdef.h>	20
21	#elif CONFIG_ARM64_PGTABLE_LEVELS == 3	21	/*
22	#include <asm/pgtable-3level-hwdef.h>	22	* PMD_SHIFT determines the size a level 2 page table entry can map.
23	#else	23	*/
24	#include <asm/pgtable-4level-hwdef.h>	24	#if CONFIG_ARM64_PGTABLE_LEVELS > 2
		25	#define PMD_SHIFT ((PAGE_SHIFT - 3) * 2 + 3)
		26	#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
		27	#define PMD_MASK (~(PMD_SIZE-1))
		28	#define PTRS_PER_PMD PTRS_PER_PTE
		29	#endif
		30
		31	/*
		32	* PUD_SHIFT determines the size a level 1 page table entry can map.
		33	*/
		34	#if CONFIG_ARM64_PGTABLE_LEVELS > 3
		35	#define PUD_SHIFT ((PAGE_SHIFT - 3) * 3 + 3)
		36	#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
		37	#define PUD_MASK (~(PUD_SIZE-1))
		38	#define PTRS_PER_PUD PTRS_PER_PTE
25	#endif	39	#endif
26		40
27	/*	41	/*
		42	* PGDIR_SHIFT determines the size a top-level page table entry can map
		43	* (depending on the configuration, this level can be 0, 1 or 2).
		44	*/
		45	#define PGDIR_SHIFT ((PAGE_SHIFT - 3) * CONFIG_ARM64_PGTABLE_LEVELS + 3)
		46	#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
		47	#define PGDIR_MASK (~(PGDIR_SIZE-1))
		48	#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
		49
		50	/*
		51	* Section address mask and size definitions.
		52	*/
		53	#define SECTION_SHIFT PMD_SHIFT
		54	#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
		55	#define SECTION_MASK (~(SECTION_SIZE-1))
		56
		57	/*
28	* Hardware page table definitions.	58	* Hardware page table definitions.
29	*	59	*
30	* Level 1 descriptor (PUD).	60	* Level 1 descriptor (PUD).