diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-26 20:41:04 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-26 20:41:04 -0400 |
commit | 69f1d1a6acbaa7d83ef3f4ee26209c58cd000204 (patch) | |
tree | 12be981f8a123b8361edd64b84fd72f339a9655d /arch | |
parent | 2d86a3f04e345b03d5e429bfe14985ce26bff4dc (diff) | |
parent | 1e09939bad24df95ddeeeca4fbec64fa94b66def (diff) |
Merge branch 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits)
ARM: S5P64X0: External Interrupt Support
ARM: EXYNOS4: Enable MFC on Samsung NURI
ARM: EXYNOS4: Enable MFC on universal_c210
ARM: S5PV210: Enable MFC on Goni
ARM: S5P: Add support for MFC device
ARM: EXYNOS4: Add support FIMD on SMDKC210
ARM: EXYNOS4: Add platform device and helper functions for FIMD
ARM: EXYNOS4: Add resource definition for FIMD
ARM: EXYNOS4: Change devname for FIMD clkdev
ARM: SAMSUNG: Add IRQ_I2S0 definition
ARM: SAMSUNG: Add platform device for idma
ARM: EXYNOS4: Add more registers to be saved and restored for PM
ARM: EXYNOS4: Add more register addresses of CMU
ARM: EXYNOS4: Add platform device for dwmci driver
ARM: EXYNOS4: configure rtc-s3c on NURI
ARM: EXYNOS4: configure MAX8903 secondary charger on NURI
ARM: EXYNOS4: configure ADC on NURI
ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI
ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI
ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs
...
Fix up tons of silly conflicts:
- arch/arm/mach-davinci/include/mach/psc.h
- arch/arm/mach-exynos4/Kconfig
- arch/arm/mach-exynos4/mach-smdkc210.c
- arch/arm/mach-exynos4/pm.c
- arch/arm/mach-imx/mm-imx1.c
- arch/arm/mach-imx/mm-imx21.c
- arch/arm/mach-imx/mm-imx25.c
- arch/arm/mach-imx/mm-imx27.c
- arch/arm/mach-imx/mm-imx31.c
- arch/arm/mach-imx/mm-imx35.c
- arch/arm/mach-mx5/mm.c
- arch/arm/mach-s5pv210/mach-goni.c
- arch/arm/mm/Kconfig
Diffstat (limited to 'arch')
213 files changed, 4527 insertions, 1156 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5cdee4bc181d..09ebf0ba64fa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -328,7 +328,7 @@ config ARCH_CLPS711X | |||
328 | 328 | ||
329 | config ARCH_CNS3XXX | 329 | config ARCH_CNS3XXX |
330 | bool "Cavium Networks CNS3XXX family" | 330 | bool "Cavium Networks CNS3XXX family" |
331 | select CPU_V6 | 331 | select CPU_V6K |
332 | select GENERIC_CLOCKEVENTS | 332 | select GENERIC_CLOCKEVENTS |
333 | select ARM_GIC | 333 | select ARM_GIC |
334 | select MIGHT_HAVE_PCI | 334 | select MIGHT_HAVE_PCI |
@@ -396,6 +396,7 @@ config ARCH_MXC | |||
396 | select ARCH_REQUIRE_GPIOLIB | 396 | select ARCH_REQUIRE_GPIOLIB |
397 | select CLKDEV_LOOKUP | 397 | select CLKDEV_LOOKUP |
398 | select CLKSRC_MMIO | 398 | select CLKSRC_MMIO |
399 | select GENERIC_IRQ_CHIP | ||
399 | select HAVE_SCHED_CLOCK | 400 | select HAVE_SCHED_CLOCK |
400 | help | 401 | help |
401 | Support for Freescale MXC/iMX-based family of processors | 402 | Support for Freescale MXC/iMX-based family of processors |
@@ -603,7 +604,6 @@ config ARCH_TEGRA | |||
603 | select GENERIC_GPIO | 604 | select GENERIC_GPIO |
604 | select HAVE_CLK | 605 | select HAVE_CLK |
605 | select HAVE_SCHED_CLOCK | 606 | select HAVE_SCHED_CLOCK |
606 | select ARCH_HAS_BARRIERS if CACHE_L2X0 | ||
607 | select ARCH_HAS_CPUFREQ | 607 | select ARCH_HAS_CPUFREQ |
608 | help | 608 | help |
609 | This enables support for NVIDIA Tegra based systems (Tegra APX, | 609 | This enables support for NVIDIA Tegra based systems (Tegra APX, |
@@ -630,6 +630,8 @@ config ARCH_PXA | |||
630 | select TICK_ONESHOT | 630 | select TICK_ONESHOT |
631 | select PLAT_PXA | 631 | select PLAT_PXA |
632 | select SPARSE_IRQ | 632 | select SPARSE_IRQ |
633 | select AUTO_ZRELADDR | ||
634 | select MULTI_IRQ_HANDLER | ||
633 | help | 635 | help |
634 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | 636 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
635 | 637 | ||
@@ -768,6 +770,7 @@ config ARCH_S5PV210 | |||
768 | bool "Samsung S5PV210/S5PC110" | 770 | bool "Samsung S5PV210/S5PC110" |
769 | select CPU_V7 | 771 | select CPU_V7 |
770 | select ARCH_SPARSEMEM_ENABLE | 772 | select ARCH_SPARSEMEM_ENABLE |
773 | select ARCH_HAS_HOLES_MEMORYMODEL | ||
771 | select GENERIC_GPIO | 774 | select GENERIC_GPIO |
772 | select HAVE_CLK | 775 | select HAVE_CLK |
773 | select CLKDEV_LOOKUP | 776 | select CLKDEV_LOOKUP |
@@ -786,6 +789,7 @@ config ARCH_EXYNOS4 | |||
786 | bool "Samsung EXYNOS4" | 789 | bool "Samsung EXYNOS4" |
787 | select CPU_V7 | 790 | select CPU_V7 |
788 | select ARCH_SPARSEMEM_ENABLE | 791 | select ARCH_SPARSEMEM_ENABLE |
792 | select ARCH_HAS_HOLES_MEMORYMODEL | ||
789 | select GENERIC_GPIO | 793 | select GENERIC_GPIO |
790 | select HAVE_CLK | 794 | select HAVE_CLK |
791 | select CLKDEV_LOOKUP | 795 | select CLKDEV_LOOKUP |
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 7bdd91766d65..3227ca952a12 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock); | |||
38 | /* Address of GIC 0 CPU interface */ | 38 | /* Address of GIC 0 CPU interface */ |
39 | void __iomem *gic_cpu_base_addr __read_mostly; | 39 | void __iomem *gic_cpu_base_addr __read_mostly; |
40 | 40 | ||
41 | struct gic_chip_data { | ||
42 | unsigned int irq_offset; | ||
43 | void __iomem *dist_base; | ||
44 | void __iomem *cpu_base; | ||
45 | }; | ||
46 | |||
47 | /* | 41 | /* |
48 | * Supported arch specific GIC irq extension. | 42 | * Supported arch specific GIC irq extension. |
49 | * Default make them NULL. | 43 | * Default make them NULL. |
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 5a6ff7c605df..db2cb7d180dc 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig | |||
@@ -22,6 +22,8 @@ CONFIG_BLK_DEV_INTEGRITY=y | |||
22 | # CONFIG_IOSCHED_DEADLINE is not set | 22 | # CONFIG_IOSCHED_DEADLINE is not set |
23 | # CONFIG_IOSCHED_CFQ is not set | 23 | # CONFIG_IOSCHED_CFQ is not set |
24 | CONFIG_ARCH_MXS=y | 24 | CONFIG_ARCH_MXS=y |
25 | CONFIG_MACH_MX23EVK=y | ||
26 | CONFIG_MACH_MX28EVK=y | ||
25 | CONFIG_MACH_STMP378X_DEVB=y | 27 | CONFIG_MACH_STMP378X_DEVB=y |
26 | CONFIG_MACH_TX28=y | 28 | CONFIG_MACH_TX28=y |
27 | # CONFIG_ARM_THUMB is not set | 29 | # CONFIG_ARM_THUMB is not set |
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index a5cce242a775..97d31a4663da 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig | |||
@@ -11,12 +11,12 @@ CONFIG_ARCH_U8500=y | |||
11 | CONFIG_UX500_SOC_DB5500=y | 11 | CONFIG_UX500_SOC_DB5500=y |
12 | CONFIG_UX500_SOC_DB8500=y | 12 | CONFIG_UX500_SOC_DB8500=y |
13 | CONFIG_MACH_U8500=y | 13 | CONFIG_MACH_U8500=y |
14 | CONFIG_MACH_SNOWBALL=y | ||
14 | CONFIG_MACH_U5500=y | 15 | CONFIG_MACH_U5500=y |
15 | CONFIG_NO_HZ=y | 16 | CONFIG_NO_HZ=y |
16 | CONFIG_HIGH_RES_TIMERS=y | 17 | CONFIG_HIGH_RES_TIMERS=y |
17 | CONFIG_SMP=y | 18 | CONFIG_SMP=y |
18 | CONFIG_NR_CPUS=2 | 19 | CONFIG_NR_CPUS=2 |
19 | CONFIG_HOTPLUG_CPU=y | ||
20 | CONFIG_PREEMPT=y | 20 | CONFIG_PREEMPT=y |
21 | CONFIG_AEABI=y | 21 | CONFIG_AEABI=y |
22 | CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" | 22 | CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" |
@@ -25,8 +25,13 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | |||
25 | CONFIG_VFP=y | 25 | CONFIG_VFP=y |
26 | CONFIG_NEON=y | 26 | CONFIG_NEON=y |
27 | CONFIG_NET=y | 27 | CONFIG_NET=y |
28 | CONFIG_PACKET=y | ||
29 | CONFIG_UNIX=y | ||
30 | CONFIG_INET=y | ||
31 | CONFIG_IP_PNP=y | ||
32 | CONFIG_IP_PNP_DHCP=y | ||
33 | CONFIG_NETFILTER=y | ||
28 | CONFIG_PHONET=y | 34 | CONFIG_PHONET=y |
29 | CONFIG_PHONET_PIPECTRLR=y | ||
30 | # CONFIG_WIRELESS is not set | 35 | # CONFIG_WIRELESS is not set |
31 | CONFIG_CAIF=y | 36 | CONFIG_CAIF=y |
32 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 37 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
@@ -35,6 +40,13 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 | |||
35 | CONFIG_MISC_DEVICES=y | 40 | CONFIG_MISC_DEVICES=y |
36 | CONFIG_AB8500_PWM=y | 41 | CONFIG_AB8500_PWM=y |
37 | CONFIG_SENSORS_BH1780=y | 42 | CONFIG_SENSORS_BH1780=y |
43 | CONFIG_NETDEVICES=y | ||
44 | CONFIG_SMSC_PHY=y | ||
45 | CONFIG_NET_ETHERNET=y | ||
46 | CONFIG_SMSC911X=y | ||
47 | # CONFIG_NETDEV_1000 is not set | ||
48 | # CONFIG_NETDEV_10000 is not set | ||
49 | # CONFIG_WLAN is not set | ||
38 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 50 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
39 | CONFIG_INPUT_EVDEV=y | 51 | CONFIG_INPUT_EVDEV=y |
40 | # CONFIG_KEYBOARD_ATKBD is not set | 52 | # CONFIG_KEYBOARD_ATKBD is not set |
@@ -49,9 +61,9 @@ CONFIG_INPUT_MISC=y | |||
49 | CONFIG_INPUT_AB8500_PONKEY=y | 61 | CONFIG_INPUT_AB8500_PONKEY=y |
50 | # CONFIG_SERIO is not set | 62 | # CONFIG_SERIO is not set |
51 | CONFIG_VT_HW_CONSOLE_BINDING=y | 63 | CONFIG_VT_HW_CONSOLE_BINDING=y |
64 | # CONFIG_LEGACY_PTYS is not set | ||
52 | CONFIG_SERIAL_AMBA_PL011=y | 65 | CONFIG_SERIAL_AMBA_PL011=y |
53 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 66 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
54 | # CONFIG_LEGACY_PTYS is not set | ||
55 | CONFIG_HW_RANDOM=y | 67 | CONFIG_HW_RANDOM=y |
56 | CONFIG_HW_RANDOM_NOMADIK=y | 68 | CONFIG_HW_RANDOM_NOMADIK=y |
57 | CONFIG_I2C=y | 69 | CONFIG_I2C=y |
@@ -64,14 +76,19 @@ CONFIG_GPIO_TC3589X=y | |||
64 | CONFIG_MFD_STMPE=y | 76 | CONFIG_MFD_STMPE=y |
65 | CONFIG_MFD_TC3589X=y | 77 | CONFIG_MFD_TC3589X=y |
66 | CONFIG_AB8500_CORE=y | 78 | CONFIG_AB8500_CORE=y |
67 | CONFIG_REGULATOR=y | ||
68 | CONFIG_REGULATOR_AB8500=y | 79 | CONFIG_REGULATOR_AB8500=y |
69 | # CONFIG_HID_SUPPORT is not set | 80 | # CONFIG_HID_SUPPORT is not set |
70 | # CONFIG_USB_SUPPORT is not set | 81 | CONFIG_USB_MUSB_HDRC=y |
82 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
83 | CONFIG_MUSB_PIO_ONLY=y | ||
84 | CONFIG_USB_GADGET=y | ||
85 | CONFIG_AB8500_USB=y | ||
71 | CONFIG_MMC=y | 86 | CONFIG_MMC=y |
87 | CONFIG_MMC_CLKGATE=y | ||
72 | CONFIG_MMC_ARMMMCI=y | 88 | CONFIG_MMC_ARMMMCI=y |
73 | CONFIG_NEW_LEDS=y | 89 | CONFIG_NEW_LEDS=y |
74 | CONFIG_LEDS_CLASS=y | 90 | CONFIG_LEDS_CLASS=y |
91 | CONFIG_LEDS_LM3530=y | ||
75 | CONFIG_LEDS_LP5521=y | 92 | CONFIG_LEDS_LP5521=y |
76 | CONFIG_RTC_CLASS=y | 93 | CONFIG_RTC_CLASS=y |
77 | CONFIG_RTC_DRV_AB8500=y | 94 | CONFIG_RTC_DRV_AB8500=y |
@@ -79,7 +96,6 @@ CONFIG_RTC_DRV_PL031=y | |||
79 | CONFIG_DMADEVICES=y | 96 | CONFIG_DMADEVICES=y |
80 | CONFIG_STE_DMA40=y | 97 | CONFIG_STE_DMA40=y |
81 | CONFIG_STAGING=y | 98 | CONFIG_STAGING=y |
82 | # CONFIG_STAGING_EXCLUDE_BUILD is not set | ||
83 | CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y | 99 | CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y |
84 | CONFIG_EXT2_FS=y | 100 | CONFIG_EXT2_FS=y |
85 | CONFIG_EXT2_FS_XATTR=y | 101 | CONFIG_EXT2_FS_XATTR=y |
@@ -91,6 +107,8 @@ CONFIG_TMPFS=y | |||
91 | CONFIG_TMPFS_POSIX_ACL=y | 107 | CONFIG_TMPFS_POSIX_ACL=y |
92 | CONFIG_CONFIGFS_FS=m | 108 | CONFIG_CONFIGFS_FS=m |
93 | # CONFIG_MISC_FILESYSTEMS is not set | 109 | # CONFIG_MISC_FILESYSTEMS is not set |
110 | CONFIG_NFS_FS=y | ||
111 | CONFIG_ROOT_NFS=y | ||
94 | CONFIG_NLS_CODEPAGE_437=y | 112 | CONFIG_NLS_CODEPAGE_437=y |
95 | CONFIG_NLS_ISO8859_1=y | 113 | CONFIG_NLS_ISO8859_1=y |
96 | CONFIG_MAGIC_SYSRQ=y | 114 | CONFIG_MAGIC_SYSRQ=y |
@@ -99,7 +117,5 @@ CONFIG_DEBUG_KERNEL=y | |||
99 | # CONFIG_SCHED_DEBUG is not set | 117 | # CONFIG_SCHED_DEBUG is not set |
100 | # CONFIG_DEBUG_PREEMPT is not set | 118 | # CONFIG_DEBUG_PREEMPT is not set |
101 | CONFIG_DEBUG_INFO=y | 119 | CONFIG_DEBUG_INFO=y |
102 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
103 | # CONFIG_FTRACE is not set | 120 | # CONFIG_FTRACE is not set |
104 | CONFIG_DEBUG_USER=y | 121 | CONFIG_DEBUG_USER=y |
105 | CONFIG_DEBUG_ERRORS=y | ||
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 0691f9dcc500..435d3f86c708 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h | |||
@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int); | |||
41 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); | 41 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
42 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); | 42 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); |
43 | void gic_enable_ppi(unsigned int); | 43 | void gic_enable_ppi(unsigned int); |
44 | |||
45 | struct gic_chip_data { | ||
46 | unsigned int irq_offset; | ||
47 | void __iomem *dist_base; | ||
48 | void __iomem *cpu_base; | ||
49 | }; | ||
44 | #endif | 50 | #endif |
45 | 51 | ||
46 | #endif | 52 | #endif |
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 2721a5814cb9..5a526afb5f18 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h | |||
@@ -23,6 +23,7 @@ struct pt_regs; | |||
23 | extern void migrate_irqs(void); | 23 | extern void migrate_irqs(void); |
24 | 24 | ||
25 | extern void asm_do_IRQ(unsigned int, struct pt_regs *); | 25 | extern void asm_do_IRQ(unsigned int, struct pt_regs *); |
26 | void handle_IRQ(unsigned int, struct pt_regs *); | ||
26 | void init_IRQ(void); | 27 | void init_IRQ(void); |
27 | 28 | ||
28 | #endif | 29 | #endif |
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 0f928a131af8..de3dcab8610b 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
@@ -67,12 +67,12 @@ int arch_show_interrupts(struct seq_file *p, int prec) | |||
67 | } | 67 | } |
68 | 68 | ||
69 | /* | 69 | /* |
70 | * do_IRQ handles all hardware IRQ's. Decoded IRQs should not | 70 | * handle_IRQ handles all hardware IRQ's. Decoded IRQs should |
71 | * come via this function. Instead, they should provide their | 71 | * not come via this function. Instead, they should provide their |
72 | * own 'handler' | 72 | * own 'handler'. Used by platform code implementing C-based 1st |
73 | * level decoding. | ||
73 | */ | 74 | */ |
74 | asmlinkage void __exception_irq_entry | 75 | void handle_IRQ(unsigned int irq, struct pt_regs *regs) |
75 | asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | ||
76 | { | 76 | { |
77 | struct pt_regs *old_regs = set_irq_regs(regs); | 77 | struct pt_regs *old_regs = set_irq_regs(regs); |
78 | 78 | ||
@@ -97,6 +97,15 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |||
97 | set_irq_regs(old_regs); | 97 | set_irq_regs(old_regs); |
98 | } | 98 | } |
99 | 99 | ||
100 | /* | ||
101 | * asm_do_IRQ is the interface to be used from assembly code. | ||
102 | */ | ||
103 | asmlinkage void __exception_irq_entry | ||
104 | asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | ||
105 | { | ||
106 | handle_IRQ(irq, regs); | ||
107 | } | ||
108 | |||
100 | void set_irq_flags(unsigned int irq, unsigned int iflags) | 109 | void set_irq_flags(unsigned int irq, unsigned int iflags) |
101 | { | 110 | { |
102 | unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | 111 | unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index 85e6390795ac..3e7d1496cb47 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c | |||
@@ -169,6 +169,8 @@ static struct platform_device *cns3420_pdevs[] __initdata = { | |||
169 | 169 | ||
170 | static void __init cns3420_init(void) | 170 | static void __init cns3420_init(void) |
171 | { | 171 | { |
172 | cns3xxx_l2x0_init(); | ||
173 | |||
172 | platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); | 174 | platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); |
173 | 175 | ||
174 | cns3xxx_ahci_init(); | 176 | cns3xxx_ahci_init(); |
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index da30078a80c1..941a308e1253 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <asm/mach/time.h> | 16 | #include <asm/mach/time.h> |
17 | #include <asm/mach/irq.h> | 17 | #include <asm/mach/irq.h> |
18 | #include <asm/hardware/gic.h> | 18 | #include <asm/hardware/gic.h> |
19 | #include <asm/hardware/cache-l2x0.h> | ||
19 | #include <mach/cns3xxx.h> | 20 | #include <mach/cns3xxx.h> |
20 | #include "core.h" | 21 | #include "core.h" |
21 | 22 | ||
@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(void) | |||
244 | struct sys_timer cns3xxx_timer = { | 245 | struct sys_timer cns3xxx_timer = { |
245 | .init = cns3xxx_timer_init, | 246 | .init = cns3xxx_timer_init, |
246 | }; | 247 | }; |
248 | |||
249 | #ifdef CONFIG_CACHE_L2X0 | ||
250 | |||
251 | void __init cns3xxx_l2x0_init(void) | ||
252 | { | ||
253 | void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); | ||
254 | u32 val; | ||
255 | |||
256 | if (WARN_ON(!base)) | ||
257 | return; | ||
258 | |||
259 | /* | ||
260 | * Tag RAM Control register | ||
261 | * | ||
262 | * bit[10:8] - 1 cycle of write accesses latency | ||
263 | * bit[6:4] - 1 cycle of read accesses latency | ||
264 | * bit[3:0] - 1 cycle of setup latency | ||
265 | * | ||
266 | * 1 cycle of latency for setup, read and write accesses | ||
267 | */ | ||
268 | val = readl(base + L2X0_TAG_LATENCY_CTRL); | ||
269 | val &= 0xfffff888; | ||
270 | writel(val, base + L2X0_TAG_LATENCY_CTRL); | ||
271 | |||
272 | /* | ||
273 | * Data RAM Control register | ||
274 | * | ||
275 | * bit[10:8] - 1 cycles of write accesses latency | ||
276 | * bit[6:4] - 1 cycles of read accesses latency | ||
277 | * bit[3:0] - 1 cycle of setup latency | ||
278 | * | ||
279 | * 1 cycle of latency for setup, read and write accesses | ||
280 | */ | ||
281 | val = readl(base + L2X0_DATA_LATENCY_CTRL); | ||
282 | val &= 0xfffff888; | ||
283 | writel(val, base + L2X0_DATA_LATENCY_CTRL); | ||
284 | |||
285 | /* 32 KiB, 8-way, parity disable */ | ||
286 | l2x0_init(base, 0x00540000, 0xfe000fff); | ||
287 | } | ||
288 | |||
289 | #endif /* CONFIG_CACHE_L2X0 */ | ||
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h index ffeb3a8b73ba..fcd225343c61 100644 --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h | |||
@@ -13,6 +13,12 @@ | |||
13 | 13 | ||
14 | extern struct sys_timer cns3xxx_timer; | 14 | extern struct sys_timer cns3xxx_timer; |
15 | 15 | ||
16 | #ifdef CONFIG_CACHE_L2X0 | ||
17 | void __init cns3xxx_l2x0_init(void); | ||
18 | #else | ||
19 | static inline void cns3xxx_l2x0_init(void) {} | ||
20 | #endif /* CONFIG_CACHE_L2X0 */ | ||
21 | |||
16 | void __init cns3xxx_map_io(void); | 22 | void __init cns3xxx_map_io(void); |
17 | void __init cns3xxx_init_irq(void); | 23 | void __init cns3xxx_init_irq(void); |
18 | void cns3xxx_power_off(void); | 24 | void cns3xxx_power_off(void); |
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 29671ef07152..bd5394537c88 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
@@ -1117,6 +1117,8 @@ static __init int da850_evm_init_cpufreq(void) | |||
1117 | static __init int da850_evm_init_cpufreq(void) { return 0; } | 1117 | static __init int da850_evm_init_cpufreq(void) { return 0; } |
1118 | #endif | 1118 | #endif |
1119 | 1119 | ||
1120 | #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) | ||
1121 | |||
1120 | static __init void da850_evm_init(void) | 1122 | static __init void da850_evm_init(void) |
1121 | { | 1123 | { |
1122 | int ret; | 1124 | int ret; |
@@ -1237,6 +1239,11 @@ static __init void da850_evm_init(void) | |||
1237 | if (ret) | 1239 | if (ret) |
1238 | pr_warning("da850_evm_init: spi 1 registration failed: %d\n", | 1240 | pr_warning("da850_evm_init: spi 1 registration failed: %d\n", |
1239 | ret); | 1241 | ret); |
1242 | |||
1243 | ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE); | ||
1244 | if (ret) | ||
1245 | pr_warning("da850_evm_init: sata registration failed: %d\n", | ||
1246 | ret); | ||
1240 | } | 1247 | } |
1241 | 1248 | ||
1242 | #ifdef CONFIG_SERIAL_8250_CONSOLE | 1249 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index ae653194b645..00861139101d 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c | |||
@@ -44,7 +44,7 @@ static void __clk_enable(struct clk *clk) | |||
44 | __clk_enable(clk->parent); | 44 | __clk_enable(clk->parent); |
45 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) | 45 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) |
46 | davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, | 46 | davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, |
47 | PSC_STATE_ENABLE); | 47 | true, clk->flags); |
48 | } | 48 | } |
49 | 49 | ||
50 | static void __clk_disable(struct clk *clk) | 50 | static void __clk_disable(struct clk *clk) |
@@ -54,8 +54,7 @@ static void __clk_disable(struct clk *clk) | |||
54 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && | 54 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && |
55 | (clk->flags & CLK_PSC)) | 55 | (clk->flags & CLK_PSC)) |
56 | davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, | 56 | davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, |
57 | (clk->flags & PSC_SWRSTDISABLE) ? | 57 | false, clk->flags); |
58 | PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE); | ||
59 | if (clk->parent) | 58 | if (clk->parent) |
60 | __clk_disable(clk->parent); | 59 | __clk_disable(clk->parent); |
61 | } | 60 | } |
@@ -239,8 +238,7 @@ static int __init clk_disable_unused(void) | |||
239 | pr_debug("Clocks: disable unused %s\n", ck->name); | 238 | pr_debug("Clocks: disable unused %s\n", ck->name); |
240 | 239 | ||
241 | davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, | 240 | davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, |
242 | (ck->flags & PSC_SWRSTDISABLE) ? | 241 | false, ck->flags); |
243 | PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE); | ||
244 | } | 242 | } |
245 | spin_unlock_irq(&clockfw_lock); | 243 | spin_unlock_irq(&clockfw_lock); |
246 | 244 | ||
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 50b2482e0ba2..a705f367a84d 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h | |||
@@ -111,6 +111,7 @@ struct clk { | |||
111 | #define CLK_PLL BIT(4) /* PLL-derived clock */ | 111 | #define CLK_PLL BIT(4) /* PLL-derived clock */ |
112 | #define PRE_PLL BIT(5) /* source is before PLL mult/div */ | 112 | #define PRE_PLL BIT(5) /* source is before PLL mult/div */ |
113 | #define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ | 113 | #define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ |
114 | #define PSC_FORCE BIT(7) /* Force module state transtition */ | ||
114 | 115 | ||
115 | #define CLK(dev, con, ck) \ | 116 | #define CLK(dev, con, ck) \ |
116 | { \ | 117 | { \ |
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 133aac405853..935dbed5c541 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c | |||
@@ -58,6 +58,7 @@ static struct pll_data pll0_data = { | |||
58 | static struct clk ref_clk = { | 58 | static struct clk ref_clk = { |
59 | .name = "ref_clk", | 59 | .name = "ref_clk", |
60 | .rate = DA850_REF_FREQ, | 60 | .rate = DA850_REF_FREQ, |
61 | .set_rate = davinci_simple_set_rate, | ||
61 | }; | 62 | }; |
62 | 63 | ||
63 | static struct clk pll0_clk = { | 64 | static struct clk pll0_clk = { |
@@ -373,6 +374,14 @@ static struct clk spi1_clk = { | |||
373 | .flags = DA850_CLK_ASYNC3, | 374 | .flags = DA850_CLK_ASYNC3, |
374 | }; | 375 | }; |
375 | 376 | ||
377 | static struct clk sata_clk = { | ||
378 | .name = "sata", | ||
379 | .parent = &pll0_sysclk2, | ||
380 | .lpsc = DA850_LPSC1_SATA, | ||
381 | .gpsc = 1, | ||
382 | .flags = PSC_FORCE, | ||
383 | }; | ||
384 | |||
376 | static struct clk_lookup da850_clks[] = { | 385 | static struct clk_lookup da850_clks[] = { |
377 | CLK(NULL, "ref", &ref_clk), | 386 | CLK(NULL, "ref", &ref_clk), |
378 | CLK(NULL, "pll0", &pll0_clk), | 387 | CLK(NULL, "pll0", &pll0_clk), |
@@ -419,6 +428,7 @@ static struct clk_lookup da850_clks[] = { | |||
419 | CLK(NULL, "usb20", &usb20_clk), | 428 | CLK(NULL, "usb20", &usb20_clk), |
420 | CLK("spi_davinci.0", NULL, &spi0_clk), | 429 | CLK("spi_davinci.0", NULL, &spi0_clk), |
421 | CLK("spi_davinci.1", NULL, &spi1_clk), | 430 | CLK("spi_davinci.1", NULL, &spi1_clk), |
431 | CLK("ahci", NULL, &sata_clk), | ||
422 | CLK(NULL, NULL, NULL), | 432 | CLK(NULL, NULL, NULL), |
423 | }; | 433 | }; |
424 | 434 | ||
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index fc4e98ea7543..2f7e719636f1 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c | |||
@@ -14,6 +14,8 @@ | |||
14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
15 | #include <linux/dma-mapping.h> | 15 | #include <linux/dma-mapping.h> |
16 | #include <linux/serial_8250.h> | 16 | #include <linux/serial_8250.h> |
17 | #include <linux/ahci_platform.h> | ||
18 | #include <linux/clk.h> | ||
17 | 19 | ||
18 | #include <mach/cputype.h> | 20 | #include <mach/cputype.h> |
19 | #include <mach/common.h> | 21 | #include <mach/common.h> |
@@ -33,6 +35,7 @@ | |||
33 | #define DA8XX_SPI0_BASE 0x01c41000 | 35 | #define DA8XX_SPI0_BASE 0x01c41000 |
34 | #define DA830_SPI1_BASE 0x01e12000 | 36 | #define DA830_SPI1_BASE 0x01e12000 |
35 | #define DA8XX_LCD_CNTRL_BASE 0x01e13000 | 37 | #define DA8XX_LCD_CNTRL_BASE 0x01e13000 |
38 | #define DA850_SATA_BASE 0x01e18000 | ||
36 | #define DA850_MMCSD1_BASE 0x01e1b000 | 39 | #define DA850_MMCSD1_BASE 0x01e1b000 |
37 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 | 40 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 |
38 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 | 41 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 |
@@ -842,3 +845,126 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info, | |||
842 | 845 | ||
843 | return platform_device_register(&da8xx_spi_device[instance]); | 846 | return platform_device_register(&da8xx_spi_device[instance]); |
844 | } | 847 | } |
848 | |||
849 | #ifdef CONFIG_ARCH_DAVINCI_DA850 | ||
850 | |||
851 | static struct resource da850_sata_resources[] = { | ||
852 | { | ||
853 | .start = DA850_SATA_BASE, | ||
854 | .end = DA850_SATA_BASE + 0x1fff, | ||
855 | .flags = IORESOURCE_MEM, | ||
856 | }, | ||
857 | { | ||
858 | .start = IRQ_DA850_SATAINT, | ||
859 | .flags = IORESOURCE_IRQ, | ||
860 | }, | ||
861 | }; | ||
862 | |||
863 | /* SATA PHY Control Register offset from AHCI base */ | ||
864 | #define SATA_P0PHYCR_REG 0x178 | ||
865 | |||
866 | #define SATA_PHY_MPY(x) ((x) << 0) | ||
867 | #define SATA_PHY_LOS(x) ((x) << 6) | ||
868 | #define SATA_PHY_RXCDR(x) ((x) << 10) | ||
869 | #define SATA_PHY_RXEQ(x) ((x) << 13) | ||
870 | #define SATA_PHY_TXSWING(x) ((x) << 19) | ||
871 | #define SATA_PHY_ENPLL(x) ((x) << 31) | ||
872 | |||
873 | static struct clk *da850_sata_clk; | ||
874 | static unsigned long da850_sata_refclkpn; | ||
875 | |||
876 | /* Supported DA850 SATA crystal frequencies */ | ||
877 | #define KHZ_TO_HZ(freq) ((freq) * 1000) | ||
878 | static unsigned long da850_sata_xtal[] = { | ||
879 | KHZ_TO_HZ(300000), | ||
880 | KHZ_TO_HZ(250000), | ||
881 | 0, /* Reserved */ | ||
882 | KHZ_TO_HZ(187500), | ||
883 | KHZ_TO_HZ(150000), | ||
884 | KHZ_TO_HZ(125000), | ||
885 | KHZ_TO_HZ(120000), | ||
886 | KHZ_TO_HZ(100000), | ||
887 | KHZ_TO_HZ(75000), | ||
888 | KHZ_TO_HZ(60000), | ||
889 | }; | ||
890 | |||
891 | static int da850_sata_init(struct device *dev, void __iomem *addr) | ||
892 | { | ||
893 | int i, ret; | ||
894 | unsigned int val; | ||
895 | |||
896 | da850_sata_clk = clk_get(dev, NULL); | ||
897 | if (IS_ERR(da850_sata_clk)) | ||
898 | return PTR_ERR(da850_sata_clk); | ||
899 | |||
900 | ret = clk_enable(da850_sata_clk); | ||
901 | if (ret) | ||
902 | goto err0; | ||
903 | |||
904 | /* Enable SATA clock receiver */ | ||
905 | val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); | ||
906 | val &= ~BIT(0); | ||
907 | __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); | ||
908 | |||
909 | /* Get the multiplier needed for 1.5GHz PLL output */ | ||
910 | for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++) | ||
911 | if (da850_sata_xtal[i] == da850_sata_refclkpn) | ||
912 | break; | ||
913 | |||
914 | if (i == ARRAY_SIZE(da850_sata_xtal)) { | ||
915 | ret = -EINVAL; | ||
916 | goto err1; | ||
917 | } | ||
918 | |||
919 | val = SATA_PHY_MPY(i + 1) | | ||
920 | SATA_PHY_LOS(1) | | ||
921 | SATA_PHY_RXCDR(4) | | ||
922 | SATA_PHY_RXEQ(1) | | ||
923 | SATA_PHY_TXSWING(3) | | ||
924 | SATA_PHY_ENPLL(1); | ||
925 | |||
926 | __raw_writel(val, addr + SATA_P0PHYCR_REG); | ||
927 | |||
928 | return 0; | ||
929 | |||
930 | err1: | ||
931 | clk_disable(da850_sata_clk); | ||
932 | err0: | ||
933 | clk_put(da850_sata_clk); | ||
934 | return ret; | ||
935 | } | ||
936 | |||
937 | static void da850_sata_exit(struct device *dev) | ||
938 | { | ||
939 | clk_disable(da850_sata_clk); | ||
940 | clk_put(da850_sata_clk); | ||
941 | } | ||
942 | |||
943 | static struct ahci_platform_data da850_sata_pdata = { | ||
944 | .init = da850_sata_init, | ||
945 | .exit = da850_sata_exit, | ||
946 | }; | ||
947 | |||
948 | static u64 da850_sata_dmamask = DMA_BIT_MASK(32); | ||
949 | |||
950 | static struct platform_device da850_sata_device = { | ||
951 | .name = "ahci", | ||
952 | .id = -1, | ||
953 | .dev = { | ||
954 | .platform_data = &da850_sata_pdata, | ||
955 | .dma_mask = &da850_sata_dmamask, | ||
956 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
957 | }, | ||
958 | .num_resources = ARRAY_SIZE(da850_sata_resources), | ||
959 | .resource = da850_sata_resources, | ||
960 | }; | ||
961 | |||
962 | int __init da850_register_sata(unsigned long refclkpn) | ||
963 | { | ||
964 | da850_sata_refclkpn = refclkpn; | ||
965 | if (!da850_sata_refclkpn) | ||
966 | return -EINVAL; | ||
967 | |||
968 | return platform_device_register(&da850_sata_device); | ||
969 | } | ||
970 | #endif | ||
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index ad64da713fc8..eaca7d8b9d68 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h | |||
@@ -57,6 +57,7 @@ extern unsigned int da850_max_speed; | |||
57 | #define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) | 57 | #define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) |
58 | #define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) | 58 | #define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) |
59 | #define DA8XX_DEEPSLEEP_REG 0x8 | 59 | #define DA8XX_DEEPSLEEP_REG 0x8 |
60 | #define DA8XX_PWRDN_REG 0x18 | ||
60 | 61 | ||
61 | #define DA8XX_PSC0_BASE 0x01c10000 | 62 | #define DA8XX_PSC0_BASE 0x01c10000 |
62 | #define DA8XX_PLL0_BASE 0x01c11000 | 63 | #define DA8XX_PLL0_BASE 0x01c11000 |
@@ -89,6 +90,7 @@ int da850_register_cpufreq(char *async_clk); | |||
89 | int da8xx_register_cpuidle(void); | 90 | int da8xx_register_cpuidle(void); |
90 | void __iomem * __init da8xx_get_mem_ctlr(void); | 91 | void __iomem * __init da8xx_get_mem_ctlr(void); |
91 | int da850_register_pm(struct platform_device *pdev); | 92 | int da850_register_pm(struct platform_device *pdev); |
93 | int __init da850_register_sata(unsigned long refclkpn); | ||
92 | 94 | ||
93 | extern struct platform_device da8xx_serial_device; | 95 | extern struct platform_device da8xx_serial_device; |
94 | extern struct emac_platform_data da8xx_emac_pdata; | 96 | extern struct emac_platform_data da8xx_emac_pdata; |
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 1110fdd77ba4..47fd0bc3d3e7 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h | |||
@@ -244,12 +244,13 @@ | |||
244 | #define PSC_STATE_ENABLE 3 | 244 | #define PSC_STATE_ENABLE 3 |
245 | 245 | ||
246 | #define MDSTAT_STATE_MASK 0x1f | 246 | #define MDSTAT_STATE_MASK 0x1f |
247 | #define MDCTL_FORCE BIT(31) | ||
247 | 248 | ||
248 | #ifndef __ASSEMBLER__ | 249 | #ifndef __ASSEMBLER__ |
249 | 250 | ||
250 | extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); | 251 | extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); |
251 | extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, | 252 | extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, |
252 | unsigned int id, u32 next_state); | 253 | unsigned int id, bool enable, u32 flags); |
253 | 254 | ||
254 | #endif | 255 | #endif |
255 | 256 | ||
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index a41580400701..1fb6bdff38c1 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c | |||
@@ -25,6 +25,8 @@ | |||
25 | #include <mach/cputype.h> | 25 | #include <mach/cputype.h> |
26 | #include <mach/psc.h> | 26 | #include <mach/psc.h> |
27 | 27 | ||
28 | #include "clock.h" | ||
29 | |||
28 | /* Return nonzero iff the domain's clock is active */ | 30 | /* Return nonzero iff the domain's clock is active */ |
29 | int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) | 31 | int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) |
30 | { | 32 | { |
@@ -48,11 +50,12 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) | |||
48 | 50 | ||
49 | /* Enable or disable a PSC domain */ | 51 | /* Enable or disable a PSC domain */ |
50 | void davinci_psc_config(unsigned int domain, unsigned int ctlr, | 52 | void davinci_psc_config(unsigned int domain, unsigned int ctlr, |
51 | unsigned int id, u32 next_state) | 53 | unsigned int id, bool enable, u32 flags) |
52 | { | 54 | { |
53 | u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; | 55 | u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; |
54 | void __iomem *psc_base; | 56 | void __iomem *psc_base; |
55 | struct davinci_soc_info *soc_info = &davinci_soc_info; | 57 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
58 | u32 next_state = PSC_STATE_ENABLE; | ||
56 | 59 | ||
57 | if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { | 60 | if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { |
58 | pr_warning("PSC: Bad psc data: 0x%x[%d]\n", | 61 | pr_warning("PSC: Bad psc data: 0x%x[%d]\n", |
@@ -62,9 +65,18 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, | |||
62 | 65 | ||
63 | psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); | 66 | psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); |
64 | 67 | ||
68 | if (!enable) { | ||
69 | if (flags & PSC_SWRSTDISABLE) | ||
70 | next_state = PSC_STATE_SWRSTDISABLE; | ||
71 | else | ||
72 | next_state = PSC_STATE_DISABLE; | ||
73 | } | ||
74 | |||
65 | mdctl = __raw_readl(psc_base + MDCTL + 4 * id); | 75 | mdctl = __raw_readl(psc_base + MDCTL + 4 * id); |
66 | mdctl &= ~MDSTAT_STATE_MASK; | 76 | mdctl &= ~MDSTAT_STATE_MASK; |
67 | mdctl |= next_state; | 77 | mdctl |= next_state; |
78 | if (flags & PSC_FORCE) | ||
79 | mdctl |= MDCTL_FORCE; | ||
68 | __raw_writel(mdctl, psc_base + MDCTL + 4 * id); | 80 | __raw_writel(mdctl, psc_base + MDCTL + 4 * id); |
69 | 81 | ||
70 | pdstat = __raw_readl(psc_base + PDSTAT); | 82 | pdstat = __raw_readl(psc_base + PDSTAT); |
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index ae433a052df6..0c77ab99fa16 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig | |||
@@ -16,7 +16,8 @@ config CPU_EXYNOS4210 | |||
16 | Enable EXYNOS4210 CPU support | 16 | Enable EXYNOS4210 CPU support |
17 | 17 | ||
18 | config EXYNOS4_MCT | 18 | config EXYNOS4_MCT |
19 | bool "Kernel timer support by MCT" | 19 | bool |
20 | default y | ||
20 | help | 21 | help |
21 | Use MCT (Multi Core Timer) as kernel timers | 22 | Use MCT (Multi Core Timer) as kernel timers |
22 | 23 | ||
@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI | |||
25 | help | 26 | help |
26 | Compile in platform device definitions for AHCI | 27 | Compile in platform device definitions for AHCI |
27 | 28 | ||
29 | config EXYNOS4_SETUP_FIMD0 | ||
30 | bool | ||
31 | help | ||
32 | Common setup code for FIMD0. | ||
33 | |||
28 | config EXYNOS4_DEV_PD | 34 | config EXYNOS4_DEV_PD |
29 | bool | 35 | bool |
30 | help | 36 | help |
@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU | |||
35 | help | 41 | help |
36 | Common setup code for SYSTEM MMU in EXYNOS4 | 42 | Common setup code for SYSTEM MMU in EXYNOS4 |
37 | 43 | ||
44 | config EXYNOS4_DEV_DWMCI | ||
45 | bool | ||
46 | help | ||
47 | Compile in platform device definitions for DWMCI | ||
48 | |||
38 | config EXYNOS4_SETUP_I2C1 | 49 | config EXYNOS4_SETUP_I2C1 |
39 | bool | 50 | bool |
40 | help | 51 | help |
@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines" | |||
103 | config MACH_SMDKC210 | 114 | config MACH_SMDKC210 |
104 | bool "SMDKC210" | 115 | bool "SMDKC210" |
105 | select CPU_EXYNOS4210 | 116 | select CPU_EXYNOS4210 |
117 | select S5P_DEV_FIMD0 | ||
106 | select S3C_DEV_RTC | 118 | select S3C_DEV_RTC |
107 | select S3C_DEV_WDT | 119 | select S3C_DEV_WDT |
108 | select S3C_DEV_I2C1 | 120 | select S3C_DEV_I2C1 |
@@ -114,6 +126,7 @@ config MACH_SMDKC210 | |||
114 | select SAMSUNG_DEV_BACKLIGHT | 126 | select SAMSUNG_DEV_BACKLIGHT |
115 | select EXYNOS4_DEV_PD | 127 | select EXYNOS4_DEV_PD |
116 | select EXYNOS4_DEV_SYSMMU | 128 | select EXYNOS4_DEV_SYSMMU |
129 | select EXYNOS4_SETUP_FIMD0 | ||
117 | select EXYNOS4_SETUP_I2C1 | 130 | select EXYNOS4_SETUP_I2C1 |
118 | select EXYNOS4_SETUP_SDHCI | 131 | select EXYNOS4_SETUP_SDHCI |
119 | help | 132 | help |
@@ -122,6 +135,7 @@ config MACH_SMDKC210 | |||
122 | config MACH_SMDKV310 | 135 | config MACH_SMDKV310 |
123 | bool "SMDKV310" | 136 | bool "SMDKV310" |
124 | select CPU_EXYNOS4210 | 137 | select CPU_EXYNOS4210 |
138 | select S5P_DEV_FIMD0 | ||
125 | select S3C_DEV_RTC | 139 | select S3C_DEV_RTC |
126 | select S3C_DEV_WDT | 140 | select S3C_DEV_WDT |
127 | select S3C_DEV_I2C1 | 141 | select S3C_DEV_I2C1 |
@@ -130,10 +144,12 @@ config MACH_SMDKV310 | |||
130 | select S3C_DEV_HSMMC2 | 144 | select S3C_DEV_HSMMC2 |
131 | select S3C_DEV_HSMMC3 | 145 | select S3C_DEV_HSMMC3 |
132 | select SAMSUNG_DEV_BACKLIGHT | 146 | select SAMSUNG_DEV_BACKLIGHT |
147 | select EXYNOS4_DEV_AHCI | ||
133 | select SAMSUNG_DEV_KEYPAD | 148 | select SAMSUNG_DEV_KEYPAD |
134 | select EXYNOS4_DEV_PD | 149 | select EXYNOS4_DEV_PD |
135 | select SAMSUNG_DEV_PWM | 150 | select SAMSUNG_DEV_PWM |
136 | select EXYNOS4_DEV_SYSMMU | 151 | select EXYNOS4_DEV_SYSMMU |
152 | select EXYNOS4_SETUP_FIMD0 | ||
137 | select EXYNOS4_SETUP_I2C1 | 153 | select EXYNOS4_SETUP_I2C1 |
138 | select EXYNOS4_SETUP_KEYPAD | 154 | select EXYNOS4_SETUP_KEYPAD |
139 | select EXYNOS4_SETUP_SDHCI | 155 | select EXYNOS4_SETUP_SDHCI |
@@ -157,13 +173,22 @@ config MACH_ARMLEX4210 | |||
157 | config MACH_UNIVERSAL_C210 | 173 | config MACH_UNIVERSAL_C210 |
158 | bool "Mobile UNIVERSAL_C210 Board" | 174 | bool "Mobile UNIVERSAL_C210 Board" |
159 | select CPU_EXYNOS4210 | 175 | select CPU_EXYNOS4210 |
176 | select S5P_GPIO_INT | ||
177 | select S5P_DEV_FIMC0 | ||
178 | select S5P_DEV_FIMC1 | ||
179 | select S5P_DEV_FIMC2 | ||
180 | select S5P_DEV_FIMC3 | ||
160 | select S3C_DEV_HSMMC | 181 | select S3C_DEV_HSMMC |
161 | select S3C_DEV_HSMMC2 | 182 | select S3C_DEV_HSMMC2 |
162 | select S3C_DEV_HSMMC3 | 183 | select S3C_DEV_HSMMC3 |
163 | select S3C_DEV_I2C1 | 184 | select S3C_DEV_I2C1 |
185 | select S3C_DEV_I2C3 | ||
164 | select S3C_DEV_I2C5 | 186 | select S3C_DEV_I2C5 |
187 | select S5P_DEV_MFC | ||
165 | select S5P_DEV_ONENAND | 188 | select S5P_DEV_ONENAND |
189 | select EXYNOS4_DEV_PD | ||
166 | select EXYNOS4_SETUP_I2C1 | 190 | select EXYNOS4_SETUP_I2C1 |
191 | select EXYNOS4_SETUP_I2C3 | ||
167 | select EXYNOS4_SETUP_I2C5 | 192 | select EXYNOS4_SETUP_I2C5 |
168 | select EXYNOS4_SETUP_SDHCI | 193 | select EXYNOS4_SETUP_SDHCI |
169 | help | 194 | help |
@@ -180,13 +205,16 @@ config MACH_NURI | |||
180 | select S3C_DEV_I2C1 | 205 | select S3C_DEV_I2C1 |
181 | select S3C_DEV_I2C3 | 206 | select S3C_DEV_I2C3 |
182 | select S3C_DEV_I2C5 | 207 | select S3C_DEV_I2C5 |
208 | select S5P_DEV_MFC | ||
183 | select S5P_DEV_USB_EHCI | 209 | select S5P_DEV_USB_EHCI |
210 | select EXYNOS4_DEV_PD | ||
184 | select EXYNOS4_SETUP_I2C1 | 211 | select EXYNOS4_SETUP_I2C1 |
185 | select EXYNOS4_SETUP_I2C3 | 212 | select EXYNOS4_SETUP_I2C3 |
186 | select EXYNOS4_SETUP_I2C5 | 213 | select EXYNOS4_SETUP_I2C5 |
187 | select EXYNOS4_SETUP_SDHCI | 214 | select EXYNOS4_SETUP_SDHCI |
188 | select EXYNOS4_SETUP_USB_PHY | 215 | select EXYNOS4_SETUP_USB_PHY |
189 | select SAMSUNG_DEV_PWM | 216 | select SAMSUNG_DEV_PWM |
217 | select SAMSUNG_DEV_ADC | ||
190 | help | 218 | help |
191 | Machine support for Samsung Mobile NURI Board. | 219 | Machine support for Samsung Mobile NURI Board. |
192 | 220 | ||
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index 1366995d8c2c..b7fe1d7b0b1f 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile | |||
@@ -13,18 +13,13 @@ obj- := | |||
13 | # Core support for EXYNOS4 system | 13 | # Core support for EXYNOS4 system |
14 | 14 | ||
15 | obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o | 15 | obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o |
16 | obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o | 16 | obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o |
17 | obj-$(CONFIG_PM) += pm.o sleep.o | 17 | obj-$(CONFIG_PM) += pm.o sleep.o |
18 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 18 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
19 | 19 | ||
20 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 20 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
21 | 21 | ||
22 | ifeq ($(CONFIG_EXYNOS4_MCT),y) | 22 | obj-$(CONFIG_EXYNOS4_MCT) += mct.o |
23 | obj-y += mct.o | ||
24 | else | ||
25 | obj-y += time.o | ||
26 | obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o | ||
27 | endif | ||
28 | 23 | ||
29 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 24 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
30 | 25 | ||
@@ -42,8 +37,10 @@ obj-y += dev-audio.o | |||
42 | obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o | 37 | obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o |
43 | obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o | 38 | obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o |
44 | obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o | 39 | obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o |
40 | obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o | ||
45 | 41 | ||
46 | obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o | 42 | obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o |
43 | obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o | ||
47 | obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o | 44 | obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o |
48 | obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o | 45 | obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o |
49 | obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o | 46 | obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o |
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 66494f28bbef..851dea018578 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c | |||
@@ -528,6 +528,11 @@ static struct clk init_clocks_off[] = { | |||
528 | .enable = exynos4_clk_ip_image_ctrl, | 528 | .enable = exynos4_clk_ip_image_ctrl, |
529 | .ctrlbit = (1 << 0), | 529 | .ctrlbit = (1 << 0), |
530 | }, { | 530 | }, { |
531 | .name = "mfc", | ||
532 | .devname = "s5p-mfc", | ||
533 | .enable = exynos4_clk_ip_mfc_ctrl, | ||
534 | .ctrlbit = (1 << 0), | ||
535 | }, { | ||
531 | .name = "i2c", | 536 | .name = "i2c", |
532 | .devname = "s3c2440-i2c.0", | 537 | .devname = "s3c2440-i2c.0", |
533 | .parent = &clk_aclk_100.clk, | 538 | .parent = &clk_aclk_100.clk, |
@@ -731,6 +736,52 @@ static struct clksrc_sources clkset_mout_g2d = { | |||
731 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), | 736 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), |
732 | }; | 737 | }; |
733 | 738 | ||
739 | static struct clk *clkset_mout_mfc0_list[] = { | ||
740 | [0] = &clk_mout_mpll.clk, | ||
741 | [1] = &clk_sclk_apll.clk, | ||
742 | }; | ||
743 | |||
744 | static struct clksrc_sources clkset_mout_mfc0 = { | ||
745 | .sources = clkset_mout_mfc0_list, | ||
746 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list), | ||
747 | }; | ||
748 | |||
749 | static struct clksrc_clk clk_mout_mfc0 = { | ||
750 | .clk = { | ||
751 | .name = "mout_mfc0", | ||
752 | }, | ||
753 | .sources = &clkset_mout_mfc0, | ||
754 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 }, | ||
755 | }; | ||
756 | |||
757 | static struct clk *clkset_mout_mfc1_list[] = { | ||
758 | [0] = &clk_mout_epll.clk, | ||
759 | [1] = &clk_sclk_vpll.clk, | ||
760 | }; | ||
761 | |||
762 | static struct clksrc_sources clkset_mout_mfc1 = { | ||
763 | .sources = clkset_mout_mfc1_list, | ||
764 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list), | ||
765 | }; | ||
766 | |||
767 | static struct clksrc_clk clk_mout_mfc1 = { | ||
768 | .clk = { | ||
769 | .name = "mout_mfc1", | ||
770 | }, | ||
771 | .sources = &clkset_mout_mfc1, | ||
772 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 }, | ||
773 | }; | ||
774 | |||
775 | static struct clk *clkset_mout_mfc_list[] = { | ||
776 | [0] = &clk_mout_mfc0.clk, | ||
777 | [1] = &clk_mout_mfc1.clk, | ||
778 | }; | ||
779 | |||
780 | static struct clksrc_sources clkset_mout_mfc = { | ||
781 | .sources = clkset_mout_mfc_list, | ||
782 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), | ||
783 | }; | ||
784 | |||
734 | static struct clksrc_clk clk_dout_mmc0 = { | 785 | static struct clksrc_clk clk_dout_mmc0 = { |
735 | .clk = { | 786 | .clk = { |
736 | .name = "dout_mmc0", | 787 | .name = "dout_mmc0", |
@@ -974,6 +1025,14 @@ static struct clksrc_clk clksrcs[] = { | |||
974 | .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, | 1025 | .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, |
975 | }, { | 1026 | }, { |
976 | .clk = { | 1027 | .clk = { |
1028 | .name = "sclk_mfc", | ||
1029 | .devname = "s5p-mfc", | ||
1030 | }, | ||
1031 | .sources = &clkset_mout_mfc, | ||
1032 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 }, | ||
1033 | .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, | ||
1034 | }, { | ||
1035 | .clk = { | ||
977 | .name = "sclk_mmc", | 1036 | .name = "sclk_mmc", |
978 | .devname = "s3c-sdhci.0", | 1037 | .devname = "s3c-sdhci.0", |
979 | .parent = &clk_dout_mmc0.clk, | 1038 | .parent = &clk_dout_mmc0.clk, |
@@ -1049,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = { | |||
1049 | &clk_dout_mmc2, | 1108 | &clk_dout_mmc2, |
1050 | &clk_dout_mmc3, | 1109 | &clk_dout_mmc3, |
1051 | &clk_dout_mmc4, | 1110 | &clk_dout_mmc4, |
1111 | &clk_mout_mfc0, | ||
1112 | &clk_mout_mfc1, | ||
1052 | }; | 1113 | }; |
1053 | 1114 | ||
1054 | static int xtal_rate; | 1115 | static int xtal_rate; |
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index bfd621460abf..2d8a40c9e6e5 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c | |||
@@ -16,12 +16,16 @@ | |||
16 | 16 | ||
17 | #include <asm/proc-fns.h> | 17 | #include <asm/proc-fns.h> |
18 | #include <asm/hardware/cache-l2x0.h> | 18 | #include <asm/hardware/cache-l2x0.h> |
19 | #include <asm/hardware/gic.h> | ||
19 | 20 | ||
20 | #include <plat/cpu.h> | 21 | #include <plat/cpu.h> |
21 | #include <plat/clock.h> | 22 | #include <plat/clock.h> |
23 | #include <plat/devs.h> | ||
22 | #include <plat/exynos4.h> | 24 | #include <plat/exynos4.h> |
25 | #include <plat/adc-core.h> | ||
23 | #include <plat/sdhci.h> | 26 | #include <plat/sdhci.h> |
24 | #include <plat/devs.h> | 27 | #include <plat/devs.h> |
28 | #include <plat/fb-core.h> | ||
25 | #include <plat/fimc-core.h> | 29 | #include <plat/fimc-core.h> |
26 | #include <plat/iic-core.h> | 30 | #include <plat/iic-core.h> |
27 | 31 | ||
@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = { | |||
103 | .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), | 107 | .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), |
104 | .length = SZ_4K, | 108 | .length = SZ_4K, |
105 | .type = MT_DEVICE, | 109 | .type = MT_DEVICE, |
106 | } | 110 | }, { |
111 | .virtual = (unsigned long)S5P_VA_GIC_CPU, | ||
112 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), | ||
113 | .length = SZ_64K, | ||
114 | .type = MT_DEVICE, | ||
115 | }, { | ||
116 | .virtual = (unsigned long)S5P_VA_GIC_DIST, | ||
117 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), | ||
118 | .length = SZ_64K, | ||
119 | .type = MT_DEVICE, | ||
120 | }, | ||
107 | }; | 121 | }; |
108 | 122 | ||
109 | static void exynos4_idle(void) | 123 | static void exynos4_idle(void) |
@@ -129,6 +143,8 @@ void __init exynos4_map_io(void) | |||
129 | exynos4_default_sdhci2(); | 143 | exynos4_default_sdhci2(); |
130 | exynos4_default_sdhci3(); | 144 | exynos4_default_sdhci3(); |
131 | 145 | ||
146 | s3c_adc_setname("samsung-adc-v3"); | ||
147 | |||
132 | s3c_fimc_setname(0, "exynos4-fimc"); | 148 | s3c_fimc_setname(0, "exynos4-fimc"); |
133 | s3c_fimc_setname(1, "exynos4-fimc"); | 149 | s3c_fimc_setname(1, "exynos4-fimc"); |
134 | s3c_fimc_setname(2, "exynos4-fimc"); | 150 | s3c_fimc_setname(2, "exynos4-fimc"); |
@@ -138,6 +154,8 @@ void __init exynos4_map_io(void) | |||
138 | s3c_i2c0_setname("s3c2440-i2c"); | 154 | s3c_i2c0_setname("s3c2440-i2c"); |
139 | s3c_i2c1_setname("s3c2440-i2c"); | 155 | s3c_i2c1_setname("s3c2440-i2c"); |
140 | s3c_i2c2_setname("s3c2440-i2c"); | 156 | s3c_i2c2_setname("s3c2440-i2c"); |
157 | |||
158 | s5p_fb_setname(0, "exynos4-fb"); | ||
141 | } | 159 | } |
142 | 160 | ||
143 | void __init exynos4_init_clocks(int xtal) | 161 | void __init exynos4_init_clocks(int xtal) |
@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal) | |||
150 | exynos4_setup_clocks(); | 168 | exynos4_setup_clocks(); |
151 | } | 169 | } |
152 | 170 | ||
171 | static void exynos4_gic_irq_eoi(struct irq_data *d) | ||
172 | { | ||
173 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); | ||
174 | |||
175 | gic_data->cpu_base = S5P_VA_GIC_CPU + | ||
176 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | ||
177 | } | ||
178 | |||
153 | void __init exynos4_init_irq(void) | 179 | void __init exynos4_init_irq(void) |
154 | { | 180 | { |
155 | int irq; | 181 | int irq; |
156 | 182 | ||
157 | gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); | 183 | gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); |
184 | gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi; | ||
158 | 185 | ||
159 | for (irq = 0; irq < MAX_COMBINER_NR; irq++) { | 186 | for (irq = 0; irq < MAX_COMBINER_NR; irq++) { |
160 | 187 | ||
161 | /* | ||
162 | * From SPI(0) to SPI(39) and SPI(51), SPI(53) are | ||
163 | * connected to the interrupt combiner. These irqs | ||
164 | * should be initialized to support cascade interrupt. | ||
165 | */ | ||
166 | if ((irq >= 40) && !(irq == 51) && !(irq == 53)) | ||
167 | continue; | ||
168 | |||
169 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), | 188 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), |
170 | COMBINER_IRQ(irq, 0)); | 189 | COMBINER_IRQ(irq, 0)); |
171 | combiner_cascade_irq(irq, IRQ_SPI(irq)); | 190 | combiner_cascade_irq(irq, IRQ_SPI(irq)); |
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c index 983069a53239..5a9f9c2e53bf 100644 --- a/arch/arm/mach-exynos4/dev-audio.c +++ b/arch/arm/mach-exynos4/dev-audio.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <mach/map.h> | 21 | #include <mach/map.h> |
22 | #include <mach/dma.h> | 22 | #include <mach/dma.h> |
23 | #include <mach/irqs.h> | 23 | #include <mach/irqs.h> |
24 | #include <mach/regs-audss.h> | ||
24 | 25 | ||
25 | static const char *rclksrc[] = { | 26 | static const char *rclksrc[] = { |
26 | [0] = "busclk", | 27 | [0] = "busclk", |
@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = { | |||
55 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | 56 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI |
56 | | QUIRK_NEED_RSTCLR, | 57 | | QUIRK_NEED_RSTCLR, |
57 | .src_clk = rclksrc, | 58 | .src_clk = rclksrc, |
59 | .idma_addr = EXYNOS4_AUDSS_INT_MEM, | ||
58 | }, | 60 | }, |
59 | }, | 61 | }, |
60 | }; | 62 | }; |
diff --git a/arch/arm/mach-exynos4/dev-dwmci.c b/arch/arm/mach-exynos4/dev-dwmci.c new file mode 100644 index 000000000000..b025db4bf602 --- /dev/null +++ b/arch/arm/mach-exynos4/dev-dwmci.c | |||
@@ -0,0 +1,82 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-exynos4/dev-dwmci.c | ||
3 | * | ||
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * | ||
7 | * Platform device for Synopsys DesignWare Mobile Storage IP | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/dma-mapping.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/mmc/dw_mmc.h> | ||
20 | |||
21 | #include <plat/devs.h> | ||
22 | |||
23 | #include <mach/map.h> | ||
24 | |||
25 | static int exynos4_dwmci_get_bus_wd(u32 slot_id) | ||
26 | { | ||
27 | return 4; | ||
28 | } | ||
29 | |||
30 | static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data) | ||
31 | { | ||
32 | return 0; | ||
33 | } | ||
34 | |||
35 | static struct resource exynos4_dwmci_resource[] = { | ||
36 | [0] = { | ||
37 | .start = EXYNOS4_PA_DWMCI, | ||
38 | .end = EXYNOS4_PA_DWMCI + SZ_4K - 1, | ||
39 | .flags = IORESOURCE_MEM, | ||
40 | }, | ||
41 | [1] = { | ||
42 | .start = IRQ_DWMCI, | ||
43 | .end = IRQ_DWMCI, | ||
44 | .flags = IORESOURCE_IRQ, | ||
45 | } | ||
46 | }; | ||
47 | |||
48 | static struct dw_mci_board exynos4_dwci_pdata = { | ||
49 | .num_slots = 1, | ||
50 | .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, | ||
51 | .bus_hz = 80 * 1000 * 1000, | ||
52 | .detect_delay_ms = 200, | ||
53 | .init = exynos4_dwmci_init, | ||
54 | .get_bus_wd = exynos4_dwmci_get_bus_wd, | ||
55 | }; | ||
56 | |||
57 | static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32); | ||
58 | |||
59 | struct platform_device exynos4_device_dwmci = { | ||
60 | .name = "dw_mmc", | ||
61 | .id = -1, | ||
62 | .num_resources = ARRAY_SIZE(exynos4_dwmci_resource), | ||
63 | .resource = exynos4_dwmci_resource, | ||
64 | .dev = { | ||
65 | .dma_mask = &exynos4_dwmci_dmamask, | ||
66 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
67 | .platform_data = &exynos4_dwci_pdata, | ||
68 | }, | ||
69 | }; | ||
70 | |||
71 | void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd) | ||
72 | { | ||
73 | struct dw_mci_board *npd; | ||
74 | |||
75 | npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board), | ||
76 | &exynos4_device_dwmci); | ||
77 | |||
78 | if (!npd->init) | ||
79 | npd->init = exynos4_dwmci_init; | ||
80 | if (!npd->get_bus_wd) | ||
81 | npd->get_bus_wd = exynos4_dwmci_get_bus_wd; | ||
82 | } | ||
diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c index 2b5909e2ccd3..7490789784c9 100644 --- a/arch/arm/mach-exynos4/hotplug.c +++ b/arch/arm/mach-exynos4/hotplug.c | |||
@@ -13,9 +13,12 @@ | |||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/errno.h> | 14 | #include <linux/errno.h> |
15 | #include <linux/smp.h> | 15 | #include <linux/smp.h> |
16 | #include <linux/io.h> | ||
16 | 17 | ||
17 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
18 | 19 | ||
20 | #include <mach/regs-pmu.h> | ||
21 | |||
19 | extern volatile int pen_release; | 22 | extern volatile int pen_release; |
20 | 23 | ||
21 | static inline void cpu_enter_lowpower(void) | 24 | static inline void cpu_enter_lowpower(void) |
@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void) | |||
58 | 61 | ||
59 | static inline void platform_do_lowpower(unsigned int cpu, int *spurious) | 62 | static inline void platform_do_lowpower(unsigned int cpu, int *spurious) |
60 | { | 63 | { |
61 | /* | ||
62 | * there is no power-control hardware on this platform, so all | ||
63 | * we can do is put the core into WFI; this is safe as the calling | ||
64 | * code will have already disabled interrupts | ||
65 | */ | ||
66 | for (;;) { | 64 | for (;;) { |
65 | |||
66 | /* make cpu1 to be turned off at next WFI command */ | ||
67 | if (cpu == 1) | ||
68 | __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION); | ||
69 | |||
67 | /* | 70 | /* |
68 | * here's the WFI | 71 | * here's the WFI |
69 | */ | 72 | */ |
diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos4/include/mach/dwmci.h new file mode 100644 index 000000000000..7ce657459cc0 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/dwmci.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/include/mach/dwmci.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Synopsys DesignWare Mobile Storage for EXYNOS4210 | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARM_ARCH_DWMCI_H | ||
14 | #define __ASM_ARM_ARCH_DWMCI_H __FILE__ | ||
15 | |||
16 | #include <linux/mmc/dw_mmc.h> | ||
17 | |||
18 | extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd); | ||
19 | |||
20 | #endif /* __ASM_ARM_ARCH_DWMCI_H */ | ||
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S index d8f38c2e5654..d7a1e281ce7a 100644 --- a/arch/arm/mach-exynos4/include/mach/entry-macro.S +++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S | |||
@@ -10,6 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <mach/hardware.h> | 12 | #include <mach/hardware.h> |
13 | #include <mach/map.h> | ||
13 | #include <asm/hardware/gic.h> | 14 | #include <asm/hardware/gic.h> |
14 | 15 | ||
15 | .macro disable_fiq | 16 | .macro disable_fiq |
@@ -18,6 +19,10 @@ | |||
18 | .macro get_irqnr_preamble, base, tmp | 19 | .macro get_irqnr_preamble, base, tmp |
19 | ldr \base, =gic_cpu_base_addr | 20 | ldr \base, =gic_cpu_base_addr |
20 | ldr \base, [\base] | 21 | ldr \base, [\base] |
22 | mrc p15, 0, \tmp, c0, c0, 5 | ||
23 | and \tmp, \tmp, #3 | ||
24 | cmp \tmp, #1 | ||
25 | addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET | ||
21 | .endm | 26 | .endm |
22 | 27 | ||
23 | .macro arch_ret_to_user, tmp1, tmp2 | 28 | .macro arch_ret_to_user, tmp1, tmp2 |
@@ -75,10 +80,4 @@ | |||
75 | /* As above, this assumes that irqstat and base are preserved.. */ | 80 | /* As above, this assumes that irqstat and base are preserved.. */ |
76 | 81 | ||
77 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | 82 | .macro test_for_ltirq, irqnr, irqstat, base, tmp |
78 | bic \irqnr, \irqstat, #0x1c00 | ||
79 | mov \tmp, #0 | ||
80 | cmp \irqnr, #29 | ||
81 | moveq \tmp, #1 | ||
82 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
83 | cmp \tmp, #0 | ||
84 | .endm | 83 | .endm |
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h index 5d037301d21a..934d2a493982 100644 --- a/arch/arm/mach-exynos4/include/mach/irqs.h +++ b/arch/arm/mach-exynos4/include/mach/irqs.h | |||
@@ -19,40 +19,105 @@ | |||
19 | 19 | ||
20 | #define IRQ_PPI(x) S5P_IRQ(x+16) | 20 | #define IRQ_PPI(x) S5P_IRQ(x+16) |
21 | 21 | ||
22 | #define IRQ_LOCALTIMER IRQ_PPI(13) | ||
23 | |||
24 | /* SPI: Shared Peripheral Interrupt */ | 22 | /* SPI: Shared Peripheral Interrupt */ |
25 | 23 | ||
26 | #define IRQ_SPI(x) S5P_IRQ(x+32) | 24 | #define IRQ_SPI(x) S5P_IRQ(x+32) |
27 | 25 | ||
28 | #define IRQ_MCT1 IRQ_SPI(35) | 26 | #define IRQ_EINT0 IRQ_SPI(16) |
29 | 27 | #define IRQ_EINT1 IRQ_SPI(17) | |
30 | #define IRQ_EINT0 IRQ_SPI(40) | 28 | #define IRQ_EINT2 IRQ_SPI(18) |
31 | #define IRQ_EINT1 IRQ_SPI(41) | 29 | #define IRQ_EINT3 IRQ_SPI(19) |
32 | #define IRQ_EINT2 IRQ_SPI(42) | 30 | #define IRQ_EINT4 IRQ_SPI(20) |
33 | #define IRQ_EINT3 IRQ_SPI(43) | 31 | #define IRQ_EINT5 IRQ_SPI(21) |
34 | #define IRQ_USB_HSOTG IRQ_SPI(44) | 32 | #define IRQ_EINT6 IRQ_SPI(22) |
35 | #define IRQ_USB_HOST IRQ_SPI(45) | 33 | #define IRQ_EINT7 IRQ_SPI(23) |
36 | #define IRQ_MODEM_IF IRQ_SPI(46) | 34 | #define IRQ_EINT8 IRQ_SPI(24) |
37 | #define IRQ_ROTATOR IRQ_SPI(47) | 35 | #define IRQ_EINT9 IRQ_SPI(25) |
38 | #define IRQ_JPEG IRQ_SPI(48) | 36 | #define IRQ_EINT10 IRQ_SPI(26) |
39 | #define IRQ_2D IRQ_SPI(49) | 37 | #define IRQ_EINT11 IRQ_SPI(27) |
40 | #define IRQ_PCIE IRQ_SPI(50) | 38 | #define IRQ_EINT12 IRQ_SPI(28) |
41 | #define IRQ_MCT0 IRQ_SPI(51) | 39 | #define IRQ_EINT13 IRQ_SPI(29) |
42 | #define IRQ_MFC IRQ_SPI(52) | 40 | #define IRQ_EINT14 IRQ_SPI(30) |
43 | #define IRQ_AUDIO_SS IRQ_SPI(54) | 41 | #define IRQ_EINT15 IRQ_SPI(31) |
44 | #define IRQ_AC97 IRQ_SPI(55) | 42 | #define IRQ_EINT16_31 IRQ_SPI(32) |
45 | #define IRQ_SPDIF IRQ_SPI(56) | 43 | |
46 | #define IRQ_KEYPAD IRQ_SPI(57) | 44 | #define IRQ_PDMA0 IRQ_SPI(35) |
47 | #define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58) | 45 | #define IRQ_PDMA1 IRQ_SPI(36) |
48 | #define IRQ_SLIMBUS IRQ_SPI(59) | 46 | #define IRQ_TIMER0_VIC IRQ_SPI(37) |
49 | #define IRQ_PMU IRQ_SPI(60) | 47 | #define IRQ_TIMER1_VIC IRQ_SPI(38) |
50 | #define IRQ_TSI IRQ_SPI(61) | 48 | #define IRQ_TIMER2_VIC IRQ_SPI(39) |
51 | #define IRQ_SATA IRQ_SPI(62) | 49 | #define IRQ_TIMER3_VIC IRQ_SPI(40) |
52 | #define IRQ_GPS IRQ_SPI(63) | 50 | #define IRQ_TIMER4_VIC IRQ_SPI(41) |
51 | #define IRQ_MCT_L0 IRQ_SPI(42) | ||
52 | #define IRQ_WDT IRQ_SPI(43) | ||
53 | #define IRQ_RTC_ALARM IRQ_SPI(44) | ||
54 | #define IRQ_RTC_TIC IRQ_SPI(45) | ||
55 | #define IRQ_GPIO_XB IRQ_SPI(46) | ||
56 | #define IRQ_GPIO_XA IRQ_SPI(47) | ||
57 | #define IRQ_MCT_L1 IRQ_SPI(48) | ||
58 | |||
59 | #define IRQ_UART0 IRQ_SPI(52) | ||
60 | #define IRQ_UART1 IRQ_SPI(53) | ||
61 | #define IRQ_UART2 IRQ_SPI(54) | ||
62 | #define IRQ_UART3 IRQ_SPI(55) | ||
63 | #define IRQ_UART4 IRQ_SPI(56) | ||
64 | #define IRQ_MCT_G0 IRQ_SPI(57) | ||
65 | #define IRQ_IIC IRQ_SPI(58) | ||
66 | #define IRQ_IIC1 IRQ_SPI(59) | ||
67 | #define IRQ_IIC2 IRQ_SPI(60) | ||
68 | #define IRQ_IIC3 IRQ_SPI(61) | ||
69 | #define IRQ_IIC4 IRQ_SPI(62) | ||
70 | #define IRQ_IIC5 IRQ_SPI(63) | ||
71 | #define IRQ_IIC6 IRQ_SPI(64) | ||
72 | #define IRQ_IIC7 IRQ_SPI(65) | ||
73 | |||
74 | #define IRQ_USB_HOST IRQ_SPI(70) | ||
75 | #define IRQ_USB_HSOTG IRQ_SPI(71) | ||
76 | #define IRQ_MODEM_IF IRQ_SPI(72) | ||
77 | #define IRQ_HSMMC0 IRQ_SPI(73) | ||
78 | #define IRQ_HSMMC1 IRQ_SPI(74) | ||
79 | #define IRQ_HSMMC2 IRQ_SPI(75) | ||
80 | #define IRQ_HSMMC3 IRQ_SPI(76) | ||
81 | #define IRQ_DWMCI IRQ_SPI(77) | ||
82 | |||
83 | #define IRQ_MIPICSI0 IRQ_SPI(78) | ||
84 | |||
85 | #define IRQ_MIPICSI1 IRQ_SPI(80) | ||
86 | |||
87 | #define IRQ_ONENAND_AUDI IRQ_SPI(82) | ||
88 | #define IRQ_ROTATOR IRQ_SPI(83) | ||
89 | #define IRQ_FIMC0 IRQ_SPI(84) | ||
90 | #define IRQ_FIMC1 IRQ_SPI(85) | ||
91 | #define IRQ_FIMC2 IRQ_SPI(86) | ||
92 | #define IRQ_FIMC3 IRQ_SPI(87) | ||
93 | #define IRQ_JPEG IRQ_SPI(88) | ||
94 | #define IRQ_2D IRQ_SPI(89) | ||
95 | #define IRQ_PCIE IRQ_SPI(90) | ||
96 | |||
97 | #define IRQ_MFC IRQ_SPI(94) | ||
98 | |||
99 | #define IRQ_AUDIO_SS IRQ_SPI(96) | ||
100 | #define IRQ_I2S0 IRQ_SPI(97) | ||
101 | #define IRQ_I2S1 IRQ_SPI(98) | ||
102 | #define IRQ_I2S2 IRQ_SPI(99) | ||
103 | #define IRQ_AC97 IRQ_SPI(100) | ||
104 | |||
105 | #define IRQ_SPDIF IRQ_SPI(104) | ||
106 | #define IRQ_ADC0 IRQ_SPI(105) | ||
107 | #define IRQ_PEN0 IRQ_SPI(106) | ||
108 | #define IRQ_ADC1 IRQ_SPI(107) | ||
109 | #define IRQ_PEN1 IRQ_SPI(108) | ||
110 | #define IRQ_KEYPAD IRQ_SPI(109) | ||
111 | #define IRQ_PMU IRQ_SPI(110) | ||
112 | #define IRQ_GPS IRQ_SPI(111) | ||
113 | #define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) | ||
114 | #define IRQ_SLIMBUS IRQ_SPI(113) | ||
115 | |||
116 | #define IRQ_TSI IRQ_SPI(115) | ||
117 | #define IRQ_SATA IRQ_SPI(116) | ||
53 | 118 | ||
54 | #define MAX_IRQ_IN_COMBINER 8 | 119 | #define MAX_IRQ_IN_COMBINER 8 |
55 | #define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) | 120 | #define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) |
56 | #define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) | 121 | #define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) |
57 | 122 | ||
58 | #define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) | 123 | #define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) |
@@ -73,75 +138,14 @@ | |||
73 | #define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) | 138 | #define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) |
74 | #define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) | 139 | #define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) |
75 | 140 | ||
76 | #define IRQ_PDMA0 COMBINER_IRQ(21, 0) | 141 | #define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) |
77 | #define IRQ_PDMA1 COMBINER_IRQ(21, 1) | 142 | #define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) |
78 | 143 | #define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) | |
79 | #define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0) | ||
80 | #define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1) | ||
81 | #define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2) | ||
82 | #define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3) | ||
83 | #define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4) | ||
84 | |||
85 | #define IRQ_RTC_ALARM COMBINER_IRQ(23, 0) | ||
86 | #define IRQ_RTC_TIC COMBINER_IRQ(23, 1) | ||
87 | |||
88 | #define IRQ_GPIO_XB COMBINER_IRQ(24, 0) | ||
89 | #define IRQ_GPIO_XA COMBINER_IRQ(24, 1) | ||
90 | |||
91 | #define IRQ_UART0 COMBINER_IRQ(26, 0) | ||
92 | #define IRQ_UART1 COMBINER_IRQ(26, 1) | ||
93 | #define IRQ_UART2 COMBINER_IRQ(26, 2) | ||
94 | #define IRQ_UART3 COMBINER_IRQ(26, 3) | ||
95 | #define IRQ_UART4 COMBINER_IRQ(26, 4) | ||
96 | |||
97 | #define IRQ_IIC COMBINER_IRQ(27, 0) | ||
98 | #define IRQ_IIC1 COMBINER_IRQ(27, 1) | ||
99 | #define IRQ_IIC2 COMBINER_IRQ(27, 2) | ||
100 | #define IRQ_IIC3 COMBINER_IRQ(27, 3) | ||
101 | #define IRQ_IIC4 COMBINER_IRQ(27, 4) | ||
102 | #define IRQ_IIC5 COMBINER_IRQ(27, 5) | ||
103 | #define IRQ_IIC6 COMBINER_IRQ(27, 6) | ||
104 | #define IRQ_IIC7 COMBINER_IRQ(27, 7) | ||
105 | |||
106 | #define IRQ_HSMMC0 COMBINER_IRQ(29, 0) | ||
107 | #define IRQ_HSMMC1 COMBINER_IRQ(29, 1) | ||
108 | #define IRQ_HSMMC2 COMBINER_IRQ(29, 2) | ||
109 | #define IRQ_HSMMC3 COMBINER_IRQ(29, 3) | ||
110 | |||
111 | #define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0) | ||
112 | #define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1) | ||
113 | |||
114 | #define IRQ_FIMC0 COMBINER_IRQ(32, 0) | ||
115 | #define IRQ_FIMC1 COMBINER_IRQ(32, 1) | ||
116 | #define IRQ_FIMC2 COMBINER_IRQ(33, 0) | ||
117 | #define IRQ_FIMC3 COMBINER_IRQ(33, 1) | ||
118 | |||
119 | #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) | ||
120 | |||
121 | #define IRQ_MCT_L1 COMBINER_IRQ(35, 3) | ||
122 | |||
123 | #define IRQ_EINT4 COMBINER_IRQ(37, 0) | ||
124 | #define IRQ_EINT5 COMBINER_IRQ(37, 1) | ||
125 | #define IRQ_EINT6 COMBINER_IRQ(37, 2) | ||
126 | #define IRQ_EINT7 COMBINER_IRQ(37, 3) | ||
127 | #define IRQ_EINT8 COMBINER_IRQ(38, 0) | ||
128 | |||
129 | #define IRQ_EINT9 COMBINER_IRQ(38, 1) | ||
130 | #define IRQ_EINT10 COMBINER_IRQ(38, 2) | ||
131 | #define IRQ_EINT11 COMBINER_IRQ(38, 3) | ||
132 | #define IRQ_EINT12 COMBINER_IRQ(38, 4) | ||
133 | #define IRQ_EINT13 COMBINER_IRQ(38, 5) | ||
134 | #define IRQ_EINT14 COMBINER_IRQ(38, 6) | ||
135 | #define IRQ_EINT15 COMBINER_IRQ(38, 7) | ||
136 | |||
137 | #define IRQ_EINT16_31 COMBINER_IRQ(39, 0) | ||
138 | |||
139 | #define IRQ_MCT_L0 COMBINER_IRQ(51, 0) | ||
140 | 144 | ||
141 | #define IRQ_WDT COMBINER_IRQ(53, 0) | 145 | #define MAX_COMBINER_NR 16 |
142 | #define IRQ_MCT_G0 COMBINER_IRQ(53, 4) | ||
143 | 146 | ||
144 | #define MAX_COMBINER_NR 54 | 147 | #define IRQ_ADC IRQ_ADC0 |
148 | #define IRQ_TC IRQ_PEN0 | ||
145 | 149 | ||
146 | #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) | 150 | #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) |
147 | 151 | ||
@@ -155,6 +159,6 @@ | |||
155 | #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) | 159 | #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) |
156 | 160 | ||
157 | /* Set the default NR_IRQS */ | 161 | /* Set the default NR_IRQS */ |
158 | #define NR_IRQS (IRQ_GPIO_END) | 162 | #define NR_IRQS (IRQ_GPIO_END + 64) |
159 | 163 | ||
160 | #endif /* __ASM_ARCH_IRQS_H */ | 164 | #endif /* __ASM_ARCH_IRQS_H */ |
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index 0009e77a05fc..d32296dc65e2 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h | |||
@@ -57,12 +57,14 @@ | |||
57 | 57 | ||
58 | #define EXYNOS4_PA_DMC0 0x10400000 | 58 | #define EXYNOS4_PA_DMC0 0x10400000 |
59 | 59 | ||
60 | #define EXYNOS4_PA_COMBINER 0x10448000 | 60 | #define EXYNOS4_PA_COMBINER 0x10440000 |
61 | |||
62 | #define EXYNOS4_PA_GIC_CPU 0x10480000 | ||
63 | #define EXYNOS4_PA_GIC_DIST 0x10490000 | ||
64 | #define EXYNOS4_GIC_BANK_OFFSET 0x8000 | ||
61 | 65 | ||
62 | #define EXYNOS4_PA_COREPERI 0x10500000 | 66 | #define EXYNOS4_PA_COREPERI 0x10500000 |
63 | #define EXYNOS4_PA_GIC_CPU 0x10500100 | ||
64 | #define EXYNOS4_PA_TWD 0x10500600 | 67 | #define EXYNOS4_PA_TWD 0x10500600 |
65 | #define EXYNOS4_PA_GIC_DIST 0x10501000 | ||
66 | #define EXYNOS4_PA_L2CC 0x10502000 | 68 | #define EXYNOS4_PA_L2CC 0x10502000 |
67 | 69 | ||
68 | #define EXYNOS4_PA_MDMA 0x10810000 | 70 | #define EXYNOS4_PA_MDMA 0x10810000 |
@@ -93,7 +95,10 @@ | |||
93 | #define EXYNOS4_PA_MIPI_CSIS0 0x11880000 | 95 | #define EXYNOS4_PA_MIPI_CSIS0 0x11880000 |
94 | #define EXYNOS4_PA_MIPI_CSIS1 0x11890000 | 96 | #define EXYNOS4_PA_MIPI_CSIS1 0x11890000 |
95 | 97 | ||
98 | #define EXYNOS4_PA_FIMD0 0x11C00000 | ||
99 | |||
96 | #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) | 100 | #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) |
101 | #define EXYNOS4_PA_DWMCI 0x12550000 | ||
97 | 102 | ||
98 | #define EXYNOS4_PA_SATA 0x12560000 | 103 | #define EXYNOS4_PA_SATA 0x12560000 |
99 | #define EXYNOS4_PA_SATAPHY 0x125D0000 | 104 | #define EXYNOS4_PA_SATAPHY 0x125D0000 |
@@ -103,11 +108,15 @@ | |||
103 | 108 | ||
104 | #define EXYNOS4_PA_EHCI 0x12580000 | 109 | #define EXYNOS4_PA_EHCI 0x12580000 |
105 | #define EXYNOS4_PA_HSPHY 0x125B0000 | 110 | #define EXYNOS4_PA_HSPHY 0x125B0000 |
111 | #define EXYNOS4_PA_MFC 0x13400000 | ||
106 | 112 | ||
107 | #define EXYNOS4_PA_UART 0x13800000 | 113 | #define EXYNOS4_PA_UART 0x13800000 |
108 | 114 | ||
109 | #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) | 115 | #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) |
110 | 116 | ||
117 | #define EXYNOS4_PA_ADC 0x13910000 | ||
118 | #define EXYNOS4_PA_ADC1 0x13911000 | ||
119 | |||
111 | #define EXYNOS4_PA_AC97 0x139A0000 | 120 | #define EXYNOS4_PA_AC97 0x139A0000 |
112 | 121 | ||
113 | #define EXYNOS4_PA_SPDIF 0x139B0000 | 122 | #define EXYNOS4_PA_SPDIF 0x139B0000 |
@@ -130,6 +139,8 @@ | |||
130 | #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) | 139 | #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) |
131 | #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) | 140 | #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) |
132 | #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) | 141 | #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) |
142 | #define SAMSUNG_PA_ADC EXYNOS4_PA_ADC | ||
143 | #define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 | ||
133 | #define S3C_PA_RTC EXYNOS4_PA_RTC | 144 | #define S3C_PA_RTC EXYNOS4_PA_RTC |
134 | #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG | 145 | #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG |
135 | 146 | ||
@@ -140,10 +151,12 @@ | |||
140 | #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 | 151 | #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 |
141 | #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 | 152 | #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 |
142 | #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 | 153 | #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 |
154 | #define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 | ||
143 | #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND | 155 | #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND |
144 | #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA | 156 | #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA |
145 | #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM | 157 | #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM |
146 | #define S5P_PA_SROMC EXYNOS4_PA_SROMC | 158 | #define S5P_PA_SROMC EXYNOS4_PA_SROMC |
159 | #define S5P_PA_MFC EXYNOS4_PA_MFC | ||
147 | #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON | 160 | #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON |
148 | #define S5P_PA_TIMER EXYNOS4_PA_TIMER | 161 | #define S5P_PA_TIMER EXYNOS4_PA_TIMER |
149 | #define S5P_PA_EHCI EXYNOS4_PA_EHCI | 162 | #define S5P_PA_EHCI EXYNOS4_PA_EHCI |
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h index f26e46bc06ca..1df3b81f96e8 100644 --- a/arch/arm/mach-exynos4/include/mach/pm-core.h +++ b/arch/arm/mach-exynos4/include/mach/pm-core.h | |||
@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, | |||
47 | { | 47 | { |
48 | /* nothing here yet */ | 48 | /* nothing here yet */ |
49 | } | 49 | } |
50 | |||
51 | static inline void s3c_pm_restored_gpios(void) | ||
52 | { | ||
53 | /* nothing here yet */ | ||
54 | } | ||
55 | |||
56 | static inline void s3c_pm_saved_gpios(void) | ||
57 | { | ||
58 | /* nothing here yet */ | ||
59 | } | ||
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h new file mode 100644 index 000000000000..a952904b010e --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/pmu.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/include/mach/pmu.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * EXYNOS4210 - PMU(Power Management Unit) support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_PMU_H | ||
14 | #define __ASM_ARCH_PMU_H __FILE__ | ||
15 | |||
16 | enum sys_powerdown { | ||
17 | SYS_AFTR, | ||
18 | SYS_LPA, | ||
19 | SYS_SLEEP, | ||
20 | NUM_SYS_POWERDOWN, | ||
21 | }; | ||
22 | |||
23 | extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); | ||
24 | |||
25 | #endif /* __ASM_ARCH_PMU_H */ | ||
diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h new file mode 100644 index 000000000000..ca5a8b64218a --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/regs-audss.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/mach-exynos4/include/mach/regs-audss.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Exynos4 Audio SubSystem clock register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __PLAT_REGS_AUDSS_H | ||
14 | #define __PLAT_REGS_AUDSS_H __FILE__ | ||
15 | |||
16 | #define EXYNOS4_AUDSS_INT_MEM (0x03000000) | ||
17 | |||
18 | #endif /* _PLAT_REGS_AUDSS_H */ | ||
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h index 6e311c1157f5..d493fdb422ff 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h | |||
@@ -25,6 +25,9 @@ | |||
25 | #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) | 25 | #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) |
26 | #define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) | 26 | #define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) |
27 | 27 | ||
28 | #define S5P_EPLL_LOCK S5P_CLKREG(0x0C010) | ||
29 | #define S5P_VPLL_LOCK S5P_CLKREG(0x0C020) | ||
30 | |||
28 | #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) | 31 | #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) |
29 | #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) | 32 | #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) |
30 | #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) | 33 | #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) |
@@ -33,7 +36,9 @@ | |||
33 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) | 36 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) |
34 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) | 37 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) |
35 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) | 38 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) |
39 | #define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) | ||
36 | #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) | 40 | #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) |
41 | #define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) | ||
37 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) | 42 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) |
38 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) | 43 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) |
39 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) | 44 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) |
@@ -61,6 +66,7 @@ | |||
61 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) | 66 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) |
62 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) | 67 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) |
63 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) | 68 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) |
69 | #define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) | ||
64 | 70 | ||
65 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) | 71 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) |
66 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) | 72 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) |
@@ -120,6 +126,12 @@ | |||
120 | #define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) | 126 | #define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) |
121 | #define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) | 127 | #define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) |
122 | 128 | ||
129 | #define S5P_EPLLCON0_ENABLE_SHIFT (31) | ||
130 | #define S5P_EPLLCON0_LOCKED_SHIFT (29) | ||
131 | |||
132 | #define S5P_VPLLCON0_ENABLE_SHIFT (31) | ||
133 | #define S5P_VPLLCON0_LOCKED_SHIFT (29) | ||
134 | |||
123 | #define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) | 135 | #define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) |
124 | #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) | 136 | #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) |
125 | 137 | ||
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h index a9643371f8e7..fa49bbb8e7b0 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h | |||
@@ -158,6 +158,7 @@ | |||
158 | #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) | 158 | #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) |
159 | 159 | ||
160 | #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 | 160 | #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 |
161 | #define S5P_CORE_LOCAL_PWR_EN 0x3 | ||
161 | #define S5P_INT_LOCAL_PWR_EN 0x7 | 162 | #define S5P_INT_LOCAL_PWR_EN 0x7 |
162 | 163 | ||
163 | #define S5P_CHECK_SLEEP 0x00000BAD | 164 | #define S5P_CHECK_SLEEP 0x00000BAD |
diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c deleted file mode 100644 index 6bf3d0ab9627..000000000000 --- a/arch/arm/mach-exynos4/localtimer.c +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/localtimer.c | ||
2 | * | ||
3 | * Cloned from linux/arch/arm/mach-realview/localtimer.c | ||
4 | * | ||
5 | * Copyright (C) 2002 ARM Ltd. | ||
6 | * All Rights Reserved | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/clockchips.h> | ||
14 | |||
15 | #include <asm/irq.h> | ||
16 | #include <asm/localtimer.h> | ||
17 | |||
18 | /* | ||
19 | * Setup the local clock events for a CPU. | ||
20 | */ | ||
21 | int __cpuinit local_timer_setup(struct clock_event_device *evt) | ||
22 | { | ||
23 | evt->irq = IRQ_LOCALTIMER; | ||
24 | twd_timer_setup(evt); | ||
25 | return 0; | ||
26 | } | ||
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c index 642702bb5b12..43be71b799cb 100644 --- a/arch/arm/mach-exynos4/mach-nuri.c +++ b/arch/arm/mach-exynos4/mach-nuri.c | |||
@@ -13,10 +13,15 @@ | |||
13 | #include <linux/input.h> | 13 | #include <linux/input.h> |
14 | #include <linux/i2c.h> | 14 | #include <linux/i2c.h> |
15 | #include <linux/i2c/atmel_mxt_ts.h> | 15 | #include <linux/i2c/atmel_mxt_ts.h> |
16 | #include <linux/i2c-gpio.h> | ||
16 | #include <linux/gpio_keys.h> | 17 | #include <linux/gpio_keys.h> |
17 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
19 | #include <linux/power/max8903_charger.h> | ||
20 | #include <linux/power/max17042_battery.h> | ||
18 | #include <linux/regulator/machine.h> | 21 | #include <linux/regulator/machine.h> |
19 | #include <linux/regulator/fixed.h> | 22 | #include <linux/regulator/fixed.h> |
23 | #include <linux/mfd/max8997.h> | ||
24 | #include <linux/mfd/max8997-private.h> | ||
20 | #include <linux/mmc/host.h> | 25 | #include <linux/mmc/host.h> |
21 | #include <linux/fb.h> | 26 | #include <linux/fb.h> |
22 | #include <linux/pwm_backlight.h> | 27 | #include <linux/pwm_backlight.h> |
@@ -26,6 +31,7 @@ | |||
26 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
27 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
28 | 33 | ||
34 | #include <plat/adc.h> | ||
29 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
30 | #include <plat/exynos4.h> | 36 | #include <plat/exynos4.h> |
31 | #include <plat/cpu.h> | 37 | #include <plat/cpu.h> |
@@ -35,6 +41,8 @@ | |||
35 | #include <plat/clock.h> | 41 | #include <plat/clock.h> |
36 | #include <plat/gpio-cfg.h> | 42 | #include <plat/gpio-cfg.h> |
37 | #include <plat/iic.h> | 43 | #include <plat/iic.h> |
44 | #include <plat/mfc.h> | ||
45 | #include <plat/pd.h> | ||
38 | 46 | ||
39 | #include <mach/map.h> | 47 | #include <mach/map.h> |
40 | 48 | ||
@@ -54,6 +62,7 @@ | |||
54 | 62 | ||
55 | enum fixed_regulator_id { | 63 | enum fixed_regulator_id { |
56 | FIXED_REG_ID_MMC = 0, | 64 | FIXED_REG_ID_MMC = 0, |
65 | FIXED_REG_ID_MAX8903, | ||
57 | }; | 66 | }; |
58 | 67 | ||
59 | static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = { | 68 | static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = { |
@@ -344,10 +353,730 @@ static void __init nuri_tsp_init(void) | |||
344 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); | 353 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); |
345 | } | 354 | } |
346 | 355 | ||
356 | static struct regulator_consumer_supply __initdata max8997_ldo1_[] = { | ||
357 | REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */ | ||
358 | }; | ||
359 | static struct regulator_consumer_supply __initdata max8997_ldo3_[] = { | ||
360 | REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ | ||
361 | }; | ||
362 | static struct regulator_consumer_supply __initdata max8997_ldo4_[] = { | ||
363 | REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ | ||
364 | }; | ||
365 | static struct regulator_consumer_supply __initdata max8997_ldo5_[] = { | ||
366 | REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */ | ||
367 | }; | ||
368 | static struct regulator_consumer_supply __initdata max8997_ldo7_[] = { | ||
369 | REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */ | ||
370 | }; | ||
371 | static struct regulator_consumer_supply __initdata max8997_ldo8_[] = { | ||
372 | REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */ | ||
373 | REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */ | ||
374 | }; | ||
375 | static struct regulator_consumer_supply __initdata max8997_ldo11_[] = { | ||
376 | REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */ | ||
377 | }; | ||
378 | static struct regulator_consumer_supply __initdata max8997_ldo12_[] = { | ||
379 | REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */ | ||
380 | }; | ||
381 | static struct regulator_consumer_supply __initdata max8997_ldo13_[] = { | ||
382 | REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */ | ||
383 | }; | ||
384 | static struct regulator_consumer_supply __initdata max8997_ldo14_[] = { | ||
385 | REGULATOR_SUPPLY("inmotor", "max8997-haptic"), | ||
386 | }; | ||
387 | static struct regulator_consumer_supply __initdata max8997_ldo15_[] = { | ||
388 | REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */ | ||
389 | }; | ||
390 | static struct regulator_consumer_supply __initdata max8997_ldo16_[] = { | ||
391 | REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */ | ||
392 | }; | ||
393 | static struct regulator_consumer_supply __initdata max8997_ldo18_[] = { | ||
394 | REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */ | ||
395 | }; | ||
396 | static struct regulator_consumer_supply __initdata max8997_buck1_[] = { | ||
397 | REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ | ||
398 | }; | ||
399 | static struct regulator_consumer_supply __initdata max8997_buck2_[] = { | ||
400 | REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */ | ||
401 | }; | ||
402 | static struct regulator_consumer_supply __initdata max8997_buck3_[] = { | ||
403 | REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */ | ||
404 | }; | ||
405 | static struct regulator_consumer_supply __initdata max8997_buck4_[] = { | ||
406 | REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */ | ||
407 | }; | ||
408 | static struct regulator_consumer_supply __initdata max8997_buck6_[] = { | ||
409 | REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */ | ||
410 | }; | ||
411 | static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = { | ||
412 | REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */ | ||
413 | }; | ||
414 | static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = { | ||
415 | REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */ | ||
416 | }; | ||
417 | |||
418 | static struct regulator_consumer_supply __initdata max8997_charger_[] = { | ||
419 | REGULATOR_SUPPLY("vinchg1", "charger-manager.0"), | ||
420 | }; | ||
421 | static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = { | ||
422 | REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */ | ||
423 | }; | ||
424 | |||
425 | static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = { | ||
426 | REGULATOR_SUPPLY("gps_clk", "bcm4751"), | ||
427 | REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"), | ||
428 | REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"), | ||
429 | }; | ||
430 | |||
431 | static struct regulator_init_data __initdata max8997_ldo1_data = { | ||
432 | .constraints = { | ||
433 | .name = "VADC_3.3V_C210", | ||
434 | .min_uV = 3300000, | ||
435 | .max_uV = 3300000, | ||
436 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
437 | .apply_uV = 1, | ||
438 | .state_mem = { | ||
439 | .disabled = 1, | ||
440 | }, | ||
441 | }, | ||
442 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_), | ||
443 | .consumer_supplies = max8997_ldo1_, | ||
444 | }; | ||
445 | |||
446 | static struct regulator_init_data __initdata max8997_ldo2_data = { | ||
447 | .constraints = { | ||
448 | .name = "VALIVE_1.1V_C210", | ||
449 | .min_uV = 1100000, | ||
450 | .max_uV = 1100000, | ||
451 | .apply_uV = 1, | ||
452 | .always_on = 1, | ||
453 | .state_mem = { | ||
454 | .enabled = 1, | ||
455 | }, | ||
456 | }, | ||
457 | }; | ||
458 | |||
459 | static struct regulator_init_data __initdata max8997_ldo3_data = { | ||
460 | .constraints = { | ||
461 | .name = "VUSB_1.1V_C210", | ||
462 | .min_uV = 1100000, | ||
463 | .max_uV = 1100000, | ||
464 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
465 | .apply_uV = 1, | ||
466 | .state_mem = { | ||
467 | .disabled = 1, | ||
468 | }, | ||
469 | }, | ||
470 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_), | ||
471 | .consumer_supplies = max8997_ldo3_, | ||
472 | }; | ||
473 | |||
474 | static struct regulator_init_data __initdata max8997_ldo4_data = { | ||
475 | .constraints = { | ||
476 | .name = "VMIPI_1.8V", | ||
477 | .min_uV = 1800000, | ||
478 | .max_uV = 1800000, | ||
479 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
480 | .apply_uV = 1, | ||
481 | .state_mem = { | ||
482 | .disabled = 1, | ||
483 | }, | ||
484 | }, | ||
485 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_), | ||
486 | .consumer_supplies = max8997_ldo4_, | ||
487 | }; | ||
488 | |||
489 | static struct regulator_init_data __initdata max8997_ldo5_data = { | ||
490 | .constraints = { | ||
491 | .name = "VHSIC_1.2V_C210", | ||
492 | .min_uV = 1200000, | ||
493 | .max_uV = 1200000, | ||
494 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
495 | .apply_uV = 1, | ||
496 | .state_mem = { | ||
497 | .disabled = 1, | ||
498 | }, | ||
499 | }, | ||
500 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_), | ||
501 | .consumer_supplies = max8997_ldo5_, | ||
502 | }; | ||
503 | |||
504 | static struct regulator_init_data __initdata max8997_ldo6_data = { | ||
505 | .constraints = { | ||
506 | .name = "VCC_1.8V_PDA", | ||
507 | .min_uV = 1800000, | ||
508 | .max_uV = 1800000, | ||
509 | .apply_uV = 1, | ||
510 | .always_on = 1, | ||
511 | .state_mem = { | ||
512 | .enabled = 1, | ||
513 | }, | ||
514 | }, | ||
515 | }; | ||
516 | |||
517 | static struct regulator_init_data __initdata max8997_ldo7_data = { | ||
518 | .constraints = { | ||
519 | .name = "CAM_ISP_1.8V", | ||
520 | .min_uV = 1800000, | ||
521 | .max_uV = 1800000, | ||
522 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
523 | .apply_uV = 1, | ||
524 | .state_mem = { | ||
525 | .disabled = 1, | ||
526 | }, | ||
527 | }, | ||
528 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_), | ||
529 | .consumer_supplies = max8997_ldo7_, | ||
530 | }; | ||
531 | |||
532 | static struct regulator_init_data __initdata max8997_ldo8_data = { | ||
533 | .constraints = { | ||
534 | .name = "VUSB/VDAC_3.3V_C210", | ||
535 | .min_uV = 3300000, | ||
536 | .max_uV = 3300000, | ||
537 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
538 | .apply_uV = 1, | ||
539 | .state_mem = { | ||
540 | .disabled = 1, | ||
541 | }, | ||
542 | }, | ||
543 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_), | ||
544 | .consumer_supplies = max8997_ldo8_, | ||
545 | }; | ||
546 | |||
547 | static struct regulator_init_data __initdata max8997_ldo9_data = { | ||
548 | .constraints = { | ||
549 | .name = "VCC_2.8V_PDA", | ||
550 | .min_uV = 2800000, | ||
551 | .max_uV = 2800000, | ||
552 | .apply_uV = 1, | ||
553 | .always_on = 1, | ||
554 | .state_mem = { | ||
555 | .enabled = 1, | ||
556 | }, | ||
557 | }, | ||
558 | }; | ||
559 | |||
560 | static struct regulator_init_data __initdata max8997_ldo10_data = { | ||
561 | .constraints = { | ||
562 | .name = "VPLL_1.1V_C210", | ||
563 | .min_uV = 1100000, | ||
564 | .max_uV = 1100000, | ||
565 | .apply_uV = 1, | ||
566 | .always_on = 1, | ||
567 | .state_mem = { | ||
568 | .disabled = 1, | ||
569 | }, | ||
570 | }, | ||
571 | }; | ||
572 | |||
573 | static struct regulator_init_data __initdata max8997_ldo11_data = { | ||
574 | .constraints = { | ||
575 | .name = "LVDS_VDD3.3V", | ||
576 | .min_uV = 3300000, | ||
577 | .max_uV = 3300000, | ||
578 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
579 | .apply_uV = 1, | ||
580 | .boot_on = 1, | ||
581 | .state_mem = { | ||
582 | .disabled = 1, | ||
583 | }, | ||
584 | }, | ||
585 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_), | ||
586 | .consumer_supplies = max8997_ldo11_, | ||
587 | }; | ||
588 | |||
589 | static struct regulator_init_data __initdata max8997_ldo12_data = { | ||
590 | .constraints = { | ||
591 | .name = "VT_CAM_1.8V", | ||
592 | .min_uV = 1800000, | ||
593 | .max_uV = 1800000, | ||
594 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
595 | .apply_uV = 1, | ||
596 | .state_mem = { | ||
597 | .disabled = 1, | ||
598 | }, | ||
599 | }, | ||
600 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_), | ||
601 | .consumer_supplies = max8997_ldo12_, | ||
602 | }; | ||
603 | |||
604 | static struct regulator_init_data __initdata max8997_ldo13_data = { | ||
605 | .constraints = { | ||
606 | .name = "VTF_2.8V", | ||
607 | .min_uV = 2800000, | ||
608 | .max_uV = 2800000, | ||
609 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
610 | .apply_uV = 1, | ||
611 | .state_mem = { | ||
612 | .disabled = 1, | ||
613 | }, | ||
614 | }, | ||
615 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_), | ||
616 | .consumer_supplies = max8997_ldo13_, | ||
617 | }; | ||
618 | |||
619 | static struct regulator_init_data __initdata max8997_ldo14_data = { | ||
620 | .constraints = { | ||
621 | .name = "VCC_3.0V_MOTOR", | ||
622 | .min_uV = 3000000, | ||
623 | .max_uV = 3000000, | ||
624 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
625 | .apply_uV = 1, | ||
626 | .state_mem = { | ||
627 | .disabled = 1, | ||
628 | }, | ||
629 | }, | ||
630 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_), | ||
631 | .consumer_supplies = max8997_ldo14_, | ||
632 | }; | ||
633 | |||
634 | static struct regulator_init_data __initdata max8997_ldo15_data = { | ||
635 | .constraints = { | ||
636 | .name = "VTOUCH_ADVV2.8V", | ||
637 | .min_uV = 2800000, | ||
638 | .max_uV = 2800000, | ||
639 | .apply_uV = 1, | ||
640 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
641 | .state_mem = { | ||
642 | .disabled = 1, | ||
643 | }, | ||
644 | }, | ||
645 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_), | ||
646 | .consumer_supplies = max8997_ldo15_, | ||
647 | }; | ||
648 | |||
649 | static struct regulator_init_data __initdata max8997_ldo16_data = { | ||
650 | .constraints = { | ||
651 | .name = "CAM_SENSOR_IO_1.8V", | ||
652 | .min_uV = 1800000, | ||
653 | .max_uV = 1800000, | ||
654 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
655 | .apply_uV = 1, | ||
656 | .state_mem = { | ||
657 | .disabled = 1, | ||
658 | }, | ||
659 | }, | ||
660 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_), | ||
661 | .consumer_supplies = max8997_ldo16_, | ||
662 | }; | ||
663 | |||
664 | static struct regulator_init_data __initdata max8997_ldo18_data = { | ||
665 | .constraints = { | ||
666 | .name = "VTOUCH_VDD2.8V", | ||
667 | .min_uV = 2800000, | ||
668 | .max_uV = 2800000, | ||
669 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
670 | .apply_uV = 1, | ||
671 | .state_mem = { | ||
672 | .disabled = 1, | ||
673 | }, | ||
674 | }, | ||
675 | .num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_), | ||
676 | .consumer_supplies = max8997_ldo18_, | ||
677 | }; | ||
678 | |||
679 | static struct regulator_init_data __initdata max8997_ldo21_data = { | ||
680 | .constraints = { | ||
681 | .name = "VDDQ_M1M2_1.2V", | ||
682 | .min_uV = 1200000, | ||
683 | .max_uV = 1200000, | ||
684 | .apply_uV = 1, | ||
685 | .always_on = 1, | ||
686 | .state_mem = { | ||
687 | .disabled = 1, | ||
688 | }, | ||
689 | }, | ||
690 | }; | ||
691 | |||
692 | static struct regulator_init_data __initdata max8997_buck1_data = { | ||
693 | .constraints = { | ||
694 | .name = "VARM_1.2V_C210", | ||
695 | .min_uV = 900000, | ||
696 | .max_uV = 1350000, | ||
697 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
698 | .always_on = 1, | ||
699 | .state_mem = { | ||
700 | .disabled = 1, | ||
701 | }, | ||
702 | }, | ||
703 | .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_), | ||
704 | .consumer_supplies = max8997_buck1_, | ||
705 | }; | ||
706 | |||
707 | static struct regulator_init_data __initdata max8997_buck2_data = { | ||
708 | .constraints = { | ||
709 | .name = "VINT_1.1V_C210", | ||
710 | .min_uV = 900000, | ||
711 | .max_uV = 1100000, | ||
712 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
713 | .always_on = 1, | ||
714 | .state_mem = { | ||
715 | .disabled = 1, | ||
716 | }, | ||
717 | }, | ||
718 | .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_), | ||
719 | .consumer_supplies = max8997_buck2_, | ||
720 | }; | ||
721 | |||
722 | static struct regulator_init_data __initdata max8997_buck3_data = { | ||
723 | .constraints = { | ||
724 | .name = "VG3D_1.1V_C210", | ||
725 | .min_uV = 900000, | ||
726 | .max_uV = 1100000, | ||
727 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | ||
728 | REGULATOR_CHANGE_STATUS, | ||
729 | .state_mem = { | ||
730 | .disabled = 1, | ||
731 | }, | ||
732 | }, | ||
733 | .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_), | ||
734 | .consumer_supplies = max8997_buck3_, | ||
735 | }; | ||
736 | |||
737 | static struct regulator_init_data __initdata max8997_buck4_data = { | ||
738 | .constraints = { | ||
739 | .name = "CAM_ISP_CORE_1.2V", | ||
740 | .min_uV = 1200000, | ||
741 | .max_uV = 1200000, | ||
742 | .apply_uV = 1, | ||
743 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
744 | .state_mem = { | ||
745 | .disabled = 1, | ||
746 | }, | ||
747 | }, | ||
748 | .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_), | ||
749 | .consumer_supplies = max8997_buck4_, | ||
750 | }; | ||
751 | |||
752 | static struct regulator_init_data __initdata max8997_buck5_data = { | ||
753 | .constraints = { | ||
754 | .name = "VMEM_1.2V_C210", | ||
755 | .min_uV = 1200000, | ||
756 | .max_uV = 1200000, | ||
757 | .apply_uV = 1, | ||
758 | .always_on = 1, | ||
759 | .state_mem = { | ||
760 | .enabled = 1, | ||
761 | }, | ||
762 | }, | ||
763 | }; | ||
764 | |||
765 | static struct regulator_init_data __initdata max8997_buck6_data = { | ||
766 | .constraints = { | ||
767 | .name = "CAM_AF_2.8V", | ||
768 | .min_uV = 2800000, | ||
769 | .max_uV = 2800000, | ||
770 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
771 | .state_mem = { | ||
772 | .disabled = 1, | ||
773 | }, | ||
774 | }, | ||
775 | .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_), | ||
776 | .consumer_supplies = max8997_buck6_, | ||
777 | }; | ||
778 | |||
779 | static struct regulator_init_data __initdata max8997_buck7_data = { | ||
780 | .constraints = { | ||
781 | .name = "VCC_SUB_2.0V", | ||
782 | .min_uV = 2000000, | ||
783 | .max_uV = 2000000, | ||
784 | .apply_uV = 1, | ||
785 | .always_on = 1, | ||
786 | .state_mem = { | ||
787 | .enabled = 1, | ||
788 | }, | ||
789 | }, | ||
790 | }; | ||
791 | |||
792 | static struct regulator_init_data __initdata max8997_32khz_ap_data = { | ||
793 | .constraints = { | ||
794 | .name = "32KHz AP", | ||
795 | .always_on = 1, | ||
796 | .state_mem = { | ||
797 | .enabled = 1, | ||
798 | }, | ||
799 | }, | ||
800 | .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_), | ||
801 | .consumer_supplies = max8997_32khz_ap_, | ||
802 | }; | ||
803 | |||
804 | static struct regulator_init_data __initdata max8997_32khz_cp_data = { | ||
805 | .constraints = { | ||
806 | .name = "32KHz CP", | ||
807 | .state_mem = { | ||
808 | .disabled = 1, | ||
809 | }, | ||
810 | }, | ||
811 | }; | ||
812 | |||
813 | static struct regulator_init_data __initdata max8997_vichg_data = { | ||
814 | .constraints = { | ||
815 | .name = "VICHG", | ||
816 | .state_mem = { | ||
817 | .disabled = 1, | ||
818 | }, | ||
819 | }, | ||
820 | }; | ||
821 | |||
822 | static struct regulator_init_data __initdata max8997_esafeout1_data = { | ||
823 | .constraints = { | ||
824 | .name = "SAFEOUT1", | ||
825 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
826 | .state_mem = { | ||
827 | .disabled = 1, | ||
828 | }, | ||
829 | }, | ||
830 | .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_), | ||
831 | .consumer_supplies = max8997_esafeout1_, | ||
832 | }; | ||
833 | |||
834 | static struct regulator_init_data __initdata max8997_esafeout2_data = { | ||
835 | .constraints = { | ||
836 | .name = "SAFEOUT2", | ||
837 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
838 | .state_mem = { | ||
839 | .disabled = 1, | ||
840 | }, | ||
841 | }, | ||
842 | .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_), | ||
843 | .consumer_supplies = max8997_esafeout2_, | ||
844 | }; | ||
845 | |||
846 | static struct regulator_init_data __initdata max8997_charger_cv_data = { | ||
847 | .constraints = { | ||
848 | .name = "CHARGER_CV", | ||
849 | .min_uV = 4200000, | ||
850 | .max_uV = 4200000, | ||
851 | .apply_uV = 1, | ||
852 | }, | ||
853 | }; | ||
854 | |||
855 | static struct regulator_init_data __initdata max8997_charger_data = { | ||
856 | .constraints = { | ||
857 | .name = "CHARGER", | ||
858 | .min_uA = 200000, | ||
859 | .max_uA = 950000, | ||
860 | .boot_on = 1, | ||
861 | .valid_ops_mask = REGULATOR_CHANGE_STATUS | | ||
862 | REGULATOR_CHANGE_CURRENT, | ||
863 | }, | ||
864 | .num_consumer_supplies = ARRAY_SIZE(max8997_charger_), | ||
865 | .consumer_supplies = max8997_charger_, | ||
866 | }; | ||
867 | |||
868 | static struct regulator_init_data __initdata max8997_charger_topoff_data = { | ||
869 | .constraints = { | ||
870 | .name = "CHARGER TOPOFF", | ||
871 | .min_uA = 50000, | ||
872 | .max_uA = 200000, | ||
873 | .valid_ops_mask = REGULATOR_CHANGE_CURRENT, | ||
874 | }, | ||
875 | .num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_), | ||
876 | .consumer_supplies = max8997_chg_toff_, | ||
877 | }; | ||
878 | |||
879 | static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = { | ||
880 | { MAX8997_LDO1, &max8997_ldo1_data }, | ||
881 | { MAX8997_LDO2, &max8997_ldo2_data }, | ||
882 | { MAX8997_LDO3, &max8997_ldo3_data }, | ||
883 | { MAX8997_LDO4, &max8997_ldo4_data }, | ||
884 | { MAX8997_LDO5, &max8997_ldo5_data }, | ||
885 | { MAX8997_LDO6, &max8997_ldo6_data }, | ||
886 | { MAX8997_LDO7, &max8997_ldo7_data }, | ||
887 | { MAX8997_LDO8, &max8997_ldo8_data }, | ||
888 | { MAX8997_LDO9, &max8997_ldo9_data }, | ||
889 | { MAX8997_LDO10, &max8997_ldo10_data }, | ||
890 | { MAX8997_LDO11, &max8997_ldo11_data }, | ||
891 | { MAX8997_LDO12, &max8997_ldo12_data }, | ||
892 | { MAX8997_LDO13, &max8997_ldo13_data }, | ||
893 | { MAX8997_LDO14, &max8997_ldo14_data }, | ||
894 | { MAX8997_LDO15, &max8997_ldo15_data }, | ||
895 | { MAX8997_LDO16, &max8997_ldo16_data }, | ||
896 | |||
897 | { MAX8997_LDO18, &max8997_ldo18_data }, | ||
898 | { MAX8997_LDO21, &max8997_ldo21_data }, | ||
899 | |||
900 | { MAX8997_BUCK1, &max8997_buck1_data }, | ||
901 | { MAX8997_BUCK2, &max8997_buck2_data }, | ||
902 | { MAX8997_BUCK3, &max8997_buck3_data }, | ||
903 | { MAX8997_BUCK4, &max8997_buck4_data }, | ||
904 | { MAX8997_BUCK5, &max8997_buck5_data }, | ||
905 | { MAX8997_BUCK6, &max8997_buck6_data }, | ||
906 | { MAX8997_BUCK7, &max8997_buck7_data }, | ||
907 | |||
908 | { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data }, | ||
909 | { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data }, | ||
910 | |||
911 | { MAX8997_ENVICHG, &max8997_vichg_data }, | ||
912 | { MAX8997_ESAFEOUT1, &max8997_esafeout1_data }, | ||
913 | { MAX8997_ESAFEOUT2, &max8997_esafeout2_data }, | ||
914 | { MAX8997_CHARGER_CV, &max8997_charger_cv_data }, | ||
915 | { MAX8997_CHARGER, &max8997_charger_data }, | ||
916 | { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data }, | ||
917 | }; | ||
918 | |||
919 | static struct max8997_platform_data __initdata nuri_max8997_pdata = { | ||
920 | .wakeup = 1, | ||
921 | |||
922 | .num_regulators = ARRAY_SIZE(nuri_max8997_regulators), | ||
923 | .regulators = nuri_max8997_regulators, | ||
924 | |||
925 | .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) }, | ||
926 | .buck2_gpiodvs = true, | ||
927 | |||
928 | .buck1_voltage[0] = 1350000, /* 1.35V */ | ||
929 | .buck1_voltage[1] = 1300000, /* 1.3V */ | ||
930 | .buck1_voltage[2] = 1250000, /* 1.25V */ | ||
931 | .buck1_voltage[3] = 1200000, /* 1.2V */ | ||
932 | .buck1_voltage[4] = 1150000, /* 1.15V */ | ||
933 | .buck1_voltage[5] = 1100000, /* 1.1V */ | ||
934 | .buck1_voltage[6] = 1000000, /* 1.0V */ | ||
935 | .buck1_voltage[7] = 950000, /* 0.95V */ | ||
936 | |||
937 | .buck2_voltage[0] = 1100000, /* 1.1V */ | ||
938 | .buck2_voltage[1] = 1000000, /* 1.0V */ | ||
939 | .buck2_voltage[2] = 950000, /* 0.95V */ | ||
940 | .buck2_voltage[3] = 900000, /* 0.9V */ | ||
941 | .buck2_voltage[4] = 1100000, /* 1.1V */ | ||
942 | .buck2_voltage[5] = 1000000, /* 1.0V */ | ||
943 | .buck2_voltage[6] = 950000, /* 0.95V */ | ||
944 | .buck2_voltage[7] = 900000, /* 0.9V */ | ||
945 | |||
946 | .buck5_voltage[0] = 1200000, /* 1.2V */ | ||
947 | .buck5_voltage[1] = 1200000, /* 1.2V */ | ||
948 | .buck5_voltage[2] = 1200000, /* 1.2V */ | ||
949 | .buck5_voltage[3] = 1200000, /* 1.2V */ | ||
950 | .buck5_voltage[4] = 1200000, /* 1.2V */ | ||
951 | .buck5_voltage[5] = 1200000, /* 1.2V */ | ||
952 | .buck5_voltage[6] = 1200000, /* 1.2V */ | ||
953 | .buck5_voltage[7] = 1200000, /* 1.2V */ | ||
954 | }; | ||
955 | |||
347 | /* GPIO I2C 5 (PMIC) */ | 956 | /* GPIO I2C 5 (PMIC) */ |
957 | enum { I2C5_MAX8997 }; | ||
348 | static struct i2c_board_info i2c5_devs[] __initdata = { | 958 | static struct i2c_board_info i2c5_devs[] __initdata = { |
349 | /* max8997, To be updated */ | 959 | [I2C5_MAX8997] = { |
960 | I2C_BOARD_INFO("max8997", 0xCC >> 1), | ||
961 | .platform_data = &nuri_max8997_pdata, | ||
962 | }, | ||
963 | }; | ||
964 | |||
965 | static struct max17042_platform_data nuri_battery_platform_data = { | ||
966 | }; | ||
967 | |||
968 | /* GPIO I2C 9 (Fuel Gauge) */ | ||
969 | static struct i2c_gpio_platform_data i2c9_gpio_data = { | ||
970 | .sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */ | ||
971 | .scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */ | ||
972 | }; | ||
973 | static struct platform_device i2c9_gpio = { | ||
974 | .name = "i2c-gpio", | ||
975 | .id = 9, | ||
976 | .dev = { | ||
977 | .platform_data = &i2c9_gpio_data, | ||
978 | }, | ||
350 | }; | 979 | }; |
980 | enum { I2C9_MAX17042}; | ||
981 | static struct i2c_board_info i2c9_devs[] __initdata = { | ||
982 | [I2C9_MAX17042] = { | ||
983 | I2C_BOARD_INFO("max17042", 0x36), | ||
984 | .platform_data = &nuri_battery_platform_data, | ||
985 | }, | ||
986 | }; | ||
987 | |||
988 | /* MAX8903 Secondary Charger */ | ||
989 | static struct regulator_consumer_supply supplies_max8903[] = { | ||
990 | REGULATOR_SUPPLY("vinchg2", "charger-manager.0"), | ||
991 | }; | ||
992 | |||
993 | static struct regulator_init_data max8903_charger_en_data = { | ||
994 | .constraints = { | ||
995 | .name = "VOUT_CHARGER", | ||
996 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
997 | .boot_on = 1, | ||
998 | }, | ||
999 | .num_consumer_supplies = ARRAY_SIZE(supplies_max8903), | ||
1000 | .consumer_supplies = supplies_max8903, | ||
1001 | }; | ||
1002 | |||
1003 | static struct fixed_voltage_config max8903_charger_en = { | ||
1004 | .supply_name = "VOUT_CHARGER", | ||
1005 | .microvolts = 5000000, /* Assume 5VDC */ | ||
1006 | .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */ | ||
1007 | .enable_high = 0, /* Enable = Low */ | ||
1008 | .enabled_at_boot = 1, | ||
1009 | .init_data = &max8903_charger_en_data, | ||
1010 | }; | ||
1011 | |||
1012 | static struct platform_device max8903_fixed_reg_dev = { | ||
1013 | .name = "reg-fixed-voltage", | ||
1014 | .id = FIXED_REG_ID_MAX8903, | ||
1015 | .dev = { .platform_data = &max8903_charger_en }, | ||
1016 | }; | ||
1017 | |||
1018 | static struct max8903_pdata nuri_max8903 = { | ||
1019 | /* | ||
1020 | * cen: don't control with the driver, let it be | ||
1021 | * controlled by regulator above | ||
1022 | */ | ||
1023 | .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */ | ||
1024 | /* uok, usus: not connected */ | ||
1025 | .chg = EXYNOS4_GPE2(0), /* TA_nCHG */ | ||
1026 | /* flt: vcc_1.8V_pda */ | ||
1027 | .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */ | ||
1028 | |||
1029 | .dc_valid = true, | ||
1030 | .usb_valid = false, /* USB is not wired to MAX8903 */ | ||
1031 | }; | ||
1032 | |||
1033 | static struct platform_device nuri_max8903_device = { | ||
1034 | .name = "max8903-charger", | ||
1035 | .dev = { | ||
1036 | .platform_data = &nuri_max8903, | ||
1037 | }, | ||
1038 | }; | ||
1039 | |||
1040 | static struct device *nuri_cm_devices[] = { | ||
1041 | &s3c_device_i2c5.dev, | ||
1042 | &s3c_device_adc.dev, | ||
1043 | NULL, /* Reserved for UART */ | ||
1044 | NULL, | ||
1045 | }; | ||
1046 | |||
1047 | static void __init nuri_power_init(void) | ||
1048 | { | ||
1049 | int gpio; | ||
1050 | int irq_base = IRQ_GPIO_END + 1; | ||
1051 | int ta_en = 0; | ||
1052 | |||
1053 | nuri_max8997_pdata.irq_base = irq_base; | ||
1054 | irq_base += MAX8997_IRQ_NR; | ||
1055 | |||
1056 | gpio = EXYNOS4_GPX0(7); | ||
1057 | gpio_request(gpio, "AP_PMIC_IRQ"); | ||
1058 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); | ||
1059 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
1060 | |||
1061 | gpio = EXYNOS4_GPX2(3); | ||
1062 | gpio_request(gpio, "FUEL_ALERT"); | ||
1063 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); | ||
1064 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
1065 | |||
1066 | gpio = nuri_max8903.dok; | ||
1067 | gpio_request(gpio, "TA_nCONNECTED"); | ||
1068 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); | ||
1069 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
1070 | ta_en = gpio_get_value(gpio) ? 0 : 1; | ||
1071 | |||
1072 | gpio = nuri_max8903.chg; | ||
1073 | gpio_request(gpio, "TA_nCHG"); | ||
1074 | gpio_direction_input(gpio); | ||
1075 | |||
1076 | gpio = nuri_max8903.dcm; | ||
1077 | gpio_request(gpio, "CURR_ADJ"); | ||
1078 | gpio_direction_output(gpio, ta_en); | ||
1079 | } | ||
351 | 1080 | ||
352 | /* USB EHCI */ | 1081 | /* USB EHCI */ |
353 | static struct s5p_ehci_platdata nuri_ehci_pdata; | 1082 | static struct s5p_ehci_platdata nuri_ehci_pdata; |
@@ -361,6 +1090,7 @@ static void __init nuri_ehci_init(void) | |||
361 | 1090 | ||
362 | static struct platform_device *nuri_devices[] __initdata = { | 1091 | static struct platform_device *nuri_devices[] __initdata = { |
363 | /* Samsung Platform Devices */ | 1092 | /* Samsung Platform Devices */ |
1093 | &s3c_device_i2c5, /* PMIC should initialize first */ | ||
364 | &emmc_fixed_voltage, | 1094 | &emmc_fixed_voltage, |
365 | &s3c_device_hsmmc0, | 1095 | &s3c_device_hsmmc0, |
366 | &s3c_device_hsmmc2, | 1096 | &s3c_device_hsmmc2, |
@@ -369,11 +1099,20 @@ static struct platform_device *nuri_devices[] __initdata = { | |||
369 | &s3c_device_timer[0], | 1099 | &s3c_device_timer[0], |
370 | &s5p_device_ehci, | 1100 | &s5p_device_ehci, |
371 | &s3c_device_i2c3, | 1101 | &s3c_device_i2c3, |
1102 | &i2c9_gpio, | ||
1103 | &s3c_device_adc, | ||
1104 | &s3c_device_rtc, | ||
1105 | &s5p_device_mfc, | ||
1106 | &s5p_device_mfc_l, | ||
1107 | &s5p_device_mfc_r, | ||
1108 | &exynos4_device_pd[PD_MFC], | ||
372 | 1109 | ||
373 | /* NURI Devices */ | 1110 | /* NURI Devices */ |
374 | &nuri_gpio_keys, | 1111 | &nuri_gpio_keys, |
375 | &nuri_lcd_device, | 1112 | &nuri_lcd_device, |
376 | &nuri_backlight_device, | 1113 | &nuri_backlight_device, |
1114 | &max8903_fixed_reg_dev, | ||
1115 | &nuri_max8903_device, | ||
377 | }; | 1116 | }; |
378 | 1117 | ||
379 | static void __init nuri_map_io(void) | 1118 | static void __init nuri_map_io(void) |
@@ -383,21 +1122,32 @@ static void __init nuri_map_io(void) | |||
383 | s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); | 1122 | s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); |
384 | } | 1123 | } |
385 | 1124 | ||
1125 | static void __init nuri_reserve(void) | ||
1126 | { | ||
1127 | s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); | ||
1128 | } | ||
1129 | |||
386 | static void __init nuri_machine_init(void) | 1130 | static void __init nuri_machine_init(void) |
387 | { | 1131 | { |
388 | nuri_sdhci_init(); | 1132 | nuri_sdhci_init(); |
389 | nuri_tsp_init(); | 1133 | nuri_tsp_init(); |
1134 | nuri_power_init(); | ||
390 | 1135 | ||
391 | i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); | 1136 | i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); |
392 | s3c_i2c3_set_platdata(&i2c3_data); | 1137 | s3c_i2c3_set_platdata(&i2c3_data); |
393 | i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); | 1138 | i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); |
1139 | s3c_i2c5_set_platdata(NULL); | ||
1140 | i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7)); | ||
394 | i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); | 1141 | i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); |
1142 | i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3)); | ||
1143 | i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs)); | ||
395 | 1144 | ||
396 | nuri_ehci_init(); | 1145 | nuri_ehci_init(); |
397 | clk_xusbxti.rate = 24000000; | 1146 | clk_xusbxti.rate = 24000000; |
398 | 1147 | ||
399 | /* Last */ | 1148 | /* Last */ |
400 | platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); | 1149 | platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); |
1150 | s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; | ||
401 | } | 1151 | } |
402 | 1152 | ||
403 | MACHINE_START(NURI, "NURI") | 1153 | MACHINE_START(NURI, "NURI") |
@@ -407,4 +1157,5 @@ MACHINE_START(NURI, "NURI") | |||
407 | .map_io = nuri_map_io, | 1157 | .map_io = nuri_map_io, |
408 | .init_machine = nuri_machine_init, | 1158 | .init_machine = nuri_machine_init, |
409 | .timer = &exynos4_timer, | 1159 | .timer = &exynos4_timer, |
1160 | .reserve = &nuri_reserve, | ||
410 | MACHINE_END | 1161 | MACHINE_END |
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c index f606ea75bf43..a7c65e05c1eb 100644 --- a/arch/arm/mach-exynos4/mach-smdkc210.c +++ b/arch/arm/mach-exynos4/mach-smdkc210.c | |||
@@ -9,7 +9,9 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/serial_core.h> | 11 | #include <linux/serial_core.h> |
12 | #include <linux/delay.h> | ||
12 | #include <linux/gpio.h> | 13 | #include <linux/gpio.h> |
14 | #include <linux/lcd.h> | ||
13 | #include <linux/mmc/host.h> | 15 | #include <linux/mmc/host.h> |
14 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
15 | #include <linux/smsc911x.h> | 17 | #include <linux/smsc911x.h> |
@@ -20,11 +22,15 @@ | |||
20 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
21 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
22 | 24 | ||
25 | #include <video/platform_lcd.h> | ||
26 | |||
23 | #include <plat/regs-serial.h> | 27 | #include <plat/regs-serial.h> |
24 | #include <plat/regs-srom.h> | 28 | #include <plat/regs-srom.h> |
29 | #include <plat/regs-fb-v4.h> | ||
25 | #include <plat/exynos4.h> | 30 | #include <plat/exynos4.h> |
26 | #include <plat/cpu.h> | 31 | #include <plat/cpu.h> |
27 | #include <plat/devs.h> | 32 | #include <plat/devs.h> |
33 | #include <plat/fb.h> | ||
28 | #include <plat/sdhci.h> | 34 | #include <plat/sdhci.h> |
29 | #include <plat/iic.h> | 35 | #include <plat/iic.h> |
30 | #include <plat/pd.h> | 36 | #include <plat/pd.h> |
@@ -114,6 +120,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { | |||
114 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | 120 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
115 | }; | 121 | }; |
116 | 122 | ||
123 | static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, | ||
124 | unsigned int power) | ||
125 | { | ||
126 | if (power) { | ||
127 | #if !defined(CONFIG_BACKLIGHT_PWM) | ||
128 | gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0"); | ||
129 | gpio_free(EXYNOS4_GPD0(1)); | ||
130 | #endif | ||
131 | /* fire nRESET on power up */ | ||
132 | gpio_request(EXYNOS4_GPX0(6), "GPX0"); | ||
133 | |||
134 | gpio_direction_output(EXYNOS4_GPX0(6), 1); | ||
135 | mdelay(100); | ||
136 | |||
137 | gpio_set_value(EXYNOS4_GPX0(6), 0); | ||
138 | mdelay(10); | ||
139 | |||
140 | gpio_set_value(EXYNOS4_GPX0(6), 1); | ||
141 | mdelay(10); | ||
142 | |||
143 | gpio_free(EXYNOS4_GPX0(6)); | ||
144 | } else { | ||
145 | #if !defined(CONFIG_BACKLIGHT_PWM) | ||
146 | gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0"); | ||
147 | gpio_free(EXYNOS4_GPD0(1)); | ||
148 | #endif | ||
149 | } | ||
150 | } | ||
151 | |||
152 | static struct plat_lcd_data smdkc210_lcd_lte480wv_data = { | ||
153 | .set_power = lcd_lte480wv_set_power, | ||
154 | }; | ||
155 | |||
156 | static struct platform_device smdkc210_lcd_lte480wv = { | ||
157 | .name = "platform-lcd", | ||
158 | .dev.parent = &s5p_device_fimd0.dev, | ||
159 | .dev.platform_data = &smdkc210_lcd_lte480wv_data, | ||
160 | }; | ||
161 | |||
162 | static struct s3c_fb_pd_win smdkc210_fb_win0 = { | ||
163 | .win_mode = { | ||
164 | .left_margin = 13, | ||
165 | .right_margin = 8, | ||
166 | .upper_margin = 7, | ||
167 | .lower_margin = 5, | ||
168 | .hsync_len = 3, | ||
169 | .vsync_len = 1, | ||
170 | .xres = 800, | ||
171 | .yres = 480, | ||
172 | }, | ||
173 | .max_bpp = 32, | ||
174 | .default_bpp = 24, | ||
175 | }; | ||
176 | |||
177 | static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = { | ||
178 | .win[0] = &smdkc210_fb_win0, | ||
179 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
180 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
181 | .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, | ||
182 | }; | ||
183 | |||
117 | static struct resource smdkc210_smsc911x_resources[] = { | 184 | static struct resource smdkc210_smsc911x_resources[] = { |
118 | [0] = { | 185 | [0] = { |
119 | .start = EXYNOS4_PA_SROM_BANK(1), | 186 | .start = EXYNOS4_PA_SROM_BANK(1), |
@@ -168,6 +235,8 @@ static struct platform_device *smdkc210_devices[] __initdata = { | |||
168 | &exynos4_device_pd[PD_GPS], | 235 | &exynos4_device_pd[PD_GPS], |
169 | &exynos4_device_sysmmu, | 236 | &exynos4_device_sysmmu, |
170 | &samsung_asoc_dma, | 237 | &samsung_asoc_dma, |
238 | &s5p_device_fimd0, | ||
239 | &smdkc210_lcd_lte480wv, | ||
171 | &smdkc210_smsc911x, | 240 | &smdkc210_smsc911x, |
172 | }; | 241 | }; |
173 | 242 | ||
@@ -225,6 +294,7 @@ static void __init smdkc210_machine_init(void) | |||
225 | s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); | 294 | s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); |
226 | 295 | ||
227 | samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data); | 296 | samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data); |
297 | s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata); | ||
228 | 298 | ||
229 | platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); | 299 | platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); |
230 | } | 300 | } |
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index df1107828abd..ea4149556860 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c | |||
@@ -184,9 +184,12 @@ static struct platform_device *smdkv310_devices[] __initdata = { | |||
184 | &exynos4_device_pd[PD_CAM], | 184 | &exynos4_device_pd[PD_CAM], |
185 | &exynos4_device_pd[PD_TV], | 185 | &exynos4_device_pd[PD_TV], |
186 | &exynos4_device_pd[PD_GPS], | 186 | &exynos4_device_pd[PD_GPS], |
187 | &exynos4_device_spdif, | ||
187 | &exynos4_device_sysmmu, | 188 | &exynos4_device_sysmmu, |
188 | &samsung_asoc_dma, | 189 | &samsung_asoc_dma, |
190 | &samsung_asoc_idma, | ||
189 | &smdkv310_smsc911x, | 191 | &smdkv310_smsc911x, |
192 | &exynos4_device_ahci, | ||
190 | }; | 193 | }; |
191 | 194 | ||
192 | static void __init smdkv310_smsc911x_init(void) | 195 | static void __init smdkv310_smsc911x_init(void) |
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c index 97d329fff2cf..0e280d12301e 100644 --- a/arch/arm/mach-exynos4/mach-universal_c210.c +++ b/arch/arm/mach-exynos4/mach-universal_c210.c | |||
@@ -18,6 +18,9 @@ | |||
18 | #include <linux/regulator/fixed.h> | 18 | #include <linux/regulator/fixed.h> |
19 | #include <linux/regulator/max8952.h> | 19 | #include <linux/regulator/max8952.h> |
20 | #include <linux/mmc/host.h> | 20 | #include <linux/mmc/host.h> |
21 | #include <linux/i2c-gpio.h> | ||
22 | #include <linux/i2c/mcs.h> | ||
23 | #include <linux/i2c/atmel_mxt_ts.h> | ||
21 | 24 | ||
22 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
23 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
@@ -27,7 +30,10 @@ | |||
27 | #include <plat/cpu.h> | 30 | #include <plat/cpu.h> |
28 | #include <plat/devs.h> | 31 | #include <plat/devs.h> |
29 | #include <plat/iic.h> | 32 | #include <plat/iic.h> |
33 | #include <plat/gpio-cfg.h> | ||
34 | #include <plat/mfc.h> | ||
30 | #include <plat/sdhci.h> | 35 | #include <plat/sdhci.h> |
36 | #include <plat/pd.h> | ||
31 | 37 | ||
32 | #include <mach/map.h> | 38 | #include <mach/map.h> |
33 | 39 | ||
@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = { | |||
477 | }, | 483 | }, |
478 | }; | 484 | }; |
479 | 485 | ||
486 | /* I2C3 (TSP) */ | ||
487 | static struct mxt_platform_data qt602240_platform_data = { | ||
488 | .x_line = 19, | ||
489 | .y_line = 11, | ||
490 | .x_size = 800, | ||
491 | .y_size = 480, | ||
492 | .blen = 0x11, | ||
493 | .threshold = 0x28, | ||
494 | .voltage = 2800000, /* 2.8V */ | ||
495 | .orient = MXT_DIAGONAL, | ||
496 | }; | ||
497 | |||
498 | static struct i2c_board_info i2c3_devs[] __initdata = { | ||
499 | { | ||
500 | I2C_BOARD_INFO("qt602240_ts", 0x4a), | ||
501 | .platform_data = &qt602240_platform_data, | ||
502 | }, | ||
503 | }; | ||
504 | |||
505 | static void __init universal_tsp_init(void) | ||
506 | { | ||
507 | int gpio; | ||
508 | |||
509 | /* TSP_LDO_ON: XMDMADDR_11 */ | ||
510 | gpio = EXYNOS4_GPE2(3); | ||
511 | gpio_request(gpio, "TSP_LDO_ON"); | ||
512 | gpio_direction_output(gpio, 1); | ||
513 | gpio_export(gpio, 0); | ||
514 | |||
515 | /* TSP_INT: XMDMADDR_7 */ | ||
516 | gpio = EXYNOS4_GPE1(7); | ||
517 | gpio_request(gpio, "TSP_INT"); | ||
518 | |||
519 | s5p_register_gpio_interrupt(gpio); | ||
520 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); | ||
521 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); | ||
522 | i2c3_devs[0].irq = gpio_to_irq(gpio); | ||
523 | } | ||
524 | |||
525 | |||
526 | /* GPIO I2C 12 (3 Touchkey) */ | ||
527 | static uint32_t touchkey_keymap[] = { | ||
528 | /* MCS_KEY_MAP(value, keycode) */ | ||
529 | MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */ | ||
530 | MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */ | ||
531 | }; | ||
532 | |||
533 | static struct mcs_platform_data touchkey_data = { | ||
534 | .keymap = touchkey_keymap, | ||
535 | .keymap_size = ARRAY_SIZE(touchkey_keymap), | ||
536 | .key_maxval = 2, | ||
537 | }; | ||
538 | |||
539 | /* GPIO I2C 3_TOUCH 2.8V */ | ||
540 | #define I2C_GPIO_BUS_12 12 | ||
541 | static struct i2c_gpio_platform_data i2c_gpio12_data = { | ||
542 | .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */ | ||
543 | .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */ | ||
544 | }; | ||
545 | |||
546 | static struct platform_device i2c_gpio12 = { | ||
547 | .name = "i2c-gpio", | ||
548 | .id = I2C_GPIO_BUS_12, | ||
549 | .dev = { | ||
550 | .platform_data = &i2c_gpio12_data, | ||
551 | }, | ||
552 | }; | ||
553 | |||
554 | static struct i2c_board_info i2c_gpio12_devs[] __initdata = { | ||
555 | { | ||
556 | I2C_BOARD_INFO("mcs5080_touchkey", 0x20), | ||
557 | .platform_data = &touchkey_data, | ||
558 | }, | ||
559 | }; | ||
560 | |||
561 | static void __init universal_touchkey_init(void) | ||
562 | { | ||
563 | int gpio; | ||
564 | |||
565 | gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */ | ||
566 | gpio_request(gpio, "3_TOUCH_INT"); | ||
567 | s5p_register_gpio_interrupt(gpio); | ||
568 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); | ||
569 | i2c_gpio12_devs[0].irq = gpio_to_irq(gpio); | ||
570 | |||
571 | gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */ | ||
572 | gpio_request(gpio, "3_TOUCH_EN"); | ||
573 | gpio_direction_output(gpio, 1); | ||
574 | } | ||
575 | |||
480 | /* GPIO KEYS */ | 576 | /* GPIO KEYS */ |
481 | static struct gpio_keys_button universal_gpio_keys_tables[] = { | 577 | static struct gpio_keys_button universal_gpio_keys_tables[] = { |
482 | { | 578 | { |
@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = { | |||
608 | 704 | ||
609 | static struct platform_device *universal_devices[] __initdata = { | 705 | static struct platform_device *universal_devices[] __initdata = { |
610 | /* Samsung Platform Devices */ | 706 | /* Samsung Platform Devices */ |
707 | &s5p_device_fimc0, | ||
708 | &s5p_device_fimc1, | ||
709 | &s5p_device_fimc2, | ||
710 | &s5p_device_fimc3, | ||
611 | &mmc0_fixed_voltage, | 711 | &mmc0_fixed_voltage, |
612 | &s3c_device_hsmmc0, | 712 | &s3c_device_hsmmc0, |
613 | &s3c_device_hsmmc2, | 713 | &s3c_device_hsmmc2, |
614 | &s3c_device_hsmmc3, | 714 | &s3c_device_hsmmc3, |
715 | &s3c_device_i2c3, | ||
615 | &s3c_device_i2c5, | 716 | &s3c_device_i2c5, |
616 | 717 | ||
617 | /* Universal Devices */ | 718 | /* Universal Devices */ |
719 | &i2c_gpio12, | ||
618 | &universal_gpio_keys, | 720 | &universal_gpio_keys, |
619 | &s5p_device_onenand, | 721 | &s5p_device_onenand, |
722 | &s5p_device_mfc, | ||
723 | &s5p_device_mfc_l, | ||
724 | &s5p_device_mfc_r, | ||
725 | &exynos4_device_pd[PD_MFC], | ||
620 | }; | 726 | }; |
621 | 727 | ||
622 | static void __init universal_map_io(void) | 728 | static void __init universal_map_io(void) |
@@ -626,6 +732,11 @@ static void __init universal_map_io(void) | |||
626 | s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); | 732 | s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); |
627 | } | 733 | } |
628 | 734 | ||
735 | static void __init universal_reserve(void) | ||
736 | { | ||
737 | s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); | ||
738 | } | ||
739 | |||
629 | static void __init universal_machine_init(void) | 740 | static void __init universal_machine_init(void) |
630 | { | 741 | { |
631 | universal_sdhci_init(); | 742 | universal_sdhci_init(); |
@@ -633,11 +744,20 @@ static void __init universal_machine_init(void) | |||
633 | i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); | 744 | i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); |
634 | i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); | 745 | i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); |
635 | 746 | ||
747 | universal_tsp_init(); | ||
748 | s3c_i2c3_set_platdata(NULL); | ||
749 | i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); | ||
750 | |||
636 | s3c_i2c5_set_platdata(NULL); | 751 | s3c_i2c5_set_platdata(NULL); |
637 | i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); | 752 | i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); |
638 | 753 | ||
754 | universal_touchkey_init(); | ||
755 | i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs, | ||
756 | ARRAY_SIZE(i2c_gpio12_devs)); | ||
757 | |||
639 | /* Last */ | 758 | /* Last */ |
640 | platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); | 759 | platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); |
760 | s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; | ||
641 | } | 761 | } |
642 | 762 | ||
643 | MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") | 763 | MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") |
@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") | |||
647 | .map_io = universal_map_io, | 767 | .map_io = universal_map_io, |
648 | .init_machine = universal_machine_init, | 768 | .init_machine = universal_machine_init, |
649 | .timer = &exynos4_timer, | 769 | .timer = &exynos4_timer, |
770 | .reserve = &universal_reserve, | ||
650 | MACHINE_END | 771 | MACHINE_END |
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c index 14ac10b7ec02..1ae059b7ad7b 100644 --- a/arch/arm/mach-exynos4/mct.c +++ b/arch/arm/mach-exynos4/mct.c | |||
@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt) | |||
383 | setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); | 383 | setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); |
384 | } else { | 384 | } else { |
385 | mct_tick1_event_irq.dev_id = &mct_tick[cpu]; | 385 | mct_tick1_event_irq.dev_id = &mct_tick[cpu]; |
386 | irq_set_affinity(IRQ_MCT1, cpumask_of(1)); | ||
387 | setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); | 386 | setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); |
387 | irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); | ||
388 | } | 388 | } |
389 | } | 389 | } |
390 | 390 | ||
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c index b68d5bdf04cf..7c2282c6ba81 100644 --- a/arch/arm/mach-exynos4/platsmp.c +++ b/arch/arm/mach-exynos4/platsmp.c | |||
@@ -28,9 +28,12 @@ | |||
28 | 28 | ||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <mach/regs-clock.h> | 30 | #include <mach/regs-clock.h> |
31 | #include <mach/regs-pmu.h> | ||
31 | 32 | ||
32 | extern void exynos4_secondary_startup(void); | 33 | extern void exynos4_secondary_startup(void); |
33 | 34 | ||
35 | #define CPU1_BOOT_REG S5P_VA_SYSRAM | ||
36 | |||
34 | /* | 37 | /* |
35 | * control for which core is the next to come out of the secondary | 38 | * control for which core is the next to come out of the secondary |
36 | * boot "holding pen" | 39 | * boot "holding pen" |
@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void) | |||
58 | 61 | ||
59 | static DEFINE_SPINLOCK(boot_lock); | 62 | static DEFINE_SPINLOCK(boot_lock); |
60 | 63 | ||
64 | static void __cpuinit exynos4_gic_secondary_init(void) | ||
65 | { | ||
66 | void __iomem *dist_base = S5P_VA_GIC_DIST + | ||
67 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | ||
68 | void __iomem *cpu_base = S5P_VA_GIC_CPU + | ||
69 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | ||
70 | int i; | ||
71 | |||
72 | /* | ||
73 | * Deal with the banked PPI and SGI interrupts - disable all | ||
74 | * PPI interrupts, ensure all SGI interrupts are enabled. | ||
75 | */ | ||
76 | __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); | ||
77 | __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); | ||
78 | |||
79 | /* | ||
80 | * Set priority on PPI and SGI interrupts | ||
81 | */ | ||
82 | for (i = 0; i < 32; i += 4) | ||
83 | __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); | ||
84 | |||
85 | __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK); | ||
86 | __raw_writel(1, cpu_base + GIC_CPU_CTRL); | ||
87 | } | ||
88 | |||
61 | void __cpuinit platform_secondary_init(unsigned int cpu) | 89 | void __cpuinit platform_secondary_init(unsigned int cpu) |
62 | { | 90 | { |
63 | /* | 91 | /* |
@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) | |||
65 | * core (e.g. timer irq), then they will not have been enabled | 93 | * core (e.g. timer irq), then they will not have been enabled |
66 | * for us: do so | 94 | * for us: do so |
67 | */ | 95 | */ |
68 | gic_secondary_init(0); | 96 | exynos4_gic_secondary_init(); |
69 | 97 | ||
70 | /* | 98 | /* |
71 | * let the primary processor know we're out of the | 99 | * let the primary processor know we're out of the |
@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
100 | */ | 128 | */ |
101 | write_pen_release(cpu); | 129 | write_pen_release(cpu); |
102 | 130 | ||
131 | if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { | ||
132 | __raw_writel(S5P_CORE_LOCAL_PWR_EN, | ||
133 | S5P_ARM_CORE1_CONFIGURATION); | ||
134 | |||
135 | timeout = 10; | ||
136 | |||
137 | /* wait max 10 ms until cpu1 is on */ | ||
138 | while ((__raw_readl(S5P_ARM_CORE1_STATUS) | ||
139 | & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { | ||
140 | if (timeout-- == 0) | ||
141 | break; | ||
142 | |||
143 | mdelay(1); | ||
144 | } | ||
145 | |||
146 | if (timeout == 0) { | ||
147 | printk(KERN_ERR "cpu1 power enable failed"); | ||
148 | spin_unlock(&boot_lock); | ||
149 | return -ETIMEDOUT; | ||
150 | } | ||
151 | } | ||
103 | /* | 152 | /* |
104 | * Send the secondary CPU a soft interrupt, thereby causing | 153 | * Send the secondary CPU a soft interrupt, thereby causing |
105 | * the boot monitor to read the system wide flags register, | 154 | * the boot monitor to read the system wide flags register, |
106 | * and branch to the address found there. | 155 | * and branch to the address found there. |
107 | */ | 156 | */ |
108 | gic_raise_softirq(cpumask_of(cpu), 1); | ||
109 | 157 | ||
110 | timeout = jiffies + (1 * HZ); | 158 | timeout = jiffies + (1 * HZ); |
111 | while (time_before(jiffies, timeout)) { | 159 | while (time_before(jiffies, timeout)) { |
112 | smp_rmb(); | 160 | smp_rmb(); |
161 | |||
162 | __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), | ||
163 | CPU1_BOOT_REG); | ||
164 | gic_raise_softirq(cpumask_of(cpu), 1); | ||
165 | |||
113 | if (pen_release == -1) | 166 | if (pen_release == -1) |
114 | break; | 167 | break; |
115 | 168 | ||
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 533c28f758ca..bc6ca9482de1 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c | |||
@@ -18,92 +18,23 @@ | |||
18 | #include <linux/suspend.h> | 18 | #include <linux/suspend.h> |
19 | #include <linux/syscore_ops.h> | 19 | #include <linux/syscore_ops.h> |
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | #include <linux/err.h> | ||
22 | #include <linux/clk.h> | ||
21 | 23 | ||
22 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
23 | #include <asm/hardware/cache-l2x0.h> | 25 | #include <asm/hardware/cache-l2x0.h> |
24 | 26 | ||
25 | #include <plat/cpu.h> | 27 | #include <plat/cpu.h> |
26 | #include <plat/pm.h> | 28 | #include <plat/pm.h> |
29 | #include <plat/pll.h> | ||
30 | #include <plat/regs-srom.h> | ||
27 | 31 | ||
28 | #include <mach/regs-irq.h> | 32 | #include <mach/regs-irq.h> |
29 | #include <mach/regs-gpio.h> | 33 | #include <mach/regs-gpio.h> |
30 | #include <mach/regs-clock.h> | 34 | #include <mach/regs-clock.h> |
31 | #include <mach/regs-pmu.h> | 35 | #include <mach/regs-pmu.h> |
32 | #include <mach/pm-core.h> | 36 | #include <mach/pm-core.h> |
33 | 37 | #include <mach/pmu.h> | |
34 | static struct sleep_save exynos4_sleep[] = { | ||
35 | { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, }, | ||
36 | { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, }, | ||
37 | { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, }, | ||
38 | { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, }, | ||
39 | { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, }, | ||
40 | { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, }, | ||
41 | { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, }, | ||
42 | { .reg = S5P_L2_0_LOWPWR , .val = 0x3, }, | ||
43 | { .reg = S5P_L2_1_LOWPWR , .val = 0x3, }, | ||
44 | { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, }, | ||
45 | { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, }, | ||
46 | { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, }, | ||
47 | { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, }, | ||
48 | { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, }, | ||
49 | { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, }, | ||
50 | { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, }, | ||
51 | { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, }, | ||
52 | { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, }, | ||
53 | { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, }, | ||
54 | { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, }, | ||
55 | { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, }, | ||
56 | { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, }, | ||
57 | { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, }, | ||
58 | { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, }, | ||
59 | { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, }, | ||
60 | { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, }, | ||
61 | { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, }, | ||
62 | { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, }, | ||
63 | { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, }, | ||
64 | { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, }, | ||
65 | { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, }, | ||
66 | { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, }, | ||
67 | { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, }, | ||
68 | { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, }, | ||
69 | { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, }, | ||
70 | { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, }, | ||
71 | { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, }, | ||
72 | { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, }, | ||
73 | { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, }, | ||
74 | { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, }, | ||
75 | { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, }, | ||
76 | { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, }, | ||
77 | { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, }, | ||
78 | { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, }, | ||
79 | { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, }, | ||
80 | { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, }, | ||
81 | { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, }, | ||
82 | { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, }, | ||
83 | { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, }, | ||
84 | { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, }, | ||
85 | { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, }, | ||
86 | { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, }, | ||
87 | { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, }, | ||
88 | { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, }, | ||
89 | { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, }, | ||
90 | { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, }, | ||
91 | { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, }, | ||
92 | { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, }, | ||
93 | { .reg = S5P_XXTI_LOWPWR , .val = 0x0, }, | ||
94 | { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, }, | ||
95 | { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, }, | ||
96 | { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, }, | ||
97 | { .reg = S5P_CAM_LOWPWR , .val = 0x0, }, | ||
98 | { .reg = S5P_TV_LOWPWR , .val = 0x0, }, | ||
99 | { .reg = S5P_MFC_LOWPWR , .val = 0x0, }, | ||
100 | { .reg = S5P_G3D_LOWPWR , .val = 0x0, }, | ||
101 | { .reg = S5P_LCD0_LOWPWR , .val = 0x0, }, | ||
102 | { .reg = S5P_LCD1_LOWPWR , .val = 0x0, }, | ||
103 | { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, }, | ||
104 | { .reg = S5P_GPS_LOWPWR , .val = 0x0, }, | ||
105 | { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, }, | ||
106 | }; | ||
107 | 38 | ||
108 | static struct sleep_save exynos4_set_clksrc[] = { | 39 | static struct sleep_save exynos4_set_clksrc[] = { |
109 | { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, | 40 | { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, |
@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = { | |||
118 | { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, | 49 | { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, |
119 | }; | 50 | }; |
120 | 51 | ||
52 | static struct sleep_save exynos4_epll_save[] = { | ||
53 | SAVE_ITEM(S5P_EPLL_CON0), | ||
54 | SAVE_ITEM(S5P_EPLL_CON1), | ||
55 | }; | ||
56 | |||
57 | static struct sleep_save exynos4_vpll_save[] = { | ||
58 | SAVE_ITEM(S5P_VPLL_CON0), | ||
59 | SAVE_ITEM(S5P_VPLL_CON1), | ||
60 | }; | ||
61 | |||
121 | static struct sleep_save exynos4_core_save[] = { | 62 | static struct sleep_save exynos4_core_save[] = { |
122 | /* CMU side */ | 63 | /* CMU side */ |
123 | SAVE_ITEM(S5P_CLKDIV_LEFTBUS), | 64 | SAVE_ITEM(S5P_CLKDIV_LEFTBUS), |
124 | SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), | 65 | SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), |
125 | SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), | 66 | SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), |
126 | SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), | 67 | SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), |
127 | SAVE_ITEM(S5P_EPLL_CON0), | ||
128 | SAVE_ITEM(S5P_EPLL_CON1), | ||
129 | SAVE_ITEM(S5P_VPLL_CON0), | ||
130 | SAVE_ITEM(S5P_VPLL_CON1), | ||
131 | SAVE_ITEM(S5P_CLKSRC_TOP0), | 68 | SAVE_ITEM(S5P_CLKSRC_TOP0), |
132 | SAVE_ITEM(S5P_CLKSRC_TOP1), | 69 | SAVE_ITEM(S5P_CLKSRC_TOP1), |
133 | SAVE_ITEM(S5P_CLKSRC_CAM), | 70 | SAVE_ITEM(S5P_CLKSRC_CAM), |
71 | SAVE_ITEM(S5P_CLKSRC_TV), | ||
134 | SAVE_ITEM(S5P_CLKSRC_MFC), | 72 | SAVE_ITEM(S5P_CLKSRC_MFC), |
73 | SAVE_ITEM(S5P_CLKSRC_G3D), | ||
135 | SAVE_ITEM(S5P_CLKSRC_IMAGE), | 74 | SAVE_ITEM(S5P_CLKSRC_IMAGE), |
136 | SAVE_ITEM(S5P_CLKSRC_LCD0), | 75 | SAVE_ITEM(S5P_CLKSRC_LCD0), |
137 | SAVE_ITEM(S5P_CLKSRC_LCD1), | 76 | SAVE_ITEM(S5P_CLKSRC_LCD1), |
@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = { | |||
158 | SAVE_ITEM(S5P_CLKDIV_PERIL4), | 97 | SAVE_ITEM(S5P_CLKDIV_PERIL4), |
159 | SAVE_ITEM(S5P_CLKDIV_PERIL5), | 98 | SAVE_ITEM(S5P_CLKDIV_PERIL5), |
160 | SAVE_ITEM(S5P_CLKDIV_TOP), | 99 | SAVE_ITEM(S5P_CLKDIV_TOP), |
100 | SAVE_ITEM(S5P_CLKSRC_MASK_TOP), | ||
161 | SAVE_ITEM(S5P_CLKSRC_MASK_CAM), | 101 | SAVE_ITEM(S5P_CLKSRC_MASK_CAM), |
162 | SAVE_ITEM(S5P_CLKSRC_MASK_TV), | 102 | SAVE_ITEM(S5P_CLKSRC_MASK_TV), |
163 | SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), | 103 | SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), |
@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = { | |||
166 | SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), | 106 | SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), |
167 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), | 107 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), |
168 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), | 108 | SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), |
109 | SAVE_ITEM(S5P_CLKDIV2_RATIO), | ||
169 | SAVE_ITEM(S5P_CLKGATE_SCLKCAM), | 110 | SAVE_ITEM(S5P_CLKGATE_SCLKCAM), |
170 | SAVE_ITEM(S5P_CLKGATE_IP_CAM), | 111 | SAVE_ITEM(S5P_CLKGATE_IP_CAM), |
171 | SAVE_ITEM(S5P_CLKGATE_IP_TV), | 112 | SAVE_ITEM(S5P_CLKGATE_IP_TV), |
@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = { | |||
186 | SAVE_ITEM(S5P_CLKGATE_IP_DMC), | 127 | SAVE_ITEM(S5P_CLKGATE_IP_DMC), |
187 | SAVE_ITEM(S5P_CLKSRC_CPU), | 128 | SAVE_ITEM(S5P_CLKSRC_CPU), |
188 | SAVE_ITEM(S5P_CLKDIV_CPU), | 129 | SAVE_ITEM(S5P_CLKDIV_CPU), |
130 | SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), | ||
189 | SAVE_ITEM(S5P_CLKGATE_SCLKCPU), | 131 | SAVE_ITEM(S5P_CLKGATE_SCLKCPU), |
190 | SAVE_ITEM(S5P_CLKGATE_IP_CPU), | 132 | SAVE_ITEM(S5P_CLKGATE_IP_CPU), |
133 | |||
191 | /* GIC side */ | 134 | /* GIC side */ |
192 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), | 135 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), |
193 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), | 136 | SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), |
@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = { | |||
270 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), | 213 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), |
271 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), | 214 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), |
272 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), | 215 | SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), |
216 | |||
217 | /* SROM side */ | ||
218 | SAVE_ITEM(S5P_SROM_BW), | ||
219 | SAVE_ITEM(S5P_SROM_BC0), | ||
220 | SAVE_ITEM(S5P_SROM_BC1), | ||
221 | SAVE_ITEM(S5P_SROM_BC2), | ||
222 | SAVE_ITEM(S5P_SROM_BC3), | ||
273 | }; | 223 | }; |
274 | 224 | ||
275 | static struct sleep_save exynos4_l2cc_save[] = { | 225 | static struct sleep_save exynos4_l2cc_save[] = { |
@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = { | |||
280 | SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), | 230 | SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), |
281 | }; | 231 | }; |
282 | 232 | ||
233 | /* For Cortex-A9 Diagnostic and Power control register */ | ||
234 | static unsigned int save_arm_register[2]; | ||
235 | |||
283 | static int exynos4_cpu_suspend(unsigned long arg) | 236 | static int exynos4_cpu_suspend(unsigned long arg) |
284 | { | 237 | { |
285 | unsigned long tmp; | ||
286 | unsigned long mask = 0xFFFFFFFF; | ||
287 | |||
288 | /* Setting Central Sequence Register for power down mode */ | ||
289 | |||
290 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | ||
291 | tmp &= ~(S5P_CENTRAL_LOWPWR_CFG); | ||
292 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | ||
293 | |||
294 | /* Setting Central Sequence option Register */ | ||
295 | |||
296 | tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); | ||
297 | tmp &= ~(S5P_USE_MASK); | ||
298 | tmp |= S5P_USE_STANDBY_WFI0; | ||
299 | __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); | ||
300 | |||
301 | /* Clear all interrupt pending to avoid early wakeup */ | ||
302 | |||
303 | __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280)); | ||
304 | __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284)); | ||
305 | __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288)); | ||
306 | |||
307 | /* Disable all interrupt */ | ||
308 | |||
309 | __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000)); | ||
310 | __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000)); | ||
311 | __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184)); | ||
312 | __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188)); | ||
313 | |||
314 | outer_flush_all(); | 238 | outer_flush_all(); |
315 | 239 | ||
316 | /* issue the standby signal into the pm unit. */ | 240 | /* issue the standby signal into the pm unit. */ |
@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void) | |||
326 | 250 | ||
327 | s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); | 251 | s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); |
328 | s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); | 252 | s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); |
253 | s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); | ||
254 | s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); | ||
329 | 255 | ||
330 | tmp = __raw_readl(S5P_INFORM1); | 256 | tmp = __raw_readl(S5P_INFORM1); |
331 | 257 | ||
332 | /* Set value of power down register for sleep mode */ | 258 | /* Set value of power down register for sleep mode */ |
333 | 259 | ||
334 | s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep)); | 260 | exynos4_sys_powerdown_conf(SYS_SLEEP); |
335 | __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); | 261 | __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); |
336 | 262 | ||
337 | /* ensure at least INFORM0 has the resume address */ | 263 | /* ensure at least INFORM0 has the resume address */ |
@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base) | |||
373 | flush_cache_all(); | 299 | flush_cache_all(); |
374 | } | 300 | } |
375 | 301 | ||
302 | static unsigned long pll_base_rate; | ||
303 | |||
304 | static void exynos4_restore_pll(void) | ||
305 | { | ||
306 | unsigned long pll_con, locktime, lockcnt; | ||
307 | unsigned long pll_in_rate; | ||
308 | unsigned int p_div, epll_wait = 0, vpll_wait = 0; | ||
309 | |||
310 | if (pll_base_rate == 0) | ||
311 | return; | ||
312 | |||
313 | pll_in_rate = pll_base_rate; | ||
314 | |||
315 | /* EPLL */ | ||
316 | pll_con = exynos4_epll_save[0].val; | ||
317 | |||
318 | if (pll_con & (1 << 31)) { | ||
319 | pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT); | ||
320 | p_div = (pll_con >> PLL46XX_PDIV_SHIFT); | ||
321 | |||
322 | pll_in_rate /= 1000000; | ||
323 | |||
324 | locktime = (3000 / pll_in_rate) * p_div; | ||
325 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | ||
326 | |||
327 | __raw_writel(lockcnt, S5P_EPLL_LOCK); | ||
328 | |||
329 | s3c_pm_do_restore_core(exynos4_epll_save, | ||
330 | ARRAY_SIZE(exynos4_epll_save)); | ||
331 | epll_wait = 1; | ||
332 | } | ||
333 | |||
334 | pll_in_rate = pll_base_rate; | ||
335 | |||
336 | /* VPLL */ | ||
337 | pll_con = exynos4_vpll_save[0].val; | ||
338 | |||
339 | if (pll_con & (1 << 31)) { | ||
340 | pll_in_rate /= 1000000; | ||
341 | /* 750us */ | ||
342 | locktime = 750; | ||
343 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | ||
344 | |||
345 | __raw_writel(lockcnt, S5P_VPLL_LOCK); | ||
346 | |||
347 | s3c_pm_do_restore_core(exynos4_vpll_save, | ||
348 | ARRAY_SIZE(exynos4_vpll_save)); | ||
349 | vpll_wait = 1; | ||
350 | } | ||
351 | |||
352 | /* Wait PLL locking */ | ||
353 | |||
354 | do { | ||
355 | if (epll_wait) { | ||
356 | pll_con = __raw_readl(S5P_EPLL_CON0); | ||
357 | if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT)) | ||
358 | epll_wait = 0; | ||
359 | } | ||
360 | |||
361 | if (vpll_wait) { | ||
362 | pll_con = __raw_readl(S5P_VPLL_CON0); | ||
363 | if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT)) | ||
364 | vpll_wait = 0; | ||
365 | } | ||
366 | } while (epll_wait || vpll_wait); | ||
367 | } | ||
368 | |||
376 | static struct sysdev_driver exynos4_pm_driver = { | 369 | static struct sysdev_driver exynos4_pm_driver = { |
377 | .add = exynos4_pm_add, | 370 | .add = exynos4_pm_add, |
378 | }; | 371 | }; |
379 | 372 | ||
380 | static __init int exynos4_pm_drvinit(void) | 373 | static __init int exynos4_pm_drvinit(void) |
381 | { | 374 | { |
375 | struct clk *pll_base; | ||
382 | unsigned int tmp; | 376 | unsigned int tmp; |
383 | 377 | ||
384 | s3c_pm_init(); | 378 | s3c_pm_init(); |
@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void) | |||
389 | tmp |= ((0xFF << 8) | (0x1F << 1)); | 383 | tmp |= ((0xFF << 8) | (0x1F << 1)); |
390 | __raw_writel(tmp, S5P_WAKEUP_MASK); | 384 | __raw_writel(tmp, S5P_WAKEUP_MASK); |
391 | 385 | ||
386 | pll_base = clk_get(NULL, "xtal"); | ||
387 | |||
388 | if (!IS_ERR(pll_base)) { | ||
389 | pll_base_rate = clk_get_rate(pll_base); | ||
390 | clk_put(pll_base); | ||
391 | } | ||
392 | |||
392 | return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); | 393 | return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); |
393 | } | 394 | } |
394 | arch_initcall(exynos4_pm_drvinit); | 395 | arch_initcall(exynos4_pm_drvinit); |
395 | 396 | ||
397 | static int exynos4_pm_suspend(void) | ||
398 | { | ||
399 | unsigned long tmp; | ||
400 | |||
401 | /* Setting Central Sequence Register for power down mode */ | ||
402 | |||
403 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | ||
404 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | ||
405 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | ||
406 | |||
407 | /* Save Power control register */ | ||
408 | asm ("mrc p15, 0, %0, c15, c0, 0" | ||
409 | : "=r" (tmp) : : "cc"); | ||
410 | save_arm_register[0] = tmp; | ||
411 | |||
412 | /* Save Diagnostic register */ | ||
413 | asm ("mrc p15, 0, %0, c15, c0, 1" | ||
414 | : "=r" (tmp) : : "cc"); | ||
415 | save_arm_register[1] = tmp; | ||
416 | |||
417 | return 0; | ||
418 | } | ||
419 | |||
396 | static void exynos4_pm_resume(void) | 420 | static void exynos4_pm_resume(void) |
397 | { | 421 | { |
422 | unsigned long tmp; | ||
423 | |||
424 | /* | ||
425 | * If PMU failed while entering sleep mode, WFI will be | ||
426 | * ignored by PMU and then exiting cpu_do_idle(). | ||
427 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically | ||
428 | * in this situation. | ||
429 | */ | ||
430 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | ||
431 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { | ||
432 | tmp |= S5P_CENTRAL_LOWPWR_CFG; | ||
433 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | ||
434 | /* No need to perform below restore code */ | ||
435 | goto early_wakeup; | ||
436 | } | ||
437 | /* Restore Power control register */ | ||
438 | tmp = save_arm_register[0]; | ||
439 | asm volatile ("mcr p15, 0, %0, c15, c0, 0" | ||
440 | : : "r" (tmp) | ||
441 | : "cc"); | ||
442 | |||
443 | /* Restore Diagnostic register */ | ||
444 | tmp = save_arm_register[1]; | ||
445 | asm volatile ("mcr p15, 0, %0, c15, c0, 1" | ||
446 | : : "r" (tmp) | ||
447 | : "cc"); | ||
448 | |||
398 | /* For release retention */ | 449 | /* For release retention */ |
399 | 450 | ||
400 | __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); | 451 | __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); |
@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void) | |||
407 | 458 | ||
408 | s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); | 459 | s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); |
409 | 460 | ||
461 | exynos4_restore_pll(); | ||
462 | |||
410 | exynos4_scu_enable(S5P_VA_SCU); | 463 | exynos4_scu_enable(S5P_VA_SCU); |
411 | 464 | ||
412 | #ifdef CONFIG_CACHE_L2X0 | 465 | #ifdef CONFIG_CACHE_L2X0 |
@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void) | |||
415 | /* enable L2X0*/ | 468 | /* enable L2X0*/ |
416 | writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); | 469 | writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); |
417 | #endif | 470 | #endif |
471 | |||
472 | early_wakeup: | ||
473 | return; | ||
418 | } | 474 | } |
419 | 475 | ||
420 | static struct syscore_ops exynos4_pm_syscore_ops = { | 476 | static struct syscore_ops exynos4_pm_syscore_ops = { |
477 | .suspend = exynos4_pm_suspend, | ||
421 | .resume = exynos4_pm_resume, | 478 | .resume = exynos4_pm_resume, |
422 | }; | 479 | }; |
423 | 480 | ||
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c new file mode 100644 index 000000000000..7ea9eb2a20d2 --- /dev/null +++ b/arch/arm/mach-exynos4/pmu.c | |||
@@ -0,0 +1,175 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/pmu.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * EXYNOS4210 - CPU PMU(Power Management Unit) support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/io.h> | ||
14 | #include <linux/kernel.h> | ||
15 | |||
16 | #include <mach/regs-clock.h> | ||
17 | #include <mach/pmu.h> | ||
18 | |||
19 | static void __iomem *sys_powerdown_reg[] = { | ||
20 | S5P_ARM_CORE0_LOWPWR, | ||
21 | S5P_DIS_IRQ_CORE0, | ||
22 | S5P_DIS_IRQ_CENTRAL0, | ||
23 | S5P_ARM_CORE1_LOWPWR, | ||
24 | S5P_DIS_IRQ_CORE1, | ||
25 | S5P_DIS_IRQ_CENTRAL1, | ||
26 | S5P_ARM_COMMON_LOWPWR, | ||
27 | S5P_L2_0_LOWPWR, | ||
28 | S5P_L2_1_LOWPWR, | ||
29 | S5P_CMU_ACLKSTOP_LOWPWR, | ||
30 | S5P_CMU_SCLKSTOP_LOWPWR, | ||
31 | S5P_CMU_RESET_LOWPWR, | ||
32 | S5P_APLL_SYSCLK_LOWPWR, | ||
33 | S5P_MPLL_SYSCLK_LOWPWR, | ||
34 | S5P_VPLL_SYSCLK_LOWPWR, | ||
35 | S5P_EPLL_SYSCLK_LOWPWR, | ||
36 | S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, | ||
37 | S5P_CMU_RESET_GPSALIVE_LOWPWR, | ||
38 | S5P_CMU_CLKSTOP_CAM_LOWPWR, | ||
39 | S5P_CMU_CLKSTOP_TV_LOWPWR, | ||
40 | S5P_CMU_CLKSTOP_MFC_LOWPWR, | ||
41 | S5P_CMU_CLKSTOP_G3D_LOWPWR, | ||
42 | S5P_CMU_CLKSTOP_LCD0_LOWPWR, | ||
43 | S5P_CMU_CLKSTOP_LCD1_LOWPWR, | ||
44 | S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, | ||
45 | S5P_CMU_CLKSTOP_GPS_LOWPWR, | ||
46 | S5P_CMU_RESET_CAM_LOWPWR, | ||
47 | S5P_CMU_RESET_TV_LOWPWR, | ||
48 | S5P_CMU_RESET_MFC_LOWPWR, | ||
49 | S5P_CMU_RESET_G3D_LOWPWR, | ||
50 | S5P_CMU_RESET_LCD0_LOWPWR, | ||
51 | S5P_CMU_RESET_LCD1_LOWPWR, | ||
52 | S5P_CMU_RESET_MAUDIO_LOWPWR, | ||
53 | S5P_CMU_RESET_GPS_LOWPWR, | ||
54 | S5P_TOP_BUS_LOWPWR, | ||
55 | S5P_TOP_RETENTION_LOWPWR, | ||
56 | S5P_TOP_PWR_LOWPWR, | ||
57 | S5P_LOGIC_RESET_LOWPWR, | ||
58 | S5P_ONENAND_MEM_LOWPWR, | ||
59 | S5P_MODIMIF_MEM_LOWPWR, | ||
60 | S5P_G2D_ACP_MEM_LOWPWR, | ||
61 | S5P_USBOTG_MEM_LOWPWR, | ||
62 | S5P_HSMMC_MEM_LOWPWR, | ||
63 | S5P_CSSYS_MEM_LOWPWR, | ||
64 | S5P_SECSS_MEM_LOWPWR, | ||
65 | S5P_PCIE_MEM_LOWPWR, | ||
66 | S5P_SATA_MEM_LOWPWR, | ||
67 | S5P_PAD_RETENTION_DRAM_LOWPWR, | ||
68 | S5P_PAD_RETENTION_MAUDIO_LOWPWR, | ||
69 | S5P_PAD_RETENTION_GPIO_LOWPWR, | ||
70 | S5P_PAD_RETENTION_UART_LOWPWR, | ||
71 | S5P_PAD_RETENTION_MMCA_LOWPWR, | ||
72 | S5P_PAD_RETENTION_MMCB_LOWPWR, | ||
73 | S5P_PAD_RETENTION_EBIA_LOWPWR, | ||
74 | S5P_PAD_RETENTION_EBIB_LOWPWR, | ||
75 | S5P_PAD_RETENTION_ISOLATION_LOWPWR, | ||
76 | S5P_PAD_RETENTION_ALV_SEL_LOWPWR, | ||
77 | S5P_XUSBXTI_LOWPWR, | ||
78 | S5P_XXTI_LOWPWR, | ||
79 | S5P_EXT_REGULATOR_LOWPWR, | ||
80 | S5P_GPIO_MODE_LOWPWR, | ||
81 | S5P_GPIO_MODE_MAUDIO_LOWPWR, | ||
82 | S5P_CAM_LOWPWR, | ||
83 | S5P_TV_LOWPWR, | ||
84 | S5P_MFC_LOWPWR, | ||
85 | S5P_G3D_LOWPWR, | ||
86 | S5P_LCD0_LOWPWR, | ||
87 | S5P_LCD1_LOWPWR, | ||
88 | S5P_MAUDIO_LOWPWR, | ||
89 | S5P_GPS_LOWPWR, | ||
90 | S5P_GPS_ALIVE_LOWPWR, | ||
91 | }; | ||
92 | |||
93 | static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = { | ||
94 | /* { AFTR, LPA, SLEEP }*/ | ||
95 | { 0, 0, 2 }, /* ARM_CORE0 */ | ||
96 | { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */ | ||
97 | { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */ | ||
98 | { 0, 0, 2 }, /* ARM_CORE1 */ | ||
99 | { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */ | ||
100 | { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */ | ||
101 | { 0, 0, 2 }, /* ARM_COMMON */ | ||
102 | { 2, 2, 3 }, /* ARM_CPU_L2_0 */ | ||
103 | { 2, 2, 3 }, /* ARM_CPU_L2_1 */ | ||
104 | { 1, 0, 0 }, /* CMU_ACLKSTOP */ | ||
105 | { 1, 0, 0 }, /* CMU_SCLKSTOP */ | ||
106 | { 1, 1, 0 }, /* CMU_RESET */ | ||
107 | { 1, 0, 0 }, /* APLL_SYSCLK */ | ||
108 | { 1, 0, 0 }, /* MPLL_SYSCLK */ | ||
109 | { 1, 0, 0 }, /* VPLL_SYSCLK */ | ||
110 | { 1, 1, 0 }, /* EPLL_SYSCLK */ | ||
111 | { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */ | ||
112 | { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */ | ||
113 | { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */ | ||
114 | { 1, 1, 0 }, /* CMU_CLKSTOP_TV */ | ||
115 | { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */ | ||
116 | { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */ | ||
117 | { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */ | ||
118 | { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */ | ||
119 | { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */ | ||
120 | { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */ | ||
121 | { 1, 1, 0 }, /* CMU_RESET_CAM */ | ||
122 | { 1, 1, 0 }, /* CMU_RESET_TV */ | ||
123 | { 1, 1, 0 }, /* CMU_RESET_MFC */ | ||
124 | { 1, 1, 0 }, /* CMU_RESET_G3D */ | ||
125 | { 1, 1, 0 }, /* CMU_RESET_LCD0 */ | ||
126 | { 1, 1, 0 }, /* CMU_RESET_LCD1 */ | ||
127 | { 1, 1, 0 }, /* CMU_RESET_MAUDIO */ | ||
128 | { 1, 1, 0 }, /* CMU_RESET_GPS */ | ||
129 | { 3, 0, 0 }, /* TOP_BUS */ | ||
130 | { 1, 0, 1 }, /* TOP_RETENTION */ | ||
131 | { 3, 0, 3 }, /* TOP_PWR */ | ||
132 | { 1, 1, 0 }, /* LOGIC_RESET */ | ||
133 | { 3, 0, 0 }, /* ONENAND_MEM */ | ||
134 | { 3, 0, 0 }, /* MODIMIF_MEM */ | ||
135 | { 3, 0, 0 }, /* G2D_ACP_MEM */ | ||
136 | { 3, 0, 0 }, /* USBOTG_MEM */ | ||
137 | { 3, 0, 0 }, /* HSMMC_MEM */ | ||
138 | { 3, 0, 0 }, /* CSSYS_MEM */ | ||
139 | { 3, 0, 0 }, /* SECSS_MEM */ | ||
140 | { 3, 0, 0 }, /* PCIE_MEM */ | ||
141 | { 3, 0, 0 }, /* SATA_MEM */ | ||
142 | { 1, 0, 0 }, /* PAD_RETENTION_DRAM */ | ||
143 | { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */ | ||
144 | { 1, 0, 0 }, /* PAD_RETENTION_GPIO */ | ||
145 | { 1, 0, 0 }, /* PAD_RETENTION_UART */ | ||
146 | { 1, 0, 0 }, /* PAD_RETENTION_MMCA */ | ||
147 | { 1, 0, 0 }, /* PAD_RETENTION_MMCB */ | ||
148 | { 1, 0, 0 }, /* PAD_RETENTION_EBIA */ | ||
149 | { 1, 0, 0 }, /* PAD_RETENTION_EBIB */ | ||
150 | { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */ | ||
151 | { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */ | ||
152 | { 1, 1, 0 }, /* XUSBXTI */ | ||
153 | { 1, 1, 0 }, /* XXTI */ | ||
154 | { 1, 1, 0 }, /* EXT_REGULATOR */ | ||
155 | { 1, 0, 0 }, /* GPIO_MODE */ | ||
156 | { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */ | ||
157 | { 7, 0, 0 }, /* CAM */ | ||
158 | { 7, 0, 0 }, /* TV */ | ||
159 | { 7, 0, 0 }, /* MFC */ | ||
160 | { 7, 0, 0 }, /* G3D */ | ||
161 | { 7, 0, 0 }, /* LCD0 */ | ||
162 | { 7, 0, 0 }, /* LCD1 */ | ||
163 | { 7, 7, 0 }, /* MAUDIO */ | ||
164 | { 7, 0, 0 }, /* GPS */ | ||
165 | { 7, 0, 0 }, /* GPS_ALIVE */ | ||
166 | }; | ||
167 | |||
168 | void exynos4_sys_powerdown_conf(enum sys_powerdown mode) | ||
169 | { | ||
170 | unsigned int count = ARRAY_SIZE(sys_powerdown_reg); | ||
171 | |||
172 | for (; count > 0; count--) | ||
173 | __raw_writel(sys_powerdown_val[count - 1][mode], | ||
174 | sys_powerdown_reg[count - 1]); | ||
175 | } | ||
diff --git a/arch/arm/mach-exynos4/setup-fimd0.c b/arch/arm/mach-exynos4/setup-fimd0.c new file mode 100644 index 000000000000..07a6dbeecdd0 --- /dev/null +++ b/arch/arm/mach-exynos4/setup-fimd0.c | |||
@@ -0,0 +1,43 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/setup-fimd0.c | ||
2 | * | ||
3 | * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Base Exynos4 FIMD 0 configuration | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/fb.h> | ||
14 | #include <linux/gpio.h> | ||
15 | |||
16 | #include <plat/gpio-cfg.h> | ||
17 | #include <plat/regs-fb-v4.h> | ||
18 | |||
19 | #include <mach/map.h> | ||
20 | |||
21 | void exynos4_fimd0_gpio_setup_24bpp(void) | ||
22 | { | ||
23 | unsigned int reg; | ||
24 | |||
25 | s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2)); | ||
26 | s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2)); | ||
27 | s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2)); | ||
28 | s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2)); | ||
29 | |||
30 | /* | ||
31 | * Set DISPLAY_CONTROL register for Display path selection. | ||
32 | * | ||
33 | * DISPLAY_CONTROL[1:0] | ||
34 | * --------------------- | ||
35 | * 00 | MIE | ||
36 | * 01 | MDINE | ||
37 | * 10 | FIMD : selected | ||
38 | * 11 | FIMD | ||
39 | */ | ||
40 | reg = __raw_readl(S3C_VA_SYS + 0x0210); | ||
41 | reg |= (1 << 1); | ||
42 | __raw_writel(reg, S3C_VA_SYS + 0x0210); | ||
43 | } | ||
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c deleted file mode 100644 index ebb8f38d5405..000000000000 --- a/arch/arm/mach-exynos4/time.c +++ /dev/null | |||
@@ -1,301 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/time.c | ||
2 | * | ||
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * EXYNOS4 (and compatible) HRT support | ||
7 | * PWM 2/4 is used for this feature | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/sched.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/clockchips.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | |||
22 | #include <asm/smp_twd.h> | ||
23 | |||
24 | #include <mach/map.h> | ||
25 | #include <plat/regs-timer.h> | ||
26 | #include <asm/mach/time.h> | ||
27 | |||
28 | static unsigned long clock_count_per_tick; | ||
29 | |||
30 | static struct clk *tin2; | ||
31 | static struct clk *tin4; | ||
32 | static struct clk *tdiv2; | ||
33 | static struct clk *tdiv4; | ||
34 | static struct clk *timerclk; | ||
35 | |||
36 | static void exynos4_pwm_stop(unsigned int pwm_id) | ||
37 | { | ||
38 | unsigned long tcon; | ||
39 | |||
40 | tcon = __raw_readl(S3C2410_TCON); | ||
41 | |||
42 | switch (pwm_id) { | ||
43 | case 2: | ||
44 | tcon &= ~S3C2410_TCON_T2START; | ||
45 | break; | ||
46 | case 4: | ||
47 | tcon &= ~S3C2410_TCON_T4START; | ||
48 | break; | ||
49 | default: | ||
50 | break; | ||
51 | } | ||
52 | __raw_writel(tcon, S3C2410_TCON); | ||
53 | } | ||
54 | |||
55 | static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt) | ||
56 | { | ||
57 | unsigned long tcon; | ||
58 | |||
59 | tcon = __raw_readl(S3C2410_TCON); | ||
60 | |||
61 | /* timers reload after counting zero, so reduce the count by 1 */ | ||
62 | tcnt--; | ||
63 | |||
64 | /* ensure timer is stopped... */ | ||
65 | switch (pwm_id) { | ||
66 | case 2: | ||
67 | tcon &= ~(0xf<<12); | ||
68 | tcon |= S3C2410_TCON_T2MANUALUPD; | ||
69 | |||
70 | __raw_writel(tcnt, S3C2410_TCNTB(2)); | ||
71 | __raw_writel(tcnt, S3C2410_TCMPB(2)); | ||
72 | __raw_writel(tcon, S3C2410_TCON); | ||
73 | |||
74 | break; | ||
75 | case 4: | ||
76 | tcon &= ~(7<<20); | ||
77 | tcon |= S3C2410_TCON_T4MANUALUPD; | ||
78 | |||
79 | __raw_writel(tcnt, S3C2410_TCNTB(4)); | ||
80 | __raw_writel(tcnt, S3C2410_TCMPB(4)); | ||
81 | __raw_writel(tcon, S3C2410_TCON); | ||
82 | |||
83 | break; | ||
84 | default: | ||
85 | break; | ||
86 | } | ||
87 | } | ||
88 | |||
89 | static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic) | ||
90 | { | ||
91 | unsigned long tcon; | ||
92 | |||
93 | tcon = __raw_readl(S3C2410_TCON); | ||
94 | |||
95 | switch (pwm_id) { | ||
96 | case 2: | ||
97 | tcon |= S3C2410_TCON_T2START; | ||
98 | tcon &= ~S3C2410_TCON_T2MANUALUPD; | ||
99 | |||
100 | if (periodic) | ||
101 | tcon |= S3C2410_TCON_T2RELOAD; | ||
102 | else | ||
103 | tcon &= ~S3C2410_TCON_T2RELOAD; | ||
104 | break; | ||
105 | case 4: | ||
106 | tcon |= S3C2410_TCON_T4START; | ||
107 | tcon &= ~S3C2410_TCON_T4MANUALUPD; | ||
108 | |||
109 | if (periodic) | ||
110 | tcon |= S3C2410_TCON_T4RELOAD; | ||
111 | else | ||
112 | tcon &= ~S3C2410_TCON_T4RELOAD; | ||
113 | break; | ||
114 | default: | ||
115 | break; | ||
116 | } | ||
117 | __raw_writel(tcon, S3C2410_TCON); | ||
118 | } | ||
119 | |||
120 | static int exynos4_pwm_set_next_event(unsigned long cycles, | ||
121 | struct clock_event_device *evt) | ||
122 | { | ||
123 | exynos4_pwm_init(2, cycles); | ||
124 | exynos4_pwm_start(2, 0); | ||
125 | return 0; | ||
126 | } | ||
127 | |||
128 | static void exynos4_pwm_set_mode(enum clock_event_mode mode, | ||
129 | struct clock_event_device *evt) | ||
130 | { | ||
131 | exynos4_pwm_stop(2); | ||
132 | |||
133 | switch (mode) { | ||
134 | case CLOCK_EVT_MODE_PERIODIC: | ||
135 | exynos4_pwm_init(2, clock_count_per_tick); | ||
136 | exynos4_pwm_start(2, 1); | ||
137 | break; | ||
138 | case CLOCK_EVT_MODE_ONESHOT: | ||
139 | break; | ||
140 | case CLOCK_EVT_MODE_UNUSED: | ||
141 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
142 | case CLOCK_EVT_MODE_RESUME: | ||
143 | break; | ||
144 | } | ||
145 | } | ||
146 | |||
147 | static struct clock_event_device pwm_event_device = { | ||
148 | .name = "pwm_timer2", | ||
149 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
150 | .rating = 200, | ||
151 | .shift = 32, | ||
152 | .set_next_event = exynos4_pwm_set_next_event, | ||
153 | .set_mode = exynos4_pwm_set_mode, | ||
154 | }; | ||
155 | |||
156 | irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id) | ||
157 | { | ||
158 | struct clock_event_device *evt = &pwm_event_device; | ||
159 | |||
160 | evt->event_handler(evt); | ||
161 | |||
162 | return IRQ_HANDLED; | ||
163 | } | ||
164 | |||
165 | static struct irqaction exynos4_clock_event_irq = { | ||
166 | .name = "pwm_timer2_irq", | ||
167 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
168 | .handler = exynos4_clock_event_isr, | ||
169 | }; | ||
170 | |||
171 | static void __init exynos4_clockevent_init(void) | ||
172 | { | ||
173 | unsigned long pclk; | ||
174 | unsigned long clock_rate; | ||
175 | struct clk *tscaler; | ||
176 | |||
177 | pclk = clk_get_rate(timerclk); | ||
178 | |||
179 | /* configure clock tick */ | ||
180 | |||
181 | tscaler = clk_get_parent(tdiv2); | ||
182 | |||
183 | clk_set_rate(tscaler, pclk / 2); | ||
184 | clk_set_rate(tdiv2, pclk / 2); | ||
185 | clk_set_parent(tin2, tdiv2); | ||
186 | |||
187 | clock_rate = clk_get_rate(tin2); | ||
188 | |||
189 | clock_count_per_tick = clock_rate / HZ; | ||
190 | |||
191 | pwm_event_device.mult = | ||
192 | div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift); | ||
193 | pwm_event_device.max_delta_ns = | ||
194 | clockevent_delta2ns(-1, &pwm_event_device); | ||
195 | pwm_event_device.min_delta_ns = | ||
196 | clockevent_delta2ns(1, &pwm_event_device); | ||
197 | |||
198 | pwm_event_device.cpumask = cpumask_of(0); | ||
199 | clockevents_register_device(&pwm_event_device); | ||
200 | |||
201 | setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq); | ||
202 | } | ||
203 | |||
204 | static cycle_t exynos4_pwm4_read(struct clocksource *cs) | ||
205 | { | ||
206 | return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40)); | ||
207 | } | ||
208 | |||
209 | #ifdef CONFIG_PM | ||
210 | static void exynos4_pwm4_resume(struct clocksource *cs) | ||
211 | { | ||
212 | unsigned long pclk; | ||
213 | |||
214 | pclk = clk_get_rate(timerclk); | ||
215 | |||
216 | clk_set_rate(tdiv4, pclk / 2); | ||
217 | clk_set_parent(tin4, tdiv4); | ||
218 | |||
219 | exynos4_pwm_init(4, ~0); | ||
220 | exynos4_pwm_start(4, 1); | ||
221 | } | ||
222 | #endif | ||
223 | |||
224 | struct clocksource pwm_clocksource = { | ||
225 | .name = "pwm_timer4", | ||
226 | .rating = 250, | ||
227 | .read = exynos4_pwm4_read, | ||
228 | .mask = CLOCKSOURCE_MASK(32), | ||
229 | .flags = CLOCK_SOURCE_IS_CONTINUOUS , | ||
230 | #ifdef CONFIG_PM | ||
231 | .resume = exynos4_pwm4_resume, | ||
232 | #endif | ||
233 | }; | ||
234 | |||
235 | static void __init exynos4_clocksource_init(void) | ||
236 | { | ||
237 | unsigned long pclk; | ||
238 | unsigned long clock_rate; | ||
239 | |||
240 | pclk = clk_get_rate(timerclk); | ||
241 | |||
242 | clk_set_rate(tdiv4, pclk / 2); | ||
243 | clk_set_parent(tin4, tdiv4); | ||
244 | |||
245 | clock_rate = clk_get_rate(tin4); | ||
246 | |||
247 | exynos4_pwm_init(4, ~0); | ||
248 | exynos4_pwm_start(4, 1); | ||
249 | |||
250 | if (clocksource_register_hz(&pwm_clocksource, clock_rate)) | ||
251 | panic("%s: can't register clocksource\n", pwm_clocksource.name); | ||
252 | } | ||
253 | |||
254 | static void __init exynos4_timer_resources(void) | ||
255 | { | ||
256 | struct platform_device tmpdev; | ||
257 | |||
258 | tmpdev.dev.bus = &platform_bus_type; | ||
259 | |||
260 | timerclk = clk_get(NULL, "timers"); | ||
261 | if (IS_ERR(timerclk)) | ||
262 | panic("failed to get timers clock for system timer"); | ||
263 | |||
264 | clk_enable(timerclk); | ||
265 | |||
266 | tmpdev.id = 2; | ||
267 | tin2 = clk_get(&tmpdev.dev, "pwm-tin"); | ||
268 | if (IS_ERR(tin2)) | ||
269 | panic("failed to get pwm-tin2 clock for system timer"); | ||
270 | |||
271 | tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv"); | ||
272 | if (IS_ERR(tdiv2)) | ||
273 | panic("failed to get pwm-tdiv2 clock for system timer"); | ||
274 | clk_enable(tin2); | ||
275 | |||
276 | tmpdev.id = 4; | ||
277 | tin4 = clk_get(&tmpdev.dev, "pwm-tin"); | ||
278 | if (IS_ERR(tin4)) | ||
279 | panic("failed to get pwm-tin4 clock for system timer"); | ||
280 | |||
281 | tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv"); | ||
282 | if (IS_ERR(tdiv4)) | ||
283 | panic("failed to get pwm-tdiv4 clock for system timer"); | ||
284 | |||
285 | clk_enable(tin4); | ||
286 | } | ||
287 | |||
288 | static void __init exynos4_timer_init(void) | ||
289 | { | ||
290 | #ifdef CONFIG_LOCAL_TIMERS | ||
291 | twd_base = S5P_VA_TWD; | ||
292 | #endif | ||
293 | |||
294 | exynos4_timer_resources(); | ||
295 | exynos4_clockevent_init(); | ||
296 | exynos4_clocksource_init(); | ||
297 | } | ||
298 | |||
299 | struct sys_timer exynos4_timer = { | ||
300 | .init = exynos4_timer_init, | ||
301 | }; | ||
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index e8dd22fa7d61..0519dd7f034b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
@@ -278,6 +278,7 @@ config MACH_MX27_3DS | |||
278 | select SOC_IMX27 | 278 | select SOC_IMX27 |
279 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | 279 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC |
280 | select IMX_HAVE_PLATFORM_IMX2_WDT | 280 | select IMX_HAVE_PLATFORM_IMX2_WDT |
281 | select IMX_HAVE_PLATFORM_IMX_FB | ||
281 | select IMX_HAVE_PLATFORM_IMX_I2C | 282 | select IMX_HAVE_PLATFORM_IMX_I2C |
282 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | 283 | select IMX_HAVE_PLATFORM_IMX_KEYPAD |
283 | select IMX_HAVE_PLATFORM_IMX_UART | 284 | select IMX_HAVE_PLATFORM_IMX_UART |
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index b31d4129e10e..6fa6934ab150 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <linux/mfd/mc13783.h> | 29 | #include <linux/mfd/mc13783.h> |
30 | #include <linux/spi/spi.h> | 30 | #include <linux/spi/spi.h> |
31 | #include <linux/regulator/machine.h> | 31 | #include <linux/regulator/machine.h> |
32 | #include <linux/spi/l4f00242t03.h> | ||
32 | 33 | ||
33 | #include <asm/mach-types.h> | 34 | #include <asm/mach-types.h> |
34 | #include <asm/mach/arch.h> | 35 | #include <asm/mach/arch.h> |
@@ -47,7 +48,10 @@ | |||
47 | #define SPI2_SS0 IMX_GPIO_NR(4, 21) | 48 | #define SPI2_SS0 IMX_GPIO_NR(4, 21) |
48 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28)) | 49 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28)) |
49 | #define PMIC_INT IMX_GPIO_NR(3, 14) | 50 | #define PMIC_INT IMX_GPIO_NR(3, 14) |
51 | #define SPI1_SS0 IMX_GPIO_NR(4, 28) | ||
50 | #define SD1_CD IMX_GPIO_NR(2, 26) | 52 | #define SD1_CD IMX_GPIO_NR(2, 26) |
53 | #define LCD_RESET IMX_GPIO_NR(1, 3) | ||
54 | #define LCD_ENABLE IMX_GPIO_NR(1, 31) | ||
51 | 55 | ||
52 | static const int mx27pdk_pins[] __initconst = { | 56 | static const int mx27pdk_pins[] __initconst = { |
53 | /* UART1 */ | 57 | /* UART1 */ |
@@ -96,6 +100,12 @@ static const int mx27pdk_pins[] __initconst = { | |||
96 | PE2_PF_USBOTG_DIR, | 100 | PE2_PF_USBOTG_DIR, |
97 | PE24_PF_USBOTG_CLK, | 101 | PE24_PF_USBOTG_CLK, |
98 | PE25_PF_USBOTG_DATA7, | 102 | PE25_PF_USBOTG_DATA7, |
103 | /* CSPI1 */ | ||
104 | PD31_PF_CSPI1_MOSI, | ||
105 | PD30_PF_CSPI1_MISO, | ||
106 | PD29_PF_CSPI1_SCLK, | ||
107 | PD25_PF_CSPI1_RDY, | ||
108 | SPI1_SS0 | GPIO_GPIO | GPIO_OUT, | ||
99 | /* CSPI2 */ | 109 | /* CSPI2 */ |
100 | PD22_PF_CSPI2_SCLK, | 110 | PD22_PF_CSPI2_SCLK, |
101 | PD23_PF_CSPI2_MISO, | 111 | PD23_PF_CSPI2_MISO, |
@@ -106,6 +116,31 @@ static const int mx27pdk_pins[] __initconst = { | |||
106 | PD18_PF_I2C_CLK, | 116 | PD18_PF_I2C_CLK, |
107 | /* PMIC INT */ | 117 | /* PMIC INT */ |
108 | PMIC_INT | GPIO_GPIO | GPIO_IN, | 118 | PMIC_INT | GPIO_GPIO | GPIO_IN, |
119 | /* LCD */ | ||
120 | PA5_PF_LSCLK, | ||
121 | PA6_PF_LD0, | ||
122 | PA7_PF_LD1, | ||
123 | PA8_PF_LD2, | ||
124 | PA9_PF_LD3, | ||
125 | PA10_PF_LD4, | ||
126 | PA11_PF_LD5, | ||
127 | PA12_PF_LD6, | ||
128 | PA13_PF_LD7, | ||
129 | PA14_PF_LD8, | ||
130 | PA15_PF_LD9, | ||
131 | PA16_PF_LD10, | ||
132 | PA17_PF_LD11, | ||
133 | PA18_PF_LD12, | ||
134 | PA19_PF_LD13, | ||
135 | PA20_PF_LD14, | ||
136 | PA21_PF_LD15, | ||
137 | PA22_PF_LD16, | ||
138 | PA23_PF_LD17, | ||
139 | PA28_PF_HSYNC, | ||
140 | PA29_PF_VSYNC, | ||
141 | PA30_PF_CONTRAST, | ||
142 | LCD_ENABLE | GPIO_GPIO | GPIO_OUT, | ||
143 | LCD_RESET | GPIO_GPIO | GPIO_OUT, | ||
109 | }; | 144 | }; |
110 | 145 | ||
111 | static const struct imxuart_platform_data uart_pdata __initconst = { | 146 | static const struct imxuart_platform_data uart_pdata __initconst = { |
@@ -258,10 +293,18 @@ static struct mc13xxx_platform_data mc13783_pdata = { | |||
258 | .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), | 293 | .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), |
259 | 294 | ||
260 | }, | 295 | }, |
261 | .flags = MC13783_USE_REGULATOR, | 296 | .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN | |
297 | MC13783_USE_RTC, | ||
262 | }; | 298 | }; |
263 | 299 | ||
264 | /* SPI */ | 300 | /* SPI */ |
301 | static int spi1_chipselect[] = {SPI1_SS0}; | ||
302 | |||
303 | static const struct spi_imx_master spi1_pdata __initconst = { | ||
304 | .chipselect = spi1_chipselect, | ||
305 | .num_chipselect = ARRAY_SIZE(spi1_chipselect), | ||
306 | }; | ||
307 | |||
265 | static int spi2_chipselect[] = {SPI2_SS0}; | 308 | static int spi2_chipselect[] = {SPI2_SS0}; |
266 | 309 | ||
267 | static const struct spi_imx_master spi2_pdata __initconst = { | 310 | static const struct spi_imx_master spi2_pdata __initconst = { |
@@ -269,6 +312,46 @@ static const struct spi_imx_master spi2_pdata __initconst = { | |||
269 | .num_chipselect = ARRAY_SIZE(spi2_chipselect), | 312 | .num_chipselect = ARRAY_SIZE(spi2_chipselect), |
270 | }; | 313 | }; |
271 | 314 | ||
315 | static struct imx_fb_videomode mx27_3ds_modes[] = { | ||
316 | { /* 480x640 @ 60 Hz */ | ||
317 | .mode = { | ||
318 | .name = "Epson-VGA", | ||
319 | .refresh = 60, | ||
320 | .xres = 480, | ||
321 | .yres = 640, | ||
322 | .pixclock = 41701, | ||
323 | .left_margin = 20, | ||
324 | .right_margin = 41, | ||
325 | .upper_margin = 10, | ||
326 | .lower_margin = 5, | ||
327 | .hsync_len = 20, | ||
328 | .vsync_len = 10, | ||
329 | .sync = FB_SYNC_OE_ACT_HIGH | | ||
330 | FB_SYNC_CLK_INVERT, | ||
331 | .vmode = FB_VMODE_NONINTERLACED, | ||
332 | .flag = 0, | ||
333 | }, | ||
334 | .bpp = 16, | ||
335 | .pcr = 0xFAC08B82, | ||
336 | }, | ||
337 | }; | ||
338 | |||
339 | static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { | ||
340 | .mode = mx27_3ds_modes, | ||
341 | .num_modes = ARRAY_SIZE(mx27_3ds_modes), | ||
342 | .pwmr = 0x00A903FF, | ||
343 | .lscr1 = 0x00120300, | ||
344 | .dmacr = 0x00020010, | ||
345 | }; | ||
346 | |||
347 | /* LCD */ | ||
348 | static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = { | ||
349 | .reset_gpio = LCD_RESET, | ||
350 | .data_enable_gpio = LCD_ENABLE, | ||
351 | .core_supply = "lcd_2v8", | ||
352 | .io_supply = "vdd_lcdio", | ||
353 | }; | ||
354 | |||
272 | static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { | 355 | static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { |
273 | { | 356 | { |
274 | .modalias = "mc13783", | 357 | .modalias = "mc13783", |
@@ -278,6 +361,12 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { | |||
278 | .platform_data = &mc13783_pdata, | 361 | .platform_data = &mc13783_pdata, |
279 | .irq = gpio_to_irq(PMIC_INT), | 362 | .irq = gpio_to_irq(PMIC_INT), |
280 | .mode = SPI_CS_HIGH, | 363 | .mode = SPI_CS_HIGH, |
364 | }, { | ||
365 | .modalias = "l4f00242t03", | ||
366 | .max_speed_hz = 5000000, | ||
367 | .bus_num = 0, | ||
368 | .chip_select = 0, /* SS0 */ | ||
369 | .platform_data = &mx27_3ds_lcd_pdata, | ||
281 | }, | 370 | }, |
282 | }; | 371 | }; |
283 | 372 | ||
@@ -311,12 +400,14 @@ static void __init mx27pdk_init(void) | |||
311 | imx27_add_fsl_usb2_udc(&otg_device_pdata); | 400 | imx27_add_fsl_usb2_udc(&otg_device_pdata); |
312 | 401 | ||
313 | imx27_add_spi_imx1(&spi2_pdata); | 402 | imx27_add_spi_imx1(&spi2_pdata); |
403 | imx27_add_spi_imx0(&spi1_pdata); | ||
314 | spi_register_board_info(mx27_3ds_spi_devs, | 404 | spi_register_board_info(mx27_3ds_spi_devs, |
315 | ARRAY_SIZE(mx27_3ds_spi_devs)); | 405 | ARRAY_SIZE(mx27_3ds_spi_devs)); |
316 | 406 | ||
317 | if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | 407 | if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
318 | pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); | 408 | pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); |
319 | imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); | 409 | imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); |
410 | imx27_add_imx_fb(&mx27_3ds_fb_data); | ||
320 | } | 411 | } |
321 | 412 | ||
322 | static void __init mx27pdk_timer_init(void) | 413 | static void __init mx27pdk_timer_init(void) |
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 6d7d518686a5..3f05dfebacc9 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
24 | #include <mach/common.h> | 24 | #include <mach/common.h> |
25 | #include <mach/devices-common.h> | ||
25 | #include <asm/pgtable.h> | 26 | #include <asm/pgtable.h> |
26 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
27 | #include <mach/irqs.h> | 28 | #include <mach/irqs.h> |
@@ -82,4 +83,6 @@ void __init imx21_soc_init(void) | |||
82 | mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); | 83 | mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); |
83 | mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); | 84 | mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); |
84 | mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); | 85 | mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); |
86 | |||
87 | imx_add_imx_dma(); | ||
85 | } | 88 | } |
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c index 9a1591c2508d..8bf029164652 100644 --- a/arch/arm/mach-imx/mm-imx25.c +++ b/arch/arm/mach-imx/mm-imx25.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
25 | 25 | ||
26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
27 | #include <mach/devices-common.h> | ||
27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
28 | #include <mach/mx25.h> | 29 | #include <mach/mx25.h> |
29 | #include <mach/iomux-v3.h> | 30 | #include <mach/iomux-v3.h> |
@@ -61,6 +62,28 @@ void __init mx25_init_irq(void) | |||
61 | mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); | 62 | mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); |
62 | } | 63 | } |
63 | 64 | ||
65 | static struct sdma_script_start_addrs imx25_sdma_script __initdata = { | ||
66 | .ap_2_ap_addr = 729, | ||
67 | .uart_2_mcu_addr = 904, | ||
68 | .per_2_app_addr = 1255, | ||
69 | .mcu_2_app_addr = 834, | ||
70 | .uartsh_2_mcu_addr = 1120, | ||
71 | .per_2_shp_addr = 1329, | ||
72 | .mcu_2_shp_addr = 1048, | ||
73 | .ata_2_mcu_addr = 1560, | ||
74 | .mcu_2_ata_addr = 1479, | ||
75 | .app_2_per_addr = 1189, | ||
76 | .app_2_mcu_addr = 770, | ||
77 | .shp_2_per_addr = 1407, | ||
78 | .shp_2_mcu_addr = 979, | ||
79 | }; | ||
80 | |||
81 | static struct sdma_platform_data imx25_sdma_pdata __initdata = { | ||
82 | .sdma_version = 2, | ||
83 | .fw_name = "sdma-imx25.bin", | ||
84 | .script_addrs = &imx25_sdma_script, | ||
85 | }; | ||
86 | |||
64 | void __init imx25_soc_init(void) | 87 | void __init imx25_soc_init(void) |
65 | { | 88 | { |
66 | /* i.mx25 has the i.mx31 type gpio */ | 89 | /* i.mx25 has the i.mx31 type gpio */ |
@@ -68,4 +91,6 @@ void __init imx25_soc_init(void) | |||
68 | mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); | 91 | mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); |
69 | mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); | 92 | mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); |
70 | mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); | 93 | mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); |
94 | |||
95 | imx_add_imx_sdma(MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata); | ||
71 | } | 96 | } |
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 133b30003ddb..96dd1f5ea7bd 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
24 | #include <mach/common.h> | 24 | #include <mach/common.h> |
25 | #include <mach/devices-common.h> | ||
25 | #include <asm/pgtable.h> | 26 | #include <asm/pgtable.h> |
26 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
27 | #include <mach/irqs.h> | 28 | #include <mach/irqs.h> |
@@ -83,4 +84,6 @@ void __init imx27_soc_init(void) | |||
83 | mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); | 84 | mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); |
84 | mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); | 85 | mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); |
85 | mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); | 86 | mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); |
87 | |||
88 | imx_add_imx_dma(); | ||
86 | } | 89 | } |
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c index 6d103c01b8b9..61bff38cb955 100644 --- a/arch/arm/mach-imx/mm-imx31.c +++ b/arch/arm/mach-imx/mm-imx31.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
25 | 25 | ||
26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
27 | #include <mach/devices-common.h> | ||
27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
28 | #include <mach/iomux-v3.h> | 29 | #include <mach/iomux-v3.h> |
29 | #include <mach/irqs.h> | 30 | #include <mach/irqs.h> |
@@ -57,9 +58,35 @@ void __init mx31_init_irq(void) | |||
57 | mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); | 58 | mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); |
58 | } | 59 | } |
59 | 60 | ||
61 | static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { | ||
62 | .per_2_per_addr = 1677, | ||
63 | }; | ||
64 | |||
65 | static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { | ||
66 | .ap_2_ap_addr = 423, | ||
67 | .ap_2_bp_addr = 829, | ||
68 | .bp_2_ap_addr = 1029, | ||
69 | }; | ||
70 | |||
71 | static struct sdma_platform_data imx31_sdma_pdata __initdata = { | ||
72 | .sdma_version = 1, | ||
73 | .fw_name = "sdma-imx31-to2.bin", | ||
74 | .script_addrs = &imx31_to2_sdma_script, | ||
75 | }; | ||
76 | |||
60 | void __init imx31_soc_init(void) | 77 | void __init imx31_soc_init(void) |
61 | { | 78 | { |
79 | int to_version = mx31_revision() >> 4; | ||
80 | |||
62 | mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); | 81 | mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); |
63 | mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); | 82 | mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); |
64 | mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); | 83 | mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); |
84 | |||
85 | if (to_version == 1) { | ||
86 | strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", | ||
87 | strlen(imx31_sdma_pdata.fw_name)); | ||
88 | imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; | ||
89 | } | ||
90 | |||
91 | imx_add_imx_sdma(MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); | ||
65 | } | 92 | } |
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c index bb068bc8dab7..98769ae34377 100644 --- a/arch/arm/mach-imx/mm-imx35.c +++ b/arch/arm/mach-imx/mm-imx35.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <asm/hardware/cache-l2x0.h> | 25 | #include <asm/hardware/cache-l2x0.h> |
26 | 26 | ||
27 | #include <mach/common.h> | 27 | #include <mach/common.h> |
28 | #include <mach/devices-common.h> | ||
28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
29 | #include <mach/iomux-v3.h> | 30 | #include <mach/iomux-v3.h> |
30 | #include <mach/irqs.h> | 31 | #include <mach/irqs.h> |
@@ -54,10 +55,56 @@ void __init mx35_init_irq(void) | |||
54 | mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); | 55 | mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); |
55 | } | 56 | } |
56 | 57 | ||
58 | static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { | ||
59 | .ap_2_ap_addr = 642, | ||
60 | .uart_2_mcu_addr = 817, | ||
61 | .mcu_2_app_addr = 747, | ||
62 | .uartsh_2_mcu_addr = 1183, | ||
63 | .per_2_shp_addr = 1033, | ||
64 | .mcu_2_shp_addr = 961, | ||
65 | .ata_2_mcu_addr = 1333, | ||
66 | .mcu_2_ata_addr = 1252, | ||
67 | .app_2_mcu_addr = 683, | ||
68 | .shp_2_per_addr = 1111, | ||
69 | .shp_2_mcu_addr = 892, | ||
70 | }; | ||
71 | |||
72 | static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { | ||
73 | .ap_2_ap_addr = 729, | ||
74 | .uart_2_mcu_addr = 904, | ||
75 | .per_2_app_addr = 1597, | ||
76 | .mcu_2_app_addr = 834, | ||
77 | .uartsh_2_mcu_addr = 1270, | ||
78 | .per_2_shp_addr = 1120, | ||
79 | .mcu_2_shp_addr = 1048, | ||
80 | .ata_2_mcu_addr = 1429, | ||
81 | .mcu_2_ata_addr = 1339, | ||
82 | .app_2_per_addr = 1531, | ||
83 | .app_2_mcu_addr = 770, | ||
84 | .shp_2_per_addr = 1198, | ||
85 | .shp_2_mcu_addr = 979, | ||
86 | }; | ||
87 | |||
88 | static struct sdma_platform_data imx35_sdma_pdata __initdata = { | ||
89 | .sdma_version = 2, | ||
90 | .fw_name = "sdma-imx35-to2.bin", | ||
91 | .script_addrs = &imx35_to2_sdma_script, | ||
92 | }; | ||
93 | |||
57 | void __init imx35_soc_init(void) | 94 | void __init imx35_soc_init(void) |
58 | { | 95 | { |
96 | int to_version = mx35_revision() >> 4; | ||
97 | |||
59 | /* i.mx35 has the i.mx31 type gpio */ | 98 | /* i.mx35 has the i.mx31 type gpio */ |
60 | mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); | 99 | mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); |
61 | mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); | 100 | mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); |
62 | mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); | 101 | mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); |
102 | |||
103 | if (to_version == 1) { | ||
104 | strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", | ||
105 | strlen(imx35_sdma_pdata.fw_name)); | ||
106 | imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; | ||
107 | } | ||
108 | |||
109 | imx_add_imx_sdma(MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); | ||
63 | } | 110 | } |
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index da0e6498110a..1e027514096d 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c | |||
@@ -1077,7 +1077,7 @@ static struct clk_lookup lookups[] = { | |||
1077 | _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) | 1077 | _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) |
1078 | _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0) | 1078 | _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0) |
1079 | _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1) | 1079 | _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1) |
1080 | _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc) | 1080 | _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc) |
1081 | _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc) | 1081 | _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc) |
1082 | _REGISTER_CLOCK("lpc-net.0", NULL, clk_net) | 1082 | _REGISTER_CLOCK("lpc-net.0", NULL, clk_net) |
1083 | _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) | 1083 | _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) |
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index ee24dc28e93e..205b2dbb565b 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c | |||
@@ -95,6 +95,48 @@ struct platform_device lpc32xx_i2c2_device = { | |||
95 | }, | 95 | }, |
96 | }; | 96 | }; |
97 | 97 | ||
98 | /* TSC (Touch Screen Controller) */ | ||
99 | |||
100 | static struct resource lpc32xx_tsc_resources[] = { | ||
101 | { | ||
102 | .start = LPC32XX_ADC_BASE, | ||
103 | .end = LPC32XX_ADC_BASE + SZ_4K - 1, | ||
104 | .flags = IORESOURCE_MEM, | ||
105 | }, { | ||
106 | .start = IRQ_LPC32XX_TS_IRQ, | ||
107 | .end = IRQ_LPC32XX_TS_IRQ, | ||
108 | .flags = IORESOURCE_IRQ, | ||
109 | }, | ||
110 | }; | ||
111 | |||
112 | struct platform_device lpc32xx_tsc_device = { | ||
113 | .name = "ts-lpc32xx", | ||
114 | .id = -1, | ||
115 | .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources), | ||
116 | .resource = lpc32xx_tsc_resources, | ||
117 | }; | ||
118 | |||
119 | /* RTC */ | ||
120 | |||
121 | static struct resource lpc32xx_rtc_resources[] = { | ||
122 | { | ||
123 | .start = LPC32XX_RTC_BASE, | ||
124 | .end = LPC32XX_RTC_BASE + SZ_4K - 1, | ||
125 | .flags = IORESOURCE_MEM, | ||
126 | },{ | ||
127 | .start = IRQ_LPC32XX_RTC, | ||
128 | .end = IRQ_LPC32XX_RTC, | ||
129 | .flags = IORESOURCE_IRQ, | ||
130 | }, | ||
131 | }; | ||
132 | |||
133 | struct platform_device lpc32xx_rtc_device = { | ||
134 | .name = "rtc-lpc32xx", | ||
135 | .id = -1, | ||
136 | .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources), | ||
137 | .resource = lpc32xx_rtc_resources, | ||
138 | }; | ||
139 | |||
98 | /* | 140 | /* |
99 | * Returns the unique ID for the device | 141 | * Returns the unique ID for the device |
100 | */ | 142 | */ |
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index f82211fd80c1..5583f52662bd 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h | |||
@@ -28,6 +28,8 @@ extern struct platform_device lpc32xx_watchdog_device; | |||
28 | extern struct platform_device lpc32xx_i2c0_device; | 28 | extern struct platform_device lpc32xx_i2c0_device; |
29 | extern struct platform_device lpc32xx_i2c1_device; | 29 | extern struct platform_device lpc32xx_i2c1_device; |
30 | extern struct platform_device lpc32xx_i2c2_device; | 30 | extern struct platform_device lpc32xx_i2c2_device; |
31 | extern struct platform_device lpc32xx_tsc_device; | ||
32 | extern struct platform_device lpc32xx_rtc_device; | ||
31 | 33 | ||
32 | /* | 34 | /* |
33 | * Other arch specific structures and functions | 35 | * Other arch specific structures and functions |
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 67793a690272..56ef5f6c8116 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig | |||
@@ -77,6 +77,13 @@ config MACH_TETON_BGA | |||
77 | Say 'Y' here if you want to support the Marvell PXA168-based | 77 | Say 'Y' here if you want to support the Marvell PXA168-based |
78 | Teton BGA Development Board. | 78 | Teton BGA Development Board. |
79 | 79 | ||
80 | config MACH_SHEEVAD | ||
81 | bool "Marvell's PXA168 GuruPlug Display (gplugD) Board" | ||
82 | select CPU_PXA168 | ||
83 | help | ||
84 | Say 'Y' here if you want to support the Marvell PXA168-based | ||
85 | GuruPlug Display (gplugD) Board | ||
86 | |||
80 | endmenu | 87 | endmenu |
81 | 88 | ||
82 | config CPU_PXA168 | 89 | config CPU_PXA168 |
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 5c68382141af..b0ac942327aa 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile | |||
@@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o | |||
19 | obj-$(CONFIG_MACH_FLINT) += flint.o | 19 | obj-$(CONFIG_MACH_FLINT) += flint.o |
20 | obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o | 20 | obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o |
21 | obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o | 21 | obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o |
22 | obj-$(CONFIG_MACH_SHEEVAD) += gplugd.o | ||
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c index 886e05648f08..7c6f95f29142 100644 --- a/arch/arm/mach-mmp/clock.c +++ b/arch/arm/mach-mmp/clock.c | |||
@@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk) | |||
88 | return rate; | 88 | return rate; |
89 | } | 89 | } |
90 | EXPORT_SYMBOL(clk_get_rate); | 90 | EXPORT_SYMBOL(clk_get_rate); |
91 | |||
92 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
93 | { | ||
94 | unsigned long flags; | ||
95 | int ret = -EINVAL; | ||
96 | |||
97 | if (clk->ops->setrate) { | ||
98 | spin_lock_irqsave(&clocks_lock, flags); | ||
99 | ret = clk->ops->setrate(clk, rate); | ||
100 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
101 | } | ||
102 | |||
103 | return ret; | ||
104 | } | ||
105 | EXPORT_SYMBOL(clk_set_rate); | ||
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h index 9b027d7491f5..3143e994e672 100644 --- a/arch/arm/mach-mmp/clock.h +++ b/arch/arm/mach-mmp/clock.h | |||
@@ -12,6 +12,7 @@ struct clkops { | |||
12 | void (*enable)(struct clk *); | 12 | void (*enable)(struct clk *); |
13 | void (*disable)(struct clk *); | 13 | void (*disable)(struct clk *); |
14 | unsigned long (*getrate)(struct clk *); | 14 | unsigned long (*getrate)(struct clk *); |
15 | int (*setrate)(struct clk *, unsigned long); | ||
15 | }; | 16 | }; |
16 | 17 | ||
17 | struct clk { | 18 | struct clk { |
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c new file mode 100644 index 000000000000..c070c24255f4 --- /dev/null +++ b/arch/arm/mach-mmp/gplugd.c | |||
@@ -0,0 +1,189 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-mmp/gplugd.c | ||
3 | * | ||
4 | * Support for the Marvell PXA168-based GuruPlug Display (gplugD) Platform. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * publishhed by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/init.h> | ||
12 | |||
13 | #include <asm/mach/arch.h> | ||
14 | #include <asm/mach-types.h> | ||
15 | |||
16 | #include <mach/gpio.h> | ||
17 | #include <mach/pxa168.h> | ||
18 | #include <mach/mfp-pxa168.h> | ||
19 | #include <mach/mfp-gplugd.h> | ||
20 | |||
21 | #include "common.h" | ||
22 | |||
23 | static unsigned long gplugd_pin_config[] __initdata = { | ||
24 | /* UART3 */ | ||
25 | GPIO8_UART3_SOUT, | ||
26 | GPIO9_UART3_SIN, | ||
27 | GPI1O_UART3_CTS, | ||
28 | GPI11_UART3_RTS, | ||
29 | |||
30 | /* MMC2 */ | ||
31 | GPIO28_MMC2_CMD, | ||
32 | GPIO29_MMC2_CLK, | ||
33 | GPIO30_MMC2_DAT0, | ||
34 | GPIO31_MMC2_DAT1, | ||
35 | GPIO32_MMC2_DAT2, | ||
36 | GPIO33_MMC2_DAT3, | ||
37 | |||
38 | /* LCD & HDMI clock selection GPIO: 0: 74.176MHz, 1: 74.25 MHz */ | ||
39 | GPIO35_GPIO, | ||
40 | GPIO36_GPIO, /* CEC Interrupt */ | ||
41 | |||
42 | /* MMC1 */ | ||
43 | GPIO43_MMC1_CLK, | ||
44 | GPIO49_MMC1_CMD, | ||
45 | GPIO41_MMC1_DAT0, | ||
46 | GPIO40_MMC1_DAT1, | ||
47 | GPIO52_MMC1_DAT2, | ||
48 | GPIO51_MMC1_DAT3, | ||
49 | GPIO53_MMC1_CD, | ||
50 | |||
51 | /* LCD */ | ||
52 | GPIO56_LCD_FCLK_RD, | ||
53 | GPIO57_LCD_LCLK_A0, | ||
54 | GPIO58_LCD_PCLK_WR, | ||
55 | GPIO59_LCD_DENA_BIAS, | ||
56 | GPIO60_LCD_DD0, | ||
57 | GPIO61_LCD_DD1, | ||
58 | GPIO62_LCD_DD2, | ||
59 | GPIO63_LCD_DD3, | ||
60 | GPIO64_LCD_DD4, | ||
61 | GPIO65_LCD_DD5, | ||
62 | GPIO66_LCD_DD6, | ||
63 | GPIO67_LCD_DD7, | ||
64 | GPIO68_LCD_DD8, | ||
65 | GPIO69_LCD_DD9, | ||
66 | GPIO70_LCD_DD10, | ||
67 | GPIO71_LCD_DD11, | ||
68 | GPIO72_LCD_DD12, | ||
69 | GPIO73_LCD_DD13, | ||
70 | GPIO74_LCD_DD14, | ||
71 | GPIO75_LCD_DD15, | ||
72 | GPIO76_LCD_DD16, | ||
73 | GPIO77_LCD_DD17, | ||
74 | GPIO78_LCD_DD18, | ||
75 | GPIO79_LCD_DD19, | ||
76 | GPIO80_LCD_DD20, | ||
77 | GPIO81_LCD_DD21, | ||
78 | GPIO82_LCD_DD22, | ||
79 | GPIO83_LCD_DD23, | ||
80 | |||
81 | /* GPIO */ | ||
82 | GPIO84_GPIO, | ||
83 | GPIO85_GPIO, | ||
84 | |||
85 | /* Fast-Ethernet*/ | ||
86 | GPIO86_TX_CLK, | ||
87 | GPIO87_TX_EN, | ||
88 | GPIO88_TX_DQ3, | ||
89 | GPIO89_TX_DQ2, | ||
90 | GPIO90_TX_DQ1, | ||
91 | GPIO91_TX_DQ0, | ||
92 | GPIO92_MII_CRS, | ||
93 | GPIO93_MII_COL, | ||
94 | GPIO94_RX_CLK, | ||
95 | GPIO95_RX_ER, | ||
96 | GPIO96_RX_DQ3, | ||
97 | GPIO97_RX_DQ2, | ||
98 | GPIO98_RX_DQ1, | ||
99 | GPIO99_RX_DQ0, | ||
100 | GPIO100_MII_MDC, | ||
101 | GPIO101_MII_MDIO, | ||
102 | GPIO103_RX_DV, | ||
103 | GPIO104_GPIO, /* Reset PHY */ | ||
104 | |||
105 | /* RTC interrupt */ | ||
106 | GPIO102_GPIO, | ||
107 | |||
108 | /* I2C */ | ||
109 | GPIO105_CI2C_SDA, | ||
110 | GPIO106_CI2C_SCL, | ||
111 | |||
112 | /* Select JTAG */ | ||
113 | GPIO109_GPIO, | ||
114 | |||
115 | /* I2S */ | ||
116 | GPIO114_I2S_FRM, | ||
117 | GPIO115_I2S_BCLK, | ||
118 | GPIO116_I2S_TXD | ||
119 | }; | ||
120 | |||
121 | static struct i2c_board_info gplugd_i2c_board_info[] = { | ||
122 | { | ||
123 | .type = "isl1208", | ||
124 | .addr = 0x6F, | ||
125 | } | ||
126 | }; | ||
127 | |||
128 | /* Bring PHY out of reset by setting GPIO 104 */ | ||
129 | static int gplugd_eth_init(void) | ||
130 | { | ||
131 | if (unlikely(gpio_request(104, "ETH_RESET_N"))) { | ||
132 | printk(KERN_ERR "Can't get hold of GPIO 104 to bring Ethernet " | ||
133 | "PHY out of reset\n"); | ||
134 | return -EIO; | ||
135 | } | ||
136 | |||
137 | gpio_direction_output(104, 1); | ||
138 | gpio_free(104); | ||
139 | return 0; | ||
140 | } | ||
141 | |||
142 | struct pxa168_eth_platform_data gplugd_eth_platform_data = { | ||
143 | .port_number = 0, | ||
144 | .phy_addr = 0, | ||
145 | .speed = 0, /* Autonagotiation */ | ||
146 | .init = gplugd_eth_init, | ||
147 | }; | ||
148 | |||
149 | static void __init select_disp_freq(void) | ||
150 | { | ||
151 | /* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */ | ||
152 | if (unlikely(gpio_request(35, "DISP_FREQ_SEL"))) { | ||
153 | printk(KERN_ERR "Can't get hold of GPIO 35 to select display " | ||
154 | "frequency\n"); | ||
155 | } else { | ||
156 | gpio_direction_output(35, 1); | ||
157 | gpio_free(104); | ||
158 | } | ||
159 | |||
160 | if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) { | ||
161 | printk(KERN_ERR "Can't get hold of GPIO 85 to select display " | ||
162 | "frequency\n"); | ||
163 | } else { | ||
164 | gpio_direction_output(85, 0); | ||
165 | gpio_free(104); | ||
166 | } | ||
167 | } | ||
168 | |||
169 | static void __init gplugd_init(void) | ||
170 | { | ||
171 | mfp_config(ARRAY_AND_SIZE(gplugd_pin_config)); | ||
172 | |||
173 | select_disp_freq(); | ||
174 | |||
175 | /* on-chip devices */ | ||
176 | pxa168_add_uart(3); | ||
177 | pxa168_add_ssp(0); | ||
178 | pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info)); | ||
179 | |||
180 | pxa168_add_eth(&gplugd_eth_platform_data); | ||
181 | } | ||
182 | |||
183 | MACHINE_START(SHEEVAD, "PXA168-based GuruPlug Display (gplugD) Platform") | ||
184 | .map_io = mmp_map_io, | ||
185 | .nr_irqs = IRQ_BOARD_START, | ||
186 | .init_irq = pxa168_init_irq, | ||
187 | .timer = &pxa168_timer, | ||
188 | .init_machine = gplugd_init, | ||
189 | MACHINE_END | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp-gplugd.h b/arch/arm/mach-mmp/include/mach/mfp-gplugd.h new file mode 100644 index 000000000000..b8cf38d85600 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-gplugd.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-mmp/include/mach/mfp-gplugd.h | ||
3 | * | ||
4 | * MFP definitions used in gplugD | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __MACH_MFP_GPLUGD_H | ||
12 | #define __MACH_MFP_GPLUGD_H | ||
13 | |||
14 | #include <plat/mfp.h> | ||
15 | #include <mach/mfp.h> | ||
16 | |||
17 | /* UART3 */ | ||
18 | #define GPIO8_UART3_SOUT MFP_CFG(GPIO8, AF2) | ||
19 | #define GPIO9_UART3_SIN MFP_CFG(GPIO9, AF2) | ||
20 | #define GPI1O_UART3_CTS MFP_CFG(GPIO10, AF2) | ||
21 | #define GPI11_UART3_RTS MFP_CFG(GPIO11, AF2) | ||
22 | |||
23 | /* MMC2 */ | ||
24 | #define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST) | ||
25 | #define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST) | ||
26 | #define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST) | ||
27 | #define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST) | ||
28 | #define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST) | ||
29 | #define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST) | ||
30 | |||
31 | /* I2S */ | ||
32 | #undef GPIO114_I2S_FRM | ||
33 | #undef GPIO115_I2S_BCLK | ||
34 | |||
35 | #define GPIO114_I2S_FRM MFP_CFG_DRV(GPIO114, AF1, FAST) | ||
36 | #define GPIO115_I2S_BCLK MFP_CFG_DRV(GPIO115, AF1, FAST) | ||
37 | #define GPIO116_I2S_TXD MFP_CFG_DRV(GPIO116, AF1, FAST) | ||
38 | |||
39 | /* MMC4 */ | ||
40 | #define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST) | ||
41 | #define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST) | ||
42 | #define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST) | ||
43 | #define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST) | ||
44 | #define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST) | ||
45 | #define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST) | ||
46 | |||
47 | /* OTG GPIO */ | ||
48 | #define GPIO_USB_OTG_PEN 18 | ||
49 | #define GPIO_USB_OIDIR 20 | ||
50 | |||
51 | /* Other GPIOs are 35, 84, 85 */ | ||
52 | #endif /* __MACH_MFP_GPLUGD_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index 713be155a44d..8c782328b21c 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h | |||
@@ -305,4 +305,23 @@ | |||
305 | #define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7) | 305 | #define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7) |
306 | #define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7) | 306 | #define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7) |
307 | 307 | ||
308 | /* Fast Ethernet */ | ||
309 | #define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5) | ||
310 | #define GPIO87_TX_EN MFP_CFG(GPIO87, AF5) | ||
311 | #define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5) | ||
312 | #define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5) | ||
313 | #define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5) | ||
314 | #define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5) | ||
315 | #define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5) | ||
316 | #define GPIO93_MII_COL MFP_CFG(GPIO93, AF5) | ||
317 | #define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5) | ||
318 | #define GPIO95_RX_ER MFP_CFG(GPIO95, AF5) | ||
319 | #define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5) | ||
320 | #define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5) | ||
321 | #define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5) | ||
322 | #define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5) | ||
323 | #define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5) | ||
324 | #define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5) | ||
325 | #define GPIO103_RX_DV MFP_CFG(GPIO103, AF5) | ||
326 | |||
308 | #endif /* __ASM_MACH_MFP_PXA168_H */ | 327 | #endif /* __ASM_MACH_MFP_PXA168_H */ |
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index a52b3d2f325c..7f005843a707 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h | |||
@@ -14,9 +14,11 @@ extern void pxa168_clear_keypad_wakeup(void); | |||
14 | #include <video/pxa168fb.h> | 14 | #include <video/pxa168fb.h> |
15 | #include <plat/pxa27x_keypad.h> | 15 | #include <plat/pxa27x_keypad.h> |
16 | #include <mach/cputype.h> | 16 | #include <mach/cputype.h> |
17 | #include <linux/pxa168_eth.h> | ||
17 | 18 | ||
18 | extern struct pxa_device_desc pxa168_device_uart1; | 19 | extern struct pxa_device_desc pxa168_device_uart1; |
19 | extern struct pxa_device_desc pxa168_device_uart2; | 20 | extern struct pxa_device_desc pxa168_device_uart2; |
21 | extern struct pxa_device_desc pxa168_device_uart3; | ||
20 | extern struct pxa_device_desc pxa168_device_twsi0; | 22 | extern struct pxa_device_desc pxa168_device_twsi0; |
21 | extern struct pxa_device_desc pxa168_device_twsi1; | 23 | extern struct pxa_device_desc pxa168_device_twsi1; |
22 | extern struct pxa_device_desc pxa168_device_pwm1; | 24 | extern struct pxa_device_desc pxa168_device_pwm1; |
@@ -31,6 +33,7 @@ extern struct pxa_device_desc pxa168_device_ssp5; | |||
31 | extern struct pxa_device_desc pxa168_device_nand; | 33 | extern struct pxa_device_desc pxa168_device_nand; |
32 | extern struct pxa_device_desc pxa168_device_fb; | 34 | extern struct pxa_device_desc pxa168_device_fb; |
33 | extern struct pxa_device_desc pxa168_device_keypad; | 35 | extern struct pxa_device_desc pxa168_device_keypad; |
36 | extern struct pxa_device_desc pxa168_device_eth; | ||
34 | 37 | ||
35 | static inline int pxa168_add_uart(int id) | 38 | static inline int pxa168_add_uart(int id) |
36 | { | 39 | { |
@@ -39,6 +42,7 @@ static inline int pxa168_add_uart(int id) | |||
39 | switch (id) { | 42 | switch (id) { |
40 | case 1: d = &pxa168_device_uart1; break; | 43 | case 1: d = &pxa168_device_uart1; break; |
41 | case 2: d = &pxa168_device_uart2; break; | 44 | case 2: d = &pxa168_device_uart2; break; |
45 | case 3: d = &pxa168_device_uart3; break; | ||
42 | } | 46 | } |
43 | 47 | ||
44 | if (d == NULL) | 48 | if (d == NULL) |
@@ -117,4 +121,8 @@ static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data) | |||
117 | return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data)); | 121 | return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data)); |
118 | } | 122 | } |
119 | 123 | ||
124 | static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data) | ||
125 | { | ||
126 | return pxa_register_device(&pxa168_device_eth, data, sizeof(*data)); | ||
127 | } | ||
120 | #endif /* __ASM_MACH_PXA168_H */ | 128 | #endif /* __ASM_MACH_PXA168_H */ |
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h index f7011ef70bf5..8447ac63e28f 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h | |||
@@ -29,6 +29,7 @@ | |||
29 | #define APMU_BUS APMU_REG(0x06c) | 29 | #define APMU_BUS APMU_REG(0x06c) |
30 | #define APMU_SDH2 APMU_REG(0x0e8) | 30 | #define APMU_SDH2 APMU_REG(0x0e8) |
31 | #define APMU_SDH3 APMU_REG(0x0ec) | 31 | #define APMU_SDH3 APMU_REG(0x0ec) |
32 | #define APMU_ETH APMU_REG(0x0fc) | ||
32 | 33 | ||
33 | #define APMU_FNCLK_EN (1 << 4) | 34 | #define APMU_FNCLK_EN (1 << 4) |
34 | #define APMU_AXICLK_EN (1 << 3) | 35 | #define APMU_AXICLK_EN (1 << 3) |
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index ab9f999106c7..0156f535dae7 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c | |||
@@ -66,6 +66,7 @@ void __init pxa168_init_irq(void) | |||
66 | /* APB peripheral clocks */ | 66 | /* APB peripheral clocks */ |
67 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); | 67 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); |
68 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); | 68 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); |
69 | static APBC_CLK(uart3, PXA168_UART3, 1, 14745600); | ||
69 | static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); | 70 | static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); |
70 | static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); | 71 | static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); |
71 | static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); | 72 | static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); |
@@ -81,11 +82,13 @@ static APBC_CLK(keypad, PXA168_KPC, 0, 32000); | |||
81 | 82 | ||
82 | static APMU_CLK(nand, NAND, 0x19b, 156000000); | 83 | static APMU_CLK(nand, NAND, 0x19b, 156000000); |
83 | static APMU_CLK(lcd, LCD, 0x7f, 312000000); | 84 | static APMU_CLK(lcd, LCD, 0x7f, 312000000); |
85 | static APMU_CLK(eth, ETH, 0x09, 0); | ||
84 | 86 | ||
85 | /* device and clock bindings */ | 87 | /* device and clock bindings */ |
86 | static struct clk_lookup pxa168_clkregs[] = { | 88 | static struct clk_lookup pxa168_clkregs[] = { |
87 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | 89 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), |
88 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | 90 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), |
91 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), | ||
89 | INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), | 92 | INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), |
90 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), | 93 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), |
91 | INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), | 94 | INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), |
@@ -100,6 +103,7 @@ static struct clk_lookup pxa168_clkregs[] = { | |||
100 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | 103 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), |
101 | INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), | 104 | INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), |
102 | INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), | 105 | INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), |
106 | INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), | ||
103 | }; | 107 | }; |
104 | 108 | ||
105 | static int __init pxa168_init(void) | 109 | static int __init pxa168_init(void) |
@@ -149,6 +153,7 @@ void pxa168_clear_keypad_wakeup(void) | |||
149 | /* on-chip devices */ | 153 | /* on-chip devices */ |
150 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); | 154 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); |
151 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); | 155 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); |
156 | PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24); | ||
152 | PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); | 157 | PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); |
153 | PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); | 158 | PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); |
154 | PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); | 159 | PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); |
@@ -163,3 +168,4 @@ PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); | |||
163 | PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); | 168 | PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); |
164 | PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8); | 169 | PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8); |
165 | PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c); | 170 | PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c); |
171 | PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff); | ||
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index e411039ea59e..6bd37a27e5fc 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c | |||
@@ -15,6 +15,8 @@ | |||
15 | #include <linux/mtd/partitions.h> | 15 | #include <linux/mtd/partitions.h> |
16 | #include <linux/mtd/onenand.h> | 16 | #include <linux/mtd/onenand.h> |
17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
18 | #include <linux/i2c/pca953x.h> | ||
19 | #include <linux/gpio.h> | ||
18 | 20 | ||
19 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
20 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
@@ -25,7 +27,17 @@ | |||
25 | 27 | ||
26 | #include "common.h" | 28 | #include "common.h" |
27 | 29 | ||
28 | #define TTCDKB_NR_IRQS (IRQ_BOARD_START + 24) | 30 | #define TTCDKB_GPIO_EXT0(x) (NR_BUILTIN_GPIO + ((x < 0) ? 0 : \ |
31 | ((x < 16) ? x : 15))) | ||
32 | #define TTCDKB_GPIO_EXT1(x) (NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \ | ||
33 | ((x < 16) ? x : 15))) | ||
34 | |||
35 | /* | ||
36 | * 16 board interrupts -- MAX7312 GPIO expander | ||
37 | * 16 board interrupts -- PCA9575 GPIO expander | ||
38 | * 24 board interrupts -- 88PM860x PMIC | ||
39 | */ | ||
40 | #define TTCDKB_NR_IRQS (IRQ_BOARD_START + 16 + 16 + 24) | ||
29 | 41 | ||
30 | static unsigned long ttc_dkb_pin_config[] __initdata = { | 42 | static unsigned long ttc_dkb_pin_config[] __initdata = { |
31 | /* UART2 */ | 43 | /* UART2 */ |
@@ -113,6 +125,22 @@ static struct platform_device *ttc_dkb_devices[] = { | |||
113 | &ttc_dkb_device_onenand, | 125 | &ttc_dkb_device_onenand, |
114 | }; | 126 | }; |
115 | 127 | ||
128 | static struct pca953x_platform_data max7312_data[] = { | ||
129 | { | ||
130 | .gpio_base = TTCDKB_GPIO_EXT0(0), | ||
131 | .irq_base = IRQ_BOARD_START, | ||
132 | }, | ||
133 | }; | ||
134 | |||
135 | static struct i2c_board_info ttc_dkb_i2c_info[] = { | ||
136 | { | ||
137 | .type = "max7312", | ||
138 | .addr = 0x23, | ||
139 | .irq = IRQ_GPIO(80), | ||
140 | .platform_data = &max7312_data, | ||
141 | }, | ||
142 | }; | ||
143 | |||
116 | static void __init ttc_dkb_init(void) | 144 | static void __init ttc_dkb_init(void) |
117 | { | 145 | { |
118 | mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); | 146 | mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); |
@@ -121,6 +149,7 @@ static void __init ttc_dkb_init(void) | |||
121 | pxa910_add_uart(1); | 149 | pxa910_add_uart(1); |
122 | 150 | ||
123 | /* off-chip devices */ | 151 | /* off-chip devices */ |
152 | pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info)); | ||
124 | platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices)); | 153 | platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices)); |
125 | } | 154 | } |
126 | 155 | ||
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index f25e9d7bf0f5..b4e7c58bbb38 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig | |||
@@ -180,6 +180,7 @@ config MACH_MX53_EVK | |||
180 | select IMX_HAVE_PLATFORM_IMX_I2C | 180 | select IMX_HAVE_PLATFORM_IMX_I2C |
181 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 181 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
182 | select IMX_HAVE_PLATFORM_SPI_IMX | 182 | select IMX_HAVE_PLATFORM_SPI_IMX |
183 | select LEDS_GPIO_REGISTER | ||
183 | help | 184 | help |
184 | Include support for MX53 EVK platform. This includes specific | 185 | Include support for MX53 EVK platform. This includes specific |
185 | configurations for the board and its peripherals. | 186 | configurations for the board and its peripherals. |
@@ -203,10 +204,23 @@ config MACH_MX53_LOCO | |||
203 | select IMX_HAVE_PLATFORM_IMX_UART | 204 | select IMX_HAVE_PLATFORM_IMX_UART |
204 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 205 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
205 | select IMX_HAVE_PLATFORM_GPIO_KEYS | 206 | select IMX_HAVE_PLATFORM_GPIO_KEYS |
207 | select LEDS_GPIO_REGISTER | ||
206 | help | 208 | help |
207 | Include support for MX53 LOCO platform. This includes specific | 209 | Include support for MX53 LOCO platform. This includes specific |
208 | configurations for the board and its peripherals. | 210 | configurations for the board and its peripherals. |
209 | 211 | ||
212 | config MACH_MX53_ARD | ||
213 | bool "Support MX53 ARD platforms" | ||
214 | select SOC_IMX53 | ||
215 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
216 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
217 | select IMX_HAVE_PLATFORM_IMX_UART | ||
218 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
219 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
220 | help | ||
221 | Include support for MX53 ARD platform. This includes specific | ||
222 | configurations for the board and its peripherals. | ||
223 | |||
210 | endif # ARCH_MX53_SUPPORTED | 224 | endif # ARCH_MX53_SUPPORTED |
211 | 225 | ||
212 | endif | 226 | endif |
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 0b9338cec516..383e7cd3fbcb 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile | |||
@@ -6,12 +6,14 @@ | |||
6 | obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o | 6 | obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o |
7 | obj-$(CONFIG_SOC_IMX50) += mm-mx50.o | 7 | obj-$(CONFIG_SOC_IMX50) += mm-mx50.o |
8 | 8 | ||
9 | obj-$(CONFIG_PM) += pm-imx5.o | ||
9 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o | 10 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o |
10 | obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o | 11 | obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o |
11 | obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o | 12 | obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o |
12 | obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o | 13 | obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o |
13 | obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o | 14 | obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o |
14 | obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o | 15 | obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o |
16 | obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o | ||
15 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o | 17 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o |
16 | obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o | 18 | obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o |
17 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o | 19 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o |
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index e54e4bf61cfd..15c600026aee 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c | |||
@@ -41,6 +41,10 @@ | |||
41 | #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) | 41 | #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) |
42 | #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) | 42 | #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) |
43 | #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) | 43 | #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) |
44 | #define BABBAGE_SD1_CD IMX_GPIO_NR(1, 0) | ||
45 | #define BABBAGE_SD1_WP IMX_GPIO_NR(1, 1) | ||
46 | #define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6) | ||
47 | #define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5) | ||
44 | 48 | ||
45 | /* USB_CTRL_1 */ | 49 | /* USB_CTRL_1 */ |
46 | #define MX51_USB_CTRL_1_OFFSET 0x10 | 50 | #define MX51_USB_CTRL_1_OFFSET 0x10 |
@@ -142,6 +146,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = { | |||
142 | MX51_PAD_SD1_DATA1__SD1_DATA1, | 146 | MX51_PAD_SD1_DATA1__SD1_DATA1, |
143 | MX51_PAD_SD1_DATA2__SD1_DATA2, | 147 | MX51_PAD_SD1_DATA2__SD1_DATA2, |
144 | MX51_PAD_SD1_DATA3__SD1_DATA3, | 148 | MX51_PAD_SD1_DATA3__SD1_DATA3, |
149 | MX51_PAD_GPIO1_0__GPIO1_0, | ||
150 | MX51_PAD_GPIO1_1__GPIO1_1, | ||
145 | 151 | ||
146 | /* SD 2 */ | 152 | /* SD 2 */ |
147 | MX51_PAD_SD2_CMD__SD2_CMD, | 153 | MX51_PAD_SD2_CMD__SD2_CMD, |
@@ -150,6 +156,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = { | |||
150 | MX51_PAD_SD2_DATA1__SD2_DATA1, | 156 | MX51_PAD_SD2_DATA1__SD2_DATA1, |
151 | MX51_PAD_SD2_DATA2__SD2_DATA2, | 157 | MX51_PAD_SD2_DATA2__SD2_DATA2, |
152 | MX51_PAD_SD2_DATA3__SD2_DATA3, | 158 | MX51_PAD_SD2_DATA3__SD2_DATA3, |
159 | MX51_PAD_GPIO1_6__GPIO1_6, | ||
160 | MX51_PAD_GPIO1_5__GPIO1_5, | ||
153 | 161 | ||
154 | /* eCSPI1 */ | 162 | /* eCSPI1 */ |
155 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, | 163 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, |
@@ -331,6 +339,16 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { | |||
331 | .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), | 339 | .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), |
332 | }; | 340 | }; |
333 | 341 | ||
342 | static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = { | ||
343 | .cd_gpio = BABBAGE_SD1_CD, | ||
344 | .wp_gpio = BABBAGE_SD1_WP, | ||
345 | }; | ||
346 | |||
347 | static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = { | ||
348 | .cd_gpio = BABBAGE_SD2_CD, | ||
349 | .wp_gpio = BABBAGE_SD2_WP, | ||
350 | }; | ||
351 | |||
334 | /* | 352 | /* |
335 | * Board specific initialization. | 353 | * Board specific initialization. |
336 | */ | 354 | */ |
@@ -376,8 +394,8 @@ static void __init mx51_babbage_init(void) | |||
376 | mxc_iomux_v3_setup_pad(usbh1stp); | 394 | mxc_iomux_v3_setup_pad(usbh1stp); |
377 | babbage_usbhub_reset(); | 395 | babbage_usbhub_reset(); |
378 | 396 | ||
379 | imx51_add_sdhci_esdhc_imx(0, NULL); | 397 | imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data); |
380 | imx51_add_sdhci_esdhc_imx(1, NULL); | 398 | imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data); |
381 | 399 | ||
382 | spi_register_board_info(mx51_babbage_spi_board_info, | 400 | spi_register_board_info(mx51_babbage_spi_board_info, |
383 | ARRAY_SIZE(mx51_babbage_spi_board_info)); | 401 | ARRAY_SIZE(mx51_babbage_spi_board_info)); |
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c new file mode 100644 index 000000000000..76a67c4a2a0b --- /dev/null +++ b/arch/arm/mach-mx5/board-mx53_ard.c | |||
@@ -0,0 +1,254 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | |||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | |||
16 | * You should have received a copy of the GNU General Public License along | ||
17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
19 | */ | ||
20 | |||
21 | #include <linux/init.h> | ||
22 | #include <linux/clk.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/gpio.h> | ||
25 | #include <linux/smsc911x.h> | ||
26 | |||
27 | #include <mach/common.h> | ||
28 | #include <mach/hardware.h> | ||
29 | #include <mach/iomux-mx53.h> | ||
30 | |||
31 | #include <asm/mach-types.h> | ||
32 | #include <asm/mach/arch.h> | ||
33 | #include <asm/mach/time.h> | ||
34 | |||
35 | #include "crm_regs.h" | ||
36 | #include "devices-imx53.h" | ||
37 | |||
38 | #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) | ||
39 | #define ARD_SD1_CD IMX_GPIO_NR(1, 1) | ||
40 | #define ARD_SD1_WP IMX_GPIO_NR(1, 9) | ||
41 | #define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3) | ||
42 | #define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0) | ||
43 | #define ARD_HOME IMX_GPIO_NR(5, 10) | ||
44 | #define ARD_BACK IMX_GPIO_NR(5, 11) | ||
45 | #define ARD_PROG IMX_GPIO_NR(5, 12) | ||
46 | #define ARD_VOLUMEUP IMX_GPIO_NR(5, 13) | ||
47 | |||
48 | static iomux_v3_cfg_t mx53_ard_pads[] = { | ||
49 | /* UART1 */ | ||
50 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX, | ||
51 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX, | ||
52 | /* WEIM for CS1 */ | ||
53 | MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ | ||
54 | MX53_PAD_EIM_D16__EMI_WEIM_D_16, | ||
55 | MX53_PAD_EIM_D17__EMI_WEIM_D_17, | ||
56 | MX53_PAD_EIM_D18__EMI_WEIM_D_18, | ||
57 | MX53_PAD_EIM_D19__EMI_WEIM_D_19, | ||
58 | MX53_PAD_EIM_D20__EMI_WEIM_D_20, | ||
59 | MX53_PAD_EIM_D21__EMI_WEIM_D_21, | ||
60 | MX53_PAD_EIM_D22__EMI_WEIM_D_22, | ||
61 | MX53_PAD_EIM_D23__EMI_WEIM_D_23, | ||
62 | MX53_PAD_EIM_D24__EMI_WEIM_D_24, | ||
63 | MX53_PAD_EIM_D25__EMI_WEIM_D_25, | ||
64 | MX53_PAD_EIM_D26__EMI_WEIM_D_26, | ||
65 | MX53_PAD_EIM_D27__EMI_WEIM_D_27, | ||
66 | MX53_PAD_EIM_D28__EMI_WEIM_D_28, | ||
67 | MX53_PAD_EIM_D29__EMI_WEIM_D_29, | ||
68 | MX53_PAD_EIM_D30__EMI_WEIM_D_30, | ||
69 | MX53_PAD_EIM_D31__EMI_WEIM_D_31, | ||
70 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, | ||
71 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, | ||
72 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, | ||
73 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, | ||
74 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, | ||
75 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, | ||
76 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, | ||
77 | MX53_PAD_EIM_OE__EMI_WEIM_OE, | ||
78 | MX53_PAD_EIM_RW__EMI_WEIM_RW, | ||
79 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, | ||
80 | /* SDHC1 */ | ||
81 | MX53_PAD_SD1_CMD__ESDHC1_CMD, | ||
82 | MX53_PAD_SD1_CLK__ESDHC1_CLK, | ||
83 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0, | ||
84 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | ||
85 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | ||
86 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | ||
87 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4, | ||
88 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5, | ||
89 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6, | ||
90 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7, | ||
91 | MX53_PAD_GPIO_1__GPIO1_1, | ||
92 | MX53_PAD_GPIO_9__GPIO1_9, | ||
93 | /* I2C2 */ | ||
94 | MX53_PAD_EIM_EB2__I2C2_SCL, | ||
95 | MX53_PAD_KEY_ROW3__I2C2_SDA, | ||
96 | /* I2C3 */ | ||
97 | MX53_PAD_GPIO_3__I2C3_SCL, | ||
98 | MX53_PAD_GPIO_16__I2C3_SDA, | ||
99 | /* GPIO */ | ||
100 | MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */ | ||
101 | MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */ | ||
102 | MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */ | ||
103 | MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */ | ||
104 | MX53_PAD_GPIO_10__GPIO4_0, /* vol down */ | ||
105 | }; | ||
106 | |||
107 | #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ | ||
108 | { \ | ||
109 | .gpio = gpio_num, \ | ||
110 | .type = EV_KEY, \ | ||
111 | .code = ev_code, \ | ||
112 | .active_low = act_low, \ | ||
113 | .desc = "btn " descr, \ | ||
114 | .wakeup = wake, \ | ||
115 | } | ||
116 | |||
117 | static struct gpio_keys_button ard_buttons[] = { | ||
118 | GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0), | ||
119 | GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0), | ||
120 | GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0), | ||
121 | GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0), | ||
122 | GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0), | ||
123 | }; | ||
124 | |||
125 | static const struct gpio_keys_platform_data ard_button_data __initconst = { | ||
126 | .buttons = ard_buttons, | ||
127 | .nbuttons = ARRAY_SIZE(ard_buttons), | ||
128 | }; | ||
129 | |||
130 | static struct resource ard_smsc911x_resources[] = { | ||
131 | { | ||
132 | .start = MX53_CS1_64MB_BASE_ADDR, | ||
133 | .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, | ||
134 | .flags = IORESOURCE_MEM, | ||
135 | }, | ||
136 | { | ||
137 | .start = gpio_to_irq(ARD_ETHERNET_INT_B), | ||
138 | .end = gpio_to_irq(ARD_ETHERNET_INT_B), | ||
139 | .flags = IORESOURCE_IRQ, | ||
140 | }, | ||
141 | }; | ||
142 | |||
143 | struct smsc911x_platform_config ard_smsc911x_config = { | ||
144 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
145 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
146 | .flags = SMSC911X_USE_32BIT, | ||
147 | }; | ||
148 | |||
149 | static struct platform_device ard_smsc_lan9220_device = { | ||
150 | .name = "smsc911x", | ||
151 | .id = -1, | ||
152 | .num_resources = ARRAY_SIZE(ard_smsc911x_resources), | ||
153 | .resource = ard_smsc911x_resources, | ||
154 | .dev = { | ||
155 | .platform_data = &ard_smsc911x_config, | ||
156 | }, | ||
157 | }; | ||
158 | |||
159 | static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = { | ||
160 | .cd_gpio = ARD_SD1_CD, | ||
161 | .wp_gpio = ARD_SD1_WP, | ||
162 | }; | ||
163 | |||
164 | static struct imxi2c_platform_data mx53_ard_i2c2_data = { | ||
165 | .bitrate = 50000, | ||
166 | }; | ||
167 | |||
168 | static struct imxi2c_platform_data mx53_ard_i2c3_data = { | ||
169 | .bitrate = 400000, | ||
170 | }; | ||
171 | |||
172 | static void __init mx53_ard_io_init(void) | ||
173 | { | ||
174 | mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, | ||
175 | ARRAY_SIZE(mx53_ard_pads)); | ||
176 | |||
177 | gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); | ||
178 | gpio_direction_input(ARD_ETHERNET_INT_B); | ||
179 | |||
180 | gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst"); | ||
181 | gpio_direction_output(ARD_I2CPORTEXP_B, 1); | ||
182 | } | ||
183 | |||
184 | /* Config CS1 settings for ethernet controller */ | ||
185 | static int weim_cs_config(void) | ||
186 | { | ||
187 | u32 reg; | ||
188 | void __iomem *weim_base, *iomuxc_base; | ||
189 | |||
190 | weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); | ||
191 | if (!weim_base) | ||
192 | return -ENOMEM; | ||
193 | |||
194 | iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); | ||
195 | if (!iomuxc_base) | ||
196 | return -ENOMEM; | ||
197 | |||
198 | /* CS1 timings for LAN9220 */ | ||
199 | writel(0x20001, (weim_base + 0x18)); | ||
200 | writel(0x0, (weim_base + 0x1C)); | ||
201 | writel(0x16000202, (weim_base + 0x20)); | ||
202 | writel(0x00000002, (weim_base + 0x24)); | ||
203 | writel(0x16002082, (weim_base + 0x28)); | ||
204 | writel(0x00000000, (weim_base + 0x2C)); | ||
205 | writel(0x00000000, (weim_base + 0x90)); | ||
206 | |||
207 | /* specify 64 MB on CS1 and CS0 on GPR1 */ | ||
208 | reg = readl(iomuxc_base + 0x4); | ||
209 | reg &= ~0x3F; | ||
210 | reg |= 0x1B; | ||
211 | writel(reg, (iomuxc_base + 0x4)); | ||
212 | |||
213 | iounmap(iomuxc_base); | ||
214 | iounmap(weim_base); | ||
215 | |||
216 | return 0; | ||
217 | } | ||
218 | |||
219 | static struct platform_device *devices[] __initdata = { | ||
220 | &ard_smsc_lan9220_device, | ||
221 | }; | ||
222 | |||
223 | static void __init mx53_ard_board_init(void) | ||
224 | { | ||
225 | imx53_soc_init(); | ||
226 | imx53_add_imx_uart(0, NULL); | ||
227 | |||
228 | mx53_ard_io_init(); | ||
229 | weim_cs_config(); | ||
230 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
231 | |||
232 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); | ||
233 | imx53_add_imx2_wdt(0, NULL); | ||
234 | imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); | ||
235 | imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); | ||
236 | imx_add_gpio_keys(&ard_button_data); | ||
237 | } | ||
238 | |||
239 | static void __init mx53_ard_timer_init(void) | ||
240 | { | ||
241 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
242 | } | ||
243 | |||
244 | static struct sys_timer mx53_ard_timer = { | ||
245 | .init = mx53_ard_timer_init, | ||
246 | }; | ||
247 | |||
248 | MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") | ||
249 | .map_io = mx53_map_io, | ||
250 | .init_early = imx53_init_early, | ||
251 | .init_irq = mx53_init_irq, | ||
252 | .timer = &mx53_ard_timer, | ||
253 | .init_machine = mx53_ard_board_init, | ||
254 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 0d9218a6e2d2..1b417b06b736 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) | 35 | #define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) |
36 | #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) | 36 | #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) |
37 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) | 37 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) |
38 | #define MX53EVK_LED IMX_GPIO_NR(7, 7) | ||
38 | 39 | ||
39 | #include "crm_regs.h" | 40 | #include "crm_regs.h" |
40 | #include "devices-imx53.h" | 41 | #include "devices-imx53.h" |
@@ -58,12 +59,27 @@ static iomux_v3_cfg_t mx53_evk_pads[] = { | |||
58 | /* ecspi chip select lines */ | 59 | /* ecspi chip select lines */ |
59 | MX53_PAD_EIM_EB2__GPIO2_30, | 60 | MX53_PAD_EIM_EB2__GPIO2_30, |
60 | MX53_PAD_EIM_D19__GPIO3_19, | 61 | MX53_PAD_EIM_D19__GPIO3_19, |
62 | /* LED */ | ||
63 | MX53_PAD_PATA_DA_1__GPIO7_7, | ||
61 | }; | 64 | }; |
62 | 65 | ||
63 | static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { | 66 | static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { |
64 | .flags = IMXUART_HAVE_RTSCTS, | 67 | .flags = IMXUART_HAVE_RTSCTS, |
65 | }; | 68 | }; |
66 | 69 | ||
70 | static const struct gpio_led mx53evk_leds[] __initconst = { | ||
71 | { | ||
72 | .name = "green", | ||
73 | .default_trigger = "heartbeat", | ||
74 | .gpio = MX53EVK_LED, | ||
75 | }, | ||
76 | }; | ||
77 | |||
78 | static const struct gpio_led_platform_data mx53evk_leds_data __initconst = { | ||
79 | .leds = mx53evk_leds, | ||
80 | .num_leds = ARRAY_SIZE(mx53evk_leds), | ||
81 | }; | ||
82 | |||
67 | static inline void mx53_evk_init_uart(void) | 83 | static inline void mx53_evk_init_uart(void) |
68 | { | 84 | { |
69 | imx53_add_imx_uart(0, NULL); | 85 | imx53_add_imx_uart(0, NULL); |
@@ -135,6 +151,7 @@ static void __init mx53_evk_board_init(void) | |||
135 | ARRAY_SIZE(mx53_evk_spi_board_info)); | 151 | ARRAY_SIZE(mx53_evk_spi_board_info)); |
136 | imx53_add_ecspi(0, &mx53_evk_spi_data); | 152 | imx53_add_ecspi(0, &mx53_evk_spi_data); |
137 | imx53_add_imx2_wdt(0, NULL); | 153 | imx53_add_imx2_wdt(0, NULL); |
154 | gpio_led_register_device(-1, &mx53evk_leds_data); | ||
138 | } | 155 | } |
139 | 156 | ||
140 | static void __init mx53_evk_timer_init(void) | 157 | static void __init mx53_evk_timer_init(void) |
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 359c3e248add..54be525e2bd7 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c | |||
@@ -38,6 +38,10 @@ | |||
38 | #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) | 38 | #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) |
39 | #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) | 39 | #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) |
40 | #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) | 40 | #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) |
41 | #define LOCO_LED IMX_GPIO_NR(7, 7) | ||
42 | #define LOCO_SD3_CD IMX_GPIO_NR(3, 11) | ||
43 | #define LOCO_SD3_WP IMX_GPIO_NR(3, 12) | ||
44 | #define LOCO_SD1_CD IMX_GPIO_NR(3, 13) | ||
41 | 45 | ||
42 | static iomux_v3_cfg_t mx53_loco_pads[] = { | 46 | static iomux_v3_cfg_t mx53_loco_pads[] = { |
43 | /* FEC */ | 47 | /* FEC */ |
@@ -70,6 +74,8 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { | |||
70 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, | 74 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1, |
71 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, | 75 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2, |
72 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, | 76 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3, |
77 | /* SD1_CD */ | ||
78 | MX53_PAD_EIM_DA13__GPIO3_13, | ||
73 | /* SD3 */ | 79 | /* SD3 */ |
74 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0, | 80 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0, |
75 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1, | 81 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1, |
@@ -163,7 +169,7 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { | |||
163 | MX53_PAD_GPIO_7__SPDIF_PLOCK, | 169 | MX53_PAD_GPIO_7__SPDIF_PLOCK, |
164 | MX53_PAD_GPIO_17__SPDIF_OUT1, | 170 | MX53_PAD_GPIO_17__SPDIF_OUT1, |
165 | /* GPIO */ | 171 | /* GPIO */ |
166 | MX53_PAD_PATA_DA_1__GPIO7_7, | 172 | MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */ |
167 | MX53_PAD_PATA_DA_2__GPIO7_8, | 173 | MX53_PAD_PATA_DA_2__GPIO7_8, |
168 | MX53_PAD_PATA_DATA5__GPIO2_5, | 174 | MX53_PAD_PATA_DATA5__GPIO2_5, |
169 | MX53_PAD_PATA_DATA6__GPIO2_6, | 175 | MX53_PAD_PATA_DATA6__GPIO2_6, |
@@ -202,6 +208,15 @@ static const struct gpio_keys_platform_data loco_button_data __initconst = { | |||
202 | .nbuttons = ARRAY_SIZE(loco_buttons), | 208 | .nbuttons = ARRAY_SIZE(loco_buttons), |
203 | }; | 209 | }; |
204 | 210 | ||
211 | static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = { | ||
212 | .cd_gpio = LOCO_SD1_CD, | ||
213 | }; | ||
214 | |||
215 | static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = { | ||
216 | .cd_gpio = LOCO_SD3_CD, | ||
217 | .wp_gpio = LOCO_SD3_WP, | ||
218 | }; | ||
219 | |||
205 | static inline void mx53_loco_fec_reset(void) | 220 | static inline void mx53_loco_fec_reset(void) |
206 | { | 221 | { |
207 | int ret; | 222 | int ret; |
@@ -225,6 +240,19 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { | |||
225 | .bitrate = 100000, | 240 | .bitrate = 100000, |
226 | }; | 241 | }; |
227 | 242 | ||
243 | static const struct gpio_led mx53loco_leds[] __initconst = { | ||
244 | { | ||
245 | .name = "green", | ||
246 | .default_trigger = "heartbeat", | ||
247 | .gpio = LOCO_LED, | ||
248 | }, | ||
249 | }; | ||
250 | |||
251 | static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { | ||
252 | .leds = mx53loco_leds, | ||
253 | .num_leds = ARRAY_SIZE(mx53loco_leds), | ||
254 | }; | ||
255 | |||
228 | static void __init mx53_loco_board_init(void) | 256 | static void __init mx53_loco_board_init(void) |
229 | { | 257 | { |
230 | imx53_soc_init(); | 258 | imx53_soc_init(); |
@@ -237,9 +265,10 @@ static void __init mx53_loco_board_init(void) | |||
237 | imx53_add_imx2_wdt(0, NULL); | 265 | imx53_add_imx2_wdt(0, NULL); |
238 | imx53_add_imx_i2c(0, &mx53_loco_i2c_data); | 266 | imx53_add_imx_i2c(0, &mx53_loco_i2c_data); |
239 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); | 267 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); |
240 | imx53_add_sdhci_esdhc_imx(0, NULL); | 268 | imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); |
241 | imx53_add_sdhci_esdhc_imx(2, NULL); | 269 | imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); |
242 | imx_add_gpio_keys(&loco_button_data); | 270 | imx_add_gpio_keys(&loco_button_data); |
271 | gpio_led_register_device(-1, &mx53loco_leds_data); | ||
243 | } | 272 | } |
244 | 273 | ||
245 | static void __init mx53_loco_timer_init(void) | 274 | static void __init mx53_loco_timer_init(void) |
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 0adeea17d123..23cd809fa8b8 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
@@ -1254,12 +1254,20 @@ DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, | |||
1254 | NULL, NULL, &ipg_clk, &aips_tz1_clk); | 1254 | NULL, NULL, &ipg_clk, &aips_tz1_clk); |
1255 | DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, | 1255 | DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, |
1256 | NULL, NULL, &ipg_clk, &spba_clk); | 1256 | NULL, NULL, &ipg_clk, &spba_clk); |
1257 | DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET, | ||
1258 | NULL, NULL, &ipg_clk, &spba_clk); | ||
1259 | DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET, | ||
1260 | NULL, NULL, &ipg_clk, &spba_clk); | ||
1257 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, | 1261 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, |
1258 | NULL, NULL, &uart_root_clk, &uart1_ipg_clk); | 1262 | NULL, NULL, &uart_root_clk, &uart1_ipg_clk); |
1259 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, | 1263 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, |
1260 | NULL, NULL, &uart_root_clk, &uart2_ipg_clk); | 1264 | NULL, NULL, &uart_root_clk, &uart2_ipg_clk); |
1261 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, | 1265 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, |
1262 | NULL, NULL, &uart_root_clk, &uart3_ipg_clk); | 1266 | NULL, NULL, &uart_root_clk, &uart3_ipg_clk); |
1267 | DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET, | ||
1268 | NULL, NULL, &uart_root_clk, &uart4_ipg_clk); | ||
1269 | DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET, | ||
1270 | NULL, NULL, &uart_root_clk, &uart5_ipg_clk); | ||
1263 | 1271 | ||
1264 | /* GPT */ | 1272 | /* GPT */ |
1265 | DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, | 1273 | DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, |
@@ -1279,6 +1287,8 @@ DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET, | |||
1279 | NULL, NULL, &ipg_perclk, NULL); | 1287 | NULL, NULL, &ipg_perclk, NULL); |
1280 | DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, | 1288 | DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, |
1281 | NULL, NULL, &ipg_clk, NULL); | 1289 | NULL, NULL, &ipg_clk, NULL); |
1290 | DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, | ||
1291 | NULL, NULL, &ipg_perclk, NULL); | ||
1282 | 1292 | ||
1283 | /* FEC */ | 1293 | /* FEC */ |
1284 | DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, | 1294 | DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, |
@@ -1463,11 +1473,14 @@ static struct clk_lookup mx53_lookups[] = { | |||
1463 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | 1473 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
1464 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | 1474 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
1465 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | 1475 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
1476 | _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) | ||
1477 | _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) | ||
1466 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | 1478 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
1467 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | 1479 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
1468 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) | 1480 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) |
1469 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) | 1481 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
1470 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | 1482 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
1483 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk) | ||
1471 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) | 1484 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) |
1472 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk) | 1485 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk) |
1473 | _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk) | 1486 | _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk) |
@@ -1479,6 +1492,11 @@ static struct clk_lookup mx53_lookups[] = { | |||
1479 | _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk) | 1492 | _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk) |
1480 | _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) | 1493 | _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) |
1481 | _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) | 1494 | _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) |
1495 | _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) | ||
1496 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) | ||
1497 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) | ||
1498 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) | ||
1499 | _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) | ||
1482 | }; | 1500 | }; |
1483 | 1501 | ||
1484 | static void clk_tree_init(void) | 1502 | static void clk_tree_init(void) |
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 87c0c58f27a7..5e11ba7daee2 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h | |||
@@ -114,6 +114,8 @@ | |||
114 | #define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) | 114 | #define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) |
115 | #define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) | 115 | #define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) |
116 | #define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) | 116 | #define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) |
117 | #define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) | ||
118 | |||
117 | #define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) | 119 | #define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) |
118 | 120 | ||
119 | /* Define the bits in register CCR */ | 121 | /* Define the bits in register CCR */ |
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index 48f4c8cc42f5..c27fe8bb4762 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h | |||
@@ -32,3 +32,11 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[]; | |||
32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; | 32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; |
33 | #define imx53_add_imx2_wdt(id, pdata) \ | 33 | #define imx53_add_imx2_wdt(id, pdata) \ |
34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) | 34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) |
35 | |||
36 | extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; | ||
37 | #define imx53_add_imx_ssi(id, pdata) \ | ||
38 | imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata) | ||
39 | |||
40 | extern const struct imx_imx_keypad_data imx53_imx_keypad_data; | ||
41 | #define imx53_add_imx_keypad(pdata) \ | ||
42 | imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) | ||
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 665843d6c2b2..ef8aec9319b6 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c | |||
@@ -18,6 +18,7 @@ | |||
18 | 18 | ||
19 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
20 | #include <mach/common.h> | 20 | #include <mach/common.h> |
21 | #include <mach/devices-common.h> | ||
21 | #include <mach/iomux-v3.h> | 22 | #include <mach/iomux-v3.h> |
22 | 23 | ||
23 | /* | 24 | /* |
@@ -100,6 +101,45 @@ void __init mx53_init_irq(void) | |||
100 | tzic_init_irq(tzic_virt); | 101 | tzic_init_irq(tzic_virt); |
101 | } | 102 | } |
102 | 103 | ||
104 | static struct sdma_script_start_addrs imx51_sdma_script __initdata = { | ||
105 | .ap_2_ap_addr = 642, | ||
106 | .uart_2_mcu_addr = 817, | ||
107 | .mcu_2_app_addr = 747, | ||
108 | .mcu_2_shp_addr = 961, | ||
109 | .ata_2_mcu_addr = 1473, | ||
110 | .mcu_2_ata_addr = 1392, | ||
111 | .app_2_per_addr = 1033, | ||
112 | .app_2_mcu_addr = 683, | ||
113 | .shp_2_per_addr = 1251, | ||
114 | .shp_2_mcu_addr = 892, | ||
115 | }; | ||
116 | |||
117 | static struct sdma_platform_data imx51_sdma_pdata __initdata = { | ||
118 | .sdma_version = 2, | ||
119 | .fw_name = "sdma-imx51.bin", | ||
120 | .script_addrs = &imx51_sdma_script, | ||
121 | }; | ||
122 | |||
123 | static struct sdma_script_start_addrs imx53_sdma_script __initdata = { | ||
124 | .ap_2_ap_addr = 642, | ||
125 | .app_2_mcu_addr = 683, | ||
126 | .mcu_2_app_addr = 747, | ||
127 | .uart_2_mcu_addr = 817, | ||
128 | .shp_2_mcu_addr = 891, | ||
129 | .mcu_2_shp_addr = 960, | ||
130 | .uartsh_2_mcu_addr = 1032, | ||
131 | .spdif_2_mcu_addr = 1100, | ||
132 | .mcu_2_spdif_addr = 1134, | ||
133 | .firi_2_mcu_addr = 1193, | ||
134 | .mcu_2_firi_addr = 1290, | ||
135 | }; | ||
136 | |||
137 | static struct sdma_platform_data imx53_sdma_pdata __initdata = { | ||
138 | .sdma_version = 2, | ||
139 | .fw_name = "sdma-imx53.bin", | ||
140 | .script_addrs = &imx53_sdma_script, | ||
141 | }; | ||
142 | |||
103 | void __init imx51_soc_init(void) | 143 | void __init imx51_soc_init(void) |
104 | { | 144 | { |
105 | /* i.mx51 has the i.mx31 type gpio */ | 145 | /* i.mx51 has the i.mx31 type gpio */ |
@@ -107,6 +147,8 @@ void __init imx51_soc_init(void) | |||
107 | mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH); | 147 | mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH); |
108 | mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH); | 148 | mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH); |
109 | mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH); | 149 | mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH); |
150 | |||
151 | imx_add_imx_sdma(MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); | ||
110 | } | 152 | } |
111 | 153 | ||
112 | void __init imx53_soc_init(void) | 154 | void __init imx53_soc_init(void) |
@@ -119,4 +161,6 @@ void __init imx53_soc_init(void) | |||
119 | mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); | 161 | mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); |
120 | mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); | 162 | mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); |
121 | mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); | 163 | mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); |
164 | |||
165 | imx_add_imx_sdma(MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); | ||
122 | } | 166 | } |
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c new file mode 100644 index 000000000000..e4529af0da72 --- /dev/null +++ b/arch/arm/mach-mx5/pm-imx5.c | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | #include <linux/suspend.h> | ||
12 | #include <linux/clk.h> | ||
13 | #include <linux/io.h> | ||
14 | #include <linux/err.h> | ||
15 | #include <asm/cacheflush.h> | ||
16 | #include <asm/tlbflush.h> | ||
17 | #include <mach/system.h> | ||
18 | #include "crm_regs.h" | ||
19 | |||
20 | static struct clk *gpc_dvfs_clk; | ||
21 | |||
22 | static int mx5_suspend_enter(suspend_state_t state) | ||
23 | { | ||
24 | clk_enable(gpc_dvfs_clk); | ||
25 | switch (state) { | ||
26 | case PM_SUSPEND_MEM: | ||
27 | mx5_cpu_lp_set(STOP_POWER_OFF); | ||
28 | break; | ||
29 | case PM_SUSPEND_STANDBY: | ||
30 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | ||
31 | break; | ||
32 | default: | ||
33 | return -EINVAL; | ||
34 | } | ||
35 | |||
36 | if (state == PM_SUSPEND_MEM) { | ||
37 | local_flush_tlb_all(); | ||
38 | flush_cache_all(); | ||
39 | |||
40 | /*clear the EMPGC0/1 bits */ | ||
41 | __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); | ||
42 | __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); | ||
43 | } | ||
44 | cpu_do_idle(); | ||
45 | clk_disable(gpc_dvfs_clk); | ||
46 | |||
47 | return 0; | ||
48 | } | ||
49 | |||
50 | static int mx5_pm_valid(suspend_state_t state) | ||
51 | { | ||
52 | return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); | ||
53 | } | ||
54 | |||
55 | static const struct platform_suspend_ops mx5_suspend_ops = { | ||
56 | .valid = mx5_pm_valid, | ||
57 | .enter = mx5_suspend_enter, | ||
58 | }; | ||
59 | |||
60 | static int __init mx5_pm_init(void) | ||
61 | { | ||
62 | if (gpc_dvfs_clk == NULL) | ||
63 | gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | ||
64 | |||
65 | if (!IS_ERR(gpc_dvfs_clk)) { | ||
66 | if (cpu_is_mx51()) | ||
67 | suspend_set_ops(&mx5_suspend_ops); | ||
68 | } else | ||
69 | return -EPERM; | ||
70 | |||
71 | return 0; | ||
72 | } | ||
73 | device_initcall(mx5_pm_init); | ||
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 162b0b0bc356..4cd0231ee539 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
@@ -41,6 +41,7 @@ config MACH_MX23EVK | |||
41 | config MACH_MX28EVK | 41 | config MACH_MX28EVK |
42 | bool "Support MX28EVK Platform" | 42 | bool "Support MX28EVK Platform" |
43 | select SOC_IMX28 | 43 | select SOC_IMX28 |
44 | select LEDS_GPIO_REGISTER | ||
44 | select MXS_HAVE_AMBA_DUART | 45 | select MXS_HAVE_AMBA_DUART |
45 | select MXS_HAVE_PLATFORM_AUART | 46 | select MXS_HAVE_PLATFORM_AUART |
46 | select MXS_HAVE_PLATFORM_FEC | 47 | select MXS_HAVE_PLATFORM_FEC |
@@ -60,6 +61,7 @@ config MODULE_TX28 | |||
60 | select MXS_HAVE_PLATFORM_AUART | 61 | select MXS_HAVE_PLATFORM_AUART |
61 | select MXS_HAVE_PLATFORM_FEC | 62 | select MXS_HAVE_PLATFORM_FEC |
62 | select MXS_HAVE_PLATFORM_MXS_I2C | 63 | select MXS_HAVE_PLATFORM_MXS_I2C |
64 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
63 | select MXS_HAVE_PLATFORM_MXS_PWM | 65 | select MXS_HAVE_PLATFORM_MXS_PWM |
64 | 66 | ||
65 | config MACH_TX28 | 67 | config MACH_TX28 |
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 56767a5cce0e..eaaf6ff28990 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
18 | #include <linux/leds.h> | ||
18 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
19 | #include <linux/clk.h> | 20 | #include <linux/clk.h> |
20 | 21 | ||
@@ -29,6 +30,7 @@ | |||
29 | 30 | ||
30 | #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) | 31 | #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) |
31 | #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) | 32 | #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) |
33 | #define MX28EVK_GPIO_LED MXS_GPIO_NR(3, 5) | ||
32 | #define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) | 34 | #define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) |
33 | #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) | 35 | #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) |
34 | #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | 36 | #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) |
@@ -178,6 +180,23 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { | |||
178 | /* slot power enable */ | 180 | /* slot power enable */ |
179 | MX28_PAD_PWM4__GPIO_3_29 | | 181 | MX28_PAD_PWM4__GPIO_3_29 | |
180 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | 182 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), |
183 | |||
184 | /* led */ | ||
185 | MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, | ||
186 | }; | ||
187 | |||
188 | /* led */ | ||
189 | static const struct gpio_led mx28evk_leds[] __initconst = { | ||
190 | { | ||
191 | .name = "GPIO-LED", | ||
192 | .default_trigger = "heartbeat", | ||
193 | .gpio = MX28EVK_GPIO_LED, | ||
194 | }, | ||
195 | }; | ||
196 | |||
197 | static const struct gpio_led_platform_data mx28evk_led_data __initconst = { | ||
198 | .leds = mx28evk_leds, | ||
199 | .num_leds = ARRAY_SIZE(mx28evk_leds), | ||
181 | }; | 200 | }; |
182 | 201 | ||
183 | /* fec */ | 202 | /* fec */ |
@@ -385,6 +404,8 @@ static void __init mx28evk_init(void) | |||
385 | if (ret) | 404 | if (ret) |
386 | pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); | 405 | pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); |
387 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); | 406 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); |
407 | |||
408 | gpio_led_register_device(0, &mx28evk_led_data); | ||
388 | } | 409 | } |
389 | 410 | ||
390 | static void __init mx28evk_timer_init(void) | 411 | static void __init mx28evk_timer_init(void) |
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c index 6766a12cca7f..515a423f82cd 100644 --- a/arch/arm/mach-mxs/mach-tx28.c +++ b/arch/arm/mach-mxs/mach-tx28.c | |||
@@ -139,6 +139,11 @@ static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = { | |||
139 | }, | 139 | }, |
140 | }; | 140 | }; |
141 | 141 | ||
142 | static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = { | ||
143 | .wp_gpio = -EINVAL, | ||
144 | .flags = SLOTF_4_BIT_CAPABLE, | ||
145 | }; | ||
146 | |||
142 | static void __init tx28_stk5v3_init(void) | 147 | static void __init tx28_stk5v3_init(void) |
143 | { | 148 | { |
144 | mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, | 149 | mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, |
@@ -155,6 +160,7 @@ static void __init tx28_stk5v3_init(void) | |||
155 | mx28_add_mxs_i2c(0); | 160 | mx28_add_mxs_i2c(0); |
156 | i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, | 161 | i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, |
157 | ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); | 162 | ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); |
163 | mx28_add_mxs_mmc(0, &tx28_mmc0_pdata); | ||
158 | } | 164 | } |
159 | 165 | ||
160 | static void __init tx28_timer_init(void) | 166 | static void __init tx28_timer_init(void) |
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 810a982a66f8..ef3e8b1e06c1 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c | |||
@@ -825,6 +825,7 @@ MACHINE_START(BALLOON3, "Balloon3") | |||
825 | .map_io = balloon3_map_io, | 825 | .map_io = balloon3_map_io, |
826 | .nr_irqs = BALLOON3_NR_IRQS, | 826 | .nr_irqs = BALLOON3_NR_IRQS, |
827 | .init_irq = balloon3_init_irq, | 827 | .init_irq = balloon3_init_irq, |
828 | .handle_irq = pxa27x_handle_irq, | ||
828 | .timer = &pxa_timer, | 829 | .timer = &pxa_timer, |
829 | .init_machine = balloon3_init, | 830 | .init_machine = balloon3_init, |
830 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 831 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c index 4284513f396a..648b0ab2bf77 100644 --- a/arch/arm/mach-pxa/capc7117.c +++ b/arch/arm/mach-pxa/capc7117.c | |||
@@ -151,6 +151,7 @@ MACHINE_START(CAPC7117, | |||
151 | .boot_params = 0xa0000100, | 151 | .boot_params = 0xa0000100, |
152 | .map_io = pxa3xx_map_io, | 152 | .map_io = pxa3xx_map_io, |
153 | .init_irq = pxa3xx_init_irq, | 153 | .init_irq = pxa3xx_init_irq, |
154 | .handle_irq = pxa3xx_handle_irq, | ||
154 | .timer = &pxa_timer, | 155 | .timer = &pxa_timer, |
155 | .init_machine = capc7117_init | 156 | .init_machine = capc7117_init |
156 | MACHINE_END | 157 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index d5152220ce94..4d466102a027 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c | |||
@@ -53,6 +53,21 @@ unsigned long clk_get_rate(struct clk *clk) | |||
53 | } | 53 | } |
54 | EXPORT_SYMBOL(clk_get_rate); | 54 | EXPORT_SYMBOL(clk_get_rate); |
55 | 55 | ||
56 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
57 | { | ||
58 | unsigned long flags; | ||
59 | int ret = -EINVAL; | ||
60 | |||
61 | if (clk->ops->setrate) { | ||
62 | spin_lock_irqsave(&clocks_lock, flags); | ||
63 | ret = clk->ops->setrate(clk, rate); | ||
64 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
65 | } | ||
66 | |||
67 | return ret; | ||
68 | } | ||
69 | EXPORT_SYMBOL(clk_set_rate); | ||
70 | |||
56 | void clk_dummy_enable(struct clk *clk) | 71 | void clk_dummy_enable(struct clk *clk) |
57 | { | 72 | { |
58 | } | 73 | } |
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index 1f2fb9c43f06..3a258b1bf1aa 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h | |||
@@ -5,6 +5,7 @@ struct clkops { | |||
5 | void (*enable)(struct clk *); | 5 | void (*enable)(struct clk *); |
6 | void (*disable)(struct clk *); | 6 | void (*disable)(struct clk *); |
7 | unsigned long (*getrate)(struct clk *); | 7 | unsigned long (*getrate)(struct clk *); |
8 | int (*setrate)(struct clk *, unsigned long); | ||
8 | }; | 9 | }; |
9 | 10 | ||
10 | struct clk { | 11 | struct clk { |
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index bc55d07566ca..13cf518bbbf8 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c | |||
@@ -21,7 +21,8 @@ | |||
21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
22 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
23 | 23 | ||
24 | #include <mach/pxa2xx-regs.h> | 24 | #include <mach/pxa25x.h> |
25 | #include <mach/pxa27x.h> | ||
25 | #include <mach/audio.h> | 26 | #include <mach/audio.h> |
26 | #include <mach/pxafb.h> | 27 | #include <mach/pxafb.h> |
27 | #include <mach/smemc.h> | 28 | #include <mach/smemc.h> |
@@ -516,6 +517,8 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX") | |||
516 | .map_io = cmx2xx_map_io, | 517 | .map_io = cmx2xx_map_io, |
517 | .nr_irqs = CMX2XX_NR_IRQS, | 518 | .nr_irqs = CMX2XX_NR_IRQS, |
518 | .init_irq = cmx2xx_init_irq, | 519 | .init_irq = cmx2xx_init_irq, |
520 | /* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */ | ||
521 | .handle_irq = pxa25x_handle_irq, | ||
519 | .timer = &pxa_timer, | 522 | .timer = &pxa_timer, |
520 | .init_machine = cmx2xx_init, | 523 | .init_machine = cmx2xx_init, |
521 | #ifdef CONFIG_PCI | 524 | #ifdef CONFIG_PCI |
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index b199596f9c3d..b6a51340270b 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
@@ -855,6 +855,7 @@ MACHINE_START(CM_X300, "CM-X300 module") | |||
855 | .boot_params = 0xa0000100, | 855 | .boot_params = 0xa0000100, |
856 | .map_io = pxa3xx_map_io, | 856 | .map_io = pxa3xx_map_io, |
857 | .init_irq = pxa3xx_init_irq, | 857 | .init_irq = pxa3xx_init_irq, |
858 | .handle_irq = pxa3xx_handle_irq, | ||
858 | .timer = &pxa_timer, | 859 | .timer = &pxa_timer, |
859 | .init_machine = cm_x300_init, | 860 | .init_machine = cm_x300_init, |
860 | .fixup = cm_x300_fixup, | 861 | .fixup = cm_x300_fixup, |
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 7545a48ed88b..870920934ecf 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c | |||
@@ -310,6 +310,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270") | |||
310 | .init_machine = colibri_pxa270_init, | 310 | .init_machine = colibri_pxa270_init, |
311 | .map_io = pxa27x_map_io, | 311 | .map_io = pxa27x_map_io, |
312 | .init_irq = pxa27x_init_irq, | 312 | .init_irq = pxa27x_init_irq, |
313 | .handle_irq = pxa27x_handle_irq, | ||
313 | .timer = &pxa_timer, | 314 | .timer = &pxa_timer, |
314 | MACHINE_END | 315 | MACHINE_END |
315 | 316 | ||
@@ -318,6 +319,7 @@ MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") | |||
318 | .init_machine = colibri_pxa270_income_init, | 319 | .init_machine = colibri_pxa270_income_init, |
319 | .map_io = pxa27x_map_io, | 320 | .map_io = pxa27x_map_io, |
320 | .init_irq = pxa27x_init_irq, | 321 | .init_irq = pxa27x_init_irq, |
322 | .handle_irq = pxa27x_handle_irq, | ||
321 | .timer = &pxa_timer, | 323 | .timer = &pxa_timer, |
322 | MACHINE_END | 324 | MACHINE_END |
323 | 325 | ||
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index 66dd81cbc8a0..60a6781e7a8e 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c | |||
@@ -187,6 +187,7 @@ MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") | |||
187 | .init_machine = colibri_pxa300_init, | 187 | .init_machine = colibri_pxa300_init, |
188 | .map_io = pxa3xx_map_io, | 188 | .map_io = pxa3xx_map_io, |
189 | .init_irq = pxa3xx_init_irq, | 189 | .init_irq = pxa3xx_init_irq, |
190 | .handle_irq = pxa3xx_handle_irq, | ||
190 | .timer = &pxa_timer, | 191 | .timer = &pxa_timer, |
191 | MACHINE_END | 192 | MACHINE_END |
192 | 193 | ||
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index ff9ff5f4fc47..d2c6631915d4 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c | |||
@@ -23,8 +23,7 @@ | |||
23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
24 | #include <asm/mach/irq.h> | 24 | #include <asm/mach/irq.h> |
25 | 25 | ||
26 | #include <mach/pxa3xx-regs.h> | 26 | #include <mach/pxa320.h> |
27 | #include <mach/mfp-pxa320.h> | ||
28 | #include <mach/colibri.h> | 27 | #include <mach/colibri.h> |
29 | #include <mach/pxafb.h> | 28 | #include <mach/pxafb.h> |
30 | #include <mach/ohci.h> | 29 | #include <mach/ohci.h> |
@@ -258,6 +257,7 @@ MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") | |||
258 | .init_machine = colibri_pxa320_init, | 257 | .init_machine = colibri_pxa320_init, |
259 | .map_io = pxa3xx_map_io, | 258 | .map_io = pxa3xx_map_io, |
260 | .init_irq = pxa3xx_init_irq, | 259 | .init_irq = pxa3xx_init_irq, |
260 | .handle_irq = pxa3xx_handle_irq, | ||
261 | .timer = &pxa_timer, | 261 | .timer = &pxa_timer, |
262 | MACHINE_END | 262 | MACHINE_END |
263 | 263 | ||
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 3a5507e31919..185a37cad254 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
@@ -722,6 +722,7 @@ MACHINE_START(CORGI, "SHARP Corgi") | |||
722 | .fixup = fixup_corgi, | 722 | .fixup = fixup_corgi, |
723 | .map_io = pxa25x_map_io, | 723 | .map_io = pxa25x_map_io, |
724 | .init_irq = pxa25x_init_irq, | 724 | .init_irq = pxa25x_init_irq, |
725 | .handle_irq = pxa25x_handle_irq, | ||
725 | .init_machine = corgi_init, | 726 | .init_machine = corgi_init, |
726 | .timer = &pxa_timer, | 727 | .timer = &pxa_timer, |
727 | MACHINE_END | 728 | MACHINE_END |
@@ -732,6 +733,7 @@ MACHINE_START(SHEPHERD, "SHARP Shepherd") | |||
732 | .fixup = fixup_corgi, | 733 | .fixup = fixup_corgi, |
733 | .map_io = pxa25x_map_io, | 734 | .map_io = pxa25x_map_io, |
734 | .init_irq = pxa25x_init_irq, | 735 | .init_irq = pxa25x_init_irq, |
736 | .handle_irq = pxa25x_handle_irq, | ||
735 | .init_machine = corgi_init, | 737 | .init_machine = corgi_init, |
736 | .timer = &pxa_timer, | 738 | .timer = &pxa_timer, |
737 | MACHINE_END | 739 | MACHINE_END |
@@ -742,6 +744,7 @@ MACHINE_START(HUSKY, "SHARP Husky") | |||
742 | .fixup = fixup_corgi, | 744 | .fixup = fixup_corgi, |
743 | .map_io = pxa25x_map_io, | 745 | .map_io = pxa25x_map_io, |
744 | .init_irq = pxa25x_init_irq, | 746 | .init_irq = pxa25x_init_irq, |
747 | .handle_irq = pxa25x_handle_irq, | ||
745 | .init_machine = corgi_init, | 748 | .init_machine = corgi_init, |
746 | .timer = &pxa_timer, | 749 | .timer = &pxa_timer, |
747 | MACHINE_END | 750 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 0481c29a70e8..fe812eafb1f1 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c | |||
@@ -22,10 +22,9 @@ | |||
22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
24 | #include <mach/csb726.h> | 24 | #include <mach/csb726.h> |
25 | #include <mach/mfp-pxa27x.h> | 25 | #include <mach/pxa27x.h> |
26 | #include <mach/mmc.h> | 26 | #include <mach/mmc.h> |
27 | #include <mach/ohci.h> | 27 | #include <mach/ohci.h> |
28 | #include <mach/pxa2xx-regs.h> | ||
29 | #include <mach/audio.h> | 28 | #include <mach/audio.h> |
30 | #include <mach/smemc.h> | 29 | #include <mach/smemc.h> |
31 | 30 | ||
@@ -276,6 +275,7 @@ MACHINE_START(CSB726, "Cogent CSB726") | |||
276 | .boot_params = 0xa0000100, | 275 | .boot_params = 0xa0000100, |
277 | .map_io = pxa27x_map_io, | 276 | .map_io = pxa27x_map_io, |
278 | .init_irq = pxa27x_init_irq, | 277 | .init_irq = pxa27x_init_irq, |
278 | .handle_irq = pxa27x_handle_irq, | ||
279 | .init_machine = csb726_init, | 279 | .init_machine = csb726_init, |
280 | .timer = &pxa_timer, | 280 | .timer = &pxa_timer, |
281 | MACHINE_END | 281 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index f8a6e9d79a3a..2e37ea52b372 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
@@ -1302,6 +1302,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270") | |||
1302 | .boot_params = 0xa0000100, | 1302 | .boot_params = 0xa0000100, |
1303 | .map_io = pxa27x_map_io, | 1303 | .map_io = pxa27x_map_io, |
1304 | .init_irq = pxa27x_init_irq, | 1304 | .init_irq = pxa27x_init_irq, |
1305 | .handle_irq = pxa27x_handle_irq, | ||
1305 | .timer = &pxa_timer, | 1306 | .timer = &pxa_timer, |
1306 | .init_machine = em_x270_init, | 1307 | .init_machine = em_x270_init, |
1307 | MACHINE_END | 1308 | MACHINE_END |
@@ -1310,6 +1311,7 @@ MACHINE_START(EXEDA, "Compulab eXeda") | |||
1310 | .boot_params = 0xa0000100, | 1311 | .boot_params = 0xa0000100, |
1311 | .map_io = pxa27x_map_io, | 1312 | .map_io = pxa27x_map_io, |
1312 | .init_irq = pxa27x_init_irq, | 1313 | .init_irq = pxa27x_init_irq, |
1314 | .handle_irq = pxa27x_handle_irq, | ||
1313 | .timer = &pxa_timer, | 1315 | .timer = &pxa_timer, |
1314 | .init_machine = em_x270_init, | 1316 | .init_machine = em_x270_init, |
1315 | MACHINE_END | 1317 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index 2e3970fdde0b..b4599ec9d619 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c | |||
@@ -193,6 +193,7 @@ MACHINE_START(E330, "Toshiba e330") | |||
193 | .map_io = pxa25x_map_io, | 193 | .map_io = pxa25x_map_io, |
194 | .nr_irqs = ESERIES_NR_IRQS, | 194 | .nr_irqs = ESERIES_NR_IRQS, |
195 | .init_irq = pxa25x_init_irq, | 195 | .init_irq = pxa25x_init_irq, |
196 | .handle_irq = pxa25x_handle_irq, | ||
196 | .fixup = eseries_fixup, | 197 | .fixup = eseries_fixup, |
197 | .init_machine = e330_init, | 198 | .init_machine = e330_init, |
198 | .timer = &pxa_timer, | 199 | .timer = &pxa_timer, |
@@ -242,6 +243,7 @@ MACHINE_START(E350, "Toshiba e350") | |||
242 | .map_io = pxa25x_map_io, | 243 | .map_io = pxa25x_map_io, |
243 | .nr_irqs = ESERIES_NR_IRQS, | 244 | .nr_irqs = ESERIES_NR_IRQS, |
244 | .init_irq = pxa25x_init_irq, | 245 | .init_irq = pxa25x_init_irq, |
246 | .handle_irq = pxa25x_handle_irq, | ||
245 | .fixup = eseries_fixup, | 247 | .fixup = eseries_fixup, |
246 | .init_machine = e350_init, | 248 | .init_machine = e350_init, |
247 | .timer = &pxa_timer, | 249 | .timer = &pxa_timer, |
@@ -364,6 +366,7 @@ MACHINE_START(E400, "Toshiba e400") | |||
364 | .map_io = pxa25x_map_io, | 366 | .map_io = pxa25x_map_io, |
365 | .nr_irqs = ESERIES_NR_IRQS, | 367 | .nr_irqs = ESERIES_NR_IRQS, |
366 | .init_irq = pxa25x_init_irq, | 368 | .init_irq = pxa25x_init_irq, |
369 | .handle_irq = pxa25x_handle_irq, | ||
367 | .fixup = eseries_fixup, | 370 | .fixup = eseries_fixup, |
368 | .init_machine = e400_init, | 371 | .init_machine = e400_init, |
369 | .timer = &pxa_timer, | 372 | .timer = &pxa_timer, |
@@ -552,6 +555,7 @@ MACHINE_START(E740, "Toshiba e740") | |||
552 | .map_io = pxa25x_map_io, | 555 | .map_io = pxa25x_map_io, |
553 | .nr_irqs = ESERIES_NR_IRQS, | 556 | .nr_irqs = ESERIES_NR_IRQS, |
554 | .init_irq = pxa25x_init_irq, | 557 | .init_irq = pxa25x_init_irq, |
558 | .handle_irq = pxa25x_handle_irq, | ||
555 | .fixup = eseries_fixup, | 559 | .fixup = eseries_fixup, |
556 | .init_machine = e740_init, | 560 | .init_machine = e740_init, |
557 | .timer = &pxa_timer, | 561 | .timer = &pxa_timer, |
@@ -743,6 +747,7 @@ MACHINE_START(E750, "Toshiba e750") | |||
743 | .map_io = pxa25x_map_io, | 747 | .map_io = pxa25x_map_io, |
744 | .nr_irqs = ESERIES_NR_IRQS, | 748 | .nr_irqs = ESERIES_NR_IRQS, |
745 | .init_irq = pxa25x_init_irq, | 749 | .init_irq = pxa25x_init_irq, |
750 | .handle_irq = pxa25x_handle_irq, | ||
746 | .fixup = eseries_fixup, | 751 | .fixup = eseries_fixup, |
747 | .init_machine = e750_init, | 752 | .init_machine = e750_init, |
748 | .timer = &pxa_timer, | 753 | .timer = &pxa_timer, |
@@ -947,6 +952,7 @@ MACHINE_START(E800, "Toshiba e800") | |||
947 | .map_io = pxa25x_map_io, | 952 | .map_io = pxa25x_map_io, |
948 | .nr_irqs = ESERIES_NR_IRQS, | 953 | .nr_irqs = ESERIES_NR_IRQS, |
949 | .init_irq = pxa25x_init_irq, | 954 | .init_irq = pxa25x_init_irq, |
955 | .handle_irq = pxa25x_handle_irq, | ||
950 | .fixup = eseries_fixup, | 956 | .fixup = eseries_fixup, |
951 | .init_machine = e800_init, | 957 | .init_machine = e800_init, |
952 | .timer = &pxa_timer, | 958 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index d88aed8fbe15..b73eadb9f5dc 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c | |||
@@ -801,6 +801,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780") | |||
801 | .map_io = pxa27x_map_io, | 801 | .map_io = pxa27x_map_io, |
802 | .nr_irqs = EZX_NR_IRQS, | 802 | .nr_irqs = EZX_NR_IRQS, |
803 | .init_irq = pxa27x_init_irq, | 803 | .init_irq = pxa27x_init_irq, |
804 | .handle_irq = pxa27x_handle_irq, | ||
804 | .timer = &pxa_timer, | 805 | .timer = &pxa_timer, |
805 | .init_machine = a780_init, | 806 | .init_machine = a780_init, |
806 | MACHINE_END | 807 | MACHINE_END |
@@ -866,6 +867,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680") | |||
866 | .map_io = pxa27x_map_io, | 867 | .map_io = pxa27x_map_io, |
867 | .nr_irqs = EZX_NR_IRQS, | 868 | .nr_irqs = EZX_NR_IRQS, |
868 | .init_irq = pxa27x_init_irq, | 869 | .init_irq = pxa27x_init_irq, |
870 | .handle_irq = pxa27x_handle_irq, | ||
869 | .timer = &pxa_timer, | 871 | .timer = &pxa_timer, |
870 | .init_machine = e680_init, | 872 | .init_machine = e680_init, |
871 | MACHINE_END | 873 | MACHINE_END |
@@ -931,6 +933,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200") | |||
931 | .map_io = pxa27x_map_io, | 933 | .map_io = pxa27x_map_io, |
932 | .nr_irqs = EZX_NR_IRQS, | 934 | .nr_irqs = EZX_NR_IRQS, |
933 | .init_irq = pxa27x_init_irq, | 935 | .init_irq = pxa27x_init_irq, |
936 | .handle_irq = pxa27x_handle_irq, | ||
934 | .timer = &pxa_timer, | 937 | .timer = &pxa_timer, |
935 | .init_machine = a1200_init, | 938 | .init_machine = a1200_init, |
936 | MACHINE_END | 939 | MACHINE_END |
@@ -1121,6 +1124,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910") | |||
1121 | .map_io = pxa27x_map_io, | 1124 | .map_io = pxa27x_map_io, |
1122 | .nr_irqs = EZX_NR_IRQS, | 1125 | .nr_irqs = EZX_NR_IRQS, |
1123 | .init_irq = pxa27x_init_irq, | 1126 | .init_irq = pxa27x_init_irq, |
1127 | .handle_irq = pxa27x_handle_irq, | ||
1124 | .timer = &pxa_timer, | 1128 | .timer = &pxa_timer, |
1125 | .init_machine = a910_init, | 1129 | .init_machine = a910_init, |
1126 | MACHINE_END | 1130 | MACHINE_END |
@@ -1186,6 +1190,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6") | |||
1186 | .map_io = pxa27x_map_io, | 1190 | .map_io = pxa27x_map_io, |
1187 | .nr_irqs = EZX_NR_IRQS, | 1191 | .nr_irqs = EZX_NR_IRQS, |
1188 | .init_irq = pxa27x_init_irq, | 1192 | .init_irq = pxa27x_init_irq, |
1193 | .handle_irq = pxa27x_handle_irq, | ||
1189 | .timer = &pxa_timer, | 1194 | .timer = &pxa_timer, |
1190 | .init_machine = e6_init, | 1195 | .init_machine = e6_init, |
1191 | MACHINE_END | 1196 | MACHINE_END |
@@ -1225,6 +1230,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2") | |||
1225 | .map_io = pxa27x_map_io, | 1230 | .map_io = pxa27x_map_io, |
1226 | .nr_irqs = EZX_NR_IRQS, | 1231 | .nr_irqs = EZX_NR_IRQS, |
1227 | .init_irq = pxa27x_init_irq, | 1232 | .init_irq = pxa27x_init_irq, |
1233 | .handle_irq = pxa27x_handle_irq, | ||
1228 | .timer = &pxa_timer, | 1234 | .timer = &pxa_timer, |
1229 | .init_machine = e2_init, | 1235 | .init_machine = e2_init, |
1230 | MACHINE_END | 1236 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index e6c9344a95ae..92a2e85ab02c 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
@@ -13,21 +13,8 @@ struct irq_data; | |||
13 | struct sys_timer; | 13 | struct sys_timer; |
14 | 14 | ||
15 | extern struct sys_timer pxa_timer; | 15 | extern struct sys_timer pxa_timer; |
16 | extern void __init pxa_init_irq(int irq_nr, | ||
17 | int (*set_wake)(struct irq_data *, | ||
18 | unsigned int)); | ||
19 | extern void __init pxa25x_init_irq(void); | ||
20 | #ifdef CONFIG_CPU_PXA26x | ||
21 | extern void __init pxa26x_init_irq(void); | ||
22 | #endif | ||
23 | extern void __init pxa27x_init_irq(void); | ||
24 | extern void __init pxa3xx_init_irq(void); | ||
25 | extern void __init pxa95x_init_irq(void); | ||
26 | 16 | ||
27 | extern void __init pxa_map_io(void); | 17 | extern void __init pxa_map_io(void); |
28 | extern void __init pxa25x_map_io(void); | ||
29 | extern void __init pxa27x_map_io(void); | ||
30 | extern void __init pxa3xx_map_io(void); | ||
31 | 18 | ||
32 | extern unsigned int get_clk_frequency_khz(int info); | 19 | extern unsigned int get_clk_frequency_khz(int info); |
33 | 20 | ||
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index d65e4bde9b91..deaa111c91f9 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c | |||
@@ -236,6 +236,7 @@ MACHINE_START(GUMSTIX, "Gumstix") | |||
236 | .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ | 236 | .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ |
237 | .map_io = pxa25x_map_io, | 237 | .map_io = pxa25x_map_io, |
238 | .init_irq = pxa25x_init_irq, | 238 | .init_irq = pxa25x_init_irq, |
239 | .handle_irq = pxa25x_handle_irq, | ||
239 | .timer = &pxa_timer, | 240 | .timer = &pxa_timer, |
240 | .init_machine = gumstix_init, | 241 | .init_machine = gumstix_init, |
241 | MACHINE_END | 242 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index 657db469de1f..0a235128914d 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
29 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
30 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
31 | #include <asm/irq.h> | ||
31 | 32 | ||
32 | #include <mach/pxa25x.h> | 33 | #include <mach/pxa25x.h> |
33 | #include <mach/h5000.h> | 34 | #include <mach/h5000.h> |
@@ -205,6 +206,7 @@ MACHINE_START(H5400, "HP iPAQ H5000") | |||
205 | .boot_params = 0xa0000100, | 206 | .boot_params = 0xa0000100, |
206 | .map_io = pxa25x_map_io, | 207 | .map_io = pxa25x_map_io, |
207 | .init_irq = pxa25x_init_irq, | 208 | .init_irq = pxa25x_init_irq, |
209 | .handle_irq = pxa25x_handle_irq, | ||
208 | .timer = &pxa_timer, | 210 | .timer = &pxa_timer, |
209 | .init_machine = h5000_init, | 211 | .init_machine = h5000_init, |
210 | MACHINE_END | 212 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c index e8603eba54bd..a997d0ab2872 100644 --- a/arch/arm/mach-pxa/himalaya.c +++ b/arch/arm/mach-pxa/himalaya.c | |||
@@ -24,8 +24,7 @@ | |||
24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | 26 | ||
27 | #include <mach/mfp-pxa25x.h> | 27 | #include <mach/pxa25x.h> |
28 | #include <mach/hardware.h> | ||
29 | 28 | ||
30 | #include "generic.h" | 29 | #include "generic.h" |
31 | 30 | ||
@@ -162,6 +161,7 @@ MACHINE_START(HIMALAYA, "HTC Himalaya") | |||
162 | .boot_params = 0xa0000100, | 161 | .boot_params = 0xa0000100, |
163 | .map_io = pxa25x_map_io, | 162 | .map_io = pxa25x_map_io, |
164 | .init_irq = pxa25x_init_irq, | 163 | .init_irq = pxa25x_init_irq, |
164 | .handle_irq = pxa25x_handle_irq, | ||
165 | .init_machine = himalaya_init, | 165 | .init_machine = himalaya_init, |
166 | .timer = &pxa_timer, | 166 | .timer = &pxa_timer, |
167 | MACHINE_END | 167 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 99960a1814e0..c748a473a2ff 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c | |||
@@ -842,6 +842,7 @@ MACHINE_START(H4700, "HP iPAQ HX4700") | |||
842 | .map_io = pxa27x_map_io, | 842 | .map_io = pxa27x_map_io, |
843 | .nr_irqs = HX4700_NR_IRQS, | 843 | .nr_irqs = HX4700_NR_IRQS, |
844 | .init_irq = pxa27x_init_irq, | 844 | .init_irq = pxa27x_init_irq, |
845 | .handle_irq = pxa27x_handle_irq, | ||
845 | .init_machine = hx4700_init, | 846 | .init_machine = hx4700_init, |
846 | .timer = &pxa_timer, | 847 | .timer = &pxa_timer, |
847 | MACHINE_END | 848 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index 6cedc81da3bc..d427429f1f34 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c | |||
@@ -194,6 +194,7 @@ MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") | |||
194 | .boot_params = 0xa0000100, | 194 | .boot_params = 0xa0000100, |
195 | .map_io = pxa3xx_map_io, | 195 | .map_io = pxa3xx_map_io, |
196 | .init_irq = pxa3xx_init_irq, | 196 | .init_irq = pxa3xx_init_irq, |
197 | .handle_irq = pxa3xx_handle_irq, | ||
197 | .timer = &pxa_timer, | 198 | .timer = &pxa_timer, |
198 | .init_machine = icontrol_init | 199 | .init_machine = icontrol_init |
199 | MACHINE_END | 200 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index f7fb64f11a7d..ddf20e5c376e 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c | |||
@@ -196,6 +196,7 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP") | |||
196 | /* Maintainer: Vibren Technologies */ | 196 | /* Maintainer: Vibren Technologies */ |
197 | .map_io = idp_map_io, | 197 | .map_io = idp_map_io, |
198 | .init_irq = pxa25x_init_irq, | 198 | .init_irq = pxa25x_init_irq, |
199 | .handle_irq = pxa25x_handle_irq, | ||
199 | .timer = &pxa_timer, | 200 | .timer = &pxa_timer, |
200 | .init_machine = idp_init, | 201 | .init_machine = idp_init, |
201 | MACHINE_END | 202 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 038402404e39..7cc5a781e99e 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h | |||
@@ -104,4 +104,16 @@ | |||
104 | 104 | ||
105 | #define NR_IRQS (IRQ_BOARD_START) | 105 | #define NR_IRQS (IRQ_BOARD_START) |
106 | 106 | ||
107 | #ifndef __ASSEMBLY__ | ||
108 | struct irq_data; | ||
109 | struct pt_regs; | ||
110 | |||
111 | void pxa_mask_irq(struct irq_data *); | ||
112 | void pxa_unmask_irq(struct irq_data *); | ||
113 | void icip_handle_irq(struct pt_regs *); | ||
114 | void ichp_handle_irq(struct pt_regs *); | ||
115 | |||
116 | void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int)); | ||
117 | #endif | ||
118 | |||
107 | #endif /* __ASM_MACH_IRQS_H */ | 119 | #endif /* __ASM_MACH_IRQS_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h index 508c3ba1f4d0..3ac0baac7350 100644 --- a/arch/arm/mach-pxa/include/mach/pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/pxa25x.h | |||
@@ -4,5 +4,14 @@ | |||
4 | #include <mach/hardware.h> | 4 | #include <mach/hardware.h> |
5 | #include <mach/pxa2xx-regs.h> | 5 | #include <mach/pxa2xx-regs.h> |
6 | #include <mach/mfp-pxa25x.h> | 6 | #include <mach/mfp-pxa25x.h> |
7 | #include <mach/irqs.h> | ||
8 | |||
9 | extern void __init pxa25x_map_io(void); | ||
10 | extern void __init pxa25x_init_irq(void); | ||
11 | #ifdef CONFIG_CPU_PXA26x | ||
12 | extern void __init pxa26x_init_irq(void); | ||
13 | #endif | ||
14 | |||
15 | #define pxa25x_handle_irq icip_handle_irq | ||
7 | 16 | ||
8 | #endif /* __MACH_PXA25x_H */ | 17 | #endif /* __MACH_PXA25x_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h index 0b702693f458..b9b1bdc4bacc 100644 --- a/arch/arm/mach-pxa/include/mach/pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/pxa27x.h | |||
@@ -4,6 +4,7 @@ | |||
4 | #include <mach/hardware.h> | 4 | #include <mach/hardware.h> |
5 | #include <mach/pxa2xx-regs.h> | 5 | #include <mach/pxa2xx-regs.h> |
6 | #include <mach/mfp-pxa27x.h> | 6 | #include <mach/mfp-pxa27x.h> |
7 | #include <mach/irqs.h> | ||
7 | 8 | ||
8 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ | 9 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ |
9 | 10 | ||
@@ -17,6 +18,10 @@ | |||
17 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ | 18 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ |
18 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ | 19 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ |
19 | 20 | ||
21 | extern void __init pxa27x_map_io(void); | ||
22 | extern void __init pxa27x_init_irq(void); | ||
20 | extern int __init pxa27x_set_pwrmode(unsigned int mode); | 23 | extern int __init pxa27x_set_pwrmode(unsigned int mode); |
21 | 24 | ||
25 | #define pxa27x_handle_irq ichp_handle_irq | ||
26 | |||
22 | #endif /* __MACH_PXA27x_H */ | 27 | #endif /* __MACH_PXA27x_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h index 2f33076c9e48..733b6412c3df 100644 --- a/arch/arm/mach-pxa/include/mach/pxa300.h +++ b/arch/arm/mach-pxa/include/mach/pxa300.h | |||
@@ -1,8 +1,7 @@ | |||
1 | #ifndef __MACH_PXA300_H | 1 | #ifndef __MACH_PXA300_H |
2 | #define __MACH_PXA300_H | 2 | #define __MACH_PXA300_H |
3 | 3 | ||
4 | #include <mach/hardware.h> | 4 | #include <mach/pxa3xx.h> |
5 | #include <mach/pxa3xx-regs.h> | ||
6 | #include <mach/mfp-pxa300.h> | 5 | #include <mach/mfp-pxa300.h> |
7 | 6 | ||
8 | #endif /* __MACH_PXA300_H */ | 7 | #endif /* __MACH_PXA300_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h index cab78e903273..b6204e470d89 100644 --- a/arch/arm/mach-pxa/include/mach/pxa320.h +++ b/arch/arm/mach-pxa/include/mach/pxa320.h | |||
@@ -1,8 +1,7 @@ | |||
1 | #ifndef __MACH_PXA320_H | 1 | #ifndef __MACH_PXA320_H |
2 | #define __MACH_PXA320_H | 2 | #define __MACH_PXA320_H |
3 | 3 | ||
4 | #include <mach/hardware.h> | 4 | #include <mach/pxa3xx.h> |
5 | #include <mach/pxa3xx-regs.h> | ||
6 | #include <mach/mfp-pxa320.h> | 5 | #include <mach/mfp-pxa320.h> |
7 | 6 | ||
8 | #endif /* __MACH_PXA320_H */ | 7 | #endif /* __MACH_PXA320_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h new file mode 100644 index 000000000000..cd3e57f42688 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa3xx.h | |||
@@ -0,0 +1,14 @@ | |||
1 | #ifndef __MACH_PXA3XX_H | ||
2 | #define __MACH_PXA3XX_H | ||
3 | |||
4 | #include <mach/hardware.h> | ||
5 | #include <mach/pxa3xx-regs.h> | ||
6 | #include <mach/irqs.h> | ||
7 | |||
8 | extern void __init pxa3xx_map_io(void); | ||
9 | extern void __init pxa3xx_init_irq(void); | ||
10 | extern void __init pxa95x_init_irq(void); | ||
11 | |||
12 | #define pxa3xx_handle_irq ichp_handle_irq | ||
13 | |||
14 | #endif /* __MACH_PXA3XX_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h index d45f76a9b54d..190363b98d01 100644 --- a/arch/arm/mach-pxa/include/mach/pxa930.h +++ b/arch/arm/mach-pxa/include/mach/pxa930.h | |||
@@ -1,8 +1,7 @@ | |||
1 | #ifndef __MACH_PXA930_H | 1 | #ifndef __MACH_PXA930_H |
2 | #define __MACH_PXA930_H | 2 | #define __MACH_PXA930_H |
3 | 3 | ||
4 | #include <mach/hardware.h> | 4 | #include <mach/pxa3xx.h> |
5 | #include <mach/pxa3xx-regs.h> | ||
6 | #include <mach/mfp-pxa930.h> | 5 | #include <mach/mfp-pxa930.h> |
7 | 6 | ||
8 | #endif /* __MACH_PXA930_H */ | 7 | #endif /* __MACH_PXA930_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h deleted file mode 100644 index 662288eb6f95..000000000000 --- a/arch/arm/mach-pxa/include/mach/regs-intc.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | #ifndef __ASM_MACH_REGS_INTC_H | ||
2 | #define __ASM_MACH_REGS_INTC_H | ||
3 | |||
4 | #include <mach/hardware.h> | ||
5 | |||
6 | /* | ||
7 | * Interrupt Controller | ||
8 | */ | ||
9 | |||
10 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | ||
11 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | ||
12 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | ||
13 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | ||
14 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | ||
15 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | ||
16 | #define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ | ||
17 | |||
18 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
19 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
20 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
21 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
22 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
23 | |||
24 | #define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */ | ||
25 | #define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */ | ||
26 | #define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */ | ||
27 | #define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ | ||
28 | #define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ | ||
29 | |||
30 | #endif /* __ASM_MACH_REGS_INTC_H */ | ||
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 32ed551bf9c5..b09e848eb6c6 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -37,6 +37,8 @@ | |||
37 | #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ | 37 | #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ |
38 | ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ | 38 | ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ |
39 | (0x144 + (((i) - 64) << 2))) | 39 | (0x144 + (((i) - 64) << 2))) |
40 | #define ICHP_VAL_IRQ (1 << 31) | ||
41 | #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) | ||
40 | #define IPR_VALID (1 << 31) | 42 | #define IPR_VALID (1 << 31) |
41 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) | 43 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) |
42 | 44 | ||
@@ -64,7 +66,7 @@ static inline void __iomem *irq_base(int i) | |||
64 | return (void __iomem *)io_p2v(phys_base[i]); | 66 | return (void __iomem *)io_p2v(phys_base[i]); |
65 | } | 67 | } |
66 | 68 | ||
67 | static void pxa_mask_irq(struct irq_data *d) | 69 | void pxa_mask_irq(struct irq_data *d) |
68 | { | 70 | { |
69 | void __iomem *base = irq_data_get_irq_chip_data(d); | 71 | void __iomem *base = irq_data_get_irq_chip_data(d); |
70 | uint32_t icmr = __raw_readl(base + ICMR); | 72 | uint32_t icmr = __raw_readl(base + ICMR); |
@@ -73,7 +75,7 @@ static void pxa_mask_irq(struct irq_data *d) | |||
73 | __raw_writel(icmr, base + ICMR); | 75 | __raw_writel(icmr, base + ICMR); |
74 | } | 76 | } |
75 | 77 | ||
76 | static void pxa_unmask_irq(struct irq_data *d) | 78 | void pxa_unmask_irq(struct irq_data *d) |
77 | { | 79 | { |
78 | void __iomem *base = irq_data_get_irq_chip_data(d); | 80 | void __iomem *base = irq_data_get_irq_chip_data(d); |
79 | uint32_t icmr = __raw_readl(base + ICMR); | 81 | uint32_t icmr = __raw_readl(base + ICMR); |
@@ -127,6 +129,36 @@ static struct irq_chip pxa_low_gpio_chip = { | |||
127 | .irq_set_type = pxa_set_low_gpio_type, | 129 | .irq_set_type = pxa_set_low_gpio_type, |
128 | }; | 130 | }; |
129 | 131 | ||
132 | asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) | ||
133 | { | ||
134 | uint32_t icip, icmr, mask; | ||
135 | |||
136 | do { | ||
137 | icip = __raw_readl(IRQ_BASE + ICIP); | ||
138 | icmr = __raw_readl(IRQ_BASE + ICMR); | ||
139 | mask = icip & icmr; | ||
140 | |||
141 | if (mask == 0) | ||
142 | break; | ||
143 | |||
144 | handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); | ||
145 | } while (1); | ||
146 | } | ||
147 | |||
148 | asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) | ||
149 | { | ||
150 | uint32_t ichp; | ||
151 | |||
152 | do { | ||
153 | __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); | ||
154 | |||
155 | if ((ichp & ICHP_VAL_IRQ) == 0) | ||
156 | break; | ||
157 | |||
158 | handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs); | ||
159 | } while (1); | ||
160 | } | ||
161 | |||
130 | static void __init pxa_init_low_gpio_irq(set_wake_t fn) | 162 | static void __init pxa_init_low_gpio_irq(set_wake_t fn) |
131 | { | 163 | { |
132 | int irq; | 164 | int irq; |
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index e5e326d2cdc9..8f97e15e86e5 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
@@ -441,6 +441,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto | |||
441 | .map_io = pxa3xx_map_io, | 441 | .map_io = pxa3xx_map_io, |
442 | .nr_irqs = LITTLETON_NR_IRQS, | 442 | .nr_irqs = LITTLETON_NR_IRQS, |
443 | .init_irq = pxa3xx_init_irq, | 443 | .init_irq = pxa3xx_init_irq, |
444 | .handle_irq = pxa3xx_handle_irq, | ||
444 | .timer = &pxa_timer, | 445 | .timer = &pxa_timer, |
445 | .init_machine = littleton_init, | 446 | .init_machine = littleton_init, |
446 | MACHINE_END | 447 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 6cf8180bf5bd..c171d6ebee49 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
@@ -503,6 +503,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") | |||
503 | .map_io = lpd270_map_io, | 503 | .map_io = lpd270_map_io, |
504 | .nr_irqs = LPD270_NR_IRQS, | 504 | .nr_irqs = LPD270_NR_IRQS, |
505 | .init_irq = lpd270_init_irq, | 505 | .init_irq = lpd270_init_irq, |
506 | .handle_irq = pxa27x_handle_irq, | ||
506 | .timer = &pxa_timer, | 507 | .timer = &pxa_timer, |
507 | .init_machine = lpd270_init, | 508 | .init_machine = lpd270_init, |
508 | MACHINE_END | 509 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index e10ddb827147..a8c696bfc132 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
@@ -553,6 +553,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)") | |||
553 | .map_io = lubbock_map_io, | 553 | .map_io = lubbock_map_io, |
554 | .nr_irqs = LUBBOCK_NR_IRQS, | 554 | .nr_irqs = LUBBOCK_NR_IRQS, |
555 | .init_irq = lubbock_init_irq, | 555 | .init_irq = lubbock_init_irq, |
556 | .handle_irq = pxa25x_handle_irq, | ||
556 | .timer = &pxa_timer, | 557 | .timer = &pxa_timer, |
557 | .init_machine = lubbock_init, | 558 | .init_machine = lubbock_init, |
558 | MACHINE_END | 559 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 0e42798942f7..5fe5bcd7c0a1 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
@@ -757,6 +757,7 @@ MACHINE_START(MAGICIAN, "HTC Magician") | |||
757 | .map_io = pxa27x_map_io, | 757 | .map_io = pxa27x_map_io, |
758 | .nr_irqs = MAGICIAN_NR_IRQS, | 758 | .nr_irqs = MAGICIAN_NR_IRQS, |
759 | .init_irq = pxa27x_init_irq, | 759 | .init_irq = pxa27x_init_irq, |
760 | .handle_irq = pxa27x_handle_irq, | ||
760 | .init_machine = magician_init, | 761 | .init_machine = magician_init, |
761 | .timer = &pxa_timer, | 762 | .timer = &pxa_timer, |
762 | MACHINE_END | 763 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 3479e2b3b511..4622eb78ef25 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
@@ -620,6 +620,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") | |||
620 | .map_io = mainstone_map_io, | 620 | .map_io = mainstone_map_io, |
621 | .nr_irqs = MAINSTONE_NR_IRQS, | 621 | .nr_irqs = MAINSTONE_NR_IRQS, |
622 | .init_irq = mainstone_init_irq, | 622 | .init_irq = mainstone_init_irq, |
623 | .handle_irq = pxa27x_handle_irq, | ||
623 | .timer = &pxa_timer, | 624 | .timer = &pxa_timer, |
624 | .init_machine = mainstone_init, | 625 | .init_machine = mainstone_init, |
625 | MACHINE_END | 626 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index aa67637ae41d..64810f908e5b 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c | |||
@@ -754,6 +754,7 @@ MACHINE_START(MIOA701, "MIO A701") | |||
754 | .boot_params = 0xa0000100, | 754 | .boot_params = 0xa0000100, |
755 | .map_io = &pxa27x_map_io, | 755 | .map_io = &pxa27x_map_io, |
756 | .init_irq = &pxa27x_init_irq, | 756 | .init_irq = &pxa27x_init_irq, |
757 | .handle_irq = &pxa27x_handle_irq, | ||
757 | .init_machine = mioa701_machine_init, | 758 | .init_machine = mioa701_machine_init, |
758 | .timer = &pxa_timer, | 759 | .timer = &pxa_timer, |
759 | MACHINE_END | 760 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index 59cce78aebd1..fb408861dbcf 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c | |||
@@ -96,6 +96,7 @@ MACHINE_START(NEC_MP900, "MobilePro900/C") | |||
96 | .timer = &pxa_timer, | 96 | .timer = &pxa_timer, |
97 | .map_io = pxa25x_map_io, | 97 | .map_io = pxa25x_map_io, |
98 | .init_irq = pxa25x_init_irq, | 98 | .init_irq = pxa25x_init_irq, |
99 | .handle_irq = pxa25x_handle_irq, | ||
99 | .init_machine = mp900c_init, | 100 | .init_machine = mp900c_init, |
100 | MACHINE_END | 101 | MACHINE_END |
101 | 102 | ||
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 4061ecddee70..6b77365ed938 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c | |||
@@ -345,6 +345,7 @@ MACHINE_START(PALMLD, "Palm LifeDrive") | |||
345 | .boot_params = 0xa0000100, | 345 | .boot_params = 0xa0000100, |
346 | .map_io = palmld_map_io, | 346 | .map_io = palmld_map_io, |
347 | .init_irq = pxa27x_init_irq, | 347 | .init_irq = pxa27x_init_irq, |
348 | .handle_irq = pxa27x_handle_irq, | ||
348 | .timer = &pxa_timer, | 349 | .timer = &pxa_timer, |
349 | .init_machine = palmld_init | 350 | .init_machine = palmld_init |
350 | MACHINE_END | 351 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index df4d7d009fbb..9bd3e47486fb 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c | |||
@@ -206,6 +206,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5") | |||
206 | .map_io = pxa27x_map_io, | 206 | .map_io = pxa27x_map_io, |
207 | .reserve = palmt5_reserve, | 207 | .reserve = palmt5_reserve, |
208 | .init_irq = pxa27x_init_irq, | 208 | .init_irq = pxa27x_init_irq, |
209 | .handle_irq = pxa27x_handle_irq, | ||
209 | .timer = &pxa_timer, | 210 | .timer = &pxa_timer, |
210 | .init_machine = palmt5_init | 211 | .init_machine = palmt5_init |
211 | MACHINE_END | 212 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index fb06bd047272..6ad4a6c7bc96 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c | |||
@@ -31,14 +31,13 @@ | |||
31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
32 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
33 | 33 | ||
34 | #include <mach/pxa25x.h> | ||
34 | #include <mach/audio.h> | 35 | #include <mach/audio.h> |
35 | #include <mach/palmtc.h> | 36 | #include <mach/palmtc.h> |
36 | #include <mach/mmc.h> | 37 | #include <mach/mmc.h> |
37 | #include <mach/pxafb.h> | 38 | #include <mach/pxafb.h> |
38 | #include <mach/mfp-pxa25x.h> | ||
39 | #include <mach/irda.h> | 39 | #include <mach/irda.h> |
40 | #include <mach/udc.h> | 40 | #include <mach/udc.h> |
41 | #include <mach/pxa2xx-regs.h> | ||
42 | 41 | ||
43 | #include "generic.h" | 42 | #include "generic.h" |
44 | #include "devices.h" | 43 | #include "devices.h" |
@@ -541,6 +540,7 @@ MACHINE_START(PALMTC, "Palm Tungsten|C") | |||
541 | .boot_params = 0xa0000100, | 540 | .boot_params = 0xa0000100, |
542 | .map_io = pxa25x_map_io, | 541 | .map_io = pxa25x_map_io, |
543 | .init_irq = pxa25x_init_irq, | 542 | .init_irq = pxa25x_init_irq, |
543 | .handle_irq = pxa25x_handle_irq, | ||
544 | .timer = &pxa_timer, | 544 | .timer = &pxa_timer, |
545 | .init_machine = palmtc_init | 545 | .init_machine = palmtc_init |
546 | MACHINE_END | 546 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 726f5b98dcd3..664232f3e62c 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c | |||
@@ -31,11 +31,11 @@ | |||
31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
32 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
33 | 33 | ||
34 | #include <mach/pxa25x.h> | ||
34 | #include <mach/audio.h> | 35 | #include <mach/audio.h> |
35 | #include <mach/palmte2.h> | 36 | #include <mach/palmte2.h> |
36 | #include <mach/mmc.h> | 37 | #include <mach/mmc.h> |
37 | #include <mach/pxafb.h> | 38 | #include <mach/pxafb.h> |
38 | #include <mach/mfp-pxa25x.h> | ||
39 | #include <mach/irda.h> | 39 | #include <mach/irda.h> |
40 | #include <mach/udc.h> | 40 | #include <mach/udc.h> |
41 | #include <mach/palmasoc.h> | 41 | #include <mach/palmasoc.h> |
@@ -359,6 +359,7 @@ MACHINE_START(PALMTE2, "Palm Tungsten|E2") | |||
359 | .boot_params = 0xa0000100, | 359 | .boot_params = 0xa0000100, |
360 | .map_io = pxa25x_map_io, | 360 | .map_io = pxa25x_map_io, |
361 | .init_irq = pxa25x_init_irq, | 361 | .init_irq = pxa25x_init_irq, |
362 | .handle_irq = pxa25x_handle_irq, | ||
362 | .timer = &pxa_timer, | 363 | .timer = &pxa_timer, |
363 | .init_machine = palmte2_init | 364 | .init_machine = palmte2_init |
364 | MACHINE_END | 365 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 20d1b18b1733..bb27d4b688d8 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c | |||
@@ -444,6 +444,7 @@ MACHINE_START(TREO680, "Palm Treo 680") | |||
444 | .map_io = pxa27x_map_io, | 444 | .map_io = pxa27x_map_io, |
445 | .reserve = treo_reserve, | 445 | .reserve = treo_reserve, |
446 | .init_irq = pxa27x_init_irq, | 446 | .init_irq = pxa27x_init_irq, |
447 | .handle_irq = pxa27x_handle_irq, | ||
447 | .timer = &pxa_timer, | 448 | .timer = &pxa_timer, |
448 | .init_machine = treo680_init, | 449 | .init_machine = treo680_init, |
449 | MACHINE_END | 450 | MACHINE_END |
@@ -453,6 +454,7 @@ MACHINE_START(CENTRO, "Palm Centro 685") | |||
453 | .map_io = pxa27x_map_io, | 454 | .map_io = pxa27x_map_io, |
454 | .reserve = treo_reserve, | 455 | .reserve = treo_reserve, |
455 | .init_irq = pxa27x_init_irq, | 456 | .init_irq = pxa27x_init_irq, |
457 | .handle_irq = pxa27x_handle_irq, | ||
456 | .timer = &pxa_timer, | 458 | .timer = &pxa_timer, |
457 | .init_machine = centro_init, | 459 | .init_machine = centro_init, |
458 | MACHINE_END | 460 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 595f002066cc..fc4285589c1f 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c | |||
@@ -367,6 +367,7 @@ MACHINE_START(PALMTX, "Palm T|X") | |||
367 | .boot_params = 0xa0000100, | 367 | .boot_params = 0xa0000100, |
368 | .map_io = palmtx_map_io, | 368 | .map_io = palmtx_map_io, |
369 | .init_irq = pxa27x_init_irq, | 369 | .init_irq = pxa27x_init_irq, |
370 | .handle_irq = pxa27x_handle_irq, | ||
370 | .timer = &pxa_timer, | 371 | .timer = &pxa_timer, |
371 | .init_machine = palmtx_init | 372 | .init_machine = palmtx_init |
372 | MACHINE_END | 373 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 5a5329bc33f1..e61c1cc05519 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c | |||
@@ -402,6 +402,7 @@ MACHINE_START(PALMZ72, "Palm Zire72") | |||
402 | .boot_params = 0xa0000100, | 402 | .boot_params = 0xa0000100, |
403 | .map_io = pxa27x_map_io, | 403 | .map_io = pxa27x_map_io, |
404 | .init_irq = pxa27x_init_irq, | 404 | .init_irq = pxa27x_init_irq, |
405 | .handle_irq = pxa27x_handle_irq, | ||
405 | .timer = &pxa_timer, | 406 | .timer = &pxa_timer, |
406 | .init_machine = palmz72_init | 407 | .init_machine = palmz72_init |
407 | MACHINE_END | 408 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 1fc8a66407ae..ffa65dfb8c6f 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c | |||
@@ -262,6 +262,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270") | |||
262 | .map_io = pcm027_map_io, | 262 | .map_io = pcm027_map_io, |
263 | .nr_irqs = PCM027_NR_IRQS, | 263 | .nr_irqs = PCM027_NR_IRQS, |
264 | .init_irq = pxa27x_init_irq, | 264 | .init_irq = pxa27x_init_irq, |
265 | .handle_irq = pxa27x_handle_irq, | ||
265 | .timer = &pxa_timer, | 266 | .timer = &pxa_timer, |
266 | .init_machine = pcm027_init, | 267 | .init_machine = pcm027_init, |
267 | MACHINE_END | 268 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 16d14fd79b4b..a113ea9ab4ab 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
@@ -468,6 +468,7 @@ MACHINE_START(POODLE, "SHARP Poodle") | |||
468 | .map_io = pxa25x_map_io, | 468 | .map_io = pxa25x_map_io, |
469 | .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */ | 469 | .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */ |
470 | .init_irq = pxa25x_init_irq, | 470 | .init_irq = pxa25x_init_irq, |
471 | .handle_irq = pxa25x_handle_irq, | ||
471 | .timer = &pxa_timer, | 472 | .timer = &pxa_timer, |
472 | .init_machine = poodle_init, | 473 | .init_machine = poodle_init, |
473 | MACHINE_END | 474 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index ef1c56a67afc..b5cd9e5aba31 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <mach/ohci.h> | 32 | #include <mach/ohci.h> |
33 | #include <mach/pm.h> | 33 | #include <mach/pm.h> |
34 | #include <mach/dma.h> | 34 | #include <mach/dma.h> |
35 | #include <mach/regs-intc.h> | ||
36 | #include <mach/smemc.h> | 35 | #include <mach/smemc.h> |
37 | 36 | ||
38 | #include "generic.h" | 37 | #include "generic.h" |
@@ -338,13 +337,13 @@ static void pxa_ack_ext_wakeup(struct irq_data *d) | |||
338 | 337 | ||
339 | static void pxa_mask_ext_wakeup(struct irq_data *d) | 338 | static void pxa_mask_ext_wakeup(struct irq_data *d) |
340 | { | 339 | { |
341 | ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f)); | 340 | pxa_mask_irq(d); |
342 | PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); | 341 | PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); |
343 | } | 342 | } |
344 | 343 | ||
345 | static void pxa_unmask_ext_wakeup(struct irq_data *d) | 344 | static void pxa_unmask_ext_wakeup(struct irq_data *d) |
346 | { | 345 | { |
347 | ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f); | 346 | pxa_unmask_irq(d); |
348 | PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); | 347 | PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); |
349 | } | 348 | } |
350 | 349 | ||
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c index ecc82a330fad..0ee166b61f81 100644 --- a/arch/arm/mach-pxa/pxa95x.c +++ b/arch/arm/mach-pxa/pxa95x.c | |||
@@ -27,7 +27,6 @@ | |||
27 | #include <mach/reset.h> | 27 | #include <mach/reset.h> |
28 | #include <mach/pm.h> | 28 | #include <mach/pm.h> |
29 | #include <mach/dma.h> | 29 | #include <mach/dma.h> |
30 | #include <mach/regs-intc.h> | ||
31 | 30 | ||
32 | #include "generic.h" | 31 | #include "generic.h" |
33 | #include "devices.h" | 32 | #include "devices.h" |
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 2f37d43f51b6..bbcd90562ebe 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c | |||
@@ -46,10 +46,7 @@ | |||
46 | #include <asm/mach-types.h> | 46 | #include <asm/mach-types.h> |
47 | #include <asm/mach/arch.h> | 47 | #include <asm/mach/arch.h> |
48 | 48 | ||
49 | #include <mach/hardware.h> | 49 | #include <mach/pxa300.h> |
50 | #include <mach/pxa3xx-regs.h> | ||
51 | #include <mach/mfp-pxa3xx.h> | ||
52 | #include <mach/mfp-pxa300.h> | ||
53 | #include <mach/ohci.h> | 50 | #include <mach/ohci.h> |
54 | #include <mach/pxafb.h> | 51 | #include <mach/pxafb.h> |
55 | #include <mach/mmc.h> | 52 | #include <mach/mmc.h> |
@@ -1093,6 +1090,7 @@ MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") | |||
1093 | .init_machine = raumfeld_controller_init, | 1090 | .init_machine = raumfeld_controller_init, |
1094 | .map_io = pxa3xx_map_io, | 1091 | .map_io = pxa3xx_map_io, |
1095 | .init_irq = pxa3xx_init_irq, | 1092 | .init_irq = pxa3xx_init_irq, |
1093 | .handle_irq = pxa3xx_handle_irq, | ||
1096 | .timer = &pxa_timer, | 1094 | .timer = &pxa_timer, |
1097 | MACHINE_END | 1095 | MACHINE_END |
1098 | #endif | 1096 | #endif |
@@ -1103,6 +1101,7 @@ MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") | |||
1103 | .init_machine = raumfeld_connector_init, | 1101 | .init_machine = raumfeld_connector_init, |
1104 | .map_io = pxa3xx_map_io, | 1102 | .map_io = pxa3xx_map_io, |
1105 | .init_irq = pxa3xx_init_irq, | 1103 | .init_irq = pxa3xx_init_irq, |
1104 | .handle_irq = pxa3xx_handle_irq, | ||
1106 | .timer = &pxa_timer, | 1105 | .timer = &pxa_timer, |
1107 | MACHINE_END | 1106 | MACHINE_END |
1108 | #endif | 1107 | #endif |
@@ -1113,6 +1112,7 @@ MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") | |||
1113 | .init_machine = raumfeld_speaker_init, | 1112 | .init_machine = raumfeld_speaker_init, |
1114 | .map_io = pxa3xx_map_io, | 1113 | .map_io = pxa3xx_map_io, |
1115 | .init_irq = pxa3xx_init_irq, | 1114 | .init_irq = pxa3xx_init_irq, |
1115 | .handle_irq = pxa3xx_handle_irq, | ||
1116 | .timer = &pxa_timer, | 1116 | .timer = &pxa_timer, |
1117 | MACHINE_END | 1117 | MACHINE_END |
1118 | #endif | 1118 | #endif |
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index fee97a935122..df4356e8acae 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c | |||
@@ -599,6 +599,7 @@ MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") | |||
599 | .boot_params = 0xa0000100, | 599 | .boot_params = 0xa0000100, |
600 | .map_io = pxa3xx_map_io, | 600 | .map_io = pxa3xx_map_io, |
601 | .init_irq = pxa3xx_init_irq, | 601 | .init_irq = pxa3xx_init_irq, |
602 | .handle_irq = pxa3xx_handle_irq, | ||
602 | .timer = &pxa_timer, | 603 | .timer = &pxa_timer, |
603 | .init_machine = saar_init, | 604 | .init_machine = saar_init, |
604 | MACHINE_END | 605 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c index e53a3334c944..ebd6379c4969 100644 --- a/arch/arm/mach-pxa/saarb.c +++ b/arch/arm/mach-pxa/saarb.c | |||
@@ -107,6 +107,7 @@ MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)") | |||
107 | .map_io = pxa3xx_map_io, | 107 | .map_io = pxa3xx_map_io, |
108 | .nr_irqs = SAARB_NR_IRQS, | 108 | .nr_irqs = SAARB_NR_IRQS, |
109 | .init_irq = pxa95x_init_irq, | 109 | .init_irq = pxa95x_init_irq, |
110 | .handle_irq = pxa3xx_handle_irq, | ||
110 | .timer = &pxa_timer, | 111 | .timer = &pxa_timer, |
111 | .init_machine = saarb_init, | 112 | .init_machine = saarb_init, |
112 | MACHINE_END | 113 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 01c576963e94..438c7b5e451f 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
@@ -984,6 +984,7 @@ MACHINE_START(SPITZ, "SHARP Spitz") | |||
984 | .fixup = spitz_fixup, | 984 | .fixup = spitz_fixup, |
985 | .map_io = pxa27x_map_io, | 985 | .map_io = pxa27x_map_io, |
986 | .init_irq = pxa27x_init_irq, | 986 | .init_irq = pxa27x_init_irq, |
987 | .handle_irq = pxa27x_handle_irq, | ||
987 | .init_machine = spitz_init, | 988 | .init_machine = spitz_init, |
988 | .timer = &pxa_timer, | 989 | .timer = &pxa_timer, |
989 | MACHINE_END | 990 | MACHINE_END |
@@ -994,6 +995,7 @@ MACHINE_START(BORZOI, "SHARP Borzoi") | |||
994 | .fixup = spitz_fixup, | 995 | .fixup = spitz_fixup, |
995 | .map_io = pxa27x_map_io, | 996 | .map_io = pxa27x_map_io, |
996 | .init_irq = pxa27x_init_irq, | 997 | .init_irq = pxa27x_init_irq, |
998 | .handle_irq = pxa27x_handle_irq, | ||
997 | .init_machine = spitz_init, | 999 | .init_machine = spitz_init, |
998 | .timer = &pxa_timer, | 1000 | .timer = &pxa_timer, |
999 | MACHINE_END | 1001 | MACHINE_END |
@@ -1004,6 +1006,7 @@ MACHINE_START(AKITA, "SHARP Akita") | |||
1004 | .fixup = spitz_fixup, | 1006 | .fixup = spitz_fixup, |
1005 | .map_io = pxa27x_map_io, | 1007 | .map_io = pxa27x_map_io, |
1006 | .init_irq = pxa27x_init_irq, | 1008 | .init_irq = pxa27x_init_irq, |
1009 | .handle_irq = pxa27x_handle_irq, | ||
1007 | .init_machine = spitz_init, | 1010 | .init_machine = spitz_init, |
1008 | .timer = &pxa_timer, | 1011 | .timer = &pxa_timer, |
1009 | MACHINE_END | 1012 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index cb5611daf5fe..3f8d0af9e2f7 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c | |||
@@ -1001,6 +1001,7 @@ static void __init stargate2_init(void) | |||
1001 | MACHINE_START(INTELMOTE2, "IMOTE 2") | 1001 | MACHINE_START(INTELMOTE2, "IMOTE 2") |
1002 | .map_io = pxa27x_map_io, | 1002 | .map_io = pxa27x_map_io, |
1003 | .init_irq = pxa27x_init_irq, | 1003 | .init_irq = pxa27x_init_irq, |
1004 | .handle_irq = pxa27x_handle_irq, | ||
1004 | .timer = &pxa_timer, | 1005 | .timer = &pxa_timer, |
1005 | .init_machine = imote2_init, | 1006 | .init_machine = imote2_init, |
1006 | .boot_params = 0xA0000100, | 1007 | .boot_params = 0xA0000100, |
@@ -1012,6 +1013,7 @@ MACHINE_START(STARGATE2, "Stargate 2") | |||
1012 | .map_io = pxa27x_map_io, | 1013 | .map_io = pxa27x_map_io, |
1013 | .nr_irqs = STARGATE_NR_IRQS, | 1014 | .nr_irqs = STARGATE_NR_IRQS, |
1014 | .init_irq = pxa27x_init_irq, | 1015 | .init_irq = pxa27x_init_irq, |
1016 | .handle_irq = pxa27x_handle_irq, | ||
1015 | .timer = &pxa_timer, | 1017 | .timer = &pxa_timer, |
1016 | .init_machine = stargate2_init, | 1018 | .init_machine = stargate2_init, |
1017 | .boot_params = 0xA0000100, | 1019 | .boot_params = 0xA0000100, |
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 53d4a472b699..32fb58e01b10 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c | |||
@@ -492,6 +492,7 @@ MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") | |||
492 | .boot_params = 0xa0000100, | 492 | .boot_params = 0xa0000100, |
493 | .map_io = pxa3xx_map_io, | 493 | .map_io = pxa3xx_map_io, |
494 | .init_irq = pxa3xx_init_irq, | 494 | .init_irq = pxa3xx_init_irq, |
495 | .handle_irq = pxa3xx_handle_irq, | ||
495 | .timer = &pxa_timer, | 496 | .timer = &pxa_timer, |
496 | .init_machine = tavorevb_init, | 497 | .init_machine = tavorevb_init, |
497 | MACHINE_END | 498 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c index 79f4422f12f4..fd5a8eae0a87 100644 --- a/arch/arm/mach-pxa/tavorevb3.c +++ b/arch/arm/mach-pxa/tavorevb3.c | |||
@@ -129,6 +129,7 @@ MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)") | |||
129 | .map_io = pxa3xx_map_io, | 129 | .map_io = pxa3xx_map_io, |
130 | .nr_irqs = TAVOREVB3_NR_IRQS, | 130 | .nr_irqs = TAVOREVB3_NR_IRQS, |
131 | .init_irq = pxa3xx_init_irq, | 131 | .init_irq = pxa3xx_init_irq, |
132 | .handle_irq = pxa3xx_handle_irq, | ||
132 | .timer = &pxa_timer, | 133 | .timer = &pxa_timer, |
133 | .init_machine = evb3_init, | 134 | .init_machine = evb3_init, |
134 | MACHINE_END | 135 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 5fa145778e7d..9f69a2682693 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
@@ -974,6 +974,7 @@ MACHINE_START(TOSA, "SHARP Tosa") | |||
974 | .map_io = pxa25x_map_io, | 974 | .map_io = pxa25x_map_io, |
975 | .nr_irqs = TOSA_NR_IRQS, | 975 | .nr_irqs = TOSA_NR_IRQS, |
976 | .init_irq = pxa25x_init_irq, | 976 | .init_irq = pxa25x_init_irq, |
977 | .handle_irq = pxa25x_handle_irq, | ||
977 | .init_machine = tosa_init, | 978 | .init_machine = tosa_init, |
978 | .timer = &pxa_timer, | 979 | .timer = &pxa_timer, |
979 | MACHINE_END | 980 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 687417a93698..c0417508f39d 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
@@ -558,6 +558,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module") | |||
558 | .init_machine = trizeps4_init, | 558 | .init_machine = trizeps4_init, |
559 | .map_io = trizeps4_map_io, | 559 | .map_io = trizeps4_map_io, |
560 | .init_irq = pxa27x_init_irq, | 560 | .init_irq = pxa27x_init_irq, |
561 | .handle_irq = pxa27x_handle_irq, | ||
561 | .timer = &pxa_timer, | 562 | .timer = &pxa_timer, |
562 | MACHINE_END | 563 | MACHINE_END |
563 | 564 | ||
@@ -567,5 +568,6 @@ MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module") | |||
567 | .init_machine = trizeps4_init, | 568 | .init_machine = trizeps4_init, |
568 | .map_io = trizeps4_map_io, | 569 | .map_io = trizeps4_map_io, |
569 | .init_irq = pxa27x_init_irq, | 570 | .init_irq = pxa27x_init_irq, |
571 | .handle_irq = pxa27x_handle_irq, | ||
570 | .timer = &pxa_timer, | 572 | .timer = &pxa_timer, |
571 | MACHINE_END | 573 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 903218eab56d..d4a3dc74e84a 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
@@ -995,6 +995,7 @@ MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC") | |||
995 | .boot_params = 0xa0000100, | 995 | .boot_params = 0xa0000100, |
996 | .map_io = viper_map_io, | 996 | .map_io = viper_map_io, |
997 | .init_irq = viper_init_irq, | 997 | .init_irq = viper_init_irq, |
998 | .handle_irq = pxa25x_handle_irq, | ||
998 | .timer = &pxa_timer, | 999 | .timer = &pxa_timer, |
999 | .init_machine = viper_init, | 1000 | .init_machine = viper_init, |
1000 | MACHINE_END | 1001 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index 67bd41488bf8..5f8490ab07cb 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c | |||
@@ -719,6 +719,7 @@ MACHINE_START(VPAC270, "Voipac PXA270") | |||
719 | .boot_params = 0xa0000100, | 719 | .boot_params = 0xa0000100, |
720 | .map_io = pxa27x_map_io, | 720 | .map_io = pxa27x_map_io, |
721 | .init_irq = pxa27x_init_irq, | 721 | .init_irq = pxa27x_init_irq, |
722 | .handle_irq = pxa27x_handle_irq, | ||
722 | .timer = &pxa_timer, | 723 | .timer = &pxa_timer, |
723 | .init_machine = vpac270_init | 724 | .init_machine = vpac270_init |
724 | MACHINE_END | 725 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index f55f8f2e0db3..acc600f5e72f 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c | |||
@@ -28,8 +28,7 @@ | |||
28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
29 | 29 | ||
30 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
31 | #include <mach/pxa2xx-regs.h> | 31 | #include <mach/pxa25x.h> |
32 | #include <mach/mfp-pxa25x.h> | ||
33 | #include <mach/smemc.h> | 32 | #include <mach/smemc.h> |
34 | 33 | ||
35 | #include "generic.h" | 34 | #include "generic.h" |
@@ -185,6 +184,7 @@ MACHINE_START(XCEP, "Iskratel XCEP") | |||
185 | .init_machine = xcep_init, | 184 | .init_machine = xcep_init, |
186 | .map_io = pxa25x_map_io, | 185 | .map_io = pxa25x_map_io, |
187 | .init_irq = pxa25x_init_irq, | 186 | .init_irq = pxa25x_init_irq, |
187 | .handle_irq = pxa25x_handle_irq, | ||
188 | .timer = &pxa_timer, | 188 | .timer = &pxa_timer, |
189 | MACHINE_END | 189 | MACHINE_END |
190 | 190 | ||
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index fbe9e02e2f9f..6c9275a20c91 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <mach/pxafb.h> | 40 | #include <mach/pxafb.h> |
41 | #include <mach/mmc.h> | 41 | #include <mach/mmc.h> |
42 | #include <plat/pxa27x_keypad.h> | 42 | #include <plat/pxa27x_keypad.h> |
43 | #include <mach/pm.h> | ||
43 | 44 | ||
44 | #include "generic.h" | 45 | #include "generic.h" |
45 | #include "devices.h" | 46 | #include "devices.h" |
@@ -677,6 +678,20 @@ static void __init z2_pmic_init(void) | |||
677 | static inline void z2_pmic_init(void) {} | 678 | static inline void z2_pmic_init(void) {} |
678 | #endif | 679 | #endif |
679 | 680 | ||
681 | #ifdef CONFIG_PM | ||
682 | static void z2_power_off(void) | ||
683 | { | ||
684 | /* We're using deep sleep as poweroff, so clear PSPR to ensure that | ||
685 | * bootloader will jump to its entry point in resume handler | ||
686 | */ | ||
687 | PSPR = 0x0; | ||
688 | local_irq_disable(); | ||
689 | pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET); | ||
690 | } | ||
691 | #else | ||
692 | #define z2_power_off NULL | ||
693 | #endif | ||
694 | |||
680 | /****************************************************************************** | 695 | /****************************************************************************** |
681 | * Machine init | 696 | * Machine init |
682 | ******************************************************************************/ | 697 | ******************************************************************************/ |
@@ -698,12 +713,15 @@ static void __init z2_init(void) | |||
698 | z2_leds_init(); | 713 | z2_leds_init(); |
699 | z2_keys_init(); | 714 | z2_keys_init(); |
700 | z2_pmic_init(); | 715 | z2_pmic_init(); |
716 | |||
717 | pm_power_off = z2_power_off; | ||
701 | } | 718 | } |
702 | 719 | ||
703 | MACHINE_START(ZIPIT2, "Zipit Z2") | 720 | MACHINE_START(ZIPIT2, "Zipit Z2") |
704 | .boot_params = 0xa0000100, | 721 | .boot_params = 0xa0000100, |
705 | .map_io = pxa27x_map_io, | 722 | .map_io = pxa27x_map_io, |
706 | .init_irq = pxa27x_init_irq, | 723 | .init_irq = pxa27x_init_irq, |
724 | .handle_irq = pxa27x_handle_irq, | ||
707 | .timer = &pxa_timer, | 725 | .timer = &pxa_timer, |
708 | .init_machine = z2_init, | 726 | .init_machine = z2_init, |
709 | MACHINE_END | 727 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 9b99cc164de5..99c49bcd9f70 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c | |||
@@ -35,14 +35,13 @@ | |||
35 | #include <asm/mach/arch.h> | 35 | #include <asm/mach/arch.h> |
36 | #include <asm/mach/map.h> | 36 | #include <asm/mach/map.h> |
37 | 37 | ||
38 | #include <mach/pxa2xx-regs.h> | 38 | #include <mach/pxa27x.h> |
39 | #include <mach/regs-uart.h> | 39 | #include <mach/regs-uart.h> |
40 | #include <mach/ohci.h> | 40 | #include <mach/ohci.h> |
41 | #include <mach/mmc.h> | 41 | #include <mach/mmc.h> |
42 | #include <mach/pxa27x-udc.h> | 42 | #include <mach/pxa27x-udc.h> |
43 | #include <mach/udc.h> | 43 | #include <mach/udc.h> |
44 | #include <mach/pxafb.h> | 44 | #include <mach/pxafb.h> |
45 | #include <mach/mfp-pxa27x.h> | ||
46 | #include <mach/pm.h> | 45 | #include <mach/pm.h> |
47 | #include <mach/audio.h> | 46 | #include <mach/audio.h> |
48 | #include <mach/arcom-pcmcia.h> | 47 | #include <mach/arcom-pcmcia.h> |
@@ -909,6 +908,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS") | |||
909 | .map_io = zeus_map_io, | 908 | .map_io = zeus_map_io, |
910 | .nr_irqs = ZEUS_NR_IRQS, | 909 | .nr_irqs = ZEUS_NR_IRQS, |
911 | .init_irq = zeus_init_irq, | 910 | .init_irq = zeus_init_irq, |
911 | .handle_irq = pxa27x_handle_irq, | ||
912 | .timer = &pxa_timer, | 912 | .timer = &pxa_timer, |
913 | .init_machine = zeus_init, | 913 | .init_machine = zeus_init, |
914 | MACHINE_END | 914 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 5821185f77ab..15ec66b3471a 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c | |||
@@ -24,7 +24,7 @@ | |||
24 | 24 | ||
25 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
27 | #include <mach/hardware.h> | 27 | #include <mach/pxa3xx.h> |
28 | #include <mach/audio.h> | 28 | #include <mach/audio.h> |
29 | #include <mach/pxafb.h> | 29 | #include <mach/pxafb.h> |
30 | #include <mach/zylonite.h> | 30 | #include <mach/zylonite.h> |
@@ -426,6 +426,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") | |||
426 | .map_io = pxa3xx_map_io, | 426 | .map_io = pxa3xx_map_io, |
427 | .nr_irqs = ZYLONITE_NR_IRQS, | 427 | .nr_irqs = ZYLONITE_NR_IRQS, |
428 | .init_irq = pxa3xx_init_irq, | 428 | .init_irq = pxa3xx_init_irq, |
429 | .handle_irq = pxa3xx_handle_irq, | ||
429 | .timer = &pxa_timer, | 430 | .timer = &pxa_timer, |
430 | .init_machine = zylonite_init, | 431 | .init_machine = zylonite_init, |
431 | MACHINE_END | 432 | MACHINE_END |
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h index 70a83b209e25..45eea5210c87 100644 --- a/arch/arm/mach-s3c2410/include/mach/pm-core.h +++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h | |||
@@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, | |||
62 | struct pm_uart_save *save) | 62 | struct pm_uart_save *save) |
63 | { | 63 | { |
64 | } | 64 | } |
65 | |||
66 | static inline void s3c_pm_restored_gpios(void) { } | ||
67 | static inline void s3c_pm_saved_gpios(void) { } | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index ddb63a1863ab..c026f67a80de 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h | |||
@@ -217,6 +217,7 @@ | |||
217 | /* Compatibility */ | 217 | /* Compatibility */ |
218 | 218 | ||
219 | #define IRQ_ONENAND IRQ_ONENAND0 | 219 | #define IRQ_ONENAND IRQ_ONENAND0 |
220 | #define IRQ_I2S0 IRQ_S3C6410_IIS | ||
220 | 221 | ||
221 | #endif /* __ASM_MACH_S3C64XX_IRQS_H */ | 222 | #endif /* __ASM_MACH_S3C64XX_IRQS_H */ |
222 | 223 | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index 1e9f20f0bb7b..38659bebe4b1 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h | |||
@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void) | |||
53 | * the IRQ wake controls depending on the CPU we are running on */ | 53 | * the IRQ wake controls depending on the CPU we are running on */ |
54 | 54 | ||
55 | #define s3c_irqwake_eintallow ((1 << 28) - 1) | 55 | #define s3c_irqwake_eintallow ((1 << 28) - 1) |
56 | #define s3c_irqwake_intallow (0) | 56 | #define s3c_irqwake_intallow (~0) |
57 | 57 | ||
58 | static inline void s3c_pm_arch_update_uart(void __iomem *regs, | 58 | static inline void s3c_pm_arch_update_uart(void __iomem *regs, |
59 | struct pm_uart_save *save) | 59 | struct pm_uart_save *save) |
@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, | |||
96 | save->ucon = new_ucon; | 96 | save->ucon = new_ucon; |
97 | } | 97 | } |
98 | } | 98 | } |
99 | |||
100 | static inline void s3c_pm_restored_gpios(void) | ||
101 | { | ||
102 | /* ensure sleep mode has been cleared from the system */ | ||
103 | |||
104 | __raw_writel(0, S3C64XX_SLPEN); | ||
105 | } | ||
106 | |||
107 | static inline void s3c_pm_saved_gpios(void) | ||
108 | { | ||
109 | /* turn on the sleep mode and keep it there, as it seems that during | ||
110 | * suspend the xCON registers get re-set and thus you can end up with | ||
111 | * problems between going to sleep and resuming. | ||
112 | */ | ||
113 | |||
114 | __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); | ||
115 | } | ||
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c index 97660c8141ae..75d9a0e49193 100644 --- a/arch/arm/mach-s3c64xx/irq.c +++ b/arch/arm/mach-s3c64xx/irq.c | |||
@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = { | |||
48 | }, | 48 | }, |
49 | }; | 49 | }; |
50 | 50 | ||
51 | /* setup the sources the vic should advertise resume for, even though it | ||
52 | * is not doing the wake (set_irq_wake needs to be valid) */ | ||
53 | #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) | ||
54 | #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \ | ||
55 | 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \ | ||
56 | 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \ | ||
57 | 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \ | ||
58 | 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE)) | ||
51 | 59 | ||
52 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) | 60 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) |
53 | { | 61 | { |
54 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | 62 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
55 | 63 | ||
56 | /* initialise the pair of VICs */ | 64 | /* initialise the pair of VICs */ |
57 | vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); | 65 | vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); |
58 | vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); | 66 | vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); |
59 | 67 | ||
60 | /* add the timer sub-irqs */ | 68 | /* add the timer sub-irqs */ |
61 | s3c_init_vic_timer_irq(5, IRQ_TIMER0); | 69 | s3c_init_vic_timer_irq(5, IRQ_TIMER0); |
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile index ae6bf6feba89..5f6afdf067ed 100644 --- a/arch/arm/mach-s5p64x0/Makefile +++ b/arch/arm/mach-s5p64x0/Makefile | |||
@@ -13,7 +13,7 @@ obj- := | |||
13 | # Core support for S5P64X0 system | 13 | # Core support for S5P64X0 system |
14 | 14 | ||
15 | obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o | 15 | obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o |
16 | obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o | 16 | obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o |
17 | obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o | 17 | obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o |
18 | obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o | 18 | obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o |
19 | 19 | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h index 513abffc7604..5837a36ece8d 100644 --- a/arch/arm/mach-s5p64x0/include/mach/irqs.h +++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h | |||
@@ -85,6 +85,8 @@ | |||
85 | #define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4 | 85 | #define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4 |
86 | #define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5 | 86 | #define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5 |
87 | 87 | ||
88 | #define IRQ_I2S0 IRQ_I2SV40 | ||
89 | |||
88 | /* S5P6450 EINT feature will be added */ | 90 | /* S5P6450 EINT feature will be added */ |
89 | 91 | ||
90 | /* | 92 | /* |
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h index 0953ef6b1c77..6ce254729f3b 100644 --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | |||
@@ -34,4 +34,14 @@ | |||
34 | #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) | 34 | #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) |
35 | #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) | 35 | #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) |
36 | 36 | ||
37 | /* External interrupt control registers for group0 */ | ||
38 | |||
39 | #define EINT0CON0_OFFSET (0x900) | ||
40 | #define EINT0MASK_OFFSET (0x920) | ||
41 | #define EINT0PEND_OFFSET (0x924) | ||
42 | |||
43 | #define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET) | ||
44 | #define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET) | ||
45 | #define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET) | ||
46 | |||
37 | #endif /* __ASM_ARCH_REGS_GPIO_H */ | 47 | #endif /* __ASM_ARCH_REGS_GPIO_H */ |
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c new file mode 100644 index 000000000000..69ed4545112b --- /dev/null +++ b/arch/arm/mach-s5p64x0/irq-eint.c | |||
@@ -0,0 +1,152 @@ | |||
1 | /* arch/arm/mach-s5p64x0/irq-eint.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c | ||
7 | * | ||
8 | * S5P64X0 - Interrupt handling for External Interrupts. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/gpio.h> | ||
17 | #include <linux/irq.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include <plat/regs-irqtype.h> | ||
21 | #include <plat/gpio-cfg.h> | ||
22 | |||
23 | #include <mach/regs-gpio.h> | ||
24 | #include <mach/regs-clock.h> | ||
25 | |||
26 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) | ||
27 | |||
28 | static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type) | ||
29 | { | ||
30 | int offs = eint_offset(data->irq); | ||
31 | int shift; | ||
32 | u32 ctrl, mask; | ||
33 | u32 newvalue = 0; | ||
34 | |||
35 | if (offs > 15) | ||
36 | return -EINVAL; | ||
37 | |||
38 | switch (type) { | ||
39 | case IRQ_TYPE_NONE: | ||
40 | printk(KERN_WARNING "No edge setting!\n"); | ||
41 | break; | ||
42 | case IRQ_TYPE_EDGE_RISING: | ||
43 | newvalue = S3C2410_EXTINT_RISEEDGE; | ||
44 | break; | ||
45 | case IRQ_TYPE_EDGE_FALLING: | ||
46 | newvalue = S3C2410_EXTINT_FALLEDGE; | ||
47 | break; | ||
48 | case IRQ_TYPE_EDGE_BOTH: | ||
49 | newvalue = S3C2410_EXTINT_BOTHEDGE; | ||
50 | break; | ||
51 | case IRQ_TYPE_LEVEL_LOW: | ||
52 | newvalue = S3C2410_EXTINT_LOWLEV; | ||
53 | break; | ||
54 | case IRQ_TYPE_LEVEL_HIGH: | ||
55 | newvalue = S3C2410_EXTINT_HILEV; | ||
56 | break; | ||
57 | default: | ||
58 | printk(KERN_ERR "No such irq type %d", type); | ||
59 | return -EINVAL; | ||
60 | } | ||
61 | |||
62 | shift = (offs / 2) * 4; | ||
63 | mask = 0x7 << shift; | ||
64 | |||
65 | ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask; | ||
66 | ctrl |= newvalue << shift; | ||
67 | __raw_writel(ctrl, S5P64X0_EINT0CON0); | ||
68 | |||
69 | /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ | ||
70 | if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000)) | ||
71 | s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); | ||
72 | else | ||
73 | s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); | ||
74 | |||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | /* | ||
79 | * s5p64x0_irq_demux_eint | ||
80 | * | ||
81 | * This function demuxes the IRQ from the group0 external interrupts, | ||
82 | * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into | ||
83 | * the specific handlers s5p64x0_irq_demux_eintX_Y. | ||
84 | */ | ||
85 | static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end) | ||
86 | { | ||
87 | u32 status = __raw_readl(S5P64X0_EINT0PEND); | ||
88 | u32 mask = __raw_readl(S5P64X0_EINT0MASK); | ||
89 | unsigned int irq; | ||
90 | |||
91 | status &= ~mask; | ||
92 | status >>= start; | ||
93 | status &= (1 << (end - start + 1)) - 1; | ||
94 | |||
95 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { | ||
96 | if (status & 1) | ||
97 | generic_handle_irq(irq); | ||
98 | status >>= 1; | ||
99 | } | ||
100 | } | ||
101 | |||
102 | static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) | ||
103 | { | ||
104 | s5p64x0_irq_demux_eint(0, 3); | ||
105 | } | ||
106 | |||
107 | static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) | ||
108 | { | ||
109 | s5p64x0_irq_demux_eint(4, 11); | ||
110 | } | ||
111 | |||
112 | static void s5p64x0_irq_demux_eint12_15(unsigned int irq, | ||
113 | struct irq_desc *desc) | ||
114 | { | ||
115 | s5p64x0_irq_demux_eint(12, 15); | ||
116 | } | ||
117 | |||
118 | static int s5p64x0_alloc_gc(void) | ||
119 | { | ||
120 | struct irq_chip_generic *gc; | ||
121 | struct irq_chip_type *ct; | ||
122 | |||
123 | gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE, | ||
124 | S5P_VA_GPIO, handle_level_irq); | ||
125 | if (!gc) { | ||
126 | printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0" | ||
127 | "external interrupts failed\n", __func__); | ||
128 | return -EINVAL; | ||
129 | } | ||
130 | |||
131 | ct = gc->chip_types; | ||
132 | ct->chip.irq_ack = irq_gc_ack; | ||
133 | ct->chip.irq_mask = irq_gc_mask_set_bit; | ||
134 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | ||
135 | ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; | ||
136 | ct->regs.ack = EINT0PEND_OFFSET; | ||
137 | ct->regs.mask = EINT0MASK_OFFSET; | ||
138 | irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, | ||
139 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | ||
140 | return 0; | ||
141 | } | ||
142 | |||
143 | static int __init s5p64x0_init_irq_eint(void) | ||
144 | { | ||
145 | int ret = s5p64x0_alloc_gc(); | ||
146 | irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3); | ||
147 | irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11); | ||
148 | irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15); | ||
149 | |||
150 | return ret; | ||
151 | } | ||
152 | arch_initcall(s5p64x0_init_irq_eint); | ||
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 79bb3a0314ef..69dd87cd8e22 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig | |||
@@ -90,6 +90,7 @@ config MACH_GONI | |||
90 | select S3C_DEV_HSMMC2 | 90 | select S3C_DEV_HSMMC2 |
91 | select S3C_DEV_I2C1 | 91 | select S3C_DEV_I2C1 |
92 | select S3C_DEV_I2C2 | 92 | select S3C_DEV_I2C2 |
93 | select S5P_DEV_MFC | ||
93 | select S3C_DEV_USB_HSOTG | 94 | select S3C_DEV_USB_HSOTG |
94 | select S5P_DEV_ONENAND | 95 | select S5P_DEV_ONENAND |
95 | select SAMSUNG_DEV_KEYPAD | 96 | select SAMSUNG_DEV_KEYPAD |
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index ae72f87eab15..52a8e607bcc2 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -324,6 +324,12 @@ static struct clk init_clocks_off[] = { | |||
324 | .enable = s5pv210_clk_ip0_ctrl, | 324 | .enable = s5pv210_clk_ip0_ctrl, |
325 | .ctrlbit = (1 << 26), | 325 | .ctrlbit = (1 << 26), |
326 | }, { | 326 | }, { |
327 | .name = "mfc", | ||
328 | .devname = "s5p-mfc", | ||
329 | .parent = &clk_pclk_psys.clk, | ||
330 | .enable = s5pv210_clk_ip0_ctrl, | ||
331 | .ctrlbit = (1 << 16), | ||
332 | }, { | ||
327 | .name = "otg", | 333 | .name = "otg", |
328 | .parent = &clk_hclk_psys.clk, | 334 | .parent = &clk_hclk_psys.clk, |
329 | .enable = s5pv210_clk_ip1_ctrl, | 335 | .enable = s5pv210_clk_ip1_ctrl, |
@@ -879,6 +885,7 @@ static struct clksrc_clk clksrcs[] = { | |||
879 | }, { | 885 | }, { |
880 | .clk = { | 886 | .clk = { |
881 | .name = "sclk_mfc", | 887 | .name = "sclk_mfc", |
888 | .devname = "s5p-mfc", | ||
882 | .enable = s5pv210_clk_ip0_ctrl, | 889 | .enable = s5pv210_clk_ip0_ctrl, |
883 | .ctrlbit = (1 << 16), | 890 | .ctrlbit = (1 << 16), |
884 | }, | 891 | }, |
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 61e6c24b90ac..79907ec78d43 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c | |||
@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void) | |||
126 | s5pv210_default_sdhci2(); | 126 | s5pv210_default_sdhci2(); |
127 | s5pv210_default_sdhci3(); | 127 | s5pv210_default_sdhci3(); |
128 | 128 | ||
129 | s3c_adc_setname("s3c64xx-adc"); | 129 | s3c_adc_setname("samsung-adc-v3"); |
130 | 130 | ||
131 | s3c_cfcon_setname("s5pv210-pata"); | 131 | s3c_cfcon_setname("s5pv210-pata"); |
132 | 132 | ||
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 8d58f1926241..63f5d82004b5 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <mach/map.h> | 18 | #include <mach/map.h> |
19 | #include <mach/dma.h> | 19 | #include <mach/dma.h> |
20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
21 | #include <mach/regs-audss.h> | ||
21 | 22 | ||
22 | static const char *rclksrc[] = { | 23 | static const char *rclksrc[] = { |
23 | [0] = "busclk", | 24 | [0] = "busclk", |
@@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = { | |||
52 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | 53 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI |
53 | | QUIRK_NEED_RSTCLR, | 54 | | QUIRK_NEED_RSTCLR, |
54 | .src_clk = rclksrc, | 55 | .src_clk = rclksrc, |
56 | .idma_addr = S5PV210_AUDSS_INT_MEM, | ||
55 | }, | 57 | }, |
56 | }, | 58 | }, |
57 | }; | 59 | }; |
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 1dd58836fd4f..aac343c180b2 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h | |||
@@ -59,6 +59,8 @@ | |||
59 | 59 | ||
60 | #define S5PV210_PA_CFCON 0xE8200000 | 60 | #define S5PV210_PA_CFCON 0xE8200000 |
61 | 61 | ||
62 | #define S5PV210_PA_MFC 0xF1700000 | ||
63 | |||
62 | #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) | 64 | #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) |
63 | 65 | ||
64 | #define S5PV210_PA_HSOTG 0xEC000000 | 66 | #define S5PV210_PA_HSOTG 0xEC000000 |
@@ -107,6 +109,7 @@ | |||
107 | #define S5P_PA_FIMC1 S5PV210_PA_FIMC1 | 109 | #define S5P_PA_FIMC1 S5PV210_PA_FIMC1 |
108 | #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 | 110 | #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 |
109 | #define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS | 111 | #define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS |
112 | #define S5P_PA_MFC S5PV210_PA_MFC | ||
110 | #define S5P_PA_ONENAND S5PC110_PA_ONENAND | 113 | #define S5P_PA_ONENAND S5PC110_PA_ONENAND |
111 | #define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA | 114 | #define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA |
112 | #define S5P_PA_SDRAM S5PV210_PA_SDRAM | 115 | #define S5P_PA_SDRAM S5PV210_PA_SDRAM |
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index e8d394f8b057..3e22109e1b7b 100644 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h | |||
@@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, | |||
41 | { | 41 | { |
42 | /* nothing here yet */ | 42 | /* nothing here yet */ |
43 | } | 43 | } |
44 | |||
45 | static inline void s3c_pm_restored_gpios(void) { } | ||
46 | static inline void s3c_pm_saved_gpios(void) { } | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h new file mode 100644 index 000000000000..eacc1f790807 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/mach-s5pv210/include/mach/regs-audss.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5PV210 Audio SubSystem clock register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __PLAT_REGS_AUDSS_H | ||
14 | #define __PLAT_REGS_AUDSS_H __FILE__ | ||
15 | |||
16 | #define S5PV210_AUDSS_INT_MEM (0xC0000000) | ||
17 | |||
18 | #endif /* _PLAT_REGS_AUDSS_H */ | ||
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index e0c4d06b9db6..85c2d51a0956 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c | |||
@@ -46,6 +46,7 @@ | |||
46 | #include <plat/sdhci.h> | 46 | #include <plat/sdhci.h> |
47 | #include <plat/clock.h> | 47 | #include <plat/clock.h> |
48 | #include <plat/s5p-time.h> | 48 | #include <plat/s5p-time.h> |
49 | #include <plat/mfc.h> | ||
49 | #include <plat/regs-fb-v4.h> | 50 | #include <plat/regs-fb-v4.h> |
50 | 51 | ||
51 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 52 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
@@ -808,6 +809,9 @@ static struct platform_device *goni_devices[] __initdata = { | |||
808 | &goni_i2c_gpio5, | 809 | &goni_i2c_gpio5, |
809 | &mmc2_fixed_voltage, | 810 | &mmc2_fixed_voltage, |
810 | &goni_device_gpiokeys, | 811 | &goni_device_gpiokeys, |
812 | &s5p_device_mfc, | ||
813 | &s5p_device_mfc_l, | ||
814 | &s5p_device_mfc_r, | ||
811 | &s3c_device_i2c0, | 815 | &s3c_device_i2c0, |
812 | &s5p_device_fimc0, | 816 | &s5p_device_fimc0, |
813 | &s5p_device_fimc1, | 817 | &s5p_device_fimc1, |
@@ -841,6 +845,11 @@ static void __init goni_map_io(void) | |||
841 | s5p_set_timer_source(S5P_PWM3, S5P_PWM4); | 845 | s5p_set_timer_source(S5P_PWM3, S5P_PWM4); |
842 | } | 846 | } |
843 | 847 | ||
848 | static void __init goni_reserve(void) | ||
849 | { | ||
850 | s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); | ||
851 | } | ||
852 | |||
844 | static void __init goni_machine_init(void) | 853 | static void __init goni_machine_init(void) |
845 | { | 854 | { |
846 | /* Radio: call before I2C 1 registeration */ | 855 | /* Radio: call before I2C 1 registeration */ |
@@ -893,4 +902,5 @@ MACHINE_START(GONI, "GONI") | |||
893 | .map_io = goni_map_io, | 902 | .map_io = goni_map_io, |
894 | .init_machine = goni_machine_init, | 903 | .init_machine = goni_machine_init, |
895 | .timer = &s5p_timer, | 904 | .timer = &s5p_timer, |
905 | .reserve = &goni_reserve, | ||
896 | MACHINE_END | 906 | MACHINE_END |
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index ef20f922249d..5e011fc6720d 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c | |||
@@ -229,6 +229,7 @@ static struct platform_device *smdkv210_devices[] __initdata = { | |||
229 | &s5pv210_device_iis0, | 229 | &s5pv210_device_iis0, |
230 | &s5pv210_device_spdif, | 230 | &s5pv210_device_spdif, |
231 | &samsung_asoc_dma, | 231 | &samsung_asoc_dma, |
232 | &samsung_asoc_idma, | ||
232 | &samsung_device_keypad, | 233 | &samsung_device_keypad, |
233 | &smdkv210_dm9000, | 234 | &smdkv210_dm9000, |
234 | &smdkv210_lcd_lte480wv, | 235 | &smdkv210_lcd_lte480wv, |
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index 30e18bc60647..846cd7d69e3e 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c | |||
@@ -25,7 +25,6 @@ | |||
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | #include <linux/gpio.h> | 26 | #include <linux/gpio.h> |
27 | #include <linux/i2c.h> | 27 | #include <linux/i2c.h> |
28 | #include <linux/i2c-tegra.h> | ||
29 | 28 | ||
30 | #include <sound/wm8903.h> | 29 | #include <sound/wm8903.h> |
31 | 30 | ||
@@ -83,22 +82,6 @@ static struct platform_device harmony_audio_device = { | |||
83 | }, | 82 | }, |
84 | }; | 83 | }; |
85 | 84 | ||
86 | static struct tegra_i2c_platform_data harmony_i2c1_platform_data = { | ||
87 | .bus_clk_rate = 400000, | ||
88 | }; | ||
89 | |||
90 | static struct tegra_i2c_platform_data harmony_i2c2_platform_data = { | ||
91 | .bus_clk_rate = 400000, | ||
92 | }; | ||
93 | |||
94 | static struct tegra_i2c_platform_data harmony_i2c3_platform_data = { | ||
95 | .bus_clk_rate = 400000, | ||
96 | }; | ||
97 | |||
98 | static struct tegra_i2c_platform_data harmony_dvc_platform_data = { | ||
99 | .bus_clk_rate = 400000, | ||
100 | }; | ||
101 | |||
102 | static struct wm8903_platform_data harmony_wm8903_pdata = { | 85 | static struct wm8903_platform_data harmony_wm8903_pdata = { |
103 | .irq_active_low = 0, | 86 | .irq_active_low = 0, |
104 | .micdet_cfg = 0, | 87 | .micdet_cfg = 0, |
@@ -121,11 +104,6 @@ static struct i2c_board_info __initdata wm8903_board_info = { | |||
121 | 104 | ||
122 | static void __init harmony_i2c_init(void) | 105 | static void __init harmony_i2c_init(void) |
123 | { | 106 | { |
124 | tegra_i2c_device1.dev.platform_data = &harmony_i2c1_platform_data; | ||
125 | tegra_i2c_device2.dev.platform_data = &harmony_i2c2_platform_data; | ||
126 | tegra_i2c_device3.dev.platform_data = &harmony_i2c3_platform_data; | ||
127 | tegra_i2c_device4.dev.platform_data = &harmony_dvc_platform_data; | ||
128 | |||
129 | platform_device_register(&tegra_i2c_device1); | 107 | platform_device_register(&tegra_i2c_device1); |
130 | platform_device_register(&tegra_i2c_device2); | 108 | platform_device_register(&tegra_i2c_device2); |
131 | platform_device_register(&tegra_i2c_device3); | 109 | platform_device_register(&tegra_i2c_device3); |
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c index 2643d1bd568b..bdd2627dd87b 100644 --- a/arch/arm/mach-tegra/board-paz00-pinmux.c +++ b/arch/arm/mach-tegra/board-paz00-pinmux.c | |||
@@ -141,12 +141,10 @@ static struct tegra_pingroup_config paz00_pinmux[] = { | |||
141 | }; | 141 | }; |
142 | 142 | ||
143 | static struct tegra_gpio_table gpio_table[] = { | 143 | static struct tegra_gpio_table gpio_table[] = { |
144 | { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, | 144 | { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, |
145 | { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, | 145 | { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, |
146 | { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, | 146 | { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, |
147 | { .gpio = TEGRA_GPIO_SD4_CD, .enable = true }, | 147 | { .gpio = TEGRA_ULPI_RST, .enable = true }, |
148 | { .gpio = TEGRA_GPIO_SD4_WP, .enable = true }, | ||
149 | { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true }, | ||
150 | }; | 148 | }; |
151 | 149 | ||
152 | void paz00_pinmux_init(void) | 150 | void paz00_pinmux_init(void) |
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 57e50a823eec..ea2f79c9879b 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/dma-mapping.h> | 25 | #include <linux/dma-mapping.h> |
26 | #include <linux/pda_power.h> | 26 | #include <linux/pda_power.h> |
27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
28 | #include <linux/i2c.h> | ||
28 | 29 | ||
29 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
30 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
@@ -34,6 +35,7 @@ | |||
34 | #include <mach/iomap.h> | 35 | #include <mach/iomap.h> |
35 | #include <mach/irqs.h> | 36 | #include <mach/irqs.h> |
36 | #include <mach/sdhci.h> | 37 | #include <mach/sdhci.h> |
38 | #include <mach/gpio.h> | ||
37 | 39 | ||
38 | #include "board.h" | 40 | #include "board.h" |
39 | #include "board-paz00.h" | 41 | #include "board-paz00.h" |
@@ -66,10 +68,22 @@ static struct platform_device debug_uart = { | |||
66 | static struct platform_device *paz00_devices[] __initdata = { | 68 | static struct platform_device *paz00_devices[] __initdata = { |
67 | &debug_uart, | 69 | &debug_uart, |
68 | &tegra_sdhci_device1, | 70 | &tegra_sdhci_device1, |
69 | &tegra_sdhci_device2, | ||
70 | &tegra_sdhci_device4, | 71 | &tegra_sdhci_device4, |
71 | }; | 72 | }; |
72 | 73 | ||
74 | static void paz00_i2c_init(void) | ||
75 | { | ||
76 | platform_device_register(&tegra_i2c_device1); | ||
77 | platform_device_register(&tegra_i2c_device2); | ||
78 | platform_device_register(&tegra_i2c_device4); | ||
79 | } | ||
80 | |||
81 | static void paz00_usb_init(void) | ||
82 | { | ||
83 | platform_device_register(&tegra_ehci2_device); | ||
84 | platform_device_register(&tegra_ehci3_device); | ||
85 | } | ||
86 | |||
73 | static void __init tegra_paz00_fixup(struct machine_desc *desc, | 87 | static void __init tegra_paz00_fixup(struct machine_desc *desc, |
74 | struct tag *tags, char **cmdline, struct meminfo *mi) | 88 | struct tag *tags, char **cmdline, struct meminfo *mi) |
75 | { | 89 | { |
@@ -84,23 +98,16 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { | |||
84 | { NULL, NULL, 0, 0}, | 98 | { NULL, NULL, 0, 0}, |
85 | }; | 99 | }; |
86 | 100 | ||
87 | |||
88 | static struct tegra_sdhci_platform_data sdhci_pdata1 = { | 101 | static struct tegra_sdhci_platform_data sdhci_pdata1 = { |
89 | .cd_gpio = TEGRA_GPIO_SD1_CD, | 102 | .cd_gpio = TEGRA_GPIO_SD1_CD, |
90 | .wp_gpio = TEGRA_GPIO_SD1_WP, | 103 | .wp_gpio = TEGRA_GPIO_SD1_WP, |
91 | .power_gpio = TEGRA_GPIO_SD1_POWER, | 104 | .power_gpio = TEGRA_GPIO_SD1_POWER, |
92 | }; | 105 | }; |
93 | 106 | ||
94 | static struct tegra_sdhci_platform_data sdhci_pdata2 = { | 107 | static struct tegra_sdhci_platform_data sdhci_pdata4 = { |
95 | .cd_gpio = -1, | 108 | .cd_gpio = -1, |
96 | .wp_gpio = -1, | 109 | .wp_gpio = -1, |
97 | .power_gpio = -1, | 110 | .power_gpio = -1, |
98 | }; | ||
99 | |||
100 | static struct tegra_sdhci_platform_data sdhci_pdata4 = { | ||
101 | .cd_gpio = TEGRA_GPIO_SD4_CD, | ||
102 | .wp_gpio = TEGRA_GPIO_SD4_WP, | ||
103 | .power_gpio = TEGRA_GPIO_SD4_POWER, | ||
104 | .is_8bit = 1, | 111 | .is_8bit = 1, |
105 | }; | 112 | }; |
106 | 113 | ||
@@ -111,13 +118,15 @@ static void __init tegra_paz00_init(void) | |||
111 | paz00_pinmux_init(); | 118 | paz00_pinmux_init(); |
112 | 119 | ||
113 | tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; | 120 | tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; |
114 | tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2; | ||
115 | tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; | 121 | tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; |
116 | 122 | ||
117 | platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices)); | 123 | platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices)); |
124 | |||
125 | paz00_i2c_init(); | ||
126 | paz00_usb_init(); | ||
118 | } | 127 | } |
119 | 128 | ||
120 | MACHINE_START(PAZ00, "paz00") | 129 | MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") |
121 | .boot_params = 0x00000100, | 130 | .boot_params = 0x00000100, |
122 | .fixup = tegra_paz00_fixup, | 131 | .fixup = tegra_paz00_fixup, |
123 | .map_io = tegra_map_common_io, | 132 | .map_io = tegra_map_common_io, |
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h index da193ca76d3b..d4ff39ddaeb3 100644 --- a/arch/arm/mach-tegra/board-paz00.h +++ b/arch/arm/mach-tegra/board-paz00.h | |||
@@ -17,12 +17,10 @@ | |||
17 | #ifndef _MACH_TEGRA_BOARD_PAZ00_H | 17 | #ifndef _MACH_TEGRA_BOARD_PAZ00_H |
18 | #define _MACH_TEGRA_BOARD_PAZ00_H | 18 | #define _MACH_TEGRA_BOARD_PAZ00_H |
19 | 19 | ||
20 | #define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 | 20 | #define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 |
21 | #define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 | 21 | #define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 |
22 | #define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 | 22 | #define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 |
23 | #define TEGRA_GPIO_SD4_CD TEGRA_GPIO_PH2 | 23 | #define TEGRA_ULPI_RST TEGRA_GPIO_PV0 |
24 | #define TEGRA_GPIO_SD4_WP TEGRA_GPIO_PH3 | ||
25 | #define TEGRA_GPIO_SD4_POWER TEGRA_GPIO_PI6 | ||
26 | 24 | ||
27 | void paz00_pinmux_init(void); | 25 | void paz00_pinmux_init(void); |
28 | 26 | ||
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index 10fbbdc8699a..56cbabf6aa68 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c | |||
@@ -19,7 +19,6 @@ | |||
19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
20 | #include <linux/serial_8250.h> | 20 | #include <linux/serial_8250.h> |
21 | #include <linux/i2c.h> | 21 | #include <linux/i2c.h> |
22 | #include <linux/i2c-tegra.h> | ||
23 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
24 | #include <linux/input.h> | 23 | #include <linux/input.h> |
25 | #include <linux/io.h> | 24 | #include <linux/io.h> |
@@ -66,22 +65,6 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = { | |||
66 | { NULL, NULL, 0, 0}, | 65 | { NULL, NULL, 0, 0}, |
67 | }; | 66 | }; |
68 | 67 | ||
69 | static struct tegra_i2c_platform_data seaboard_i2c1_platform_data = { | ||
70 | .bus_clk_rate = 400000. | ||
71 | }; | ||
72 | |||
73 | static struct tegra_i2c_platform_data seaboard_i2c2_platform_data = { | ||
74 | .bus_clk_rate = 400000, | ||
75 | }; | ||
76 | |||
77 | static struct tegra_i2c_platform_data seaboard_i2c3_platform_data = { | ||
78 | .bus_clk_rate = 400000, | ||
79 | }; | ||
80 | |||
81 | static struct tegra_i2c_platform_data seaboard_dvc_platform_data = { | ||
82 | .bus_clk_rate = 400000, | ||
83 | }; | ||
84 | |||
85 | static struct gpio_keys_button seaboard_gpio_keys_buttons[] = { | 68 | static struct gpio_keys_button seaboard_gpio_keys_buttons[] = { |
86 | { | 69 | { |
87 | .code = SW_LID, | 70 | .code = SW_LID, |
@@ -137,9 +120,9 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = { | |||
137 | static struct platform_device *seaboard_devices[] __initdata = { | 120 | static struct platform_device *seaboard_devices[] __initdata = { |
138 | &debug_uart, | 121 | &debug_uart, |
139 | &tegra_pmu_device, | 122 | &tegra_pmu_device, |
140 | &tegra_sdhci_device1, | ||
141 | &tegra_sdhci_device3, | ||
142 | &tegra_sdhci_device4, | 123 | &tegra_sdhci_device4, |
124 | &tegra_sdhci_device3, | ||
125 | &tegra_sdhci_device1, | ||
143 | &seaboard_gpio_keys_device, | 126 | &seaboard_gpio_keys_device, |
144 | }; | 127 | }; |
145 | 128 | ||
@@ -161,11 +144,6 @@ static void __init seaboard_i2c_init(void) | |||
161 | 144 | ||
162 | i2c_register_board_info(3, &adt7461_device, 1); | 145 | i2c_register_board_info(3, &adt7461_device, 1); |
163 | 146 | ||
164 | tegra_i2c_device1.dev.platform_data = &seaboard_i2c1_platform_data; | ||
165 | tegra_i2c_device2.dev.platform_data = &seaboard_i2c2_platform_data; | ||
166 | tegra_i2c_device3.dev.platform_data = &seaboard_i2c3_platform_data; | ||
167 | tegra_i2c_device4.dev.platform_data = &seaboard_dvc_platform_data; | ||
168 | |||
169 | platform_device_register(&tegra_i2c_device1); | 147 | platform_device_register(&tegra_i2c_device1); |
170 | platform_device_register(&tegra_i2c_device2); | 148 | platform_device_register(&tegra_i2c_device2); |
171 | platform_device_register(&tegra_i2c_device3); | 149 | platform_device_register(&tegra_i2c_device3); |
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c index d9dc5d297edd..47c596cdbf32 100644 --- a/arch/arm/mach-tegra/board-trimslice-pinmux.c +++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c | |||
@@ -29,7 +29,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { | |||
29 | {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | 29 | {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, |
30 | {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | 30 | {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, |
31 | {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | 31 | {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, |
32 | {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, | 32 | {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, |
33 | {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, | 33 | {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, |
34 | {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | 34 | {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, |
35 | {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, | 35 | {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, |
@@ -126,7 +126,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { | |||
126 | {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | 126 | {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, |
127 | {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | 127 | {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, |
128 | {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | 128 | {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, |
129 | {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, | 129 | {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, |
130 | {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | 130 | {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, |
131 | {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | 131 | {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, |
132 | {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, | 132 | {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, |
@@ -145,6 +145,9 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = { | |||
145 | static struct tegra_gpio_table gpio_table[] = { | 145 | static struct tegra_gpio_table gpio_table[] = { |
146 | { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ | 146 | { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ |
147 | { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ | 147 | { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ |
148 | |||
149 | { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */ | ||
150 | { .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */ | ||
148 | }; | 151 | }; |
149 | 152 | ||
150 | void __init trimslice_pinmux_init(void) | 153 | void __init trimslice_pinmux_init(void) |
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index cda4cfd78e84..89a6d2adc1de 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c | |||
@@ -23,6 +23,8 @@ | |||
23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
24 | #include <linux/serial_8250.h> | 24 | #include <linux/serial_8250.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | #include <linux/i2c.h> | ||
27 | #include <linux/gpio.h> | ||
26 | 28 | ||
27 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
28 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
@@ -30,6 +32,7 @@ | |||
30 | 32 | ||
31 | #include <mach/iomap.h> | 33 | #include <mach/iomap.h> |
32 | #include <mach/sdhci.h> | 34 | #include <mach/sdhci.h> |
35 | #include <mach/gpio.h> | ||
33 | 36 | ||
34 | #include "board.h" | 37 | #include "board.h" |
35 | #include "clock.h" | 38 | #include "clock.h" |
@@ -71,12 +74,58 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = { | |||
71 | .power_gpio = -1, | 74 | .power_gpio = -1, |
72 | }; | 75 | }; |
73 | 76 | ||
77 | static struct platform_device trimslice_audio_device = { | ||
78 | .name = "tegra-snd-trimslice", | ||
79 | .id = 0, | ||
80 | }; | ||
81 | |||
74 | static struct platform_device *trimslice_devices[] __initdata = { | 82 | static struct platform_device *trimslice_devices[] __initdata = { |
75 | &debug_uart, | 83 | &debug_uart, |
76 | &tegra_sdhci_device1, | 84 | &tegra_sdhci_device1, |
77 | &tegra_sdhci_device4, | 85 | &tegra_sdhci_device4, |
86 | &tegra_i2s_device1, | ||
87 | &tegra_das_device, | ||
88 | &tegra_pcm_device, | ||
89 | &trimslice_audio_device, | ||
78 | }; | 90 | }; |
79 | 91 | ||
92 | static struct i2c_board_info trimslice_i2c3_board_info[] = { | ||
93 | { | ||
94 | I2C_BOARD_INFO("tlv320aic23", 0x1a), | ||
95 | }, | ||
96 | { | ||
97 | I2C_BOARD_INFO("em3027", 0x56), | ||
98 | }, | ||
99 | }; | ||
100 | |||
101 | static void trimslice_i2c_init(void) | ||
102 | { | ||
103 | platform_device_register(&tegra_i2c_device1); | ||
104 | platform_device_register(&tegra_i2c_device2); | ||
105 | platform_device_register(&tegra_i2c_device3); | ||
106 | |||
107 | i2c_register_board_info(2, trimslice_i2c3_board_info, | ||
108 | ARRAY_SIZE(trimslice_i2c3_board_info)); | ||
109 | } | ||
110 | |||
111 | static void trimslice_usb_init(void) | ||
112 | { | ||
113 | int err; | ||
114 | |||
115 | platform_device_register(&tegra_ehci3_device); | ||
116 | |||
117 | platform_device_register(&tegra_ehci2_device); | ||
118 | |||
119 | err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH, | ||
120 | "usb1mode"); | ||
121 | if (err) { | ||
122 | pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err); | ||
123 | return; | ||
124 | } | ||
125 | |||
126 | platform_device_register(&tegra_ehci1_device); | ||
127 | } | ||
128 | |||
80 | static void __init tegra_trimslice_fixup(struct machine_desc *desc, | 129 | static void __init tegra_trimslice_fixup(struct machine_desc *desc, |
81 | struct tag *tags, char **cmdline, struct meminfo *mi) | 130 | struct tag *tags, char **cmdline, struct meminfo *mi) |
82 | { | 131 | { |
@@ -90,6 +139,10 @@ static void __init tegra_trimslice_fixup(struct machine_desc *desc, | |||
90 | static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = { | 139 | static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = { |
91 | /* name parent rate enabled */ | 140 | /* name parent rate enabled */ |
92 | { "uarta", "pll_p", 216000000, true }, | 141 | { "uarta", "pll_p", 216000000, true }, |
142 | { "pll_a", "pll_p_out1", 56448000, true }, | ||
143 | { "pll_a_out0", "pll_a", 11289600, true }, | ||
144 | { "cdev1", NULL, 0, true }, | ||
145 | { "i2s1", "pll_a_out0", 11289600, false}, | ||
93 | { NULL, NULL, 0, 0}, | 146 | { NULL, NULL, 0, 0}, |
94 | }; | 147 | }; |
95 | 148 | ||
@@ -112,6 +165,9 @@ static void __init tegra_trimslice_init(void) | |||
112 | tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; | 165 | tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; |
113 | 166 | ||
114 | platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices)); | 167 | platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices)); |
168 | |||
169 | trimslice_i2c_init(); | ||
170 | trimslice_usb_init(); | ||
115 | } | 171 | } |
116 | 172 | ||
117 | MACHINE_START(TRIMSLICE, "trimslice") | 173 | MACHINE_START(TRIMSLICE, "trimslice") |
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h index e8ef6291c6f1..7a7dee86b4da 100644 --- a/arch/arm/mach-tegra/board-trimslice.h +++ b/arch/arm/mach-tegra/board-trimslice.h | |||
@@ -20,6 +20,9 @@ | |||
20 | #define TRIMSLICE_GPIO_SD4_CD TEGRA_GPIO_PP1 /* mmc4 cd */ | 20 | #define TRIMSLICE_GPIO_SD4_CD TEGRA_GPIO_PP1 /* mmc4 cd */ |
21 | #define TRIMSLICE_GPIO_SD4_WP TEGRA_GPIO_PP2 /* mmc4 wp */ | 21 | #define TRIMSLICE_GPIO_SD4_WP TEGRA_GPIO_PP2 /* mmc4 wp */ |
22 | 22 | ||
23 | #define TRIMSLICE_GPIO_USB1_MODE TEGRA_GPIO_PV2 /* USB1 mode */ | ||
24 | #define TRIMSLICE_GPIO_USB2_RST TEGRA_GPIO_PV0 /* USB2 PHY reset */ | ||
25 | |||
23 | void trimslice_pinmux_init(void); | 26 | void trimslice_pinmux_init(void); |
24 | 27 | ||
25 | #endif | 28 | #endif |
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index 1528f9daef1f..57e35d20c24c 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c | |||
@@ -22,10 +22,14 @@ | |||
22 | #include <linux/dma-mapping.h> | 22 | #include <linux/dma-mapping.h> |
23 | #include <linux/fsl_devices.h> | 23 | #include <linux/fsl_devices.h> |
24 | #include <linux/serial_8250.h> | 24 | #include <linux/serial_8250.h> |
25 | #include <linux/i2c-tegra.h> | ||
26 | #include <linux/platform_data/tegra_usb.h> | ||
25 | #include <asm/pmu.h> | 27 | #include <asm/pmu.h> |
26 | #include <mach/irqs.h> | 28 | #include <mach/irqs.h> |
27 | #include <mach/iomap.h> | 29 | #include <mach/iomap.h> |
28 | #include <mach/dma.h> | 30 | #include <mach/dma.h> |
31 | #include <mach/usb_phy.h> | ||
32 | #include "gpio-names.h" | ||
29 | 33 | ||
30 | static struct resource i2c_resource1[] = { | 34 | static struct resource i2c_resource1[] = { |
31 | [0] = { | 35 | [0] = { |
@@ -79,13 +83,29 @@ static struct resource i2c_resource4[] = { | |||
79 | }, | 83 | }, |
80 | }; | 84 | }; |
81 | 85 | ||
86 | static struct tegra_i2c_platform_data tegra_i2c1_platform_data = { | ||
87 | .bus_clk_rate = 400000, | ||
88 | }; | ||
89 | |||
90 | static struct tegra_i2c_platform_data tegra_i2c2_platform_data = { | ||
91 | .bus_clk_rate = 400000, | ||
92 | }; | ||
93 | |||
94 | static struct tegra_i2c_platform_data tegra_i2c3_platform_data = { | ||
95 | .bus_clk_rate = 400000, | ||
96 | }; | ||
97 | |||
98 | static struct tegra_i2c_platform_data tegra_dvc_platform_data = { | ||
99 | .bus_clk_rate = 400000, | ||
100 | }; | ||
101 | |||
82 | struct platform_device tegra_i2c_device1 = { | 102 | struct platform_device tegra_i2c_device1 = { |
83 | .name = "tegra-i2c", | 103 | .name = "tegra-i2c", |
84 | .id = 0, | 104 | .id = 0, |
85 | .resource = i2c_resource1, | 105 | .resource = i2c_resource1, |
86 | .num_resources = ARRAY_SIZE(i2c_resource1), | 106 | .num_resources = ARRAY_SIZE(i2c_resource1), |
87 | .dev = { | 107 | .dev = { |
88 | .platform_data = 0, | 108 | .platform_data = &tegra_i2c1_platform_data, |
89 | }, | 109 | }, |
90 | }; | 110 | }; |
91 | 111 | ||
@@ -95,7 +115,7 @@ struct platform_device tegra_i2c_device2 = { | |||
95 | .resource = i2c_resource2, | 115 | .resource = i2c_resource2, |
96 | .num_resources = ARRAY_SIZE(i2c_resource2), | 116 | .num_resources = ARRAY_SIZE(i2c_resource2), |
97 | .dev = { | 117 | .dev = { |
98 | .platform_data = 0, | 118 | .platform_data = &tegra_i2c2_platform_data, |
99 | }, | 119 | }, |
100 | }; | 120 | }; |
101 | 121 | ||
@@ -105,7 +125,7 @@ struct platform_device tegra_i2c_device3 = { | |||
105 | .resource = i2c_resource3, | 125 | .resource = i2c_resource3, |
106 | .num_resources = ARRAY_SIZE(i2c_resource3), | 126 | .num_resources = ARRAY_SIZE(i2c_resource3), |
107 | .dev = { | 127 | .dev = { |
108 | .platform_data = 0, | 128 | .platform_data = &tegra_i2c3_platform_data, |
109 | }, | 129 | }, |
110 | }; | 130 | }; |
111 | 131 | ||
@@ -115,7 +135,7 @@ struct platform_device tegra_i2c_device4 = { | |||
115 | .resource = i2c_resource4, | 135 | .resource = i2c_resource4, |
116 | .num_resources = ARRAY_SIZE(i2c_resource4), | 136 | .num_resources = ARRAY_SIZE(i2c_resource4), |
117 | .dev = { | 137 | .dev = { |
118 | .platform_data = 0, | 138 | .platform_data = &tegra_dvc_platform_data, |
119 | }, | 139 | }, |
120 | }; | 140 | }; |
121 | 141 | ||
@@ -334,6 +354,28 @@ static struct resource tegra_usb3_resources[] = { | |||
334 | }, | 354 | }, |
335 | }; | 355 | }; |
336 | 356 | ||
357 | static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { | ||
358 | /* All existing boards use GPIO PV0 for phy reset */ | ||
359 | .reset_gpio = TEGRA_GPIO_PV0, | ||
360 | .clk = "cdev2", | ||
361 | }; | ||
362 | |||
363 | static struct tegra_ehci_platform_data tegra_ehci1_pdata = { | ||
364 | .operating_mode = TEGRA_USB_OTG, | ||
365 | .power_down_on_bus_suspend = 1, | ||
366 | }; | ||
367 | |||
368 | static struct tegra_ehci_platform_data tegra_ehci2_pdata = { | ||
369 | .phy_config = &tegra_ehci2_ulpi_phy_config, | ||
370 | .operating_mode = TEGRA_USB_HOST, | ||
371 | .power_down_on_bus_suspend = 1, | ||
372 | }; | ||
373 | |||
374 | static struct tegra_ehci_platform_data tegra_ehci3_pdata = { | ||
375 | .operating_mode = TEGRA_USB_HOST, | ||
376 | .power_down_on_bus_suspend = 1, | ||
377 | }; | ||
378 | |||
337 | static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); | 379 | static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); |
338 | 380 | ||
339 | struct platform_device tegra_ehci1_device = { | 381 | struct platform_device tegra_ehci1_device = { |
@@ -342,6 +384,7 @@ struct platform_device tegra_ehci1_device = { | |||
342 | .dev = { | 384 | .dev = { |
343 | .dma_mask = &tegra_ehci_dmamask, | 385 | .dma_mask = &tegra_ehci_dmamask, |
344 | .coherent_dma_mask = DMA_BIT_MASK(32), | 386 | .coherent_dma_mask = DMA_BIT_MASK(32), |
387 | .platform_data = &tegra_ehci1_pdata, | ||
345 | }, | 388 | }, |
346 | .resource = tegra_usb1_resources, | 389 | .resource = tegra_usb1_resources, |
347 | .num_resources = ARRAY_SIZE(tegra_usb1_resources), | 390 | .num_resources = ARRAY_SIZE(tegra_usb1_resources), |
@@ -353,6 +396,7 @@ struct platform_device tegra_ehci2_device = { | |||
353 | .dev = { | 396 | .dev = { |
354 | .dma_mask = &tegra_ehci_dmamask, | 397 | .dma_mask = &tegra_ehci_dmamask, |
355 | .coherent_dma_mask = DMA_BIT_MASK(32), | 398 | .coherent_dma_mask = DMA_BIT_MASK(32), |
399 | .platform_data = &tegra_ehci2_pdata, | ||
356 | }, | 400 | }, |
357 | .resource = tegra_usb2_resources, | 401 | .resource = tegra_usb2_resources, |
358 | .num_resources = ARRAY_SIZE(tegra_usb2_resources), | 402 | .num_resources = ARRAY_SIZE(tegra_usb2_resources), |
@@ -364,6 +408,7 @@ struct platform_device tegra_ehci3_device = { | |||
364 | .dev = { | 408 | .dev = { |
365 | .dma_mask = &tegra_ehci_dmamask, | 409 | .dma_mask = &tegra_ehci_dmamask, |
366 | .coherent_dma_mask = DMA_BIT_MASK(32), | 410 | .coherent_dma_mask = DMA_BIT_MASK(32), |
411 | .platform_data = &tegra_ehci3_pdata, | ||
367 | }, | 412 | }, |
368 | .resource = tegra_usb3_resources, | 413 | .resource = tegra_usb3_resources, |
369 | .num_resources = ARRAY_SIZE(tegra_usb3_resources), | 414 | .num_resources = ARRAY_SIZE(tegra_usb3_resources), |
diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h deleted file mode 100644 index 425b42e91ef6..000000000000 --- a/arch/arm/mach-tegra/include/mach/barriers.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-realview/include/mach/barriers.h | ||
3 | * | ||
4 | * Copyright (C) 2010 ARM Ltd. | ||
5 | * Written by Catalin Marinas <catalin.marinas@arm.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #ifndef __MACH_BARRIERS_H | ||
22 | #define __MACH_BARRIERS_H | ||
23 | |||
24 | #include <asm/outercache.h> | ||
25 | |||
26 | #define rmb() dsb() | ||
27 | #define wmb() do { dsb(); outer_sync(); } while (0) | ||
28 | #define mb() wmb() | ||
29 | |||
30 | #endif /* __MACH_BARRIERS_H */ | ||
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 32ca6267b9ff..0886cbccddee 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
@@ -121,7 +121,7 @@ void __init smp_init_cpus(void) | |||
121 | } | 121 | } |
122 | 122 | ||
123 | for (i = 0; i < ncores; i++) | 123 | for (i = 0; i < ncores; i++) |
124 | cpu_set(i, cpu_possible_map); | 124 | set_cpu_possible(i, true); |
125 | 125 | ||
126 | set_smp_cross_call(gic_raise_softirq); | 126 | set_smp_cross_call(gic_raise_softirq); |
127 | } | 127 | } |
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index bb618075fab6..0fe9b3ee2947 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c | |||
@@ -2182,8 +2182,8 @@ struct clk tegra_list_clks[] = { | |||
2182 | PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ | 2182 | PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ |
2183 | PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ | 2183 | PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ |
2184 | PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ | 2184 | PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ |
2185 | PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ | 2185 | PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */ |
2186 | PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ | 2186 | PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */ |
2187 | PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | 2187 | PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ |
2188 | PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | 2188 | PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ |
2189 | PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | 2189 | PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ |
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index 5767208f1c1d..7b597e2b19e2 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c | |||
@@ -40,8 +40,8 @@ struct pl022_config_chip dummy_chip_info = { | |||
40 | .hierarchy = SSP_MASTER, | 40 | .hierarchy = SSP_MASTER, |
41 | /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ | 41 | /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ |
42 | .slave_tx_disable = 0, | 42 | .slave_tx_disable = 0, |
43 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | 43 | .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, |
44 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | 44 | .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, |
45 | .ctrl_len = SSP_BITS_12, | 45 | .ctrl_len = SSP_BITS_12, |
46 | .wait_state = SSP_MWIRE_WAIT_ZERO, | 46 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
47 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | 47 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 18d7fa0603c2..5f51bdeef0ef 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c | |||
@@ -27,9 +27,6 @@ | |||
27 | #include <asm/mach/time.h> | 27 | #include <asm/mach/time.h> |
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | 29 | ||
30 | /* Be able to sleep for atleast 4 seconds (usually more) */ | ||
31 | #define APPTIMER_MIN_RANGE 4 | ||
32 | |||
33 | /* | 30 | /* |
34 | * APP side special timer registers | 31 | * APP side special timer registers |
35 | * This timer contains four timers which can fire an interrupt each. | 32 | * This timer contains four timers which can fire an interrupt each. |
@@ -309,11 +306,11 @@ static int u300_set_next_event(unsigned long cycles, | |||
309 | 306 | ||
310 | /* Use general purpose timer 1 as clock event */ | 307 | /* Use general purpose timer 1 as clock event */ |
311 | static struct clock_event_device clockevent_u300_1mhz = { | 308 | static struct clock_event_device clockevent_u300_1mhz = { |
312 | .name = "GPT1", | 309 | .name = "GPT1", |
313 | .rating = 300, /* Reasonably fast and accurate clock event */ | 310 | .rating = 300, /* Reasonably fast and accurate clock event */ |
314 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | 311 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
315 | .set_next_event = u300_set_next_event, | 312 | .set_next_event = u300_set_next_event, |
316 | .set_mode = u300_set_mode, | 313 | .set_mode = u300_set_mode, |
317 | }; | 314 | }; |
318 | 315 | ||
319 | /* Clock event timer interrupt handler */ | 316 | /* Clock event timer interrupt handler */ |
@@ -328,9 +325,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) | |||
328 | } | 325 | } |
329 | 326 | ||
330 | static struct irqaction u300_timer_irq = { | 327 | static struct irqaction u300_timer_irq = { |
331 | .name = "U300 Timer Tick", | 328 | .name = "U300 Timer Tick", |
332 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 329 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
333 | .handler = u300_timer_interrupt, | 330 | .handler = u300_timer_interrupt, |
334 | }; | 331 | }; |
335 | 332 | ||
336 | /* | 333 | /* |
@@ -413,16 +410,10 @@ static void __init u300_timer_init(void) | |||
413 | "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) | 410 | "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) |
414 | pr_err("timer: failed to initialize U300 clock source\n"); | 411 | pr_err("timer: failed to initialize U300 clock source\n"); |
415 | 412 | ||
416 | clockevents_calc_mult_shift(&clockevent_u300_1mhz, | 413 | /* Configure and register the clockevent */ |
417 | rate, APPTIMER_MIN_RANGE); | 414 | clockevents_config_and_register(&clockevent_u300_1mhz, rate, |
418 | /* 32bit counter, so 32bits delta is max */ | 415 | 1, 0xffffffff); |
419 | clockevent_u300_1mhz.max_delta_ns = | 416 | |
420 | clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz); | ||
421 | /* This timer is slow enough to set for 1 cycle == 1 MHz */ | ||
422 | clockevent_u300_1mhz.min_delta_ns = | ||
423 | clockevent_delta2ns(1, &clockevent_u300_1mhz); | ||
424 | clockevent_u300_1mhz.cpumask = cpumask_of(0); | ||
425 | clockevents_register_device(&clockevent_u300_1mhz); | ||
426 | /* | 417 | /* |
427 | * TODO: init and register the rest of the timers too, they can be | 418 | * TODO: init and register the rest of the timers too, they can be |
428 | * used by hrtimers! | 419 | * used by hrtimers! |
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index f8b9392ee347..4210cb434dbc 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig | |||
@@ -20,7 +20,7 @@ config UX500_SOC_DB8500 | |||
20 | 20 | ||
21 | endmenu | 21 | endmenu |
22 | 22 | ||
23 | menu "Ux500 target platform" | 23 | menu "Ux500 target platform (boards)" |
24 | 24 | ||
25 | config MACH_U8500 | 25 | config MACH_U8500 |
26 | bool "U8500 Development platform" | 26 | bool "U8500 Development platform" |
@@ -29,6 +29,19 @@ config MACH_U8500 | |||
29 | help | 29 | help |
30 | Include support for the mop500 development platform. | 30 | Include support for the mop500 development platform. |
31 | 31 | ||
32 | config MACH_HREFV60 | ||
33 | bool "U85000 Development platform, HREFv60 version" | ||
34 | depends on UX500_SOC_DB8500 | ||
35 | help | ||
36 | Include support for the HREFv60 new development platform. | ||
37 | |||
38 | config MACH_SNOWBALL | ||
39 | bool "U8500 Snowball platform" | ||
40 | depends on UX500_SOC_DB8500 | ||
41 | select MACH_U8500 | ||
42 | help | ||
43 | Include support for the snowball development platform. | ||
44 | |||
32 | config MACH_U5500 | 45 | config MACH_U5500 |
33 | bool "U5500 Development platform" | 46 | bool "U5500 Development platform" |
34 | depends on UX500_SOC_DB5500 | 47 | depends on UX500_SOC_DB5500 |
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 70cdbd60596a..f26fd76f72b4 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c | |||
@@ -236,6 +236,46 @@ static pin_cfg_t mop500_pins_hrefv60[] = { | |||
236 | 236 | ||
237 | }; | 237 | }; |
238 | 238 | ||
239 | static pin_cfg_t snowball_pins[] = { | ||
240 | /* SSP0, to AB8500 */ | ||
241 | GPIO143_SSP0_CLK, | ||
242 | GPIO144_SSP0_FRM, | ||
243 | GPIO145_SSP0_RXD | PIN_PULL_DOWN, | ||
244 | GPIO146_SSP0_TXD, | ||
245 | |||
246 | /* MMC0: MicroSD card */ | ||
247 | GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, | ||
248 | |||
249 | /* MMC2: LAN */ | ||
250 | GPIO86_SM_ADQ0, | ||
251 | GPIO87_SM_ADQ1, | ||
252 | GPIO88_SM_ADQ2, | ||
253 | GPIO89_SM_ADQ3, | ||
254 | GPIO90_SM_ADQ4, | ||
255 | GPIO91_SM_ADQ5, | ||
256 | GPIO92_SM_ADQ6, | ||
257 | GPIO93_SM_ADQ7, | ||
258 | |||
259 | GPIO94_SM_ADVn, | ||
260 | GPIO95_SM_CS0n, | ||
261 | GPIO96_SM_OEn, | ||
262 | GPIO97_SM_WEn, | ||
263 | |||
264 | GPIO128_SM_CKO, | ||
265 | GPIO130_SM_FBCLK, | ||
266 | GPIO131_SM_ADQ8, | ||
267 | GPIO132_SM_ADQ9, | ||
268 | GPIO133_SM_ADQ10, | ||
269 | GPIO134_SM_ADQ11, | ||
270 | GPIO135_SM_ADQ12, | ||
271 | GPIO136_SM_ADQ13, | ||
272 | GPIO137_SM_ADQ14, | ||
273 | GPIO138_SM_ADQ15, | ||
274 | |||
275 | /* RSTn_LAN */ | ||
276 | GPIO141_GPIO | PIN_OUTPUT_HIGH, | ||
277 | }; | ||
278 | |||
239 | void __init mop500_pins_init(void) | 279 | void __init mop500_pins_init(void) |
240 | { | 280 | { |
241 | nmk_config_pins(mop500_pins_common, | 281 | nmk_config_pins(mop500_pins_common, |
@@ -243,6 +283,9 @@ void __init mop500_pins_init(void) | |||
243 | if (machine_is_hrefv60()) | 283 | if (machine_is_hrefv60()) |
244 | nmk_config_pins(mop500_pins_hrefv60, | 284 | nmk_config_pins(mop500_pins_hrefv60, |
245 | ARRAY_SIZE(mop500_pins_hrefv60)); | 285 | ARRAY_SIZE(mop500_pins_hrefv60)); |
286 | else if (machine_is_snowball()) | ||
287 | nmk_config_pins(snowball_pins, | ||
288 | ARRAY_SIZE(snowball_pins)); | ||
246 | else | 289 | else |
247 | nmk_config_pins(mop500_pins_default, | 290 | nmk_config_pins(mop500_pins_default, |
248 | ARRAY_SIZE(mop500_pins_default)); | 291 | ARRAY_SIZE(mop500_pins_default)); |
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 0f2e522f387d..2735d03996cf 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c | |||
@@ -272,7 +272,14 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { | |||
272 | .max_uV = 2900000, | 272 | .max_uV = 2900000, |
273 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | 273 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
274 | REGULATOR_CHANGE_STATUS, | 274 | REGULATOR_CHANGE_STATUS, |
275 | .boot_on = 1, /* must be on for display */ | 275 | .boot_on = 1, /* display is on at boot */ |
276 | /* | ||
277 | * This voltage cannot be disabled right now because | ||
278 | * it is somehow affecting the external MMC | ||
279 | * functionality, though that typically will use | ||
280 | * AUX3. | ||
281 | */ | ||
282 | .always_on = 1, | ||
276 | }, | 283 | }, |
277 | .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), | 284 | .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), |
278 | .consumer_supplies = ab8500_vaux1_consumers, | 285 | .consumer_supplies = ab8500_vaux1_consumers, |
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 7c6cb4fa47a9..d0cb9e5eb87c 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c | |||
@@ -32,13 +32,32 @@ | |||
32 | #define MCI_DATA31DIREN (1 << 5) | 32 | #define MCI_DATA31DIREN (1 << 5) |
33 | #define MCI_FBCLKEN (1 << 7) | 33 | #define MCI_FBCLKEN (1 << 7) |
34 | 34 | ||
35 | /* GPIO pins used by the sdi0 level shifter */ | ||
36 | static int sdi0_en = -1; | ||
37 | static int sdi0_vsel = -1; | ||
38 | |||
35 | static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd, | 39 | static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd, |
36 | unsigned char power_mode) | 40 | unsigned char power_mode) |
37 | { | 41 | { |
38 | if (power_mode == MMC_POWER_UP) | 42 | switch (power_mode) { |
39 | gpio_set_value_cansleep(GPIO_SDMMC_EN, 1); | 43 | case MMC_POWER_UP: |
40 | else if (power_mode == MMC_POWER_OFF) | 44 | case MMC_POWER_ON: |
41 | gpio_set_value_cansleep(GPIO_SDMMC_EN, 0); | 45 | /* |
46 | * Level shifter voltage should depend on vdd to when deciding | ||
47 | * on either 1.8V or 2.9V. Once the decision has been made the | ||
48 | * level shifter must be disabled and re-enabled with a changed | ||
49 | * select signal in order to switch the voltage. Since there is | ||
50 | * no framework support yet for indicating 1.8V in vdd, use the | ||
51 | * default 2.9V. | ||
52 | */ | ||
53 | gpio_direction_output(sdi0_vsel, 0); | ||
54 | gpio_direction_output(sdi0_en, 1); | ||
55 | break; | ||
56 | case MMC_POWER_OFF: | ||
57 | gpio_direction_output(sdi0_vsel, 0); | ||
58 | gpio_direction_output(sdi0_en, 0); | ||
59 | break; | ||
60 | } | ||
42 | 61 | ||
43 | return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN | | 62 | return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN | |
44 | MCI_DATA2DIREN | MCI_DATA31DIREN; | 63 | MCI_DATA2DIREN | MCI_DATA31DIREN; |
@@ -67,8 +86,10 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { | |||
67 | static struct mmci_platform_data mop500_sdi0_data = { | 86 | static struct mmci_platform_data mop500_sdi0_data = { |
68 | .vdd_handler = mop500_sdi0_vdd_handler, | 87 | .vdd_handler = mop500_sdi0_vdd_handler, |
69 | .ocr_mask = MMC_VDD_29_30, | 88 | .ocr_mask = MMC_VDD_29_30, |
70 | .f_max = 100000000, | 89 | .f_max = 50000000, |
71 | .capabilities = MMC_CAP_4_BIT_DATA, | 90 | .capabilities = MMC_CAP_4_BIT_DATA | |
91 | MMC_CAP_SD_HIGHSPEED | | ||
92 | MMC_CAP_MMC_HIGHSPEED, | ||
72 | .gpio_wp = -1, | 93 | .gpio_wp = -1, |
73 | #ifdef CONFIG_STE_DMA40 | 94 | #ifdef CONFIG_STE_DMA40 |
74 | .dma_filter = stedma40_filter, | 95 | .dma_filter = stedma40_filter, |
@@ -77,10 +98,6 @@ static struct mmci_platform_data mop500_sdi0_data = { | |||
77 | #endif | 98 | #endif |
78 | }; | 99 | }; |
79 | 100 | ||
80 | /* GPIO pins used by the sdi0 level shifter */ | ||
81 | static int sdi0_en = -1; | ||
82 | static int sdi0_vsel = -1; | ||
83 | |||
84 | static void sdi0_configure(void) | 101 | static void sdi0_configure(void) |
85 | { | 102 | { |
86 | int ret; | 103 | int ret; |
@@ -140,7 +157,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { | |||
140 | 157 | ||
141 | static struct mmci_platform_data mop500_sdi2_data = { | 158 | static struct mmci_platform_data mop500_sdi2_data = { |
142 | .ocr_mask = MMC_VDD_165_195, | 159 | .ocr_mask = MMC_VDD_165_195, |
143 | .f_max = 100000000, | 160 | .f_max = 50000000, |
144 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, | 161 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
145 | .gpio_cd = -1, | 162 | .gpio_cd = -1, |
146 | .gpio_wp = -1, | 163 | .gpio_wp = -1, |
@@ -177,7 +194,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { | |||
177 | 194 | ||
178 | static struct mmci_platform_data mop500_sdi4_data = { | 195 | static struct mmci_platform_data mop500_sdi4_data = { |
179 | .ocr_mask = MMC_VDD_29_30, | 196 | .ocr_mask = MMC_VDD_29_30, |
180 | .f_max = 100000000, | 197 | .f_max = 50000000, |
181 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | | 198 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | |
182 | MMC_CAP_MMC_HIGHSPEED, | 199 | MMC_CAP_MMC_HIGHSPEED, |
183 | .gpio_cd = -1, | 200 | .gpio_cd = -1, |
@@ -199,17 +216,27 @@ void __init mop500_sdi_init(void) | |||
199 | /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */ | 216 | /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */ |
200 | if (!cpu_is_u8500v10()) | 217 | if (!cpu_is_u8500v10()) |
201 | mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; | 218 | mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; |
202 | db8500_add_sdi2(&mop500_sdi2_data, periphid); | 219 | /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */ |
220 | if (!machine_is_snowball()) | ||
221 | db8500_add_sdi2(&mop500_sdi2_data, periphid); | ||
203 | 222 | ||
204 | /* On-board eMMC */ | 223 | /* On-board eMMC */ |
205 | db8500_add_sdi4(&mop500_sdi4_data, periphid); | 224 | db8500_add_sdi4(&mop500_sdi4_data, periphid); |
206 | 225 | ||
207 | if (machine_is_hrefv60()) { | 226 | if (machine_is_hrefv60() || machine_is_snowball()) { |
208 | mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; | 227 | if (machine_is_hrefv60()) { |
209 | sdi0_en = HREFV60_SDMMC_EN_GPIO; | 228 | mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; |
210 | sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; | 229 | sdi0_en = HREFV60_SDMMC_EN_GPIO; |
230 | sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; | ||
231 | } else if (machine_is_snowball()) { | ||
232 | mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; | ||
233 | mop500_sdi0_data.cd_invert = true; | ||
234 | sdi0_en = SNOWBALL_SDMMC_EN_GPIO; | ||
235 | sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; | ||
236 | } | ||
211 | sdi0_configure(); | 237 | sdi0_configure(); |
212 | } | 238 | } |
239 | |||
213 | /* | 240 | /* |
214 | * On boards with the TC35892 GPIO expander, sdi0 will finally | 241 | * On boards with the TC35892 GPIO expander, sdi0 will finally |
215 | * be added when the TC35892 initializes and calls | 242 | * be added when the TC35892 initializes and calls |
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c index 69cce41f602a..5af36aa56c08 100644 --- a/arch/arm/mach-ux500/board-mop500-uib.c +++ b/arch/arm/mach-ux500/board-mop500-uib.c | |||
@@ -25,7 +25,7 @@ struct uib { | |||
25 | void (*init)(void); | 25 | void (*init)(void); |
26 | }; | 26 | }; |
27 | 27 | ||
28 | static struct __initdata uib mop500_uibs[] = { | 28 | static struct uib __initdata mop500_uibs[] = { |
29 | [STUIB] = { | 29 | [STUIB] = { |
30 | .name = "ST-UIB", | 30 | .name = "ST-UIB", |
31 | .option = "stuib", | 31 | .option = "stuib", |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 2a08c07dec6d..cd54abaccd96 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
@@ -26,9 +26,11 @@ | |||
26 | #include <linux/mfd/ab8500/gpio.h> | 26 | #include <linux/mfd/ab8500/gpio.h> |
27 | #include <linux/leds-lp5521.h> | 27 | #include <linux/leds-lp5521.h> |
28 | #include <linux/input.h> | 28 | #include <linux/input.h> |
29 | #include <linux/smsc911x.h> | ||
29 | #include <linux/gpio_keys.h> | 30 | #include <linux/gpio_keys.h> |
30 | #include <linux/delay.h> | 31 | #include <linux/delay.h> |
31 | 32 | ||
33 | #include <linux/leds.h> | ||
32 | #include <asm/mach-types.h> | 34 | #include <asm/mach-types.h> |
33 | #include <asm/mach/arch.h> | 35 | #include <asm/mach/arch.h> |
34 | 36 | ||
@@ -47,6 +49,26 @@ | |||
47 | #include "board-mop500.h" | 49 | #include "board-mop500.h" |
48 | #include "board-mop500-regulators.h" | 50 | #include "board-mop500-regulators.h" |
49 | 51 | ||
52 | static struct gpio_led snowball_led_array[] = { | ||
53 | { | ||
54 | .name = "user_led", | ||
55 | .default_trigger = "none", | ||
56 | .gpio = 142, | ||
57 | }, | ||
58 | }; | ||
59 | |||
60 | static struct gpio_led_platform_data snowball_led_data = { | ||
61 | .leds = snowball_led_array, | ||
62 | .num_leds = ARRAY_SIZE(snowball_led_array), | ||
63 | }; | ||
64 | |||
65 | static struct platform_device snowball_led_dev = { | ||
66 | .name = "leds-gpio", | ||
67 | .dev = { | ||
68 | .platform_data = &snowball_led_data, | ||
69 | }, | ||
70 | }; | ||
71 | |||
50 | static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { | 72 | static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { |
51 | .gpio_base = MOP500_AB8500_GPIO(0), | 73 | .gpio_base = MOP500_AB8500_GPIO(0), |
52 | .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, | 74 | .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, |
@@ -69,6 +91,97 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { | |||
69 | 0x7A, 0x00, 0x00}, | 91 | 0x7A, 0x00, 0x00}, |
70 | }; | 92 | }; |
71 | 93 | ||
94 | static struct gpio_keys_button snowball_key_array[] = { | ||
95 | { | ||
96 | .gpio = 32, | ||
97 | .type = EV_KEY, | ||
98 | .code = KEY_1, | ||
99 | .desc = "userpb", | ||
100 | .active_low = 1, | ||
101 | .debounce_interval = 50, | ||
102 | .wakeup = 1, | ||
103 | }, | ||
104 | { | ||
105 | .gpio = 151, | ||
106 | .type = EV_KEY, | ||
107 | .code = KEY_2, | ||
108 | .desc = "extkb1", | ||
109 | .active_low = 1, | ||
110 | .debounce_interval = 50, | ||
111 | .wakeup = 1, | ||
112 | }, | ||
113 | { | ||
114 | .gpio = 152, | ||
115 | .type = EV_KEY, | ||
116 | .code = KEY_3, | ||
117 | .desc = "extkb2", | ||
118 | .active_low = 1, | ||
119 | .debounce_interval = 50, | ||
120 | .wakeup = 1, | ||
121 | }, | ||
122 | { | ||
123 | .gpio = 161, | ||
124 | .type = EV_KEY, | ||
125 | .code = KEY_4, | ||
126 | .desc = "extkb3", | ||
127 | .active_low = 1, | ||
128 | .debounce_interval = 50, | ||
129 | .wakeup = 1, | ||
130 | }, | ||
131 | { | ||
132 | .gpio = 162, | ||
133 | .type = EV_KEY, | ||
134 | .code = KEY_5, | ||
135 | .desc = "extkb4", | ||
136 | .active_low = 1, | ||
137 | .debounce_interval = 50, | ||
138 | .wakeup = 1, | ||
139 | }, | ||
140 | }; | ||
141 | |||
142 | static struct gpio_keys_platform_data snowball_key_data = { | ||
143 | .buttons = snowball_key_array, | ||
144 | .nbuttons = ARRAY_SIZE(snowball_key_array), | ||
145 | }; | ||
146 | |||
147 | static struct platform_device snowball_key_dev = { | ||
148 | .name = "gpio-keys", | ||
149 | .id = -1, | ||
150 | .dev = { | ||
151 | .platform_data = &snowball_key_data, | ||
152 | } | ||
153 | }; | ||
154 | |||
155 | static struct smsc911x_platform_config snowball_sbnet_cfg = { | ||
156 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, | ||
157 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
158 | .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, | ||
159 | .shift = 1, | ||
160 | }; | ||
161 | |||
162 | static struct resource sbnet_res[] = { | ||
163 | { | ||
164 | .name = "smsc911x-memory", | ||
165 | .start = (0x5000 << 16), | ||
166 | .end = (0x5000 << 16) + 0xffff, | ||
167 | .flags = IORESOURCE_MEM, | ||
168 | }, | ||
169 | { | ||
170 | .start = NOMADIK_GPIO_TO_IRQ(140), | ||
171 | .end = NOMADIK_GPIO_TO_IRQ(140), | ||
172 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
173 | }, | ||
174 | }; | ||
175 | |||
176 | static struct platform_device snowball_sbnet_dev = { | ||
177 | .name = "smsc911x", | ||
178 | .num_resources = ARRAY_SIZE(sbnet_res), | ||
179 | .resource = sbnet_res, | ||
180 | .dev = { | ||
181 | .platform_data = &snowball_sbnet_cfg, | ||
182 | }, | ||
183 | }; | ||
184 | |||
72 | static struct ab8500_platform_data ab8500_platdata = { | 185 | static struct ab8500_platform_data ab8500_platdata = { |
73 | .irq_base = MOP500_AB8500_IRQ_BASE, | 186 | .irq_base = MOP500_AB8500_IRQ_BASE, |
74 | .regulator_reg_init = ab8500_regulator_reg_init, | 187 | .regulator_reg_init = ab8500_regulator_reg_init, |
@@ -295,8 +408,9 @@ static void mop500_prox_deactivate(struct device *dev) | |||
295 | } | 408 | } |
296 | 409 | ||
297 | /* add any platform devices here - TODO */ | 410 | /* add any platform devices here - TODO */ |
298 | static struct platform_device *platform_devs[] __initdata = { | 411 | static struct platform_device *mop500_platform_devs[] __initdata = { |
299 | &mop500_gpio_keys_device, | 412 | &mop500_gpio_keys_device, |
413 | &ab8500_device, | ||
300 | }; | 414 | }; |
301 | 415 | ||
302 | #ifdef CONFIG_STE_DMA40 | 416 | #ifdef CONFIG_STE_DMA40 |
@@ -478,6 +592,13 @@ static void __init mop500_uart_init(void) | |||
478 | db8500_add_uart2(&uart2_plat); | 592 | db8500_add_uart2(&uart2_plat); |
479 | } | 593 | } |
480 | 594 | ||
595 | static struct platform_device *snowball_platform_devs[] __initdata = { | ||
596 | &snowball_led_dev, | ||
597 | &snowball_key_dev, | ||
598 | &snowball_sbnet_dev, | ||
599 | &ab8500_device, | ||
600 | }; | ||
601 | |||
481 | static void __init mop500_init_machine(void) | 602 | static void __init mop500_init_machine(void) |
482 | { | 603 | { |
483 | int i2c0_devs; | 604 | int i2c0_devs; |
@@ -487,24 +608,29 @@ static void __init mop500_init_machine(void) | |||
487 | * all these GPIO pins to the internal GPIO controller | 608 | * all these GPIO pins to the internal GPIO controller |
488 | * instead. | 609 | * instead. |
489 | */ | 610 | */ |
490 | if (machine_is_hrefv60()) | 611 | if (!machine_is_snowball()) { |
491 | mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; | 612 | if (machine_is_hrefv60()) |
492 | else | 613 | mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; |
493 | mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; | 614 | else |
615 | mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; | ||
616 | } | ||
494 | 617 | ||
495 | u8500_init_devices(); | 618 | u8500_init_devices(); |
496 | 619 | ||
497 | mop500_pins_init(); | 620 | mop500_pins_init(); |
498 | 621 | ||
499 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); | 622 | if (machine_is_snowball()) |
623 | platform_add_devices(snowball_platform_devs, | ||
624 | ARRAY_SIZE(snowball_platform_devs)); | ||
625 | else | ||
626 | platform_add_devices(mop500_platform_devs, | ||
627 | ARRAY_SIZE(mop500_platform_devs)); | ||
500 | 628 | ||
501 | mop500_i2c_init(); | 629 | mop500_i2c_init(); |
502 | mop500_sdi_init(); | 630 | mop500_sdi_init(); |
503 | mop500_spi_init(); | 631 | mop500_spi_init(); |
504 | mop500_uart_init(); | 632 | mop500_uart_init(); |
505 | 633 | ||
506 | platform_device_register(&ab8500_device); | ||
507 | |||
508 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); | 634 | i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); |
509 | if (machine_is_hrefv60()) | 635 | if (machine_is_hrefv60()) |
510 | i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; | 636 | i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; |
@@ -512,6 +638,9 @@ static void __init mop500_init_machine(void) | |||
512 | i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); | 638 | i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); |
513 | i2c_register_board_info(2, mop500_i2c2_devices, | 639 | i2c_register_board_info(2, mop500_i2c2_devices, |
514 | ARRAY_SIZE(mop500_i2c2_devices)); | 640 | ARRAY_SIZE(mop500_i2c2_devices)); |
641 | |||
642 | /* This board has full regulator constraints */ | ||
643 | regulator_has_full_constraints(); | ||
515 | } | 644 | } |
516 | 645 | ||
517 | MACHINE_START(U8500, "ST-Ericsson MOP500 platform") | 646 | MACHINE_START(U8500, "ST-Ericsson MOP500 platform") |
@@ -531,3 +660,12 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") | |||
531 | .timer = &ux500_timer, | 660 | .timer = &ux500_timer, |
532 | .init_machine = mop500_init_machine, | 661 | .init_machine = mop500_init_machine, |
533 | MACHINE_END | 662 | MACHINE_END |
663 | |||
664 | MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") | ||
665 | .boot_params = 0x100, | ||
666 | .map_io = u8500_map_io, | ||
667 | .init_irq = ux500_init_irq, | ||
668 | /* we re-use nomadik timer here */ | ||
669 | .timer = &ux500_timer, | ||
670 | .init_machine = mop500_init_machine, | ||
671 | MACHINE_END | ||
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 03a31cc9b084..ee77a8970c33 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h | |||
@@ -7,6 +7,11 @@ | |||
7 | #ifndef __BOARD_MOP500_H | 7 | #ifndef __BOARD_MOP500_H |
8 | #define __BOARD_MOP500_H | 8 | #define __BOARD_MOP500_H |
9 | 9 | ||
10 | /* snowball GPIO for MMC card */ | ||
11 | #define SNOWBALL_SDMMC_EN_GPIO 217 | ||
12 | #define SNOWBALL_SDMMC_1V8_3V_GPIO 228 | ||
13 | #define SNOWBALL_SDMMC_CD_GPIO 218 | ||
14 | |||
10 | /* HREFv60-specific GPIO assignments, this board has no GPIO expander */ | 15 | /* HREFv60-specific GPIO assignments, this board has no GPIO expander */ |
11 | #define HREFV60_TOUCH_RST_GPIO 143 | 16 | #define HREFV60_TOUCH_RST_GPIO 143 |
12 | #define HREFV60_PROX_SENSE_GPIO 217 | 17 | #define HREFV60_PROX_SENSE_GPIO 217 |
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index 7d107be63eb4..e832664d1bd9 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/clk.h> | 14 | #include <linux/clk.h> |
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | #include <linux/clkdev.h> | 16 | #include <linux/clkdev.h> |
17 | #include <linux/cpufreq.h> | ||
17 | 18 | ||
18 | #include <plat/mtu.h> | 19 | #include <plat/mtu.h> |
19 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
@@ -742,6 +743,51 @@ err_out: | |||
742 | late_initcall(clk_debugfs_init); | 743 | late_initcall(clk_debugfs_init); |
743 | #endif /* defined(CONFIG_DEBUG_FS) */ | 744 | #endif /* defined(CONFIG_DEBUG_FS) */ |
744 | 745 | ||
746 | unsigned long clk_smp_twd_rate = 400000000; | ||
747 | |||
748 | unsigned long clk_smp_twd_get_rate(struct clk *clk) | ||
749 | { | ||
750 | return clk_smp_twd_rate; | ||
751 | } | ||
752 | |||
753 | static struct clk clk_smp_twd = { | ||
754 | .get_rate = clk_smp_twd_get_rate, | ||
755 | .name = "smp_twd", | ||
756 | }; | ||
757 | |||
758 | static struct clk_lookup clk_smp_twd_lookup = { | ||
759 | .dev_id = "smp_twd", | ||
760 | .clk = &clk_smp_twd, | ||
761 | }; | ||
762 | |||
763 | #ifdef CONFIG_CPU_FREQ | ||
764 | |||
765 | static int clk_twd_cpufreq_transition(struct notifier_block *nb, | ||
766 | unsigned long state, void *data) | ||
767 | { | ||
768 | struct cpufreq_freqs *f = data; | ||
769 | |||
770 | if (state == CPUFREQ_PRECHANGE) { | ||
771 | /* Save frequency in simple Hz */ | ||
772 | clk_smp_twd_rate = f->new * 1000; | ||
773 | } | ||
774 | |||
775 | return NOTIFY_OK; | ||
776 | } | ||
777 | |||
778 | static struct notifier_block clk_twd_cpufreq_nb = { | ||
779 | .notifier_call = clk_twd_cpufreq_transition, | ||
780 | }; | ||
781 | |||
782 | static int clk_init_smp_twd_cpufreq(void) | ||
783 | { | ||
784 | return cpufreq_register_notifier(&clk_twd_cpufreq_nb, | ||
785 | CPUFREQ_TRANSITION_NOTIFIER); | ||
786 | } | ||
787 | late_initcall(clk_init_smp_twd_cpufreq); | ||
788 | |||
789 | #endif | ||
790 | |||
745 | int __init clk_init(void) | 791 | int __init clk_init(void) |
746 | { | 792 | { |
747 | if (cpu_is_u8500ed()) { | 793 | if (cpu_is_u8500ed()) { |
@@ -762,6 +808,8 @@ int __init clk_init(void) | |||
762 | else | 808 | else |
763 | clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); | 809 | clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); |
764 | 810 | ||
811 | clkdev_add(&clk_smp_twd_lookup); | ||
812 | |||
765 | #ifdef CONFIG_DEBUG_FS | 813 | #ifdef CONFIG_DEBUG_FS |
766 | clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); | 814 | clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); |
767 | if (cpu_is_u8500ed()) | 815 | if (cpu_is_u8500ed()) |
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index c01bc19e3c5e..22705d246fc7 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c | |||
@@ -44,6 +44,7 @@ static struct map_desc u5500_io_desc[] __initdata = { | |||
44 | __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), | 44 | __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), |
45 | __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), | 45 | __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), |
46 | __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), | 46 | __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), |
47 | __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), | ||
47 | }; | 48 | }; |
48 | 49 | ||
49 | static struct resource db5500_pmu_resources[] = { | 50 | static struct resource db5500_pmu_resources[] = { |
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 088b550c40df..7dd08074c37b 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h | |||
@@ -54,7 +54,8 @@ static inline void arch_decomp_setup(void) | |||
54 | if (machine_is_u8500() || | 54 | if (machine_is_u8500() || |
55 | machine_is_svp8500v1() || | 55 | machine_is_svp8500v1() || |
56 | machine_is_svp8500v2() || | 56 | machine_is_svp8500v2() || |
57 | machine_is_hrefv60()) | 57 | machine_is_hrefv60() || |
58 | machine_is_snowball()) | ||
58 | ux500_uart_base = U8500_UART2_BASE; | 59 | ux500_uart_base = U8500_UART2_BASE; |
59 | else if (machine_is_u5500()) | 60 | else if (machine_is_u5500()) |
60 | ux500_uart_base = U5500_UART0_BASE; | 61 | ux500_uart_base = U5500_UART0_BASE; |
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c index 82e535953fd9..0a01cbdfe063 100644 --- a/arch/arm/mach-ux500/usb.c +++ b/arch/arm/mach-ux500/usb.c | |||
@@ -6,6 +6,7 @@ | |||
6 | */ | 6 | */ |
7 | #include <linux/platform_device.h> | 7 | #include <linux/platform_device.h> |
8 | #include <linux/usb/musb.h> | 8 | #include <linux/usb/musb.h> |
9 | #include <linux/dma-mapping.h> | ||
9 | #include <plat/ste_dma40.h> | 10 | #include <plat/ste_dma40.h> |
10 | #include <mach/hardware.h> | 11 | #include <mach/hardware.h> |
11 | #include <mach/usb.h> | 12 | #include <mach/usb.h> |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index a0ea5848d40d..88633fe01a5d 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -822,7 +822,7 @@ config CACHE_L2X0 | |||
822 | REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ | 822 | REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ |
823 | ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \ | 823 | ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \ |
824 | ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \ | 824 | ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \ |
825 | ARCH_PRIMA2 || ARCH_ZYNQ | 825 | ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX |
826 | default y | 826 | default y |
827 | select OUTER_CACHE | 827 | select OUTER_CACHE |
828 | select OUTER_CACHE_SYNC | 828 | select OUTER_CACHE_SYNC |
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index fb166b20f60f..0d6ed31bdbf2 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c | |||
@@ -95,8 +95,22 @@ struct device mxc_aips_bus = { | |||
95 | .parent = &platform_bus, | 95 | .parent = &platform_bus, |
96 | }; | 96 | }; |
97 | 97 | ||
98 | struct device mxc_ahb_bus = { | ||
99 | .init_name = "mxc_ahb", | ||
100 | .parent = &platform_bus, | ||
101 | }; | ||
102 | |||
98 | static int __init mxc_device_init(void) | 103 | static int __init mxc_device_init(void) |
99 | { | 104 | { |
100 | return device_register(&mxc_aips_bus); | 105 | int ret; |
106 | |||
107 | ret = device_register(&mxc_aips_bus); | ||
108 | if (IS_ERR_VALUE(ret)) | ||
109 | goto done; | ||
110 | |||
111 | ret = device_register(&mxc_ahb_bus); | ||
112 | |||
113 | done: | ||
114 | return ret; | ||
101 | } | 115 | } |
102 | core_initcall(mxc_device_init); | 116 | core_initcall(mxc_device_init); |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index c64f015e031b..2b0fdb23beb8 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c | |||
@@ -6,207 +6,29 @@ | |||
6 | * the terms of the GNU General Public License version 2 as published by the | 6 | * the terms of the GNU General Public License version 2 as published by the |
7 | * Free Software Foundation. | 7 | * Free Software Foundation. |
8 | */ | 8 | */ |
9 | #include <linux/compiler.h> | ||
10 | #include <linux/err.h> | ||
11 | #include <linux/init.h> | ||
12 | |||
13 | #include <mach/hardware.h> | ||
14 | #include <mach/devices-common.h> | 9 | #include <mach/devices-common.h> |
15 | #include <mach/sdma.h> | ||
16 | |||
17 | struct imx_imx_sdma_data { | ||
18 | resource_size_t iobase; | ||
19 | resource_size_t irq; | ||
20 | struct sdma_platform_data pdata; | ||
21 | }; | ||
22 | |||
23 | #define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\ | ||
24 | { \ | ||
25 | .iobase = soc ## _SDMA ## _BASE_ADDR, \ | ||
26 | .irq = soc ## _INT_SDMA, \ | ||
27 | .pdata = { \ | ||
28 | .sdma_version = _sdma_version, \ | ||
29 | .cpu_name = _cpu_name, \ | ||
30 | .to_version = _to_version, \ | ||
31 | }, \ | ||
32 | } | ||
33 | |||
34 | #ifdef CONFIG_SOC_IMX25 | ||
35 | struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = | ||
36 | imx_imx_sdma_data_entry_single(MX25, 2, "imx25", 1); | ||
37 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
38 | 10 | ||
39 | #ifdef CONFIG_SOC_IMX31 | 11 | struct platform_device __init __maybe_unused *imx_add_imx_dma(void) |
40 | struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = | 12 | { |
41 | imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 1); | 13 | return platform_device_register_resndata(&mxc_ahb_bus, |
42 | #endif /* ifdef CONFIG_SOC_IMX31 */ | 14 | "imx-dma", -1, NULL, 0, NULL, 0); |
43 | 15 | } | |
44 | #ifdef CONFIG_SOC_IMX35 | ||
45 | struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = | ||
46 | imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 1); | ||
47 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
48 | |||
49 | #ifdef CONFIG_SOC_IMX51 | ||
50 | struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = | ||
51 | imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 1); | ||
52 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
53 | 16 | ||
54 | static struct platform_device __init __maybe_unused *imx_add_imx_sdma( | 17 | struct platform_device __init __maybe_unused *imx_add_imx_sdma( |
55 | const struct imx_imx_sdma_data *data) | 18 | resource_size_t iobase, int irq, struct sdma_platform_data *pdata) |
56 | { | 19 | { |
57 | struct resource res[] = { | 20 | struct resource res[] = { |
58 | { | 21 | { |
59 | .start = data->iobase, | 22 | .start = iobase, |
60 | .end = data->iobase + SZ_16K - 1, | 23 | .end = iobase + SZ_16K - 1, |
61 | .flags = IORESOURCE_MEM, | 24 | .flags = IORESOURCE_MEM, |
62 | }, { | 25 | }, { |
63 | .start = data->irq, | 26 | .start = irq, |
64 | .end = data->irq, | 27 | .end = irq, |
65 | .flags = IORESOURCE_IRQ, | 28 | .flags = IORESOURCE_IRQ, |
66 | }, | 29 | }, |
67 | }; | 30 | }; |
68 | 31 | ||
69 | return imx_add_platform_device("imx-sdma", -1, | 32 | return platform_device_register_resndata(&mxc_ahb_bus, "imx-sdma", |
70 | res, ARRAY_SIZE(res), | 33 | -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); |
71 | &data->pdata, sizeof(data->pdata)); | ||
72 | } | ||
73 | |||
74 | static struct platform_device __init __maybe_unused *imx_add_imx_dma(void) | ||
75 | { | ||
76 | return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); | ||
77 | } | ||
78 | |||
79 | #ifdef CONFIG_ARCH_MX25 | ||
80 | static struct sdma_script_start_addrs addr_imx25 = { | ||
81 | .ap_2_ap_addr = 729, | ||
82 | .uart_2_mcu_addr = 904, | ||
83 | .per_2_app_addr = 1255, | ||
84 | .mcu_2_app_addr = 834, | ||
85 | .uartsh_2_mcu_addr = 1120, | ||
86 | .per_2_shp_addr = 1329, | ||
87 | .mcu_2_shp_addr = 1048, | ||
88 | .ata_2_mcu_addr = 1560, | ||
89 | .mcu_2_ata_addr = 1479, | ||
90 | .app_2_per_addr = 1189, | ||
91 | .app_2_mcu_addr = 770, | ||
92 | .shp_2_per_addr = 1407, | ||
93 | .shp_2_mcu_addr = 979, | ||
94 | }; | ||
95 | #endif | ||
96 | |||
97 | #ifdef CONFIG_SOC_IMX31 | ||
98 | static struct sdma_script_start_addrs addr_imx31_to1 = { | ||
99 | .per_2_per_addr = 1677, | ||
100 | }; | ||
101 | |||
102 | static struct sdma_script_start_addrs addr_imx31_to2 = { | ||
103 | .ap_2_ap_addr = 423, | ||
104 | .ap_2_bp_addr = 829, | ||
105 | .bp_2_ap_addr = 1029, | ||
106 | }; | ||
107 | #endif | ||
108 | |||
109 | #ifdef CONFIG_SOC_IMX35 | ||
110 | static struct sdma_script_start_addrs addr_imx35_to1 = { | ||
111 | .ap_2_ap_addr = 642, | ||
112 | .uart_2_mcu_addr = 817, | ||
113 | .mcu_2_app_addr = 747, | ||
114 | .uartsh_2_mcu_addr = 1183, | ||
115 | .per_2_shp_addr = 1033, | ||
116 | .mcu_2_shp_addr = 961, | ||
117 | .ata_2_mcu_addr = 1333, | ||
118 | .mcu_2_ata_addr = 1252, | ||
119 | .app_2_mcu_addr = 683, | ||
120 | .shp_2_per_addr = 1111, | ||
121 | .shp_2_mcu_addr = 892, | ||
122 | }; | ||
123 | |||
124 | static struct sdma_script_start_addrs addr_imx35_to2 = { | ||
125 | .ap_2_ap_addr = 729, | ||
126 | .uart_2_mcu_addr = 904, | ||
127 | .per_2_app_addr = 1597, | ||
128 | .mcu_2_app_addr = 834, | ||
129 | .uartsh_2_mcu_addr = 1270, | ||
130 | .per_2_shp_addr = 1120, | ||
131 | .mcu_2_shp_addr = 1048, | ||
132 | .ata_2_mcu_addr = 1429, | ||
133 | .mcu_2_ata_addr = 1339, | ||
134 | .app_2_per_addr = 1531, | ||
135 | .app_2_mcu_addr = 770, | ||
136 | .shp_2_per_addr = 1198, | ||
137 | .shp_2_mcu_addr = 979, | ||
138 | }; | ||
139 | #endif | ||
140 | |||
141 | #ifdef CONFIG_SOC_IMX51 | ||
142 | static struct sdma_script_start_addrs addr_imx51 = { | ||
143 | .ap_2_ap_addr = 642, | ||
144 | .uart_2_mcu_addr = 817, | ||
145 | .mcu_2_app_addr = 747, | ||
146 | .mcu_2_shp_addr = 961, | ||
147 | .ata_2_mcu_addr = 1473, | ||
148 | .mcu_2_ata_addr = 1392, | ||
149 | .app_2_per_addr = 1033, | ||
150 | .app_2_mcu_addr = 683, | ||
151 | .shp_2_per_addr = 1251, | ||
152 | .shp_2_mcu_addr = 892, | ||
153 | }; | ||
154 | #endif | ||
155 | |||
156 | static int __init imxXX_add_imx_dma(void) | ||
157 | { | ||
158 | struct platform_device *ret; | ||
159 | |||
160 | #if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27) | ||
161 | if (cpu_is_mx21() || cpu_is_mx27()) | ||
162 | ret = imx_add_imx_dma(); | ||
163 | else | ||
164 | #endif | ||
165 | |||
166 | #if defined(CONFIG_SOC_IMX25) | ||
167 | if (cpu_is_mx25()) { | ||
168 | imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25; | ||
169 | ret = imx_add_imx_sdma(&imx25_imx_sdma_data); | ||
170 | } else | ||
171 | #endif | ||
172 | |||
173 | #if defined(CONFIG_SOC_IMX31) | ||
174 | if (cpu_is_mx31()) { | ||
175 | int to_version = mx31_revision() >> 4; | ||
176 | imx31_imx_sdma_data.pdata.to_version = to_version; | ||
177 | if (to_version == 1) | ||
178 | imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1; | ||
179 | else | ||
180 | imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2; | ||
181 | ret = imx_add_imx_sdma(&imx31_imx_sdma_data); | ||
182 | } else | ||
183 | #endif | ||
184 | |||
185 | #if defined(CONFIG_SOC_IMX35) | ||
186 | if (cpu_is_mx35()) { | ||
187 | int to_version = mx35_revision() >> 4; | ||
188 | imx35_imx_sdma_data.pdata.to_version = to_version; | ||
189 | if (to_version == 1) | ||
190 | imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1; | ||
191 | else | ||
192 | imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2; | ||
193 | ret = imx_add_imx_sdma(&imx35_imx_sdma_data); | ||
194 | } else | ||
195 | #endif | ||
196 | |||
197 | #if defined(CONFIG_SOC_IMX51) | ||
198 | if (cpu_is_mx51()) { | ||
199 | int to_version = mx51_revision() >> 4; | ||
200 | imx51_imx_sdma_data.pdata.to_version = to_version; | ||
201 | imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51; | ||
202 | ret = imx_add_imx_sdma(&imx51_imx_sdma_data); | ||
203 | } else | ||
204 | #endif | ||
205 | ret = ERR_PTR(-ENODEV); | ||
206 | |||
207 | if (IS_ERR(ret)) | ||
208 | return PTR_ERR(ret); | ||
209 | |||
210 | return 0; | ||
211 | } | 34 | } |
212 | arch_initcall(imxXX_add_imx_dma); | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 2ab74f0da9a6..afe60f7244a8 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c | |||
@@ -94,8 +94,9 @@ const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = { | |||
94 | imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K) | 94 | imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K) |
95 | imx53_imx_i2c_data_entry(0, 1), | 95 | imx53_imx_i2c_data_entry(0, 1), |
96 | imx53_imx_i2c_data_entry(1, 2), | 96 | imx53_imx_i2c_data_entry(1, 2), |
97 | imx53_imx_i2c_data_entry(2, 3), | ||
97 | }; | 98 | }; |
98 | #endif /* ifdef CONFIG_SOC_IMX51 */ | 99 | #endif /* ifdef CONFIG_SOC_IMX53 */ |
99 | 100 | ||
100 | struct platform_device *__init imx_add_imx_i2c( | 101 | struct platform_device *__init imx_add_imx_i2c( |
101 | const struct imx_imx_i2c_data *data, | 102 | const struct imx_imx_i2c_data *data, |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c index 26366114b021..479c3e9f771f 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c | |||
@@ -46,6 +46,11 @@ const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst = | |||
46 | imx_imx_keypad_data_entry_single(MX51, SZ_16); | 46 | imx_imx_keypad_data_entry_single(MX51, SZ_16); |
47 | #endif /* ifdef CONFIG_SOC_IMX51 */ | 47 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
48 | 48 | ||
49 | #ifdef CONFIG_SOC_IMX53 | ||
50 | const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst = | ||
51 | imx_imx_keypad_data_entry_single(MX53, SZ_16); | ||
52 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
53 | |||
49 | struct platform_device *__init imx_add_imx_keypad( | 54 | struct platform_device *__init imx_add_imx_keypad( |
50 | const struct imx_imx_keypad_data *data, | 55 | const struct imx_imx_keypad_data *data, |
51 | const struct matrix_keymap_data *pdata) | 56 | const struct matrix_keymap_data *pdata) |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 66b8593e9b69..21c6f30e1017 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c | |||
@@ -76,6 +76,16 @@ const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { | |||
76 | }; | 76 | }; |
77 | #endif /* ifdef CONFIG_SOC_IMX51 */ | 77 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
78 | 78 | ||
79 | #ifdef CONFIG_SOC_IMX53 | ||
80 | const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = { | ||
81 | #define imx53_imx_ssi_data_entry(_id, _hwid) \ | ||
82 | imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K) | ||
83 | imx53_imx_ssi_data_entry(0, 1), | ||
84 | imx53_imx_ssi_data_entry(1, 2), | ||
85 | imx53_imx_ssi_data_entry(2, 3), | ||
86 | }; | ||
87 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
88 | |||
79 | struct platform_device *__init imx_add_imx_ssi( | 89 | struct platform_device *__init imx_add_imx_ssi( |
80 | const struct imx_imx_ssi_data *data, | 90 | const struct imx_imx_ssi_data *data, |
81 | const struct imx_ssi_platform_data *pdata) | 91 | const struct imx_ssi_platform_data *pdata) |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 3c854c2cc6dd..cfce8c918b73 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c | |||
@@ -123,6 +123,8 @@ const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = { | |||
123 | imx53_imx_uart_data_entry(0, 1), | 123 | imx53_imx_uart_data_entry(0, 1), |
124 | imx53_imx_uart_data_entry(1, 2), | 124 | imx53_imx_uart_data_entry(1, 2), |
125 | imx53_imx_uart_data_entry(2, 3), | 125 | imx53_imx_uart_data_entry(2, 3), |
126 | imx53_imx_uart_data_entry(3, 4), | ||
127 | imx53_imx_uart_data_entry(4, 5), | ||
126 | }; | 128 | }; |
127 | #endif /* ifdef CONFIG_SOC_IMX53 */ | 129 | #endif /* ifdef CONFIG_SOC_IMX53 */ |
128 | 130 | ||
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 03f626645374..bf93820ab61c 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h | |||
@@ -9,8 +9,10 @@ | |||
9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
10 | #include <linux/platform_device.h> | 10 | #include <linux/platform_device.h> |
11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
12 | #include <mach/sdma.h> | ||
12 | 13 | ||
13 | extern struct device mxc_aips_bus; | 14 | extern struct device mxc_aips_bus; |
15 | extern struct device mxc_ahb_bus; | ||
14 | 16 | ||
15 | struct platform_device *imx_add_platform_device_dmamask( | 17 | struct platform_device *imx_add_platform_device_dmamask( |
16 | const char *name, int id, | 18 | const char *name, int id, |
@@ -293,3 +295,7 @@ struct imx_spi_imx_data { | |||
293 | struct platform_device *__init imx_add_spi_imx( | 295 | struct platform_device *__init imx_add_spi_imx( |
294 | const struct imx_spi_imx_data *data, | 296 | const struct imx_spi_imx_data *data, |
295 | const struct spi_imx_master *pdata); | 297 | const struct spi_imx_master *pdata); |
298 | |||
299 | struct platform_device *imx_add_imx_dma(void); | ||
300 | struct platform_device *imx_add_imx_sdma( | ||
301 | resource_size_t iobase, int irq, struct sdma_platform_data *pdata); | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 74cd093203e0..5e3c3236ebf3 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h | |||
@@ -176,10 +176,10 @@ | |||
176 | /* | 176 | /* |
177 | * DMA request assignments | 177 | * DMA request assignments |
178 | */ | 178 | */ |
179 | #define MX53_DMA_REQ_SSI3_TX1 47 | 179 | #define MX53_DMA_REQ_SSI3_TX0 47 |
180 | #define MX53_DMA_REQ_SSI3_RX1 46 | 180 | #define MX53_DMA_REQ_SSI3_RX0 46 |
181 | #define MX53_DMA_REQ_SSI3_TX2 45 | 181 | #define MX53_DMA_REQ_SSI3_TX1 45 |
182 | #define MX53_DMA_REQ_SSI3_RX2 44 | 182 | #define MX53_DMA_REQ_SSI3_RX1 44 |
183 | #define MX53_DMA_REQ_UART3_TX 43 | 183 | #define MX53_DMA_REQ_UART3_TX 43 |
184 | #define MX53_DMA_REQ_UART3_RX 42 | 184 | #define MX53_DMA_REQ_UART3_RX 42 |
185 | #define MX53_DMA_REQ_ESAI_TX 41 | 185 | #define MX53_DMA_REQ_ESAI_TX 41 |
@@ -194,14 +194,14 @@ | |||
194 | #define MX53_DMA_REQ_ASRC_DMA1 32 | 194 | #define MX53_DMA_REQ_ASRC_DMA1 32 |
195 | #define MX53_DMA_REQ_EMI_WR 31 | 195 | #define MX53_DMA_REQ_EMI_WR 31 |
196 | #define MX53_DMA_REQ_EMI_RD 30 | 196 | #define MX53_DMA_REQ_EMI_RD 30 |
197 | #define MX53_DMA_REQ_SSI1_TX1 29 | 197 | #define MX53_DMA_REQ_SSI1_TX0 29 |
198 | #define MX53_DMA_REQ_SSI1_RX1 28 | 198 | #define MX53_DMA_REQ_SSI1_RX0 28 |
199 | #define MX53_DMA_REQ_SSI1_TX2 27 | 199 | #define MX53_DMA_REQ_SSI1_TX1 27 |
200 | #define MX53_DMA_REQ_SSI1_RX2 26 | 200 | #define MX53_DMA_REQ_SSI1_RX1 26 |
201 | #define MX53_DMA_REQ_SSI2_TX1 25 | 201 | #define MX53_DMA_REQ_SSI2_TX0 25 |
202 | #define MX53_DMA_REQ_SSI2_RX1 24 | 202 | #define MX53_DMA_REQ_SSI2_RX0 24 |
203 | #define MX53_DMA_REQ_SSI2_TX2 23 | 203 | #define MX53_DMA_REQ_SSI2_TX1 23 |
204 | #define MX53_DMA_REQ_SSI2_RX2 22 | 204 | #define MX53_DMA_REQ_SSI2_RX1 22 |
205 | #define MX53_DMA_REQ_I2C2_SDHC2 21 | 205 | #define MX53_DMA_REQ_I2C2_SDHC2 21 |
206 | #define MX53_DMA_REQ_I2C1_SDHC1 20 | 206 | #define MX53_DMA_REQ_I2C1_SDHC1 20 |
207 | #define MX53_DMA_REQ_UART1_TX 19 | 207 | #define MX53_DMA_REQ_UART1_TX 19 |
@@ -241,7 +241,7 @@ | |||
241 | #define MX53_INT_IPU_ERR 10 | 241 | #define MX53_INT_IPU_ERR 10 |
242 | #define MX53_INT_IPU_SYN 11 | 242 | #define MX53_INT_IPU_SYN 11 |
243 | #define MX53_INT_GPU 12 | 243 | #define MX53_INT_GPU 12 |
244 | #define MX53_INT_RESV13 13 | 244 | #define MX53_INT_UART4 13 |
245 | #define MX53_INT_USB_H1 14 | 245 | #define MX53_INT_USB_H1 14 |
246 | #define MX53_INT_EMI 15 | 246 | #define MX53_INT_EMI 15 |
247 | #define MX53_INT_USB_H2 16 | 247 | #define MX53_INT_USB_H2 16 |
@@ -314,7 +314,7 @@ | |||
314 | #define MX53_INT_CAN2 83 | 314 | #define MX53_INT_CAN2 83 |
315 | #define MX53_INT_GPU2_IRQ 84 | 315 | #define MX53_INT_GPU2_IRQ 84 |
316 | #define MX53_INT_GPU2_BUSY 85 | 316 | #define MX53_INT_GPU2_BUSY 85 |
317 | #define MX53_INT_RESV86 86 | 317 | #define MX53_INT_UART5 86 |
318 | #define MX53_INT_FEC 87 | 318 | #define MX53_INT_FEC 87 |
319 | #define MX53_INT_OWIRE 88 | 319 | #define MX53_INT_OWIRE 88 |
320 | #define MX53_INT_CTI1_TG2 89 | 320 | #define MX53_INT_CTI1_TG2 89 |
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h index 913e0432e40e..f495c87c113f 100644 --- a/arch/arm/plat-mxc/include/mach/sdma.h +++ b/arch/arm/plat-mxc/include/mach/sdma.h | |||
@@ -49,14 +49,12 @@ struct sdma_script_start_addrs { | |||
49 | * struct sdma_platform_data - platform specific data for SDMA engine | 49 | * struct sdma_platform_data - platform specific data for SDMA engine |
50 | * | 50 | * |
51 | * @sdma_version The version of this SDMA engine | 51 | * @sdma_version The version of this SDMA engine |
52 | * @cpu_name used to generate the firmware name | 52 | * @fw_name The firmware name |
53 | * @to_version CPU Tape out version | ||
54 | * @script_addrs SDMA scripts addresses in SDMA ROM | 53 | * @script_addrs SDMA scripts addresses in SDMA ROM |
55 | */ | 54 | */ |
56 | struct sdma_platform_data { | 55 | struct sdma_platform_data { |
57 | int sdma_version; | 56 | int sdma_version; |
58 | char *cpu_name; | 57 | char *fw_name; |
59 | int to_version; | ||
60 | struct sdma_script_start_addrs *script_addrs; | 58 | struct sdma_script_start_addrs *script_addrs; |
61 | }; | 59 | }; |
62 | 60 | ||
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index d85e2d1c0324..88fd40452567 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h | |||
@@ -117,6 +117,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) | |||
117 | case MACH_TYPE_MX53_EVK: | 117 | case MACH_TYPE_MX53_EVK: |
118 | case MACH_TYPE_MX53_LOCO: | 118 | case MACH_TYPE_MX53_LOCO: |
119 | case MACH_TYPE_MX53_SMD: | 119 | case MACH_TYPE_MX53_SMD: |
120 | case MACH_TYPE_MX53_ARD: | ||
120 | uart_base = MX53_UART1_BASE_ADDR; | 121 | uart_base = MX53_UART1_BASE_ADDR; |
121 | break; | 122 | break; |
122 | default: | 123 | default: |
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index e1c6eff7258a..96953e2e4f11 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c | |||
@@ -42,17 +42,16 @@ EXPORT_SYMBOL(imx_irq_set_priority); | |||
42 | 42 | ||
43 | int mxc_set_irq_fiq(unsigned int irq, unsigned int type) | 43 | int mxc_set_irq_fiq(unsigned int irq, unsigned int type) |
44 | { | 44 | { |
45 | struct mxc_irq_chip *chip; | 45 | struct irq_chip_generic *gc; |
46 | struct irq_chip *base; | 46 | int (*set_irq_fiq)(unsigned int, unsigned int); |
47 | int ret; | 47 | int ret; |
48 | 48 | ||
49 | ret = -ENOSYS; | 49 | ret = -ENOSYS; |
50 | 50 | ||
51 | base = irq_get_chip(irq); | 51 | gc = irq_get_chip_data(irq); |
52 | if (base) { | 52 | if (gc && gc->private) { |
53 | chip = container_of(base, struct mxc_irq_chip, base); | 53 | set_irq_fiq = gc->private; |
54 | if (chip->set_irq_fiq) | 54 | ret = set_irq_fiq(irq, type); |
55 | ret = chip->set_irq_fiq(irq, type); | ||
56 | } | 55 | } |
57 | 56 | ||
58 | return ret; | 57 | return ret; |
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 710f2e7da4ce..f257fccdc394 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
@@ -68,78 +68,34 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | |||
68 | 68 | ||
69 | return 0; | 69 | return 0; |
70 | } | 70 | } |
71 | #else | ||
72 | #define tzic_set_irq_fiq NULL | ||
71 | #endif | 73 | #endif |
72 | 74 | ||
73 | /** | 75 | static unsigned int *wakeup_intr[4]; |
74 | * tzic_mask_irq() - Disable interrupt source "d" in the TZIC | ||
75 | * | ||
76 | * @param d interrupt source | ||
77 | */ | ||
78 | static void tzic_mask_irq(struct irq_data *d) | ||
79 | { | ||
80 | int index, off; | ||
81 | |||
82 | index = d->irq >> 5; | ||
83 | off = d->irq & 0x1F; | ||
84 | __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); | ||
85 | } | ||
86 | |||
87 | /** | ||
88 | * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC | ||
89 | * | ||
90 | * @param d interrupt source | ||
91 | */ | ||
92 | static void tzic_unmask_irq(struct irq_data *d) | ||
93 | { | ||
94 | int index, off; | ||
95 | |||
96 | index = d->irq >> 5; | ||
97 | off = d->irq & 0x1F; | ||
98 | __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); | ||
99 | } | ||
100 | |||
101 | static unsigned int wakeup_intr[4]; | ||
102 | 76 | ||
103 | /** | 77 | static __init void tzic_init_gc(unsigned int irq_start) |
104 | * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source. | ||
105 | * | ||
106 | * @param d interrupt source | ||
107 | * @param enable enable as wake-up if equal to non-zero | ||
108 | * disble as wake-up if equal to zero | ||
109 | * | ||
110 | * @return This function returns 0 on success. | ||
111 | */ | ||
112 | static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable) | ||
113 | { | 78 | { |
114 | unsigned int index, off; | 79 | struct irq_chip_generic *gc; |
115 | 80 | struct irq_chip_type *ct; | |
116 | index = d->irq >> 5; | 81 | int idx = irq_start >> 5; |
117 | off = d->irq & 0x1F; | 82 | |
118 | 83 | gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, | |
119 | if (index > 3) | 84 | handle_level_irq); |
120 | return -EINVAL; | 85 | gc->private = tzic_set_irq_fiq; |
121 | 86 | gc->wake_enabled = IRQ_MSK(32); | |
122 | if (enable) | 87 | wakeup_intr[idx] = &gc->wake_active; |
123 | wakeup_intr[index] |= (1 << off); | 88 | |
124 | else | 89 | ct = gc->chip_types; |
125 | wakeup_intr[index] &= ~(1 << off); | 90 | ct->chip.irq_mask = irq_gc_mask_disable_reg; |
126 | 91 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
127 | return 0; | 92 | ct->chip.irq_set_wake = irq_gc_set_wake; |
93 | ct->regs.disable = TZIC_ENCLEAR0(idx); | ||
94 | ct->regs.enable = TZIC_ENSET0(idx); | ||
95 | |||
96 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); | ||
128 | } | 97 | } |
129 | 98 | ||
130 | static struct mxc_irq_chip mxc_tzic_chip = { | ||
131 | .base = { | ||
132 | .name = "MXC_TZIC", | ||
133 | .irq_ack = tzic_mask_irq, | ||
134 | .irq_mask = tzic_mask_irq, | ||
135 | .irq_unmask = tzic_unmask_irq, | ||
136 | .irq_set_wake = tzic_set_wake_irq, | ||
137 | }, | ||
138 | #ifdef CONFIG_FIQ | ||
139 | .set_irq_fiq = tzic_set_irq_fiq, | ||
140 | #endif | ||
141 | }; | ||
142 | |||
143 | /* | 99 | /* |
144 | * This function initializes the TZIC hardware and disables all the | 100 | * This function initializes the TZIC hardware and disables all the |
145 | * interrupts. It registers the interrupt enable and disable functions | 101 | * interrupts. It registers the interrupt enable and disable functions |
@@ -168,11 +124,8 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
168 | 124 | ||
169 | /* all IRQ no FIQ Warning :: No selection */ | 125 | /* all IRQ no FIQ Warning :: No selection */ |
170 | 126 | ||
171 | for (i = 0; i < TZIC_NUM_IRQS; i++) { | 127 | for (i = 0; i < TZIC_NUM_IRQS; i += 32) |
172 | irq_set_chip_and_handler(i, &mxc_tzic_chip.base, | 128 | tzic_init_gc(i); |
173 | handle_level_irq); | ||
174 | set_irq_flags(i, IRQF_VALID); | ||
175 | } | ||
176 | 129 | ||
177 | #ifdef CONFIG_FIQ | 130 | #ifdef CONFIG_FIQ |
178 | /* Initialize FIQ */ | 131 | /* Initialize FIQ */ |
@@ -199,7 +152,7 @@ int tzic_enable_wake(int is_idle) | |||
199 | 152 | ||
200 | for (i = 0; i < 4; i++) { | 153 | for (i = 0; i < 4; i++) { |
201 | v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : | 154 | v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : |
202 | wakeup_intr[i]; | 155 | *wakeup_intr[i]; |
203 | __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); | 156 | __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); |
204 | } | 157 | } |
205 | 158 | ||
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index e98f5c5c7879..9843c954c042 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig | |||
@@ -39,6 +39,7 @@ config S5P_GPIO_INT | |||
39 | 39 | ||
40 | config S5P_HRT | 40 | config S5P_HRT |
41 | bool | 41 | bool |
42 | select SAMSUNG_DEV_PWM | ||
42 | help | 43 | help |
43 | Use the High Resolution timer support | 44 | Use the High Resolution timer support |
44 | 45 | ||
@@ -70,6 +71,16 @@ config S5P_DEV_FIMC3 | |||
70 | help | 71 | help |
71 | Compile in platform device definitions for FIMC controller 3 | 72 | Compile in platform device definitions for FIMC controller 3 |
72 | 73 | ||
74 | config S5P_DEV_FIMD0 | ||
75 | bool | ||
76 | help | ||
77 | Compile in platform device definitions for FIMD controller 0 | ||
78 | |||
79 | config S5P_DEV_MFC | ||
80 | bool | ||
81 | help | ||
82 | Compile in platform device definitions for MFC | ||
83 | |||
73 | config S5P_DEV_ONENAND | 84 | config S5P_DEV_ONENAND |
74 | bool | 85 | bool |
75 | help | 86 | help |
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index e234cc4d49a0..4b53e04eeca4 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile | |||
@@ -25,11 +25,12 @@ obj-$(CONFIG_PM) += irq-pm.o | |||
25 | obj-$(CONFIG_S5P_HRT) += s5p-time.o | 25 | obj-$(CONFIG_S5P_HRT) += s5p-time.o |
26 | 26 | ||
27 | # devices | 27 | # devices |
28 | 28 | obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o | |
29 | obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o | 29 | obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o |
30 | obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o | 30 | obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o |
31 | obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o | 31 | obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o |
32 | obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o | 32 | obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o |
33 | obj-$(CONFIG_S5P_DEV_FIMD0) += dev-fimd0.o | ||
33 | obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o | 34 | obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o |
34 | obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o | 35 | obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o |
35 | obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o | 36 | obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o |
diff --git a/arch/arm/plat-s5p/dev-fimd0.c b/arch/arm/plat-s5p/dev-fimd0.c new file mode 100644 index 000000000000..f728bb5abcef --- /dev/null +++ b/arch/arm/plat-s5p/dev-fimd0.c | |||
@@ -0,0 +1,67 @@ | |||
1 | /* linux/arch/arm/plat-s5p/dev-fimd0.c | ||
2 | * | ||
3 | * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Core file for Samsung Display Controller (FIMD) driver | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/string.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/fb.h> | ||
17 | #include <linux/gfp.h> | ||
18 | #include <linux/dma-mapping.h> | ||
19 | |||
20 | #include <mach/irqs.h> | ||
21 | #include <mach/map.h> | ||
22 | |||
23 | #include <plat/fb.h> | ||
24 | #include <plat/devs.h> | ||
25 | #include <plat/cpu.h> | ||
26 | |||
27 | static struct resource s5p_fimd0_resource[] = { | ||
28 | [0] = { | ||
29 | .start = S5P_PA_FIMD0, | ||
30 | .end = S5P_PA_FIMD0 + SZ_32K - 1, | ||
31 | .flags = IORESOURCE_MEM, | ||
32 | }, | ||
33 | [1] = { | ||
34 | .start = IRQ_FIMD0_VSYNC, | ||
35 | .end = IRQ_FIMD0_VSYNC, | ||
36 | .flags = IORESOURCE_IRQ, | ||
37 | }, | ||
38 | [2] = { | ||
39 | .start = IRQ_FIMD0_FIFO, | ||
40 | .end = IRQ_FIMD0_FIFO, | ||
41 | .flags = IORESOURCE_IRQ, | ||
42 | }, | ||
43 | [3] = { | ||
44 | .start = IRQ_FIMD0_SYSTEM, | ||
45 | .end = IRQ_FIMD0_SYSTEM, | ||
46 | .flags = IORESOURCE_IRQ, | ||
47 | }, | ||
48 | }; | ||
49 | |||
50 | static u64 fimd0_dmamask = DMA_BIT_MASK(32); | ||
51 | |||
52 | struct platform_device s5p_device_fimd0 = { | ||
53 | .name = "s5p-fb", | ||
54 | .id = 0, | ||
55 | .num_resources = ARRAY_SIZE(s5p_fimd0_resource), | ||
56 | .resource = s5p_fimd0_resource, | ||
57 | .dev = { | ||
58 | .dma_mask = &fimd0_dmamask, | ||
59 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
60 | }, | ||
61 | }; | ||
62 | |||
63 | void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd) | ||
64 | { | ||
65 | s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), | ||
66 | &s5p_device_fimd0); | ||
67 | } | ||
diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c new file mode 100644 index 000000000000..94226a0010f7 --- /dev/null +++ b/arch/arm/plat-s5p/dev-mfc.c | |||
@@ -0,0 +1,123 @@ | |||
1 | /* linux/arch/arm/plat-s5p/dev-mfc.c | ||
2 | * | ||
3 | * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd | ||
4 | * | ||
5 | * Base S5P MFC resource and device definitions | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/dma-mapping.h> | ||
17 | #include <linux/memblock.h> | ||
18 | #include <linux/ioport.h> | ||
19 | |||
20 | #include <mach/map.h> | ||
21 | #include <plat/devs.h> | ||
22 | #include <plat/irqs.h> | ||
23 | #include <plat/mfc.h> | ||
24 | |||
25 | static struct resource s5p_mfc_resource[] = { | ||
26 | [0] = { | ||
27 | .start = S5P_PA_MFC, | ||
28 | .end = S5P_PA_MFC + SZ_64K - 1, | ||
29 | .flags = IORESOURCE_MEM, | ||
30 | }, | ||
31 | [1] = { | ||
32 | .start = IRQ_MFC, | ||
33 | .end = IRQ_MFC, | ||
34 | .flags = IORESOURCE_IRQ, | ||
35 | } | ||
36 | }; | ||
37 | |||
38 | struct platform_device s5p_device_mfc = { | ||
39 | .name = "s5p-mfc", | ||
40 | .id = -1, | ||
41 | .num_resources = ARRAY_SIZE(s5p_mfc_resource), | ||
42 | .resource = s5p_mfc_resource, | ||
43 | }; | ||
44 | |||
45 | /* | ||
46 | * MFC hardware has 2 memory interfaces which are modelled as two separate | ||
47 | * platform devices to let dma-mapping distinguish between them. | ||
48 | * | ||
49 | * MFC parent device (s5p_device_mfc) must be registered before memory | ||
50 | * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r). | ||
51 | */ | ||
52 | |||
53 | static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32); | ||
54 | |||
55 | struct platform_device s5p_device_mfc_l = { | ||
56 | .name = "s5p-mfc-l", | ||
57 | .id = -1, | ||
58 | .dev = { | ||
59 | .parent = &s5p_device_mfc.dev, | ||
60 | .dma_mask = &s5p_mfc_dma_mask, | ||
61 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
62 | }, | ||
63 | }; | ||
64 | |||
65 | struct platform_device s5p_device_mfc_r = { | ||
66 | .name = "s5p-mfc-r", | ||
67 | .id = -1, | ||
68 | .dev = { | ||
69 | .parent = &s5p_device_mfc.dev, | ||
70 | .dma_mask = &s5p_mfc_dma_mask, | ||
71 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
72 | }, | ||
73 | }; | ||
74 | |||
75 | struct s5p_mfc_reserved_mem { | ||
76 | phys_addr_t base; | ||
77 | unsigned long size; | ||
78 | struct device *dev; | ||
79 | }; | ||
80 | |||
81 | static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; | ||
82 | |||
83 | void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, | ||
84 | phys_addr_t lbase, unsigned int lsize) | ||
85 | { | ||
86 | int i; | ||
87 | |||
88 | s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev; | ||
89 | s5p_mfc_mem[0].base = rbase; | ||
90 | s5p_mfc_mem[0].size = rsize; | ||
91 | |||
92 | s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev; | ||
93 | s5p_mfc_mem[1].base = lbase; | ||
94 | s5p_mfc_mem[1].size = lsize; | ||
95 | |||
96 | for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) { | ||
97 | struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i]; | ||
98 | if (memblock_remove(area->base, area->size)) { | ||
99 | printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n", | ||
100 | area->size, (unsigned long) area->base); | ||
101 | area->base = 0; | ||
102 | } | ||
103 | } | ||
104 | } | ||
105 | |||
106 | static int __init s5p_mfc_memory_init(void) | ||
107 | { | ||
108 | int i; | ||
109 | |||
110 | for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) { | ||
111 | struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i]; | ||
112 | if (!area->base) | ||
113 | continue; | ||
114 | |||
115 | if (dma_declare_coherent_memory(area->dev, area->base, | ||
116 | area->base, area->size, | ||
117 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) | ||
118 | printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n", | ||
119 | area->size, (unsigned long) area->base); | ||
120 | } | ||
121 | return 0; | ||
122 | } | ||
123 | device_initcall(s5p_mfc_memory_init); | ||
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index d973d39666a3..36d3551173b2 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h | |||
@@ -35,9 +35,10 @@ | |||
35 | #define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) | 35 | #define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) |
36 | #define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) | 36 | #define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) |
37 | #define S5P_VA_SCU S5P_VA_COREPERI(0x0) | 37 | #define S5P_VA_SCU S5P_VA_COREPERI(0x0) |
38 | #define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100) | ||
39 | #define S5P_VA_TWD S5P_VA_COREPERI(0x600) | 38 | #define S5P_VA_TWD S5P_VA_COREPERI(0x600) |
40 | #define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) | 39 | |
40 | #define S5P_VA_GIC_CPU S3C_ADDR(0x02810000) | ||
41 | #define S5P_VA_GIC_DIST S3C_ADDR(0x02820000) | ||
41 | 42 | ||
42 | #define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) | 43 | #define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) |
43 | 44 | ||
diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h new file mode 100644 index 000000000000..6697f8cb2949 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/mfc.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms of the GNU General Public License as published by the | ||
6 | * Free Software Foundation; either version 2 of the License, or (at your | ||
7 | * option) any later version. | ||
8 | */ | ||
9 | |||
10 | #ifndef __PLAT_S5P_MFC_H | ||
11 | #define __PLAT_S5P_MFC_H | ||
12 | |||
13 | /** | ||
14 | * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver | ||
15 | * @rbase: base address for MFC 'right' memory interface | ||
16 | * @rsize: size of the memory reserved for MFC 'right' interface | ||
17 | * @lbase: base address for MFC 'left' memory interface | ||
18 | * @lsize: size of the memory reserved for MFC 'left' interface | ||
19 | * | ||
20 | * This function reserves system memory for both MFC device memory | ||
21 | * interfaces and registers it to respective struct device entries as | ||
22 | * coherent memory. | ||
23 | */ | ||
24 | void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, | ||
25 | phys_addr_t lbase, unsigned int lsize); | ||
26 | |||
27 | #endif /* __PLAT_S5P_MFC_H */ | ||
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index e8f2be2d67f2..ee8deef19481 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/regulator/consumer.h> | ||
24 | 25 | ||
25 | #include <plat/regs-adc.h> | 26 | #include <plat/regs-adc.h> |
26 | #include <plat/adc.h> | 27 | #include <plat/adc.h> |
@@ -39,8 +40,9 @@ | |||
39 | */ | 40 | */ |
40 | 41 | ||
41 | enum s3c_cpu_type { | 42 | enum s3c_cpu_type { |
42 | TYPE_S3C24XX, | 43 | TYPE_ADCV1, /* S3C24XX */ |
43 | TYPE_S3C64XX | 44 | TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */ |
45 | TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ | ||
44 | }; | 46 | }; |
45 | 47 | ||
46 | struct s3c_adc_client { | 48 | struct s3c_adc_client { |
@@ -71,6 +73,7 @@ struct adc_device { | |||
71 | unsigned int prescale; | 73 | unsigned int prescale; |
72 | 74 | ||
73 | int irq; | 75 | int irq; |
76 | struct regulator *vdd; | ||
74 | }; | 77 | }; |
75 | 78 | ||
76 | static struct adc_device *adc_dev; | 79 | static struct adc_device *adc_dev; |
@@ -91,6 +94,7 @@ static inline void s3c_adc_select(struct adc_device *adc, | |||
91 | struct s3c_adc_client *client) | 94 | struct s3c_adc_client *client) |
92 | { | 95 | { |
93 | unsigned con = readl(adc->regs + S3C2410_ADCCON); | 96 | unsigned con = readl(adc->regs + S3C2410_ADCCON); |
97 | enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data; | ||
94 | 98 | ||
95 | client->select_cb(client, 1); | 99 | client->select_cb(client, 1); |
96 | 100 | ||
@@ -98,8 +102,12 @@ static inline void s3c_adc_select(struct adc_device *adc, | |||
98 | con &= ~S3C2410_ADCCON_STDBM; | 102 | con &= ~S3C2410_ADCCON_STDBM; |
99 | con &= ~S3C2410_ADCCON_STARTMASK; | 103 | con &= ~S3C2410_ADCCON_STARTMASK; |
100 | 104 | ||
101 | if (!client->is_ts) | 105 | if (!client->is_ts) { |
102 | con |= S3C2410_ADCCON_SELMUX(client->channel); | 106 | if (cpu == TYPE_ADCV3) |
107 | writel(client->channel & 0xf, adc->regs + S5P_ADCMUX); | ||
108 | else | ||
109 | con |= S3C2410_ADCCON_SELMUX(client->channel); | ||
110 | } | ||
103 | 111 | ||
104 | writel(con, adc->regs + S3C2410_ADCCON); | 112 | writel(con, adc->regs + S3C2410_ADCCON); |
105 | } | 113 | } |
@@ -285,8 +293,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) | |||
285 | 293 | ||
286 | client->nr_samples--; | 294 | client->nr_samples--; |
287 | 295 | ||
288 | if (cpu == TYPE_S3C64XX) { | 296 | if (cpu != TYPE_ADCV1) { |
289 | /* S3C64XX ADC resolution is 12-bit */ | 297 | /* S3C64XX/S5P ADC resolution is 12-bit */ |
290 | data0 &= 0xfff; | 298 | data0 &= 0xfff; |
291 | data1 &= 0xfff; | 299 | data1 &= 0xfff; |
292 | } else { | 300 | } else { |
@@ -312,7 +320,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) | |||
312 | } | 320 | } |
313 | 321 | ||
314 | exit: | 322 | exit: |
315 | if (cpu == TYPE_S3C64XX) { | 323 | if (cpu != TYPE_ADCV1) { |
316 | /* Clear ADC interrupt */ | 324 | /* Clear ADC interrupt */ |
317 | writel(0, adc->regs + S3C64XX_ADCCLRINT); | 325 | writel(0, adc->regs + S3C64XX_ADCCLRINT); |
318 | } | 326 | } |
@@ -338,17 +346,24 @@ static int s3c_adc_probe(struct platform_device *pdev) | |||
338 | adc->pdev = pdev; | 346 | adc->pdev = pdev; |
339 | adc->prescale = S3C2410_ADCCON_PRSCVL(49); | 347 | adc->prescale = S3C2410_ADCCON_PRSCVL(49); |
340 | 348 | ||
349 | adc->vdd = regulator_get(dev, "vdd"); | ||
350 | if (IS_ERR(adc->vdd)) { | ||
351 | dev_err(dev, "operating without regulator \"vdd\" .\n"); | ||
352 | ret = PTR_ERR(adc->vdd); | ||
353 | goto err_alloc; | ||
354 | } | ||
355 | |||
341 | adc->irq = platform_get_irq(pdev, 1); | 356 | adc->irq = platform_get_irq(pdev, 1); |
342 | if (adc->irq <= 0) { | 357 | if (adc->irq <= 0) { |
343 | dev_err(dev, "failed to get adc irq\n"); | 358 | dev_err(dev, "failed to get adc irq\n"); |
344 | ret = -ENOENT; | 359 | ret = -ENOENT; |
345 | goto err_alloc; | 360 | goto err_reg; |
346 | } | 361 | } |
347 | 362 | ||
348 | ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc); | 363 | ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc); |
349 | if (ret < 0) { | 364 | if (ret < 0) { |
350 | dev_err(dev, "failed to attach adc irq\n"); | 365 | dev_err(dev, "failed to attach adc irq\n"); |
351 | goto err_alloc; | 366 | goto err_reg; |
352 | } | 367 | } |
353 | 368 | ||
354 | adc->clk = clk_get(dev, "adc"); | 369 | adc->clk = clk_get(dev, "adc"); |
@@ -372,10 +387,14 @@ static int s3c_adc_probe(struct platform_device *pdev) | |||
372 | goto err_clk; | 387 | goto err_clk; |
373 | } | 388 | } |
374 | 389 | ||
390 | ret = regulator_enable(adc->vdd); | ||
391 | if (ret) | ||
392 | goto err_ioremap; | ||
393 | |||
375 | clk_enable(adc->clk); | 394 | clk_enable(adc->clk); |
376 | 395 | ||
377 | tmp = adc->prescale | S3C2410_ADCCON_PRSCEN; | 396 | tmp = adc->prescale | S3C2410_ADCCON_PRSCEN; |
378 | if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) { | 397 | if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) { |
379 | /* Enable 12-bit ADC resolution */ | 398 | /* Enable 12-bit ADC resolution */ |
380 | tmp |= S3C64XX_ADCCON_RESSEL; | 399 | tmp |= S3C64XX_ADCCON_RESSEL; |
381 | } | 400 | } |
@@ -388,12 +407,15 @@ static int s3c_adc_probe(struct platform_device *pdev) | |||
388 | 407 | ||
389 | return 0; | 408 | return 0; |
390 | 409 | ||
410 | err_ioremap: | ||
411 | iounmap(adc->regs); | ||
391 | err_clk: | 412 | err_clk: |
392 | clk_put(adc->clk); | 413 | clk_put(adc->clk); |
393 | 414 | ||
394 | err_irq: | 415 | err_irq: |
395 | free_irq(adc->irq, adc); | 416 | free_irq(adc->irq, adc); |
396 | 417 | err_reg: | |
418 | regulator_put(adc->vdd); | ||
397 | err_alloc: | 419 | err_alloc: |
398 | kfree(adc); | 420 | kfree(adc); |
399 | return ret; | 421 | return ret; |
@@ -406,6 +428,8 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev) | |||
406 | iounmap(adc->regs); | 428 | iounmap(adc->regs); |
407 | free_irq(adc->irq, adc); | 429 | free_irq(adc->irq, adc); |
408 | clk_disable(adc->clk); | 430 | clk_disable(adc->clk); |
431 | regulator_disable(adc->vdd); | ||
432 | regulator_put(adc->vdd); | ||
409 | clk_put(adc->clk); | 433 | clk_put(adc->clk); |
410 | kfree(adc); | 434 | kfree(adc); |
411 | 435 | ||
@@ -413,8 +437,10 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev) | |||
413 | } | 437 | } |
414 | 438 | ||
415 | #ifdef CONFIG_PM | 439 | #ifdef CONFIG_PM |
416 | static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) | 440 | static int s3c_adc_suspend(struct device *dev) |
417 | { | 441 | { |
442 | struct platform_device *pdev = container_of(dev, | ||
443 | struct platform_device, dev); | ||
418 | struct adc_device *adc = platform_get_drvdata(pdev); | 444 | struct adc_device *adc = platform_get_drvdata(pdev); |
419 | unsigned long flags; | 445 | unsigned long flags; |
420 | u32 con; | 446 | u32 con; |
@@ -428,19 +454,30 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) | |||
428 | disable_irq(adc->irq); | 454 | disable_irq(adc->irq); |
429 | spin_unlock_irqrestore(&adc->lock, flags); | 455 | spin_unlock_irqrestore(&adc->lock, flags); |
430 | clk_disable(adc->clk); | 456 | clk_disable(adc->clk); |
457 | regulator_disable(adc->vdd); | ||
431 | 458 | ||
432 | return 0; | 459 | return 0; |
433 | } | 460 | } |
434 | 461 | ||
435 | static int s3c_adc_resume(struct platform_device *pdev) | 462 | static int s3c_adc_resume(struct device *dev) |
436 | { | 463 | { |
464 | struct platform_device *pdev = container_of(dev, | ||
465 | struct platform_device, dev); | ||
437 | struct adc_device *adc = platform_get_drvdata(pdev); | 466 | struct adc_device *adc = platform_get_drvdata(pdev); |
467 | int ret; | ||
468 | unsigned long tmp; | ||
438 | 469 | ||
470 | ret = regulator_enable(adc->vdd); | ||
471 | if (ret) | ||
472 | return ret; | ||
439 | clk_enable(adc->clk); | 473 | clk_enable(adc->clk); |
440 | enable_irq(adc->irq); | 474 | enable_irq(adc->irq); |
441 | 475 | ||
442 | writel(adc->prescale | S3C2410_ADCCON_PRSCEN, | 476 | tmp = adc->prescale | S3C2410_ADCCON_PRSCEN; |
443 | adc->regs + S3C2410_ADCCON); | 477 | /* Enable 12-bit ADC resolution */ |
478 | if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) | ||
479 | tmp |= S3C64XX_ADCCON_RESSEL; | ||
480 | writel(tmp, adc->regs + S3C2410_ADCCON); | ||
444 | 481 | ||
445 | return 0; | 482 | return 0; |
446 | } | 483 | } |
@@ -453,25 +490,32 @@ static int s3c_adc_resume(struct platform_device *pdev) | |||
453 | static struct platform_device_id s3c_adc_driver_ids[] = { | 490 | static struct platform_device_id s3c_adc_driver_ids[] = { |
454 | { | 491 | { |
455 | .name = "s3c24xx-adc", | 492 | .name = "s3c24xx-adc", |
456 | .driver_data = TYPE_S3C24XX, | 493 | .driver_data = TYPE_ADCV1, |
457 | }, { | 494 | }, { |
458 | .name = "s3c64xx-adc", | 495 | .name = "s3c64xx-adc", |
459 | .driver_data = TYPE_S3C64XX, | 496 | .driver_data = TYPE_ADCV2, |
497 | }, { | ||
498 | .name = "samsung-adc-v3", | ||
499 | .driver_data = TYPE_ADCV3, | ||
460 | }, | 500 | }, |
461 | { } | 501 | { } |
462 | }; | 502 | }; |
463 | MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids); | 503 | MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids); |
464 | 504 | ||
505 | static const struct dev_pm_ops adc_pm_ops = { | ||
506 | .suspend = s3c_adc_suspend, | ||
507 | .resume = s3c_adc_resume, | ||
508 | }; | ||
509 | |||
465 | static struct platform_driver s3c_adc_driver = { | 510 | static struct platform_driver s3c_adc_driver = { |
466 | .id_table = s3c_adc_driver_ids, | 511 | .id_table = s3c_adc_driver_ids, |
467 | .driver = { | 512 | .driver = { |
468 | .name = "s3c-adc", | 513 | .name = "s3c-adc", |
469 | .owner = THIS_MODULE, | 514 | .owner = THIS_MODULE, |
515 | .pm = &adc_pm_ops, | ||
470 | }, | 516 | }, |
471 | .probe = s3c_adc_probe, | 517 | .probe = s3c_adc_probe, |
472 | .remove = __devexit_p(s3c_adc_remove), | 518 | .remove = __devexit_p(s3c_adc_remove), |
473 | .suspend = s3c_adc_suspend, | ||
474 | .resume = s3c_adc_resume, | ||
475 | }; | 519 | }; |
476 | 520 | ||
477 | static int __init adc_init(void) | 521 | static int __init adc_init(void) |
@@ -485,4 +529,4 @@ static int __init adc_init(void) | |||
485 | return ret; | 529 | return ret; |
486 | } | 530 | } |
487 | 531 | ||
488 | arch_initcall(adc_init); | 532 | module_init(adc_init); |
diff --git a/arch/arm/plat-samsung/dev-asocdma.c b/arch/arm/plat-samsung/dev-asocdma.c index a068c4f42d56..97e35d3c064d 100644 --- a/arch/arm/plat-samsung/dev-asocdma.c +++ b/arch/arm/plat-samsung/dev-asocdma.c | |||
@@ -23,3 +23,13 @@ struct platform_device samsung_asoc_dma = { | |||
23 | } | 23 | } |
24 | }; | 24 | }; |
25 | EXPORT_SYMBOL(samsung_asoc_dma); | 25 | EXPORT_SYMBOL(samsung_asoc_dma); |
26 | |||
27 | struct platform_device samsung_asoc_idma = { | ||
28 | .name = "samsung-idma", | ||
29 | .id = -1, | ||
30 | .dev = { | ||
31 | .dma_mask = &audio_dmamask, | ||
32 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
33 | } | ||
34 | }; | ||
35 | EXPORT_SYMBOL(samsung_asoc_idma); | ||
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h index a0826ed2f9fe..aa9875f77c40 100644 --- a/arch/arm/plat-samsung/include/plat/audio.h +++ b/arch/arm/plat-samsung/include/plat/audio.h | |||
@@ -44,6 +44,7 @@ struct samsung_i2s { | |||
44 | * Also corresponds to clocks of I2SMOD[10] | 44 | * Also corresponds to clocks of I2SMOD[10] |
45 | */ | 45 | */ |
46 | const char **src_clk; | 46 | const char **src_clk; |
47 | dma_addr_t idma_addr; | ||
47 | }; | 48 | }; |
48 | 49 | ||
49 | /** | 50 | /** |
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index e3b31c26ac3e..24ebb1e1de41 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
@@ -40,6 +40,7 @@ extern struct platform_device s3c64xx_device_spi0; | |||
40 | extern struct platform_device s3c64xx_device_spi1; | 40 | extern struct platform_device s3c64xx_device_spi1; |
41 | 41 | ||
42 | extern struct platform_device samsung_asoc_dma; | 42 | extern struct platform_device samsung_asoc_dma; |
43 | extern struct platform_device samsung_asoc_idma; | ||
43 | 44 | ||
44 | extern struct platform_device s3c64xx_device_pcm0; | 45 | extern struct platform_device s3c64xx_device_pcm0; |
45 | extern struct platform_device s3c64xx_device_pcm1; | 46 | extern struct platform_device s3c64xx_device_pcm1; |
@@ -49,6 +50,7 @@ extern struct platform_device s3c64xx_device_ac97; | |||
49 | extern struct platform_device s3c_device_ts; | 50 | extern struct platform_device s3c_device_ts; |
50 | 51 | ||
51 | extern struct platform_device s3c_device_fb; | 52 | extern struct platform_device s3c_device_fb; |
53 | extern struct platform_device s5p_device_fimd0; | ||
52 | extern struct platform_device s3c_device_ohci; | 54 | extern struct platform_device s3c_device_ohci; |
53 | extern struct platform_device s3c_device_lcd; | 55 | extern struct platform_device s3c_device_lcd; |
54 | extern struct platform_device s3c_device_wdt; | 56 | extern struct platform_device s3c_device_wdt; |
@@ -112,6 +114,7 @@ extern struct platform_device exynos4_device_i2s2; | |||
112 | extern struct platform_device exynos4_device_spdif; | 114 | extern struct platform_device exynos4_device_spdif; |
113 | extern struct platform_device exynos4_device_pd[]; | 115 | extern struct platform_device exynos4_device_pd[]; |
114 | extern struct platform_device exynos4_device_ahci; | 116 | extern struct platform_device exynos4_device_ahci; |
117 | extern struct platform_device exynos4_device_dwmci; | ||
115 | 118 | ||
116 | extern struct platform_device s5p6440_device_pcm; | 119 | extern struct platform_device s5p6440_device_pcm; |
117 | extern struct platform_device s5p6440_device_iis; | 120 | extern struct platform_device s5p6440_device_iis; |
@@ -136,6 +139,9 @@ extern struct platform_device s5p_device_fimc1; | |||
136 | extern struct platform_device s5p_device_fimc2; | 139 | extern struct platform_device s5p_device_fimc2; |
137 | extern struct platform_device s5p_device_fimc3; | 140 | extern struct platform_device s5p_device_fimc3; |
138 | 141 | ||
142 | extern struct platform_device s5p_device_mfc; | ||
143 | extern struct platform_device s5p_device_mfc_l; | ||
144 | extern struct platform_device s5p_device_mfc_r; | ||
139 | extern struct platform_device s5p_device_mipi_csis0; | 145 | extern struct platform_device s5p_device_mipi_csis0; |
140 | extern struct platform_device s5p_device_mipi_csis1; | 146 | extern struct platform_device s5p_device_mipi_csis1; |
141 | 147 | ||
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h index bca383efcf6d..6abcbf139cee 100644 --- a/arch/arm/plat-samsung/include/plat/fb-core.h +++ b/arch/arm/plat-samsung/include/plat/fb-core.h | |||
@@ -26,4 +26,19 @@ static inline void s3c_fb_setname(char *name) | |||
26 | #endif | 26 | #endif |
27 | } | 27 | } |
28 | 28 | ||
29 | /* Re-define device name depending on support. */ | ||
30 | static inline void s5p_fb_setname(int id, char *name) | ||
31 | { | ||
32 | switch (id) { | ||
33 | #ifdef CONFIG_S5P_DEV_FIMD0 | ||
34 | case 0: | ||
35 | s5p_device_fimd0.name = name; | ||
36 | break; | ||
37 | #endif | ||
38 | default: | ||
39 | printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id); | ||
40 | break; | ||
41 | } | ||
42 | } | ||
43 | |||
29 | #endif /* __ASM_PLAT_FB_CORE_H */ | 44 | #endif /* __ASM_PLAT_FB_CORE_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index cb3ca3adc685..01f10e4d00c7 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h | |||
@@ -74,6 +74,14 @@ struct s3c_fb_platdata { | |||
74 | extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); | 74 | extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); |
75 | 75 | ||
76 | /** | 76 | /** |
77 | * s5p_fimd0_set_platdata() - Setup the FB device with platform data. | ||
78 | * @pd: The platform data to set. The data is copied from the passed structure | ||
79 | * so the machine data can mark the data __initdata so that any unused | ||
80 | * machines will end up dumping their data at runtime. | ||
81 | */ | ||
82 | extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd); | ||
83 | |||
84 | /** | ||
77 | * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD | 85 | * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD |
78 | * | 86 | * |
79 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. | 87 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. |
@@ -94,4 +102,11 @@ extern void s5pc100_fb_gpio_setup_24bpp(void); | |||
94 | */ | 102 | */ |
95 | extern void s5pv210_fb_gpio_setup_24bpp(void); | 103 | extern void s5pv210_fb_gpio_setup_24bpp(void); |
96 | 104 | ||
105 | /** | ||
106 | * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0 | ||
107 | * | ||
108 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0. | ||
109 | */ | ||
110 | extern void exynos4_fimd0_gpio_setup_24bpp(void); | ||
111 | |||
97 | #endif /* __PLAT_S3C_FB_H */ | 112 | #endif /* __PLAT_S3C_FB_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h index 7554c4fcddb9..035e8c38d69c 100644 --- a/arch/arm/plat-samsung/include/plat/regs-adc.h +++ b/arch/arm/plat-samsung/include/plat/regs-adc.h | |||
@@ -21,6 +21,7 @@ | |||
21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) | 21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) |
22 | #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) | 22 | #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) |
23 | #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) | 23 | #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) |
24 | #define S5P_ADCMUX S3C2410_ADCREG(0x1C) | ||
24 | #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) | 25 | #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) |
25 | 26 | ||
26 | 27 | ||
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 657405c481d0..3014c7226bd1 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c | |||
@@ -19,6 +19,8 @@ | |||
19 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | 21 | ||
22 | #include <asm/mach/irq.h> | ||
23 | |||
22 | #include <mach/map.h> | 24 | #include <mach/map.h> |
23 | #include <plat/irq-uart.h> | 25 | #include <plat/irq-uart.h> |
24 | #include <plat/regs-serial.h> | 26 | #include <plat/regs-serial.h> |
@@ -30,9 +32,12 @@ | |||
30 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | 32 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) |
31 | { | 33 | { |
32 | struct s3c_uart_irq *uirq = desc->irq_data.handler_data; | 34 | struct s3c_uart_irq *uirq = desc->irq_data.handler_data; |
35 | struct irq_chip *chip = irq_get_chip(irq); | ||
33 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); | 36 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); |
34 | int base = uirq->base_irq; | 37 | int base = uirq->base_irq; |
35 | 38 | ||
39 | chained_irq_enter(chip, desc); | ||
40 | |||
36 | if (pend & (1 << 0)) | 41 | if (pend & (1 << 0)) |
37 | generic_handle_irq(base); | 42 | generic_handle_irq(base); |
38 | if (pend & (1 << 1)) | 43 | if (pend & (1 << 1)) |
@@ -41,6 +46,8 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | |||
41 | generic_handle_irq(base + 2); | 46 | generic_handle_irq(base + 2); |
42 | if (pend & (1 << 3)) | 47 | if (pend & (1 << 3)) |
43 | generic_handle_irq(base + 3); | 48 | generic_handle_irq(base + 3); |
49 | |||
50 | chained_irq_exit(chip, desc); | ||
44 | } | 51 | } |
45 | 52 | ||
46 | static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) | 53 | static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) |
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 5fa1742d019b..ae6f99834cdd 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c | |||
@@ -269,6 +269,7 @@ static int s3c_pm_enter(suspend_state_t state) | |||
269 | /* save all necessary core registers not covered by the drivers */ | 269 | /* save all necessary core registers not covered by the drivers */ |
270 | 270 | ||
271 | s3c_pm_save_gpios(); | 271 | s3c_pm_save_gpios(); |
272 | s3c_pm_saved_gpios(); | ||
272 | s3c_pm_save_uarts(); | 273 | s3c_pm_save_uarts(); |
273 | s3c_pm_save_core(); | 274 | s3c_pm_save_core(); |
274 | 275 | ||
@@ -306,6 +307,7 @@ static int s3c_pm_enter(suspend_state_t state) | |||
306 | s3c_pm_restore_core(); | 307 | s3c_pm_restore_core(); |
307 | s3c_pm_restore_uarts(); | 308 | s3c_pm_restore_uarts(); |
308 | s3c_pm_restore_gpios(); | 309 | s3c_pm_restore_gpios(); |
310 | s3c_pm_restored_gpios(); | ||
309 | 311 | ||
310 | s3c_pm_debug_init(); | 312 | s3c_pm_debug_init(); |
311 | 313 | ||