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authorPaul Walmsley <paul@pwsan.com>2011-02-25 17:39:30 -0500
committerPaul Walmsley <paul@pwsan.com>2011-03-07 22:04:15 -0500
commit4ef70c0694bf428d9f1d4722edaffa1dc5fa39e1 (patch)
tree827937561b0829d62b9d21c33fbe187bf45e5edd /arch
parentec538e30f7eded2c4af8d9184619a3de65bc378e (diff)
OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in mach-omap2/pm*xx.c
These CM_AUTOIDLE bits are now set by the clock code via the common PM code in mach-omap2/pm.c. N.B.: The pm24xx.c code that this patch removes didn't ensure that the CM_AUTOIDLE bits were set for several 2430-only modules, such as GPIO5, MDM_INTC, MMCHS1/2, the modem oscillator clock, and USBHS. Similarly, the pm34xx.c code that this patch removes didn't ensure that the CM_AUTOIDLE bits were set for USIM and the AM3517 UART4. Those cases should now be handled. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/pm24xx.c63
-rw-r--r--arch/arm/mach-omap2/pm34xx.c105
2 files changed, 5 insertions, 163 deletions
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index abe08f49b2ec..96907da1910a 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -379,7 +379,10 @@ static void __init prcm_setup_regs(void)
379 int i, num_mem_banks; 379 int i, num_mem_banks;
380 struct powerdomain *pwrdm; 380 struct powerdomain *pwrdm;
381 381
382 /* Enable autoidle */ 382 /*
383 * Enable autoidle
384 * XXX This should be handled by hwmod code or PRCM init code
385 */
383 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, 386 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
384 OMAP2_PRCM_SYSCONFIG_OFFSET); 387 OMAP2_PRCM_SYSCONFIG_OFFSET);
385 388
@@ -418,64 +421,6 @@ static void __init prcm_setup_regs(void)
418 clkdm_for_each(clkdms_setup, NULL); 421 clkdm_for_each(clkdms_setup, NULL);
419 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); 422 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
420 423
421 /* Enable clock autoidle for all domains */
422 omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
423 OMAP24XX_AUTO_MAILBOXES_MASK |
424 OMAP24XX_AUTO_WDT4_MASK |
425 OMAP2420_AUTO_WDT3_MASK |
426 OMAP24XX_AUTO_MSPRO_MASK |
427 OMAP2420_AUTO_MMC_MASK |
428 OMAP24XX_AUTO_FAC_MASK |
429 OMAP2420_AUTO_EAC_MASK |
430 OMAP24XX_AUTO_HDQ_MASK |
431 OMAP24XX_AUTO_UART2_MASK |
432 OMAP24XX_AUTO_UART1_MASK |
433 OMAP24XX_AUTO_I2C2_MASK |
434 OMAP24XX_AUTO_I2C1_MASK |
435 OMAP24XX_AUTO_MCSPI2_MASK |
436 OMAP24XX_AUTO_MCSPI1_MASK |
437 OMAP24XX_AUTO_MCBSP2_MASK |
438 OMAP24XX_AUTO_MCBSP1_MASK |
439 OMAP24XX_AUTO_GPT12_MASK |
440 OMAP24XX_AUTO_GPT11_MASK |
441 OMAP24XX_AUTO_GPT10_MASK |
442 OMAP24XX_AUTO_GPT9_MASK |
443 OMAP24XX_AUTO_GPT8_MASK |
444 OMAP24XX_AUTO_GPT7_MASK |
445 OMAP24XX_AUTO_GPT6_MASK |
446 OMAP24XX_AUTO_GPT5_MASK |
447 OMAP24XX_AUTO_GPT4_MASK |
448 OMAP24XX_AUTO_GPT3_MASK |
449 OMAP24XX_AUTO_GPT2_MASK |
450 OMAP2420_AUTO_VLYNQ_MASK |
451 OMAP24XX_AUTO_DSS_MASK,
452 CORE_MOD, CM_AUTOIDLE1);
453 omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
454 OMAP24XX_AUTO_SSI_MASK |
455 OMAP24XX_AUTO_USB_MASK,
456 CORE_MOD, CM_AUTOIDLE2);
457 omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
458 OMAP24XX_AUTO_GPMC_MASK |
459 OMAP24XX_AUTO_SDMA_MASK,
460 CORE_MOD, CM_AUTOIDLE3);
461 omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
462 OMAP24XX_AUTO_AES_MASK |
463 OMAP24XX_AUTO_RNG_MASK |
464 OMAP24XX_AUTO_SHA_MASK |
465 OMAP24XX_AUTO_DES_MASK,
466 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
467
468 omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
469 CM_AUTOIDLE);
470
471 omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
472 OMAP24XX_AUTO_WDT1_MASK |
473 OMAP24XX_AUTO_MPU_WDT_MASK |
474 OMAP24XX_AUTO_GPIOS_MASK |
475 OMAP24XX_AUTO_32KSYNC_MASK |
476 OMAP24XX_AUTO_GPT1_MASK,
477 WKUP_MOD, CM_AUTOIDLE);
478
479 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk 424 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
480 * stabilisation */ 425 * stabilisation */
481 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, 426 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a99f296bdbfd..3d6a00e07a5b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -688,14 +688,11 @@ static void __init omap3_d2d_idle(void)
688 688
689static void __init prcm_setup_regs(void) 689static void __init prcm_setup_regs(void)
690{ 690{
691 u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
692 OMAP3630_AUTO_UART4_MASK : 0;
693 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 691 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
694 OMAP3630_EN_UART4_MASK : 0; 692 OMAP3630_EN_UART4_MASK : 0;
695 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 693 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
696 OMAP3630_GRPSEL_UART4_MASK : 0; 694 OMAP3630_GRPSEL_UART4_MASK : 0;
697 695
698
699 /* XXX Reset all wkdeps. This should be done when initializing 696 /* XXX Reset all wkdeps. This should be done when initializing
700 * powerdomains */ 697 * powerdomains */
701 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 698 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
@@ -710,107 +707,7 @@ static void __init prcm_setup_regs(void)
710 } else 707 } else
711 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 708 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
712 709
713 /* 710 /* XXX This should be handled by hwmod code or SCM init code */
714 * Enable interface clock autoidle for all modules.
715 * Note that in the long run this should be done by clockfw
716 */
717 omap2_cm_write_mod_reg(
718 OMAP3430_AUTO_MODEM_MASK |
719 OMAP3430ES2_AUTO_MMC3_MASK |
720 OMAP3430ES2_AUTO_ICR_MASK |
721 OMAP3430_AUTO_AES2_MASK |
722 OMAP3430_AUTO_SHA12_MASK |
723 OMAP3430_AUTO_DES2_MASK |
724 OMAP3430_AUTO_MMC2_MASK |
725 OMAP3430_AUTO_MMC1_MASK |
726 OMAP3430_AUTO_MSPRO_MASK |
727 OMAP3430_AUTO_HDQ_MASK |
728 OMAP3430_AUTO_MCSPI4_MASK |
729 OMAP3430_AUTO_MCSPI3_MASK |
730 OMAP3430_AUTO_MCSPI2_MASK |
731 OMAP3430_AUTO_MCSPI1_MASK |
732 OMAP3430_AUTO_I2C3_MASK |
733 OMAP3430_AUTO_I2C2_MASK |
734 OMAP3430_AUTO_I2C1_MASK |
735 OMAP3430_AUTO_UART2_MASK |
736 OMAP3430_AUTO_UART1_MASK |
737 OMAP3430_AUTO_GPT11_MASK |
738 OMAP3430_AUTO_GPT10_MASK |
739 OMAP3430_AUTO_MCBSP5_MASK |
740 OMAP3430_AUTO_MCBSP1_MASK |
741 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
742 OMAP3430_AUTO_MAILBOXES_MASK |
743 OMAP3430_AUTO_OMAPCTRL_MASK |
744 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
745 OMAP3430_AUTO_HSOTGUSB_MASK |
746 OMAP3430_AUTO_SAD2D_MASK |
747 OMAP3430_AUTO_SSI_MASK,
748 CORE_MOD, CM_AUTOIDLE1);
749
750 omap2_cm_write_mod_reg(
751 OMAP3430_AUTO_PKA_MASK |
752 OMAP3430_AUTO_AES1_MASK |
753 OMAP3430_AUTO_RNG_MASK |
754 OMAP3430_AUTO_SHA11_MASK |
755 OMAP3430_AUTO_DES1_MASK,
756 CORE_MOD, CM_AUTOIDLE2);
757
758 if (omap_rev() > OMAP3430_REV_ES1_0) {
759 omap2_cm_write_mod_reg(
760 OMAP3430_AUTO_MAD2D_MASK |
761 OMAP3430ES2_AUTO_USBTLL_MASK,
762 CORE_MOD, CM_AUTOIDLE3);
763 }
764
765 omap2_cm_write_mod_reg(
766 OMAP3430_AUTO_WDT2_MASK |
767 OMAP3430_AUTO_WDT1_MASK |
768 OMAP3430_AUTO_GPIO1_MASK |
769 OMAP3430_AUTO_32KSYNC_MASK |
770 OMAP3430_AUTO_GPT12_MASK |
771 OMAP3430_AUTO_GPT1_MASK,
772 WKUP_MOD, CM_AUTOIDLE);
773
774 omap2_cm_write_mod_reg(
775 OMAP3430_AUTO_DSS_MASK,
776 OMAP3430_DSS_MOD,
777 CM_AUTOIDLE);
778
779 omap2_cm_write_mod_reg(
780 OMAP3430_AUTO_CAM_MASK,
781 OMAP3430_CAM_MOD,
782 CM_AUTOIDLE);
783
784 omap2_cm_write_mod_reg(
785 omap3630_auto_uart4_mask |
786 OMAP3430_AUTO_GPIO6_MASK |
787 OMAP3430_AUTO_GPIO5_MASK |
788 OMAP3430_AUTO_GPIO4_MASK |
789 OMAP3430_AUTO_GPIO3_MASK |
790 OMAP3430_AUTO_GPIO2_MASK |
791 OMAP3430_AUTO_WDT3_MASK |
792 OMAP3430_AUTO_UART3_MASK |
793 OMAP3430_AUTO_GPT9_MASK |
794 OMAP3430_AUTO_GPT8_MASK |
795 OMAP3430_AUTO_GPT7_MASK |
796 OMAP3430_AUTO_GPT6_MASK |
797 OMAP3430_AUTO_GPT5_MASK |
798 OMAP3430_AUTO_GPT4_MASK |
799 OMAP3430_AUTO_GPT3_MASK |
800 OMAP3430_AUTO_GPT2_MASK |
801 OMAP3430_AUTO_MCBSP4_MASK |
802 OMAP3430_AUTO_MCBSP3_MASK |
803 OMAP3430_AUTO_MCBSP2_MASK,
804 OMAP3430_PER_MOD,
805 CM_AUTOIDLE);
806
807 if (omap_rev() > OMAP3430_REV_ES1_0) {
808 omap2_cm_write_mod_reg(
809 OMAP3430ES2_AUTO_USBHOST_MASK,
810 OMAP3430ES2_USBHOST_MOD,
811 CM_AUTOIDLE);
812 }
813
814 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 711 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
815 712
816 /* 713 /*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 17:54:22 -0500