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authorStefan Agner <stefan@agner.ch>2014-05-14 17:45:58 -0400
committerStephen Warren <swarren@nvidia.com>2014-05-15 14:30:40 -0400
commit446e9c63161519902a251c3670d2fbb455146475 (patch)
treea1615c85688a3f82bcf620561c4eea1955ed4a89 /arch
parente9d68f90df4faed62f16290abdfbc68b32aa2c5e (diff)
ARM: tegra: initial add of Colibri T30
This patch adds the device tree to support Toradex Colibri T30, a computer on module which can be used on different carrier boards. The module consists of a Tegra 30 SoC, two PMIC, DDR3L RAM, eMMC, a LM95245 temperature sensor and an AX88772B USB Ethernet Controller. Furthermore, there is a STMPE811 and SGTL5000 audio codec which are not yet supported. Anything that is not self contained on the module is disabled by default. The device tree for the Evaluation Board includes the modules device tree and enables the supported pheripherials of the carrier board (the Evaluation Board supports almost all of them). Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/tegra30-colibri-eval-v3.dts205
-rw-r--r--arch/arm/boot/dts/tegra30-colibri.dtsi377
3 files changed, 583 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8cc2fad4867f..c1a257a89d15 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -367,6 +367,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
367 tegra30-beaver.dtb \ 367 tegra30-beaver.dtb \
368 tegra30-cardhu-a02.dtb \ 368 tegra30-cardhu-a02.dtb \
369 tegra30-cardhu-a04.dtb \ 369 tegra30-cardhu-a04.dtb \
370 tegra30-colibri-eval-v3.dtb \
370 tegra114-dalmore.dtb \ 371 tegra114-dalmore.dtb \
371 tegra114-roth.dtb \ 372 tegra114-roth.dtb \
372 tegra114-tn7.dtb \ 373 tegra114-tn7.dtb \
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7793abd5bef1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -0,0 +1,205 @@
1/dts-v1/;
2
3#include "tegra30-colibri.dtsi"
4
5/ {
6 model = "Toradex Colibri T30 on Colibri Evaluation Board";
7 compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30";
8
9 aliases {
10 rtc0 = "/i2c@7000c000/rtc@68";
11 rtc1 = "/i2c@7000d000/tps65911@2d";
12 rtc2 = "/rtc@7000e000";
13 };
14
15 host1x@50000000 {
16 dc@54200000 {
17 rgb {
18 status = "okay";
19 nvidia,panel = <&panel>;
20 };
21 };
22 hdmi@54280000 {
23 status = "okay";
24 };
25 };
26
27 serial@70006000 {
28 status = "okay";
29 };
30
31 serial@70006040 {
32 compatible = "nvidia,tegra30-hsuart";
33 status = "okay";
34 };
35
36 serial@70006300 {
37 compatible = "nvidia,tegra30-hsuart";
38 status = "okay";
39 };
40
41 pwm@7000a000 {
42 status = "okay";
43 };
44
45 /*
46 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
47 * board)
48 */
49 i2c@7000c000 {
50 status = "okay";
51 clock-frequency = <100000>;
52
53 /* M41T0M6 real time clock on carrier board */
54 rtc@68 {
55 compatible = "stm,m41t00";
56 reg = <0x68>;
57 };
58 };
59
60 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
61 hdmiddc: i2c@7000c700 {
62 status = "okay";
63 };
64
65 /* SPI1: Colibri SSP */
66 spi@7000d400 {
67 status = "okay";
68 spi-max-frequency = <25000000>;
69 can0: can@0 {
70 compatible = "microchip,mcp2515";
71 reg = <0>;
72 clocks = <&clk16m>;
73 interrupt-parent = <&gpio>;
74 interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
75 spi-max-frequency = <10000000>;
76 };
77 spidev0: spi@1 {
78 compatible = "spidev";
79 reg = <1>;
80 spi-max-frequency = <25000000>;
81 };
82 };
83
84 sdhci@78000200 {
85 status = "okay";
86 bus-width = <4>;
87 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
88 no-1-8-v;
89 };
90
91 /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
92 usb@7d000000 {
93 status = "okay";
94 };
95
96 usb-phy@7d000000 {
97 status = "okay";
98 dr_mode = "otg";
99 vbus-supply = <&usbc_vbus_reg>;
100 };
101
102 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
103 usb@7d008000 {
104 status = "okay";
105 };
106
107 usb-phy@7d008000 {
108 status = "okay";
109 vbus-supply = <&usbh_vbus_reg>;
110 };
111
112 backlight: backlight {
113 compatible = "pwm-backlight";
114
115 /* PWM<A> */
116 pwms = <&pwm 0 5000000>;
117 brightness-levels = <255 128 64 32 16 8 4 0>;
118 default-brightness-level = <6>;
119 /* BL_ON */
120 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
121 };
122
123 clocks {
124 clk16m: clk@1 {
125 compatible = "fixed-clock";
126 reg=<1>;
127 #clock-cells = <0>;
128 clock-frequency = <16000000>;
129 clock-output-names = "clk16m";
130 };
131 };
132
133 gpio-keys {
134 compatible = "gpio-keys";
135
136 power {
137 label = "Power";
138 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
139 linux,code = <KEY_POWER>;
140 debounce-interval = <10>;
141 gpio-key,wakeup;
142 };
143 };
144
145 panel: panel {
146 /*
147 * edt,et057090dhu: EDT 5.7" LCD TFT
148 * edt,et070080dh6: EDT 7.0" LCD TFT
149 */
150 compatible = "edt,et057090dhu", "simple-panel";
151
152 backlight = <&backlight>;
153 };
154
155 pwmleds {
156 compatible = "pwm-leds";
157
158 pwmb {
159 label = "PWM<B>";
160 pwms = <&pwm 1 19600>;
161 max-brightness = <255>;
162 };
163 pwmc {
164 label = "PWM<C>";
165 pwms = <&pwm 2 19600>;
166 max-brightness = <255>;
167 };
168 pwmd {
169 label = "PWM<D>";
170 pwms = <&pwm 3 19600>;
171 max-brightness = <255>;
172 };
173 };
174
175 regulators {
176 sys_5v0_reg: regulator@1 {
177 compatible = "regulator-fixed";
178 reg = <1>;
179 regulator-name = "5v0";
180 regulator-min-microvolt = <5000000>;
181 regulator-max-microvolt = <5000000>;
182 regulator-always-on;
183 };
184
185 usbc_vbus_reg: regulator@2 {
186 compatible = "regulator-fixed";
187 reg = <2>;
188 regulator-name = "usbc_vbus";
189 regulator-min-microvolt = <5000000>;
190 regulator-max-microvolt = <5000000>;
191 vin-supply = <&sys_5v0_reg>;
192 };
193
194 /* USBH_PEN */
195 usbh_vbus_reg: regulator@3 {
196 compatible = "regulator-fixed";
197 reg = <3>;
198 regulator-name = "usbh_vbus";
199 regulator-min-microvolt = <5000000>;
200 regulator-max-microvolt = <5000000>;
201 gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
202 vin-supply = <&sys_5v0_reg>;
203 };
204 };
205};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
new file mode 100644
index 000000000000..bf16f8e65627
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -0,0 +1,377 @@
1#include <dt-bindings/input/input.h>
2#include "tegra30.dtsi"
3
4/*
5 * Toradex Colibri T30 Device Tree
6 * Compatible for Revisions 1.1B/1.1C/1.1D
7 */
8/ {
9 model = "Toradex Colibri T30";
10 compatible = "toradex,colibri_t30", "nvidia,tegra30";
11
12 memory {
13 reg = <0x80000000 0x40000000>;
14 };
15
16 host1x@50000000 {
17 hdmi@54280000 {
18 vdd-supply = <&sys_3v3_reg>;
19 pll-supply = <&vio_reg>;
20
21 nvidia,hpd-gpio =
22 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
23 nvidia,ddc-i2c-bus = <&hdmiddc>;
24 };
25 };
26
27 pinmux@70000868 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 /* Colibri BL_ON */
33 pv2 {
34 nvidia,pins = "pv2";
35 nvidia,function = "rsvd4";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 };
39
40 /* Colibri Backlight PWM<A> */
41 sdmmc3_dat3_pb4 {
42 nvidia,pins = "sdmmc3_dat3_pb4";
43 nvidia,function = "pwm0";
44 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45 nvidia,tristate = <TEGRA_PIN_DISABLE>;
46 };
47
48 /* Colibri CAN_INT */
49 kb_row8_ps0 {
50 nvidia,pins = "kb_row8_ps0";
51 nvidia,function = "kbc";
52 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
53 nvidia,tristate = <TEGRA_PIN_DISABLE>;
54 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 };
56
57 /*
58 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
59 * todays display need DE, disable LCD_M1
60 */
61 lcd_m1_pw1 {
62 nvidia,pins = "lcd_m1_pw1";
63 nvidia,function = "rsvd3";
64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
67 };
68
69 /* Thermal alert, need to be disabled */
70 lcd_dc1_pd2 {
71 nvidia,pins = "lcd_dc1_pd2";
72 nvidia,function = "rsvd3";
73 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76 };
77
78 /* Colibri MMC */
79 kb_row10_ps2 {
80 nvidia,pins = "kb_row10_ps2";
81 nvidia,function = "sdmmc2";
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_DISABLE>;
84 };
85 kb_row11_ps3 {
86 nvidia,pins = "kb_row11_ps3",
87 "kb_row12_ps4",
88 "kb_row13_ps5",
89 "kb_row14_ps6",
90 "kb_row15_ps7";
91 nvidia,function = "sdmmc2";
92 nvidia,pull = <TEGRA_PIN_PULL_UP>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 };
95
96 /* Colibri SSP */
97 ulpi_clk_py0 {
98 nvidia,pins = "ulpi_clk_py0",
99 "ulpi_dir_py1",
100 "ulpi_nxt_py2",
101 "ulpi_stp_py3";
102 nvidia,function = "spi1";
103 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 };
106 sdmmc3_dat6_pd3 {
107 nvidia,pins = "sdmmc3_dat6_pd3",
108 "sdmmc3_dat7_pd4";
109 nvidia,function = "spdif";
110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_ENABLE>;
112 };
113
114 /* Colibri UART_A */
115 ulpi_data0 {
116 nvidia,pins = "ulpi_data0_po1",
117 "ulpi_data1_po2",
118 "ulpi_data2_po3",
119 "ulpi_data3_po4",
120 "ulpi_data4_po5",
121 "ulpi_data5_po6",
122 "ulpi_data6_po7",
123 "ulpi_data7_po0";
124 nvidia,function = "uarta";
125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 };
128
129 /* Colibri UART_B */
130 gmi_a16_pj7 {
131 nvidia,pins = "gmi_a16_pj7",
132 "gmi_a17_pb0",
133 "gmi_a18_pb1",
134 "gmi_a19_pk7";
135 nvidia,function = "uartd";
136 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
138 };
139
140 /* Colibri UART_C */
141 uart2_rxd {
142 nvidia,pins = "uart2_rxd_pc3",
143 "uart2_txd_pc2";
144 nvidia,function = "uartb";
145 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
147 };
148
149 /* eMMC */
150 sdmmc4_clk_pcc4 {
151 nvidia,pins = "sdmmc4_clk_pcc4",
152 "sdmmc4_rst_n_pcc3";
153 nvidia,function = "sdmmc4";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 };
157 sdmmc4_dat0_paa0 {
158 nvidia,pins = "sdmmc4_dat0_paa0",
159 "sdmmc4_dat1_paa1",
160 "sdmmc4_dat2_paa2",
161 "sdmmc4_dat3_paa3",
162 "sdmmc4_dat4_paa4",
163 "sdmmc4_dat5_paa5",
164 "sdmmc4_dat6_paa6",
165 "sdmmc4_dat7_paa7";
166 nvidia,function = "sdmmc4";
167 nvidia,pull = <TEGRA_PIN_PULL_UP>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 };
170 };
171 };
172
173 hdmiddc: i2c@7000c700 {
174 clock-frequency = <100000>;
175 };
176
177 /*
178 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
179 * touch screen controller
180 */
181 i2c@7000d000 {
182 status = "okay";
183 clock-frequency = <100000>;
184
185 pmic: tps65911@2d {
186 compatible = "ti,tps65911";
187 reg = <0x2d>;
188
189 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
190 #interrupt-cells = <2>;
191 interrupt-controller;
192
193 ti,system-power-controller;
194
195 #gpio-cells = <2>;
196 gpio-controller;
197
198 vcc1-supply = <&sys_3v3_reg>;
199 vcc2-supply = <&sys_3v3_reg>;
200 vcc3-supply = <&vio_reg>;
201 vcc4-supply = <&sys_3v3_reg>;
202 vcc5-supply = <&sys_3v3_reg>;
203 vcc6-supply = <&vio_reg>;
204 vcc7-supply = <&sys_5v0_reg>;
205 vccio-supply = <&sys_3v3_reg>;
206
207 regulators {
208 /* SW1: +V1.35_VDDIO_DDR */
209 vdd1_reg: vdd1 {
210 regulator-name = "vddio_ddr_1v35";
211 regulator-min-microvolt = <1350000>;
212 regulator-max-microvolt = <1350000>;
213 regulator-always-on;
214 };
215
216 /* SW2: unused */
217
218 /* SW CTRL: +V1.0_VDD_CPU */
219 vddctrl_reg: vddctrl {
220 regulator-name = "vdd_cpu,vdd_sys";
221 regulator-min-microvolt = <1150000>;
222 regulator-max-microvolt = <1150000>;
223 regulator-always-on;
224 };
225
226 /* SWIO: +V1.8 */
227 vio_reg: vio {
228 regulator-name = "vdd_1v8_gen";
229 regulator-min-microvolt = <1800000>;
230 regulator-max-microvolt = <1800000>;
231 regulator-always-on;
232 };
233
234 /* LDO1: unused */
235
236 /*
237 * EN_+V3.3 switching via FET:
238 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
239 * see also v3_3 fixed supply
240 */
241 ldo2_reg: ldo2 {
242 regulator-name = "en_3v3";
243 regulator-min-microvolt = <3300000>;
244 regulator-max-microvolt = <3300000>;
245 regulator-always-on;
246 };
247
248 /* LDO3: unused */
249
250 /* +V1.2_VDD_RTC */
251 ldo4_reg: ldo4 {
252 regulator-name = "vdd_rtc";
253 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1200000>;
255 regulator-always-on;
256 };
257
258 /*
259 * +V2.8_AVDD_VDAC:
260 * only required for analog RGB
261 */
262 ldo5_reg: ldo5 {
263 regulator-name = "avdd_vdac";
264 regulator-min-microvolt = <2800000>;
265 regulator-max-microvolt = <2800000>;
266 regulator-always-on;
267 };
268
269 /*
270 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
271 * but LDO6 can't set voltage in 50mV
272 * granularity
273 */
274 ldo6_reg: ldo6 {
275 regulator-name = "avdd_plle";
276 regulator-min-microvolt = <1100000>;
277 regulator-max-microvolt = <1100000>;
278 };
279
280 /* +V1.2_AVDD_PLL */
281 ldo7_reg: ldo7 {
282 regulator-name = "avdd_pll";
283 regulator-min-microvolt = <1200000>;
284 regulator-max-microvolt = <1200000>;
285 regulator-always-on;
286 };
287
288 /* +V1.0_VDD_DDR_HS */
289 ldo8_reg: ldo8 {
290 regulator-name = "vdd_ddr_hs";
291 regulator-min-microvolt = <1000000>;
292 regulator-max-microvolt = <1000000>;
293 regulator-always-on;
294 };
295 };
296 };
297
298 /*
299 * LM95245 temperature sensor
300 * Note: OVERT_N directly connected to PMIC PWRDN
301 */
302 temp-sensor@4c {
303 compatible = "national,lm95245";
304 reg = <0x4c>;
305 };
306
307 /* SW: +V1.2_VDD_CORE */
308 tps62362@60 {
309 compatible = "ti,tps62362";
310 reg = <0x60>;
311
312 regulator-name = "tps62362-vout";
313 regulator-min-microvolt = <900000>;
314 regulator-max-microvolt = <1400000>;
315 regulator-boot-on;
316 regulator-always-on;
317 ti,vsel0-state-low;
318 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
319 ti,vsel1-state-low;
320 };
321 };
322
323 pmc@7000e400 {
324 nvidia,invert-interrupt;
325 nvidia,suspend-mode = <1>;
326 nvidia,cpu-pwr-good-time = <5000>;
327 nvidia,cpu-pwr-off-time = <5000>;
328 nvidia,core-pwr-good-time = <3845 3845>;
329 nvidia,core-pwr-off-time = <0>;
330 nvidia,core-power-req-active-high;
331 nvidia,sys-clock-req-active-high;
332 };
333
334 emmc: sdhci@78000600 {
335 status = "okay";
336 bus-width = <8>;
337 non-removable;
338 };
339
340 /* EHCI instance 1: USB2_DP/N -> AX88772B */
341 usb@7d004000 {
342 status = "okay";
343 };
344
345 usb-phy@7d004000 {
346 status = "okay";
347 nvidia,is-wired = <1>;
348 };
349
350 clocks {
351 compatible = "simple-bus";
352 #address-cells = <1>;
353 #size-cells = <0>;
354
355 clk32k_in: clk@0 {
356 compatible = "fixed-clock";
357 reg=<0>;
358 #clock-cells = <0>;
359 clock-frequency = <32768>;
360 };
361 };
362
363 regulators {
364 compatible = "simple-bus";
365 #address-cells = <1>;
366 #size-cells = <0>;
367
368 sys_3v3_reg: regulator@100 {
369 compatible = "regulator-fixed";
370 reg = <100>;
371 regulator-name = "3v3";
372 regulator-min-microvolt = <3300000>;
373 regulator-max-microvolt = <3300000>;
374 regulator-always-on;
375 };
376 };
377};
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-03 11:48:12 -0400