Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc: soc specific changes (part 2) from Olof Johansson:
 "This adds support for the spear13xx platform, which has first been
  under review a long time ago and finally been completed after generic
  spear work has gone into the clock, dt and pinctrl branches.

  Also a number of updates for the samsung socs are part of this branch."

Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much
worse than they are: the exonys5 init code was refactored in commit
fd454997d687 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and
then commit f10590c9836c ("ARM: EXYNOS: add GPC4 bank instance") added a
new gpio chip define and did tiny updates to the init code.

So the conflict diff looks like hell, but it's actually a fairly simple
change.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
  ARM: exynos: fix building with CONFIG_OF disabled
  ARM: EXYNOS: Add AUXDATA for i2c controllers
  ARM: dts: Update device tree source files for EXYNOS5250
  ARM: EXYNOS: Add device tree support for interrupt combiner
  ARM: EXYNOS: Add irq_domain support for interrupt combiner
  ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
  ARM: EXYNOS: update irqs for EXYNOS5250 SoC
  ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
  ARM: EXYNOS: add GPC4 bank instance
  ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
  ARM: EXYNOS: Modify the GIC physical address for static io-mapping
  ARM: EXYNOS: Add watchdog timer clock instance
  pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
  SPEAr: Update MAINTAINERS and Documentation
  SPEAr13xx: Add defconfig
  SPEAr13xx: Add compilation support
  SPEAr13xx: Add dts and dtsi files
  pinctrl: Add SPEAr13xx pinctrl drivers
  pinctrl: SPEAr: Create macro for declaring GPIO PINS
  SPEAr13xx: Add common clock framework support
  ...

65 files changed, 2978 insertions, 177 deletions

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 18194acab493..0298b00fe241 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -186,6 +186,8 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
 machine-$(CONFIG_ARCH_VT8500)           := vt8500
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_MACH_SPEAR1310)        := spear13xx
+machine-$(CONFIG_MACH_SPEAR1340)        := spear13xx
 machine-$(CONFIG_MACH_SPEAR300)         := spear3xx
 machine-$(CONFIG_MACH_SPEAR310)         := spear3xx
 machine-$(CONFIG_MACH_SPEAR320)         := spear3xx
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 399d17b231d2..49945cc1bc7d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -23,4 +23,52 @@
         chosen {
                 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
         };
+
+        i2c@12C60000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                gpios = <&gpb3 0 2 3 0>,
+                        <&gpb3 1 2 3 0>;
+
+                eeprom@50 {
+                        compatible = "samsung,s524ad0xd1";
+                        reg = <0x50>;
+                };
+        };
+
+        i2c@12C70000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                gpios = <&gpb3 2 2 3 0>,
+                        <&gpb3 3 2 3 0>;
+
+                eeprom@51 {
+                        compatible = "samsung,s524ad0xd1";
+                        reg = <0x51>;
+                };
+        };
+
+        i2c@12C80000 {
+                status = "disabled";
+        };
+
+        i2c@12C90000 {
+                status = "disabled";
+        };
+
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+
+        i2c@12CB0000 {
+                status = "disabled";
+        };
+
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+
+        i2c@12CD0000 {
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dfc433599436..5ca0cdb76413 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,11 +23,11 @@
         compatible = "samsung,exynos5250";
         interrupt-parent = <&gic>;
 
-        gic:interrupt-controller@10490000 {
+        gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
-                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+                reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
         };
 
         watchdog {
@@ -42,30 +42,6 @@
                 interrupts = <0 43 0>, <0 44 0>;
         };
 
-        sdhci@12200000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12200000 0x100>;
-                interrupts = <0 75 0>;
-        };
-
-        sdhci@12210000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12210000 0x100>;
-                interrupts = <0 76 0>;
-        };
-
-        sdhci@12220000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12220000 0x100>;
-                interrupts = <0 77 0>;
-        };
-
-        sdhci@12230000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12230000 0x100>;
-                interrupts = <0 78 0>;
-        };
-
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
@@ -94,48 +70,64 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C60000 0x100>;
                 interrupts = <0 56 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12C70000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C70000 0x100>;
                 interrupts = <0 57 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12C80000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C80000 0x100>;
                 interrupts = <0 58 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12C90000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12C90000 0x100>;
                 interrupts = <0 59 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CA0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CA0000 0x100>;
                 interrupts = <0 60 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CB0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CB0000 0x100>;
                 interrupts = <0 61 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CC0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CC0000 0x100>;
                 interrupts = <0 62 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         i2c@12CD0000 {
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x12CD0000 0x100>;
                 interrupts = <0 63 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
         amba {
@@ -157,13 +149,13 @@
                         interrupts = <0 35 0>;
                 };
 
-                mdma0: pdma@10800000 {
+                mdma0: mdma@10800000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
                 };
 
-                mdma1: pdma@11C10000 {
+                mdma1: mdma@11C10000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
@@ -242,6 +234,12 @@
                         #gpio-cells = <4>;
                 };
 
+                gpc4: gpio-controller@114002E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114002E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+
                 gpd0: gpio-controller@11400160 {
                         compatible = "samsung,exynos4-gpio";
                         reg = <0x11400160 0x20>;
@@ -388,19 +386,19 @@
 
                 gpv2: gpio-controller@10D10040 {
                         compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10040 0x20>;
+                        reg = <0x10D10060 0x20>;
                         #gpio-cells = <4>;
                 };
 
                 gpv3: gpio-controller@10D10060 {
                         compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10060 0x20>;
+                        reg = <0x10D10080 0x20>;
                         #gpio-cells = <4>;
                 };
 
                 gpv4: gpio-controller@10D10080 {
                         compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10080 0x20>;
+                        reg = <0x10D100C0 0x20>;
                         #gpio-cells = <4>;
                 };
 
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
new file mode 100644
index 000000000000..8314e4171884
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -0,0 +1,292 @@
+/*
+ * DTS file for SPEAr1310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear1310.dtsi"
+
+/ {
+        model = "ST SPEAr1310 Evaluation Board";
+        compatible = "st,spear1310-evb", "st,spear1310";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@e0700000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                i2c0-pmx {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                i2s1 {
+                                        st,pins = "i2s1_grp";
+                                        st,function = "i2s1";
+                                };
+                                gpio {
+                                        st,pins = "arm_gpio_grp";
+                                        st,function = "arm_gpio";
+                                };
+                                eth {
+                                        st,pins = "gmii_grp";
+                                        st,function = "gmii";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                kbd {
+                                        st,pins = "keyboard_6x6_grp";
+                                        st,function = "keyboard";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_grp";
+                                        st,function = "sdhci";
+                                };
+                                smi-pmx {
+                                        st,pins = "smi_2_chips_grp";
+                                        st,function = "smi";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                rs485 {
+                                        st,pins = "rs485_0_1_tdm_0_1_grp";
+                                        st,function = "rs485_0_1_tdm_0_1";
+                                };
+                                i2c1_2 {
+                                        st,pins = "i2c_1_2_grp";
+                                        st,function = "i2c_1_2";
+                                };
+                                pci {
+                                        st,pins = "pcie0_grp","pcie1_grp",
+                                                "pcie2_grp";
+                                        st,function = "pci";
+                                };
+                                smii {
+                                        st,pins = "smii_0_1_2_grp";
+                                        st,function = "smii_0_1_2";
+                                };
+                                nand {
+                                        st,pins = "nand_8bit_grp",
+                                                "nand_16bit_grp";
+                                        st,function = "nand";
+                                };
+                        };
+                };
+
+                ahci@b1000000 {
+                        status = "okay";
+                };
+
+                cf@b2800000 {
+                        status = "okay";
+                };
+
+                dma@ea800000 {
+                        status = "okay";
+                };
+
+                dma@eb000000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@b0000000 {
+                        status = "okay";
+                };
+
+                gmac0: eth@e2000000 {
+                        status = "okay";
+                };
+
+                sdhci@b3000000 {
+                        status = "okay";
+                };
+
+                smi: flash@ea000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@e6000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xe6000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@e0100000 {
+                        status = "okay";
+                };
+
+                ehci@e4800000 {
+                        status = "okay";
+                };
+
+                ehci@e5800000 {
+                        status = "okay";
+                };
+
+                ohci@e4000000 {
+                        status = "okay";
+                };
+
+                ohci@e5000000 {
+                        status = "okay";
+                };
+
+                apb {
+                        adc@e0080000 {
+                                status = "okay";
+                        };
+
+                        gpio0: gpio@e0600000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@e0680000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@e0280000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@5cd00000 {
+                               status = "okay";
+                        };
+
+                        kbd@e0300000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@e0580000 {
+                               status = "okay";
+                        };
+
+                        serial@e0000000 {
+                               status = "okay";
+                        };
+
+                        wdt@ec800620 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
new file mode 100644
index 000000000000..9e61da404d57
--- /dev/null
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -0,0 +1,184 @@
+/*
+ * DTS file for all SPEAr1310 SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear13xx.dtsi"
+
+/ {
+        compatible = "st,spear1310";
+
+        ahb {
+                ahci@b1000000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb1000000 0x10000>;
+                        interrupts = <0 68 0x4>;
+                        status = "disabled";
+                };
+
+                ahci@b1800000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb1800000 0x10000>;
+                        interrupts = <0 69 0x4>;
+                        status = "disabled";
+                };
+
+                ahci@b4000000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb4000000 0x10000>;
+                        interrupts = <0 70 0x4>;
+                        status = "disabled";
+                };
+
+                gmac1: eth@5c400000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c400000 0x8000>;
+                        interrupts = <0 95 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                gmac2: eth@5c500000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c500000 0x8000>;
+                        interrupts = <0 96 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                gmac3: eth@5c600000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c600000 0x8000>;
+                        interrupts = <0 97 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                gmac4: eth@5c700000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0x5c700000 0x8000>;
+                        interrupts = <0 98 0x4>;
+                        interrupt-names = "macirq";
+                        status = "disabled";
+                };
+
+                spi1: spi@5d400000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x5d400000 0x1000>;
+                        interrupts = <0 99 0x4>;
+                        status = "disabled";
+                };
+
+                apb {
+                        i2c1: i2c@5cd00000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5cd00000 0x1000>;
+                                interrupts = <0 87 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@5ce00000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5ce00000 0x1000>;
+                                interrupts = <0 88 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c3: i2c@5cf00000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5cf00000 0x1000>;
+                                interrupts = <0 89 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c4: i2c@5d000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d000000 0x1000>;
+                                interrupts = <0 90 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c5: i2c@5d100000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d100000 0x1000>;
+                                interrupts = <0 91 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c6: i2c@5d200000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d200000 0x1000>;
+                                interrupts = <0 92 0x4>;
+                                status = "disabled";
+                        };
+
+                        i2c7: i2c@5d300000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0x5d300000 0x1000>;
+                                interrupts = <0 93 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5c800000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5c800000 0x1000>;
+                                interrupts = <0 82 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5c900000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5c900000 0x1000>;
+                                interrupts = <0 83 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5ca00000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5ca00000 0x1000>;
+                                interrupts = <0 84 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5cb00000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5cb00000 0x1000>;
+                                interrupts = <0 85 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@5cc00000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x5cc00000 0x1000>;
+                                interrupts = <0 86 0x4>;
+                                status = "disabled";
+                        };
+
+                        thermal@e07008c4 {
+                                st,thermal-flags = <0x7000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
new file mode 100644
index 000000000000..0d8472e5ab9f
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -0,0 +1,308 @@
+/*
+ * DTS file for SPEAr1340 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear1340.dtsi"
+
+/ {
+        model = "ST SPEAr1340 Evaluation Board";
+        compatible = "st,spear1340-evb", "st,spear1340";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        ahb {
+                pinmux@e0700000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+
+                        state_default: pinmux {
+                                pads_as_gpio {
+                                        st,pins = "pads_as_gpio_grp";
+                                        st,function = "pads_as_gpio";
+                                };
+                                fsmc {
+                                        st,pins = "fsmc_8bit_grp";
+                                        st,function = "fsmc";
+                                };
+                                kbd {
+                                        st,pins = "keyboard_row_col_grp",
+                                                "keyboard_col5_grp";
+                                        st,function = "keyboard";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp", "uart0_enh_grp";
+                                        st,function = "uart0";
+                                };
+                                i2c0-pmx {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                i2c1-pmx {
+                                        st,pins = "i2c1_grp";
+                                        st,function = "i2c1";
+                                };
+                                spdif-in {
+                                        st,pins = "spdif_in_grp";
+                                        st,function = "spdif_in";
+                                };
+                                spdif-out {
+                                        st,pins = "spdif_out_grp";
+                                        st,function = "spdif_out";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp", "ssp0_cs1_grp",
+                                                "ssp0_cs3_grp";
+                                        st,function = "ssp0";
+                                };
+                                pwm {
+                                        st,pins = "pwm2_grp", "pwm3_grp";
+                                        st,function = "pwm";
+                                };
+                                smi-pmx {
+                                        st,pins = "smi_grp";
+                                        st,function = "smi";
+                                };
+                                i2s {
+                                        st,pins = "i2s_in_grp", "i2s_out_grp";
+                                        st,function = "i2s";
+                                };
+                                gmac {
+                                        st,pins = "gmii_grp", "rgmii_grp";
+                                        st,function = "gmac";
+                                };
+                                cam3 {
+                                        st,pins = "cam3_grp";
+                                        st,function = "cam3";
+                                };
+                                cec0 {
+                                        st,pins = "cec0_grp";
+                                        st,function = "cec0";
+                                };
+                                cec1 {
+                                        st,pins = "cec1_grp";
+                                        st,function = "cec1";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_grp";
+                                        st,function = "sdhci";
+                                };
+                                clcd {
+                                        st,pins = "clcd_grp";
+                                        st,function = "clcd";
+                                };
+                                sata {
+                                        st,pins = "sata_grp";
+                                        st,function = "sata";
+                                };
+                        };
+                };
+
+                dma@ea800000 {
+                        status = "okay";
+                };
+
+                dma@eb000000 {
+                        status = "okay";
+                };
+
+                fsmc: flash@b0000000 {
+                        status = "okay";
+                };
+
+                gmac0: eth@e2000000 {
+                        status = "okay";
+                };
+
+                sdhci@b3000000 {
+                        status = "okay";
+                };
+
+                smi: flash@ea000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+
+                        flash@e6000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xe6000000 0x800000>;
+                                st,smi-fast-mode;
+
+                                partition@0 {
+                                        label = "xloader";
+                                        reg = <0x0 0x10000>;
+                                };
+                                partition@10000 {
+                                        label = "u-boot";
+                                        reg = <0x10000 0x40000>;
+                                };
+                                partition@50000 {
+                                        label = "linux";
+                                        reg = <0x50000 0x2c0000>;
+                                };
+                                partition@310000 {
+                                        label = "rootfs";
+                                        reg = <0x310000 0x4f0000>;
+                                };
+                        };
+                };
+
+                spi0: spi@e0100000 {
+                        status = "okay";
+                };
+
+                ehci@e4800000 {
+                        status = "okay";
+                };
+
+                ehci@e5800000 {
+                        status = "okay";
+                };
+
+                ohci@e4000000 {
+                        status = "okay";
+                };
+
+                ohci@e5000000 {
+                        status = "okay";
+                };
+
+                apb {
+                        adc@e0080000 {
+                                status = "okay";
+                        };
+
+                        gpio0: gpio@e0600000 {
+                               status = "okay";
+                        };
+
+                        gpio1: gpio@e0680000 {
+                               status = "okay";
+                        };
+
+                        i2c0: i2c@e0280000 {
+                               status = "okay";
+                        };
+
+                        i2c1: i2c@b4000000 {
+                               status = "okay";
+                        };
+
+                        kbd@e0300000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+
+                        rtc@e0580000 {
+                               status = "okay";
+                        };
+
+                        serial@e0000000 {
+                               status = "okay";
+                        };
+
+                        serial@b4100000 {
+                               status = "okay";
+                        };
+
+                        wdt@ec800620 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
new file mode 100644
index 000000000000..a26fc47a55e8
--- /dev/null
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -0,0 +1,56 @@
+/*
+ * DTS file for all SPEAr1340 SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear13xx.dtsi"
+
+/ {
+        compatible = "st,spear1340";
+
+        ahb {
+                ahci@b1000000 {
+                        compatible = "snps,spear-ahci";
+                        reg = <0xb1000000 0x10000>;
+                        interrupts = <0 72 0x4>;
+                        status = "disabled";
+                };
+
+                spi1: spi@5d400000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x5d400000 0x1000>;
+                        interrupts = <0 99 0x4>;
+                        status = "disabled";
+                };
+
+                apb {
+                        i2c1: i2c@b4000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xb4000000 0x1000>;
+                                interrupts = <0 104 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@b4100000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb4100000 0x1000>;
+                                interrupts = <0 105 0x4>;
+                                status = "disabled";
+                        };
+
+                        thermal@e07008c4 {
+                                st,thermal-flags = <0x2a00>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
new file mode 100644
index 000000000000..1f8e1e1481df
--- /dev/null
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -0,0 +1,262 @@
+/*
+ * DTS file for all SPEAr13xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        gic: interrupt-controller@ec801000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0xec801000 0x1000 >,
+                      < 0xec800100 0x0100 >;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 8 0x04
+                              0 9 0x04>;
+        };
+
+        L2: l2-cache {
+                    compatible = "arm,pl310-cache";
+                    reg = <0xed000000 0x1000>;
+                    cache-unified;
+                    cache-level = <2>;
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyAMA0,115200";
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x50000000 0x50000000 0x10000000
+                          0xb0000000 0xb0000000 0x10000000
+                          0xe0000000 0xe0000000 0x10000000>;
+
+                sdhci@b3000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0xb3000000 0x100>;
+                        interrupts = <0 28 0x4>;
+                        status = "disabled";
+                };
+
+                cf@b2800000 {
+                        compatible = "arasan,cf-spear1340";
+                        reg = <0xb2800000 0x100>;
+                        interrupts = <0 29 0x4>;
+                        status = "disabled";
+                };
+
+                dma@ea800000 {
+                        compatible = "snps,dma-spear1340";
+                        reg = <0xea800000 0x1000>;
+                        interrupts = <0 19 0x4>;
+                        status = "disabled";
+                };
+
+                dma@eb000000 {
+                        compatible = "snps,dma-spear1340";
+                        reg = <0xeb000000 0x1000>;
+                        interrupts = <0 59 0x4>;
+                        status = "disabled";
+                };
+
+                fsmc: flash@b0000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xb0000000 0x1000        /* FSMC Register */
+                               0xb0800000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        interrupts = <0 20 0x4
+                                      0 21 0x4
+                                      0 22 0x4
+                                      0 23 0x4>;
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+
+                gmac0: eth@e2000000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe2000000 0x8000>;
+                        interrupts = <0 23 0x4
+                                      0 24 0x4>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+
+                smi: flash@ea000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xea000000 0x1000>;
+                        interrupts = <0 30 0x4>;
+                        status = "disabled";
+                };
+
+                spi0: spi@e0100000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xe0100000 0x1000>;
+                        interrupts = <0 31 0x4>;
+                        status = "disabled";
+                };
+
+                ehci@e4800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe4800000 0x1000>;
+                        interrupts = <0 64 0x4>;
+                        status = "disabled";
+                };
+
+                ehci@e5800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe5800000 0x1000>;
+                        interrupts = <0 66 0x4>;
+                        status = "disabled";
+                };
+
+                ohci@e4000000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe4000000 0x1000>;
+                        interrupts = <0 65 0x4>;
+                        status = "disabled";
+                };
+
+                ohci@e5000000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe5000000 0x1000>;
+                        interrupts = <0 67 0x4>;
+                        status = "disabled";
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0x50000000 0x50000000 0x10000000
+                                  0xb0000000 0xb0000000 0x10000000
+                                  0xe0000000 0xe0000000 0x10000000>;
+
+                        gpio0: gpio@e0600000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xe0600000 0x1000>;
+                                interrupts = <0 24 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio1: gpio@e0680000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xe0680000 0x1000>;
+                                interrupts = <0 25 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        kbd@e0300000 {
+                                compatible = "st,spear300-kbd";
+                                reg = <0xe0300000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@e0280000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xe0280000 0x1000>;
+                                interrupts = <0 41 0x4>;
+                                status = "disabled";
+                        };
+
+                        rtc@e0580000 {
+                                compatible = "st,spear-rtc";
+                                reg = <0xe0580000 0x1000>;
+                                interrupts = <0 36 0x4>;
+                                status = "disabled";
+                        };
+
+                        serial@e0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xe0000000 0x1000>;
+                                interrupts = <0 36 0x4>;
+                                status = "disabled";
+                        };
+
+                        adc@e0080000 {
+                                compatible = "st,spear600-adc";
+                                reg = <0xe0080000 0x1000>;
+                                interrupts = <0 44 0x4>;
+                                status = "disabled";
+                        };
+
+                        timer@e0380000 {
+                                compatible = "st,spear-timer";
+                                reg = <0xe0380000 0x400>;
+                                interrupts = <0 37 0x4>;
+                        };
+
+                        timer@ec800600 {
+                                compatible = "arm,cortex-a9-twd-timer";
+                                reg = <0xec800600 0x20>;
+                                interrupts = <1 13 0x301>;
+                        };
+
+                        wdt@ec800620 {
+                                compatible = "arm,cortex-a9-twd-wdt";
+                                reg = <0xec800620 0x20>;
+                                status = "disabled";
+                        };
+
+                        thermal@e07008c4 {
+                                compatible = "st,thermal-spear1340";
+                                reg = <0xe07008c4 0x4>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
new file mode 100644
index 000000000000..1fdb82694ca2
--- /dev/null
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -0,0 +1,95 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_MACH_SPEAR1310=y
+CONFIG_MACH_SPEAR1340=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_PATA_ARASAN_CF=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_MPCORE_WATCHDOG=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_DMAC=y
+CONFIG_DMATEST=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e3cfd5fd7dd5..43ebe9094411 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select SAMSUNG_DMADEV
         help
           Enable EXYNOS5250 SoC support
 
@@ -70,7 +71,7 @@ config EXYNOS4_MCT
         help
           Use MCT (Multi Core Timer) as kernel timers
 
-config EXYNOS4_DEV_DMA
+config EXYNOS_DEV_DMA
         bool
         help
           Compile in amba device definitions for DMA controller
@@ -80,6 +81,11 @@ config EXYNOS4_DEV_AHCI
         help
           Compile in platform device definitions for AHCI
 
+config EXYNOS_DEV_DRM
+        bool
+        help
+          Compile in platform device definitions for core DRM device
+
 config EXYNOS4_SETUP_FIMD0
         bool
         help
@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY
         help
           Common setup code for USB PHY controller
 
-config EXYNOS4_SETUP_SPI
+config EXYNOS_SETUP_SPI
         bool
         help
           Common setup code for SPI GPIO configurations.
@@ -224,7 +230,7 @@ config MACH_ARMLEX4210
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
         select EXYNOS4_DEV_AHCI
-        select EXYNOS4_DEV_DMA
+        select EXYNOS_DEV_DMA
         select EXYNOS4_SETUP_SDHCI
         help
           Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -362,7 +368,7 @@ config MACH_SMDK4212
         select SAMSUNG_DEV_KEYPAD
         select SAMSUNG_DEV_PWM
         select EXYNOS_DEV_SYSMMU
-        select EXYNOS4_DEV_DMA
+        select EXYNOS_DEV_DMA
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C7
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 272625231c73..440a637c76f1 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 obj-y                                   += dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
-obj-$(CONFIG_EXYNOS_DEV_SYSMMU)         += dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)         += dev-dwmci.o
-obj-$(CONFIG_EXYNOS4_DEV_DMA)           += dma.o
+obj-$(CONFIG_EXYNOS_DEV_DMA)            += dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
+obj-$(CONFIG_EXYNOS_DEV_DRM)            += dev-drm.o
+obj-$(CONFIG_EXYNOS_DEV_SYSMMU)         += dev-sysmmu.o
 
 obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7)	+= setup-i2c7.o
 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)     += setup-usb-phy.o
-obj-$(CONFIG_EXYNOS4_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_EXYNOS_SETUP_SPI)          += setup-spi.o
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index b9862e22bf10..31bd181b0514 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,2 +1,5 @@
    zreladdr-y   += 0x40008000
 params_phys-y   := 0x40000100
+
+dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
+dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 98823120570e..da397d21bbcf 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = {
                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
                 .enable         = exynos4212_clk_ip_isp1_ctrl,
                 .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "flite",
+                .devname        = "exynos-fimc-lite.0",
+                .enable         = exynos4212_clk_ip_isp0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "flite",
+                .devname        = "exynos-fimc-lite.1",
+                .enable         = exynos4212_clk_ip_isp0_ctrl,
+                .ctrlbit        = (1 << 3),
         }
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 9f87a07b0bf8..5aa460b01fdf 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+        .clk    = {
+                .name           = "mout_bpll_fout",
+        },
+        .sources = &clk_src_bpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_list[] = {
+        [0] = &clk_fin_bpll,
+        [1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll = {
+        .sources        = exynos5_clk_src_bpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
         .clk    = {
                 .name           = "mout_bpll",
         },
-        .sources = &clk_src_bpll,
+        .sources = &exynos5_clk_src_bpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 };
 
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+        .clk    = {
+                .name           = "mout_mpll_fout",
+        },
+        .sources = &clk_src_mpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll = {
+        .sources        = exynos5_clk_src_mpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
         .clk = {
                 .name           = "mout_mpll",
         },
-        .sources = &clk_src_mpll,
+        .sources = &exynos5_clk_src_mpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };
 
@@ -474,6 +510,11 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_peris_ctrl,
                 .ctrlbit        = (1 << 20),
         }, {
+                .name           = "watchdog",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peris_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
                 .name           = "hsmmc",
                 .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos5_clk_aclk_200.clk,
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_mout_apll,
         &exynos5_clk_sclk_apll,
         &exynos5_clk_mout_bpll,
+        &exynos5_clk_mout_bpll_fout,
         &exynos5_clk_mout_bpll_user,
         &exynos5_clk_mout_cpll,
         &exynos5_clk_mout_epll,
         &exynos5_clk_mout_mpll,
+        &exynos5_clk_mout_mpll_fout,
         &exynos5_clk_mout_mpll_user,
         &exynos5_clk_vpllsrc,
         &exynos5_clk_sclk_vpll,
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
         &exynos5_clk_sclk_hdmi27m,
         &exynos5_clk_sclk_hdmiphy,
         &clk_fout_bpll,
+        &clk_fout_bpll_div2,
         &clk_fout_cpll,
+        &clk_fout_mpll_div2,
         &exynos5_clk_armclk,
 };
 
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
         clk_fout_apll.ops = &exynos5_fout_apll_ops;
         clk_fout_bpll.rate = bpll;
+        clk_fout_bpll_div2.rate = bpll >> 1;
         clk_fout_cpll.rate = cpll;
         clk_fout_mpll.rate = mpll;
+        clk_fout_mpll_div2.rate = mpll >> 1;
         clk_fout_epll.rate = epll;
         clk_fout_vpll.rate = vpll;
 
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5ccd6e80a607..49134711f4c6 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,9 @@
 #include <linux/serial_core.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/export.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
         }, {
                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
-                .length         = SZ_64K,
+                .length         = SZ_8K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
-                .length         = SZ_64K,
+                .length         = SZ_4K,
                 .type           = MT_DEVICE,
         },
 };
@@ -399,6 +402,7 @@ struct combiner_chip_data {
         void __iomem *base;
 };
 
+static struct irq_domain *combiner_irq_domain;
 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 
 static inline void __iomem *combiner_base(struct irq_data *data)
@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
 
 static void combiner_mask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (data->irq % 32);
+        u32 mask = 1 << (data->hwirq % 32);
 
         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (data->irq % 32);
+        u32 mask = 1 << (data->hwirq % 32);
 
         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
@@ -474,49 +478,131 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 }
 
-static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
-                          unsigned int irq_start)
+static void __init combiner_init_one(unsigned int combiner_nr,
+                                     void __iomem *base)
 {
-        unsigned int i;
-        unsigned int max_nr;
-
-        if (soc_is_exynos5250())
-                max_nr = EXYNOS5_MAX_COMBINER_NR;
-        else
-                max_nr = EXYNOS4_MAX_COMBINER_NR;
-
-        if (combiner_nr >= max_nr)
-                BUG();
-
         combiner_data[combiner_nr].base = base;
-        combiner_data[combiner_nr].irq_offset = irq_start;
+        combiner_data[combiner_nr].irq_offset = irq_find_mapping(
+                combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 
         /* Disable all interrupts */
-
         __raw_writel(combiner_data[combiner_nr].irq_mask,
                      base + COMBINER_ENABLE_CLEAR);
+}
+
+#ifdef CONFIG_OF
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+                                     struct device_node *controller,
+                                     const u32 *intspec, unsigned int intsize,
+                                     unsigned long *out_hwirq,
+                                     unsigned int *out_type)
+{
+        if (d->of_node != controller)
+                return -EINVAL;
+
+        if (intsize < 2)
+                return -EINVAL;
+
+        *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
+        *out_type = 0;
+
+        return 0;
+}
+#else
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+                                     struct device_node *controller,
+                                     const u32 *intspec, unsigned int intsize,
+                                     unsigned long *out_hwirq,
+                                     unsigned int *out_type)
+{
+        return -EINVAL;
+}
+#endif
+
+static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                                   irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
+        irq_set_chip_data(irq, &combiner_data[hw >> 3]);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 
-        /* Setup the Linux IRQ subsystem */
+        return 0;
+}
+
+static struct irq_domain_ops combiner_irq_domain_ops = {
+        .xlate  = combiner_irq_domain_xlate,
+        .map    = combiner_irq_domain_map,
+};
 
-        for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
-                                + MAX_IRQ_IN_COMBINER; i++) {
-                irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
-                irq_set_chip_data(i, &combiner_data[combiner_nr]);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+{
+        int i, irq, irq_base;
+        unsigned int max_nr, nr_irq;
+
+        if (np) {
+                if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
+                        pr_warning("%s: number of combiners not specified, "
+                                "setting default as %d.\n",
+                                __func__, EXYNOS4_MAX_COMBINER_NR);
+                        max_nr = EXYNOS4_MAX_COMBINER_NR;
+                }
+        } else {
+                max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+                                                EXYNOS4_MAX_COMBINER_NR;
+        }
+        nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
+
+        irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
+        if (IS_ERR_VALUE(irq_base)) {
+                irq_base = COMBINER_IRQ(0, 0);
+                pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
+        }
+
+        combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
+                                &combiner_irq_domain_ops, &combiner_data);
+        if (WARN_ON(!combiner_irq_domain)) {
+                pr_warning("%s: irq domain init failed\n", __func__);
+                return;
+        }
+
+        for (i = 0; i < max_nr; i++) {
+                combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
+                irq = IRQ_SPI(i);
+#ifdef CONFIG_OF
+                if (np)
+                        irq = irq_of_parse_and_map(np, i);
+#endif
+                combiner_cascade_irq(i, irq);
         }
 }
 
 #ifdef CONFIG_OF
+int __init combiner_of_init(struct device_node *np, struct device_node *parent)
+{
+        void __iomem *combiner_base;
+
+        combiner_base = of_iomap(np, 0);
+        if (!combiner_base) {
+                pr_err("%s: failed to map combiner registers\n", __func__);
+                return -ENXIO;
+        }
+
+        combiner_init(combiner_base, np);
+
+        return 0;
+}
+
 static const struct of_device_id exynos4_dt_irq_match[] = {
         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "samsung,exynos4210-combiner",
+                        .data = combiner_of_init, },
         {},
 };
 #endif
 
 void __init exynos4_init_irq(void)
 {
-        int irq;
         unsigned int gic_bank_offset;
 
         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -528,12 +614,8 @@ void __init exynos4_init_irq(void)
                 of_irq_init(exynos4_dt_irq_match);
 #endif
 
-        for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
-
-                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                                COMBINER_IRQ(irq, 0));
-                combiner_cascade_irq(irq, IRQ_SPI(irq));
-        }
+        if (!of_have_populated_dt())
+                combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
         /*
          * The parameters of s5p_init_irq() are for VIC init.
@@ -545,18 +627,9 @@ void __init exynos4_init_irq(void)
 
 void __init exynos5_init_irq(void)
 {
-        int irq;
-
 #ifdef CONFIG_OF
         of_irq_init(exynos4_dt_irq_match);
 #endif
-
-        for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
-                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                                COMBINER_IRQ(irq, 0));
-                combiner_cascade_irq(irq, IRQ_SPI(irq));
-        }
-
         /*
          * The parameters of s5p_init_irq() are for VIC init.
          * Theses parameters should be NULL and 0 because EXYNOS4
@@ -565,30 +638,18 @@ void __init exynos5_init_irq(void)
         s5p_init_irq(NULL, 0);
 }
 
-struct bus_type exynos4_subsys = {
-        .name           = "exynos4-core",
-        .dev_name       = "exynos4-core",
-};
-
-struct bus_type exynos5_subsys = {
-        .name           = "exynos5-core",
-        .dev_name       = "exynos5-core",
+struct bus_type exynos_subsys = {
+        .name           = "exynos-core",
+        .dev_name       = "exynos-core",
 };
 
 static struct device exynos4_dev = {
-        .bus    = &exynos4_subsys,
-};
-
-static struct device exynos5_dev = {
-        .bus    = &exynos5_subsys,
+        .bus    = &exynos_subsys,
 };
 
 static int __init exynos_core_init(void)
 {
-        if (soc_is_exynos5250())
-                return subsys_system_register(&exynos5_subsys, NULL);
-        else
-                return subsys_system_register(&exynos4_subsys, NULL);
+        return subsys_system_register(&exynos_subsys, NULL);
 }
 core_initcall(exynos_core_init);
 
@@ -675,10 +736,7 @@ static int __init exynos_init(void)
 {
         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-        if (soc_is_exynos5250())
-                return device_register(&exynos5_dev);
-        else
-                return device_register(&exynos4_dev);
+        return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
new file mode 100644
index 000000000000..17c9c6ecc2e0
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-drm.c
@@ -0,0 +1,29 @@
+/*
+ * linux/arch/arm/mach-exynos/dev-drm.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - core DRM device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <plat/devs.h>
+
+static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_drm = {
+        .name   = "exynos-drm",
+        .dev    = {
+                .dma_mask               = &exynos_drm_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 69aaa4503205..f60b66dbcf84 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
         DMACH_MIPI_HSI5,
 };
 
-struct dma_pl330_platdata exynos4_pdma0_pdata;
+static u8 exynos5250_pdma0_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM2_RX,
+        DMACH_PCM2_TX,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_SLIMBUS0_RX,
+        DMACH_SLIMBUS0_TX,
+        DMACH_SLIMBUS2_RX,
+        DMACH_SLIMBUS2_TX,
+        DMACH_SLIMBUS4_RX,
+        DMACH_SLIMBUS4_TX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
+        DMACH_MIPI_HSI0,
+        DMACH_MIPI_HSI2,
+        DMACH_MIPI_HSI4,
+        DMACH_MIPI_HSI6,
+};
+
+static struct dma_pl330_platdata exynos_pdma0_pdata;
 
-static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
-        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
+static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
+        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
 
 static u8 exynos4210_pdma1_peri[] = {
         DMACH_PCM0_RX,
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
         DMACH_MIPI_HSI7,
 };
 
-static struct dma_pl330_platdata exynos4_pdma1_pdata;
+static u8 exynos5250_pdma1_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM1_TX,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_PWM,
+        DMACH_SPDIF,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_SLIMBUS1_RX,
+        DMACH_SLIMBUS1_TX,
+        DMACH_SLIMBUS3_RX,
+        DMACH_SLIMBUS3_TX,
+        DMACH_SLIMBUS5_RX,
+        DMACH_SLIMBUS5_TX,
+        DMACH_SLIMBUS0AUX_RX,
+        DMACH_SLIMBUS0AUX_TX,
+        DMACH_DISP1,
+        DMACH_MIPI_HSI1,
+        DMACH_MIPI_HSI3,
+        DMACH_MIPI_HSI5,
+        DMACH_MIPI_HSI7,
+};
 
-static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
-        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
+static struct dma_pl330_platdata exynos_pdma1_pdata;
+
+static AMBA_AHB_DEVICE(exynos_pdma1,  "dma-pl330.1", 0x00041330,
+        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
 
 static u8 mdma_peri[] = {
         DMACH_MTOM_0,
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
         DMACH_MTOM_7,
 };
 
-static struct dma_pl330_platdata exynos4_mdma1_pdata = {
+static struct dma_pl330_platdata exynos_mdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(mdma_peri),
         .peri_id = mdma_peri,
 };
 
-static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
-        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
+static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
+        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
 
-static int __init exynos4_dma_init(void)
+static int __init exynos_dma_init(void)
 {
         if (of_have_populated_dt())
                 return 0;
 
         if (soc_is_exynos4210()) {
-                exynos4_pdma0_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4210_pdma0_peri);
-                exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
-                exynos4_pdma1_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+                exynos_pdma1_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4210_pdma1_peri);
-                exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+                exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                exynos4_pdma0_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4212_pdma0_peri);
-                exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
-                exynos4_pdma1_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+                exynos_pdma1_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4212_pdma1_peri);
-                exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+                exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+        } else if (soc_is_exynos5250()) {
+                exynos_pdma0_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos5250_pdma0_peri);
+                exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
+                exynos_pdma1_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos5250_pdma1_peri);
+                exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
+
+                exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
+                exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
+                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
+                exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
+                exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
+                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
+                exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
+                exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
+                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
         }
 
-        dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
-        amba_device_register(&exynos4_pdma0_device, &iomem_resource);
+        dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
+        amba_device_register(&exynos_pdma0_device, &iomem_resource);
 
-        dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
-        amba_device_register(&exynos4_pdma1_device, &iomem_resource);
+        dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
+        amba_device_register(&exynos_pdma1_device, &iomem_resource);
 
-        dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
-        amba_device_register(&exynos4_mdma1_device, &iomem_resource);
+        dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
+        amba_device_register(&exynos_mdma1_device, &iomem_resource);
 
         return 0;
 }
-arch_initcall(exynos4_dma_init);
+arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index d7498afe036a..eb24f1eb8e3b 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 #define EXYNOS5_GPIO_B2_NR      (4)
 #define EXYNOS5_GPIO_B3_NR      (4)
 #define EXYNOS5_GPIO_C0_NR      (7)
-#define EXYNOS5_GPIO_C1_NR      (7)
+#define EXYNOS5_GPIO_C1_NR      (4)
 #define EXYNOS5_GPIO_C2_NR      (7)
 #define EXYNOS5_GPIO_C3_NR      (7)
-#define EXYNOS5_GPIO_D0_NR      (8)
+#define EXYNOS5_GPIO_C4_NR      (7)
+#define EXYNOS5_GPIO_D0_NR      (4)
 #define EXYNOS5_GPIO_D1_NR      (8)
 #define EXYNOS5_GPIO_Y0_NR      (6)
 #define EXYNOS5_GPIO_Y1_NR      (4)
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
         EXYNOS5_GPIO_C1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
         EXYNOS5_GPIO_C2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
         EXYNOS5_GPIO_C3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+        EXYNOS5_GPIO_C4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
         EXYNOS5_GPIO_D1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
         EXYNOS5_GPIO_Y0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
         EXYNOS5_GPIO_Y1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 #define EXYNOS5_GPC1(_nr)       (EXYNOS5_GPIO_C1_START + (_nr))
 #define EXYNOS5_GPC2(_nr)       (EXYNOS5_GPIO_C2_START + (_nr))
 #define EXYNOS5_GPC3(_nr)       (EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)       (EXYNOS5_GPIO_C4_START + (_nr))
 #define EXYNOS5_GPD0(_nr)       (EXYNOS5_GPIO_D0_START + (_nr))
 #define EXYNOS5_GPD1(_nr)       (EXYNOS5_GPIO_D1_START + (_nr))
 #define EXYNOS5_GPY0(_nr)       (EXYNOS5_GPIO_Y0_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index ddde8f3a24d4..7a4b4789eb72 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -287,6 +287,7 @@
 #define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
 #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
 #define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
+#define EXYNOS5_IRQ_WDT_IOP             IRQ_SPI(83)
 #define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
 #define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
 #define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
@@ -295,8 +296,8 @@
 #define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
 #define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
 #define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
-#define EXYNOS5_IRQ_SFMC0               IRQ_SPI(92)
-#define EXYNOS5_IRQ_SFMC1               IRQ_SPI(93)
+#define EXYNOS5_IRQ_EFNFCON_0           IRQ_SPI(92)
+#define EXYNOS5_IRQ_EFNFCON_1           IRQ_SPI(93)
 #define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
 #define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
 #define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
@@ -310,7 +311,7 @@
 #define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
 #define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
 #define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
-
+#define EXYNOS5_IRQ_ADC1                IRQ_SPI(107)
 #define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
 #define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
 #define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
@@ -319,8 +320,9 @@
 #define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
-#define EXYNOS5_IRQ_NFCON               IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -328,7 +330,6 @@
 #define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
 
 #define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
-#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(1, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
 #define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
@@ -339,6 +340,8 @@
 #define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
 #define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
 
+#define EXYNOS5_IRQ_SYSMMU_LITE2_0      COMBINER_IRQ(3, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE2_1      COMBINER_IRQ(3, 1)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
 #define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
@@ -362,8 +365,8 @@
 
 #define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
 #define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(6, 3)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
 #define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
@@ -375,11 +378,9 @@
 #define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
 #define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
 #define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_0       COMBINER_IRQ(7, 6)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_1       COMBINER_IRQ(7, 7)
 
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(8, 6)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(8, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
 #define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
@@ -395,17 +396,24 @@
 #define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
 #define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
 
+#define EXYNOS5_IRQ_MDMA1_ABORT         COMBINER_IRQ(13, 1)
+
+#define EXYNOS5_IRQ_MDMA0_ABORT         COMBINER_IRQ(15, 3)
+
 #define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
 #define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
 #define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
 
+#define EXYNOS5_IRQ_ARMIOP_GIC          COMBINER_IRQ(19, 0)
+#define EXYNOS5_IRQ_ARMISP_GIC          COMBINER_IRQ(19, 1)
+#define EXYNOS5_IRQ_IOP_GIC             COMBINER_IRQ(19, 3)
+#define EXYNOS5_IRQ_ISP_GIC             COMBINER_IRQ(19, 4)
+
+#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
+
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0              COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1              COMBINER_IRQ(23, 2)
 #define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
 #define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
-#define EXYNOS5_IRQ_MCT_G2              COMBINER_IRQ(23, 5)
-#define EXYNOS5_IRQ_MCT_G3              COMBINER_IRQ(23, 6)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
@@ -436,7 +444,7 @@
 
 #define EXYNOS5_MAX_COMBINER_NR         32
 
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     13
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     14
 #define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
 #define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
 #define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 2196af2d8218..ca4aa89aa46b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -34,6 +34,9 @@
 
 #define EXYNOS4_PA_JPEG                 0x11840000
 
+/* x = 0...1 */
+#define EXYNOS4_PA_FIMC_LITE(x)         (0x12390000 + ((x) * 0x10000))
+
 #define EXYNOS4_PA_G2D                  0x12800000
 
 #define EXYNOS4_PA_I2S0                 0x03830000
@@ -78,8 +81,8 @@
 
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
-#define EXYNOS5_PA_GIC_CPU              0x10480000
-#define EXYNOS5_PA_GIC_DIST             0x10490000
+#define EXYNOS5_PA_GIC_CPU              0x10482000
+#define EXYNOS5_PA_GIC_DIST             0x10481000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index dba83e91f0fd..b78b5f3ad9c0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -322,6 +322,8 @@
 #define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
 
+#define EXYNOS5_PLL_DIV2_SEL                    EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
 
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d457d052a420..4dbb8629b200 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -180,7 +180,7 @@
 
 #define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
 
-/* Only for EXYNOS4212 */
+/* Only for EXYNOS4x12 */
 #define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      S5P_PMUREG(0x1058)
@@ -221,4 +221,12 @@
 #define S5P_SECSS_MEM_OPTION                    S5P_PMUREG(0x2EC8)
 #define S5P_ROTATOR_MEM_OPTION                  S5P_PMUREG(0x2F48)
 
+/* Only for EXYNOS4412 */
+#define S5P_ARM_CORE2_LOWPWR                    S5P_PMUREG(0x1020)
+#define S5P_DIS_IRQ_CORE2                       S5P_PMUREG(0x1024)
+#define S5P_DIS_IRQ_CENTRAL2                    S5P_PMUREG(0x1028)
+#define S5P_ARM_CORE3_LOWPWR                    S5P_PMUREG(0x1030)
+#define S5P_DIS_IRQ_CORE3                       S5P_PMUREG(0x1034)
+#define S5P_DIS_IRQ_CENTRAL3                    S5P_PMUREG(0x1038)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
index 576efdf6d091..c71a5fba6a84 100644
--- a/arch/arm/mach-exynos/include/mach/spi-clocks.h
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -11,6 +11,6 @@
 #define __ASM_ARCH_SPI_CLKS_H __FILE__
 
 /* Must source from SCLK_SPI */
-#define EXYNOS4_SPI_SRCCLK_SCLK         0
+#define EXYNOS_SPI_SRCCLK_SCLK          0
 
 #endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 4711c8920e37..cf5d2228e998 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                 "exynos4210-uart.2", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
                                 "exynos4210-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+                                "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+                                "s3c2440-i2c.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 897d9a9cf226..b601fb8a408b 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
+        int mct_lx_irq;
 
         mevt = this_cpu_ptr(&percpu_mct_tick);
         mevt->evt = evt;
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
+                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+                                                EXYNOS5_IRQ_MCT_L0;
                         mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = EXYNOS4_IRQ_MCT_L0;
-                        setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
+                        evt->irq = mct_lx_irq;
+                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
                 } else {
+                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+                                                EXYNOS5_IRQ_MCT_L1;
                         mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = EXYNOS4_IRQ_MCT_L1;
-                        setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
-                        irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+                        evt->irq = mct_lx_irq;
+                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
                 }
         } else {
                 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
 
 static void __init exynos4_timer_init(void)
 {
-        if (soc_is_exynos4210())
+        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
                 mct_int_type = MCT_INT_SPI;
         else
                 mct_int_type = MCT_INT_PPI;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 428cfeb57724..563dea9a6dbb 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void)
 
 static struct subsys_interface exynos4_pm_interface = {
         .name           = "exynos4_pm",
-        .subsys         = &exynos4_subsys,
+        .subsys         = &exynos_subsys,
         .add_dev        = exynos4_pm_add,
 };
 
@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
-        if (soc_is_exynos4212()) {
+        if (soc_is_exynos4212() || soc_is_exynos4412()) {
                 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
                 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
                          S5P_USE_STANDBYWFE_ISP_ARM);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bba48f5c3e8f..77c6815eebee 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
+static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
+        { S5P_ARM_CORE2_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE2,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL2,                 { 0x0, 0x0, 0x0 } },
+        { S5P_ARM_CORE3_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE3,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL3,                 { 0x0, 0x0, 0x0 } },
+        { PMU_TABLE_END,},
+};
+
 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
 {
         unsigned int i;
@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
         for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
                 __raw_writel(exynos4_pmu_config[i].val[mode],
                                 exynos4_pmu_config[i].reg);
+
+        if (soc_is_exynos4412()) {
+                for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
+                        __raw_writel(exynos4412_pmu_config[i].val[mode],
+                                exynos4412_pmu_config[i].reg);
+        }
 }
 
 static int __init exynos4_pmu_init(void)
@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
         if (soc_is_exynos4210()) {
                 exynos4_pmu_config = exynos4210_pmu_config;
                 pr_info("EXYNOS4210 PMU Initialize\n");
-        } else if (soc_is_exynos4212()) {
-                exynos4_pmu_config = exynos4212_pmu_config;
-                pr_info("EXYNOS4212 PMU Initialize\n");
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                exynos4_pmu_config = exynos4x12_pmu_config;
+                pr_info("EXYNOS4x12 PMU Initialize\n");
         } else {
                 pr_info("EXYNOS4: PMU not supported\n");
         }
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index b34287ab5afd..e24961109b70 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -518,6 +518,11 @@ config S3C2443_DMA
         help
           Internal config node for S3C2443 DMA support
 
+config S3C2443_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations
+
 endif   # CPU_S3C2443 || CPU_S3C2416
 
 if CPU_S3C2443
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 270a0b6f4f22..0ab6ab15da4c 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -97,5 +97,6 @@ obj-$(CONFIG_MACH_OSIRIS_DVS)		+= mach-osiris-dvs.o
 # device setup
 
 obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S3C2443_SETUP_SPI)         += setup-spi.o
 obj-$(CONFIG_ARCH_S3C24XX)              += setup-i2c.o
 obj-$(CONFIG_S3C24XX_SETUP_TS)          += setup-ts.o
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index dbc9ab4aaca2..8702ecfaab30 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index efb3ac359566..a4c5a520d994 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,6 +179,11 @@ static struct clk *clks[] __initdata = {
         &clk_hsmmc,
 };
 
+static struct clk_lookup s3c2443_clk_lookup[] = {
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
+};
+
 void __init s3c2443_init_clocks(int xtal)
 {
         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -210,6 +215,7 @@ void __init s3c2443_init_clocks(int xtal)
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 460431589f39..aeeb2be283fa 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -424,11 +424,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c2443_clkcon_enable_p,
                 .ctrlbit        = S3C2443_PCLKCON_IIS,
         }, {
-                .name           = "hsspi",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_HSSPI,
-        }, {
                 .name           = "adc",
                 .parent         = &clk_p,
                 .enable         = s3c2443_clkcon_enable_p,
@@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
         .ctrlbit        = S3C2443_HCLKCON_HSMMC,
 };
 
+static struct clk hsspi_clk = {
+        .name           = "spi",
+        .devname        = "s3c64xx-spi.0",
+        .parent         = &clk_p,
+        .enable         = s3c2443_clkcon_enable_p,
+        .ctrlbit        = S3C2443_PCLKCON_HSSPI,
+};
+
 /* EPLLCON compatible enough to get on/off information */
 
 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
@@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
         &clk_usb_bus,
         &clk_armdiv,
         &hsmmc1_clk,
+        &hsspi_clk,
 };
 
 static struct clksrc_clk *clksrcs[] __initdata = {
@@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index e227c472a40a..2d94228d2866 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2443_DMAREQSEL_SDI),
         },
-        [DMACH_SPI0] = {
-                .name           = "spi0",
+        [DMACH_SPI0_RX] = {
+                .name           = "spi0-rx",
+                .channels       = MAP(S3C2443_DMAREQSEL_SPI0RX),
+        },
+        [DMACH_SPI0_TX] = {
+                .name           = "spi0-tx",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI0TX),
         },
-        [DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
-                .name           = "spi1",
+        [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
+                .name           = "spi1-rx",
+                .channels       = MAP(S3C2443_DMAREQSEL_SPI1RX),
+        },
+        [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
+                .name           = "spi1-tx",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI1TX),
         },
         [DMACH_UART0] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index acbdfecd4186..454831b66037 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -47,6 +47,10 @@ enum dma_ch {
         DMACH_UART2_SRC2,
         DMACH_UART3,            /* s3c2443 has extra uart */
         DMACH_UART3_SRC2,
+        DMACH_SPI0_TX,          /* s3c2443/2416/2450 hsspi0 */
+        DMACH_SPI0_RX,          /* s3c2443/2416/2450 hsspi0 */
+        DMACH_SPI1_TX,          /* s3c2443/2450 hsspi1 */
+        DMACH_SPI1_RX,          /* s3c2443/2450 hsspi1 */
         DMACH_MAX,              /* the end entry */
 };
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 78ae807f1281..8ba381f2dbe1 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -98,6 +98,8 @@
 
 /* SPI */
 #define S3C2410_PA_SPI     (0x59000000)
+#define S3C2443_PA_SPI0         (0x52000000)
+#define S3C2443_PA_SPI1         S3C2410_PA_SPI
 
 /* SDI */
 #define S3C2410_PA_SDI     (0x5A000000)
@@ -162,4 +164,7 @@
 #define S3C_PA_WDT          S3C2410_PA_WATCHDOG
 #define S3C_PA_NAND         S3C24XX_PA_NAND
 
+#define S3C_PA_SPI0             S3C2443_PA_SPI0
+#define S3C_PA_SPI1             S3C2443_PA_SPI1
+
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
new file mode 100644
index 000000000000..5712c85f39b1
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -0,0 +1,39 @@
+/*
+ * HS-SPI device setup for S3C2443/S3C2416
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .tx_st_done     = 21,
+        .high_speed     = 1,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+{
+        /* enable hsspi bit in misccr */
+        s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
+
+        s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
new file mode 100644
index 000000000000..eaadc66d96b3
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Kconfig
@@ -0,0 +1,20 @@
+#
+# SPEAr13XX Machine configuration file
+#
+
+if ARCH_SPEAR13XX
+
+menu "SPEAr13xx Implementations"
+config MACH_SPEAR1310
+        bool "SPEAr1310 Machine support with Device Tree"
+        select PINCTRL_SPEAR1310
+        help
+          Supports ST SPEAr1310 machine configured via the device-tree
+
+config MACH_SPEAR1340
+        bool "SPEAr1340 Machine support with Device Tree"
+        select PINCTRL_SPEAR1340
+        help
+          Supports ST SPEAr1340 machine configured via the device-tree
+endmenu
+endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
new file mode 100644
index 000000000000..3435ea78c15d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for SPEAr13XX machine series
+#
+
+obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+
+obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o
+obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
+obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot
new file mode 100644
index 000000000000..403efd7e6d27
--- /dev/null
+++ b/arch/arm/mach-spear13xx/Makefile.boot
@@ -0,0 +1,6 @@
+zreladdr-y      += 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR1310)    += spear1310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR1340)    += spear1340-evb.dtb
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S
new file mode 100644
index 000000000000..ed85473a047f
--- /dev/null
+++ b/arch/arm/mach-spear13xx/headsmp.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-spear13XX/headsmp.S
+ *
+ * Picked from realview
+ * Copyright (c) 2012 ST Microelectronics Limited
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        __INIT
+
+/*
+ * spear13xx specific entry point for secondary CPUs. This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(spear13xx_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+
+        /* re-enable coherency */
+        mrc     p15, 0, r0, c1, c0, 1
+        orr     r0, r0, #(1 << 6) | (1 << 0)
+        mcr     p15, 0, r0, c1, c0, 1
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+
+        .align
+1:      .long   .
+        .long   pen_release
+ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c
new file mode 100644
index 000000000000..5c6867b46d09
--- /dev/null
+++ b/arch/arm/mach-spear13xx/hotplug.c
@@ -0,0 +1,119 @@
+/*
+ * linux/arch/arm/mach-spear13xx/hotplug.c
+ *
+ * Copyright (C) 2012 ST Microelectronics Ltd.
+ * Deepak Sikri <deepak.sikri@st.com>
+ *
+ * based upon linux/arch/arm/mach-realview/hotplug.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+        unsigned int v;
+
+        flush_cache_all();
+        asm volatile(
+        "       mcr     p15, 0, %1, c7, c5, 0\n"
+        "       dsb\n"
+        /*
+         * Turn off coherency
+         */
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, %2\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        : "=&r" (v)
+        : "r" (0), "Ir" (CR_C)
+        : "cc", "memory");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile("mrc       p15, 0, %0, c1, c0, 0\n"
+        "       orr     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       orr     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        : "=&r" (v)
+        : "Ir" (CR_C)
+        : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+        for (;;) {
+                wfi();
+
+                if (pen_release == cpu) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+
+                /*
+                 * Getting here, means that we have come out of WFI without
+                 * having been woken up - this shouldn't happen
+                 *
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
+                 */
+                (*spurious)++;
+        }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __cpuinit platform_cpu_die(unsigned int cpu)
+{
+        int spurious = 0;
+
+        /*
+         * we're ready for shutdown now, so do it
+         */
+        cpu_enter_lowpower();
+        platform_do_lowpower(cpu, &spurious);
+
+        /*
+         * bring this CPU back into the world of cache
+         * coherency, and then restore interrupts
+         */
+        cpu_leave_lowpower();
+
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..ea1564609bd4
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h
new file mode 100644
index 000000000000..383ab04dc6c9
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/dma.h
@@ -0,0 +1,128 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/dma.h
+ *
+ * DMA information for SPEAr13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* request id of all the peripherals */
+enum dma_master_info {
+        /* Accessible from only one master */
+        DMA_MASTER_MCIF = 0,
+        DMA_MASTER_FSMC = 1,
+        /* Accessible from both 0 & 1 */
+        DMA_MASTER_MEMORY = 0,
+        DMA_MASTER_ADC = 0,
+        DMA_MASTER_UART0 = 0,
+        DMA_MASTER_SSP0 = 0,
+        DMA_MASTER_I2C0 = 0,
+
+#ifdef CONFIG_MACH_SPEAR1310
+        /* Accessible from only one master */
+        SPEAR1310_DMA_MASTER_JPEG = 1,
+
+        /* Accessible from both 0 & 1 */
+        SPEAR1310_DMA_MASTER_I2S = 0,
+        SPEAR1310_DMA_MASTER_UART1 = 0,
+        SPEAR1310_DMA_MASTER_UART2 = 0,
+        SPEAR1310_DMA_MASTER_UART3 = 0,
+        SPEAR1310_DMA_MASTER_UART4 = 0,
+        SPEAR1310_DMA_MASTER_UART5 = 0,
+        SPEAR1310_DMA_MASTER_I2C1 = 0,
+        SPEAR1310_DMA_MASTER_I2C2 = 0,
+        SPEAR1310_DMA_MASTER_I2C3 = 0,
+        SPEAR1310_DMA_MASTER_I2C4 = 0,
+        SPEAR1310_DMA_MASTER_I2C5 = 0,
+        SPEAR1310_DMA_MASTER_I2C6 = 0,
+        SPEAR1310_DMA_MASTER_I2C7 = 0,
+        SPEAR1310_DMA_MASTER_SSP1 = 0,
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1340
+        /* Accessible from only one master */
+        SPEAR1340_DMA_MASTER_I2S_PLAY = 1,
+        SPEAR1340_DMA_MASTER_I2S_REC = 1,
+        SPEAR1340_DMA_MASTER_I2C1 = 1,
+        SPEAR1340_DMA_MASTER_UART1 = 1,
+
+        /* following are accessible from both master 0 & 1 */
+        SPEAR1340_DMA_MASTER_SPDIF = 0,
+        SPEAR1340_DMA_MASTER_CAM = 1,
+        SPEAR1340_DMA_MASTER_VIDEO_IN = 0,
+        SPEAR1340_DMA_MASTER_MALI = 0,
+#endif
+};
+
+enum request_id {
+        DMA_REQ_ADC = 0,
+        DMA_REQ_SSP0_TX = 4,
+        DMA_REQ_SSP0_RX = 5,
+        DMA_REQ_UART0_TX = 6,
+        DMA_REQ_UART0_RX = 7,
+        DMA_REQ_I2C0_TX = 8,
+        DMA_REQ_I2C0_RX = 9,
+
+#ifdef CONFIG_MACH_SPEAR1310
+        SPEAR1310_DMA_REQ_FROM_JPEG = 2,
+        SPEAR1310_DMA_REQ_TO_JPEG = 3,
+        SPEAR1310_DMA_REQ_I2S_TX = 10,
+        SPEAR1310_DMA_REQ_I2S_RX = 11,
+
+        SPEAR1310_DMA_REQ_I2C1_RX = 0,
+        SPEAR1310_DMA_REQ_I2C1_TX = 1,
+        SPEAR1310_DMA_REQ_I2C2_RX = 2,
+        SPEAR1310_DMA_REQ_I2C2_TX = 3,
+        SPEAR1310_DMA_REQ_I2C3_RX = 4,
+        SPEAR1310_DMA_REQ_I2C3_TX = 5,
+        SPEAR1310_DMA_REQ_I2C4_RX = 6,
+        SPEAR1310_DMA_REQ_I2C4_TX = 7,
+        SPEAR1310_DMA_REQ_I2C5_RX = 8,
+        SPEAR1310_DMA_REQ_I2C5_TX = 9,
+        SPEAR1310_DMA_REQ_I2C6_RX = 10,
+        SPEAR1310_DMA_REQ_I2C6_TX = 11,
+        SPEAR1310_DMA_REQ_UART1_RX = 12,
+        SPEAR1310_DMA_REQ_UART1_TX = 13,
+        SPEAR1310_DMA_REQ_UART2_RX = 14,
+        SPEAR1310_DMA_REQ_UART2_TX = 15,
+        SPEAR1310_DMA_REQ_UART5_RX = 16,
+        SPEAR1310_DMA_REQ_UART5_TX = 17,
+        SPEAR1310_DMA_REQ_SSP1_RX = 18,
+        SPEAR1310_DMA_REQ_SSP1_TX = 19,
+        SPEAR1310_DMA_REQ_I2C7_RX = 20,
+        SPEAR1310_DMA_REQ_I2C7_TX = 21,
+        SPEAR1310_DMA_REQ_UART3_RX = 28,
+        SPEAR1310_DMA_REQ_UART3_TX = 29,
+        SPEAR1310_DMA_REQ_UART4_RX = 30,
+        SPEAR1310_DMA_REQ_UART4_TX = 31,
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1340
+        SPEAR1340_DMA_REQ_SPDIF_TX = 2,
+        SPEAR1340_DMA_REQ_SPDIF_RX = 3,
+        SPEAR1340_DMA_REQ_I2S_TX = 10,
+        SPEAR1340_DMA_REQ_I2S_RX = 11,
+        SPEAR1340_DMA_REQ_UART1_TX = 12,
+        SPEAR1340_DMA_REQ_UART1_RX = 13,
+        SPEAR1340_DMA_REQ_I2C1_TX = 14,
+        SPEAR1340_DMA_REQ_I2C1_RX = 15,
+        SPEAR1340_DMA_REQ_CAM0_EVEN = 0,
+        SPEAR1340_DMA_REQ_CAM0_ODD = 1,
+        SPEAR1340_DMA_REQ_CAM1_EVEN = 2,
+        SPEAR1340_DMA_REQ_CAM1_ODD = 3,
+        SPEAR1340_DMA_REQ_CAM2_EVEN = 4,
+        SPEAR1340_DMA_REQ_CAM2_ODD = 5,
+        SPEAR1340_DMA_REQ_CAM3_EVEN = 6,
+        SPEAR1340_DMA_REQ_CAM3_ODD = 7,
+#endif
+};
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h
new file mode 100644
index 000000000000..6d8c45b9f298
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/generic.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/generic.h
+ *
+ * spear13xx machine family generic header file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <linux/dmaengine.h>
+#include <asm/mach/time.h>
+
+/* Add spear13xx structure declarations here */
+extern struct sys_timer spear13xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct dw_dma_platform_data dmac_plat_data;
+extern struct dw_dma_slave cf_dma_priv;
+extern struct dw_dma_slave nand_read_dma_priv;
+extern struct dw_dma_slave nand_write_dma_priv;
+
+/* Add spear13xx family function declarations here */
+void __init spear_setup_of_timer(void);
+void __init spear13xx_map_io(void);
+void __init spear13xx_dt_init_irq(void);
+void __init spear13xx_l2x0_init(void);
+bool dw_dma_filter(struct dma_chan *chan, void *slave);
+void spear_restart(char, const char *);
+void spear13xx_secondary_startup(void);
+
+#ifdef CONFIG_MACH_SPEAR1310
+void __init spear1310_clk_init(void);
+#else
+static inline void spear1310_clk_init(void) {}
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1340
+void __init spear1340_clk_init(void);
+#else
+static inline void spear1340_clk_init(void) {}
+#endif
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
new file mode 100644
index 000000000000..cd6f4f86a56b
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/gpio.h
+ *
+ * GPIO macros for SPEAr13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
new file mode 100644
index 000000000000..f542a24aa5f2
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/irqs.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for spear13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_GIC_END                     160
+#define NR_IRQS                         IRQ_GIC_END
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
new file mode 100644
index 000000000000..30c57ef72686
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/spear.h
+ *
+ * spear13xx Machine family specific definition
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR13XX_H
+#define __MACH_SPEAR13XX_H
+
+#include <asm/memory.h>
+
+#define PERIP_GRP2_BASE                         UL(0xB3000000)
+#define VA_PERIP_GRP2_BASE                      UL(0xFE000000)
+#define MCIF_SDHCI_BASE                         UL(0xB3000000)
+#define SYSRAM0_BASE                            UL(0xB3800000)
+#define VA_SYSRAM0_BASE                         UL(0xFE800000)
+#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
+
+#define PERIP_GRP1_BASE                         UL(0xE0000000)
+#define VA_PERIP_GRP1_BASE                      UL(0xFD000000)
+#define UART_BASE                               UL(0xE0000000)
+#define VA_UART_BASE                            UL(0xFD000000)
+#define SSP_BASE                                UL(0xE0100000)
+#define MISC_BASE                               UL(0xE0700000)
+#define VA_MISC_BASE                            IOMEM(UL(0xFD700000))
+
+#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
+#define VA_A9SM_AND_MPMC_BASE                   UL(0xFC000000)
+
+/* A9SM peripheral offsets */
+#define A9SM_PERIP_BASE                         UL(0xEC800000)
+#define VA_A9SM_PERIP_BASE                      UL(0xFC800000)
+#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
+
+#define L2CC_BASE                               UL(0xED000000)
+#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
+
+/* others */
+#define DMAC0_BASE                              UL(0xEA800000)
+#define DMAC1_BASE                              UL(0xEB000000)
+#define MCIF_CF_BASE                            UL(0xB2800000)
+
+/* Devices present in SPEAr1310 */
+#ifdef CONFIG_MACH_SPEAR1310
+#define SPEAR1310_RAS_GRP1_BASE                 UL(0xD8000000)
+#define VA_SPEAR1310_RAS_GRP1_BASE              UL(0xFA000000)
+#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
+#endif /* CONFIG_MACH_SPEAR1310 */
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE                     UART_BASE
+#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
+
+#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
new file mode 100644
index 000000000000..31af3e8d976e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/timex.h
+ *
+ * SPEAr3XX machine family specific timex definitions
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#include <plat/timex.h>
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c7840896ae6e
--- /dev/null
+++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
new file mode 100644
index 000000000000..f5d07f2663d7
--- /dev/null
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-spear13xx/platsmp.c
+ *
+ * based upon linux/arch/arm/mach-realview/platsmp.c
+ *
+ * Copyright (C) 2012 ST Microelectronics Ltd.
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <mach/spear.h>
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
+extern void spear13xx_secondary_startup(void);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_secondary_init(0);
+
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        pen_release = -1;
+        smp_wmb();
+
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        pen_release = cpu;
+        flush_cache_all();
+        outer_flush_all();
+
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                smp_rmb();
+                if (pen_release == -1)
+                        break;
+
+                udelay(10);
+        }
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+        unsigned int i, ncores = scu_get_core_count(scu_base);
+
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                        ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
+        }
+
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+
+        set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+
+        scu_enable(scu_base);
+
+        /*
+         * Write the address of secondary startup into the system-wide location
+         * (presently it is in SRAM). The BootMonitor waits until it receives a
+         * soft interrupt, and then the secondary CPU branches to this address.
+         */
+        __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
+}
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
new file mode 100644
index 000000000000..fefd15b2f380
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/mach-spear13xx/spear1310.c
+ *
+ * SPEAr1310 machine source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) "SPEAr1310: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Base addresses */
+#define SPEAR1310_SSP1_BASE                     UL(0x5D400000)
+#define SPEAR1310_SATA0_BASE                    UL(0xB1000000)
+#define SPEAR1310_SATA1_BASE                    UL(0xB1800000)
+#define SPEAR1310_SATA2_BASE                    UL(0xB4000000)
+
+/* ssp device registration */
+static struct pl022_ssp_controller ssp1_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 3,
+};
+
+/* Add SPEAr1310 auxdata to pass platform data */
+static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
+
+        OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
+        {}
+};
+
+static void __init spear1310_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear1310_auxdata_lookup, NULL);
+}
+
+static const char * const spear1310_dt_board_compat[] = {
+        "st,spear1310",
+        "st,spear1310-evb",
+        NULL,
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xD8000000           0xFA000000
+ */
+struct map_desc spear1310_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR1310_RAS_GRP1_BASE,
+                .pfn            = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        },
+};
+
+static void __init spear1310_map_io(void)
+{
+        iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc));
+        spear13xx_map_io();
+}
+
+DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
+        .map_io         =       spear1310_map_io,
+        .init_irq       =       spear13xx_dt_init_irq,
+        .handle_irq     =       gic_handle_irq,
+        .timer          =       &spear13xx_timer,
+        .init_machine   =       spear1310_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear1310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
new file mode 100644
index 000000000000..ee38cbc56869
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -0,0 +1,192 @@
+/*
+ * arch/arm/mach-spear13xx/spear1340.c
+ *
+ * SPEAr1340 machine source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) "SPEAr1340: " fmt
+
+#include <linux/ahci_platform.h>
+#include <linux/amba/serial.h>
+#include <linux/delay.h>
+#include <linux/dw_dmac.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <mach/dma.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Base addresses */
+#define SPEAR1340_SATA_BASE                     UL(0xB1000000)
+#define SPEAR1340_UART1_BASE                    UL(0xB4100000)
+
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG                       (VA_MISC_BASE + 0x100)
+#define SPEAR1340_PCM_WKUP_CFG                  (VA_MISC_BASE + 0x104)
+#define SPEAR1340_SWITCH_CTR                    (VA_MISC_BASE + 0x108)
+
+#define SPEAR1340_PERIP1_SW_RST                 (VA_MISC_BASE + 0x318)
+#define SPEAR1340_PERIP2_SW_RST                 (VA_MISC_BASE + 0x31C)
+#define SPEAR1340_PERIP3_SW_RST                 (VA_MISC_BASE + 0x320)
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG                 (VA_MISC_BASE + 0x424)
+        /* PCIE CFG MASks */
+        #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT       (1 << 11)
+        #define SPEAR1340_PCIE_CFG_POWERUP_RESET        (1 << 10)
+        #define SPEAR1340_PCIE_CFG_CORE_CLK_EN          (1 << 9)
+        #define SPEAR1340_PCIE_CFG_AUX_CLK_EN           (1 << 8)
+        #define SPEAR1340_SATA_CFG_TX_CLK_EN            (1 << 4)
+        #define SPEAR1340_SATA_CFG_RX_CLK_EN            (1 << 3)
+        #define SPEAR1340_SATA_CFG_POWERUP_RESET        (1 << 2)
+        #define SPEAR1340_SATA_CFG_PM_CLK_EN            (1 << 1)
+        #define SPEAR1340_PCIE_SATA_SEL_PCIE            (0)
+        #define SPEAR1340_PCIE_SATA_SEL_SATA            (1)
+        #define SPEAR1340_SATA_PCIE_CFG_MASK            0xF1F
+        #define SPEAR1340_PCIE_CFG_VAL  (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+                        SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+                        SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+                        SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+                        SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+        #define SPEAR1340_SATA_CFG_VAL  (SPEAR1340_PCIE_SATA_SEL_SATA | \
+                        SPEAR1340_SATA_CFG_PM_CLK_EN | \
+                        SPEAR1340_SATA_CFG_POWERUP_RESET | \
+                        SPEAR1340_SATA_CFG_RX_CLK_EN | \
+                        SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG                (VA_MISC_BASE + 0x428)
+        #define SPEAR1340_MIPHY_OSC_BYPASS_EXT          (1 << 31)
+        #define SPEAR1340_MIPHY_CLK_REF_DIV2            (1 << 27)
+        #define SPEAR1340_MIPHY_CLK_REF_DIV4            (2 << 27)
+        #define SPEAR1340_MIPHY_CLK_REF_DIV8            (3 << 27)
+        #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)        (x << 0)
+        #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+                        (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+                        SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+                        SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+        #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+                        (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+        #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+                        (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+                        SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+static struct dw_dma_slave uart1_dma_param[] = {
+        {
+                /* Tx */
+                .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
+                .cfg_lo = 0,
+                .src_master = DMA_MASTER_MEMORY,
+                .dst_master = SPEAR1340_DMA_MASTER_UART1,
+        }, {
+                /* Rx */
+                .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
+                .cfg_lo = 0,
+                .src_master = SPEAR1340_DMA_MASTER_UART1,
+                .dst_master = DMA_MASTER_MEMORY,
+        }
+};
+
+static struct amba_pl011_data uart1_data = {
+        .dma_filter = dw_dma_filter,
+        .dma_tx_param = &uart1_dma_param[0],
+        .dma_rx_param = &uart1_dma_param[1],
+};
+
+/* SATA device registration */
+static int sata_miphy_init(struct device *dev, void __iomem *addr)
+{
+        writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
+        writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
+                        SPEAR1340_PCIE_MIPHY_CFG);
+        /* Switch on sata power domain */
+        writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
+        msleep(20);
+        /* Disable PCIE SATA Controller reset */
+        writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
+                        SPEAR1340_PERIP1_SW_RST);
+        msleep(20);
+
+        return 0;
+}
+
+void sata_miphy_exit(struct device *dev)
+{
+        writel(0, SPEAR1340_PCIE_SATA_CFG);
+        writel(0, SPEAR1340_PCIE_MIPHY_CFG);
+
+        /* Enable PCIE SATA Controller reset */
+        writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
+                        SPEAR1340_PERIP1_SW_RST);
+        msleep(20);
+        /* Switch off sata power domain */
+        writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
+        msleep(20);
+}
+
+int sata_suspend(struct device *dev)
+{
+        if (dev->power.power_state.event == PM_EVENT_FREEZE)
+                return 0;
+
+        sata_miphy_exit(dev);
+
+        return 0;
+}
+
+int sata_resume(struct device *dev)
+{
+        if (dev->power.power_state.event == PM_EVENT_THAW)
+                return 0;
+
+        return sata_miphy_init(dev, NULL);
+}
+
+static struct ahci_platform_data sata_pdata = {
+        .init = sata_miphy_init,
+        .exit = sata_miphy_exit,
+        .suspend = sata_suspend,
+        .resume = sata_resume,
+};
+
+/* Add SPEAr1340 auxdata to pass platform data */
+static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
+
+        OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
+                        &sata_pdata),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data),
+        {}
+};
+
+static void __init spear1340_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear1340_auxdata_lookup, NULL);
+}
+
+static const char * const spear1340_dt_board_compat[] = {
+        "st,spear1340",
+        "st,spear1340-evb",
+        NULL,
+};
+
+DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
+        .map_io         =       spear13xx_map_io,
+        .init_irq       =       spear13xx_dt_init_irq,
+        .handle_irq     =       gic_handle_irq,
+        .timer          =       &spear13xx_timer,
+        .init_machine   =       spear1340_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear1340_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
new file mode 100644
index 000000000000..50b349ae863d
--- /dev/null
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -0,0 +1,197 @@
+/*
+ * arch/arm/mach-spear13xx/spear13xx.c
+ *
+ * SPEAr13XX machines common source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) "SPEAr13xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/clk.h>
+#include <linux/dw_dmac.h>
+#include <linux/err.h>
+#include <linux/of_irq.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
+#include <asm/smp_twd.h>
+#include <mach/dma.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* common dw_dma filter routine to be used by peripherals */
+bool dw_dma_filter(struct dma_chan *chan, void *slave)
+{
+        struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
+
+        if (chan->device->dev == dws->dma_dev) {
+                chan->private = slave;
+                return true;
+        } else {
+                return false;
+        }
+}
+
+/* ssp device registration */
+static struct dw_dma_slave ssp_dma_param[] = {
+        {
+                /* Tx */
+                .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
+                .cfg_lo = 0,
+                .src_master = DMA_MASTER_MEMORY,
+                .dst_master = DMA_MASTER_SSP0,
+        }, {
+                /* Rx */
+                .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
+                .cfg_lo = 0,
+                .src_master = DMA_MASTER_SSP0,
+                .dst_master = DMA_MASTER_MEMORY,
+        }
+};
+
+struct pl022_ssp_controller pl022_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 1,
+        .dma_filter = dw_dma_filter,
+        .dma_rx_param = &ssp_dma_param[1],
+        .dma_tx_param = &ssp_dma_param[0],
+        .num_chipselect = 3,
+};
+
+/* CF device registration */
+struct dw_dma_slave cf_dma_priv = {
+        .cfg_hi = 0,
+        .cfg_lo = 0,
+        .src_master = 0,
+        .dst_master = 0,
+};
+
+/* dmac device registeration */
+struct dw_dma_platform_data dmac_plat_data = {
+        .nr_channels = 8,
+        .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
+        .chan_priority = CHAN_PRIORITY_DESCENDING,
+};
+
+void __init spear13xx_l2x0_init(void)
+{
+        /*
+         * 512KB (64KB/way), 8-way associativity, parity supported
+         *
+         * FIXME: 9th bit, of Auxillary Controller register must be set
+         * for some spear13xx devices for stable L2 operation.
+         *
+         * Enable Early BRESP, L2 prefetch for Instruction and Data,
+         * write alloc and 'Full line of zero' options
+         *
+         */
+
+        writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
+
+        /*
+         * Program following latencies in order to make
+         * SPEAr1340 work at 600 MHz
+         */
+        writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
+        writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
+        l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
+}
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xB3000000           0xFE000000
+ * 0xE0000000           0xFD000000
+ * 0xEC000000           0xFC000000
+ * 0xED000000           0xFB000000
+ */
+struct map_desc spear13xx_io_desc[] __initdata = {
+        {
+                .virtual        = VA_PERIP_GRP2_BASE,
+                .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = VA_PERIP_GRP1_BASE,
+                .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = VA_A9SM_AND_MPMC_BASE,
+                .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = (unsigned long)VA_L2CC_BASE,
+                .pfn            = __phys_to_pfn(L2CC_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE
+        },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear13xx_map_io(void)
+{
+        iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
+}
+
+static void __init spear13xx_clk_init(void)
+{
+        if (of_machine_is_compatible("st,spear1310"))
+                spear1310_clk_init();
+        else if (of_machine_is_compatible("st,spear1340"))
+                spear1340_clk_init();
+        else
+                pr_err("%s: Unknown machine\n", __func__);
+}
+
+static void __init spear13xx_timer_init(void)
+{
+        char pclk_name[] = "osc_24m_clk";
+        struct clk *gpt_clk, *pclk;
+
+        spear13xx_clk_init();
+
+        /* get the system timer clock */
+        gpt_clk = clk_get_sys("gpt0", NULL);
+        if (IS_ERR(gpt_clk)) {
+                pr_err("%s:couldn't get clk for gpt\n", __func__);
+                BUG();
+        }
+
+        /* get the suitable parent clock for timer*/
+        pclk = clk_get(NULL, pclk_name);
+        if (IS_ERR(pclk)) {
+                pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
+                                pclk_name);
+                BUG();
+        }
+
+        clk_set_parent(gpt_clk, pclk);
+        clk_put(gpt_clk);
+        clk_put(pclk);
+
+        spear_setup_of_timer();
+        twd_local_timer_of_register();
+}
+
+struct sys_timer spear13xx_timer = {
+        .init = spear13xx_timer_init,
+};
+
+static const struct of_device_id gic_of_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
+        { /* Sentinel */ }
+};
+
+void __init spear13xx_dt_init_irq(void)
+{
+        of_irq_init(gic_of_match);
+}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8c571031da8..a2fae4ea0936 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -419,7 +419,7 @@ config S3C_DMA
 config SAMSUNG_DMADEV
         bool
         select DMADEVICES
-        select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \
+        select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
                                         CPU_S5P6450 || CPU_S5P6440)
         select ARM_AMBA
         help
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 787ceaca0be8..0721293fad63 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -202,7 +202,7 @@ extern struct bus_type s3c2443_subsys;
 extern struct bus_type s3c6410_subsys;
 extern struct bus_type s5p64x0_subsys;
 extern struct bus_type s5pv210_subsys;
-extern struct bus_type exynos4_subsys;
+extern struct bus_type exynos_subsys;
 
 extern void (*s5pc1xx_idle)(void);
 
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4067d1dd7f1c..61ca2f356c52 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -134,6 +134,8 @@ extern struct platform_device exynos4_device_pcm2;
 extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
 
+extern struct platform_device exynos_device_drm;
+
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 0670f37aaaed..d384a8016b47 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -90,6 +90,7 @@ enum dma_ch {
         DMACH_MIPI_HSI5,
         DMACH_MIPI_HSI6,
         DMACH_MIPI_HSI7,
+        DMACH_DISP1,
         DMACH_MTOM_0,
         DMACH_MTOM_1,
         DMACH_MTOM_2,
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 1de4b32f98e9..8364b4bea8b8 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -32,8 +32,10 @@ extern struct clk clk_48m;
 extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
 extern struct clk clk_fout_bpll;
+extern struct clk clk_fout_bpll_div2;
 extern struct clk clk_fout_cpll;
 extern struct clk clk_fout_mpll;
+extern struct clk clk_fout_mpll_div2;
 extern struct clk clk_fout_epll;
 extern struct clk clk_fout_dpll;
 extern struct clk clk_fout_vpll;
@@ -42,8 +44,10 @@ extern struct clk clk_vpll;
 
 extern struct clksrc_sources clk_src_apll;
 extern struct clksrc_sources clk_src_bpll;
+extern struct clksrc_sources clk_src_bpll_fout;
 extern struct clksrc_sources clk_src_cpll;
 extern struct clksrc_sources clk_src_mpll;
+extern struct clksrc_sources clk_src_mpll_fout;
 extern struct clksrc_sources clk_src_epll;
 extern struct clksrc_sources clk_src_dpll;
 
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
index 41d3dfd5dddb..031a61899bef 100644
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ b/arch/arm/plat-samsung/s5p-clock.c
@@ -67,6 +67,11 @@ struct clk clk_fout_bpll = {
         .id             = -1,
 };
 
+struct clk clk_fout_bpll_div2 = {
+        .name           = "fout_bpll_div2",
+        .id             = -1,
+};
+
 /* CPLL clock output */
 
 struct clk clk_fout_cpll = {
@@ -82,6 +87,11 @@ struct clk clk_fout_mpll = {
         .id             = -1,
 };
 
+struct clk clk_fout_mpll_div2 = {
+        .name           = "fout_mpll_div2",
+        .id             = -1,
+};
+
 /* EPLL clock output */
 struct clk clk_fout_epll = {
         .name           = "fout_epll",
@@ -125,6 +135,16 @@ struct clksrc_sources clk_src_bpll = {
         .nr_sources     = ARRAY_SIZE(clk_src_bpll_list),
 };
 
+static struct clk *clk_src_bpll_fout_list[] = {
+        [0] = &clk_fout_bpll_div2,
+        [1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll_fout = {
+        .sources        = clk_src_bpll_fout_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_bpll_fout_list),
+};
+
 /* Possible clock sources for CPLL Mux */
 static struct clk *clk_src_cpll_list[] = {
         [0] = &clk_fin_cpll,
@@ -147,6 +167,16 @@ struct clksrc_sources clk_src_mpll = {
         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
 };
 
+static struct clk *clk_src_mpll_fout_list[] = {
+        [0] = &clk_fout_mpll_div2,
+        [1] = &clk_fout_mpll,
+};
+
+struct clksrc_sources clk_src_mpll_fout = {
+        .sources        = clk_src_mpll_fout_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_fout_list),
+};
+
 /* Possible clock sources for EPLL Mux */
 static struct clk *clk_src_epll_list[] = {
         [0] = &clk_fin_epll,
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 387655b5ce05..4404f82d5979 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,6 +8,17 @@ choice
         prompt "ST SPEAr Family"
         default ARCH_SPEAR3XX
 
+config ARCH_SPEAR13XX
+        bool "ST SPEAr13xx with Device Tree"
+        select ARM_GIC
+        select CPU_V7
+        select USE_OF
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        help
+          Supports for ARM's SPEAR13XX family
+
 config ARCH_SPEAR3XX
         bool "ST SPEAr3xx with Device Tree"
         select ARM_VIC
@@ -27,6 +38,7 @@ config ARCH_SPEAR6XX
 endchoice
 
 # Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear13xx/Kconfig"
 source "arch/arm/mach-spear3xx/Kconfig"
 source "arch/arm/mach-spear6xx/Kconfig"
 
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 38f1235f4632..2607bd05c525 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,7 @@
 #
 
 # Common support
-obj-y   := restart.o time.o pl080.o
+obj-y   := restart.o time.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o shirq.o
+obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 4471a232713a..ea0a61302b7e 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -16,6 +16,7 @@
 #include <mach/spear.h>
 #include <mach/generic.h>
 
+#define SPEAR13XX_SYS_SW_RES                    (VA_MISC_BASE + 0x204)
 void spear_restart(char mode, const char *cmd)
 {
         if (mode == 's') {
@@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd)
                 soft_restart(0);
         } else {
                 /* hardware reset, Use on-chip reset capability */
+#ifdef CONFIG_ARCH_SPEAR13XX
+                writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
+#else
                 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
+#endif
         }
 }