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authorScott Wood <scottwood@freescale.com>2007-09-14 15:38:16 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-10-04 12:02:38 -0400
commit20906ecea2004c0667c8b229ac6461d16ea6bde3 (patch)
treea883f211d08cb666739e865fee173df61929ea64 /arch
parent96fca1dea8f32e96668d55727d66416fdd67360b (diff)
[POWERPC] 8xx: mpc885ads cleanup
It now uses the new CPM binding and the generic pin/clock functions, and has assorted fixes and cleanup. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts195
-rw-r--r--arch/powerpc/configs/mpc885_ads_defconfig297
-rw-r--r--arch/powerpc/platforms/8xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/8xx/mpc885ads.h38
-rw-r--r--arch/powerpc/platforms/8xx/mpc885ads_setup.c450
5 files changed, 420 insertions, 561 deletions
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index e9aa9d00da24..cbcd16f74c45 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -2,6 +2,7 @@
2 * MPC885 ADS Device Tree Source 2 * MPC885 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2007 Freescale Semiconductor, Inc.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -12,7 +13,7 @@
12 13
13/ { 14/ {
14 model = "MPC885ADS"; 15 model = "MPC885ADS";
15 compatible = "mpc8xx"; 16 compatible = "fsl,mpc885ads";
16 #address-cells = <1>; 17 #address-cells = <1>;
17 #size-cells = <1>; 18 #size-cells = <1>;
18 19
@@ -23,156 +24,188 @@
23 PowerPC,885@0 { 24 PowerPC,885@0 {
24 device_type = "cpu"; 25 device_type = "cpu";
25 reg = <0>; 26 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes 27 d-cache-line-size = <d#16>;
27 i-cache-line-size = <20>; // 32 bytes 28 i-cache-line-size = <d#16>;
28 d-cache-size = <2000>; // L1, 8K 29 d-cache-size = <d#8192>;
29 i-cache-size = <2000>; // L1, 8K 30 i-cache-size = <d#8192>;
30 timebase-frequency = <0>; 31 timebase-frequency = <0>;
31 bus-frequency = <0>; 32 bus-frequency = <0>;
32 clock-frequency = <0>; 33 clock-frequency = <0>;
33 interrupts = <f 2>; // decrementer interrupt 34 interrupts = <f 2>; // decrementer interrupt
34 interrupt-parent = <&Mpc8xx_pic>; 35 interrupt-parent = <&PIC>;
35 }; 36 };
36 }; 37 };
37 38
38 memory { 39 memory {
39 device_type = "memory"; 40 device_type = "memory";
40 reg = <00000000 800000>; 41 reg = <0 0>;
41 }; 42 };
42 43
43 soc885@ff000000 { 44 localbus@ff000100 {
45 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
46 #address-cells = <2>;
47 #size-cells = <1>;
48 reg = <ff000100 40>;
49
50 ranges = <
51 0 0 fe000000 00800000
52 1 0 ff080000 00008000
53 5 0 ff0a0000 00008000
54 >;
55
56 flash@0,0 {
57 compatible = "jedec-flash";
58 reg = <0 0 800000>;
59 bank-width = <4>;
60 device-width = <1>;
61 };
62
63 board-control@1,0 {
64 reg = <1 0 20 5 300 4>;
65 compatible = "fsl,mpc885ads-bcsr";
66 };
67 };
68
69 soc@ff000000 {
70 compatible = "fsl,mpc885", "fsl,pq1-soc";
44 #address-cells = <1>; 71 #address-cells = <1>;
45 #size-cells = <1>; 72 #size-cells = <1>;
46 device_type = "soc"; 73 device_type = "soc";
47 ranges = <0 ff000000 00100000>; 74 ranges = <0 ff000000 00004000>;
48 reg = <ff000000 00000200>;
49 bus-frequency = <0>; 75 bus-frequency = <0>;
50 mdio@e80 { 76
51 device_type = "mdio"; 77 // Temporary -- will go away once kernel uses ranges for get_immrbase().
52 compatible = "fs_enet"; 78 reg = <ff000000 4000>;
53 reg = <e80 8>; 79
80 mdio@e00 {
81 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
82 reg = <e00 188>;
54 #address-cells = <1>; 83 #address-cells = <1>;
55 #size-cells = <0>; 84 #size-cells = <0>;
56 Phy0: ethernet-phy@0 { 85
86 PHY0: ethernet-phy@0 {
57 reg = <0>; 87 reg = <0>;
58 device_type = "ethernet-phy"; 88 device_type = "ethernet-phy";
59 }; 89 };
60 Phy1: ethernet-phy@1 { 90
91 PHY1: ethernet-phy@1 {
61 reg = <1>; 92 reg = <1>;
62 device_type = "ethernet-phy"; 93 device_type = "ethernet-phy";
63 }; 94 };
64 Phy2: ethernet-phy@2 { 95
96 PHY2: ethernet-phy@2 {
65 reg = <2>; 97 reg = <2>;
66 device_type = "ethernet-phy"; 98 device_type = "ethernet-phy";
67 }; 99 };
68 }; 100 };
69 101
70 fec@e00 { 102 ethernet@e00 {
71 device_type = "network"; 103 device_type = "network";
72 compatible = "fs_enet"; 104 compatible = "fsl,mpc885-fec-enet",
73 model = "FEC"; 105 "fsl,pq1-fec-enet";
74 device-id = <1>;
75 reg = <e00 188>; 106 reg = <e00 188>;
76 mac-address = [ 00 00 0C 00 01 FD ]; 107 local-mac-address = [ 00 00 00 00 00 00 ];
77 interrupts = <3 1>; 108 interrupts = <3 1>;
78 interrupt-parent = <&Mpc8xx_pic>; 109 interrupt-parent = <&PIC>;
79 phy-handle = <&Phy1>; 110 phy-handle = <&PHY0>;
111 linux,network-index = <0>;
80 }; 112 };
81 113
82 fec@1e00 { 114 ethernet@1e00 {
83 device_type = "network"; 115 device_type = "network";
84 compatible = "fs_enet"; 116 compatible = "fsl,mpc885-fec-enet",
85 model = "FEC"; 117 "fsl,pq1-fec-enet";
86 device-id = <2>;
87 reg = <1e00 188>; 118 reg = <1e00 188>;
88 mac-address = [ 00 00 0C 00 02 FD ]; 119 local-mac-address = [ 00 00 00 00 00 00 ];
89 interrupts = <7 1>; 120 interrupts = <7 1>;
90 interrupt-parent = <&Mpc8xx_pic>; 121 interrupt-parent = <&PIC>;
91 phy-handle = <&Phy2>; 122 phy-handle = <&PHY1>;
123 linux,network-index = <1>;
92 }; 124 };
93 125
94 Mpc8xx_pic: pic@ff000000 { 126 PIC: interrupt-controller@0 {
95 interrupt-controller; 127 interrupt-controller;
96 #address-cells = <0>;
97 #interrupt-cells = <2>; 128 #interrupt-cells = <2>;
98 reg = <0 24>; 129 reg = <0 24>;
99 device_type = "mpc8xx-pic"; 130 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
100 compatible = "CPM";
101 }; 131 };
102 132
103 pcmcia@0080 { 133 pcmcia@80 {
104 #address-cells = <3>; 134 #address-cells = <3>;
105 #interrupt-cells = <1>; 135 #interrupt-cells = <1>;
106 #size-cells = <2>; 136 #size-cells = <2>;
107 compatible = "fsl,pq-pcmcia"; 137 compatible = "fsl,pq-pcmcia";
108 device_type = "pcmcia"; 138 device_type = "pcmcia";
109 reg = <80 80>; 139 reg = <80 80>;
110 interrupt-parent = <&Mpc8xx_pic>; 140 interrupt-parent = <&PIC>;
111 interrupts = <d 1>; 141 interrupts = <d 1>;
112 }; 142 };
113 143
114 cpm@ff000000 { 144 cpm@9c0 {
115 #address-cells = <1>; 145 #address-cells = <1>;
116 #size-cells = <1>; 146 #size-cells = <1>;
117 device_type = "cpm"; 147 compatible = "fsl,mpc885-cpm", "fsl,cpm1";
118 model = "CPM";
119 ranges = <0 0 4000>;
120 reg = <860 f0>;
121 command-proc = <9c0>; 148 command-proc = <9c0>;
122 brg-frequency = <0>; 149 interrupts = <0>; // cpm error interrupt
123 interrupts = <0 2>; // cpm error interrupt 150 interrupt-parent = <&CPM_PIC>;
124 interrupt-parent = <&Cpm_pic>; 151 reg = <9c0 40 2000 1c00>;
152 ranges;
125 153
126 Cpm_pic: pic@930 { 154 brg@9f0 {
155 compatible = "fsl,mpc885-brg",
156 "fsl,cpm1-brg",
157 "fsl,cpm-brg";
158 reg = <9f0 10>;
159 };
160
161 CPM_PIC: interrupt-controller@930 {
127 interrupt-controller; 162 interrupt-controller;
128 #address-cells = <0>; 163 #interrupt-cells = <1>;
129 #interrupt-cells = <2>;
130 interrupts = <5 2 0 2>; 164 interrupts = <5 2 0 2>;
131 interrupt-parent = <&Mpc8xx_pic>; 165 interrupt-parent = <&PIC>;
132 reg = <930 20>; 166 reg = <930 20>;
133 device_type = "cpm-pic"; 167 compatible = "fsl,mpc885-cpm-pic",
134 compatible = "CPM"; 168 "fsl,cpm1-pic";
135 }; 169 };
136 170
137 smc@a80 { 171 serial@a80 {
138 device_type = "serial"; 172 device_type = "serial";
139 compatible = "cpm_uart"; 173 compatible = "fsl,mpc885-smc-uart",
140 model = "SMC"; 174 "fsl,cpm1-smc-uart";
141 device-id = <1>;
142 reg = <a80 10 3e80 40>; 175 reg = <a80 10 3e80 40>;
143 clock-setup = <00ffffff 0>; 176 interrupts = <4>;
144 rx-clock = <1>; 177 interrupt-parent = <&CPM_PIC>;
145 tx-clock = <1>; 178 fsl,cpm-brg = <1>;
146 current-speed = <0>; 179 fsl,cpm-command = <0090>;
147 interrupts = <4 3>;
148 interrupt-parent = <&Cpm_pic>;
149 }; 180 };
150 181
151 smc@a90 { 182 serial@a90 {
152 device_type = "serial"; 183 device_type = "serial";
153 compatible = "cpm_uart"; 184 compatible = "fsl,mpc885-smc-uart",
154 model = "SMC"; 185 "fsl,cpm1-smc-uart";
155 device-id = <2>; 186 reg = <a90 10 3f80 40>;
156 reg = <a90 20 3f80 40>; 187 interrupts = <3>;
157 clock-setup = <ff00ffff 90000>; 188 interrupt-parent = <&CPM_PIC>;
158 rx-clock = <2>; 189 fsl,cpm-brg = <2>;
159 tx-clock = <2>; 190 fsl,cpm-command = <00d0>;
160 current-speed = <0>;
161 interrupts = <3 3>;
162 interrupt-parent = <&Cpm_pic>;
163 }; 191 };
164 192
165 scc@a40 { 193 ethernet@a40 {
166 device_type = "network"; 194 device_type = "network";
167 compatible = "fs_enet"; 195 compatible = "fsl,mpc885-scc-enet",
168 model = "SCC"; 196 "fsl,cpm1-scc-enet";
169 device-id = <3>; 197 reg = <a40 18 3e00 100>;
170 reg = <a40 18 3e00 80>; 198 local-mac-address = [ 00 00 00 00 00 00 ];
171 mac-address = [ 00 00 0C 00 03 FD ]; 199 interrupts = <1c>;
172 interrupts = <1c 3>; 200 interrupt-parent = <&CPM_PIC>;
173 interrupt-parent = <&Cpm_pic>; 201 phy-handle = <&PHY2>;
174 phy-handle = <&Phy2>; 202 fsl,cpm-command = <0080>;
203 linux,network-index = <2>;
175 }; 204 };
176 }; 205 };
177 }; 206 };
207
208 chosen {
209 linux,stdout-path = "/soc/cpm/serial@a80";
210 };
178}; 211};
diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig
index d27e1f8c38fa..482d99db6870 100644
--- a/arch/powerpc/configs/mpc885_ads_defconfig
+++ b/arch/powerpc/configs/mpc885_ads_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc4 3# Linux kernel version: 2.6.23-rc3
4# Tue Aug 28 21:24:45 2007 4# Mon Aug 27 15:23:16 2007
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -38,6 +38,7 @@ CONFIG_OF=y
38# CONFIG_PPC_UDBG_16550 is not set 38# CONFIG_PPC_UDBG_16550 is not set
39# CONFIG_GENERIC_TBSYNC is not set 39# CONFIG_GENERIC_TBSYNC is not set
40CONFIG_AUDIT_ARCH=y 40CONFIG_AUDIT_ARCH=y
41CONFIG_GENERIC_BUG=y
41# CONFIG_DEFAULT_UIMAGE is not set 42# CONFIG_DEFAULT_UIMAGE is not set
42# CONFIG_PPC_DCR_NATIVE is not set 43# CONFIG_PPC_DCR_NATIVE is not set
43# CONFIG_PPC_DCR_MMIO is not set 44# CONFIG_PPC_DCR_MMIO is not set
@@ -69,24 +70,25 @@ CONFIG_SYSCTL=y
69CONFIG_EMBEDDED=y 70CONFIG_EMBEDDED=y
70# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
71CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
73# CONFIG_KALLSYMS_ALL is not set
72# CONFIG_KALLSYMS_EXTRA_PASS is not set 74# CONFIG_KALLSYMS_EXTRA_PASS is not set
73# CONFIG_HOTPLUG is not set 75CONFIG_HOTPLUG=y
74CONFIG_PRINTK=y 76CONFIG_PRINTK=y
75# CONFIG_BUG is not set 77CONFIG_BUG=y
76CONFIG_ELF_CORE=y 78# CONFIG_ELF_CORE is not set
77# CONFIG_BASE_FULL is not set 79# CONFIG_BASE_FULL is not set
78CONFIG_FUTEX=y 80# CONFIG_FUTEX is not set
79CONFIG_ANON_INODES=y 81CONFIG_ANON_INODES=y
80# CONFIG_EPOLL is not set 82CONFIG_EPOLL=y
81CONFIG_SIGNALFD=y 83CONFIG_SIGNALFD=y
82CONFIG_TIMERFD=y 84CONFIG_TIMERFD=y
83CONFIG_EVENTFD=y 85CONFIG_EVENTFD=y
84CONFIG_SHMEM=y 86CONFIG_SHMEM=y
85# CONFIG_VM_EVENT_COUNTERS is not set 87# CONFIG_VM_EVENT_COUNTERS is not set
86CONFIG_SLAB=y 88CONFIG_SLUB_DEBUG=y
87# CONFIG_SLUB is not set 89# CONFIG_SLAB is not set
90CONFIG_SLUB=y
88# CONFIG_SLOB is not set 91# CONFIG_SLOB is not set
89CONFIG_RT_MUTEXES=y
90# CONFIG_TINY_SHMEM is not set 92# CONFIG_TINY_SHMEM is not set
91CONFIG_BASE_SMALL=1 93CONFIG_BASE_SMALL=1
92# CONFIG_MODULES is not set 94# CONFIG_MODULES is not set
@@ -100,14 +102,14 @@ CONFIG_BLOCK=y
100# IO Schedulers 102# IO Schedulers
101# 103#
102CONFIG_IOSCHED_NOOP=y 104CONFIG_IOSCHED_NOOP=y
103CONFIG_IOSCHED_AS=y 105# CONFIG_IOSCHED_AS is not set
104CONFIG_IOSCHED_DEADLINE=y 106CONFIG_IOSCHED_DEADLINE=y
105CONFIG_IOSCHED_CFQ=y 107# CONFIG_IOSCHED_CFQ is not set
106CONFIG_DEFAULT_AS=y 108# CONFIG_DEFAULT_AS is not set
107# CONFIG_DEFAULT_DEADLINE is not set 109CONFIG_DEFAULT_DEADLINE=y
108# CONFIG_DEFAULT_CFQ is not set 110# CONFIG_DEFAULT_CFQ is not set
109# CONFIG_DEFAULT_NOOP is not set 111# CONFIG_DEFAULT_NOOP is not set
110CONFIG_DEFAULT_IOSCHED="anticipatory" 112CONFIG_DEFAULT_IOSCHED="deadline"
111 113
112# 114#
113# Platform support 115# Platform support
@@ -120,6 +122,7 @@ CONFIG_CPM1=y
120# CONFIG_MPC8XXFADS is not set 122# CONFIG_MPC8XXFADS is not set
121# CONFIG_MPC86XADS is not set 123# CONFIG_MPC86XADS is not set
122CONFIG_MPC885ADS=y 124CONFIG_MPC885ADS=y
125# CONFIG_PPC_EP88XC is not set
123 126
124# 127#
125# Freescale Ethernet driver platform-specific options 128# Freescale Ethernet driver platform-specific options
@@ -137,6 +140,7 @@ CONFIG_MPC8xx_SECOND_ETH_FEC2=y
137# 140#
138CONFIG_8xx_COPYBACK=y 141CONFIG_8xx_COPYBACK=y
139# CONFIG_8xx_CPU6 is not set 142# CONFIG_8xx_CPU6 is not set
143CONFIG_8xx_CPU15=y
140CONFIG_NO_UCODE_PATCH=y 144CONFIG_NO_UCODE_PATCH=y
141# CONFIG_USB_SOF_UCODE_PATCH is not set 145# CONFIG_USB_SOF_UCODE_PATCH is not set
142# CONFIG_I2C_SPI_UCODE_PATCH is not set 146# CONFIG_I2C_SPI_UCODE_PATCH is not set
@@ -153,23 +157,23 @@ CONFIG_NO_UCODE_PATCH=y
153# CONFIG_GENERIC_IOMAP is not set 157# CONFIG_GENERIC_IOMAP is not set
154# CONFIG_CPU_FREQ is not set 158# CONFIG_CPU_FREQ is not set
155# CONFIG_CPM2 is not set 159# CONFIG_CPM2 is not set
156# CONFIG_FSL_ULI1575 is not set 160CONFIG_PPC_CPM_NEW_BINDING=y
157 161
158# 162#
159# Kernel options 163# Kernel options
160# 164#
161# CONFIG_HIGHMEM is not set 165# CONFIG_HIGHMEM is not set
162# CONFIG_HZ_100 is not set 166CONFIG_HZ_100=y
163# CONFIG_HZ_250 is not set 167# CONFIG_HZ_250 is not set
164# CONFIG_HZ_300 is not set 168# CONFIG_HZ_300 is not set
165CONFIG_HZ_1000=y 169# CONFIG_HZ_1000 is not set
166CONFIG_HZ=1000 170CONFIG_HZ=100
167CONFIG_PREEMPT_NONE=y 171CONFIG_PREEMPT_NONE=y
168# CONFIG_PREEMPT_VOLUNTARY is not set 172# CONFIG_PREEMPT_VOLUNTARY is not set
169# CONFIG_PREEMPT is not set 173# CONFIG_PREEMPT is not set
170CONFIG_BINFMT_ELF=y 174CONFIG_BINFMT_ELF=y
171# CONFIG_BINFMT_MISC is not set 175# CONFIG_BINFMT_MISC is not set
172CONFIG_MATH_EMULATION=y 176# CONFIG_MATH_EMULATION is not set
173CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 177CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
174CONFIG_ARCH_FLATMEM_ENABLE=y 178CONFIG_ARCH_FLATMEM_ENABLE=y
175CONFIG_ARCH_POPULATES_NODE_MAP=y 179CONFIG_ARCH_POPULATES_NODE_MAP=y
@@ -185,11 +189,12 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
185CONFIG_ZONE_DMA_FLAG=1 189CONFIG_ZONE_DMA_FLAG=1
186CONFIG_BOUNCE=y 190CONFIG_BOUNCE=y
187CONFIG_VIRT_TO_BUS=y 191CONFIG_VIRT_TO_BUS=y
188# CONFIG_PROC_DEVICETREE is not set 192CONFIG_PROC_DEVICETREE=y
189# CONFIG_CMDLINE_BOOL is not set 193# CONFIG_CMDLINE_BOOL is not set
190# CONFIG_PM is not set 194# CONFIG_PM is not set
191# CONFIG_SECCOMP is not set 195# CONFIG_SECCOMP is not set
192# CONFIG_WANT_DEVICE_TREE is not set 196CONFIG_WANT_DEVICE_TREE=y
197CONFIG_DEVICE_TREE="mpc885ads.dts"
193CONFIG_ISA_DMA_API=y 198CONFIG_ISA_DMA_API=y
194 199
195# 200#
@@ -206,6 +211,7 @@ CONFIG_FSL_SOC=y
206# 211#
207# PCCARD (PCMCIA/CardBus) support 212# PCCARD (PCMCIA/CardBus) support
208# 213#
214# CONFIG_PCCARD is not set
209 215
210# 216#
211# Advanced setup 217# Advanced setup
@@ -234,10 +240,6 @@ CONFIG_NET=y
234CONFIG_PACKET=y 240CONFIG_PACKET=y
235# CONFIG_PACKET_MMAP is not set 241# CONFIG_PACKET_MMAP is not set
236CONFIG_UNIX=y 242CONFIG_UNIX=y
237CONFIG_XFRM=y
238# CONFIG_XFRM_USER is not set
239# CONFIG_XFRM_SUB_POLICY is not set
240# CONFIG_XFRM_MIGRATE is not set
241# CONFIG_NET_KEY is not set 243# CONFIG_NET_KEY is not set
242CONFIG_INET=y 244CONFIG_INET=y
243CONFIG_IP_MULTICAST=y 245CONFIG_IP_MULTICAST=y
@@ -257,9 +259,9 @@ CONFIG_SYN_COOKIES=y
257# CONFIG_INET_IPCOMP is not set 259# CONFIG_INET_IPCOMP is not set
258# CONFIG_INET_XFRM_TUNNEL is not set 260# CONFIG_INET_XFRM_TUNNEL is not set
259# CONFIG_INET_TUNNEL is not set 261# CONFIG_INET_TUNNEL is not set
260CONFIG_INET_XFRM_MODE_TRANSPORT=y 262# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
261CONFIG_INET_XFRM_MODE_TUNNEL=y 263# CONFIG_INET_XFRM_MODE_TUNNEL is not set
262CONFIG_INET_XFRM_MODE_BEET=y 264# CONFIG_INET_XFRM_MODE_BEET is not set
263CONFIG_INET_DIAG=y 265CONFIG_INET_DIAG=y
264CONFIG_INET_TCP_DIAG=y 266CONFIG_INET_TCP_DIAG=y
265# CONFIG_TCP_CONG_ADVANCED is not set 267# CONFIG_TCP_CONG_ADVANCED is not set
@@ -319,22 +321,91 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
319# 321#
320CONFIG_STANDALONE=y 322CONFIG_STANDALONE=y
321CONFIG_PREVENT_FIRMWARE_BUILD=y 323CONFIG_PREVENT_FIRMWARE_BUILD=y
324# CONFIG_FW_LOADER is not set
325# CONFIG_DEBUG_DRIVER is not set
326# CONFIG_DEBUG_DEVRES is not set
322# CONFIG_SYS_HYPERVISOR is not set 327# CONFIG_SYS_HYPERVISOR is not set
323# CONFIG_CONNECTOR is not set 328# CONFIG_CONNECTOR is not set
324# CONFIG_MTD is not set 329CONFIG_MTD=y
330# CONFIG_MTD_DEBUG is not set
331# CONFIG_MTD_CONCAT is not set
332# CONFIG_MTD_PARTITIONS is not set
333
334#
335# User Modules And Translation Layers
336#
337CONFIG_MTD_CHAR=y
338CONFIG_MTD_BLKDEVS=y
339CONFIG_MTD_BLOCK=y
340# CONFIG_FTL is not set
341# CONFIG_NFTL is not set
342# CONFIG_INFTL is not set
343# CONFIG_RFD_FTL is not set
344# CONFIG_SSFDC is not set
345
346#
347# RAM/ROM/Flash chip drivers
348#
349# CONFIG_MTD_CFI is not set
350CONFIG_MTD_JEDECPROBE=y
351CONFIG_MTD_GEN_PROBE=y
352CONFIG_MTD_CFI_ADV_OPTIONS=y
353CONFIG_MTD_CFI_NOSWAP=y
354# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
355# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
356CONFIG_MTD_CFI_GEOMETRY=y
357# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
358# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
359CONFIG_MTD_MAP_BANK_WIDTH_4=y
360# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
361# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
362# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
363# CONFIG_MTD_CFI_I1 is not set
364# CONFIG_MTD_CFI_I2 is not set
365CONFIG_MTD_CFI_I4=y
366# CONFIG_MTD_CFI_I8 is not set
367# CONFIG_MTD_OTP is not set
368# CONFIG_MTD_CFI_INTELEXT is not set
369CONFIG_MTD_CFI_AMDSTD=y
370# CONFIG_MTD_CFI_STAA is not set
371CONFIG_MTD_CFI_UTIL=y
372# CONFIG_MTD_RAM is not set
373# CONFIG_MTD_ROM is not set
374# CONFIG_MTD_ABSENT is not set
375
376#
377# Mapping drivers for chip access
378#
379# CONFIG_MTD_COMPLEX_MAPPINGS is not set
380# CONFIG_MTD_PHYSMAP is not set
381CONFIG_MTD_PHYSMAP_OF=y
382# CONFIG_MTD_PLATRAM is not set
383
384#
385# Self-contained MTD device drivers
386#
387# CONFIG_MTD_SLRAM is not set
388# CONFIG_MTD_PHRAM is not set
389# CONFIG_MTD_MTDRAM is not set
390# CONFIG_MTD_BLOCK2MTD is not set
391
392#
393# Disk-On-Chip Device Drivers
394#
395# CONFIG_MTD_DOC2000 is not set
396# CONFIG_MTD_DOC2001 is not set
397# CONFIG_MTD_DOC2001PLUS is not set
398# CONFIG_MTD_NAND is not set
399# CONFIG_MTD_ONENAND is not set
400
401#
402# UBI - Unsorted block images
403#
404# CONFIG_MTD_UBI is not set
325CONFIG_OF_DEVICE=y 405CONFIG_OF_DEVICE=y
326# CONFIG_PARPORT is not set 406# CONFIG_PARPORT is not set
327CONFIG_BLK_DEV=y 407# CONFIG_BLK_DEV is not set
328# CONFIG_BLK_DEV_FD is not set 408# CONFIG_MISC_DEVICES is not set
329# CONFIG_BLK_DEV_COW_COMMON is not set
330CONFIG_BLK_DEV_LOOP=y
331# CONFIG_BLK_DEV_CRYPTOLOOP is not set
332# CONFIG_BLK_DEV_NBD is not set
333# CONFIG_BLK_DEV_RAM is not set
334# CONFIG_CDROM_PKTCDVD is not set
335# CONFIG_ATA_OVER_ETH is not set
336CONFIG_MISC_DEVICES=y
337# CONFIG_EEPROM_93CX6 is not set
338# CONFIG_IDE is not set 409# CONFIG_IDE is not set
339 410
340# 411#
@@ -368,16 +439,15 @@ CONFIG_DAVICOM_PHY=y
368# CONFIG_SMSC_PHY is not set 439# CONFIG_SMSC_PHY is not set
369# CONFIG_BROADCOM_PHY is not set 440# CONFIG_BROADCOM_PHY is not set
370# CONFIG_ICPLUS_PHY is not set 441# CONFIG_ICPLUS_PHY is not set
371CONFIG_FIXED_PHY=y 442# CONFIG_FIXED_PHY is not set
372CONFIG_FIXED_MII_10_FDX=y 443# CONFIG_MDIO_BITBANG is not set
373# CONFIG_FIXED_MII_100_FDX is not set
374CONFIG_NET_ETHERNET=y 444CONFIG_NET_ETHERNET=y
375CONFIG_MII=y 445CONFIG_MII=y
376CONFIG_FS_ENET=y 446CONFIG_FS_ENET=y
377CONFIG_FS_ENET_HAS_SCC=y 447# CONFIG_FS_ENET_HAS_SCC is not set
378CONFIG_FS_ENET_HAS_FEC=y 448CONFIG_FS_ENET_HAS_FEC=y
379CONFIG_NETDEV_1000=y 449# CONFIG_NETDEV_1000 is not set
380CONFIG_NETDEV_10000=y 450# CONFIG_NETDEV_10000 is not set
381 451
382# 452#
383# Wireless LAN 453# Wireless LAN
@@ -397,55 +467,12 @@ CONFIG_NETDEV_10000=y
397# 467#
398# Input device support 468# Input device support
399# 469#
400CONFIG_INPUT=y 470# CONFIG_INPUT is not set
401# CONFIG_INPUT_FF_MEMLESS is not set
402# CONFIG_INPUT_POLLDEV is not set
403
404#
405# Userland interfaces
406#
407CONFIG_INPUT_MOUSEDEV=y
408CONFIG_INPUT_MOUSEDEV_PSAUX=y
409CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
410CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
411# CONFIG_INPUT_JOYDEV is not set
412# CONFIG_INPUT_TSDEV is not set
413# CONFIG_INPUT_EVDEV is not set
414# CONFIG_INPUT_EVBUG is not set
415
416#
417# Input Device Drivers
418#
419CONFIG_INPUT_KEYBOARD=y
420CONFIG_KEYBOARD_ATKBD=y
421# CONFIG_KEYBOARD_SUNKBD is not set
422# CONFIG_KEYBOARD_LKKBD is not set
423# CONFIG_KEYBOARD_XTKBD is not set
424# CONFIG_KEYBOARD_NEWTON is not set
425# CONFIG_KEYBOARD_STOWAWAY is not set
426CONFIG_INPUT_MOUSE=y
427CONFIG_MOUSE_PS2=y
428CONFIG_MOUSE_PS2_ALPS=y
429CONFIG_MOUSE_PS2_LOGIPS2PP=y
430CONFIG_MOUSE_PS2_SYNAPTICS=y
431CONFIG_MOUSE_PS2_LIFEBOOK=y
432CONFIG_MOUSE_PS2_TRACKPOINT=y
433# CONFIG_MOUSE_PS2_TOUCHKIT is not set
434# CONFIG_MOUSE_SERIAL is not set
435# CONFIG_MOUSE_VSXXXAA is not set
436# CONFIG_INPUT_JOYSTICK is not set
437# CONFIG_INPUT_TABLET is not set
438# CONFIG_INPUT_TOUCHSCREEN is not set
439# CONFIG_INPUT_MISC is not set
440 471
441# 472#
442# Hardware I/O ports 473# Hardware I/O ports
443# 474#
444CONFIG_SERIO=y 475# CONFIG_SERIO is not set
445CONFIG_SERIO_I8042=y
446CONFIG_SERIO_SERPORT=y
447CONFIG_SERIO_LIBPS2=y
448# CONFIG_SERIO_RAW is not set
449# CONFIG_GAMEPORT is not set 476# CONFIG_GAMEPORT is not set
450 477
451# 478#
@@ -493,20 +520,7 @@ CONFIG_GEN_RTC=y
493# CONFIG_SPI_MASTER is not set 520# CONFIG_SPI_MASTER is not set
494# CONFIG_W1 is not set 521# CONFIG_W1 is not set
495# CONFIG_POWER_SUPPLY is not set 522# CONFIG_POWER_SUPPLY is not set
496CONFIG_HWMON=y 523# CONFIG_HWMON is not set
497# CONFIG_HWMON_VID is not set
498# CONFIG_SENSORS_ABITUGURU is not set
499# CONFIG_SENSORS_ABITUGURU3 is not set
500# CONFIG_SENSORS_F71805F is not set
501# CONFIG_SENSORS_IT87 is not set
502# CONFIG_SENSORS_PC87360 is not set
503# CONFIG_SENSORS_PC87427 is not set
504# CONFIG_SENSORS_SMSC47M1 is not set
505# CONFIG_SENSORS_SMSC47B397 is not set
506# CONFIG_SENSORS_VT1211 is not set
507# CONFIG_SENSORS_W83627HF is not set
508# CONFIG_SENSORS_W83627EHF is not set
509# CONFIG_HWMON_DEBUG_CHIP is not set
510 524
511# 525#
512# Multifunction device drivers 526# Multifunction device drivers
@@ -530,7 +544,7 @@ CONFIG_DAB=y
530# 544#
531# CONFIG_DISPLAY_SUPPORT is not set 545# CONFIG_DISPLAY_SUPPORT is not set
532# CONFIG_VGASTATE is not set 546# CONFIG_VGASTATE is not set
533CONFIG_VIDEO_OUTPUT_CONTROL=y 547# CONFIG_VIDEO_OUTPUT_CONTROL is not set
534# CONFIG_FB is not set 548# CONFIG_FB is not set
535# CONFIG_FB_IBM_GXT4500 is not set 549# CONFIG_FB_IBM_GXT4500 is not set
536 550
@@ -538,22 +552,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
538# Sound 552# Sound
539# 553#
540# CONFIG_SOUND is not set 554# CONFIG_SOUND is not set
541CONFIG_HID_SUPPORT=y 555# CONFIG_USB_SUPPORT is not set
542CONFIG_HID=y
543# CONFIG_HID_DEBUG is not set
544CONFIG_USB_SUPPORT=y
545# CONFIG_USB_ARCH_HAS_HCD is not set
546# CONFIG_USB_ARCH_HAS_OHCI is not set
547# CONFIG_USB_ARCH_HAS_EHCI is not set
548
549#
550# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
551#
552
553#
554# USB Gadget Support
555#
556# CONFIG_USB_GADGET is not set
557# CONFIG_MMC is not set 556# CONFIG_MMC is not set
558# CONFIG_NEW_LEDS is not set 557# CONFIG_NEW_LEDS is not set
559# CONFIG_EDAC is not set 558# CONFIG_EDAC is not set
@@ -580,19 +579,9 @@ CONFIG_USB_SUPPORT=y
580# 579#
581# File systems 580# File systems
582# 581#
583CONFIG_EXT2_FS=y 582# CONFIG_EXT2_FS is not set
584CONFIG_EXT2_FS_XATTR=y 583# CONFIG_EXT3_FS is not set
585# CONFIG_EXT2_FS_POSIX_ACL is not set
586# CONFIG_EXT2_FS_SECURITY is not set
587# CONFIG_EXT2_FS_XIP is not set
588CONFIG_EXT3_FS=y
589CONFIG_EXT3_FS_XATTR=y
590# CONFIG_EXT3_FS_POSIX_ACL is not set
591# CONFIG_EXT3_FS_SECURITY is not set
592# CONFIG_EXT4DEV_FS is not set 584# CONFIG_EXT4DEV_FS is not set
593CONFIG_JBD=y
594# CONFIG_JBD_DEBUG is not set
595CONFIG_FS_MBCACHE=y
596# CONFIG_REISERFS_FS is not set 585# CONFIG_REISERFS_FS is not set
597# CONFIG_JFS_FS is not set 586# CONFIG_JFS_FS is not set
598# CONFIG_FS_POSIX_ACL is not set 587# CONFIG_FS_POSIX_ACL is not set
@@ -601,10 +590,9 @@ CONFIG_FS_MBCACHE=y
601# CONFIG_OCFS2_FS is not set 590# CONFIG_OCFS2_FS is not set
602# CONFIG_MINIX_FS is not set 591# CONFIG_MINIX_FS is not set
603# CONFIG_ROMFS_FS is not set 592# CONFIG_ROMFS_FS is not set
604CONFIG_INOTIFY=y 593# CONFIG_INOTIFY is not set
605CONFIG_INOTIFY_USER=y
606# CONFIG_QUOTA is not set 594# CONFIG_QUOTA is not set
607CONFIG_DNOTIFY=y 595# CONFIG_DNOTIFY is not set
608# CONFIG_AUTOFS_FS is not set 596# CONFIG_AUTOFS_FS is not set
609# CONFIG_AUTOFS4_FS is not set 597# CONFIG_AUTOFS4_FS is not set
610# CONFIG_FUSE_FS is not set 598# CONFIG_FUSE_FS is not set
@@ -645,6 +633,7 @@ CONFIG_RAMFS=y
645# CONFIG_BEFS_FS is not set 633# CONFIG_BEFS_FS is not set
646# CONFIG_BFS_FS is not set 634# CONFIG_BFS_FS is not set
647# CONFIG_EFS_FS is not set 635# CONFIG_EFS_FS is not set
636# CONFIG_JFFS2_FS is not set
648CONFIG_CRAMFS=y 637CONFIG_CRAMFS=y
649# CONFIG_VXFS_FS is not set 638# CONFIG_VXFS_FS is not set
650# CONFIG_HPFS_FS is not set 639# CONFIG_HPFS_FS is not set
@@ -711,15 +700,13 @@ CONFIG_MSDOS_PARTITION=y
711# 700#
712# Library routines 701# Library routines
713# 702#
714CONFIG_BITREVERSE=y 703# CONFIG_CRC_CCITT is not set
715CONFIG_CRC_CCITT=y
716# CONFIG_CRC16 is not set 704# CONFIG_CRC16 is not set
717# CONFIG_CRC_ITU_T is not set 705# CONFIG_CRC_ITU_T is not set
718CONFIG_CRC32=y 706# CONFIG_CRC32 is not set
719# CONFIG_CRC7 is not set 707# CONFIG_CRC7 is not set
720# CONFIG_LIBCRC32C is not set 708# CONFIG_LIBCRC32C is not set
721CONFIG_ZLIB_INFLATE=y 709CONFIG_ZLIB_INFLATE=y
722CONFIG_PLIST=y
723CONFIG_HAS_IOMEM=y 710CONFIG_HAS_IOMEM=y
724CONFIG_HAS_IOPORT=y 711CONFIG_HAS_IOPORT=y
725CONFIG_HAS_DMA=y 712CONFIG_HAS_DMA=y
@@ -734,11 +721,33 @@ CONFIG_HAS_DMA=y
734# 721#
735# CONFIG_PRINTK_TIME is not set 722# CONFIG_PRINTK_TIME is not set
736CONFIG_ENABLE_MUST_CHECK=y 723CONFIG_ENABLE_MUST_CHECK=y
737# CONFIG_MAGIC_SYSRQ is not set 724CONFIG_MAGIC_SYSRQ=y
738# CONFIG_UNUSED_SYMBOLS is not set 725# CONFIG_UNUSED_SYMBOLS is not set
739# CONFIG_DEBUG_FS is not set 726# CONFIG_DEBUG_FS is not set
740# CONFIG_HEADERS_CHECK is not set 727# CONFIG_HEADERS_CHECK is not set
741# CONFIG_DEBUG_KERNEL is not set 728CONFIG_DEBUG_KERNEL=y
729# CONFIG_DEBUG_SHIRQ is not set
730CONFIG_DETECT_SOFTLOCKUP=y
731CONFIG_SCHED_DEBUG=y
732# CONFIG_SCHEDSTATS is not set
733# CONFIG_TIMER_STATS is not set
734# CONFIG_SLUB_DEBUG_ON is not set
735# CONFIG_DEBUG_SPINLOCK is not set
736# CONFIG_DEBUG_MUTEXES is not set
737# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
738# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
739# CONFIG_DEBUG_KOBJECT is not set
740CONFIG_DEBUG_BUGVERBOSE=y
741CONFIG_DEBUG_INFO=y
742# CONFIG_DEBUG_VM is not set
743# CONFIG_DEBUG_LIST is not set
744CONFIG_FORCED_INLINING=y
745# CONFIG_FAULT_INJECTION is not set
746# CONFIG_DEBUG_STACKOVERFLOW is not set
747# CONFIG_DEBUG_STACK_USAGE is not set
748# CONFIG_DEBUG_PAGEALLOC is not set
749# CONFIG_DEBUGGER is not set
750# CONFIG_BDI_SWITCH is not set
742# CONFIG_PPC_EARLY_DEBUG is not set 751# CONFIG_PPC_EARLY_DEBUG is not set
743 752
744# 753#
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 322b155f24ec..0d4ff0ae0746 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -26,6 +26,7 @@ config MPC86XADS
26config MPC885ADS 26config MPC885ADS
27 bool "MPC885ADS" 27 bool "MPC885ADS"
28 select CPM1 28 select CPM1
29 select PPC_CPM_NEW_BINDING
29 help 30 help
30 Freescale Semiconductor MPC885 Application Development System (ADS). 31 Freescale Semiconductor MPC885 Application Development System (ADS).
31 Also known as DUET. 32 Also known as DUET.
diff --git a/arch/powerpc/platforms/8xx/mpc885ads.h b/arch/powerpc/platforms/8xx/mpc885ads.h
index a21e528f26c6..a5076668bad6 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads.h
+++ b/arch/powerpc/platforms/8xx/mpc885ads.h
@@ -17,25 +17,10 @@
17 17
18#include <sysdev/fsl_soc.h> 18#include <sysdev/fsl_soc.h>
19 19
20/* U-Boot maps BCSR to 0xff080000 */
21#define BCSR_ADDR ((uint)0xff080000)
22#define BCSR_SIZE ((uint)32)
23#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
24#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
25#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
26#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
27#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
28
29#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
30#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
31
32#define MPC8xx_CPM_OFFSET (0x9c0) 20#define MPC8xx_CPM_OFFSET (0x9c0)
33#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET) 21#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
34#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver 22#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
35 23
36#define PCMCIA_MEM_ADDR ((uint)0xff020000)
37#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
38
39/* Bits of interest in the BCSRs. 24/* Bits of interest in the BCSRs.
40 */ 25 */
41#define BCSR1_ETHEN ((uint)0x20000000) 26#define BCSR1_ETHEN ((uint)0x20000000)
@@ -64,28 +49,5 @@
64#define BCSR5_MII1_EN 0x02 49#define BCSR5_MII1_EN 0x02
65#define BCSR5_MII1_RST 0x01 50#define BCSR5_MII1_RST 0x01
66 51
67/* Interrupt level assignments */
68#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
69#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
70#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
71#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
72
73/* We don't use the 8259 */
74#define NR_8259_INTS 0
75
76/* CPM Ethernet through SCC3 */
77#define PA_ENET_RXD ((ushort)0x0040)
78#define PA_ENET_TXD ((ushort)0x0080)
79#define PE_ENET_TCLK ((uint)0x00004000)
80#define PE_ENET_RCLK ((uint)0x00008000)
81#define PE_ENET_TENA ((uint)0x00000010)
82#define PC_ENET_CLSN ((ushort)0x0400)
83#define PC_ENET_RENA ((ushort)0x0800)
84
85/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
86 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
87#define SICR_ENET_MASK ((uint)0x00ff0000)
88#define SICR_ENET_CLKRT ((uint)0x002c0000)
89
90#endif /* __ASM_MPC885ADS_H__ */ 52#endif /* __ASM_MPC885ADS_H__ */
91#endif /* __KERNEL__ */ 53#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
index bad08683f7ae..2cf1b6a75173 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -1,11 +1,13 @@
1/*arch/powerpc/platforms/8xx/mpc885ads_setup.c 1/*
2 *
3 * Platform setup for the Freescale mpc885ads board 2 * Platform setup for the Freescale mpc885ads board
4 * 3 *
5 * Vitaly Bordug <vbordug@ru.mvista.com> 4 * Vitaly Bordug <vbordug@ru.mvista.com>
6 * 5 *
7 * Copyright 2005 MontaVista Software Inc. 6 * Copyright 2005 MontaVista Software Inc.
8 * 7 *
8 * Heavily modified by Scott Wood <scottwood@freescale.com>
9 * Copyright 2007 Freescale Semiconductor, Inc.
10 *
9 * This file is licensed under the terms of the GNU General Public License 11 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any 12 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied. 13 * kind, whether express or implied.
@@ -18,12 +20,12 @@
18#include <linux/ioport.h> 20#include <linux/ioport.h>
19#include <linux/device.h> 21#include <linux/device.h>
20#include <linux/delay.h> 22#include <linux/delay.h>
21#include <linux/root_dev.h>
22 23
23#include <linux/fs_enet_pd.h> 24#include <linux/fs_enet_pd.h>
24#include <linux/fs_uart_pd.h> 25#include <linux/fs_uart_pd.h>
25#include <linux/fsl_devices.h> 26#include <linux/fsl_devices.h>
26#include <linux/mii.h> 27#include <linux/mii.h>
28#include <linux/of_platform.h>
27 29
28#include <asm/delay.h> 30#include <asm/delay.h>
29#include <asm/io.h> 31#include <asm/io.h>
@@ -36,34 +38,24 @@
36#include <asm/8xx_immap.h> 38#include <asm/8xx_immap.h>
37#include <asm/commproc.h> 39#include <asm/commproc.h>
38#include <asm/fs_pd.h> 40#include <asm/fs_pd.h>
39#include <asm/prom.h> 41#include <asm/udbg.h>
40 42
41#include <sysdev/commproc.h> 43#include <sysdev/commproc.h>
42 44
43static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi); 45static u32 __iomem *bcsr, *bcsr5;
44static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
45static void init_scc3_ioports(struct fs_platform_info *ptr);
46 46
47#ifdef CONFIG_PCMCIA_M8XX 47#ifdef CONFIG_PCMCIA_M8XX
48static void pcmcia_hw_setup(int slot, int enable) 48static void pcmcia_hw_setup(int slot, int enable)
49{ 49{
50 unsigned *bcsr_io;
51
52 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
53 if (enable) 50 if (enable)
54 clrbits32(bcsr_io, BCSR1_PCCEN); 51 clrbits32(&bcsr[1], BCSR1_PCCEN);
55 else 52 else
56 setbits32(bcsr_io, BCSR1_PCCEN); 53 setbits32(&bcsr[1], BCSR1_PCCEN);
57
58 iounmap(bcsr_io);
59} 54}
60 55
61static int pcmcia_set_voltage(int slot, int vcc, int vpp) 56static int pcmcia_set_voltage(int slot, int vcc, int vpp)
62{ 57{
63 u32 reg = 0; 58 u32 reg = 0;
64 unsigned *bcsr_io;
65
66 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
67 59
68 switch (vcc) { 60 switch (vcc) {
69 case 0: 61 case 0:
@@ -98,334 +90,196 @@ static int pcmcia_set_voltage(int slot, int vcc, int vpp)
98 } 90 }
99 91
100 /* first, turn off all power */ 92 /* first, turn off all power */
101 clrbits32(bcsr_io, 0x00610000); 93 clrbits32(&bcsr[1], 0x00610000);
102 94
103 /* enable new powersettings */ 95 /* enable new powersettings */
104 setbits32(bcsr_io, reg); 96 setbits32(&bcsr[1], reg);
105 97
106 iounmap(bcsr_io);
107 return 0; 98 return 0;
108} 99}
109#endif 100#endif
110 101
111void __init mpc885ads_board_setup(void) 102struct cpm_pin {
112{ 103 int port, pin, flags;
113 cpm8xx_t *cp; 104};
114 unsigned int *bcsr_io;
115 u8 tmpval8;
116
117#ifdef CONFIG_FS_ENET
118 iop8xx_t *io_port;
119#endif
120
121 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
122 cp = (cpm8xx_t *) immr_map(im_cpm);
123
124 if (bcsr_io == NULL) {
125 printk(KERN_CRIT "Could not remap BCSR\n");
126 return;
127 }
128#ifdef CONFIG_SERIAL_CPM_SMC1
129 clrbits32(bcsr_io, BCSR1_RS232EN_1);
130 clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
131 tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
132 out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
133 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
134#else
135 setbits32(bcsr_io, BCSR1_RS232EN_1);
136 out_be16(&cp->cp_smc[0].smc_smcmr, 0);
137 out_8(&cp->cp_smc[0].smc_smce, 0);
138#endif
139
140#ifdef CONFIG_SERIAL_CPM_SMC2
141 clrbits32(bcsr_io, BCSR1_RS232EN_2);
142 clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
143 setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
144 tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
145 out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
146 clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
147
148 init_smc2_uart_ioports(0);
149#else
150 setbits32(bcsr_io, BCSR1_RS232EN_2);
151 out_be16(&cp->cp_smc[1].smc_smcmr, 0);
152 out_8(&cp->cp_smc[1].smc_smce, 0);
153#endif
154 immr_unmap(cp);
155 iounmap(bcsr_io);
156
157#ifdef CONFIG_FS_ENET
158 /* use MDC for MII (common) */
159 io_port = (iop8xx_t *) immr_map(im_ioport);
160 setbits16(&io_port->iop_pdpar, 0x0080);
161 clrbits16(&io_port->iop_pddir, 0x0080);
162
163 bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
164 clrbits32(bcsr_io, BCSR5_MII1_EN);
165 clrbits32(bcsr_io, BCSR5_MII1_RST);
166#ifndef CONFIG_FC_ENET_HAS_SCC
167 clrbits32(bcsr_io, BCSR5_MII2_EN);
168 clrbits32(bcsr_io, BCSR5_MII2_RST);
169 105
170#endif 106static struct cpm_pin mpc885ads_pins[] = {
171 iounmap(bcsr_io); 107 /* SMC1 */
172 immr_unmap(io_port); 108 {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
109 {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
173 110
111 /* SMC2 */
112#ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
113 {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
114 {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
174#endif 115#endif
175 116
176#ifdef CONFIG_PCMCIA_M8XX 117 /* SCC3 */
177 /*Set up board specific hook-ups */ 118 {CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
178 m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup; 119 {CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
179 m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage; 120 {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
121 {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
122 {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
123 {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
124 {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
125
126 /* MII1 */
127 {CPM_PORTA, 0, CPM_PIN_INPUT},
128 {CPM_PORTA, 1, CPM_PIN_INPUT},
129 {CPM_PORTA, 2, CPM_PIN_INPUT},
130 {CPM_PORTA, 3, CPM_PIN_INPUT},
131 {CPM_PORTA, 4, CPM_PIN_OUTPUT},
132 {CPM_PORTA, 10, CPM_PIN_OUTPUT},
133 {CPM_PORTA, 11, CPM_PIN_OUTPUT},
134 {CPM_PORTB, 19, CPM_PIN_INPUT},
135 {CPM_PORTB, 31, CPM_PIN_INPUT},
136 {CPM_PORTC, 12, CPM_PIN_INPUT},
137 {CPM_PORTC, 13, CPM_PIN_INPUT},
138 {CPM_PORTE, 30, CPM_PIN_OUTPUT},
139 {CPM_PORTE, 31, CPM_PIN_OUTPUT},
140
141 /* MII2 */
142#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
143 {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
144 {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
145 {CPM_PORTE, 16, CPM_PIN_OUTPUT},
146 {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
147 {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
148 {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
149 {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
150 {CPM_PORTE, 21, CPM_PIN_OUTPUT},
151 {CPM_PORTE, 22, CPM_PIN_OUTPUT},
152 {CPM_PORTE, 23, CPM_PIN_OUTPUT},
153 {CPM_PORTE, 24, CPM_PIN_OUTPUT},
154 {CPM_PORTE, 25, CPM_PIN_OUTPUT},
155 {CPM_PORTE, 26, CPM_PIN_OUTPUT},
156 {CPM_PORTE, 27, CPM_PIN_OUTPUT},
157 {CPM_PORTE, 28, CPM_PIN_OUTPUT},
158 {CPM_PORTE, 29, CPM_PIN_OUTPUT},
180#endif 159#endif
181} 160};
182 161
183static void init_fec1_ioports(struct fs_platform_info *ptr) 162static void __init init_ioports(void)
184{ 163{
185 cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm); 164 int i;
186 iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
187
188 /* configure FEC1 pins */
189 setbits16(&io_port->iop_papar, 0xf830);
190 setbits16(&io_port->iop_padir, 0x0830);
191 clrbits16(&io_port->iop_padir, 0xf000);
192
193 setbits32(&cp->cp_pbpar, 0x00001001);
194 clrbits32(&cp->cp_pbdir, 0x00001001);
195 165
196 setbits16(&io_port->iop_pcpar, 0x000c); 166 for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
197 clrbits16(&io_port->iop_pcdir, 0x000c); 167 struct cpm_pin *pin = &mpc885ads_pins[i];
168 cpm1_set_pin(pin->port, pin->pin, pin->flags);
169 }
198 170
199 setbits32(&cp->cp_pepar, 0x00000003); 171 cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
200 setbits32(&cp->cp_pedir, 0x00000003); 172 cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
201 clrbits32(&cp->cp_peso, 0x00000003); 173 cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
202 clrbits32(&cp->cp_cptr, 0x00000100); 174 cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
203 175
204 immr_unmap(io_port); 176 /* Set FEC1 and FEC2 to MII mode */
205 immr_unmap(cp); 177 clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
206} 178}
207 179
208static void init_fec2_ioports(struct fs_platform_info *ptr) 180static void __init mpc885ads_setup_arch(void)
209{ 181{
210 cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm); 182 struct device_node *np;
211 iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
212
213 /* configure FEC2 pins */
214 setbits32(&cp->cp_pepar, 0x0003fffc);
215 setbits32(&cp->cp_pedir, 0x0003fffc);
216 clrbits32(&cp->cp_peso, 0x000087fc);
217 setbits32(&cp->cp_peso, 0x00037800);
218 clrbits32(&cp->cp_cptr, 0x00000080);
219
220 immr_unmap(io_port);
221 immr_unmap(cp);
222}
223 183
224void init_fec_ioports(struct fs_platform_info *fpi) 184 cpm_reset();
225{ 185 init_ioports();
226 int fec_no = fs_get_fec_index(fpi->fs_no);
227 186
228 switch (fec_no) { 187 np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
229 case 0: 188 if (!np) {
230 init_fec1_ioports(fpi); 189 printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
231 break;
232 case 1:
233 init_fec2_ioports(fpi);
234 break;
235 default:
236 printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
237 return; 190 return;
238 } 191 }
239}
240 192
241static void init_scc3_ioports(struct fs_platform_info *fpi) 193 bcsr = of_iomap(np, 0);
242{ 194 bcsr5 = of_iomap(np, 1);
243 unsigned *bcsr_io; 195 of_node_put(np);
244 iop8xx_t *io_port;
245 cpm8xx_t *cp;
246 196
247 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); 197 if (!bcsr || !bcsr5) {
248 io_port = (iop8xx_t *) immr_map(im_ioport);
249 cp = (cpm8xx_t *) immr_map(im_cpm);
250
251 if (bcsr_io == NULL) {
252 printk(KERN_CRIT "Could not remap BCSR\n"); 198 printk(KERN_CRIT "Could not remap BCSR\n");
253 return; 199 return;
254 } 200 }
255 201
256 /* Enable the PHY. 202 clrbits32(&bcsr[1], BCSR1_RS232EN_1);
257 */ 203#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
258 clrbits32(bcsr_io + 4, BCSR4_ETH10_RST); 204 setbits32(&bcsr[1], BCSR1_RS232EN_2);
259 udelay(1000); 205#else
260 setbits32(bcsr_io + 4, BCSR4_ETH10_RST); 206 clrbits32(&bcsr[1], BCSR1_RS232EN_2);
261 /* Configure port A pins for Txd and Rxd. 207#endif
262 */
263 setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
264 clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
265 208
266 /* Configure port C pins to enable CLSN and RENA. 209 clrbits32(bcsr5, BCSR5_MII1_EN);
267 */ 210 setbits32(bcsr5, BCSR5_MII1_RST);
268 clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); 211 udelay(1000);
269 clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); 212 clrbits32(bcsr5, BCSR5_MII1_RST);
270 setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
271 213
272 /* Configure port E for TCLK and RCLK. 214#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
273 */ 215 clrbits32(bcsr5, BCSR5_MII2_EN);
274 setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK); 216 setbits32(bcsr5, BCSR5_MII2_RST);
275 clrbits32(&cp->cp_pepar, PE_ENET_TENA); 217 udelay(1000);
276 clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA); 218 clrbits32(bcsr5, BCSR5_MII2_RST);
277 clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK); 219#else
278 setbits32(&cp->cp_peso, PE_ENET_TENA); 220 setbits32(bcsr5, BCSR5_MII2_EN);
279 221#endif
280 /* Configure Serial Interface clock routing.
281 * First, clear all SCC bits to zero, then set the ones we want.
282 */
283 clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
284 setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
285 222
286 /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used. 223#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
287 */ 224 clrbits32(&bcsr[4], BCSR4_ETH10_RST);
288 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); 225 udelay(1000);
289 /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode 226 setbits32(&bcsr[4], BCSR4_ETH10_RST);
290 * by H/W setting after reset. SCC ethernet controller support only half duplex.
291 * This discrepancy of modes causes a lot of carrier lost errors.
292 */
293 227
294 /* In the original SCC enet driver the following code is placed at 228 setbits32(&bcsr[1], BCSR1_ETHEN);
295 the end of the initialization */
296 setbits32(&cp->cp_pepar, PE_ENET_TENA);
297 clrbits32(&cp->cp_pedir, PE_ENET_TENA);
298 setbits32(&cp->cp_peso, PE_ENET_TENA);
299 229
300 setbits32(bcsr_io + 4, BCSR1_ETHEN); 230 np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
301 iounmap(bcsr_io); 231#else
302 immr_unmap(io_port); 232 np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
303 immr_unmap(cp); 233#endif
304}
305 234
306void init_scc_ioports(struct fs_platform_info *fpi) 235 /* The SCC3 enet registers overlap the SMC1 registers, so
307{ 236 * one of the two must be removed from the device tree.
308 int scc_no = fs_get_scc_index(fpi->fs_no); 237 */
309 238
310 switch (scc_no) { 239 if (np) {
311 case 2: 240 of_detach_node(np);
312 init_scc3_ioports(fpi); 241 of_node_put(np);
313 break;
314 default:
315 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
316 return;
317 } 242 }
318}
319
320static void init_smc1_uart_ioports(struct fs_uart_platform_info *ptr)
321{
322 unsigned *bcsr_io;
323 cpm8xx_t *cp;
324
325 cp = (cpm8xx_t *) immr_map(im_cpm);
326 setbits32(&cp->cp_pepar, 0x000000c0);
327 clrbits32(&cp->cp_pedir, 0x000000c0);
328 clrbits32(&cp->cp_peso, 0x00000040);
329 setbits32(&cp->cp_peso, 0x00000080);
330 immr_unmap(cp);
331
332 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
333 243
334 if (bcsr_io == NULL) { 244#ifdef CONFIG_PCMCIA_M8XX
335 printk(KERN_CRIT "Could not remap BCSR1\n"); 245 /* Set up board specific hook-ups.*/
336 return; 246 m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
337 } 247 m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
338 clrbits32(bcsr_io, BCSR1_RS232EN_1); 248#endif
339 iounmap(bcsr_io);
340} 249}
341 250
342static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi) 251static int __init mpc885ads_probe(void)
343{ 252{
344 unsigned *bcsr_io; 253 unsigned long root = of_get_flat_dt_root();
345 cpm8xx_t *cp; 254 return of_flat_dt_is_compatible(root, "fsl,mpc885ads");
346
347 cp = (cpm8xx_t *) immr_map(im_cpm);
348 setbits32(&cp->cp_pepar, 0x00000c00);
349 clrbits32(&cp->cp_pedir, 0x00000c00);
350 clrbits32(&cp->cp_peso, 0x00000400);
351 setbits32(&cp->cp_peso, 0x00000800);
352 immr_unmap(cp);
353
354 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
355
356 if (bcsr_io == NULL) {
357 printk(KERN_CRIT "Could not remap BCSR1\n");
358 return;
359 }
360 clrbits32(bcsr_io, BCSR1_RS232EN_2);
361 iounmap(bcsr_io);
362} 255}
363 256
364void init_smc_ioports(struct fs_uart_platform_info *data) 257static struct of_device_id __initdata of_bus_ids[] = {
365{ 258 { .name = "soc", },
366 int smc_no = fs_uart_id_fsid2smc(data->fs_no); 259 { .name = "cpm", },
367 260 { .name = "localbus", },
368 switch (smc_no) { 261 {},
369 case 0: 262};
370 init_smc1_uart_ioports(data);
371 data->brg = data->clk_rx;
372 break;
373 case 1:
374 init_smc2_uart_ioports(data);
375 data->brg = data->clk_rx;
376 break;
377 default:
378 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
379 return;
380 }
381}
382 263
383int platform_device_skip(const char *model, int id) 264static int __init declare_of_platform_devices(void)
384{ 265{
385#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 266 /* Publish the QE devices */
386 const char *dev = "FEC"; 267 if (machine_is(mpc885_ads))
387 int n = 2; 268 of_platform_bus_probe(NULL, of_bus_ids, NULL);
388#else
389 const char *dev = "SCC";
390 int n = 3;
391#endif
392
393 if (!strcmp(model, dev) && n == id)
394 return 1;
395 269
396 return 0; 270 return 0;
397} 271}
398 272device_initcall(declare_of_platform_devices);
399static void __init mpc885ads_setup_arch(void) 273
400{ 274define_machine(mpc885_ads) {
401 cpm_reset(); 275 .name = "Freescale MPC885 ADS",
402 276 .probe = mpc885ads_probe,
403 mpc885ads_board_setup(); 277 .setup_arch = mpc885ads_setup_arch,
404 278 .init_IRQ = m8xx_pic_init,
405 ROOT_DEV = Root_NFS; 279 .get_irq = mpc8xx_get_irq,
406} 280 .restart = mpc8xx_restart,
407 281 .calibrate_decr = mpc8xx_calibrate_decr,
408static int __init mpc885ads_probe(void) 282 .set_rtc_time = mpc8xx_set_rtc_time,
409{ 283 .get_rtc_time = mpc8xx_get_rtc_time,
410 char *model = of_get_flat_dt_prop(of_get_flat_dt_root(), 284 .progress = udbg_progress,
411 "model", NULL);
412 if (model == NULL)
413 return 0;
414 if (strcmp(model, "MPC885ADS"))
415 return 0;
416
417 return 1;
418}
419
420define_machine(mpc885_ads)
421{
422 .name = "MPC885 ADS",
423 .probe = mpc885ads_probe,
424 .setup_arch = mpc885ads_setup_arch,
425 .init_IRQ = m8xx_pic_init,
426 .get_irq = mpc8xx_get_irq,
427 .restart = mpc8xx_restart,
428 .calibrate_decr = mpc8xx_calibrate_decr,
429 .set_rtc_time = mpc8xx_set_rtc_time,
430 .get_rtc_time = mpc8xx_get_rtc_time,
431}; 285};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 20:19:42 -0500