Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

From Kukjin Kim <kgene.kim@samsung.com>:

add suppport common clock framework for exynos

* tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits)
  ARM: EXYNOS: fix compilation error introduced due to common clock migration
  clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
  clk: exynos4: export clocks required for fimc-is
  clk: samsung: Fix compilation error
  clk: exynos5250: register display block gate clocks to common clock framework
  clk: exynos4: Add support for SoC-specific register save list
  clk: exynos4: Add missing registers to suspend save list
  clk: exynos4: Remove E4X12 prefix from SRC_DMC register
  clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
  clk: exynos4: Add E4210 prefix to LCD1 clock registers
  clk: exynos4: Remove SoC-specific registers from save list
  clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
  clk: exynos4: Define {E,V}PLL registers
  clk: exynos4: Add missing mout_sata on Exynos4210
  clk: exynos4: Add missing CMU_TOP and ISP clocks
  clk: exynos4: Add G3D clocks
  clk: exynos4: Add camera related clock definitions
  clk: exynos4: Export mout_core clock of Exynos4210
  clk: samsung: Remove unimplemented ops for pll
  clk: exynos4: Export clocks used by exynos cpufreq drivers
  ...

[arnd: add missing #address-cells property in mshc DT node]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

38 files changed, 1223 insertions, 4111 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 03301cb114ac..1dc16e539808 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -866,6 +866,7 @@ config ARCH_EXYNOS
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_SPARSEMEM_ENABLE
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..d3cd880d70b3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -42,7 +42,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
+        exynos4412-odroidx.dtb \
         exynos4412-smdk4412.dtb \
+        exynos4412-origen.dtb \
+        exynos5250-arndale.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
         exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 46c098017036..62eceb4f0d3f 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -24,6 +24,144 @@
                 samsung,i2c-max-bus-freq = <378000>;
                 gpios = <&gpb3 0 2 3 0>,
                         <&gpb3 1 2 3 0>;
+
+                max77686@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "P1.0V_LDO_OUT1";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "P1.8V_LDO_OUT2";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "P1.8V_LDO_OUT3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "P1.1V_LDO_OUT7";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "P1.0V_LDO_OUT8";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "P1.8V_LDO_OUT10";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "P3.0V_LDO_OUT12";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "P1.8V_LDO_OUT14";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "P1.0V_LDO_OUT15";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "P1.8V_LDO_OUT16";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "P1.8V_BUCK_OUT5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "P1.35V_BUCK_OUT6";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "P2.0V_BUCK_OUT7";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "P2.85V_BUCK_OUT8";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
         };
 
         i2c@12C70000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1a62bcf18aa3..9ac47d51c407 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -86,6 +86,8 @@
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 43 0>;
+                clocks = <&clock 345>;
+                clock-names = "watchdog";
                 status = "disabled";
         };
 
@@ -93,6 +95,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x10070000 0x100>;
                 interrupts = <0 44 0>, <0 45 0>;
+                clocks = <&clock 346>;
+                clock-names = "rtc";
                 status = "disabled";
         };
 
@@ -100,6 +104,8 @@
                 compatible = "samsung,s5pv210-keypad";
                 reg = <0x100A0000 0x100>;
                 interrupts = <0 109 0>;
+                clocks = <&clock 347>;
+                clock-names = "keypad";
                 status = "disabled";
         };
 
@@ -107,6 +113,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12510000 0x100>;
                 interrupts = <0 73 0>;
+                clocks = <&clock 297>, <&clock 145>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -114,6 +122,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12520000 0x100>;
                 interrupts = <0 74 0>;
+                clocks = <&clock 298>, <&clock 146>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -121,6 +131,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12530000 0x100>;
                 interrupts = <0 75 0>;
+                clocks = <&clock 299>, <&clock 147>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -128,6 +140,16 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12540000 0x100>;
                 interrupts = <0 76 0>;
+                clocks = <&clock 300>, <&clock 148>;
+                clock-names = "hsmmc", "mmc_busclk.2";
+                status = "disabled";
+        };
+
+        mfc: codec@13400000 {
+                compatible = "samsung,mfc-v5";
+                reg = <0x13400000 0x10000>;
+                interrupts = <0 94 0>;
+                samsung,power-domain = <&pd_mfc>;
                 status = "disabled";
         };
 
@@ -135,6 +157,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13800000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 312>, <&clock 151>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -142,6 +166,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13810000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 313>, <&clock 152>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -149,6 +175,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13820000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -156,6 +184,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13830000 0x100>;
                 interrupts = <0 55 0>;
+                clocks = <&clock 315>, <&clock 154>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -165,6 +195,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13860000 0x100>;
                 interrupts = <0 58 0>;
+                clocks = <&clock 317>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -174,6 +206,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13870000 0x100>;
                 interrupts = <0 59 0>;
+                clocks = <&clock 318>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -183,6 +217,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13880000 0x100>;
                 interrupts = <0 60 0>;
+                clocks = <&clock 319>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -192,6 +228,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13890000 0x100>;
                 interrupts = <0 61 0>;
+                clocks = <&clock 320>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -201,6 +239,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138A0000 0x100>;
                 interrupts = <0 62 0>;
+                clocks = <&clock 321>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -210,6 +250,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138B0000 0x100>;
                 interrupts = <0 63 0>;
+                clocks = <&clock 322>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -219,6 +261,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138C0000 0x100>;
                 interrupts = <0 64 0>;
+                clocks = <&clock 323>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -228,6 +272,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138D0000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 324>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -239,6 +285,8 @@
                 rx-dma-channel = <&pdma0 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 327>, <&clock 159>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -250,6 +298,8 @@
                 rx-dma-channel = <&pdma1 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 328>, <&clock 160>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -261,6 +311,8 @@
                 rx-dma-channel = <&pdma0 8>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 329>, <&clock 161>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -275,6 +327,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12680000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 292>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -284,6 +338,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12690000 0x1000>;
                         interrupts = <0 36 0>;
+                        clocks = <&clock 293>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -293,6 +349,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12850000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 279>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f2710018e84e..1b30bc8e2654 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -121,4 +127,16 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f63490707f3a..f52c86e2d424 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -189,4 +195,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <12000000>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index c346b64dff55..9a14484c7bb1 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,4 +289,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 49a2786e00b9..ff23ae29f5cf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -55,6 +55,8 @@
                 interrupt-parent = <&mct_map>;
                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
                              <4 0>, <5 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
 
                 mct_map: mct-map {
                         #interrupt-cells = <2>;
@@ -69,6 +71,12 @@
                 };
         };
 
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4210-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4210-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 000000000000..53bc8bf77984
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,111 @@
+/*
+ * Hardkernel's Exynos4412 based ODROID-X board device tree source
+ *
+ * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
+ *
+ * Device tree source file for Hardkernel's ODROID-X board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Hardkernel ODROID-X board based on Exynos4412";
+        compatible = "hardkernel,odroid-x", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        label = "led1:heart";
+                        gpios = <&gpc1 0 1>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led2 {
+                        label = "led2:mmc0";
+                        gpios = <&gpc1 2 1>;
+                        default-state = "on";
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        regulator_p3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "p3v3_en";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpa1 1 1>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        rtc@10070000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
new file mode 100644
index 000000000000..1fecf7666dc0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -0,0 +1,432 @@
+/*
+ * Insignal's Exynos4412 based Origen board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Insignal Origen evaluation board based on Exynos4412";
+        compatible = "insignal,origen4412", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs ="console=ttySAC2,115200";
+        };
+
+        mmc_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpx1 1 0>;
+                enable-active-high;
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                vmmc-supply = <&mmc_reg>;
+                status = "okay";
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                s5m8767_pmic@66 {
+                        compatible = "samsung,s5m8767-pmic";
+                        reg = <0x66>;
+
+                        s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+                        s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
+                                                         <&gpx2 4 0>,
+                                                         <&gpx2 5 0>;
+
+                        s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
+                                                        <&gpm3 6 0>,
+                                                        <&gpm3 7 0>;
+
+                        s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>;
+
+                        s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDIOAP_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_PRE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDD18_2M";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VDD10_MIPI";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VDD33_LCD";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD18_MIPI";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_UOTG";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDIOPERI_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB02";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_USH";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDDIOAP_MMC012_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo18_reg: LDO18 {
+                                        regulator-name = "VDDIOPERI_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo19_reg: LDO19 {
+                                        regulator-name = "DVDD25";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "VDD28_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD28_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo22_reg: LDO22 {
+                                        regulator-name = "VDDA28_2M";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo23_reg: LDO23 {
+                                        regulator-name = "VDD28_TF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo24_reg: LDO24 {
+                                        regulator-name = "VDD33_A31";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDD18_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo26_reg: LDO26 {
+                                        regulator-name = "VDD18_A31";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo27_reg: LDO27 {
+                                        regulator-name = "GPS_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo28_reg: LDO28 {
+                                        regulator-name = "DVDD12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <925000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "vdd_m12";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "vdd12_5m";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "vddf28_emmc";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+                        };
+                };
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf575cc45..874beeaef99d 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,6 +27,19 @@
                 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
         };
 
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -42,4 +55,16 @@
         serial@13830000 {
                 status = "okay";
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 821c9fdd1e3b..d75c047e80a9 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -34,6 +34,8 @@
                 interrupt-parent = <&mct_map>;
                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
                              <4 0>, <5 0>, <6 0>, <7 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
 
                 mct_map: mct-map {
                         #interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 9a8780694909..7496b8d633ea 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
                              <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
         };
 
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4412-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4x12-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
new file mode 100644
index 000000000000..5de019cb0e58
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -0,0 +1,129 @@
+/*
+ * Samsung's Exynos5250 based Arndale board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+        model = "Insignal Arndale evaluation board based on EXYNOS5250";
+        compatible = "insignal,arndale", "samsung,exynos5250";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200";
+        };
+
+        i2c@12C60000 {
+                status = "disabled";
+        };
+
+        i2c@12C70000 {
+                status = "disabled";
+        };
+
+        i2c@12C80000 {
+                status = "disabled";
+        };
+
+        i2c@12C90000 {
+                status = "disabled";
+        };
+
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+
+        i2c@12CB0000 {
+                status = "disabled";
+        };
+
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+
+        i2c@12CD0000 {
+                status = "disabled";
+        };
+
+        i2c@121D0000 {
+                status = "disabled";
+        };
+
+        dwmmc_0: dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
+                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
+                };
+        };
+
+        dwmmc_1: dwmmc1@12210000 {
+                status = "disabled";
+        };
+
+        dwmmc_2: dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
+                };
+        };
+
+        dwmmc_3: dwmmc3@12230000 {
+                status = "disabled";
+        };
+
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1b8d4106d338..872ae1f93c75 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -231,4 +231,24 @@
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&wm8994>;
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+        };
+
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 17dd951c1cd2..babd9f9b1bf9 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -40,4 +40,15 @@
                                 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
                 };
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx1 1 1 3 3>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index c60108e0d27e..f8c9964f367c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,22 @@
                 i2c8 = &i2c_8;
         };
 
+        pd_gsc: gsc-power-domain@0x10044000 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044000 0x20>;
+        };
+
+        pd_mfc: mfc-power-domain@0x10044040 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044040 0x20>;
+        };
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5250-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -77,6 +93,8 @@
                 interrupt-parent = <&mct_map>;
                 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
                              <4 0>, <5 0>;
+                clocks = <&clock 1>, <&clock 335>;
+                clock-names = "fin_pll", "mct";
 
                 mct_map: mct-map {
                         #interrupt-cells = <2>;
@@ -95,54 +113,71 @@
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
                 interrupts = <0 42 0>;
+                clocks = <&clock 336>;
+                clock-names = "watchdog";
         };
 
         codec@11000000 {
                 compatible = "samsung,mfc-v6";
                 reg = <0x11000000 0x10000>;
                 interrupts = <0 96 0>;
+                samsung,power-domain = <&pd_mfc>;
         };
 
         rtc {
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x101E0000 0x100>;
                 interrupts = <0 43 0>, <0 44 0>;
+                clocks = <&clock 337>;
+                clock-names = "rtc";
         };
 
         tmu@10060000 {
                 compatible = "samsung,exynos5250-tmu";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 338>;
+                clock-names = "tmu_apbif";
         };
 
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
                 interrupts = <0 51 0>;
+                clocks = <&clock 289>, <&clock 146>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C10000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C10000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 290>, <&clock 147>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C20000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C20000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 291>, <&clock 148>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C30000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C30000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 292>, <&clock 149>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         sata@122F0000 {
                 compatible = "samsung,exynos5-sata-ahci";
                 reg = <0x122F0000 0x1ff>;
                 interrupts = <0 115 0>;
+                clocks = <&clock 277>, <&clock 143>;
+                clock-names = "sata", "sclk_sata";
         };
 
         sata-phy@12170000 {
@@ -156,6 +191,8 @@
                 interrupts = <0 56 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 294>;
+                clock-names = "i2c";
         };
 
         i2c_1: i2c@12C70000 {
@@ -164,6 +201,8 @@
                 interrupts = <0 57 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 295>;
+                clock-names = "i2c";
         };
 
         i2c_2: i2c@12C80000 {
@@ -172,6 +211,8 @@
                 interrupts = <0 58 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 296>;
+                clock-names = "i2c";
         };
 
         i2c_3: i2c@12C90000 {
@@ -180,6 +221,8 @@
                 interrupts = <0 59 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 297>;
+                clock-names = "i2c";
         };
 
         i2c_4: i2c@12CA0000 {
@@ -188,6 +231,8 @@
                 interrupts = <0 60 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 298>;
+                clock-names = "i2c";
         };
 
         i2c_5: i2c@12CB0000 {
@@ -196,6 +241,8 @@
                 interrupts = <0 61 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 299>;
+                clock-names = "i2c";
         };
 
         i2c_6: i2c@12CC0000 {
@@ -204,6 +251,8 @@
                 interrupts = <0 62 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 300>;
+                clock-names = "i2c";
         };
 
         i2c_7: i2c@12CD0000 {
@@ -212,6 +261,8 @@
                 interrupts = <0 63 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 301>;
+                clock-names = "i2c";
         };
 
         i2c_8: i2c@12CE0000 {
@@ -220,6 +271,8 @@
                 interrupts = <0 64 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 302>;
+                clock-names = "i2c";
         };
 
         i2c@121D0000 {
@@ -227,6 +280,8 @@
                 reg = <0x121D0000 0x100>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 288>;
+                clock-names = "i2c";
         };
 
         spi_0: spi@12d20000 {
@@ -238,6 +293,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 304>, <&clock 154>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_1: spi@12d30000 {
@@ -249,6 +306,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 305>, <&clock 155>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_2: spi@12d40000 {
@@ -260,6 +319,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 306>, <&clock 156>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         dwmmc_0: dwmmc0@12200000 {
@@ -268,6 +329,8 @@
                 interrupts = <0 75 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 280>, <&clock 139>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_1: dwmmc1@12210000 {
@@ -276,6 +339,8 @@
                 interrupts = <0 76 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 281>, <&clock 140>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_2: dwmmc2@12220000 {
@@ -284,6 +349,8 @@
                 interrupts = <0 77 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 282>, <&clock 141>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_3: dwmmc3@12230000 {
@@ -292,6 +359,8 @@
                 interrupts = <0 78 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 283>, <&clock 142>;
+                clock-names = "biu", "ciu";
         };
 
         i2s0: i2s@03830000 {
@@ -323,6 +392,18 @@
                 dma-names = "tx", "rx";
         };
 
+        usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
+        usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -334,6 +415,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121A0000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 275>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -343,6 +426,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121B0000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 276>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -352,6 +437,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -361,6 +448,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -614,34 +703,51 @@
                 };
         };
 
+
         gsc_0:  gsc@0x13e00000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e00000 0x1000>;
                 interrupts = <0 85 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 256>;
+                clock-names = "gscl";
         };
 
         gsc_1:  gsc@0x13e10000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e10000 0x1000>;
                 interrupts = <0 86 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 257>;
+                clock-names = "gscl";
         };
 
         gsc_2:  gsc@0x13e20000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e20000 0x1000>;
                 interrupts = <0 87 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 258>;
+                clock-names = "gscl";
         };
 
         gsc_3:  gsc@0x13e30000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e30000 0x1000>;
                 interrupts = <0 88 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 259>;
+                clock-names = "gscl";
         };
 
         hdmi {
                 compatible = "samsung,exynos5-hdmi";
                 reg = <0x14530000 0x70000>;
                 interrupts = <0 95 0>;
+                clocks = <&clock 333>, <&clock 136>, <&clock 137>,
+                                <&clock 333>, <&clock 333>;
+                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                "sclk_hdmiphy", "hdmiphy";
         };
 
         mixer {
@@ -649,4 +755,18 @@
                 reg = <0x14450000 0x10000>;
                 interrupts = <0 94 0>;
         };
+
+        dp-controller {
+                compatible = "samsung,exynos5-dp";
+                reg = <0x145b0000 0x1000>;
+                interrupts = <10 3>;
+                interrupt-parent = <&combiner>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                dptx-phy {
+                        reg = <0x10040720>;
+                        samsung,enable-mask = <1>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 81e2c964a900..a21eb4cbe893 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -28,19 +28,10 @@
                 status = "disabled";
         };
 
-        i2c@F0000 {
-                status = "disabled";
-        };
-
-        i2c@100000 {
-                status = "disabled";
-        };
-
-        watchdog {
-                status = "disabled";
-        };
-
-        rtc {
-                status = "disabled";
+        fixed-rate-clocks {
+                xtal {
+                        compatible = "samsung,clock-xtal";
+                        clock-frequency = <50000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9a99755920c0..c374a31e9c3d 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,12 @@
 
         interrupt-parent = <&gic>;
 
+        clock: clock-controller@0x160000 {
+                compatible = "samsung,exynos5440-clock";
+                reg = <0x160000 0x1000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@2E0000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
@@ -24,55 +30,51 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 13 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <0>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <1>;
                 };
                 cpu@2 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <2>;
                 };
                 cpu@3 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <3>;
                 };
         };
 
-        common {
-                compatible = "samsung,exynos5440";
-
+        timer {
+                compatible = "arm,cortex-a15-timer",
+                             "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+                clock-frequency = <50000000>;
         };
 
         serial@B0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xB0000 0x1000>;
                 interrupts = <0 2 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@C0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xC0000 0x1000>;
                 interrupts = <0 3 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         spi {
@@ -83,6 +85,8 @@
                 rx-dma-channel = <&pdma0 4>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>, <&clock 16>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         pinctrl {
@@ -110,25 +114,31 @@
         };
 
         i2c@F0000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0xF0000 0x1000>;
                 interrupts = <0 5 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         i2c@100000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0x100000 0x1000>;
                 interrupts = <0 6 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x110000 0x1000>;
                 interrupts = <0 1 0>;
+                clocks = <&clock 21>;
+                clock-names = "watchdog";
         };
 
         amba {
@@ -142,6 +152,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x120000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -151,6 +163,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -161,5 +175,7 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x130000 0x1000>;
                 interrupts = <0 17 0>, <0 16 0>;
+                clocks = <&clock 21>;
+                clock-names = "rtc";
         };
 };
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index faca4326b46a..ef3b69a6277c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select S5P_DEV_MFC
@@ -405,6 +406,7 @@ config MACH_EXYNOS4_DT
         select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
         select PINCTRL
         select PINCTRL_EXYNOS
+        select S5P_DEV_MFC
         select USE_OF
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index daf289b21486..d2f6b362b6dd 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,10 +13,6 @@ obj-				:=
 # Core
 
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
-obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
-obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
-obj-$(CONFIG_SOC_EXYNOS5250)    += clock-exynos5.o
 
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
deleted file mode 100644
index 8a8468d83c8c..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ /dev/null
@@ -1,1601 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
-        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
-        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
-        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
-};
-#endif
-
-static struct clk exynos4_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos4_clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
-}
-
-int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
-}
-
-int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos4_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos4_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk exynos4_clk_mout_mpll = {
-        .clk    = {
-                .name           = "mout_mpll",
-        },
-        .sources = &clk_src_mpll,
-
-        /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *exynos4_clkset_moutcore_list[] = {
-        [0] = &exynos4_clk_mout_apll.clk,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_moutcore = {
-        .sources        = exynos4_clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
-};
-
-static struct clksrc_clk exynos4_clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources = &exynos4_clkset_moutcore,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &exynos4_clk_moutcore.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-static struct clk *exynos4_clkset_corebus_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_corebus = {
-        .sources        = exynos4_clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources = &exynos4_clkset_mout_corebus,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &exynos4_clk_sclk_dmc.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &exynos4_clk_aclk_cored.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos4_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *exynos4_clkset_aclk_top_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_aclk = {
-        .sources        = exynos4_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos4_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk exynos4_clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *exynos4_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos4_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos4_clkset_vpllsrc = {
-        .sources        = exynos4_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos4_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_vpll_list[] = {
-        [0] = &exynos4_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_vpll = {
-        .sources        = exynos4_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos4_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk exynos4_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "jpeg",
-                .id             = 0,
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "tsi",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "biu",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "onenand",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "tmu_apbif",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "slimbus",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }
-};
-
-static struct clk exynos4_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos4_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk exynos4_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos4_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos4_clk_ip_image_ctrl,
-        .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
-};
-
-static struct clk exynos4_clk_fimd0 = {
-        .name           = "fimd",
-        .devname        = "exynos4-fb.0",
-        .enable         = exynos4_clk_ip_lcd0_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-struct clk *exynos4_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &exynos4_clk_sclk_hdmi27m,
-        [3] = &exynos4_clk_sclk_usbphy0,
-        [4] = &exynos4_clk_sclk_usbphy1,
-        [5] = &exynos4_clk_sclk_hdmiphy,
-        [6] = &exynos4_clk_mout_mpll.clk,
-        [7] = &exynos4_clk_mout_epll.clk,
-        [8] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_group = {
-        .sources        = exynos4_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d0 = {
-        .sources        = exynos4_clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d1 = {
-        .sources        = exynos4_clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
-};
-
-static struct clk *exynos4_clkset_mout_mfc0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
-        .sources        = exynos4_clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources = &exynos4_clkset_mout_mfc0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
-        .sources        = exynos4_clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources = &exynos4_clkset_mout_mfc1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc_list[] = {
-        [0] = &exynos4_clk_mout_mfc0.clk,
-        [1] = &exynos4_clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc = {
-        .sources        = exynos4_clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
-};
-
-static struct clk *exynos4_clkset_sclk_dac_list[] = {
-        [0] = &exynos4_clk_sclk_vpll.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_dac = {
-        .sources        = exynos4_clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_sclk_dac,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos4_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos4_clk_sclk_pixel.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
-        .sources        = exynos4_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_mixer_list[] = {
-        [0] = &exynos4_clk_sclk_dac.clk,
-        [1] = &exynos4_clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_mixer = {
-        .sources        = exynos4_clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mixer = {
-        .clk    = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_sclk_mixer,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *exynos4_sclk_tv[] = {
-        &exynos4_clk_sclk_dac,
-        &exynos4_clk_sclk_pixel,
-        &exynos4_clk_sclk_hdmi,
-        &exynos4_clk_sclk_mixer,
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc0 = {
-        .clk    = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc1 = {
-        .clk    = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc2 = {
-        .clk    = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc3 = {
-        .clk    = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &exynos4_clkset_mout_mfc,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "ciu",
-                        .parent         = &exynos4_clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos4_clk_mdout_spi0.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos4_clk_mdout_spi1.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos4_clk_mdout_spi2.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos4_sysclks[] = {
-        &exynos4_clk_mout_apll,
-        &exynos4_clk_sclk_apll,
-        &exynos4_clk_mout_epll,
-        &exynos4_clk_mout_mpll,
-        &exynos4_clk_moutcore,
-        &exynos4_clk_coreclk,
-        &exynos4_clk_armclk,
-        &exynos4_clk_aclk_corem0,
-        &exynos4_clk_aclk_cores,
-        &exynos4_clk_aclk_corem1,
-        &exynos4_clk_periphclk,
-        &exynos4_clk_mout_corebus,
-        &exynos4_clk_sclk_dmc,
-        &exynos4_clk_aclk_cored,
-        &exynos4_clk_aclk_corep,
-        &exynos4_clk_aclk_acp,
-        &exynos4_clk_pclk_acp,
-        &exynos4_clk_vpllsrc,
-        &exynos4_clk_sclk_vpll,
-        &exynos4_clk_aclk_200,
-        &exynos4_clk_aclk_100,
-        &exynos4_clk_aclk_160,
-        &exynos4_clk_aclk_133,
-        &exynos4_clk_dout_mmc0,
-        &exynos4_clk_dout_mmc1,
-        &exynos4_clk_dout_mmc2,
-        &exynos4_clk_dout_mmc3,
-        &exynos4_clk_dout_mmc4,
-        &exynos4_clk_mout_mfc0,
-        &exynos4_clk_mout_mfc1,
-};
-
-static struct clk *exynos4_clk_cdev[] = {
-        &exynos4_clk_pdma0,
-        &exynos4_clk_pdma1,
-        &exynos4_clk_mdma1,
-        &exynos4_clk_fimd0,
-};
-
-static struct clksrc_clk *exynos4_clksrc_cdev[] = {
-        &exynos4_clk_sclk_uart0,
-        &exynos4_clk_sclk_uart1,
-        &exynos4_clk_sclk_uart2,
-        &exynos4_clk_sclk_uart3,
-        &exynos4_clk_sclk_mmc0,
-        &exynos4_clk_sclk_mmc1,
-        &exynos4_clk_sclk_mmc2,
-        &exynos4_clk_sclk_mmc3,
-        &exynos4_clk_sclk_spi0,
-        &exynos4_clk_sclk_spi1,
-        &exynos4_clk_sclk_spi2,
-        &exynos4_clk_mdout_spi0,
-        &exynos4_clk_mdout_spi1,
-        &exynos4_clk_mdout_spi2,
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
-        else
-                return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 exynos4_vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
-                if (exynos4_vpll_div[i][0] == rate) {
-                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
-        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1));
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
-
-        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
-
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
-}
-
-static struct clk *exynos4_clks[] __initdata = {
-        &exynos4_clk_sclk_hdmi27m,
-        &exynos4_clk_sclk_hdmiphy,
-        &exynos4_clk_sclk_usbphy0,
-        &exynos4_clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
-                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
-        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
deleted file mode 100644
index bd12d5f8b63d..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clksrc_clk exynos4_clk_aclk_133;
-extern struct clksrc_clk exynos4_clk_mout_mpll;
-
-extern struct clksrc_sources exynos4_clkset_mout_corebus;
-extern struct clksrc_sources exynos4_clkset_group;
-
-extern struct clk *exynos4_clkset_aclk_top_list[];
-extern struct clk *exynos4_clkset_group_list[];
-
-extern struct clksrc_sources exynos4_clkset_mout_g2d0;
-extern struct clksrc_sources exynos4_clkset_mout_g2d1;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
deleted file mode 100644
index 19af9f783c56..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4210 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
-};
-#endif
-
-static struct clksrc_clk *sysclks[] = {
-        /* nothing here yet */
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4210_clkset_mout_g2d_list[] = {
-        [0] = &exynos4210_clk_mout_g2d0.clk,
-        [1] = &exynos4210_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4210_clkset_mout_g2d = {
-        .sources        = exynos4210_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
-};
-
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .id             = -1,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_mout_corebus,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4210_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sataphy",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sata",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4210_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-
-        return 0;
-}
-
-static void exynos4210_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-}
-
-#else
-#define exynos4210_clock_suspend NULL
-#define exynos4210_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4210_clock_syscore_ops = {
-        .suspend        = exynos4210_clock_suspend,
-        .resume         = exynos4210_clock_resume,
-};
-
-void __init exynos4210_register_clocks(void)
-{
-        int ptr;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
-        exynos4_clk_mout_mpll.reg_src.shift = 8;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4210_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
deleted file mode 100644
index 529476f8ec71..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4212 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
-};
-#endif
-
-static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static struct clk *clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_mpll_user = {
-        .sources        = clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk clk_mout_mpll_user = {
-        .clk = {
-                .name           = "mout_mpll_user",
-        },
-        .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
-        [0] = &exynos4x12_clk_mout_g2d0.clk,
-        [1] = &exynos4x12_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
-        .sources        = exynos4x12_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
-};
-
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_mpll_user,
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4x12_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (7 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = exynos4212_clk_ip_isp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.15",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.0",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.1",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 23),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4212_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-
-        return 0;
-}
-
-static void exynos4212_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-}
-
-#else
-#define exynos4212_clock_suspend NULL
-#define exynos4212_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4212_clock_syscore_ops = {
-        .suspend        = exynos4212_clock_suspend,
-        .resume         = exynos4212_clock_resume,
-};
-
-void __init exynos4212_register_clocks(void)
-{
-        int ptr;
-
-        /* usbphy1 is removed */
-        exynos4_clkset_group_list[4] = NULL;
-
-        /* mout_mpll_user is used */
-        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
-        exynos4_clk_mout_mpll.reg_src.shift = 12;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4212_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Clock support for EXYNOS5 SoCs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos5_clock_save[] = {
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
-        SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
-        SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
-        SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
-        SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
-        SAVE_ITEM(EXYNOS5_EPLL_CON0),
-        SAVE_ITEM(EXYNOS5_EPLL_CON1),
-        SAVE_ITEM(EXYNOS5_EPLL_CON2),
-        SAVE_ITEM(EXYNOS5_VPLL_CON0),
-        SAVE_ITEM(EXYNOS5_VPLL_CON1),
-        SAVE_ITEM(EXYNOS5_VPLL_CON2),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL1),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL2),
-};
-#endif
-
-static struct clk exynos5_clk_sclk_dptxphy = {
-        .name           = "sclk_dptx",
-};
-
-static struct clk exynos5_clk_sclk_hdmi24m = {
-        .name           = "sclk_hdmi24m",
-        .rate           = 24000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos5_clk_sclk_usbphy = {
-        .name           = "sclk_usbphy",
-        .rate           = 48000000,
-};
-
-static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
-}
-
-static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
-}
-
-static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
-}
-
-static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
-}
-
-static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
-}
-
-static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
-}
-
-static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
-}
-
-static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
-}
-
-static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
-}
-
-static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos5_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos5_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
-        .clk    = {
-                .name           = "mout_bpll_fout",
-        },
-        .sources = &clk_src_bpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_list[] = {
-        [0] = &clk_fin_bpll,
-        [1] = &exynos5_clk_mout_bpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll = {
-        .sources        = exynos5_clk_src_bpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll = {
-        .clk    = {
-                .name           = "mout_bpll",
-        },
-        .sources = &exynos5_clk_src_bpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll_user = {
-        .sources        = exynos5_clk_src_bpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_user = {
-        .clk    = {
-                .name           = "mout_bpll_user",
-        },
-        .sources = &exynos5_clk_src_bpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpll = {
-        .clk    = {
-                .name           = "mout_cpll",
-        },
-        .sources = &clk_src_cpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
-        .clk    = {
-                .name           = "mout_mpll_fout",
-        },
-        .sources = &clk_src_mpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll = {
-        .sources        = exynos5_clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources = &exynos5_clk_src_mpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
-};
-
-static struct clk *exynos_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos5_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos5_clkset_vpllsrc = {
-        .sources        = exynos_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos5_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos5_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_sclk_vpll_list[] = {
-        [0] = &exynos5_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_vpll = {
-        .sources        = exynos5_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos5_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_pixel = {
-        .clk    = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos5_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
-};
-
-static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos5_clk_sclk_pixel.clk,
-        [1] = &exynos5_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
-        .sources        = exynos5_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_hdmi = {
-        .clk    = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .sources = &exynos5_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk *exynos5_sclk_tv[] = {
-        &exynos5_clk_sclk_pixel,
-        &exynos5_clk_sclk_hdmi,
-};
-
-static struct clk *exynos5_clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll_user = {
-        .sources        = exynos5_clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_user = {
-        .clk    = {
-                .name           = "mout_mpll_user",
-        },
-        .sources = &exynos5_clk_src_mpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_mout_cpu_list[] = {
-        [0] = &exynos5_clk_mout_apll.clk,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_mout_cpu = {
-        .sources        = exynos5_clkset_mout_cpu_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpu = {
-        .clk    = {
-                .name           = "mout_cpu",
-        },
-        .sources = &exynos5_clkset_mout_cpu,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_armclk = {
-        .clk    = {
-                .name           = "dout_armclk",
-                .parent         = &exynos5_clk_mout_cpu.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_arm2clk = {
-        .clk    = {
-                .name           = "dout_arm2clk",
-                .parent         = &exynos5_clk_dout_armclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
-};
-
-static struct clk exynos5_clk_armclk = {
-        .name           = "armclk",
-        .parent         = &exynos5_clk_dout_arm2clk.clk,
-};
-
-/* Core list of CMU_CDREX side */
-
-static struct clk *exynos5_clkset_cdrex_list[] = {
-        [0] = &exynos5_clk_mout_mpll.clk,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_cdrex = {
-        .sources        = exynos5_clkset_cdrex_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
-};
-
-static struct clksrc_clk exynos5_clk_cdrex = {
-        .clk    = {
-                .name           = "clk_cdrex",
-        },
-        .sources = &exynos5_clkset_cdrex,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos5_clk_mout_mpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos5_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-static struct clk *exynos5_clkset_aclk_top_list[] = {
-        [0] = &exynos5_clk_mout_mpll_user.clk,
-        [1] = &exynos5_clk_mout_bpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk = {
-        .sources        = exynos5_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_400 = {
-        .clk    = {
-                .name           = "aclk_400",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-};
-
-static struct clk *exynos5_clkset_aclk_333_166_list[] = {
-        [0] = &exynos5_clk_mout_cpll.clk,
-        [1] = &exynos5_clk_mout_mpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
-        .sources        = exynos5_clkset_aclk_333_166_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_333 = {
-        .clk    = {
-                .name           = "aclk_333",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_166 = {
-        .clk    = {
-                .name           = "aclk_166",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_266 = {
-        .clk    = {
-                .name           = "aclk_266",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66_pre = {
-        .clk    = {
-                .name           = "aclk_66_pre",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66 = {
-        .clk    = {
-                .name           = "aclk_66",
-                .parent         = &exynos5_clk_aclk_66_pre.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
-        [0] = &exynos5_clk_sclk_vpll.clk,
-        [1] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
-        .sources        = exynos5_clkset_aclk_300_mid1_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid1",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl_mid1,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
-        [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
-        [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
-        .sources        = exynos5_clkset_aclk_300_gscl_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_gscl_300_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_gscl_300 = {
-        .sources        = exynos5_clk_src_gscl_300_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
-        .clk    = {
-                .name           = "aclk_300_gscl",
-        },
-        .sources = &exynos5_clk_src_gscl_300,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
-};
-
-static struct clk exynos5_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "tmu_apbif",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "rtc",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "biu",        /* bus interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "sata",
-                .devname        = "exynos5-sata",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "sata-phy",
-                .devname        = "exynos5-sata-phy",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "i2c",
-                .devname        = "exynos5-sata-phy-i2c",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc-v6",
-                .enable         = exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mixer",
-                .devname        = "exynos5-mixer",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "dp",
-                .devname        = "exynos-dp",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "jpeg",
-                .enable         = exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "dsim0",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos5_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "usbotg",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
-        }, {
-                .name           = "core_iop",
-                .enable         = exynos5_clk_ip_core_ctrl,
-                .ctrlbit        = ((1 << 21) | (1 << 3)),
-        }, {
-                .name           = "mcu_iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.0",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.1",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.2",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.3",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 9)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 6)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = &exynos5_clk_ip_isp0_ctrl,
-                .ctrlbit        = (0x3F << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = &exynos5_clk_ip_isp1_ctrl,
-                .ctrlbit        = (0xF << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 8)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = &exynos5_clk_ip_acp_ctrl,
-                .ctrlbit        = (1 << 7)
-        }
-};
-
-static struct clk exynos5_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos5_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 2),
-};
-
-static struct clk exynos5_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos5_clk_ip_gen_ctrl,
-        .ctrlbit        = (1 << 4),
-};
-
-static struct clk exynos5_clk_fimd1 = {
-        .name           = "fimd",
-        .devname        = "exynos5-fb.1",
-        .enable         = exynos5_clk_ip_disp1_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk *exynos5_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = NULL,
-        [2] = &exynos5_clk_sclk_hdmi24m,
-        [3] = &exynos5_clk_sclk_dptxphy,
-        [4] = &exynos5_clk_sclk_usbphy,
-        [5] = &exynos5_clk_sclk_hdmiphy,
-        [6] = &exynos5_clk_mout_mpll_user.clk,
-        [7] = &exynos5_clk_mout_epll.clk,
-        [8] = &exynos5_clk_sclk_vpll.clk,
-        [9] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_group = {
-        .sources        = exynos5_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
-};
-
-/* Possible clock sources for aclk_266_gscl_sub Mux */
-static struct clk *clk_src_gscl_266_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_aclk_266.clk,
-};
-
-static struct clksrc_sources clk_src_gscl_266 = {
-        .sources        = clk_src_gscl_266_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "ciu",        /* card interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_dout_mmc0.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_dout_mmc1.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_dout_mmc2.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_dout_mmc3.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_mdout_spi0.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_mdout_spi1.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_mdout_spi2.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
-        .clk    = {
-                .name           = "sclk_fimd",
-                .devname        = "exynos5-fb.1",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "aclk_266_gscl",
-                },
-                .sources = &clk_src_gscl_266,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_g3d",
-                        .devname        = "mali-t604.0",
-                        .enable         = exynos5_clk_block_ctrl,
-                        .ctrlbit        = (1 << 1),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_sata",
-                        .devname        = "exynos5-sata",
-                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_jpeg",
-                        .parent         = &exynos5_clk_mout_cpll.clk,
-                },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
-        },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos5_sysclks[] = {
-        &exynos5_clk_mout_apll,
-        &exynos5_clk_sclk_apll,
-        &exynos5_clk_mout_bpll,
-        &exynos5_clk_mout_bpll_fout,
-        &exynos5_clk_mout_bpll_user,
-        &exynos5_clk_mout_cpll,
-        &exynos5_clk_mout_epll,
-        &exynos5_clk_mout_mpll,
-        &exynos5_clk_mout_mpll_fout,
-        &exynos5_clk_mout_mpll_user,
-        &exynos5_clk_vpllsrc,
-        &exynos5_clk_sclk_vpll,
-        &exynos5_clk_mout_cpu,
-        &exynos5_clk_dout_armclk,
-        &exynos5_clk_dout_arm2clk,
-        &exynos5_clk_cdrex,
-        &exynos5_clk_aclk_400,
-        &exynos5_clk_aclk_333,
-        &exynos5_clk_aclk_266,
-        &exynos5_clk_aclk_200,
-        &exynos5_clk_aclk_166,
-        &exynos5_clk_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl_mid,
-        &exynos5_clk_mout_aclk_300_gscl_mid1,
-        &exynos5_clk_aclk_66_pre,
-        &exynos5_clk_aclk_66,
-        &exynos5_clk_dout_mmc0,
-        &exynos5_clk_dout_mmc1,
-        &exynos5_clk_dout_mmc2,
-        &exynos5_clk_dout_mmc3,
-        &exynos5_clk_dout_mmc4,
-        &exynos5_clk_aclk_acp,
-        &exynos5_clk_pclk_acp,
-        &exynos5_clk_sclk_spi0,
-        &exynos5_clk_sclk_spi1,
-        &exynos5_clk_sclk_spi2,
-        &exynos5_clk_mdout_spi0,
-        &exynos5_clk_mdout_spi1,
-        &exynos5_clk_mdout_spi2,
-        &exynos5_clk_sclk_fimd1,
-};
-
-static struct clk *exynos5_clk_cdev[] = {
-        &exynos5_clk_pdma0,
-        &exynos5_clk_pdma1,
-        &exynos5_clk_mdma1,
-        &exynos5_clk_fimd1,
-};
-
-static struct clksrc_clk *exynos5_clksrc_cdev[] = {
-        &exynos5_clk_sclk_uart0,
-        &exynos5_clk_sclk_uart1,
-        &exynos5_clk_sclk_uart2,
-        &exynos5_clk_sclk_uart3,
-        &exynos5_clk_sclk_mmc0,
-        &exynos5_clk_sclk_mmc1,
-        &exynos5_clk_sclk_mmc2,
-        &exynos5_clk_sclk_mmc3,
-};
-
-static struct clk_lookup exynos5_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
-        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
-};
-
-static unsigned long exynos5_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static struct clk *exynos5_clks[] __initdata = {
-        &exynos5_clk_sclk_hdmi27m,
-        &exynos5_clk_sclk_hdmiphy,
-        &clk_fout_bpll,
-        &clk_fout_bpll_div2,
-        &clk_fout_cpll,
-        &clk_fout_mpll_div2,
-        &exynos5_clk_armclk,
-};
-
-static u32 epll_div[][6] = {
-        { 192000000, 0, 48, 3, 1, 0 },
-        { 180000000, 0, 45, 3, 1, 0 },
-        {  73728000, 1, 73, 3, 3, 47710 },
-        {  67737600, 1, 90, 4, 3, 20762 },
-        {  49152000, 0, 49, 3, 3, 9961 },
-        {  45158400, 0, 45, 3, 3, 10381 },
-        { 180633600, 0, 45, 3, 1, 10381 },
-};
-
-static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-        unsigned int tmp;
-        unsigned int epll_rate;
-        unsigned int locktime;
-        unsigned int lockcnt;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        if (clk->parent)
-                epll_rate = clk_get_rate(clk->parent);
-        else
-                epll_rate = clk_ext_xtal_mux.rate;
-
-        if (epll_rate != 24000000) {
-                pr_err("Invalid Clock : recommended clock is 24MHz.\n");
-                return -EINVAL;
-        }
-
-        epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
-        epll_con &= ~(0x1 << 27 | \
-                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
-                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
-                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                if (epll_div[i][0] == rate) {
-                        epll_con_k = epll_div[i][5] << 0;
-                        epll_con |= epll_div[i][1] << 27;
-                        epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
-                        epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        epll_rate /= 1000000;
-
-        /* 3000 max_cycls : specification data */
-        locktime = 3000 / epll_rate * epll_div[i][3];
-        lockcnt = locktime * 10000 / (10000 / epll_rate);
-
-        __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
-
-        __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
-        __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
-
-        do {
-                tmp = __raw_readl(EXYNOS5_EPLL_CON0);
-        } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops exynos5_epll_ops = {
-        .get_rate = exynos5_epll_get_rate,
-        .set_rate = exynos5_epll_set_rate,
-};
-
-static int xtal_rate;
-
-static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
-{
-        return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
-}
-
-static struct clk_ops exynos5_fout_apll_ops = {
-        .get_rate = exynos5_fout_apll_get_rate,
-};
-
-#ifdef CONFIG_PM
-static int exynos5_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-
-        return 0;
-}
-
-static void exynos5_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-}
-#else
-#define exynos5_clock_suspend NULL
-#define exynos5_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos5_clock_syscore_ops = {
-        .suspend        = exynos5_clock_suspend,
-        .resume         = exynos5_clock_resume,
-};
-
-void __init_or_cpufreq exynos5_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll;
-        unsigned long bpll;
-        unsigned long cpll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long mout_cdrex;
-        unsigned long aclk_400;
-        unsigned long aclk_333;
-        unsigned long aclk_266;
-        unsigned long aclk_200;
-        unsigned long aclk_166;
-        unsigned long aclk_66;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
-        bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
-        cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
-        mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
-        epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
-                        __raw_readl(EXYNOS5_EPLL_CON1));
-
-        vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
-        vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
-                        __raw_readl(EXYNOS5_VPLL_CON1));
-
-        clk_fout_apll.ops = &exynos5_fout_apll_ops;
-        clk_fout_bpll.rate = bpll;
-        clk_fout_bpll_div2.rate = bpll >> 1;
-        clk_fout_cpll.rate = cpll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_mpll_div2.rate = mpll >> 1;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
-                        "M=%ld, E=%ld V=%ld",
-                        apll, bpll, cpll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos5_clk_armclk);
-        mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
-
-        aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
-        aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
-        aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
-        aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
-        aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
-        aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
-
-        printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
-                        "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
-                        "ACLK166=%ld, ACLK66=%ld\n",
-                        armclk, mout_cdrex, aclk_400,
-                        aclk_333, aclk_266, aclk_200,
-                        aclk_166, aclk_66);
-
-
-        clk_fout_epll.ops = &exynos5_epll_ops;
-
-        if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
-                printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
-                                clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
-
-        clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
-        clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
-
-        clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
-        clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
-}
-
-void __init exynos5_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
-                s3c_register_clksrc(exynos5_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
-        s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
-
-        register_syscore_ops(&exynos5_clock_syscore_ops);
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index db7dbd0eb6b4..d3efd6768ff8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -25,6 +25,8 @@
 #include <linux/irqdomain.h>
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
 #include <linux/irqchip/arm-gic.h>
 
 #include <asm/proc-fns.h>
@@ -39,7 +41,6 @@
 #include <mach/regs-gpio.h>
 
 #include <plat/cpu.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/sdhci.h>
@@ -65,17 +66,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
-static void exynos4_init_clocks(int xtal);
-static void exynos5_init_clocks(int xtal);
 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = EXYNOS4210_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
@@ -83,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4212_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4412_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
@@ -99,7 +97,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS5250_SOC_ID,
                 .idmask         = EXYNOS5_SOC_MASK,
                 .map_io         = exynos5_map_io,
-                .init_clocks    = exynos5_init_clocks,
                 .init           = exynos_init,
                 .name           = name_exynos5250,
         }, {
@@ -397,43 +394,26 @@ static void __init exynos5_map_io(void)
         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 }
 
-static void __init exynos4_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        if (soc_is_exynos4210())
-                exynos4210_register_clocks();
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                exynos4212_register_clocks();
-
-        exynos4_register_clocks();
-        exynos4_setup_clocks();
-}
-
 static void __init exynos5440_map_io(void)
 {
         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 }
 
-static void __init exynos5_init_clocks(int xtal)
+void __init exynos_init_time(void)
 {
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        /* EXYNOS5440 can support only common clock framework */
-
-        if (soc_is_exynos5440())
-                return;
-
-#ifdef CONFIG_SOC_EXYNOS5250
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        exynos5_register_clocks();
-        exynos5_setup_clocks();
+        if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
+                of_clk_init(NULL);
+                clocksource_of_init();
+#endif
+        } else {
+                /* todo: remove after migrating legacy E4 platforms to dt */
+#ifdef CONFIG_ARCH_EXYNOS4
+                exynos4_clk_init(NULL);
+                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 #endif
+                mct_init();
+        }
 }
 
 void __init exynos4_init_irq(void)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 3b186eaaaa7b..cb89ab886950 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,11 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+#include <linux/of.h>
+
 extern void mct_init(void);
+void exynos_init_time(void);
+extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
+/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
+void exynos4_clk_init(struct device_node *np);
+void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index d36ad76ad6a4..20fbbdddd105 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -256,113 +256,6 @@
 #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT          (0)
 #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK           (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
 
-/* For EXYNOS5250 */
-
-#define EXYNOS5_APLL_LOCK                       EXYNOS_CLKREG(0x00000)
-#define EXYNOS5_APLL_CON0                       EXYNOS_CLKREG(0x00100)
-#define EXYNOS5_CLKSRC_CPU                      EXYNOS_CLKREG(0x00200)
-#define EXYNOS5_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x00400)
-#define EXYNOS5_CLKDIV_CPU0                     EXYNOS_CLKREG(0x00500)
-#define EXYNOS5_CLKDIV_CPU1                     EXYNOS_CLKREG(0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0                 EXYNOS_CLKREG(0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x00604)
-
-#define EXYNOS5_PWR_CTRL1                       EXYNOS_CLKREG(0x01020)
-#define EXYNOS5_PWR_CTRL2                       EXYNOS_CLKREG(0x01024)
-
-#define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
-#define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
-
-#define EXYNOS5_CLKGATE_IP_CORE                 EXYNOS_CLKREG(0x04900)
-
-#define EXYNOS5_CLKDIV_ACP                      EXYNOS_CLKREG(0x08500)
-
-#define EXYNOS5_EPLL_CON0                       EXYNOS_CLKREG(0x10130)
-#define EXYNOS5_EPLL_CON1                       EXYNOS_CLKREG(0x10134)
-#define EXYNOS5_EPLL_CON2                       EXYNOS_CLKREG(0x10138)
-#define EXYNOS5_VPLL_CON0                       EXYNOS_CLKREG(0x10140)
-#define EXYNOS5_VPLL_CON1                       EXYNOS_CLKREG(0x10144)
-#define EXYNOS5_VPLL_CON2                       EXYNOS_CLKREG(0x10148)
-#define EXYNOS5_CPLL_CON0                       EXYNOS_CLKREG(0x10120)
-
-#define EXYNOS5_CLKSRC_TOP0                     EXYNOS_CLKREG(0x10210)
-#define EXYNOS5_CLKSRC_TOP1                     EXYNOS_CLKREG(0x10214)
-#define EXYNOS5_CLKSRC_TOP2                     EXYNOS_CLKREG(0x10218)
-#define EXYNOS5_CLKSRC_TOP3                     EXYNOS_CLKREG(0x1021C)
-#define EXYNOS5_CLKSRC_GSCL                     EXYNOS_CLKREG(0x10220)
-#define EXYNOS5_CLKSRC_DISP1_0                  EXYNOS_CLKREG(0x1022C)
-#define EXYNOS5_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x10240)
-#define EXYNOS5_CLKSRC_FSYS                     EXYNOS_CLKREG(0x10244)
-#define EXYNOS5_CLKSRC_PERIC0                   EXYNOS_CLKREG(0x10250)
-#define EXYNOS5_CLKSRC_PERIC1                   EXYNOS_CLKREG(0x10254)
-#define EXYNOS5_SCLK_SRC_ISP                    EXYNOS_CLKREG(0x10270)
-
-#define EXYNOS5_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x10310)
-#define EXYNOS5_CLKSRC_MASK_GSCL                EXYNOS_CLKREG(0x10320)
-#define EXYNOS5_CLKSRC_MASK_DISP1_0             EXYNOS_CLKREG(0x1032C)
-#define EXYNOS5_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x10334)
-#define EXYNOS5_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x10340)
-#define EXYNOS5_CLKSRC_MASK_PERIC0              EXYNOS_CLKREG(0x10350)
-#define EXYNOS5_CLKSRC_MASK_PERIC1              EXYNOS_CLKREG(0x10354)
-
-#define EXYNOS5_CLKDIV_TOP0                     EXYNOS_CLKREG(0x10510)
-#define EXYNOS5_CLKDIV_TOP1                     EXYNOS_CLKREG(0x10514)
-#define EXYNOS5_CLKDIV_GSCL                     EXYNOS_CLKREG(0x10520)
-#define EXYNOS5_CLKDIV_DISP1_0                  EXYNOS_CLKREG(0x1052C)
-#define EXYNOS5_CLKDIV_GEN                      EXYNOS_CLKREG(0x1053C)
-#define EXYNOS5_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x10544)
-#define EXYNOS5_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x10548)
-#define EXYNOS5_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x1054C)
-#define EXYNOS5_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x10550)
-#define EXYNOS5_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x10554)
-#define EXYNOS5_CLKDIV_PERIC0                   EXYNOS_CLKREG(0x10558)
-#define EXYNOS5_CLKDIV_PERIC1                   EXYNOS_CLKREG(0x1055C)
-#define EXYNOS5_CLKDIV_PERIC2                   EXYNOS_CLKREG(0x10560)
-#define EXYNOS5_CLKDIV_PERIC3                   EXYNOS_CLKREG(0x10564)
-#define EXYNOS5_CLKDIV_PERIC4                   EXYNOS_CLKREG(0x10568)
-#define EXYNOS5_CLKDIV_PERIC5                   EXYNOS_CLKREG(0x1056C)
-#define EXYNOS5_SCLK_DIV_ISP                    EXYNOS_CLKREG(0x10580)
-
-#define EXYNOS5_CLKGATE_IP_ACP                  EXYNOS_CLKREG(0x08800)
-#define EXYNOS5_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x0C800)
-#define EXYNOS5_CLKGATE_IP_ISP1                 EXYNOS_CLKREG(0x0C804)
-#define EXYNOS5_CLKGATE_IP_GSCL                 EXYNOS_CLKREG(0x10920)
-#define EXYNOS5_CLKGATE_IP_DISP1                EXYNOS_CLKREG(0x10928)
-#define EXYNOS5_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x1092C)
-#define EXYNOS5_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x10930)
-#define EXYNOS5_CLKGATE_IP_GEN                  EXYNOS_CLKREG(0x10934)
-#define EXYNOS5_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x10944)
-#define EXYNOS5_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x1094C)
-#define EXYNOS5_CLKGATE_IP_PERIC                EXYNOS_CLKREG(0x10950)
-#define EXYNOS5_CLKGATE_IP_PERIS                EXYNOS_CLKREG(0x10960)
-#define EXYNOS5_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x10980)
-
-#define EXYNOS5_BPLL_CON0                       EXYNOS_CLKREG(0x20110)
-#define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
-#define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
-
-#define EXYNOS5_PLL_DIV2_SEL                    EXYNOS_CLKREG(0x20A24)
-
-#define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
-
-#define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
-
-#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
-#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
-#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
-#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
-#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
-#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
-#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
-#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
-
-#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
-#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
-#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
-#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
-#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
-#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
-
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 3b1a34742679..2c23b659ae3e 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
 static void __init armlex4210_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(armlex4210_uartcfgs,
                            ARRAY_SIZE(armlex4210_uartcfgs));
 }
@@ -202,6 +201,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = mct_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index c4ae108e192d..ac27f3cd121f 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,122 +11,26 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 #include <linux/serial_core.h>
+#include <linux/memblock.h>
 #include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-serial.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
-                                "exynos4-sdhci.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
-                                "exynos4-sdhci.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
-                                "exynos4-sdhci.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
-                                "exynos4-sdhci.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
-                        "exynos-sysmmu.0", NULL), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
-                        "exynos-sysmmu.1", NULL), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
-                        "exynos-sysmmu.3", NULL), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
-                        "exynos-sysmmu.5", NULL), /* FIMC0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
-                        "exynos-sysmmu.6", NULL), /* FIMC1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
-                        "exynos-sysmmu.7", NULL), /* FIMC2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
-                        "exynos-sysmmu.8", NULL), /* FIMC3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
-                        "exynos-sysmmu.10", NULL), /* FIMD0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
-                        "exynos-sysmmu.12", NULL), /* IS0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
-                        "exynos-sysmmu.13", NULL), /* IS1(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
-                        "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
-                        "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
-        {},
-};
-
 static void __init exynos4_dt_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos4_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos4_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos4_dt_compat[] __initdata = {
@@ -136,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
         NULL
 };
 
+static void __init exynos4_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+        struct s5p_mfc_dt_meminfo mfc_mem;
+
+        /* Reserve memory for MFC only if it's available */
+        mfc_mem.compatible = "samsung,mfc-v5";
+        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+                                mfc_mem.lsize);
+#endif
+}
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .smp            = smp_ops(exynos_smp_ops),
@@ -143,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         .map_io         = exynos4_dt_map_io,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = clocksource_of_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
+        .reserve        = exynos4_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7da4791bfb8b..753b94f3fca7 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,152 +11,21 @@
 
 #include <linux/of_platform.h>
 #include <linux/of_fdt.h>
-#include <linux/serial_core.h>
 #include <linux/memblock.h>
 #include <linux/io.h>
 #include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
 #include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the EXYNOS5 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
-                                "s3c2440-hdmiphy-i2c", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
-                                "dw_mmc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
-                                "dw_mmc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
-                                "dw_mmc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
-                                "dw_mmc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
-                                "exynos5-sata", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
-                                "exynos5-sata-phy", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
-                                "exynos5-sata-phy-i2c", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
-                                "exynos-gsc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
-                                "exynos-gsc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
-                                "exynos-gsc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
-                                "exynos-gsc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
-                                "exynos5-hdmi", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
-                                "exynos5-mixer", NULL),
-        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
-                                "samsung-i2s.0", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
-                                "samsung-i2s.1", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
-                                "samsung-i2s.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
-                        "exynos-sysmmu.0", "mfc"), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
-                        "exynos-sysmmu.1", "mfc"), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
-                        "exynos-sysmmu.3", "jpeg"), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
-                        "exynos-sysmmu.5", "gscl"), /* GSCL0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
-                        "exynos-sysmmu.6", "gscl"), /* GSCL1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
-                        "exynos-sysmmu.7", "gscl"), /* GSCL2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
-                        "exynos-sysmmu.8", "gscl"), /* GSCL3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
-                        "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
-                        "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
-                        "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
-                        "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
-                        "exynos-sysmmu.14", NULL), /* G2D */
-        {},
-};
-
-static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        {},
-};
-
 static void __init exynos5_dt_map_io(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
         exynos_init_io(NULL, 0);
-
-        if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
-                s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos5_dt_machine_init(void)
@@ -183,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
                 }
         }
 
-        if (of_machine_is_compatible("samsung,exynos5250"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5250_auxdata_lookup, NULL);
-        else if (of_machine_is_compatible("samsung,exynos5440"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5440_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos5_dt_compat[] __initdata = {
@@ -217,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         .map_io         = exynos5_dt_map_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = clocksource_of_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
         .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index da3605d15110..0c10852423c3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1330,8 +1330,9 @@ static struct platform_device *nuri_devices[] __initdata = {
 static void __init nuri_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init nuri_reserve(void)
@@ -1380,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = mct_init,
+        .init_time      = exynos_init_time,
         .reserve        = &nuri_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 1772cd284f4c..a9aa5c034b23 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -754,8 +754,9 @@ static void s5p_tv_setup(void)
 static void __init origen_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init origen_power_init(void)
@@ -815,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
         .map_io         = origen_map_io,
         .init_machine   = origen_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = mct_init,
+        .init_time      = exynos_init_time,
         .reserve        = &origen_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 34a6356364eb..184faa3bd93a 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
 static void __init smdk4x12_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
 }
 
@@ -376,7 +375,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
-        .init_time      = mct_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -390,7 +389,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = mct_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 893b14e8c62a..75eca7d4e128 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -371,8 +371,9 @@ static void s5p_tv_setup(void)
 static void __init smdkv310_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+        xxti_f = 12000000;
+        xusbxti_f = 24000000;
 }
 
 static void __init smdkv310_reserve(void)
@@ -423,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .init_time      = mct_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
@@ -436,7 +437,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = mct_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index c870b0aaa5e0..72f08fd7cfa9 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1092,9 +1092,10 @@ static struct platform_device *universal_devices[] __initdata = {
 static void __init universal_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void s5p_tv_setup(void)
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b708b3e56d27..6cb19c6aa9d6 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,7 @@ config PLAT_S5P
         select PLAT_SAMSUNG
         select S3C_GPIO_TRACK
         select S5P_GPIO_DRVSTR
-        select SAMSUNG_CLKSRC
+        select SAMSUNG_CLKSRC if !COMMON_CLK
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_IRQ_VIC_TIMER
         help
@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
           used by newer systems such as the S3C64XX.
 
 config S5P_CLOCK
-        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         help
           Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs