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authorOlof Johansson <olof@lixom.net>2014-09-24 14:27:17 -0400
committerOlof Johansson <olof@lixom.net>2014-09-24 14:27:35 -0400
commit14bbd322f4264afc26c93907add4870f686d28b9 (patch)
tree788ba91a5febe3b9c54d716df862db8fe3b93655 /arch
parent739d8d8bc33488ef11b34875e84860db7e09c8b4 (diff)
parent64546e9fe3a5b8cf62c946521c71d0532d399850 (diff)
Merge tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: SoC updates for 3.18" from Shawn Guo: The i.MX SoC updates for 3.18: - Add initial devicetree support for i.MX1 - Support GPT per clock source from OSC for i.MX6 - A couple of parent selection corrections for i.MX6SL clock driver - Support more chip revision for i.MX6 - Convert pr_warning to pr_warn - Add exclusive gate clock support - Add BYPASS support for i.MX6 PLL clocks - Update i.MX6 clock tree for audio use case - A couple of VF610 clock driver updates * tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (30 commits) ARM: imx_v6_v7_defconfig updates ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM arm: mach-imx: Convert pr_warning to pr_warn ARM: imx: source gpt per clk from OSC for system timer ARM: imx: add gpt_3m clk for i.mx6qdl ARM: imx: fix register offset of pll7_usb_host gate clock ARM: clk-imx6sl: refine clock tree for SSI ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver ARM: imx6sx: add BYPASS support for PLL clocks ARM: imx6sl: add BYPASS support for PLL clocks ARM: imx6q: add BYPASS support for PLL clocks ARM: imx: add an exclusive gate clock type ARM: clk-imx6q: refine clock tree for SSI ARM: clk-imx6q: refine clock tree for ASRC ARM: clk-imx6sl: correct the pxp and epdc axi clock selections ARM: clk-imx6q: refine clock tree for ESAI ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks ARM: clk-imx6sl: Remove csi_lcdif_sels[] ARM: imx: clk-vf610: Add USBPHY clocks ARM: imx: add cpufreq support for i.mx6sx ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts1
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig16
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig10
-rw-r--r--arch/arm/mach-imx/Kconfig111
-rw-r--r--arch/arm/mach-imx/Makefile10
-rw-r--r--arch/arm/mach-imx/anatop.c13
-rw-r--r--arch/arm/mach-imx/board-pcm038.h36
-rw-r--r--arch/arm/mach-imx/clk-gate-exclusive.c94
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c99
-rw-r--r--arch/arm/mach-imx/clk-imx6sl.c103
-rw-r--r--arch/arm/mach-imx/clk-imx6sx.c63
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c37
-rw-r--r--arch/arm/mach-imx/clk-vf610.c21
-rw-r--r--arch/arm/mach-imx/clk.h3
-rw-r--r--arch/arm/mach-imx/common.h2
-rw-r--r--arch/arm/mach-imx/cpuidle-imx6q.c4
-rw-r--r--arch/arm/mach-imx/eukrea-baseboards.h10
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c351
-rw-r--r--arch/arm/mach-imx/imx1-dt.c26
-rw-r--r--arch/arm/mach-imx/iomux-imx31.c7
-rw-r--r--arch/arm/mach-imx/iomux-v1.c2
-rw-r--r--arch/arm/mach-imx/iomux-v3.c2
-rw-r--r--arch/arm/mach-imx/mach-armadillo5x0.c2
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c321
-rw-r--r--arch/arm/mach-imx/mach-imx6sx.c3
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c154
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c4
-rw-r--r--arch/arm/mach-imx/mach-mx31lite.c2
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c273
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c4
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c358
-rw-r--r--arch/arm/mach-imx/mxc.h2
-rw-r--r--arch/arm/mach-imx/pcm970-baseboard.c231
-rw-r--r--arch/arm/mach-imx/platsmp.c10
-rw-r--r--arch/arm/mach-imx/time.c31
35 files changed, 432 insertions, 1984 deletions
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index b8a5e8c68f06..e4bffbae515f 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -76,7 +76,6 @@
76 76
77 simple-audio-card,cpu { 77 simple-audio-card,cpu {
78 sound-dai = <&sai2>; 78 sound-dai = <&sai2>;
79 master-clkdir-out;
80 frame-master; 79 frame-master;
81 bitclock-master; 80 bitclock-master;
82 }; 81 };
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 63bde0efc041..e688741c89aa 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -21,8 +21,6 @@ CONFIG_ARCH_MULTI_V4T=y
21CONFIG_ARCH_MULTI_V5=y 21CONFIG_ARCH_MULTI_V5=y
22# CONFIG_ARCH_MULTI_V7 is not set 22# CONFIG_ARCH_MULTI_V7 is not set
23CONFIG_ARCH_MXC=y 23CONFIG_ARCH_MXC=y
24CONFIG_MXC_IRQ_PRIOR=y
25CONFIG_ARCH_MX1ADS=y
26CONFIG_MACH_SCB9328=y 24CONFIG_MACH_SCB9328=y
27CONFIG_MACH_APF9328=y 25CONFIG_MACH_APF9328=y
28CONFIG_MACH_MX21ADS=y 26CONFIG_MACH_MX21ADS=y
@@ -30,10 +28,6 @@ CONFIG_MACH_MX25_3DS=y
30CONFIG_MACH_EUKREA_CPUIMX25SD=y 28CONFIG_MACH_EUKREA_CPUIMX25SD=y
31CONFIG_MACH_IMX25_DT=y 29CONFIG_MACH_IMX25_DT=y
32CONFIG_MACH_MX27ADS=y 30CONFIG_MACH_MX27ADS=y
33CONFIG_MACH_PCM038=y
34CONFIG_MACH_CPUIMX27=y
35CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
36CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
37CONFIG_MACH_MX27_3DS=y 31CONFIG_MACH_MX27_3DS=y
38CONFIG_MACH_IMX27_VISSTRIM_M10=y 32CONFIG_MACH_IMX27_VISSTRIM_M10=y
39CONFIG_MACH_PCA100=y 33CONFIG_MACH_PCA100=y
@@ -43,8 +37,6 @@ CONFIG_PREEMPT=y
43CONFIG_AEABI=y 37CONFIG_AEABI=y
44CONFIG_ZBOOT_ROM_TEXT=0x0 38CONFIG_ZBOOT_ROM_TEXT=0x0
45CONFIG_ZBOOT_ROM_BSS=0x0 39CONFIG_ZBOOT_ROM_BSS=0x0
46CONFIG_FPE_NWFPE=y
47CONFIG_FPE_NWFPE_XP=y
48CONFIG_PM_DEBUG=y 40CONFIG_PM_DEBUG=y
49CONFIG_NET=y 41CONFIG_NET=y
50CONFIG_PACKET=y 42CONFIG_PACKET=y
@@ -63,6 +55,7 @@ CONFIG_NETFILTER=y
63CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 55CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
64CONFIG_DEVTMPFS=y 56CONFIG_DEVTMPFS=y
65CONFIG_DEVTMPFS_MOUNT=y 57CONFIG_DEVTMPFS_MOUNT=y
58CONFIG_IMX_WEIM=y
66CONFIG_MTD=y 59CONFIG_MTD=y
67CONFIG_MTD_CMDLINE_PARTS=y 60CONFIG_MTD_CMDLINE_PARTS=y
68CONFIG_MTD_BLOCK=y 61CONFIG_MTD_BLOCK=y
@@ -78,8 +71,8 @@ CONFIG_MTD_NAND_MXC=y
78CONFIG_MTD_UBI=y 71CONFIG_MTD_UBI=y
79CONFIG_EEPROM_AT24=y 72CONFIG_EEPROM_AT24=y
80CONFIG_EEPROM_AT25=y 73CONFIG_EEPROM_AT25=y
81CONFIG_ATA=y
82CONFIG_BLK_DEV_SD=y 74CONFIG_BLK_DEV_SD=y
75CONFIG_ATA=y
83CONFIG_PATA_IMX=y 76CONFIG_PATA_IMX=y
84CONFIG_NETDEVICES=y 77CONFIG_NETDEVICES=y
85CONFIG_CS89x0=y 78CONFIG_CS89x0=y
@@ -102,10 +95,8 @@ CONFIG_SERIAL_8250=m
102CONFIG_SERIAL_IMX=y 95CONFIG_SERIAL_IMX=y
103CONFIG_SERIAL_IMX_CONSOLE=y 96CONFIG_SERIAL_IMX_CONSOLE=y
104# CONFIG_HW_RANDOM is not set 97# CONFIG_HW_RANDOM is not set
105CONFIG_I2C=y
106CONFIG_I2C_CHARDEV=y 98CONFIG_I2C_CHARDEV=y
107CONFIG_I2C_IMX=y 99CONFIG_I2C_IMX=y
108CONFIG_SPI=y
109CONFIG_SPI_IMX=y 100CONFIG_SPI_IMX=y
110CONFIG_SPI_SPIDEV=y 101CONFIG_SPI_SPIDEV=y
111CONFIG_GPIO_SYSFS=y 102CONFIG_GPIO_SYSFS=y
@@ -132,10 +123,7 @@ CONFIG_VIDEO_CODA=y
132CONFIG_SOC_CAMERA_OV2640=y 123CONFIG_SOC_CAMERA_OV2640=y
133CONFIG_FB=y 124CONFIG_FB=y
134CONFIG_FB_IMX=y 125CONFIG_FB_IMX=y
135CONFIG_BACKLIGHT_LCD_SUPPORT=y
136CONFIG_LCD_CLASS_DEVICE=y
137CONFIG_LCD_L4F00242T03=y 126CONFIG_LCD_L4F00242T03=y
138CONFIG_BACKLIGHT_CLASS_DEVICE=y
139CONFIG_FRAMEBUFFER_CONSOLE=y 127CONFIG_FRAMEBUFFER_CONSOLE=y
140CONFIG_LOGO=y 128CONFIG_LOGO=y
141CONFIG_SOUND=y 129CONFIG_SOUND=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 16cfec4385c8..8fca6e276b69 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,8 +32,8 @@ CONFIG_MACH_IMX35_DT=y
32CONFIG_MACH_PCM043=y 32CONFIG_MACH_PCM043=y
33CONFIG_MACH_MX35_3DS=y 33CONFIG_MACH_MX35_3DS=y
34CONFIG_MACH_VPR200=y 34CONFIG_MACH_VPR200=y
35CONFIG_SOC_IMX51=y
36CONFIG_SOC_IMX50=y 35CONFIG_SOC_IMX50=y
36CONFIG_SOC_IMX51=y
37CONFIG_SOC_IMX53=y 37CONFIG_SOC_IMX53=y
38CONFIG_SOC_IMX6Q=y 38CONFIG_SOC_IMX6Q=y
39CONFIG_SOC_IMX6SL=y 39CONFIG_SOC_IMX6SL=y
@@ -105,7 +105,6 @@ CONFIG_EEPROM_AT24=y
105CONFIG_EEPROM_AT25=y 105CONFIG_EEPROM_AT25=y
106# CONFIG_SCSI_PROC_FS is not set 106# CONFIG_SCSI_PROC_FS is not set
107CONFIG_BLK_DEV_SD=y 107CONFIG_BLK_DEV_SD=y
108CONFIG_SCSI_MULTI_LUN=y
109CONFIG_SCSI_CONSTANTS=y 108CONFIG_SCSI_CONSTANTS=y
110CONFIG_SCSI_LOGGING=y 109CONFIG_SCSI_LOGGING=y
111CONFIG_SCSI_SCAN_ASYNC=y 110CONFIG_SCSI_SCAN_ASYNC=y
@@ -153,14 +152,12 @@ CONFIG_SERIAL_IMX_CONSOLE=y
153CONFIG_SERIAL_FSL_LPUART=y 152CONFIG_SERIAL_FSL_LPUART=y
154CONFIG_SERIAL_FSL_LPUART_CONSOLE=y 153CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
155CONFIG_HW_RANDOM=y 154CONFIG_HW_RANDOM=y
156CONFIG_HW_RANDOM_MXC_RNGA=y
157# CONFIG_I2C_COMPAT is not set 155# CONFIG_I2C_COMPAT is not set
158CONFIG_I2C_CHARDEV=y 156CONFIG_I2C_CHARDEV=y
159# CONFIG_I2C_HELPER_AUTO is not set 157# CONFIG_I2C_HELPER_AUTO is not set
160CONFIG_I2C_ALGOPCF=m 158CONFIG_I2C_ALGOPCF=m
161CONFIG_I2C_ALGOPCA=m 159CONFIG_I2C_ALGOPCA=m
162CONFIG_I2C_IMX=y 160CONFIG_I2C_IMX=y
163CONFIG_SPI=y
164CONFIG_SPI_IMX=y 161CONFIG_SPI_IMX=y
165CONFIG_GPIO_SYSFS=y 162CONFIG_GPIO_SYSFS=y
166CONFIG_GPIO_MC9S08DZ60=y 163CONFIG_GPIO_MC9S08DZ60=y
@@ -198,7 +195,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
198CONFIG_LCD_CLASS_DEVICE=y 195CONFIG_LCD_CLASS_DEVICE=y
199CONFIG_LCD_L4F00242T03=y 196CONFIG_LCD_L4F00242T03=y
200CONFIG_LCD_PLATFORM=y 197CONFIG_LCD_PLATFORM=y
201CONFIG_BACKLIGHT_CLASS_DEVICE=y
202CONFIG_BACKLIGHT_PWM=y 198CONFIG_BACKLIGHT_PWM=y
203CONFIG_BACKLIGHT_GPIO=y 199CONFIG_BACKLIGHT_GPIO=y
204CONFIG_FRAMEBUFFER_CONSOLE=y 200CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -206,6 +202,7 @@ CONFIG_LOGO=y
206CONFIG_SOUND=y 202CONFIG_SOUND=y
207CONFIG_SND=y 203CONFIG_SND=y
208CONFIG_SND_SOC=y 204CONFIG_SND_SOC=y
205CONFIG_SND_SOC_FSL_SAI=y
209CONFIG_SND_IMX_SOC=y 206CONFIG_SND_IMX_SOC=y
210CONFIG_SND_SOC_PHYCORE_AC97=y 207CONFIG_SND_SOC_PHYCORE_AC97=y
211CONFIG_SND_SOC_EUKREA_TLV320=y 208CONFIG_SND_SOC_EUKREA_TLV320=y
@@ -213,6 +210,7 @@ CONFIG_SND_SOC_IMX_WM8962=y
213CONFIG_SND_SOC_IMX_SGTL5000=y 210CONFIG_SND_SOC_IMX_SGTL5000=y
214CONFIG_SND_SOC_IMX_SPDIF=y 211CONFIG_SND_SOC_IMX_SPDIF=y
215CONFIG_SND_SOC_IMX_MC13783=y 212CONFIG_SND_SOC_IMX_MC13783=y
213CONFIG_SND_SIMPLE_CARD=y
216CONFIG_USB=y 214CONFIG_USB=y
217CONFIG_USB_EHCI_HCD=y 215CONFIG_USB_EHCI_HCD=y
218CONFIG_USB_EHCI_MXC=y 216CONFIG_USB_EHCI_MXC=y
@@ -240,6 +238,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
240CONFIG_LEDS_TRIGGER_GPIO=y 238CONFIG_LEDS_TRIGGER_GPIO=y
241CONFIG_RTC_CLASS=y 239CONFIG_RTC_CLASS=y
242CONFIG_RTC_INTF_DEV_UIE_EMUL=y 240CONFIG_RTC_INTF_DEV_UIE_EMUL=y
241CONFIG_RTC_DRV_ISL1208=y
243CONFIG_RTC_DRV_PCF8563=y 242CONFIG_RTC_DRV_PCF8563=y
244CONFIG_RTC_DRV_MC13XXX=y 243CONFIG_RTC_DRV_MC13XXX=y
245CONFIG_RTC_DRV_MXC=y 244CONFIG_RTC_DRV_MXC=y
@@ -254,7 +253,6 @@ CONFIG_DRM_IMX_FB_HELPER=y
254CONFIG_DRM_IMX_PARALLEL_DISPLAY=y 253CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
255CONFIG_DRM_IMX_TVE=y 254CONFIG_DRM_IMX_TVE=y
256CONFIG_DRM_IMX_LDB=y 255CONFIG_DRM_IMX_LDB=y
257CONFIG_DRM_IMX_IPUV3_CORE=y
258CONFIG_DRM_IMX_IPUV3=y 256CONFIG_DRM_IMX_IPUV3=y
259CONFIG_DRM_IMX_HDMI=y 257CONFIG_DRM_IMX_HDMI=y
260# CONFIG_IOMMU_SUPPORT is not set 258# CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index be9a51afe05a..11b2957f792b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -69,6 +69,7 @@ config SOC_IMX1
69 select CPU_ARM920T 69 select CPU_ARM920T
70 select IMX_HAVE_IOMUX_V1 70 select IMX_HAVE_IOMUX_V1
71 select MXC_AVIC 71 select MXC_AVIC
72 select PINCTRL_IMX1
72 73
73config SOC_IMX21 74config SOC_IMX21
74 bool 75 bool
@@ -108,17 +109,6 @@ config SOC_IMX35
108if ARCH_MULTI_V4T 109if ARCH_MULTI_V4T
109 110
110comment "MX1 platforms:" 111comment "MX1 platforms:"
111config MACH_MXLADS
112 bool
113
114config ARCH_MX1ADS
115 bool "MX1ADS platform"
116 select IMX_HAVE_PLATFORM_IMX_I2C
117 select IMX_HAVE_PLATFORM_IMX_UART
118 select MACH_MXLADS
119 select SOC_IMX1
120 help
121 Say Y here if you are using Motorola MX1ADS/MXLADS boards
122 112
123config MACH_SCB9328 113config MACH_SCB9328
124 bool "Synertronixx scb9328" 114 bool "Synertronixx scb9328"
@@ -135,6 +125,13 @@ config MACH_APF9328
135 help 125 help
136 Say Yes here if you are using the Armadeus APF9328 development board 126 Say Yes here if you are using the Armadeus APF9328 development board
137 127
128config MACH_IMX1_DT
129 bool "Support i.MX1 platforms from device tree"
130 select SOC_IMX1
131 help
132 Include support for Freescale i.MX1 based platforms
133 using the device tree for discovery.
134
138endif 135endif
139 136
140if ARCH_MULTI_V5 137if ARCH_MULTI_V5
@@ -223,86 +220,6 @@ config MACH_MX27ADS
223 Include support for MX27ADS platform. This includes specific 220 Include support for MX27ADS platform. This includes specific
224 configurations for the board and its peripherals. 221 configurations for the board and its peripherals.
225 222
226config MACH_PCM038
227 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
228 select IMX_HAVE_PLATFORM_IMX2_WDT
229 select IMX_HAVE_PLATFORM_IMX_I2C
230 select IMX_HAVE_PLATFORM_IMX_UART
231 select IMX_HAVE_PLATFORM_MXC_EHCI
232 select IMX_HAVE_PLATFORM_MXC_NAND
233 select IMX_HAVE_PLATFORM_MXC_W1
234 select IMX_HAVE_PLATFORM_SPI_IMX
235 select USB_ULPI_VIEWPORT if USB_ULPI
236 select SOC_IMX27
237 help
238 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
239 includes specific configurations for the module and its peripherals.
240
241choice
242 prompt "Baseboard"
243 depends on MACH_PCM038
244 default MACH_PCM970_BASEBOARD
245
246config MACH_PCM970_BASEBOARD
247 bool "PHYTEC PCM970 development board"
248 select IMX_HAVE_PLATFORM_IMX_FB
249 select IMX_HAVE_PLATFORM_MXC_MMC
250 help
251 This adds board specific devices that can be found on Phytec's
252 PCM970 evaluation board.
253
254endchoice
255
256config MACH_CPUIMX27
257 bool "Eukrea CPUIMX27 module"
258 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
259 select IMX_HAVE_PLATFORM_IMX2_WDT
260 select IMX_HAVE_PLATFORM_IMX_I2C
261 select IMX_HAVE_PLATFORM_IMX_UART
262 select IMX_HAVE_PLATFORM_MXC_EHCI
263 select IMX_HAVE_PLATFORM_MXC_NAND
264 select IMX_HAVE_PLATFORM_MXC_W1
265 select USB_ULPI_VIEWPORT if USB_ULPI
266 select SOC_IMX27
267 help
268 Include support for Eukrea CPUIMX27 platform. This includes
269 specific configurations for the module and its peripherals.
270
271config MACH_EUKREA_CPUIMX27_USESDHC2
272 bool "CPUIMX27 integrates SDHC2 module"
273 depends on MACH_CPUIMX27
274 select IMX_HAVE_PLATFORM_MXC_MMC
275 help
276 This adds support for the internal SDHC2 used on CPUIMX27
277 for wifi or eMMC.
278
279config MACH_EUKREA_CPUIMX27_USEUART4
280 bool "CPUIMX27 integrates UART4 module"
281 depends on MACH_CPUIMX27
282 help
283 This adds support for the internal UART4 used on CPUIMX27
284 for bluetooth.
285
286choice
287 prompt "Baseboard"
288 depends on MACH_CPUIMX27
289 default MACH_EUKREA_MBIMX27_BASEBOARD
290
291config MACH_EUKREA_MBIMX27_BASEBOARD
292 bool "Eukrea MBIMX27 development board"
293 select IMX_HAVE_PLATFORM_IMX_FB
294 select IMX_HAVE_PLATFORM_IMX_KEYPAD
295 select IMX_HAVE_PLATFORM_IMX_SSI
296 select IMX_HAVE_PLATFORM_IMX_UART
297 select IMX_HAVE_PLATFORM_MXC_MMC
298 select IMX_HAVE_PLATFORM_SPI_IMX
299 select LEDS_GPIO_REGISTER
300 help
301 This adds board specific devices that can be found on Eukrea's
302 MBIMX27 evaluation board.
303
304endchoice
305
306config MACH_MX27_3DS 223config MACH_MX27_3DS
307 bool "MX27PDK platform" 224 bool "MX27PDK platform"
308 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 225 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
@@ -359,18 +276,6 @@ config MACH_PCA100
359 Include support for phyCARD-s (aka pca100) platform. This 276 Include support for phyCARD-s (aka pca100) platform. This
360 includes specific configurations for the module and its peripherals. 277 includes specific configurations for the module and its peripherals.
361 278
362config MACH_MXT_TD60
363 bool "Maxtrack i-MXT TD60"
364 select IMX_HAVE_PLATFORM_IMX_FB
365 select IMX_HAVE_PLATFORM_IMX_I2C
366 select IMX_HAVE_PLATFORM_IMX_UART
367 select IMX_HAVE_PLATFORM_MXC_MMC
368 select IMX_HAVE_PLATFORM_MXC_NAND
369 select SOC_IMX27
370 help
371 Include support for i-MXT (aka td60) platform. This
372 includes specific configurations for the module and its peripherals.
373
374config MACH_IMX27_DT 279config MACH_IMX27_DT
375 bool "Support i.MX27 platforms from device tree" 280 bool "Support i.MX27 platforms from device tree"
376 select SOC_IMX27 281 select SOC_IMX27
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 23c02932bf84..6e4fcd8339cd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
16 16
17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ 17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18 clk-pfd.o clk-busy.o clk.o \ 18 clk-pfd.o clk-busy.o clk.o \
19 clk-fixup-div.o clk-fixup-mux.o 19 clk-fixup-div.o clk-fixup-mux.o \
20 clk-gate-exclusive.o
20 21
21obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 22obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
22obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 23obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
@@ -41,9 +42,9 @@ obj-y += ssi-fiq-ksym.o
41endif 42endif
42 43
43# i.MX1 based machines 44# i.MX1 based machines
44obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
45obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o 45obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
46obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o 46obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
47obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
47 48
48# i.MX21 based machines 49# i.MX21 based machines
49obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 50obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
@@ -56,14 +57,9 @@ obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
56 57
57# i.MX27 based machines 58# i.MX27 based machines
58obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 59obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
59obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
60obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
61obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o 60obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
62obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o 61obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
63obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
64obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
65obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 62obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
66obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
67obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o 63obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
68 64
69# i.MX31 based machines 65# i.MX31 based machines
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 4a40bbb46183..8259a625a920 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -104,6 +104,19 @@ void __init imx_init_revision_from_anatop(void)
104 case 2: 104 case 2:
105 revision = IMX_CHIP_REVISION_1_2; 105 revision = IMX_CHIP_REVISION_1_2;
106 break; 106 break;
107 case 3:
108 revision = IMX_CHIP_REVISION_1_3;
109 break;
110 case 4:
111 revision = IMX_CHIP_REVISION_1_4;
112 break;
113 case 5:
114 /*
115 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
116 * as 'D' in Part Number last character.
117 */
118 revision = IMX_CHIP_REVISION_1_5;
119 break;
107 default: 120 default:
108 revision = IMX_CHIP_REVISION_UNKNOWN; 121 revision = IMX_CHIP_REVISION_UNKNOWN;
109 } 122 }
diff --git a/arch/arm/mach-imx/board-pcm038.h b/arch/arm/mach-imx/board-pcm038.h
deleted file mode 100644
index 6f371e35753d..000000000000
--- a/arch/arm/mach-imx/board-pcm038.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
20#define __ASM_ARCH_MXC_BOARD_PCM038_H__
21
22#ifndef __ASSEMBLY__
23/*
24 * This CPU module needs a baseboard to work. After basic initializing
25 * its own devices, it calls the baseboard's init function.
26 * TODO: Add your own baseboard init function and call it from
27 * inside pcm038_init().
28 *
29 * This example here is for the development board. Refer pcm970-baseboard.c
30 */
31
32extern void pcm970_baseboard_init(void);
33
34#endif
35
36#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/arch/arm/mach-imx/clk-gate-exclusive.c b/arch/arm/mach-imx/clk-gate-exclusive.c
new file mode 100644
index 000000000000..c12f5f2e04dc
--- /dev/null
+++ b/arch/arm/mach-imx/clk-gate-exclusive.c
@@ -0,0 +1,94 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/slab.h>
13#include "clk.h"
14
15/**
16 * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
17 * exclusive with other gate clocks
18 *
19 * @gate: the parent class
20 * @exclusive_mask: mask of gate bits which are mutually exclusive to this
21 * gate clock
22 *
23 * The imx exclusive gate clock is a subclass of basic clk_gate
24 * with an addtional mask to indicate which other gate bits in the same
25 * register is mutually exclusive to this gate clock.
26 */
27struct clk_gate_exclusive {
28 struct clk_gate gate;
29 u32 exclusive_mask;
30};
31
32static int clk_gate_exclusive_enable(struct clk_hw *hw)
33{
34 struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
35 struct clk_gate_exclusive *exgate = container_of(gate,
36 struct clk_gate_exclusive, gate);
37 u32 val = readl(gate->reg);
38
39 if (val & exgate->exclusive_mask)
40 return -EBUSY;
41
42 return clk_gate_ops.enable(hw);
43}
44
45static void clk_gate_exclusive_disable(struct clk_hw *hw)
46{
47 clk_gate_ops.disable(hw);
48}
49
50static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
51{
52 return clk_gate_ops.is_enabled(hw);
53}
54
55static const struct clk_ops clk_gate_exclusive_ops = {
56 .enable = clk_gate_exclusive_enable,
57 .disable = clk_gate_exclusive_disable,
58 .is_enabled = clk_gate_exclusive_is_enabled,
59};
60
61struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
62 void __iomem *reg, u8 shift, u32 exclusive_mask)
63{
64 struct clk_gate_exclusive *exgate;
65 struct clk_gate *gate;
66 struct clk *clk;
67 struct clk_init_data init;
68
69 if (exclusive_mask == 0)
70 return ERR_PTR(-EINVAL);
71
72 exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
73 if (!exgate)
74 return ERR_PTR(-ENOMEM);
75 gate = &exgate->gate;
76
77 init.name = name;
78 init.ops = &clk_gate_exclusive_ops;
79 init.flags = CLK_SET_RATE_PARENT;
80 init.parent_names = parent ? &parent : NULL;
81 init.num_parents = parent ? 1 : 0;
82
83 gate->reg = reg;
84 gate->bit_idx = shift;
85 gate->lock = &imx_ccm_lock;
86 gate->hw.init = &init;
87 exgate->exclusive_mask = exclusive_mask;
88
89 clk = clk_register(NULL, &gate->hw);
90 if (IS_ERR(clk))
91 kfree(exgate);
92
93 return clk;
94}
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 29d412975aff..1412daf4a714 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -64,7 +64,7 @@ static const char *cko2_sels[] = {
64 "ipu2", "vdo_axi", "osc", "gpu2d_core", 64 "ipu2", "vdo_axi", "osc", "gpu2d_core",
65 "gpu3d_core", "usdhc2", "ssi1", "ssi2", 65 "gpu3d_core", "usdhc2", "ssi1", "ssi2",
66 "ssi3", "gpu3d_shader", "vpu_axi", "can_root", 66 "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
67 "ldb_di0", "ldb_di1", "esai", "eim_slow", 67 "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
68 "uart_serial", "spdif", "asrc", "hsi_tx", 68 "uart_serial", "spdif", "asrc", "hsi_tx",
69}; 69};
70static const char *cko_sels[] = { "cko1", "cko2", }; 70static const char *cko_sels[] = { "cko1", "cko2", };
@@ -73,6 +73,14 @@ static const char *lvds_sels[] = {
73 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", 73 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
74 "pcie_ref_125m", "sata_ref_100m", 74 "pcie_ref_125m", "sata_ref_100m",
75}; 75};
76static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
77static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
78static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
79static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
80static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
81static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
82static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
83static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
76 84
77static struct clk *clk[IMX6QDL_CLK_END]; 85static struct clk *clk[IMX6QDL_CLK_END];
78static struct clk_onecell_data clk_data; 86static struct clk_onecell_data clk_data;
@@ -107,6 +115,10 @@ static struct clk_div_table video_div_table[] = {
107}; 115};
108 116
109static unsigned int share_count_esai; 117static unsigned int share_count_esai;
118static unsigned int share_count_asrc;
119static unsigned int share_count_ssi1;
120static unsigned int share_count_ssi2;
121static unsigned int share_count_ssi3;
110 122
111static void __init imx6q_clocks_init(struct device_node *ccm_node) 123static void __init imx6q_clocks_init(struct device_node *ccm_node)
112{ 124{
@@ -119,6 +131,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
119 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); 131 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
120 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); 132 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
121 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); 133 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
134 /* Clock source from external clock via CLK1/2 PADs */
135 clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
136 clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
122 137
123 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 138 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
124 base = of_iomap(np, 0); 139 base = of_iomap(np, 0);
@@ -132,14 +147,47 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
132 video_div_table[2].div = 1; 147 video_div_table[2].div = 1;
133 }; 148 };
134 149
135 /* type name parent_name base div_mask */ 150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
136 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 151 clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
137 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 152 clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
138 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 153 clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
139 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 154 clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
140 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 155 clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
141 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 156 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
142 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); 157
158 /* type name parent_name base div_mask */
159 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
160 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
161 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
162 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
163 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
164 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
165 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
166
167 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
168 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
169 clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
170 clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
171 clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
172 clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
173 clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
174
175 /* Do not bypass PLLs initially */
176 clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
177 clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
178 clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
179 clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
180 clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
181 clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
182 clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
183
184 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
185 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
186 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
187 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
188 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
189 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
190 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
143 191
144 /* 192 /*
145 * Bit 20 is the reserved and read-only bit, we do this only for: 193 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,8 +224,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
176 * the "output_enable" bit as a gate, even though it's really just 224 * the "output_enable" bit as a gate, even though it's really just
177 * enabling clock output. 225 * enabling clock output.
178 */ 226 */
179 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); 227 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
180 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); 228 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
229
230 clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
231 clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
181 232
182 /* name parent_name reg idx */ 233 /* name parent_name reg idx */
183 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 234 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
@@ -194,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
194 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 245 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
195 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 246 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
196 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); 247 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
248 clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
197 if (cpu_is_imx6dl()) { 249 if (cpu_is_imx6dl()) {
198 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); 250 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
199 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); 251 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
@@ -317,7 +369,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
317 369
318 /* name parent_name reg shift */ 370 /* name parent_name reg shift */
319 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); 371 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
320 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); 372 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
373 clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
374 clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
321 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); 375 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
322 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); 376 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
323 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); 377 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
@@ -331,8 +385,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
331 else 385 else
332 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 386 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
333 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 387 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
334 clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); 388 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
335 clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); 389 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ipg", base + 0x6c, 16, &share_count_esai);
390 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
336 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 391 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
337 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 392 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
338 if (cpu_is_imx6dl()) 393 if (cpu_is_imx6dl())
@@ -388,9 +443,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
388 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 443 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
389 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 444 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
390 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); 445 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
391 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); 446 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
392 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); 447 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
393 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); 448 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
449 clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
450 clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
451 clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
394 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 452 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
395 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 453 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
396 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 454 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
@@ -404,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
404 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
405 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); 463 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
406 464
465 /*
466 * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it
467 * to clock gpt_ipg_per to ease the gpt driver code.
468 */
469 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
470 clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];
471
407 imx_check_clocks(clk, ARRAY_SIZE(clk)); 472 imx_check_clocks(clk, ARRAY_SIZE(clk));
408 473
409 clk_data.clks = clk; 474 clk_data.clks = clk;
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index fef46faf692f..e982ebe10814 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -43,11 +43,13 @@ static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy",
43static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 43static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
44static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; 44static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
45static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; 45static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
46static const char *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; 46static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
47static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
47static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; 48static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
48static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; 49static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
49static const char *perclk_sels[] = { "ipg", "osc", }; 50static const char *perclk_sels[] = { "ipg", "osc", };
50static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; 51static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
52static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
51static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; 53static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
52static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; 54static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
53static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; 55static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
@@ -55,6 +57,20 @@ static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_d
55static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; 57static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
56static const char *ecspi_sels[] = { "pll3_60m", "osc", }; 58static const char *ecspi_sels[] = { "pll3_60m", "osc", };
57static const char *uart_sels[] = { "pll3_80m", "osc", }; 59static const char *uart_sels[] = { "pll3_80m", "osc", };
60static const char *lvds_sels[] = {
61 "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
62 "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
63 "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
64 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
65};
66static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
67static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
68static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
69static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
70static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
71static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
72static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
73static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
58 74
59static struct clk_div_table clk_enet_ref_table[] = { 75static struct clk_div_table clk_enet_ref_table[] = {
60 { .val = 0, .div = 20, }, 76 { .val = 0, .div = 20, },
@@ -79,6 +95,10 @@ static struct clk_div_table video_div_table[] = {
79 { } 95 { }
80}; 96};
81 97
98static unsigned int share_count_ssi1;
99static unsigned int share_count_ssi2;
100static unsigned int share_count_ssi3;
101
82static struct clk *clks[IMX6SL_CLK_END]; 102static struct clk *clks[IMX6SL_CLK_END];
83static struct clk_onecell_data clk_data; 103static struct clk_onecell_data clk_data;
84static void __iomem *ccm_base; 104static void __iomem *ccm_base;
@@ -175,20 +195,59 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
175 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 195 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
176 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); 196 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
177 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); 197 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
198 /* Clock source from external clock via CLK1 PAD */
199 clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
178 200
179 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); 201 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
180 base = of_iomap(np, 0); 202 base = of_iomap(np, 0);
181 WARN_ON(!base); 203 WARN_ON(!base);
182 anatop_base = base; 204 anatop_base = base;
183 205
184 /* type name parent base div_mask */ 206 clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
185 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 207 clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
186 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 208 clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
187 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 209 clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
188 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 210 clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
189 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 211 clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
190 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 212 clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
191 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); 213
214 /* type name parent_name base div_mask */
215 clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
216 clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
217 clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
218 clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
219 clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
220 clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
221 clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
222
223 clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
224 clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
225 clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
226 clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
227 clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
228 clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
229 clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
230
231 /* Do not bypass PLLs initially */
232 clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
233 clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
234 clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
235 clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
236 clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
237 clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
238 clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
239
240 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
241 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
242 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
243 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
244 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
245 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
246 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
247
248 clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
249 clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
250 clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
192 251
193 /* 252 /*
194 * usbphy1 and usbphy2 are implemented as dummy gates using reserve 253 * usbphy1 and usbphy2 are implemented as dummy gates using reserve
@@ -241,8 +300,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
241 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); 300 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
242 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); 301 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
243 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 302 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
244 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); 303 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
245 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); 304 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
246 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 305 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
247 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 306 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
248 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 307 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
@@ -251,8 +310,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
251 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 310 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
252 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 311 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
253 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); 312 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
254 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); 313 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
255 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); 314 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
256 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); 315 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
257 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); 316 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
258 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); 317 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
@@ -337,9 +396,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
337 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); 396 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
338 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 397 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
339 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); 398 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
340 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); 399 clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
341 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); 400 clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
342 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); 401 clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
402 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
403 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
404 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
343 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); 405 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
344 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); 406 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
345 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 407 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
@@ -375,6 +437,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
375 /* Audio-related clocks configuration */ 437 /* Audio-related clocks configuration */
376 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); 438 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
377 439
440 /* set PLL5 video as lcdif pix parent clock */
441 clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
442 clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
443
444 clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
445 clks[IMX6SL_CLK_PLL2_PFD2]);
446
378 /* Set initial power mode */ 447 /* Set initial power mode */
379 imx6q_set_lpm(WAIT_CLOCKED); 448 imx6q_set_lpm(WAIT_CLOCKED);
380} 449}
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index ecde72bdfe88..17354a11356f 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -81,6 +81,14 @@ static const char *lvds_sels[] = {
81 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", 81 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
82 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", 82 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
83}; 83};
84static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
85static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
86static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
87static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
88static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
89static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
90static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
91static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
84 92
85static struct clk *clks[IMX6SX_CLK_CLK_END]; 93static struct clk *clks[IMX6SX_CLK_CLK_END];
86static struct clk_onecell_data clk_data; 94static struct clk_onecell_data clk_data;
@@ -143,18 +151,54 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
143 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); 151 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
144 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); 152 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
145 153
154 /* Clock source from external clock via CLK1 PAD */
155 clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
156
146 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); 157 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
147 base = of_iomap(np, 0); 158 base = of_iomap(np, 0);
148 WARN_ON(!base); 159 WARN_ON(!base);
149 160
150 /* type name parent_name base div_mask */ 161 clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
151 clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 162 clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
152 clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 163 clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
153 clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 164 clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
154 clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 165 clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
155 clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 166 clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
156 clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 167 clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
157 clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); 168
169 /* type name parent_name base div_mask */
170 clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
171 clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
172 clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
173 clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
174 clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
175 clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
176 clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
177
178 clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
179 clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
180 clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
181 clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
182 clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
183 clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
184 clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
185
186 /* Do not bypass PLLs initially */
187 clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
188 clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
189 clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
190 clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
191 clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
192 clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
193 clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
194
195 clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
196 clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
197 clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
198 clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
199 clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
200 clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
201 clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
158 202
159 /* 203 /*
160 * Bit 20 is the reserved and read-only bit, we do this only for: 204 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,7 +220,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
176 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5); 220 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
177 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 221 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
178 222
179 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10); 223 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
224 clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
180 225
181 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 226 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
182 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 227 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 61364050fccd..57de74da0acf 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -23,8 +23,6 @@
23#define PLL_DENOM_OFFSET 0x20 23#define PLL_DENOM_OFFSET 0x20
24 24
25#define BM_PLL_POWER (0x1 << 12) 25#define BM_PLL_POWER (0x1 << 12)
26#define BM_PLL_ENABLE (0x1 << 13)
27#define BM_PLL_BYPASS (0x1 << 16)
28#define BM_PLL_LOCK (0x1 << 31) 26#define BM_PLL_LOCK (0x1 << 31)
29 27
30/** 28/**
@@ -84,10 +82,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
84 if (ret) 82 if (ret)
85 return ret; 83 return ret;
86 84
87 val = readl_relaxed(pll->base);
88 val &= ~BM_PLL_BYPASS;
89 writel_relaxed(val, pll->base);
90
91 return 0; 85 return 0;
92} 86}
93 87
@@ -97,7 +91,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
97 u32 val; 91 u32 val;
98 92
99 val = readl_relaxed(pll->base); 93 val = readl_relaxed(pll->base);
100 val |= BM_PLL_BYPASS;
101 if (pll->powerup_set) 94 if (pll->powerup_set)
102 val &= ~BM_PLL_POWER; 95 val &= ~BM_PLL_POWER;
103 else 96 else
@@ -105,28 +98,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
105 writel_relaxed(val, pll->base); 98 writel_relaxed(val, pll->base);
106} 99}
107 100
108static int clk_pllv3_enable(struct clk_hw *hw)
109{
110 struct clk_pllv3 *pll = to_clk_pllv3(hw);
111 u32 val;
112
113 val = readl_relaxed(pll->base);
114 val |= BM_PLL_ENABLE;
115 writel_relaxed(val, pll->base);
116
117 return 0;
118}
119
120static void clk_pllv3_disable(struct clk_hw *hw)
121{
122 struct clk_pllv3 *pll = to_clk_pllv3(hw);
123 u32 val;
124
125 val = readl_relaxed(pll->base);
126 val &= ~BM_PLL_ENABLE;
127 writel_relaxed(val, pll->base);
128}
129
130static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 101static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
131 unsigned long parent_rate) 102 unsigned long parent_rate)
132{ 103{
@@ -169,8 +140,6 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
169static const struct clk_ops clk_pllv3_ops = { 140static const struct clk_ops clk_pllv3_ops = {
170 .prepare = clk_pllv3_prepare, 141 .prepare = clk_pllv3_prepare,
171 .unprepare = clk_pllv3_unprepare, 142 .unprepare = clk_pllv3_unprepare,
172 .enable = clk_pllv3_enable,
173 .disable = clk_pllv3_disable,
174 .recalc_rate = clk_pllv3_recalc_rate, 143 .recalc_rate = clk_pllv3_recalc_rate,
175 .round_rate = clk_pllv3_round_rate, 144 .round_rate = clk_pllv3_round_rate,
176 .set_rate = clk_pllv3_set_rate, 145 .set_rate = clk_pllv3_set_rate,
@@ -225,8 +194,6 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
225static const struct clk_ops clk_pllv3_sys_ops = { 194static const struct clk_ops clk_pllv3_sys_ops = {
226 .prepare = clk_pllv3_prepare, 195 .prepare = clk_pllv3_prepare,
227 .unprepare = clk_pllv3_unprepare, 196 .unprepare = clk_pllv3_unprepare,
228 .enable = clk_pllv3_enable,
229 .disable = clk_pllv3_disable,
230 .recalc_rate = clk_pllv3_sys_recalc_rate, 197 .recalc_rate = clk_pllv3_sys_recalc_rate,
231 .round_rate = clk_pllv3_sys_round_rate, 198 .round_rate = clk_pllv3_sys_round_rate,
232 .set_rate = clk_pllv3_sys_set_rate, 199 .set_rate = clk_pllv3_sys_set_rate,
@@ -299,8 +266,6 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
299static const struct clk_ops clk_pllv3_av_ops = { 266static const struct clk_ops clk_pllv3_av_ops = {
300 .prepare = clk_pllv3_prepare, 267 .prepare = clk_pllv3_prepare,
301 .unprepare = clk_pllv3_unprepare, 268 .unprepare = clk_pllv3_unprepare,
302 .enable = clk_pllv3_enable,
303 .disable = clk_pllv3_disable,
304 .recalc_rate = clk_pllv3_av_recalc_rate, 269 .recalc_rate = clk_pllv3_av_recalc_rate,
305 .round_rate = clk_pllv3_av_round_rate, 270 .round_rate = clk_pllv3_av_round_rate,
306 .set_rate = clk_pllv3_av_set_rate, 271 .set_rate = clk_pllv3_av_set_rate,
@@ -315,8 +280,6 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
315static const struct clk_ops clk_pllv3_enet_ops = { 280static const struct clk_ops clk_pllv3_enet_ops = {
316 .prepare = clk_pllv3_prepare, 281 .prepare = clk_pllv3_prepare,
317 .unprepare = clk_pllv3_unprepare, 282 .unprepare = clk_pllv3_unprepare,
318 .enable = clk_pllv3_enable,
319 .disable = clk_pllv3_disable,
320 .recalc_rate = clk_pllv3_enet_recalc_rate, 283 .recalc_rate = clk_pllv3_enet_recalc_rate,
321}; 284};
322 285
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index f60d6d569ce3..a17818475050 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -58,6 +58,8 @@
58#define PFD_PLL1_BASE (anatop_base + 0x2b0) 58#define PFD_PLL1_BASE (anatop_base + 0x2b0)
59#define PFD_PLL2_BASE (anatop_base + 0x100) 59#define PFD_PLL2_BASE (anatop_base + 0x100)
60#define PFD_PLL3_BASE (anatop_base + 0xf0) 60#define PFD_PLL3_BASE (anatop_base + 0xf0)
61#define PLL3_CTRL (anatop_base + 0x10)
62#define PLL7_CTRL (anatop_base + 0x20)
61 63
62static void __iomem *anatop_base; 64static void __iomem *anatop_base;
63static void __iomem *ccm_base; 65static void __iomem *ccm_base;
@@ -98,9 +100,15 @@ static struct clk_div_table pll4_main_div_table[] = {
98static struct clk *clk[VF610_CLK_END]; 100static struct clk *clk[VF610_CLK_END];
99static struct clk_onecell_data clk_data; 101static struct clk_onecell_data clk_data;
100 102
103static unsigned int const clks_init_on[] __initconst = {
104 VF610_CLK_SYS_BUS,
105 VF610_CLK_DDR_SEL,
106};
107
101static void __init vf610_clocks_init(struct device_node *ccm_node) 108static void __init vf610_clocks_init(struct device_node *ccm_node)
102{ 109{
103 struct device_node *np; 110 struct device_node *np;
111 int i;
104 112
105 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 113 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
106 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); 114 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
@@ -148,6 +156,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
148 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); 156 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
149 /* pll6: default 960Mhz */ 157 /* pll6: default 960Mhz */
150 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); 158 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
159 /* pll7: USB1 PLL at 480MHz */
160 clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
161
151 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); 162 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
152 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); 163 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
153 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); 164 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
@@ -160,8 +171,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
160 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); 171 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
161 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); 172 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
162 173
163 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); 174 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
164 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); 175 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
176
177 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
178 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
165 179
166 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); 180 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
167 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); 181 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
@@ -322,6 +336,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
322 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); 336 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
323 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); 337 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
324 338
339 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
340 clk_prepare_enable(clk[clks_init_on[i]]);
341
325 /* Add the clocks to provider list */ 342 /* Add the clocks to provider list */
326 clk_data.clks = clk; 343 clk_data.clks = clk;
327 clk_data.clk_num = ARRAY_SIZE(clk); 344 clk_data.clk_num = ARRAY_SIZE(clk);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d5ba76fee115..4cdf8b6a74e8 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -36,6 +36,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
36struct clk * imx_obtain_fixed_clock( 36struct clk * imx_obtain_fixed_clock(
37 const char *name, unsigned long rate); 37 const char *name, unsigned long rate);
38 38
39struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
40 void __iomem *reg, u8 shift, u32 exclusive_mask);
41
39static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 42static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
40 void __iomem *reg, u8 shift) 43 void __iomem *reg, u8 shift)
41{ 44{
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 22ba8973bcb9..1dabf435c592 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -98,11 +98,9 @@ void imx_set_cpu_arg(int cpu, u32 arg);
98void v7_secondary_startup(void); 98void v7_secondary_startup(void);
99void imx_scu_map_io(void); 99void imx_scu_map_io(void);
100void imx_smp_prepare(void); 100void imx_smp_prepare(void);
101void imx_scu_standby_enable(void);
102#else 101#else
103static inline void imx_scu_map_io(void) {} 102static inline void imx_scu_map_io(void) {}
104static inline void imx_smp_prepare(void) {} 103static inline void imx_smp_prepare(void) {}
105static inline void imx_scu_standby_enable(void) {}
106#endif 104#endif
107void imx_src_init(void); 105void imx_src_init(void);
108void imx_gpc_init(void); 106void imx_gpc_init(void);
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 10844d3bb926..aa935787b743 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -66,10 +66,6 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
66 66
67int __init imx6q_cpuidle_init(void) 67int __init imx6q_cpuidle_init(void)
68{ 68{
69 /* Need to enable SCU standby for entering WAIT modes */
70 if (!cpu_is_imx6sx())
71 imx_scu_standby_enable();
72
73 /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ 69 /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
74 imx6q_set_int_mem_clk_lpm(true); 70 imx6q_set_int_mem_clk_lpm(true);
75 71
diff --git a/arch/arm/mach-imx/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h
index a21d3313f994..bb2c90d65914 100644
--- a/arch/arm/mach-imx/eukrea-baseboards.h
+++ b/arch/arm/mach-imx/eukrea-baseboards.h
@@ -27,23 +27,15 @@
27 * This CPU module needs a baseboard to work. After basic initializing 27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() 30 * inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init()
31 * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
32 * or eukrea_cpuimx51sd_init().
33 * 31 *
34 * This example here is for the development board. Refer 32 * This example here is for the development board. Refer
35 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 33 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
36 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
37 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 34 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
38 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
39 * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
40 */ 35 */
41 36
42extern void eukrea_mbimxsd25_baseboard_init(void); 37extern void eukrea_mbimxsd25_baseboard_init(void);
43extern void eukrea_mbimx27_baseboard_init(void);
44extern void eukrea_mbimxsd35_baseboard_init(void); 38extern void eukrea_mbimxsd35_baseboard_init(void);
45extern void eukrea_mbimx51_baseboard_init(void);
46extern void eukrea_mbimxsd51_baseboard_init(void);
47 39
48#endif 40#endif
49 41
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
deleted file mode 100644
index b2f08bfbbdd3..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ /dev/null
@@ -1,351 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/gpio.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h>
27#include <linux/backlight.h>
28#include <video/platform_lcd.h>
29
30#include <asm/mach/arch.h>
31
32#include "common.h"
33#include "devices-imx27.h"
34#include "hardware.h"
35#include "iomux-mx27.h"
36
37static const int eukrea_mbimx27_pins[] __initconst = {
38 /* UART2 */
39 PE3_PF_UART2_CTS,
40 PE4_PF_UART2_RTS,
41 PE6_PF_UART2_TXD,
42 PE7_PF_UART2_RXD,
43 /* UART3 */
44 PE8_PF_UART3_TXD,
45 PE9_PF_UART3_RXD,
46 PE10_PF_UART3_CTS,
47 PE11_PF_UART3_RTS,
48 /* UART4 */
49#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
50 PB26_AF_UART4_RTS,
51 PB28_AF_UART4_TXD,
52 PB29_AF_UART4_CTS,
53 PB31_AF_UART4_RXD,
54#endif
55 /* SDHC1*/
56 PE18_PF_SD1_D0,
57 PE19_PF_SD1_D1,
58 PE20_PF_SD1_D2,
59 PE21_PF_SD1_D3,
60 PE22_PF_SD1_CMD,
61 PE23_PF_SD1_CLK,
62 /* display */
63 PA5_PF_LSCLK,
64 PA6_PF_LD0,
65 PA7_PF_LD1,
66 PA8_PF_LD2,
67 PA9_PF_LD3,
68 PA10_PF_LD4,
69 PA11_PF_LD5,
70 PA12_PF_LD6,
71 PA13_PF_LD7,
72 PA14_PF_LD8,
73 PA15_PF_LD9,
74 PA16_PF_LD10,
75 PA17_PF_LD11,
76 PA18_PF_LD12,
77 PA19_PF_LD13,
78 PA20_PF_LD14,
79 PA21_PF_LD15,
80 PA22_PF_LD16,
81 PA23_PF_LD17,
82 PA28_PF_HSYNC,
83 PA29_PF_VSYNC,
84 PA30_PF_CONTRAST,
85 PA31_PF_OE_ACD,
86 /* SPI1 */
87 PD29_PF_CSPI1_SCLK,
88 PD30_PF_CSPI1_MISO,
89 PD31_PF_CSPI1_MOSI,
90 /* SSI4 */
91#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
92 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
93 PC16_PF_SSI4_FS,
94 PC17_PF_SSI4_RXD | GPIO_PUEN,
95 PC18_PF_SSI4_TXD | GPIO_PUEN,
96 PC19_PF_SSI4_CLK,
97#endif
98};
99
100static const uint32_t eukrea_mbimx27_keymap[] = {
101 KEY(0, 0, KEY_UP),
102 KEY(0, 1, KEY_DOWN),
103 KEY(1, 0, KEY_RIGHT),
104 KEY(1, 1, KEY_LEFT),
105};
106
107static const struct matrix_keymap_data
108eukrea_mbimx27_keymap_data __initconst = {
109 .keymap = eukrea_mbimx27_keymap,
110 .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
111};
112
113static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = {
114 {
115 .name = "led1",
116 .default_trigger = "heartbeat",
117 .active_low = 1,
118 .gpio = GPIO_PORTF | 16,
119 },
120 {
121 .name = "led2",
122 .default_trigger = "none",
123 .active_low = 1,
124 .gpio = GPIO_PORTF | 19,
125 },
126};
127
128static const struct gpio_led_platform_data
129 eukrea_mbimx27_gpio_led_info __initconst = {
130 .leds = eukrea_mbimx27_gpio_leds,
131 .num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds),
132};
133
134static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
135 {
136 .mode = {
137 .name = "CMO-QVGA",
138 .refresh = 60,
139 .xres = 320,
140 .yres = 240,
141 .pixclock = 156000,
142 .hsync_len = 30,
143 .left_margin = 38,
144 .right_margin = 20,
145 .vsync_len = 3,
146 .upper_margin = 15,
147 .lower_margin = 4,
148 },
149 .pcr = 0xFAD08B80,
150 .bpp = 16,
151 }, {
152 .mode = {
153 .name = "DVI-VGA",
154 .refresh = 60,
155 .xres = 640,
156 .yres = 480,
157 .pixclock = 32000,
158 .hsync_len = 1,
159 .left_margin = 35,
160 .right_margin = 0,
161 .vsync_len = 1,
162 .upper_margin = 7,
163 .lower_margin = 0,
164 },
165 .pcr = 0xFA208B80,
166 .bpp = 16,
167 }, {
168 .mode = {
169 .name = "DVI-SVGA",
170 .refresh = 60,
171 .xres = 800,
172 .yres = 600,
173 .pixclock = 25000,
174 .hsync_len = 1,
175 .left_margin = 35,
176 .right_margin = 0,
177 .vsync_len = 1,
178 .upper_margin = 7,
179 .lower_margin = 0,
180 },
181 .pcr = 0xFA208B80,
182 .bpp = 16,
183 },
184};
185
186static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
187 .mode = eukrea_mbimx27_modes,
188 .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
189
190 .pwmr = 0x00A903FF,
191 .lscr1 = 0x00120300,
192 .dmacr = 0x00040060,
193};
194
195static void eukrea_mbimx27_bl_set_intensity(int intensity)
196{
197 if (intensity)
198 gpio_direction_output(GPIO_PORTE | 5, 1);
199 else
200 gpio_direction_output(GPIO_PORTE | 5, 0);
201}
202
203static struct generic_bl_info eukrea_mbimx27_bl_info = {
204 .name = "eukrea_mbimx27-bl",
205 .max_intensity = 0xff,
206 .default_intensity = 0xff,
207 .set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
208};
209
210static struct platform_device eukrea_mbimx27_bl_dev = {
211 .name = "generic-bl",
212 .id = 1,
213 .dev = {
214 .platform_data = &eukrea_mbimx27_bl_info,
215 },
216};
217
218static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
219 unsigned int power)
220{
221 if (power)
222 gpio_direction_output(GPIO_PORTA | 25, 1);
223 else
224 gpio_direction_output(GPIO_PORTA | 25, 0);
225}
226
227static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
228 .set_power = eukrea_mbimx27_lcd_power_set,
229};
230
231static struct platform_device eukrea_mbimx27_lcd_powerdev = {
232 .name = "platform-lcd",
233 .dev.platform_data = &eukrea_mbimx27_lcd_power_data,
234};
235
236static const struct imxuart_platform_data uart_pdata __initconst = {
237 .flags = IMXUART_HAVE_RTSCTS,
238};
239
240#define ADS7846_PENDOWN (GPIO_PORTD | 25)
241
242static void __maybe_unused ads7846_dev_init(void)
243{
244 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
245 printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
246 return;
247 }
248 gpio_direction_input(ADS7846_PENDOWN);
249}
250
251static int ads7846_get_pendown_state(void)
252{
253 return !gpio_get_value(ADS7846_PENDOWN);
254}
255
256static struct ads7846_platform_data ads7846_config __initdata = {
257 .get_pendown_state = ads7846_get_pendown_state,
258 .keep_vref_on = 1,
259};
260
261static struct spi_board_info __maybe_unused
262 eukrea_mbimx27_spi_board_info[] __initdata = {
263 [0] = {
264 .modalias = "ads7846",
265 .bus_num = 0,
266 .chip_select = 0,
267 .max_speed_hz = 1500000,
268 /* irq number is run-time assigned */
269 .platform_data = &ads7846_config,
270 .mode = SPI_MODE_2,
271 },
272};
273
274static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
275
276static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
277 .chipselect = eukrea_mbimx27_spi_cs,
278 .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
279};
280
281static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
282 {
283 I2C_BOARD_INFO("tlv320aic23", 0x1a),
284 },
285};
286
287static const struct imxmmc_platform_data sdhc_pdata __initconst = {
288 .dat3_card_detect = 1,
289};
290
291static const
292struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
293 .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
294};
295
296/*
297 * system init for baseboard usage. Will be called by cpuimx27 init.
298 *
299 * Add platform devices present on this baseboard and init
300 * them from CPU side as far as required to use them later on
301 */
302void __init eukrea_mbimx27_baseboard_init(void)
303{
304 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
305 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
306
307 imx27_add_imx_uart1(&uart_pdata);
308 imx27_add_imx_uart2(&uart_pdata);
309#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
310 imx27_add_imx_uart3(&uart_pdata);
311#endif
312
313 imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
314 imx27_add_mxc_mmc(0, &sdhc_pdata);
315
316 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
317 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
318
319 imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
320
321#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
322 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
323 /* ADS7846 Touchscreen controller init */
324 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
325 ads7846_dev_init();
326#endif
327
328 /* SPI_CS0 init */
329 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
330 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
331 eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
332 spi_register_board_info(eukrea_mbimx27_spi_board_info,
333 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
334
335 /* Leds configuration */
336 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
337 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
338 /* Backlight */
339 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
340 gpio_request(GPIO_PORTE | 5, "backlight");
341 platform_device_register(&eukrea_mbimx27_bl_dev);
342 /* LCD Reset */
343 mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
344 gpio_request(GPIO_PORTA | 25, "lcd_enable");
345 platform_device_register(&eukrea_mbimx27_lcd_powerdev);
346
347 imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
348
349 gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
350 imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
351}
diff --git a/arch/arm/mach-imx/imx1-dt.c b/arch/arm/mach-imx/imx1-dt.c
new file mode 100644
index 000000000000..6f915b0961c4
--- /dev/null
+++ b/arch/arm/mach-imx/imx1-dt.c
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/of_platform.h>
11#include <asm/mach/arch.h>
12
13#include "common.h"
14
15static const char * const imx1_dt_board_compat[] __initconst = {
16 "fsl,imx1",
17 NULL
18};
19
20DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
21 .map_io = mx1_map_io,
22 .init_early = imx1_init_early,
23 .init_irq = mx1_init_irq,
24 .dt_compat = imx1_dt_board_compat,
25 .restart = mxc_restart,
26MACHINE_END
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 7c66805d2cc0..1657fe64cd0f 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -64,7 +64,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
64 64
65 return ret; 65 return ret;
66} 66}
67EXPORT_SYMBOL(mxc_iomux_mode);
68 67
69/* 68/*
70 * This function configures the pad value for a IOMUX pin. 69 * This function configures the pad value for a IOMUX pin.
@@ -90,7 +89,6 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
90 89
91 spin_unlock(&gpio_mux_lock); 90 spin_unlock(&gpio_mux_lock);
92} 91}
93EXPORT_SYMBOL(mxc_iomux_set_pad);
94 92
95/* 93/*
96 * allocs a single pin: 94 * allocs a single pin:
@@ -116,7 +114,6 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
116 114
117 return 0; 115 return 0;
118} 116}
119EXPORT_SYMBOL(mxc_iomux_alloc_pin);
120 117
121int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, 118int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
122 const char *label) 119 const char *label)
@@ -137,7 +134,6 @@ setup_error:
137 mxc_iomux_release_multiple_pins(pin_list, i); 134 mxc_iomux_release_multiple_pins(pin_list, i);
138 return ret; 135 return ret;
139} 136}
140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
141 137
142void mxc_iomux_release_pin(unsigned int pin) 138void mxc_iomux_release_pin(unsigned int pin)
143{ 139{
@@ -146,7 +142,6 @@ void mxc_iomux_release_pin(unsigned int pin)
146 if (pad < (PIN_MAX + 1)) 142 if (pad < (PIN_MAX + 1))
147 clear_bit(pad, mxc_pin_alloc_map); 143 clear_bit(pad, mxc_pin_alloc_map);
148} 144}
149EXPORT_SYMBOL(mxc_iomux_release_pin);
150 145
151void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) 146void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
152{ 147{
@@ -158,7 +153,6 @@ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
158 p++; 153 p++;
159 } 154 }
160} 155}
161EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
162 156
163/* 157/*
164 * This function enables/disables the general purpose function for a particular 158 * This function enables/disables the general purpose function for a particular
@@ -178,4 +172,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
178 __raw_writel(l, IOMUXGPR); 172 __raw_writel(l, IOMUXGPR);
179 spin_unlock(&gpio_mux_lock); 173 spin_unlock(&gpio_mux_lock);
180} 174}
181EXPORT_SYMBOL(mxc_iomux_set_gpr);
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index 2b156d1d9e21..ecd543664644 100644
--- a/arch/arm/mach-imx/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -153,7 +153,6 @@ int mxc_gpio_mode(int gpio_mode)
153 153
154 return 0; 154 return 0;
155} 155}
156EXPORT_SYMBOL(mxc_gpio_mode);
157 156
158static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) 157static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
159{ 158{
@@ -178,7 +177,6 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
178 ret = imx_iomuxv1_setup_multiple(pin_list, count); 177 ret = imx_iomuxv1_setup_multiple(pin_list, count);
179 return ret; 178 return ret;
180} 179}
181EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
182 180
183int __init imx_iomuxv1_init(void __iomem *base, int numports) 181int __init imx_iomuxv1_init(void __iomem *base, int numports)
184{ 182{
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 9dae74bf47fc..d61f9606fc56 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -55,7 +55,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
55 55
56 return 0; 56 return 0;
57} 57}
58EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
59 58
60int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) 59int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
61{ 60{
@@ -71,7 +70,6 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
71 } 70 }
72 return 0; 71 return 0;
73} 72}
74EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
75 73
76void mxc_iomux_v3_init(void __iomem *iomux_v3_base) 74void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
77{ 75{
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index a7e9bd26a552..f2060523ba48 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -537,7 +537,7 @@ static void __init armadillo5x0_init(void)
537 gpio_free(ARMADILLO5X0_RTC_GPIO); 537 gpio_free(ARMADILLO5X0_RTC_GPIO);
538 } 538 }
539 if (armadillo5x0_i2c_rtc.irq == 0) 539 if (armadillo5x0_i2c_rtc.irq == 0)
540 pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); 540 pr_warn("armadillo5x0_init: failed to get RTC IRQ\n");
541 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); 541 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
542 542
543 /* USB */ 543 /* USB */
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
deleted file mode 100644
index e6d4b9929571..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm038.c which is :
5 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
6 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/mtd/plat-ram.h>
26#include <linux/mtd/physmap.h>
27#include <linux/platform_device.h>
28#include <linux/serial_8250.h>
29#include <linux/usb/otg.h>
30#include <linux/usb/ulpi.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35#include <asm/mach/map.h>
36
37#include "common.h"
38#include "devices-imx27.h"
39#include "ehci.h"
40#include "eukrea-baseboards.h"
41#include "hardware.h"
42#include "iomux-mx27.h"
43#include "ulpi.h"
44
45static const int eukrea_cpuimx27_pins[] __initconst = {
46 /* UART1 */
47 PE12_PF_UART1_TXD,
48 PE13_PF_UART1_RXD,
49 PE14_PF_UART1_CTS,
50 PE15_PF_UART1_RTS,
51 /* UART4 */
52#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
53 PB26_AF_UART4_RTS,
54 PB28_AF_UART4_TXD,
55 PB29_AF_UART4_CTS,
56 PB31_AF_UART4_RXD,
57#endif
58 /* FEC */
59 PD0_AIN_FEC_TXD0,
60 PD1_AIN_FEC_TXD1,
61 PD2_AIN_FEC_TXD2,
62 PD3_AIN_FEC_TXD3,
63 PD4_AOUT_FEC_RX_ER,
64 PD5_AOUT_FEC_RXD1,
65 PD6_AOUT_FEC_RXD2,
66 PD7_AOUT_FEC_RXD3,
67 PD8_AF_FEC_MDIO,
68 PD9_AIN_FEC_MDC,
69 PD10_AOUT_FEC_CRS,
70 PD11_AOUT_FEC_TX_CLK,
71 PD12_AOUT_FEC_RXD0,
72 PD13_AOUT_FEC_RX_DV,
73 PD14_AOUT_FEC_RX_CLK,
74 PD15_AOUT_FEC_COL,
75 PD16_AIN_FEC_TX_ER,
76 PF23_AIN_FEC_TX_EN,
77 /* I2C1 */
78 PD17_PF_I2C_DATA,
79 PD18_PF_I2C_CLK,
80 /* SDHC2 */
81#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
82 PB4_PF_SD2_D0,
83 PB5_PF_SD2_D1,
84 PB6_PF_SD2_D2,
85 PB7_PF_SD2_D3,
86 PB8_PF_SD2_CMD,
87 PB9_PF_SD2_CLK,
88#endif
89#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
90 /* Quad UART's IRQ */
91 GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
92 GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
93 GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
94 GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
95#endif
96 /* OTG */
97 PC7_PF_USBOTG_DATA5,
98 PC8_PF_USBOTG_DATA6,
99 PC9_PF_USBOTG_DATA0,
100 PC10_PF_USBOTG_DATA2,
101 PC11_PF_USBOTG_DATA1,
102 PC12_PF_USBOTG_DATA4,
103 PC13_PF_USBOTG_DATA3,
104 PE0_PF_USBOTG_NXT,
105 PE1_PF_USBOTG_STP,
106 PE2_PF_USBOTG_DIR,
107 PE24_PF_USBOTG_CLK,
108 PE25_PF_USBOTG_DATA7,
109 /* USBH2 */
110 PA0_PF_USBH2_CLK,
111 PA1_PF_USBH2_DIR,
112 PA2_PF_USBH2_DATA7,
113 PA3_PF_USBH2_NXT,
114 PA4_PF_USBH2_STP,
115 PD19_AF_USBH2_DATA4,
116 PD20_AF_USBH2_DATA3,
117 PD21_AF_USBH2_DATA6,
118 PD22_AF_USBH2_DATA0,
119 PD23_AF_USBH2_DATA2,
120 PD24_AF_USBH2_DATA1,
121 PD26_AF_USBH2_DATA5,
122};
123
124static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
125 .width = 2,
126};
127
128static struct resource eukrea_cpuimx27_flash_resource = {
129 .start = 0xc0000000,
130 .end = 0xc3ffffff,
131 .flags = IORESOURCE_MEM,
132};
133
134static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
135 .name = "physmap-flash",
136 .id = 0,
137 .dev = {
138 .platform_data = &eukrea_cpuimx27_flash_data,
139 },
140 .num_resources = 1,
141 .resource = &eukrea_cpuimx27_flash_resource,
142};
143
144static const struct imxuart_platform_data uart_pdata __initconst = {
145 .flags = IMXUART_HAVE_RTSCTS,
146};
147
148static const struct mxc_nand_platform_data
149cpuimx27_nand_board_info __initconst = {
150 .width = 1,
151 .hw_ecc = 1,
152};
153
154static struct platform_device *platform_devices[] __initdata = {
155 &eukrea_cpuimx27_nor_mtd_device,
156};
157
158static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
159 .bitrate = 100000,
160};
161
162static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
163 {
164 I2C_BOARD_INFO("pcf8563", 0x51),
165 },
166};
167
168#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
169static struct plat_serial8250_port serial_platform_data[] = {
170 {
171 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
172 /* irq number is run-time assigned */
173 .uartclk = 14745600,
174 .regshift = 1,
175 .iotype = UPIO_MEM,
176 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
177 }, {
178 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
179 /* irq number is run-time assigned */
180 .uartclk = 14745600,
181 .regshift = 1,
182 .iotype = UPIO_MEM,
183 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
184 }, {
185 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
186 /* irq number is run-time assigned */
187 .uartclk = 14745600,
188 .regshift = 1,
189 .iotype = UPIO_MEM,
190 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
191 }, {
192 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
193 /* irq number is run-time assigned */
194 .uartclk = 14745600,
195 .regshift = 1,
196 .iotype = UPIO_MEM,
197 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
198 }, {
199 }
200};
201
202static struct platform_device serial_device = {
203 .name = "serial8250",
204 .id = 0,
205 .dev = {
206 .platform_data = serial_platform_data,
207 },
208};
209#endif
210
211static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
212{
213 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
214}
215
216static struct mxc_usbh_platform_data otg_pdata __initdata = {
217 .init = eukrea_cpuimx27_otg_init,
218 .portsc = MXC_EHCI_MODE_ULPI,
219};
220
221static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
222{
223 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
224}
225
226static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
227 .init = eukrea_cpuimx27_usbh2_init,
228 .portsc = MXC_EHCI_MODE_ULPI,
229};
230
231static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
232 .operating_mode = FSL_USB2_DR_DEVICE,
233 .phy_mode = FSL_USB2_PHY_ULPI,
234};
235
236static bool otg_mode_host __initdata;
237
238static int __init eukrea_cpuimx27_otg_mode(char *options)
239{
240 if (!strcmp(options, "host"))
241 otg_mode_host = true;
242 else if (!strcmp(options, "device"))
243 otg_mode_host = false;
244 else
245 pr_info("otg_mode neither \"host\" nor \"device\". "
246 "Defaulting to device\n");
247 return 1;
248}
249__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
250
251static void __init eukrea_cpuimx27_init(void)
252{
253 imx27_soc_init();
254
255 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
256 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
257
258 imx27_add_imx_uart0(&uart_pdata);
259
260 imx27_add_mxc_nand(&cpuimx27_nand_board_info);
261
262 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
263 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
264
265 imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
266
267 imx27_add_fec(NULL);
268 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
269 imx27_add_imx2_wdt();
270 imx27_add_mxc_w1();
271
272#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
273 /* SDHC2 can be used for Wifi */
274 imx27_add_mxc_mmc(1, NULL);
275#endif
276#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
277 /* in which case UART4 is also used for Bluetooth */
278 imx27_add_imx_uart3(&uart_pdata);
279#endif
280
281#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
282 serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
283 serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
284 serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
285 serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
286 platform_device_register(&serial_device);
287#endif
288
289 if (otg_mode_host) {
290 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
291 ULPI_OTG_DRVVBUS_EXT);
292 if (otg_pdata.otg)
293 imx27_add_mxc_ehci_otg(&otg_pdata);
294 } else {
295 imx27_add_fsl_usb2_udc(&otg_device_pdata);
296 }
297
298 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
299 ULPI_OTG_DRVVBUS_EXT);
300 if (usbh2_pdata.otg)
301 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
302
303#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
304 eukrea_mbimx27_baseboard_init();
305#endif
306}
307
308static void __init eukrea_cpuimx27_timer_init(void)
309{
310 mx27_clocks_init(26000000);
311}
312
313MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
314 .atag_offset = 0x100,
315 .map_io = mx27_map_io,
316 .init_early = imx27_init_early,
317 .init_irq = mx27_init_irq,
318 .init_time = eukrea_cpuimx27_timer_init,
319 .init_machine = eukrea_cpuimx27_init,
320 .restart = mxc_restart,
321MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 673a734165ba..3de3b7369aef 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -42,6 +42,9 @@ static void __init imx6sx_init_irq(void)
42static void __init imx6sx_init_late(void) 42static void __init imx6sx_init_late(void)
43{ 43{
44 imx6q_cpuidle_init(); 44 imx6q_cpuidle_init();
45
46 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
47 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
45} 48}
46 49
47static const char * const imx6sx_dt_compat[] __initconst = { 50static const char * const imx6sx_dt_compat[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
deleted file mode 100644
index 77fda3de4290..000000000000
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * arch/arm/mach-imx/mach-mx1ads.c
3 *
4 * Initially based on:
5 * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
6 * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
7 *
8 * 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/i2c.h>
16#include <linux/i2c/pcf857x.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/time.h>
25
26#include "common.h"
27#include "devices-imx1.h"
28#include "hardware.h"
29#include "iomux-mx1.h"
30
31static const int mx1ads_pins[] __initconst = {
32 /* UART1 */
33 PC9_PF_UART1_CTS,
34 PC10_PF_UART1_RTS,
35 PC11_PF_UART1_TXD,
36 PC12_PF_UART1_RXD,
37 /* UART2 */
38 PB28_PF_UART2_CTS,
39 PB29_PF_UART2_RTS,
40 PB30_PF_UART2_TXD,
41 PB31_PF_UART2_RXD,
42 /* I2C */
43 PA15_PF_I2C_SDA,
44 PA16_PF_I2C_SCL,
45 /* SPI */
46 PC13_PF_SPI1_SPI_RDY,
47 PC14_PF_SPI1_SCLK,
48 PC15_PF_SPI1_SS,
49 PC16_PF_SPI1_MISO,
50 PC17_PF_SPI1_MOSI,
51};
52
53/*
54 * UARTs platform data
55 */
56
57static const struct imxuart_platform_data uart0_pdata __initconst = {
58 .flags = IMXUART_HAVE_RTSCTS,
59};
60
61static const struct imxuart_platform_data uart1_pdata __initconst = {
62 .flags = IMXUART_HAVE_RTSCTS,
63};
64
65/*
66 * Physmap flash
67 */
68
69static const struct physmap_flash_data mx1ads_flash_data __initconst = {
70 .width = 4, /* bankwidth in bytes */
71};
72
73static const struct resource flash_resource __initconst = {
74 .start = MX1_CS0_PHYS,
75 .end = MX1_CS0_PHYS + SZ_32M - 1,
76 .flags = IORESOURCE_MEM,
77};
78
79/*
80 * I2C
81 */
82static struct pcf857x_platform_data pcf857x_data[] = {
83 {
84 .gpio_base = 4 * 32,
85 }, {
86 .gpio_base = 4 * 32 + 16,
87 }
88};
89
90static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
91 .bitrate = 100000,
92};
93
94static struct i2c_board_info mx1ads_i2c_devices[] = {
95 {
96 I2C_BOARD_INFO("pcf8575", 0x22),
97 .platform_data = &pcf857x_data[0],
98 }, {
99 I2C_BOARD_INFO("pcf8575", 0x24),
100 .platform_data = &pcf857x_data[1],
101 },
102};
103
104/*
105 * Board init
106 */
107static void __init mx1ads_init(void)
108{
109 imx1_soc_init();
110
111 mxc_gpio_setup_multiple_pins(mx1ads_pins,
112 ARRAY_SIZE(mx1ads_pins), "mx1ads");
113
114 /* UART */
115 imx1_add_imx_uart0(&uart0_pdata);
116 imx1_add_imx_uart1(&uart1_pdata);
117
118 /* Physmap flash */
119 platform_device_register_resndata(NULL, "physmap-flash", 0,
120 &flash_resource, 1,
121 &mx1ads_flash_data, sizeof(mx1ads_flash_data));
122
123 /* I2C */
124 i2c_register_board_info(0, mx1ads_i2c_devices,
125 ARRAY_SIZE(mx1ads_i2c_devices));
126
127 imx1_add_imx_i2c(&mx1ads_i2c_data);
128}
129
130static void __init mx1ads_timer_init(void)
131{
132 mx1_clocks_init(32000);
133}
134
135MACHINE_START(MX1ADS, "Freescale MX1ADS")
136 /* Maintainer: Sascha Hauer, Pengutronix */
137 .atag_offset = 0x100,
138 .map_io = mx1_map_io,
139 .init_early = imx1_init_early,
140 .init_irq = mx1_init_irq,
141 .init_time = mx1ads_timer_init,
142 .init_machine = mx1ads_init,
143 .restart = mxc_restart,
144MACHINE_END
145
146MACHINE_START(MXLADS, "Freescale MXLADS")
147 .atag_offset = 0x100,
148 .map_io = mx1_map_io,
149 .init_early = imx1_init_early,
150 .init_irq = mx1_init_irq,
151 .init_time = mx1ads_timer_init,
152 .init_machine = mx1ads_init,
153 .restart = mxc_restart,
154MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 453f41a2c5a9..65a0dc06a97c 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -307,7 +307,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
307 ret = gpio_request_array(mx31_3ds_sdhc1_gpios, 307 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
308 ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); 308 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
309 if (ret) { 309 if (ret) {
310 pr_warning("Unable to request the SD/MMC GPIOs.\n"); 310 pr_warn("Unable to request the SD/MMC GPIOs.\n");
311 return ret; 311 return ret;
312 } 312 }
313 313
@@ -316,7 +316,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
316 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 316 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
317 "sdhc1-detect", data); 317 "sdhc1-detect", data);
318 if (ret) { 318 if (ret) {
319 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); 319 pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
320 goto gpio_free; 320 goto gpio_free;
321 } 321 }
322 322
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 57eac6f45fab..4822a1738de4 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -270,7 +270,7 @@ static void __init mx31lite_init(void)
270 /* SMSC9117 IRQ pin */ 270 /* SMSC9117 IRQ pin */
271 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); 271 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
272 if (ret) 272 if (ret)
273 pr_warning("could not get LAN irq gpio\n"); 273 pr_warn("could not get LAN irq gpio\n");
274 else { 274 else {
275 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); 275 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
276 smsc911x_resources[1].start = 276 smsc911x_resources[1].start =
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
deleted file mode 100644
index 0b5d1ca31b9f..000000000000
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ /dev/null
@@ -1,273 +0,0 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_device.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/map.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/physmap.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
28#include <linux/gpio.h>
29#include <linux/platform_data/pca953x.h>
30
31#include "common.h"
32#include "devices-imx27.h"
33#include "hardware.h"
34#include "iomux-mx27.h"
35
36static const int mxt_td60_pins[] __initconst = {
37 /* UART0 */
38 PE12_PF_UART1_TXD,
39 PE13_PF_UART1_RXD,
40 PE14_PF_UART1_CTS,
41 PE15_PF_UART1_RTS,
42 /* UART1 */
43 PE3_PF_UART2_CTS,
44 PE4_PF_UART2_RTS,
45 PE6_PF_UART2_TXD,
46 PE7_PF_UART2_RXD,
47 /* UART2 */
48 PE8_PF_UART3_TXD,
49 PE9_PF_UART3_RXD,
50 PE10_PF_UART3_CTS,
51 PE11_PF_UART3_RTS,
52 /* FEC */
53 PD0_AIN_FEC_TXD0,
54 PD1_AIN_FEC_TXD1,
55 PD2_AIN_FEC_TXD2,
56 PD3_AIN_FEC_TXD3,
57 PD4_AOUT_FEC_RX_ER,
58 PD5_AOUT_FEC_RXD1,
59 PD6_AOUT_FEC_RXD2,
60 PD7_AOUT_FEC_RXD3,
61 PD8_AF_FEC_MDIO,
62 PD9_AIN_FEC_MDC,
63 PD10_AOUT_FEC_CRS,
64 PD11_AOUT_FEC_TX_CLK,
65 PD12_AOUT_FEC_RXD0,
66 PD13_AOUT_FEC_RX_DV,
67 PD14_AOUT_FEC_RX_CLK,
68 PD15_AOUT_FEC_COL,
69 PD16_AIN_FEC_TX_ER,
70 PF23_AIN_FEC_TX_EN,
71 /* I2C1 */
72 PD17_PF_I2C_DATA,
73 PD18_PF_I2C_CLK,
74 /* I2C2 */
75 PC5_PF_I2C2_SDA,
76 PC6_PF_I2C2_SCL,
77 /* FB */
78 PA5_PF_LSCLK,
79 PA6_PF_LD0,
80 PA7_PF_LD1,
81 PA8_PF_LD2,
82 PA9_PF_LD3,
83 PA10_PF_LD4,
84 PA11_PF_LD5,
85 PA12_PF_LD6,
86 PA13_PF_LD7,
87 PA14_PF_LD8,
88 PA15_PF_LD9,
89 PA16_PF_LD10,
90 PA17_PF_LD11,
91 PA18_PF_LD12,
92 PA19_PF_LD13,
93 PA20_PF_LD14,
94 PA21_PF_LD15,
95 PA22_PF_LD16,
96 PA23_PF_LD17,
97 PA25_PF_CLS,
98 PA27_PF_SPL_SPR,
99 PA28_PF_HSYNC,
100 PA29_PF_VSYNC,
101 PA30_PF_CONTRAST,
102 PA31_PF_OE_ACD,
103 /* OWIRE */
104 PE16_AF_OWIRE,
105 /* SDHC1*/
106 PE18_PF_SD1_D0,
107 PE19_PF_SD1_D1,
108 PE20_PF_SD1_D2,
109 PE21_PF_SD1_D3,
110 PE22_PF_SD1_CMD,
111 PE23_PF_SD1_CLK,
112 PF8_AF_ATA_IORDY,
113 /* SDHC2*/
114 PB4_PF_SD2_D0,
115 PB5_PF_SD2_D1,
116 PB6_PF_SD2_D2,
117 PB7_PF_SD2_D3,
118 PB8_PF_SD2_CMD,
119 PB9_PF_SD2_CLK,
120};
121
122static const struct mxc_nand_platform_data
123mxt_td60_nand_board_info __initconst = {
124 .width = 1,
125 .hw_ecc = 1,
126};
127
128static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
129 .bitrate = 100000,
130};
131
132/* PCA9557 */
133static int mxt_td60_pca9557_setup(struct i2c_client *client,
134 unsigned gpio_base, unsigned ngpio,
135 void *context)
136{
137 static int mxt_td60_gpio_value[] = {
138 -1, -1, -1, -1, -1, -1, -1, 1
139 };
140 int n;
141
142 for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
143 gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
144 if (mxt_td60_gpio_value[n] < 0)
145 gpio_direction_input(gpio_base + n);
146 else
147 gpio_direction_output(gpio_base + n,
148 mxt_td60_gpio_value[n]);
149 gpio_export(gpio_base + n, 0);
150 }
151
152 return 0;
153}
154
155static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
156 .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */
157 .invert = 0, /* Do not invert */
158 .setup = mxt_td60_pca9557_setup,
159};
160
161static struct i2c_board_info mxt_td60_i2c_devices[] = {
162 {
163 I2C_BOARD_INFO("pca9557", 0x18),
164 .platform_data = &mxt_td60_pca9557_pdata,
165 },
166};
167
168static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
169 .bitrate = 100000,
170};
171
172static struct i2c_board_info mxt_td60_i2c2_devices[] = {
173};
174
175static struct imx_fb_videomode mxt_td60_modes[] = {
176 {
177 .mode = {
178 .name = "Chimei LW700AT9003",
179 .refresh = 60,
180 .xres = 800,
181 .yres = 480,
182 .pixclock = 30303,
183 .hsync_len = 64,
184 .left_margin = 0x67,
185 .right_margin = 0x68,
186 .vsync_len = 16,
187 .upper_margin = 0x0f,
188 .lower_margin = 0x0f,
189 },
190 .bpp = 16,
191 .pcr = 0xFA208B83,
192 },
193};
194
195static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
196 .mode = mxt_td60_modes,
197 .num_modes = ARRAY_SIZE(mxt_td60_modes),
198
199 /*
200 * - HSYNC active high
201 * - VSYNC active high
202 * - clk notenabled while idle
203 * - clock inverted
204 * - data not inverted
205 * - data enable low active
206 * - enable sharp mode
207 */
208 .pwmr = 0x00A903FF,
209 .lscr1 = 0x00120300,
210 .dmacr = 0x00020010,
211};
212
213static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
214 void *data)
215{
216 return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
217 IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
218}
219
220static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
221{
222 free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
223}
224
225static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
226 .init = mxt_td60_sdhc1_init,
227 .exit = mxt_td60_sdhc1_exit,
228};
229
230static const struct imxuart_platform_data uart_pdata __initconst = {
231 .flags = IMXUART_HAVE_RTSCTS,
232};
233
234static void __init mxt_td60_board_init(void)
235{
236 imx27_soc_init();
237
238 mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
239 "MXT_TD60");
240
241 imx27_add_imx_uart0(&uart_pdata);
242 imx27_add_imx_uart1(&uart_pdata);
243 imx27_add_imx_uart2(&uart_pdata);
244 imx27_add_mxc_nand(&mxt_td60_nand_board_info);
245
246 i2c_register_board_info(0, mxt_td60_i2c_devices,
247 ARRAY_SIZE(mxt_td60_i2c_devices));
248
249 i2c_register_board_info(1, mxt_td60_i2c2_devices,
250 ARRAY_SIZE(mxt_td60_i2c2_devices));
251
252 imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
253 imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
254 imx27_add_imx_fb(&mxt_td60_fb_data);
255 imx27_add_mxc_mmc(0, &sdhc1_pdata);
256 imx27_add_fec(NULL);
257}
258
259static void __init mxt_td60_timer_init(void)
260{
261 mx27_clocks_init(26000000);
262}
263
264MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
265 /* maintainer: Maxtrack Industrial */
266 .atag_offset = 0x100,
267 .map_io = mx27_map_io,
268 .init_early = imx27_init_early,
269 .init_irq = mx27_init_irq,
270 .init_time = mxt_td60_timer_init,
271 .init_machine = mxt_td60_board_init,
272 .restart = mxc_restart,
273MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 8eb1570f7851..6d879417db49 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -58,7 +58,7 @@ static int __init pcm037_variant_setup(char *str)
58 if (!strcmp("eet", str)) 58 if (!strcmp("eet", str))
59 pcm037_instance = PCM037_EET; 59 pcm037_instance = PCM037_EET;
60 else if (strcmp("pcm970", str)) 60 else if (strcmp("pcm970", str))
61 pr_warning("Unknown pcm037 baseboard variant %s\n", str); 61 pr_warn("Unknown pcm037 baseboard variant %s\n", str);
62 62
63 return 1; 63 return 1;
64} 64}
@@ -624,7 +624,7 @@ static void __init pcm037_init(void)
624 /* LAN9217 IRQ pin */ 624 /* LAN9217 IRQ pin */
625 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); 625 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
626 if (ret) 626 if (ret)
627 pr_warning("could not get LAN irq gpio\n"); 627 pr_warn("could not get LAN irq gpio\n");
628 else { 628 else {
629 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); 629 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
630 smsc911x_resources[1].start = 630 smsc911x_resources[1].start =
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
deleted file mode 100644
index ee862ad6b6fc..000000000000
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ /dev/null
@@ -1,358 +0,0 @@
1/*
2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/i2c.h>
21#include <linux/platform_data/at24.h>
22#include <linux/io.h>
23#include <linux/mtd/plat-ram.h>
24#include <linux/mtd/physmap.h>
25#include <linux/platform_device.h>
26#include <linux/regulator/machine.h>
27#include <linux/mfd/mc13783.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
30#include <linux/gpio.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35
36#include "board-pcm038.h"
37#include "common.h"
38#include "devices-imx27.h"
39#include "ehci.h"
40#include "hardware.h"
41#include "iomux-mx27.h"
42#include "ulpi.h"
43
44static const int pcm038_pins[] __initconst = {
45 /* UART1 */
46 PE12_PF_UART1_TXD,
47 PE13_PF_UART1_RXD,
48 PE14_PF_UART1_CTS,
49 PE15_PF_UART1_RTS,
50 /* UART2 */
51 PE3_PF_UART2_CTS,
52 PE4_PF_UART2_RTS,
53 PE6_PF_UART2_TXD,
54 PE7_PF_UART2_RXD,
55 /* UART3 */
56 PE8_PF_UART3_TXD,
57 PE9_PF_UART3_RXD,
58 PE10_PF_UART3_CTS,
59 PE11_PF_UART3_RTS,
60 /* FEC */
61 PD0_AIN_FEC_TXD0,
62 PD1_AIN_FEC_TXD1,
63 PD2_AIN_FEC_TXD2,
64 PD3_AIN_FEC_TXD3,
65 PD4_AOUT_FEC_RX_ER,
66 PD5_AOUT_FEC_RXD1,
67 PD6_AOUT_FEC_RXD2,
68 PD7_AOUT_FEC_RXD3,
69 PD8_AF_FEC_MDIO,
70 PD9_AIN_FEC_MDC,
71 PD10_AOUT_FEC_CRS,
72 PD11_AOUT_FEC_TX_CLK,
73 PD12_AOUT_FEC_RXD0,
74 PD13_AOUT_FEC_RX_DV,
75 PD14_AOUT_FEC_RX_CLK,
76 PD15_AOUT_FEC_COL,
77 PD16_AIN_FEC_TX_ER,
78 PF23_AIN_FEC_TX_EN,
79 /* I2C2 */
80 PC5_PF_I2C2_SDA,
81 PC6_PF_I2C2_SCL,
82 /* SPI1 */
83 PD25_PF_CSPI1_RDY,
84 PD29_PF_CSPI1_SCLK,
85 PD30_PF_CSPI1_MISO,
86 PD31_PF_CSPI1_MOSI,
87 /* SSI1 */
88 PC20_PF_SSI1_FS,
89 PC21_PF_SSI1_RXD,
90 PC22_PF_SSI1_TXD,
91 PC23_PF_SSI1_CLK,
92 /* SSI4 */
93 PC16_PF_SSI4_FS,
94 PC17_PF_SSI4_RXD,
95 PC18_PF_SSI4_TXD,
96 PC19_PF_SSI4_CLK,
97 /* USB host */
98 PA0_PF_USBH2_CLK,
99 PA1_PF_USBH2_DIR,
100 PA2_PF_USBH2_DATA7,
101 PA3_PF_USBH2_NXT,
102 PA4_PF_USBH2_STP,
103 PD19_AF_USBH2_DATA4,
104 PD20_AF_USBH2_DATA3,
105 PD21_AF_USBH2_DATA6,
106 PD22_AF_USBH2_DATA0,
107 PD23_AF_USBH2_DATA2,
108 PD24_AF_USBH2_DATA1,
109 PD26_AF_USBH2_DATA5,
110};
111
112/*
113 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
114 * 16 bit width
115 */
116
117static struct platdata_mtd_ram pcm038_sram_data = {
118 .bankwidth = 2,
119};
120
121static struct resource pcm038_sram_resource = {
122 .start = MX27_CS1_BASE_ADDR,
123 .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
124 .flags = IORESOURCE_MEM,
125};
126
127static struct platform_device pcm038_sram_mtd_device = {
128 .name = "mtd-ram",
129 .id = 0,
130 .dev = {
131 .platform_data = &pcm038_sram_data,
132 },
133 .num_resources = 1,
134 .resource = &pcm038_sram_resource,
135};
136
137/*
138 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
139 * 16 bit width
140 */
141static struct physmap_flash_data pcm038_flash_data = {
142 .width = 2,
143};
144
145static struct resource pcm038_flash_resource = {
146 .start = 0xc0000000,
147 .end = 0xc1ffffff,
148 .flags = IORESOURCE_MEM,
149};
150
151static struct platform_device pcm038_nor_mtd_device = {
152 .name = "physmap-flash",
153 .id = 0,
154 .dev = {
155 .platform_data = &pcm038_flash_data,
156 },
157 .num_resources = 1,
158 .resource = &pcm038_flash_resource,
159};
160
161static const struct imxuart_platform_data uart_pdata __initconst = {
162 .flags = IMXUART_HAVE_RTSCTS,
163};
164
165static const struct mxc_nand_platform_data
166pcm038_nand_board_info __initconst = {
167 .width = 1,
168 .hw_ecc = 1,
169};
170
171static struct platform_device *platform_devices[] __initdata = {
172 &pcm038_nor_mtd_device,
173 &pcm038_sram_mtd_device,
174};
175
176/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
177 * setup other stuffs to access the sram. */
178static void __init pcm038_init_sram(void)
179{
180 __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1)));
181 __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1)));
182 __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1)));
183}
184
185static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
186 .bitrate = 100000,
187};
188
189static struct at24_platform_data board_eeprom = {
190 .byte_len = 4096,
191 .page_size = 32,
192 .flags = AT24_FLAG_ADDR16,
193};
194
195static struct i2c_board_info pcm038_i2c_devices[] = {
196 {
197 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
198 .platform_data = &board_eeprom,
199 }, {
200 I2C_BOARD_INFO("pcf8563", 0x51),
201 }, {
202 I2C_BOARD_INFO("lm75", 0x4a),
203 }
204};
205
206static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
207
208static const struct spi_imx_master pcm038_spi0_data __initconst = {
209 .chipselect = pcm038_spi_cs,
210 .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
211};
212
213static struct regulator_consumer_supply sdhc1_consumers[] = {
214 {
215 .dev_name = "imx21-mmc.1",
216 .supply = "sdhc_vcc",
217 },
218};
219
220static struct regulator_init_data sdhc1_data = {
221 .constraints = {
222 .min_uV = 3000000,
223 .max_uV = 3400000,
224 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
225 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
226 .valid_modes_mask = REGULATOR_MODE_NORMAL |
227 REGULATOR_MODE_FAST,
228 .always_on = 0,
229 .boot_on = 0,
230 },
231 .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers),
232 .consumer_supplies = sdhc1_consumers,
233};
234
235static struct regulator_consumer_supply cam_consumers[] = {
236 {
237 .dev_name = NULL,
238 .supply = "imx_cam_vcc",
239 },
240};
241
242static struct regulator_init_data cam_data = {
243 .constraints = {
244 .min_uV = 3000000,
245 .max_uV = 3400000,
246 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
247 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
248 .valid_modes_mask = REGULATOR_MODE_NORMAL |
249 REGULATOR_MODE_FAST,
250 .always_on = 0,
251 .boot_on = 0,
252 },
253 .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
254 .consumer_supplies = cam_consumers,
255};
256
257static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
258 {
259 .id = MC13783_REG_VCAM,
260 .init_data = &cam_data,
261 }, {
262 .id = MC13783_REG_VMMC1,
263 .init_data = &sdhc1_data,
264 },
265};
266
267static struct mc13xxx_platform_data pcm038_pmic = {
268 .regulators = {
269 .regulators = pcm038_regulators,
270 .num_regulators = ARRAY_SIZE(pcm038_regulators),
271 },
272 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
273};
274
275static struct spi_board_info pcm038_spi_board_info[] __initdata = {
276 {
277 .modalias = "mc13783",
278 /* irq number is run-time assigned */
279 .max_speed_hz = 300000,
280 .bus_num = 0,
281 .chip_select = 0,
282 .platform_data = &pcm038_pmic,
283 .mode = SPI_CS_HIGH,
284 }
285};
286
287static int pcm038_usbh2_init(struct platform_device *pdev)
288{
289 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
290 MXC_EHCI_INTERFACE_DIFF_UNI);
291}
292
293static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
294 .init = pcm038_usbh2_init,
295 .portsc = MXC_EHCI_MODE_ULPI,
296};
297
298static void __init pcm038_init(void)
299{
300 imx27_soc_init();
301
302 mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
303 "PCM038");
304
305 pcm038_init_sram();
306
307 imx27_add_imx_uart0(&uart_pdata);
308 imx27_add_imx_uart1(&uart_pdata);
309 imx27_add_imx_uart2(&uart_pdata);
310
311 mxc_gpio_mode(PE16_AF_OWIRE);
312 imx27_add_mxc_nand(&pcm038_nand_board_info);
313
314 /* only the i2c master 1 is used on this CPU card */
315 i2c_register_board_info(1, pcm038_i2c_devices,
316 ARRAY_SIZE(pcm038_i2c_devices));
317
318 imx27_add_imx_i2c(1, &pcm038_i2c1_data);
319
320 /* PE18 for user-LED D40 */
321 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
322
323 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
324
325 /* MC13783 IRQ */
326 mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
327
328 imx27_add_spi_imx0(&pcm038_spi0_data);
329 pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
330 spi_register_board_info(pcm038_spi_board_info,
331 ARRAY_SIZE(pcm038_spi_board_info));
332
333 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
334
335 imx27_add_fec(NULL);
336 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
337 imx27_add_imx2_wdt();
338 imx27_add_mxc_w1();
339
340#ifdef CONFIG_MACH_PCM970_BASEBOARD
341 pcm970_baseboard_init();
342#endif
343}
344
345static void __init pcm038_timer_init(void)
346{
347 mx27_clocks_init(26000000);
348}
349
350MACHINE_START(PCM038, "phyCORE-i.MX27")
351 .atag_offset = 0x100,
352 .map_io = mx27_map_io,
353 .init_early = imx27_init_early,
354 .init_irq = mx27_init_irq,
355 .init_time = pcm038_timer_init,
356 .init_machine = pcm038_init,
357 .restart = mxc_restart,
358MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index a39b69ef4301..17a41ca65acf 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -43,6 +43,8 @@
43#define IMX_CHIP_REVISION_1_1 0x11 43#define IMX_CHIP_REVISION_1_1 0x11
44#define IMX_CHIP_REVISION_1_2 0x12 44#define IMX_CHIP_REVISION_1_2 0x12
45#define IMX_CHIP_REVISION_1_3 0x13 45#define IMX_CHIP_REVISION_1_3 0x13
46#define IMX_CHIP_REVISION_1_4 0x14
47#define IMX_CHIP_REVISION_1_5 0x15
46#define IMX_CHIP_REVISION_2_0 0x20 48#define IMX_CHIP_REVISION_2_0 0x20
47#define IMX_CHIP_REVISION_2_1 0x21 49#define IMX_CHIP_REVISION_2_1 0x21
48#define IMX_CHIP_REVISION_2_2 0x22 50#define IMX_CHIP_REVISION_2_2 0x22
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
deleted file mode 100644
index 51c608234089..000000000000
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/gpio.h>
20#include <linux/irq.h>
21#include <linux/platform_device.h>
22#include <linux/can/platform/sja1000.h>
23
24#include <asm/mach/arch.h>
25
26#include "common.h"
27#include "devices-imx27.h"
28#include "hardware.h"
29#include "iomux-mx27.h"
30
31static const int pcm970_pins[] __initconst = {
32 /* SDHC */
33 PB4_PF_SD2_D0,
34 PB5_PF_SD2_D1,
35 PB6_PF_SD2_D2,
36 PB7_PF_SD2_D3,
37 PB8_PF_SD2_CMD,
38 PB9_PF_SD2_CLK,
39 /* display */
40 PA5_PF_LSCLK,
41 PA6_PF_LD0,
42 PA7_PF_LD1,
43 PA8_PF_LD2,
44 PA9_PF_LD3,
45 PA10_PF_LD4,
46 PA11_PF_LD5,
47 PA12_PF_LD6,
48 PA13_PF_LD7,
49 PA14_PF_LD8,
50 PA15_PF_LD9,
51 PA16_PF_LD10,
52 PA17_PF_LD11,
53 PA18_PF_LD12,
54 PA19_PF_LD13,
55 PA20_PF_LD14,
56 PA21_PF_LD15,
57 PA22_PF_LD16,
58 PA23_PF_LD17,
59 PA24_PF_REV,
60 PA25_PF_CLS,
61 PA26_PF_PS,
62 PA27_PF_SPL_SPR,
63 PA28_PF_HSYNC,
64 PA29_PF_VSYNC,
65 PA30_PF_CONTRAST,
66 PA31_PF_OE_ACD,
67 /*
68 * it seems the data line misses a pullup, so we must enable
69 * the internal pullup as a local workaround
70 */
71 PD17_PF_I2C_DATA | GPIO_PUEN,
72 PD18_PF_I2C_CLK,
73 /* Camera */
74 PB10_PF_CSI_D0,
75 PB11_PF_CSI_D1,
76 PB12_PF_CSI_D2,
77 PB13_PF_CSI_D3,
78 PB14_PF_CSI_D4,
79 PB15_PF_CSI_MCLK,
80 PB16_PF_CSI_PIXCLK,
81 PB17_PF_CSI_D5,
82 PB18_PF_CSI_D6,
83 PB19_PF_CSI_D7,
84 PB20_PF_CSI_VSYNC,
85 PB21_PF_CSI_HSYNC,
86};
87
88static int pcm970_sdhc2_get_ro(struct device *dev)
89{
90 return gpio_get_value(GPIO_PORTC + 28);
91}
92
93static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
94{
95 int ret;
96
97 ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
98 IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
99 if (ret)
100 return ret;
101
102 ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
103 if (ret) {
104 free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
105 return ret;
106 }
107
108 gpio_direction_input(GPIO_PORTC + 28);
109
110 return 0;
111}
112
113static void pcm970_sdhc2_exit(struct device *dev, void *data)
114{
115 free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
116 gpio_free(GPIO_PORTC + 28);
117}
118
119static const struct imxmmc_platform_data sdhc_pdata __initconst = {
120 .get_ro = pcm970_sdhc2_get_ro,
121 .init = pcm970_sdhc2_init,
122 .exit = pcm970_sdhc2_exit,
123};
124
125static struct imx_fb_videomode pcm970_modes[] = {
126 {
127 .mode = {
128 .name = "Sharp-LQ035Q7",
129 .refresh = 60,
130 .xres = 240,
131 .yres = 320,
132 .pixclock = 188679, /* in ps (5.3MHz) */
133 .hsync_len = 7,
134 .left_margin = 5,
135 .right_margin = 16,
136 .vsync_len = 1,
137 .upper_margin = 7,
138 .lower_margin = 9,
139 },
140 /*
141 * - HSYNC active high
142 * - VSYNC active high
143 * - clk notenabled while idle
144 * - clock not inverted
145 * - data not inverted
146 * - data enable low active
147 * - enable sharp mode
148 */
149 .pcr = 0xF00080C0,
150 .bpp = 16,
151 }, {
152 .mode = {
153 .name = "TX090",
154 .refresh = 60,
155 .xres = 240,
156 .yres = 320,
157 .pixclock = 38255,
158 .left_margin = 144,
159 .right_margin = 0,
160 .upper_margin = 7,
161 .lower_margin = 40,
162 .hsync_len = 96,
163 .vsync_len = 1,
164 },
165 /*
166 * - HSYNC active low (1 << 22)
167 * - VSYNC active low (1 << 23)
168 * - clk notenabled while idle
169 * - clock not inverted
170 * - data not inverted
171 * - data enable low active
172 * - enable sharp mode
173 */
174 .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
175 .bpp = 32,
176 },
177};
178
179static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
180 .mode = pcm970_modes,
181 .num_modes = ARRAY_SIZE(pcm970_modes),
182
183 .pwmr = 0x00A903FF,
184 .lscr1 = 0x00120300,
185 .dmacr = 0x00020010,
186};
187
188static struct resource pcm970_sja1000_resources[] = {
189 {
190 .start = MX27_CS4_BASE_ADDR,
191 .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
192 .flags = IORESOURCE_MEM,
193 }, {
194 /* irq number is run-time assigned */
195 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
196 },
197};
198
199static struct sja1000_platform_data pcm970_sja1000_platform_data = {
200 .osc_freq = 16000000,
201 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
202 .cdr = CDR_CBP,
203};
204
205static struct platform_device pcm970_sja1000 = {
206 .name = "sja1000_platform",
207 .dev = {
208 .platform_data = &pcm970_sja1000_platform_data,
209 },
210 .resource = pcm970_sja1000_resources,
211 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
212};
213
214/*
215 * system init for baseboard usage. Will be called by pcm038 init.
216 *
217 * Add platform devices present on this baseboard and init
218 * them from CPU side as far as required to use them later on
219 */
220void __init pcm970_baseboard_init(void)
221{
222 mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
223 "PCM970");
224
225 imx27_add_imx_fb(&pcm038_fb_data);
226 mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
227 imx27_add_mxc_mmc(1, &sdhc_pdata);
228 pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
229 pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
230 platform_device_register(&pcm970_sja1000);
231}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 5b57c17c06bd..771bd25c1025 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -20,8 +20,6 @@
20#include "common.h" 20#include "common.h"
21#include "hardware.h" 21#include "hardware.h"
22 22
23#define SCU_STANDBY_ENABLE (1 << 5)
24
25u32 g_diag_reg; 23u32 g_diag_reg;
26static void __iomem *scu_base; 24static void __iomem *scu_base;
27 25
@@ -45,14 +43,6 @@ void __init imx_scu_map_io(void)
45 scu_base = IMX_IO_ADDRESS(base); 43 scu_base = IMX_IO_ADDRESS(base);
46} 44}
47 45
48void imx_scu_standby_enable(void)
49{
50 u32 val = readl_relaxed(scu_base);
51
52 val |= SCU_STANDBY_ENABLE;
53 writel_relaxed(val, scu_base);
54}
55
56static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) 46static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
57{ 47{
58 imx_set_cpu_jump(cpu, v7_secondary_startup); 48 imx_set_cpu_jump(cpu, v7_secondary_startup);
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bf92e5a351c0..15d18e198303 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -60,17 +60,22 @@
60#define MX2_TSTAT_CAPT (1 << 1) 60#define MX2_TSTAT_CAPT (1 << 1)
61#define MX2_TSTAT_COMP (1 << 0) 61#define MX2_TSTAT_COMP (1 << 0)
62 62
63/* MX31, MX35, MX25, MX5 */ 63/* MX31, MX35, MX25, MX5, MX6 */
64#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 64#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
65#define V2_TCTL_CLK_IPG (1 << 6) 65#define V2_TCTL_CLK_IPG (1 << 6)
66#define V2_TCTL_CLK_PER (2 << 6) 66#define V2_TCTL_CLK_PER (2 << 6)
67#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
67#define V2_TCTL_FRR (1 << 9) 68#define V2_TCTL_FRR (1 << 9)
69#define V2_TCTL_24MEN (1 << 10)
70#define V2_TPRER_PRE24M 12
68#define V2_IR 0x0c 71#define V2_IR 0x0c
69#define V2_TSTAT 0x08 72#define V2_TSTAT 0x08
70#define V2_TSTAT_OF1 (1 << 0) 73#define V2_TSTAT_OF1 (1 << 0)
71#define V2_TCN 0x24 74#define V2_TCN 0x24
72#define V2_TCMP 0x10 75#define V2_TCMP 0x10
73 76
77#define V2_TIMER_RATE_OSC_DIV8 3000000
78
74#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) 79#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
75#define timer_is_v2() (!timer_is_v1()) 80#define timer_is_v2() (!timer_is_v1())
76 81
@@ -312,10 +317,22 @@ static void __init _mxc_timer_init(int irq,
312 __raw_writel(0, timer_base + MXC_TCTL); 317 __raw_writel(0, timer_base + MXC_TCTL);
313 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 318 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
314 319
315 if (timer_is_v2()) 320 if (timer_is_v2()) {
316 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; 321 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
317 else 322 if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) {
323 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
324 if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
325 /* 24 / 8 = 3 MHz */
326 __raw_writel(7 << V2_TPRER_PRE24M,
327 timer_base + MXC_TPRER);
328 tctl_val |= V2_TCTL_24MEN;
329 }
330 } else {
331 tctl_val |= V2_TCTL_CLK_PER;
332 }
333 } else {
318 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 334 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
335 }
319 336
320 __raw_writel(tctl_val, timer_base + MXC_TCTL); 337 __raw_writel(tctl_val, timer_base + MXC_TCTL);
321 338
@@ -349,9 +366,13 @@ static void __init mxc_timer_init_dt(struct device_node *np)
349 WARN_ON(!timer_base); 366 WARN_ON(!timer_base);
350 irq = irq_of_parse_and_map(np, 0); 367 irq = irq_of_parse_and_map(np, 0);
351 368
352 clk_per = of_clk_get_by_name(np, "per");
353 clk_ipg = of_clk_get_by_name(np, "ipg"); 369 clk_ipg = of_clk_get_by_name(np, "ipg");
354 370
371 /* Try osc_per first, and fall back to per otherwise */
372 clk_per = of_clk_get_by_name(np, "osc_per");
373 if (IS_ERR(clk_per))
374 clk_per = of_clk_get_by_name(np, "per");
375
355 _mxc_timer_init(irq, clk_per, clk_ipg); 376 _mxc_timer_init(irq, clk_per, clk_ipg);
356} 377}
357CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); 378CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 23:03:17 -0500