[Blackfin] arch: Add a note describing what is going on - no functional changes

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>

1 files changed, 13 insertions, 2 deletions

diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S
index 6f909cbfac7b..faca1ab344d2 100644
--- a/arch/blackfin/mach-common/cplbmgr.S
+++ b/arch/blackfin/mach-common/cplbmgr.S
@@ -75,6 +75,15 @@ ENTRY(_cplb_mgr)
         * from the configuration table.
         */
 
+        /* A multi-word instruction can cross a page boundary. This means the
+         * first part of the instruction can be in a valid page, but the
+         * second part is not, and hence generates the instruction miss.
+         * However, the fault address is for the start of the instruction,
+         * not the part that's in the bad page. Therefore, we have to check
+         * whether the fault address applies to a page that is already present
+         * in the table.
+         */
+
         P4.L = LO(ICPLB_FAULT_ADDR);
         P4.H = HI(ICPLB_FAULT_ADDR);
 
@@ -87,7 +96,7 @@ ENTRY(_cplb_mgr)
         R4 = [P4];              /* Get faulting address*/
         R6 = 64;                /* Advance past the fault address, which*/
         R6 = R6 + R4;           /* we'll use if we find a match*/
-        R3 = ((16 << 8) | 2);   /* Extract mask, bits 16 and 17.*/
+        R3 = ((16 << 8) | 2);   /* Extract mask, two bits at posn 16 */
 
         R5 = 0;
 .Lisearch:
@@ -125,7 +134,9 @@ ENTRY(_cplb_mgr)
         P4.L = LO(IMEM_CONTROL);
         P4.H = HI(IMEM_CONTROL);
 
-        /* disable cplbs */
+        /* Turn off CPLBs while we work, necessary according to HRM before
+         * modifying CPLB descriptors
+         */
         R5 = [P4];              /* Control Register*/
         BITCLR(R5,ENICPLB_P);
         CLI R1;