diff options
author | Marcelo Tosatti <marcelo.tosatti@cyclades.com> | 2005-10-28 20:46:10 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-10-28 23:55:27 -0400 |
commit | e37b0c9670fed2264661ade1beb5c228dec29c96 (patch) | |
tree | 4f23bc5ea578db11de39222aa046804ed9286782 /arch | |
parent | 9e3699ea7b8d63eabde7fefa9892e3a258c9c27d (diff) |
[PATCH] ppc32 8xx: use io accessor macros instead of direct memory reference
Convert core 8xx drivers to use in_xxxbe/in_xxx macros instead of direct
memory references.
Other than making IO accesses explicit (which is a plus for readability), a
common set of macros provides a unified place for the volatile flag to
constraint compiler code reordering.
There are several unlucky places at the moment which lack the volatile
flag.
Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/ppc/8xx_io/commproc.c | 20 | ||||
-rw-r--r-- | arch/ppc/syslib/m8xx_setup.c | 45 | ||||
-rw-r--r-- | arch/ppc/syslib/m8xx_wdt.c | 14 | ||||
-rw-r--r-- | arch/ppc/syslib/ppc8xx_pic.c | 17 |
4 files changed, 44 insertions, 52 deletions
diff --git a/arch/ppc/8xx_io/commproc.c b/arch/ppc/8xx_io/commproc.c index 11726e2a4ec8..b42789f8eb76 100644 --- a/arch/ppc/8xx_io/commproc.c +++ b/arch/ppc/8xx_io/commproc.c | |||
@@ -73,7 +73,7 @@ cpm_mask_irq(unsigned int irq) | |||
73 | { | 73 | { |
74 | int cpm_vec = irq - CPM_IRQ_OFFSET; | 74 | int cpm_vec = irq - CPM_IRQ_OFFSET; |
75 | 75 | ||
76 | ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_vec); | 76 | out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) & ~(1 << cpm_vec)); |
77 | } | 77 | } |
78 | 78 | ||
79 | static void | 79 | static void |
@@ -81,7 +81,7 @@ cpm_unmask_irq(unsigned int irq) | |||
81 | { | 81 | { |
82 | int cpm_vec = irq - CPM_IRQ_OFFSET; | 82 | int cpm_vec = irq - CPM_IRQ_OFFSET; |
83 | 83 | ||
84 | ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << cpm_vec); | 84 | out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) | (1 << cpm_vec)); |
85 | } | 85 | } |
86 | 86 | ||
87 | static void | 87 | static void |
@@ -95,7 +95,7 @@ cpm_eoi(unsigned int irq) | |||
95 | { | 95 | { |
96 | int cpm_vec = irq - CPM_IRQ_OFFSET; | 96 | int cpm_vec = irq - CPM_IRQ_OFFSET; |
97 | 97 | ||
98 | ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << cpm_vec); | 98 | out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr, (1 << cpm_vec)); |
99 | } | 99 | } |
100 | 100 | ||
101 | struct hw_interrupt_type cpm_pic = { | 101 | struct hw_interrupt_type cpm_pic = { |
@@ -133,7 +133,7 @@ m8xx_cpm_reset(void) | |||
133 | * manual recommends it. | 133 | * manual recommends it. |
134 | * Bit 25, FAM can also be set to use FEC aggressive mode (860T). | 134 | * Bit 25, FAM can also be set to use FEC aggressive mode (860T). |
135 | */ | 135 | */ |
136 | imp->im_siu_conf.sc_sdcr = 1; | 136 | out_be32(&imp->im_siu_conf.sc_sdcr, 1), |
137 | 137 | ||
138 | /* Reclaim the DP memory for our use. */ | 138 | /* Reclaim the DP memory for our use. */ |
139 | m8xx_cpm_dpinit(); | 139 | m8xx_cpm_dpinit(); |
@@ -178,10 +178,10 @@ cpm_interrupt_init(void) | |||
178 | 178 | ||
179 | /* Initialize the CPM interrupt controller. | 179 | /* Initialize the CPM interrupt controller. |
180 | */ | 180 | */ |
181 | ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr = | 181 | out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, |
182 | (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | | 182 | (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | |
183 | ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK; | 183 | ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK); |
184 | ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0; | 184 | out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, 0); |
185 | 185 | ||
186 | /* install the CPM interrupt controller routines for the CPM | 186 | /* install the CPM interrupt controller routines for the CPM |
187 | * interrupt vectors | 187 | * interrupt vectors |
@@ -198,7 +198,7 @@ cpm_interrupt_init(void) | |||
198 | if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction)) | 198 | if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction)) |
199 | panic("Could not allocate CPM error IRQ!"); | 199 | panic("Could not allocate CPM error IRQ!"); |
200 | 200 | ||
201 | ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; | 201 | out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr) | CICR_IEN); |
202 | } | 202 | } |
203 | 203 | ||
204 | /* | 204 | /* |
@@ -212,8 +212,8 @@ cpm_get_irq(struct pt_regs *regs) | |||
212 | /* Get the vector by setting the ACK bit and then reading | 212 | /* Get the vector by setting the ACK bit and then reading |
213 | * the register. | 213 | * the register. |
214 | */ | 214 | */ |
215 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1; | 215 | out_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr, 1); |
216 | cpm_vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr; | 216 | cpm_vec = in_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr); |
217 | cpm_vec >>= 11; | 217 | cpm_vec >>= 11; |
218 | 218 | ||
219 | return cpm_vec; | 219 | return cpm_vec; |
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c index c88e2d4dceb7..a192719929d3 100644 --- a/arch/ppc/syslib/m8xx_setup.c +++ b/arch/ppc/syslib/m8xx_setup.c | |||
@@ -144,12 +144,12 @@ void __init m8xx_calibrate_decr(void) | |||
144 | int freq, fp, divisor; | 144 | int freq, fp, divisor; |
145 | 145 | ||
146 | /* Unlock the SCCR. */ | 146 | /* Unlock the SCCR. */ |
147 | ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = ~KAPWR_KEY; | 147 | out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY); |
148 | ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = KAPWR_KEY; | 148 | out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY); |
149 | 149 | ||
150 | /* Force all 8xx processors to use divide by 16 processor clock. */ | 150 | /* Force all 8xx processors to use divide by 16 processor clock. */ |
151 | ((volatile immap_t *)IMAP_ADDR)->im_clkrst.car_sccr |= 0x02000000; | 151 | out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, |
152 | 152 | in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr)|0x02000000); | |
153 | /* Processor frequency is MHz. | 153 | /* Processor frequency is MHz. |
154 | * The value 'fp' is the number of decrementer ticks per second. | 154 | * The value 'fp' is the number of decrementer ticks per second. |
155 | */ | 155 | */ |
@@ -175,28 +175,24 @@ void __init m8xx_calibrate_decr(void) | |||
175 | * we guarantee the registers are locked, then we unlock them | 175 | * we guarantee the registers are locked, then we unlock them |
176 | * for our use. | 176 | * for our use. |
177 | */ | 177 | */ |
178 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = ~KAPWR_KEY; | 178 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY); |
179 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = ~KAPWR_KEY; | 179 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY); |
180 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk = ~KAPWR_KEY; | 180 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY); |
181 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = KAPWR_KEY; | 181 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY); |
182 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = KAPWR_KEY; | 182 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY); |
183 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk = KAPWR_KEY; | 183 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY); |
184 | 184 | ||
185 | /* Disable the RTC one second and alarm interrupts. */ | 185 | /* Disable the RTC one second and alarm interrupts. */ |
186 | ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc &= | 186 | out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE)); |
187 | ~(RTCSC_SIE | RTCSC_ALE); | ||
188 | /* Enable the RTC */ | 187 | /* Enable the RTC */ |
189 | ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc |= | 188 | out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE)); |
190 | (RTCSC_RTF | RTCSC_RTE); | ||
191 | 189 | ||
192 | /* Enabling the decrementer also enables the timebase interrupts | 190 | /* Enabling the decrementer also enables the timebase interrupts |
193 | * (or from the other point of view, to get decrementer interrupts | 191 | * (or from the other point of view, to get decrementer interrupts |
194 | * we have to enable the timebase). The decrementer interrupt | 192 | * we have to enable the timebase). The decrementer interrupt |
195 | * is wired into the vector table, nothing to do here for that. | 193 | * is wired into the vector table, nothing to do here for that. |
196 | */ | 194 | */ |
197 | ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_tbscr = | 195 | out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE)); |
198 | ((mk_int_int_mask(DEC_INTERRUPT) << 8) | | ||
199 | (TBSCR_TBF | TBSCR_TBE)); | ||
200 | 196 | ||
201 | if (setup_irq(DEC_INTERRUPT, &tbint_irqaction)) | 197 | if (setup_irq(DEC_INTERRUPT, &tbint_irqaction)) |
202 | panic("Could not allocate timer IRQ!"); | 198 | panic("Could not allocate timer IRQ!"); |
@@ -216,9 +212,9 @@ void __init m8xx_calibrate_decr(void) | |||
216 | static int | 212 | static int |
217 | m8xx_set_rtc_time(unsigned long time) | 213 | m8xx_set_rtc_time(unsigned long time) |
218 | { | 214 | { |
219 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = KAPWR_KEY; | 215 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY); |
220 | ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtc = time; | 216 | out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time); |
221 | ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = ~KAPWR_KEY; | 217 | out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY); |
222 | return(0); | 218 | return(0); |
223 | } | 219 | } |
224 | 220 | ||
@@ -226,7 +222,7 @@ static unsigned long | |||
226 | m8xx_get_rtc_time(void) | 222 | m8xx_get_rtc_time(void) |
227 | { | 223 | { |
228 | /* Get time from the RTC. */ | 224 | /* Get time from the RTC. */ |
229 | return((unsigned long)(((immap_t *)IMAP_ADDR)->im_sit.sit_rtc)); | 225 | return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc); |
230 | } | 226 | } |
231 | 227 | ||
232 | static void | 228 | static void |
@@ -235,13 +231,13 @@ m8xx_restart(char *cmd) | |||
235 | __volatile__ unsigned char dummy; | 231 | __volatile__ unsigned char dummy; |
236 | 232 | ||
237 | local_irq_disable(); | 233 | local_irq_disable(); |
238 | ((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr |= 0x00000080; | 234 | out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr) | 0x00000080); |
239 | 235 | ||
240 | /* Clear the ME bit in MSR to cause checkstop on machine check | 236 | /* Clear the ME bit in MSR to cause checkstop on machine check |
241 | */ | 237 | */ |
242 | mtmsr(mfmsr() & ~0x1000); | 238 | mtmsr(mfmsr() & ~0x1000); |
243 | 239 | ||
244 | dummy = ((immap_t *)IMAP_ADDR)->im_clkrst.res[0]; | 240 | dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]); |
245 | printk("Restart failed\n"); | 241 | printk("Restart failed\n"); |
246 | while(1); | 242 | while(1); |
247 | } | 243 | } |
@@ -306,8 +302,7 @@ m8xx_init_IRQ(void) | |||
306 | i8259_init(0); | 302 | i8259_init(0); |
307 | 303 | ||
308 | /* The i8259 cascade interrupt must be level sensitive. */ | 304 | /* The i8259 cascade interrupt must be level sensitive. */ |
309 | ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel &= | 305 | out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel & ~(0x80000000 >> ISA_BRIDGE_INT))); |
310 | ~(0x80000000 >> ISA_BRIDGE_INT); | ||
311 | 306 | ||
312 | if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction)) | 307 | if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction)) |
313 | enable_irq(ISA_BRIDGE_INT); | 308 | enable_irq(ISA_BRIDGE_INT); |
diff --git a/arch/ppc/syslib/m8xx_wdt.c b/arch/ppc/syslib/m8xx_wdt.c index 2ddc857e7fc7..c5ac5ce5d7d2 100644 --- a/arch/ppc/syslib/m8xx_wdt.c +++ b/arch/ppc/syslib/m8xx_wdt.c | |||
@@ -29,8 +29,8 @@ void m8xx_wdt_reset(void) | |||
29 | { | 29 | { |
30 | volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR; | 30 | volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR; |
31 | 31 | ||
32 | imap->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ | 32 | out_be16(imap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */ |
33 | imap->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ | 33 | out_be16(imap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ |
34 | } | 34 | } |
35 | 35 | ||
36 | static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs) | 36 | static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs) |
@@ -39,7 +39,7 @@ static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs) | |||
39 | 39 | ||
40 | m8xx_wdt_reset(); | 40 | m8xx_wdt_reset(); |
41 | 41 | ||
42 | imap->im_sit.sit_piscr |= PISCR_PS; /* clear irq */ | 42 | out_be16(imap->im_sit.sit_piscr, in_be16(imap->im_sit.sit_piscr | PISCR_PS)); /* clear irq */ |
43 | 43 | ||
44 | return IRQ_HANDLED; | 44 | return IRQ_HANDLED; |
45 | } | 45 | } |
@@ -51,7 +51,7 @@ void __init m8xx_wdt_handler_install(bd_t * binfo) | |||
51 | u32 sypcr; | 51 | u32 sypcr; |
52 | u32 pitrtclk; | 52 | u32 pitrtclk; |
53 | 53 | ||
54 | sypcr = imap->im_siu_conf.sc_sypcr; | 54 | sypcr = in_be32(imap->im_siu_conf.sc_sypcr); |
55 | 55 | ||
56 | if (!(sypcr & 0x04)) { | 56 | if (!(sypcr & 0x04)) { |
57 | printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n", | 57 | printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n", |
@@ -87,9 +87,9 @@ void __init m8xx_wdt_handler_install(bd_t * binfo) | |||
87 | else | 87 | else |
88 | pitc = pitrtclk * wdt_timeout / binfo->bi_intfreq / 2; | 88 | pitc = pitrtclk * wdt_timeout / binfo->bi_intfreq / 2; |
89 | 89 | ||
90 | imap->im_sit.sit_pitc = pitc << 16; | 90 | out_be32(imap->im_sit.sit_pitc, pitc << 16); |
91 | imap->im_sit.sit_piscr = | 91 | |
92 | (mk_int_int_mask(PIT_INTERRUPT) << 8) | PISCR_PIE | PISCR_PTE; | 92 | out_be16(imap->im_sit.sit_piscr, (mk_int_int_mask(PIT_INTERRUPT) << 8) | PISCR_PIE | PISCR_PTE); |
93 | 93 | ||
94 | if (setup_irq(PIT_INTERRUPT, &m8xx_wdt_irqaction)) | 94 | if (setup_irq(PIT_INTERRUPT, &m8xx_wdt_irqaction)) |
95 | panic("m8xx_wdt: error setting up the watchdog irq!"); | 95 | panic("m8xx_wdt: error setting up the watchdog irq!"); |
diff --git a/arch/ppc/syslib/ppc8xx_pic.c b/arch/ppc/syslib/ppc8xx_pic.c index d3b01c6c97de..3e6f51a61d46 100644 --- a/arch/ppc/syslib/ppc8xx_pic.c +++ b/arch/ppc/syslib/ppc8xx_pic.c | |||
@@ -6,6 +6,7 @@ | |||
6 | #include <linux/signal.h> | 6 | #include <linux/signal.h> |
7 | #include <linux/interrupt.h> | 7 | #include <linux/interrupt.h> |
8 | #include <asm/irq.h> | 8 | #include <asm/irq.h> |
9 | #include <asm/io.h> | ||
9 | #include <asm/8xx_immap.h> | 10 | #include <asm/8xx_immap.h> |
10 | #include <asm/mpc8xx.h> | 11 | #include <asm/mpc8xx.h> |
11 | #include "ppc8xx_pic.h" | 12 | #include "ppc8xx_pic.h" |
@@ -29,8 +30,7 @@ static void m8xx_mask_irq(unsigned int irq_nr) | |||
29 | word = irq_nr >> 5; | 30 | word = irq_nr >> 5; |
30 | 31 | ||
31 | ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); | 32 | ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); |
32 | ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = | 33 | out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); |
33 | ppc_cached_irq_mask[word]; | ||
34 | } | 34 | } |
35 | 35 | ||
36 | static void m8xx_unmask_irq(unsigned int irq_nr) | 36 | static void m8xx_unmask_irq(unsigned int irq_nr) |
@@ -41,8 +41,7 @@ static void m8xx_unmask_irq(unsigned int irq_nr) | |||
41 | word = irq_nr >> 5; | 41 | word = irq_nr >> 5; |
42 | 42 | ||
43 | ppc_cached_irq_mask[word] |= (1 << (31-bit)); | 43 | ppc_cached_irq_mask[word] |= (1 << (31-bit)); |
44 | ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = | 44 | out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); |
45 | ppc_cached_irq_mask[word]; | ||
46 | } | 45 | } |
47 | 46 | ||
48 | static void m8xx_end_irq(unsigned int irq_nr) | 47 | static void m8xx_end_irq(unsigned int irq_nr) |
@@ -55,8 +54,7 @@ static void m8xx_end_irq(unsigned int irq_nr) | |||
55 | word = irq_nr >> 5; | 54 | word = irq_nr >> 5; |
56 | 55 | ||
57 | ppc_cached_irq_mask[word] |= (1 << (31-bit)); | 56 | ppc_cached_irq_mask[word] |= (1 << (31-bit)); |
58 | ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = | 57 | out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); |
59 | ppc_cached_irq_mask[word]; | ||
60 | } | 58 | } |
61 | } | 59 | } |
62 | 60 | ||
@@ -69,9 +67,8 @@ static void m8xx_mask_and_ack(unsigned int irq_nr) | |||
69 | word = irq_nr >> 5; | 67 | word = irq_nr >> 5; |
70 | 68 | ||
71 | ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); | 69 | ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); |
72 | ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = | 70 | out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]); |
73 | ppc_cached_irq_mask[word]; | 71 | out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend, 1 << (31-bit)); |
74 | ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = 1 << (31-bit); | ||
75 | } | 72 | } |
76 | 73 | ||
77 | struct hw_interrupt_type ppc8xx_pic = { | 74 | struct hw_interrupt_type ppc8xx_pic = { |
@@ -93,7 +90,7 @@ m8xx_get_irq(struct pt_regs *regs) | |||
93 | /* For MPC8xx, read the SIVEC register and shift the bits down | 90 | /* For MPC8xx, read the SIVEC register and shift the bits down |
94 | * to get the irq number. | 91 | * to get the irq number. |
95 | */ | 92 | */ |
96 | irq = ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26; | 93 | irq = in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec) >> 26; |
97 | 94 | ||
98 | /* | 95 | /* |
99 | * When we read the sivec without an interrupt to process, we will | 96 | * When we read the sivec without an interrupt to process, we will |