Merge branch 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/i7core

* 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/i7core: (83 commits)
  i7core_edac: Better describe the supported devices
  Add support for Westmere to i7core_edac driver
  i7core_edac: don't free on success
  i7core_edac: Add support for X5670
  Always call i7core_[ur]dimm_check_mc_ecc_err
  i7core_edac: fix memory leak of i7core_dev
  EDAC: add __init to i7core_xeon_pci_fixup
  i7core_edac: Fix wrong device id for channel 1 devices
  i7core: add support for Lynnfield alternate address
  i7core_edac: Add initial support for Lynnfield
  i7core_edac: do not export static functions
  edac: fix i7core build
  edac: i7core_edac produces undefined behaviour on 32bit
  i7core_edac: Use a more generic approach for probing PCI devices
  i7core_edac: PCI device is called NONCORE, instead of NOCORE
  i7core_edac: Fix ringbuffer maxsize
  i7core_edac: First store, then increment
  i7core_edac: Better parse "any" addrmask
  i7core_edac: Use a lockless ringbuffer
  edac: Create an unique instance for each kobj
  ...

3 files changed, 37 insertions, 17 deletions

diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index 8d8797eae5d7..cd2a31dc5fb8 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -53,6 +53,8 @@ extern int pcibios_last_bus;
 extern struct pci_bus *pci_root_bus;
 extern struct pci_ops pci_root_ops;
 
+void pcibios_scan_specific_bus(int busn);
+
 /* pci-irq.c */
 
 struct irq_info {
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 707165dbc203..18cc42562250 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -36,6 +36,7 @@
 #include <linux/fs.h>
 #include <linux/mm.h>
 #include <linux/debugfs.h>
+#include <linux/edac_mce.h>
 
 #include <asm/processor.h>
 #include <asm/hw_irq.h>
@@ -169,6 +170,15 @@ void mce_log(struct mce *mce)
                 entry = rcu_dereference_check_mce(mcelog.next);
                 for (;;) {
                         /*
+                         * If edac_mce is enabled, it will check the error type
+                         * and will process it, if it is a known error.
+                         * Otherwise, the error will be sent through mcelog
+                         * interface
+                         */
+                        if (edac_mce_parse(mce))
+                                return;
+
+                        /*
                          * When the buffer fills up discard new entries.
                          * Assume that the earlier errors are the more
                          * interesting ones:
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index 0db5eaf54560..8d460eaf524f 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -11,28 +11,14 @@
  */
 static void __devinit pcibios_fixup_peer_bridges(void)
 {
-        int n, devfn;
-        long node;
+        int n;
 
         if (pcibios_last_bus <= 0 || pcibios_last_bus > 0xff)
                 return;
         DBG("PCI: Peer bridge fixup\n");
 
-        for (n=0; n <= pcibios_last_bus; n++) {
-                u32 l;
-                if (pci_find_bus(0, n))
-                        continue;
-                node = get_mp_bus_to_node(n);
-                for (devfn = 0; devfn < 256; devfn += 8) {
-                        if (!raw_pci_read(0, n, devfn, PCI_VENDOR_ID, 2, &l) &&
-                            l != 0x0000 && l != 0xffff) {
-                                DBG("Found device at %02x:%02x [%04x]\n", n, devfn, l);
-                                printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
-                                pci_scan_bus_on_node(n, &pci_root_ops, node);
-                                break;
-                        }
-                }
-        }
+        for (n=0; n <= pcibios_last_bus; n++)
+                pcibios_scan_specific_bus(n);
 }
 
 int __init pci_legacy_init(void)
@@ -50,6 +36,28 @@ int __init pci_legacy_init(void)
         return 0;
 }
 
+void pcibios_scan_specific_bus(int busn)
+{
+        int devfn;
+        long node;
+        u32 l;
+
+        if (pci_find_bus(0, busn))
+                return;
+
+        node = get_mp_bus_to_node(busn);
+        for (devfn = 0; devfn < 256; devfn += 8) {
+                if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) &&
+                    l != 0x0000 && l != 0xffff) {
+                        DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l);
+                        printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn);
+                        pci_scan_bus_on_node(busn, &pci_root_ops, node);
+                        return;
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(pcibios_scan_specific_bus);
+
 int __init pci_subsys_init(void)
 {
         /*