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authorChris Metcalf <cmetcalf@tilera.com>2010-06-25 17:02:05 -0400
committerChris Metcalf <cmetcalf@tilera.com>2010-07-06 13:40:56 -0400
commit863fbac67138882b99fc60fcb0ec568bbad9a44f (patch)
tree1457799a6258d9502111f1da45f55b917ace56db /arch
parent9f9c0382cda2334b35b40b00f4ed9d6f89f37a7b (diff)
arch/tile: Shrink the tile-opcode files considerably.
The C file (tile-desc_{32,64}.c) was about 300KB before this change, and is now shrunk down to 100K. The original file included support for BFD in the binutils toolchain, which is not necessary in the kernel; the kernel version only needs to include enough support to enable the single-stepper and backtracer. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/tile/include/asm/opcode-tile_32.h93
-rw-r--r--arch/tile/include/asm/opcode-tile_64.h93
-rw-r--r--arch/tile/kernel/tile-desc_32.c13358
3 files changed, 1017 insertions, 12527 deletions
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h
index 90f8dd372531..eda60ecbae3d 100644
--- a/arch/tile/include/asm/opcode-tile_32.h
+++ b/arch/tile/include/asm/opcode-tile_32.h
@@ -28,6 +28,7 @@ typedef enum
28 TILE_OPC_MOVELI_SN, 28 TILE_OPC_MOVELI_SN,
29 TILE_OPC_MOVELIS, 29 TILE_OPC_MOVELIS,
30 TILE_OPC_PREFETCH, 30 TILE_OPC_PREFETCH,
31 TILE_OPC_RAISE,
31 TILE_OPC_ADD, 32 TILE_OPC_ADD,
32 TILE_OPC_ADD_SN, 33 TILE_OPC_ADD_SN,
33 TILE_OPC_ADDB, 34 TILE_OPC_ADDB,
@@ -419,43 +420,6 @@ typedef enum
419 420
420#define TILE_ELF_NAME "elf32-tilepro" 421#define TILE_ELF_NAME "elf32-tilepro"
421 422
422enum
423{
424 TILE_SN_MAX_OPERANDS = 6 /* route */
425};
426
427typedef enum
428{
429 TILE_SN_OPC_BZ,
430 TILE_SN_OPC_BNZ,
431 TILE_SN_OPC_JRR,
432 TILE_SN_OPC_FNOP,
433 TILE_SN_OPC_BLZ,
434 TILE_SN_OPC_NOP,
435 TILE_SN_OPC_MOVEI,
436 TILE_SN_OPC_MOVE,
437 TILE_SN_OPC_BGEZ,
438 TILE_SN_OPC_JR,
439 TILE_SN_OPC_BLEZ,
440 TILE_SN_OPC_BBNS,
441 TILE_SN_OPC_JALRR,
442 TILE_SN_OPC_BPT,
443 TILE_SN_OPC_JALR,
444 TILE_SN_OPC_SHR1,
445 TILE_SN_OPC_BGZ,
446 TILE_SN_OPC_BBS,
447 TILE_SN_OPC_SHL8II,
448 TILE_SN_OPC_ADDI,
449 TILE_SN_OPC_HALT,
450 TILE_SN_OPC_ROUTE,
451 TILE_SN_OPC_NONE
452} tile_sn_mnemonic;
453
454extern const unsigned char tile_sn_route_encode[6 * 6 * 6];
455extern const signed char tile_sn_route_decode[256][3];
456extern const char tile_sn_direction_names[6][5];
457extern const signed char tile_sn_dest_map[6][6];
458
459 423
460static __inline unsigned int 424static __inline unsigned int
461get_BrOff_SN(tile_bundle_bits num) 425get_BrOff_SN(tile_bundle_bits num)
@@ -1387,8 +1351,6 @@ create_UnShOpcodeExtension_Y1(int num)
1387} 1351}
1388 1352
1389 1353
1390typedef unsigned short tile_sn_instruction_bits;
1391
1392 1354
1393typedef enum 1355typedef enum
1394{ 1356{
@@ -1519,41 +1481,10 @@ struct tile_opcode
1519 * index into the tile_operands[] table. */ 1481 * index into the tile_operands[] table. */
1520 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS]; 1482 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS];
1521 1483
1522 /* A mask of which bits have predefined values for each pipeline.
1523 * This is useful for disassembly. */
1524 tile_bundle_bits fixed_bit_masks[TILE_NUM_PIPELINE_ENCODINGS];
1525
1526 /* For each bit set in fixed_bit_masks, what the value is for this
1527 * instruction. */
1528 tile_bundle_bits fixed_bit_values[TILE_NUM_PIPELINE_ENCODINGS];
1529}; 1484};
1530 1485
1531extern const struct tile_opcode tile_opcodes[]; 1486extern const struct tile_opcode tile_opcodes[];
1532 1487
1533struct tile_sn_opcode
1534{
1535 /* The opcode mnemonic, e.g. "add" */
1536 const char *name;
1537
1538 /* The enum value for this mnemonic. */
1539 tile_sn_mnemonic mnemonic;
1540
1541 /* How many operands are there? */
1542 unsigned char num_operands;
1543
1544 /* The description of the operands. Each of these is an
1545 * index into the tile_operands[] table. */
1546 unsigned char operands[TILE_SN_MAX_OPERANDS];
1547
1548 /* A mask of which bits have predefined values.
1549 * This is useful for disassembly. */
1550 tile_sn_instruction_bits fixed_bit_mask;
1551
1552 /* For each bit set in fixed_bit_masks, what its value is. */
1553 tile_sn_instruction_bits fixed_bit_values;
1554};
1555
1556extern const struct tile_sn_opcode tile_sn_opcodes[];
1557 1488
1558/* Used for non-textual disassembly into structs. */ 1489/* Used for non-textual disassembly into structs. */
1559struct tile_decoded_instruction 1490struct tile_decoded_instruction
@@ -1571,27 +1502,5 @@ extern int parse_insn_tile(tile_bundle_bits bits,
1571 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
1572 1503
1573 1504
1574/* Canonical names of all the registers. */
1575/* ISSUE: This table lives in "tile-dis.c" */
1576extern const char * const tile_register_names[];
1577
1578/* Descriptor for a special-purpose register. */
1579struct tile_spr
1580{
1581 /* The number */
1582 int number;
1583
1584 /* The name */
1585 const char *name;
1586};
1587
1588/* List of all the SPRs; ordered by increasing number. */
1589extern const struct tile_spr tile_sprs[];
1590
1591/* Number of special-purpose registers. */
1592extern const int tile_num_sprs;
1593
1594extern const char *
1595get_tile_spr_name (int num);
1596 1505
1597#endif /* opcode_tile_h */ 1506#endif /* opcode_tile_h */
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
index 90f8dd372531..eda60ecbae3d 100644
--- a/arch/tile/include/asm/opcode-tile_64.h
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -28,6 +28,7 @@ typedef enum
28 TILE_OPC_MOVELI_SN, 28 TILE_OPC_MOVELI_SN,
29 TILE_OPC_MOVELIS, 29 TILE_OPC_MOVELIS,
30 TILE_OPC_PREFETCH, 30 TILE_OPC_PREFETCH,
31 TILE_OPC_RAISE,
31 TILE_OPC_ADD, 32 TILE_OPC_ADD,
32 TILE_OPC_ADD_SN, 33 TILE_OPC_ADD_SN,
33 TILE_OPC_ADDB, 34 TILE_OPC_ADDB,
@@ -419,43 +420,6 @@ typedef enum
419 420
420#define TILE_ELF_NAME "elf32-tilepro" 421#define TILE_ELF_NAME "elf32-tilepro"
421 422
422enum
423{
424 TILE_SN_MAX_OPERANDS = 6 /* route */
425};
426
427typedef enum
428{
429 TILE_SN_OPC_BZ,
430 TILE_SN_OPC_BNZ,
431 TILE_SN_OPC_JRR,
432 TILE_SN_OPC_FNOP,
433 TILE_SN_OPC_BLZ,
434 TILE_SN_OPC_NOP,
435 TILE_SN_OPC_MOVEI,
436 TILE_SN_OPC_MOVE,
437 TILE_SN_OPC_BGEZ,
438 TILE_SN_OPC_JR,
439 TILE_SN_OPC_BLEZ,
440 TILE_SN_OPC_BBNS,
441 TILE_SN_OPC_JALRR,
442 TILE_SN_OPC_BPT,
443 TILE_SN_OPC_JALR,
444 TILE_SN_OPC_SHR1,
445 TILE_SN_OPC_BGZ,
446 TILE_SN_OPC_BBS,
447 TILE_SN_OPC_SHL8II,
448 TILE_SN_OPC_ADDI,
449 TILE_SN_OPC_HALT,
450 TILE_SN_OPC_ROUTE,
451 TILE_SN_OPC_NONE
452} tile_sn_mnemonic;
453
454extern const unsigned char tile_sn_route_encode[6 * 6 * 6];
455extern const signed char tile_sn_route_decode[256][3];
456extern const char tile_sn_direction_names[6][5];
457extern const signed char tile_sn_dest_map[6][6];
458
459 423
460static __inline unsigned int 424static __inline unsigned int
461get_BrOff_SN(tile_bundle_bits num) 425get_BrOff_SN(tile_bundle_bits num)
@@ -1387,8 +1351,6 @@ create_UnShOpcodeExtension_Y1(int num)
1387} 1351}
1388 1352
1389 1353
1390typedef unsigned short tile_sn_instruction_bits;
1391
1392 1354
1393typedef enum 1355typedef enum
1394{ 1356{
@@ -1519,41 +1481,10 @@ struct tile_opcode
1519 * index into the tile_operands[] table. */ 1481 * index into the tile_operands[] table. */
1520 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS]; 1482 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS];
1521 1483
1522 /* A mask of which bits have predefined values for each pipeline.
1523 * This is useful for disassembly. */
1524 tile_bundle_bits fixed_bit_masks[TILE_NUM_PIPELINE_ENCODINGS];
1525
1526 /* For each bit set in fixed_bit_masks, what the value is for this
1527 * instruction. */
1528 tile_bundle_bits fixed_bit_values[TILE_NUM_PIPELINE_ENCODINGS];
1529}; 1484};
1530 1485
1531extern const struct tile_opcode tile_opcodes[]; 1486extern const struct tile_opcode tile_opcodes[];
1532 1487
1533struct tile_sn_opcode
1534{
1535 /* The opcode mnemonic, e.g. "add" */
1536 const char *name;
1537
1538 /* The enum value for this mnemonic. */
1539 tile_sn_mnemonic mnemonic;
1540
1541 /* How many operands are there? */
1542 unsigned char num_operands;
1543
1544 /* The description of the operands. Each of these is an
1545 * index into the tile_operands[] table. */
1546 unsigned char operands[TILE_SN_MAX_OPERANDS];
1547
1548 /* A mask of which bits have predefined values.
1549 * This is useful for disassembly. */
1550 tile_sn_instruction_bits fixed_bit_mask;
1551
1552 /* For each bit set in fixed_bit_masks, what its value is. */
1553 tile_sn_instruction_bits fixed_bit_values;
1554};
1555
1556extern const struct tile_sn_opcode tile_sn_opcodes[];
1557 1488
1558/* Used for non-textual disassembly into structs. */ 1489/* Used for non-textual disassembly into structs. */
1559struct tile_decoded_instruction 1490struct tile_decoded_instruction
@@ -1571,27 +1502,5 @@ extern int parse_insn_tile(tile_bundle_bits bits,
1571 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
1572 1503
1573 1504
1574/* Canonical names of all the registers. */
1575/* ISSUE: This table lives in "tile-dis.c" */
1576extern const char * const tile_register_names[];
1577
1578/* Descriptor for a special-purpose register. */
1579struct tile_spr
1580{
1581 /* The number */
1582 int number;
1583
1584 /* The name */
1585 const char *name;
1586};
1587
1588/* List of all the SPRs; ordered by increasing number. */
1589extern const struct tile_spr tile_sprs[];
1590
1591/* Number of special-purpose registers. */
1592extern const int tile_num_sprs;
1593
1594extern const char *
1595get_tile_spr_name (int num);
1596 1505
1597#endif /* opcode_tile_h */ 1506#endif /* opcode_tile_h */
diff --git a/arch/tile/kernel/tile-desc_32.c b/arch/tile/kernel/tile-desc_32.c
index 3b78369f86b0..69af0e150f78 100644
--- a/arch/tile/kernel/tile-desc_32.c
+++ b/arch/tile/kernel/tile-desc_32.c
@@ -1,12 +1,5 @@
1/* Define to include "bfd.h" and get actual BFD relocations below. */ 1/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
2/* #define WANT_BFD_RELOCS */ 2#define BFD_RELOC(x) -1
3
4#ifdef WANT_BFD_RELOCS
5#include "bfd.h"
6#define MAYBE_BFD_RELOC(X) (X)
7#else
8#define MAYBE_BFD_RELOC(X) -1
9#endif
10 3
11/* Special registers. */ 4/* Special registers. */
12#define TREG_LR 55 5#define TREG_LR 55
@@ -16,11014 +9,1193 @@
16/* FIXME: Rename this. */ 9/* FIXME: Rename this. */
17#include <asm/opcode-tile.h> 10#include <asm/opcode-tile.h>
18 11
12#include <linux/stddef.h>
19 13
20const struct tile_opcode tile_opcodes[394] = 14const struct tile_opcode tile_opcodes[395] =
21{ 15{
22 { "bpt", TILE_OPC_BPT, 0x2 /* pipes */, 0 /* num_operands */, 16 { "bpt", TILE_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
23 TREG_ZERO, /* implicitly_written_register */ 17 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
24 0, /* can_bundle */
25 {
26 /* operands */
27 { 0, },
28 { },
29 { 0, },
30 { 0, },
31 { 0, }
32 },
33 {
34 /* fixed_bit_masks */
35 0ULL,
36 0xfbffffff80000000ULL,
37 0ULL,
38 0ULL,
39 0ULL
40 },
41 {
42 /* fixed_bit_values */
43 -1ULL,
44 0x400b3cae00000000ULL,
45 -1ULL,
46 -1ULL,
47 -1ULL
48 }
49 }, 18 },
50 { "info", TILE_OPC_INFO, 0xf /* pipes */, 1 /* num_operands */, 19 { "info", TILE_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
51 TREG_ZERO, /* implicitly_written_register */ 20 { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
52 1, /* can_bundle */
53 {
54 /* operands */
55 { 0 },
56 { 1 },
57 { 2 },
58 { 3 },
59 { 0, }
60 },
61 {
62 /* fixed_bit_masks */
63 0x800000007ff00fffULL,
64 0xfff807ff80000000ULL,
65 0x8000000078000fffULL,
66 0xf80007ff80000000ULL,
67 0ULL
68 },
69 {
70 /* fixed_bit_values */
71 0x0000000050100fffULL,
72 0x302007ff80000000ULL,
73 0x8000000050000fffULL,
74 0xc00007ff80000000ULL,
75 -1ULL
76 }
77 }, 21 },
78 { "infol", TILE_OPC_INFOL, 0x3 /* pipes */, 1 /* num_operands */, 22 { "infol", TILE_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
79 TREG_ZERO, /* implicitly_written_register */ 23 { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
80 1, /* can_bundle */
81 {
82 /* operands */
83 { 4 },
84 { 5 },
85 { 0, },
86 { 0, },
87 { 0, }
88 },
89 {
90 /* fixed_bit_masks */
91 0x8000000070000fffULL,
92 0xf80007ff80000000ULL,
93 0ULL,
94 0ULL,
95 0ULL
96 },
97 {
98 /* fixed_bit_values */
99 0x0000000030000fffULL,
100 0x200007ff80000000ULL,
101 -1ULL,
102 -1ULL,
103 -1ULL
104 }
105 }, 24 },
106 { "j", TILE_OPC_J, 0x2 /* pipes */, 1 /* num_operands */, 25 { "j", TILE_OPC_J, 0x2, 1, TREG_ZERO, 1,
107 TREG_ZERO, /* implicitly_written_register */ 26 { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } },
108 1, /* can_bundle */
109 {
110 /* operands */
111 { 0, },
112 { 6 },
113 { 0, },
114 { 0, },
115 { 0, }
116 },
117 {
118 /* fixed_bit_masks */
119 0ULL,
120 0xf000000000000000ULL,
121 0ULL,
122 0ULL,
123 0ULL
124 },
125 {
126 /* fixed_bit_values */
127 -1ULL,
128 0x5000000000000000ULL,
129 -1ULL,
130 -1ULL,
131 -1ULL
132 }
133 }, 27 },
134 { "jal", TILE_OPC_JAL, 0x2 /* pipes */, 1 /* num_operands */, 28 { "jal", TILE_OPC_JAL, 0x2, 1, TREG_LR, 1,
135 TREG_LR, /* implicitly_written_register */ 29 { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } },
136 1, /* can_bundle */
137 {
138 /* operands */
139 { 0, },
140 { 6 },
141 { 0, },
142 { 0, },
143 { 0, }
144 },
145 {
146 /* fixed_bit_masks */
147 0ULL,
148 0xf000000000000000ULL,
149 0ULL,
150 0ULL,
151 0ULL
152 },
153 {
154 /* fixed_bit_values */
155 -1ULL,
156 0x6000000000000000ULL,
157 -1ULL,
158 -1ULL,
159 -1ULL
160 }
161 }, 30 },
162 { "move", TILE_OPC_MOVE, 0xf /* pipes */, 2 /* num_operands */, 31 { "move", TILE_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
163 TREG_ZERO, /* implicitly_written_register */ 32 { { 7, 8 }, { 9, 10 }, { 11, 12 }, { 13, 14 }, { 0, } },
164 1, /* can_bundle */
165 {
166 /* operands */
167 { 7, 8 },
168 { 9, 10 },
169 { 11, 12 },
170 { 13, 14 },
171 { 0, }
172 },
173 {
174 /* fixed_bit_masks */
175 0x800000007ffff000ULL,
176 0xfffff80000000000ULL,
177 0x80000000780ff000ULL,
178 0xf807f80000000000ULL,
179 0ULL
180 },
181 {
182 /* fixed_bit_values */
183 0x0000000000cff000ULL,
184 0x0833f80000000000ULL,
185 0x80000000180bf000ULL,
186 0x9805f80000000000ULL,
187 -1ULL
188 }
189 }, 33 },
190 { "move.sn", TILE_OPC_MOVE_SN, 0x3 /* pipes */, 2 /* num_operands */, 34 { "move.sn", TILE_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1,
191 TREG_SN, /* implicitly_written_register */ 35 { { 7, 8 }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
192 1, /* can_bundle */
193 {
194 /* operands */
195 { 7, 8 },
196 { 9, 10 },
197 { 0, },
198 { 0, },
199 { 0, }
200 },
201 {
202 /* fixed_bit_masks */
203 0x800000007ffff000ULL,
204 0xfffff80000000000ULL,
205 0ULL,
206 0ULL,
207 0ULL
208 },
209 {
210 /* fixed_bit_values */
211 0x0000000008cff000ULL,
212 0x0c33f80000000000ULL,
213 -1ULL,
214 -1ULL,
215 -1ULL
216 }
217 }, 36 },
218 { "movei", TILE_OPC_MOVEI, 0xf /* pipes */, 2 /* num_operands */, 37 { "movei", TILE_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
219 TREG_ZERO, /* implicitly_written_register */ 38 { { 7, 0 }, { 9, 1 }, { 11, 2 }, { 13, 3 }, { 0, } },
220 1, /* can_bundle */
221 {
222 /* operands */
223 { 7, 0 },
224 { 9, 1 },
225 { 11, 2 },
226 { 13, 3 },
227 { 0, }
228 },
229 {
230 /* fixed_bit_masks */
231 0x800000007ff00fc0ULL,
232 0xfff807e000000000ULL,
233 0x8000000078000fc0ULL,
234 0xf80007e000000000ULL,
235 0ULL
236 },
237 {
238 /* fixed_bit_values */
239 0x0000000040800fc0ULL,
240 0x305807e000000000ULL,
241 0x8000000058000fc0ULL,
242 0xc80007e000000000ULL,
243 -1ULL
244 }
245 }, 39 },
246 { "movei.sn", TILE_OPC_MOVEI_SN, 0x3 /* pipes */, 2 /* num_operands */, 40 { "movei.sn", TILE_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1,
247 TREG_SN, /* implicitly_written_register */ 41 { { 7, 0 }, { 9, 1 }, { 0, }, { 0, }, { 0, } },
248 1, /* can_bundle */
249 {
250 /* operands */
251 { 7, 0 },
252 { 9, 1 },
253 { 0, },
254 { 0, },
255 { 0, }
256 },
257 {
258 /* fixed_bit_masks */
259 0x800000007ff00fc0ULL,
260 0xfff807e000000000ULL,
261 0ULL,
262 0ULL,
263 0ULL
264 },
265 {
266 /* fixed_bit_values */
267 0x0000000048800fc0ULL,
268 0x345807e000000000ULL,
269 -1ULL,
270 -1ULL,
271 -1ULL
272 }
273 }, 42 },
274 { "moveli", TILE_OPC_MOVELI, 0x3 /* pipes */, 2 /* num_operands */, 43 { "moveli", TILE_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
275 TREG_ZERO, /* implicitly_written_register */ 44 { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
276 1, /* can_bundle */
277 {
278 /* operands */
279 { 7, 4 },
280 { 9, 5 },
281 { 0, },
282 { 0, },
283 { 0, }
284 },
285 {
286 /* fixed_bit_masks */
287 0x8000000070000fc0ULL,
288 0xf80007e000000000ULL,
289 0ULL,
290 0ULL,
291 0ULL
292 },
293 {
294 /* fixed_bit_values */
295 0x0000000020000fc0ULL,
296 0x180007e000000000ULL,
297 -1ULL,
298 -1ULL,
299 -1ULL
300 }
301 }, 45 },
302 { "moveli.sn", TILE_OPC_MOVELI_SN, 0x3 /* pipes */, 2 /* num_operands */, 46 { "moveli.sn", TILE_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1,
303 TREG_SN, /* implicitly_written_register */ 47 { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
304 1, /* can_bundle */
305 {
306 /* operands */
307 { 7, 4 },
308 { 9, 5 },
309 { 0, },
310 { 0, },
311 { 0, }
312 },
313 {
314 /* fixed_bit_masks */
315 0x8000000070000fc0ULL,
316 0xf80007e000000000ULL,
317 0ULL,
318 0ULL,
319 0ULL
320 },
321 {
322 /* fixed_bit_values */
323 0x0000000010000fc0ULL,
324 0x100007e000000000ULL,
325 -1ULL,
326 -1ULL,
327 -1ULL
328 }
329 }, 48 },
330 { "movelis", TILE_OPC_MOVELIS, 0x3 /* pipes */, 2 /* num_operands */, 49 { "movelis", TILE_OPC_MOVELIS, 0x3, 2, TREG_SN, 1,
331 TREG_SN, /* implicitly_written_register */ 50 { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
332 1, /* can_bundle */
333 {
334 /* operands */
335 { 7, 4 },
336 { 9, 5 },
337 { 0, },
338 { 0, },
339 { 0, }
340 },
341 {
342 /* fixed_bit_masks */
343 0x8000000070000fc0ULL,
344 0xf80007e000000000ULL,
345 0ULL,
346 0ULL,
347 0ULL
348 },
349 {
350 /* fixed_bit_values */
351 0x0000000010000fc0ULL,
352 0x100007e000000000ULL,
353 -1ULL,
354 -1ULL,
355 -1ULL
356 }
357 }, 51 },
358 { "prefetch", TILE_OPC_PREFETCH, 0x12 /* pipes */, 1 /* num_operands */, 52 { "prefetch", TILE_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
359 TREG_ZERO, /* implicitly_written_register */ 53 { { 0, }, { 10 }, { 0, }, { 0, }, { 15 } },
360 1, /* can_bundle */
361 {
362 /* operands */
363 { 0, },
364 { 10 },
365 { 0, },
366 { 0, },
367 { 15 }
368 },
369 {
370 /* fixed_bit_masks */
371 0ULL,
372 0xfffff81f80000000ULL,
373 0ULL,
374 0ULL,
375 0x8700000003f00000ULL
376 },
377 {
378 /* fixed_bit_values */
379 -1ULL,
380 0x400b501f80000000ULL,
381 -1ULL,
382 -1ULL,
383 0x8000000003f00000ULL
384 }
385 }, 54 },
386 { "add", TILE_OPC_ADD, 0xf /* pipes */, 3 /* num_operands */, 55 { "raise", TILE_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
387 TREG_ZERO, /* implicitly_written_register */ 56 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
388 1, /* can_bundle */
389 {
390 /* operands */
391 { 7, 8, 16 },
392 { 9, 10, 17 },
393 { 11, 12, 18 },
394 { 13, 14, 19 },
395 { 0, }
396 },
397 {
398 /* fixed_bit_masks */
399 0x800000007ffc0000ULL,
400 0xfffe000000000000ULL,
401 0x80000000780c0000ULL,
402 0xf806000000000000ULL,
403 0ULL
404 },
405 {
406 /* fixed_bit_values */
407 0x00000000000c0000ULL,
408 0x0806000000000000ULL,
409 0x8000000008000000ULL,
410 0x8800000000000000ULL,
411 -1ULL
412 }
413 }, 57 },
414 { "add.sn", TILE_OPC_ADD_SN, 0x3 /* pipes */, 3 /* num_operands */, 58 { "add", TILE_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
415 TREG_SN, /* implicitly_written_register */ 59 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
416 1, /* can_bundle */
417 {
418 /* operands */
419 { 7, 8, 16 },
420 { 9, 10, 17 },
421 { 0, },
422 { 0, },
423 { 0, }
424 },
425 {
426 /* fixed_bit_masks */
427 0x800000007ffc0000ULL,
428 0xfffe000000000000ULL,
429 0ULL,
430 0ULL,
431 0ULL
432 },
433 {
434 /* fixed_bit_values */
435 0x00000000080c0000ULL,
436 0x0c06000000000000ULL,
437 -1ULL,
438 -1ULL,
439 -1ULL
440 }
441 }, 60 },
442 { "addb", TILE_OPC_ADDB, 0x3 /* pipes */, 3 /* num_operands */, 61 { "add.sn", TILE_OPC_ADD_SN, 0x3, 3, TREG_SN, 1,
443 TREG_ZERO, /* implicitly_written_register */ 62 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
444 1, /* can_bundle */
445 {
446 /* operands */
447 { 7, 8, 16 },
448 { 9, 10, 17 },
449 { 0, },
450 { 0, },
451 { 0, }
452 },
453 {
454 /* fixed_bit_masks */
455 0x800000007ffc0000ULL,
456 0xfffe000000000000ULL,
457 0ULL,
458 0ULL,
459 0ULL
460 },
461 {
462 /* fixed_bit_values */
463 0x0000000000040000ULL,
464 0x0802000000000000ULL,
465 -1ULL,
466 -1ULL,
467 -1ULL
468 }
469 }, 63 },
470 { "addb.sn", TILE_OPC_ADDB_SN, 0x3 /* pipes */, 3 /* num_operands */, 64 { "addb", TILE_OPC_ADDB, 0x3, 3, TREG_ZERO, 1,
471 TREG_SN, /* implicitly_written_register */ 65 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
472 1, /* can_bundle */
473 {
474 /* operands */
475 { 7, 8, 16 },
476 { 9, 10, 17 },
477 { 0, },
478 { 0, },
479 { 0, }
480 },
481 {
482 /* fixed_bit_masks */
483 0x800000007ffc0000ULL,
484 0xfffe000000000000ULL,
485 0ULL,
486 0ULL,
487 0ULL
488 },
489 {
490 /* fixed_bit_values */
491 0x0000000008040000ULL,
492 0x0c02000000000000ULL,
493 -1ULL,
494 -1ULL,
495 -1ULL
496 }
497 }, 66 },
498 { "addbs_u", TILE_OPC_ADDBS_U, 0x3 /* pipes */, 3 /* num_operands */, 67 { "addb.sn", TILE_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1,
499 TREG_ZERO, /* implicitly_written_register */ 68 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
500 1, /* can_bundle */
501 {
502 /* operands */
503 { 7, 8, 16 },
504 { 9, 10, 17 },
505 { 0, },
506 { 0, },
507 { 0, }
508 },
509 {
510 /* fixed_bit_masks */
511 0x800000007ffc0000ULL,
512 0xfffe000000000000ULL,
513 0ULL,
514 0ULL,
515 0ULL
516 },
517 {
518 /* fixed_bit_values */
519 0x0000000001880000ULL,
520 0x0888000000000000ULL,
521 -1ULL,
522 -1ULL,
523 -1ULL
524 }
525 }, 69 },
526 { "addbs_u.sn", TILE_OPC_ADDBS_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 70 { "addbs_u", TILE_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1,
527 TREG_SN, /* implicitly_written_register */ 71 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
528 1, /* can_bundle */
529 {
530 /* operands */
531 { 7, 8, 16 },
532 { 9, 10, 17 },
533 { 0, },
534 { 0, },
535 { 0, }
536 },
537 {
538 /* fixed_bit_masks */
539 0x800000007ffc0000ULL,
540 0xfffe000000000000ULL,
541 0ULL,
542 0ULL,
543 0ULL
544 },
545 {
546 /* fixed_bit_values */
547 0x0000000009880000ULL,
548 0x0c88000000000000ULL,
549 -1ULL,
550 -1ULL,
551 -1ULL
552 }
553 }, 72 },
554 { "addh", TILE_OPC_ADDH, 0x3 /* pipes */, 3 /* num_operands */, 73 { "addbs_u.sn", TILE_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1,
555 TREG_ZERO, /* implicitly_written_register */ 74 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
556 1, /* can_bundle */
557 {
558 /* operands */
559 { 7, 8, 16 },
560 { 9, 10, 17 },
561 { 0, },
562 { 0, },
563 { 0, }
564 },
565 {
566 /* fixed_bit_masks */
567 0x800000007ffc0000ULL,
568 0xfffe000000000000ULL,
569 0ULL,
570 0ULL,
571 0ULL
572 },
573 {
574 /* fixed_bit_values */
575 0x0000000000080000ULL,
576 0x0804000000000000ULL,
577 -1ULL,
578 -1ULL,
579 -1ULL
580 }
581 }, 75 },
582 { "addh.sn", TILE_OPC_ADDH_SN, 0x3 /* pipes */, 3 /* num_operands */, 76 { "addh", TILE_OPC_ADDH, 0x3, 3, TREG_ZERO, 1,
583 TREG_SN, /* implicitly_written_register */ 77 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
584 1, /* can_bundle */
585 {
586 /* operands */
587 { 7, 8, 16 },
588 { 9, 10, 17 },
589 { 0, },
590 { 0, },
591 { 0, }
592 },
593 {
594 /* fixed_bit_masks */
595 0x800000007ffc0000ULL,
596 0xfffe000000000000ULL,
597 0ULL,
598 0ULL,
599 0ULL
600 },
601 {
602 /* fixed_bit_values */
603 0x0000000008080000ULL,
604 0x0c04000000000000ULL,
605 -1ULL,
606 -1ULL,
607 -1ULL
608 }
609 }, 78 },
610 { "addhs", TILE_OPC_ADDHS, 0x3 /* pipes */, 3 /* num_operands */, 79 { "addh.sn", TILE_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1,
611 TREG_ZERO, /* implicitly_written_register */ 80 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
612 1, /* can_bundle */
613 {
614 /* operands */
615 { 7, 8, 16 },
616 { 9, 10, 17 },
617 { 0, },
618 { 0, },
619 { 0, }
620 },
621 {
622 /* fixed_bit_masks */
623 0x800000007ffc0000ULL,
624 0xfffe000000000000ULL,
625 0ULL,
626 0ULL,
627 0ULL
628 },
629 {
630 /* fixed_bit_values */
631 0x00000000018c0000ULL,
632 0x088a000000000000ULL,
633 -1ULL,
634 -1ULL,
635 -1ULL
636 }
637 }, 81 },
638 { "addhs.sn", TILE_OPC_ADDHS_SN, 0x3 /* pipes */, 3 /* num_operands */, 82 { "addhs", TILE_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1,
639 TREG_SN, /* implicitly_written_register */ 83 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
640 1, /* can_bundle */
641 {
642 /* operands */
643 { 7, 8, 16 },
644 { 9, 10, 17 },
645 { 0, },
646 { 0, },
647 { 0, }
648 },
649 {
650 /* fixed_bit_masks */
651 0x800000007ffc0000ULL,
652 0xfffe000000000000ULL,
653 0ULL,
654 0ULL,
655 0ULL
656 },
657 {
658 /* fixed_bit_values */
659 0x00000000098c0000ULL,
660 0x0c8a000000000000ULL,
661 -1ULL,
662 -1ULL,
663 -1ULL
664 }
665 }, 84 },
666 { "addi", TILE_OPC_ADDI, 0xf /* pipes */, 3 /* num_operands */, 85 { "addhs.sn", TILE_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1,
667 TREG_ZERO, /* implicitly_written_register */ 86 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
668 1, /* can_bundle */
669 {
670 /* operands */
671 { 7, 8, 0 },
672 { 9, 10, 1 },
673 { 11, 12, 2 },
674 { 13, 14, 3 },
675 { 0, }
676 },
677 {
678 /* fixed_bit_masks */
679 0x800000007ff00000ULL,
680 0xfff8000000000000ULL,
681 0x8000000078000000ULL,
682 0xf800000000000000ULL,
683 0ULL
684 },
685 {
686 /* fixed_bit_values */
687 0x0000000040300000ULL,
688 0x3018000000000000ULL,
689 0x8000000048000000ULL,
690 0xb800000000000000ULL,
691 -1ULL
692 }
693 }, 87 },
694 { "addi.sn", TILE_OPC_ADDI_SN, 0x3 /* pipes */, 3 /* num_operands */, 88 { "addi", TILE_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
695 TREG_SN, /* implicitly_written_register */ 89 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
696 1, /* can_bundle */
697 {
698 /* operands */
699 { 7, 8, 0 },
700 { 9, 10, 1 },
701 { 0, },
702 { 0, },
703 { 0, }
704 },
705 {
706 /* fixed_bit_masks */
707 0x800000007ff00000ULL,
708 0xfff8000000000000ULL,
709 0ULL,
710 0ULL,
711 0ULL
712 },
713 {
714 /* fixed_bit_values */
715 0x0000000048300000ULL,
716 0x3418000000000000ULL,
717 -1ULL,
718 -1ULL,
719 -1ULL
720 }
721 }, 90 },
722 { "addib", TILE_OPC_ADDIB, 0x3 /* pipes */, 3 /* num_operands */, 91 { "addi.sn", TILE_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1,
723 TREG_ZERO, /* implicitly_written_register */ 92 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
724 1, /* can_bundle */
725 {
726 /* operands */
727 { 7, 8, 0 },
728 { 9, 10, 1 },
729 { 0, },
730 { 0, },
731 { 0, }
732 },
733 {
734 /* fixed_bit_masks */
735 0x800000007ff00000ULL,
736 0xfff8000000000000ULL,
737 0ULL,
738 0ULL,
739 0ULL
740 },
741 {
742 /* fixed_bit_values */
743 0x0000000040100000ULL,
744 0x3008000000000000ULL,
745 -1ULL,
746 -1ULL,
747 -1ULL
748 }
749 }, 93 },
750 { "addib.sn", TILE_OPC_ADDIB_SN, 0x3 /* pipes */, 3 /* num_operands */, 94 { "addib", TILE_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1,
751 TREG_SN, /* implicitly_written_register */ 95 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
752 1, /* can_bundle */
753 {
754 /* operands */
755 { 7, 8, 0 },
756 { 9, 10, 1 },
757 { 0, },
758 { 0, },
759 { 0, }
760 },
761 {
762 /* fixed_bit_masks */
763 0x800000007ff00000ULL,
764 0xfff8000000000000ULL,
765 0ULL,
766 0ULL,
767 0ULL
768 },
769 {
770 /* fixed_bit_values */
771 0x0000000048100000ULL,
772 0x3408000000000000ULL,
773 -1ULL,
774 -1ULL,
775 -1ULL
776 }
777 }, 96 },
778 { "addih", TILE_OPC_ADDIH, 0x3 /* pipes */, 3 /* num_operands */, 97 { "addib.sn", TILE_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1,
779 TREG_ZERO, /* implicitly_written_register */ 98 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
780 1, /* can_bundle */
781 {
782 /* operands */
783 { 7, 8, 0 },
784 { 9, 10, 1 },
785 { 0, },
786 { 0, },
787 { 0, }
788 },
789 {
790 /* fixed_bit_masks */
791 0x800000007ff00000ULL,
792 0xfff8000000000000ULL,
793 0ULL,
794 0ULL,
795 0ULL
796 },
797 {
798 /* fixed_bit_values */
799 0x0000000040200000ULL,
800 0x3010000000000000ULL,
801 -1ULL,
802 -1ULL,
803 -1ULL
804 }
805 }, 99 },
806 { "addih.sn", TILE_OPC_ADDIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 100 { "addih", TILE_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1,
807 TREG_SN, /* implicitly_written_register */ 101 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
808 1, /* can_bundle */
809 {
810 /* operands */
811 { 7, 8, 0 },
812 { 9, 10, 1 },
813 { 0, },
814 { 0, },
815 { 0, }
816 },
817 {
818 /* fixed_bit_masks */
819 0x800000007ff00000ULL,
820 0xfff8000000000000ULL,
821 0ULL,
822 0ULL,
823 0ULL
824 },
825 {
826 /* fixed_bit_values */
827 0x0000000048200000ULL,
828 0x3410000000000000ULL,
829 -1ULL,
830 -1ULL,
831 -1ULL
832 }
833 }, 102 },
834 { "addli", TILE_OPC_ADDLI, 0x3 /* pipes */, 3 /* num_operands */, 103 { "addih.sn", TILE_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1,
835 TREG_ZERO, /* implicitly_written_register */ 104 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
836 1, /* can_bundle */
837 {
838 /* operands */
839 { 7, 8, 4 },
840 { 9, 10, 5 },
841 { 0, },
842 { 0, },
843 { 0, }
844 },
845 {
846 /* fixed_bit_masks */
847 0x8000000070000000ULL,
848 0xf800000000000000ULL,
849 0ULL,
850 0ULL,
851 0ULL
852 },
853 {
854 /* fixed_bit_values */
855 0x0000000020000000ULL,
856 0x1800000000000000ULL,
857 -1ULL,
858 -1ULL,
859 -1ULL
860 }
861 }, 105 },
862 { "addli.sn", TILE_OPC_ADDLI_SN, 0x3 /* pipes */, 3 /* num_operands */, 106 { "addli", TILE_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
863 TREG_SN, /* implicitly_written_register */ 107 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
864 1, /* can_bundle */
865 {
866 /* operands */
867 { 7, 8, 4 },
868 { 9, 10, 5 },
869 { 0, },
870 { 0, },
871 { 0, }
872 },
873 {
874 /* fixed_bit_masks */
875 0x8000000070000000ULL,
876 0xf800000000000000ULL,
877 0ULL,
878 0ULL,
879 0ULL
880 },
881 {
882 /* fixed_bit_values */
883 0x0000000010000000ULL,
884 0x1000000000000000ULL,
885 -1ULL,
886 -1ULL,
887 -1ULL
888 }
889 }, 108 },
890 { "addlis", TILE_OPC_ADDLIS, 0x3 /* pipes */, 3 /* num_operands */, 109 { "addli.sn", TILE_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1,
891 TREG_SN, /* implicitly_written_register */ 110 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
892 1, /* can_bundle */
893 {
894 /* operands */
895 { 7, 8, 4 },
896 { 9, 10, 5 },
897 { 0, },
898 { 0, },
899 { 0, }
900 },
901 {
902 /* fixed_bit_masks */
903 0x8000000070000000ULL,
904 0xf800000000000000ULL,
905 0ULL,
906 0ULL,
907 0ULL
908 },
909 {
910 /* fixed_bit_values */
911 0x0000000010000000ULL,
912 0x1000000000000000ULL,
913 -1ULL,
914 -1ULL,
915 -1ULL
916 }
917 }, 111 },
918 { "adds", TILE_OPC_ADDS, 0x3 /* pipes */, 3 /* num_operands */, 112 { "addlis", TILE_OPC_ADDLIS, 0x3, 3, TREG_SN, 1,
919 TREG_ZERO, /* implicitly_written_register */ 113 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
920 1, /* can_bundle */
921 {
922 /* operands */
923 { 7, 8, 16 },
924 { 9, 10, 17 },
925 { 0, },
926 { 0, },
927 { 0, }
928 },
929 {
930 /* fixed_bit_masks */
931 0x800000007ffc0000ULL,
932 0xfffe000000000000ULL,
933 0ULL,
934 0ULL,
935 0ULL
936 },
937 {
938 /* fixed_bit_values */
939 0x0000000001800000ULL,
940 0x0884000000000000ULL,
941 -1ULL,
942 -1ULL,
943 -1ULL
944 }
945 }, 114 },
946 { "adds.sn", TILE_OPC_ADDS_SN, 0x3 /* pipes */, 3 /* num_operands */, 115 { "adds", TILE_OPC_ADDS, 0x3, 3, TREG_ZERO, 1,
947 TREG_SN, /* implicitly_written_register */ 116 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
948 1, /* can_bundle */
949 {
950 /* operands */
951 { 7, 8, 16 },
952 { 9, 10, 17 },
953 { 0, },
954 { 0, },
955 { 0, }
956 },
957 {
958 /* fixed_bit_masks */
959 0x800000007ffc0000ULL,
960 0xfffe000000000000ULL,
961 0ULL,
962 0ULL,
963 0ULL
964 },
965 {
966 /* fixed_bit_values */
967 0x0000000009800000ULL,
968 0x0c84000000000000ULL,
969 -1ULL,
970 -1ULL,
971 -1ULL
972 }
973 }, 117 },
974 { "adiffb_u", TILE_OPC_ADIFFB_U, 0x1 /* pipes */, 3 /* num_operands */, 118 { "adds.sn", TILE_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1,
975 TREG_ZERO, /* implicitly_written_register */ 119 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
976 1, /* can_bundle */
977 {
978 /* operands */
979 { 7, 8, 16 },
980 { 0, },
981 { 0, },
982 { 0, },
983 { 0, }
984 },
985 {
986 /* fixed_bit_masks */
987 0x800000007ffc0000ULL,
988 0ULL,
989 0ULL,
990 0ULL,
991 0ULL
992 },
993 {
994 /* fixed_bit_values */
995 0x0000000000100000ULL,
996 -1ULL,
997 -1ULL,
998 -1ULL,
999 -1ULL
1000 }
1001 }, 120 },
1002 { "adiffb_u.sn", TILE_OPC_ADIFFB_U_SN, 0x1 /* pipes */, 3 /* num_operands */, 121 { "adiffb_u", TILE_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1,
1003 TREG_SN, /* implicitly_written_register */ 122 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1004 1, /* can_bundle */
1005 {
1006 /* operands */
1007 { 7, 8, 16 },
1008 { 0, },
1009 { 0, },
1010 { 0, },
1011 { 0, }
1012 },
1013 {
1014 /* fixed_bit_masks */
1015 0x800000007ffc0000ULL,
1016 0ULL,
1017 0ULL,
1018 0ULL,
1019 0ULL
1020 },
1021 {
1022 /* fixed_bit_values */
1023 0x0000000008100000ULL,
1024 -1ULL,
1025 -1ULL,
1026 -1ULL,
1027 -1ULL
1028 }
1029 }, 123 },
1030 { "adiffh", TILE_OPC_ADIFFH, 0x1 /* pipes */, 3 /* num_operands */, 124 { "adiffb_u.sn", TILE_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1,
1031 TREG_ZERO, /* implicitly_written_register */ 125 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1032 1, /* can_bundle */
1033 {
1034 /* operands */
1035 { 7, 8, 16 },
1036 { 0, },
1037 { 0, },
1038 { 0, },
1039 { 0, }
1040 },
1041 {
1042 /* fixed_bit_masks */
1043 0x800000007ffc0000ULL,
1044 0ULL,
1045 0ULL,
1046 0ULL,
1047 0ULL
1048 },
1049 {
1050 /* fixed_bit_values */
1051 0x0000000000140000ULL,
1052 -1ULL,
1053 -1ULL,
1054 -1ULL,
1055 -1ULL
1056 }
1057 }, 126 },
1058 { "adiffh.sn", TILE_OPC_ADIFFH_SN, 0x1 /* pipes */, 3 /* num_operands */, 127 { "adiffh", TILE_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1,
1059 TREG_SN, /* implicitly_written_register */ 128 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1060 1, /* can_bundle */
1061 {
1062 /* operands */
1063 { 7, 8, 16 },
1064 { 0, },
1065 { 0, },
1066 { 0, },
1067 { 0, }
1068 },
1069 {
1070 /* fixed_bit_masks */
1071 0x800000007ffc0000ULL,
1072 0ULL,
1073 0ULL,
1074 0ULL,
1075 0ULL
1076 },
1077 {
1078 /* fixed_bit_values */
1079 0x0000000008140000ULL,
1080 -1ULL,
1081 -1ULL,
1082 -1ULL,
1083 -1ULL
1084 }
1085 }, 129 },
1086 { "and", TILE_OPC_AND, 0xf /* pipes */, 3 /* num_operands */, 130 { "adiffh.sn", TILE_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1,
1087 TREG_ZERO, /* implicitly_written_register */ 131 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1088 1, /* can_bundle */
1089 {
1090 /* operands */
1091 { 7, 8, 16 },
1092 { 9, 10, 17 },
1093 { 11, 12, 18 },
1094 { 13, 14, 19 },
1095 { 0, }
1096 },
1097 {
1098 /* fixed_bit_masks */
1099 0x800000007ffc0000ULL,
1100 0xfffe000000000000ULL,
1101 0x80000000780c0000ULL,
1102 0xf806000000000000ULL,
1103 0ULL
1104 },
1105 {
1106 /* fixed_bit_values */
1107 0x0000000000180000ULL,
1108 0x0808000000000000ULL,
1109 0x8000000018000000ULL,
1110 0x9800000000000000ULL,
1111 -1ULL
1112 }
1113 }, 132 },
1114 { "and.sn", TILE_OPC_AND_SN, 0x3 /* pipes */, 3 /* num_operands */, 133 { "and", TILE_OPC_AND, 0xf, 3, TREG_ZERO, 1,
1115 TREG_SN, /* implicitly_written_register */ 134 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
1116 1, /* can_bundle */
1117 {
1118 /* operands */
1119 { 7, 8, 16 },
1120 { 9, 10, 17 },
1121 { 0, },
1122 { 0, },
1123 { 0, }
1124 },
1125 {
1126 /* fixed_bit_masks */
1127 0x800000007ffc0000ULL,
1128 0xfffe000000000000ULL,
1129 0ULL,
1130 0ULL,
1131 0ULL
1132 },
1133 {
1134 /* fixed_bit_values */
1135 0x0000000008180000ULL,
1136 0x0c08000000000000ULL,
1137 -1ULL,
1138 -1ULL,
1139 -1ULL
1140 }
1141 }, 135 },
1142 { "andi", TILE_OPC_ANDI, 0xf /* pipes */, 3 /* num_operands */, 136 { "and.sn", TILE_OPC_AND_SN, 0x3, 3, TREG_SN, 1,
1143 TREG_ZERO, /* implicitly_written_register */ 137 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
1144 1, /* can_bundle */
1145 {
1146 /* operands */
1147 { 7, 8, 0 },
1148 { 9, 10, 1 },
1149 { 11, 12, 2 },
1150 { 13, 14, 3 },
1151 { 0, }
1152 },
1153 {
1154 /* fixed_bit_masks */
1155 0x800000007ff00000ULL,
1156 0xfff8000000000000ULL,
1157 0x8000000078000000ULL,
1158 0xf800000000000000ULL,
1159 0ULL
1160 },
1161 {
1162 /* fixed_bit_values */
1163 0x0000000050100000ULL,
1164 0x3020000000000000ULL,
1165 0x8000000050000000ULL,
1166 0xc000000000000000ULL,
1167 -1ULL
1168 }
1169 }, 138 },
1170 { "andi.sn", TILE_OPC_ANDI_SN, 0x3 /* pipes */, 3 /* num_operands */, 139 { "andi", TILE_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
1171 TREG_SN, /* implicitly_written_register */ 140 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
1172 1, /* can_bundle */
1173 {
1174 /* operands */
1175 { 7, 8, 0 },
1176 { 9, 10, 1 },
1177 { 0, },
1178 { 0, },
1179 { 0, }
1180 },
1181 {
1182 /* fixed_bit_masks */
1183 0x800000007ff00000ULL,
1184 0xfff8000000000000ULL,
1185 0ULL,
1186 0ULL,
1187 0ULL
1188 },
1189 {
1190 /* fixed_bit_values */
1191 0x0000000058100000ULL,
1192 0x3420000000000000ULL,
1193 -1ULL,
1194 -1ULL,
1195 -1ULL
1196 }
1197 }, 141 },
1198 { "auli", TILE_OPC_AULI, 0x3 /* pipes */, 3 /* num_operands */, 142 { "andi.sn", TILE_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1,
1199 TREG_ZERO, /* implicitly_written_register */ 143 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
1200 1, /* can_bundle */
1201 {
1202 /* operands */
1203 { 7, 8, 4 },
1204 { 9, 10, 5 },
1205 { 0, },
1206 { 0, },
1207 { 0, }
1208 },
1209 {
1210 /* fixed_bit_masks */
1211 0x8000000070000000ULL,
1212 0xf800000000000000ULL,
1213 0ULL,
1214 0ULL,
1215 0ULL
1216 },
1217 {
1218 /* fixed_bit_values */
1219 0x0000000030000000ULL,
1220 0x2000000000000000ULL,
1221 -1ULL,
1222 -1ULL,
1223 -1ULL
1224 }
1225 }, 144 },
1226 { "avgb_u", TILE_OPC_AVGB_U, 0x1 /* pipes */, 3 /* num_operands */, 145 { "auli", TILE_OPC_AULI, 0x3, 3, TREG_ZERO, 1,
1227 TREG_ZERO, /* implicitly_written_register */ 146 { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
1228 1, /* can_bundle */
1229 {
1230 /* operands */
1231 { 7, 8, 16 },
1232 { 0, },
1233 { 0, },
1234 { 0, },
1235 { 0, }
1236 },
1237 {
1238 /* fixed_bit_masks */
1239 0x800000007ffc0000ULL,
1240 0ULL,
1241 0ULL,
1242 0ULL,
1243 0ULL
1244 },
1245 {
1246 /* fixed_bit_values */
1247 0x00000000001c0000ULL,
1248 -1ULL,
1249 -1ULL,
1250 -1ULL,
1251 -1ULL
1252 }
1253 }, 147 },
1254 { "avgb_u.sn", TILE_OPC_AVGB_U_SN, 0x1 /* pipes */, 3 /* num_operands */, 148 { "avgb_u", TILE_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1,
1255 TREG_SN, /* implicitly_written_register */ 149 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1256 1, /* can_bundle */
1257 {
1258 /* operands */
1259 { 7, 8, 16 },
1260 { 0, },
1261 { 0, },
1262 { 0, },
1263 { 0, }
1264 },
1265 {
1266 /* fixed_bit_masks */
1267 0x800000007ffc0000ULL,
1268 0ULL,
1269 0ULL,
1270 0ULL,
1271 0ULL
1272 },
1273 {
1274 /* fixed_bit_values */
1275 0x00000000081c0000ULL,
1276 -1ULL,
1277 -1ULL,
1278 -1ULL,
1279 -1ULL
1280 }
1281 }, 150 },
1282 { "avgh", TILE_OPC_AVGH, 0x1 /* pipes */, 3 /* num_operands */, 151 { "avgb_u.sn", TILE_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1,
1283 TREG_ZERO, /* implicitly_written_register */ 152 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1284 1, /* can_bundle */
1285 {
1286 /* operands */
1287 { 7, 8, 16 },
1288 { 0, },
1289 { 0, },
1290 { 0, },
1291 { 0, }
1292 },
1293 {
1294 /* fixed_bit_masks */
1295 0x800000007ffc0000ULL,
1296 0ULL,
1297 0ULL,
1298 0ULL,
1299 0ULL
1300 },
1301 {
1302 /* fixed_bit_values */
1303 0x0000000000200000ULL,
1304 -1ULL,
1305 -1ULL,
1306 -1ULL,
1307 -1ULL
1308 }
1309 }, 153 },
1310 { "avgh.sn", TILE_OPC_AVGH_SN, 0x1 /* pipes */, 3 /* num_operands */, 154 { "avgh", TILE_OPC_AVGH, 0x1, 3, TREG_ZERO, 1,
1311 TREG_SN, /* implicitly_written_register */ 155 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1312 1, /* can_bundle */
1313 {
1314 /* operands */
1315 { 7, 8, 16 },
1316 { 0, },
1317 { 0, },
1318 { 0, },
1319 { 0, }
1320 },
1321 {
1322 /* fixed_bit_masks */
1323 0x800000007ffc0000ULL,
1324 0ULL,
1325 0ULL,
1326 0ULL,
1327 0ULL
1328 },
1329 {
1330 /* fixed_bit_values */
1331 0x0000000008200000ULL,
1332 -1ULL,
1333 -1ULL,
1334 -1ULL,
1335 -1ULL
1336 }
1337 }, 156 },
1338 { "bbns", TILE_OPC_BBNS, 0x2 /* pipes */, 2 /* num_operands */, 157 { "avgh.sn", TILE_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1,
1339 TREG_ZERO, /* implicitly_written_register */ 158 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
1340 1, /* can_bundle */
1341 {
1342 /* operands */
1343 { 0, },
1344 { 10, 20 },
1345 { 0, },
1346 { 0, },
1347 { 0, }
1348 },
1349 {
1350 /* fixed_bit_masks */
1351 0ULL,
1352 0xfc00000780000000ULL,
1353 0ULL,
1354 0ULL,
1355 0ULL
1356 },
1357 {
1358 /* fixed_bit_values */
1359 -1ULL,
1360 0x2800000700000000ULL,
1361 -1ULL,
1362 -1ULL,
1363 -1ULL
1364 }
1365 }, 159 },
1366 { "bbns.sn", TILE_OPC_BBNS_SN, 0x2 /* pipes */, 2 /* num_operands */, 160 { "bbns", TILE_OPC_BBNS, 0x2, 2, TREG_ZERO, 1,
1367 TREG_SN, /* implicitly_written_register */ 161 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1368 1, /* can_bundle */
1369 {
1370 /* operands */
1371 { 0, },
1372 { 10, 20 },
1373 { 0, },
1374 { 0, },
1375 { 0, }
1376 },
1377 {
1378 /* fixed_bit_masks */
1379 0ULL,
1380 0xfc00000780000000ULL,
1381 0ULL,
1382 0ULL,
1383 0ULL
1384 },
1385 {
1386 /* fixed_bit_values */
1387 -1ULL,
1388 0x2c00000700000000ULL,
1389 -1ULL,
1390 -1ULL,
1391 -1ULL
1392 }
1393 }, 162 },
1394 { "bbnst", TILE_OPC_BBNST, 0x2 /* pipes */, 2 /* num_operands */, 163 { "bbns.sn", TILE_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1,
1395 TREG_ZERO, /* implicitly_written_register */ 164 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1396 1, /* can_bundle */
1397 {
1398 /* operands */
1399 { 0, },
1400 { 10, 20 },
1401 { 0, },
1402 { 0, },
1403 { 0, }
1404 },
1405 {
1406 /* fixed_bit_masks */
1407 0ULL,
1408 0xfc00000780000000ULL,
1409 0ULL,
1410 0ULL,
1411 0ULL
1412 },
1413 {
1414 /* fixed_bit_values */
1415 -1ULL,
1416 0x2800000780000000ULL,
1417 -1ULL,
1418 -1ULL,
1419 -1ULL
1420 }
1421 }, 165 },
1422 { "bbnst.sn", TILE_OPC_BBNST_SN, 0x2 /* pipes */, 2 /* num_operands */, 166 { "bbnst", TILE_OPC_BBNST, 0x2, 2, TREG_ZERO, 1,
1423 TREG_SN, /* implicitly_written_register */ 167 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1424 1, /* can_bundle */
1425 {
1426 /* operands */
1427 { 0, },
1428 { 10, 20 },
1429 { 0, },
1430 { 0, },
1431 { 0, }
1432 },
1433 {
1434 /* fixed_bit_masks */
1435 0ULL,
1436 0xfc00000780000000ULL,
1437 0ULL,
1438 0ULL,
1439 0ULL
1440 },
1441 {
1442 /* fixed_bit_values */
1443 -1ULL,
1444 0x2c00000780000000ULL,
1445 -1ULL,
1446 -1ULL,
1447 -1ULL
1448 }
1449 }, 168 },
1450 { "bbs", TILE_OPC_BBS, 0x2 /* pipes */, 2 /* num_operands */, 169 { "bbnst.sn", TILE_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1,
1451 TREG_ZERO, /* implicitly_written_register */ 170 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1452 1, /* can_bundle */
1453 {
1454 /* operands */
1455 { 0, },
1456 { 10, 20 },
1457 { 0, },
1458 { 0, },
1459 { 0, }
1460 },
1461 {
1462 /* fixed_bit_masks */
1463 0ULL,
1464 0xfc00000780000000ULL,
1465 0ULL,
1466 0ULL,
1467 0ULL
1468 },
1469 {
1470 /* fixed_bit_values */
1471 -1ULL,
1472 0x2800000600000000ULL,
1473 -1ULL,
1474 -1ULL,
1475 -1ULL
1476 }
1477 }, 171 },
1478 { "bbs.sn", TILE_OPC_BBS_SN, 0x2 /* pipes */, 2 /* num_operands */, 172 { "bbs", TILE_OPC_BBS, 0x2, 2, TREG_ZERO, 1,
1479 TREG_SN, /* implicitly_written_register */ 173 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1480 1, /* can_bundle */
1481 {
1482 /* operands */
1483 { 0, },
1484 { 10, 20 },
1485 { 0, },
1486 { 0, },
1487 { 0, }
1488 },
1489 {
1490 /* fixed_bit_masks */
1491 0ULL,
1492 0xfc00000780000000ULL,
1493 0ULL,
1494 0ULL,
1495 0ULL
1496 },
1497 {
1498 /* fixed_bit_values */
1499 -1ULL,
1500 0x2c00000600000000ULL,
1501 -1ULL,
1502 -1ULL,
1503 -1ULL
1504 }
1505 }, 174 },
1506 { "bbst", TILE_OPC_BBST, 0x2 /* pipes */, 2 /* num_operands */, 175 { "bbs.sn", TILE_OPC_BBS_SN, 0x2, 2, TREG_SN, 1,
1507 TREG_ZERO, /* implicitly_written_register */ 176 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1508 1, /* can_bundle */
1509 {
1510 /* operands */
1511 { 0, },
1512 { 10, 20 },
1513 { 0, },
1514 { 0, },
1515 { 0, }
1516 },
1517 {
1518 /* fixed_bit_masks */
1519 0ULL,
1520 0xfc00000780000000ULL,
1521 0ULL,
1522 0ULL,
1523 0ULL
1524 },
1525 {
1526 /* fixed_bit_values */
1527 -1ULL,
1528 0x2800000680000000ULL,
1529 -1ULL,
1530 -1ULL,
1531 -1ULL
1532 }
1533 }, 177 },
1534 { "bbst.sn", TILE_OPC_BBST_SN, 0x2 /* pipes */, 2 /* num_operands */, 178 { "bbst", TILE_OPC_BBST, 0x2, 2, TREG_ZERO, 1,
1535 TREG_SN, /* implicitly_written_register */ 179 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1536 1, /* can_bundle */
1537 {
1538 /* operands */
1539 { 0, },
1540 { 10, 20 },
1541 { 0, },
1542 { 0, },
1543 { 0, }
1544 },
1545 {
1546 /* fixed_bit_masks */
1547 0ULL,
1548 0xfc00000780000000ULL,
1549 0ULL,
1550 0ULL,
1551 0ULL
1552 },
1553 {
1554 /* fixed_bit_values */
1555 -1ULL,
1556 0x2c00000680000000ULL,
1557 -1ULL,
1558 -1ULL,
1559 -1ULL
1560 }
1561 }, 180 },
1562 { "bgez", TILE_OPC_BGEZ, 0x2 /* pipes */, 2 /* num_operands */, 181 { "bbst.sn", TILE_OPC_BBST_SN, 0x2, 2, TREG_SN, 1,
1563 TREG_ZERO, /* implicitly_written_register */ 182 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1564 1, /* can_bundle */
1565 {
1566 /* operands */
1567 { 0, },
1568 { 10, 20 },
1569 { 0, },
1570 { 0, },
1571 { 0, }
1572 },
1573 {
1574 /* fixed_bit_masks */
1575 0ULL,
1576 0xfc00000780000000ULL,
1577 0ULL,
1578 0ULL,
1579 0ULL
1580 },
1581 {
1582 /* fixed_bit_values */
1583 -1ULL,
1584 0x2800000300000000ULL,
1585 -1ULL,
1586 -1ULL,
1587 -1ULL
1588 }
1589 }, 183 },
1590 { "bgez.sn", TILE_OPC_BGEZ_SN, 0x2 /* pipes */, 2 /* num_operands */, 184 { "bgez", TILE_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
1591 TREG_SN, /* implicitly_written_register */ 185 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1592 1, /* can_bundle */
1593 {
1594 /* operands */
1595 { 0, },
1596 { 10, 20 },
1597 { 0, },
1598 { 0, },
1599 { 0, }
1600 },
1601 {
1602 /* fixed_bit_masks */
1603 0ULL,
1604 0xfc00000780000000ULL,
1605 0ULL,
1606 0ULL,
1607 0ULL
1608 },
1609 {
1610 /* fixed_bit_values */
1611 -1ULL,
1612 0x2c00000300000000ULL,
1613 -1ULL,
1614 -1ULL,
1615 -1ULL
1616 }
1617 }, 186 },
1618 { "bgezt", TILE_OPC_BGEZT, 0x2 /* pipes */, 2 /* num_operands */, 187 { "bgez.sn", TILE_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1,
1619 TREG_ZERO, /* implicitly_written_register */ 188 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1620 1, /* can_bundle */
1621 {
1622 /* operands */
1623 { 0, },
1624 { 10, 20 },
1625 { 0, },
1626 { 0, },
1627 { 0, }
1628 },
1629 {
1630 /* fixed_bit_masks */
1631 0ULL,
1632 0xfc00000780000000ULL,
1633 0ULL,
1634 0ULL,
1635 0ULL
1636 },
1637 {
1638 /* fixed_bit_values */
1639 -1ULL,
1640 0x2800000380000000ULL,
1641 -1ULL,
1642 -1ULL,
1643 -1ULL
1644 }
1645 }, 189 },
1646 { "bgezt.sn", TILE_OPC_BGEZT_SN, 0x2 /* pipes */, 2 /* num_operands */, 190 { "bgezt", TILE_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
1647 TREG_SN, /* implicitly_written_register */ 191 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1648 1, /* can_bundle */
1649 {
1650 /* operands */
1651 { 0, },
1652 { 10, 20 },
1653 { 0, },
1654 { 0, },
1655 { 0, }
1656 },
1657 {
1658 /* fixed_bit_masks */
1659 0ULL,
1660 0xfc00000780000000ULL,
1661 0ULL,
1662 0ULL,
1663 0ULL
1664 },
1665 {
1666 /* fixed_bit_values */
1667 -1ULL,
1668 0x2c00000380000000ULL,
1669 -1ULL,
1670 -1ULL,
1671 -1ULL
1672 }
1673 }, 192 },
1674 { "bgz", TILE_OPC_BGZ, 0x2 /* pipes */, 2 /* num_operands */, 193 { "bgezt.sn", TILE_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1,
1675 TREG_ZERO, /* implicitly_written_register */ 194 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1676 1, /* can_bundle */
1677 {
1678 /* operands */
1679 { 0, },
1680 { 10, 20 },
1681 { 0, },
1682 { 0, },
1683 { 0, }
1684 },
1685 {
1686 /* fixed_bit_masks */
1687 0ULL,
1688 0xfc00000780000000ULL,
1689 0ULL,
1690 0ULL,
1691 0ULL
1692 },
1693 {
1694 /* fixed_bit_values */
1695 -1ULL,
1696 0x2800000200000000ULL,
1697 -1ULL,
1698 -1ULL,
1699 -1ULL
1700 }
1701 }, 195 },
1702 { "bgz.sn", TILE_OPC_BGZ_SN, 0x2 /* pipes */, 2 /* num_operands */, 196 { "bgz", TILE_OPC_BGZ, 0x2, 2, TREG_ZERO, 1,
1703 TREG_SN, /* implicitly_written_register */ 197 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1704 1, /* can_bundle */
1705 {
1706 /* operands */
1707 { 0, },
1708 { 10, 20 },
1709 { 0, },
1710 { 0, },
1711 { 0, }
1712 },
1713 {
1714 /* fixed_bit_masks */
1715 0ULL,
1716 0xfc00000780000000ULL,
1717 0ULL,
1718 0ULL,
1719 0ULL
1720 },
1721 {
1722 /* fixed_bit_values */
1723 -1ULL,
1724 0x2c00000200000000ULL,
1725 -1ULL,
1726 -1ULL,
1727 -1ULL
1728 }
1729 }, 198 },
1730 { "bgzt", TILE_OPC_BGZT, 0x2 /* pipes */, 2 /* num_operands */, 199 { "bgz.sn", TILE_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1,
1731 TREG_ZERO, /* implicitly_written_register */ 200 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1732 1, /* can_bundle */
1733 {
1734 /* operands */
1735 { 0, },
1736 { 10, 20 },
1737 { 0, },
1738 { 0, },
1739 { 0, }
1740 },
1741 {
1742 /* fixed_bit_masks */
1743 0ULL,
1744 0xfc00000780000000ULL,
1745 0ULL,
1746 0ULL,
1747 0ULL
1748 },
1749 {
1750 /* fixed_bit_values */
1751 -1ULL,
1752 0x2800000280000000ULL,
1753 -1ULL,
1754 -1ULL,
1755 -1ULL
1756 }
1757 }, 201 },
1758 { "bgzt.sn", TILE_OPC_BGZT_SN, 0x2 /* pipes */, 2 /* num_operands */, 202 { "bgzt", TILE_OPC_BGZT, 0x2, 2, TREG_ZERO, 1,
1759 TREG_SN, /* implicitly_written_register */ 203 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1760 1, /* can_bundle */
1761 {
1762 /* operands */
1763 { 0, },
1764 { 10, 20 },
1765 { 0, },
1766 { 0, },
1767 { 0, }
1768 },
1769 {
1770 /* fixed_bit_masks */
1771 0ULL,
1772 0xfc00000780000000ULL,
1773 0ULL,
1774 0ULL,
1775 0ULL
1776 },
1777 {
1778 /* fixed_bit_values */
1779 -1ULL,
1780 0x2c00000280000000ULL,
1781 -1ULL,
1782 -1ULL,
1783 -1ULL
1784 }
1785 }, 204 },
1786 { "bitx", TILE_OPC_BITX, 0x5 /* pipes */, 2 /* num_operands */, 205 { "bgzt.sn", TILE_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1,
1787 TREG_ZERO, /* implicitly_written_register */ 206 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1788 1, /* can_bundle */
1789 {
1790 /* operands */
1791 { 7, 8 },
1792 { 0, },
1793 { 11, 12 },
1794 { 0, },
1795 { 0, }
1796 },
1797 {
1798 /* fixed_bit_masks */
1799 0x800000007ffff000ULL,
1800 0ULL,
1801 0x80000000780ff000ULL,
1802 0ULL,
1803 0ULL
1804 },
1805 {
1806 /* fixed_bit_values */
1807 0x0000000070161000ULL,
1808 -1ULL,
1809 0x80000000680a1000ULL,
1810 -1ULL,
1811 -1ULL
1812 }
1813 }, 207 },
1814 { "bitx.sn", TILE_OPC_BITX_SN, 0x1 /* pipes */, 2 /* num_operands */, 208 { "bitx", TILE_OPC_BITX, 0x5, 2, TREG_ZERO, 1,
1815 TREG_SN, /* implicitly_written_register */ 209 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
1816 1, /* can_bundle */
1817 {
1818 /* operands */
1819 { 7, 8 },
1820 { 0, },
1821 { 0, },
1822 { 0, },
1823 { 0, }
1824 },
1825 {
1826 /* fixed_bit_masks */
1827 0x800000007ffff000ULL,
1828 0ULL,
1829 0ULL,
1830 0ULL,
1831 0ULL
1832 },
1833 {
1834 /* fixed_bit_values */
1835 0x0000000078161000ULL,
1836 -1ULL,
1837 -1ULL,
1838 -1ULL,
1839 -1ULL
1840 }
1841 }, 210 },
1842 { "blez", TILE_OPC_BLEZ, 0x2 /* pipes */, 2 /* num_operands */, 211 { "bitx.sn", TILE_OPC_BITX_SN, 0x1, 2, TREG_SN, 1,
1843 TREG_ZERO, /* implicitly_written_register */ 212 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
1844 1, /* can_bundle */
1845 {
1846 /* operands */
1847 { 0, },
1848 { 10, 20 },
1849 { 0, },
1850 { 0, },
1851 { 0, }
1852 },
1853 {
1854 /* fixed_bit_masks */
1855 0ULL,
1856 0xfc00000780000000ULL,
1857 0ULL,
1858 0ULL,
1859 0ULL
1860 },
1861 {
1862 /* fixed_bit_values */
1863 -1ULL,
1864 0x2800000500000000ULL,
1865 -1ULL,
1866 -1ULL,
1867 -1ULL
1868 }
1869 }, 213 },
1870 { "blez.sn", TILE_OPC_BLEZ_SN, 0x2 /* pipes */, 2 /* num_operands */, 214 { "blez", TILE_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
1871 TREG_SN, /* implicitly_written_register */ 215 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1872 1, /* can_bundle */
1873 {
1874 /* operands */
1875 { 0, },
1876 { 10, 20 },
1877 { 0, },
1878 { 0, },
1879 { 0, }
1880 },
1881 {
1882 /* fixed_bit_masks */
1883 0ULL,
1884 0xfc00000780000000ULL,
1885 0ULL,
1886 0ULL,
1887 0ULL
1888 },
1889 {
1890 /* fixed_bit_values */
1891 -1ULL,
1892 0x2c00000500000000ULL,
1893 -1ULL,
1894 -1ULL,
1895 -1ULL
1896 }
1897 }, 216 },
1898 { "blezt", TILE_OPC_BLEZT, 0x2 /* pipes */, 2 /* num_operands */, 217 { "blez.sn", TILE_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1,
1899 TREG_ZERO, /* implicitly_written_register */ 218 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1900 1, /* can_bundle */
1901 {
1902 /* operands */
1903 { 0, },
1904 { 10, 20 },
1905 { 0, },
1906 { 0, },
1907 { 0, }
1908 },
1909 {
1910 /* fixed_bit_masks */
1911 0ULL,
1912 0xfc00000780000000ULL,
1913 0ULL,
1914 0ULL,
1915 0ULL
1916 },
1917 {
1918 /* fixed_bit_values */
1919 -1ULL,
1920 0x2800000580000000ULL,
1921 -1ULL,
1922 -1ULL,
1923 -1ULL
1924 }
1925 }, 219 },
1926 { "blezt.sn", TILE_OPC_BLEZT_SN, 0x2 /* pipes */, 2 /* num_operands */, 220 { "blezt", TILE_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
1927 TREG_SN, /* implicitly_written_register */ 221 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1928 1, /* can_bundle */
1929 {
1930 /* operands */
1931 { 0, },
1932 { 10, 20 },
1933 { 0, },
1934 { 0, },
1935 { 0, }
1936 },
1937 {
1938 /* fixed_bit_masks */
1939 0ULL,
1940 0xfc00000780000000ULL,
1941 0ULL,
1942 0ULL,
1943 0ULL
1944 },
1945 {
1946 /* fixed_bit_values */
1947 -1ULL,
1948 0x2c00000580000000ULL,
1949 -1ULL,
1950 -1ULL,
1951 -1ULL
1952 }
1953 }, 222 },
1954 { "blz", TILE_OPC_BLZ, 0x2 /* pipes */, 2 /* num_operands */, 223 { "blezt.sn", TILE_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1,
1955 TREG_ZERO, /* implicitly_written_register */ 224 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1956 1, /* can_bundle */
1957 {
1958 /* operands */
1959 { 0, },
1960 { 10, 20 },
1961 { 0, },
1962 { 0, },
1963 { 0, }
1964 },
1965 {
1966 /* fixed_bit_masks */
1967 0ULL,
1968 0xfc00000780000000ULL,
1969 0ULL,
1970 0ULL,
1971 0ULL
1972 },
1973 {
1974 /* fixed_bit_values */
1975 -1ULL,
1976 0x2800000400000000ULL,
1977 -1ULL,
1978 -1ULL,
1979 -1ULL
1980 }
1981 }, 225 },
1982 { "blz.sn", TILE_OPC_BLZ_SN, 0x2 /* pipes */, 2 /* num_operands */, 226 { "blz", TILE_OPC_BLZ, 0x2, 2, TREG_ZERO, 1,
1983 TREG_SN, /* implicitly_written_register */ 227 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
1984 1, /* can_bundle */
1985 {
1986 /* operands */
1987 { 0, },
1988 { 10, 20 },
1989 { 0, },
1990 { 0, },
1991 { 0, }
1992 },
1993 {
1994 /* fixed_bit_masks */
1995 0ULL,
1996 0xfc00000780000000ULL,
1997 0ULL,
1998 0ULL,
1999 0ULL
2000 },
2001 {
2002 /* fixed_bit_values */
2003 -1ULL,
2004 0x2c00000400000000ULL,
2005 -1ULL,
2006 -1ULL,
2007 -1ULL
2008 }
2009 }, 228 },
2010 { "blzt", TILE_OPC_BLZT, 0x2 /* pipes */, 2 /* num_operands */, 229 { "blz.sn", TILE_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1,
2011 TREG_ZERO, /* implicitly_written_register */ 230 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2012 1, /* can_bundle */
2013 {
2014 /* operands */
2015 { 0, },
2016 { 10, 20 },
2017 { 0, },
2018 { 0, },
2019 { 0, }
2020 },
2021 {
2022 /* fixed_bit_masks */
2023 0ULL,
2024 0xfc00000780000000ULL,
2025 0ULL,
2026 0ULL,
2027 0ULL
2028 },
2029 {
2030 /* fixed_bit_values */
2031 -1ULL,
2032 0x2800000480000000ULL,
2033 -1ULL,
2034 -1ULL,
2035 -1ULL
2036 }
2037 }, 231 },
2038 { "blzt.sn", TILE_OPC_BLZT_SN, 0x2 /* pipes */, 2 /* num_operands */, 232 { "blzt", TILE_OPC_BLZT, 0x2, 2, TREG_ZERO, 1,
2039 TREG_SN, /* implicitly_written_register */ 233 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2040 1, /* can_bundle */
2041 {
2042 /* operands */
2043 { 0, },
2044 { 10, 20 },
2045 { 0, },
2046 { 0, },
2047 { 0, }
2048 },
2049 {
2050 /* fixed_bit_masks */
2051 0ULL,
2052 0xfc00000780000000ULL,
2053 0ULL,
2054 0ULL,
2055 0ULL
2056 },
2057 {
2058 /* fixed_bit_values */
2059 -1ULL,
2060 0x2c00000480000000ULL,
2061 -1ULL,
2062 -1ULL,
2063 -1ULL
2064 }
2065 }, 234 },
2066 { "bnz", TILE_OPC_BNZ, 0x2 /* pipes */, 2 /* num_operands */, 235 { "blzt.sn", TILE_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1,
2067 TREG_ZERO, /* implicitly_written_register */ 236 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2068 1, /* can_bundle */
2069 {
2070 /* operands */
2071 { 0, },
2072 { 10, 20 },
2073 { 0, },
2074 { 0, },
2075 { 0, }
2076 },
2077 {
2078 /* fixed_bit_masks */
2079 0ULL,
2080 0xfc00000780000000ULL,
2081 0ULL,
2082 0ULL,
2083 0ULL
2084 },
2085 {
2086 /* fixed_bit_values */
2087 -1ULL,
2088 0x2800000100000000ULL,
2089 -1ULL,
2090 -1ULL,
2091 -1ULL
2092 }
2093 }, 237 },
2094 { "bnz.sn", TILE_OPC_BNZ_SN, 0x2 /* pipes */, 2 /* num_operands */, 238 { "bnz", TILE_OPC_BNZ, 0x2, 2, TREG_ZERO, 1,
2095 TREG_SN, /* implicitly_written_register */ 239 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2096 1, /* can_bundle */
2097 {
2098 /* operands */
2099 { 0, },
2100 { 10, 20 },
2101 { 0, },
2102 { 0, },
2103 { 0, }
2104 },
2105 {
2106 /* fixed_bit_masks */
2107 0ULL,
2108 0xfc00000780000000ULL,
2109 0ULL,
2110 0ULL,
2111 0ULL
2112 },
2113 {
2114 /* fixed_bit_values */
2115 -1ULL,
2116 0x2c00000100000000ULL,
2117 -1ULL,
2118 -1ULL,
2119 -1ULL
2120 }
2121 }, 240 },
2122 { "bnzt", TILE_OPC_BNZT, 0x2 /* pipes */, 2 /* num_operands */, 241 { "bnz.sn", TILE_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1,
2123 TREG_ZERO, /* implicitly_written_register */ 242 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2124 1, /* can_bundle */
2125 {
2126 /* operands */
2127 { 0, },
2128 { 10, 20 },
2129 { 0, },
2130 { 0, },
2131 { 0, }
2132 },
2133 {
2134 /* fixed_bit_masks */
2135 0ULL,
2136 0xfc00000780000000ULL,
2137 0ULL,
2138 0ULL,
2139 0ULL
2140 },
2141 {
2142 /* fixed_bit_values */
2143 -1ULL,
2144 0x2800000180000000ULL,
2145 -1ULL,
2146 -1ULL,
2147 -1ULL
2148 }
2149 }, 243 },
2150 { "bnzt.sn", TILE_OPC_BNZT_SN, 0x2 /* pipes */, 2 /* num_operands */, 244 { "bnzt", TILE_OPC_BNZT, 0x2, 2, TREG_ZERO, 1,
2151 TREG_SN, /* implicitly_written_register */ 245 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2152 1, /* can_bundle */
2153 {
2154 /* operands */
2155 { 0, },
2156 { 10, 20 },
2157 { 0, },
2158 { 0, },
2159 { 0, }
2160 },
2161 {
2162 /* fixed_bit_masks */
2163 0ULL,
2164 0xfc00000780000000ULL,
2165 0ULL,
2166 0ULL,
2167 0ULL
2168 },
2169 {
2170 /* fixed_bit_values */
2171 -1ULL,
2172 0x2c00000180000000ULL,
2173 -1ULL,
2174 -1ULL,
2175 -1ULL
2176 }
2177 }, 246 },
2178 { "bytex", TILE_OPC_BYTEX, 0x5 /* pipes */, 2 /* num_operands */, 247 { "bnzt.sn", TILE_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1,
2179 TREG_ZERO, /* implicitly_written_register */ 248 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2180 1, /* can_bundle */
2181 {
2182 /* operands */
2183 { 7, 8 },
2184 { 0, },
2185 { 11, 12 },
2186 { 0, },
2187 { 0, }
2188 },
2189 {
2190 /* fixed_bit_masks */
2191 0x800000007ffff000ULL,
2192 0ULL,
2193 0x80000000780ff000ULL,
2194 0ULL,
2195 0ULL
2196 },
2197 {
2198 /* fixed_bit_values */
2199 0x0000000070162000ULL,
2200 -1ULL,
2201 0x80000000680a2000ULL,
2202 -1ULL,
2203 -1ULL
2204 }
2205 }, 249 },
2206 { "bytex.sn", TILE_OPC_BYTEX_SN, 0x1 /* pipes */, 2 /* num_operands */, 250 { "bytex", TILE_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1,
2207 TREG_SN, /* implicitly_written_register */ 251 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
2208 1, /* can_bundle */
2209 {
2210 /* operands */
2211 { 7, 8 },
2212 { 0, },
2213 { 0, },
2214 { 0, },
2215 { 0, }
2216 },
2217 {
2218 /* fixed_bit_masks */
2219 0x800000007ffff000ULL,
2220 0ULL,
2221 0ULL,
2222 0ULL,
2223 0ULL
2224 },
2225 {
2226 /* fixed_bit_values */
2227 0x0000000078162000ULL,
2228 -1ULL,
2229 -1ULL,
2230 -1ULL,
2231 -1ULL
2232 }
2233 }, 252 },
2234 { "bz", TILE_OPC_BZ, 0x2 /* pipes */, 2 /* num_operands */, 253 { "bytex.sn", TILE_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1,
2235 TREG_ZERO, /* implicitly_written_register */ 254 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
2236 1, /* can_bundle */
2237 {
2238 /* operands */
2239 { 0, },
2240 { 10, 20 },
2241 { 0, },
2242 { 0, },
2243 { 0, }
2244 },
2245 {
2246 /* fixed_bit_masks */
2247 0ULL,
2248 0xfc00000780000000ULL,
2249 0ULL,
2250 0ULL,
2251 0ULL
2252 },
2253 {
2254 /* fixed_bit_values */
2255 -1ULL,
2256 0x2800000000000000ULL,
2257 -1ULL,
2258 -1ULL,
2259 -1ULL
2260 }
2261 }, 255 },
2262 { "bz.sn", TILE_OPC_BZ_SN, 0x2 /* pipes */, 2 /* num_operands */, 256 { "bz", TILE_OPC_BZ, 0x2, 2, TREG_ZERO, 1,
2263 TREG_SN, /* implicitly_written_register */ 257 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2264 1, /* can_bundle */
2265 {
2266 /* operands */
2267 { 0, },
2268 { 10, 20 },
2269 { 0, },
2270 { 0, },
2271 { 0, }
2272 },
2273 {
2274 /* fixed_bit_masks */
2275 0ULL,
2276 0xfc00000780000000ULL,
2277 0ULL,
2278 0ULL,
2279 0ULL
2280 },
2281 {
2282 /* fixed_bit_values */
2283 -1ULL,
2284 0x2c00000000000000ULL,
2285 -1ULL,
2286 -1ULL,
2287 -1ULL
2288 }
2289 }, 258 },
2290 { "bzt", TILE_OPC_BZT, 0x2 /* pipes */, 2 /* num_operands */, 259 { "bz.sn", TILE_OPC_BZ_SN, 0x2, 2, TREG_SN, 1,
2291 TREG_ZERO, /* implicitly_written_register */ 260 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2292 1, /* can_bundle */
2293 {
2294 /* operands */
2295 { 0, },
2296 { 10, 20 },
2297 { 0, },
2298 { 0, },
2299 { 0, }
2300 },
2301 {
2302 /* fixed_bit_masks */
2303 0ULL,
2304 0xfc00000780000000ULL,
2305 0ULL,
2306 0ULL,
2307 0ULL
2308 },
2309 {
2310 /* fixed_bit_values */
2311 -1ULL,
2312 0x2800000080000000ULL,
2313 -1ULL,
2314 -1ULL,
2315 -1ULL
2316 }
2317 }, 261 },
2318 { "bzt.sn", TILE_OPC_BZT_SN, 0x2 /* pipes */, 2 /* num_operands */, 262 { "bzt", TILE_OPC_BZT, 0x2, 2, TREG_ZERO, 1,
2319 TREG_SN, /* implicitly_written_register */ 263 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2320 1, /* can_bundle */
2321 {
2322 /* operands */
2323 { 0, },
2324 { 10, 20 },
2325 { 0, },
2326 { 0, },
2327 { 0, }
2328 },
2329 {
2330 /* fixed_bit_masks */
2331 0ULL,
2332 0xfc00000780000000ULL,
2333 0ULL,
2334 0ULL,
2335 0ULL
2336 },
2337 {
2338 /* fixed_bit_values */
2339 -1ULL,
2340 0x2c00000080000000ULL,
2341 -1ULL,
2342 -1ULL,
2343 -1ULL
2344 }
2345 }, 264 },
2346 { "clz", TILE_OPC_CLZ, 0x5 /* pipes */, 2 /* num_operands */, 265 { "bzt.sn", TILE_OPC_BZT_SN, 0x2, 2, TREG_SN, 1,
2347 TREG_ZERO, /* implicitly_written_register */ 266 { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
2348 1, /* can_bundle */
2349 {
2350 /* operands */
2351 { 7, 8 },
2352 { 0, },
2353 { 11, 12 },
2354 { 0, },
2355 { 0, }
2356 },
2357 {
2358 /* fixed_bit_masks */
2359 0x800000007ffff000ULL,
2360 0ULL,
2361 0x80000000780ff000ULL,
2362 0ULL,
2363 0ULL
2364 },
2365 {
2366 /* fixed_bit_values */
2367 0x0000000070163000ULL,
2368 -1ULL,
2369 0x80000000680a3000ULL,
2370 -1ULL,
2371 -1ULL
2372 }
2373 }, 267 },
2374 { "clz.sn", TILE_OPC_CLZ_SN, 0x1 /* pipes */, 2 /* num_operands */, 268 { "clz", TILE_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
2375 TREG_SN, /* implicitly_written_register */ 269 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
2376 1, /* can_bundle */
2377 {
2378 /* operands */
2379 { 7, 8 },
2380 { 0, },
2381 { 0, },
2382 { 0, },
2383 { 0, }
2384 },
2385 {
2386 /* fixed_bit_masks */
2387 0x800000007ffff000ULL,
2388 0ULL,
2389 0ULL,
2390 0ULL,
2391 0ULL
2392 },
2393 {
2394 /* fixed_bit_values */
2395 0x0000000078163000ULL,
2396 -1ULL,
2397 -1ULL,
2398 -1ULL,
2399 -1ULL
2400 }
2401 }, 270 },
2402 { "crc32_32", TILE_OPC_CRC32_32, 0x1 /* pipes */, 3 /* num_operands */, 271 { "clz.sn", TILE_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1,
2403 TREG_ZERO, /* implicitly_written_register */ 272 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
2404 1, /* can_bundle */
2405 {
2406 /* operands */
2407 { 7, 8, 16 },
2408 { 0, },
2409 { 0, },
2410 { 0, },
2411 { 0, }
2412 },
2413 {
2414 /* fixed_bit_masks */
2415 0x800000007ffc0000ULL,
2416 0ULL,
2417 0ULL,
2418 0ULL,
2419 0ULL
2420 },
2421 {
2422 /* fixed_bit_values */
2423 0x0000000000240000ULL,
2424 -1ULL,
2425 -1ULL,
2426 -1ULL,
2427 -1ULL
2428 }
2429 }, 273 },
2430 { "crc32_32.sn", TILE_OPC_CRC32_32_SN, 0x1 /* pipes */, 3 /* num_operands */, 274 { "crc32_32", TILE_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
2431 TREG_SN, /* implicitly_written_register */ 275 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
2432 1, /* can_bundle */
2433 {
2434 /* operands */
2435 { 7, 8, 16 },
2436 { 0, },
2437 { 0, },
2438 { 0, },
2439 { 0, }
2440 },
2441 {
2442 /* fixed_bit_masks */
2443 0x800000007ffc0000ULL,
2444 0ULL,
2445 0ULL,
2446 0ULL,
2447 0ULL
2448 },
2449 {
2450 /* fixed_bit_values */
2451 0x0000000008240000ULL,
2452 -1ULL,
2453 -1ULL,
2454 -1ULL,
2455 -1ULL
2456 }
2457 }, 276 },
2458 { "crc32_8", TILE_OPC_CRC32_8, 0x1 /* pipes */, 3 /* num_operands */, 277 { "crc32_32.sn", TILE_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1,
2459 TREG_ZERO, /* implicitly_written_register */ 278 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
2460 1, /* can_bundle */
2461 {
2462 /* operands */
2463 { 7, 8, 16 },
2464 { 0, },
2465 { 0, },
2466 { 0, },
2467 { 0, }
2468 },
2469 {
2470 /* fixed_bit_masks */
2471 0x800000007ffc0000ULL,
2472 0ULL,
2473 0ULL,
2474 0ULL,
2475 0ULL
2476 },
2477 {
2478 /* fixed_bit_values */
2479 0x0000000000280000ULL,
2480 -1ULL,
2481 -1ULL,
2482 -1ULL,
2483 -1ULL
2484 }
2485 }, 279 },
2486 { "crc32_8.sn", TILE_OPC_CRC32_8_SN, 0x1 /* pipes */, 3 /* num_operands */, 280 { "crc32_8", TILE_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
2487 TREG_SN, /* implicitly_written_register */ 281 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
2488 1, /* can_bundle */
2489 {
2490 /* operands */
2491 { 7, 8, 16 },
2492 { 0, },
2493 { 0, },
2494 { 0, },
2495 { 0, }
2496 },
2497 {
2498 /* fixed_bit_masks */
2499 0x800000007ffc0000ULL,
2500 0ULL,
2501 0ULL,
2502 0ULL,
2503 0ULL
2504 },
2505 {
2506 /* fixed_bit_values */
2507 0x0000000008280000ULL,
2508 -1ULL,
2509 -1ULL,
2510 -1ULL,
2511 -1ULL
2512 }
2513 }, 282 },
2514 { "ctz", TILE_OPC_CTZ, 0x5 /* pipes */, 2 /* num_operands */, 283 { "crc32_8.sn", TILE_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1,
2515 TREG_ZERO, /* implicitly_written_register */ 284 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
2516 1, /* can_bundle */
2517 {
2518 /* operands */
2519 { 7, 8 },
2520 { 0, },
2521 { 11, 12 },
2522 { 0, },
2523 { 0, }
2524 },
2525 {
2526 /* fixed_bit_masks */
2527 0x800000007ffff000ULL,
2528 0ULL,
2529 0x80000000780ff000ULL,
2530 0ULL,
2531 0ULL
2532 },
2533 {
2534 /* fixed_bit_values */
2535 0x0000000070164000ULL,
2536 -1ULL,
2537 0x80000000680a4000ULL,
2538 -1ULL,
2539 -1ULL
2540 }
2541 }, 285 },
2542 { "ctz.sn", TILE_OPC_CTZ_SN, 0x1 /* pipes */, 2 /* num_operands */, 286 { "ctz", TILE_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
2543 TREG_SN, /* implicitly_written_register */ 287 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
2544 1, /* can_bundle */
2545 {
2546 /* operands */
2547 { 7, 8 },
2548 { 0, },
2549 { 0, },
2550 { 0, },
2551 { 0, }
2552 },
2553 {
2554 /* fixed_bit_masks */
2555 0x800000007ffff000ULL,
2556 0ULL,
2557 0ULL,
2558 0ULL,
2559 0ULL
2560 },
2561 {
2562 /* fixed_bit_values */
2563 0x0000000078164000ULL,
2564 -1ULL,
2565 -1ULL,
2566 -1ULL,
2567 -1ULL
2568 }
2569 }, 288 },
2570 { "drain", TILE_OPC_DRAIN, 0x2 /* pipes */, 0 /* num_operands */, 289 { "ctz.sn", TILE_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1,
2571 TREG_ZERO, /* implicitly_written_register */ 290 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
2572 0, /* can_bundle */
2573 {
2574 /* operands */
2575 { 0, },
2576 { },
2577 { 0, },
2578 { 0, },
2579 { 0, }
2580 },
2581 {
2582 /* fixed_bit_masks */
2583 0ULL,
2584 0xfbfff80000000000ULL,
2585 0ULL,
2586 0ULL,
2587 0ULL
2588 },
2589 {
2590 /* fixed_bit_values */
2591 -1ULL,
2592 0x400b080000000000ULL,
2593 -1ULL,
2594 -1ULL,
2595 -1ULL
2596 }
2597 }, 291 },
2598 { "dtlbpr", TILE_OPC_DTLBPR, 0x2 /* pipes */, 1 /* num_operands */, 292 { "drain", TILE_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
2599 TREG_ZERO, /* implicitly_written_register */ 293 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
2600 1, /* can_bundle */
2601 {
2602 /* operands */
2603 { 0, },
2604 { 10 },
2605 { 0, },
2606 { 0, },
2607 { 0, }
2608 },
2609 {
2610 /* fixed_bit_masks */
2611 0ULL,
2612 0xfbfff80000000000ULL,
2613 0ULL,
2614 0ULL,
2615 0ULL
2616 },
2617 {
2618 /* fixed_bit_values */
2619 -1ULL,
2620 0x400b100000000000ULL,
2621 -1ULL,
2622 -1ULL,
2623 -1ULL
2624 }
2625 }, 294 },
2626 { "dword_align", TILE_OPC_DWORD_ALIGN, 0x1 /* pipes */, 3 /* num_operands */, 295 { "dtlbpr", TILE_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
2627 TREG_ZERO, /* implicitly_written_register */ 296 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
2628 1, /* can_bundle */
2629 {
2630 /* operands */
2631 { 21, 8, 16 },
2632 { 0, },
2633 { 0, },
2634 { 0, },
2635 { 0, }
2636 },
2637 {
2638 /* fixed_bit_masks */
2639 0x800000007ffc0000ULL,
2640 0ULL,
2641 0ULL,
2642 0ULL,
2643 0ULL
2644 },
2645 {
2646 /* fixed_bit_values */
2647 0x00000000017c0000ULL,
2648 -1ULL,
2649 -1ULL,
2650 -1ULL,
2651 -1ULL
2652 }
2653 }, 297 },
2654 { "dword_align.sn", TILE_OPC_DWORD_ALIGN_SN, 0x1 /* pipes */, 3 /* num_operands */, 298 { "dword_align", TILE_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1,
2655 TREG_SN, /* implicitly_written_register */ 299 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
2656 1, /* can_bundle */
2657 {
2658 /* operands */
2659 { 21, 8, 16 },
2660 { 0, },
2661 { 0, },
2662 { 0, },
2663 { 0, }
2664 },
2665 {
2666 /* fixed_bit_masks */
2667 0x800000007ffc0000ULL,
2668 0ULL,
2669 0ULL,
2670 0ULL,
2671 0ULL
2672 },
2673 {
2674 /* fixed_bit_values */
2675 0x00000000097c0000ULL,
2676 -1ULL,
2677 -1ULL,
2678 -1ULL,
2679 -1ULL
2680 }
2681 }, 300 },
2682 { "finv", TILE_OPC_FINV, 0x2 /* pipes */, 1 /* num_operands */, 301 { "dword_align.sn", TILE_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1,
2683 TREG_ZERO, /* implicitly_written_register */ 302 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
2684 1, /* can_bundle */
2685 {
2686 /* operands */
2687 { 0, },
2688 { 10 },
2689 { 0, },
2690 { 0, },
2691 { 0, }
2692 },
2693 {
2694 /* fixed_bit_masks */
2695 0ULL,
2696 0xfbfff80000000000ULL,
2697 0ULL,
2698 0ULL,
2699 0ULL
2700 },
2701 {
2702 /* fixed_bit_values */
2703 -1ULL,
2704 0x400b180000000000ULL,
2705 -1ULL,
2706 -1ULL,
2707 -1ULL
2708 }
2709 }, 303 },
2710 { "flush", TILE_OPC_FLUSH, 0x2 /* pipes */, 1 /* num_operands */, 304 { "finv", TILE_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
2711 TREG_ZERO, /* implicitly_written_register */ 305 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
2712 1, /* can_bundle */
2713 {
2714 /* operands */
2715 { 0, },
2716 { 10 },
2717 { 0, },
2718 { 0, },
2719 { 0, }
2720 },
2721 {
2722 /* fixed_bit_masks */
2723 0ULL,
2724 0xfbfff80000000000ULL,
2725 0ULL,
2726 0ULL,
2727 0ULL
2728 },
2729 {
2730 /* fixed_bit_values */
2731 -1ULL,
2732 0x400b200000000000ULL,
2733 -1ULL,
2734 -1ULL,
2735 -1ULL
2736 }
2737 }, 306 },
2738 { "fnop", TILE_OPC_FNOP, 0xf /* pipes */, 0 /* num_operands */, 307 { "flush", TILE_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
2739 TREG_ZERO, /* implicitly_written_register */ 308 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
2740 1, /* can_bundle */
2741 {
2742 /* operands */
2743 { },
2744 { },
2745 { },
2746 { },
2747 { 0, }
2748 },
2749 {
2750 /* fixed_bit_masks */
2751 0x8000000077fff000ULL,
2752 0xfbfff80000000000ULL,
2753 0x80000000780ff000ULL,
2754 0xf807f80000000000ULL,
2755 0ULL
2756 },
2757 {
2758 /* fixed_bit_values */
2759 0x0000000070165000ULL,
2760 0x400b280000000000ULL,
2761 0x80000000680a5000ULL,
2762 0xd805080000000000ULL,
2763 -1ULL
2764 }
2765 }, 309 },
2766 { "icoh", TILE_OPC_ICOH, 0x2 /* pipes */, 1 /* num_operands */, 310 { "fnop", TILE_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
2767 TREG_ZERO, /* implicitly_written_register */ 311 { { }, { }, { }, { }, { 0, } },
2768 1, /* can_bundle */
2769 {
2770 /* operands */
2771 { 0, },
2772 { 10 },
2773 { 0, },
2774 { 0, },
2775 { 0, }
2776 },
2777 {
2778 /* fixed_bit_masks */
2779 0ULL,
2780 0xfbfff80000000000ULL,
2781 0ULL,
2782 0ULL,
2783 0ULL
2784 },
2785 {
2786 /* fixed_bit_values */
2787 -1ULL,
2788 0x400b300000000000ULL,
2789 -1ULL,
2790 -1ULL,
2791 -1ULL
2792 }
2793 }, 312 },
2794 { "ill", TILE_OPC_ILL, 0xa /* pipes */, 0 /* num_operands */, 313 { "icoh", TILE_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
2795 TREG_ZERO, /* implicitly_written_register */ 314 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
2796 1, /* can_bundle */
2797 {
2798 /* operands */
2799 { 0, },
2800 { },
2801 { 0, },
2802 { },
2803 { 0, }
2804 },
2805 {
2806 /* fixed_bit_masks */
2807 0ULL,
2808 0xfbfff80000000000ULL,
2809 0ULL,
2810 0xf807f80000000000ULL,
2811 0ULL
2812 },
2813 {
2814 /* fixed_bit_values */
2815 -1ULL,
2816 0x400b380000000000ULL,
2817 -1ULL,
2818 0xd805100000000000ULL,
2819 -1ULL
2820 }
2821 }, 315 },
2822 { "inthb", TILE_OPC_INTHB, 0x3 /* pipes */, 3 /* num_operands */, 316 { "ill", TILE_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
2823 TREG_ZERO, /* implicitly_written_register */ 317 { { 0, }, { }, { 0, }, { }, { 0, } },
2824 1, /* can_bundle */
2825 {
2826 /* operands */
2827 { 7, 8, 16 },
2828 { 9, 10, 17 },
2829 { 0, },
2830 { 0, },
2831 { 0, }
2832 },
2833 {
2834 /* fixed_bit_masks */
2835 0x800000007ffc0000ULL,
2836 0xfffe000000000000ULL,
2837 0ULL,
2838 0ULL,
2839 0ULL
2840 },
2841 {
2842 /* fixed_bit_values */
2843 0x00000000002c0000ULL,
2844 0x080a000000000000ULL,
2845 -1ULL,
2846 -1ULL,
2847 -1ULL
2848 }
2849 }, 318 },
2850 { "inthb.sn", TILE_OPC_INTHB_SN, 0x3 /* pipes */, 3 /* num_operands */, 319 { "inthb", TILE_OPC_INTHB, 0x3, 3, TREG_ZERO, 1,
2851 TREG_SN, /* implicitly_written_register */ 320 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
2852 1, /* can_bundle */
2853 {
2854 /* operands */
2855 { 7, 8, 16 },
2856 { 9, 10, 17 },
2857 { 0, },
2858 { 0, },
2859 { 0, }
2860 },
2861 {
2862 /* fixed_bit_masks */
2863 0x800000007ffc0000ULL,
2864 0xfffe000000000000ULL,
2865 0ULL,
2866 0ULL,
2867 0ULL
2868 },
2869 {
2870 /* fixed_bit_values */
2871 0x00000000082c0000ULL,
2872 0x0c0a000000000000ULL,
2873 -1ULL,
2874 -1ULL,
2875 -1ULL
2876 }
2877 }, 321 },
2878 { "inthh", TILE_OPC_INTHH, 0x3 /* pipes */, 3 /* num_operands */, 322 { "inthb.sn", TILE_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1,
2879 TREG_ZERO, /* implicitly_written_register */ 323 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
2880 1, /* can_bundle */
2881 {
2882 /* operands */
2883 { 7, 8, 16 },
2884 { 9, 10, 17 },
2885 { 0, },
2886 { 0, },
2887 { 0, }
2888 },
2889 {
2890 /* fixed_bit_masks */
2891 0x800000007ffc0000ULL,
2892 0xfffe000000000000ULL,
2893 0ULL,
2894 0ULL,
2895 0ULL
2896 },
2897 {
2898 /* fixed_bit_values */
2899 0x0000000000300000ULL,
2900 0x080c000000000000ULL,
2901 -1ULL,
2902 -1ULL,
2903 -1ULL
2904 }
2905 }, 324 },
2906 { "inthh.sn", TILE_OPC_INTHH_SN, 0x3 /* pipes */, 3 /* num_operands */, 325 { "inthh", TILE_OPC_INTHH, 0x3, 3, TREG_ZERO, 1,
2907 TREG_SN, /* implicitly_written_register */ 326 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
2908 1, /* can_bundle */
2909 {
2910 /* operands */
2911 { 7, 8, 16 },
2912 { 9, 10, 17 },
2913 { 0, },
2914 { 0, },
2915 { 0, }
2916 },
2917 {
2918 /* fixed_bit_masks */
2919 0x800000007ffc0000ULL,
2920 0xfffe000000000000ULL,
2921 0ULL,
2922 0ULL,
2923 0ULL
2924 },
2925 {
2926 /* fixed_bit_values */
2927 0x0000000008300000ULL,
2928 0x0c0c000000000000ULL,
2929 -1ULL,
2930 -1ULL,
2931 -1ULL
2932 }
2933 }, 327 },
2934 { "intlb", TILE_OPC_INTLB, 0x3 /* pipes */, 3 /* num_operands */, 328 { "inthh.sn", TILE_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1,
2935 TREG_ZERO, /* implicitly_written_register */ 329 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
2936 1, /* can_bundle */
2937 {
2938 /* operands */
2939 { 7, 8, 16 },
2940 { 9, 10, 17 },
2941 { 0, },
2942 { 0, },
2943 { 0, }
2944 },
2945 {
2946 /* fixed_bit_masks */
2947 0x800000007ffc0000ULL,
2948 0xfffe000000000000ULL,
2949 0ULL,
2950 0ULL,
2951 0ULL
2952 },
2953 {
2954 /* fixed_bit_values */
2955 0x0000000000340000ULL,
2956 0x080e000000000000ULL,
2957 -1ULL,
2958 -1ULL,
2959 -1ULL
2960 }
2961 }, 330 },
2962 { "intlb.sn", TILE_OPC_INTLB_SN, 0x3 /* pipes */, 3 /* num_operands */, 331 { "intlb", TILE_OPC_INTLB, 0x3, 3, TREG_ZERO, 1,
2963 TREG_SN, /* implicitly_written_register */ 332 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
2964 1, /* can_bundle */
2965 {
2966 /* operands */
2967 { 7, 8, 16 },
2968 { 9, 10, 17 },
2969 { 0, },
2970 { 0, },
2971 { 0, }
2972 },
2973 {
2974 /* fixed_bit_masks */
2975 0x800000007ffc0000ULL,
2976 0xfffe000000000000ULL,
2977 0ULL,
2978 0ULL,
2979 0ULL
2980 },
2981 {
2982 /* fixed_bit_values */
2983 0x0000000008340000ULL,
2984 0x0c0e000000000000ULL,
2985 -1ULL,
2986 -1ULL,
2987 -1ULL
2988 }
2989 }, 333 },
2990 { "intlh", TILE_OPC_INTLH, 0x3 /* pipes */, 3 /* num_operands */, 334 { "intlb.sn", TILE_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1,
2991 TREG_ZERO, /* implicitly_written_register */ 335 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
2992 1, /* can_bundle */
2993 {
2994 /* operands */
2995 { 7, 8, 16 },
2996 { 9, 10, 17 },
2997 { 0, },
2998 { 0, },
2999 { 0, }
3000 },
3001 {
3002 /* fixed_bit_masks */
3003 0x800000007ffc0000ULL,
3004 0xfffe000000000000ULL,
3005 0ULL,
3006 0ULL,
3007 0ULL
3008 },
3009 {
3010 /* fixed_bit_values */
3011 0x0000000000380000ULL,
3012 0x0810000000000000ULL,
3013 -1ULL,
3014 -1ULL,
3015 -1ULL
3016 }
3017 }, 336 },
3018 { "intlh.sn", TILE_OPC_INTLH_SN, 0x3 /* pipes */, 3 /* num_operands */, 337 { "intlh", TILE_OPC_INTLH, 0x3, 3, TREG_ZERO, 1,
3019 TREG_SN, /* implicitly_written_register */ 338 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
3020 1, /* can_bundle */
3021 {
3022 /* operands */
3023 { 7, 8, 16 },
3024 { 9, 10, 17 },
3025 { 0, },
3026 { 0, },
3027 { 0, }
3028 },
3029 {
3030 /* fixed_bit_masks */
3031 0x800000007ffc0000ULL,
3032 0xfffe000000000000ULL,
3033 0ULL,
3034 0ULL,
3035 0ULL
3036 },
3037 {
3038 /* fixed_bit_values */
3039 0x0000000008380000ULL,
3040 0x0c10000000000000ULL,
3041 -1ULL,
3042 -1ULL,
3043 -1ULL
3044 }
3045 }, 339 },
3046 { "inv", TILE_OPC_INV, 0x2 /* pipes */, 1 /* num_operands */, 340 { "intlh.sn", TILE_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1,
3047 TREG_ZERO, /* implicitly_written_register */ 341 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
3048 1, /* can_bundle */
3049 {
3050 /* operands */
3051 { 0, },
3052 { 10 },
3053 { 0, },
3054 { 0, },
3055 { 0, }
3056 },
3057 {
3058 /* fixed_bit_masks */
3059 0ULL,
3060 0xfbfff80000000000ULL,
3061 0ULL,
3062 0ULL,
3063 0ULL
3064 },
3065 {
3066 /* fixed_bit_values */
3067 -1ULL,
3068 0x400b400000000000ULL,
3069 -1ULL,
3070 -1ULL,
3071 -1ULL
3072 }
3073 }, 342 },
3074 { "iret", TILE_OPC_IRET, 0x2 /* pipes */, 0 /* num_operands */, 343 { "inv", TILE_OPC_INV, 0x2, 1, TREG_ZERO, 1,
3075 TREG_ZERO, /* implicitly_written_register */ 344 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
3076 1, /* can_bundle */
3077 {
3078 /* operands */
3079 { 0, },
3080 { },
3081 { 0, },
3082 { 0, },
3083 { 0, }
3084 },
3085 {
3086 /* fixed_bit_masks */
3087 0ULL,
3088 0xfbfff80000000000ULL,
3089 0ULL,
3090 0ULL,
3091 0ULL
3092 },
3093 {
3094 /* fixed_bit_values */
3095 -1ULL,
3096 0x400b480000000000ULL,
3097 -1ULL,
3098 -1ULL,
3099 -1ULL
3100 }
3101 }, 345 },
3102 { "jalb", TILE_OPC_JALB, 0x2 /* pipes */, 1 /* num_operands */, 346 { "iret", TILE_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
3103 TREG_LR, /* implicitly_written_register */ 347 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
3104 1, /* can_bundle */
3105 {
3106 /* operands */
3107 { 0, },
3108 { 22 },
3109 { 0, },
3110 { 0, },
3111 { 0, }
3112 },
3113 {
3114 /* fixed_bit_masks */
3115 0ULL,
3116 0xf800000000000000ULL,
3117 0ULL,
3118 0ULL,
3119 0ULL
3120 },
3121 {
3122 /* fixed_bit_values */
3123 -1ULL,
3124 0x6800000000000000ULL,
3125 -1ULL,
3126 -1ULL,
3127 -1ULL
3128 }
3129 }, 348 },
3130 { "jalf", TILE_OPC_JALF, 0x2 /* pipes */, 1 /* num_operands */, 349 { "jalb", TILE_OPC_JALB, 0x2, 1, TREG_LR, 1,
3131 TREG_LR, /* implicitly_written_register */ 350 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
3132 1, /* can_bundle */
3133 {
3134 /* operands */
3135 { 0, },
3136 { 22 },
3137 { 0, },
3138 { 0, },
3139 { 0, }
3140 },
3141 {
3142 /* fixed_bit_masks */
3143 0ULL,
3144 0xf800000000000000ULL,
3145 0ULL,
3146 0ULL,
3147 0ULL
3148 },
3149 {
3150 /* fixed_bit_values */
3151 -1ULL,
3152 0x6000000000000000ULL,
3153 -1ULL,
3154 -1ULL,
3155 -1ULL
3156 }
3157 }, 351 },
3158 { "jalr", TILE_OPC_JALR, 0x2 /* pipes */, 1 /* num_operands */, 352 { "jalf", TILE_OPC_JALF, 0x2, 1, TREG_LR, 1,
3159 TREG_LR, /* implicitly_written_register */ 353 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
3160 1, /* can_bundle */
3161 {
3162 /* operands */
3163 { 0, },
3164 { 10 },
3165 { 0, },
3166 { 0, },
3167 { 0, }
3168 },
3169 {
3170 /* fixed_bit_masks */
3171 0ULL,
3172 0xfbfe000000000000ULL,
3173 0ULL,
3174 0ULL,
3175 0ULL
3176 },
3177 {
3178 /* fixed_bit_values */
3179 -1ULL,
3180 0x0814000000000000ULL,
3181 -1ULL,
3182 -1ULL,
3183 -1ULL
3184 }
3185 }, 354 },
3186 { "jalrp", TILE_OPC_JALRP, 0x2 /* pipes */, 1 /* num_operands */, 355 { "jalr", TILE_OPC_JALR, 0x2, 1, TREG_LR, 1,
3187 TREG_LR, /* implicitly_written_register */ 356 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
3188 1, /* can_bundle */
3189 {
3190 /* operands */
3191 { 0, },
3192 { 10 },
3193 { 0, },
3194 { 0, },
3195 { 0, }
3196 },
3197 {
3198 /* fixed_bit_masks */
3199 0ULL,
3200 0xfbfe000000000000ULL,
3201 0ULL,
3202 0ULL,
3203 0ULL
3204 },
3205 {
3206 /* fixed_bit_values */
3207 -1ULL,
3208 0x0812000000000000ULL,
3209 -1ULL,
3210 -1ULL,
3211 -1ULL
3212 }
3213 }, 357 },
3214 { "jb", TILE_OPC_JB, 0x2 /* pipes */, 1 /* num_operands */, 358 { "jalrp", TILE_OPC_JALRP, 0x2, 1, TREG_LR, 1,
3215 TREG_ZERO, /* implicitly_written_register */ 359 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
3216 1, /* can_bundle */
3217 {
3218 /* operands */
3219 { 0, },
3220 { 22 },
3221 { 0, },
3222 { 0, },
3223 { 0, }
3224 },
3225 {
3226 /* fixed_bit_masks */
3227 0ULL,
3228 0xf800000000000000ULL,
3229 0ULL,
3230 0ULL,
3231 0ULL
3232 },
3233 {
3234 /* fixed_bit_values */
3235 -1ULL,
3236 0x5800000000000000ULL,
3237 -1ULL,
3238 -1ULL,
3239 -1ULL
3240 }
3241 }, 360 },
3242 { "jf", TILE_OPC_JF, 0x2 /* pipes */, 1 /* num_operands */, 361 { "jb", TILE_OPC_JB, 0x2, 1, TREG_ZERO, 1,
3243 TREG_ZERO, /* implicitly_written_register */ 362 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
3244 1, /* can_bundle */
3245 {
3246 /* operands */
3247 { 0, },
3248 { 22 },
3249 { 0, },
3250 { 0, },
3251 { 0, }
3252 },
3253 {
3254 /* fixed_bit_masks */
3255 0ULL,
3256 0xf800000000000000ULL,
3257 0ULL,
3258 0ULL,
3259 0ULL
3260 },
3261 {
3262 /* fixed_bit_values */
3263 -1ULL,
3264 0x5000000000000000ULL,
3265 -1ULL,
3266 -1ULL,
3267 -1ULL
3268 }
3269 }, 363 },
3270 { "jr", TILE_OPC_JR, 0x2 /* pipes */, 1 /* num_operands */, 364 { "jf", TILE_OPC_JF, 0x2, 1, TREG_ZERO, 1,
3271 TREG_ZERO, /* implicitly_written_register */ 365 { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
3272 1, /* can_bundle */
3273 {
3274 /* operands */
3275 { 0, },
3276 { 10 },
3277 { 0, },
3278 { 0, },
3279 { 0, }
3280 },
3281 {
3282 /* fixed_bit_masks */
3283 0ULL,
3284 0xfbfe000000000000ULL,
3285 0ULL,
3286 0ULL,
3287 0ULL
3288 },
3289 {
3290 /* fixed_bit_values */
3291 -1ULL,
3292 0x0818000000000000ULL,
3293 -1ULL,
3294 -1ULL,
3295 -1ULL
3296 }
3297 }, 366 },
3298 { "jrp", TILE_OPC_JRP, 0x2 /* pipes */, 1 /* num_operands */, 367 { "jr", TILE_OPC_JR, 0x2, 1, TREG_ZERO, 1,
3299 TREG_ZERO, /* implicitly_written_register */ 368 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
3300 1, /* can_bundle */
3301 {
3302 /* operands */
3303 { 0, },
3304 { 10 },
3305 { 0, },
3306 { 0, },
3307 { 0, }
3308 },
3309 {
3310 /* fixed_bit_masks */
3311 0ULL,
3312 0xfbfe000000000000ULL,
3313 0ULL,
3314 0ULL,
3315 0ULL
3316 },
3317 {
3318 /* fixed_bit_values */
3319 -1ULL,
3320 0x0816000000000000ULL,
3321 -1ULL,
3322 -1ULL,
3323 -1ULL
3324 }
3325 }, 369 },
3326 { "lb", TILE_OPC_LB, 0x12 /* pipes */, 2 /* num_operands */, 370 { "jrp", TILE_OPC_JRP, 0x2, 1, TREG_ZERO, 1,
3327 TREG_ZERO, /* implicitly_written_register */ 371 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
3328 1, /* can_bundle */
3329 {
3330 /* operands */
3331 { 0, },
3332 { 9, 10 },
3333 { 0, },
3334 { 0, },
3335 { 23, 15 }
3336 },
3337 {
3338 /* fixed_bit_masks */
3339 0ULL,
3340 0xfffff80000000000ULL,
3341 0ULL,
3342 0ULL,
3343 0x8700000000000000ULL
3344 },
3345 {
3346 /* fixed_bit_values */
3347 -1ULL,
3348 0x400b500000000000ULL,
3349 -1ULL,
3350 -1ULL,
3351 0x8000000000000000ULL
3352 }
3353 }, 372 },
3354 { "lb.sn", TILE_OPC_LB_SN, 0x2 /* pipes */, 2 /* num_operands */, 373 { "lb", TILE_OPC_LB, 0x12, 2, TREG_ZERO, 1,
3355 TREG_SN, /* implicitly_written_register */ 374 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
3356 1, /* can_bundle */
3357 {
3358 /* operands */
3359 { 0, },
3360 { 9, 10 },
3361 { 0, },
3362 { 0, },
3363 { 0, }
3364 },
3365 {
3366 /* fixed_bit_masks */
3367 0ULL,
3368 0xfffff80000000000ULL,
3369 0ULL,
3370 0ULL,
3371 0ULL
3372 },
3373 {
3374 /* fixed_bit_values */
3375 -1ULL,
3376 0x440b500000000000ULL,
3377 -1ULL,
3378 -1ULL,
3379 -1ULL
3380 }
3381 }, 375 },
3382 { "lb_u", TILE_OPC_LB_U, 0x12 /* pipes */, 2 /* num_operands */, 376 { "lb.sn", TILE_OPC_LB_SN, 0x2, 2, TREG_SN, 1,
3383 TREG_ZERO, /* implicitly_written_register */ 377 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
3384 1, /* can_bundle */
3385 {
3386 /* operands */
3387 { 0, },
3388 { 9, 10 },
3389 { 0, },
3390 { 0, },
3391 { 23, 15 }
3392 },
3393 {
3394 /* fixed_bit_masks */
3395 0ULL,
3396 0xfffff80000000000ULL,
3397 0ULL,
3398 0ULL,
3399 0x8700000000000000ULL
3400 },
3401 {
3402 /* fixed_bit_values */
3403 -1ULL,
3404 0x400b580000000000ULL,
3405 -1ULL,
3406 -1ULL,
3407 0x8100000000000000ULL
3408 }
3409 }, 378 },
3410 { "lb_u.sn", TILE_OPC_LB_U_SN, 0x2 /* pipes */, 2 /* num_operands */, 379 { "lb_u", TILE_OPC_LB_U, 0x12, 2, TREG_ZERO, 1,
3411 TREG_SN, /* implicitly_written_register */ 380 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
3412 1, /* can_bundle */
3413 {
3414 /* operands */
3415 { 0, },
3416 { 9, 10 },
3417 { 0, },
3418 { 0, },
3419 { 0, }
3420 },
3421 {
3422 /* fixed_bit_masks */
3423 0ULL,
3424 0xfffff80000000000ULL,
3425 0ULL,
3426 0ULL,
3427 0ULL
3428 },
3429 {
3430 /* fixed_bit_values */
3431 -1ULL,
3432 0x440b580000000000ULL,
3433 -1ULL,
3434 -1ULL,
3435 -1ULL
3436 }
3437 }, 381 },
3438 { "lbadd", TILE_OPC_LBADD, 0x2 /* pipes */, 3 /* num_operands */, 382 { "lb_u.sn", TILE_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1,
3439 TREG_ZERO, /* implicitly_written_register */ 383 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
3440 1, /* can_bundle */
3441 {
3442 /* operands */
3443 { 0, },
3444 { 9, 24, 1 },
3445 { 0, },
3446 { 0, },
3447 { 0, }
3448 },
3449 {
3450 /* fixed_bit_masks */
3451 0ULL,
3452 0xfff8000000000000ULL,
3453 0ULL,
3454 0ULL,
3455 0ULL
3456 },
3457 {
3458 /* fixed_bit_values */
3459 -1ULL,
3460 0x30b0000000000000ULL,
3461 -1ULL,
3462 -1ULL,
3463 -1ULL
3464 }
3465 }, 384 },
3466 { "lbadd.sn", TILE_OPC_LBADD_SN, 0x2 /* pipes */, 3 /* num_operands */, 385 { "lbadd", TILE_OPC_LBADD, 0x2, 3, TREG_ZERO, 1,
3467 TREG_SN, /* implicitly_written_register */ 386 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3468 1, /* can_bundle */
3469 {
3470 /* operands */
3471 { 0, },
3472 { 9, 24, 1 },
3473 { 0, },
3474 { 0, },
3475 { 0, }
3476 },
3477 {
3478 /* fixed_bit_masks */
3479 0ULL,
3480 0xfff8000000000000ULL,
3481 0ULL,
3482 0ULL,
3483 0ULL
3484 },
3485 {
3486 /* fixed_bit_values */
3487 -1ULL,
3488 0x34b0000000000000ULL,
3489 -1ULL,
3490 -1ULL,
3491 -1ULL
3492 }
3493 }, 387 },
3494 { "lbadd_u", TILE_OPC_LBADD_U, 0x2 /* pipes */, 3 /* num_operands */, 388 { "lbadd.sn", TILE_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1,
3495 TREG_ZERO, /* implicitly_written_register */ 389 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3496 1, /* can_bundle */
3497 {
3498 /* operands */
3499 { 0, },
3500 { 9, 24, 1 },
3501 { 0, },
3502 { 0, },
3503 { 0, }
3504 },
3505 {
3506 /* fixed_bit_masks */
3507 0ULL,
3508 0xfff8000000000000ULL,
3509 0ULL,
3510 0ULL,
3511 0ULL
3512 },
3513 {
3514 /* fixed_bit_values */
3515 -1ULL,
3516 0x30b8000000000000ULL,
3517 -1ULL,
3518 -1ULL,
3519 -1ULL
3520 }
3521 }, 390 },
3522 { "lbadd_u.sn", TILE_OPC_LBADD_U_SN, 0x2 /* pipes */, 3 /* num_operands */, 391 { "lbadd_u", TILE_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1,
3523 TREG_SN, /* implicitly_written_register */ 392 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3524 1, /* can_bundle */
3525 {
3526 /* operands */
3527 { 0, },
3528 { 9, 24, 1 },
3529 { 0, },
3530 { 0, },
3531 { 0, }
3532 },
3533 {
3534 /* fixed_bit_masks */
3535 0ULL,
3536 0xfff8000000000000ULL,
3537 0ULL,
3538 0ULL,
3539 0ULL
3540 },
3541 {
3542 /* fixed_bit_values */
3543 -1ULL,
3544 0x34b8000000000000ULL,
3545 -1ULL,
3546 -1ULL,
3547 -1ULL
3548 }
3549 }, 393 },
3550 { "lh", TILE_OPC_LH, 0x12 /* pipes */, 2 /* num_operands */, 394 { "lbadd_u.sn", TILE_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1,
3551 TREG_ZERO, /* implicitly_written_register */ 395 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3552 1, /* can_bundle */
3553 {
3554 /* operands */
3555 { 0, },
3556 { 9, 10 },
3557 { 0, },
3558 { 0, },
3559 { 23, 15 }
3560 },
3561 {
3562 /* fixed_bit_masks */
3563 0ULL,
3564 0xfffff80000000000ULL,
3565 0ULL,
3566 0ULL,
3567 0x8700000000000000ULL
3568 },
3569 {
3570 /* fixed_bit_values */
3571 -1ULL,
3572 0x400b600000000000ULL,
3573 -1ULL,
3574 -1ULL,
3575 0x8200000000000000ULL
3576 }
3577 }, 396 },
3578 { "lh.sn", TILE_OPC_LH_SN, 0x2 /* pipes */, 2 /* num_operands */, 397 { "lh", TILE_OPC_LH, 0x12, 2, TREG_ZERO, 1,
3579 TREG_SN, /* implicitly_written_register */ 398 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
3580 1, /* can_bundle */
3581 {
3582 /* operands */
3583 { 0, },
3584 { 9, 10 },
3585 { 0, },
3586 { 0, },
3587 { 0, }
3588 },
3589 {
3590 /* fixed_bit_masks */
3591 0ULL,
3592 0xfffff80000000000ULL,
3593 0ULL,
3594 0ULL,
3595 0ULL
3596 },
3597 {
3598 /* fixed_bit_values */
3599 -1ULL,
3600 0x440b600000000000ULL,
3601 -1ULL,
3602 -1ULL,
3603 -1ULL
3604 }
3605 }, 399 },
3606 { "lh_u", TILE_OPC_LH_U, 0x12 /* pipes */, 2 /* num_operands */, 400 { "lh.sn", TILE_OPC_LH_SN, 0x2, 2, TREG_SN, 1,
3607 TREG_ZERO, /* implicitly_written_register */ 401 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
3608 1, /* can_bundle */
3609 {
3610 /* operands */
3611 { 0, },
3612 { 9, 10 },
3613 { 0, },
3614 { 0, },
3615 { 23, 15 }
3616 },
3617 {
3618 /* fixed_bit_masks */
3619 0ULL,
3620 0xfffff80000000000ULL,
3621 0ULL,
3622 0ULL,
3623 0x8700000000000000ULL
3624 },
3625 {
3626 /* fixed_bit_values */
3627 -1ULL,
3628 0x400b680000000000ULL,
3629 -1ULL,
3630 -1ULL,
3631 0x8300000000000000ULL
3632 }
3633 }, 402 },
3634 { "lh_u.sn", TILE_OPC_LH_U_SN, 0x2 /* pipes */, 2 /* num_operands */, 403 { "lh_u", TILE_OPC_LH_U, 0x12, 2, TREG_ZERO, 1,
3635 TREG_SN, /* implicitly_written_register */ 404 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
3636 1, /* can_bundle */
3637 {
3638 /* operands */
3639 { 0, },
3640 { 9, 10 },
3641 { 0, },
3642 { 0, },
3643 { 0, }
3644 },
3645 {
3646 /* fixed_bit_masks */
3647 0ULL,
3648 0xfffff80000000000ULL,
3649 0ULL,
3650 0ULL,
3651 0ULL
3652 },
3653 {
3654 /* fixed_bit_values */
3655 -1ULL,
3656 0x440b680000000000ULL,
3657 -1ULL,
3658 -1ULL,
3659 -1ULL
3660 }
3661 }, 405 },
3662 { "lhadd", TILE_OPC_LHADD, 0x2 /* pipes */, 3 /* num_operands */, 406 { "lh_u.sn", TILE_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1,
3663 TREG_ZERO, /* implicitly_written_register */ 407 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
3664 1, /* can_bundle */
3665 {
3666 /* operands */
3667 { 0, },
3668 { 9, 24, 1 },
3669 { 0, },
3670 { 0, },
3671 { 0, }
3672 },
3673 {
3674 /* fixed_bit_masks */
3675 0ULL,
3676 0xfff8000000000000ULL,
3677 0ULL,
3678 0ULL,
3679 0ULL
3680 },
3681 {
3682 /* fixed_bit_values */
3683 -1ULL,
3684 0x30c0000000000000ULL,
3685 -1ULL,
3686 -1ULL,
3687 -1ULL
3688 }
3689 }, 408 },
3690 { "lhadd.sn", TILE_OPC_LHADD_SN, 0x2 /* pipes */, 3 /* num_operands */, 409 { "lhadd", TILE_OPC_LHADD, 0x2, 3, TREG_ZERO, 1,
3691 TREG_SN, /* implicitly_written_register */ 410 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3692 1, /* can_bundle */
3693 {
3694 /* operands */
3695 { 0, },
3696 { 9, 24, 1 },
3697 { 0, },
3698 { 0, },
3699 { 0, }
3700 },
3701 {
3702 /* fixed_bit_masks */
3703 0ULL,
3704 0xfff8000000000000ULL,
3705 0ULL,
3706 0ULL,
3707 0ULL
3708 },
3709 {
3710 /* fixed_bit_values */
3711 -1ULL,
3712 0x34c0000000000000ULL,
3713 -1ULL,
3714 -1ULL,
3715 -1ULL
3716 }
3717 }, 411 },
3718 { "lhadd_u", TILE_OPC_LHADD_U, 0x2 /* pipes */, 3 /* num_operands */, 412 { "lhadd.sn", TILE_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1,
3719 TREG_ZERO, /* implicitly_written_register */ 413 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3720 1, /* can_bundle */
3721 {
3722 /* operands */
3723 { 0, },
3724 { 9, 24, 1 },
3725 { 0, },
3726 { 0, },
3727 { 0, }
3728 },
3729 {
3730 /* fixed_bit_masks */
3731 0ULL,
3732 0xfff8000000000000ULL,
3733 0ULL,
3734 0ULL,
3735 0ULL
3736 },
3737 {
3738 /* fixed_bit_values */
3739 -1ULL,
3740 0x30c8000000000000ULL,
3741 -1ULL,
3742 -1ULL,
3743 -1ULL
3744 }
3745 }, 414 },
3746 { "lhadd_u.sn", TILE_OPC_LHADD_U_SN, 0x2 /* pipes */, 3 /* num_operands */, 415 { "lhadd_u", TILE_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1,
3747 TREG_SN, /* implicitly_written_register */ 416 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3748 1, /* can_bundle */
3749 {
3750 /* operands */
3751 { 0, },
3752 { 9, 24, 1 },
3753 { 0, },
3754 { 0, },
3755 { 0, }
3756 },
3757 {
3758 /* fixed_bit_masks */
3759 0ULL,
3760 0xfff8000000000000ULL,
3761 0ULL,
3762 0ULL,
3763 0ULL
3764 },
3765 {
3766 /* fixed_bit_values */
3767 -1ULL,
3768 0x34c8000000000000ULL,
3769 -1ULL,
3770 -1ULL,
3771 -1ULL
3772 }
3773 }, 417 },
3774 { "lnk", TILE_OPC_LNK, 0x2 /* pipes */, 1 /* num_operands */, 418 { "lhadd_u.sn", TILE_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1,
3775 TREG_ZERO, /* implicitly_written_register */ 419 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3776 1, /* can_bundle */
3777 {
3778 /* operands */
3779 { 0, },
3780 { 9 },
3781 { 0, },
3782 { 0, },
3783 { 0, }
3784 },
3785 {
3786 /* fixed_bit_masks */
3787 0ULL,
3788 0xfffe000000000000ULL,
3789 0ULL,
3790 0ULL,
3791 0ULL
3792 },
3793 {
3794 /* fixed_bit_values */
3795 -1ULL,
3796 0x081a000000000000ULL,
3797 -1ULL,
3798 -1ULL,
3799 -1ULL
3800 }
3801 }, 420 },
3802 { "lnk.sn", TILE_OPC_LNK_SN, 0x2 /* pipes */, 1 /* num_operands */, 421 { "lnk", TILE_OPC_LNK, 0x2, 1, TREG_ZERO, 1,
3803 TREG_SN, /* implicitly_written_register */ 422 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
3804 1, /* can_bundle */
3805 {
3806 /* operands */
3807 { 0, },
3808 { 9 },
3809 { 0, },
3810 { 0, },
3811 { 0, }
3812 },
3813 {
3814 /* fixed_bit_masks */
3815 0ULL,
3816 0xfffe000000000000ULL,
3817 0ULL,
3818 0ULL,
3819 0ULL
3820 },
3821 {
3822 /* fixed_bit_values */
3823 -1ULL,
3824 0x0c1a000000000000ULL,
3825 -1ULL,
3826 -1ULL,
3827 -1ULL
3828 }
3829 }, 423 },
3830 { "lw", TILE_OPC_LW, 0x12 /* pipes */, 2 /* num_operands */, 424 { "lnk.sn", TILE_OPC_LNK_SN, 0x2, 1, TREG_SN, 1,
3831 TREG_ZERO, /* implicitly_written_register */ 425 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
3832 1, /* can_bundle */
3833 {
3834 /* operands */
3835 { 0, },
3836 { 9, 10 },
3837 { 0, },
3838 { 0, },
3839 { 23, 15 }
3840 },
3841 {
3842 /* fixed_bit_masks */
3843 0ULL,
3844 0xfffff80000000000ULL,
3845 0ULL,
3846 0ULL,
3847 0x8700000000000000ULL
3848 },
3849 {
3850 /* fixed_bit_values */
3851 -1ULL,
3852 0x400b700000000000ULL,
3853 -1ULL,
3854 -1ULL,
3855 0x8400000000000000ULL
3856 }
3857 }, 426 },
3858 { "lw.sn", TILE_OPC_LW_SN, 0x2 /* pipes */, 2 /* num_operands */, 427 { "lw", TILE_OPC_LW, 0x12, 2, TREG_ZERO, 1,
3859 TREG_SN, /* implicitly_written_register */ 428 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
3860 1, /* can_bundle */
3861 {
3862 /* operands */
3863 { 0, },
3864 { 9, 10 },
3865 { 0, },
3866 { 0, },
3867 { 0, }
3868 },
3869 {
3870 /* fixed_bit_masks */
3871 0ULL,
3872 0xfffff80000000000ULL,
3873 0ULL,
3874 0ULL,
3875 0ULL
3876 },
3877 {
3878 /* fixed_bit_values */
3879 -1ULL,
3880 0x440b700000000000ULL,
3881 -1ULL,
3882 -1ULL,
3883 -1ULL
3884 }
3885 }, 429 },
3886 { "lw_na", TILE_OPC_LW_NA, 0x2 /* pipes */, 2 /* num_operands */, 430 { "lw.sn", TILE_OPC_LW_SN, 0x2, 2, TREG_SN, 1,
3887 TREG_ZERO, /* implicitly_written_register */ 431 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
3888 1, /* can_bundle */
3889 {
3890 /* operands */
3891 { 0, },
3892 { 9, 10 },
3893 { 0, },
3894 { 0, },
3895 { 0, }
3896 },
3897 {
3898 /* fixed_bit_masks */
3899 0ULL,
3900 0xfffff80000000000ULL,
3901 0ULL,
3902 0ULL,
3903 0ULL
3904 },
3905 {
3906 /* fixed_bit_values */
3907 -1ULL,
3908 0x400bc00000000000ULL,
3909 -1ULL,
3910 -1ULL,
3911 -1ULL
3912 }
3913 }, 432 },
3914 { "lw_na.sn", TILE_OPC_LW_NA_SN, 0x2 /* pipes */, 2 /* num_operands */, 433 { "lw_na", TILE_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1,
3915 TREG_SN, /* implicitly_written_register */ 434 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
3916 1, /* can_bundle */
3917 {
3918 /* operands */
3919 { 0, },
3920 { 9, 10 },
3921 { 0, },
3922 { 0, },
3923 { 0, }
3924 },
3925 {
3926 /* fixed_bit_masks */
3927 0ULL,
3928 0xfffff80000000000ULL,
3929 0ULL,
3930 0ULL,
3931 0ULL
3932 },
3933 {
3934 /* fixed_bit_values */
3935 -1ULL,
3936 0x440bc00000000000ULL,
3937 -1ULL,
3938 -1ULL,
3939 -1ULL
3940 }
3941 }, 435 },
3942 { "lwadd", TILE_OPC_LWADD, 0x2 /* pipes */, 3 /* num_operands */, 436 { "lw_na.sn", TILE_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1,
3943 TREG_ZERO, /* implicitly_written_register */ 437 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
3944 1, /* can_bundle */
3945 {
3946 /* operands */
3947 { 0, },
3948 { 9, 24, 1 },
3949 { 0, },
3950 { 0, },
3951 { 0, }
3952 },
3953 {
3954 /* fixed_bit_masks */
3955 0ULL,
3956 0xfff8000000000000ULL,
3957 0ULL,
3958 0ULL,
3959 0ULL
3960 },
3961 {
3962 /* fixed_bit_values */
3963 -1ULL,
3964 0x30d0000000000000ULL,
3965 -1ULL,
3966 -1ULL,
3967 -1ULL
3968 }
3969 }, 438 },
3970 { "lwadd.sn", TILE_OPC_LWADD_SN, 0x2 /* pipes */, 3 /* num_operands */, 439 { "lwadd", TILE_OPC_LWADD, 0x2, 3, TREG_ZERO, 1,
3971 TREG_SN, /* implicitly_written_register */ 440 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
3972 1, /* can_bundle */
3973 {
3974 /* operands */
3975 { 0, },
3976 { 9, 24, 1 },
3977 { 0, },
3978 { 0, },
3979 { 0, }
3980 },
3981 {
3982 /* fixed_bit_masks */
3983 0ULL,
3984 0xfff8000000000000ULL,
3985 0ULL,
3986 0ULL,
3987 0ULL
3988 },
3989 {
3990 /* fixed_bit_values */
3991 -1ULL,
3992 0x34d0000000000000ULL,
3993 -1ULL,
3994 -1ULL,
3995 -1ULL
3996 }
3997 }, 441 },
3998 { "lwadd_na", TILE_OPC_LWADD_NA, 0x2 /* pipes */, 3 /* num_operands */, 442 { "lwadd.sn", TILE_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1,
3999 TREG_ZERO, /* implicitly_written_register */ 443 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
4000 1, /* can_bundle */
4001 {
4002 /* operands */
4003 { 0, },
4004 { 9, 24, 1 },
4005 { 0, },
4006 { 0, },
4007 { 0, }
4008 },
4009 {
4010 /* fixed_bit_masks */
4011 0ULL,
4012 0xfff8000000000000ULL,
4013 0ULL,
4014 0ULL,
4015 0ULL
4016 },
4017 {
4018 /* fixed_bit_values */
4019 -1ULL,
4020 0x30d8000000000000ULL,
4021 -1ULL,
4022 -1ULL,
4023 -1ULL
4024 }
4025 }, 444 },
4026 { "lwadd_na.sn", TILE_OPC_LWADD_NA_SN, 0x2 /* pipes */, 3 /* num_operands */, 445 { "lwadd_na", TILE_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1,
4027 TREG_SN, /* implicitly_written_register */ 446 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
4028 1, /* can_bundle */
4029 {
4030 /* operands */
4031 { 0, },
4032 { 9, 24, 1 },
4033 { 0, },
4034 { 0, },
4035 { 0, }
4036 },
4037 {
4038 /* fixed_bit_masks */
4039 0ULL,
4040 0xfff8000000000000ULL,
4041 0ULL,
4042 0ULL,
4043 0ULL
4044 },
4045 {
4046 /* fixed_bit_values */
4047 -1ULL,
4048 0x34d8000000000000ULL,
4049 -1ULL,
4050 -1ULL,
4051 -1ULL
4052 }
4053 }, 447 },
4054 { "maxb_u", TILE_OPC_MAXB_U, 0x3 /* pipes */, 3 /* num_operands */, 448 { "lwadd_na.sn", TILE_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1,
4055 TREG_ZERO, /* implicitly_written_register */ 449 { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
4056 1, /* can_bundle */
4057 {
4058 /* operands */
4059 { 7, 8, 16 },
4060 { 9, 10, 17 },
4061 { 0, },
4062 { 0, },
4063 { 0, }
4064 },
4065 {
4066 /* fixed_bit_masks */
4067 0x800000007ffc0000ULL,
4068 0xfffe000000000000ULL,
4069 0ULL,
4070 0ULL,
4071 0ULL
4072 },
4073 {
4074 /* fixed_bit_values */
4075 0x00000000003c0000ULL,
4076 0x081c000000000000ULL,
4077 -1ULL,
4078 -1ULL,
4079 -1ULL
4080 }
4081 }, 450 },
4082 { "maxb_u.sn", TILE_OPC_MAXB_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 451 { "maxb_u", TILE_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1,
4083 TREG_SN, /* implicitly_written_register */ 452 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4084 1, /* can_bundle */
4085 {
4086 /* operands */
4087 { 7, 8, 16 },
4088 { 9, 10, 17 },
4089 { 0, },
4090 { 0, },
4091 { 0, }
4092 },
4093 {
4094 /* fixed_bit_masks */
4095 0x800000007ffc0000ULL,
4096 0xfffe000000000000ULL,
4097 0ULL,
4098 0ULL,
4099 0ULL
4100 },
4101 {
4102 /* fixed_bit_values */
4103 0x00000000083c0000ULL,
4104 0x0c1c000000000000ULL,
4105 -1ULL,
4106 -1ULL,
4107 -1ULL
4108 }
4109 }, 453 },
4110 { "maxh", TILE_OPC_MAXH, 0x3 /* pipes */, 3 /* num_operands */, 454 { "maxb_u.sn", TILE_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1,
4111 TREG_ZERO, /* implicitly_written_register */ 455 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4112 1, /* can_bundle */
4113 {
4114 /* operands */
4115 { 7, 8, 16 },
4116 { 9, 10, 17 },
4117 { 0, },
4118 { 0, },
4119 { 0, }
4120 },
4121 {
4122 /* fixed_bit_masks */
4123 0x800000007ffc0000ULL,
4124 0xfffe000000000000ULL,
4125 0ULL,
4126 0ULL,
4127 0ULL
4128 },
4129 {
4130 /* fixed_bit_values */
4131 0x0000000000400000ULL,
4132 0x081e000000000000ULL,
4133 -1ULL,
4134 -1ULL,
4135 -1ULL
4136 }
4137 }, 456 },
4138 { "maxh.sn", TILE_OPC_MAXH_SN, 0x3 /* pipes */, 3 /* num_operands */, 457 { "maxh", TILE_OPC_MAXH, 0x3, 3, TREG_ZERO, 1,
4139 TREG_SN, /* implicitly_written_register */ 458 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4140 1, /* can_bundle */
4141 {
4142 /* operands */
4143 { 7, 8, 16 },
4144 { 9, 10, 17 },
4145 { 0, },
4146 { 0, },
4147 { 0, }
4148 },
4149 {
4150 /* fixed_bit_masks */
4151 0x800000007ffc0000ULL,
4152 0xfffe000000000000ULL,
4153 0ULL,
4154 0ULL,
4155 0ULL
4156 },
4157 {
4158 /* fixed_bit_values */
4159 0x0000000008400000ULL,
4160 0x0c1e000000000000ULL,
4161 -1ULL,
4162 -1ULL,
4163 -1ULL
4164 }
4165 }, 459 },
4166 { "maxib_u", TILE_OPC_MAXIB_U, 0x3 /* pipes */, 3 /* num_operands */, 460 { "maxh.sn", TILE_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1,
4167 TREG_ZERO, /* implicitly_written_register */ 461 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4168 1, /* can_bundle */
4169 {
4170 /* operands */
4171 { 7, 8, 0 },
4172 { 9, 10, 1 },
4173 { 0, },
4174 { 0, },
4175 { 0, }
4176 },
4177 {
4178 /* fixed_bit_masks */
4179 0x800000007ff00000ULL,
4180 0xfff8000000000000ULL,
4181 0ULL,
4182 0ULL,
4183 0ULL
4184 },
4185 {
4186 /* fixed_bit_values */
4187 0x0000000040400000ULL,
4188 0x3028000000000000ULL,
4189 -1ULL,
4190 -1ULL,
4191 -1ULL
4192 }
4193 }, 462 },
4194 { "maxib_u.sn", TILE_OPC_MAXIB_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 463 { "maxib_u", TILE_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1,
4195 TREG_SN, /* implicitly_written_register */ 464 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4196 1, /* can_bundle */
4197 {
4198 /* operands */
4199 { 7, 8, 0 },
4200 { 9, 10, 1 },
4201 { 0, },
4202 { 0, },
4203 { 0, }
4204 },
4205 {
4206 /* fixed_bit_masks */
4207 0x800000007ff00000ULL,
4208 0xfff8000000000000ULL,
4209 0ULL,
4210 0ULL,
4211 0ULL
4212 },
4213 {
4214 /* fixed_bit_values */
4215 0x0000000048400000ULL,
4216 0x3428000000000000ULL,
4217 -1ULL,
4218 -1ULL,
4219 -1ULL
4220 }
4221 }, 465 },
4222 { "maxih", TILE_OPC_MAXIH, 0x3 /* pipes */, 3 /* num_operands */, 466 { "maxib_u.sn", TILE_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1,
4223 TREG_ZERO, /* implicitly_written_register */ 467 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4224 1, /* can_bundle */
4225 {
4226 /* operands */
4227 { 7, 8, 0 },
4228 { 9, 10, 1 },
4229 { 0, },
4230 { 0, },
4231 { 0, }
4232 },
4233 {
4234 /* fixed_bit_masks */
4235 0x800000007ff00000ULL,
4236 0xfff8000000000000ULL,
4237 0ULL,
4238 0ULL,
4239 0ULL
4240 },
4241 {
4242 /* fixed_bit_values */
4243 0x0000000040500000ULL,
4244 0x3030000000000000ULL,
4245 -1ULL,
4246 -1ULL,
4247 -1ULL
4248 }
4249 }, 468 },
4250 { "maxih.sn", TILE_OPC_MAXIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 469 { "maxih", TILE_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1,
4251 TREG_SN, /* implicitly_written_register */ 470 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4252 1, /* can_bundle */
4253 {
4254 /* operands */
4255 { 7, 8, 0 },
4256 { 9, 10, 1 },
4257 { 0, },
4258 { 0, },
4259 { 0, }
4260 },
4261 {
4262 /* fixed_bit_masks */
4263 0x800000007ff00000ULL,
4264 0xfff8000000000000ULL,
4265 0ULL,
4266 0ULL,
4267 0ULL
4268 },
4269 {
4270 /* fixed_bit_values */
4271 0x0000000048500000ULL,
4272 0x3430000000000000ULL,
4273 -1ULL,
4274 -1ULL,
4275 -1ULL
4276 }
4277 }, 471 },
4278 { "mf", TILE_OPC_MF, 0x2 /* pipes */, 0 /* num_operands */, 472 { "maxih.sn", TILE_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1,
4279 TREG_ZERO, /* implicitly_written_register */ 473 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4280 1, /* can_bundle */
4281 {
4282 /* operands */
4283 { 0, },
4284 { },
4285 { 0, },
4286 { 0, },
4287 { 0, }
4288 },
4289 {
4290 /* fixed_bit_masks */
4291 0ULL,
4292 0xfbfff80000000000ULL,
4293 0ULL,
4294 0ULL,
4295 0ULL
4296 },
4297 {
4298 /* fixed_bit_values */
4299 -1ULL,
4300 0x400b780000000000ULL,
4301 -1ULL,
4302 -1ULL,
4303 -1ULL
4304 }
4305 }, 474 },
4306 { "mfspr", TILE_OPC_MFSPR, 0x2 /* pipes */, 2 /* num_operands */, 475 { "mf", TILE_OPC_MF, 0x2, 0, TREG_ZERO, 1,
4307 TREG_ZERO, /* implicitly_written_register */ 476 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
4308 1, /* can_bundle */
4309 {
4310 /* operands */
4311 { 0, },
4312 { 9, 25 },
4313 { 0, },
4314 { 0, },
4315 { 0, }
4316 },
4317 {
4318 /* fixed_bit_masks */
4319 0ULL,
4320 0xfbf8000000000000ULL,
4321 0ULL,
4322 0ULL,
4323 0ULL
4324 },
4325 {
4326 /* fixed_bit_values */
4327 -1ULL,
4328 0x3038000000000000ULL,
4329 -1ULL,
4330 -1ULL,
4331 -1ULL
4332 }
4333 }, 477 },
4334 { "minb_u", TILE_OPC_MINB_U, 0x3 /* pipes */, 3 /* num_operands */, 478 { "mfspr", TILE_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
4335 TREG_ZERO, /* implicitly_written_register */ 479 { { 0, }, { 9, 25 }, { 0, }, { 0, }, { 0, } },
4336 1, /* can_bundle */
4337 {
4338 /* operands */
4339 { 7, 8, 16 },
4340 { 9, 10, 17 },
4341 { 0, },
4342 { 0, },
4343 { 0, }
4344 },
4345 {
4346 /* fixed_bit_masks */
4347 0x800000007ffc0000ULL,
4348 0xfffe000000000000ULL,
4349 0ULL,
4350 0ULL,
4351 0ULL
4352 },
4353 {
4354 /* fixed_bit_values */
4355 0x0000000000440000ULL,
4356 0x0820000000000000ULL,
4357 -1ULL,
4358 -1ULL,
4359 -1ULL
4360 }
4361 }, 480 },
4362 { "minb_u.sn", TILE_OPC_MINB_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 481 { "minb_u", TILE_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1,
4363 TREG_SN, /* implicitly_written_register */ 482 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4364 1, /* can_bundle */
4365 {
4366 /* operands */
4367 { 7, 8, 16 },
4368 { 9, 10, 17 },
4369 { 0, },
4370 { 0, },
4371 { 0, }
4372 },
4373 {
4374 /* fixed_bit_masks */
4375 0x800000007ffc0000ULL,
4376 0xfffe000000000000ULL,
4377 0ULL,
4378 0ULL,
4379 0ULL
4380 },
4381 {
4382 /* fixed_bit_values */
4383 0x0000000008440000ULL,
4384 0x0c20000000000000ULL,
4385 -1ULL,
4386 -1ULL,
4387 -1ULL
4388 }
4389 }, 483 },
4390 { "minh", TILE_OPC_MINH, 0x3 /* pipes */, 3 /* num_operands */, 484 { "minb_u.sn", TILE_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1,
4391 TREG_ZERO, /* implicitly_written_register */ 485 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4392 1, /* can_bundle */
4393 {
4394 /* operands */
4395 { 7, 8, 16 },
4396 { 9, 10, 17 },
4397 { 0, },
4398 { 0, },
4399 { 0, }
4400 },
4401 {
4402 /* fixed_bit_masks */
4403 0x800000007ffc0000ULL,
4404 0xfffe000000000000ULL,
4405 0ULL,
4406 0ULL,
4407 0ULL
4408 },
4409 {
4410 /* fixed_bit_values */
4411 0x0000000000480000ULL,
4412 0x0822000000000000ULL,
4413 -1ULL,
4414 -1ULL,
4415 -1ULL
4416 }
4417 }, 486 },
4418 { "minh.sn", TILE_OPC_MINH_SN, 0x3 /* pipes */, 3 /* num_operands */, 487 { "minh", TILE_OPC_MINH, 0x3, 3, TREG_ZERO, 1,
4419 TREG_SN, /* implicitly_written_register */ 488 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4420 1, /* can_bundle */
4421 {
4422 /* operands */
4423 { 7, 8, 16 },
4424 { 9, 10, 17 },
4425 { 0, },
4426 { 0, },
4427 { 0, }
4428 },
4429 {
4430 /* fixed_bit_masks */
4431 0x800000007ffc0000ULL,
4432 0xfffe000000000000ULL,
4433 0ULL,
4434 0ULL,
4435 0ULL
4436 },
4437 {
4438 /* fixed_bit_values */
4439 0x0000000008480000ULL,
4440 0x0c22000000000000ULL,
4441 -1ULL,
4442 -1ULL,
4443 -1ULL
4444 }
4445 }, 489 },
4446 { "minib_u", TILE_OPC_MINIB_U, 0x3 /* pipes */, 3 /* num_operands */, 490 { "minh.sn", TILE_OPC_MINH_SN, 0x3, 3, TREG_SN, 1,
4447 TREG_ZERO, /* implicitly_written_register */ 491 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4448 1, /* can_bundle */
4449 {
4450 /* operands */
4451 { 7, 8, 0 },
4452 { 9, 10, 1 },
4453 { 0, },
4454 { 0, },
4455 { 0, }
4456 },
4457 {
4458 /* fixed_bit_masks */
4459 0x800000007ff00000ULL,
4460 0xfff8000000000000ULL,
4461 0ULL,
4462 0ULL,
4463 0ULL
4464 },
4465 {
4466 /* fixed_bit_values */
4467 0x0000000040600000ULL,
4468 0x3040000000000000ULL,
4469 -1ULL,
4470 -1ULL,
4471 -1ULL
4472 }
4473 }, 492 },
4474 { "minib_u.sn", TILE_OPC_MINIB_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 493 { "minib_u", TILE_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1,
4475 TREG_SN, /* implicitly_written_register */ 494 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4476 1, /* can_bundle */
4477 {
4478 /* operands */
4479 { 7, 8, 0 },
4480 { 9, 10, 1 },
4481 { 0, },
4482 { 0, },
4483 { 0, }
4484 },
4485 {
4486 /* fixed_bit_masks */
4487 0x800000007ff00000ULL,
4488 0xfff8000000000000ULL,
4489 0ULL,
4490 0ULL,
4491 0ULL
4492 },
4493 {
4494 /* fixed_bit_values */
4495 0x0000000048600000ULL,
4496 0x3440000000000000ULL,
4497 -1ULL,
4498 -1ULL,
4499 -1ULL
4500 }
4501 }, 495 },
4502 { "minih", TILE_OPC_MINIH, 0x3 /* pipes */, 3 /* num_operands */, 496 { "minib_u.sn", TILE_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1,
4503 TREG_ZERO, /* implicitly_written_register */ 497 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4504 1, /* can_bundle */
4505 {
4506 /* operands */
4507 { 7, 8, 0 },
4508 { 9, 10, 1 },
4509 { 0, },
4510 { 0, },
4511 { 0, }
4512 },
4513 {
4514 /* fixed_bit_masks */
4515 0x800000007ff00000ULL,
4516 0xfff8000000000000ULL,
4517 0ULL,
4518 0ULL,
4519 0ULL
4520 },
4521 {
4522 /* fixed_bit_values */
4523 0x0000000040700000ULL,
4524 0x3048000000000000ULL,
4525 -1ULL,
4526 -1ULL,
4527 -1ULL
4528 }
4529 }, 498 },
4530 { "minih.sn", TILE_OPC_MINIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 499 { "minih", TILE_OPC_MINIH, 0x3, 3, TREG_ZERO, 1,
4531 TREG_SN, /* implicitly_written_register */ 500 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4532 1, /* can_bundle */
4533 {
4534 /* operands */
4535 { 7, 8, 0 },
4536 { 9, 10, 1 },
4537 { 0, },
4538 { 0, },
4539 { 0, }
4540 },
4541 {
4542 /* fixed_bit_masks */
4543 0x800000007ff00000ULL,
4544 0xfff8000000000000ULL,
4545 0ULL,
4546 0ULL,
4547 0ULL
4548 },
4549 {
4550 /* fixed_bit_values */
4551 0x0000000048700000ULL,
4552 0x3448000000000000ULL,
4553 -1ULL,
4554 -1ULL,
4555 -1ULL
4556 }
4557 }, 501 },
4558 { "mm", TILE_OPC_MM, 0x3 /* pipes */, 5 /* num_operands */, 502 { "minih.sn", TILE_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1,
4559 TREG_ZERO, /* implicitly_written_register */ 503 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
4560 1, /* can_bundle */
4561 {
4562 /* operands */
4563 { 7, 8, 16, 26, 27 },
4564 { 9, 10, 17, 28, 29 },
4565 { 0, },
4566 { 0, },
4567 { 0, }
4568 },
4569 {
4570 /* fixed_bit_masks */
4571 0x8000000070000000ULL,
4572 0xf800000000000000ULL,
4573 0ULL,
4574 0ULL,
4575 0ULL
4576 },
4577 {
4578 /* fixed_bit_values */
4579 0x0000000060000000ULL,
4580 0x3800000000000000ULL,
4581 -1ULL,
4582 -1ULL,
4583 -1ULL
4584 }
4585 }, 504 },
4586 { "mnz", TILE_OPC_MNZ, 0xf /* pipes */, 3 /* num_operands */, 505 { "mm", TILE_OPC_MM, 0x3, 5, TREG_ZERO, 1,
4587 TREG_ZERO, /* implicitly_written_register */ 506 { { 7, 8, 16, 26, 27 }, { 9, 10, 17, 28, 29 }, { 0, }, { 0, }, { 0, } },
4588 1, /* can_bundle */
4589 {
4590 /* operands */
4591 { 7, 8, 16 },
4592 { 9, 10, 17 },
4593 { 11, 12, 18 },
4594 { 13, 14, 19 },
4595 { 0, }
4596 },
4597 {
4598 /* fixed_bit_masks */
4599 0x800000007ffc0000ULL,
4600 0xfffe000000000000ULL,
4601 0x80000000780c0000ULL,
4602 0xf806000000000000ULL,
4603 0ULL
4604 },
4605 {
4606 /* fixed_bit_values */
4607 0x0000000000540000ULL,
4608 0x0828000000000000ULL,
4609 0x8000000010000000ULL,
4610 0x9002000000000000ULL,
4611 -1ULL
4612 }
4613 }, 507 },
4614 { "mnz.sn", TILE_OPC_MNZ_SN, 0x3 /* pipes */, 3 /* num_operands */, 508 { "mnz", TILE_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
4615 TREG_SN, /* implicitly_written_register */ 509 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
4616 1, /* can_bundle */
4617 {
4618 /* operands */
4619 { 7, 8, 16 },
4620 { 9, 10, 17 },
4621 { 0, },
4622 { 0, },
4623 { 0, }
4624 },
4625 {
4626 /* fixed_bit_masks */
4627 0x800000007ffc0000ULL,
4628 0xfffe000000000000ULL,
4629 0ULL,
4630 0ULL,
4631 0ULL
4632 },
4633 {
4634 /* fixed_bit_values */
4635 0x0000000008540000ULL,
4636 0x0c28000000000000ULL,
4637 -1ULL,
4638 -1ULL,
4639 -1ULL
4640 }
4641 }, 510 },
4642 { "mnzb", TILE_OPC_MNZB, 0x3 /* pipes */, 3 /* num_operands */, 511 { "mnz.sn", TILE_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1,
4643 TREG_ZERO, /* implicitly_written_register */ 512 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4644 1, /* can_bundle */
4645 {
4646 /* operands */
4647 { 7, 8, 16 },
4648 { 9, 10, 17 },
4649 { 0, },
4650 { 0, },
4651 { 0, }
4652 },
4653 {
4654 /* fixed_bit_masks */
4655 0x800000007ffc0000ULL,
4656 0xfffe000000000000ULL,
4657 0ULL,
4658 0ULL,
4659 0ULL
4660 },
4661 {
4662 /* fixed_bit_values */
4663 0x00000000004c0000ULL,
4664 0x0824000000000000ULL,
4665 -1ULL,
4666 -1ULL,
4667 -1ULL
4668 }
4669 }, 513 },
4670 { "mnzb.sn", TILE_OPC_MNZB_SN, 0x3 /* pipes */, 3 /* num_operands */, 514 { "mnzb", TILE_OPC_MNZB, 0x3, 3, TREG_ZERO, 1,
4671 TREG_SN, /* implicitly_written_register */ 515 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4672 1, /* can_bundle */
4673 {
4674 /* operands */
4675 { 7, 8, 16 },
4676 { 9, 10, 17 },
4677 { 0, },
4678 { 0, },
4679 { 0, }
4680 },
4681 {
4682 /* fixed_bit_masks */
4683 0x800000007ffc0000ULL,
4684 0xfffe000000000000ULL,
4685 0ULL,
4686 0ULL,
4687 0ULL
4688 },
4689 {
4690 /* fixed_bit_values */
4691 0x00000000084c0000ULL,
4692 0x0c24000000000000ULL,
4693 -1ULL,
4694 -1ULL,
4695 -1ULL
4696 }
4697 }, 516 },
4698 { "mnzh", TILE_OPC_MNZH, 0x3 /* pipes */, 3 /* num_operands */, 517 { "mnzb.sn", TILE_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1,
4699 TREG_ZERO, /* implicitly_written_register */ 518 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4700 1, /* can_bundle */
4701 {
4702 /* operands */
4703 { 7, 8, 16 },
4704 { 9, 10, 17 },
4705 { 0, },
4706 { 0, },
4707 { 0, }
4708 },
4709 {
4710 /* fixed_bit_masks */
4711 0x800000007ffc0000ULL,
4712 0xfffe000000000000ULL,
4713 0ULL,
4714 0ULL,
4715 0ULL
4716 },
4717 {
4718 /* fixed_bit_values */
4719 0x0000000000500000ULL,
4720 0x0826000000000000ULL,
4721 -1ULL,
4722 -1ULL,
4723 -1ULL
4724 }
4725 }, 519 },
4726 { "mnzh.sn", TILE_OPC_MNZH_SN, 0x3 /* pipes */, 3 /* num_operands */, 520 { "mnzh", TILE_OPC_MNZH, 0x3, 3, TREG_ZERO, 1,
4727 TREG_SN, /* implicitly_written_register */ 521 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4728 1, /* can_bundle */
4729 {
4730 /* operands */
4731 { 7, 8, 16 },
4732 { 9, 10, 17 },
4733 { 0, },
4734 { 0, },
4735 { 0, }
4736 },
4737 {
4738 /* fixed_bit_masks */
4739 0x800000007ffc0000ULL,
4740 0xfffe000000000000ULL,
4741 0ULL,
4742 0ULL,
4743 0ULL
4744 },
4745 {
4746 /* fixed_bit_values */
4747 0x0000000008500000ULL,
4748 0x0c26000000000000ULL,
4749 -1ULL,
4750 -1ULL,
4751 -1ULL
4752 }
4753 }, 522 },
4754 { "mtspr", TILE_OPC_MTSPR, 0x2 /* pipes */, 2 /* num_operands */, 523 { "mnzh.sn", TILE_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1,
4755 TREG_ZERO, /* implicitly_written_register */ 524 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
4756 1, /* can_bundle */
4757 {
4758 /* operands */
4759 { 0, },
4760 { 30, 10 },
4761 { 0, },
4762 { 0, },
4763 { 0, }
4764 },
4765 {
4766 /* fixed_bit_masks */
4767 0ULL,
4768 0xfbf8000000000000ULL,
4769 0ULL,
4770 0ULL,
4771 0ULL
4772 },
4773 {
4774 /* fixed_bit_values */
4775 -1ULL,
4776 0x3050000000000000ULL,
4777 -1ULL,
4778 -1ULL,
4779 -1ULL
4780 }
4781 }, 525 },
4782 { "mulhh_ss", TILE_OPC_MULHH_SS, 0x5 /* pipes */, 3 /* num_operands */, 526 { "mtspr", TILE_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
4783 TREG_ZERO, /* implicitly_written_register */ 527 { { 0, }, { 30, 10 }, { 0, }, { 0, }, { 0, } },
4784 1, /* can_bundle */
4785 {
4786 /* operands */
4787 { 7, 8, 16 },
4788 { 0, },
4789 { 11, 12, 18 },
4790 { 0, },
4791 { 0, }
4792 },
4793 {
4794 /* fixed_bit_masks */
4795 0x800000007ffc0000ULL,
4796 0ULL,
4797 0x80000000780c0000ULL,
4798 0ULL,
4799 0ULL
4800 },
4801 {
4802 /* fixed_bit_values */
4803 0x0000000000680000ULL,
4804 -1ULL,
4805 0x8000000038000000ULL,
4806 -1ULL,
4807 -1ULL
4808 }
4809 }, 528 },
4810 { "mulhh_ss.sn", TILE_OPC_MULHH_SS_SN, 0x1 /* pipes */, 3 /* num_operands */, 529 { "mulhh_ss", TILE_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1,
4811 TREG_SN, /* implicitly_written_register */ 530 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
4812 1, /* can_bundle */
4813 {
4814 /* operands */
4815 { 7, 8, 16 },
4816 { 0, },
4817 { 0, },
4818 { 0, },
4819 { 0, }
4820 },
4821 {
4822 /* fixed_bit_masks */
4823 0x800000007ffc0000ULL,
4824 0ULL,
4825 0ULL,
4826 0ULL,
4827 0ULL
4828 },
4829 {
4830 /* fixed_bit_values */
4831 0x0000000008680000ULL,
4832 -1ULL,
4833 -1ULL,
4834 -1ULL,
4835 -1ULL
4836 }
4837 }, 531 },
4838 { "mulhh_su", TILE_OPC_MULHH_SU, 0x1 /* pipes */, 3 /* num_operands */, 532 { "mulhh_ss.sn", TILE_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1,
4839 TREG_ZERO, /* implicitly_written_register */ 533 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4840 1, /* can_bundle */
4841 {
4842 /* operands */
4843 { 7, 8, 16 },
4844 { 0, },
4845 { 0, },
4846 { 0, },
4847 { 0, }
4848 },
4849 {
4850 /* fixed_bit_masks */
4851 0x800000007ffc0000ULL,
4852 0ULL,
4853 0ULL,
4854 0ULL,
4855 0ULL
4856 },
4857 {
4858 /* fixed_bit_values */
4859 0x00000000006c0000ULL,
4860 -1ULL,
4861 -1ULL,
4862 -1ULL,
4863 -1ULL
4864 }
4865 }, 534 },
4866 { "mulhh_su.sn", TILE_OPC_MULHH_SU_SN, 0x1 /* pipes */, 3 /* num_operands */, 535 { "mulhh_su", TILE_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1,
4867 TREG_SN, /* implicitly_written_register */ 536 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4868 1, /* can_bundle */
4869 {
4870 /* operands */
4871 { 7, 8, 16 },
4872 { 0, },
4873 { 0, },
4874 { 0, },
4875 { 0, }
4876 },
4877 {
4878 /* fixed_bit_masks */
4879 0x800000007ffc0000ULL,
4880 0ULL,
4881 0ULL,
4882 0ULL,
4883 0ULL
4884 },
4885 {
4886 /* fixed_bit_values */
4887 0x00000000086c0000ULL,
4888 -1ULL,
4889 -1ULL,
4890 -1ULL,
4891 -1ULL
4892 }
4893 }, 537 },
4894 { "mulhh_uu", TILE_OPC_MULHH_UU, 0x5 /* pipes */, 3 /* num_operands */, 538 { "mulhh_su.sn", TILE_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1,
4895 TREG_ZERO, /* implicitly_written_register */ 539 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4896 1, /* can_bundle */
4897 {
4898 /* operands */
4899 { 7, 8, 16 },
4900 { 0, },
4901 { 11, 12, 18 },
4902 { 0, },
4903 { 0, }
4904 },
4905 {
4906 /* fixed_bit_masks */
4907 0x800000007ffc0000ULL,
4908 0ULL,
4909 0x80000000780c0000ULL,
4910 0ULL,
4911 0ULL
4912 },
4913 {
4914 /* fixed_bit_values */
4915 0x0000000000700000ULL,
4916 -1ULL,
4917 0x8000000038040000ULL,
4918 -1ULL,
4919 -1ULL
4920 }
4921 }, 540 },
4922 { "mulhh_uu.sn", TILE_OPC_MULHH_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 541 { "mulhh_uu", TILE_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1,
4923 TREG_SN, /* implicitly_written_register */ 542 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
4924 1, /* can_bundle */
4925 {
4926 /* operands */
4927 { 7, 8, 16 },
4928 { 0, },
4929 { 0, },
4930 { 0, },
4931 { 0, }
4932 },
4933 {
4934 /* fixed_bit_masks */
4935 0x800000007ffc0000ULL,
4936 0ULL,
4937 0ULL,
4938 0ULL,
4939 0ULL
4940 },
4941 {
4942 /* fixed_bit_values */
4943 0x0000000008700000ULL,
4944 -1ULL,
4945 -1ULL,
4946 -1ULL,
4947 -1ULL
4948 }
4949 }, 543 },
4950 { "mulhha_ss", TILE_OPC_MULHHA_SS, 0x5 /* pipes */, 3 /* num_operands */, 544 { "mulhh_uu.sn", TILE_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1,
4951 TREG_ZERO, /* implicitly_written_register */ 545 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
4952 1, /* can_bundle */
4953 {
4954 /* operands */
4955 { 21, 8, 16 },
4956 { 0, },
4957 { 31, 12, 18 },
4958 { 0, },
4959 { 0, }
4960 },
4961 {
4962 /* fixed_bit_masks */
4963 0x800000007ffc0000ULL,
4964 0ULL,
4965 0x80000000780c0000ULL,
4966 0ULL,
4967 0ULL
4968 },
4969 {
4970 /* fixed_bit_values */
4971 0x0000000000580000ULL,
4972 -1ULL,
4973 0x8000000040000000ULL,
4974 -1ULL,
4975 -1ULL
4976 }
4977 }, 546 },
4978 { "mulhha_ss.sn", TILE_OPC_MULHHA_SS_SN, 0x1 /* pipes */, 3 /* num_operands */, 547 { "mulhha_ss", TILE_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1,
4979 TREG_SN, /* implicitly_written_register */ 548 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
4980 1, /* can_bundle */
4981 {
4982 /* operands */
4983 { 21, 8, 16 },
4984 { 0, },
4985 { 0, },
4986 { 0, },
4987 { 0, }
4988 },
4989 {
4990 /* fixed_bit_masks */
4991 0x800000007ffc0000ULL,
4992 0ULL,
4993 0ULL,
4994 0ULL,
4995 0ULL
4996 },
4997 {
4998 /* fixed_bit_values */
4999 0x0000000008580000ULL,
5000 -1ULL,
5001 -1ULL,
5002 -1ULL,
5003 -1ULL
5004 }
5005 }, 549 },
5006 { "mulhha_su", TILE_OPC_MULHHA_SU, 0x1 /* pipes */, 3 /* num_operands */, 550 { "mulhha_ss.sn", TILE_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1,
5007 TREG_ZERO, /* implicitly_written_register */ 551 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5008 1, /* can_bundle */
5009 {
5010 /* operands */
5011 { 21, 8, 16 },
5012 { 0, },
5013 { 0, },
5014 { 0, },
5015 { 0, }
5016 },
5017 {
5018 /* fixed_bit_masks */
5019 0x800000007ffc0000ULL,
5020 0ULL,
5021 0ULL,
5022 0ULL,
5023 0ULL
5024 },
5025 {
5026 /* fixed_bit_values */
5027 0x00000000005c0000ULL,
5028 -1ULL,
5029 -1ULL,
5030 -1ULL,
5031 -1ULL
5032 }
5033 }, 552 },
5034 { "mulhha_su.sn", TILE_OPC_MULHHA_SU_SN, 0x1 /* pipes */, 3 /* num_operands */, 553 { "mulhha_su", TILE_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1,
5035 TREG_SN, /* implicitly_written_register */ 554 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5036 1, /* can_bundle */
5037 {
5038 /* operands */
5039 { 21, 8, 16 },
5040 { 0, },
5041 { 0, },
5042 { 0, },
5043 { 0, }
5044 },
5045 {
5046 /* fixed_bit_masks */
5047 0x800000007ffc0000ULL,
5048 0ULL,
5049 0ULL,
5050 0ULL,
5051 0ULL
5052 },
5053 {
5054 /* fixed_bit_values */
5055 0x00000000085c0000ULL,
5056 -1ULL,
5057 -1ULL,
5058 -1ULL,
5059 -1ULL
5060 }
5061 }, 555 },
5062 { "mulhha_uu", TILE_OPC_MULHHA_UU, 0x5 /* pipes */, 3 /* num_operands */, 556 { "mulhha_su.sn", TILE_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1,
5063 TREG_ZERO, /* implicitly_written_register */ 557 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5064 1, /* can_bundle */
5065 {
5066 /* operands */
5067 { 21, 8, 16 },
5068 { 0, },
5069 { 31, 12, 18 },
5070 { 0, },
5071 { 0, }
5072 },
5073 {
5074 /* fixed_bit_masks */
5075 0x800000007ffc0000ULL,
5076 0ULL,
5077 0x80000000780c0000ULL,
5078 0ULL,
5079 0ULL
5080 },
5081 {
5082 /* fixed_bit_values */
5083 0x0000000000600000ULL,
5084 -1ULL,
5085 0x8000000040040000ULL,
5086 -1ULL,
5087 -1ULL
5088 }
5089 }, 558 },
5090 { "mulhha_uu.sn", TILE_OPC_MULHHA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 559 { "mulhha_uu", TILE_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1,
5091 TREG_SN, /* implicitly_written_register */ 560 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
5092 1, /* can_bundle */
5093 {
5094 /* operands */
5095 { 21, 8, 16 },
5096 { 0, },
5097 { 0, },
5098 { 0, },
5099 { 0, }
5100 },
5101 {
5102 /* fixed_bit_masks */
5103 0x800000007ffc0000ULL,
5104 0ULL,
5105 0ULL,
5106 0ULL,
5107 0ULL
5108 },
5109 {
5110 /* fixed_bit_values */
5111 0x0000000008600000ULL,
5112 -1ULL,
5113 -1ULL,
5114 -1ULL,
5115 -1ULL
5116 }
5117 }, 561 },
5118 { "mulhhsa_uu", TILE_OPC_MULHHSA_UU, 0x1 /* pipes */, 3 /* num_operands */, 562 { "mulhha_uu.sn", TILE_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1,
5119 TREG_ZERO, /* implicitly_written_register */ 563 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5120 1, /* can_bundle */
5121 {
5122 /* operands */
5123 { 21, 8, 16 },
5124 { 0, },
5125 { 0, },
5126 { 0, },
5127 { 0, }
5128 },
5129 {
5130 /* fixed_bit_masks */
5131 0x800000007ffc0000ULL,
5132 0ULL,
5133 0ULL,
5134 0ULL,
5135 0ULL
5136 },
5137 {
5138 /* fixed_bit_values */
5139 0x0000000000640000ULL,
5140 -1ULL,
5141 -1ULL,
5142 -1ULL,
5143 -1ULL
5144 }
5145 }, 564 },
5146 { "mulhhsa_uu.sn", TILE_OPC_MULHHSA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 565 { "mulhhsa_uu", TILE_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1,
5147 TREG_SN, /* implicitly_written_register */ 566 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5148 1, /* can_bundle */
5149 {
5150 /* operands */
5151 { 21, 8, 16 },
5152 { 0, },
5153 { 0, },
5154 { 0, },
5155 { 0, }
5156 },
5157 {
5158 /* fixed_bit_masks */
5159 0x800000007ffc0000ULL,
5160 0ULL,
5161 0ULL,
5162 0ULL,
5163 0ULL
5164 },
5165 {
5166 /* fixed_bit_values */
5167 0x0000000008640000ULL,
5168 -1ULL,
5169 -1ULL,
5170 -1ULL,
5171 -1ULL
5172 }
5173 }, 567 },
5174 { "mulhl_ss", TILE_OPC_MULHL_SS, 0x1 /* pipes */, 3 /* num_operands */, 568 { "mulhhsa_uu.sn", TILE_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1,
5175 TREG_ZERO, /* implicitly_written_register */ 569 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5176 1, /* can_bundle */
5177 {
5178 /* operands */
5179 { 7, 8, 16 },
5180 { 0, },
5181 { 0, },
5182 { 0, },
5183 { 0, }
5184 },
5185 {
5186 /* fixed_bit_masks */
5187 0x800000007ffc0000ULL,
5188 0ULL,
5189 0ULL,
5190 0ULL,
5191 0ULL
5192 },
5193 {
5194 /* fixed_bit_values */
5195 0x0000000000880000ULL,
5196 -1ULL,
5197 -1ULL,
5198 -1ULL,
5199 -1ULL
5200 }
5201 }, 570 },
5202 { "mulhl_ss.sn", TILE_OPC_MULHL_SS_SN, 0x1 /* pipes */, 3 /* num_operands */, 571 { "mulhl_ss", TILE_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1,
5203 TREG_SN, /* implicitly_written_register */ 572 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5204 1, /* can_bundle */
5205 {
5206 /* operands */
5207 { 7, 8, 16 },
5208 { 0, },
5209 { 0, },
5210 { 0, },
5211 { 0, }
5212 },
5213 {
5214 /* fixed_bit_masks */
5215 0x800000007ffc0000ULL,
5216 0ULL,
5217 0ULL,
5218 0ULL,
5219 0ULL
5220 },
5221 {
5222 /* fixed_bit_values */
5223 0x0000000008880000ULL,
5224 -1ULL,
5225 -1ULL,
5226 -1ULL,
5227 -1ULL
5228 }
5229 }, 573 },
5230 { "mulhl_su", TILE_OPC_MULHL_SU, 0x1 /* pipes */, 3 /* num_operands */, 574 { "mulhl_ss.sn", TILE_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1,
5231 TREG_ZERO, /* implicitly_written_register */ 575 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5232 1, /* can_bundle */
5233 {
5234 /* operands */
5235 { 7, 8, 16 },
5236 { 0, },
5237 { 0, },
5238 { 0, },
5239 { 0, }
5240 },
5241 {
5242 /* fixed_bit_masks */
5243 0x800000007ffc0000ULL,
5244 0ULL,
5245 0ULL,
5246 0ULL,
5247 0ULL
5248 },
5249 {
5250 /* fixed_bit_values */
5251 0x00000000008c0000ULL,
5252 -1ULL,
5253 -1ULL,
5254 -1ULL,
5255 -1ULL
5256 }
5257 }, 576 },
5258 { "mulhl_su.sn", TILE_OPC_MULHL_SU_SN, 0x1 /* pipes */, 3 /* num_operands */, 577 { "mulhl_su", TILE_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1,
5259 TREG_SN, /* implicitly_written_register */ 578 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5260 1, /* can_bundle */
5261 {
5262 /* operands */
5263 { 7, 8, 16 },
5264 { 0, },
5265 { 0, },
5266 { 0, },
5267 { 0, }
5268 },
5269 {
5270 /* fixed_bit_masks */
5271 0x800000007ffc0000ULL,
5272 0ULL,
5273 0ULL,
5274 0ULL,
5275 0ULL
5276 },
5277 {
5278 /* fixed_bit_values */
5279 0x00000000088c0000ULL,
5280 -1ULL,
5281 -1ULL,
5282 -1ULL,
5283 -1ULL
5284 }
5285 }, 579 },
5286 { "mulhl_us", TILE_OPC_MULHL_US, 0x1 /* pipes */, 3 /* num_operands */, 580 { "mulhl_su.sn", TILE_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1,
5287 TREG_ZERO, /* implicitly_written_register */ 581 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5288 1, /* can_bundle */
5289 {
5290 /* operands */
5291 { 7, 8, 16 },
5292 { 0, },
5293 { 0, },
5294 { 0, },
5295 { 0, }
5296 },
5297 {
5298 /* fixed_bit_masks */
5299 0x800000007ffc0000ULL,
5300 0ULL,
5301 0ULL,
5302 0ULL,
5303 0ULL
5304 },
5305 {
5306 /* fixed_bit_values */
5307 0x0000000000900000ULL,
5308 -1ULL,
5309 -1ULL,
5310 -1ULL,
5311 -1ULL
5312 }
5313 }, 582 },
5314 { "mulhl_us.sn", TILE_OPC_MULHL_US_SN, 0x1 /* pipes */, 3 /* num_operands */, 583 { "mulhl_us", TILE_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1,
5315 TREG_SN, /* implicitly_written_register */ 584 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5316 1, /* can_bundle */
5317 {
5318 /* operands */
5319 { 7, 8, 16 },
5320 { 0, },
5321 { 0, },
5322 { 0, },
5323 { 0, }
5324 },
5325 {
5326 /* fixed_bit_masks */
5327 0x800000007ffc0000ULL,
5328 0ULL,
5329 0ULL,
5330 0ULL,
5331 0ULL
5332 },
5333 {
5334 /* fixed_bit_values */
5335 0x0000000008900000ULL,
5336 -1ULL,
5337 -1ULL,
5338 -1ULL,
5339 -1ULL
5340 }
5341 }, 585 },
5342 { "mulhl_uu", TILE_OPC_MULHL_UU, 0x1 /* pipes */, 3 /* num_operands */, 586 { "mulhl_us.sn", TILE_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1,
5343 TREG_ZERO, /* implicitly_written_register */ 587 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5344 1, /* can_bundle */
5345 {
5346 /* operands */
5347 { 7, 8, 16 },
5348 { 0, },
5349 { 0, },
5350 { 0, },
5351 { 0, }
5352 },
5353 {
5354 /* fixed_bit_masks */
5355 0x800000007ffc0000ULL,
5356 0ULL,
5357 0ULL,
5358 0ULL,
5359 0ULL
5360 },
5361 {
5362 /* fixed_bit_values */
5363 0x0000000000940000ULL,
5364 -1ULL,
5365 -1ULL,
5366 -1ULL,
5367 -1ULL
5368 }
5369 }, 588 },
5370 { "mulhl_uu.sn", TILE_OPC_MULHL_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 589 { "mulhl_uu", TILE_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1,
5371 TREG_SN, /* implicitly_written_register */ 590 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5372 1, /* can_bundle */
5373 {
5374 /* operands */
5375 { 7, 8, 16 },
5376 { 0, },
5377 { 0, },
5378 { 0, },
5379 { 0, }
5380 },
5381 {
5382 /* fixed_bit_masks */
5383 0x800000007ffc0000ULL,
5384 0ULL,
5385 0ULL,
5386 0ULL,
5387 0ULL
5388 },
5389 {
5390 /* fixed_bit_values */
5391 0x0000000008940000ULL,
5392 -1ULL,
5393 -1ULL,
5394 -1ULL,
5395 -1ULL
5396 }
5397 }, 591 },
5398 { "mulhla_ss", TILE_OPC_MULHLA_SS, 0x1 /* pipes */, 3 /* num_operands */, 592 { "mulhl_uu.sn", TILE_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1,
5399 TREG_ZERO, /* implicitly_written_register */ 593 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5400 1, /* can_bundle */
5401 {
5402 /* operands */
5403 { 21, 8, 16 },
5404 { 0, },
5405 { 0, },
5406 { 0, },
5407 { 0, }
5408 },
5409 {
5410 /* fixed_bit_masks */
5411 0x800000007ffc0000ULL,
5412 0ULL,
5413 0ULL,
5414 0ULL,
5415 0ULL
5416 },
5417 {
5418 /* fixed_bit_values */
5419 0x0000000000740000ULL,
5420 -1ULL,
5421 -1ULL,
5422 -1ULL,
5423 -1ULL
5424 }
5425 }, 594 },
5426 { "mulhla_ss.sn", TILE_OPC_MULHLA_SS_SN, 0x1 /* pipes */, 3 /* num_operands */, 595 { "mulhla_ss", TILE_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1,
5427 TREG_SN, /* implicitly_written_register */ 596 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5428 1, /* can_bundle */
5429 {
5430 /* operands */
5431 { 21, 8, 16 },
5432 { 0, },
5433 { 0, },
5434 { 0, },
5435 { 0, }
5436 },
5437 {
5438 /* fixed_bit_masks */
5439 0x800000007ffc0000ULL,
5440 0ULL,
5441 0ULL,
5442 0ULL,
5443 0ULL
5444 },
5445 {
5446 /* fixed_bit_values */
5447 0x0000000008740000ULL,
5448 -1ULL,
5449 -1ULL,
5450 -1ULL,
5451 -1ULL
5452 }
5453 }, 597 },
5454 { "mulhla_su", TILE_OPC_MULHLA_SU, 0x1 /* pipes */, 3 /* num_operands */, 598 { "mulhla_ss.sn", TILE_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1,
5455 TREG_ZERO, /* implicitly_written_register */ 599 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5456 1, /* can_bundle */
5457 {
5458 /* operands */
5459 { 21, 8, 16 },
5460 { 0, },
5461 { 0, },
5462 { 0, },
5463 { 0, }
5464 },
5465 {
5466 /* fixed_bit_masks */
5467 0x800000007ffc0000ULL,
5468 0ULL,
5469 0ULL,
5470 0ULL,
5471 0ULL
5472 },
5473 {
5474 /* fixed_bit_values */
5475 0x0000000000780000ULL,
5476 -1ULL,
5477 -1ULL,
5478 -1ULL,
5479 -1ULL
5480 }
5481 }, 600 },
5482 { "mulhla_su.sn", TILE_OPC_MULHLA_SU_SN, 0x1 /* pipes */, 3 /* num_operands */, 601 { "mulhla_su", TILE_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1,
5483 TREG_SN, /* implicitly_written_register */ 602 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5484 1, /* can_bundle */
5485 {
5486 /* operands */
5487 { 21, 8, 16 },
5488 { 0, },
5489 { 0, },
5490 { 0, },
5491 { 0, }
5492 },
5493 {
5494 /* fixed_bit_masks */
5495 0x800000007ffc0000ULL,
5496 0ULL,
5497 0ULL,
5498 0ULL,
5499 0ULL
5500 },
5501 {
5502 /* fixed_bit_values */
5503 0x0000000008780000ULL,
5504 -1ULL,
5505 -1ULL,
5506 -1ULL,
5507 -1ULL
5508 }
5509 }, 603 },
5510 { "mulhla_us", TILE_OPC_MULHLA_US, 0x1 /* pipes */, 3 /* num_operands */, 604 { "mulhla_su.sn", TILE_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1,
5511 TREG_ZERO, /* implicitly_written_register */ 605 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5512 1, /* can_bundle */
5513 {
5514 /* operands */
5515 { 21, 8, 16 },
5516 { 0, },
5517 { 0, },
5518 { 0, },
5519 { 0, }
5520 },
5521 {
5522 /* fixed_bit_masks */
5523 0x800000007ffc0000ULL,
5524 0ULL,
5525 0ULL,
5526 0ULL,
5527 0ULL
5528 },
5529 {
5530 /* fixed_bit_values */
5531 0x00000000007c0000ULL,
5532 -1ULL,
5533 -1ULL,
5534 -1ULL,
5535 -1ULL
5536 }
5537 }, 606 },
5538 { "mulhla_us.sn", TILE_OPC_MULHLA_US_SN, 0x1 /* pipes */, 3 /* num_operands */, 607 { "mulhla_us", TILE_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1,
5539 TREG_SN, /* implicitly_written_register */ 608 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5540 1, /* can_bundle */
5541 {
5542 /* operands */
5543 { 21, 8, 16 },
5544 { 0, },
5545 { 0, },
5546 { 0, },
5547 { 0, }
5548 },
5549 {
5550 /* fixed_bit_masks */
5551 0x800000007ffc0000ULL,
5552 0ULL,
5553 0ULL,
5554 0ULL,
5555 0ULL
5556 },
5557 {
5558 /* fixed_bit_values */
5559 0x00000000087c0000ULL,
5560 -1ULL,
5561 -1ULL,
5562 -1ULL,
5563 -1ULL
5564 }
5565 }, 609 },
5566 { "mulhla_uu", TILE_OPC_MULHLA_UU, 0x1 /* pipes */, 3 /* num_operands */, 610 { "mulhla_us.sn", TILE_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1,
5567 TREG_ZERO, /* implicitly_written_register */ 611 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5568 1, /* can_bundle */
5569 {
5570 /* operands */
5571 { 21, 8, 16 },
5572 { 0, },
5573 { 0, },
5574 { 0, },
5575 { 0, }
5576 },
5577 {
5578 /* fixed_bit_masks */
5579 0x800000007ffc0000ULL,
5580 0ULL,
5581 0ULL,
5582 0ULL,
5583 0ULL
5584 },
5585 {
5586 /* fixed_bit_values */
5587 0x0000000000800000ULL,
5588 -1ULL,
5589 -1ULL,
5590 -1ULL,
5591 -1ULL
5592 }
5593 }, 612 },
5594 { "mulhla_uu.sn", TILE_OPC_MULHLA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 613 { "mulhla_uu", TILE_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1,
5595 TREG_SN, /* implicitly_written_register */ 614 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5596 1, /* can_bundle */
5597 {
5598 /* operands */
5599 { 21, 8, 16 },
5600 { 0, },
5601 { 0, },
5602 { 0, },
5603 { 0, }
5604 },
5605 {
5606 /* fixed_bit_masks */
5607 0x800000007ffc0000ULL,
5608 0ULL,
5609 0ULL,
5610 0ULL,
5611 0ULL
5612 },
5613 {
5614 /* fixed_bit_values */
5615 0x0000000008800000ULL,
5616 -1ULL,
5617 -1ULL,
5618 -1ULL,
5619 -1ULL
5620 }
5621 }, 615 },
5622 { "mulhlsa_uu", TILE_OPC_MULHLSA_UU, 0x5 /* pipes */, 3 /* num_operands */, 616 { "mulhla_uu.sn", TILE_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1,
5623 TREG_ZERO, /* implicitly_written_register */ 617 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5624 1, /* can_bundle */
5625 {
5626 /* operands */
5627 { 21, 8, 16 },
5628 { 0, },
5629 { 31, 12, 18 },
5630 { 0, },
5631 { 0, }
5632 },
5633 {
5634 /* fixed_bit_masks */
5635 0x800000007ffc0000ULL,
5636 0ULL,
5637 0x80000000780c0000ULL,
5638 0ULL,
5639 0ULL
5640 },
5641 {
5642 /* fixed_bit_values */
5643 0x0000000000840000ULL,
5644 -1ULL,
5645 0x8000000030000000ULL,
5646 -1ULL,
5647 -1ULL
5648 }
5649 }, 618 },
5650 { "mulhlsa_uu.sn", TILE_OPC_MULHLSA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 619 { "mulhlsa_uu", TILE_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1,
5651 TREG_SN, /* implicitly_written_register */ 620 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
5652 1, /* can_bundle */
5653 {
5654 /* operands */
5655 { 21, 8, 16 },
5656 { 0, },
5657 { 0, },
5658 { 0, },
5659 { 0, }
5660 },
5661 {
5662 /* fixed_bit_masks */
5663 0x800000007ffc0000ULL,
5664 0ULL,
5665 0ULL,
5666 0ULL,
5667 0ULL
5668 },
5669 {
5670 /* fixed_bit_values */
5671 0x0000000008840000ULL,
5672 -1ULL,
5673 -1ULL,
5674 -1ULL,
5675 -1ULL
5676 }
5677 }, 621 },
5678 { "mulll_ss", TILE_OPC_MULLL_SS, 0x5 /* pipes */, 3 /* num_operands */, 622 { "mulhlsa_uu.sn", TILE_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1,
5679 TREG_ZERO, /* implicitly_written_register */ 623 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5680 1, /* can_bundle */
5681 {
5682 /* operands */
5683 { 7, 8, 16 },
5684 { 0, },
5685 { 11, 12, 18 },
5686 { 0, },
5687 { 0, }
5688 },
5689 {
5690 /* fixed_bit_masks */
5691 0x800000007ffc0000ULL,
5692 0ULL,
5693 0x80000000780c0000ULL,
5694 0ULL,
5695 0ULL
5696 },
5697 {
5698 /* fixed_bit_values */
5699 0x0000000000a80000ULL,
5700 -1ULL,
5701 0x8000000038080000ULL,
5702 -1ULL,
5703 -1ULL
5704 }
5705 }, 624 },
5706 { "mulll_ss.sn", TILE_OPC_MULLL_SS_SN, 0x1 /* pipes */, 3 /* num_operands */, 625 { "mulll_ss", TILE_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1,
5707 TREG_SN, /* implicitly_written_register */ 626 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
5708 1, /* can_bundle */
5709 {
5710 /* operands */
5711 { 7, 8, 16 },
5712 { 0, },
5713 { 0, },
5714 { 0, },
5715 { 0, }
5716 },
5717 {
5718 /* fixed_bit_masks */
5719 0x800000007ffc0000ULL,
5720 0ULL,
5721 0ULL,
5722 0ULL,
5723 0ULL
5724 },
5725 {
5726 /* fixed_bit_values */
5727 0x0000000008a80000ULL,
5728 -1ULL,
5729 -1ULL,
5730 -1ULL,
5731 -1ULL
5732 }
5733 }, 627 },
5734 { "mulll_su", TILE_OPC_MULLL_SU, 0x1 /* pipes */, 3 /* num_operands */, 628 { "mulll_ss.sn", TILE_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1,
5735 TREG_ZERO, /* implicitly_written_register */ 629 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5736 1, /* can_bundle */
5737 {
5738 /* operands */
5739 { 7, 8, 16 },
5740 { 0, },
5741 { 0, },
5742 { 0, },
5743 { 0, }
5744 },
5745 {
5746 /* fixed_bit_masks */
5747 0x800000007ffc0000ULL,
5748 0ULL,
5749 0ULL,
5750 0ULL,
5751 0ULL
5752 },
5753 {
5754 /* fixed_bit_values */
5755 0x0000000000ac0000ULL,
5756 -1ULL,
5757 -1ULL,
5758 -1ULL,
5759 -1ULL
5760 }
5761 }, 630 },
5762 { "mulll_su.sn", TILE_OPC_MULLL_SU_SN, 0x1 /* pipes */, 3 /* num_operands */, 631 { "mulll_su", TILE_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1,
5763 TREG_SN, /* implicitly_written_register */ 632 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5764 1, /* can_bundle */
5765 {
5766 /* operands */
5767 { 7, 8, 16 },
5768 { 0, },
5769 { 0, },
5770 { 0, },
5771 { 0, }
5772 },
5773 {
5774 /* fixed_bit_masks */
5775 0x800000007ffc0000ULL,
5776 0ULL,
5777 0ULL,
5778 0ULL,
5779 0ULL
5780 },
5781 {
5782 /* fixed_bit_values */
5783 0x0000000008ac0000ULL,
5784 -1ULL,
5785 -1ULL,
5786 -1ULL,
5787 -1ULL
5788 }
5789 }, 633 },
5790 { "mulll_uu", TILE_OPC_MULLL_UU, 0x5 /* pipes */, 3 /* num_operands */, 634 { "mulll_su.sn", TILE_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1,
5791 TREG_ZERO, /* implicitly_written_register */ 635 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5792 1, /* can_bundle */
5793 {
5794 /* operands */
5795 { 7, 8, 16 },
5796 { 0, },
5797 { 11, 12, 18 },
5798 { 0, },
5799 { 0, }
5800 },
5801 {
5802 /* fixed_bit_masks */
5803 0x800000007ffc0000ULL,
5804 0ULL,
5805 0x80000000780c0000ULL,
5806 0ULL,
5807 0ULL
5808 },
5809 {
5810 /* fixed_bit_values */
5811 0x0000000000b00000ULL,
5812 -1ULL,
5813 0x80000000380c0000ULL,
5814 -1ULL,
5815 -1ULL
5816 }
5817 }, 636 },
5818 { "mulll_uu.sn", TILE_OPC_MULLL_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 637 { "mulll_uu", TILE_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1,
5819 TREG_SN, /* implicitly_written_register */ 638 { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
5820 1, /* can_bundle */
5821 {
5822 /* operands */
5823 { 7, 8, 16 },
5824 { 0, },
5825 { 0, },
5826 { 0, },
5827 { 0, }
5828 },
5829 {
5830 /* fixed_bit_masks */
5831 0x800000007ffc0000ULL,
5832 0ULL,
5833 0ULL,
5834 0ULL,
5835 0ULL
5836 },
5837 {
5838 /* fixed_bit_values */
5839 0x0000000008b00000ULL,
5840 -1ULL,
5841 -1ULL,
5842 -1ULL,
5843 -1ULL
5844 }
5845 }, 639 },
5846 { "mullla_ss", TILE_OPC_MULLLA_SS, 0x5 /* pipes */, 3 /* num_operands */, 640 { "mulll_uu.sn", TILE_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1,
5847 TREG_ZERO, /* implicitly_written_register */ 641 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5848 1, /* can_bundle */
5849 {
5850 /* operands */
5851 { 21, 8, 16 },
5852 { 0, },
5853 { 31, 12, 18 },
5854 { 0, },
5855 { 0, }
5856 },
5857 {
5858 /* fixed_bit_masks */
5859 0x800000007ffc0000ULL,
5860 0ULL,
5861 0x80000000780c0000ULL,
5862 0ULL,
5863 0ULL
5864 },
5865 {
5866 /* fixed_bit_values */
5867 0x0000000000980000ULL,
5868 -1ULL,
5869 0x8000000040080000ULL,
5870 -1ULL,
5871 -1ULL
5872 }
5873 }, 642 },
5874 { "mullla_ss.sn", TILE_OPC_MULLLA_SS_SN, 0x1 /* pipes */, 3 /* num_operands */, 643 { "mullla_ss", TILE_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1,
5875 TREG_SN, /* implicitly_written_register */ 644 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
5876 1, /* can_bundle */
5877 {
5878 /* operands */
5879 { 21, 8, 16 },
5880 { 0, },
5881 { 0, },
5882 { 0, },
5883 { 0, }
5884 },
5885 {
5886 /* fixed_bit_masks */
5887 0x800000007ffc0000ULL,
5888 0ULL,
5889 0ULL,
5890 0ULL,
5891 0ULL
5892 },
5893 {
5894 /* fixed_bit_values */
5895 0x0000000008980000ULL,
5896 -1ULL,
5897 -1ULL,
5898 -1ULL,
5899 -1ULL
5900 }
5901 }, 645 },
5902 { "mullla_su", TILE_OPC_MULLLA_SU, 0x1 /* pipes */, 3 /* num_operands */, 646 { "mullla_ss.sn", TILE_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1,
5903 TREG_ZERO, /* implicitly_written_register */ 647 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5904 1, /* can_bundle */
5905 {
5906 /* operands */
5907 { 21, 8, 16 },
5908 { 0, },
5909 { 0, },
5910 { 0, },
5911 { 0, }
5912 },
5913 {
5914 /* fixed_bit_masks */
5915 0x800000007ffc0000ULL,
5916 0ULL,
5917 0ULL,
5918 0ULL,
5919 0ULL
5920 },
5921 {
5922 /* fixed_bit_values */
5923 0x00000000009c0000ULL,
5924 -1ULL,
5925 -1ULL,
5926 -1ULL,
5927 -1ULL
5928 }
5929 }, 648 },
5930 { "mullla_su.sn", TILE_OPC_MULLLA_SU_SN, 0x1 /* pipes */, 3 /* num_operands */, 649 { "mullla_su", TILE_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1,
5931 TREG_SN, /* implicitly_written_register */ 650 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5932 1, /* can_bundle */
5933 {
5934 /* operands */
5935 { 21, 8, 16 },
5936 { 0, },
5937 { 0, },
5938 { 0, },
5939 { 0, }
5940 },
5941 {
5942 /* fixed_bit_masks */
5943 0x800000007ffc0000ULL,
5944 0ULL,
5945 0ULL,
5946 0ULL,
5947 0ULL
5948 },
5949 {
5950 /* fixed_bit_values */
5951 0x00000000089c0000ULL,
5952 -1ULL,
5953 -1ULL,
5954 -1ULL,
5955 -1ULL
5956 }
5957 }, 651 },
5958 { "mullla_uu", TILE_OPC_MULLLA_UU, 0x5 /* pipes */, 3 /* num_operands */, 652 { "mullla_su.sn", TILE_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1,
5959 TREG_ZERO, /* implicitly_written_register */ 653 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
5960 1, /* can_bundle */
5961 {
5962 /* operands */
5963 { 21, 8, 16 },
5964 { 0, },
5965 { 31, 12, 18 },
5966 { 0, },
5967 { 0, }
5968 },
5969 {
5970 /* fixed_bit_masks */
5971 0x800000007ffc0000ULL,
5972 0ULL,
5973 0x80000000780c0000ULL,
5974 0ULL,
5975 0ULL
5976 },
5977 {
5978 /* fixed_bit_values */
5979 0x0000000000a00000ULL,
5980 -1ULL,
5981 0x80000000400c0000ULL,
5982 -1ULL,
5983 -1ULL
5984 }
5985 }, 654 },
5986 { "mullla_uu.sn", TILE_OPC_MULLLA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 655 { "mullla_uu", TILE_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1,
5987 TREG_SN, /* implicitly_written_register */ 656 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
5988 1, /* can_bundle */
5989 {
5990 /* operands */
5991 { 21, 8, 16 },
5992 { 0, },
5993 { 0, },
5994 { 0, },
5995 { 0, }
5996 },
5997 {
5998 /* fixed_bit_masks */
5999 0x800000007ffc0000ULL,
6000 0ULL,
6001 0ULL,
6002 0ULL,
6003 0ULL
6004 },
6005 {
6006 /* fixed_bit_values */
6007 0x0000000008a00000ULL,
6008 -1ULL,
6009 -1ULL,
6010 -1ULL,
6011 -1ULL
6012 }
6013 }, 657 },
6014 { "mulllsa_uu", TILE_OPC_MULLLSA_UU, 0x1 /* pipes */, 3 /* num_operands */, 658 { "mullla_uu.sn", TILE_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1,
6015 TREG_ZERO, /* implicitly_written_register */ 659 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6016 1, /* can_bundle */
6017 {
6018 /* operands */
6019 { 21, 8, 16 },
6020 { 0, },
6021 { 0, },
6022 { 0, },
6023 { 0, }
6024 },
6025 {
6026 /* fixed_bit_masks */
6027 0x800000007ffc0000ULL,
6028 0ULL,
6029 0ULL,
6030 0ULL,
6031 0ULL
6032 },
6033 {
6034 /* fixed_bit_values */
6035 0x0000000000a40000ULL,
6036 -1ULL,
6037 -1ULL,
6038 -1ULL,
6039 -1ULL
6040 }
6041 }, 660 },
6042 { "mulllsa_uu.sn", TILE_OPC_MULLLSA_UU_SN, 0x1 /* pipes */, 3 /* num_operands */, 661 { "mulllsa_uu", TILE_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1,
6043 TREG_SN, /* implicitly_written_register */ 662 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6044 1, /* can_bundle */
6045 {
6046 /* operands */
6047 { 21, 8, 16 },
6048 { 0, },
6049 { 0, },
6050 { 0, },
6051 { 0, }
6052 },
6053 {
6054 /* fixed_bit_masks */
6055 0x800000007ffc0000ULL,
6056 0ULL,
6057 0ULL,
6058 0ULL,
6059 0ULL
6060 },
6061 {
6062 /* fixed_bit_values */
6063 0x0000000008a40000ULL,
6064 -1ULL,
6065 -1ULL,
6066 -1ULL,
6067 -1ULL
6068 }
6069 }, 663 },
6070 { "mvnz", TILE_OPC_MVNZ, 0x5 /* pipes */, 3 /* num_operands */, 664 { "mulllsa_uu.sn", TILE_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1,
6071 TREG_ZERO, /* implicitly_written_register */ 665 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6072 1, /* can_bundle */
6073 {
6074 /* operands */
6075 { 21, 8, 16 },
6076 { 0, },
6077 { 31, 12, 18 },
6078 { 0, },
6079 { 0, }
6080 },
6081 {
6082 /* fixed_bit_masks */
6083 0x800000007ffc0000ULL,
6084 0ULL,
6085 0x80000000780c0000ULL,
6086 0ULL,
6087 0ULL
6088 },
6089 {
6090 /* fixed_bit_values */
6091 0x0000000000b40000ULL,
6092 -1ULL,
6093 0x8000000010040000ULL,
6094 -1ULL,
6095 -1ULL
6096 }
6097 }, 666 },
6098 { "mvnz.sn", TILE_OPC_MVNZ_SN, 0x1 /* pipes */, 3 /* num_operands */, 667 { "mvnz", TILE_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1,
6099 TREG_SN, /* implicitly_written_register */ 668 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
6100 1, /* can_bundle */
6101 {
6102 /* operands */
6103 { 21, 8, 16 },
6104 { 0, },
6105 { 0, },
6106 { 0, },
6107 { 0, }
6108 },
6109 {
6110 /* fixed_bit_masks */
6111 0x800000007ffc0000ULL,
6112 0ULL,
6113 0ULL,
6114 0ULL,
6115 0ULL
6116 },
6117 {
6118 /* fixed_bit_values */
6119 0x0000000008b40000ULL,
6120 -1ULL,
6121 -1ULL,
6122 -1ULL,
6123 -1ULL
6124 }
6125 }, 669 },
6126 { "mvz", TILE_OPC_MVZ, 0x5 /* pipes */, 3 /* num_operands */, 670 { "mvnz.sn", TILE_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1,
6127 TREG_ZERO, /* implicitly_written_register */ 671 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6128 1, /* can_bundle */
6129 {
6130 /* operands */
6131 { 21, 8, 16 },
6132 { 0, },
6133 { 31, 12, 18 },
6134 { 0, },
6135 { 0, }
6136 },
6137 {
6138 /* fixed_bit_masks */
6139 0x800000007ffc0000ULL,
6140 0ULL,
6141 0x80000000780c0000ULL,
6142 0ULL,
6143 0ULL
6144 },
6145 {
6146 /* fixed_bit_values */
6147 0x0000000000b80000ULL,
6148 -1ULL,
6149 0x8000000010080000ULL,
6150 -1ULL,
6151 -1ULL
6152 }
6153 }, 672 },
6154 { "mvz.sn", TILE_OPC_MVZ_SN, 0x1 /* pipes */, 3 /* num_operands */, 673 { "mvz", TILE_OPC_MVZ, 0x5, 3, TREG_ZERO, 1,
6155 TREG_SN, /* implicitly_written_register */ 674 { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
6156 1, /* can_bundle */
6157 {
6158 /* operands */
6159 { 21, 8, 16 },
6160 { 0, },
6161 { 0, },
6162 { 0, },
6163 { 0, }
6164 },
6165 {
6166 /* fixed_bit_masks */
6167 0x800000007ffc0000ULL,
6168 0ULL,
6169 0ULL,
6170 0ULL,
6171 0ULL
6172 },
6173 {
6174 /* fixed_bit_values */
6175 0x0000000008b80000ULL,
6176 -1ULL,
6177 -1ULL,
6178 -1ULL,
6179 -1ULL
6180 }
6181 }, 675 },
6182 { "mz", TILE_OPC_MZ, 0xf /* pipes */, 3 /* num_operands */, 676 { "mvz.sn", TILE_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1,
6183 TREG_ZERO, /* implicitly_written_register */ 677 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
6184 1, /* can_bundle */
6185 {
6186 /* operands */
6187 { 7, 8, 16 },
6188 { 9, 10, 17 },
6189 { 11, 12, 18 },
6190 { 13, 14, 19 },
6191 { 0, }
6192 },
6193 {
6194 /* fixed_bit_masks */
6195 0x800000007ffc0000ULL,
6196 0xfffe000000000000ULL,
6197 0x80000000780c0000ULL,
6198 0xf806000000000000ULL,
6199 0ULL
6200 },
6201 {
6202 /* fixed_bit_values */
6203 0x0000000000c40000ULL,
6204 0x082e000000000000ULL,
6205 0x80000000100c0000ULL,
6206 0x9004000000000000ULL,
6207 -1ULL
6208 }
6209 }, 678 },
6210 { "mz.sn", TILE_OPC_MZ_SN, 0x3 /* pipes */, 3 /* num_operands */, 679 { "mz", TILE_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
6211 TREG_SN, /* implicitly_written_register */ 680 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
6212 1, /* can_bundle */
6213 {
6214 /* operands */
6215 { 7, 8, 16 },
6216 { 9, 10, 17 },
6217 { 0, },
6218 { 0, },
6219 { 0, }
6220 },
6221 {
6222 /* fixed_bit_masks */
6223 0x800000007ffc0000ULL,
6224 0xfffe000000000000ULL,
6225 0ULL,
6226 0ULL,
6227 0ULL
6228 },
6229 {
6230 /* fixed_bit_values */
6231 0x0000000008c40000ULL,
6232 0x0c2e000000000000ULL,
6233 -1ULL,
6234 -1ULL,
6235 -1ULL
6236 }
6237 }, 681 },
6238 { "mzb", TILE_OPC_MZB, 0x3 /* pipes */, 3 /* num_operands */, 682 { "mz.sn", TILE_OPC_MZ_SN, 0x3, 3, TREG_SN, 1,
6239 TREG_ZERO, /* implicitly_written_register */ 683 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6240 1, /* can_bundle */
6241 {
6242 /* operands */
6243 { 7, 8, 16 },
6244 { 9, 10, 17 },
6245 { 0, },
6246 { 0, },
6247 { 0, }
6248 },
6249 {
6250 /* fixed_bit_masks */
6251 0x800000007ffc0000ULL,
6252 0xfffe000000000000ULL,
6253 0ULL,
6254 0ULL,
6255 0ULL
6256 },
6257 {
6258 /* fixed_bit_values */
6259 0x0000000000bc0000ULL,
6260 0x082a000000000000ULL,
6261 -1ULL,
6262 -1ULL,
6263 -1ULL
6264 }
6265 }, 684 },
6266 { "mzb.sn", TILE_OPC_MZB_SN, 0x3 /* pipes */, 3 /* num_operands */, 685 { "mzb", TILE_OPC_MZB, 0x3, 3, TREG_ZERO, 1,
6267 TREG_SN, /* implicitly_written_register */ 686 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6268 1, /* can_bundle */
6269 {
6270 /* operands */
6271 { 7, 8, 16 },
6272 { 9, 10, 17 },
6273 { 0, },
6274 { 0, },
6275 { 0, }
6276 },
6277 {
6278 /* fixed_bit_masks */
6279 0x800000007ffc0000ULL,
6280 0xfffe000000000000ULL,
6281 0ULL,
6282 0ULL,
6283 0ULL
6284 },
6285 {
6286 /* fixed_bit_values */
6287 0x0000000008bc0000ULL,
6288 0x0c2a000000000000ULL,
6289 -1ULL,
6290 -1ULL,
6291 -1ULL
6292 }
6293 }, 687 },
6294 { "mzh", TILE_OPC_MZH, 0x3 /* pipes */, 3 /* num_operands */, 688 { "mzb.sn", TILE_OPC_MZB_SN, 0x3, 3, TREG_SN, 1,
6295 TREG_ZERO, /* implicitly_written_register */ 689 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6296 1, /* can_bundle */
6297 {
6298 /* operands */
6299 { 7, 8, 16 },
6300 { 9, 10, 17 },
6301 { 0, },
6302 { 0, },
6303 { 0, }
6304 },
6305 {
6306 /* fixed_bit_masks */
6307 0x800000007ffc0000ULL,
6308 0xfffe000000000000ULL,
6309 0ULL,
6310 0ULL,
6311 0ULL
6312 },
6313 {
6314 /* fixed_bit_values */
6315 0x0000000000c00000ULL,
6316 0x082c000000000000ULL,
6317 -1ULL,
6318 -1ULL,
6319 -1ULL
6320 }
6321 }, 690 },
6322 { "mzh.sn", TILE_OPC_MZH_SN, 0x3 /* pipes */, 3 /* num_operands */, 691 { "mzh", TILE_OPC_MZH, 0x3, 3, TREG_ZERO, 1,
6323 TREG_SN, /* implicitly_written_register */ 692 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6324 1, /* can_bundle */
6325 {
6326 /* operands */
6327 { 7, 8, 16 },
6328 { 9, 10, 17 },
6329 { 0, },
6330 { 0, },
6331 { 0, }
6332 },
6333 {
6334 /* fixed_bit_masks */
6335 0x800000007ffc0000ULL,
6336 0xfffe000000000000ULL,
6337 0ULL,
6338 0ULL,
6339 0ULL
6340 },
6341 {
6342 /* fixed_bit_values */
6343 0x0000000008c00000ULL,
6344 0x0c2c000000000000ULL,
6345 -1ULL,
6346 -1ULL,
6347 -1ULL
6348 }
6349 }, 693 },
6350 { "nap", TILE_OPC_NAP, 0x2 /* pipes */, 0 /* num_operands */, 694 { "mzh.sn", TILE_OPC_MZH_SN, 0x3, 3, TREG_SN, 1,
6351 TREG_ZERO, /* implicitly_written_register */ 695 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6352 0, /* can_bundle */
6353 {
6354 /* operands */
6355 { 0, },
6356 { },
6357 { 0, },
6358 { 0, },
6359 { 0, }
6360 },
6361 {
6362 /* fixed_bit_masks */
6363 0ULL,
6364 0xfbfff80000000000ULL,
6365 0ULL,
6366 0ULL,
6367 0ULL
6368 },
6369 {
6370 /* fixed_bit_values */
6371 -1ULL,
6372 0x400b800000000000ULL,
6373 -1ULL,
6374 -1ULL,
6375 -1ULL
6376 }
6377 }, 696 },
6378 { "nop", TILE_OPC_NOP, 0xf /* pipes */, 0 /* num_operands */, 697 { "nap", TILE_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
6379 TREG_ZERO, /* implicitly_written_register */ 698 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
6380 1, /* can_bundle */
6381 {
6382 /* operands */
6383 { },
6384 { },
6385 { },
6386 { },
6387 { 0, }
6388 },
6389 {
6390 /* fixed_bit_masks */
6391 0x8000000077fff000ULL,
6392 0xfbfff80000000000ULL,
6393 0x80000000780ff000ULL,
6394 0xf807f80000000000ULL,
6395 0ULL
6396 },
6397 {
6398 /* fixed_bit_values */
6399 0x0000000070166000ULL,
6400 0x400b880000000000ULL,
6401 0x80000000680a6000ULL,
6402 0xd805180000000000ULL,
6403 -1ULL
6404 }
6405 }, 699 },
6406 { "nor", TILE_OPC_NOR, 0xf /* pipes */, 3 /* num_operands */, 700 { "nop", TILE_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
6407 TREG_ZERO, /* implicitly_written_register */ 701 { { }, { }, { }, { }, { 0, } },
6408 1, /* can_bundle */
6409 {
6410 /* operands */
6411 { 7, 8, 16 },
6412 { 9, 10, 17 },
6413 { 11, 12, 18 },
6414 { 13, 14, 19 },
6415 { 0, }
6416 },
6417 {
6418 /* fixed_bit_masks */
6419 0x800000007ffc0000ULL,
6420 0xfffe000000000000ULL,
6421 0x80000000780c0000ULL,
6422 0xf806000000000000ULL,
6423 0ULL
6424 },
6425 {
6426 /* fixed_bit_values */
6427 0x0000000000c80000ULL,
6428 0x0830000000000000ULL,
6429 0x8000000018040000ULL,
6430 0x9802000000000000ULL,
6431 -1ULL
6432 }
6433 }, 702 },
6434 { "nor.sn", TILE_OPC_NOR_SN, 0x3 /* pipes */, 3 /* num_operands */, 703 { "nor", TILE_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
6435 TREG_SN, /* implicitly_written_register */ 704 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
6436 1, /* can_bundle */
6437 {
6438 /* operands */
6439 { 7, 8, 16 },
6440 { 9, 10, 17 },
6441 { 0, },
6442 { 0, },
6443 { 0, }
6444 },
6445 {
6446 /* fixed_bit_masks */
6447 0x800000007ffc0000ULL,
6448 0xfffe000000000000ULL,
6449 0ULL,
6450 0ULL,
6451 0ULL
6452 },
6453 {
6454 /* fixed_bit_values */
6455 0x0000000008c80000ULL,
6456 0x0c30000000000000ULL,
6457 -1ULL,
6458 -1ULL,
6459 -1ULL
6460 }
6461 }, 705 },
6462 { "or", TILE_OPC_OR, 0xf /* pipes */, 3 /* num_operands */, 706 { "nor.sn", TILE_OPC_NOR_SN, 0x3, 3, TREG_SN, 1,
6463 TREG_ZERO, /* implicitly_written_register */ 707 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6464 1, /* can_bundle */
6465 {
6466 /* operands */
6467 { 7, 8, 16 },
6468 { 9, 10, 17 },
6469 { 11, 12, 18 },
6470 { 13, 14, 19 },
6471 { 0, }
6472 },
6473 {
6474 /* fixed_bit_masks */
6475 0x800000007ffc0000ULL,
6476 0xfffe000000000000ULL,
6477 0x80000000780c0000ULL,
6478 0xf806000000000000ULL,
6479 0ULL
6480 },
6481 {
6482 /* fixed_bit_values */
6483 0x0000000000cc0000ULL,
6484 0x0832000000000000ULL,
6485 0x8000000018080000ULL,
6486 0x9804000000000000ULL,
6487 -1ULL
6488 }
6489 }, 708 },
6490 { "or.sn", TILE_OPC_OR_SN, 0x3 /* pipes */, 3 /* num_operands */, 709 { "or", TILE_OPC_OR, 0xf, 3, TREG_ZERO, 1,
6491 TREG_SN, /* implicitly_written_register */ 710 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
6492 1, /* can_bundle */
6493 {
6494 /* operands */
6495 { 7, 8, 16 },
6496 { 9, 10, 17 },
6497 { 0, },
6498 { 0, },
6499 { 0, }
6500 },
6501 {
6502 /* fixed_bit_masks */
6503 0x800000007ffc0000ULL,
6504 0xfffe000000000000ULL,
6505 0ULL,
6506 0ULL,
6507 0ULL
6508 },
6509 {
6510 /* fixed_bit_values */
6511 0x0000000008cc0000ULL,
6512 0x0c32000000000000ULL,
6513 -1ULL,
6514 -1ULL,
6515 -1ULL
6516 }
6517 }, 711 },
6518 { "ori", TILE_OPC_ORI, 0xf /* pipes */, 3 /* num_operands */, 712 { "or.sn", TILE_OPC_OR_SN, 0x3, 3, TREG_SN, 1,
6519 TREG_ZERO, /* implicitly_written_register */ 713 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6520 1, /* can_bundle */
6521 {
6522 /* operands */
6523 { 7, 8, 0 },
6524 { 9, 10, 1 },
6525 { 11, 12, 2 },
6526 { 13, 14, 3 },
6527 { 0, }
6528 },
6529 {
6530 /* fixed_bit_masks */
6531 0x800000007ff00000ULL,
6532 0xfff8000000000000ULL,
6533 0x8000000078000000ULL,
6534 0xf800000000000000ULL,
6535 0ULL
6536 },
6537 {
6538 /* fixed_bit_values */
6539 0x0000000040800000ULL,
6540 0x3058000000000000ULL,
6541 0x8000000058000000ULL,
6542 0xc800000000000000ULL,
6543 -1ULL
6544 }
6545 }, 714 },
6546 { "ori.sn", TILE_OPC_ORI_SN, 0x3 /* pipes */, 3 /* num_operands */, 715 { "ori", TILE_OPC_ORI, 0xf, 3, TREG_ZERO, 1,
6547 TREG_SN, /* implicitly_written_register */ 716 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
6548 1, /* can_bundle */
6549 {
6550 /* operands */
6551 { 7, 8, 0 },
6552 { 9, 10, 1 },
6553 { 0, },
6554 { 0, },
6555 { 0, }
6556 },
6557 {
6558 /* fixed_bit_masks */
6559 0x800000007ff00000ULL,
6560 0xfff8000000000000ULL,
6561 0ULL,
6562 0ULL,
6563 0ULL
6564 },
6565 {
6566 /* fixed_bit_values */
6567 0x0000000048800000ULL,
6568 0x3458000000000000ULL,
6569 -1ULL,
6570 -1ULL,
6571 -1ULL
6572 }
6573 }, 717 },
6574 { "packbs_u", TILE_OPC_PACKBS_U, 0x3 /* pipes */, 3 /* num_operands */, 718 { "ori.sn", TILE_OPC_ORI_SN, 0x3, 3, TREG_SN, 1,
6575 TREG_ZERO, /* implicitly_written_register */ 719 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
6576 1, /* can_bundle */
6577 {
6578 /* operands */
6579 { 7, 8, 16 },
6580 { 9, 10, 17 },
6581 { 0, },
6582 { 0, },
6583 { 0, }
6584 },
6585 {
6586 /* fixed_bit_masks */
6587 0x800000007ffc0000ULL,
6588 0xfffe000000000000ULL,
6589 0ULL,
6590 0ULL,
6591 0ULL
6592 },
6593 {
6594 /* fixed_bit_values */
6595 0x00000000019c0000ULL,
6596 0x0892000000000000ULL,
6597 -1ULL,
6598 -1ULL,
6599 -1ULL
6600 }
6601 }, 720 },
6602 { "packbs_u.sn", TILE_OPC_PACKBS_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 721 { "packbs_u", TILE_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1,
6603 TREG_SN, /* implicitly_written_register */ 722 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6604 1, /* can_bundle */
6605 {
6606 /* operands */
6607 { 7, 8, 16 },
6608 { 9, 10, 17 },
6609 { 0, },
6610 { 0, },
6611 { 0, }
6612 },
6613 {
6614 /* fixed_bit_masks */
6615 0x800000007ffc0000ULL,
6616 0xfffe000000000000ULL,
6617 0ULL,
6618 0ULL,
6619 0ULL
6620 },
6621 {
6622 /* fixed_bit_values */
6623 0x00000000099c0000ULL,
6624 0x0c92000000000000ULL,
6625 -1ULL,
6626 -1ULL,
6627 -1ULL
6628 }
6629 }, 723 },
6630 { "packhb", TILE_OPC_PACKHB, 0x3 /* pipes */, 3 /* num_operands */, 724 { "packbs_u.sn", TILE_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1,
6631 TREG_ZERO, /* implicitly_written_register */ 725 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6632 1, /* can_bundle */
6633 {
6634 /* operands */
6635 { 7, 8, 16 },
6636 { 9, 10, 17 },
6637 { 0, },
6638 { 0, },
6639 { 0, }
6640 },
6641 {
6642 /* fixed_bit_masks */
6643 0x800000007ffc0000ULL,
6644 0xfffe000000000000ULL,
6645 0ULL,
6646 0ULL,
6647 0ULL
6648 },
6649 {
6650 /* fixed_bit_values */
6651 0x0000000000d00000ULL,
6652 0x0834000000000000ULL,
6653 -1ULL,
6654 -1ULL,
6655 -1ULL
6656 }
6657 }, 726 },
6658 { "packhb.sn", TILE_OPC_PACKHB_SN, 0x3 /* pipes */, 3 /* num_operands */, 727 { "packhb", TILE_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1,
6659 TREG_SN, /* implicitly_written_register */ 728 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6660 1, /* can_bundle */
6661 {
6662 /* operands */
6663 { 7, 8, 16 },
6664 { 9, 10, 17 },
6665 { 0, },
6666 { 0, },
6667 { 0, }
6668 },
6669 {
6670 /* fixed_bit_masks */
6671 0x800000007ffc0000ULL,
6672 0xfffe000000000000ULL,
6673 0ULL,
6674 0ULL,
6675 0ULL
6676 },
6677 {
6678 /* fixed_bit_values */
6679 0x0000000008d00000ULL,
6680 0x0c34000000000000ULL,
6681 -1ULL,
6682 -1ULL,
6683 -1ULL
6684 }
6685 }, 729 },
6686 { "packhs", TILE_OPC_PACKHS, 0x3 /* pipes */, 3 /* num_operands */, 730 { "packhb.sn", TILE_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1,
6687 TREG_ZERO, /* implicitly_written_register */ 731 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6688 1, /* can_bundle */
6689 {
6690 /* operands */
6691 { 7, 8, 16 },
6692 { 9, 10, 17 },
6693 { 0, },
6694 { 0, },
6695 { 0, }
6696 },
6697 {
6698 /* fixed_bit_masks */
6699 0x800000007ffc0000ULL,
6700 0xfffe000000000000ULL,
6701 0ULL,
6702 0ULL,
6703 0ULL
6704 },
6705 {
6706 /* fixed_bit_values */
6707 0x0000000001980000ULL,
6708 0x0890000000000000ULL,
6709 -1ULL,
6710 -1ULL,
6711 -1ULL
6712 }
6713 }, 732 },
6714 { "packhs.sn", TILE_OPC_PACKHS_SN, 0x3 /* pipes */, 3 /* num_operands */, 733 { "packhs", TILE_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1,
6715 TREG_SN, /* implicitly_written_register */ 734 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6716 1, /* can_bundle */
6717 {
6718 /* operands */
6719 { 7, 8, 16 },
6720 { 9, 10, 17 },
6721 { 0, },
6722 { 0, },
6723 { 0, }
6724 },
6725 {
6726 /* fixed_bit_masks */
6727 0x800000007ffc0000ULL,
6728 0xfffe000000000000ULL,
6729 0ULL,
6730 0ULL,
6731 0ULL
6732 },
6733 {
6734 /* fixed_bit_values */
6735 0x0000000009980000ULL,
6736 0x0c90000000000000ULL,
6737 -1ULL,
6738 -1ULL,
6739 -1ULL
6740 }
6741 }, 735 },
6742 { "packlb", TILE_OPC_PACKLB, 0x3 /* pipes */, 3 /* num_operands */, 736 { "packhs.sn", TILE_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1,
6743 TREG_ZERO, /* implicitly_written_register */ 737 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6744 1, /* can_bundle */
6745 {
6746 /* operands */
6747 { 7, 8, 16 },
6748 { 9, 10, 17 },
6749 { 0, },
6750 { 0, },
6751 { 0, }
6752 },
6753 {
6754 /* fixed_bit_masks */
6755 0x800000007ffc0000ULL,
6756 0xfffe000000000000ULL,
6757 0ULL,
6758 0ULL,
6759 0ULL
6760 },
6761 {
6762 /* fixed_bit_values */
6763 0x0000000000d40000ULL,
6764 0x0836000000000000ULL,
6765 -1ULL,
6766 -1ULL,
6767 -1ULL
6768 }
6769 }, 738 },
6770 { "packlb.sn", TILE_OPC_PACKLB_SN, 0x3 /* pipes */, 3 /* num_operands */, 739 { "packlb", TILE_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1,
6771 TREG_SN, /* implicitly_written_register */ 740 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6772 1, /* can_bundle */
6773 {
6774 /* operands */
6775 { 7, 8, 16 },
6776 { 9, 10, 17 },
6777 { 0, },
6778 { 0, },
6779 { 0, }
6780 },
6781 {
6782 /* fixed_bit_masks */
6783 0x800000007ffc0000ULL,
6784 0xfffe000000000000ULL,
6785 0ULL,
6786 0ULL,
6787 0ULL
6788 },
6789 {
6790 /* fixed_bit_values */
6791 0x0000000008d40000ULL,
6792 0x0c36000000000000ULL,
6793 -1ULL,
6794 -1ULL,
6795 -1ULL
6796 }
6797 }, 741 },
6798 { "pcnt", TILE_OPC_PCNT, 0x5 /* pipes */, 2 /* num_operands */, 742 { "packlb.sn", TILE_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1,
6799 TREG_ZERO, /* implicitly_written_register */ 743 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6800 1, /* can_bundle */
6801 {
6802 /* operands */
6803 { 7, 8 },
6804 { 0, },
6805 { 11, 12 },
6806 { 0, },
6807 { 0, }
6808 },
6809 {
6810 /* fixed_bit_masks */
6811 0x800000007ffff000ULL,
6812 0ULL,
6813 0x80000000780ff000ULL,
6814 0ULL,
6815 0ULL
6816 },
6817 {
6818 /* fixed_bit_values */
6819 0x0000000070167000ULL,
6820 -1ULL,
6821 0x80000000680a7000ULL,
6822 -1ULL,
6823 -1ULL
6824 }
6825 }, 744 },
6826 { "pcnt.sn", TILE_OPC_PCNT_SN, 0x1 /* pipes */, 2 /* num_operands */, 745 { "pcnt", TILE_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
6827 TREG_SN, /* implicitly_written_register */ 746 { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
6828 1, /* can_bundle */
6829 {
6830 /* operands */
6831 { 7, 8 },
6832 { 0, },
6833 { 0, },
6834 { 0, },
6835 { 0, }
6836 },
6837 {
6838 /* fixed_bit_masks */
6839 0x800000007ffff000ULL,
6840 0ULL,
6841 0ULL,
6842 0ULL,
6843 0ULL
6844 },
6845 {
6846 /* fixed_bit_values */
6847 0x0000000078167000ULL,
6848 -1ULL,
6849 -1ULL,
6850 -1ULL,
6851 -1ULL
6852 }
6853 }, 747 },
6854 { "rl", TILE_OPC_RL, 0xf /* pipes */, 3 /* num_operands */, 748 { "pcnt.sn", TILE_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1,
6855 TREG_ZERO, /* implicitly_written_register */ 749 { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
6856 1, /* can_bundle */
6857 {
6858 /* operands */
6859 { 7, 8, 16 },
6860 { 9, 10, 17 },
6861 { 11, 12, 18 },
6862 { 13, 14, 19 },
6863 { 0, }
6864 },
6865 {
6866 /* fixed_bit_masks */
6867 0x800000007ffc0000ULL,
6868 0xfffe000000000000ULL,
6869 0x80000000780c0000ULL,
6870 0xf806000000000000ULL,
6871 0ULL
6872 },
6873 {
6874 /* fixed_bit_values */
6875 0x0000000000d80000ULL,
6876 0x0838000000000000ULL,
6877 0x8000000020000000ULL,
6878 0xa000000000000000ULL,
6879 -1ULL
6880 }
6881 }, 750 },
6882 { "rl.sn", TILE_OPC_RL_SN, 0x3 /* pipes */, 3 /* num_operands */, 751 { "rl", TILE_OPC_RL, 0xf, 3, TREG_ZERO, 1,
6883 TREG_SN, /* implicitly_written_register */ 752 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
6884 1, /* can_bundle */
6885 {
6886 /* operands */
6887 { 7, 8, 16 },
6888 { 9, 10, 17 },
6889 { 0, },
6890 { 0, },
6891 { 0, }
6892 },
6893 {
6894 /* fixed_bit_masks */
6895 0x800000007ffc0000ULL,
6896 0xfffe000000000000ULL,
6897 0ULL,
6898 0ULL,
6899 0ULL
6900 },
6901 {
6902 /* fixed_bit_values */
6903 0x0000000008d80000ULL,
6904 0x0c38000000000000ULL,
6905 -1ULL,
6906 -1ULL,
6907 -1ULL
6908 }
6909 }, 753 },
6910 { "rli", TILE_OPC_RLI, 0xf /* pipes */, 3 /* num_operands */, 754 { "rl.sn", TILE_OPC_RL_SN, 0x3, 3, TREG_SN, 1,
6911 TREG_ZERO, /* implicitly_written_register */ 755 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
6912 1, /* can_bundle */
6913 {
6914 /* operands */
6915 { 7, 8, 32 },
6916 { 9, 10, 33 },
6917 { 11, 12, 34 },
6918 { 13, 14, 35 },
6919 { 0, }
6920 },
6921 {
6922 /* fixed_bit_masks */
6923 0x800000007ffe0000ULL,
6924 0xffff000000000000ULL,
6925 0x80000000780e0000ULL,
6926 0xf807000000000000ULL,
6927 0ULL
6928 },
6929 {
6930 /* fixed_bit_values */
6931 0x0000000070020000ULL,
6932 0x4001000000000000ULL,
6933 0x8000000068020000ULL,
6934 0xd801000000000000ULL,
6935 -1ULL
6936 }
6937 }, 756 },
6938 { "rli.sn", TILE_OPC_RLI_SN, 0x3 /* pipes */, 3 /* num_operands */, 757 { "rli", TILE_OPC_RLI, 0xf, 3, TREG_ZERO, 1,
6939 TREG_SN, /* implicitly_written_register */ 758 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
6940 1, /* can_bundle */
6941 {
6942 /* operands */
6943 { 7, 8, 32 },
6944 { 9, 10, 33 },
6945 { 0, },
6946 { 0, },
6947 { 0, }
6948 },
6949 {
6950 /* fixed_bit_masks */
6951 0x800000007ffe0000ULL,
6952 0xffff000000000000ULL,
6953 0ULL,
6954 0ULL,
6955 0ULL
6956 },
6957 {
6958 /* fixed_bit_values */
6959 0x0000000078020000ULL,
6960 0x4401000000000000ULL,
6961 -1ULL,
6962 -1ULL,
6963 -1ULL
6964 }
6965 }, 759 },
6966 { "s1a", TILE_OPC_S1A, 0xf /* pipes */, 3 /* num_operands */, 760 { "rli.sn", TILE_OPC_RLI_SN, 0x3, 3, TREG_SN, 1,
6967 TREG_ZERO, /* implicitly_written_register */ 761 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
6968 1, /* can_bundle */
6969 {
6970 /* operands */
6971 { 7, 8, 16 },
6972 { 9, 10, 17 },
6973 { 11, 12, 18 },
6974 { 13, 14, 19 },
6975 { 0, }
6976 },
6977 {
6978 /* fixed_bit_masks */
6979 0x800000007ffc0000ULL,
6980 0xfffe000000000000ULL,
6981 0x80000000780c0000ULL,
6982 0xf806000000000000ULL,
6983 0ULL
6984 },
6985 {
6986 /* fixed_bit_values */
6987 0x0000000000dc0000ULL,
6988 0x083a000000000000ULL,
6989 0x8000000008040000ULL,
6990 0x8802000000000000ULL,
6991 -1ULL
6992 }
6993 }, 762 },
6994 { "s1a.sn", TILE_OPC_S1A_SN, 0x3 /* pipes */, 3 /* num_operands */, 763 { "s1a", TILE_OPC_S1A, 0xf, 3, TREG_ZERO, 1,
6995 TREG_SN, /* implicitly_written_register */ 764 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
6996 1, /* can_bundle */
6997 {
6998 /* operands */
6999 { 7, 8, 16 },
7000 { 9, 10, 17 },
7001 { 0, },
7002 { 0, },
7003 { 0, }
7004 },
7005 {
7006 /* fixed_bit_masks */
7007 0x800000007ffc0000ULL,
7008 0xfffe000000000000ULL,
7009 0ULL,
7010 0ULL,
7011 0ULL
7012 },
7013 {
7014 /* fixed_bit_values */
7015 0x0000000008dc0000ULL,
7016 0x0c3a000000000000ULL,
7017 -1ULL,
7018 -1ULL,
7019 -1ULL
7020 }
7021 }, 765 },
7022 { "s2a", TILE_OPC_S2A, 0xf /* pipes */, 3 /* num_operands */, 766 { "s1a.sn", TILE_OPC_S1A_SN, 0x3, 3, TREG_SN, 1,
7023 TREG_ZERO, /* implicitly_written_register */ 767 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7024 1, /* can_bundle */
7025 {
7026 /* operands */
7027 { 7, 8, 16 },
7028 { 9, 10, 17 },
7029 { 11, 12, 18 },
7030 { 13, 14, 19 },
7031 { 0, }
7032 },
7033 {
7034 /* fixed_bit_masks */
7035 0x800000007ffc0000ULL,
7036 0xfffe000000000000ULL,
7037 0x80000000780c0000ULL,
7038 0xf806000000000000ULL,
7039 0ULL
7040 },
7041 {
7042 /* fixed_bit_values */
7043 0x0000000000e00000ULL,
7044 0x083c000000000000ULL,
7045 0x8000000008080000ULL,
7046 0x8804000000000000ULL,
7047 -1ULL
7048 }
7049 }, 768 },
7050 { "s2a.sn", TILE_OPC_S2A_SN, 0x3 /* pipes */, 3 /* num_operands */, 769 { "s2a", TILE_OPC_S2A, 0xf, 3, TREG_ZERO, 1,
7051 TREG_SN, /* implicitly_written_register */ 770 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
7052 1, /* can_bundle */
7053 {
7054 /* operands */
7055 { 7, 8, 16 },
7056 { 9, 10, 17 },
7057 { 0, },
7058 { 0, },
7059 { 0, }
7060 },
7061 {
7062 /* fixed_bit_masks */
7063 0x800000007ffc0000ULL,
7064 0xfffe000000000000ULL,
7065 0ULL,
7066 0ULL,
7067 0ULL
7068 },
7069 {
7070 /* fixed_bit_values */
7071 0x0000000008e00000ULL,
7072 0x0c3c000000000000ULL,
7073 -1ULL,
7074 -1ULL,
7075 -1ULL
7076 }
7077 }, 771 },
7078 { "s3a", TILE_OPC_S3A, 0xf /* pipes */, 3 /* num_operands */, 772 { "s2a.sn", TILE_OPC_S2A_SN, 0x3, 3, TREG_SN, 1,
7079 TREG_ZERO, /* implicitly_written_register */ 773 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7080 1, /* can_bundle */
7081 {
7082 /* operands */
7083 { 7, 8, 16 },
7084 { 9, 10, 17 },
7085 { 11, 12, 18 },
7086 { 13, 14, 19 },
7087 { 0, }
7088 },
7089 {
7090 /* fixed_bit_masks */
7091 0x800000007ffc0000ULL,
7092 0xfffe000000000000ULL,
7093 0x80000000780c0000ULL,
7094 0xf806000000000000ULL,
7095 0ULL
7096 },
7097 {
7098 /* fixed_bit_values */
7099 0x0000000000e40000ULL,
7100 0x083e000000000000ULL,
7101 0x8000000030040000ULL,
7102 0xb002000000000000ULL,
7103 -1ULL
7104 }
7105 }, 774 },
7106 { "s3a.sn", TILE_OPC_S3A_SN, 0x3 /* pipes */, 3 /* num_operands */, 775 { "s3a", TILE_OPC_S3A, 0xf, 3, TREG_ZERO, 1,
7107 TREG_SN, /* implicitly_written_register */ 776 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
7108 1, /* can_bundle */
7109 {
7110 /* operands */
7111 { 7, 8, 16 },
7112 { 9, 10, 17 },
7113 { 0, },
7114 { 0, },
7115 { 0, }
7116 },
7117 {
7118 /* fixed_bit_masks */
7119 0x800000007ffc0000ULL,
7120 0xfffe000000000000ULL,
7121 0ULL,
7122 0ULL,
7123 0ULL
7124 },
7125 {
7126 /* fixed_bit_values */
7127 0x0000000008e40000ULL,
7128 0x0c3e000000000000ULL,
7129 -1ULL,
7130 -1ULL,
7131 -1ULL
7132 }
7133 }, 777 },
7134 { "sadab_u", TILE_OPC_SADAB_U, 0x1 /* pipes */, 3 /* num_operands */, 778 { "s3a.sn", TILE_OPC_S3A_SN, 0x3, 3, TREG_SN, 1,
7135 TREG_ZERO, /* implicitly_written_register */ 779 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7136 1, /* can_bundle */
7137 {
7138 /* operands */
7139 { 21, 8, 16 },
7140 { 0, },
7141 { 0, },
7142 { 0, },
7143 { 0, }
7144 },
7145 {
7146 /* fixed_bit_masks */
7147 0x800000007ffc0000ULL,
7148 0ULL,
7149 0ULL,
7150 0ULL,
7151 0ULL
7152 },
7153 {
7154 /* fixed_bit_values */
7155 0x0000000000e80000ULL,
7156 -1ULL,
7157 -1ULL,
7158 -1ULL,
7159 -1ULL
7160 }
7161 }, 780 },
7162 { "sadab_u.sn", TILE_OPC_SADAB_U_SN, 0x1 /* pipes */, 3 /* num_operands */, 781 { "sadab_u", TILE_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1,
7163 TREG_SN, /* implicitly_written_register */ 782 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7164 1, /* can_bundle */
7165 {
7166 /* operands */
7167 { 21, 8, 16 },
7168 { 0, },
7169 { 0, },
7170 { 0, },
7171 { 0, }
7172 },
7173 {
7174 /* fixed_bit_masks */
7175 0x800000007ffc0000ULL,
7176 0ULL,
7177 0ULL,
7178 0ULL,
7179 0ULL
7180 },
7181 {
7182 /* fixed_bit_values */
7183 0x0000000008e80000ULL,
7184 -1ULL,
7185 -1ULL,
7186 -1ULL,
7187 -1ULL
7188 }
7189 }, 783 },
7190 { "sadah", TILE_OPC_SADAH, 0x1 /* pipes */, 3 /* num_operands */, 784 { "sadab_u.sn", TILE_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1,
7191 TREG_ZERO, /* implicitly_written_register */ 785 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7192 1, /* can_bundle */
7193 {
7194 /* operands */
7195 { 21, 8, 16 },
7196 { 0, },
7197 { 0, },
7198 { 0, },
7199 { 0, }
7200 },
7201 {
7202 /* fixed_bit_masks */
7203 0x800000007ffc0000ULL,
7204 0ULL,
7205 0ULL,
7206 0ULL,
7207 0ULL
7208 },
7209 {
7210 /* fixed_bit_values */
7211 0x0000000000ec0000ULL,
7212 -1ULL,
7213 -1ULL,
7214 -1ULL,
7215 -1ULL
7216 }
7217 }, 786 },
7218 { "sadah.sn", TILE_OPC_SADAH_SN, 0x1 /* pipes */, 3 /* num_operands */, 787 { "sadah", TILE_OPC_SADAH, 0x1, 3, TREG_ZERO, 1,
7219 TREG_SN, /* implicitly_written_register */ 788 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7220 1, /* can_bundle */
7221 {
7222 /* operands */
7223 { 21, 8, 16 },
7224 { 0, },
7225 { 0, },
7226 { 0, },
7227 { 0, }
7228 },
7229 {
7230 /* fixed_bit_masks */
7231 0x800000007ffc0000ULL,
7232 0ULL,
7233 0ULL,
7234 0ULL,
7235 0ULL
7236 },
7237 {
7238 /* fixed_bit_values */
7239 0x0000000008ec0000ULL,
7240 -1ULL,
7241 -1ULL,
7242 -1ULL,
7243 -1ULL
7244 }
7245 }, 789 },
7246 { "sadah_u", TILE_OPC_SADAH_U, 0x1 /* pipes */, 3 /* num_operands */, 790 { "sadah.sn", TILE_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1,
7247 TREG_ZERO, /* implicitly_written_register */ 791 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7248 1, /* can_bundle */
7249 {
7250 /* operands */
7251 { 21, 8, 16 },
7252 { 0, },
7253 { 0, },
7254 { 0, },
7255 { 0, }
7256 },
7257 {
7258 /* fixed_bit_masks */
7259 0x800000007ffc0000ULL,
7260 0ULL,
7261 0ULL,
7262 0ULL,
7263 0ULL
7264 },
7265 {
7266 /* fixed_bit_values */
7267 0x0000000000f00000ULL,
7268 -1ULL,
7269 -1ULL,
7270 -1ULL,
7271 -1ULL
7272 }
7273 }, 792 },
7274 { "sadah_u.sn", TILE_OPC_SADAH_U_SN, 0x1 /* pipes */, 3 /* num_operands */, 793 { "sadah_u", TILE_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1,
7275 TREG_SN, /* implicitly_written_register */ 794 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7276 1, /* can_bundle */
7277 {
7278 /* operands */
7279 { 21, 8, 16 },
7280 { 0, },
7281 { 0, },
7282 { 0, },
7283 { 0, }
7284 },
7285 {
7286 /* fixed_bit_masks */
7287 0x800000007ffc0000ULL,
7288 0ULL,
7289 0ULL,
7290 0ULL,
7291 0ULL
7292 },
7293 {
7294 /* fixed_bit_values */
7295 0x0000000008f00000ULL,
7296 -1ULL,
7297 -1ULL,
7298 -1ULL,
7299 -1ULL
7300 }
7301 }, 795 },
7302 { "sadb_u", TILE_OPC_SADB_U, 0x1 /* pipes */, 3 /* num_operands */, 796 { "sadah_u.sn", TILE_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1,
7303 TREG_ZERO, /* implicitly_written_register */ 797 { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7304 1, /* can_bundle */
7305 {
7306 /* operands */
7307 { 7, 8, 16 },
7308 { 0, },
7309 { 0, },
7310 { 0, },
7311 { 0, }
7312 },
7313 {
7314 /* fixed_bit_masks */
7315 0x800000007ffc0000ULL,
7316 0ULL,
7317 0ULL,
7318 0ULL,
7319 0ULL
7320 },
7321 {
7322 /* fixed_bit_values */
7323 0x0000000000f40000ULL,
7324 -1ULL,
7325 -1ULL,
7326 -1ULL,
7327 -1ULL
7328 }
7329 }, 798 },
7330 { "sadb_u.sn", TILE_OPC_SADB_U_SN, 0x1 /* pipes */, 3 /* num_operands */, 799 { "sadb_u", TILE_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1,
7331 TREG_SN, /* implicitly_written_register */ 800 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7332 1, /* can_bundle */
7333 {
7334 /* operands */
7335 { 7, 8, 16 },
7336 { 0, },
7337 { 0, },
7338 { 0, },
7339 { 0, }
7340 },
7341 {
7342 /* fixed_bit_masks */
7343 0x800000007ffc0000ULL,
7344 0ULL,
7345 0ULL,
7346 0ULL,
7347 0ULL
7348 },
7349 {
7350 /* fixed_bit_values */
7351 0x0000000008f40000ULL,
7352 -1ULL,
7353 -1ULL,
7354 -1ULL,
7355 -1ULL
7356 }
7357 }, 801 },
7358 { "sadh", TILE_OPC_SADH, 0x1 /* pipes */, 3 /* num_operands */, 802 { "sadb_u.sn", TILE_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1,
7359 TREG_ZERO, /* implicitly_written_register */ 803 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7360 1, /* can_bundle */
7361 {
7362 /* operands */
7363 { 7, 8, 16 },
7364 { 0, },
7365 { 0, },
7366 { 0, },
7367 { 0, }
7368 },
7369 {
7370 /* fixed_bit_masks */
7371 0x800000007ffc0000ULL,
7372 0ULL,
7373 0ULL,
7374 0ULL,
7375 0ULL
7376 },
7377 {
7378 /* fixed_bit_values */
7379 0x0000000000f80000ULL,
7380 -1ULL,
7381 -1ULL,
7382 -1ULL,
7383 -1ULL
7384 }
7385 }, 804 },
7386 { "sadh.sn", TILE_OPC_SADH_SN, 0x1 /* pipes */, 3 /* num_operands */, 805 { "sadh", TILE_OPC_SADH, 0x1, 3, TREG_ZERO, 1,
7387 TREG_SN, /* implicitly_written_register */ 806 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7388 1, /* can_bundle */
7389 {
7390 /* operands */
7391 { 7, 8, 16 },
7392 { 0, },
7393 { 0, },
7394 { 0, },
7395 { 0, }
7396 },
7397 {
7398 /* fixed_bit_masks */
7399 0x800000007ffc0000ULL,
7400 0ULL,
7401 0ULL,
7402 0ULL,
7403 0ULL
7404 },
7405 {
7406 /* fixed_bit_values */
7407 0x0000000008f80000ULL,
7408 -1ULL,
7409 -1ULL,
7410 -1ULL,
7411 -1ULL
7412 }
7413 }, 807 },
7414 { "sadh_u", TILE_OPC_SADH_U, 0x1 /* pipes */, 3 /* num_operands */, 808 { "sadh.sn", TILE_OPC_SADH_SN, 0x1, 3, TREG_SN, 1,
7415 TREG_ZERO, /* implicitly_written_register */ 809 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7416 1, /* can_bundle */
7417 {
7418 /* operands */
7419 { 7, 8, 16 },
7420 { 0, },
7421 { 0, },
7422 { 0, },
7423 { 0, }
7424 },
7425 {
7426 /* fixed_bit_masks */
7427 0x800000007ffc0000ULL,
7428 0ULL,
7429 0ULL,
7430 0ULL,
7431 0ULL
7432 },
7433 {
7434 /* fixed_bit_values */
7435 0x0000000000fc0000ULL,
7436 -1ULL,
7437 -1ULL,
7438 -1ULL,
7439 -1ULL
7440 }
7441 }, 810 },
7442 { "sadh_u.sn", TILE_OPC_SADH_U_SN, 0x1 /* pipes */, 3 /* num_operands */, 811 { "sadh_u", TILE_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1,
7443 TREG_SN, /* implicitly_written_register */ 812 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7444 1, /* can_bundle */
7445 {
7446 /* operands */
7447 { 7, 8, 16 },
7448 { 0, },
7449 { 0, },
7450 { 0, },
7451 { 0, }
7452 },
7453 {
7454 /* fixed_bit_masks */
7455 0x800000007ffc0000ULL,
7456 0ULL,
7457 0ULL,
7458 0ULL,
7459 0ULL
7460 },
7461 {
7462 /* fixed_bit_values */
7463 0x0000000008fc0000ULL,
7464 -1ULL,
7465 -1ULL,
7466 -1ULL,
7467 -1ULL
7468 }
7469 }, 813 },
7470 { "sb", TILE_OPC_SB, 0x12 /* pipes */, 2 /* num_operands */, 814 { "sadh_u.sn", TILE_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1,
7471 TREG_ZERO, /* implicitly_written_register */ 815 { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
7472 1, /* can_bundle */
7473 {
7474 /* operands */
7475 { 0, },
7476 { 10, 17 },
7477 { 0, },
7478 { 0, },
7479 { 15, 36 }
7480 },
7481 {
7482 /* fixed_bit_masks */
7483 0ULL,
7484 0xfbfe000000000000ULL,
7485 0ULL,
7486 0ULL,
7487 0x8700000000000000ULL
7488 },
7489 {
7490 /* fixed_bit_values */
7491 -1ULL,
7492 0x0840000000000000ULL,
7493 -1ULL,
7494 -1ULL,
7495 0x8500000000000000ULL
7496 }
7497 }, 816 },
7498 { "sbadd", TILE_OPC_SBADD, 0x2 /* pipes */, 3 /* num_operands */, 817 { "sb", TILE_OPC_SB, 0x12, 2, TREG_ZERO, 1,
7499 TREG_ZERO, /* implicitly_written_register */ 818 { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
7500 1, /* can_bundle */
7501 {
7502 /* operands */
7503 { 0, },
7504 { 24, 17, 37 },
7505 { 0, },
7506 { 0, },
7507 { 0, }
7508 },
7509 {
7510 /* fixed_bit_masks */
7511 0ULL,
7512 0xfbf8000000000000ULL,
7513 0ULL,
7514 0ULL,
7515 0ULL
7516 },
7517 {
7518 /* fixed_bit_values */
7519 -1ULL,
7520 0x30e0000000000000ULL,
7521 -1ULL,
7522 -1ULL,
7523 -1ULL
7524 }
7525 }, 819 },
7526 { "seq", TILE_OPC_SEQ, 0xf /* pipes */, 3 /* num_operands */, 820 { "sbadd", TILE_OPC_SBADD, 0x2, 3, TREG_ZERO, 1,
7527 TREG_ZERO, /* implicitly_written_register */ 821 { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } },
7528 1, /* can_bundle */
7529 {
7530 /* operands */
7531 { 7, 8, 16 },
7532 { 9, 10, 17 },
7533 { 11, 12, 18 },
7534 { 13, 14, 19 },
7535 { 0, }
7536 },
7537 {
7538 /* fixed_bit_masks */
7539 0x800000007ffc0000ULL,
7540 0xfffe000000000000ULL,
7541 0x80000000780c0000ULL,
7542 0xf806000000000000ULL,
7543 0ULL
7544 },
7545 {
7546 /* fixed_bit_values */
7547 0x0000000001080000ULL,
7548 0x0846000000000000ULL,
7549 0x8000000030080000ULL,
7550 0xb004000000000000ULL,
7551 -1ULL
7552 }
7553 }, 822 },
7554 { "seq.sn", TILE_OPC_SEQ_SN, 0x3 /* pipes */, 3 /* num_operands */, 823 { "seq", TILE_OPC_SEQ, 0xf, 3, TREG_ZERO, 1,
7555 TREG_SN, /* implicitly_written_register */ 824 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
7556 1, /* can_bundle */
7557 {
7558 /* operands */
7559 { 7, 8, 16 },
7560 { 9, 10, 17 },
7561 { 0, },
7562 { 0, },
7563 { 0, }
7564 },
7565 {
7566 /* fixed_bit_masks */
7567 0x800000007ffc0000ULL,
7568 0xfffe000000000000ULL,
7569 0ULL,
7570 0ULL,
7571 0ULL
7572 },
7573 {
7574 /* fixed_bit_values */
7575 0x0000000009080000ULL,
7576 0x0c46000000000000ULL,
7577 -1ULL,
7578 -1ULL,
7579 -1ULL
7580 }
7581 }, 825 },
7582 { "seqb", TILE_OPC_SEQB, 0x3 /* pipes */, 3 /* num_operands */, 826 { "seq.sn", TILE_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1,
7583 TREG_ZERO, /* implicitly_written_register */ 827 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7584 1, /* can_bundle */
7585 {
7586 /* operands */
7587 { 7, 8, 16 },
7588 { 9, 10, 17 },
7589 { 0, },
7590 { 0, },
7591 { 0, }
7592 },
7593 {
7594 /* fixed_bit_masks */
7595 0x800000007ffc0000ULL,
7596 0xfffe000000000000ULL,
7597 0ULL,
7598 0ULL,
7599 0ULL
7600 },
7601 {
7602 /* fixed_bit_values */
7603 0x0000000001000000ULL,
7604 0x0842000000000000ULL,
7605 -1ULL,
7606 -1ULL,
7607 -1ULL
7608 }
7609 }, 828 },
7610 { "seqb.sn", TILE_OPC_SEQB_SN, 0x3 /* pipes */, 3 /* num_operands */, 829 { "seqb", TILE_OPC_SEQB, 0x3, 3, TREG_ZERO, 1,
7611 TREG_SN, /* implicitly_written_register */ 830 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7612 1, /* can_bundle */
7613 {
7614 /* operands */
7615 { 7, 8, 16 },
7616 { 9, 10, 17 },
7617 { 0, },
7618 { 0, },
7619 { 0, }
7620 },
7621 {
7622 /* fixed_bit_masks */
7623 0x800000007ffc0000ULL,
7624 0xfffe000000000000ULL,
7625 0ULL,
7626 0ULL,
7627 0ULL
7628 },
7629 {
7630 /* fixed_bit_values */
7631 0x0000000009000000ULL,
7632 0x0c42000000000000ULL,
7633 -1ULL,
7634 -1ULL,
7635 -1ULL
7636 }
7637 }, 831 },
7638 { "seqh", TILE_OPC_SEQH, 0x3 /* pipes */, 3 /* num_operands */, 832 { "seqb.sn", TILE_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1,
7639 TREG_ZERO, /* implicitly_written_register */ 833 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7640 1, /* can_bundle */
7641 {
7642 /* operands */
7643 { 7, 8, 16 },
7644 { 9, 10, 17 },
7645 { 0, },
7646 { 0, },
7647 { 0, }
7648 },
7649 {
7650 /* fixed_bit_masks */
7651 0x800000007ffc0000ULL,
7652 0xfffe000000000000ULL,
7653 0ULL,
7654 0ULL,
7655 0ULL
7656 },
7657 {
7658 /* fixed_bit_values */
7659 0x0000000001040000ULL,
7660 0x0844000000000000ULL,
7661 -1ULL,
7662 -1ULL,
7663 -1ULL
7664 }
7665 }, 834 },
7666 { "seqh.sn", TILE_OPC_SEQH_SN, 0x3 /* pipes */, 3 /* num_operands */, 835 { "seqh", TILE_OPC_SEQH, 0x3, 3, TREG_ZERO, 1,
7667 TREG_SN, /* implicitly_written_register */ 836 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7668 1, /* can_bundle */
7669 {
7670 /* operands */
7671 { 7, 8, 16 },
7672 { 9, 10, 17 },
7673 { 0, },
7674 { 0, },
7675 { 0, }
7676 },
7677 {
7678 /* fixed_bit_masks */
7679 0x800000007ffc0000ULL,
7680 0xfffe000000000000ULL,
7681 0ULL,
7682 0ULL,
7683 0ULL
7684 },
7685 {
7686 /* fixed_bit_values */
7687 0x0000000009040000ULL,
7688 0x0c44000000000000ULL,
7689 -1ULL,
7690 -1ULL,
7691 -1ULL
7692 }
7693 }, 837 },
7694 { "seqi", TILE_OPC_SEQI, 0xf /* pipes */, 3 /* num_operands */, 838 { "seqh.sn", TILE_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1,
7695 TREG_ZERO, /* implicitly_written_register */ 839 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7696 1, /* can_bundle */
7697 {
7698 /* operands */
7699 { 7, 8, 0 },
7700 { 9, 10, 1 },
7701 { 11, 12, 2 },
7702 { 13, 14, 3 },
7703 { 0, }
7704 },
7705 {
7706 /* fixed_bit_masks */
7707 0x800000007ff00000ULL,
7708 0xfff8000000000000ULL,
7709 0x8000000078000000ULL,
7710 0xf800000000000000ULL,
7711 0ULL
7712 },
7713 {
7714 /* fixed_bit_values */
7715 0x0000000040b00000ULL,
7716 0x3070000000000000ULL,
7717 0x8000000060000000ULL,
7718 0xd000000000000000ULL,
7719 -1ULL
7720 }
7721 }, 840 },
7722 { "seqi.sn", TILE_OPC_SEQI_SN, 0x3 /* pipes */, 3 /* num_operands */, 841 { "seqi", TILE_OPC_SEQI, 0xf, 3, TREG_ZERO, 1,
7723 TREG_SN, /* implicitly_written_register */ 842 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
7724 1, /* can_bundle */
7725 {
7726 /* operands */
7727 { 7, 8, 0 },
7728 { 9, 10, 1 },
7729 { 0, },
7730 { 0, },
7731 { 0, }
7732 },
7733 {
7734 /* fixed_bit_masks */
7735 0x800000007ff00000ULL,
7736 0xfff8000000000000ULL,
7737 0ULL,
7738 0ULL,
7739 0ULL
7740 },
7741 {
7742 /* fixed_bit_values */
7743 0x0000000048b00000ULL,
7744 0x3470000000000000ULL,
7745 -1ULL,
7746 -1ULL,
7747 -1ULL
7748 }
7749 }, 843 },
7750 { "seqib", TILE_OPC_SEQIB, 0x3 /* pipes */, 3 /* num_operands */, 844 { "seqi.sn", TILE_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1,
7751 TREG_ZERO, /* implicitly_written_register */ 845 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
7752 1, /* can_bundle */
7753 {
7754 /* operands */
7755 { 7, 8, 0 },
7756 { 9, 10, 1 },
7757 { 0, },
7758 { 0, },
7759 { 0, }
7760 },
7761 {
7762 /* fixed_bit_masks */
7763 0x800000007ff00000ULL,
7764 0xfff8000000000000ULL,
7765 0ULL,
7766 0ULL,
7767 0ULL
7768 },
7769 {
7770 /* fixed_bit_values */
7771 0x0000000040900000ULL,
7772 0x3060000000000000ULL,
7773 -1ULL,
7774 -1ULL,
7775 -1ULL
7776 }
7777 }, 846 },
7778 { "seqib.sn", TILE_OPC_SEQIB_SN, 0x3 /* pipes */, 3 /* num_operands */, 847 { "seqib", TILE_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1,
7779 TREG_SN, /* implicitly_written_register */ 848 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
7780 1, /* can_bundle */
7781 {
7782 /* operands */
7783 { 7, 8, 0 },
7784 { 9, 10, 1 },
7785 { 0, },
7786 { 0, },
7787 { 0, }
7788 },
7789 {
7790 /* fixed_bit_masks */
7791 0x800000007ff00000ULL,
7792 0xfff8000000000000ULL,
7793 0ULL,
7794 0ULL,
7795 0ULL
7796 },
7797 {
7798 /* fixed_bit_values */
7799 0x0000000048900000ULL,
7800 0x3460000000000000ULL,
7801 -1ULL,
7802 -1ULL,
7803 -1ULL
7804 }
7805 }, 849 },
7806 { "seqih", TILE_OPC_SEQIH, 0x3 /* pipes */, 3 /* num_operands */, 850 { "seqib.sn", TILE_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1,
7807 TREG_ZERO, /* implicitly_written_register */ 851 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
7808 1, /* can_bundle */
7809 {
7810 /* operands */
7811 { 7, 8, 0 },
7812 { 9, 10, 1 },
7813 { 0, },
7814 { 0, },
7815 { 0, }
7816 },
7817 {
7818 /* fixed_bit_masks */
7819 0x800000007ff00000ULL,
7820 0xfff8000000000000ULL,
7821 0ULL,
7822 0ULL,
7823 0ULL
7824 },
7825 {
7826 /* fixed_bit_values */
7827 0x0000000040a00000ULL,
7828 0x3068000000000000ULL,
7829 -1ULL,
7830 -1ULL,
7831 -1ULL
7832 }
7833 }, 852 },
7834 { "seqih.sn", TILE_OPC_SEQIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 853 { "seqih", TILE_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1,
7835 TREG_SN, /* implicitly_written_register */ 854 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
7836 1, /* can_bundle */
7837 {
7838 /* operands */
7839 { 7, 8, 0 },
7840 { 9, 10, 1 },
7841 { 0, },
7842 { 0, },
7843 { 0, }
7844 },
7845 {
7846 /* fixed_bit_masks */
7847 0x800000007ff00000ULL,
7848 0xfff8000000000000ULL,
7849 0ULL,
7850 0ULL,
7851 0ULL
7852 },
7853 {
7854 /* fixed_bit_values */
7855 0x0000000048a00000ULL,
7856 0x3468000000000000ULL,
7857 -1ULL,
7858 -1ULL,
7859 -1ULL
7860 }
7861 }, 855 },
7862 { "sh", TILE_OPC_SH, 0x12 /* pipes */, 2 /* num_operands */, 856 { "seqih.sn", TILE_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1,
7863 TREG_ZERO, /* implicitly_written_register */ 857 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
7864 1, /* can_bundle */
7865 {
7866 /* operands */
7867 { 0, },
7868 { 10, 17 },
7869 { 0, },
7870 { 0, },
7871 { 15, 36 }
7872 },
7873 {
7874 /* fixed_bit_masks */
7875 0ULL,
7876 0xfbfe000000000000ULL,
7877 0ULL,
7878 0ULL,
7879 0x8700000000000000ULL
7880 },
7881 {
7882 /* fixed_bit_values */
7883 -1ULL,
7884 0x0854000000000000ULL,
7885 -1ULL,
7886 -1ULL,
7887 0x8600000000000000ULL
7888 }
7889 }, 858 },
7890 { "shadd", TILE_OPC_SHADD, 0x2 /* pipes */, 3 /* num_operands */, 859 { "sh", TILE_OPC_SH, 0x12, 2, TREG_ZERO, 1,
7891 TREG_ZERO, /* implicitly_written_register */ 860 { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
7892 1, /* can_bundle */
7893 {
7894 /* operands */
7895 { 0, },
7896 { 24, 17, 37 },
7897 { 0, },
7898 { 0, },
7899 { 0, }
7900 },
7901 {
7902 /* fixed_bit_masks */
7903 0ULL,
7904 0xfbf8000000000000ULL,
7905 0ULL,
7906 0ULL,
7907 0ULL
7908 },
7909 {
7910 /* fixed_bit_values */
7911 -1ULL,
7912 0x30e8000000000000ULL,
7913 -1ULL,
7914 -1ULL,
7915 -1ULL
7916 }
7917 }, 861 },
7918 { "shl", TILE_OPC_SHL, 0xf /* pipes */, 3 /* num_operands */, 862 { "shadd", TILE_OPC_SHADD, 0x2, 3, TREG_ZERO, 1,
7919 TREG_ZERO, /* implicitly_written_register */ 863 { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } },
7920 1, /* can_bundle */
7921 {
7922 /* operands */
7923 { 7, 8, 16 },
7924 { 9, 10, 17 },
7925 { 11, 12, 18 },
7926 { 13, 14, 19 },
7927 { 0, }
7928 },
7929 {
7930 /* fixed_bit_masks */
7931 0x800000007ffc0000ULL,
7932 0xfffe000000000000ULL,
7933 0x80000000780c0000ULL,
7934 0xf806000000000000ULL,
7935 0ULL
7936 },
7937 {
7938 /* fixed_bit_values */
7939 0x0000000001140000ULL,
7940 0x084c000000000000ULL,
7941 0x8000000020040000ULL,
7942 0xa002000000000000ULL,
7943 -1ULL
7944 }
7945 }, 864 },
7946 { "shl.sn", TILE_OPC_SHL_SN, 0x3 /* pipes */, 3 /* num_operands */, 865 { "shl", TILE_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
7947 TREG_SN, /* implicitly_written_register */ 866 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
7948 1, /* can_bundle */
7949 {
7950 /* operands */
7951 { 7, 8, 16 },
7952 { 9, 10, 17 },
7953 { 0, },
7954 { 0, },
7955 { 0, }
7956 },
7957 {
7958 /* fixed_bit_masks */
7959 0x800000007ffc0000ULL,
7960 0xfffe000000000000ULL,
7961 0ULL,
7962 0ULL,
7963 0ULL
7964 },
7965 {
7966 /* fixed_bit_values */
7967 0x0000000009140000ULL,
7968 0x0c4c000000000000ULL,
7969 -1ULL,
7970 -1ULL,
7971 -1ULL
7972 }
7973 }, 867 },
7974 { "shlb", TILE_OPC_SHLB, 0x3 /* pipes */, 3 /* num_operands */, 868 { "shl.sn", TILE_OPC_SHL_SN, 0x3, 3, TREG_SN, 1,
7975 TREG_ZERO, /* implicitly_written_register */ 869 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
7976 1, /* can_bundle */
7977 {
7978 /* operands */
7979 { 7, 8, 16 },
7980 { 9, 10, 17 },
7981 { 0, },
7982 { 0, },
7983 { 0, }
7984 },
7985 {
7986 /* fixed_bit_masks */
7987 0x800000007ffc0000ULL,
7988 0xfffe000000000000ULL,
7989 0ULL,
7990 0ULL,
7991 0ULL
7992 },
7993 {
7994 /* fixed_bit_values */
7995 0x00000000010c0000ULL,
7996 0x0848000000000000ULL,
7997 -1ULL,
7998 -1ULL,
7999 -1ULL
8000 }
8001 }, 870 },
8002 { "shlb.sn", TILE_OPC_SHLB_SN, 0x3 /* pipes */, 3 /* num_operands */, 871 { "shlb", TILE_OPC_SHLB, 0x3, 3, TREG_ZERO, 1,
8003 TREG_SN, /* implicitly_written_register */ 872 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8004 1, /* can_bundle */
8005 {
8006 /* operands */
8007 { 7, 8, 16 },
8008 { 9, 10, 17 },
8009 { 0, },
8010 { 0, },
8011 { 0, }
8012 },
8013 {
8014 /* fixed_bit_masks */
8015 0x800000007ffc0000ULL,
8016 0xfffe000000000000ULL,
8017 0ULL,
8018 0ULL,
8019 0ULL
8020 },
8021 {
8022 /* fixed_bit_values */
8023 0x00000000090c0000ULL,
8024 0x0c48000000000000ULL,
8025 -1ULL,
8026 -1ULL,
8027 -1ULL
8028 }
8029 }, 873 },
8030 { "shlh", TILE_OPC_SHLH, 0x3 /* pipes */, 3 /* num_operands */, 874 { "shlb.sn", TILE_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1,
8031 TREG_ZERO, /* implicitly_written_register */ 875 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8032 1, /* can_bundle */
8033 {
8034 /* operands */
8035 { 7, 8, 16 },
8036 { 9, 10, 17 },
8037 { 0, },
8038 { 0, },
8039 { 0, }
8040 },
8041 {
8042 /* fixed_bit_masks */
8043 0x800000007ffc0000ULL,
8044 0xfffe000000000000ULL,
8045 0ULL,
8046 0ULL,
8047 0ULL
8048 },
8049 {
8050 /* fixed_bit_values */
8051 0x0000000001100000ULL,
8052 0x084a000000000000ULL,
8053 -1ULL,
8054 -1ULL,
8055 -1ULL
8056 }
8057 }, 876 },
8058 { "shlh.sn", TILE_OPC_SHLH_SN, 0x3 /* pipes */, 3 /* num_operands */, 877 { "shlh", TILE_OPC_SHLH, 0x3, 3, TREG_ZERO, 1,
8059 TREG_SN, /* implicitly_written_register */ 878 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8060 1, /* can_bundle */
8061 {
8062 /* operands */
8063 { 7, 8, 16 },
8064 { 9, 10, 17 },
8065 { 0, },
8066 { 0, },
8067 { 0, }
8068 },
8069 {
8070 /* fixed_bit_masks */
8071 0x800000007ffc0000ULL,
8072 0xfffe000000000000ULL,
8073 0ULL,
8074 0ULL,
8075 0ULL
8076 },
8077 {
8078 /* fixed_bit_values */
8079 0x0000000009100000ULL,
8080 0x0c4a000000000000ULL,
8081 -1ULL,
8082 -1ULL,
8083 -1ULL
8084 }
8085 }, 879 },
8086 { "shli", TILE_OPC_SHLI, 0xf /* pipes */, 3 /* num_operands */, 880 { "shlh.sn", TILE_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1,
8087 TREG_ZERO, /* implicitly_written_register */ 881 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8088 1, /* can_bundle */
8089 {
8090 /* operands */
8091 { 7, 8, 32 },
8092 { 9, 10, 33 },
8093 { 11, 12, 34 },
8094 { 13, 14, 35 },
8095 { 0, }
8096 },
8097 {
8098 /* fixed_bit_masks */
8099 0x800000007ffe0000ULL,
8100 0xffff000000000000ULL,
8101 0x80000000780e0000ULL,
8102 0xf807000000000000ULL,
8103 0ULL
8104 },
8105 {
8106 /* fixed_bit_values */
8107 0x0000000070080000ULL,
8108 0x4004000000000000ULL,
8109 0x8000000068040000ULL,
8110 0xd802000000000000ULL,
8111 -1ULL
8112 }
8113 }, 882 },
8114 { "shli.sn", TILE_OPC_SHLI_SN, 0x3 /* pipes */, 3 /* num_operands */, 883 { "shli", TILE_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
8115 TREG_SN, /* implicitly_written_register */ 884 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
8116 1, /* can_bundle */
8117 {
8118 /* operands */
8119 { 7, 8, 32 },
8120 { 9, 10, 33 },
8121 { 0, },
8122 { 0, },
8123 { 0, }
8124 },
8125 {
8126 /* fixed_bit_masks */
8127 0x800000007ffe0000ULL,
8128 0xffff000000000000ULL,
8129 0ULL,
8130 0ULL,
8131 0ULL
8132 },
8133 {
8134 /* fixed_bit_values */
8135 0x0000000078080000ULL,
8136 0x4404000000000000ULL,
8137 -1ULL,
8138 -1ULL,
8139 -1ULL
8140 }
8141 }, 885 },
8142 { "shlib", TILE_OPC_SHLIB, 0x3 /* pipes */, 3 /* num_operands */, 886 { "shli.sn", TILE_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1,
8143 TREG_ZERO, /* implicitly_written_register */ 887 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8144 1, /* can_bundle */
8145 {
8146 /* operands */
8147 { 7, 8, 32 },
8148 { 9, 10, 33 },
8149 { 0, },
8150 { 0, },
8151 { 0, }
8152 },
8153 {
8154 /* fixed_bit_masks */
8155 0x800000007ffe0000ULL,
8156 0xffff000000000000ULL,
8157 0ULL,
8158 0ULL,
8159 0ULL
8160 },
8161 {
8162 /* fixed_bit_values */
8163 0x0000000070040000ULL,
8164 0x4002000000000000ULL,
8165 -1ULL,
8166 -1ULL,
8167 -1ULL
8168 }
8169 }, 888 },
8170 { "shlib.sn", TILE_OPC_SHLIB_SN, 0x3 /* pipes */, 3 /* num_operands */, 889 { "shlib", TILE_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1,
8171 TREG_SN, /* implicitly_written_register */ 890 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8172 1, /* can_bundle */
8173 {
8174 /* operands */
8175 { 7, 8, 32 },
8176 { 9, 10, 33 },
8177 { 0, },
8178 { 0, },
8179 { 0, }
8180 },
8181 {
8182 /* fixed_bit_masks */
8183 0x800000007ffe0000ULL,
8184 0xffff000000000000ULL,
8185 0ULL,
8186 0ULL,
8187 0ULL
8188 },
8189 {
8190 /* fixed_bit_values */
8191 0x0000000078040000ULL,
8192 0x4402000000000000ULL,
8193 -1ULL,
8194 -1ULL,
8195 -1ULL
8196 }
8197 }, 891 },
8198 { "shlih", TILE_OPC_SHLIH, 0x3 /* pipes */, 3 /* num_operands */, 892 { "shlib.sn", TILE_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1,
8199 TREG_ZERO, /* implicitly_written_register */ 893 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8200 1, /* can_bundle */
8201 {
8202 /* operands */
8203 { 7, 8, 32 },
8204 { 9, 10, 33 },
8205 { 0, },
8206 { 0, },
8207 { 0, }
8208 },
8209 {
8210 /* fixed_bit_masks */
8211 0x800000007ffe0000ULL,
8212 0xffff000000000000ULL,
8213 0ULL,
8214 0ULL,
8215 0ULL
8216 },
8217 {
8218 /* fixed_bit_values */
8219 0x0000000070060000ULL,
8220 0x4003000000000000ULL,
8221 -1ULL,
8222 -1ULL,
8223 -1ULL
8224 }
8225 }, 894 },
8226 { "shlih.sn", TILE_OPC_SHLIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 895 { "shlih", TILE_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1,
8227 TREG_SN, /* implicitly_written_register */ 896 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8228 1, /* can_bundle */
8229 {
8230 /* operands */
8231 { 7, 8, 32 },
8232 { 9, 10, 33 },
8233 { 0, },
8234 { 0, },
8235 { 0, }
8236 },
8237 {
8238 /* fixed_bit_masks */
8239 0x800000007ffe0000ULL,
8240 0xffff000000000000ULL,
8241 0ULL,
8242 0ULL,
8243 0ULL
8244 },
8245 {
8246 /* fixed_bit_values */
8247 0x0000000078060000ULL,
8248 0x4403000000000000ULL,
8249 -1ULL,
8250 -1ULL,
8251 -1ULL
8252 }
8253 }, 897 },
8254 { "shr", TILE_OPC_SHR, 0xf /* pipes */, 3 /* num_operands */, 898 { "shlih.sn", TILE_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1,
8255 TREG_ZERO, /* implicitly_written_register */ 899 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8256 1, /* can_bundle */
8257 {
8258 /* operands */
8259 { 7, 8, 16 },
8260 { 9, 10, 17 },
8261 { 11, 12, 18 },
8262 { 13, 14, 19 },
8263 { 0, }
8264 },
8265 {
8266 /* fixed_bit_masks */
8267 0x800000007ffc0000ULL,
8268 0xfffe000000000000ULL,
8269 0x80000000780c0000ULL,
8270 0xf806000000000000ULL,
8271 0ULL
8272 },
8273 {
8274 /* fixed_bit_values */
8275 0x0000000001200000ULL,
8276 0x0852000000000000ULL,
8277 0x8000000020080000ULL,
8278 0xa004000000000000ULL,
8279 -1ULL
8280 }
8281 }, 900 },
8282 { "shr.sn", TILE_OPC_SHR_SN, 0x3 /* pipes */, 3 /* num_operands */, 901 { "shr", TILE_OPC_SHR, 0xf, 3, TREG_ZERO, 1,
8283 TREG_SN, /* implicitly_written_register */ 902 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
8284 1, /* can_bundle */
8285 {
8286 /* operands */
8287 { 7, 8, 16 },
8288 { 9, 10, 17 },
8289 { 0, },
8290 { 0, },
8291 { 0, }
8292 },
8293 {
8294 /* fixed_bit_masks */
8295 0x800000007ffc0000ULL,
8296 0xfffe000000000000ULL,
8297 0ULL,
8298 0ULL,
8299 0ULL
8300 },
8301 {
8302 /* fixed_bit_values */
8303 0x0000000009200000ULL,
8304 0x0c52000000000000ULL,
8305 -1ULL,
8306 -1ULL,
8307 -1ULL
8308 }
8309 }, 903 },
8310 { "shrb", TILE_OPC_SHRB, 0x3 /* pipes */, 3 /* num_operands */, 904 { "shr.sn", TILE_OPC_SHR_SN, 0x3, 3, TREG_SN, 1,
8311 TREG_ZERO, /* implicitly_written_register */ 905 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8312 1, /* can_bundle */
8313 {
8314 /* operands */
8315 { 7, 8, 16 },
8316 { 9, 10, 17 },
8317 { 0, },
8318 { 0, },
8319 { 0, }
8320 },
8321 {
8322 /* fixed_bit_masks */
8323 0x800000007ffc0000ULL,
8324 0xfffe000000000000ULL,
8325 0ULL,
8326 0ULL,
8327 0ULL
8328 },
8329 {
8330 /* fixed_bit_values */
8331 0x0000000001180000ULL,
8332 0x084e000000000000ULL,
8333 -1ULL,
8334 -1ULL,
8335 -1ULL
8336 }
8337 }, 906 },
8338 { "shrb.sn", TILE_OPC_SHRB_SN, 0x3 /* pipes */, 3 /* num_operands */, 907 { "shrb", TILE_OPC_SHRB, 0x3, 3, TREG_ZERO, 1,
8339 TREG_SN, /* implicitly_written_register */ 908 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8340 1, /* can_bundle */
8341 {
8342 /* operands */
8343 { 7, 8, 16 },
8344 { 9, 10, 17 },
8345 { 0, },
8346 { 0, },
8347 { 0, }
8348 },
8349 {
8350 /* fixed_bit_masks */
8351 0x800000007ffc0000ULL,
8352 0xfffe000000000000ULL,
8353 0ULL,
8354 0ULL,
8355 0ULL
8356 },
8357 {
8358 /* fixed_bit_values */
8359 0x0000000009180000ULL,
8360 0x0c4e000000000000ULL,
8361 -1ULL,
8362 -1ULL,
8363 -1ULL
8364 }
8365 }, 909 },
8366 { "shrh", TILE_OPC_SHRH, 0x3 /* pipes */, 3 /* num_operands */, 910 { "shrb.sn", TILE_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1,
8367 TREG_ZERO, /* implicitly_written_register */ 911 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8368 1, /* can_bundle */
8369 {
8370 /* operands */
8371 { 7, 8, 16 },
8372 { 9, 10, 17 },
8373 { 0, },
8374 { 0, },
8375 { 0, }
8376 },
8377 {
8378 /* fixed_bit_masks */
8379 0x800000007ffc0000ULL,
8380 0xfffe000000000000ULL,
8381 0ULL,
8382 0ULL,
8383 0ULL
8384 },
8385 {
8386 /* fixed_bit_values */
8387 0x00000000011c0000ULL,
8388 0x0850000000000000ULL,
8389 -1ULL,
8390 -1ULL,
8391 -1ULL
8392 }
8393 }, 912 },
8394 { "shrh.sn", TILE_OPC_SHRH_SN, 0x3 /* pipes */, 3 /* num_operands */, 913 { "shrh", TILE_OPC_SHRH, 0x3, 3, TREG_ZERO, 1,
8395 TREG_SN, /* implicitly_written_register */ 914 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8396 1, /* can_bundle */
8397 {
8398 /* operands */
8399 { 7, 8, 16 },
8400 { 9, 10, 17 },
8401 { 0, },
8402 { 0, },
8403 { 0, }
8404 },
8405 {
8406 /* fixed_bit_masks */
8407 0x800000007ffc0000ULL,
8408 0xfffe000000000000ULL,
8409 0ULL,
8410 0ULL,
8411 0ULL
8412 },
8413 {
8414 /* fixed_bit_values */
8415 0x00000000091c0000ULL,
8416 0x0c50000000000000ULL,
8417 -1ULL,
8418 -1ULL,
8419 -1ULL
8420 }
8421 }, 915 },
8422 { "shri", TILE_OPC_SHRI, 0xf /* pipes */, 3 /* num_operands */, 916 { "shrh.sn", TILE_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1,
8423 TREG_ZERO, /* implicitly_written_register */ 917 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8424 1, /* can_bundle */
8425 {
8426 /* operands */
8427 { 7, 8, 32 },
8428 { 9, 10, 33 },
8429 { 11, 12, 34 },
8430 { 13, 14, 35 },
8431 { 0, }
8432 },
8433 {
8434 /* fixed_bit_masks */
8435 0x800000007ffe0000ULL,
8436 0xffff000000000000ULL,
8437 0x80000000780e0000ULL,
8438 0xf807000000000000ULL,
8439 0ULL
8440 },
8441 {
8442 /* fixed_bit_values */
8443 0x00000000700e0000ULL,
8444 0x4007000000000000ULL,
8445 0x8000000068060000ULL,
8446 0xd803000000000000ULL,
8447 -1ULL
8448 }
8449 }, 918 },
8450 { "shri.sn", TILE_OPC_SHRI_SN, 0x3 /* pipes */, 3 /* num_operands */, 919 { "shri", TILE_OPC_SHRI, 0xf, 3, TREG_ZERO, 1,
8451 TREG_SN, /* implicitly_written_register */ 920 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
8452 1, /* can_bundle */
8453 {
8454 /* operands */
8455 { 7, 8, 32 },
8456 { 9, 10, 33 },
8457 { 0, },
8458 { 0, },
8459 { 0, }
8460 },
8461 {
8462 /* fixed_bit_masks */
8463 0x800000007ffe0000ULL,
8464 0xffff000000000000ULL,
8465 0ULL,
8466 0ULL,
8467 0ULL
8468 },
8469 {
8470 /* fixed_bit_values */
8471 0x00000000780e0000ULL,
8472 0x4407000000000000ULL,
8473 -1ULL,
8474 -1ULL,
8475 -1ULL
8476 }
8477 }, 921 },
8478 { "shrib", TILE_OPC_SHRIB, 0x3 /* pipes */, 3 /* num_operands */, 922 { "shri.sn", TILE_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1,
8479 TREG_ZERO, /* implicitly_written_register */ 923 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8480 1, /* can_bundle */
8481 {
8482 /* operands */
8483 { 7, 8, 32 },
8484 { 9, 10, 33 },
8485 { 0, },
8486 { 0, },
8487 { 0, }
8488 },
8489 {
8490 /* fixed_bit_masks */
8491 0x800000007ffe0000ULL,
8492 0xffff000000000000ULL,
8493 0ULL,
8494 0ULL,
8495 0ULL
8496 },
8497 {
8498 /* fixed_bit_values */
8499 0x00000000700a0000ULL,
8500 0x4005000000000000ULL,
8501 -1ULL,
8502 -1ULL,
8503 -1ULL
8504 }
8505 }, 924 },
8506 { "shrib.sn", TILE_OPC_SHRIB_SN, 0x3 /* pipes */, 3 /* num_operands */, 925 { "shrib", TILE_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1,
8507 TREG_SN, /* implicitly_written_register */ 926 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8508 1, /* can_bundle */
8509 {
8510 /* operands */
8511 { 7, 8, 32 },
8512 { 9, 10, 33 },
8513 { 0, },
8514 { 0, },
8515 { 0, }
8516 },
8517 {
8518 /* fixed_bit_masks */
8519 0x800000007ffe0000ULL,
8520 0xffff000000000000ULL,
8521 0ULL,
8522 0ULL,
8523 0ULL
8524 },
8525 {
8526 /* fixed_bit_values */
8527 0x00000000780a0000ULL,
8528 0x4405000000000000ULL,
8529 -1ULL,
8530 -1ULL,
8531 -1ULL
8532 }
8533 }, 927 },
8534 { "shrih", TILE_OPC_SHRIH, 0x3 /* pipes */, 3 /* num_operands */, 928 { "shrib.sn", TILE_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1,
8535 TREG_ZERO, /* implicitly_written_register */ 929 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8536 1, /* can_bundle */
8537 {
8538 /* operands */
8539 { 7, 8, 32 },
8540 { 9, 10, 33 },
8541 { 0, },
8542 { 0, },
8543 { 0, }
8544 },
8545 {
8546 /* fixed_bit_masks */
8547 0x800000007ffe0000ULL,
8548 0xffff000000000000ULL,
8549 0ULL,
8550 0ULL,
8551 0ULL
8552 },
8553 {
8554 /* fixed_bit_values */
8555 0x00000000700c0000ULL,
8556 0x4006000000000000ULL,
8557 -1ULL,
8558 -1ULL,
8559 -1ULL
8560 }
8561 }, 930 },
8562 { "shrih.sn", TILE_OPC_SHRIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 931 { "shrih", TILE_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1,
8563 TREG_SN, /* implicitly_written_register */ 932 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8564 1, /* can_bundle */
8565 {
8566 /* operands */
8567 { 7, 8, 32 },
8568 { 9, 10, 33 },
8569 { 0, },
8570 { 0, },
8571 { 0, }
8572 },
8573 {
8574 /* fixed_bit_masks */
8575 0x800000007ffe0000ULL,
8576 0xffff000000000000ULL,
8577 0ULL,
8578 0ULL,
8579 0ULL
8580 },
8581 {
8582 /* fixed_bit_values */
8583 0x00000000780c0000ULL,
8584 0x4406000000000000ULL,
8585 -1ULL,
8586 -1ULL,
8587 -1ULL
8588 }
8589 }, 933 },
8590 { "slt", TILE_OPC_SLT, 0xf /* pipes */, 3 /* num_operands */, 934 { "shrih.sn", TILE_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1,
8591 TREG_ZERO, /* implicitly_written_register */ 935 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
8592 1, /* can_bundle */
8593 {
8594 /* operands */
8595 { 7, 8, 16 },
8596 { 9, 10, 17 },
8597 { 11, 12, 18 },
8598 { 13, 14, 19 },
8599 { 0, }
8600 },
8601 {
8602 /* fixed_bit_masks */
8603 0x800000007ffc0000ULL,
8604 0xfffe000000000000ULL,
8605 0x80000000780c0000ULL,
8606 0xf806000000000000ULL,
8607 0ULL
8608 },
8609 {
8610 /* fixed_bit_values */
8611 0x00000000014c0000ULL,
8612 0x086a000000000000ULL,
8613 0x8000000028080000ULL,
8614 0xa804000000000000ULL,
8615 -1ULL
8616 }
8617 }, 936 },
8618 { "slt.sn", TILE_OPC_SLT_SN, 0x3 /* pipes */, 3 /* num_operands */, 937 { "slt", TILE_OPC_SLT, 0xf, 3, TREG_ZERO, 1,
8619 TREG_SN, /* implicitly_written_register */ 938 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
8620 1, /* can_bundle */
8621 {
8622 /* operands */
8623 { 7, 8, 16 },
8624 { 9, 10, 17 },
8625 { 0, },
8626 { 0, },
8627 { 0, }
8628 },
8629 {
8630 /* fixed_bit_masks */
8631 0x800000007ffc0000ULL,
8632 0xfffe000000000000ULL,
8633 0ULL,
8634 0ULL,
8635 0ULL
8636 },
8637 {
8638 /* fixed_bit_values */
8639 0x00000000094c0000ULL,
8640 0x0c6a000000000000ULL,
8641 -1ULL,
8642 -1ULL,
8643 -1ULL
8644 }
8645 }, 939 },
8646 { "slt_u", TILE_OPC_SLT_U, 0xf /* pipes */, 3 /* num_operands */, 940 { "slt.sn", TILE_OPC_SLT_SN, 0x3, 3, TREG_SN, 1,
8647 TREG_ZERO, /* implicitly_written_register */ 941 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8648 1, /* can_bundle */
8649 {
8650 /* operands */
8651 { 7, 8, 16 },
8652 { 9, 10, 17 },
8653 { 11, 12, 18 },
8654 { 13, 14, 19 },
8655 { 0, }
8656 },
8657 {
8658 /* fixed_bit_masks */
8659 0x800000007ffc0000ULL,
8660 0xfffe000000000000ULL,
8661 0x80000000780c0000ULL,
8662 0xf806000000000000ULL,
8663 0ULL
8664 },
8665 {
8666 /* fixed_bit_values */
8667 0x0000000001500000ULL,
8668 0x086c000000000000ULL,
8669 0x80000000280c0000ULL,
8670 0xa806000000000000ULL,
8671 -1ULL
8672 }
8673 }, 942 },
8674 { "slt_u.sn", TILE_OPC_SLT_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 943 { "slt_u", TILE_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1,
8675 TREG_SN, /* implicitly_written_register */ 944 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
8676 1, /* can_bundle */
8677 {
8678 /* operands */
8679 { 7, 8, 16 },
8680 { 9, 10, 17 },
8681 { 0, },
8682 { 0, },
8683 { 0, }
8684 },
8685 {
8686 /* fixed_bit_masks */
8687 0x800000007ffc0000ULL,
8688 0xfffe000000000000ULL,
8689 0ULL,
8690 0ULL,
8691 0ULL
8692 },
8693 {
8694 /* fixed_bit_values */
8695 0x0000000009500000ULL,
8696 0x0c6c000000000000ULL,
8697 -1ULL,
8698 -1ULL,
8699 -1ULL
8700 }
8701 }, 945 },
8702 { "sltb", TILE_OPC_SLTB, 0x3 /* pipes */, 3 /* num_operands */, 946 { "slt_u.sn", TILE_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1,
8703 TREG_ZERO, /* implicitly_written_register */ 947 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8704 1, /* can_bundle */
8705 {
8706 /* operands */
8707 { 7, 8, 16 },
8708 { 9, 10, 17 },
8709 { 0, },
8710 { 0, },
8711 { 0, }
8712 },
8713 {
8714 /* fixed_bit_masks */
8715 0x800000007ffc0000ULL,
8716 0xfffe000000000000ULL,
8717 0ULL,
8718 0ULL,
8719 0ULL
8720 },
8721 {
8722 /* fixed_bit_values */
8723 0x0000000001240000ULL,
8724 0x0856000000000000ULL,
8725 -1ULL,
8726 -1ULL,
8727 -1ULL
8728 }
8729 }, 948 },
8730 { "sltb.sn", TILE_OPC_SLTB_SN, 0x3 /* pipes */, 3 /* num_operands */, 949 { "sltb", TILE_OPC_SLTB, 0x3, 3, TREG_ZERO, 1,
8731 TREG_SN, /* implicitly_written_register */ 950 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8732 1, /* can_bundle */
8733 {
8734 /* operands */
8735 { 7, 8, 16 },
8736 { 9, 10, 17 },
8737 { 0, },
8738 { 0, },
8739 { 0, }
8740 },
8741 {
8742 /* fixed_bit_masks */
8743 0x800000007ffc0000ULL,
8744 0xfffe000000000000ULL,
8745 0ULL,
8746 0ULL,
8747 0ULL
8748 },
8749 {
8750 /* fixed_bit_values */
8751 0x0000000009240000ULL,
8752 0x0c56000000000000ULL,
8753 -1ULL,
8754 -1ULL,
8755 -1ULL
8756 }
8757 }, 951 },
8758 { "sltb_u", TILE_OPC_SLTB_U, 0x3 /* pipes */, 3 /* num_operands */, 952 { "sltb.sn", TILE_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1,
8759 TREG_ZERO, /* implicitly_written_register */ 953 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8760 1, /* can_bundle */
8761 {
8762 /* operands */
8763 { 7, 8, 16 },
8764 { 9, 10, 17 },
8765 { 0, },
8766 { 0, },
8767 { 0, }
8768 },
8769 {
8770 /* fixed_bit_masks */
8771 0x800000007ffc0000ULL,
8772 0xfffe000000000000ULL,
8773 0ULL,
8774 0ULL,
8775 0ULL
8776 },
8777 {
8778 /* fixed_bit_values */
8779 0x0000000001280000ULL,
8780 0x0858000000000000ULL,
8781 -1ULL,
8782 -1ULL,
8783 -1ULL
8784 }
8785 }, 954 },
8786 { "sltb_u.sn", TILE_OPC_SLTB_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 955 { "sltb_u", TILE_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1,
8787 TREG_SN, /* implicitly_written_register */ 956 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8788 1, /* can_bundle */
8789 {
8790 /* operands */
8791 { 7, 8, 16 },
8792 { 9, 10, 17 },
8793 { 0, },
8794 { 0, },
8795 { 0, }
8796 },
8797 {
8798 /* fixed_bit_masks */
8799 0x800000007ffc0000ULL,
8800 0xfffe000000000000ULL,
8801 0ULL,
8802 0ULL,
8803 0ULL
8804 },
8805 {
8806 /* fixed_bit_values */
8807 0x0000000009280000ULL,
8808 0x0c58000000000000ULL,
8809 -1ULL,
8810 -1ULL,
8811 -1ULL
8812 }
8813 }, 957 },
8814 { "slte", TILE_OPC_SLTE, 0xf /* pipes */, 3 /* num_operands */, 958 { "sltb_u.sn", TILE_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1,
8815 TREG_ZERO, /* implicitly_written_register */ 959 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8816 1, /* can_bundle */
8817 {
8818 /* operands */
8819 { 7, 8, 16 },
8820 { 9, 10, 17 },
8821 { 11, 12, 18 },
8822 { 13, 14, 19 },
8823 { 0, }
8824 },
8825 {
8826 /* fixed_bit_masks */
8827 0x800000007ffc0000ULL,
8828 0xfffe000000000000ULL,
8829 0x80000000780c0000ULL,
8830 0xf806000000000000ULL,
8831 0ULL
8832 },
8833 {
8834 /* fixed_bit_values */
8835 0x00000000013c0000ULL,
8836 0x0862000000000000ULL,
8837 0x8000000028000000ULL,
8838 0xa800000000000000ULL,
8839 -1ULL
8840 }
8841 }, 960 },
8842 { "slte.sn", TILE_OPC_SLTE_SN, 0x3 /* pipes */, 3 /* num_operands */, 961 { "slte", TILE_OPC_SLTE, 0xf, 3, TREG_ZERO, 1,
8843 TREG_SN, /* implicitly_written_register */ 962 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
8844 1, /* can_bundle */
8845 {
8846 /* operands */
8847 { 7, 8, 16 },
8848 { 9, 10, 17 },
8849 { 0, },
8850 { 0, },
8851 { 0, }
8852 },
8853 {
8854 /* fixed_bit_masks */
8855 0x800000007ffc0000ULL,
8856 0xfffe000000000000ULL,
8857 0ULL,
8858 0ULL,
8859 0ULL
8860 },
8861 {
8862 /* fixed_bit_values */
8863 0x00000000093c0000ULL,
8864 0x0c62000000000000ULL,
8865 -1ULL,
8866 -1ULL,
8867 -1ULL
8868 }
8869 }, 963 },
8870 { "slte_u", TILE_OPC_SLTE_U, 0xf /* pipes */, 3 /* num_operands */, 964 { "slte.sn", TILE_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1,
8871 TREG_ZERO, /* implicitly_written_register */ 965 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8872 1, /* can_bundle */
8873 {
8874 /* operands */
8875 { 7, 8, 16 },
8876 { 9, 10, 17 },
8877 { 11, 12, 18 },
8878 { 13, 14, 19 },
8879 { 0, }
8880 },
8881 {
8882 /* fixed_bit_masks */
8883 0x800000007ffc0000ULL,
8884 0xfffe000000000000ULL,
8885 0x80000000780c0000ULL,
8886 0xf806000000000000ULL,
8887 0ULL
8888 },
8889 {
8890 /* fixed_bit_values */
8891 0x0000000001400000ULL,
8892 0x0864000000000000ULL,
8893 0x8000000028040000ULL,
8894 0xa802000000000000ULL,
8895 -1ULL
8896 }
8897 }, 966 },
8898 { "slte_u.sn", TILE_OPC_SLTE_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 967 { "slte_u", TILE_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1,
8899 TREG_SN, /* implicitly_written_register */ 968 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
8900 1, /* can_bundle */
8901 {
8902 /* operands */
8903 { 7, 8, 16 },
8904 { 9, 10, 17 },
8905 { 0, },
8906 { 0, },
8907 { 0, }
8908 },
8909 {
8910 /* fixed_bit_masks */
8911 0x800000007ffc0000ULL,
8912 0xfffe000000000000ULL,
8913 0ULL,
8914 0ULL,
8915 0ULL
8916 },
8917 {
8918 /* fixed_bit_values */
8919 0x0000000009400000ULL,
8920 0x0c64000000000000ULL,
8921 -1ULL,
8922 -1ULL,
8923 -1ULL
8924 }
8925 }, 969 },
8926 { "slteb", TILE_OPC_SLTEB, 0x3 /* pipes */, 3 /* num_operands */, 970 { "slte_u.sn", TILE_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1,
8927 TREG_ZERO, /* implicitly_written_register */ 971 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8928 1, /* can_bundle */
8929 {
8930 /* operands */
8931 { 7, 8, 16 },
8932 { 9, 10, 17 },
8933 { 0, },
8934 { 0, },
8935 { 0, }
8936 },
8937 {
8938 /* fixed_bit_masks */
8939 0x800000007ffc0000ULL,
8940 0xfffe000000000000ULL,
8941 0ULL,
8942 0ULL,
8943 0ULL
8944 },
8945 {
8946 /* fixed_bit_values */
8947 0x00000000012c0000ULL,
8948 0x085a000000000000ULL,
8949 -1ULL,
8950 -1ULL,
8951 -1ULL
8952 }
8953 }, 972 },
8954 { "slteb.sn", TILE_OPC_SLTEB_SN, 0x3 /* pipes */, 3 /* num_operands */, 973 { "slteb", TILE_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1,
8955 TREG_SN, /* implicitly_written_register */ 974 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8956 1, /* can_bundle */
8957 {
8958 /* operands */
8959 { 7, 8, 16 },
8960 { 9, 10, 17 },
8961 { 0, },
8962 { 0, },
8963 { 0, }
8964 },
8965 {
8966 /* fixed_bit_masks */
8967 0x800000007ffc0000ULL,
8968 0xfffe000000000000ULL,
8969 0ULL,
8970 0ULL,
8971 0ULL
8972 },
8973 {
8974 /* fixed_bit_values */
8975 0x00000000092c0000ULL,
8976 0x0c5a000000000000ULL,
8977 -1ULL,
8978 -1ULL,
8979 -1ULL
8980 }
8981 }, 975 },
8982 { "slteb_u", TILE_OPC_SLTEB_U, 0x3 /* pipes */, 3 /* num_operands */, 976 { "slteb.sn", TILE_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1,
8983 TREG_ZERO, /* implicitly_written_register */ 977 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
8984 1, /* can_bundle */
8985 {
8986 /* operands */
8987 { 7, 8, 16 },
8988 { 9, 10, 17 },
8989 { 0, },
8990 { 0, },
8991 { 0, }
8992 },
8993 {
8994 /* fixed_bit_masks */
8995 0x800000007ffc0000ULL,
8996 0xfffe000000000000ULL,
8997 0ULL,
8998 0ULL,
8999 0ULL
9000 },
9001 {
9002 /* fixed_bit_values */
9003 0x0000000001300000ULL,
9004 0x085c000000000000ULL,
9005 -1ULL,
9006 -1ULL,
9007 -1ULL
9008 }
9009 }, 978 },
9010 { "slteb_u.sn", TILE_OPC_SLTEB_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 979 { "slteb_u", TILE_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1,
9011 TREG_SN, /* implicitly_written_register */ 980 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9012 1, /* can_bundle */
9013 {
9014 /* operands */
9015 { 7, 8, 16 },
9016 { 9, 10, 17 },
9017 { 0, },
9018 { 0, },
9019 { 0, }
9020 },
9021 {
9022 /* fixed_bit_masks */
9023 0x800000007ffc0000ULL,
9024 0xfffe000000000000ULL,
9025 0ULL,
9026 0ULL,
9027 0ULL
9028 },
9029 {
9030 /* fixed_bit_values */
9031 0x0000000009300000ULL,
9032 0x0c5c000000000000ULL,
9033 -1ULL,
9034 -1ULL,
9035 -1ULL
9036 }
9037 }, 981 },
9038 { "slteh", TILE_OPC_SLTEH, 0x3 /* pipes */, 3 /* num_operands */, 982 { "slteb_u.sn", TILE_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1,
9039 TREG_ZERO, /* implicitly_written_register */ 983 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9040 1, /* can_bundle */
9041 {
9042 /* operands */
9043 { 7, 8, 16 },
9044 { 9, 10, 17 },
9045 { 0, },
9046 { 0, },
9047 { 0, }
9048 },
9049 {
9050 /* fixed_bit_masks */
9051 0x800000007ffc0000ULL,
9052 0xfffe000000000000ULL,
9053 0ULL,
9054 0ULL,
9055 0ULL
9056 },
9057 {
9058 /* fixed_bit_values */
9059 0x0000000001340000ULL,
9060 0x085e000000000000ULL,
9061 -1ULL,
9062 -1ULL,
9063 -1ULL
9064 }
9065 }, 984 },
9066 { "slteh.sn", TILE_OPC_SLTEH_SN, 0x3 /* pipes */, 3 /* num_operands */, 985 { "slteh", TILE_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1,
9067 TREG_SN, /* implicitly_written_register */ 986 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9068 1, /* can_bundle */
9069 {
9070 /* operands */
9071 { 7, 8, 16 },
9072 { 9, 10, 17 },
9073 { 0, },
9074 { 0, },
9075 { 0, }
9076 },
9077 {
9078 /* fixed_bit_masks */
9079 0x800000007ffc0000ULL,
9080 0xfffe000000000000ULL,
9081 0ULL,
9082 0ULL,
9083 0ULL
9084 },
9085 {
9086 /* fixed_bit_values */
9087 0x0000000009340000ULL,
9088 0x0c5e000000000000ULL,
9089 -1ULL,
9090 -1ULL,
9091 -1ULL
9092 }
9093 }, 987 },
9094 { "slteh_u", TILE_OPC_SLTEH_U, 0x3 /* pipes */, 3 /* num_operands */, 988 { "slteh.sn", TILE_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1,
9095 TREG_ZERO, /* implicitly_written_register */ 989 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9096 1, /* can_bundle */
9097 {
9098 /* operands */
9099 { 7, 8, 16 },
9100 { 9, 10, 17 },
9101 { 0, },
9102 { 0, },
9103 { 0, }
9104 },
9105 {
9106 /* fixed_bit_masks */
9107 0x800000007ffc0000ULL,
9108 0xfffe000000000000ULL,
9109 0ULL,
9110 0ULL,
9111 0ULL
9112 },
9113 {
9114 /* fixed_bit_values */
9115 0x0000000001380000ULL,
9116 0x0860000000000000ULL,
9117 -1ULL,
9118 -1ULL,
9119 -1ULL
9120 }
9121 }, 990 },
9122 { "slteh_u.sn", TILE_OPC_SLTEH_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 991 { "slteh_u", TILE_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1,
9123 TREG_SN, /* implicitly_written_register */ 992 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9124 1, /* can_bundle */
9125 {
9126 /* operands */
9127 { 7, 8, 16 },
9128 { 9, 10, 17 },
9129 { 0, },
9130 { 0, },
9131 { 0, }
9132 },
9133 {
9134 /* fixed_bit_masks */
9135 0x800000007ffc0000ULL,
9136 0xfffe000000000000ULL,
9137 0ULL,
9138 0ULL,
9139 0ULL
9140 },
9141 {
9142 /* fixed_bit_values */
9143 0x0000000009380000ULL,
9144 0x0c60000000000000ULL,
9145 -1ULL,
9146 -1ULL,
9147 -1ULL
9148 }
9149 }, 993 },
9150 { "slth", TILE_OPC_SLTH, 0x3 /* pipes */, 3 /* num_operands */, 994 { "slteh_u.sn", TILE_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1,
9151 TREG_ZERO, /* implicitly_written_register */ 995 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9152 1, /* can_bundle */
9153 {
9154 /* operands */
9155 { 7, 8, 16 },
9156 { 9, 10, 17 },
9157 { 0, },
9158 { 0, },
9159 { 0, }
9160 },
9161 {
9162 /* fixed_bit_masks */
9163 0x800000007ffc0000ULL,
9164 0xfffe000000000000ULL,
9165 0ULL,
9166 0ULL,
9167 0ULL
9168 },
9169 {
9170 /* fixed_bit_values */
9171 0x0000000001440000ULL,
9172 0x0866000000000000ULL,
9173 -1ULL,
9174 -1ULL,
9175 -1ULL
9176 }
9177 }, 996 },
9178 { "slth.sn", TILE_OPC_SLTH_SN, 0x3 /* pipes */, 3 /* num_operands */, 997 { "slth", TILE_OPC_SLTH, 0x3, 3, TREG_ZERO, 1,
9179 TREG_SN, /* implicitly_written_register */ 998 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9180 1, /* can_bundle */
9181 {
9182 /* operands */
9183 { 7, 8, 16 },
9184 { 9, 10, 17 },
9185 { 0, },
9186 { 0, },
9187 { 0, }
9188 },
9189 {
9190 /* fixed_bit_masks */
9191 0x800000007ffc0000ULL,
9192 0xfffe000000000000ULL,
9193 0ULL,
9194 0ULL,
9195 0ULL
9196 },
9197 {
9198 /* fixed_bit_values */
9199 0x0000000009440000ULL,
9200 0x0c66000000000000ULL,
9201 -1ULL,
9202 -1ULL,
9203 -1ULL
9204 }
9205 }, 999 },
9206 { "slth_u", TILE_OPC_SLTH_U, 0x3 /* pipes */, 3 /* num_operands */, 1000 { "slth.sn", TILE_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1,
9207 TREG_ZERO, /* implicitly_written_register */ 1001 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9208 1, /* can_bundle */
9209 {
9210 /* operands */
9211 { 7, 8, 16 },
9212 { 9, 10, 17 },
9213 { 0, },
9214 { 0, },
9215 { 0, }
9216 },
9217 {
9218 /* fixed_bit_masks */
9219 0x800000007ffc0000ULL,
9220 0xfffe000000000000ULL,
9221 0ULL,
9222 0ULL,
9223 0ULL
9224 },
9225 {
9226 /* fixed_bit_values */
9227 0x0000000001480000ULL,
9228 0x0868000000000000ULL,
9229 -1ULL,
9230 -1ULL,
9231 -1ULL
9232 }
9233 }, 1002 },
9234 { "slth_u.sn", TILE_OPC_SLTH_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 1003 { "slth_u", TILE_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1,
9235 TREG_SN, /* implicitly_written_register */ 1004 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9236 1, /* can_bundle */
9237 {
9238 /* operands */
9239 { 7, 8, 16 },
9240 { 9, 10, 17 },
9241 { 0, },
9242 { 0, },
9243 { 0, }
9244 },
9245 {
9246 /* fixed_bit_masks */
9247 0x800000007ffc0000ULL,
9248 0xfffe000000000000ULL,
9249 0ULL,
9250 0ULL,
9251 0ULL
9252 },
9253 {
9254 /* fixed_bit_values */
9255 0x0000000009480000ULL,
9256 0x0c68000000000000ULL,
9257 -1ULL,
9258 -1ULL,
9259 -1ULL
9260 }
9261 }, 1005 },
9262 { "slti", TILE_OPC_SLTI, 0xf /* pipes */, 3 /* num_operands */, 1006 { "slth_u.sn", TILE_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1,
9263 TREG_ZERO, /* implicitly_written_register */ 1007 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9264 1, /* can_bundle */
9265 {
9266 /* operands */
9267 { 7, 8, 0 },
9268 { 9, 10, 1 },
9269 { 11, 12, 2 },
9270 { 13, 14, 3 },
9271 { 0, }
9272 },
9273 {
9274 /* fixed_bit_masks */
9275 0x800000007ff00000ULL,
9276 0xfff8000000000000ULL,
9277 0x8000000078000000ULL,
9278 0xf800000000000000ULL,
9279 0ULL
9280 },
9281 {
9282 /* fixed_bit_values */
9283 0x0000000041000000ULL,
9284 0x3098000000000000ULL,
9285 0x8000000070000000ULL,
9286 0xe000000000000000ULL,
9287 -1ULL
9288 }
9289 }, 1008 },
9290 { "slti.sn", TILE_OPC_SLTI_SN, 0x3 /* pipes */, 3 /* num_operands */, 1009 { "slti", TILE_OPC_SLTI, 0xf, 3, TREG_ZERO, 1,
9291 TREG_SN, /* implicitly_written_register */ 1010 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
9292 1, /* can_bundle */
9293 {
9294 /* operands */
9295 { 7, 8, 0 },
9296 { 9, 10, 1 },
9297 { 0, },
9298 { 0, },
9299 { 0, }
9300 },
9301 {
9302 /* fixed_bit_masks */
9303 0x800000007ff00000ULL,
9304 0xfff8000000000000ULL,
9305 0ULL,
9306 0ULL,
9307 0ULL
9308 },
9309 {
9310 /* fixed_bit_values */
9311 0x0000000049000000ULL,
9312 0x3498000000000000ULL,
9313 -1ULL,
9314 -1ULL,
9315 -1ULL
9316 }
9317 }, 1011 },
9318 { "slti_u", TILE_OPC_SLTI_U, 0xf /* pipes */, 3 /* num_operands */, 1012 { "slti.sn", TILE_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1,
9319 TREG_ZERO, /* implicitly_written_register */ 1013 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9320 1, /* can_bundle */
9321 {
9322 /* operands */
9323 { 7, 8, 0 },
9324 { 9, 10, 1 },
9325 { 11, 12, 2 },
9326 { 13, 14, 3 },
9327 { 0, }
9328 },
9329 {
9330 /* fixed_bit_masks */
9331 0x800000007ff00000ULL,
9332 0xfff8000000000000ULL,
9333 0x8000000078000000ULL,
9334 0xf800000000000000ULL,
9335 0ULL
9336 },
9337 {
9338 /* fixed_bit_values */
9339 0x0000000041100000ULL,
9340 0x30a0000000000000ULL,
9341 0x8000000078000000ULL,
9342 0xe800000000000000ULL,
9343 -1ULL
9344 }
9345 }, 1014 },
9346 { "slti_u.sn", TILE_OPC_SLTI_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 1015 { "slti_u", TILE_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1,
9347 TREG_SN, /* implicitly_written_register */ 1016 { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
9348 1, /* can_bundle */
9349 {
9350 /* operands */
9351 { 7, 8, 0 },
9352 { 9, 10, 1 },
9353 { 0, },
9354 { 0, },
9355 { 0, }
9356 },
9357 {
9358 /* fixed_bit_masks */
9359 0x800000007ff00000ULL,
9360 0xfff8000000000000ULL,
9361 0ULL,
9362 0ULL,
9363 0ULL
9364 },
9365 {
9366 /* fixed_bit_values */
9367 0x0000000049100000ULL,
9368 0x34a0000000000000ULL,
9369 -1ULL,
9370 -1ULL,
9371 -1ULL
9372 }
9373 }, 1017 },
9374 { "sltib", TILE_OPC_SLTIB, 0x3 /* pipes */, 3 /* num_operands */, 1018 { "slti_u.sn", TILE_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1,
9375 TREG_ZERO, /* implicitly_written_register */ 1019 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9376 1, /* can_bundle */
9377 {
9378 /* operands */
9379 { 7, 8, 0 },
9380 { 9, 10, 1 },
9381 { 0, },
9382 { 0, },
9383 { 0, }
9384 },
9385 {
9386 /* fixed_bit_masks */
9387 0x800000007ff00000ULL,
9388 0xfff8000000000000ULL,
9389 0ULL,
9390 0ULL,
9391 0ULL
9392 },
9393 {
9394 /* fixed_bit_values */
9395 0x0000000040c00000ULL,
9396 0x3078000000000000ULL,
9397 -1ULL,
9398 -1ULL,
9399 -1ULL
9400 }
9401 }, 1020 },
9402 { "sltib.sn", TILE_OPC_SLTIB_SN, 0x3 /* pipes */, 3 /* num_operands */, 1021 { "sltib", TILE_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1,
9403 TREG_SN, /* implicitly_written_register */ 1022 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9404 1, /* can_bundle */
9405 {
9406 /* operands */
9407 { 7, 8, 0 },
9408 { 9, 10, 1 },
9409 { 0, },
9410 { 0, },
9411 { 0, }
9412 },
9413 {
9414 /* fixed_bit_masks */
9415 0x800000007ff00000ULL,
9416 0xfff8000000000000ULL,
9417 0ULL,
9418 0ULL,
9419 0ULL
9420 },
9421 {
9422 /* fixed_bit_values */
9423 0x0000000048c00000ULL,
9424 0x3478000000000000ULL,
9425 -1ULL,
9426 -1ULL,
9427 -1ULL
9428 }
9429 }, 1023 },
9430 { "sltib_u", TILE_OPC_SLTIB_U, 0x3 /* pipes */, 3 /* num_operands */, 1024 { "sltib.sn", TILE_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1,
9431 TREG_ZERO, /* implicitly_written_register */ 1025 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9432 1, /* can_bundle */
9433 {
9434 /* operands */
9435 { 7, 8, 0 },
9436 { 9, 10, 1 },
9437 { 0, },
9438 { 0, },
9439 { 0, }
9440 },
9441 {
9442 /* fixed_bit_masks */
9443 0x800000007ff00000ULL,
9444 0xfff8000000000000ULL,
9445 0ULL,
9446 0ULL,
9447 0ULL
9448 },
9449 {
9450 /* fixed_bit_values */
9451 0x0000000040d00000ULL,
9452 0x3080000000000000ULL,
9453 -1ULL,
9454 -1ULL,
9455 -1ULL
9456 }
9457 }, 1026 },
9458 { "sltib_u.sn", TILE_OPC_SLTIB_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 1027 { "sltib_u", TILE_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1,
9459 TREG_SN, /* implicitly_written_register */ 1028 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9460 1, /* can_bundle */
9461 {
9462 /* operands */
9463 { 7, 8, 0 },
9464 { 9, 10, 1 },
9465 { 0, },
9466 { 0, },
9467 { 0, }
9468 },
9469 {
9470 /* fixed_bit_masks */
9471 0x800000007ff00000ULL,
9472 0xfff8000000000000ULL,
9473 0ULL,
9474 0ULL,
9475 0ULL
9476 },
9477 {
9478 /* fixed_bit_values */
9479 0x0000000048d00000ULL,
9480 0x3480000000000000ULL,
9481 -1ULL,
9482 -1ULL,
9483 -1ULL
9484 }
9485 }, 1029 },
9486 { "sltih", TILE_OPC_SLTIH, 0x3 /* pipes */, 3 /* num_operands */, 1030 { "sltib_u.sn", TILE_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1,
9487 TREG_ZERO, /* implicitly_written_register */ 1031 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9488 1, /* can_bundle */
9489 {
9490 /* operands */
9491 { 7, 8, 0 },
9492 { 9, 10, 1 },
9493 { 0, },
9494 { 0, },
9495 { 0, }
9496 },
9497 {
9498 /* fixed_bit_masks */
9499 0x800000007ff00000ULL,
9500 0xfff8000000000000ULL,
9501 0ULL,
9502 0ULL,
9503 0ULL
9504 },
9505 {
9506 /* fixed_bit_values */
9507 0x0000000040e00000ULL,
9508 0x3088000000000000ULL,
9509 -1ULL,
9510 -1ULL,
9511 -1ULL
9512 }
9513 }, 1032 },
9514 { "sltih.sn", TILE_OPC_SLTIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 1033 { "sltih", TILE_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1,
9515 TREG_SN, /* implicitly_written_register */ 1034 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9516 1, /* can_bundle */
9517 {
9518 /* operands */
9519 { 7, 8, 0 },
9520 { 9, 10, 1 },
9521 { 0, },
9522 { 0, },
9523 { 0, }
9524 },
9525 {
9526 /* fixed_bit_masks */
9527 0x800000007ff00000ULL,
9528 0xfff8000000000000ULL,
9529 0ULL,
9530 0ULL,
9531 0ULL
9532 },
9533 {
9534 /* fixed_bit_values */
9535 0x0000000048e00000ULL,
9536 0x3488000000000000ULL,
9537 -1ULL,
9538 -1ULL,
9539 -1ULL
9540 }
9541 }, 1035 },
9542 { "sltih_u", TILE_OPC_SLTIH_U, 0x3 /* pipes */, 3 /* num_operands */, 1036 { "sltih.sn", TILE_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1,
9543 TREG_ZERO, /* implicitly_written_register */ 1037 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9544 1, /* can_bundle */
9545 {
9546 /* operands */
9547 { 7, 8, 0 },
9548 { 9, 10, 1 },
9549 { 0, },
9550 { 0, },
9551 { 0, }
9552 },
9553 {
9554 /* fixed_bit_masks */
9555 0x800000007ff00000ULL,
9556 0xfff8000000000000ULL,
9557 0ULL,
9558 0ULL,
9559 0ULL
9560 },
9561 {
9562 /* fixed_bit_values */
9563 0x0000000040f00000ULL,
9564 0x3090000000000000ULL,
9565 -1ULL,
9566 -1ULL,
9567 -1ULL
9568 }
9569 }, 1038 },
9570 { "sltih_u.sn", TILE_OPC_SLTIH_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 1039 { "sltih_u", TILE_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1,
9571 TREG_SN, /* implicitly_written_register */ 1040 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9572 1, /* can_bundle */
9573 {
9574 /* operands */
9575 { 7, 8, 0 },
9576 { 9, 10, 1 },
9577 { 0, },
9578 { 0, },
9579 { 0, }
9580 },
9581 {
9582 /* fixed_bit_masks */
9583 0x800000007ff00000ULL,
9584 0xfff8000000000000ULL,
9585 0ULL,
9586 0ULL,
9587 0ULL
9588 },
9589 {
9590 /* fixed_bit_values */
9591 0x0000000048f00000ULL,
9592 0x3490000000000000ULL,
9593 -1ULL,
9594 -1ULL,
9595 -1ULL
9596 }
9597 }, 1041 },
9598 { "sne", TILE_OPC_SNE, 0xf /* pipes */, 3 /* num_operands */, 1042 { "sltih_u.sn", TILE_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1,
9599 TREG_ZERO, /* implicitly_written_register */ 1043 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
9600 1, /* can_bundle */
9601 {
9602 /* operands */
9603 { 7, 8, 16 },
9604 { 9, 10, 17 },
9605 { 11, 12, 18 },
9606 { 13, 14, 19 },
9607 { 0, }
9608 },
9609 {
9610 /* fixed_bit_masks */
9611 0x800000007ffc0000ULL,
9612 0xfffe000000000000ULL,
9613 0x80000000780c0000ULL,
9614 0xf806000000000000ULL,
9615 0ULL
9616 },
9617 {
9618 /* fixed_bit_values */
9619 0x00000000015c0000ULL,
9620 0x0872000000000000ULL,
9621 0x80000000300c0000ULL,
9622 0xb006000000000000ULL,
9623 -1ULL
9624 }
9625 }, 1044 },
9626 { "sne.sn", TILE_OPC_SNE_SN, 0x3 /* pipes */, 3 /* num_operands */, 1045 { "sne", TILE_OPC_SNE, 0xf, 3, TREG_ZERO, 1,
9627 TREG_SN, /* implicitly_written_register */ 1046 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
9628 1, /* can_bundle */
9629 {
9630 /* operands */
9631 { 7, 8, 16 },
9632 { 9, 10, 17 },
9633 { 0, },
9634 { 0, },
9635 { 0, }
9636 },
9637 {
9638 /* fixed_bit_masks */
9639 0x800000007ffc0000ULL,
9640 0xfffe000000000000ULL,
9641 0ULL,
9642 0ULL,
9643 0ULL
9644 },
9645 {
9646 /* fixed_bit_values */
9647 0x00000000095c0000ULL,
9648 0x0c72000000000000ULL,
9649 -1ULL,
9650 -1ULL,
9651 -1ULL
9652 }
9653 }, 1047 },
9654 { "sneb", TILE_OPC_SNEB, 0x3 /* pipes */, 3 /* num_operands */, 1048 { "sne.sn", TILE_OPC_SNE_SN, 0x3, 3, TREG_SN, 1,
9655 TREG_ZERO, /* implicitly_written_register */ 1049 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9656 1, /* can_bundle */
9657 {
9658 /* operands */
9659 { 7, 8, 16 },
9660 { 9, 10, 17 },
9661 { 0, },
9662 { 0, },
9663 { 0, }
9664 },
9665 {
9666 /* fixed_bit_masks */
9667 0x800000007ffc0000ULL,
9668 0xfffe000000000000ULL,
9669 0ULL,
9670 0ULL,
9671 0ULL
9672 },
9673 {
9674 /* fixed_bit_values */
9675 0x0000000001540000ULL,
9676 0x086e000000000000ULL,
9677 -1ULL,
9678 -1ULL,
9679 -1ULL
9680 }
9681 }, 1050 },
9682 { "sneb.sn", TILE_OPC_SNEB_SN, 0x3 /* pipes */, 3 /* num_operands */, 1051 { "sneb", TILE_OPC_SNEB, 0x3, 3, TREG_ZERO, 1,
9683 TREG_SN, /* implicitly_written_register */ 1052 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9684 1, /* can_bundle */
9685 {
9686 /* operands */
9687 { 7, 8, 16 },
9688 { 9, 10, 17 },
9689 { 0, },
9690 { 0, },
9691 { 0, }
9692 },
9693 {
9694 /* fixed_bit_masks */
9695 0x800000007ffc0000ULL,
9696 0xfffe000000000000ULL,
9697 0ULL,
9698 0ULL,
9699 0ULL
9700 },
9701 {
9702 /* fixed_bit_values */
9703 0x0000000009540000ULL,
9704 0x0c6e000000000000ULL,
9705 -1ULL,
9706 -1ULL,
9707 -1ULL
9708 }
9709 }, 1053 },
9710 { "sneh", TILE_OPC_SNEH, 0x3 /* pipes */, 3 /* num_operands */, 1054 { "sneb.sn", TILE_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1,
9711 TREG_ZERO, /* implicitly_written_register */ 1055 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9712 1, /* can_bundle */
9713 {
9714 /* operands */
9715 { 7, 8, 16 },
9716 { 9, 10, 17 },
9717 { 0, },
9718 { 0, },
9719 { 0, }
9720 },
9721 {
9722 /* fixed_bit_masks */
9723 0x800000007ffc0000ULL,
9724 0xfffe000000000000ULL,
9725 0ULL,
9726 0ULL,
9727 0ULL
9728 },
9729 {
9730 /* fixed_bit_values */
9731 0x0000000001580000ULL,
9732 0x0870000000000000ULL,
9733 -1ULL,
9734 -1ULL,
9735 -1ULL
9736 }
9737 }, 1056 },
9738 { "sneh.sn", TILE_OPC_SNEH_SN, 0x3 /* pipes */, 3 /* num_operands */, 1057 { "sneh", TILE_OPC_SNEH, 0x3, 3, TREG_ZERO, 1,
9739 TREG_SN, /* implicitly_written_register */ 1058 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9740 1, /* can_bundle */
9741 {
9742 /* operands */
9743 { 7, 8, 16 },
9744 { 9, 10, 17 },
9745 { 0, },
9746 { 0, },
9747 { 0, }
9748 },
9749 {
9750 /* fixed_bit_masks */
9751 0x800000007ffc0000ULL,
9752 0xfffe000000000000ULL,
9753 0ULL,
9754 0ULL,
9755 0ULL
9756 },
9757 {
9758 /* fixed_bit_values */
9759 0x0000000009580000ULL,
9760 0x0c70000000000000ULL,
9761 -1ULL,
9762 -1ULL,
9763 -1ULL
9764 }
9765 }, 1059 },
9766 { "sra", TILE_OPC_SRA, 0xf /* pipes */, 3 /* num_operands */, 1060 { "sneh.sn", TILE_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1,
9767 TREG_ZERO, /* implicitly_written_register */ 1061 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9768 1, /* can_bundle */
9769 {
9770 /* operands */
9771 { 7, 8, 16 },
9772 { 9, 10, 17 },
9773 { 11, 12, 18 },
9774 { 13, 14, 19 },
9775 { 0, }
9776 },
9777 {
9778 /* fixed_bit_masks */
9779 0x800000007ffc0000ULL,
9780 0xfffe000000000000ULL,
9781 0x80000000780c0000ULL,
9782 0xf806000000000000ULL,
9783 0ULL
9784 },
9785 {
9786 /* fixed_bit_values */
9787 0x0000000001680000ULL,
9788 0x0878000000000000ULL,
9789 0x80000000200c0000ULL,
9790 0xa006000000000000ULL,
9791 -1ULL
9792 }
9793 }, 1062 },
9794 { "sra.sn", TILE_OPC_SRA_SN, 0x3 /* pipes */, 3 /* num_operands */, 1063 { "sra", TILE_OPC_SRA, 0xf, 3, TREG_ZERO, 1,
9795 TREG_SN, /* implicitly_written_register */ 1064 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
9796 1, /* can_bundle */
9797 {
9798 /* operands */
9799 { 7, 8, 16 },
9800 { 9, 10, 17 },
9801 { 0, },
9802 { 0, },
9803 { 0, }
9804 },
9805 {
9806 /* fixed_bit_masks */
9807 0x800000007ffc0000ULL,
9808 0xfffe000000000000ULL,
9809 0ULL,
9810 0ULL,
9811 0ULL
9812 },
9813 {
9814 /* fixed_bit_values */
9815 0x0000000009680000ULL,
9816 0x0c78000000000000ULL,
9817 -1ULL,
9818 -1ULL,
9819 -1ULL
9820 }
9821 }, 1065 },
9822 { "srab", TILE_OPC_SRAB, 0x3 /* pipes */, 3 /* num_operands */, 1066 { "sra.sn", TILE_OPC_SRA_SN, 0x3, 3, TREG_SN, 1,
9823 TREG_ZERO, /* implicitly_written_register */ 1067 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9824 1, /* can_bundle */
9825 {
9826 /* operands */
9827 { 7, 8, 16 },
9828 { 9, 10, 17 },
9829 { 0, },
9830 { 0, },
9831 { 0, }
9832 },
9833 {
9834 /* fixed_bit_masks */
9835 0x800000007ffc0000ULL,
9836 0xfffe000000000000ULL,
9837 0ULL,
9838 0ULL,
9839 0ULL
9840 },
9841 {
9842 /* fixed_bit_values */
9843 0x0000000001600000ULL,
9844 0x0874000000000000ULL,
9845 -1ULL,
9846 -1ULL,
9847 -1ULL
9848 }
9849 }, 1068 },
9850 { "srab.sn", TILE_OPC_SRAB_SN, 0x3 /* pipes */, 3 /* num_operands */, 1069 { "srab", TILE_OPC_SRAB, 0x3, 3, TREG_ZERO, 1,
9851 TREG_SN, /* implicitly_written_register */ 1070 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9852 1, /* can_bundle */
9853 {
9854 /* operands */
9855 { 7, 8, 16 },
9856 { 9, 10, 17 },
9857 { 0, },
9858 { 0, },
9859 { 0, }
9860 },
9861 {
9862 /* fixed_bit_masks */
9863 0x800000007ffc0000ULL,
9864 0xfffe000000000000ULL,
9865 0ULL,
9866 0ULL,
9867 0ULL
9868 },
9869 {
9870 /* fixed_bit_values */
9871 0x0000000009600000ULL,
9872 0x0c74000000000000ULL,
9873 -1ULL,
9874 -1ULL,
9875 -1ULL
9876 }
9877 }, 1071 },
9878 { "srah", TILE_OPC_SRAH, 0x3 /* pipes */, 3 /* num_operands */, 1072 { "srab.sn", TILE_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1,
9879 TREG_ZERO, /* implicitly_written_register */ 1073 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9880 1, /* can_bundle */
9881 {
9882 /* operands */
9883 { 7, 8, 16 },
9884 { 9, 10, 17 },
9885 { 0, },
9886 { 0, },
9887 { 0, }
9888 },
9889 {
9890 /* fixed_bit_masks */
9891 0x800000007ffc0000ULL,
9892 0xfffe000000000000ULL,
9893 0ULL,
9894 0ULL,
9895 0ULL
9896 },
9897 {
9898 /* fixed_bit_values */
9899 0x0000000001640000ULL,
9900 0x0876000000000000ULL,
9901 -1ULL,
9902 -1ULL,
9903 -1ULL
9904 }
9905 }, 1074 },
9906 { "srah.sn", TILE_OPC_SRAH_SN, 0x3 /* pipes */, 3 /* num_operands */, 1075 { "srah", TILE_OPC_SRAH, 0x3, 3, TREG_ZERO, 1,
9907 TREG_SN, /* implicitly_written_register */ 1076 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9908 1, /* can_bundle */
9909 {
9910 /* operands */
9911 { 7, 8, 16 },
9912 { 9, 10, 17 },
9913 { 0, },
9914 { 0, },
9915 { 0, }
9916 },
9917 {
9918 /* fixed_bit_masks */
9919 0x800000007ffc0000ULL,
9920 0xfffe000000000000ULL,
9921 0ULL,
9922 0ULL,
9923 0ULL
9924 },
9925 {
9926 /* fixed_bit_values */
9927 0x0000000009640000ULL,
9928 0x0c76000000000000ULL,
9929 -1ULL,
9930 -1ULL,
9931 -1ULL
9932 }
9933 }, 1077 },
9934 { "srai", TILE_OPC_SRAI, 0xf /* pipes */, 3 /* num_operands */, 1078 { "srah.sn", TILE_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1,
9935 TREG_ZERO, /* implicitly_written_register */ 1079 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
9936 1, /* can_bundle */
9937 {
9938 /* operands */
9939 { 7, 8, 32 },
9940 { 9, 10, 33 },
9941 { 11, 12, 34 },
9942 { 13, 14, 35 },
9943 { 0, }
9944 },
9945 {
9946 /* fixed_bit_masks */
9947 0x800000007ffe0000ULL,
9948 0xffff000000000000ULL,
9949 0x80000000780e0000ULL,
9950 0xf807000000000000ULL,
9951 0ULL
9952 },
9953 {
9954 /* fixed_bit_values */
9955 0x0000000070140000ULL,
9956 0x400a000000000000ULL,
9957 0x8000000068080000ULL,
9958 0xd804000000000000ULL,
9959 -1ULL
9960 }
9961 }, 1080 },
9962 { "srai.sn", TILE_OPC_SRAI_SN, 0x3 /* pipes */, 3 /* num_operands */, 1081 { "srai", TILE_OPC_SRAI, 0xf, 3, TREG_ZERO, 1,
9963 TREG_SN, /* implicitly_written_register */ 1082 { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
9964 1, /* can_bundle */
9965 {
9966 /* operands */
9967 { 7, 8, 32 },
9968 { 9, 10, 33 },
9969 { 0, },
9970 { 0, },
9971 { 0, }
9972 },
9973 {
9974 /* fixed_bit_masks */
9975 0x800000007ffe0000ULL,
9976 0xffff000000000000ULL,
9977 0ULL,
9978 0ULL,
9979 0ULL
9980 },
9981 {
9982 /* fixed_bit_values */
9983 0x0000000078140000ULL,
9984 0x440a000000000000ULL,
9985 -1ULL,
9986 -1ULL,
9987 -1ULL
9988 }
9989 }, 1083 },
9990 { "sraib", TILE_OPC_SRAIB, 0x3 /* pipes */, 3 /* num_operands */, 1084 { "srai.sn", TILE_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1,
9991 TREG_ZERO, /* implicitly_written_register */ 1085 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
9992 1, /* can_bundle */
9993 {
9994 /* operands */
9995 { 7, 8, 32 },
9996 { 9, 10, 33 },
9997 { 0, },
9998 { 0, },
9999 { 0, }
10000 },
10001 {
10002 /* fixed_bit_masks */
10003 0x800000007ffe0000ULL,
10004 0xffff000000000000ULL,
10005 0ULL,
10006 0ULL,
10007 0ULL
10008 },
10009 {
10010 /* fixed_bit_values */
10011 0x0000000070100000ULL,
10012 0x4008000000000000ULL,
10013 -1ULL,
10014 -1ULL,
10015 -1ULL
10016 }
10017 }, 1086 },
10018 { "sraib.sn", TILE_OPC_SRAIB_SN, 0x3 /* pipes */, 3 /* num_operands */, 1087 { "sraib", TILE_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1,
10019 TREG_SN, /* implicitly_written_register */ 1088 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
10020 1, /* can_bundle */
10021 {
10022 /* operands */
10023 { 7, 8, 32 },
10024 { 9, 10, 33 },
10025 { 0, },
10026 { 0, },
10027 { 0, }
10028 },
10029 {
10030 /* fixed_bit_masks */
10031 0x800000007ffe0000ULL,
10032 0xffff000000000000ULL,
10033 0ULL,
10034 0ULL,
10035 0ULL
10036 },
10037 {
10038 /* fixed_bit_values */
10039 0x0000000078100000ULL,
10040 0x4408000000000000ULL,
10041 -1ULL,
10042 -1ULL,
10043 -1ULL
10044 }
10045 }, 1089 },
10046 { "sraih", TILE_OPC_SRAIH, 0x3 /* pipes */, 3 /* num_operands */, 1090 { "sraib.sn", TILE_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1,
10047 TREG_ZERO, /* implicitly_written_register */ 1091 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
10048 1, /* can_bundle */
10049 {
10050 /* operands */
10051 { 7, 8, 32 },
10052 { 9, 10, 33 },
10053 { 0, },
10054 { 0, },
10055 { 0, }
10056 },
10057 {
10058 /* fixed_bit_masks */
10059 0x800000007ffe0000ULL,
10060 0xffff000000000000ULL,
10061 0ULL,
10062 0ULL,
10063 0ULL
10064 },
10065 {
10066 /* fixed_bit_values */
10067 0x0000000070120000ULL,
10068 0x4009000000000000ULL,
10069 -1ULL,
10070 -1ULL,
10071 -1ULL
10072 }
10073 }, 1092 },
10074 { "sraih.sn", TILE_OPC_SRAIH_SN, 0x3 /* pipes */, 3 /* num_operands */, 1093 { "sraih", TILE_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1,
10075 TREG_SN, /* implicitly_written_register */ 1094 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
10076 1, /* can_bundle */
10077 {
10078 /* operands */
10079 { 7, 8, 32 },
10080 { 9, 10, 33 },
10081 { 0, },
10082 { 0, },
10083 { 0, }
10084 },
10085 {
10086 /* fixed_bit_masks */
10087 0x800000007ffe0000ULL,
10088 0xffff000000000000ULL,
10089 0ULL,
10090 0ULL,
10091 0ULL
10092 },
10093 {
10094 /* fixed_bit_values */
10095 0x0000000078120000ULL,
10096 0x4409000000000000ULL,
10097 -1ULL,
10098 -1ULL,
10099 -1ULL
10100 }
10101 }, 1095 },
10102 { "sub", TILE_OPC_SUB, 0xf /* pipes */, 3 /* num_operands */, 1096 { "sraih.sn", TILE_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1,
10103 TREG_ZERO, /* implicitly_written_register */ 1097 { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
10104 1, /* can_bundle */
10105 {
10106 /* operands */
10107 { 7, 8, 16 },
10108 { 9, 10, 17 },
10109 { 11, 12, 18 },
10110 { 13, 14, 19 },
10111 { 0, }
10112 },
10113 {
10114 /* fixed_bit_masks */
10115 0x800000007ffc0000ULL,
10116 0xfffe000000000000ULL,
10117 0x80000000780c0000ULL,
10118 0xf806000000000000ULL,
10119 0ULL
10120 },
10121 {
10122 /* fixed_bit_values */
10123 0x0000000001740000ULL,
10124 0x087e000000000000ULL,
10125 0x80000000080c0000ULL,
10126 0x8806000000000000ULL,
10127 -1ULL
10128 }
10129 }, 1098 },
10130 { "sub.sn", TILE_OPC_SUB_SN, 0x3 /* pipes */, 3 /* num_operands */, 1099 { "sub", TILE_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
10131 TREG_SN, /* implicitly_written_register */ 1100 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
10132 1, /* can_bundle */
10133 {
10134 /* operands */
10135 { 7, 8, 16 },
10136 { 9, 10, 17 },
10137 { 0, },
10138 { 0, },
10139 { 0, }
10140 },
10141 {
10142 /* fixed_bit_masks */
10143 0x800000007ffc0000ULL,
10144 0xfffe000000000000ULL,
10145 0ULL,
10146 0ULL,
10147 0ULL
10148 },
10149 {
10150 /* fixed_bit_values */
10151 0x0000000009740000ULL,
10152 0x0c7e000000000000ULL,
10153 -1ULL,
10154 -1ULL,
10155 -1ULL
10156 }
10157 }, 1101 },
10158 { "subb", TILE_OPC_SUBB, 0x3 /* pipes */, 3 /* num_operands */, 1102 { "sub.sn", TILE_OPC_SUB_SN, 0x3, 3, TREG_SN, 1,
10159 TREG_ZERO, /* implicitly_written_register */ 1103 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10160 1, /* can_bundle */
10161 {
10162 /* operands */
10163 { 7, 8, 16 },
10164 { 9, 10, 17 },
10165 { 0, },
10166 { 0, },
10167 { 0, }
10168 },
10169 {
10170 /* fixed_bit_masks */
10171 0x800000007ffc0000ULL,
10172 0xfffe000000000000ULL,
10173 0ULL,
10174 0ULL,
10175 0ULL
10176 },
10177 {
10178 /* fixed_bit_values */
10179 0x00000000016c0000ULL,
10180 0x087a000000000000ULL,
10181 -1ULL,
10182 -1ULL,
10183 -1ULL
10184 }
10185 }, 1104 },
10186 { "subb.sn", TILE_OPC_SUBB_SN, 0x3 /* pipes */, 3 /* num_operands */, 1105 { "subb", TILE_OPC_SUBB, 0x3, 3, TREG_ZERO, 1,
10187 TREG_SN, /* implicitly_written_register */ 1106 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10188 1, /* can_bundle */
10189 {
10190 /* operands */
10191 { 7, 8, 16 },
10192 { 9, 10, 17 },
10193 { 0, },
10194 { 0, },
10195 { 0, }
10196 },
10197 {
10198 /* fixed_bit_masks */
10199 0x800000007ffc0000ULL,
10200 0xfffe000000000000ULL,
10201 0ULL,
10202 0ULL,
10203 0ULL
10204 },
10205 {
10206 /* fixed_bit_values */
10207 0x00000000096c0000ULL,
10208 0x0c7a000000000000ULL,
10209 -1ULL,
10210 -1ULL,
10211 -1ULL
10212 }
10213 }, 1107 },
10214 { "subbs_u", TILE_OPC_SUBBS_U, 0x3 /* pipes */, 3 /* num_operands */, 1108 { "subb.sn", TILE_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1,
10215 TREG_ZERO, /* implicitly_written_register */ 1109 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10216 1, /* can_bundle */
10217 {
10218 /* operands */
10219 { 7, 8, 16 },
10220 { 9, 10, 17 },
10221 { 0, },
10222 { 0, },
10223 { 0, }
10224 },
10225 {
10226 /* fixed_bit_masks */
10227 0x800000007ffc0000ULL,
10228 0xfffe000000000000ULL,
10229 0ULL,
10230 0ULL,
10231 0ULL
10232 },
10233 {
10234 /* fixed_bit_values */
10235 0x0000000001900000ULL,
10236 0x088c000000000000ULL,
10237 -1ULL,
10238 -1ULL,
10239 -1ULL
10240 }
10241 }, 1110 },
10242 { "subbs_u.sn", TILE_OPC_SUBBS_U_SN, 0x3 /* pipes */, 3 /* num_operands */, 1111 { "subbs_u", TILE_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1,
10243 TREG_SN, /* implicitly_written_register */ 1112 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10244 1, /* can_bundle */
10245 {
10246 /* operands */
10247 { 7, 8, 16 },
10248 { 9, 10, 17 },
10249 { 0, },
10250 { 0, },
10251 { 0, }
10252 },
10253 {
10254 /* fixed_bit_masks */
10255 0x800000007ffc0000ULL,
10256 0xfffe000000000000ULL,
10257 0ULL,
10258 0ULL,
10259 0ULL
10260 },
10261 {
10262 /* fixed_bit_values */
10263 0x0000000009900000ULL,
10264 0x0c8c000000000000ULL,
10265 -1ULL,
10266 -1ULL,
10267 -1ULL
10268 }
10269 }, 1113 },
10270 { "subh", TILE_OPC_SUBH, 0x3 /* pipes */, 3 /* num_operands */, 1114 { "subbs_u.sn", TILE_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1,
10271 TREG_ZERO, /* implicitly_written_register */ 1115 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10272 1, /* can_bundle */
10273 {
10274 /* operands */
10275 { 7, 8, 16 },
10276 { 9, 10, 17 },
10277 { 0, },
10278 { 0, },
10279 { 0, }
10280 },
10281 {
10282 /* fixed_bit_masks */
10283 0x800000007ffc0000ULL,
10284 0xfffe000000000000ULL,
10285 0ULL,
10286 0ULL,
10287 0ULL
10288 },
10289 {
10290 /* fixed_bit_values */
10291 0x0000000001700000ULL,
10292 0x087c000000000000ULL,
10293 -1ULL,
10294 -1ULL,
10295 -1ULL
10296 }
10297 }, 1116 },
10298 { "subh.sn", TILE_OPC_SUBH_SN, 0x3 /* pipes */, 3 /* num_operands */, 1117 { "subh", TILE_OPC_SUBH, 0x3, 3, TREG_ZERO, 1,
10299 TREG_SN, /* implicitly_written_register */ 1118 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10300 1, /* can_bundle */
10301 {
10302 /* operands */
10303 { 7, 8, 16 },
10304 { 9, 10, 17 },
10305 { 0, },
10306 { 0, },
10307 { 0, }
10308 },
10309 {
10310 /* fixed_bit_masks */
10311 0x800000007ffc0000ULL,
10312 0xfffe000000000000ULL,
10313 0ULL,
10314 0ULL,
10315 0ULL
10316 },
10317 {
10318 /* fixed_bit_values */
10319 0x0000000009700000ULL,
10320 0x0c7c000000000000ULL,
10321 -1ULL,
10322 -1ULL,
10323 -1ULL
10324 }
10325 }, 1119 },
10326 { "subhs", TILE_OPC_SUBHS, 0x3 /* pipes */, 3 /* num_operands */, 1120 { "subh.sn", TILE_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1,
10327 TREG_ZERO, /* implicitly_written_register */ 1121 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10328 1, /* can_bundle */
10329 {
10330 /* operands */
10331 { 7, 8, 16 },
10332 { 9, 10, 17 },
10333 { 0, },
10334 { 0, },
10335 { 0, }
10336 },
10337 {
10338 /* fixed_bit_masks */
10339 0x800000007ffc0000ULL,
10340 0xfffe000000000000ULL,
10341 0ULL,
10342 0ULL,
10343 0ULL
10344 },
10345 {
10346 /* fixed_bit_values */
10347 0x0000000001940000ULL,
10348 0x088e000000000000ULL,
10349 -1ULL,
10350 -1ULL,
10351 -1ULL
10352 }
10353 }, 1122 },
10354 { "subhs.sn", TILE_OPC_SUBHS_SN, 0x3 /* pipes */, 3 /* num_operands */, 1123 { "subhs", TILE_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1,
10355 TREG_SN, /* implicitly_written_register */ 1124 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10356 1, /* can_bundle */
10357 {
10358 /* operands */
10359 { 7, 8, 16 },
10360 { 9, 10, 17 },
10361 { 0, },
10362 { 0, },
10363 { 0, }
10364 },
10365 {
10366 /* fixed_bit_masks */
10367 0x800000007ffc0000ULL,
10368 0xfffe000000000000ULL,
10369 0ULL,
10370 0ULL,
10371 0ULL
10372 },
10373 {
10374 /* fixed_bit_values */
10375 0x0000000009940000ULL,
10376 0x0c8e000000000000ULL,
10377 -1ULL,
10378 -1ULL,
10379 -1ULL
10380 }
10381 }, 1125 },
10382 { "subs", TILE_OPC_SUBS, 0x3 /* pipes */, 3 /* num_operands */, 1126 { "subhs.sn", TILE_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1,
10383 TREG_ZERO, /* implicitly_written_register */ 1127 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10384 1, /* can_bundle */
10385 {
10386 /* operands */
10387 { 7, 8, 16 },
10388 { 9, 10, 17 },
10389 { 0, },
10390 { 0, },
10391 { 0, }
10392 },
10393 {
10394 /* fixed_bit_masks */
10395 0x800000007ffc0000ULL,
10396 0xfffe000000000000ULL,
10397 0ULL,
10398 0ULL,
10399 0ULL
10400 },
10401 {
10402 /* fixed_bit_values */
10403 0x0000000001840000ULL,
10404 0x0886000000000000ULL,
10405 -1ULL,
10406 -1ULL,
10407 -1ULL
10408 }
10409 }, 1128 },
10410 { "subs.sn", TILE_OPC_SUBS_SN, 0x3 /* pipes */, 3 /* num_operands */, 1129 { "subs", TILE_OPC_SUBS, 0x3, 3, TREG_ZERO, 1,
10411 TREG_SN, /* implicitly_written_register */ 1130 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10412 1, /* can_bundle */
10413 {
10414 /* operands */
10415 { 7, 8, 16 },
10416 { 9, 10, 17 },
10417 { 0, },
10418 { 0, },
10419 { 0, }
10420 },
10421 {
10422 /* fixed_bit_masks */
10423 0x800000007ffc0000ULL,
10424 0xfffe000000000000ULL,
10425 0ULL,
10426 0ULL,
10427 0ULL
10428 },
10429 {
10430 /* fixed_bit_values */
10431 0x0000000009840000ULL,
10432 0x0c86000000000000ULL,
10433 -1ULL,
10434 -1ULL,
10435 -1ULL
10436 }
10437 }, 1131 },
10438 { "sw", TILE_OPC_SW, 0x12 /* pipes */, 2 /* num_operands */, 1132 { "subs.sn", TILE_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1,
10439 TREG_ZERO, /* implicitly_written_register */ 1133 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10440 1, /* can_bundle */
10441 {
10442 /* operands */
10443 { 0, },
10444 { 10, 17 },
10445 { 0, },
10446 { 0, },
10447 { 15, 36 }
10448 },
10449 {
10450 /* fixed_bit_masks */
10451 0ULL,
10452 0xfbfe000000000000ULL,
10453 0ULL,
10454 0ULL,
10455 0x8700000000000000ULL
10456 },
10457 {
10458 /* fixed_bit_values */
10459 -1ULL,
10460 0x0880000000000000ULL,
10461 -1ULL,
10462 -1ULL,
10463 0x8700000000000000ULL
10464 }
10465 }, 1134 },
10466 { "swadd", TILE_OPC_SWADD, 0x2 /* pipes */, 3 /* num_operands */, 1135 { "sw", TILE_OPC_SW, 0x12, 2, TREG_ZERO, 1,
10467 TREG_ZERO, /* implicitly_written_register */ 1136 { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
10468 1, /* can_bundle */
10469 {
10470 /* operands */
10471 { 0, },
10472 { 24, 17, 37 },
10473 { 0, },
10474 { 0, },
10475 { 0, }
10476 },
10477 {
10478 /* fixed_bit_masks */
10479 0ULL,
10480 0xfbf8000000000000ULL,
10481 0ULL,
10482 0ULL,
10483 0ULL
10484 },
10485 {
10486 /* fixed_bit_values */
10487 -1ULL,
10488 0x30f0000000000000ULL,
10489 -1ULL,
10490 -1ULL,
10491 -1ULL
10492 }
10493 }, 1137 },
10494 { "swint0", TILE_OPC_SWINT0, 0x2 /* pipes */, 0 /* num_operands */, 1138 { "swadd", TILE_OPC_SWADD, 0x2, 3, TREG_ZERO, 1,
10495 TREG_ZERO, /* implicitly_written_register */ 1139 { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } },
10496 0, /* can_bundle */
10497 {
10498 /* operands */
10499 { 0, },
10500 { },
10501 { 0, },
10502 { 0, },
10503 { 0, }
10504 },
10505 {
10506 /* fixed_bit_masks */
10507 0ULL,
10508 0xfbfff80000000000ULL,
10509 0ULL,
10510 0ULL,
10511 0ULL
10512 },
10513 {
10514 /* fixed_bit_values */
10515 -1ULL,
10516 0x400b900000000000ULL,
10517 -1ULL,
10518 -1ULL,
10519 -1ULL
10520 }
10521 }, 1140 },
10522 { "swint1", TILE_OPC_SWINT1, 0x2 /* pipes */, 0 /* num_operands */, 1141 { "swint0", TILE_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
10523 TREG_ZERO, /* implicitly_written_register */ 1142 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
10524 0, /* can_bundle */
10525 {
10526 /* operands */
10527 { 0, },
10528 { },
10529 { 0, },
10530 { 0, },
10531 { 0, }
10532 },
10533 {
10534 /* fixed_bit_masks */
10535 0ULL,
10536 0xfbfff80000000000ULL,
10537 0ULL,
10538 0ULL,
10539 0ULL
10540 },
10541 {
10542 /* fixed_bit_values */
10543 -1ULL,
10544 0x400b980000000000ULL,
10545 -1ULL,
10546 -1ULL,
10547 -1ULL
10548 }
10549 }, 1143 },
10550 { "swint2", TILE_OPC_SWINT2, 0x2 /* pipes */, 0 /* num_operands */, 1144 { "swint1", TILE_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
10551 TREG_ZERO, /* implicitly_written_register */ 1145 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
10552 0, /* can_bundle */
10553 {
10554 /* operands */
10555 { 0, },
10556 { },
10557 { 0, },
10558 { 0, },
10559 { 0, }
10560 },
10561 {
10562 /* fixed_bit_masks */
10563 0ULL,
10564 0xfbfff80000000000ULL,
10565 0ULL,
10566 0ULL,
10567 0ULL
10568 },
10569 {
10570 /* fixed_bit_values */
10571 -1ULL,
10572 0x400ba00000000000ULL,
10573 -1ULL,
10574 -1ULL,
10575 -1ULL
10576 }
10577 }, 1146 },
10578 { "swint3", TILE_OPC_SWINT3, 0x2 /* pipes */, 0 /* num_operands */, 1147 { "swint2", TILE_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
10579 TREG_ZERO, /* implicitly_written_register */ 1148 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
10580 0, /* can_bundle */
10581 {
10582 /* operands */
10583 { 0, },
10584 { },
10585 { 0, },
10586 { 0, },
10587 { 0, }
10588 },
10589 {
10590 /* fixed_bit_masks */
10591 0ULL,
10592 0xfbfff80000000000ULL,
10593 0ULL,
10594 0ULL,
10595 0ULL
10596 },
10597 {
10598 /* fixed_bit_values */
10599 -1ULL,
10600 0x400ba80000000000ULL,
10601 -1ULL,
10602 -1ULL,
10603 -1ULL
10604 }
10605 }, 1149 },
10606 { "tblidxb0", TILE_OPC_TBLIDXB0, 0x5 /* pipes */, 2 /* num_operands */, 1150 { "swint3", TILE_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
10607 TREG_ZERO, /* implicitly_written_register */ 1151 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
10608 1, /* can_bundle */
10609 {
10610 /* operands */
10611 { 21, 8 },
10612 { 0, },
10613 { 31, 12 },
10614 { 0, },
10615 { 0, }
10616 },
10617 {
10618 /* fixed_bit_masks */
10619 0x800000007ffff000ULL,
10620 0ULL,
10621 0x80000000780ff000ULL,
10622 0ULL,
10623 0ULL
10624 },
10625 {
10626 /* fixed_bit_values */
10627 0x0000000070168000ULL,
10628 -1ULL,
10629 0x80000000680a8000ULL,
10630 -1ULL,
10631 -1ULL
10632 }
10633 }, 1152 },
10634 { "tblidxb0.sn", TILE_OPC_TBLIDXB0_SN, 0x1 /* pipes */, 2 /* num_operands */, 1153 { "tblidxb0", TILE_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
10635 TREG_SN, /* implicitly_written_register */ 1154 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
10636 1, /* can_bundle */
10637 {
10638 /* operands */
10639 { 21, 8 },
10640 { 0, },
10641 { 0, },
10642 { 0, },
10643 { 0, }
10644 },
10645 {
10646 /* fixed_bit_masks */
10647 0x800000007ffff000ULL,
10648 0ULL,
10649 0ULL,
10650 0ULL,
10651 0ULL
10652 },
10653 {
10654 /* fixed_bit_values */
10655 0x0000000078168000ULL,
10656 -1ULL,
10657 -1ULL,
10658 -1ULL,
10659 -1ULL
10660 }
10661 }, 1155 },
10662 { "tblidxb1", TILE_OPC_TBLIDXB1, 0x5 /* pipes */, 2 /* num_operands */, 1156 { "tblidxb0.sn", TILE_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1,
10663 TREG_ZERO, /* implicitly_written_register */ 1157 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
10664 1, /* can_bundle */
10665 {
10666 /* operands */
10667 { 21, 8 },
10668 { 0, },
10669 { 31, 12 },
10670 { 0, },
10671 { 0, }
10672 },
10673 {
10674 /* fixed_bit_masks */
10675 0x800000007ffff000ULL,
10676 0ULL,
10677 0x80000000780ff000ULL,
10678 0ULL,
10679 0ULL
10680 },
10681 {
10682 /* fixed_bit_values */
10683 0x0000000070169000ULL,
10684 -1ULL,
10685 0x80000000680a9000ULL,
10686 -1ULL,
10687 -1ULL
10688 }
10689 }, 1158 },
10690 { "tblidxb1.sn", TILE_OPC_TBLIDXB1_SN, 0x1 /* pipes */, 2 /* num_operands */, 1159 { "tblidxb1", TILE_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
10691 TREG_SN, /* implicitly_written_register */ 1160 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
10692 1, /* can_bundle */
10693 {
10694 /* operands */
10695 { 21, 8 },
10696 { 0, },
10697 { 0, },
10698 { 0, },
10699 { 0, }
10700 },
10701 {
10702 /* fixed_bit_masks */
10703 0x800000007ffff000ULL,
10704 0ULL,
10705 0ULL,
10706 0ULL,
10707 0ULL
10708 },
10709 {
10710 /* fixed_bit_values */
10711 0x0000000078169000ULL,
10712 -1ULL,
10713 -1ULL,
10714 -1ULL,
10715 -1ULL
10716 }
10717 }, 1161 },
10718 { "tblidxb2", TILE_OPC_TBLIDXB2, 0x5 /* pipes */, 2 /* num_operands */, 1162 { "tblidxb1.sn", TILE_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1,
10719 TREG_ZERO, /* implicitly_written_register */ 1163 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
10720 1, /* can_bundle */
10721 {
10722 /* operands */
10723 { 21, 8 },
10724 { 0, },
10725 { 31, 12 },
10726 { 0, },
10727 { 0, }
10728 },
10729 {
10730 /* fixed_bit_masks */
10731 0x800000007ffff000ULL,
10732 0ULL,
10733 0x80000000780ff000ULL,
10734 0ULL,
10735 0ULL
10736 },
10737 {
10738 /* fixed_bit_values */
10739 0x000000007016a000ULL,
10740 -1ULL,
10741 0x80000000680aa000ULL,
10742 -1ULL,
10743 -1ULL
10744 }
10745 }, 1164 },
10746 { "tblidxb2.sn", TILE_OPC_TBLIDXB2_SN, 0x1 /* pipes */, 2 /* num_operands */, 1165 { "tblidxb2", TILE_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
10747 TREG_SN, /* implicitly_written_register */ 1166 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
10748 1, /* can_bundle */
10749 {
10750 /* operands */
10751 { 21, 8 },
10752 { 0, },
10753 { 0, },
10754 { 0, },
10755 { 0, }
10756 },
10757 {
10758 /* fixed_bit_masks */
10759 0x800000007ffff000ULL,
10760 0ULL,
10761 0ULL,
10762 0ULL,
10763 0ULL
10764 },
10765 {
10766 /* fixed_bit_values */
10767 0x000000007816a000ULL,
10768 -1ULL,
10769 -1ULL,
10770 -1ULL,
10771 -1ULL
10772 }
10773 }, 1167 },
10774 { "tblidxb3", TILE_OPC_TBLIDXB3, 0x5 /* pipes */, 2 /* num_operands */, 1168 { "tblidxb2.sn", TILE_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1,
10775 TREG_ZERO, /* implicitly_written_register */ 1169 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
10776 1, /* can_bundle */
10777 {
10778 /* operands */
10779 { 21, 8 },
10780 { 0, },
10781 { 31, 12 },
10782 { 0, },
10783 { 0, }
10784 },
10785 {
10786 /* fixed_bit_masks */
10787 0x800000007ffff000ULL,
10788 0ULL,
10789 0x80000000780ff000ULL,
10790 0ULL,
10791 0ULL
10792 },
10793 {
10794 /* fixed_bit_values */
10795 0x000000007016b000ULL,
10796 -1ULL,
10797 0x80000000680ab000ULL,
10798 -1ULL,
10799 -1ULL
10800 }
10801 }, 1170 },
10802 { "tblidxb3.sn", TILE_OPC_TBLIDXB3_SN, 0x1 /* pipes */, 2 /* num_operands */, 1171 { "tblidxb3", TILE_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
10803 TREG_SN, /* implicitly_written_register */ 1172 { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
10804 1, /* can_bundle */
10805 {
10806 /* operands */
10807 { 21, 8 },
10808 { 0, },
10809 { 0, },
10810 { 0, },
10811 { 0, }
10812 },
10813 {
10814 /* fixed_bit_masks */
10815 0x800000007ffff000ULL,
10816 0ULL,
10817 0ULL,
10818 0ULL,
10819 0ULL
10820 },
10821 {
10822 /* fixed_bit_values */
10823 0x000000007816b000ULL,
10824 -1ULL,
10825 -1ULL,
10826 -1ULL,
10827 -1ULL
10828 }
10829 }, 1173 },
10830 { "tns", TILE_OPC_TNS, 0x2 /* pipes */, 2 /* num_operands */, 1174 { "tblidxb3.sn", TILE_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1,
10831 TREG_ZERO, /* implicitly_written_register */ 1175 { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
10832 1, /* can_bundle */
10833 {
10834 /* operands */
10835 { 0, },
10836 { 9, 10 },
10837 { 0, },
10838 { 0, },
10839 { 0, }
10840 },
10841 {
10842 /* fixed_bit_masks */
10843 0ULL,
10844 0xfffff80000000000ULL,
10845 0ULL,
10846 0ULL,
10847 0ULL
10848 },
10849 {
10850 /* fixed_bit_values */
10851 -1ULL,
10852 0x400bb00000000000ULL,
10853 -1ULL,
10854 -1ULL,
10855 -1ULL
10856 }
10857 }, 1176 },
10858 { "tns.sn", TILE_OPC_TNS_SN, 0x2 /* pipes */, 2 /* num_operands */, 1177 { "tns", TILE_OPC_TNS, 0x2, 2, TREG_ZERO, 1,
10859 TREG_SN, /* implicitly_written_register */ 1178 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
10860 1, /* can_bundle */
10861 {
10862 /* operands */
10863 { 0, },
10864 { 9, 10 },
10865 { 0, },
10866 { 0, },
10867 { 0, }
10868 },
10869 {
10870 /* fixed_bit_masks */
10871 0ULL,
10872 0xfffff80000000000ULL,
10873 0ULL,
10874 0ULL,
10875 0ULL
10876 },
10877 {
10878 /* fixed_bit_values */
10879 -1ULL,
10880 0x440bb00000000000ULL,
10881 -1ULL,
10882 -1ULL,
10883 -1ULL
10884 }
10885 }, 1179 },
10886 { "wh64", TILE_OPC_WH64, 0x2 /* pipes */, 1 /* num_operands */, 1180 { "tns.sn", TILE_OPC_TNS_SN, 0x2, 2, TREG_SN, 1,
10887 TREG_ZERO, /* implicitly_written_register */ 1181 { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
10888 1, /* can_bundle */
10889 {
10890 /* operands */
10891 { 0, },
10892 { 10 },
10893 { 0, },
10894 { 0, },
10895 { 0, }
10896 },
10897 {
10898 /* fixed_bit_masks */
10899 0ULL,
10900 0xfbfff80000000000ULL,
10901 0ULL,
10902 0ULL,
10903 0ULL
10904 },
10905 {
10906 /* fixed_bit_values */
10907 -1ULL,
10908 0x400bb80000000000ULL,
10909 -1ULL,
10910 -1ULL,
10911 -1ULL
10912 }
10913 }, 1182 },
10914 { "xor", TILE_OPC_XOR, 0xf /* pipes */, 3 /* num_operands */, 1183 { "wh64", TILE_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
10915 TREG_ZERO, /* implicitly_written_register */ 1184 { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
10916 1, /* can_bundle */
10917 {
10918 /* operands */
10919 { 7, 8, 16 },
10920 { 9, 10, 17 },
10921 { 11, 12, 18 },
10922 { 13, 14, 19 },
10923 { 0, }
10924 },
10925 {
10926 /* fixed_bit_masks */
10927 0x800000007ffc0000ULL,
10928 0xfffe000000000000ULL,
10929 0x80000000780c0000ULL,
10930 0xf806000000000000ULL,
10931 0ULL
10932 },
10933 {
10934 /* fixed_bit_values */
10935 0x0000000001780000ULL,
10936 0x0882000000000000ULL,
10937 0x80000000180c0000ULL,
10938 0x9806000000000000ULL,
10939 -1ULL
10940 }
10941 }, 1185 },
10942 { "xor.sn", TILE_OPC_XOR_SN, 0x3 /* pipes */, 3 /* num_operands */, 1186 { "xor", TILE_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
10943 TREG_SN, /* implicitly_written_register */ 1187 { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
10944 1, /* can_bundle */
10945 {
10946 /* operands */
10947 { 7, 8, 16 },
10948 { 9, 10, 17 },
10949 { 0, },
10950 { 0, },
10951 { 0, }
10952 },
10953 {
10954 /* fixed_bit_masks */
10955 0x800000007ffc0000ULL,
10956 0xfffe000000000000ULL,
10957 0ULL,
10958 0ULL,
10959 0ULL
10960 },
10961 {
10962 /* fixed_bit_values */
10963 0x0000000009780000ULL,
10964 0x0c82000000000000ULL,
10965 -1ULL,
10966 -1ULL,
10967 -1ULL
10968 }
10969 }, 1188 },
10970 { "xori", TILE_OPC_XORI, 0x3 /* pipes */, 3 /* num_operands */, 1189 { "xor.sn", TILE_OPC_XOR_SN, 0x3, 3, TREG_SN, 1,
10971 TREG_ZERO, /* implicitly_written_register */ 1190 { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
10972 1, /* can_bundle */
10973 {
10974 /* operands */
10975 { 7, 8, 0 },
10976 { 9, 10, 1 },
10977 { 0, },
10978 { 0, },
10979 { 0, }
10980 },
10981 {
10982 /* fixed_bit_masks */
10983 0x800000007ff00000ULL,
10984 0xfff8000000000000ULL,
10985 0ULL,
10986 0ULL,
10987 0ULL
10988 },
10989 {
10990 /* fixed_bit_values */
10991 0x0000000050200000ULL,
10992 0x30a8000000000000ULL,
10993 -1ULL,
10994 -1ULL,
10995 -1ULL
10996 }
10997 }, 1191 },
10998 { "xori.sn", TILE_OPC_XORI_SN, 0x3 /* pipes */, 3 /* num_operands */, 1192 { "xori", TILE_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
10999 TREG_SN, /* implicitly_written_register */ 1193 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
11000 1, /* can_bundle */ 1194 },
11001 { 1195 { "xori.sn", TILE_OPC_XORI_SN, 0x3, 3, TREG_SN, 1,
11002 /* operands */ 1196 { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
11003 { 7, 8, 0 },
11004 { 9, 10, 1 },
11005 { 0, },
11006 { 0, },
11007 { 0, }
11008 },
11009 {
11010 /* fixed_bit_masks */
11011 0x800000007ff00000ULL,
11012 0xfff8000000000000ULL,
11013 0ULL,
11014 0ULL,
11015 0ULL
11016 },
11017 {
11018 /* fixed_bit_values */
11019 0x0000000058200000ULL,
11020 0x34a8000000000000ULL,
11021 -1ULL,
11022 -1ULL,
11023 -1ULL
11024 }
11025 }, 1197 },
11026 { 0, TILE_OPC_NONE, 0, 0, 0, TREG_ZERO, { { 0, } }, { 0, }, { 0, } 1198 { NULL, TILE_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
11027 } 1199 }
11028}; 1200};
11029#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6)) 1201#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
@@ -11387,7 +1559,7 @@ static const unsigned short decode_X0_fsm[1153] =
11387 TILE_OPC_TBLIDXB3_SN, TILE_OPC_NONE, 1559 TILE_OPC_TBLIDXB3_SN, TILE_OPC_NONE,
11388}; 1560};
11389 1561
11390static const unsigned short decode_X1_fsm[1509] = 1562static const unsigned short decode_X1_fsm[1540] =
11391{ 1563{
11392 BITFIELD(54, 9) /* index 0 */, 1564 BITFIELD(54, 9) /* index 0 */,
11393 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1565 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
@@ -11440,7 +1612,7 @@ static const unsigned short decode_X1_fsm[1509] =
11440 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1612 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11441 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1613 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11442 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1614 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11443 CHILD(1303), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1615 CHILD(1334), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11444 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1616 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11445 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1617 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11446 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1618 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
@@ -11673,7 +1845,7 @@ static const unsigned short decode_X1_fsm[1509] =
11673 CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142), CHILD(1142), 1845 CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142), CHILD(1142),
11674 CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145), CHILD(1145), 1846 CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145), CHILD(1145),
11675 CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1151), 1847 CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1151),
11676 CHILD(1211), CHILD(1259), CHILD(1292), TILE_OPC_NONE, TILE_OPC_NONE, 1848 CHILD(1242), CHILD(1290), CHILD(1323), TILE_OPC_NONE, TILE_OPC_NONE,
11677 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1849 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11678 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1850 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11679 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1851 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
@@ -11725,10 +1897,10 @@ static const unsigned short decode_X1_fsm[1509] =
11725 TILE_OPC_FNOP, TILE_OPC_NONE, 1897 TILE_OPC_FNOP, TILE_OPC_NONE,
11726 BITFIELD(53, 1) /* index 1175 */, 1898 BITFIELD(53, 1) /* index 1175 */,
11727 TILE_OPC_ICOH, TILE_OPC_NONE, 1899 TILE_OPC_ICOH, TILE_OPC_NONE,
11728 BITFIELD(53, 1) /* index 1178 */, 1900 BITFIELD(31, 2) /* index 1178 */,
11729 CHILD(1181), TILE_OPC_NONE, 1901 CHILD(1183), CHILD(1211), CHILD(1239), CHILD(1239),
11730 BITFIELD(31, 2) /* index 1181 */, 1902 BITFIELD(53, 1) /* index 1183 */,
11731 CHILD(1186), TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, 1903 CHILD(1186), TILE_OPC_NONE,
11732 BITFIELD(33, 2) /* index 1186 */, 1904 BITFIELD(33, 2) /* index 1186 */,
11733 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1191), 1905 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1191),
11734 BITFIELD(35, 2) /* index 1191 */, 1906 BITFIELD(35, 2) /* index 1191 */,
@@ -11739,67 +1911,81 @@ static const unsigned short decode_X1_fsm[1509] =
11739 TILE_OPC_ILL, CHILD(1206), TILE_OPC_ILL, TILE_OPC_ILL, 1911 TILE_OPC_ILL, CHILD(1206), TILE_OPC_ILL, TILE_OPC_ILL,
11740 BITFIELD(41, 2) /* index 1206 */, 1912 BITFIELD(41, 2) /* index 1206 */,
11741 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_BPT, TILE_OPC_ILL, 1913 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_BPT, TILE_OPC_ILL,
11742 BITFIELD(43, 3) /* index 1211 */, 1914 BITFIELD(53, 1) /* index 1211 */,
11743 CHILD(1220), CHILD(1223), CHILD(1226), CHILD(1244), CHILD(1247), 1915 CHILD(1214), TILE_OPC_NONE,
11744 CHILD(1250), CHILD(1253), CHILD(1256), 1916 BITFIELD(33, 2) /* index 1214 */,
11745 BITFIELD(53, 1) /* index 1220 */, 1917 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1219),
1918 BITFIELD(35, 2) /* index 1219 */,
1919 TILE_OPC_ILL, CHILD(1224), TILE_OPC_ILL, TILE_OPC_ILL,
1920 BITFIELD(37, 2) /* index 1224 */,
1921 TILE_OPC_ILL, CHILD(1229), TILE_OPC_ILL, TILE_OPC_ILL,
1922 BITFIELD(39, 2) /* index 1229 */,
1923 TILE_OPC_ILL, CHILD(1234), TILE_OPC_ILL, TILE_OPC_ILL,
1924 BITFIELD(41, 2) /* index 1234 */,
1925 TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_RAISE, TILE_OPC_ILL,
1926 BITFIELD(53, 1) /* index 1239 */,
1927 TILE_OPC_ILL, TILE_OPC_NONE,
1928 BITFIELD(43, 3) /* index 1242 */,
1929 CHILD(1251), CHILD(1254), CHILD(1257), CHILD(1275), CHILD(1278),
1930 CHILD(1281), CHILD(1284), CHILD(1287),
1931 BITFIELD(53, 1) /* index 1251 */,
11746 TILE_OPC_INV, TILE_OPC_NONE, 1932 TILE_OPC_INV, TILE_OPC_NONE,
11747 BITFIELD(53, 1) /* index 1223 */, 1933 BITFIELD(53, 1) /* index 1254 */,
11748 TILE_OPC_IRET, TILE_OPC_NONE, 1934 TILE_OPC_IRET, TILE_OPC_NONE,
11749 BITFIELD(53, 1) /* index 1226 */, 1935 BITFIELD(53, 1) /* index 1257 */,
11750 CHILD(1229), TILE_OPC_NONE, 1936 CHILD(1260), TILE_OPC_NONE,
11751 BITFIELD(31, 2) /* index 1229 */, 1937 BITFIELD(31, 2) /* index 1260 */,
11752 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1234), 1938 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1265),
11753 BITFIELD(33, 2) /* index 1234 */, 1939 BITFIELD(33, 2) /* index 1265 */,
11754 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1239), 1940 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1270),
11755 BITFIELD(35, 2) /* index 1239 */, 1941 BITFIELD(35, 2) /* index 1270 */,
11756 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH, 1942 TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH,
11757 BITFIELD(53, 1) /* index 1244 */, 1943 BITFIELD(53, 1) /* index 1275 */,
11758 TILE_OPC_LB_U, TILE_OPC_NONE, 1944 TILE_OPC_LB_U, TILE_OPC_NONE,
11759 BITFIELD(53, 1) /* index 1247 */, 1945 BITFIELD(53, 1) /* index 1278 */,
11760 TILE_OPC_LH, TILE_OPC_NONE, 1946 TILE_OPC_LH, TILE_OPC_NONE,
11761 BITFIELD(53, 1) /* index 1250 */, 1947 BITFIELD(53, 1) /* index 1281 */,
11762 TILE_OPC_LH_U, TILE_OPC_NONE, 1948 TILE_OPC_LH_U, TILE_OPC_NONE,
11763 BITFIELD(53, 1) /* index 1253 */, 1949 BITFIELD(53, 1) /* index 1284 */,
11764 TILE_OPC_LW, TILE_OPC_NONE, 1950 TILE_OPC_LW, TILE_OPC_NONE,
11765 BITFIELD(53, 1) /* index 1256 */, 1951 BITFIELD(53, 1) /* index 1287 */,
11766 TILE_OPC_MF, TILE_OPC_NONE, 1952 TILE_OPC_MF, TILE_OPC_NONE,
11767 BITFIELD(43, 3) /* index 1259 */, 1953 BITFIELD(43, 3) /* index 1290 */,
11768 CHILD(1268), CHILD(1271), CHILD(1274), CHILD(1277), CHILD(1280), 1954 CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311),
11769 CHILD(1283), CHILD(1286), CHILD(1289), 1955 CHILD(1314), CHILD(1317), CHILD(1320),
11770 BITFIELD(53, 1) /* index 1268 */, 1956 BITFIELD(53, 1) /* index 1299 */,
11771 TILE_OPC_NAP, TILE_OPC_NONE, 1957 TILE_OPC_NAP, TILE_OPC_NONE,
11772 BITFIELD(53, 1) /* index 1271 */, 1958 BITFIELD(53, 1) /* index 1302 */,
11773 TILE_OPC_NOP, TILE_OPC_NONE, 1959 TILE_OPC_NOP, TILE_OPC_NONE,
11774 BITFIELD(53, 1) /* index 1274 */, 1960 BITFIELD(53, 1) /* index 1305 */,
11775 TILE_OPC_SWINT0, TILE_OPC_NONE, 1961 TILE_OPC_SWINT0, TILE_OPC_NONE,
11776 BITFIELD(53, 1) /* index 1277 */, 1962 BITFIELD(53, 1) /* index 1308 */,
11777 TILE_OPC_SWINT1, TILE_OPC_NONE, 1963 TILE_OPC_SWINT1, TILE_OPC_NONE,
11778 BITFIELD(53, 1) /* index 1280 */, 1964 BITFIELD(53, 1) /* index 1311 */,
11779 TILE_OPC_SWINT2, TILE_OPC_NONE, 1965 TILE_OPC_SWINT2, TILE_OPC_NONE,
11780 BITFIELD(53, 1) /* index 1283 */, 1966 BITFIELD(53, 1) /* index 1314 */,
11781 TILE_OPC_SWINT3, TILE_OPC_NONE, 1967 TILE_OPC_SWINT3, TILE_OPC_NONE,
11782 BITFIELD(53, 1) /* index 1286 */, 1968 BITFIELD(53, 1) /* index 1317 */,
11783 TILE_OPC_TNS, TILE_OPC_NONE, 1969 TILE_OPC_TNS, TILE_OPC_NONE,
11784 BITFIELD(53, 1) /* index 1289 */, 1970 BITFIELD(53, 1) /* index 1320 */,
11785 TILE_OPC_WH64, TILE_OPC_NONE, 1971 TILE_OPC_WH64, TILE_OPC_NONE,
11786 BITFIELD(43, 2) /* index 1292 */, 1972 BITFIELD(43, 2) /* index 1323 */,
11787 CHILD(1297), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1973 CHILD(1328), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11788 BITFIELD(45, 1) /* index 1297 */, 1974 BITFIELD(45, 1) /* index 1328 */,
11789 CHILD(1300), TILE_OPC_NONE, 1975 CHILD(1331), TILE_OPC_NONE,
11790 BITFIELD(53, 1) /* index 1300 */, 1976 BITFIELD(53, 1) /* index 1331 */,
11791 TILE_OPC_LW_NA, TILE_OPC_NONE, 1977 TILE_OPC_LW_NA, TILE_OPC_NONE,
11792 BITFIELD(46, 7) /* index 1303 */, 1978 BITFIELD(46, 7) /* index 1334 */,
11793 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1432), 1979 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1463),
11794 CHILD(1432), CHILD(1432), CHILD(1432), CHILD(1435), CHILD(1435), 1980 CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1466), CHILD(1466),
11795 CHILD(1435), CHILD(1435), CHILD(1438), CHILD(1438), CHILD(1438), 1981 CHILD(1466), CHILD(1466), CHILD(1469), CHILD(1469), CHILD(1469),
11796 CHILD(1438), CHILD(1441), CHILD(1441), CHILD(1441), CHILD(1441), 1982 CHILD(1469), CHILD(1472), CHILD(1472), CHILD(1472), CHILD(1472),
11797 CHILD(1444), CHILD(1444), CHILD(1444), CHILD(1444), CHILD(1447), 1983 CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1478),
11798 CHILD(1447), CHILD(1447), CHILD(1447), CHILD(1450), CHILD(1450), 1984 CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1481), CHILD(1481),
11799 CHILD(1450), CHILD(1450), CHILD(1453), CHILD(1453), CHILD(1453), 1985 CHILD(1481), CHILD(1481), CHILD(1484), CHILD(1484), CHILD(1484),
11800 CHILD(1453), CHILD(1456), CHILD(1456), CHILD(1456), CHILD(1456), 1986 CHILD(1484), CHILD(1487), CHILD(1487), CHILD(1487), CHILD(1487),
11801 CHILD(1459), CHILD(1459), CHILD(1459), CHILD(1459), CHILD(1151), 1987 CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1151),
11802 CHILD(1462), CHILD(1486), CHILD(1498), TILE_OPC_NONE, TILE_OPC_NONE, 1988 CHILD(1493), CHILD(1517), CHILD(1529), TILE_OPC_NONE, TILE_OPC_NONE,
11803 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1989 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11804 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1990 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11805 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 1991 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
@@ -11816,49 +2002,49 @@ static const unsigned short decode_X1_fsm[1509] =
11816 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2002 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11817 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2003 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11818 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2004 TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11819 BITFIELD(53, 1) /* index 1432 */, 2005 BITFIELD(53, 1) /* index 1463 */,
11820 TILE_OPC_RLI_SN, TILE_OPC_NONE, 2006 TILE_OPC_RLI_SN, TILE_OPC_NONE,
11821 BITFIELD(53, 1) /* index 1435 */, 2007 BITFIELD(53, 1) /* index 1466 */,
11822 TILE_OPC_SHLIB_SN, TILE_OPC_NONE, 2008 TILE_OPC_SHLIB_SN, TILE_OPC_NONE,
11823 BITFIELD(53, 1) /* index 1438 */, 2009 BITFIELD(53, 1) /* index 1469 */,
11824 TILE_OPC_SHLIH_SN, TILE_OPC_NONE, 2010 TILE_OPC_SHLIH_SN, TILE_OPC_NONE,
11825 BITFIELD(53, 1) /* index 1441 */, 2011 BITFIELD(53, 1) /* index 1472 */,
11826 TILE_OPC_SHLI_SN, TILE_OPC_NONE, 2012 TILE_OPC_SHLI_SN, TILE_OPC_NONE,
11827 BITFIELD(53, 1) /* index 1444 */, 2013 BITFIELD(53, 1) /* index 1475 */,
11828 TILE_OPC_SHRIB_SN, TILE_OPC_NONE, 2014 TILE_OPC_SHRIB_SN, TILE_OPC_NONE,
11829 BITFIELD(53, 1) /* index 1447 */, 2015 BITFIELD(53, 1) /* index 1478 */,
11830 TILE_OPC_SHRIH_SN, TILE_OPC_NONE, 2016 TILE_OPC_SHRIH_SN, TILE_OPC_NONE,
11831 BITFIELD(53, 1) /* index 1450 */, 2017 BITFIELD(53, 1) /* index 1481 */,
11832 TILE_OPC_SHRI_SN, TILE_OPC_NONE, 2018 TILE_OPC_SHRI_SN, TILE_OPC_NONE,
11833 BITFIELD(53, 1) /* index 1453 */, 2019 BITFIELD(53, 1) /* index 1484 */,
11834 TILE_OPC_SRAIB_SN, TILE_OPC_NONE, 2020 TILE_OPC_SRAIB_SN, TILE_OPC_NONE,
11835 BITFIELD(53, 1) /* index 1456 */, 2021 BITFIELD(53, 1) /* index 1487 */,
11836 TILE_OPC_SRAIH_SN, TILE_OPC_NONE, 2022 TILE_OPC_SRAIH_SN, TILE_OPC_NONE,
11837 BITFIELD(53, 1) /* index 1459 */, 2023 BITFIELD(53, 1) /* index 1490 */,
11838 TILE_OPC_SRAI_SN, TILE_OPC_NONE, 2024 TILE_OPC_SRAI_SN, TILE_OPC_NONE,
11839 BITFIELD(43, 3) /* index 1462 */, 2025 BITFIELD(43, 3) /* index 1493 */,
11840 CHILD(1220), CHILD(1223), CHILD(1471), CHILD(1474), CHILD(1477), 2026 CHILD(1251), CHILD(1254), CHILD(1502), CHILD(1505), CHILD(1508),
11841 CHILD(1480), CHILD(1483), CHILD(1256), 2027 CHILD(1511), CHILD(1514), CHILD(1287),
11842 BITFIELD(53, 1) /* index 1471 */, 2028 BITFIELD(53, 1) /* index 1502 */,
11843 TILE_OPC_LB_SN, TILE_OPC_NONE, 2029 TILE_OPC_LB_SN, TILE_OPC_NONE,
11844 BITFIELD(53, 1) /* index 1474 */, 2030 BITFIELD(53, 1) /* index 1505 */,
11845 TILE_OPC_LB_U_SN, TILE_OPC_NONE, 2031 TILE_OPC_LB_U_SN, TILE_OPC_NONE,
11846 BITFIELD(53, 1) /* index 1477 */, 2032 BITFIELD(53, 1) /* index 1508 */,
11847 TILE_OPC_LH_SN, TILE_OPC_NONE, 2033 TILE_OPC_LH_SN, TILE_OPC_NONE,
11848 BITFIELD(53, 1) /* index 1480 */, 2034 BITFIELD(53, 1) /* index 1511 */,
11849 TILE_OPC_LH_U_SN, TILE_OPC_NONE, 2035 TILE_OPC_LH_U_SN, TILE_OPC_NONE,
11850 BITFIELD(53, 1) /* index 1483 */, 2036 BITFIELD(53, 1) /* index 1514 */,
11851 TILE_OPC_LW_SN, TILE_OPC_NONE, 2037 TILE_OPC_LW_SN, TILE_OPC_NONE,
11852 BITFIELD(43, 3) /* index 1486 */, 2038 BITFIELD(43, 3) /* index 1517 */,
11853 CHILD(1268), CHILD(1271), CHILD(1274), CHILD(1277), CHILD(1280), 2039 CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311),
11854 CHILD(1283), CHILD(1495), CHILD(1289), 2040 CHILD(1314), CHILD(1526), CHILD(1320),
11855 BITFIELD(53, 1) /* index 1495 */, 2041 BITFIELD(53, 1) /* index 1526 */,
11856 TILE_OPC_TNS_SN, TILE_OPC_NONE, 2042 TILE_OPC_TNS_SN, TILE_OPC_NONE,
11857 BITFIELD(43, 2) /* index 1498 */, 2043 BITFIELD(43, 2) /* index 1529 */,
11858 CHILD(1503), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, 2044 CHILD(1534), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE,
11859 BITFIELD(45, 1) /* index 1503 */, 2045 BITFIELD(45, 1) /* index 1534 */,
11860 CHILD(1506), TILE_OPC_NONE, 2046 CHILD(1537), TILE_OPC_NONE,
11861 BITFIELD(53, 1) /* index 1506 */, 2047 BITFIELD(53, 1) /* index 1537 */,
11862 TILE_OPC_LW_NA_SN, TILE_OPC_NONE, 2048 TILE_OPC_LW_NA_SN, TILE_OPC_NONE,
11863}; 2049};
11864 2050
@@ -12005,1741 +2191,227 @@ tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS] =
12005 decode_Y1_fsm, 2191 decode_Y1_fsm,
12006 decode_Y2_fsm 2192 decode_Y2_fsm
12007}; 2193};
12008const struct tile_sn_opcode tile_sn_opcodes[23] =
12009{
12010 { "bz", TILE_SN_OPC_BZ,
12011 1 /* num_operands */,
12012 /* operands */
12013 { 38 },
12014 /* fixed_bit_mask */
12015 0xfc00,
12016 /* fixed_bit_value */
12017 0xe000
12018 },
12019 { "bnz", TILE_SN_OPC_BNZ,
12020 1 /* num_operands */,
12021 /* operands */
12022 { 38 },
12023 /* fixed_bit_mask */
12024 0xfc00,
12025 /* fixed_bit_value */
12026 0xe400
12027 },
12028 { "jrr", TILE_SN_OPC_JRR,
12029 1 /* num_operands */,
12030 /* operands */
12031 { 39 },
12032 /* fixed_bit_mask */
12033 0xff00,
12034 /* fixed_bit_value */
12035 0x0600
12036 },
12037 { "fnop", TILE_SN_OPC_FNOP,
12038 0 /* num_operands */,
12039 /* operands */
12040 { 0, },
12041 /* fixed_bit_mask */
12042 0xffff,
12043 /* fixed_bit_value */
12044 0x0003
12045 },
12046 { "blz", TILE_SN_OPC_BLZ,
12047 1 /* num_operands */,
12048 /* operands */
12049 { 38 },
12050 /* fixed_bit_mask */
12051 0xfc00,
12052 /* fixed_bit_value */
12053 0xf000
12054 },
12055 { "nop", TILE_SN_OPC_NOP,
12056 0 /* num_operands */,
12057 /* operands */
12058 { 0, },
12059 /* fixed_bit_mask */
12060 0xffff,
12061 /* fixed_bit_value */
12062 0x0002
12063 },
12064 { "movei", TILE_SN_OPC_MOVEI,
12065 1 /* num_operands */,
12066 /* operands */
12067 { 40 },
12068 /* fixed_bit_mask */
12069 0xff00,
12070 /* fixed_bit_value */
12071 0x0400
12072 },
12073 { "move", TILE_SN_OPC_MOVE,
12074 2 /* num_operands */,
12075 /* operands */
12076 { 41, 42 },
12077 /* fixed_bit_mask */
12078 0xfff0,
12079 /* fixed_bit_value */
12080 0x0080
12081 },
12082 { "bgez", TILE_SN_OPC_BGEZ,
12083 1 /* num_operands */,
12084 /* operands */
12085 { 38 },
12086 /* fixed_bit_mask */
12087 0xfc00,
12088 /* fixed_bit_value */
12089 0xf400
12090 },
12091 { "jr", TILE_SN_OPC_JR,
12092 1 /* num_operands */,
12093 /* operands */
12094 { 42 },
12095 /* fixed_bit_mask */
12096 0xfff0,
12097 /* fixed_bit_value */
12098 0x0040
12099 },
12100 { "blez", TILE_SN_OPC_BLEZ,
12101 1 /* num_operands */,
12102 /* operands */
12103 { 38 },
12104 /* fixed_bit_mask */
12105 0xfc00,
12106 /* fixed_bit_value */
12107 0xec00
12108 },
12109 { "bbns", TILE_SN_OPC_BBNS,
12110 1 /* num_operands */,
12111 /* operands */
12112 { 38 },
12113 /* fixed_bit_mask */
12114 0xfc00,
12115 /* fixed_bit_value */
12116 0xfc00
12117 },
12118 { "jalrr", TILE_SN_OPC_JALRR,
12119 1 /* num_operands */,
12120 /* operands */
12121 { 39 },
12122 /* fixed_bit_mask */
12123 0xff00,
12124 /* fixed_bit_value */
12125 0x0700
12126 },
12127 { "bpt", TILE_SN_OPC_BPT,
12128 0 /* num_operands */,
12129 /* operands */
12130 { 0, },
12131 /* fixed_bit_mask */
12132 0xffff,
12133 /* fixed_bit_value */
12134 0x0001
12135 },
12136 { "jalr", TILE_SN_OPC_JALR,
12137 1 /* num_operands */,
12138 /* operands */
12139 { 42 },
12140 /* fixed_bit_mask */
12141 0xfff0,
12142 /* fixed_bit_value */
12143 0x0050
12144 },
12145 { "shr1", TILE_SN_OPC_SHR1,
12146 2 /* num_operands */,
12147 /* operands */
12148 { 41, 42 },
12149 /* fixed_bit_mask */
12150 0xfff0,
12151 /* fixed_bit_value */
12152 0x0090
12153 },
12154 { "bgz", TILE_SN_OPC_BGZ,
12155 1 /* num_operands */,
12156 /* operands */
12157 { 38 },
12158 /* fixed_bit_mask */
12159 0xfc00,
12160 /* fixed_bit_value */
12161 0xe800
12162 },
12163 { "bbs", TILE_SN_OPC_BBS,
12164 1 /* num_operands */,
12165 /* operands */
12166 { 38 },
12167 /* fixed_bit_mask */
12168 0xfc00,
12169 /* fixed_bit_value */
12170 0xf800
12171 },
12172 { "shl8ii", TILE_SN_OPC_SHL8II,
12173 1 /* num_operands */,
12174 /* operands */
12175 { 39 },
12176 /* fixed_bit_mask */
12177 0xff00,
12178 /* fixed_bit_value */
12179 0x0300
12180 },
12181 { "addi", TILE_SN_OPC_ADDI,
12182 1 /* num_operands */,
12183 /* operands */
12184 { 40 },
12185 /* fixed_bit_mask */
12186 0xff00,
12187 /* fixed_bit_value */
12188 0x0500
12189 },
12190 { "halt", TILE_SN_OPC_HALT,
12191 0 /* num_operands */,
12192 /* operands */
12193 { 0, },
12194 /* fixed_bit_mask */
12195 0xffff,
12196 /* fixed_bit_value */
12197 0x0000
12198 },
12199 { "route", TILE_SN_OPC_ROUTE, 0, { 0, }, 0, 0,
12200 },
12201 { 0, TILE_SN_OPC_NONE, 0, { 0, }, 0, 0,
12202 }
12203};
12204const unsigned char tile_sn_route_encode[6 * 6 * 6] =
12205{
12206 0xdf,
12207 0xde,
12208 0xdd,
12209 0xdc,
12210 0xdb,
12211 0xda,
12212 0xb9,
12213 0xb8,
12214 0xa1,
12215 0xa0,
12216 0x11,
12217 0x10,
12218 0x9f,
12219 0x9e,
12220 0x9d,
12221 0x9c,
12222 0x9b,
12223 0x9a,
12224 0x79,
12225 0x78,
12226 0x61,
12227 0x60,
12228 0xb,
12229 0xa,
12230 0x5f,
12231 0x5e,
12232 0x5d,
12233 0x5c,
12234 0x5b,
12235 0x5a,
12236 0x1f,
12237 0x1e,
12238 0x1d,
12239 0x1c,
12240 0x1b,
12241 0x1a,
12242 0xd7,
12243 0xd6,
12244 0xd5,
12245 0xd4,
12246 0xd3,
12247 0xd2,
12248 0xa7,
12249 0xa6,
12250 0xb1,
12251 0xb0,
12252 0x13,
12253 0x12,
12254 0x97,
12255 0x96,
12256 0x95,
12257 0x94,
12258 0x93,
12259 0x92,
12260 0x67,
12261 0x66,
12262 0x71,
12263 0x70,
12264 0x9,
12265 0x8,
12266 0x57,
12267 0x56,
12268 0x55,
12269 0x54,
12270 0x53,
12271 0x52,
12272 0x17,
12273 0x16,
12274 0x15,
12275 0x14,
12276 0x19,
12277 0x18,
12278 0xcf,
12279 0xce,
12280 0xcd,
12281 0xcc,
12282 0xcb,
12283 0xca,
12284 0xaf,
12285 0xae,
12286 0xad,
12287 0xac,
12288 0xab,
12289 0xaa,
12290 0x8f,
12291 0x8e,
12292 0x8d,
12293 0x8c,
12294 0x8b,
12295 0x8a,
12296 0x6f,
12297 0x6e,
12298 0x6d,
12299 0x6c,
12300 0x6b,
12301 0x6a,
12302 0x4f,
12303 0x4e,
12304 0x4d,
12305 0x4c,
12306 0x4b,
12307 0x4a,
12308 0x2f,
12309 0x2e,
12310 0x2d,
12311 0x2c,
12312 0x2b,
12313 0x2a,
12314 0xc9,
12315 0xc8,
12316 0xc5,
12317 0xc4,
12318 0xc3,
12319 0xc2,
12320 0xa9,
12321 0xa8,
12322 0xa5,
12323 0xa4,
12324 0xa3,
12325 0xa2,
12326 0x89,
12327 0x88,
12328 0x85,
12329 0x84,
12330 0x83,
12331 0x82,
12332 0x69,
12333 0x68,
12334 0x65,
12335 0x64,
12336 0x63,
12337 0x62,
12338 0x47,
12339 0x46,
12340 0x45,
12341 0x44,
12342 0x43,
12343 0x42,
12344 0x27,
12345 0x26,
12346 0x25,
12347 0x24,
12348 0x23,
12349 0x22,
12350 0xd9,
12351 0xd8,
12352 0xc1,
12353 0xc0,
12354 0x3b,
12355 0x3a,
12356 0xbf,
12357 0xbe,
12358 0xbd,
12359 0xbc,
12360 0xbb,
12361 0xba,
12362 0x99,
12363 0x98,
12364 0x81,
12365 0x80,
12366 0x31,
12367 0x30,
12368 0x7f,
12369 0x7e,
12370 0x7d,
12371 0x7c,
12372 0x7b,
12373 0x7a,
12374 0x59,
12375 0x58,
12376 0x3d,
12377 0x3c,
12378 0x49,
12379 0x48,
12380 0xf,
12381 0xe,
12382 0xd,
12383 0xc,
12384 0x29,
12385 0x28,
12386 0xc7,
12387 0xc6,
12388 0xd1,
12389 0xd0,
12390 0x39,
12391 0x38,
12392 0xb7,
12393 0xb6,
12394 0xb5,
12395 0xb4,
12396 0xb3,
12397 0xb2,
12398 0x87,
12399 0x86,
12400 0x91,
12401 0x90,
12402 0x33,
12403 0x32,
12404 0x77,
12405 0x76,
12406 0x75,
12407 0x74,
12408 0x73,
12409 0x72,
12410 0x3f,
12411 0x3e,
12412 0x51,
12413 0x50,
12414 0x41,
12415 0x40,
12416 0x37,
12417 0x36,
12418 0x35,
12419 0x34,
12420 0x21,
12421 0x20
12422};
12423
12424const signed char tile_sn_route_decode[256][3] =
12425{
12426 { -1, -1, -1 },
12427 { -1, -1, -1 },
12428 { -1, -1, -1 },
12429 { -1, -1, -1 },
12430 { -1, -1, -1 },
12431 { -1, -1, -1 },
12432 { -1, -1, -1 },
12433 { -1, -1, -1 },
12434 { 5, 3, 1 },
12435 { 4, 3, 1 },
12436 { 5, 3, 0 },
12437 { 4, 3, 0 },
12438 { 3, 5, 4 },
12439 { 2, 5, 4 },
12440 { 1, 5, 4 },
12441 { 0, 5, 4 },
12442 { 5, 1, 0 },
12443 { 4, 1, 0 },
12444 { 5, 1, 1 },
12445 { 4, 1, 1 },
12446 { 3, 5, 1 },
12447 { 2, 5, 1 },
12448 { 1, 5, 1 },
12449 { 0, 5, 1 },
12450 { 5, 5, 1 },
12451 { 4, 5, 1 },
12452 { 5, 5, 0 },
12453 { 4, 5, 0 },
12454 { 3, 5, 0 },
12455 { 2, 5, 0 },
12456 { 1, 5, 0 },
12457 { 0, 5, 0 },
12458 { 5, 5, 5 },
12459 { 4, 5, 5 },
12460 { 5, 5, 3 },
12461 { 4, 5, 3 },
12462 { 3, 5, 3 },
12463 { 2, 5, 3 },
12464 { 1, 5, 3 },
12465 { 0, 5, 3 },
12466 { 5, 5, 4 },
12467 { 4, 5, 4 },
12468 { 5, 5, 2 },
12469 { 4, 5, 2 },
12470 { 3, 5, 2 },
12471 { 2, 5, 2 },
12472 { 1, 5, 2 },
12473 { 0, 5, 2 },
12474 { 5, 2, 4 },
12475 { 4, 2, 4 },
12476 { 5, 2, 5 },
12477 { 4, 2, 5 },
12478 { 3, 5, 5 },
12479 { 2, 5, 5 },
12480 { 1, 5, 5 },
12481 { 0, 5, 5 },
12482 { 5, 0, 5 },
12483 { 4, 0, 5 },
12484 { 5, 0, 4 },
12485 { 4, 0, 4 },
12486 { 3, 4, 4 },
12487 { 2, 4, 4 },
12488 { 1, 4, 5 },
12489 { 0, 4, 5 },
12490 { 5, 4, 5 },
12491 { 4, 4, 5 },
12492 { 5, 4, 3 },
12493 { 4, 4, 3 },
12494 { 3, 4, 3 },
12495 { 2, 4, 3 },
12496 { 1, 4, 3 },
12497 { 0, 4, 3 },
12498 { 5, 4, 4 },
12499 { 4, 4, 4 },
12500 { 5, 4, 2 },
12501 { 4, 4, 2 },
12502 { 3, 4, 2 },
12503 { 2, 4, 2 },
12504 { 1, 4, 2 },
12505 { 0, 4, 2 },
12506 { 3, 4, 5 },
12507 { 2, 4, 5 },
12508 { 5, 4, 1 },
12509 { 4, 4, 1 },
12510 { 3, 4, 1 },
12511 { 2, 4, 1 },
12512 { 1, 4, 1 },
12513 { 0, 4, 1 },
12514 { 1, 4, 4 },
12515 { 0, 4, 4 },
12516 { 5, 4, 0 },
12517 { 4, 4, 0 },
12518 { 3, 4, 0 },
12519 { 2, 4, 0 },
12520 { 1, 4, 0 },
12521 { 0, 4, 0 },
12522 { 3, 3, 0 },
12523 { 2, 3, 0 },
12524 { 5, 3, 3 },
12525 { 4, 3, 3 },
12526 { 3, 3, 3 },
12527 { 2, 3, 3 },
12528 { 1, 3, 1 },
12529 { 0, 3, 1 },
12530 { 1, 3, 3 },
12531 { 0, 3, 3 },
12532 { 5, 3, 2 },
12533 { 4, 3, 2 },
12534 { 3, 3, 2 },
12535 { 2, 3, 2 },
12536 { 1, 3, 2 },
12537 { 0, 3, 2 },
12538 { 3, 3, 1 },
12539 { 2, 3, 1 },
12540 { 5, 3, 5 },
12541 { 4, 3, 5 },
12542 { 3, 3, 5 },
12543 { 2, 3, 5 },
12544 { 1, 3, 5 },
12545 { 0, 3, 5 },
12546 { 1, 3, 0 },
12547 { 0, 3, 0 },
12548 { 5, 3, 4 },
12549 { 4, 3, 4 },
12550 { 3, 3, 4 },
12551 { 2, 3, 4 },
12552 { 1, 3, 4 },
12553 { 0, 3, 4 },
12554 { 3, 2, 4 },
12555 { 2, 2, 4 },
12556 { 5, 2, 3 },
12557 { 4, 2, 3 },
12558 { 3, 2, 3 },
12559 { 2, 2, 3 },
12560 { 1, 2, 5 },
12561 { 0, 2, 5 },
12562 { 1, 2, 3 },
12563 { 0, 2, 3 },
12564 { 5, 2, 2 },
12565 { 4, 2, 2 },
12566 { 3, 2, 2 },
12567 { 2, 2, 2 },
12568 { 1, 2, 2 },
12569 { 0, 2, 2 },
12570 { 3, 2, 5 },
12571 { 2, 2, 5 },
12572 { 5, 2, 1 },
12573 { 4, 2, 1 },
12574 { 3, 2, 1 },
12575 { 2, 2, 1 },
12576 { 1, 2, 1 },
12577 { 0, 2, 1 },
12578 { 1, 2, 4 },
12579 { 0, 2, 4 },
12580 { 5, 2, 0 },
12581 { 4, 2, 0 },
12582 { 3, 2, 0 },
12583 { 2, 2, 0 },
12584 { 1, 2, 0 },
12585 { 0, 2, 0 },
12586 { 3, 1, 0 },
12587 { 2, 1, 0 },
12588 { 5, 1, 3 },
12589 { 4, 1, 3 },
12590 { 3, 1, 3 },
12591 { 2, 1, 3 },
12592 { 1, 1, 1 },
12593 { 0, 1, 1 },
12594 { 1, 1, 3 },
12595 { 0, 1, 3 },
12596 { 5, 1, 2 },
12597 { 4, 1, 2 },
12598 { 3, 1, 2 },
12599 { 2, 1, 2 },
12600 { 1, 1, 2 },
12601 { 0, 1, 2 },
12602 { 3, 1, 1 },
12603 { 2, 1, 1 },
12604 { 5, 1, 5 },
12605 { 4, 1, 5 },
12606 { 3, 1, 5 },
12607 { 2, 1, 5 },
12608 { 1, 1, 5 },
12609 { 0, 1, 5 },
12610 { 1, 1, 0 },
12611 { 0, 1, 0 },
12612 { 5, 1, 4 },
12613 { 4, 1, 4 },
12614 { 3, 1, 4 },
12615 { 2, 1, 4 },
12616 { 1, 1, 4 },
12617 { 0, 1, 4 },
12618 { 3, 0, 4 },
12619 { 2, 0, 4 },
12620 { 5, 0, 3 },
12621 { 4, 0, 3 },
12622 { 3, 0, 3 },
12623 { 2, 0, 3 },
12624 { 1, 0, 5 },
12625 { 0, 0, 5 },
12626 { 1, 0, 3 },
12627 { 0, 0, 3 },
12628 { 5, 0, 2 },
12629 { 4, 0, 2 },
12630 { 3, 0, 2 },
12631 { 2, 0, 2 },
12632 { 1, 0, 2 },
12633 { 0, 0, 2 },
12634 { 3, 0, 5 },
12635 { 2, 0, 5 },
12636 { 5, 0, 1 },
12637 { 4, 0, 1 },
12638 { 3, 0, 1 },
12639 { 2, 0, 1 },
12640 { 1, 0, 1 },
12641 { 0, 0, 1 },
12642 { 1, 0, 4 },
12643 { 0, 0, 4 },
12644 { 5, 0, 0 },
12645 { 4, 0, 0 },
12646 { 3, 0, 0 },
12647 { 2, 0, 0 },
12648 { 1, 0, 0 },
12649 { 0, 0, 0 },
12650 { -1, -1, -1 },
12651 { -1, -1, -1 },
12652 { -1, -1, -1 },
12653 { -1, -1, -1 },
12654 { -1, -1, -1 },
12655 { -1, -1, -1 },
12656 { -1, -1, -1 },
12657 { -1, -1, -1 },
12658 { -1, -1, -1 },
12659 { -1, -1, -1 },
12660 { -1, -1, -1 },
12661 { -1, -1, -1 },
12662 { -1, -1, -1 },
12663 { -1, -1, -1 },
12664 { -1, -1, -1 },
12665 { -1, -1, -1 },
12666 { -1, -1, -1 },
12667 { -1, -1, -1 },
12668 { -1, -1, -1 },
12669 { -1, -1, -1 },
12670 { -1, -1, -1 },
12671 { -1, -1, -1 },
12672 { -1, -1, -1 },
12673 { -1, -1, -1 },
12674 { -1, -1, -1 },
12675 { -1, -1, -1 },
12676 { -1, -1, -1 },
12677 { -1, -1, -1 },
12678 { -1, -1, -1 },
12679 { -1, -1, -1 },
12680 { -1, -1, -1 },
12681 { -1, -1, -1 }
12682};
12683
12684const char tile_sn_direction_names[6][5] =
12685{
12686 "w",
12687 "c",
12688 "acc",
12689 "n",
12690 "e",
12691 "s"
12692};
12693
12694const signed char tile_sn_dest_map[6][6] = {
12695 { -1, 3, 4, 5, 1, 2 } /* val -> w */,
12696 { -1, 3, 4, 5, 0, 2 } /* val -> c */,
12697 { -1, 3, 4, 5, 0, 1 } /* val -> acc */,
12698 { -1, 4, 5, 0, 1, 2 } /* val -> n */,
12699 { -1, 3, 5, 0, 1, 2 } /* val -> e */,
12700 { -1, 3, 4, 0, 1, 2 } /* val -> s */
12701};
12702
12703const struct tile_operand tile_operands[43] = 2194const struct tile_operand tile_operands[43] =
12704{ 2195{
12705 { 2196 {
12706 TILE_OP_TYPE_IMMEDIATE, /* type */ 2197 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_X0),
12707 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_X0), /* default_reloc */ 2198 8, 1, 0, 0, 0, 0,
12708 8, /* num_bits */ 2199 create_Imm8_X0, get_Imm8_X0
12709 1, /* is_signed */
12710 0, /* is_src_reg */
12711 0, /* is_dest_reg */
12712 0, /* is_pc_relative */
12713 0, /* rightshift */
12714 create_Imm8_X0, /* insert */
12715 get_Imm8_X0 /* extract */
12716 }, 2200 },
12717 { 2201 {
12718 TILE_OP_TYPE_IMMEDIATE, /* type */ 2202 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_X1),
12719 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_X1), /* default_reloc */ 2203 8, 1, 0, 0, 0, 0,
12720 8, /* num_bits */ 2204 create_Imm8_X1, get_Imm8_X1
12721 1, /* is_signed */
12722 0, /* is_src_reg */
12723 0, /* is_dest_reg */
12724 0, /* is_pc_relative */
12725 0, /* rightshift */
12726 create_Imm8_X1, /* insert */
12727 get_Imm8_X1 /* extract */
12728 }, 2205 },
12729 { 2206 {
12730 TILE_OP_TYPE_IMMEDIATE, /* type */ 2207 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_Y0),
12731 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_Y0), /* default_reloc */ 2208 8, 1, 0, 0, 0, 0,
12732 8, /* num_bits */ 2209 create_Imm8_Y0, get_Imm8_Y0
12733 1, /* is_signed */
12734 0, /* is_src_reg */
12735 0, /* is_dest_reg */
12736 0, /* is_pc_relative */
12737 0, /* rightshift */
12738 create_Imm8_Y0, /* insert */
12739 get_Imm8_Y0 /* extract */
12740 }, 2210 },
12741 { 2211 {
12742 TILE_OP_TYPE_IMMEDIATE, /* type */ 2212 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_Y1),
12743 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM8_Y1), /* default_reloc */ 2213 8, 1, 0, 0, 0, 0,
12744 8, /* num_bits */ 2214 create_Imm8_Y1, get_Imm8_Y1
12745 1, /* is_signed */
12746 0, /* is_src_reg */
12747 0, /* is_dest_reg */
12748 0, /* is_pc_relative */
12749 0, /* rightshift */
12750 create_Imm8_Y1, /* insert */
12751 get_Imm8_Y1 /* extract */
12752 }, 2215 },
12753 { 2216 {
12754 TILE_OP_TYPE_IMMEDIATE, /* type */ 2217 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM16_X0),
12755 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM16_X0), /* default_reloc */ 2218 16, 1, 0, 0, 0, 0,
12756 16, /* num_bits */ 2219 create_Imm16_X0, get_Imm16_X0
12757 1, /* is_signed */
12758 0, /* is_src_reg */
12759 0, /* is_dest_reg */
12760 0, /* is_pc_relative */
12761 0, /* rightshift */
12762 create_Imm16_X0, /* insert */
12763 get_Imm16_X0 /* extract */
12764 }, 2220 },
12765 { 2221 {
12766 TILE_OP_TYPE_IMMEDIATE, /* type */ 2222 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM16_X1),
12767 MAYBE_BFD_RELOC(BFD_RELOC_TILE_IMM16_X1), /* default_reloc */ 2223 16, 1, 0, 0, 0, 0,
12768 16, /* num_bits */ 2224 create_Imm16_X1, get_Imm16_X1
12769 1, /* is_signed */
12770 0, /* is_src_reg */
12771 0, /* is_dest_reg */
12772 0, /* is_pc_relative */
12773 0, /* rightshift */
12774 create_Imm16_X1, /* insert */
12775 get_Imm16_X1 /* extract */
12776 }, 2225 },
12777 { 2226 {
12778 TILE_OP_TYPE_ADDRESS, /* type */ 2227 TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_JOFFLONG_X1),
12779 MAYBE_BFD_RELOC(BFD_RELOC_TILE_JOFFLONG_X1), /* default_reloc */ 2228 29, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
12780 29, /* num_bits */ 2229 create_JOffLong_X1, get_JOffLong_X1
12781 1, /* is_signed */
12782 0, /* is_src_reg */
12783 0, /* is_dest_reg */
12784 1, /* is_pc_relative */
12785 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, /* rightshift */
12786 create_JOffLong_X1, /* insert */
12787 get_JOffLong_X1 /* extract */
12788 }, 2230 },
12789 { 2231 {
12790 TILE_OP_TYPE_REGISTER, /* type */ 2232 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12791 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2233 6, 0, 0, 1, 0, 0,
12792 6, /* num_bits */ 2234 create_Dest_X0, get_Dest_X0
12793 0, /* is_signed */
12794 0, /* is_src_reg */
12795 1, /* is_dest_reg */
12796 0, /* is_pc_relative */
12797 0, /* rightshift */
12798 create_Dest_X0, /* insert */
12799 get_Dest_X0 /* extract */
12800 }, 2235 },
12801 { 2236 {
12802 TILE_OP_TYPE_REGISTER, /* type */ 2237 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12803 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2238 6, 0, 1, 0, 0, 0,
12804 6, /* num_bits */ 2239 create_SrcA_X0, get_SrcA_X0
12805 0, /* is_signed */
12806 1, /* is_src_reg */
12807 0, /* is_dest_reg */
12808 0, /* is_pc_relative */
12809 0, /* rightshift */
12810 create_SrcA_X0, /* insert */
12811 get_SrcA_X0 /* extract */
12812 }, 2240 },
12813 { 2241 {
12814 TILE_OP_TYPE_REGISTER, /* type */ 2242 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12815 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2243 6, 0, 0, 1, 0, 0,
12816 6, /* num_bits */ 2244 create_Dest_X1, get_Dest_X1
12817 0, /* is_signed */
12818 0, /* is_src_reg */
12819 1, /* is_dest_reg */
12820 0, /* is_pc_relative */
12821 0, /* rightshift */
12822 create_Dest_X1, /* insert */
12823 get_Dest_X1 /* extract */
12824 }, 2245 },
12825 { 2246 {
12826 TILE_OP_TYPE_REGISTER, /* type */ 2247 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12827 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2248 6, 0, 1, 0, 0, 0,
12828 6, /* num_bits */ 2249 create_SrcA_X1, get_SrcA_X1
12829 0, /* is_signed */
12830 1, /* is_src_reg */
12831 0, /* is_dest_reg */
12832 0, /* is_pc_relative */
12833 0, /* rightshift */
12834 create_SrcA_X1, /* insert */
12835 get_SrcA_X1 /* extract */
12836 }, 2250 },
12837 { 2251 {
12838 TILE_OP_TYPE_REGISTER, /* type */ 2252 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12839 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2253 6, 0, 0, 1, 0, 0,
12840 6, /* num_bits */ 2254 create_Dest_Y0, get_Dest_Y0
12841 0, /* is_signed */
12842 0, /* is_src_reg */
12843 1, /* is_dest_reg */
12844 0, /* is_pc_relative */
12845 0, /* rightshift */
12846 create_Dest_Y0, /* insert */
12847 get_Dest_Y0 /* extract */
12848 }, 2255 },
12849 { 2256 {
12850 TILE_OP_TYPE_REGISTER, /* type */ 2257 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12851 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2258 6, 0, 1, 0, 0, 0,
12852 6, /* num_bits */ 2259 create_SrcA_Y0, get_SrcA_Y0
12853 0, /* is_signed */
12854 1, /* is_src_reg */
12855 0, /* is_dest_reg */
12856 0, /* is_pc_relative */
12857 0, /* rightshift */
12858 create_SrcA_Y0, /* insert */
12859 get_SrcA_Y0 /* extract */
12860 }, 2260 },
12861 { 2261 {
12862 TILE_OP_TYPE_REGISTER, /* type */ 2262 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12863 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2263 6, 0, 0, 1, 0, 0,
12864 6, /* num_bits */ 2264 create_Dest_Y1, get_Dest_Y1
12865 0, /* is_signed */
12866 0, /* is_src_reg */
12867 1, /* is_dest_reg */
12868 0, /* is_pc_relative */
12869 0, /* rightshift */
12870 create_Dest_Y1, /* insert */
12871 get_Dest_Y1 /* extract */
12872 }, 2265 },
12873 { 2266 {
12874 TILE_OP_TYPE_REGISTER, /* type */ 2267 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12875 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2268 6, 0, 1, 0, 0, 0,
12876 6, /* num_bits */ 2269 create_SrcA_Y1, get_SrcA_Y1
12877 0, /* is_signed */
12878 1, /* is_src_reg */
12879 0, /* is_dest_reg */
12880 0, /* is_pc_relative */
12881 0, /* rightshift */
12882 create_SrcA_Y1, /* insert */
12883 get_SrcA_Y1 /* extract */
12884 }, 2270 },
12885 { 2271 {
12886 TILE_OP_TYPE_REGISTER, /* type */ 2272 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12887 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2273 6, 0, 1, 0, 0, 0,
12888 6, /* num_bits */ 2274 create_SrcA_Y2, get_SrcA_Y2
12889 0, /* is_signed */
12890 1, /* is_src_reg */
12891 0, /* is_dest_reg */
12892 0, /* is_pc_relative */
12893 0, /* rightshift */
12894 create_SrcA_Y2, /* insert */
12895 get_SrcA_Y2 /* extract */
12896 }, 2275 },
12897 { 2276 {
12898 TILE_OP_TYPE_REGISTER, /* type */ 2277 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12899 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2278 6, 0, 1, 0, 0, 0,
12900 6, /* num_bits */ 2279 create_SrcB_X0, get_SrcB_X0
12901 0, /* is_signed */
12902 1, /* is_src_reg */
12903 0, /* is_dest_reg */
12904 0, /* is_pc_relative */
12905 0, /* rightshift */
12906 create_SrcB_X0, /* insert */
12907 get_SrcB_X0 /* extract */
12908 }, 2280 },
12909 { 2281 {
12910 TILE_OP_TYPE_REGISTER, /* type */ 2282 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12911 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2283 6, 0, 1, 0, 0, 0,
12912 6, /* num_bits */ 2284 create_SrcB_X1, get_SrcB_X1
12913 0, /* is_signed */
12914 1, /* is_src_reg */
12915 0, /* is_dest_reg */
12916 0, /* is_pc_relative */
12917 0, /* rightshift */
12918 create_SrcB_X1, /* insert */
12919 get_SrcB_X1 /* extract */
12920 }, 2285 },
12921 { 2286 {
12922 TILE_OP_TYPE_REGISTER, /* type */ 2287 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12923 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2288 6, 0, 1, 0, 0, 0,
12924 6, /* num_bits */ 2289 create_SrcB_Y0, get_SrcB_Y0
12925 0, /* is_signed */
12926 1, /* is_src_reg */
12927 0, /* is_dest_reg */
12928 0, /* is_pc_relative */
12929 0, /* rightshift */
12930 create_SrcB_Y0, /* insert */
12931 get_SrcB_Y0 /* extract */
12932 }, 2290 },
12933 { 2291 {
12934 TILE_OP_TYPE_REGISTER, /* type */ 2292 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12935 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2293 6, 0, 1, 0, 0, 0,
12936 6, /* num_bits */ 2294 create_SrcB_Y1, get_SrcB_Y1
12937 0, /* is_signed */
12938 1, /* is_src_reg */
12939 0, /* is_dest_reg */
12940 0, /* is_pc_relative */
12941 0, /* rightshift */
12942 create_SrcB_Y1, /* insert */
12943 get_SrcB_Y1 /* extract */
12944 }, 2295 },
12945 { 2296 {
12946 TILE_OP_TYPE_ADDRESS, /* type */ 2297 TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_BROFF_X1),
12947 MAYBE_BFD_RELOC(BFD_RELOC_TILE_BROFF_X1), /* default_reloc */ 2298 17, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
12948 17, /* num_bits */ 2299 create_BrOff_X1, get_BrOff_X1
12949 1, /* is_signed */
12950 0, /* is_src_reg */
12951 0, /* is_dest_reg */
12952 1, /* is_pc_relative */
12953 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, /* rightshift */
12954 create_BrOff_X1, /* insert */
12955 get_BrOff_X1 /* extract */
12956 }, 2300 },
12957 { 2301 {
12958 TILE_OP_TYPE_REGISTER, /* type */ 2302 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12959 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2303 6, 0, 1, 1, 0, 0,
12960 6, /* num_bits */ 2304 create_Dest_X0, get_Dest_X0
12961 0, /* is_signed */
12962 1, /* is_src_reg */
12963 1, /* is_dest_reg */
12964 0, /* is_pc_relative */
12965 0, /* rightshift */
12966 create_Dest_X0, /* insert */
12967 get_Dest_X0 /* extract */
12968 }, 2305 },
12969 { 2306 {
12970 TILE_OP_TYPE_ADDRESS, /* type */ 2307 TILE_OP_TYPE_ADDRESS, BFD_RELOC(NONE),
12971 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2308 28, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
12972 28, /* num_bits */ 2309 create_JOff_X1, get_JOff_X1
12973 1, /* is_signed */
12974 0, /* is_src_reg */
12975 0, /* is_dest_reg */
12976 1, /* is_pc_relative */
12977 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, /* rightshift */
12978 create_JOff_X1, /* insert */
12979 get_JOff_X1 /* extract */
12980 }, 2310 },
12981 { 2311 {
12982 TILE_OP_TYPE_REGISTER, /* type */ 2312 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12983 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2313 6, 0, 0, 1, 0, 0,
12984 6, /* num_bits */ 2314 create_SrcBDest_Y2, get_SrcBDest_Y2
12985 0, /* is_signed */
12986 0, /* is_src_reg */
12987 1, /* is_dest_reg */
12988 0, /* is_pc_relative */
12989 0, /* rightshift */
12990 create_SrcBDest_Y2, /* insert */
12991 get_SrcBDest_Y2 /* extract */
12992 }, 2315 },
12993 { 2316 {
12994 TILE_OP_TYPE_REGISTER, /* type */ 2317 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
12995 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2318 6, 0, 1, 1, 0, 0,
12996 6, /* num_bits */ 2319 create_SrcA_X1, get_SrcA_X1
12997 0, /* is_signed */
12998 1, /* is_src_reg */
12999 1, /* is_dest_reg */
13000 0, /* is_pc_relative */
13001 0, /* rightshift */
13002 create_SrcA_X1, /* insert */
13003 get_SrcA_X1 /* extract */
13004 }, 2320 },
13005 { 2321 {
13006 TILE_OP_TYPE_SPR, /* type */ 2322 TILE_OP_TYPE_SPR, BFD_RELOC(TILE_MF_IMM15_X1),
13007 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MF_IMM15_X1), /* default_reloc */ 2323 15, 0, 0, 0, 0, 0,
13008 15, /* num_bits */ 2324 create_MF_Imm15_X1, get_MF_Imm15_X1
13009 0, /* is_signed */
13010 0, /* is_src_reg */
13011 0, /* is_dest_reg */
13012 0, /* is_pc_relative */
13013 0, /* rightshift */
13014 create_MF_Imm15_X1, /* insert */
13015 get_MF_Imm15_X1 /* extract */
13016 }, 2325 },
13017 { 2326 {
13018 TILE_OP_TYPE_IMMEDIATE, /* type */ 2327 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMSTART_X0),
13019 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMSTART_X0), /* default_reloc */ 2328 5, 0, 0, 0, 0, 0,
13020 5, /* num_bits */ 2329 create_MMStart_X0, get_MMStart_X0
13021 0, /* is_signed */
13022 0, /* is_src_reg */
13023 0, /* is_dest_reg */
13024 0, /* is_pc_relative */
13025 0, /* rightshift */
13026 create_MMStart_X0, /* insert */
13027 get_MMStart_X0 /* extract */
13028 }, 2330 },
13029 { 2331 {
13030 TILE_OP_TYPE_IMMEDIATE, /* type */ 2332 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMEND_X0),
13031 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMEND_X0), /* default_reloc */ 2333 5, 0, 0, 0, 0, 0,
13032 5, /* num_bits */ 2334 create_MMEnd_X0, get_MMEnd_X0
13033 0, /* is_signed */
13034 0, /* is_src_reg */
13035 0, /* is_dest_reg */
13036 0, /* is_pc_relative */
13037 0, /* rightshift */
13038 create_MMEnd_X0, /* insert */
13039 get_MMEnd_X0 /* extract */
13040 }, 2335 },
13041 { 2336 {
13042 TILE_OP_TYPE_IMMEDIATE, /* type */ 2337 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMSTART_X1),
13043 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMSTART_X1), /* default_reloc */ 2338 5, 0, 0, 0, 0, 0,
13044 5, /* num_bits */ 2339 create_MMStart_X1, get_MMStart_X1
13045 0, /* is_signed */
13046 0, /* is_src_reg */
13047 0, /* is_dest_reg */
13048 0, /* is_pc_relative */
13049 0, /* rightshift */
13050 create_MMStart_X1, /* insert */
13051 get_MMStart_X1 /* extract */
13052 }, 2340 },
13053 { 2341 {
13054 TILE_OP_TYPE_IMMEDIATE, /* type */ 2342 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMEND_X1),
13055 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MMEND_X1), /* default_reloc */ 2343 5, 0, 0, 0, 0, 0,
13056 5, /* num_bits */ 2344 create_MMEnd_X1, get_MMEnd_X1
13057 0, /* is_signed */
13058 0, /* is_src_reg */
13059 0, /* is_dest_reg */
13060 0, /* is_pc_relative */
13061 0, /* rightshift */
13062 create_MMEnd_X1, /* insert */
13063 get_MMEnd_X1 /* extract */
13064 }, 2345 },
13065 { 2346 {
13066 TILE_OP_TYPE_SPR, /* type */ 2347 TILE_OP_TYPE_SPR, BFD_RELOC(TILE_MT_IMM15_X1),
13067 MAYBE_BFD_RELOC(BFD_RELOC_TILE_MT_IMM15_X1), /* default_reloc */ 2348 15, 0, 0, 0, 0, 0,
13068 15, /* num_bits */ 2349 create_MT_Imm15_X1, get_MT_Imm15_X1
13069 0, /* is_signed */
13070 0, /* is_src_reg */
13071 0, /* is_dest_reg */
13072 0, /* is_pc_relative */
13073 0, /* rightshift */
13074 create_MT_Imm15_X1, /* insert */
13075 get_MT_Imm15_X1 /* extract */
13076 }, 2350 },
13077 { 2351 {
13078 TILE_OP_TYPE_REGISTER, /* type */ 2352 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
13079 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2353 6, 0, 1, 1, 0, 0,
13080 6, /* num_bits */ 2354 create_Dest_Y0, get_Dest_Y0
13081 0, /* is_signed */
13082 1, /* is_src_reg */
13083 1, /* is_dest_reg */
13084 0, /* is_pc_relative */
13085 0, /* rightshift */
13086 create_Dest_Y0, /* insert */
13087 get_Dest_Y0 /* extract */
13088 }, 2355 },
13089 { 2356 {
13090 TILE_OP_TYPE_IMMEDIATE, /* type */ 2357 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_X0),
13091 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_X0), /* default_reloc */ 2358 5, 0, 0, 0, 0, 0,
13092 5, /* num_bits */ 2359 create_ShAmt_X0, get_ShAmt_X0
13093 0, /* is_signed */
13094 0, /* is_src_reg */
13095 0, /* is_dest_reg */
13096 0, /* is_pc_relative */
13097 0, /* rightshift */
13098 create_ShAmt_X0, /* insert */
13099 get_ShAmt_X0 /* extract */
13100 }, 2360 },
13101 { 2361 {
13102 TILE_OP_TYPE_IMMEDIATE, /* type */ 2362 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_X1),
13103 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_X1), /* default_reloc */ 2363 5, 0, 0, 0, 0, 0,
13104 5, /* num_bits */ 2364 create_ShAmt_X1, get_ShAmt_X1
13105 0, /* is_signed */
13106 0, /* is_src_reg */
13107 0, /* is_dest_reg */
13108 0, /* is_pc_relative */
13109 0, /* rightshift */
13110 create_ShAmt_X1, /* insert */
13111 get_ShAmt_X1 /* extract */
13112 }, 2365 },
13113 { 2366 {
13114 TILE_OP_TYPE_IMMEDIATE, /* type */ 2367 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_Y0),
13115 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_Y0), /* default_reloc */ 2368 5, 0, 0, 0, 0, 0,
13116 5, /* num_bits */ 2369 create_ShAmt_Y0, get_ShAmt_Y0
13117 0, /* is_signed */
13118 0, /* is_src_reg */
13119 0, /* is_dest_reg */
13120 0, /* is_pc_relative */
13121 0, /* rightshift */
13122 create_ShAmt_Y0, /* insert */
13123 get_ShAmt_Y0 /* extract */
13124 }, 2370 },
13125 { 2371 {
13126 TILE_OP_TYPE_IMMEDIATE, /* type */ 2372 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_Y1),
13127 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SHAMT_Y1), /* default_reloc */ 2373 5, 0, 0, 0, 0, 0,
13128 5, /* num_bits */ 2374 create_ShAmt_Y1, get_ShAmt_Y1
13129 0, /* is_signed */
13130 0, /* is_src_reg */
13131 0, /* is_dest_reg */
13132 0, /* is_pc_relative */
13133 0, /* rightshift */
13134 create_ShAmt_Y1, /* insert */
13135 get_ShAmt_Y1 /* extract */
13136 }, 2375 },
13137 { 2376 {
13138 TILE_OP_TYPE_REGISTER, /* type */ 2377 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
13139 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2378 6, 0, 1, 0, 0, 0,
13140 6, /* num_bits */ 2379 create_SrcBDest_Y2, get_SrcBDest_Y2
13141 0, /* is_signed */
13142 1, /* is_src_reg */
13143 0, /* is_dest_reg */
13144 0, /* is_pc_relative */
13145 0, /* rightshift */
13146 create_SrcBDest_Y2, /* insert */
13147 get_SrcBDest_Y2 /* extract */
13148 }, 2380 },
13149 { 2381 {
13150 TILE_OP_TYPE_IMMEDIATE, /* type */ 2382 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
13151 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2383 8, 1, 0, 0, 0, 0,
13152 8, /* num_bits */ 2384 create_Dest_Imm8_X1, get_Dest_Imm8_X1
13153 1, /* is_signed */
13154 0, /* is_src_reg */
13155 0, /* is_dest_reg */
13156 0, /* is_pc_relative */
13157 0, /* rightshift */
13158 create_Dest_Imm8_X1, /* insert */
13159 get_Dest_Imm8_X1 /* extract */
13160 }, 2385 },
13161 { 2386 {
13162 TILE_OP_TYPE_ADDRESS, /* type */ 2387 TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_SN_BROFF),
13163 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SN_BROFF), /* default_reloc */ 2388 10, 1, 0, 0, 1, TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES,
13164 10, /* num_bits */ 2389 create_BrOff_SN, get_BrOff_SN
13165 1, /* is_signed */
13166 0, /* is_src_reg */
13167 0, /* is_dest_reg */
13168 1, /* is_pc_relative */
13169 TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES, /* rightshift */
13170 create_BrOff_SN, /* insert */
13171 get_BrOff_SN /* extract */
13172 }, 2390 },
13173 { 2391 {
13174 TILE_OP_TYPE_IMMEDIATE, /* type */ 2392 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SN_UIMM8),
13175 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SN_UIMM8), /* default_reloc */ 2393 8, 0, 0, 0, 0, 0,
13176 8, /* num_bits */ 2394 create_Imm8_SN, get_Imm8_SN
13177 0, /* is_signed */
13178 0, /* is_src_reg */
13179 0, /* is_dest_reg */
13180 0, /* is_pc_relative */
13181 0, /* rightshift */
13182 create_Imm8_SN, /* insert */
13183 get_Imm8_SN /* extract */
13184 }, 2395 },
13185 { 2396 {
13186 TILE_OP_TYPE_IMMEDIATE, /* type */ 2397 TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SN_IMM8),
13187 MAYBE_BFD_RELOC(BFD_RELOC_TILE_SN_IMM8), /* default_reloc */ 2398 8, 1, 0, 0, 0, 0,
13188 8, /* num_bits */ 2399 create_Imm8_SN, get_Imm8_SN
13189 1, /* is_signed */
13190 0, /* is_src_reg */
13191 0, /* is_dest_reg */
13192 0, /* is_pc_relative */
13193 0, /* rightshift */
13194 create_Imm8_SN, /* insert */
13195 get_Imm8_SN /* extract */
13196 }, 2400 },
13197 { 2401 {
13198 TILE_OP_TYPE_REGISTER, /* type */ 2402 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
13199 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2403 2, 0, 0, 1, 0, 0,
13200 2, /* num_bits */ 2404 create_Dest_SN, get_Dest_SN
13201 0, /* is_signed */
13202 0, /* is_src_reg */
13203 1, /* is_dest_reg */
13204 0, /* is_pc_relative */
13205 0, /* rightshift */
13206 create_Dest_SN, /* insert */
13207 get_Dest_SN /* extract */
13208 }, 2405 },
13209 { 2406 {
13210 TILE_OP_TYPE_REGISTER, /* type */ 2407 TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE),
13211 MAYBE_BFD_RELOC(BFD_RELOC_NONE), /* default_reloc */ 2408 2, 0, 1, 0, 0, 0,
13212 2, /* num_bits */ 2409 create_Src_SN, get_Src_SN
13213 0, /* is_signed */
13214 1, /* is_src_reg */
13215 0, /* is_dest_reg */
13216 0, /* is_pc_relative */
13217 0, /* rightshift */
13218 create_Src_SN, /* insert */
13219 get_Src_SN /* extract */
13220 } 2410 }
13221}; 2411};
13222 2412
13223const struct tile_spr tile_sprs[] = {
13224 { 0, "MPL_ITLB_MISS_SET_0" },
13225 { 1, "MPL_ITLB_MISS_SET_1" },
13226 { 2, "MPL_ITLB_MISS_SET_2" },
13227 { 3, "MPL_ITLB_MISS_SET_3" },
13228 { 4, "MPL_ITLB_MISS" },
13229 { 256, "ITLB_CURRENT_0" },
13230 { 257, "ITLB_CURRENT_1" },
13231 { 258, "ITLB_CURRENT_2" },
13232 { 259, "ITLB_CURRENT_3" },
13233 { 260, "ITLB_INDEX" },
13234 { 261, "ITLB_MATCH_0" },
13235 { 262, "ITLB_PR" },
13236 { 263, "NUMBER_ITLB" },
13237 { 264, "REPLACEMENT_ITLB" },
13238 { 265, "WIRED_ITLB" },
13239 { 266, "ITLB_PERF" },
13240 { 512, "MPL_MEM_ERROR_SET_0" },
13241 { 513, "MPL_MEM_ERROR_SET_1" },
13242 { 514, "MPL_MEM_ERROR_SET_2" },
13243 { 515, "MPL_MEM_ERROR_SET_3" },
13244 { 516, "MPL_MEM_ERROR" },
13245 { 517, "L1_I_ERROR" },
13246 { 518, "MEM_ERROR_CBOX_ADDR" },
13247 { 519, "MEM_ERROR_CBOX_STATUS" },
13248 { 520, "MEM_ERROR_ENABLE" },
13249 { 521, "MEM_ERROR_MBOX_ADDR" },
13250 { 522, "MEM_ERROR_MBOX_STATUS" },
13251 { 523, "SNIC_ERROR_LOG_STATUS" },
13252 { 524, "SNIC_ERROR_LOG_VA" },
13253 { 525, "XDN_DEMUX_ERROR" },
13254 { 1024, "MPL_ILL_SET_0" },
13255 { 1025, "MPL_ILL_SET_1" },
13256 { 1026, "MPL_ILL_SET_2" },
13257 { 1027, "MPL_ILL_SET_3" },
13258 { 1028, "MPL_ILL" },
13259 { 1536, "MPL_GPV_SET_0" },
13260 { 1537, "MPL_GPV_SET_1" },
13261 { 1538, "MPL_GPV_SET_2" },
13262 { 1539, "MPL_GPV_SET_3" },
13263 { 1540, "MPL_GPV" },
13264 { 1541, "GPV_REASON" },
13265 { 2048, "MPL_SN_ACCESS_SET_0" },
13266 { 2049, "MPL_SN_ACCESS_SET_1" },
13267 { 2050, "MPL_SN_ACCESS_SET_2" },
13268 { 2051, "MPL_SN_ACCESS_SET_3" },
13269 { 2052, "MPL_SN_ACCESS" },
13270 { 2053, "SNCTL" },
13271 { 2054, "SNFIFO_DATA" },
13272 { 2055, "SNFIFO_SEL" },
13273 { 2056, "SNIC_INVADDR" },
13274 { 2057, "SNISTATE" },
13275 { 2058, "SNOSTATE" },
13276 { 2059, "SNPC" },
13277 { 2060, "SNSTATIC" },
13278 { 2304, "SN_DATA_AVAIL" },
13279 { 2560, "MPL_IDN_ACCESS_SET_0" },
13280 { 2561, "MPL_IDN_ACCESS_SET_1" },
13281 { 2562, "MPL_IDN_ACCESS_SET_2" },
13282 { 2563, "MPL_IDN_ACCESS_SET_3" },
13283 { 2564, "MPL_IDN_ACCESS" },
13284 { 2565, "IDN_DEMUX_CA_COUNT" },
13285 { 2566, "IDN_DEMUX_COUNT_0" },
13286 { 2567, "IDN_DEMUX_COUNT_1" },
13287 { 2568, "IDN_DEMUX_CTL" },
13288 { 2569, "IDN_DEMUX_CURR_TAG" },
13289 { 2570, "IDN_DEMUX_QUEUE_SEL" },
13290 { 2571, "IDN_DEMUX_STATUS" },
13291 { 2572, "IDN_DEMUX_WRITE_FIFO" },
13292 { 2573, "IDN_DEMUX_WRITE_QUEUE" },
13293 { 2574, "IDN_PENDING" },
13294 { 2575, "IDN_SP_FIFO_DATA" },
13295 { 2576, "IDN_SP_FIFO_SEL" },
13296 { 2577, "IDN_SP_FREEZE" },
13297 { 2578, "IDN_SP_STATE" },
13298 { 2579, "IDN_TAG_0" },
13299 { 2580, "IDN_TAG_1" },
13300 { 2581, "IDN_TAG_VALID" },
13301 { 2582, "IDN_TILE_COORD" },
13302 { 2816, "IDN_CA_DATA" },
13303 { 2817, "IDN_CA_REM" },
13304 { 2818, "IDN_CA_TAG" },
13305 { 2819, "IDN_DATA_AVAIL" },
13306 { 3072, "MPL_UDN_ACCESS_SET_0" },
13307 { 3073, "MPL_UDN_ACCESS_SET_1" },
13308 { 3074, "MPL_UDN_ACCESS_SET_2" },
13309 { 3075, "MPL_UDN_ACCESS_SET_3" },
13310 { 3076, "MPL_UDN_ACCESS" },
13311 { 3077, "UDN_DEMUX_CA_COUNT" },
13312 { 3078, "UDN_DEMUX_COUNT_0" },
13313 { 3079, "UDN_DEMUX_COUNT_1" },
13314 { 3080, "UDN_DEMUX_COUNT_2" },
13315 { 3081, "UDN_DEMUX_COUNT_3" },
13316 { 3082, "UDN_DEMUX_CTL" },
13317 { 3083, "UDN_DEMUX_CURR_TAG" },
13318 { 3084, "UDN_DEMUX_QUEUE_SEL" },
13319 { 3085, "UDN_DEMUX_STATUS" },
13320 { 3086, "UDN_DEMUX_WRITE_FIFO" },
13321 { 3087, "UDN_DEMUX_WRITE_QUEUE" },
13322 { 3088, "UDN_PENDING" },
13323 { 3089, "UDN_SP_FIFO_DATA" },
13324 { 3090, "UDN_SP_FIFO_SEL" },
13325 { 3091, "UDN_SP_FREEZE" },
13326 { 3092, "UDN_SP_STATE" },
13327 { 3093, "UDN_TAG_0" },
13328 { 3094, "UDN_TAG_1" },
13329 { 3095, "UDN_TAG_2" },
13330 { 3096, "UDN_TAG_3" },
13331 { 3097, "UDN_TAG_VALID" },
13332 { 3098, "UDN_TILE_COORD" },
13333 { 3328, "UDN_CA_DATA" },
13334 { 3329, "UDN_CA_REM" },
13335 { 3330, "UDN_CA_TAG" },
13336 { 3331, "UDN_DATA_AVAIL" },
13337 { 3584, "MPL_IDN_REFILL_SET_0" },
13338 { 3585, "MPL_IDN_REFILL_SET_1" },
13339 { 3586, "MPL_IDN_REFILL_SET_2" },
13340 { 3587, "MPL_IDN_REFILL_SET_3" },
13341 { 3588, "MPL_IDN_REFILL" },
13342 { 3589, "IDN_REFILL_EN" },
13343 { 4096, "MPL_UDN_REFILL_SET_0" },
13344 { 4097, "MPL_UDN_REFILL_SET_1" },
13345 { 4098, "MPL_UDN_REFILL_SET_2" },
13346 { 4099, "MPL_UDN_REFILL_SET_3" },
13347 { 4100, "MPL_UDN_REFILL" },
13348 { 4101, "UDN_REFILL_EN" },
13349 { 4608, "MPL_IDN_COMPLETE_SET_0" },
13350 { 4609, "MPL_IDN_COMPLETE_SET_1" },
13351 { 4610, "MPL_IDN_COMPLETE_SET_2" },
13352 { 4611, "MPL_IDN_COMPLETE_SET_3" },
13353 { 4612, "MPL_IDN_COMPLETE" },
13354 { 4613, "IDN_REMAINING" },
13355 { 5120, "MPL_UDN_COMPLETE_SET_0" },
13356 { 5121, "MPL_UDN_COMPLETE_SET_1" },
13357 { 5122, "MPL_UDN_COMPLETE_SET_2" },
13358 { 5123, "MPL_UDN_COMPLETE_SET_3" },
13359 { 5124, "MPL_UDN_COMPLETE" },
13360 { 5125, "UDN_REMAINING" },
13361 { 5632, "MPL_SWINT_3_SET_0" },
13362 { 5633, "MPL_SWINT_3_SET_1" },
13363 { 5634, "MPL_SWINT_3_SET_2" },
13364 { 5635, "MPL_SWINT_3_SET_3" },
13365 { 5636, "MPL_SWINT_3" },
13366 { 6144, "MPL_SWINT_2_SET_0" },
13367 { 6145, "MPL_SWINT_2_SET_1" },
13368 { 6146, "MPL_SWINT_2_SET_2" },
13369 { 6147, "MPL_SWINT_2_SET_3" },
13370 { 6148, "MPL_SWINT_2" },
13371 { 6656, "MPL_SWINT_1_SET_0" },
13372 { 6657, "MPL_SWINT_1_SET_1" },
13373 { 6658, "MPL_SWINT_1_SET_2" },
13374 { 6659, "MPL_SWINT_1_SET_3" },
13375 { 6660, "MPL_SWINT_1" },
13376 { 7168, "MPL_SWINT_0_SET_0" },
13377 { 7169, "MPL_SWINT_0_SET_1" },
13378 { 7170, "MPL_SWINT_0_SET_2" },
13379 { 7171, "MPL_SWINT_0_SET_3" },
13380 { 7172, "MPL_SWINT_0" },
13381 { 7680, "MPL_UNALIGN_DATA_SET_0" },
13382 { 7681, "MPL_UNALIGN_DATA_SET_1" },
13383 { 7682, "MPL_UNALIGN_DATA_SET_2" },
13384 { 7683, "MPL_UNALIGN_DATA_SET_3" },
13385 { 7684, "MPL_UNALIGN_DATA" },
13386 { 8192, "MPL_DTLB_MISS_SET_0" },
13387 { 8193, "MPL_DTLB_MISS_SET_1" },
13388 { 8194, "MPL_DTLB_MISS_SET_2" },
13389 { 8195, "MPL_DTLB_MISS_SET_3" },
13390 { 8196, "MPL_DTLB_MISS" },
13391 { 8448, "AER_0" },
13392 { 8449, "AER_1" },
13393 { 8450, "DTLB_BAD_ADDR" },
13394 { 8451, "DTLB_BAD_ADDR_REASON" },
13395 { 8452, "DTLB_CURRENT_0" },
13396 { 8453, "DTLB_CURRENT_1" },
13397 { 8454, "DTLB_CURRENT_2" },
13398 { 8455, "DTLB_CURRENT_3" },
13399 { 8456, "DTLB_INDEX" },
13400 { 8457, "DTLB_MATCH_0" },
13401 { 8458, "NUMBER_DTLB" },
13402 { 8459, "PHYSICAL_MEMORY_MODE" },
13403 { 8460, "REPLACEMENT_DTLB" },
13404 { 8461, "WIRED_DTLB" },
13405 { 8462, "CACHE_RED_WAY_OVERRIDDEN" },
13406 { 8463, "DTLB_PERF" },
13407 { 8704, "MPL_DTLB_ACCESS_SET_0" },
13408 { 8705, "MPL_DTLB_ACCESS_SET_1" },
13409 { 8706, "MPL_DTLB_ACCESS_SET_2" },
13410 { 8707, "MPL_DTLB_ACCESS_SET_3" },
13411 { 8708, "MPL_DTLB_ACCESS" },
13412 { 9216, "MPL_DMATLB_MISS_SET_0" },
13413 { 9217, "MPL_DMATLB_MISS_SET_1" },
13414 { 9218, "MPL_DMATLB_MISS_SET_2" },
13415 { 9219, "MPL_DMATLB_MISS_SET_3" },
13416 { 9220, "MPL_DMATLB_MISS" },
13417 { 9472, "DMA_BAD_ADDR" },
13418 { 9473, "DMA_STATUS" },
13419 { 9728, "MPL_DMATLB_ACCESS_SET_0" },
13420 { 9729, "MPL_DMATLB_ACCESS_SET_1" },
13421 { 9730, "MPL_DMATLB_ACCESS_SET_2" },
13422 { 9731, "MPL_DMATLB_ACCESS_SET_3" },
13423 { 9732, "MPL_DMATLB_ACCESS" },
13424 { 10240, "MPL_SNITLB_MISS_SET_0" },
13425 { 10241, "MPL_SNITLB_MISS_SET_1" },
13426 { 10242, "MPL_SNITLB_MISS_SET_2" },
13427 { 10243, "MPL_SNITLB_MISS_SET_3" },
13428 { 10244, "MPL_SNITLB_MISS" },
13429 { 10245, "NUMBER_SNITLB" },
13430 { 10246, "REPLACEMENT_SNITLB" },
13431 { 10247, "SNITLB_CURRENT_0" },
13432 { 10248, "SNITLB_CURRENT_1" },
13433 { 10249, "SNITLB_CURRENT_2" },
13434 { 10250, "SNITLB_CURRENT_3" },
13435 { 10251, "SNITLB_INDEX" },
13436 { 10252, "SNITLB_MATCH_0" },
13437 { 10253, "SNITLB_PR" },
13438 { 10254, "WIRED_SNITLB" },
13439 { 10255, "SNITLB_STATUS" },
13440 { 10752, "MPL_SN_NOTIFY_SET_0" },
13441 { 10753, "MPL_SN_NOTIFY_SET_1" },
13442 { 10754, "MPL_SN_NOTIFY_SET_2" },
13443 { 10755, "MPL_SN_NOTIFY_SET_3" },
13444 { 10756, "MPL_SN_NOTIFY" },
13445 { 10757, "SN_NOTIFY_STATUS" },
13446 { 11264, "MPL_SN_FIREWALL_SET_0" },
13447 { 11265, "MPL_SN_FIREWALL_SET_1" },
13448 { 11266, "MPL_SN_FIREWALL_SET_2" },
13449 { 11267, "MPL_SN_FIREWALL_SET_3" },
13450 { 11268, "MPL_SN_FIREWALL" },
13451 { 11269, "SN_DIRECTION_PROTECT" },
13452 { 11776, "MPL_IDN_FIREWALL_SET_0" },
13453 { 11777, "MPL_IDN_FIREWALL_SET_1" },
13454 { 11778, "MPL_IDN_FIREWALL_SET_2" },
13455 { 11779, "MPL_IDN_FIREWALL_SET_3" },
13456 { 11780, "MPL_IDN_FIREWALL" },
13457 { 11781, "IDN_DIRECTION_PROTECT" },
13458 { 12288, "MPL_UDN_FIREWALL_SET_0" },
13459 { 12289, "MPL_UDN_FIREWALL_SET_1" },
13460 { 12290, "MPL_UDN_FIREWALL_SET_2" },
13461 { 12291, "MPL_UDN_FIREWALL_SET_3" },
13462 { 12292, "MPL_UDN_FIREWALL" },
13463 { 12293, "UDN_DIRECTION_PROTECT" },
13464 { 12800, "MPL_TILE_TIMER_SET_0" },
13465 { 12801, "MPL_TILE_TIMER_SET_1" },
13466 { 12802, "MPL_TILE_TIMER_SET_2" },
13467 { 12803, "MPL_TILE_TIMER_SET_3" },
13468 { 12804, "MPL_TILE_TIMER" },
13469 { 12805, "TILE_TIMER_CONTROL" },
13470 { 13312, "MPL_IDN_TIMER_SET_0" },
13471 { 13313, "MPL_IDN_TIMER_SET_1" },
13472 { 13314, "MPL_IDN_TIMER_SET_2" },
13473 { 13315, "MPL_IDN_TIMER_SET_3" },
13474 { 13316, "MPL_IDN_TIMER" },
13475 { 13317, "IDN_DEADLOCK_COUNT" },
13476 { 13318, "IDN_DEADLOCK_TIMEOUT" },
13477 { 13824, "MPL_UDN_TIMER_SET_0" },
13478 { 13825, "MPL_UDN_TIMER_SET_1" },
13479 { 13826, "MPL_UDN_TIMER_SET_2" },
13480 { 13827, "MPL_UDN_TIMER_SET_3" },
13481 { 13828, "MPL_UDN_TIMER" },
13482 { 13829, "UDN_DEADLOCK_COUNT" },
13483 { 13830, "UDN_DEADLOCK_TIMEOUT" },
13484 { 14336, "MPL_DMA_NOTIFY_SET_0" },
13485 { 14337, "MPL_DMA_NOTIFY_SET_1" },
13486 { 14338, "MPL_DMA_NOTIFY_SET_2" },
13487 { 14339, "MPL_DMA_NOTIFY_SET_3" },
13488 { 14340, "MPL_DMA_NOTIFY" },
13489 { 14592, "DMA_BYTE" },
13490 { 14593, "DMA_CHUNK_SIZE" },
13491 { 14594, "DMA_CTR" },
13492 { 14595, "DMA_DST_ADDR" },
13493 { 14596, "DMA_DST_CHUNK_ADDR" },
13494 { 14597, "DMA_SRC_ADDR" },
13495 { 14598, "DMA_SRC_CHUNK_ADDR" },
13496 { 14599, "DMA_STRIDE" },
13497 { 14600, "DMA_USER_STATUS" },
13498 { 14848, "MPL_IDN_CA_SET_0" },
13499 { 14849, "MPL_IDN_CA_SET_1" },
13500 { 14850, "MPL_IDN_CA_SET_2" },
13501 { 14851, "MPL_IDN_CA_SET_3" },
13502 { 14852, "MPL_IDN_CA" },
13503 { 15360, "MPL_UDN_CA_SET_0" },
13504 { 15361, "MPL_UDN_CA_SET_1" },
13505 { 15362, "MPL_UDN_CA_SET_2" },
13506 { 15363, "MPL_UDN_CA_SET_3" },
13507 { 15364, "MPL_UDN_CA" },
13508 { 15872, "MPL_IDN_AVAIL_SET_0" },
13509 { 15873, "MPL_IDN_AVAIL_SET_1" },
13510 { 15874, "MPL_IDN_AVAIL_SET_2" },
13511 { 15875, "MPL_IDN_AVAIL_SET_3" },
13512 { 15876, "MPL_IDN_AVAIL" },
13513 { 15877, "IDN_AVAIL_EN" },
13514 { 16384, "MPL_UDN_AVAIL_SET_0" },
13515 { 16385, "MPL_UDN_AVAIL_SET_1" },
13516 { 16386, "MPL_UDN_AVAIL_SET_2" },
13517 { 16387, "MPL_UDN_AVAIL_SET_3" },
13518 { 16388, "MPL_UDN_AVAIL" },
13519 { 16389, "UDN_AVAIL_EN" },
13520 { 16896, "MPL_PERF_COUNT_SET_0" },
13521 { 16897, "MPL_PERF_COUNT_SET_1" },
13522 { 16898, "MPL_PERF_COUNT_SET_2" },
13523 { 16899, "MPL_PERF_COUNT_SET_3" },
13524 { 16900, "MPL_PERF_COUNT" },
13525 { 16901, "PERF_COUNT_0" },
13526 { 16902, "PERF_COUNT_1" },
13527 { 16903, "PERF_COUNT_CTL" },
13528 { 16904, "PERF_COUNT_STS" },
13529 { 16905, "WATCH_CTL" },
13530 { 16906, "WATCH_MASK" },
13531 { 16907, "WATCH_VAL" },
13532 { 16912, "PERF_COUNT_DN_CTL" },
13533 { 17408, "MPL_INTCTRL_3_SET_0" },
13534 { 17409, "MPL_INTCTRL_3_SET_1" },
13535 { 17410, "MPL_INTCTRL_3_SET_2" },
13536 { 17411, "MPL_INTCTRL_3_SET_3" },
13537 { 17412, "MPL_INTCTRL_3" },
13538 { 17413, "EX_CONTEXT_3_0" },
13539 { 17414, "EX_CONTEXT_3_1" },
13540 { 17415, "INTERRUPT_MASK_3_0" },
13541 { 17416, "INTERRUPT_MASK_3_1" },
13542 { 17417, "INTERRUPT_MASK_RESET_3_0" },
13543 { 17418, "INTERRUPT_MASK_RESET_3_1" },
13544 { 17419, "INTERRUPT_MASK_SET_3_0" },
13545 { 17420, "INTERRUPT_MASK_SET_3_1" },
13546 { 17432, "INTCTRL_3_STATUS" },
13547 { 17664, "SYSTEM_SAVE_3_0" },
13548 { 17665, "SYSTEM_SAVE_3_1" },
13549 { 17666, "SYSTEM_SAVE_3_2" },
13550 { 17667, "SYSTEM_SAVE_3_3" },
13551 { 17920, "MPL_INTCTRL_2_SET_0" },
13552 { 17921, "MPL_INTCTRL_2_SET_1" },
13553 { 17922, "MPL_INTCTRL_2_SET_2" },
13554 { 17923, "MPL_INTCTRL_2_SET_3" },
13555 { 17924, "MPL_INTCTRL_2" },
13556 { 17925, "EX_CONTEXT_2_0" },
13557 { 17926, "EX_CONTEXT_2_1" },
13558 { 17927, "INTCTRL_2_STATUS" },
13559 { 17928, "INTERRUPT_MASK_2_0" },
13560 { 17929, "INTERRUPT_MASK_2_1" },
13561 { 17930, "INTERRUPT_MASK_RESET_2_0" },
13562 { 17931, "INTERRUPT_MASK_RESET_2_1" },
13563 { 17932, "INTERRUPT_MASK_SET_2_0" },
13564 { 17933, "INTERRUPT_MASK_SET_2_1" },
13565 { 18176, "SYSTEM_SAVE_2_0" },
13566 { 18177, "SYSTEM_SAVE_2_1" },
13567 { 18178, "SYSTEM_SAVE_2_2" },
13568 { 18179, "SYSTEM_SAVE_2_3" },
13569 { 18432, "MPL_INTCTRL_1_SET_0" },
13570 { 18433, "MPL_INTCTRL_1_SET_1" },
13571 { 18434, "MPL_INTCTRL_1_SET_2" },
13572 { 18435, "MPL_INTCTRL_1_SET_3" },
13573 { 18436, "MPL_INTCTRL_1" },
13574 { 18437, "EX_CONTEXT_1_0" },
13575 { 18438, "EX_CONTEXT_1_1" },
13576 { 18439, "INTCTRL_1_STATUS" },
13577 { 18440, "INTCTRL_3_STATUS_REV0" },
13578 { 18441, "INTERRUPT_MASK_1_0" },
13579 { 18442, "INTERRUPT_MASK_1_1" },
13580 { 18443, "INTERRUPT_MASK_RESET_1_0" },
13581 { 18444, "INTERRUPT_MASK_RESET_1_1" },
13582 { 18445, "INTERRUPT_MASK_SET_1_0" },
13583 { 18446, "INTERRUPT_MASK_SET_1_1" },
13584 { 18688, "SYSTEM_SAVE_1_0" },
13585 { 18689, "SYSTEM_SAVE_1_1" },
13586 { 18690, "SYSTEM_SAVE_1_2" },
13587 { 18691, "SYSTEM_SAVE_1_3" },
13588 { 18944, "MPL_INTCTRL_0_SET_0" },
13589 { 18945, "MPL_INTCTRL_0_SET_1" },
13590 { 18946, "MPL_INTCTRL_0_SET_2" },
13591 { 18947, "MPL_INTCTRL_0_SET_3" },
13592 { 18948, "MPL_INTCTRL_0" },
13593 { 18949, "EX_CONTEXT_0_0" },
13594 { 18950, "EX_CONTEXT_0_1" },
13595 { 18951, "INTCTRL_0_STATUS" },
13596 { 18952, "INTERRUPT_MASK_0_0" },
13597 { 18953, "INTERRUPT_MASK_0_1" },
13598 { 18954, "INTERRUPT_MASK_RESET_0_0" },
13599 { 18955, "INTERRUPT_MASK_RESET_0_1" },
13600 { 18956, "INTERRUPT_MASK_SET_0_0" },
13601 { 18957, "INTERRUPT_MASK_SET_0_1" },
13602 { 19200, "SYSTEM_SAVE_0_0" },
13603 { 19201, "SYSTEM_SAVE_0_1" },
13604 { 19202, "SYSTEM_SAVE_0_2" },
13605 { 19203, "SYSTEM_SAVE_0_3" },
13606 { 19456, "MPL_BOOT_ACCESS_SET_0" },
13607 { 19457, "MPL_BOOT_ACCESS_SET_1" },
13608 { 19458, "MPL_BOOT_ACCESS_SET_2" },
13609 { 19459, "MPL_BOOT_ACCESS_SET_3" },
13610 { 19460, "MPL_BOOT_ACCESS" },
13611 { 19461, "CBOX_CACHEASRAM_CONFIG" },
13612 { 19462, "CBOX_CACHE_CONFIG" },
13613 { 19463, "CBOX_MMAP_0" },
13614 { 19464, "CBOX_MMAP_1" },
13615 { 19465, "CBOX_MMAP_2" },
13616 { 19466, "CBOX_MMAP_3" },
13617 { 19467, "CBOX_MSR" },
13618 { 19468, "CBOX_SRC_ID" },
13619 { 19469, "CYCLE_HIGH_MODIFY" },
13620 { 19470, "CYCLE_LOW_MODIFY" },
13621 { 19471, "DIAG_BCST_CTL" },
13622 { 19472, "DIAG_BCST_MASK" },
13623 { 19473, "DIAG_BCST_TRIGGER" },
13624 { 19474, "DIAG_MUX_CTL" },
13625 { 19475, "DIAG_TRACE_CTL" },
13626 { 19476, "DIAG_TRACE_STS" },
13627 { 19477, "IDN_DEMUX_BUF_THRESH" },
13628 { 19478, "SBOX_CONFIG" },
13629 { 19479, "TILE_COORD" },
13630 { 19480, "UDN_DEMUX_BUF_THRESH" },
13631 { 19481, "CBOX_HOME_MAP_ADDR" },
13632 { 19482, "CBOX_HOME_MAP_DATA" },
13633 { 19483, "CBOX_MSR1" },
13634 { 19484, "BIG_ENDIAN_CONFIG" },
13635 { 19485, "MEM_STRIPE_CONFIG" },
13636 { 19486, "DIAG_TRACE_WAY" },
13637 { 19487, "VDN_SNOOP_SHIM_CTL" },
13638 { 19488, "PERF_COUNT_PLS" },
13639 { 19489, "DIAG_TRACE_DATA" },
13640 { 19712, "I_AER_0" },
13641 { 19713, "I_AER_1" },
13642 { 19714, "I_PHYSICAL_MEMORY_MODE" },
13643 { 19968, "MPL_WORLD_ACCESS_SET_0" },
13644 { 19969, "MPL_WORLD_ACCESS_SET_1" },
13645 { 19970, "MPL_WORLD_ACCESS_SET_2" },
13646 { 19971, "MPL_WORLD_ACCESS_SET_3" },
13647 { 19972, "MPL_WORLD_ACCESS" },
13648 { 19973, "SIM_SOCKET" },
13649 { 19974, "CYCLE_HIGH" },
13650 { 19975, "CYCLE_LOW" },
13651 { 19976, "DONE" },
13652 { 19977, "FAIL" },
13653 { 19978, "INTERRUPT_CRITICAL_SECTION" },
13654 { 19979, "PASS" },
13655 { 19980, "SIM_CONTROL" },
13656 { 19981, "EVENT_BEGIN" },
13657 { 19982, "EVENT_END" },
13658 { 19983, "TILE_WRITE_PENDING" },
13659 { 19984, "TILE_RTF_HWM" },
13660 { 20224, "PROC_STATUS" },
13661 { 20225, "STATUS_SATURATE" },
13662 { 20480, "MPL_I_ASID_SET_0" },
13663 { 20481, "MPL_I_ASID_SET_1" },
13664 { 20482, "MPL_I_ASID_SET_2" },
13665 { 20483, "MPL_I_ASID_SET_3" },
13666 { 20484, "MPL_I_ASID" },
13667 { 20485, "I_ASID" },
13668 { 20992, "MPL_D_ASID_SET_0" },
13669 { 20993, "MPL_D_ASID_SET_1" },
13670 { 20994, "MPL_D_ASID_SET_2" },
13671 { 20995, "MPL_D_ASID_SET_3" },
13672 { 20996, "MPL_D_ASID" },
13673 { 20997, "D_ASID" },
13674 { 21504, "MPL_DMA_ASID_SET_0" },
13675 { 21505, "MPL_DMA_ASID_SET_1" },
13676 { 21506, "MPL_DMA_ASID_SET_2" },
13677 { 21507, "MPL_DMA_ASID_SET_3" },
13678 { 21508, "MPL_DMA_ASID" },
13679 { 21509, "DMA_ASID" },
13680 { 22016, "MPL_SNI_ASID_SET_0" },
13681 { 22017, "MPL_SNI_ASID_SET_1" },
13682 { 22018, "MPL_SNI_ASID_SET_2" },
13683 { 22019, "MPL_SNI_ASID_SET_3" },
13684 { 22020, "MPL_SNI_ASID" },
13685 { 22021, "SNI_ASID" },
13686 { 22528, "MPL_DMA_CPL_SET_0" },
13687 { 22529, "MPL_DMA_CPL_SET_1" },
13688 { 22530, "MPL_DMA_CPL_SET_2" },
13689 { 22531, "MPL_DMA_CPL_SET_3" },
13690 { 22532, "MPL_DMA_CPL" },
13691 { 23040, "MPL_SN_CPL_SET_0" },
13692 { 23041, "MPL_SN_CPL_SET_1" },
13693 { 23042, "MPL_SN_CPL_SET_2" },
13694 { 23043, "MPL_SN_CPL_SET_3" },
13695 { 23044, "MPL_SN_CPL" },
13696 { 23552, "MPL_DOUBLE_FAULT_SET_0" },
13697 { 23553, "MPL_DOUBLE_FAULT_SET_1" },
13698 { 23554, "MPL_DOUBLE_FAULT_SET_2" },
13699 { 23555, "MPL_DOUBLE_FAULT_SET_3" },
13700 { 23556, "MPL_DOUBLE_FAULT" },
13701 { 23557, "LAST_INTERRUPT_REASON" },
13702 { 24064, "MPL_SN_STATIC_ACCESS_SET_0" },
13703 { 24065, "MPL_SN_STATIC_ACCESS_SET_1" },
13704 { 24066, "MPL_SN_STATIC_ACCESS_SET_2" },
13705 { 24067, "MPL_SN_STATIC_ACCESS_SET_3" },
13706 { 24068, "MPL_SN_STATIC_ACCESS" },
13707 { 24069, "SN_STATIC_CTL" },
13708 { 24070, "SN_STATIC_FIFO_DATA" },
13709 { 24071, "SN_STATIC_FIFO_SEL" },
13710 { 24073, "SN_STATIC_ISTATE" },
13711 { 24074, "SN_STATIC_OSTATE" },
13712 { 24076, "SN_STATIC_STATIC" },
13713 { 24320, "SN_STATIC_DATA_AVAIL" },
13714 { 24576, "MPL_AUX_PERF_COUNT_SET_0" },
13715 { 24577, "MPL_AUX_PERF_COUNT_SET_1" },
13716 { 24578, "MPL_AUX_PERF_COUNT_SET_2" },
13717 { 24579, "MPL_AUX_PERF_COUNT_SET_3" },
13718 { 24580, "MPL_AUX_PERF_COUNT" },
13719 { 24581, "AUX_PERF_COUNT_0" },
13720 { 24582, "AUX_PERF_COUNT_1" },
13721 { 24583, "AUX_PERF_COUNT_CTL" },
13722 { 24584, "AUX_PERF_COUNT_STS" },
13723};
13724
13725const int tile_num_sprs = 499;
13726
13727
13728 2413
13729 2414
13730/* Canonical name of each register. */
13731const char *const tile_register_names[] =
13732{
13733 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
13734 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
13735 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
13736 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
13737 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
13738 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
13739 "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr",
13740 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero"
13741};
13742
13743 2415
13744/* Given a set of bundle bits and the lookup FSM for a specific pipe, 2416/* Given a set of bundle bits and the lookup FSM for a specific pipe,
13745 * returns which instruction the bundle contains in that pipe. 2417 * returns which instruction the bundle contains in that pipe.
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-02 18:30:38 -0400