aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorNicolas Ferre <nicolas.ferre@atmel.com>2009-06-26 10:36:58 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-27 06:05:22 -0400
commit789b23bc40a67d9a19bedc2655c6bcab79bcabd8 (patch)
tree01b47924223763d33034ca7d6ec85f102fd5fcc0 /arch
parentfddcc0ae58edefeb7ac1e460411d7dfbe8ebdacc (diff)
[ARM] 5572/1: at91: Support for at91sam9g45 series: core chip & board support
Here are the at91 specific files dedicated to the at91sam9g45 series. They mimic the traditional at91 way of managing chips & boards. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. In the future, the main board for this 9g45 series will be the AT91SAM9M10G45-EK (I choose this last name for the board file). Simple drivers are enabled in _devices and board- files. Newer peripheral support will be added in future patches. Incuded peripherals support (for now): - USART - SPI - Ethernet - NAND flash - LCD - gpio/joystick/buttons - leds and pwm Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-at91/Kconfig26
-rw-r--r--arch/arm/mach-at91/Makefile4
-rw-r--r--arch/arm/mach-at91/Makefile.boot4
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c360
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c1230
-rw-r--r--arch/arm/mach-at91/board-sam9m10g45ek.c389
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h8
8 files changed, 2020 insertions, 3 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 323b47f2b52f..22309ba97fa6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -41,6 +41,12 @@ config ARCH_AT91SAM9G20
41 select GENERIC_TIME 41 select GENERIC_TIME
42 select GENERIC_CLOCKEVENTS 42 select GENERIC_CLOCKEVENTS
43 43
44config ARCH_AT91SAM9G45
45 bool "AT91SAM9G45"
46 select CPU_ARM926T
47 select GENERIC_TIME
48 select GENERIC_CLOCKEVENTS
49
44config ARCH_AT91CAP9 50config ARCH_AT91CAP9
45 bool "AT91CAP9" 51 bool "AT91CAP9"
46 select CPU_ARM926T 52 select CPU_ARM926T
@@ -280,6 +286,22 @@ endif
280 286
281# ---------------------------------------------------------- 287# ----------------------------------------------------------
282 288
289if ARCH_AT91SAM9G45
290
291comment "AT91SAM9G45 Board Type"
292
293config MACH_AT91SAM9G45EKES
294 bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
295 depends on ARCH_AT91SAM9G45
296 help
297 Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
298 "ES" at the end of the name means that this board is an
299 Engineering Sample.
300
301endif
302
303# ----------------------------------------------------------
304
283if ARCH_AT91CAP9 305if ARCH_AT91CAP9
284 306
285comment "AT91CAP9 Board Type" 307comment "AT91CAP9 Board Type"
@@ -321,7 +343,7 @@ config MTD_AT91_DATAFLASH_CARD
321 343
322config MTD_NAND_ATMEL_BUSWIDTH_16 344config MTD_NAND_ATMEL_BUSWIDTH_16
323 bool "Enable 16-bit data bus interface to NAND flash" 345 bool "Enable 16-bit data bus interface to NAND flash"
324 depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK) 346 depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK)
325 help 347 help
326 On AT91SAM926x boards both types of NAND flash can be present 348 On AT91SAM926x boards both types of NAND flash can be present
327 (8 and 16 bit data bus width). 349 (8 and 16 bit data bus width).
@@ -383,7 +405,7 @@ config AT91_EARLY_USART2
383 405
384config AT91_EARLY_USART3 406config AT91_EARLY_USART3
385 bool "USART3" 407 bool "USART3"
386 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) 408 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45)
387 409
388config AT91_EARLY_USART4 410config AT91_EARLY_USART4
389 bool "USART4" 411 bool "USART4"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c69ff237fd14..2975f9ab861c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_d
16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o 16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o 17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
18obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 18obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
19 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
19obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 20obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
20obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 21obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
21 22
@@ -55,6 +56,9 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
55# AT91SAM9G20 board-specific support 56# AT91SAM9G20 board-specific support
56obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o 57obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
57 58
59# AT91SAM9G45 board-specific support
60obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
61
58# AT91CAP9 board-specific support 62# AT91CAP9 board-specific support
59obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o 63obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
60 64
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 071a2506a69f..3462b815054a 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -7,6 +7,10 @@ ifeq ($(CONFIG_ARCH_AT91CAP9),y)
7 zreladdr-y := 0x70008000 7 zreladdr-y := 0x70008000
8params_phys-y := 0x70000100 8params_phys-y := 0x70000100
9initrd_phys-y := 0x70410000 9initrd_phys-y := 0x70410000
10else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
11 zreladdr-y := 0x70008000
12params_phys-y := 0x70000100
13initrd_phys-y := 0x70410000
10else 14else
11 zreladdr-y := 0x20008000 15 zreladdr-y := 0x20008000
12params_phys-y := 0x20000100 16params_phys-y := 0x20000100
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
new file mode 100644
index 000000000000..85166b7e69a1
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -0,0 +1,360 @@
1/*
2 * Chip-specific setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/pm.h>
15
16#include <asm/irq.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19#include <mach/at91sam9g45.h>
20#include <mach/at91_pmc.h>
21#include <mach/at91_rstc.h>
22#include <mach/at91_shdwc.h>
23
24#include "generic.h"
25#include "clock.h"
26
27static struct map_desc at91sam9g45_io_desc[] __initdata = {
28 {
29 .virtual = AT91_VA_BASE_SYS,
30 .pfn = __phys_to_pfn(AT91_BASE_SYS),
31 .length = SZ_16K,
32 .type = MT_DEVICE,
33 }, {
34 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
35 .pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
36 .length = AT91SAM9G45_SRAM_SIZE,
37 .type = MT_DEVICE,
38 }
39};
40
41/* --------------------------------------------------------------------
42 * Clocks
43 * -------------------------------------------------------------------- */
44
45/*
46 * The peripheral clocks.
47 */
48static struct clk pioA_clk = {
49 .name = "pioA_clk",
50 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk pioB_clk = {
54 .name = "pioB_clk",
55 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk pioC_clk = {
59 .name = "pioC_clk",
60 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk pioDE_clk = {
64 .name = "pioDE_clk",
65 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk usart0_clk = {
69 .name = "usart0_clk",
70 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk usart1_clk = {
74 .name = "usart1_clk",
75 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart2_clk = {
79 .name = "usart2_clk",
80 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk usart3_clk = {
84 .name = "usart3_clk",
85 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk mmc0_clk = {
89 .name = "mci0_clk",
90 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk twi0_clk = {
94 .name = "twi0_clk",
95 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk twi1_clk = {
99 .name = "twi1_clk",
100 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk spi0_clk = {
104 .name = "spi0_clk",
105 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk spi1_clk = {
109 .name = "spi1_clk",
110 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk ssc0_clk = {
114 .name = "ssc0_clk",
115 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk ssc1_clk = {
119 .name = "ssc1_clk",
120 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk tcb_clk = {
124 .name = "tcb_clk",
125 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk pwm_clk = {
129 .name = "pwm_clk",
130 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk tsc_clk = {
134 .name = "tsc_clk",
135 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk dma_clk = {
139 .name = "dma_clk",
140 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk uhphs_clk = {
144 .name = "uhphs_clk",
145 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk lcdc_clk = {
149 .name = "lcdc_clk",
150 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk ac97_clk = {
154 .name = "ac97_clk",
155 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk macb_clk = {
159 .name = "macb_clk",
160 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk isi_clk = {
164 .name = "isi_clk",
165 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk udphs_clk = {
169 .name = "udphs_clk",
170 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173static struct clk mmc1_clk = {
174 .name = "mci1_clk",
175 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178
179/* One additional fake clock for ohci */
180static struct clk ohci_clk = {
181 .name = "ohci_clk",
182 .pmc_mask = 0,
183 .type = CLK_TYPE_PERIPHERAL,
184 .parent = &uhphs_clk,
185};
186
187static struct clk *periph_clocks[] __initdata = {
188 &pioA_clk,
189 &pioB_clk,
190 &pioC_clk,
191 &pioDE_clk,
192 &usart0_clk,
193 &usart1_clk,
194 &usart2_clk,
195 &usart3_clk,
196 &mmc0_clk,
197 &twi0_clk,
198 &twi1_clk,
199 &spi0_clk,
200 &spi1_clk,
201 &ssc0_clk,
202 &ssc1_clk,
203 &tcb_clk,
204 &pwm_clk,
205 &tsc_clk,
206 &dma_clk,
207 &uhphs_clk,
208 &lcdc_clk,
209 &ac97_clk,
210 &macb_clk,
211 &isi_clk,
212 &udphs_clk,
213 &mmc1_clk,
214 // irq0
215 &ohci_clk,
216};
217
218/*
219 * The two programmable clocks.
220 * You must configure pin multiplexing to bring these signals out.
221 */
222static struct clk pck0 = {
223 .name = "pck0",
224 .pmc_mask = AT91_PMC_PCK0,
225 .type = CLK_TYPE_PROGRAMMABLE,
226 .id = 0,
227};
228static struct clk pck1 = {
229 .name = "pck1",
230 .pmc_mask = AT91_PMC_PCK1,
231 .type = CLK_TYPE_PROGRAMMABLE,
232 .id = 1,
233};
234
235static void __init at91sam9g45_register_clocks(void)
236{
237 int i;
238
239 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
240 clk_register(periph_clocks[i]);
241
242 clk_register(&pck0);
243 clk_register(&pck1);
244}
245
246/* --------------------------------------------------------------------
247 * GPIO
248 * -------------------------------------------------------------------- */
249
250static struct at91_gpio_bank at91sam9g45_gpio[] = {
251 {
252 .id = AT91SAM9G45_ID_PIOA,
253 .offset = AT91_PIOA,
254 .clock = &pioA_clk,
255 }, {
256 .id = AT91SAM9G45_ID_PIOB,
257 .offset = AT91_PIOB,
258 .clock = &pioB_clk,
259 }, {
260 .id = AT91SAM9G45_ID_PIOC,
261 .offset = AT91_PIOC,
262 .clock = &pioC_clk,
263 }, {
264 .id = AT91SAM9G45_ID_PIODE,
265 .offset = AT91_PIOD,
266 .clock = &pioDE_clk,
267 }, {
268 .id = AT91SAM9G45_ID_PIODE,
269 .offset = AT91_PIOE,
270 .clock = &pioDE_clk,
271 }
272};
273
274static void at91sam9g45_reset(void)
275{
276 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
277}
278
279static void at91sam9g45_poweroff(void)
280{
281 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
282}
283
284
285/* --------------------------------------------------------------------
286 * AT91SAM9G45 processor initialization
287 * -------------------------------------------------------------------- */
288
289void __init at91sam9g45_initialize(unsigned long main_clock)
290{
291 /* Map peripherals */
292 iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
293
294 at91_arch_reset = at91sam9g45_reset;
295 pm_power_off = at91sam9g45_poweroff;
296 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
297
298 /* Init clock subsystem */
299 at91_clock_init(main_clock);
300
301 /* Register the processor-specific clocks */
302 at91sam9g45_register_clocks();
303
304 /* Register GPIO subsystem */
305 at91_gpio_init(at91sam9g45_gpio, 5);
306}
307
308/* --------------------------------------------------------------------
309 * Interrupt initialization
310 * -------------------------------------------------------------------- */
311
312/*
313 * The default interrupt priority levels (0 = lowest, 7 = highest).
314 */
315static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
316 7, /* Advanced Interrupt Controller (FIQ) */
317 7, /* System Peripherals */
318 1, /* Parallel IO Controller A */
319 1, /* Parallel IO Controller B */
320 1, /* Parallel IO Controller C */
321 1, /* Parallel IO Controller D and E */
322 0,
323 5, /* USART 0 */
324 5, /* USART 1 */
325 5, /* USART 2 */
326 5, /* USART 3 */
327 0, /* Multimedia Card Interface 0 */
328 6, /* Two-Wire Interface 0 */
329 6, /* Two-Wire Interface 1 */
330 5, /* Serial Peripheral Interface 0 */
331 5, /* Serial Peripheral Interface 1 */
332 4, /* Serial Synchronous Controller 0 */
333 4, /* Serial Synchronous Controller 1 */
334 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
335 0, /* Pulse Width Modulation Controller */
336 0, /* Touch Screen Controller */
337 0, /* DMA Controller */
338 2, /* USB Host High Speed port */
339 3, /* LDC Controller */
340 5, /* AC97 Controller */
341 3, /* Ethernet */
342 0, /* Image Sensor Interface */
343 2, /* USB Device High speed port */
344 0,
345 0, /* Multimedia Card Interface 1 */
346 0,
347 0, /* Advanced Interrupt Controller (IRQ0) */
348};
349
350void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])
351{
352 if (!priority)
353 priority = at91sam9g45_default_irq_priority;
354
355 /* Initialize the AIC interrupt controller */
356 at91_aic_init(priority);
357
358 /* Enable GPIO interrupts */
359 at91_gpio_irq_setup();
360}
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
new file mode 100644
index 000000000000..d746e8621bc2
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -0,0 +1,1230 @@
1/*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/i2c-gpio.h>
18
19#include <linux/fb.h>
20#include <video/atmel_lcdc.h>
21
22#include <mach/board.h>
23#include <mach/gpio.h>
24#include <mach/at91sam9g45.h>
25#include <mach/at91sam9g45_matrix.h>
26#include <mach/at91sam9_smc.h>
27
28#include "generic.h"
29
30
31/* --------------------------------------------------------------------
32 * USB Host (OHCI)
33 * -------------------------------------------------------------------- */
34
35#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
36static u64 ohci_dmamask = DMA_BIT_MASK(32);
37static struct at91_usbh_data usbh_ohci_data;
38
39static struct resource usbh_ohci_resources[] = {
40 [0] = {
41 .start = AT91SAM9G45_OHCI_BASE,
42 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9G45_ID_UHPHS,
47 .end = AT91SAM9G45_ID_UHPHS,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static struct platform_device at91_usbh_ohci_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
57 .coherent_dma_mask = DMA_BIT_MASK(32),
58 .platform_data = &usbh_ohci_data,
59 },
60 .resource = usbh_ohci_resources,
61 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
62};
63
64void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
65{
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (data->vbus_pin[i])
74 at91_set_gpio_output(data->vbus_pin[i], 0);
75 }
76
77 usbh_ohci_data = *data;
78 platform_device_register(&at91_usbh_ohci_device);
79}
80#else
81void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
82#endif
83
84
85/* --------------------------------------------------------------------
86 * USB HS Device (Gadget)
87 * -------------------------------------------------------------------- */
88
89#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
90static struct resource usba_udc_resources[] = {
91 [0] = {
92 .start = AT91SAM9G45_UDPHS_FIFO,
93 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91SAM9G45_BASE_UDPHS,
98 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 [2] = {
102 .start = AT91SAM9G45_ID_UDPHS,
103 .end = AT91SAM9G45_ID_UDPHS,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
109 [idx] = { \
110 .name = nam, \
111 .index = idx, \
112 .fifo_size = maxpkt, \
113 .nr_banks = maxbk, \
114 .can_dma = dma, \
115 .can_isoc = isoc, \
116 }
117
118static struct usba_ep_data usba_udc_ep[] __initdata = {
119 EP("ep0", 0, 64, 1, 0, 0),
120 EP("ep1", 1, 1024, 2, 1, 1),
121 EP("ep2", 2, 1024, 2, 1, 1),
122 EP("ep3", 3, 1024, 3, 1, 0),
123 EP("ep4", 4, 1024, 3, 1, 0),
124 EP("ep5", 5, 1024, 3, 1, 1),
125 EP("ep6", 6, 1024, 3, 1, 1),
126};
127
128#undef EP
129
130/*
131 * pdata doesn't have room for any endpoints, so we need to
132 * append room for the ones we need right after it.
133 */
134static struct {
135 struct usba_platform_data pdata;
136 struct usba_ep_data ep[7];
137} usba_udc_data;
138
139static struct platform_device at91_usba_udc_device = {
140 .name = "atmel_usba_udc",
141 .id = -1,
142 .dev = {
143 .platform_data = &usba_udc_data.pdata,
144 },
145 .resource = usba_udc_resources,
146 .num_resources = ARRAY_SIZE(usba_udc_resources),
147};
148
149void __init at91_add_device_usba(struct usba_platform_data *data)
150{
151 usba_udc_data.pdata.vbus_pin = -EINVAL;
152 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
153 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
154
155 if (data && data->vbus_pin > 0) {
156 at91_set_gpio_input(data->vbus_pin, 0);
157 at91_set_deglitch(data->vbus_pin, 1);
158 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
159 }
160
161 /* Pullup pin is handled internally by USB device peripheral */
162
163 /* Clocks */
164 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
165 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
166
167 platform_device_register(&at91_usba_udc_device);
168}
169#else
170void __init at91_add_device_usba(struct usba_platform_data *data) {}
171#endif
172
173
174/* --------------------------------------------------------------------
175 * Ethernet
176 * -------------------------------------------------------------------- */
177
178#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
179static u64 eth_dmamask = DMA_BIT_MASK(32);
180static struct at91_eth_data eth_data;
181
182static struct resource eth_resources[] = {
183 [0] = {
184 .start = AT91SAM9G45_BASE_EMAC,
185 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = AT91SAM9G45_ID_EMAC,
190 .end = AT91SAM9G45_ID_EMAC,
191 .flags = IORESOURCE_IRQ,
192 },
193};
194
195static struct platform_device at91sam9g45_eth_device = {
196 .name = "macb",
197 .id = -1,
198 .dev = {
199 .dma_mask = &eth_dmamask,
200 .coherent_dma_mask = DMA_BIT_MASK(32),
201 .platform_data = &eth_data,
202 },
203 .resource = eth_resources,
204 .num_resources = ARRAY_SIZE(eth_resources),
205};
206
207void __init at91_add_device_eth(struct at91_eth_data *data)
208{
209 if (!data)
210 return;
211
212 if (data->phy_irq_pin) {
213 at91_set_gpio_input(data->phy_irq_pin, 0);
214 at91_set_deglitch(data->phy_irq_pin, 1);
215 }
216
217 /* Pins used for MII and RMII */
218 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
219 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
220 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
221 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
222 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
223 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
224 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
225 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
226 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
227 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
228
229 if (!data->is_rmii) {
230 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
231 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
232 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
233 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
234 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
235 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
236 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
237 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
238 }
239
240 eth_data = *data;
241 platform_device_register(&at91sam9g45_eth_device);
242}
243#else
244void __init at91_add_device_eth(struct at91_eth_data *data) {}
245#endif
246
247
248/* --------------------------------------------------------------------
249 * NAND / SmartMedia
250 * -------------------------------------------------------------------- */
251
252#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
253static struct atmel_nand_data nand_data;
254
255#define NAND_BASE AT91_CHIPSELECT_3
256
257static struct resource nand_resources[] = {
258 [0] = {
259 .start = NAND_BASE,
260 .end = NAND_BASE + SZ_256M - 1,
261 .flags = IORESOURCE_MEM,
262 },
263 [1] = {
264 .start = AT91_BASE_SYS + AT91_ECC,
265 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
266 .flags = IORESOURCE_MEM,
267 }
268};
269
270static struct platform_device at91sam9g45_nand_device = {
271 .name = "atmel_nand",
272 .id = -1,
273 .dev = {
274 .platform_data = &nand_data,
275 },
276 .resource = nand_resources,
277 .num_resources = ARRAY_SIZE(nand_resources),
278};
279
280void __init at91_add_device_nand(struct atmel_nand_data *data)
281{
282 unsigned long csa;
283
284 if (!data)
285 return;
286
287 csa = at91_sys_read(AT91_MATRIX_EBICSA);
288 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
289
290 /* enable pin */
291 if (data->enable_pin)
292 at91_set_gpio_output(data->enable_pin, 1);
293
294 /* ready/busy pin */
295 if (data->rdy_pin)
296 at91_set_gpio_input(data->rdy_pin, 1);
297
298 /* card detect pin */
299 if (data->det_pin)
300 at91_set_gpio_input(data->det_pin, 1);
301
302 nand_data = *data;
303 platform_device_register(&at91sam9g45_nand_device);
304}
305#else
306void __init at91_add_device_nand(struct atmel_nand_data *data) {}
307#endif
308
309
310/* --------------------------------------------------------------------
311 * TWI (i2c)
312 * -------------------------------------------------------------------- */
313
314/*
315 * Prefer the GPIO code since the TWI controller isn't robust
316 * (gets overruns and underruns under load) and can only issue
317 * repeated STARTs in one scenario (the driver doesn't yet handle them).
318 */
319#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
320static struct i2c_gpio_platform_data pdata_i2c0 = {
321 .sda_pin = AT91_PIN_PA20,
322 .sda_is_open_drain = 1,
323 .scl_pin = AT91_PIN_PA21,
324 .scl_is_open_drain = 1,
325 .udelay = 2, /* ~100 kHz */
326};
327
328static struct platform_device at91sam9g45_twi0_device = {
329 .name = "i2c-gpio",
330 .id = 0,
331 .dev.platform_data = &pdata_i2c0,
332};
333
334static struct i2c_gpio_platform_data pdata_i2c1 = {
335 .sda_pin = AT91_PIN_PB10,
336 .sda_is_open_drain = 1,
337 .scl_pin = AT91_PIN_PB11,
338 .scl_is_open_drain = 1,
339 .udelay = 2, /* ~100 kHz */
340};
341
342static struct platform_device at91sam9g45_twi1_device = {
343 .name = "i2c-gpio",
344 .id = 1,
345 .dev.platform_data = &pdata_i2c1,
346};
347
348void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
349{
350 i2c_register_board_info(i2c_id, devices, nr_devices);
351
352 if (i2c_id == 0) {
353 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
354 at91_set_multi_drive(AT91_PIN_PA20, 1);
355
356 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
357 at91_set_multi_drive(AT91_PIN_PA21, 1);
358
359 platform_device_register(&at91sam9g45_twi0_device);
360 } else {
361 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
362 at91_set_multi_drive(AT91_PIN_PB10, 1);
363
364 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
365 at91_set_multi_drive(AT91_PIN_PB11, 1);
366
367 platform_device_register(&at91sam9g45_twi1_device);
368 }
369}
370
371#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
372static struct resource twi0_resources[] = {
373 [0] = {
374 .start = AT91SAM9G45_BASE_TWI0,
375 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = AT91SAM9G45_ID_TWI0,
380 .end = AT91SAM9G45_ID_TWI0,
381 .flags = IORESOURCE_IRQ,
382 },
383};
384
385static struct platform_device at91sam9g45_twi0_device = {
386 .name = "at91_i2c",
387 .id = 0,
388 .resource = twi0_resources,
389 .num_resources = ARRAY_SIZE(twi0_resources),
390};
391
392static struct resource twi1_resources[] = {
393 [0] = {
394 .start = AT91SAM9G45_BASE_TWI1,
395 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
396 .flags = IORESOURCE_MEM,
397 },
398 [1] = {
399 .start = AT91SAM9G45_ID_TWI1,
400 .end = AT91SAM9G45_ID_TWI1,
401 .flags = IORESOURCE_IRQ,
402 },
403};
404
405static struct platform_device at91sam9g45_twi1_device = {
406 .name = "at91_i2c",
407 .id = 1,
408 .resource = twi1_resources,
409 .num_resources = ARRAY_SIZE(twi1_resources),
410};
411
412void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
413{
414 i2c_register_board_info(i2c_id, devices, nr_devices);
415
416 /* pins used for TWI interface */
417 if (i2c_id == 0) {
418 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
419 at91_set_multi_drive(AT91_PIN_PA20, 1);
420
421 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
422 at91_set_multi_drive(AT91_PIN_PA21, 1);
423
424 platform_device_register(&at91sam9g45_twi0_device);
425 } else {
426 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
427 at91_set_multi_drive(AT91_PIN_PB10, 1);
428
429 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
430 at91_set_multi_drive(AT91_PIN_PB11, 1);
431
432 platform_device_register(&at91sam9g45_twi1_device);
433 }
434}
435#else
436void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
437#endif
438
439
440/* --------------------------------------------------------------------
441 * SPI
442 * -------------------------------------------------------------------- */
443
444#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
445static u64 spi_dmamask = DMA_BIT_MASK(32);
446
447static struct resource spi0_resources[] = {
448 [0] = {
449 .start = AT91SAM9G45_BASE_SPI0,
450 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
451 .flags = IORESOURCE_MEM,
452 },
453 [1] = {
454 .start = AT91SAM9G45_ID_SPI0,
455 .end = AT91SAM9G45_ID_SPI0,
456 .flags = IORESOURCE_IRQ,
457 },
458};
459
460static struct platform_device at91sam9g45_spi0_device = {
461 .name = "atmel_spi",
462 .id = 0,
463 .dev = {
464 .dma_mask = &spi_dmamask,
465 .coherent_dma_mask = DMA_BIT_MASK(32),
466 },
467 .resource = spi0_resources,
468 .num_resources = ARRAY_SIZE(spi0_resources),
469};
470
471static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
472
473static struct resource spi1_resources[] = {
474 [0] = {
475 .start = AT91SAM9G45_BASE_SPI1,
476 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .start = AT91SAM9G45_ID_SPI1,
481 .end = AT91SAM9G45_ID_SPI1,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static struct platform_device at91sam9g45_spi1_device = {
487 .name = "atmel_spi",
488 .id = 1,
489 .dev = {
490 .dma_mask = &spi_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(32),
492 },
493 .resource = spi1_resources,
494 .num_resources = ARRAY_SIZE(spi1_resources),
495};
496
497static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
498
499void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
500{
501 int i;
502 unsigned long cs_pin;
503 short enable_spi0 = 0;
504 short enable_spi1 = 0;
505
506 /* Choose SPI chip-selects */
507 for (i = 0; i < nr_devices; i++) {
508 if (devices[i].controller_data)
509 cs_pin = (unsigned long) devices[i].controller_data;
510 else if (devices[i].bus_num == 0)
511 cs_pin = spi0_standard_cs[devices[i].chip_select];
512 else
513 cs_pin = spi1_standard_cs[devices[i].chip_select];
514
515 if (devices[i].bus_num == 0)
516 enable_spi0 = 1;
517 else
518 enable_spi1 = 1;
519
520 /* enable chip-select pin */
521 at91_set_gpio_output(cs_pin, 1);
522
523 /* pass chip-select pin to driver */
524 devices[i].controller_data = (void *) cs_pin;
525 }
526
527 spi_register_board_info(devices, nr_devices);
528
529 /* Configure SPI bus(es) */
530 if (enable_spi0) {
531 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
532 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
533 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
534
535 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
536 platform_device_register(&at91sam9g45_spi0_device);
537 }
538 if (enable_spi1) {
539 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
540 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
541 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
542
543 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
544 platform_device_register(&at91sam9g45_spi1_device);
545 }
546}
547#else
548void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
549#endif
550
551
552/* --------------------------------------------------------------------
553 * LCD Controller
554 * -------------------------------------------------------------------- */
555
556#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
557static u64 lcdc_dmamask = DMA_BIT_MASK(32);
558static struct atmel_lcdfb_info lcdc_data;
559
560static struct resource lcdc_resources[] = {
561 [0] = {
562 .start = AT91SAM9G45_LCDC_BASE,
563 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 [1] = {
567 .start = AT91SAM9G45_ID_LCDC,
568 .end = AT91SAM9G45_ID_LCDC,
569 .flags = IORESOURCE_IRQ,
570 },
571};
572
573static struct platform_device at91_lcdc_device = {
574 .name = "atmel_lcdfb",
575 .id = 0,
576 .dev = {
577 .dma_mask = &lcdc_dmamask,
578 .coherent_dma_mask = DMA_BIT_MASK(32),
579 .platform_data = &lcdc_data,
580 },
581 .resource = lcdc_resources,
582 .num_resources = ARRAY_SIZE(lcdc_resources),
583};
584
585void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
586{
587 if (!data)
588 return;
589
590 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
591
592 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
593 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
594 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
595 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
596 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
597 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
598 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
599 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
600 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
601 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
602 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
603 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
604 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
605 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
606 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
607 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
608 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
609 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
610 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
611 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
612 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
613 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
614 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
615 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
616 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
617 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
618 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
619 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
620 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
621
622 lcdc_data = *data;
623 platform_device_register(&at91_lcdc_device);
624}
625#else
626void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
627#endif
628
629
630/* --------------------------------------------------------------------
631 * Timer/Counter block
632 * -------------------------------------------------------------------- */
633
634#ifdef CONFIG_ATMEL_TCLIB
635static struct resource tcb0_resources[] = {
636 [0] = {
637 .start = AT91SAM9G45_BASE_TCB0,
638 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
639 .flags = IORESOURCE_MEM,
640 },
641 [1] = {
642 .start = AT91SAM9G45_ID_TCB,
643 .end = AT91SAM9G45_ID_TCB,
644 .flags = IORESOURCE_IRQ,
645 },
646};
647
648static struct platform_device at91sam9g45_tcb0_device = {
649 .name = "atmel_tcb",
650 .id = 0,
651 .resource = tcb0_resources,
652 .num_resources = ARRAY_SIZE(tcb0_resources),
653};
654
655/* TCB1 begins with TC3 */
656static struct resource tcb1_resources[] = {
657 [0] = {
658 .start = AT91SAM9G45_BASE_TCB1,
659 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
660 .flags = IORESOURCE_MEM,
661 },
662 [1] = {
663 .start = AT91SAM9G45_ID_TCB,
664 .end = AT91SAM9G45_ID_TCB,
665 .flags = IORESOURCE_IRQ,
666 },
667};
668
669static struct platform_device at91sam9g45_tcb1_device = {
670 .name = "atmel_tcb",
671 .id = 1,
672 .resource = tcb1_resources,
673 .num_resources = ARRAY_SIZE(tcb1_resources),
674};
675
676static void __init at91_add_device_tc(void)
677{
678 /* this chip has one clock and irq for all six TC channels */
679 at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
680 platform_device_register(&at91sam9g45_tcb0_device);
681 at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
682 platform_device_register(&at91sam9g45_tcb1_device);
683}
684#else
685static void __init at91_add_device_tc(void) { }
686#endif
687
688
689/* --------------------------------------------------------------------
690 * RTC
691 * -------------------------------------------------------------------- */
692
693#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
694static struct platform_device at91sam9g45_rtc_device = {
695 .name = "at91_rtc",
696 .id = -1,
697 .num_resources = 0,
698};
699
700static void __init at91_add_device_rtc(void)
701{
702 platform_device_register(&at91sam9g45_rtc_device);
703}
704#else
705static void __init at91_add_device_rtc(void) {}
706#endif
707
708
709/* --------------------------------------------------------------------
710 * RTT
711 * -------------------------------------------------------------------- */
712
713static struct resource rtt_resources[] = {
714 {
715 .start = AT91_BASE_SYS + AT91_RTT,
716 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
717 .flags = IORESOURCE_MEM,
718 }
719};
720
721static struct platform_device at91sam9g45_rtt_device = {
722 .name = "at91_rtt",
723 .id = 0,
724 .resource = rtt_resources,
725 .num_resources = ARRAY_SIZE(rtt_resources),
726};
727
728static void __init at91_add_device_rtt(void)
729{
730 platform_device_register(&at91sam9g45_rtt_device);
731}
732
733
734/* --------------------------------------------------------------------
735 * Watchdog
736 * -------------------------------------------------------------------- */
737
738#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
739static struct platform_device at91sam9g45_wdt_device = {
740 .name = "at91_wdt",
741 .id = -1,
742 .num_resources = 0,
743};
744
745static void __init at91_add_device_watchdog(void)
746{
747 platform_device_register(&at91sam9g45_wdt_device);
748}
749#else
750static void __init at91_add_device_watchdog(void) {}
751#endif
752
753
754/* --------------------------------------------------------------------
755 * PWM
756 * --------------------------------------------------------------------*/
757
758#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
759static u32 pwm_mask;
760
761static struct resource pwm_resources[] = {
762 [0] = {
763 .start = AT91SAM9G45_BASE_PWMC,
764 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
765 .flags = IORESOURCE_MEM,
766 },
767 [1] = {
768 .start = AT91SAM9G45_ID_PWMC,
769 .end = AT91SAM9G45_ID_PWMC,
770 .flags = IORESOURCE_IRQ,
771 },
772};
773
774static struct platform_device at91sam9g45_pwm0_device = {
775 .name = "atmel_pwm",
776 .id = -1,
777 .dev = {
778 .platform_data = &pwm_mask,
779 },
780 .resource = pwm_resources,
781 .num_resources = ARRAY_SIZE(pwm_resources),
782};
783
784void __init at91_add_device_pwm(u32 mask)
785{
786 if (mask & (1 << AT91_PWM0))
787 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
788
789 if (mask & (1 << AT91_PWM1))
790 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
791
792 if (mask & (1 << AT91_PWM2))
793 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
794
795 if (mask & (1 << AT91_PWM3))
796 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
797
798 pwm_mask = mask;
799
800 platform_device_register(&at91sam9g45_pwm0_device);
801}
802#else
803void __init at91_add_device_pwm(u32 mask) {}
804#endif
805
806
807/* --------------------------------------------------------------------
808 * SSC -- Synchronous Serial Controller
809 * -------------------------------------------------------------------- */
810
811#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
812static u64 ssc0_dmamask = DMA_BIT_MASK(32);
813
814static struct resource ssc0_resources[] = {
815 [0] = {
816 .start = AT91SAM9G45_BASE_SSC0,
817 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
818 .flags = IORESOURCE_MEM,
819 },
820 [1] = {
821 .start = AT91SAM9G45_ID_SSC0,
822 .end = AT91SAM9G45_ID_SSC0,
823 .flags = IORESOURCE_IRQ,
824 },
825};
826
827static struct platform_device at91sam9g45_ssc0_device = {
828 .name = "ssc",
829 .id = 0,
830 .dev = {
831 .dma_mask = &ssc0_dmamask,
832 .coherent_dma_mask = DMA_BIT_MASK(32),
833 },
834 .resource = ssc0_resources,
835 .num_resources = ARRAY_SIZE(ssc0_resources),
836};
837
838static inline void configure_ssc0_pins(unsigned pins)
839{
840 if (pins & ATMEL_SSC_TF)
841 at91_set_A_periph(AT91_PIN_PD1, 1);
842 if (pins & ATMEL_SSC_TK)
843 at91_set_A_periph(AT91_PIN_PD0, 1);
844 if (pins & ATMEL_SSC_TD)
845 at91_set_A_periph(AT91_PIN_PD2, 1);
846 if (pins & ATMEL_SSC_RD)
847 at91_set_A_periph(AT91_PIN_PD3, 1);
848 if (pins & ATMEL_SSC_RK)
849 at91_set_A_periph(AT91_PIN_PD4, 1);
850 if (pins & ATMEL_SSC_RF)
851 at91_set_A_periph(AT91_PIN_PD5, 1);
852}
853
854static u64 ssc1_dmamask = DMA_BIT_MASK(32);
855
856static struct resource ssc1_resources[] = {
857 [0] = {
858 .start = AT91SAM9G45_BASE_SSC1,
859 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
860 .flags = IORESOURCE_MEM,
861 },
862 [1] = {
863 .start = AT91SAM9G45_ID_SSC1,
864 .end = AT91SAM9G45_ID_SSC1,
865 .flags = IORESOURCE_IRQ,
866 },
867};
868
869static struct platform_device at91sam9g45_ssc1_device = {
870 .name = "ssc",
871 .id = 1,
872 .dev = {
873 .dma_mask = &ssc1_dmamask,
874 .coherent_dma_mask = DMA_BIT_MASK(32),
875 },
876 .resource = ssc1_resources,
877 .num_resources = ARRAY_SIZE(ssc1_resources),
878};
879
880static inline void configure_ssc1_pins(unsigned pins)
881{
882 if (pins & ATMEL_SSC_TF)
883 at91_set_A_periph(AT91_PIN_PD14, 1);
884 if (pins & ATMEL_SSC_TK)
885 at91_set_A_periph(AT91_PIN_PD12, 1);
886 if (pins & ATMEL_SSC_TD)
887 at91_set_A_periph(AT91_PIN_PD10, 1);
888 if (pins & ATMEL_SSC_RD)
889 at91_set_A_periph(AT91_PIN_PD11, 1);
890 if (pins & ATMEL_SSC_RK)
891 at91_set_A_periph(AT91_PIN_PD13, 1);
892 if (pins & ATMEL_SSC_RF)
893 at91_set_A_periph(AT91_PIN_PD15, 1);
894}
895
896/*
897 * SSC controllers are accessed through library code, instead of any
898 * kind of all-singing/all-dancing driver. For example one could be
899 * used by a particular I2S audio codec's driver, while another one
900 * on the same system might be used by a custom data capture driver.
901 */
902void __init at91_add_device_ssc(unsigned id, unsigned pins)
903{
904 struct platform_device *pdev;
905
906 /*
907 * NOTE: caller is responsible for passing information matching
908 * "pins" to whatever will be using each particular controller.
909 */
910 switch (id) {
911 case AT91SAM9G45_ID_SSC0:
912 pdev = &at91sam9g45_ssc0_device;
913 configure_ssc0_pins(pins);
914 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
915 break;
916 case AT91SAM9G45_ID_SSC1:
917 pdev = &at91sam9g45_ssc1_device;
918 configure_ssc1_pins(pins);
919 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
920 break;
921 default:
922 return;
923 }
924
925 platform_device_register(pdev);
926}
927
928#else
929void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
930#endif
931
932
933/* --------------------------------------------------------------------
934 * UART
935 * -------------------------------------------------------------------- */
936
937#if defined(CONFIG_SERIAL_ATMEL)
938static struct resource dbgu_resources[] = {
939 [0] = {
940 .start = AT91_VA_BASE_SYS + AT91_DBGU,
941 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
942 .flags = IORESOURCE_MEM,
943 },
944 [1] = {
945 .start = AT91_ID_SYS,
946 .end = AT91_ID_SYS,
947 .flags = IORESOURCE_IRQ,
948 },
949};
950
951static struct atmel_uart_data dbgu_data = {
952 .use_dma_tx = 0,
953 .use_dma_rx = 0,
954 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
955};
956
957static u64 dbgu_dmamask = DMA_BIT_MASK(32);
958
959static struct platform_device at91sam9g45_dbgu_device = {
960 .name = "atmel_usart",
961 .id = 0,
962 .dev = {
963 .dma_mask = &dbgu_dmamask,
964 .coherent_dma_mask = DMA_BIT_MASK(32),
965 .platform_data = &dbgu_data,
966 },
967 .resource = dbgu_resources,
968 .num_resources = ARRAY_SIZE(dbgu_resources),
969};
970
971static inline void configure_dbgu_pins(void)
972{
973 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
974 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
975}
976
977static struct resource uart0_resources[] = {
978 [0] = {
979 .start = AT91SAM9G45_BASE_US0,
980 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
981 .flags = IORESOURCE_MEM,
982 },
983 [1] = {
984 .start = AT91SAM9G45_ID_US0,
985 .end = AT91SAM9G45_ID_US0,
986 .flags = IORESOURCE_IRQ,
987 },
988};
989
990static struct atmel_uart_data uart0_data = {
991 .use_dma_tx = 1,
992 .use_dma_rx = 1,
993};
994
995static u64 uart0_dmamask = DMA_BIT_MASK(32);
996
997static struct platform_device at91sam9g45_uart0_device = {
998 .name = "atmel_usart",
999 .id = 1,
1000 .dev = {
1001 .dma_mask = &uart0_dmamask,
1002 .coherent_dma_mask = DMA_BIT_MASK(32),
1003 .platform_data = &uart0_data,
1004 },
1005 .resource = uart0_resources,
1006 .num_resources = ARRAY_SIZE(uart0_resources),
1007};
1008
1009static inline void configure_usart0_pins(unsigned pins)
1010{
1011 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1012 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1013
1014 if (pins & ATMEL_UART_RTS)
1015 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1016 if (pins & ATMEL_UART_CTS)
1017 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1018}
1019
1020static struct resource uart1_resources[] = {
1021 [0] = {
1022 .start = AT91SAM9G45_BASE_US1,
1023 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1024 .flags = IORESOURCE_MEM,
1025 },
1026 [1] = {
1027 .start = AT91SAM9G45_ID_US1,
1028 .end = AT91SAM9G45_ID_US1,
1029 .flags = IORESOURCE_IRQ,
1030 },
1031};
1032
1033static struct atmel_uart_data uart1_data = {
1034 .use_dma_tx = 1,
1035 .use_dma_rx = 1,
1036};
1037
1038static u64 uart1_dmamask = DMA_BIT_MASK(32);
1039
1040static struct platform_device at91sam9g45_uart1_device = {
1041 .name = "atmel_usart",
1042 .id = 2,
1043 .dev = {
1044 .dma_mask = &uart1_dmamask,
1045 .coherent_dma_mask = DMA_BIT_MASK(32),
1046 .platform_data = &uart1_data,
1047 },
1048 .resource = uart1_resources,
1049 .num_resources = ARRAY_SIZE(uart1_resources),
1050};
1051
1052static inline void configure_usart1_pins(unsigned pins)
1053{
1054 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1055 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1056
1057 if (pins & ATMEL_UART_RTS)
1058 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1059 if (pins & ATMEL_UART_CTS)
1060 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1061}
1062
1063static struct resource uart2_resources[] = {
1064 [0] = {
1065 .start = AT91SAM9G45_BASE_US2,
1066 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1067 .flags = IORESOURCE_MEM,
1068 },
1069 [1] = {
1070 .start = AT91SAM9G45_ID_US2,
1071 .end = AT91SAM9G45_ID_US2,
1072 .flags = IORESOURCE_IRQ,
1073 },
1074};
1075
1076static struct atmel_uart_data uart2_data = {
1077 .use_dma_tx = 1,
1078 .use_dma_rx = 1,
1079};
1080
1081static u64 uart2_dmamask = DMA_BIT_MASK(32);
1082
1083static struct platform_device at91sam9g45_uart2_device = {
1084 .name = "atmel_usart",
1085 .id = 3,
1086 .dev = {
1087 .dma_mask = &uart2_dmamask,
1088 .coherent_dma_mask = DMA_BIT_MASK(32),
1089 .platform_data = &uart2_data,
1090 },
1091 .resource = uart2_resources,
1092 .num_resources = ARRAY_SIZE(uart2_resources),
1093};
1094
1095static inline void configure_usart2_pins(unsigned pins)
1096{
1097 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1098 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1099
1100 if (pins & ATMEL_UART_RTS)
1101 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1102 if (pins & ATMEL_UART_CTS)
1103 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1104}
1105
1106static struct resource uart3_resources[] = {
1107 [0] = {
1108 .start = AT91SAM9G45_BASE_US3,
1109 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1110 .flags = IORESOURCE_MEM,
1111 },
1112 [1] = {
1113 .start = AT91SAM9G45_ID_US3,
1114 .end = AT91SAM9G45_ID_US3,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117};
1118
1119static struct atmel_uart_data uart3_data = {
1120 .use_dma_tx = 1,
1121 .use_dma_rx = 1,
1122};
1123
1124static u64 uart3_dmamask = DMA_BIT_MASK(32);
1125
1126static struct platform_device at91sam9g45_uart3_device = {
1127 .name = "atmel_usart",
1128 .id = 4,
1129 .dev = {
1130 .dma_mask = &uart3_dmamask,
1131 .coherent_dma_mask = DMA_BIT_MASK(32),
1132 .platform_data = &uart3_data,
1133 },
1134 .resource = uart3_resources,
1135 .num_resources = ARRAY_SIZE(uart3_resources),
1136};
1137
1138static inline void configure_usart3_pins(unsigned pins)
1139{
1140 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1141 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1142
1143 if (pins & ATMEL_UART_RTS)
1144 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1145 if (pins & ATMEL_UART_CTS)
1146 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1147}
1148
1149static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1150struct platform_device *atmel_default_console_device; /* the serial console device */
1151
1152void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1153{
1154 struct platform_device *pdev;
1155
1156 switch (id) {
1157 case 0: /* DBGU */
1158 pdev = &at91sam9g45_dbgu_device;
1159 configure_dbgu_pins();
1160 at91_clock_associate("mck", &pdev->dev, "usart");
1161 break;
1162 case AT91SAM9G45_ID_US0:
1163 pdev = &at91sam9g45_uart0_device;
1164 configure_usart0_pins(pins);
1165 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1166 break;
1167 case AT91SAM9G45_ID_US1:
1168 pdev = &at91sam9g45_uart1_device;
1169 configure_usart1_pins(pins);
1170 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1171 break;
1172 case AT91SAM9G45_ID_US2:
1173 pdev = &at91sam9g45_uart2_device;
1174 configure_usart2_pins(pins);
1175 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1176 break;
1177 case AT91SAM9G45_ID_US3:
1178 pdev = &at91sam9g45_uart3_device;
1179 configure_usart3_pins(pins);
1180 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1181 break;
1182 default:
1183 return;
1184 }
1185 pdev->id = portnr; /* update to mapped ID */
1186
1187 if (portnr < ATMEL_MAX_UART)
1188 at91_uarts[portnr] = pdev;
1189}
1190
1191void __init at91_set_serial_console(unsigned portnr)
1192{
1193 if (portnr < ATMEL_MAX_UART)
1194 atmel_default_console_device = at91_uarts[portnr];
1195}
1196
1197void __init at91_add_device_serial(void)
1198{
1199 int i;
1200
1201 for (i = 0; i < ATMEL_MAX_UART; i++) {
1202 if (at91_uarts[i])
1203 platform_device_register(at91_uarts[i]);
1204 }
1205
1206 if (!atmel_default_console_device)
1207 printk(KERN_INFO "AT91: No default serial console defined.\n");
1208}
1209#else
1210void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1211void __init at91_set_serial_console(unsigned portnr) {}
1212void __init at91_add_device_serial(void) {}
1213#endif
1214
1215
1216/* -------------------------------------------------------------------- */
1217/*
1218 * These devices are always present and don't need any board-specific
1219 * setup.
1220 */
1221static int __init at91_add_standard_devices(void)
1222{
1223 at91_add_device_rtc();
1224 at91_add_device_rtt();
1225 at91_add_device_watchdog();
1226 at91_add_device_tc();
1227 return 0;
1228}
1229
1230arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
new file mode 100644
index 000000000000..b8558eae5229
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -0,0 +1,389 @@
1/*
2 * Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
3 *
4 * Covers: * AT91SAM9G45-EKES board
5 * * AT91SAM9M10G45-EK board
6 *
7 * Copyright (C) 2009 Atmel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
22#include <linux/fb.h>
23#include <linux/gpio_keys.h>
24#include <linux/input.h>
25#include <linux/leds.h>
26#include <linux/clk.h>
27
28#include <mach/hardware.h>
29#include <video/atmel_lcdc.h>
30
31#include <asm/setup.h>
32#include <asm/mach-types.h>
33#include <asm/irq.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38
39#include <mach/hardware.h>
40#include <mach/board.h>
41#include <mach/gpio.h>
42#include <mach/at91sam9_smc.h>
43#include <mach/at91_shdwc.h>
44
45#include "sam9_smc.h"
46#include "generic.h"
47
48
49static void __init ek_map_io(void)
50{
51 /* Initialize processor: 12.000 MHz crystal */
52 at91sam9g45_initialize(12000000);
53
54 /* DGBU on ttyS0. (Rx & Tx only) */
55 at91_register_uart(0, 0, 0);
56
57 /* USART0 not connected on the -EK board */
58 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
59 at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
60
61 /* set serial console to ttyS0 (ie, DBGU) */
62 at91_set_serial_console(0);
63}
64
65static void __init ek_init_irq(void)
66{
67 at91sam9g45_init_interrupts(NULL);
68}
69
70
71/*
72 * USB HS Host port (common to OHCI & EHCI)
73 */
74static struct at91_usbh_data __initdata ek_usbh_hs_data = {
75 .ports = 2,
76 .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3},
77};
78
79
80/*
81 * USB HS Device port
82 */
83static struct usba_platform_data __initdata ek_usba_udc_data = {
84 .vbus_pin = AT91_PIN_PB19,
85};
86
87
88/*
89 * SPI devices.
90 */
91static struct spi_board_info ek_spi_devices[] = {
92 { /* DataFlash chip */
93 .modalias = "mtd_dataflash",
94 .chip_select = 0,
95 .max_speed_hz = 15 * 1000 * 1000,
96 .bus_num = 0,
97 },
98};
99
100
101/*
102 * MACB Ethernet device
103 */
104static struct at91_eth_data __initdata ek_macb_data = {
105 .phy_irq_pin = AT91_PIN_PD5,
106 .is_rmii = 1,
107};
108
109
110/*
111 * NAND flash
112 */
113static struct mtd_partition __initdata ek_nand_partition[] = {
114 {
115 .name = "Partition 1",
116 .offset = 0,
117 .size = SZ_64M,
118 },
119 {
120 .name = "Partition 2",
121 .offset = MTDPART_OFS_NXTBLK,
122 .size = MTDPART_SIZ_FULL,
123 },
124};
125
126static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
127{
128 *num_partitions = ARRAY_SIZE(ek_nand_partition);
129 return ek_nand_partition;
130}
131
132/* det_pin is not connected */
133static struct atmel_nand_data __initdata ek_nand_data = {
134 .ale = 21,
135 .cle = 22,
136 .rdy_pin = AT91_PIN_PC8,
137 .enable_pin = AT91_PIN_PC14,
138 .partition_info = nand_partitions,
139#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
140 .bus_width_16 = 1,
141#else
142 .bus_width_16 = 0,
143#endif
144};
145
146static struct sam9_smc_config __initdata ek_nand_smc_config = {
147 .ncs_read_setup = 0,
148 .nrd_setup = 2,
149 .ncs_write_setup = 0,
150 .nwe_setup = 2,
151
152 .ncs_read_pulse = 4,
153 .nrd_pulse = 4,
154 .ncs_write_pulse = 4,
155 .nwe_pulse = 4,
156
157 .read_cycle = 7,
158 .write_cycle = 7,
159
160 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
161 .tdf_cycles = 3,
162};
163
164static void __init ek_add_device_nand(void)
165{
166 /* setup bus-width (8 or 16) */
167 if (ek_nand_data.bus_width_16)
168 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
169 else
170 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
171
172 /* configure chip-select 3 (NAND) */
173 sam9_smc_configure(3, &ek_nand_smc_config);
174
175 at91_add_device_nand(&ek_nand_data);
176}
177
178
179/*
180 * LCD Controller
181 */
182#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
183static struct fb_videomode at91_tft_vga_modes[] = {
184 {
185 .name = "LG",
186 .refresh = 60,
187 .xres = 480, .yres = 272,
188 .pixclock = KHZ2PICOS(9000),
189
190 .left_margin = 1, .right_margin = 1,
191 .upper_margin = 40, .lower_margin = 1,
192 .hsync_len = 45, .vsync_len = 1,
193
194 .sync = 0,
195 .vmode = FB_VMODE_NONINTERLACED,
196 },
197};
198
199static struct fb_monspecs at91fb_default_monspecs = {
200 .manufacturer = "LG",
201 .monitor = "LB043WQ1",
202
203 .modedb = at91_tft_vga_modes,
204 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
205 .hfmin = 15000,
206 .hfmax = 17640,
207 .vfmin = 57,
208 .vfmax = 67,
209};
210
211#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
212 | ATMEL_LCDC_DISTYPE_TFT \
213 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
214
215/* Driver datas */
216static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
217 .lcdcon_is_backlight = true,
218 .default_bpp = 32,
219 .default_dmacon = ATMEL_LCDC_DMAEN,
220 .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
221 .default_monspecs = &at91fb_default_monspecs,
222 .guard_time = 9,
223 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
224};
225
226#else
227static struct atmel_lcdfb_info __initdata ek_lcdc_data;
228#endif
229
230
231/*
232 * GPIO Buttons
233 */
234#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
235static struct gpio_keys_button ek_buttons[] = {
236 { /* BP1, "leftclic" */
237 .code = BTN_LEFT,
238 .gpio = AT91_PIN_PB6,
239 .active_low = 1,
240 .desc = "left_click",
241 .wakeup = 1,
242 },
243 { /* BP2, "rightclic" */
244 .code = BTN_RIGHT,
245 .gpio = AT91_PIN_PB7,
246 .active_low = 1,
247 .desc = "right_click",
248 .wakeup = 1,
249 },
250 /* BP3, "joystick" */
251 {
252 .code = KEY_LEFT,
253 .gpio = AT91_PIN_PB14,
254 .active_low = 1,
255 .desc = "Joystick Left",
256 },
257 {
258 .code = KEY_RIGHT,
259 .gpio = AT91_PIN_PB15,
260 .active_low = 1,
261 .desc = "Joystick Right",
262 },
263 {
264 .code = KEY_UP,
265 .gpio = AT91_PIN_PB16,
266 .active_low = 1,
267 .desc = "Joystick Up",
268 },
269 {
270 .code = KEY_DOWN,
271 .gpio = AT91_PIN_PB17,
272 .active_low = 1,
273 .desc = "Joystick Down",
274 },
275 {
276 .code = KEY_ENTER,
277 .gpio = AT91_PIN_PB18,
278 .active_low = 1,
279 .desc = "Joystick Press",
280 },
281};
282
283static struct gpio_keys_platform_data ek_button_data = {
284 .buttons = ek_buttons,
285 .nbuttons = ARRAY_SIZE(ek_buttons),
286};
287
288static struct platform_device ek_button_device = {
289 .name = "gpio-keys",
290 .id = -1,
291 .num_resources = 0,
292 .dev = {
293 .platform_data = &ek_button_data,
294 }
295};
296
297static void __init ek_add_device_buttons(void)
298{
299 int i;
300
301 for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
302 at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
303 at91_set_deglitch(ek_buttons[i].gpio, 1);
304 }
305
306 platform_device_register(&ek_button_device);
307}
308#else
309static void __init ek_add_device_buttons(void) {}
310#endif
311
312
313/*
314 * LEDs ... these could all be PWM-driven, for variable brightness
315 */
316static struct gpio_led ek_leds[] = {
317 { /* "top" led, red, powerled */
318 .name = "d8",
319 .gpio = AT91_PIN_PD30,
320 .default_trigger = "heartbeat",
321 },
322 { /* "left" led, green, userled2, pwm3 */
323 .name = "d6",
324 .gpio = AT91_PIN_PD0,
325 .active_low = 1,
326 .default_trigger = "nand-disk",
327 },
328#if !(defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE))
329 { /* "right" led, green, userled1, pwm1 */
330 .name = "d7",
331 .gpio = AT91_PIN_PD31,
332 .active_low = 1,
333 .default_trigger = "mmc0",
334 },
335#endif
336};
337
338
339/*
340 * PWM Leds
341 */
342static struct gpio_led ek_pwm_led[] = {
343#if defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE)
344 { /* "right" led, green, userled1, pwm1 */
345 .name = "d7",
346 .gpio = 1, /* is PWM channel number */
347 .active_low = 1,
348 .default_trigger = "none",
349 },
350#endif
351};
352
353
354
355static void __init ek_board_init(void)
356{
357 /* Serial */
358 at91_add_device_serial();
359 /* USB HS Host */
360 at91_add_device_usbh_ohci(&ek_usbh_hs_data);
361 /* USB HS Device */
362 at91_add_device_usba(&ek_usba_udc_data);
363 /* SPI */
364 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
365 /* Ethernet */
366 at91_add_device_eth(&ek_macb_data);
367 /* NAND */
368 ek_add_device_nand();
369 /* I2C */
370 at91_add_device_i2c(0, NULL, 0);
371 /* LCD Controller */
372 at91_add_device_lcdc(&ek_lcdc_data);
373 /* Push Buttons */
374 ek_add_device_buttons();
375 /* LEDs */
376 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
377 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
378}
379
380MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
381 /* Maintainer: Atmel */
382 .phys_io = AT91_BASE_SYS,
383 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
384 .boot_params = AT91_SDRAM_BASE + 0x100,
385 .timer = &at91sam926x_timer,
386 .map_io = ek_map_io,
387 .init_irq = ek_init_irq,
388 .init_machine = ek_board_init,
389MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index b5daf7f5e011..88e413b38480 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -14,6 +14,7 @@ extern void __init at91sam9260_initialize(unsigned long main_clock);
14extern void __init at91sam9261_initialize(unsigned long main_clock); 14extern void __init at91sam9261_initialize(unsigned long main_clock);
15extern void __init at91sam9263_initialize(unsigned long main_clock); 15extern void __init at91sam9263_initialize(unsigned long main_clock);
16extern void __init at91sam9rl_initialize(unsigned long main_clock); 16extern void __init at91sam9rl_initialize(unsigned long main_clock);
17extern void __init at91sam9g45_initialize(unsigned long main_clock);
17extern void __init at91x40_initialize(unsigned long main_clock); 18extern void __init at91x40_initialize(unsigned long main_clock);
18extern void __init at91cap9_initialize(unsigned long main_clock); 19extern void __init at91cap9_initialize(unsigned long main_clock);
19 20
@@ -23,6 +24,7 @@ extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
23extern void __init at91sam9261_init_interrupts(unsigned int priority[]); 24extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
24extern void __init at91sam9263_init_interrupts(unsigned int priority[]); 25extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
25extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); 26extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
27extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
26extern void __init at91x40_init_interrupts(unsigned int priority[]); 28extern void __init at91x40_init_interrupts(unsigned int priority[]);
27extern void __init at91cap9_init_interrupts(unsigned int priority[]); 29extern void __init at91cap9_init_interrupts(unsigned int priority[]);
28extern void __init at91_aic_init(unsigned int priority[]); 30extern void __init at91_aic_init(unsigned int priority[]);
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index e6afff849b85..74801d275cdc 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -80,7 +80,8 @@ struct at91_eth_data {
80}; 80};
81extern void __init at91_add_device_eth(struct at91_eth_data *data); 81extern void __init at91_add_device_eth(struct at91_eth_data *data);
82 82
83#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) 83#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
84 || defined(CONFIG_ARCH_AT91SAM9G45)
84#define eth_platform_data at91_eth_data 85#define eth_platform_data at91_eth_data
85#endif 86#endif
86 87
@@ -90,6 +91,7 @@ struct at91_usbh_data {
90 u8 vbus_pin[2]; /* port power-control pin */ 91 u8 vbus_pin[2]; /* port power-control pin */
91}; 92};
92extern void __init at91_add_device_usbh(struct at91_usbh_data *data); 93extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
94extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
93 95
94 /* NAND / SmartMedia */ 96 /* NAND / SmartMedia */
95struct atmel_nand_data { 97struct atmel_nand_data {
@@ -105,7 +107,11 @@ struct atmel_nand_data {
105extern void __init at91_add_device_nand(struct atmel_nand_data *data); 107extern void __init at91_add_device_nand(struct atmel_nand_data *data);
106 108
107 /* I2C*/ 109 /* I2C*/
110#if defined(CONFIG_ARCH_AT91SAM9G45)
111extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
112#else
108extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); 113extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
114#endif
109 115
110 /* SPI */ 116 /* SPI */
111extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); 117extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 20:02:18 -0500