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authorDavid Daney <ddaney@caviumnetworks.com>2010-02-18 14:48:20 -0500
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 06:53:40 -0500
commit541247f4d26f90ce0d277082d108feb121b6ae03 (patch)
treef8282f4bab6112f07d98366ac19d281e581553db /arch
parent399614226cfa45ffaba45b269e8af9ddc26de537 (diff)
MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c.
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/973/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index 4b92bfc662db..be531ec1f206 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -41,7 +41,7 @@ struct bar1_index_state {
41}; 41};
42 42
43#ifdef CONFIG_PCI 43#ifdef CONFIG_PCI
44static DEFINE_SPINLOCK(bar1_lock); 44static DEFINE_RAW_SPINLOCK(bar1_lock);
45static struct bar1_index_state bar1_state[32]; 45static struct bar1_index_state bar1_state[32];
46#endif 46#endif
47 47
@@ -198,7 +198,7 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
198 start_index = 31; 198 start_index = 31;
199 199
200 /* Only one processor can access the Bar register at once */ 200 /* Only one processor can access the Bar register at once */
201 spin_lock_irqsave(&bar1_lock, flags); 201 raw_spin_lock_irqsave(&bar1_lock, flags);
202 202
203 /* Look through Bar1 for existing mapping that will work */ 203 /* Look through Bar1 for existing mapping that will work */
204 for (index = start_index; index >= 0; index--) { 204 for (index = start_index; index >= 0; index--) {
@@ -250,7 +250,7 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
250 (unsigned long long) physical); 250 (unsigned long long) physical);
251 251
252done_unlock: 252done_unlock:
253 spin_unlock_irqrestore(&bar1_lock, flags); 253 raw_spin_unlock_irqrestore(&bar1_lock, flags);
254done: 254done:
255 pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result); 255 pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
256 return result; 256 return result;
@@ -324,14 +324,14 @@ void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
324 "Attempt to unmap an invalid address (0x%llx)\n", 324 "Attempt to unmap an invalid address (0x%llx)\n",
325 dma_addr); 325 dma_addr);
326 326
327 spin_lock_irqsave(&bar1_lock, flags); 327 raw_spin_lock_irqsave(&bar1_lock, flags);
328 bar1_state[index].ref_count--; 328 bar1_state[index].ref_count--;
329 if (bar1_state[index].ref_count == 0) 329 if (bar1_state[index].ref_count == 0)
330 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0); 330 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
331 else if (unlikely(bar1_state[index].ref_count < 0)) 331 else if (unlikely(bar1_state[index].ref_count < 0))
332 panic("dma_unmap_single: Bar1[%u] reference count < 0\n", 332 panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
333 (int) index); 333 (int) index);
334 spin_unlock_irqrestore(&bar1_lock, flags); 334 raw_spin_unlock_irqrestore(&bar1_lock, flags);
335done: 335done:
336 pr_debug("dma_unmap_single 0x%llx\n", dma_addr); 336 pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
337 return; 337 return;