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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-23 18:15:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-23 18:15:27 -0400
commit42cd71bf1e3a081b3150018bbf448cb6c8a844a5 (patch)
tree4a5d2eb0444255e4ad827a76dbd1417dd3876db6 /arch
parentf5039935ac685b3b9b8c13fbc33cac8643dee32e (diff)
parent9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0 (diff)
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (137 commits) ARM: bcmring: convert to use sp804 clockevents ARM: bcmring: convert to sp804 clocksource ARM: 6912/1: bcmring: Add clkdev table in init_early clockevents: ARM sp804: obtain sp804 timer rate via clks clockevents: ARM sp804: allow clockevent name to be specified clocksource: ARM sp804: obtain sp804 timer rate via clks clocksource: ARM sp804: allow clocksource name to be specified clocksource: convert OMAP1 to 32-bit down counting clocksource clocksource: convert MXS timrotv2 to 32-bit down counting clocksource clocksource: convert SPEAr platforms 16-bit up counting clocksource clocksource: convert Integrator/AP 16-bit down counting clocksource clocksource: convert W90x900 24-bit down counting clocksource clocksource: convert ARM 32-bit down counting clocksources clocksource: convert ARM 32-bit up counting clocksources clocksource: add common mmio clocksource ARM: update sa1100 to reflect PXA updates ARM: omap1: convert to using readl/writel instead of volatile struct ARM: omap1: delete useless interrupt handler ARM: s5p: consolidate selection of timer register ARM: 6939/1: fix missing 'cpu_relax()' declaration ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig89
-rw-r--r--arch/arm/Makefile7
-rw-r--r--arch/arm/boot/compressed/Makefile17
-rw-r--r--arch/arm/boot/compressed/decompress.c4
-rw-r--r--arch/arm/boot/compressed/head.S46
-rw-r--r--arch/arm/boot/compressed/misc.c24
-rw-r--r--arch/arm/common/gic.c84
-rw-r--r--arch/arm/common/sa1111.c8
-rw-r--r--arch/arm/common/timer-sp.c82
-rw-r--r--arch/arm/configs/dove_defconfig12
-rw-r--r--arch/arm/configs/mx1_defconfig1
-rw-r--r--arch/arm/configs/mx51_defconfig2
-rw-r--r--arch/arm/configs/mxs_defconfig129
-rw-r--r--arch/arm/configs/ns9xxx_defconfig56
-rw-r--r--arch/arm/configs/realview-smp_defconfig2
-rw-r--r--arch/arm/configs/realview_defconfig2
-rw-r--r--arch/arm/configs/spear310_defconfig52
-rw-r--r--arch/arm/configs/spear320_defconfig52
-rw-r--r--arch/arm/configs/spear3xx_defconfig (renamed from arch/arm/configs/spear300_defconfig)4
-rw-r--r--arch/arm/configs/spear6xx_defconfig (renamed from arch/arm/configs/spear600_defconfig)2
-rw-r--r--arch/arm/configs/stmp378x_defconfig128
-rw-r--r--arch/arm/configs/stmp37xx_defconfig108
-rw-r--r--arch/arm/configs/versatile_defconfig2
-rw-r--r--arch/arm/include/asm/dma.h4
-rw-r--r--arch/arm/include/asm/elf.h1
-rw-r--r--arch/arm/include/asm/futex.h137
-rw-r--r--arch/arm/include/asm/hardware/timer-sp.h4
-rw-r--r--arch/arm/include/asm/memory.h10
-rw-r--r--arch/arm/include/asm/ptrace.h6
-rw-r--r--arch/arm/include/asm/sizes.h42
-rw-r--r--arch/arm/include/asm/smp.h6
-rw-r--r--arch/arm/include/asm/spinlock.h2
-rw-r--r--arch/arm/kernel/perf_event.c5
-rw-r--r--arch/arm/kernel/ptrace.c348
-rw-r--r--arch/arm/kernel/setup.c13
-rw-r--r--arch/arm/kernel/smp.c7
-rw-r--r--arch/arm/mach-bcmring/arch.c1
-rw-r--r--arch/arm/mach-bcmring/core.c227
-rw-r--r--arch/arm/mach-bcmring/core.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h18
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h5
-rw-r--r--arch/arm/mach-davinci/irq.c93
-rw-r--r--arch/arm/mach-dove/common.c616
-rw-r--r--arch/arm/mach-dove/mpp.c134
-rw-r--r--arch/arm/mach-dove/mpp.h362
-rw-r--r--arch/arm/mach-ep93xx/gpio.c24
-rw-r--r--arch/arm/mach-exynos4/include/mach/smp.h19
-rw-r--r--arch/arm/mach-exynos4/irq-combiner.c6
-rw-r--r--arch/arm/mach-exynos4/platsmp.c5
-rw-r--r--arch/arm/mach-gemini/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-h720x/include/mach/memory.h3
-rw-r--r--arch/arm/mach-imx/Kconfig286
-rw-r--r--arch/arm/mach-imx/Makefile38
-rw-r--r--arch/arm/mach-imx/Makefile.boot4
-rw-r--r--arch/arm/mach-imx/cache-l2x0.c56
-rw-r--r--arch/arm/mach-imx/clock-imx31.c (renamed from arch/arm/mach-mx3/clock-imx31.c)3
-rw-r--r--arch/arm/mach-imx/clock-imx35.c (renamed from arch/arm/mach-mx3/clock-imx35.c)1
-rw-r--r--arch/arm/mach-imx/cpu-imx31.c (renamed from arch/arm/mach-mx3/cpu.c)38
-rw-r--r--arch/arm/mach-imx/cpu-imx35.c44
-rw-r--r--arch/arm/mach-imx/crmregs-imx31.h (renamed from arch/arm/mach-mx3/crm_regs.h)0
-rw-r--r--arch/arm/mach-imx/devices-imx1.h8
-rw-r--r--arch/arm/mach-imx/devices-imx21.h22
-rw-r--r--arch/arm/mach-imx/devices-imx25.h35
-rw-r--r--arch/arm/mach-imx/devices-imx27.h30
-rw-r--r--arch/arm/mach-imx/devices-imx31.h (renamed from arch/arm/mach-mx3/devices-imx31.h)36
-rw-r--r--arch/arm/mach-imx/devices-imx35.h (renamed from arch/arm/mach-mx3/devices-imx35.h)37
-rw-r--r--arch/arm/mach-imx/ehci-imx31.c (renamed from arch/arm/mach-mx3/ehci-imx31.c)1
-rw-r--r--arch/arm/mach-imx/ehci-imx35.c (renamed from arch/arm/mach-mx3/ehci-imx35.c)1
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c1
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c17
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c (renamed from arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c)29
-rw-r--r--arch/arm/mach-imx/iomux-imx31.c (renamed from arch/arm/mach-mx3/iomux-imx31.c)0
-rw-r--r--arch/arm/mach-imx/mach-apf9328.c144
-rw-r--r--arch/arm/mach-imx/mach-armadillo5x0.c (renamed from arch/arm/mach-mx3/mach-armadillo5x0.c)29
-rw-r--r--arch/arm/mach-imx/mach-bug.c (renamed from arch/arm/mach-mx3/mach-bug.c)1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c (renamed from arch/arm/mach-mx3/mach-cpuimx35.c)2
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c2
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c14
-rw-r--r--arch/arm/mach-imx/mach-kzm_arm11_01.c (renamed from arch/arm/mach-mx3/mach-kzm_arm11_01.c)1
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c1
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c1
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c13
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c1
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c (renamed from arch/arm/mach-mx3/mach-mx31_3ds.c)50
-rw-r--r--arch/arm/mach-imx/mach-mx31ads.c (renamed from arch/arm/mach-mx3/mach-mx31ads.c)1
-rw-r--r--arch/arm/mach-imx/mach-mx31lilly.c (renamed from arch/arm/mach-mx3/mach-mx31lilly.c)1
-rw-r--r--arch/arm/mach-imx/mach-mx31lite.c (renamed from arch/arm/mach-mx3/mach-mx31lite.c)1
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c (renamed from arch/arm/mach-mx3/mach-mx31moboard.c)75
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c (renamed from arch/arm/mach-mx3/mach-mx35_3ds.c)1
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c1
-rw-r--r--arch/arm/mach-imx/mach-pca100.c1
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c (renamed from arch/arm/mach-mx3/mach-pcm037.c)65
-rw-r--r--arch/arm/mach-imx/mach-pcm037_eet.c (renamed from arch/arm/mach-mx3/mach-pcm037_eet.c)17
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c1
-rw-r--r--arch/arm/mach-imx/mach-pcm043.c (renamed from arch/arm/mach-mx3/mach-pcm043.c)17
-rw-r--r--arch/arm/mach-imx/mach-qong.c (renamed from arch/arm/mach-mx3/mach-qong.c)15
-rw-r--r--arch/arm/mach-imx/mach-vpr200.c (renamed from arch/arm/mach-mx3/mach-vpr200.c)25
-rw-r--r--arch/arm/mach-imx/mm-imx31.c66
-rw-r--r--arch/arm/mach-imx/mm-imx35.c63
-rw-r--r--arch/arm/mach-imx/mx31lilly-db.c (renamed from arch/arm/mach-mx3/mx31lilly-db.c)13
-rw-r--r--arch/arm/mach-imx/mx31lite-db.c (renamed from arch/arm/mach-mx3/mx31lite-db.c)3
-rw-r--r--arch/arm/mach-imx/mx31moboard-devboard.c (renamed from arch/arm/mach-mx3/mx31moboard-devboard.c)1
-rw-r--r--arch/arm/mach-imx/mx31moboard-marxbot.c (renamed from arch/arm/mach-mx3/mx31moboard-marxbot.c)2
-rw-r--r--arch/arm/mach-imx/mx31moboard-smartbot.c (renamed from arch/arm/mach-mx3/mx31moboard-smartbot.c)1
-rw-r--r--arch/arm/mach-imx/pcm037.h (renamed from arch/arm/mach-mx3/pcm037.h)0
-rw-r--r--arch/arm/mach-integrator/Kconfig1
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c34
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c24
-rw-r--r--arch/arm/mach-iop32x/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-iop33x/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c23
-rw-r--r--arch/arm/mach-ixp4xx/common.c16
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/memory.h12
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-kirkwood/common.c601
-rw-r--r--arch/arm/mach-kirkwood/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-kirkwood/mpp.c58
-rw-r--r--arch/arm/mach-kirkwood/mpp.h6
-rw-r--r--arch/arm/mach-loki/common.c190
-rw-r--r--arch/arm/mach-lpc32xx/timer.c17
-rw-r--r--arch/arm/mach-mmp/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-msm/gpio-v2.c10
-rw-r--r--arch/arm/mach-msm/include/mach/smp.h23
-rw-r--r--arch/arm/mach-msm/platsmp.c4
-rw-r--r--arch/arm/mach-mv78xx0/common.c570
-rw-r--r--arch/arm/mach-mv78xx0/mpp.c58
-rw-r--r--arch/arm/mach-mv78xx0/mpp.h6
-rw-r--r--arch/arm/mach-mx3/Kconfig257
-rw-r--r--arch/arm/mach-mx3/Makefile26
-rw-r--r--arch/arm/mach-mx3/Makefile.boot3
-rw-r--r--arch/arm/mach-mx3/devices.c115
-rw-r--r--arch/arm/mach-mx3/devices.h4
-rw-r--r--arch/arm/mach-mx3/mm.c141
-rw-r--r--arch/arm/mach-mx5/Kconfig58
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c2
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c2
-rw-r--r--arch/arm/mach-mx5/board-mx50_rdp.c1
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c18
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c5
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikasb.c5
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c2
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c2
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c30
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c1
-rw-r--r--arch/arm/mach-mx5/cpu.c23
-rw-r--r--arch/arm/mach-mx5/devices-imx50.h6
-rw-r--r--arch/arm/mach-mx5/devices-imx51.h25
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h13
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c2
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c16
-rw-r--r--arch/arm/mach-mx5/mx51_efika.c3
-rw-r--r--arch/arm/mach-mxc91231/Kconfig11
-rw-r--r--arch/arm/mach-mxc91231/Makefile2
-rw-r--r--arch/arm/mach-mxc91231/Makefile.boot3
-rw-r--r--arch/arm/mach-mxc91231/clock.c640
-rw-r--r--arch/arm/mach-mxc91231/crm_regs.h394
-rw-r--r--arch/arm/mach-mxc91231/devices.c251
-rw-r--r--arch/arm/mach-mxc91231/devices.h13
-rw-r--r--arch/arm/mach-mxc91231/iomux.c177
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c62
-rw-r--r--arch/arm/mach-mxc91231/mm.c62
-rw-r--r--arch/arm/mach-mxc91231/system.c51
-rw-r--r--arch/arm/mach-mxs/Kconfig12
-rw-r--r--arch/arm/mach-mxs/Makefile1
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c2
-rw-r--r--arch/arm/mach-mxs/devices-mx28.h2
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-i2c.c5
-rw-r--r--arch/arm/mach-mxs/include/mach/devices-common.h5
-rw-r--r--arch/arm/mach-mxs/include/mach/mx23.h2
-rw-r--r--arch/arm/mach-mxs/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c4
-rw-r--r--arch/arm/mach-mxs/mach-stmp378x_devb.c120
-rw-r--r--arch/arm/mach-mxs/timer.c20
-rw-r--r--arch/arm/mach-netx/time.c16
-rw-r--r--arch/arm/mach-ns9xxx/Kconfig40
-rw-r--r--arch/arm/mach-ns9xxx/Makefile12
-rw-r--r--arch/arm/mach-ns9xxx/Makefile.boot2
-rw-r--r--arch/arm/mach-ns9xxx/board-a9m9750dev.c156
-rw-r--r--arch/arm/mach-ns9xxx/board-a9m9750dev.h15
-rw-r--r--arch/arm/mach-ns9xxx/board-jscc9p9360.c17
-rw-r--r--arch/arm/mach-ns9xxx/board-jscc9p9360.h13
-rw-r--r--arch/arm/mach-ns9xxx/clock.c215
-rw-r--r--arch/arm/mach-ns9xxx/clock.h35
-rw-r--r--arch/arm/mach-ns9xxx/generic.c19
-rw-r--r--arch/arm/mach-ns9xxx/generic.h16
-rw-r--r--arch/arm/mach-ns9xxx/gpio-ns9360.c118
-rw-r--r--arch/arm/mach-ns9xxx/gpio-ns9360.h13
-rw-r--r--arch/arm/mach-ns9xxx/gpio.c147
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/board.h40
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/entry-macro.S28
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/gpio.h47
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/hardware.h77
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/io.h20
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/irqs.h86
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/memory.h24
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/module.h55
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h32
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/processor.h42
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/regs-bbu.h45
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h24
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/regs-mem.h135
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h31
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h148
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/system.h35
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/timex.h20
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/uncompress.h164
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/vmalloc.h16
-rw-r--r--arch/arm/mach-ns9xxx/irq.c74
-rw-r--r--arch/arm/mach-ns9xxx/mach-cc9p9360dev.c43
-rw-r--r--arch/arm/mach-ns9xxx/mach-cc9p9360js.c31
-rw-r--r--arch/arm/mach-ns9xxx/plat-serial8250.c70
-rw-r--r--arch/arm/mach-ns9xxx/processor-ns9360.c53
-rw-r--r--arch/arm/mach-ns9xxx/time-ns9360.c181
-rw-r--r--arch/arm/mach-nuc93x/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-omap1/flash.c2
-rw-r--r--arch/arm/mach-omap1/time.c69
-rw-r--r--arch/arm/mach-omap2/include/mach/omap4-common.h7
-rw-r--r--arch/arm/mach-omap2/irq.c97
-rw-r--r--arch/arm/mach-omap2/omap-smp.c5
-rw-r--r--arch/arm/mach-orion5x/common.c478
-rw-r--r--arch/arm/mach-orion5x/d2net-setup.c44
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c44
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c132
-rw-r--r--arch/arm/mach-orion5x/edmini_v2-setup.c44
-rw-r--r--arch/arm/mach-orion5x/kurobox_pro-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ls-chl-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ls_hgl-setup.c44
-rw-r--r--arch/arm/mach-orion5x/lsmini-setup.c44
-rw-r--r--arch/arm/mach-orion5x/mpp.c150
-rw-r--r--arch/arm/mach-orion5x/mpp.h191
-rw-r--r--arch/arm/mach-orion5x/mss2-setup.c44
-rw-r--r--arch/arm/mach-orion5x/mv2120-setup.c44
-rw-r--r--arch/arm/mach-orion5x/net2big-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-ge-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f5182-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c1
-rw-r--r--arch/arm/mach-orion5x/terastation_pro2-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ts78xx-setup.c44
-rw-r--r--arch/arm/mach-orion5x/wnr854t-setup.c44
-rw-r--r--arch/arm/mach-orion5x/wrt350n-v2-setup.c44
-rw-r--r--arch/arm/mach-pxa/cm-x2xx-pci.c27
-rw-r--r--arch/arm/mach-pxa/hx4700.c2
-rw-r--r--arch/arm/mach-pxa/include/mach/memory.h10
-rw-r--r--arch/arm/mach-pxa/include/mach/uncompress.h6
-rw-r--r--arch/arm/mach-pxa/magician.c2
-rw-r--r--arch/arm/mach-pxa/time.c17
-rw-r--r--arch/arm/mach-realview/core.c63
-rw-r--r--arch/arm/mach-realview/include/mach/memory.h9
-rw-r--r--arch/arm/mach-realview/include/mach/smp.h14
-rw-r--r--arch/arm/mach-realview/platsmp.c3
-rw-r--r--arch/arm/mach-rpc/include/mach/uncompress.h12
-rw-r--r--arch/arm/mach-s3c2410/nor-simtec.c2
-rw-r--r--arch/arm/mach-s3c64xx/irq.c7
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/uncompress.h6
-rw-r--r--arch/arm/mach-sa1100/include/mach/memory.h12
-rw-r--r--arch/arm/mach-sa1100/time.c24
-rw-r--r--arch/arm/mach-shark/include/mach/memory.h20
-rw-r--r--arch/arm/mach-shmobile/include/mach/smp.h16
-rw-r--r--arch/arm/mach-shmobile/platsmp.c3
-rw-r--r--arch/arm/mach-spear3xx/Kconfig30
-rw-r--r--arch/arm/mach-spear3xx/Kconfig30017
-rw-r--r--arch/arm/mach-spear3xx/Kconfig31017
-rw-r--r--arch/arm/mach-spear3xx/Kconfig32017
-rw-r--r--arch/arm/mach-spear3xx/clock.c74
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h205
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h206
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h26
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h44
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h48
-rw-r--r--arch/arm/mach-spear3xx/spear300.c163
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c32
-rw-r--r--arch/arm/mach-spear3xx/spear310.c149
-rw-r--r--arch/arm/mach-spear3xx/spear310_evb.c45
-rw-r--r--arch/arm/mach-spear3xx/spear320.c251
-rw-r--r--arch/arm/mach-spear3xx/spear320_evb.c40
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c132
-rw-r--r--arch/arm/mach-spear6xx/Kconfig15
-rw-r--r--arch/arm/mach-spear6xx/Kconfig60017
-rw-r--r--arch/arm/mach-spear6xx/clock.c4
-rw-r--r--arch/arm/mach-spear6xx/include/mach/generic.h2
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c2
-rw-r--r--arch/arm/mach-stmp378x/Makefile2
-rw-r--r--arch/arm/mach-stmp378x/Makefile.boot3
-rw-r--r--arch/arm/mach-stmp378x/include/mach/entry-macro.S35
-rw-r--r--arch/arm/mach-stmp378x/include/mach/irqs.h95
-rw-r--r--arch/arm/mach-stmp378x/include/mach/pins.h151
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbh.h101
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbx.h119
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioin.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioout.h104
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-bch.h56
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h88
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dcp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-digctl.h38
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dram.h27
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dri.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ecc8.h39
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-emi.h25
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-gpmi.h78
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-icoll.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ir.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lcdif.h195
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lradc.h99
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ocotp.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h90
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-power.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pwm.h53
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pxp.h140
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-rtc.h59
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-saif.h21
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-spdif.h49
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ssp.h102
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-sydma.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-timrot.h68
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-tvenc.h67
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartapp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbphy.h37
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.c299
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.h25
-rw-r--r--arch/arm/mach-stmp378x/stmp378x_devb.c332
-rw-r--r--arch/arm/mach-stmp37xx/Makefile2
-rw-r--r--arch/arm/mach-stmp37xx/Makefile.boot3
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/entry-macro.S37
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/irqs.h99
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/pins.h147
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbh.h97
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbx.h113
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioin.h61
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioout.h111
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h72
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-digctl.h24
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h37
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h63
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-icoll.h43
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h89
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lradc.h97
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h88
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-power.h56
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pwm.h51
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-rtc.h57
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ssp.h101
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-timrot.h49
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h85
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h37
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx.c219
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx.h24
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx_devb.c99
-rw-r--r--arch/arm/mach-tcc8k/time.c16
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/gpio.c9
-rw-r--r--arch/arm/mach-tegra/include/mach/legacy_irq.h35
-rw-r--r--arch/arm/mach-tegra/include/mach/smp.h14
-rw-r--r--arch/arm/mach-tegra/irq.c174
-rw-r--r--arch/arm/mach-tegra/legacy_irq.c215
-rw-r--r--arch/arm/mach-tegra/platsmp.c3
-rw-r--r--arch/arm/mach-tegra/timer.c16
-rw-r--r--arch/arm/mach-u300/timer.c18
-rw-r--r--arch/arm/mach-ux500/include/mach/smp.h24
-rw-r--r--arch/arm/mach-ux500/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-ux500/platsmp.c8
-rw-r--r--arch/arm/mach-versatile/core.c44
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c19
-rw-r--r--arch/arm/mach-vexpress/include/mach/smp.h13
-rw-r--r--arch/arm/mach-vexpress/v2m.c39
-rw-r--r--arch/arm/mach-w90x900/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-w90x900/time.c17
-rw-r--r--arch/arm/mm/flush.c7
-rw-r--r--arch/arm/mm/init.c23
-rw-r--r--arch/arm/mm/proc-v6.S34
-rw-r--r--arch/arm/plat-mxc/Kconfig28
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig7
-rw-r--r--arch/arm/plat-mxc/devices/Makefile2
-rw-r--r--arch/arm/plat-mxc/devices/platform-ipu-core.c129
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_rtc.c40
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c2
-rw-r--r--arch/arm/plat-mxc/epit.c18
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S7
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h27
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/io.h23
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h283
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h256
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h2
-rw-r--r--arch/arm/plat-mxc/system.c6
-rw-r--r--arch/arm/plat-mxc/time.c40
-rw-r--r--arch/arm/plat-nomadik/Kconfig1
-rw-r--r--arch/arm/plat-nomadik/gpio.c12
-rw-r--r--arch/arm/plat-nomadik/timer.c31
-rw-r--r--arch/arm/plat-omap/Kconfig2
-rw-r--r--arch/arm/plat-omap/gpio.c7
-rw-r--r--arch/arm/plat-omap/include/plat/flash.h2
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h36
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h4
-rw-r--r--arch/arm/plat-orion/Makefile2
-rw-r--r--arch/arm/plat-orion/common.c957
-rw-r--r--arch/arm/plat-orion/gpio.c112
-rw-r--r--arch/arm/plat-orion/include/plat/common.h117
-rw-r--r--arch/arm/plat-orion/include/plat/gpio.h1
-rw-r--r--arch/arm/plat-orion/include/plat/mpp.h34
-rw-r--r--arch/arm/plat-orion/irq.c49
-rw-r--r--arch/arm/plat-orion/mpp.c78
-rw-r--r--arch/arm/plat-orion/time.c21
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c116
-rw-r--r--arch/arm/plat-s5p/irq.c6
-rw-r--r--arch/arm/plat-s5p/s5p-time.c58
-rw-r--r--arch/arm/plat-samsung/Kconfig1
-rw-r--r--arch/arm/plat-samsung/include/plat/irq-vic-timer.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/uncompress.h4
-rw-r--r--arch/arm/plat-samsung/irq-uart.c83
-rw-r--r--arch/arm/plat-samsung/irq-vic-timer.c69
-rw-r--r--arch/arm/plat-spear/clock.c5
-rw-r--r--arch/arm/plat-spear/include/plat/clock.h1
-rw-r--r--arch/arm/plat-spear/time.c16
-rw-r--r--arch/arm/plat-stmp3xxx/Kconfig37
-rw-r--r--arch/arm/plat-stmp3xxx/Makefile5
-rw-r--r--arch/arm/plat-stmp3xxx/clock.c1134
-rw-r--r--arch/arm/plat-stmp3xxx/clock.h61
-rw-r--r--arch/arm/plat-stmp3xxx/core.c128
-rw-r--r--arch/arm/plat-stmp3xxx/devices.c389
-rw-r--r--arch/arm/plat-stmp3xxx/dma.c464
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/clkdev.h18
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/cputype.h33
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/debug-macro.S39
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/dma.h153
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpio.h28
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpmi.h12
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/hardware.h32
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/io.h25
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/memory.h22
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/mmc.h14
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pinmux.h157
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pins.h30
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/platform.h68
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h54
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/system.h49
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/timex.h20
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/uncompress.h53
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/vmalloc.h12
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c50
-rw-r--r--arch/arm/plat-stmp3xxx/pinmux.c550
-rw-r--r--arch/arm/plat-stmp3xxx/timer.c186
-rw-r--r--arch/arm/plat-versatile/platsmp.c3
-rw-r--r--arch/arm/tools/mach-types142
465 files changed, 5782 insertions, 22194 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 377a7a595b08..7275009686e6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -197,15 +197,21 @@ config ARM_PATCH_PHYS_VIRT
197 depends on !XIP_KERNEL && MMU 197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM 198 depends on !ARCH_REALVIEW || !SPARSEMEM
199 help 199 help
200 Patch phys-to-virt translation functions at runtime according to 200 Patch phys-to-virt and virt-to-phys translation functions at
201 the position of the kernel in system memory. 201 boot and module load time according to the position of the
202 kernel in system memory.
202 203
203 This can only be used with non-XIP with MMU kernels where 204 This can only be used with non-XIP MMU kernels where the base
204 the base of physical memory is at a 16MB boundary. 205 of physical memory is at a 16MB boundary, or theoretically 64K
206 for the MSM machine class.
205 207
206config ARM_PATCH_PHYS_VIRT_16BIT 208config ARM_PATCH_PHYS_VIRT_16BIT
207 def_bool y 209 def_bool y
208 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM 210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
211 help
212 This option extends the physical to virtual translation patching
213 to allow physical memory down to a theoretical minimum of 64K
214 boundaries.
209 215
210source "init/Kconfig" 216source "init/Kconfig"
211 217
@@ -297,6 +303,7 @@ config ARCH_BCMRING
297 depends on MMU 303 depends on MMU
298 select CPU_V6 304 select CPU_V6
299 select ARM_AMBA 305 select ARM_AMBA
306 select ARM_TIMER_SP804
300 select CLKDEV_LOOKUP 307 select CLKDEV_LOOKUP
301 select GENERIC_CLOCKEVENTS 308 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB 309 select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -366,6 +373,7 @@ config ARCH_MXC
366 select GENERIC_CLOCKEVENTS 373 select GENERIC_CLOCKEVENTS
367 select ARCH_REQUIRE_GPIOLIB 374 select ARCH_REQUIRE_GPIOLIB
368 select CLKDEV_LOOKUP 375 select CLKDEV_LOOKUP
376 select CLKSRC_MMIO
369 select HAVE_SCHED_CLOCK 377 select HAVE_SCHED_CLOCK
370 help 378 help
371 Support for Freescale MXC/iMX-based family of processors 379 Support for Freescale MXC/iMX-based family of processors
@@ -375,21 +383,13 @@ config ARCH_MXS
375 select GENERIC_CLOCKEVENTS 383 select GENERIC_CLOCKEVENTS
376 select ARCH_REQUIRE_GPIOLIB 384 select ARCH_REQUIRE_GPIOLIB
377 select CLKDEV_LOOKUP 385 select CLKDEV_LOOKUP
386 select CLKSRC_MMIO
378 help 387 help
379 Support for Freescale MXS-based family of processors 388 Support for Freescale MXS-based family of processors
380 389
381config ARCH_STMP3XXX
382 bool "Freescale STMP3xxx"
383 select CPU_ARM926T
384 select CLKDEV_LOOKUP
385 select ARCH_REQUIRE_GPIOLIB
386 select GENERIC_CLOCKEVENTS
387 select USB_ARCH_HAS_EHCI
388 help
389 Support for systems based on the Freescale 3xxx CPUs.
390
391config ARCH_NETX 390config ARCH_NETX
392 bool "Hilscher NetX based" 391 bool "Hilscher NetX based"
392 select CLKSRC_MMIO
393 select CPU_ARM926T 393 select CPU_ARM926T
394 select ARM_VIC 394 select ARM_VIC
395 select GENERIC_CLOCKEVENTS 395 select GENERIC_CLOCKEVENTS
@@ -457,6 +457,7 @@ config ARCH_IXP2000
457config ARCH_IXP4XX 457config ARCH_IXP4XX
458 bool "IXP4xx-based" 458 bool "IXP4xx-based"
459 depends on MMU 459 depends on MMU
460 select CLKSRC_MMIO
460 select CPU_XSCALE 461 select CPU_XSCALE
461 select GENERIC_GPIO 462 select GENERIC_GPIO
462 select GENERIC_CLOCKEVENTS 463 select GENERIC_CLOCKEVENTS
@@ -468,7 +469,7 @@ config ARCH_IXP4XX
468 469
469config ARCH_DOVE 470config ARCH_DOVE
470 bool "Marvell Dove" 471 bool "Marvell Dove"
471 select CPU_V6K 472 select CPU_V7
472 select PCI 473 select PCI
473 select ARCH_REQUIRE_GPIOLIB 474 select ARCH_REQUIRE_GPIOLIB
474 select GENERIC_CLOCKEVENTS 475 select GENERIC_CLOCKEVENTS
@@ -497,6 +498,7 @@ config ARCH_LOKI
497 498
498config ARCH_LPC32XX 499config ARCH_LPC32XX
499 bool "NXP LPC32XX" 500 bool "NXP LPC32XX"
501 select CLKSRC_MMIO
500 select CPU_ARM926T 502 select CPU_ARM926T
501 select ARCH_REQUIRE_GPIOLIB 503 select ARCH_REQUIRE_GPIOLIB
502 select HAVE_IDE 504 select HAVE_IDE
@@ -554,23 +556,12 @@ config ARCH_KS8695
554 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 556 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
555 System-on-Chip devices. 557 System-on-Chip devices.
556 558
557config ARCH_NS9XXX
558 bool "NetSilicon NS9xxx"
559 select CPU_ARM926T
560 select GENERIC_GPIO
561 select GENERIC_CLOCKEVENTS
562 select HAVE_CLK
563 help
564 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
565 System.
566
567 <http://www.digi.com/products/microprocessors/index.jsp>
568
569config ARCH_W90X900 559config ARCH_W90X900
570 bool "Nuvoton W90X900 CPU" 560 bool "Nuvoton W90X900 CPU"
571 select CPU_ARM926T 561 select CPU_ARM926T
572 select ARCH_REQUIRE_GPIOLIB 562 select ARCH_REQUIRE_GPIOLIB
573 select CLKDEV_LOOKUP 563 select CLKDEV_LOOKUP
564 select CLKSRC_MMIO
574 select GENERIC_CLOCKEVENTS 565 select GENERIC_CLOCKEVENTS
575 help 566 help
576 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 567 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
@@ -592,6 +583,7 @@ config ARCH_NUC93X
592config ARCH_TEGRA 583config ARCH_TEGRA
593 bool "NVIDIA Tegra" 584 bool "NVIDIA Tegra"
594 select CLKDEV_LOOKUP 585 select CLKDEV_LOOKUP
586 select CLKSRC_MMIO
595 select GENERIC_TIME 587 select GENERIC_TIME
596 select GENERIC_CLOCKEVENTS 588 select GENERIC_CLOCKEVENTS
597 select GENERIC_GPIO 589 select GENERIC_GPIO
@@ -617,6 +609,7 @@ config ARCH_PXA
617 select ARCH_MTD_XIP 609 select ARCH_MTD_XIP
618 select ARCH_HAS_CPUFREQ 610 select ARCH_HAS_CPUFREQ
619 select CLKDEV_LOOKUP 611 select CLKDEV_LOOKUP
612 select CLKSRC_MMIO
620 select ARCH_REQUIRE_GPIOLIB 613 select ARCH_REQUIRE_GPIOLIB
621 select GENERIC_CLOCKEVENTS 614 select GENERIC_CLOCKEVENTS
622 select HAVE_SCHED_CLOCK 615 select HAVE_SCHED_CLOCK
@@ -667,6 +660,7 @@ config ARCH_RPC
667 660
668config ARCH_SA1100 661config ARCH_SA1100
669 bool "SA1100-based" 662 bool "SA1100-based"
663 select CLKSRC_MMIO
670 select CPU_SA1100 664 select CPU_SA1100
671 select ISA 665 select ISA
672 select ARCH_SPARSEMEM_ENABLE 666 select ARCH_SPARSEMEM_ENABLE
@@ -803,6 +797,7 @@ config ARCH_SHARK
803 797
804config ARCH_TCC_926 798config ARCH_TCC_926
805 bool "Telechips TCC ARM926-based systems" 799 bool "Telechips TCC ARM926-based systems"
800 select CLKSRC_MMIO
806 select CPU_ARM926T 801 select CPU_ARM926T
807 select HAVE_CLK 802 select HAVE_CLK
808 select CLKDEV_LOOKUP 803 select CLKDEV_LOOKUP
@@ -813,6 +808,7 @@ config ARCH_TCC_926
813config ARCH_U300 808config ARCH_U300
814 bool "ST-Ericsson U300 Series" 809 bool "ST-Ericsson U300 Series"
815 depends on MMU 810 depends on MMU
811 select CLKSRC_MMIO
816 select CPU_ARM926T 812 select CPU_ARM926T
817 select HAVE_SCHED_CLOCK 813 select HAVE_SCHED_CLOCK
818 select HAVE_TCM 814 select HAVE_TCM
@@ -854,6 +850,7 @@ config ARCH_DAVINCI
854 select HAVE_IDE 850 select HAVE_IDE
855 select CLKDEV_LOOKUP 851 select CLKDEV_LOOKUP
856 select GENERIC_ALLOCATOR 852 select GENERIC_ALLOCATOR
853 select GENERIC_IRQ_CHIP
857 select ARCH_HAS_HOLES_MEMORYMODEL 854 select ARCH_HAS_HOLES_MEMORYMODEL
858 help 855 help
859 Support for TI's DaVinci platform. 856 Support for TI's DaVinci platform.
@@ -874,6 +871,7 @@ config PLAT_SPEAR
874 select ARM_AMBA 871 select ARM_AMBA
875 select ARCH_REQUIRE_GPIOLIB 872 select ARCH_REQUIRE_GPIOLIB
876 select CLKDEV_LOOKUP 873 select CLKDEV_LOOKUP
874 select CLKSRC_MMIO
877 select GENERIC_CLOCKEVENTS 875 select GENERIC_CLOCKEVENTS
878 select HAVE_CLK 876 select HAVE_CLK
879 help 877 help
@@ -951,8 +949,6 @@ source "arch/arm/mach-netx/Kconfig"
951source "arch/arm/mach-nomadik/Kconfig" 949source "arch/arm/mach-nomadik/Kconfig"
952source "arch/arm/plat-nomadik/Kconfig" 950source "arch/arm/plat-nomadik/Kconfig"
953 951
954source "arch/arm/mach-ns9xxx/Kconfig"
955
956source "arch/arm/mach-nuc93x/Kconfig" 952source "arch/arm/mach-nuc93x/Kconfig"
957 953
958source "arch/arm/plat-omap/Kconfig" 954source "arch/arm/plat-omap/Kconfig"
@@ -1005,8 +1001,6 @@ source "arch/arm/mach-exynos4/Kconfig"
1005 1001
1006source "arch/arm/mach-shmobile/Kconfig" 1002source "arch/arm/mach-shmobile/Kconfig"
1007 1003
1008source "arch/arm/plat-stmp3xxx/Kconfig"
1009
1010source "arch/arm/mach-tegra/Kconfig" 1004source "arch/arm/mach-tegra/Kconfig"
1011 1005
1012source "arch/arm/mach-u300/Kconfig" 1006source "arch/arm/mach-u300/Kconfig"
@@ -1033,6 +1027,8 @@ config PLAT_IOP
1033 1027
1034config PLAT_ORION 1028config PLAT_ORION
1035 bool 1029 bool
1030 select CLKSRC_MMIO
1031 select GENERIC_IRQ_CHIP
1036 select HAVE_SCHED_CLOCK 1032 select HAVE_SCHED_CLOCK
1037 1033
1038config PLAT_PXA 1034config PLAT_PXA
@@ -1043,6 +1039,7 @@ config PLAT_VERSATILE
1043 1039
1044config ARM_TIMER_SP804 1040config ARM_TIMER_SP804
1045 bool 1041 bool
1042 select CLKSRC_MMIO
1046 1043
1047source arch/arm/mm/Kconfig 1044source arch/arm/mm/Kconfig
1048 1045
@@ -1318,8 +1315,7 @@ menu "Kernel Features"
1318source "kernel/time/Kconfig" 1315source "kernel/time/Kconfig"
1319 1316
1320config SMP 1317config SMP
1321 bool "Symmetric Multi-Processing (EXPERIMENTAL)" 1318 bool "Symmetric Multi-Processing"
1322 depends on EXPERIMENTAL
1323 depends on CPU_V6K || CPU_V7 1319 depends on CPU_V6K || CPU_V7
1324 depends on GENERIC_CLOCKEVENTS 1320 depends on GENERIC_CLOCKEVENTS
1325 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ 1321 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
@@ -1521,8 +1517,8 @@ config ARCH_SELECT_MEMORY_MODEL
1521 def_bool ARCH_SPARSEMEM_ENABLE 1517 def_bool ARCH_SPARSEMEM_ENABLE
1522 1518
1523config HIGHMEM 1519config HIGHMEM
1524 bool "High Memory Support (EXPERIMENTAL)" 1520 bool "High Memory Support"
1525 depends on MMU && EXPERIMENTAL 1521 depends on MMU
1526 help 1522 help
1527 The address space of ARM processors is only 4 Gigabytes large 1523 The address space of ARM processors is only 4 Gigabytes large
1528 and it has to accommodate user address space, kernel address 1524 and it has to accommodate user address space, kernel address
@@ -1742,16 +1738,31 @@ config CMDLINE
1742 time by entering them here. As a minimum, you should specify the 1738 time by entering them here. As a minimum, you should specify the
1743 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1739 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1744 1740
1741choice
1742 prompt "Kernel command line type" if CMDLINE != ""
1743 default CMDLINE_FROM_BOOTLOADER
1744
1745config CMDLINE_FROM_BOOTLOADER
1746 bool "Use bootloader kernel arguments if available"
1747 help
1748 Uses the command-line options passed by the boot loader. If
1749 the boot loader doesn't provide any, the default kernel command
1750 string provided in CMDLINE will be used.
1751
1752config CMDLINE_EXTEND
1753 bool "Extend bootloader kernel arguments"
1754 help
1755 The command-line arguments provided by the boot loader will be
1756 appended to the default kernel command string.
1757
1745config CMDLINE_FORCE 1758config CMDLINE_FORCE
1746 bool "Always use the default kernel command string" 1759 bool "Always use the default kernel command string"
1747 depends on CMDLINE != ""
1748 help 1760 help
1749 Always use the default kernel command string, even if the boot 1761 Always use the default kernel command string, even if the boot
1750 loader passes other arguments to the kernel. 1762 loader passes other arguments to the kernel.
1751 This is useful if you cannot or don't want to change the 1763 This is useful if you cannot or don't want to change the
1752 command-line options your boot loader passes to the kernel. 1764 command-line options your boot loader passes to the kernel.
1753 1765endchoice
1754 If unsure, say N.
1755 1766
1756config XIP_KERNEL 1767config XIP_KERNEL
1757 bool "Kernel Execute-In-Place from ROM" 1768 bool "Kernel Execute-In-Place from ROM"
@@ -2010,7 +2021,7 @@ menu "Power management options"
2010source "kernel/power/Kconfig" 2021source "kernel/power/Kconfig"
2011 2022
2012config ARCH_SUSPEND_POSSIBLE 2023config ARCH_SUSPEND_POSSIBLE
2013 depends on !ARCH_S5P64X0 && !ARCH_S5P6442 2024 depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100
2014 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2025 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2015 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2026 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2016 def_bool y 2027 def_bool y
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c7d321a3d95d..25750bcb3397 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -158,13 +158,11 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
158machine-$(CONFIG_ARCH_MX1) := imx 158machine-$(CONFIG_ARCH_MX1) := imx
159machine-$(CONFIG_ARCH_MX2) := imx 159machine-$(CONFIG_ARCH_MX2) := imx
160machine-$(CONFIG_ARCH_MX25) := imx 160machine-$(CONFIG_ARCH_MX25) := imx
161machine-$(CONFIG_ARCH_MX3) := mx3 161machine-$(CONFIG_ARCH_MX3) := imx
162machine-$(CONFIG_ARCH_MX5) := mx5 162machine-$(CONFIG_ARCH_MX5) := mx5
163machine-$(CONFIG_ARCH_MXC91231) := mxc91231
164machine-$(CONFIG_ARCH_MXS) := mxs 163machine-$(CONFIG_ARCH_MXS) := mxs
165machine-$(CONFIG_ARCH_NETX) := netx 164machine-$(CONFIG_ARCH_NETX) := netx
166machine-$(CONFIG_ARCH_NOMADIK) := nomadik 165machine-$(CONFIG_ARCH_NOMADIK) := nomadik
167machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
168machine-$(CONFIG_ARCH_OMAP1) := omap1 166machine-$(CONFIG_ARCH_OMAP1) := omap1
169machine-$(CONFIG_ARCH_OMAP2) := omap2 167machine-$(CONFIG_ARCH_OMAP2) := omap2
170machine-$(CONFIG_ARCH_OMAP3) := omap2 168machine-$(CONFIG_ARCH_OMAP3) := omap2
@@ -185,8 +183,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
185machine-$(CONFIG_ARCH_SA1100) := sa1100 183machine-$(CONFIG_ARCH_SA1100) := sa1100
186machine-$(CONFIG_ARCH_SHARK) := shark 184machine-$(CONFIG_ARCH_SHARK) := shark
187machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 185machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
188machine-$(CONFIG_ARCH_STMP378X) := stmp378x
189machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
190machine-$(CONFIG_ARCH_TCC8K) := tcc8k 186machine-$(CONFIG_ARCH_TCC8K) := tcc8k
191machine-$(CONFIG_ARCH_TEGRA) := tegra 187machine-$(CONFIG_ARCH_TEGRA) := tegra
192machine-$(CONFIG_ARCH_U300) := u300 188machine-$(CONFIG_ARCH_U300) := u300
@@ -207,7 +203,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx
207plat-$(CONFIG_ARCH_MXC) := mxc 203plat-$(CONFIG_ARCH_MXC) := mxc
208plat-$(CONFIG_ARCH_OMAP) := omap 204plat-$(CONFIG_ARCH_OMAP) := omap
209plat-$(CONFIG_ARCH_S3C64XX) := samsung 205plat-$(CONFIG_ARCH_S3C64XX) := samsung
210plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
211plat-$(CONFIG_ARCH_TCC_926) := tcc 206plat-$(CONFIG_ARCH_TCC_926) := tcc
212plat-$(CONFIG_PLAT_IOP) := iop 207plat-$(CONFIG_PLAT_IOP) := iop
213plat-$(CONFIG_PLAT_NOMADIK) := nomadik 208plat-$(CONFIG_PLAT_NOMADIK) := nomadik
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 0c6852d93506..23aad0722303 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -98,8 +98,6 @@ endif
98ccflags-y := -fpic -fno-builtin 98ccflags-y := -fpic -fno-builtin
99asflags-y := -Wa,-march=all 99asflags-y := -Wa,-march=all
100 100
101# Provide size of uncompressed kernel to the decompressor via a linker symbol.
102LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image)
103# Supply ZRELADDR to the decompressor via a linker symbol. 101# Supply ZRELADDR to the decompressor via a linker symbol.
104ifneq ($(CONFIG_AUTO_ZRELADDR),y) 102ifneq ($(CONFIG_AUTO_ZRELADDR),y)
105LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) 103LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
@@ -122,10 +120,23 @@ lib1funcs = $(obj)/lib1funcs.o
122$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE 120$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
123 $(call cmd,shipped) 121 $(call cmd,shipped)
124 122
123# We need to prevent any GOTOFF relocs being used with references
124# to symbols in the .bss section since we cannot relocate them
125# independently from the rest at run time. This can be achieved by
126# ensuring that no private .bss symbols exist, as global symbols
127# always have a GOT entry which is what we need.
128# The .data section is already discarded by the linker script so no need
129# to bother about it here.
130check_for_bad_syms = \
131bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \
132[ -z "$$bad_syms" ] || \
133 ( echo "following symbols must have non local/private scope:" >&2; \
134 echo "$$bad_syms" >&2; rm -f $@; false )
135
125$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ 136$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
126 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE 137 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
127 $(call if_changed,ld) 138 $(call if_changed,ld)
128 @: 139 @$(check_for_bad_syms)
129 140
130$(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE 141$(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE
131 $(call if_changed,$(suffix_y)) 142 $(call if_changed,$(suffix_y))
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 4c72a97bc3e1..07be5a2f8302 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -44,7 +44,7 @@ extern void error(char *);
44#include "../../../../lib/decompress_unlzma.c" 44#include "../../../../lib/decompress_unlzma.c"
45#endif 45#endif
46 46
47void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) 47int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
48{ 48{
49 decompress(input, len, NULL, NULL, output, NULL, error); 49 return decompress(input, len, NULL, NULL, output, NULL, error);
50} 50}
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 49f5b2eaaa87..f9da41921c52 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -179,7 +179,7 @@ not_angel:
179 bl cache_on 179 bl cache_on
180 180
181restart: adr r0, LC0 181restart: adr r0, LC0
182 ldmia r0, {r1, r2, r3, r6, r9, r11, r12} 182 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
183 ldr sp, [r0, #28] 183 ldr sp, [r0, #28]
184 184
185 /* 185 /*
@@ -188,6 +188,20 @@ restart: adr r0, LC0
188 */ 188 */
189 sub r0, r0, r1 @ calculate the delta offset 189 sub r0, r0, r1 @ calculate the delta offset
190 add r6, r6, r0 @ _edata 190 add r6, r6, r0 @ _edata
191 add r10, r10, r0 @ inflated kernel size location
192
193 /*
194 * The kernel build system appends the size of the
195 * decompressed kernel at the end of the compressed data
196 * in little-endian form.
197 */
198 ldrb r9, [r10, #0]
199 ldrb lr, [r10, #1]
200 orr r9, r9, lr, lsl #8
201 ldrb lr, [r10, #2]
202 ldrb r10, [r10, #3]
203 orr r9, r9, lr, lsl #16
204 orr r9, r9, r10, lsl #24
191 205
192#ifndef CONFIG_ZBOOT_ROM 206#ifndef CONFIG_ZBOOT_ROM
193 /* malloc space is above the relocated stack (64k max) */ 207 /* malloc space is above the relocated stack (64k max) */
@@ -347,10 +361,10 @@ LC0: .word LC0 @ r1
347 .word __bss_start @ r2 361 .word __bss_start @ r2
348 .word _end @ r3 362 .word _end @ r3
349 .word _edata @ r6 363 .word _edata @ r6
350 .word _image_size @ r9 364 .word input_data_end - 4 @ r10 (inflated size location)
351 .word _got_start @ r11 365 .word _got_start @ r11
352 .word _got_end @ ip 366 .word _got_end @ ip
353 .word user_stack_end @ sp 367 .word .L_user_stack_end @ sp
354 .size LC0, . - LC0 368 .size LC0, . - LC0
355 369
356#ifdef CONFIG_ARCH_RPC 370#ifdef CONFIG_ARCH_RPC
@@ -459,7 +473,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
459 orr r1, r1, #3 << 10 473 orr r1, r1, #3 << 10
460 add r2, r3, #16384 474 add r2, r3, #16384
4611: cmp r1, r9 @ if virt > start of RAM 4751: cmp r1, r9 @ if virt > start of RAM
476#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
477 orrhs r1, r1, #0x08 @ set cacheable
478#else
462 orrhs r1, r1, #0x0c @ set cacheable, bufferable 479 orrhs r1, r1, #0x0c @ set cacheable, bufferable
480#endif
463 cmp r1, r10 @ if virt > end of RAM 481 cmp r1, r10 @ if virt > end of RAM
464 bichs r1, r1, #0x0c @ clear cacheable, bufferable 482 bichs r1, r1, #0x0c @ clear cacheable, bufferable
465 str r1, [r0], #4 @ 1:1 mapping 483 str r1, [r0], #4 @ 1:1 mapping
@@ -484,6 +502,12 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
484 mov pc, lr 502 mov pc, lr
485ENDPROC(__setup_mmu) 503ENDPROC(__setup_mmu)
486 504
505__arm926ejs_mmu_cache_on:
506#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
507 mov r0, #4 @ put dcache in WT mode
508 mcr p15, 7, r0, c15, c0, 0
509#endif
510
487__armv4_mmu_cache_on: 511__armv4_mmu_cache_on:
488 mov r12, lr 512 mov r12, lr
489#ifdef CONFIG_MMU 513#ifdef CONFIG_MMU
@@ -665,6 +689,12 @@ proc_types:
665 W(b) __armv4_mpu_cache_off 689 W(b) __armv4_mpu_cache_off
666 W(b) __armv4_mpu_cache_flush 690 W(b) __armv4_mpu_cache_flush
667 691
692 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
693 .word 0xff0ffff0
694 b __arm926ejs_mmu_cache_on
695 b __armv4_mmu_cache_off
696 b __armv5tej_mmu_cache_flush
697
668 .word 0x00007000 @ ARM7 IDs 698 .word 0x00007000 @ ARM7 IDs
669 .word 0x0000f000 699 .word 0x0000f000
670 mov pc, lr 700 mov pc, lr
@@ -747,12 +777,6 @@ proc_types:
747 W(b) __armv4_mmu_cache_off 777 W(b) __armv4_mmu_cache_off
748 W(b) __armv6_mmu_cache_flush 778 W(b) __armv6_mmu_cache_flush
749 779
750 .word 0x560f5810 @ Marvell PJ4 ARMv6
751 .word 0xff0ffff0
752 W(b) __armv4_mmu_cache_on
753 W(b) __armv4_mmu_cache_off
754 W(b) __armv6_mmu_cache_flush
755
756 .word 0x000f0000 @ new CPU Id 780 .word 0x000f0000 @ new CPU Id
757 .word 0x000f0000 781 .word 0x000f0000
758 W(b) __armv7_mmu_cache_on 782 W(b) __armv7_mmu_cache_on
@@ -1078,5 +1102,5 @@ reloc_code_end:
1078 1102
1079 .align 1103 .align
1080 .section ".stack", "aw", %nobits 1104 .section ".stack", "aw", %nobits
1081user_stack: .space 4096 1105.L_user_stack: .space 4096
1082user_stack_end: 1106.L_user_stack_end:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 2df38263124c..832d37236c59 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -26,8 +26,6 @@ unsigned int __machine_arch_type;
26#include <linux/linkage.h> 26#include <linux/linkage.h>
27#include <asm/string.h> 27#include <asm/string.h>
28 28
29#include <asm/unaligned.h>
30
31 29
32static void putstr(const char *ptr); 30static void putstr(const char *ptr);
33extern void error(char *x); 31extern void error(char *x);
@@ -139,13 +137,12 @@ void *memcpy(void *__dest, __const void *__src, size_t __n)
139} 137}
140 138
141/* 139/*
142 * gzip delarations 140 * gzip declarations
143 */ 141 */
144extern char input_data[]; 142extern char input_data[];
145extern char input_data_end[]; 143extern char input_data_end[];
146 144
147unsigned char *output_data; 145unsigned char *output_data;
148unsigned long output_ptr;
149 146
150unsigned long free_mem_ptr; 147unsigned long free_mem_ptr;
151unsigned long free_mem_end_ptr; 148unsigned long free_mem_end_ptr;
@@ -170,15 +167,15 @@ asmlinkage void __div0(void)
170 error("Attempting division by 0!"); 167 error("Attempting division by 0!");
171} 168}
172 169
173extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); 170extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
174 171
175 172
176unsigned long 173void
177decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, 174decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
178 unsigned long free_mem_ptr_end_p, 175 unsigned long free_mem_ptr_end_p,
179 int arch_id) 176 int arch_id)
180{ 177{
181 unsigned char *tmp; 178 int ret;
182 179
183 output_data = (unsigned char *)output_start; 180 output_data = (unsigned char *)output_start;
184 free_mem_ptr = free_mem_ptr_p; 181 free_mem_ptr = free_mem_ptr_p;
@@ -187,12 +184,11 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
187 184
188 arch_decomp_setup(); 185 arch_decomp_setup();
189 186
190 tmp = (unsigned char *) (((unsigned long)input_data_end) - 4);
191 output_ptr = get_unaligned_le32(tmp);
192
193 putstr("Uncompressing Linux..."); 187 putstr("Uncompressing Linux...");
194 do_decompress(input_data, input_data_end - input_data, 188 ret = do_decompress(input_data, input_data_end - input_data,
195 output_data, error); 189 output_data, error);
196 putstr(" done, booting the kernel.\n"); 190 if (ret)
197 return output_ptr; 191 error("decompressor returned an error");
192 else
193 putstr(" done, booting the kernel.\n");
198} 194}
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f70ec7dadebb..4ddd0a6ac7ff 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -49,7 +49,7 @@ struct gic_chip_data {
49 * Default make them NULL. 49 * Default make them NULL.
50 */ 50 */
51struct irq_chip gic_arch_extn = { 51struct irq_chip gic_arch_extn = {
52 .irq_ack = NULL, 52 .irq_eoi = NULL,
53 .irq_mask = NULL, 53 .irq_mask = NULL,
54 .irq_unmask = NULL, 54 .irq_unmask = NULL,
55 .irq_retrigger = NULL, 55 .irq_retrigger = NULL,
@@ -84,21 +84,12 @@ static inline unsigned int gic_irq(struct irq_data *d)
84/* 84/*
85 * Routines to acknowledge, disable and enable interrupts 85 * Routines to acknowledge, disable and enable interrupts
86 */ 86 */
87static void gic_ack_irq(struct irq_data *d)
88{
89 spin_lock(&irq_controller_lock);
90 if (gic_arch_extn.irq_ack)
91 gic_arch_extn.irq_ack(d);
92 writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
93 spin_unlock(&irq_controller_lock);
94}
95
96static void gic_mask_irq(struct irq_data *d) 87static void gic_mask_irq(struct irq_data *d)
97{ 88{
98 u32 mask = 1 << (d->irq % 32); 89 u32 mask = 1 << (d->irq % 32);
99 90
100 spin_lock(&irq_controller_lock); 91 spin_lock(&irq_controller_lock);
101 writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); 92 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
102 if (gic_arch_extn.irq_mask) 93 if (gic_arch_extn.irq_mask)
103 gic_arch_extn.irq_mask(d); 94 gic_arch_extn.irq_mask(d);
104 spin_unlock(&irq_controller_lock); 95 spin_unlock(&irq_controller_lock);
@@ -111,10 +102,21 @@ static void gic_unmask_irq(struct irq_data *d)
111 spin_lock(&irq_controller_lock); 102 spin_lock(&irq_controller_lock);
112 if (gic_arch_extn.irq_unmask) 103 if (gic_arch_extn.irq_unmask)
113 gic_arch_extn.irq_unmask(d); 104 gic_arch_extn.irq_unmask(d);
114 writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); 105 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
115 spin_unlock(&irq_controller_lock); 106 spin_unlock(&irq_controller_lock);
116} 107}
117 108
109static void gic_eoi_irq(struct irq_data *d)
110{
111 if (gic_arch_extn.irq_eoi) {
112 spin_lock(&irq_controller_lock);
113 gic_arch_extn.irq_eoi(d);
114 spin_unlock(&irq_controller_lock);
115 }
116
117 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
118}
119
118static int gic_set_type(struct irq_data *d, unsigned int type) 120static int gic_set_type(struct irq_data *d, unsigned int type)
119{ 121{
120 void __iomem *base = gic_dist_base(d); 122 void __iomem *base = gic_dist_base(d);
@@ -138,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
138 if (gic_arch_extn.irq_set_type) 140 if (gic_arch_extn.irq_set_type)
139 gic_arch_extn.irq_set_type(d, type); 141 gic_arch_extn.irq_set_type(d, type);
140 142
141 val = readl(base + GIC_DIST_CONFIG + confoff); 143 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
142 if (type == IRQ_TYPE_LEVEL_HIGH) 144 if (type == IRQ_TYPE_LEVEL_HIGH)
143 val &= ~confmask; 145 val &= ~confmask;
144 else if (type == IRQ_TYPE_EDGE_RISING) 146 else if (type == IRQ_TYPE_EDGE_RISING)
@@ -148,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
148 * As recommended by the spec, disable the interrupt before changing 150 * As recommended by the spec, disable the interrupt before changing
149 * the configuration 151 * the configuration
150 */ 152 */
151 if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { 153 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
152 writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); 154 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
153 enabled = true; 155 enabled = true;
154 } 156 }
155 157
156 writel(val, base + GIC_DIST_CONFIG + confoff); 158 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
157 159
158 if (enabled) 160 if (enabled)
159 writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); 161 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
160 162
161 spin_unlock(&irq_controller_lock); 163 spin_unlock(&irq_controller_lock);
162 164
@@ -188,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
188 190
189 spin_lock(&irq_controller_lock); 191 spin_lock(&irq_controller_lock);
190 d->node = cpu; 192 d->node = cpu;
191 val = readl(reg) & ~mask; 193 val = readl_relaxed(reg) & ~mask;
192 writel(val | bit, reg); 194 writel_relaxed(val | bit, reg);
193 spin_unlock(&irq_controller_lock); 195 spin_unlock(&irq_controller_lock);
194 196
195 return 0; 197 return 0;
@@ -218,11 +220,10 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
218 unsigned int cascade_irq, gic_irq; 220 unsigned int cascade_irq, gic_irq;
219 unsigned long status; 221 unsigned long status;
220 222
221 /* primary controller ack'ing */ 223 chained_irq_enter(chip, desc);
222 chip->irq_ack(&desc->irq_data);
223 224
224 spin_lock(&irq_controller_lock); 225 spin_lock(&irq_controller_lock);
225 status = readl(chip_data->cpu_base + GIC_CPU_INTACK); 226 status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
226 spin_unlock(&irq_controller_lock); 227 spin_unlock(&irq_controller_lock);
227 228
228 gic_irq = (status & 0x3ff); 229 gic_irq = (status & 0x3ff);
@@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
236 generic_handle_irq(cascade_irq); 237 generic_handle_irq(cascade_irq);
237 238
238 out: 239 out:
239 /* primary controller unmasking */ 240 chained_irq_exit(chip, desc);
240 chip->irq_unmask(&desc->irq_data);
241} 241}
242 242
243static struct irq_chip gic_chip = { 243static struct irq_chip gic_chip = {
244 .name = "GIC", 244 .name = "GIC",
245 .irq_ack = gic_ack_irq,
246 .irq_mask = gic_mask_irq, 245 .irq_mask = gic_mask_irq,
247 .irq_unmask = gic_unmask_irq, 246 .irq_unmask = gic_unmask_irq,
247 .irq_eoi = gic_eoi_irq,
248 .irq_set_type = gic_set_type, 248 .irq_set_type = gic_set_type,
249 .irq_retrigger = gic_retrigger, 249 .irq_retrigger = gic_retrigger,
250#ifdef CONFIG_SMP 250#ifdef CONFIG_SMP
@@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
272 cpumask |= cpumask << 8; 272 cpumask |= cpumask << 8;
273 cpumask |= cpumask << 16; 273 cpumask |= cpumask << 16;
274 274
275 writel(0, base + GIC_DIST_CTRL); 275 writel_relaxed(0, base + GIC_DIST_CTRL);
276 276
277 /* 277 /*
278 * Find out how many interrupts are supported. 278 * Find out how many interrupts are supported.
279 * The GIC only supports up to 1020 interrupt sources. 279 * The GIC only supports up to 1020 interrupt sources.
280 */ 280 */
281 gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f; 281 gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
282 gic_irqs = (gic_irqs + 1) * 32; 282 gic_irqs = (gic_irqs + 1) * 32;
283 if (gic_irqs > 1020) 283 if (gic_irqs > 1020)
284 gic_irqs = 1020; 284 gic_irqs = 1020;
@@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
287 * Set all global interrupts to be level triggered, active low. 287 * Set all global interrupts to be level triggered, active low.
288 */ 288 */
289 for (i = 32; i < gic_irqs; i += 16) 289 for (i = 32; i < gic_irqs; i += 16)
290 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); 290 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
291 291
292 /* 292 /*
293 * Set all global interrupts to this CPU only. 293 * Set all global interrupts to this CPU only.
294 */ 294 */
295 for (i = 32; i < gic_irqs; i += 4) 295 for (i = 32; i < gic_irqs; i += 4)
296 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 296 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
297 297
298 /* 298 /*
299 * Set priority on all global interrupts. 299 * Set priority on all global interrupts.
300 */ 300 */
301 for (i = 32; i < gic_irqs; i += 4) 301 for (i = 32; i < gic_irqs; i += 4)
302 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); 302 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
303 303
304 /* 304 /*
305 * Disable all interrupts. Leave the PPI and SGIs alone 305 * Disable all interrupts. Leave the PPI and SGIs alone
306 * as these enables are banked registers. 306 * as these enables are banked registers.
307 */ 307 */
308 for (i = 32; i < gic_irqs; i += 32) 308 for (i = 32; i < gic_irqs; i += 32)
309 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); 309 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
310 310
311 /* 311 /*
312 * Limit number of interrupts registered to the platform maximum 312 * Limit number of interrupts registered to the platform maximum
@@ -319,12 +319,12 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
319 * Setup the Linux IRQ subsystem. 319 * Setup the Linux IRQ subsystem.
320 */ 320 */
321 for (i = irq_start; i < irq_limit; i++) { 321 for (i = irq_start; i < irq_limit; i++) {
322 irq_set_chip_and_handler(i, &gic_chip, handle_level_irq); 322 irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
323 irq_set_chip_data(i, gic); 323 irq_set_chip_data(i, gic);
324 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 324 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
325 } 325 }
326 326
327 writel(1, base + GIC_DIST_CTRL); 327 writel_relaxed(1, base + GIC_DIST_CTRL);
328} 328}
329 329
330static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) 330static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
@@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
337 * Deal with the banked PPI and SGI interrupts - disable all 337 * Deal with the banked PPI and SGI interrupts - disable all
338 * PPI interrupts, ensure all SGI interrupts are enabled. 338 * PPI interrupts, ensure all SGI interrupts are enabled.
339 */ 339 */
340 writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); 340 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
341 writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); 341 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
342 342
343 /* 343 /*
344 * Set priority on PPI and SGI interrupts 344 * Set priority on PPI and SGI interrupts
345 */ 345 */
346 for (i = 0; i < 32; i += 4) 346 for (i = 0; i < 32; i += 4)
347 writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); 347 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
348 348
349 writel(0xf0, base + GIC_CPU_PRIMASK); 349 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
350 writel(1, base + GIC_CPU_CTRL); 350 writel_relaxed(1, base + GIC_CPU_CTRL);
351} 351}
352 352
353void __init gic_init(unsigned int gic_nr, unsigned int irq_start, 353void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
@@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
391{ 391{
392 unsigned long map = *cpus_addr(*mask); 392 unsigned long map = *cpus_addr(*mask);
393 393
394 /*
395 * Ensure that stores to Normal memory are visible to the
396 * other CPUs before issuing the IPI.
397 */
398 dsb();
399
394 /* this always happens on GIC0 */ 400 /* this always happens on GIC0 */
395 writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); 401 writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
396} 402}
397#endif 403#endif
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index a12b33c0dc42..9c49a46a2b7a 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -185,14 +185,6 @@ static struct sa1111_dev_info sa1111_devices[] = {
185 }, 185 },
186}; 186};
187 187
188void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
189{
190 unsigned int sz = SZ_1M >> PAGE_SHIFT;
191
192 size[1] = size[0] - sz;
193 size[0] = sz;
194}
195
196/* 188/*
197 * SA1111 interrupt support. Since clearing an IRQ while there are 189 * SA1111 interrupt support. Since clearing an IRQ while there are
198 * active IRQs causes the interrupt output to pulse, the upper levels 190 * active IRQs causes the interrupt output to pulse, the upper levels
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 6ef3342153b9..41df47875122 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -18,53 +18,67 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21#include <linux/clk.h>
21#include <linux/clocksource.h> 22#include <linux/clocksource.h>
22#include <linux/clockchips.h> 23#include <linux/clockchips.h>
24#include <linux/err.h>
23#include <linux/interrupt.h> 25#include <linux/interrupt.h>
24#include <linux/irq.h> 26#include <linux/irq.h>
25#include <linux/io.h> 27#include <linux/io.h>
26 28
27#include <asm/hardware/arm_timer.h> 29#include <asm/hardware/arm_timer.h>
28 30
29/* 31static long __init sp804_get_clock_rate(const char *name)
30 * These timers are currently always setup to be clocked at 1MHz. 32{
31 */ 33 struct clk *clk;
32#define TIMER_FREQ_KHZ (1000) 34 long rate;
33#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ) 35 int err;
36
37 clk = clk_get_sys("sp804", name);
38 if (IS_ERR(clk)) {
39 pr_err("sp804: %s clock not found: %d\n", name,
40 (int)PTR_ERR(clk));
41 return PTR_ERR(clk);
42 }
34 43
35static void __iomem *clksrc_base; 44 err = clk_enable(clk);
45 if (err) {
46 pr_err("sp804: %s clock failed to enable: %d\n", name, err);
47 clk_put(clk);
48 return err;
49 }
36 50
37static cycle_t sp804_read(struct clocksource *cs) 51 rate = clk_get_rate(clk);
38{ 52 if (rate < 0) {
39 return ~readl(clksrc_base + TIMER_VALUE); 53 pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
40} 54 clk_disable(clk);
55 clk_put(clk);
56 }
41 57
42static struct clocksource clocksource_sp804 = { 58 return rate;
43 .name = "timer3", 59}
44 .rating = 200,
45 .read = sp804_read,
46 .mask = CLOCKSOURCE_MASK(32),
47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
48};
49 60
50void __init sp804_clocksource_init(void __iomem *base) 61void __init sp804_clocksource_init(void __iomem *base, const char *name)
51{ 62{
52 struct clocksource *cs = &clocksource_sp804; 63 long rate = sp804_get_clock_rate(name);
53 64
54 clksrc_base = base; 65 if (rate < 0)
66 return;
55 67
56 /* setup timer 0 as free-running clocksource */ 68 /* setup timer 0 as free-running clocksource */
57 writel(0, clksrc_base + TIMER_CTRL); 69 writel(0, base + TIMER_CTRL);
58 writel(0xffffffff, clksrc_base + TIMER_LOAD); 70 writel(0xffffffff, base + TIMER_LOAD);
59 writel(0xffffffff, clksrc_base + TIMER_VALUE); 71 writel(0xffffffff, base + TIMER_VALUE);
60 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, 72 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
61 clksrc_base + TIMER_CTRL); 73 base + TIMER_CTRL);
62 74
63 clocksource_register_khz(cs, TIMER_FREQ_KHZ); 75 clocksource_mmio_init(base + TIMER_VALUE, name,
76 rate, 200, 32, clocksource_mmio_readl_down);
64} 77}
65 78
66 79
67static void __iomem *clkevt_base; 80static void __iomem *clkevt_base;
81static unsigned long clkevt_reload;
68 82
69/* 83/*
70 * IRQ handler for the timer 84 * IRQ handler for the timer
@@ -90,7 +104,7 @@ static void sp804_set_mode(enum clock_event_mode mode,
90 104
91 switch (mode) { 105 switch (mode) {
92 case CLOCK_EVT_MODE_PERIODIC: 106 case CLOCK_EVT_MODE_PERIODIC:
93 writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); 107 writel(clkevt_reload, clkevt_base + TIMER_LOAD);
94 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; 108 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
95 break; 109 break;
96 110
@@ -120,7 +134,6 @@ static int sp804_set_next_event(unsigned long next,
120} 134}
121 135
122static struct clock_event_device sp804_clockevent = { 136static struct clock_event_device sp804_clockevent = {
123 .name = "timer0",
124 .shift = 32, 137 .shift = 32,
125 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 138 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
126 .set_mode = sp804_set_mode, 139 .set_mode = sp804_set_mode,
@@ -136,17 +149,24 @@ static struct irqaction sp804_timer_irq = {
136 .dev_id = &sp804_clockevent, 149 .dev_id = &sp804_clockevent,
137}; 150};
138 151
139void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq) 152void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
153 const char *name)
140{ 154{
141 struct clock_event_device *evt = &sp804_clockevent; 155 struct clock_event_device *evt = &sp804_clockevent;
156 long rate = sp804_get_clock_rate(name);
157
158 if (rate < 0)
159 return;
142 160
143 clkevt_base = base; 161 clkevt_base = base;
162 clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
144 163
145 evt->irq = timer_irq; 164 evt->name = name;
146 evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); 165 evt->irq = irq;
166 evt->mult = div_sc(rate, NSEC_PER_SEC, evt->shift);
147 evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); 167 evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
148 evt->min_delta_ns = clockevent_delta2ns(0xf, evt); 168 evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
149 169
150 setup_irq(timer_irq, &sp804_timer_irq); 170 setup_irq(irq, &sp804_timer_irq);
151 clockevents_register_device(evt); 171 clockevents_register_device(evt);
152} 172}
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 54bf5eec8016..40db34cf2771 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
8# CONFIG_BLK_DEV_BSG is not set 8# CONFIG_BLK_DEV_BSG is not set
9CONFIG_ARCH_DOVE=y 9CONFIG_ARCH_DOVE=y
10CONFIG_MACH_DOVE_DB=y 10CONFIG_MACH_DOVE_DB=y
11CONFIG_CPU_V6=y
12CONFIG_CPU_32v6K=y
13CONFIG_NO_HZ=y 11CONFIG_NO_HZ=y
14CONFIG_HIGH_RES_TIMERS=y 12CONFIG_HIGH_RES_TIMERS=y
15CONFIG_AEABI=y 13CONFIG_AEABI=y
@@ -44,7 +42,6 @@ CONFIG_MTD_UBI=y
44CONFIG_BLK_DEV_LOOP=y 42CONFIG_BLK_DEV_LOOP=y
45CONFIG_BLK_DEV_RAM=y 43CONFIG_BLK_DEV_RAM=y
46CONFIG_BLK_DEV_RAM_COUNT=1 44CONFIG_BLK_DEV_RAM_COUNT=1
47# CONFIG_MISC_DEVICES is not set
48# CONFIG_SCSI_PROC_FS is not set 45# CONFIG_SCSI_PROC_FS is not set
49CONFIG_BLK_DEV_SD=y 46CONFIG_BLK_DEV_SD=y
50# CONFIG_SCSI_LOWLEVEL is not set 47# CONFIG_SCSI_LOWLEVEL is not set
@@ -59,12 +56,12 @@ CONFIG_INPUT_EVDEV=y
59# CONFIG_KEYBOARD_ATKBD is not set 56# CONFIG_KEYBOARD_ATKBD is not set
60# CONFIG_MOUSE_PS2 is not set 57# CONFIG_MOUSE_PS2 is not set
61# CONFIG_SERIO is not set 58# CONFIG_SERIO is not set
59CONFIG_LEGACY_PTY_COUNT=16
62# CONFIG_DEVKMEM is not set 60# CONFIG_DEVKMEM is not set
63CONFIG_SERIAL_8250=y 61CONFIG_SERIAL_8250=y
64CONFIG_SERIAL_8250_CONSOLE=y 62CONFIG_SERIAL_8250_CONSOLE=y
65# CONFIG_SERIAL_8250_PCI is not set 63# CONFIG_SERIAL_8250_PCI is not set
66CONFIG_SERIAL_8250_RUNTIME_UARTS=2 64CONFIG_SERIAL_8250_RUNTIME_UARTS=2
67CONFIG_LEGACY_PTY_COUNT=16
68# CONFIG_HW_RANDOM is not set 65# CONFIG_HW_RANDOM is not set
69CONFIG_I2C=y 66CONFIG_I2C=y
70CONFIG_I2C_CHARDEV=y 67CONFIG_I2C_CHARDEV=y
@@ -72,12 +69,10 @@ CONFIG_I2C_MV64XXX=y
72CONFIG_SPI=y 69CONFIG_SPI=y
73CONFIG_SPI_ORION=y 70CONFIG_SPI_ORION=y
74# CONFIG_HWMON is not set 71# CONFIG_HWMON is not set
75# CONFIG_VGA_CONSOLE is not set
76CONFIG_USB=y 72CONFIG_USB=y
77CONFIG_USB_DEVICEFS=y 73CONFIG_USB_DEVICEFS=y
78CONFIG_USB_EHCI_HCD=y 74CONFIG_USB_EHCI_HCD=y
79CONFIG_USB_EHCI_ROOT_HUB_TT=y 75CONFIG_USB_EHCI_ROOT_HUB_TT=y
80CONFIG_USB_EHCI_TT_NEWSCHED=y
81CONFIG_USB_STORAGE=y 76CONFIG_USB_STORAGE=y
82CONFIG_RTC_CLASS=y 77CONFIG_RTC_CLASS=y
83CONFIG_RTC_DRV_MV=y 78CONFIG_RTC_DRV_MV=y
@@ -86,7 +81,6 @@ CONFIG_MV_XOR=y
86CONFIG_EXT2_FS=y 81CONFIG_EXT2_FS=y
87CONFIG_EXT3_FS=y 82CONFIG_EXT3_FS=y
88# CONFIG_EXT3_FS_XATTR is not set 83# CONFIG_EXT3_FS_XATTR is not set
89CONFIG_INOTIFY=y
90CONFIG_ISO9660_FS=y 84CONFIG_ISO9660_FS=y
91CONFIG_JOLIET=y 85CONFIG_JOLIET=y
92CONFIG_UDF_FS=m 86CONFIG_UDF_FS=m
@@ -110,23 +104,19 @@ CONFIG_DEBUG_KERNEL=y
110CONFIG_TIMER_STATS=y 104CONFIG_TIMER_STATS=y
111# CONFIG_DEBUG_BUGVERBOSE is not set 105# CONFIG_DEBUG_BUGVERBOSE is not set
112CONFIG_DEBUG_INFO=y 106CONFIG_DEBUG_INFO=y
113# CONFIG_RCU_CPU_STALL_DETECTOR is not set
114CONFIG_SYSCTL_SYSCALL_CHECK=y 107CONFIG_SYSCTL_SYSCALL_CHECK=y
115CONFIG_DEBUG_USER=y 108CONFIG_DEBUG_USER=y
116CONFIG_DEBUG_ERRORS=y 109CONFIG_DEBUG_ERRORS=y
117CONFIG_CRYPTO_NULL=y 110CONFIG_CRYPTO_NULL=y
118CONFIG_CRYPTO_CBC=y
119CONFIG_CRYPTO_ECB=m 111CONFIG_CRYPTO_ECB=m
120CONFIG_CRYPTO_PCBC=m 112CONFIG_CRYPTO_PCBC=m
121CONFIG_CRYPTO_HMAC=y 113CONFIG_CRYPTO_HMAC=y
122CONFIG_CRYPTO_MD4=y 114CONFIG_CRYPTO_MD4=y
123CONFIG_CRYPTO_MD5=y
124CONFIG_CRYPTO_SHA1=y 115CONFIG_CRYPTO_SHA1=y
125CONFIG_CRYPTO_SHA256=y 116CONFIG_CRYPTO_SHA256=y
126CONFIG_CRYPTO_SHA512=y 117CONFIG_CRYPTO_SHA512=y
127CONFIG_CRYPTO_AES=y 118CONFIG_CRYPTO_AES=y
128CONFIG_CRYPTO_BLOWFISH=y 119CONFIG_CRYPTO_BLOWFISH=y
129CONFIG_CRYPTO_DES=y
130CONFIG_CRYPTO_TEA=y 120CONFIG_CRYPTO_TEA=y
131CONFIG_CRYPTO_TWOFISH=y 121CONFIG_CRYPTO_TWOFISH=y
132CONFIG_CRYPTO_DEFLATE=y 122CONFIG_CRYPTO_DEFLATE=y
diff --git a/arch/arm/configs/mx1_defconfig b/arch/arm/configs/mx1_defconfig
index b39b5ced8a10..c9436d0bf593 100644
--- a/arch/arm/configs/mx1_defconfig
+++ b/arch/arm/configs/mx1_defconfig
@@ -15,6 +15,7 @@ CONFIG_ARCH_MXC=y
15CONFIG_ARCH_MX1=y 15CONFIG_ARCH_MX1=y
16CONFIG_ARCH_MX1ADS=y 16CONFIG_ARCH_MX1ADS=y
17CONFIG_MACH_SCB9328=y 17CONFIG_MACH_SCB9328=y
18CONFIG_MACH_APF9328=y
18CONFIG_MXC_IRQ_PRIOR=y 19CONFIG_MXC_IRQ_PRIOR=y
19CONFIG_NO_HZ=y 20CONFIG_NO_HZ=y
20CONFIG_HIGH_RES_TIMERS=y 21CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index e3c903281f70..0ace16cba9b5 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -13,7 +13,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
13# CONFIG_LBDAF is not set 13# CONFIG_LBDAF is not set
14# CONFIG_BLK_DEV_BSG is not set 14# CONFIG_BLK_DEV_BSG is not set
15CONFIG_ARCH_MXC=y 15CONFIG_ARCH_MXC=y
16CONFIG_ARCH_MX5=y 16CONFIG_ARCH_MX51=y
17CONFIG_MACH_MX51_BABBAGE=y 17CONFIG_MACH_MX51_BABBAGE=y
18CONFIG_MACH_MX51_3DS=y 18CONFIG_MACH_MX51_3DS=y
19CONFIG_MACH_EUKREA_CPUIMX51=y 19CONFIG_MACH_EUKREA_CPUIMX51=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
new file mode 100644
index 000000000000..2bf224310fb4
--- /dev/null
+++ b/arch/arm/configs/mxs_defconfig
@@ -0,0 +1,129 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_TASKSTATS=y
4CONFIG_TASK_DELAY_ACCT=y
5CONFIG_TASK_XACCT=y
6CONFIG_TASK_IO_ACCOUNTING=y
7CONFIG_IKCONFIG=y
8CONFIG_IKCONFIG_PROC=y
9# CONFIG_UTS_NS is not set
10# CONFIG_IPC_NS is not set
11# CONFIG_USER_NS is not set
12# CONFIG_PID_NS is not set
13# CONFIG_NET_NS is not set
14CONFIG_PERF_EVENTS=y
15# CONFIG_COMPAT_BRK is not set
16CONFIG_MODULES=y
17CONFIG_MODULE_FORCE_LOAD=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_MODVERSIONS=y
21CONFIG_BLK_DEV_INTEGRITY=y
22# CONFIG_IOSCHED_DEADLINE is not set
23# CONFIG_IOSCHED_CFQ is not set
24CONFIG_ARCH_MXS=y
25CONFIG_MACH_STMP378X_DEVB=y
26CONFIG_MACH_TX28=y
27# CONFIG_ARM_THUMB is not set
28CONFIG_NO_HZ=y
29CONFIG_HIGH_RES_TIMERS=y
30CONFIG_PREEMPT_VOLUNTARY=y
31CONFIG_AEABI=y
32CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
33CONFIG_AUTO_ZRELADDR=y
34CONFIG_FPE_NWFPE=y
35CONFIG_NET=y
36CONFIG_PACKET=y
37CONFIG_UNIX=y
38CONFIG_INET=y
39CONFIG_IP_PNP=y
40CONFIG_IP_PNP_DHCP=y
41CONFIG_SYN_COOKIES=y
42# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET_XFRM_MODE_BEET is not set
45# CONFIG_INET_LRO is not set
46# CONFIG_INET_DIAG is not set
47# CONFIG_IPV6 is not set
48CONFIG_CAN=m
49CONFIG_CAN_RAW=m
50CONFIG_CAN_BCM=m
51CONFIG_CAN_DEV=m
52CONFIG_CAN_FLEXCAN=m
53# CONFIG_WIRELESS is not set
54CONFIG_DEVTMPFS=y
55# CONFIG_FIRMWARE_IN_KERNEL is not set
56# CONFIG_BLK_DEV is not set
57CONFIG_NETDEVICES=y
58CONFIG_NET_ETHERNET=y
59CONFIG_ENC28J60=y
60# CONFIG_NETDEV_1000 is not set
61# CONFIG_NETDEV_10000 is not set
62# CONFIG_WLAN is not set
63# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
64CONFIG_INPUT_EVDEV=m
65# CONFIG_INPUT_KEYBOARD is not set
66# CONFIG_INPUT_MOUSE is not set
67CONFIG_INPUT_TOUCHSCREEN=y
68CONFIG_TOUCHSCREEN_TSC2007=m
69# CONFIG_SERIO is not set
70CONFIG_VT_HW_CONSOLE_BINDING=y
71CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
72# CONFIG_LEGACY_PTYS is not set
73# CONFIG_DEVKMEM is not set
74CONFIG_SERIAL_AMBA_PL011=y
75CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
76# CONFIG_HW_RANDOM is not set
77CONFIG_I2C=m
78# CONFIG_I2C_COMPAT is not set
79CONFIG_I2C_CHARDEV=m
80CONFIG_I2C_MXS=m
81CONFIG_SPI=y
82CONFIG_SPI_GPIO=m
83CONFIG_DEBUG_GPIO=y
84CONFIG_GPIO_SYSFS=y
85# CONFIG_HWMON is not set
86# CONFIG_MFD_SUPPORT is not set
87CONFIG_DISPLAY_SUPPORT=m
88# CONFIG_HID_SUPPORT is not set
89# CONFIG_USB_SUPPORT is not set
90CONFIG_MMC=y
91CONFIG_MMC_MXS=y
92CONFIG_RTC_CLASS=m
93CONFIG_RTC_DRV_DS1307=m
94CONFIG_DMADEVICES=y
95CONFIG_MXS_DMA=y
96CONFIG_EXT3_FS=y
97# CONFIG_DNOTIFY is not set
98CONFIG_FSCACHE=m
99CONFIG_FSCACHE_STATS=y
100CONFIG_CACHEFILES=m
101CONFIG_TMPFS=y
102CONFIG_TMPFS_POSIX_ACL=y
103# CONFIG_MISC_FILESYSTEMS is not set
104CONFIG_NFS_FS=y
105CONFIG_NFS_V3=y
106CONFIG_NFS_V3_ACL=y
107CONFIG_NFS_V4=y
108CONFIG_ROOT_NFS=y
109CONFIG_PRINTK_TIME=y
110CONFIG_FRAME_WARN=2048
111CONFIG_MAGIC_SYSRQ=y
112CONFIG_UNUSED_SYMBOLS=y
113CONFIG_DEBUG_KERNEL=y
114CONFIG_LOCKUP_DETECTOR=y
115CONFIG_DETECT_HUNG_TASK=y
116CONFIG_TIMER_STATS=y
117CONFIG_PROVE_LOCKING=y
118CONFIG_DEBUG_SPINLOCK_SLEEP=y
119CONFIG_DEBUG_INFO=y
120CONFIG_SYSCTL_SYSCALL_CHECK=y
121CONFIG_BLK_DEV_IO_TRACE=y
122CONFIG_STRICT_DEVMEM=y
123CONFIG_DEBUG_USER=y
124CONFIG_CRYPTO=y
125CONFIG_CRYPTO_CRC32C=m
126# CONFIG_CRYPTO_ANSI_CPRNG is not set
127# CONFIG_CRYPTO_HW is not set
128CONFIG_CRC_ITU_T=m
129CONFIG_CRC7=m
diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig
deleted file mode 100644
index 1f528a002983..000000000000
--- a/arch/arm/configs/ns9xxx_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
1CONFIG_IKCONFIG=y
2CONFIG_IKCONFIG_PROC=y
3CONFIG_BLK_DEV_INITRD=y
4CONFIG_MODULES=y
5CONFIG_MODULE_UNLOAD=y
6# CONFIG_IOSCHED_DEADLINE is not set
7# CONFIG_IOSCHED_CFQ is not set
8CONFIG_ARCH_NS9XXX=y
9CONFIG_MACH_CC9P9360DEV=y
10CONFIG_MACH_CC9P9360JS=y
11CONFIG_NO_HZ=y
12CONFIG_HIGH_RES_TIMERS=y
13CONFIG_FPE_NWFPE=y
14CONFIG_NET=y
15CONFIG_PACKET=m
16CONFIG_INET=y
17CONFIG_IP_PNP=y
18CONFIG_SYN_COOKIES=y
19CONFIG_MTD=m
20CONFIG_MTD_CONCAT=m
21CONFIG_MTD_CHAR=m
22CONFIG_MTD_BLOCK=m
23CONFIG_MTD_CFI=m
24CONFIG_MTD_JEDECPROBE=m
25CONFIG_MTD_CFI_AMDSTD=m
26CONFIG_MTD_PHYSMAP=m
27CONFIG_BLK_DEV_LOOP=m
28CONFIG_NETDEVICES=y
29CONFIG_NET_ETHERNET=y
30# CONFIG_SERIO_SERPORT is not set
31CONFIG_SERIAL_8250=y
32CONFIG_SERIAL_8250_CONSOLE=y
33# CONFIG_LEGACY_PTYS is not set
34# CONFIG_HW_RANDOM is not set
35CONFIG_I2C=m
36CONFIG_I2C_GPIO=m
37# CONFIG_HWMON is not set
38# CONFIG_VGA_CONSOLE is not set
39# CONFIG_USB_SUPPORT is not set
40CONFIG_NEW_LEDS=y
41CONFIG_LEDS_CLASS=m
42CONFIG_LEDS_GPIO=m
43CONFIG_LEDS_TRIGGERS=y
44CONFIG_LEDS_TRIGGER_TIMER=m
45CONFIG_LEDS_TRIGGER_HEARTBEAT=m
46CONFIG_RTC_CLASS=m
47CONFIG_EXT2_FS=m
48CONFIG_TMPFS=y
49CONFIG_JFFS2_FS=m
50CONFIG_NFS_FS=y
51CONFIG_ROOT_NFS=y
52# CONFIG_ENABLE_MUST_CHECK is not set
53CONFIG_DEBUG_KERNEL=y
54CONFIG_DEBUG_INFO=y
55CONFIG_DEBUG_USER=y
56CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index 5ca7a61f7c01..abe61bf379d2 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y
38CONFIG_MTD_CFI=y 38CONFIG_MTD_CFI=y
39CONFIG_MTD_CFI_INTELEXT=y 39CONFIG_MTD_CFI_INTELEXT=y
40CONFIG_MTD_CFI_AMDSTD=y 40CONFIG_MTD_CFI_AMDSTD=y
41CONFIG_MTD_ARM_INTEGRATOR=y 41CONFIG_MTD_PHYSMAP=y
42CONFIG_ARM_CHARLCD=y 42CONFIG_ARM_CHARLCD=y
43CONFIG_NETDEVICES=y 43CONFIG_NETDEVICES=y
44CONFIG_SMSC_PHY=y 44CONFIG_SMSC_PHY=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index fcaa60328051..7079cbe898a8 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y
37CONFIG_MTD_CFI=y 37CONFIG_MTD_CFI=y
38CONFIG_MTD_CFI_INTELEXT=y 38CONFIG_MTD_CFI_INTELEXT=y
39CONFIG_MTD_CFI_AMDSTD=y 39CONFIG_MTD_CFI_AMDSTD=y
40CONFIG_MTD_ARM_INTEGRATOR=y 40CONFIG_MTD_PHYSMAP=y
41CONFIG_ARM_CHARLCD=y 41CONFIG_ARM_CHARLCD=y
42CONFIG_NETDEVICES=y 42CONFIG_NETDEVICES=y
43CONFIG_SMSC_PHY=y 43CONFIG_SMSC_PHY=y
diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig
deleted file mode 100644
index 824e44418b18..000000000000
--- a/arch/arm/configs/spear310_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y
9CONFIG_PLAT_SPEAR=y
10CONFIG_MACH_SPEAR310=y
11CONFIG_BINFMT_MISC=y
12CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
13CONFIG_BLK_DEV_RAM=y
14CONFIG_BLK_DEV_RAM_SIZE=16384
15CONFIG_INPUT_FF_MEMLESS=y
16# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
17# CONFIG_INPUT_KEYBOARD is not set
18# CONFIG_INPUT_MOUSE is not set
19CONFIG_SERIAL_AMBA_PL011=y
20CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
21# CONFIG_LEGACY_PTYS is not set
22# CONFIG_HW_RANDOM is not set
23CONFIG_RAW_DRIVER=y
24CONFIG_MAX_RAW_DEVS=8192
25CONFIG_GPIO_SYSFS=y
26CONFIG_GPIO_PL061=y
27# CONFIG_HWMON is not set
28# CONFIG_VGA_CONSOLE is not set
29# CONFIG_HID_SUPPORT is not set
30# CONFIG_USB_SUPPORT is not set
31CONFIG_EXT2_FS=y
32CONFIG_EXT2_FS_XATTR=y
33CONFIG_EXT2_FS_SECURITY=y
34CONFIG_EXT3_FS=y
35CONFIG_EXT3_FS_SECURITY=y
36CONFIG_AUTOFS4_FS=m
37CONFIG_MSDOS_FS=m
38CONFIG_VFAT_FS=m
39CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
40CONFIG_TMPFS=y
41CONFIG_PARTITION_ADVANCED=y
42CONFIG_NLS=y
43CONFIG_NLS_DEFAULT="utf8"
44CONFIG_NLS_CODEPAGE_437=y
45CONFIG_NLS_ASCII=m
46CONFIG_MAGIC_SYSRQ=y
47CONFIG_DEBUG_FS=y
48CONFIG_DEBUG_KERNEL=y
49CONFIG_DEBUG_SPINLOCK=y
50CONFIG_DEBUG_SPINLOCK_SLEEP=y
51CONFIG_DEBUG_INFO=y
52# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig
deleted file mode 100644
index 842f7f3c512a..000000000000
--- a/arch/arm/configs/spear320_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_EXTRA_PASS=y
6CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y
9CONFIG_PLAT_SPEAR=y
10CONFIG_MACH_SPEAR320=y
11CONFIG_BINFMT_MISC=y
12CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
13CONFIG_BLK_DEV_RAM=y
14CONFIG_BLK_DEV_RAM_SIZE=16384
15CONFIG_INPUT_FF_MEMLESS=y
16# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
17# CONFIG_INPUT_KEYBOARD is not set
18# CONFIG_INPUT_MOUSE is not set
19CONFIG_SERIAL_AMBA_PL011=y
20CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
21# CONFIG_LEGACY_PTYS is not set
22# CONFIG_HW_RANDOM is not set
23CONFIG_RAW_DRIVER=y
24CONFIG_MAX_RAW_DEVS=8192
25CONFIG_GPIO_SYSFS=y
26CONFIG_GPIO_PL061=y
27# CONFIG_HWMON is not set
28# CONFIG_VGA_CONSOLE is not set
29# CONFIG_HID_SUPPORT is not set
30# CONFIG_USB_SUPPORT is not set
31CONFIG_EXT2_FS=y
32CONFIG_EXT2_FS_XATTR=y
33CONFIG_EXT2_FS_SECURITY=y
34CONFIG_EXT3_FS=y
35CONFIG_EXT3_FS_SECURITY=y
36CONFIG_AUTOFS4_FS=m
37CONFIG_MSDOS_FS=m
38CONFIG_VFAT_FS=m
39CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
40CONFIG_TMPFS=y
41CONFIG_PARTITION_ADVANCED=y
42CONFIG_NLS=y
43CONFIG_NLS_DEFAULT="utf8"
44CONFIG_NLS_CODEPAGE_437=y
45CONFIG_NLS_ASCII=m
46CONFIG_MAGIC_SYSRQ=y
47CONFIG_DEBUG_FS=y
48CONFIG_DEBUG_KERNEL=y
49CONFIG_DEBUG_SPINLOCK=y
50CONFIG_DEBUG_SPINLOCK_SLEEP=y
51CONFIG_DEBUG_INFO=y
52# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear3xx_defconfig
index cf29f3e56922..fea7e1f026a3 100644
--- a/arch/arm/configs/spear300_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -7,6 +7,9 @@ CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y 7CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 8CONFIG_MODVERSIONS=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_BOARD_SPEAR300_EVB=y
11CONFIG_BOARD_SPEAR310_EVB=y
12CONFIG_BOARD_SPEAR320_EVB=y
10CONFIG_BINFMT_MISC=y 13CONFIG_BINFMT_MISC=y
11CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 14CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
12CONFIG_BLK_DEV_RAM=y 15CONFIG_BLK_DEV_RAM=y
@@ -24,7 +27,6 @@ CONFIG_MAX_RAW_DEVS=8192
24CONFIG_GPIO_SYSFS=y 27CONFIG_GPIO_SYSFS=y
25CONFIG_GPIO_PL061=y 28CONFIG_GPIO_PL061=y
26# CONFIG_HWMON is not set 29# CONFIG_HWMON is not set
27# CONFIG_VGA_CONSOLE is not set
28# CONFIG_HID_SUPPORT is not set 30# CONFIG_HID_SUPPORT is not set
29# CONFIG_USB_SUPPORT is not set 31# CONFIG_USB_SUPPORT is not set
30CONFIG_EXT2_FS=y 32CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear6xx_defconfig
index 6777c11f63e7..cef2e836afd2 100644
--- a/arch/arm/configs/spear600_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y
8CONFIG_MODVERSIONS=y 8CONFIG_MODVERSIONS=y
9CONFIG_PLAT_SPEAR=y 9CONFIG_PLAT_SPEAR=y
10CONFIG_ARCH_SPEAR6XX=y 10CONFIG_ARCH_SPEAR6XX=y
11CONFIG_BOARD_SPEAR600_EVB=y
11CONFIG_BINFMT_MISC=y 12CONFIG_BINFMT_MISC=y
12CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 13CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
13CONFIG_BLK_DEV_RAM=y 14CONFIG_BLK_DEV_RAM=y
@@ -22,7 +23,6 @@ CONFIG_MAX_RAW_DEVS=8192
22CONFIG_GPIO_SYSFS=y 23CONFIG_GPIO_SYSFS=y
23CONFIG_GPIO_PL061=y 24CONFIG_GPIO_PL061=y
24# CONFIG_HWMON is not set 25# CONFIG_HWMON is not set
25# CONFIG_VGA_CONSOLE is not set
26# CONFIG_HID_SUPPORT is not set 26# CONFIG_HID_SUPPORT is not set
27# CONFIG_USB_SUPPORT is not set 27# CONFIG_USB_SUPPORT is not set
28CONFIG_EXT2_FS=y 28CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig
deleted file mode 100644
index 1079c2b6eb3a..000000000000
--- a/arch/arm/configs/stmp378x_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="-default"
3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y
5CONFIG_BSD_PROCESS_ACCT=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_EXPERT=y
9CONFIG_SLAB=y
10CONFIG_MODULES=y
11CONFIG_MODULE_UNLOAD=y
12CONFIG_MODULE_FORCE_UNLOAD=y
13CONFIG_MODVERSIONS=y
14CONFIG_MODULE_SRCVERSION_ALL=y
15# CONFIG_BLK_DEV_BSG is not set
16CONFIG_ARCH_STMP3XXX=y
17CONFIG_ARCH_STMP378X=y
18CONFIG_NO_HZ=y
19CONFIG_HIGH_RES_TIMERS=y
20CONFIG_PREEMPT=y
21CONFIG_AEABI=y
22CONFIG_HIGHMEM=y
23CONFIG_ZBOOT_ROM_TEXT=0x0
24CONFIG_ZBOOT_ROM_BSS=0x0
25CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M"
26CONFIG_NET=y
27CONFIG_PACKET=y
28CONFIG_UNIX=y
29CONFIG_INET=y
30CONFIG_IP_MULTICAST=y
31CONFIG_IP_ADVANCED_ROUTER=y
32CONFIG_IP_MULTIPLE_TABLES=y
33CONFIG_IP_ROUTE_MULTIPATH=y
34CONFIG_IP_ROUTE_VERBOSE=y
35CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y
37CONFIG_IP_PNP_BOOTP=y
38CONFIG_IP_MROUTE=y
39CONFIG_IP_PIMSM_V1=y
40CONFIG_IP_PIMSM_V2=y
41CONFIG_SYN_COOKIES=y
42# CONFIG_INET_LRO is not set
43# CONFIG_IPV6 is not set
44CONFIG_NET_SCHED=y
45# CONFIG_WIRELESS is not set
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
47# CONFIG_STANDALONE is not set
48CONFIG_MTD=y
49CONFIG_MTD_CHAR=y
50CONFIG_MTD_NAND=y
51CONFIG_MTD_UBI=y
52CONFIG_MTD_UBI_GLUEBI=y
53CONFIG_BLK_DEV_LOOP=y
54CONFIG_BLK_DEV_CRYPTOLOOP=y
55CONFIG_BLK_DEV_RAM=y
56CONFIG_BLK_DEV_RAM_COUNT=4
57CONFIG_BLK_DEV_RAM_SIZE=6144
58# CONFIG_MISC_DEVICES is not set
59CONFIG_SCSI=y
60CONFIG_BLK_DEV_SD=y
61CONFIG_CHR_DEV_SG=y
62# CONFIG_SCSI_LOWLEVEL is not set
63CONFIG_INPUT_POLLDEV=y
64CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
65CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
66CONFIG_INPUT_EVDEV=y
67# CONFIG_KEYBOARD_ATKBD is not set
68# CONFIG_INPUT_MOUSE is not set
69CONFIG_INPUT_TOUCHSCREEN=y
70CONFIG_INPUT_MISC=y
71# CONFIG_SERIO_SERPORT is not set
72CONFIG_VT_HW_CONSOLE_BINDING=y
73# CONFIG_LEGACY_PTYS is not set
74CONFIG_HW_RANDOM=y
75CONFIG_DEBUG_GPIO=y
76CONFIG_GPIO_SYSFS=y
77# CONFIG_HWMON is not set
78CONFIG_FB=y
79CONFIG_BACKLIGHT_LCD_SUPPORT=y
80CONFIG_LCD_CLASS_DEVICE=y
81CONFIG_BACKLIGHT_CLASS_DEVICE=y
82# CONFIG_VGA_CONSOLE is not set
83CONFIG_FRAMEBUFFER_CONSOLE=y
84CONFIG_LOGO=y
85# CONFIG_HID_SUPPORT is not set
86# CONFIG_USB_SUPPORT is not set
87# CONFIG_DNOTIFY is not set
88CONFIG_TMPFS=y
89CONFIG_CONFIGFS_FS=m
90# CONFIG_MISC_FILESYSTEMS is not set
91# CONFIG_NETWORK_FILESYSTEMS is not set
92# CONFIG_ENABLE_MUST_CHECK is not set
93CONFIG_STRIP_ASM_SYMS=y
94CONFIG_DEBUG_KERNEL=y
95CONFIG_DEBUG_SHIRQ=y
96# CONFIG_SCHED_DEBUG is not set
97CONFIG_DEBUG_OBJECTS=y
98CONFIG_DEBUG_OBJECTS_SELFTEST=y
99CONFIG_DEBUG_OBJECTS_FREE=y
100CONFIG_DEBUG_OBJECTS_TIMERS=y
101CONFIG_DEBUG_SLAB=y
102CONFIG_DEBUG_SLAB_LEAK=y
103CONFIG_DEBUG_RT_MUTEXES=y
104CONFIG_PROVE_LOCKING=y
105CONFIG_DEBUG_SPINLOCK_SLEEP=y
106CONFIG_DEBUG_KOBJECT=y
107# CONFIG_DEBUG_BUGVERBOSE is not set
108CONFIG_DEBUG_INFO=y
109# CONFIG_RCU_CPU_STALL_DETECTOR is not set
110CONFIG_SYSCTL_SYSCALL_CHECK=y
111CONFIG_BOOT_TRACER=y
112CONFIG_STACK_TRACER=y
113CONFIG_BLK_DEV_IO_TRACE=y
114CONFIG_KEYS=y
115CONFIG_KEYS_DEBUG_PROC_KEYS=y
116CONFIG_SECURITY=y
117CONFIG_CRYPTO_TEST=m
118CONFIG_CRYPTO_ECB=y
119CONFIG_CRYPTO_HMAC=y
120CONFIG_CRYPTO_MD5=y
121CONFIG_CRYPTO_SHA1=m
122CONFIG_CRYPTO_AES=m
123CONFIG_CRYPTO_DES=y
124CONFIG_CRYPTO_DEFLATE=y
125CONFIG_CRYPTO_LZO=y
126# CONFIG_CRYPTO_ANSI_CPRNG is not set
127CONFIG_CRC_CCITT=m
128CONFIG_CRC16=y
diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig
deleted file mode 100644
index 564a5cc44085..000000000000
--- a/arch/arm/configs/stmp37xx_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="-default"
3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y
5CONFIG_BSD_PROCESS_ACCT=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_EXPERT=y
9CONFIG_SLAB=y
10CONFIG_MODULES=y
11CONFIG_MODULE_UNLOAD=y
12CONFIG_MODULE_FORCE_UNLOAD=y
13CONFIG_MODVERSIONS=y
14CONFIG_MODULE_SRCVERSION_ALL=y
15# CONFIG_BLK_DEV_BSG is not set
16CONFIG_ARCH_STMP3XXX=y
17CONFIG_NO_HZ=y
18CONFIG_HIGH_RES_TIMERS=y
19CONFIG_PREEMPT=y
20CONFIG_AEABI=y
21CONFIG_ZBOOT_ROM_TEXT=0x0
22CONFIG_ZBOOT_ROM_BSS=0x0
23CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel"
24CONFIG_NET=y
25CONFIG_PACKET=y
26CONFIG_UNIX=y
27CONFIG_INET=y
28CONFIG_IP_MULTICAST=y
29CONFIG_IP_ADVANCED_ROUTER=y
30CONFIG_IP_MULTIPLE_TABLES=y
31CONFIG_IP_ROUTE_MULTIPATH=y
32CONFIG_IP_ROUTE_VERBOSE=y
33CONFIG_IP_PNP=y
34CONFIG_IP_PNP_DHCP=y
35CONFIG_IP_PNP_BOOTP=y
36CONFIG_IP_MROUTE=y
37CONFIG_IP_PIMSM_V1=y
38CONFIG_IP_PIMSM_V2=y
39CONFIG_SYN_COOKIES=y
40# CONFIG_INET_LRO is not set
41# CONFIG_IPV6 is not set
42CONFIG_NET_SCHED=y
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45# CONFIG_STANDALONE is not set
46CONFIG_BLK_DEV_LOOP=y
47CONFIG_BLK_DEV_CRYPTOLOOP=y
48CONFIG_BLK_DEV_RAM=y
49CONFIG_BLK_DEV_RAM_COUNT=4
50CONFIG_BLK_DEV_RAM_SIZE=6144
51# CONFIG_MISC_DEVICES is not set
52CONFIG_SCSI=y
53CONFIG_BLK_DEV_SD=y
54CONFIG_CHR_DEV_SG=y
55# CONFIG_SCSI_LOWLEVEL is not set
56CONFIG_INPUT_POLLDEV=y
57CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
58CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
59CONFIG_INPUT_EVDEV=y
60# CONFIG_KEYBOARD_ATKBD is not set
61# CONFIG_INPUT_MOUSE is not set
62CONFIG_INPUT_TOUCHSCREEN=y
63CONFIG_INPUT_MISC=y
64# CONFIG_SERIO_SERPORT is not set
65CONFIG_VT_HW_CONSOLE_BINDING=y
66# CONFIG_LEGACY_PTYS is not set
67CONFIG_HW_RANDOM=y
68CONFIG_DEBUG_GPIO=y
69CONFIG_GPIO_SYSFS=y
70# CONFIG_HWMON is not set
71CONFIG_FB=y
72CONFIG_BACKLIGHT_LCD_SUPPORT=y
73CONFIG_LCD_CLASS_DEVICE=y
74CONFIG_BACKLIGHT_CLASS_DEVICE=y
75# CONFIG_VGA_CONSOLE is not set
76CONFIG_FRAMEBUFFER_CONSOLE=y
77CONFIG_LOGO=y
78# CONFIG_HID_SUPPORT is not set
79# CONFIG_USB_SUPPORT is not set
80# CONFIG_DNOTIFY is not set
81CONFIG_TMPFS=y
82CONFIG_CONFIGFS_FS=m
83# CONFIG_MISC_FILESYSTEMS is not set
84# CONFIG_NETWORK_FILESYSTEMS is not set
85# CONFIG_ENABLE_MUST_CHECK is not set
86CONFIG_DEBUG_KERNEL=y
87# CONFIG_DEBUG_BUGVERBOSE is not set
88# CONFIG_RCU_CPU_STALL_DETECTOR is not set
89CONFIG_SYSCTL_SYSCALL_CHECK=y
90CONFIG_BOOT_TRACER=y
91CONFIG_STACK_TRACER=y
92CONFIG_BLK_DEV_IO_TRACE=y
93CONFIG_DEBUG_LL=y
94CONFIG_KEYS=y
95CONFIG_KEYS_DEBUG_PROC_KEYS=y
96CONFIG_SECURITY=y
97CONFIG_CRYPTO_TEST=m
98CONFIG_CRYPTO_ECB=y
99CONFIG_CRYPTO_HMAC=y
100CONFIG_CRYPTO_MD5=y
101CONFIG_CRYPTO_SHA1=m
102CONFIG_CRYPTO_AES=m
103CONFIG_CRYPTO_DES=y
104CONFIG_CRYPTO_DEFLATE=y
105CONFIG_CRYPTO_LZO=y
106# CONFIG_CRYPTO_ANSI_CPRNG is not set
107CONFIG_CRC_CCITT=m
108CONFIG_CRC16=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 0ce710f47500..cdd4d2bd3962 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y
32CONFIG_MTD_CFI=y 32CONFIG_MTD_CFI=y
33CONFIG_MTD_CFI_ADV_OPTIONS=y 33CONFIG_MTD_CFI_ADV_OPTIONS=y
34CONFIG_MTD_CFI_INTELEXT=y 34CONFIG_MTD_CFI_INTELEXT=y
35CONFIG_MTD_ARM_INTEGRATOR=y 35CONFIG_MTD_PHYSMAP=y
36CONFIG_BLK_DEV_RAM=y 36CONFIG_BLK_DEV_RAM=y
37CONFIG_EEPROM_LEGACY=m 37CONFIG_EEPROM_LEGACY=m
38CONFIG_NETDEVICES=y 38CONFIG_NETDEVICES=y
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index ca51143f97f1..42005542932b 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -6,8 +6,10 @@
6/* 6/*
7 * This is the maximum virtual address which can be DMA'd from. 7 * This is the maximum virtual address which can be DMA'd from.
8 */ 8 */
9#ifndef MAX_DMA_ADDRESS 9#ifndef ARM_DMA_ZONE_SIZE
10#define MAX_DMA_ADDRESS 0xffffffff 10#define MAX_DMA_ADDRESS 0xffffffff
11#else
12#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE)
11#endif 13#endif
12 14
13#ifdef CONFIG_ISA_DMA_API 15#ifdef CONFIG_ISA_DMA_API
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index c3cd8755e648..0e9ce8d9686e 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -108,6 +108,7 @@ struct task_struct;
108int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); 108int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
109#define ELF_CORE_COPY_TASK_REGS dump_task_regs 109#define ELF_CORE_COPY_TASK_REGS dump_task_regs
110 110
111#define CORE_DUMP_USE_REGSET
111#define ELF_EXEC_PAGESIZE 4096 112#define ELF_EXEC_PAGESIZE 4096
112 113
113/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 114/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 199a6b6de7f4..8c73900da9ed 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -3,16 +3,74 @@
3 3
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
7/* ARM doesn't provide unprivileged exclusive memory accessors */
8#include <asm-generic/futex.h>
9#else
10
11#include <linux/futex.h>
12#include <linux/uaccess.h>
13#include <asm/errno.h>
14
15#define __futex_atomic_ex_table(err_reg) \
16 "3:\n" \
17 " .pushsection __ex_table,\"a\"\n" \
18 " .align 3\n" \
19 " .long 1b, 4f, 2b, 4f\n" \
20 " .popsection\n" \
21 " .pushsection .fixup,\"ax\"\n" \
22 "4: mov %0, " err_reg "\n" \
23 " b 3b\n" \
24 " .popsection"
25
6#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
7 27
8#include <asm-generic/futex.h> 28#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
29 smp_mb(); \
30 __asm__ __volatile__( \
31 "1: ldrex %1, [%2]\n" \
32 " " insn "\n" \
33 "2: strex %1, %0, [%2]\n" \
34 " teq %1, #0\n" \
35 " bne 1b\n" \
36 " mov %0, #0\n" \
37 __futex_atomic_ex_table("%4") \
38 : "=&r" (ret), "=&r" (oldval) \
39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40 : "cc", "memory")
41
42static inline int
43futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
44 u32 oldval, u32 newval)
45{
46 int ret;
47 u32 val;
48
49 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
50 return -EFAULT;
51
52 smp_mb();
53 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
54 "1: ldrex %1, [%4]\n"
55 " teq %1, %2\n"
56 " ite eq @ explicit IT needed for the 2b label\n"
57 "2: strexeq %0, %3, [%4]\n"
58 " movne %0, #0\n"
59 " teq %0, #0\n"
60 " bne 1b\n"
61 __futex_atomic_ex_table("%5")
62 : "=&r" (ret), "=&r" (val)
63 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
64 : "cc", "memory");
65 smp_mb();
66
67 *uval = val;
68 return ret;
69}
9 70
10#else /* !SMP, we can work around lack of atomic ops by disabling preemption */ 71#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
11 72
12#include <linux/futex.h>
13#include <linux/preempt.h> 73#include <linux/preempt.h>
14#include <linux/uaccess.h>
15#include <asm/errno.h>
16#include <asm/domain.h> 74#include <asm/domain.h>
17 75
18#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
@@ -21,20 +79,38 @@
21 " " insn "\n" \ 79 " " insn "\n" \
22 "2: " T(str) " %0, [%2]\n" \ 80 "2: " T(str) " %0, [%2]\n" \
23 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
24 "3:\n" \ 82 __futex_atomic_ex_table("%4") \
25 " .pushsection __ex_table,\"a\"\n" \
26 " .align 3\n" \
27 " .long 1b, 4f, 2b, 4f\n" \
28 " .popsection\n" \
29 " .pushsection .fixup,\"ax\"\n" \
30 "4: mov %0, %4\n" \
31 " b 3b\n" \
32 " .popsection" \
33 : "=&r" (ret), "=&r" (oldval) \ 83 : "=&r" (ret), "=&r" (oldval) \
34 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
35 : "cc", "memory") 85 : "cc", "memory")
36 86
37static inline int 87static inline int
88futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
89 u32 oldval, u32 newval)
90{
91 int ret = 0;
92 u32 val;
93
94 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
95 return -EFAULT;
96
97 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
98 "1: " T(ldr) " %1, [%4]\n"
99 " teq %1, %2\n"
100 " it eq @ explicit IT needed for the 2b label\n"
101 "2: " T(streq) " %3, [%4]\n"
102 __futex_atomic_ex_table("%5")
103 : "+r" (ret), "=&r" (val)
104 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
105 : "cc", "memory");
106
107 *uval = val;
108 return ret;
109}
110
111#endif /* !SMP */
112
113static inline int
38futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) 114futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
39{ 115{
40 int op = (encoded_op >> 28) & 7; 116 int op = (encoded_op >> 28) & 7;
@@ -87,39 +163,6 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
87 return ret; 163 return ret;
88} 164}
89 165
90static inline int 166#endif /* !(CPU_USE_DOMAINS && SMP) */
91futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
92 u32 oldval, u32 newval)
93{
94 int ret = 0;
95 u32 val;
96
97 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
98 return -EFAULT;
99
100 __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
101 "1: " T(ldr) " %1, [%4]\n"
102 " teq %1, %2\n"
103 " it eq @ explicit IT needed for the 2b label\n"
104 "2: " T(streq) " %3, [%4]\n"
105 "3:\n"
106 " .pushsection __ex_table,\"a\"\n"
107 " .align 3\n"
108 " .long 1b, 4f, 2b, 4f\n"
109 " .popsection\n"
110 " .pushsection .fixup,\"ax\"\n"
111 "4: mov %0, %5\n"
112 " b 3b\n"
113 " .popsection"
114 : "+r" (ret), "=&r" (val)
115 : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
116 : "cc", "memory");
117
118 *uval = val;
119 return ret;
120}
121
122#endif /* !SMP */
123
124#endif /* __KERNEL__ */ 167#endif /* __KERNEL__ */
125#endif /* _ASM_ARM_FUTEX_H */ 168#endif /* _ASM_ARM_FUTEX_H */
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 21e75e30d497..4384d81eee79 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,2 +1,2 @@
1void sp804_clocksource_init(void __iomem *); 1void sp804_clocksource_init(void __iomem *, const char *);
2void sp804_clockevents_init(void __iomem *, unsigned int); 2void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 431077c5a867..af44a8fb3480 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -209,14 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x)
209 * allocations. This must be the smallest DMA mask in the system, 209 * allocations. This must be the smallest DMA mask in the system,
210 * so a successful GFP_DMA allocation will always satisfy this. 210 * so a successful GFP_DMA allocation will always satisfy this.
211 */ 211 */
212#ifndef ISA_DMA_THRESHOLD 212#ifndef ARM_DMA_ZONE_SIZE
213#define ISA_DMA_THRESHOLD (0xffffffffULL) 213#define ISA_DMA_THRESHOLD (0xffffffffULL)
214#endif 214#else
215 215#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1)
216#ifndef arch_adjust_zones
217#define arch_adjust_zones(size,holes) do { } while (0)
218#elif !defined(CONFIG_ZONE_DMA)
219#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
220#endif 216#endif
221 217
222/* 218/*
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index a8ff22b2a391..312d10877bd7 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -128,6 +128,12 @@ struct pt_regs {
128#define ARM_r0 uregs[0] 128#define ARM_r0 uregs[0]
129#define ARM_ORIG_r0 uregs[17] 129#define ARM_ORIG_r0 uregs[17]
130 130
131/*
132 * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
133 * and core dumps.
134 */
135#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )
136
131#ifdef __KERNEL__ 137#ifdef __KERNEL__
132 138
133#define user_mode(regs) \ 139#define user_mode(regs) \
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 316bb2b2be3d..154b89b81d3e 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -16,44 +16,6 @@
16/* Size definitions 16/* Size definitions
17 * Copyright (C) ARM Limited 1998. All rights reserved. 17 * Copyright (C) ARM Limited 1998. All rights reserved.
18 */ 18 */
19#include <asm-generic/sizes.h>
19 20
20#ifndef __sizes_h 21#define SZ_48M (SZ_32M + SZ_16M)
21#define __sizes_h 1
22
23/* handy sizes */
24#define SZ_16 0x00000010
25#define SZ_32 0x00000020
26#define SZ_64 0x00000040
27#define SZ_128 0x00000080
28#define SZ_256 0x00000100
29#define SZ_512 0x00000200
30
31#define SZ_1K 0x00000400
32#define SZ_2K 0x00000800
33#define SZ_4K 0x00001000
34#define SZ_8K 0x00002000
35#define SZ_16K 0x00004000
36#define SZ_32K 0x00008000
37#define SZ_64K 0x00010000
38#define SZ_128K 0x00020000
39#define SZ_256K 0x00040000
40#define SZ_512K 0x00080000
41
42#define SZ_1M 0x00100000
43#define SZ_2M 0x00200000
44#define SZ_4M 0x00400000
45#define SZ_8M 0x00800000
46#define SZ_16M 0x01000000
47#define SZ_32M 0x02000000
48#define SZ_48M 0x03000000
49#define SZ_64M 0x04000000
50#define SZ_128M 0x08000000
51#define SZ_256M 0x10000000
52#define SZ_512M 0x20000000
53
54#define SZ_1G 0x40000000
55#define SZ_2G 0x80000000
56
57#endif
58
59/* END */
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 96ed521f2408..a87664f54f93 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -14,8 +14,6 @@
14#include <linux/cpumask.h> 14#include <linux/cpumask.h>
15#include <linux/thread_info.h> 15#include <linux/thread_info.h>
16 16
17#include <mach/smp.h>
18
19#ifndef CONFIG_SMP 17#ifndef CONFIG_SMP
20# error "<asm/smp.h> included in non-SMP build" 18# error "<asm/smp.h> included in non-SMP build"
21#endif 19#endif
@@ -47,9 +45,9 @@ extern void smp_init_cpus(void);
47 45
48 46
49/* 47/*
50 * Raise an IPI cross call on CPUs in callmap. 48 * Provide a function to raise an IPI cross call on CPUs in callmap.
51 */ 49 */
52extern void smp_cross_call(const struct cpumask *mask, int ipi); 50extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
53 51
54/* 52/*
55 * Boot a secondary CPU, and assign it the specified idle task. 53 * Boot a secondary CPU, and assign it the specified idle task.
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index fdd3820edff8..65fa3c88095c 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -5,6 +5,8 @@
5#error SMP not supported on pre-ARMv6 CPUs 5#error SMP not supported on pre-ARMv6 CPUs
6#endif 6#endif
7 7
8#include <asm/processor.h>
9
8/* 10/*
9 * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K 11 * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K
10 * extensions, so when running on UP, we have to patch these instructions away. 12 * extensions, so when running on UP, we have to patch these instructions away.
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 139e3c827369..d53c0abc4dd3 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -560,11 +560,6 @@ static int armpmu_event_init(struct perf_event *event)
560 event->destroy = hw_perf_event_destroy; 560 event->destroy = hw_perf_event_destroy;
561 561
562 if (!atomic_inc_not_zero(&active_events)) { 562 if (!atomic_inc_not_zero(&active_events)) {
563 if (atomic_read(&active_events) > armpmu->num_events) {
564 atomic_dec(&active_events);
565 return -ENOSPC;
566 }
567
568 mutex_lock(&pmu_reserve_mutex); 563 mutex_lock(&pmu_reserve_mutex);
569 if (atomic_read(&active_events) == 0) { 564 if (atomic_read(&active_events) == 0) {
570 err = armpmu_reserve_hardware(); 565 err = armpmu_reserve_hardware();
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 8182f45ca493..97260060bf26 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -21,6 +21,7 @@
21#include <linux/uaccess.h> 21#include <linux/uaccess.h>
22#include <linux/perf_event.h> 22#include <linux/perf_event.h>
23#include <linux/hw_breakpoint.h> 23#include <linux/hw_breakpoint.h>
24#include <linux/regset.h>
24 25
25#include <asm/pgtable.h> 26#include <asm/pgtable.h>
26#include <asm/system.h> 27#include <asm/system.h>
@@ -308,58 +309,6 @@ static int ptrace_write_user(struct task_struct *tsk, unsigned long off,
308 return put_user_reg(tsk, off >> 2, val); 309 return put_user_reg(tsk, off >> 2, val);
309} 310}
310 311
311/*
312 * Get all user integer registers.
313 */
314static int ptrace_getregs(struct task_struct *tsk, void __user *uregs)
315{
316 struct pt_regs *regs = task_pt_regs(tsk);
317
318 return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
319}
320
321/*
322 * Set all user integer registers.
323 */
324static int ptrace_setregs(struct task_struct *tsk, void __user *uregs)
325{
326 struct pt_regs newregs;
327 int ret;
328
329 ret = -EFAULT;
330 if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) {
331 struct pt_regs *regs = task_pt_regs(tsk);
332
333 ret = -EINVAL;
334 if (valid_user_regs(&newregs)) {
335 *regs = newregs;
336 ret = 0;
337 }
338 }
339
340 return ret;
341}
342
343/*
344 * Get the child FPU state.
345 */
346static int ptrace_getfpregs(struct task_struct *tsk, void __user *ufp)
347{
348 return copy_to_user(ufp, &task_thread_info(tsk)->fpstate,
349 sizeof(struct user_fp)) ? -EFAULT : 0;
350}
351
352/*
353 * Set the child FPU state.
354 */
355static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp)
356{
357 struct thread_info *thread = task_thread_info(tsk);
358 thread->used_cp[1] = thread->used_cp[2] = 1;
359 return copy_from_user(&thread->fpstate, ufp,
360 sizeof(struct user_fp)) ? -EFAULT : 0;
361}
362
363#ifdef CONFIG_IWMMXT 312#ifdef CONFIG_IWMMXT
364 313
365/* 314/*
@@ -418,56 +367,6 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp)
418} 367}
419#endif 368#endif
420 369
421#ifdef CONFIG_VFP
422/*
423 * Get the child VFP state.
424 */
425static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
426{
427 struct thread_info *thread = task_thread_info(tsk);
428 union vfp_state *vfp = &thread->vfpstate;
429 struct user_vfp __user *ufp = data;
430
431 vfp_sync_hwstate(thread);
432
433 /* copy the floating point registers */
434 if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
435 sizeof(vfp->hard.fpregs)))
436 return -EFAULT;
437
438 /* copy the status and control register */
439 if (put_user(vfp->hard.fpscr, &ufp->fpscr))
440 return -EFAULT;
441
442 return 0;
443}
444
445/*
446 * Set the child VFP state.
447 */
448static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
449{
450 struct thread_info *thread = task_thread_info(tsk);
451 union vfp_state *vfp = &thread->vfpstate;
452 struct user_vfp __user *ufp = data;
453
454 vfp_sync_hwstate(thread);
455
456 /* copy the floating point registers */
457 if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
458 sizeof(vfp->hard.fpregs)))
459 return -EFAULT;
460
461 /* copy the status and control register */
462 if (get_user(vfp->hard.fpscr, &ufp->fpscr))
463 return -EFAULT;
464
465 vfp_flush_hwstate(thread);
466
467 return 0;
468}
469#endif
470
471#ifdef CONFIG_HAVE_HW_BREAKPOINT 370#ifdef CONFIG_HAVE_HW_BREAKPOINT
472/* 371/*
473 * Convert a virtual register number into an index for a thread_info 372 * Convert a virtual register number into an index for a thread_info
@@ -694,6 +593,219 @@ out:
694} 593}
695#endif 594#endif
696 595
596/* regset get/set implementations */
597
598static int gpr_get(struct task_struct *target,
599 const struct user_regset *regset,
600 unsigned int pos, unsigned int count,
601 void *kbuf, void __user *ubuf)
602{
603 struct pt_regs *regs = task_pt_regs(target);
604
605 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
606 regs,
607 0, sizeof(*regs));
608}
609
610static int gpr_set(struct task_struct *target,
611 const struct user_regset *regset,
612 unsigned int pos, unsigned int count,
613 const void *kbuf, const void __user *ubuf)
614{
615 int ret;
616 struct pt_regs newregs;
617
618 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
619 &newregs,
620 0, sizeof(newregs));
621 if (ret)
622 return ret;
623
624 if (!valid_user_regs(&newregs))
625 return -EINVAL;
626
627 *task_pt_regs(target) = newregs;
628 return 0;
629}
630
631static int fpa_get(struct task_struct *target,
632 const struct user_regset *regset,
633 unsigned int pos, unsigned int count,
634 void *kbuf, void __user *ubuf)
635{
636 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
637 &task_thread_info(target)->fpstate,
638 0, sizeof(struct user_fp));
639}
640
641static int fpa_set(struct task_struct *target,
642 const struct user_regset *regset,
643 unsigned int pos, unsigned int count,
644 const void *kbuf, const void __user *ubuf)
645{
646 struct thread_info *thread = task_thread_info(target);
647
648 thread->used_cp[1] = thread->used_cp[2] = 1;
649
650 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
651 &thread->fpstate,
652 0, sizeof(struct user_fp));
653}
654
655#ifdef CONFIG_VFP
656/*
657 * VFP register get/set implementations.
658 *
659 * With respect to the kernel, struct user_fp is divided into three chunks:
660 * 16 or 32 real VFP registers (d0-d15 or d0-31)
661 * These are transferred to/from the real registers in the task's
662 * vfp_hard_struct. The number of registers depends on the kernel
663 * configuration.
664 *
665 * 16 or 0 fake VFP registers (d16-d31 or empty)
666 * i.e., the user_vfp structure has space for 32 registers even if
667 * the kernel doesn't have them all.
668 *
669 * vfp_get() reads this chunk as zero where applicable
670 * vfp_set() ignores this chunk
671 *
672 * 1 word for the FPSCR
673 *
674 * The bounds-checking logic built into user_regset_copyout and friends
675 * means that we can make a simple sequence of calls to map the relevant data
676 * to/from the specified slice of the user regset structure.
677 */
678static int vfp_get(struct task_struct *target,
679 const struct user_regset *regset,
680 unsigned int pos, unsigned int count,
681 void *kbuf, void __user *ubuf)
682{
683 int ret;
684 struct thread_info *thread = task_thread_info(target);
685 struct vfp_hard_struct const *vfp = &thread->vfpstate.hard;
686 const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
687 const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
688
689 vfp_sync_hwstate(thread);
690
691 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
692 &vfp->fpregs,
693 user_fpregs_offset,
694 user_fpregs_offset + sizeof(vfp->fpregs));
695 if (ret)
696 return ret;
697
698 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
699 user_fpregs_offset + sizeof(vfp->fpregs),
700 user_fpscr_offset);
701 if (ret)
702 return ret;
703
704 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
705 &vfp->fpscr,
706 user_fpscr_offset,
707 user_fpscr_offset + sizeof(vfp->fpscr));
708}
709
710/*
711 * For vfp_set() a read-modify-write is done on the VFP registers,
712 * in order to avoid writing back a half-modified set of registers on
713 * failure.
714 */
715static int vfp_set(struct task_struct *target,
716 const struct user_regset *regset,
717 unsigned int pos, unsigned int count,
718 const void *kbuf, const void __user *ubuf)
719{
720 int ret;
721 struct thread_info *thread = task_thread_info(target);
722 struct vfp_hard_struct new_vfp = thread->vfpstate.hard;
723 const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
724 const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
725
726 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
727 &new_vfp.fpregs,
728 user_fpregs_offset,
729 user_fpregs_offset + sizeof(new_vfp.fpregs));
730 if (ret)
731 return ret;
732
733 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
734 user_fpregs_offset + sizeof(new_vfp.fpregs),
735 user_fpscr_offset);
736 if (ret)
737 return ret;
738
739 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
740 &new_vfp.fpscr,
741 user_fpscr_offset,
742 user_fpscr_offset + sizeof(new_vfp.fpscr));
743 if (ret)
744 return ret;
745
746 vfp_sync_hwstate(thread);
747 thread->vfpstate.hard = new_vfp;
748 vfp_flush_hwstate(thread);
749
750 return 0;
751}
752#endif /* CONFIG_VFP */
753
754enum arm_regset {
755 REGSET_GPR,
756 REGSET_FPR,
757#ifdef CONFIG_VFP
758 REGSET_VFP,
759#endif
760};
761
762static const struct user_regset arm_regsets[] = {
763 [REGSET_GPR] = {
764 .core_note_type = NT_PRSTATUS,
765 .n = ELF_NGREG,
766 .size = sizeof(u32),
767 .align = sizeof(u32),
768 .get = gpr_get,
769 .set = gpr_set
770 },
771 [REGSET_FPR] = {
772 /*
773 * For the FPA regs in fpstate, the real fields are a mixture
774 * of sizes, so pretend that the registers are word-sized:
775 */
776 .core_note_type = NT_PRFPREG,
777 .n = sizeof(struct user_fp) / sizeof(u32),
778 .size = sizeof(u32),
779 .align = sizeof(u32),
780 .get = fpa_get,
781 .set = fpa_set
782 },
783#ifdef CONFIG_VFP
784 [REGSET_VFP] = {
785 /*
786 * Pretend that the VFP regs are word-sized, since the FPSCR is
787 * a single word dangling at the end of struct user_vfp:
788 */
789 .core_note_type = NT_ARM_VFP,
790 .n = ARM_VFPREGS_SIZE / sizeof(u32),
791 .size = sizeof(u32),
792 .align = sizeof(u32),
793 .get = vfp_get,
794 .set = vfp_set
795 },
796#endif /* CONFIG_VFP */
797};
798
799static const struct user_regset_view user_arm_view = {
800 .name = "arm", .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
801 .regsets = arm_regsets, .n = ARRAY_SIZE(arm_regsets)
802};
803
804const struct user_regset_view *task_user_regset_view(struct task_struct *task)
805{
806 return &user_arm_view;
807}
808
697long arch_ptrace(struct task_struct *child, long request, 809long arch_ptrace(struct task_struct *child, long request,
698 unsigned long addr, unsigned long data) 810 unsigned long addr, unsigned long data)
699{ 811{
@@ -710,19 +822,31 @@ long arch_ptrace(struct task_struct *child, long request,
710 break; 822 break;
711 823
712 case PTRACE_GETREGS: 824 case PTRACE_GETREGS:
713 ret = ptrace_getregs(child, datap); 825 ret = copy_regset_to_user(child,
826 &user_arm_view, REGSET_GPR,
827 0, sizeof(struct pt_regs),
828 datap);
714 break; 829 break;
715 830
716 case PTRACE_SETREGS: 831 case PTRACE_SETREGS:
717 ret = ptrace_setregs(child, datap); 832 ret = copy_regset_from_user(child,
833 &user_arm_view, REGSET_GPR,
834 0, sizeof(struct pt_regs),
835 datap);
718 break; 836 break;
719 837
720 case PTRACE_GETFPREGS: 838 case PTRACE_GETFPREGS:
721 ret = ptrace_getfpregs(child, datap); 839 ret = copy_regset_to_user(child,
840 &user_arm_view, REGSET_FPR,
841 0, sizeof(union fp_state),
842 datap);
722 break; 843 break;
723 844
724 case PTRACE_SETFPREGS: 845 case PTRACE_SETFPREGS:
725 ret = ptrace_setfpregs(child, datap); 846 ret = copy_regset_from_user(child,
847 &user_arm_view, REGSET_FPR,
848 0, sizeof(union fp_state),
849 datap);
726 break; 850 break;
727 851
728#ifdef CONFIG_IWMMXT 852#ifdef CONFIG_IWMMXT
@@ -757,11 +881,17 @@ long arch_ptrace(struct task_struct *child, long request,
757 881
758#ifdef CONFIG_VFP 882#ifdef CONFIG_VFP
759 case PTRACE_GETVFPREGS: 883 case PTRACE_GETVFPREGS:
760 ret = ptrace_getvfpregs(child, datap); 884 ret = copy_regset_to_user(child,
885 &user_arm_view, REGSET_VFP,
886 0, ARM_VFPREGS_SIZE,
887 datap);
761 break; 888 break;
762 889
763 case PTRACE_SETVFPREGS: 890 case PTRACE_SETVFPREGS:
764 ret = ptrace_setvfpregs(child, datap); 891 ret = copy_regset_from_user(child,
892 &user_arm_view, REGSET_VFP,
893 0, ARM_VFPREGS_SIZE,
894 datap);
765 break; 895 break;
766#endif 896#endif
767 897
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 006c1e884eaf..6dce209a623b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -672,11 +672,16 @@ __tagtable(ATAG_REVISION, parse_tag_revision);
672 672
673static int __init parse_tag_cmdline(const struct tag *tag) 673static int __init parse_tag_cmdline(const struct tag *tag)
674{ 674{
675#ifndef CONFIG_CMDLINE_FORCE 675#if defined(CONFIG_CMDLINE_EXTEND)
676 strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); 676 strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
677#else 677 strlcat(default_command_line, tag->u.cmdline.cmdline,
678 COMMAND_LINE_SIZE);
679#elif defined(CONFIG_CMDLINE_FORCE)
678 pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); 680 pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
679#endif /* CONFIG_CMDLINE_FORCE */ 681#else
682 strlcpy(default_command_line, tag->u.cmdline.cmdline,
683 COMMAND_LINE_SIZE);
684#endif
680 return 0; 685 return 0;
681} 686}
682 687
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 007a0a950e75..d439a8f4c078 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -376,6 +376,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
376 } 376 }
377} 377}
378 378
379static void (*smp_cross_call)(const struct cpumask *, unsigned int);
380
381void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
382{
383 smp_cross_call = fn;
384}
385
379void arch_send_call_function_ipi_mask(const struct cpumask *mask) 386void arch_send_call_function_ipi_mask(const struct cpumask *mask)
380{ 387{
381 smp_cross_call(mask, IPI_CALL_FUNC); 388 smp_cross_call(mask, IPI_CALL_FUNC);
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 73eb066d2329..a604b9ebb501 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -169,6 +169,7 @@ MACHINE_START(BCMRING, "BCMRING")
169 /* Maintainer: Broadcom Corporation */ 169 /* Maintainer: Broadcom Corporation */
170 .fixup = bcmring_fixup, 170 .fixup = bcmring_fixup,
171 .map_io = bcmring_map_io, 171 .map_io = bcmring_map_io,
172 .init_early = bcmring_init_early,
172 .init_irq = bcmring_init_irq, 173 .init_irq = bcmring_init_irq,
173 .timer = &bcmring_timer, 174 .timer = &bcmring_timer,
174 .init_machine = bcmring_init_machine 175 .init_machine = bcmring_init_machine
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 8fc2035759fb..43eadbcc29ed 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -28,8 +28,6 @@
28#include <linux/sysdev.h> 28#include <linux/sysdev.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/clocksource.h>
32#include <linux/clockchips.h>
33#include <linux/clkdev.h> 31#include <linux/clkdev.h>
34 32
35#include <mach/csp/mm_addr.h> 33#include <mach/csp/mm_addr.h>
@@ -37,6 +35,7 @@
37#include <linux/io.h> 35#include <linux/io.h>
38#include <asm/irq.h> 36#include <asm/irq.h>
39#include <asm/hardware/arm_timer.h> 37#include <asm/hardware/arm_timer.h>
38#include <asm/hardware/timer-sp.h>
40#include <asm/mach-types.h> 39#include <asm/mach-types.h>
41 40
42#include <asm/mach/arch.h> 41#include <asm/mach/arch.h>
@@ -97,6 +96,35 @@ static struct clk dummy_apb_pclk = {
97 .mode = CLK_MODE_XTAL, 96 .mode = CLK_MODE_XTAL,
98}; 97};
99 98
99/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
100#if defined(CONFIG_ARCH_FPGA11107)
101/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
102/* slow down Linux's sense of time */
103#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
104#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
105#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
106#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
107#else
108#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
109#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
110#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
111#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
112#endif
113
114static struct clk sp804_timer012_clk = {
115 .name = "sp804-timer-0,1,2",
116 .type = CLK_TYPE_PRIMARY,
117 .mode = CLK_MODE_XTAL,
118 .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
119};
120
121static struct clk sp804_timer3_clk = {
122 .name = "sp804-timer-3",
123 .type = CLK_TYPE_PRIMARY,
124 .mode = CLK_MODE_XTAL,
125 .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
126};
127
100static struct clk_lookup lookups[] = { 128static struct clk_lookup lookups[] = {
101 { /* Bus clock */ 129 { /* Bus clock */
102 .con_id = "apb_pclk", 130 .con_id = "apb_pclk",
@@ -107,6 +135,18 @@ static struct clk_lookup lookups[] = {
107 }, { /* UART1 */ 135 }, { /* UART1 */
108 .dev_id = "uartb", 136 .dev_id = "uartb",
109 .clk = &uart_clk, 137 .clk = &uart_clk,
138 }, { /* SP804 timer 0 */
139 .dev_id = "sp804",
140 .con_id = "timer0",
141 .clk = &sp804_timer012_clk,
142 }, { /* SP804 timer 1 */
143 .dev_id = "sp804",
144 .con_id = "timer1",
145 .clk = &sp804_timer012_clk,
146 }, { /* SP804 timer 3 */
147 .dev_id = "sp804",
148 .con_id = "timer3",
149 .clk = &sp804_timer3_clk,
110 } 150 }
111}; 151};
112 152
@@ -151,8 +191,6 @@ void __init bcmring_amba_init(void)
151 191
152 chipcHw_busInterfaceClockEnable(bus_clock); 192 chipcHw_busInterfaceClockEnable(bus_clock);
153 193
154 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
155
156 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 194 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
157 struct amba_device *d = amba_devs[i]; 195 struct amba_device *d = amba_devs[i];
158 amba_device_register(d, &iomem_resource); 196 amba_device_register(d, &iomem_resource);
@@ -162,170 +200,18 @@ void __init bcmring_amba_init(void)
162/* 200/*
163 * Where is the timer (VA)? 201 * Where is the timer (VA)?
164 */ 202 */
165#define TIMER0_VA_BASE MM_IO_BASE_TMR 203#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
166#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20) 204#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
167#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40) 205#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
168#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60) 206#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
169
170/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
171#if defined(CONFIG_ARCH_FPGA11107)
172/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
173/* slow down Linux's sense of time */
174#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
175#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
176#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
177#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
178#else
179#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
180#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
181#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
182#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
183#endif
184
185#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
186
187/*
188 * These are useconds NOT ticks.
189 *
190 */
191#define mSEC_1 1000
192#define mSEC_5 (mSEC_1 * 5)
193#define mSEC_10 (mSEC_1 * 10)
194#define mSEC_25 (mSEC_1 * 25)
195#define SEC_1 (mSEC_1 * 1000)
196
197/*
198 * How long is the timer interval?
199 */
200#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
201#if TIMER_INTERVAL >= 0x100000
202#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
203#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
204#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
205#elif TIMER_INTERVAL >= 0x10000
206#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
207#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
208#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
209#else
210#define TIMER_RELOAD (TIMER_INTERVAL)
211#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
212#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
213#endif
214
215static void timer_set_mode(enum clock_event_mode mode,
216 struct clock_event_device *clk)
217{
218 unsigned long ctrl;
219
220 switch (mode) {
221 case CLOCK_EVT_MODE_PERIODIC:
222 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
223
224 ctrl = TIMER_CTRL_PERIODIC;
225 ctrl |=
226 TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
227 TIMER_CTRL_ENABLE;
228 break;
229 case CLOCK_EVT_MODE_ONESHOT:
230 /* period set, and timer enabled in 'next_event' hook */
231 ctrl = TIMER_CTRL_ONESHOT;
232 ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
233 break;
234 case CLOCK_EVT_MODE_UNUSED:
235 case CLOCK_EVT_MODE_SHUTDOWN:
236 default:
237 ctrl = 0;
238 }
239
240 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
241}
242
243static int timer_set_next_event(unsigned long evt,
244 struct clock_event_device *unused)
245{
246 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
247
248 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
249 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
250
251 return 0;
252}
253
254static struct clock_event_device timer0_clockevent = {
255 .name = "timer0",
256 .shift = 32,
257 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
258 .set_mode = timer_set_mode,
259 .set_next_event = timer_set_next_event,
260};
261
262/*
263 * IRQ handler for the timer
264 */
265static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
266{
267 struct clock_event_device *evt = &timer0_clockevent;
268
269 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
270
271 evt->event_handler(evt);
272
273 return IRQ_HANDLED;
274}
275
276static struct irqaction bcmring_timer_irq = {
277 .name = "bcmring Timer Tick",
278 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
279 .handler = bcmring_timer_interrupt,
280};
281
282static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs)
283{
284 return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
285}
286
287static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs)
288{
289 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
290}
291
292static struct clocksource clocksource_bcmring_timer1 = {
293 .name = "timer1",
294 .rating = 200,
295 .read = bcmring_get_cycles_timer1,
296 .mask = CLOCKSOURCE_MASK(32),
297 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
298};
299
300static struct clocksource clocksource_bcmring_timer3 = {
301 .name = "timer3",
302 .rating = 100,
303 .read = bcmring_get_cycles_timer3,
304 .mask = CLOCKSOURCE_MASK(32),
305 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
306};
307 207
308static int __init bcmring_clocksource_init(void) 208static int __init bcmring_clocksource_init(void)
309{ 209{
310 /* setup timer1 as free-running clocksource */ 210 /* setup timer1 as free-running clocksource */
311 writel(0, TIMER1_VA_BASE + TIMER_CTRL); 211 sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
312 writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
313 writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
314 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
315 TIMER1_VA_BASE + TIMER_CTRL);
316
317 clocksource_register_khz(&clocksource_bcmring_timer1,
318 TIMER1_FREQUENCY_MHZ * 1000);
319 212
320 /* setup timer3 as free-running clocksource */ 213 /* setup timer3 as free-running clocksource */
321 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 214 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
322 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
323 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
324 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
325 TIMER3_VA_BASE + TIMER_CTRL);
326
327 clocksource_register_khz(&clocksource_bcmring_timer3,
328 TIMER3_FREQUENCY_KHZ);
329 215
330 return 0; 216 return 0;
331} 217}
@@ -347,21 +233,16 @@ void __init bcmring_init_timer(void)
347 /* 233 /*
348 * Make irqs happen for the system timer 234 * Make irqs happen for the system timer
349 */ 235 */
350 setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
351
352 bcmring_clocksource_init(); 236 bcmring_clocksource_init();
353 237
354 timer0_clockevent.mult = 238 sp804_clockevents_register(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
355 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
356 timer0_clockevent.max_delta_ns =
357 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
358 timer0_clockevent.min_delta_ns =
359 clockevent_delta2ns(0xf, &timer0_clockevent);
360
361 timer0_clockevent.cpumask = cpumask_of(0);
362 clockevents_register_device(&timer0_clockevent);
363} 239}
364 240
365struct sys_timer bcmring_timer = { 241struct sys_timer bcmring_timer = {
366 .init = bcmring_init_timer, 242 .init = bcmring_init_timer,
367}; 243};
244
245void __init bcmring_init_early(void)
246{
247 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
248}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
index b197ba48e36e..e0e02c48f9b1 100644
--- a/arch/arm/mach-bcmring/core.h
+++ b/arch/arm/mach-bcmring/core.h
@@ -25,6 +25,7 @@
25void __init bcmring_amba_init(void); 25void __init bcmring_amba_init(void);
26void __init bcmring_map_io(void); 26void __init bcmring_map_io(void);
27void __init bcmring_init_irq(void); 27void __init bcmring_init_irq(void);
28void __init bcmring_init_early(void);
28 29
29extern struct sys_timer bcmring_timer; 30extern struct sys_timer bcmring_timer;
30#endif 31#endif
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 78822723f382..491249ef209c 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -41,27 +41,11 @@
41 */ 41 */
42#define CONSISTENT_DMA_SIZE (14<<20) 42#define CONSISTENT_DMA_SIZE (14<<20)
43 43
44#ifndef __ASSEMBLY__
45/* 44/*
46 * Restrict DMA-able region to workaround silicon bug. The bug 45 * Restrict DMA-able region to workaround silicon bug. The bug
47 * restricts buffers available for DMA to video hardware to be 46 * restricts buffers available for DMA to video hardware to be
48 * below 128M 47 * below 128M
49 */ 48 */
50static inline void 49#define ARM_DMA_ZONE_SIZE SZ_128M
51__arch_adjust_zones(unsigned long *size, unsigned long *holes)
52{
53 unsigned int sz = (128<<20) >> PAGE_SHIFT;
54
55 size[1] = size[0] - sz;
56 size[0] = sz;
57}
58
59#define arch_adjust_zones(zone_size, holes) \
60 if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
61
62#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
63#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))
64
65#endif
66 50
67#endif /* __ASM_ARCH_MEMORY_H */ 51#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 47723e8d75a4..78d80683cdc2 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,8 +25,7 @@
25 25
26#include <mach/serial.h> 26#include <mach/serial.h>
27 27
28static u32 *uart; 28u32 *uart;
29static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
30 29
31/* PORT_16C550A, in polled non-fifo mode */ 30/* PORT_16C550A, in polled non-fifo mode */
32static void putc(char c) 31static void putc(char c)
@@ -44,6 +43,8 @@ static inline void flush(void)
44 43
45static inline void set_uart_info(u32 phys, void * __iomem virt) 44static inline void set_uart_info(u32 phys, void * __iomem virt)
46{ 45{
46 u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
47
47 uart = (u32 *)phys; 48 uart = (u32 *)phys;
48 uart_info[0] = phys; 49 uart_info[0] = phys;
49 uart_info[1] = (u32)virt; 50 uart_info[1] = (u32)virt;
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index e6269a6e0014..bfe68ec4e1a6 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -29,8 +29,6 @@
29#include <mach/common.h> 29#include <mach/common.h>
30#include <asm/mach/irq.h> 30#include <asm/mach/irq.h>
31 31
32#define IRQ_BIT(irq) ((irq) & 0x1f)
33
34#define FIQ_REG0_OFFSET 0x0000 32#define FIQ_REG0_OFFSET 0x0000
35#define FIQ_REG1_OFFSET 0x0004 33#define FIQ_REG1_OFFSET 0x0004
36#define IRQ_REG0_OFFSET 0x0008 34#define IRQ_REG0_OFFSET 0x0008
@@ -42,78 +40,33 @@
42#define IRQ_INTPRI0_REG_OFFSET 0x0030 40#define IRQ_INTPRI0_REG_OFFSET 0x0030
43#define IRQ_INTPRI7_REG_OFFSET 0x004C 41#define IRQ_INTPRI7_REG_OFFSET 0x004C
44 42
45static inline unsigned int davinci_irq_readl(int offset)
46{
47 return __raw_readl(davinci_intc_base + offset);
48}
49
50static inline void davinci_irq_writel(unsigned long value, int offset) 43static inline void davinci_irq_writel(unsigned long value, int offset)
51{ 44{
52 __raw_writel(value, davinci_intc_base + offset); 45 __raw_writel(value, davinci_intc_base + offset);
53} 46}
54 47
55/* Disable interrupt */ 48static __init void
56static void davinci_mask_irq(struct irq_data *d) 49davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
57{ 50{
58 unsigned int mask; 51 struct irq_chip_generic *gc;
59 u32 l; 52 struct irq_chip_type *ct;
60 53
61 mask = 1 << IRQ_BIT(d->irq); 54 gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
62 55 ct = gc->chip_types;
63 if (d->irq > 31) { 56 ct->chip.irq_ack = irq_gc_ack;
64 l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); 57 ct->chip.irq_mask = irq_gc_mask_clr_bit;
65 l &= ~mask; 58 ct->chip.irq_unmask = irq_gc_mask_set_bit;
66 davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); 59
67 } else { 60 ct->regs.ack = IRQ_REG0_OFFSET;
68 l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); 61 ct->regs.mask = IRQ_ENT_REG0_OFFSET;
69 l &= ~mask; 62 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
70 davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); 63 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
71 }
72}
73
74/* Enable interrupt */
75static void davinci_unmask_irq(struct irq_data *d)
76{
77 unsigned int mask;
78 u32 l;
79
80 mask = 1 << IRQ_BIT(d->irq);
81
82 if (d->irq > 31) {
83 l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
84 l |= mask;
85 davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
86 } else {
87 l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
88 l |= mask;
89 davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
90 }
91} 64}
92 65
93/* EOI interrupt */
94static void davinci_ack_irq(struct irq_data *d)
95{
96 unsigned int mask;
97
98 mask = 1 << IRQ_BIT(d->irq);
99
100 if (d->irq > 31)
101 davinci_irq_writel(mask, IRQ_REG1_OFFSET);
102 else
103 davinci_irq_writel(mask, IRQ_REG0_OFFSET);
104}
105
106static struct irq_chip davinci_irq_chip_0 = {
107 .name = "AINTC",
108 .irq_ack = davinci_ack_irq,
109 .irq_mask = davinci_mask_irq,
110 .irq_unmask = davinci_unmask_irq,
111};
112
113/* ARM Interrupt Controller Initialization */ 66/* ARM Interrupt Controller Initialization */
114void __init davinci_irq_init(void) 67void __init davinci_irq_init(void)
115{ 68{
116 unsigned i; 69 unsigned i, j;
117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; 70 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
118 71
119 davinci_intc_type = DAVINCI_INTC_TYPE_AINTC; 72 davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
@@ -144,7 +97,6 @@ void __init davinci_irq_init(void)
144 davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); 97 davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
145 98
146 for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { 99 for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
147 unsigned j;
148 u32 pri; 100 u32 pri;
149 101
150 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) 102 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
@@ -152,13 +104,8 @@ void __init davinci_irq_init(void)
152 davinci_irq_writel(pri, i); 104 davinci_irq_writel(pri, i);
153 } 105 }
154 106
155 /* set up genirq dispatch for ARM INTC */ 107 for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
156 for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { 108 davinci_alloc_gc(davinci_intc_base + j, i, 32);
157 irq_set_chip(i, &davinci_irq_chip_0); 109
158 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 110 irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
159 if (i != IRQ_TINT1_TINT34)
160 irq_set_handler(i, handle_edge_irq);
161 else
162 irq_set_handler(i, handle_level_irq);
163 }
164} 111}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e06a88f1f81d..5ed51b84c1b2 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,10 +16,8 @@
16#include <linux/serial_8250.h> 16#include <linux/serial_8250.h>
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/mbus.h> 18#include <linux/mbus.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/mv643xx_i2c.h>
21#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
22#include <linux/spi/orion_spi.h> 20#include <linux/serial_8250.h>
23#include <linux/gpio.h> 21#include <linux/gpio.h>
24#include <asm/page.h> 22#include <asm/page.h>
25#include <asm/setup.h> 23#include <asm/setup.h>
@@ -32,11 +30,12 @@
32#include <mach/bridge-regs.h> 30#include <mach/bridge-regs.h>
33#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
34#include <linux/irq.h> 32#include <linux/irq.h>
35#include <plat/mv_xor.h>
36#include <plat/ehci-orion.h>
37#include <plat/time.h> 33#include <plat/time.h>
34#include <plat/common.h>
38#include "common.h" 35#include "common.h"
39 36
37static int get_tclk(void);
38
40/***************************************************************************** 39/*****************************************************************************
41 * I/O Address Mapping 40 * I/O Address Mapping
42 ****************************************************************************/ 41 ****************************************************************************/
@@ -70,463 +69,106 @@ void __init dove_map_io(void)
70} 69}
71 70
72/***************************************************************************** 71/*****************************************************************************
73 * EHCI
74 ****************************************************************************/
75static struct orion_ehci_data dove_ehci_data = {
76 .dram = &dove_mbus_dram_info,
77 .phy_version = EHCI_PHY_NA,
78};
79
80static u64 ehci_dmamask = DMA_BIT_MASK(32);
81
82/*****************************************************************************
83 * EHCI0 72 * EHCI0
84 ****************************************************************************/ 73 ****************************************************************************/
85static struct resource dove_ehci0_resources[] = {
86 {
87 .start = DOVE_USB0_PHYS_BASE,
88 .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .start = IRQ_DOVE_USB0,
92 .end = IRQ_DOVE_USB0,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device dove_ehci0 = {
98 .name = "orion-ehci",
99 .id = 0,
100 .dev = {
101 .dma_mask = &ehci_dmamask,
102 .coherent_dma_mask = DMA_BIT_MASK(32),
103 .platform_data = &dove_ehci_data,
104 },
105 .resource = dove_ehci0_resources,
106 .num_resources = ARRAY_SIZE(dove_ehci0_resources),
107};
108
109void __init dove_ehci0_init(void) 74void __init dove_ehci0_init(void)
110{ 75{
111 platform_device_register(&dove_ehci0); 76 orion_ehci_init(&dove_mbus_dram_info,
77 DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
112} 78}
113 79
114/***************************************************************************** 80/*****************************************************************************
115 * EHCI1 81 * EHCI1
116 ****************************************************************************/ 82 ****************************************************************************/
117static struct resource dove_ehci1_resources[] = {
118 {
119 .start = DOVE_USB1_PHYS_BASE,
120 .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
121 .flags = IORESOURCE_MEM,
122 }, {
123 .start = IRQ_DOVE_USB1,
124 .end = IRQ_DOVE_USB1,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device dove_ehci1 = {
130 .name = "orion-ehci",
131 .id = 1,
132 .dev = {
133 .dma_mask = &ehci_dmamask,
134 .coherent_dma_mask = DMA_BIT_MASK(32),
135 .platform_data = &dove_ehci_data,
136 },
137 .resource = dove_ehci1_resources,
138 .num_resources = ARRAY_SIZE(dove_ehci1_resources),
139};
140
141void __init dove_ehci1_init(void) 83void __init dove_ehci1_init(void)
142{ 84{
143 platform_device_register(&dove_ehci1); 85 orion_ehci_1_init(&dove_mbus_dram_info,
86 DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
144} 87}
145 88
146/***************************************************************************** 89/*****************************************************************************
147 * GE00 90 * GE00
148 ****************************************************************************/ 91 ****************************************************************************/
149struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
150 .t_clk = 0,
151 .dram = &dove_mbus_dram_info,
152};
153
154static struct resource dove_ge00_shared_resources[] = {
155 {
156 .name = "ge00 base",
157 .start = DOVE_GE00_PHYS_BASE + 0x2000,
158 .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device dove_ge00_shared = {
164 .name = MV643XX_ETH_SHARED_NAME,
165 .id = 0,
166 .dev = {
167 .platform_data = &dove_ge00_shared_data,
168 },
169 .num_resources = 1,
170 .resource = dove_ge00_shared_resources,
171};
172
173static struct resource dove_ge00_resources[] = {
174 {
175 .name = "ge00 irq",
176 .start = IRQ_DOVE_GE00_SUM,
177 .end = IRQ_DOVE_GE00_SUM,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182static struct platform_device dove_ge00 = {
183 .name = MV643XX_ETH_NAME,
184 .id = 0,
185 .num_resources = 1,
186 .resource = dove_ge00_resources,
187 .dev = {
188 .coherent_dma_mask = 0xffffffff,
189 },
190};
191
192void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 92void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
193{ 93{
194 eth_data->shared = &dove_ge00_shared; 94 orion_ge00_init(eth_data, &dove_mbus_dram_info,
195 dove_ge00.dev.platform_data = eth_data; 95 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
196 96 0, get_tclk());
197 platform_device_register(&dove_ge00_shared);
198 platform_device_register(&dove_ge00);
199} 97}
200 98
201/***************************************************************************** 99/*****************************************************************************
202 * SoC RTC 100 * SoC RTC
203 ****************************************************************************/ 101 ****************************************************************************/
204static struct resource dove_rtc_resource[] = {
205 {
206 .start = DOVE_RTC_PHYS_BASE,
207 .end = DOVE_RTC_PHYS_BASE + 32 - 1,
208 .flags = IORESOURCE_MEM,
209 }, {
210 .start = IRQ_DOVE_RTC,
211 .flags = IORESOURCE_IRQ,
212 }
213};
214
215void __init dove_rtc_init(void) 102void __init dove_rtc_init(void)
216{ 103{
217 platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); 104 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
218} 105}
219 106
220/***************************************************************************** 107/*****************************************************************************
221 * SATA 108 * SATA
222 ****************************************************************************/ 109 ****************************************************************************/
223static struct resource dove_sata_resources[] = {
224 {
225 .name = "sata base",
226 .start = DOVE_SATA_PHYS_BASE,
227 .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .name = "sata irq",
231 .start = IRQ_DOVE_SATA,
232 .end = IRQ_DOVE_SATA,
233 .flags = IORESOURCE_IRQ,
234 },
235};
236
237static struct platform_device dove_sata = {
238 .name = "sata_mv",
239 .id = 0,
240 .dev = {
241 .coherent_dma_mask = DMA_BIT_MASK(32),
242 },
243 .num_resources = ARRAY_SIZE(dove_sata_resources),
244 .resource = dove_sata_resources,
245};
246
247void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 110void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
248{ 111{
249 sata_data->dram = &dove_mbus_dram_info; 112 orion_sata_init(sata_data, &dove_mbus_dram_info,
250 dove_sata.dev.platform_data = sata_data; 113 DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
251 platform_device_register(&dove_sata); 114
252} 115}
253 116
254/***************************************************************************** 117/*****************************************************************************
255 * UART0 118 * UART0
256 ****************************************************************************/ 119 ****************************************************************************/
257static struct plat_serial8250_port dove_uart0_data[] = {
258 {
259 .mapbase = DOVE_UART0_PHYS_BASE,
260 .membase = (char *)DOVE_UART0_VIRT_BASE,
261 .irq = IRQ_DOVE_UART_0,
262 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
263 .iotype = UPIO_MEM,
264 .regshift = 2,
265 .uartclk = 0,
266 }, {
267 },
268};
269
270static struct resource dove_uart0_resources[] = {
271 {
272 .start = DOVE_UART0_PHYS_BASE,
273 .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
274 .flags = IORESOURCE_MEM,
275 }, {
276 .start = IRQ_DOVE_UART_0,
277 .end = IRQ_DOVE_UART_0,
278 .flags = IORESOURCE_IRQ,
279 },
280};
281
282static struct platform_device dove_uart0 = {
283 .name = "serial8250",
284 .id = 0,
285 .dev = {
286 .platform_data = dove_uart0_data,
287 },
288 .resource = dove_uart0_resources,
289 .num_resources = ARRAY_SIZE(dove_uart0_resources),
290};
291
292void __init dove_uart0_init(void) 120void __init dove_uart0_init(void)
293{ 121{
294 platform_device_register(&dove_uart0); 122 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
123 IRQ_DOVE_UART_0, get_tclk());
295} 124}
296 125
297/***************************************************************************** 126/*****************************************************************************
298 * UART1 127 * UART1
299 ****************************************************************************/ 128 ****************************************************************************/
300static struct plat_serial8250_port dove_uart1_data[] = {
301 {
302 .mapbase = DOVE_UART1_PHYS_BASE,
303 .membase = (char *)DOVE_UART1_VIRT_BASE,
304 .irq = IRQ_DOVE_UART_1,
305 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
306 .iotype = UPIO_MEM,
307 .regshift = 2,
308 .uartclk = 0,
309 }, {
310 },
311};
312
313static struct resource dove_uart1_resources[] = {
314 {
315 .start = DOVE_UART1_PHYS_BASE,
316 .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
317 .flags = IORESOURCE_MEM,
318 }, {
319 .start = IRQ_DOVE_UART_1,
320 .end = IRQ_DOVE_UART_1,
321 .flags = IORESOURCE_IRQ,
322 },
323};
324
325static struct platform_device dove_uart1 = {
326 .name = "serial8250",
327 .id = 1,
328 .dev = {
329 .platform_data = dove_uart1_data,
330 },
331 .resource = dove_uart1_resources,
332 .num_resources = ARRAY_SIZE(dove_uart1_resources),
333};
334
335void __init dove_uart1_init(void) 129void __init dove_uart1_init(void)
336{ 130{
337 platform_device_register(&dove_uart1); 131 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
132 IRQ_DOVE_UART_1, get_tclk());
338} 133}
339 134
340/***************************************************************************** 135/*****************************************************************************
341 * UART2 136 * UART2
342 ****************************************************************************/ 137 ****************************************************************************/
343static struct plat_serial8250_port dove_uart2_data[] = {
344 {
345 .mapbase = DOVE_UART2_PHYS_BASE,
346 .membase = (char *)DOVE_UART2_VIRT_BASE,
347 .irq = IRQ_DOVE_UART_2,
348 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
349 .iotype = UPIO_MEM,
350 .regshift = 2,
351 .uartclk = 0,
352 }, {
353 },
354};
355
356static struct resource dove_uart2_resources[] = {
357 {
358 .start = DOVE_UART2_PHYS_BASE,
359 .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
360 .flags = IORESOURCE_MEM,
361 }, {
362 .start = IRQ_DOVE_UART_2,
363 .end = IRQ_DOVE_UART_2,
364 .flags = IORESOURCE_IRQ,
365 },
366};
367
368static struct platform_device dove_uart2 = {
369 .name = "serial8250",
370 .id = 2,
371 .dev = {
372 .platform_data = dove_uart2_data,
373 },
374 .resource = dove_uart2_resources,
375 .num_resources = ARRAY_SIZE(dove_uart2_resources),
376};
377
378void __init dove_uart2_init(void) 138void __init dove_uart2_init(void)
379{ 139{
380 platform_device_register(&dove_uart2); 140 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
141 IRQ_DOVE_UART_2, get_tclk());
381} 142}
382 143
383/***************************************************************************** 144/*****************************************************************************
384 * UART3 145 * UART3
385 ****************************************************************************/ 146 ****************************************************************************/
386static struct plat_serial8250_port dove_uart3_data[] = {
387 {
388 .mapbase = DOVE_UART3_PHYS_BASE,
389 .membase = (char *)DOVE_UART3_VIRT_BASE,
390 .irq = IRQ_DOVE_UART_3,
391 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
392 .iotype = UPIO_MEM,
393 .regshift = 2,
394 .uartclk = 0,
395 }, {
396 },
397};
398
399static struct resource dove_uart3_resources[] = {
400 {
401 .start = DOVE_UART3_PHYS_BASE,
402 .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
403 .flags = IORESOURCE_MEM,
404 }, {
405 .start = IRQ_DOVE_UART_3,
406 .end = IRQ_DOVE_UART_3,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct platform_device dove_uart3 = {
412 .name = "serial8250",
413 .id = 3,
414 .dev = {
415 .platform_data = dove_uart3_data,
416 },
417 .resource = dove_uart3_resources,
418 .num_resources = ARRAY_SIZE(dove_uart3_resources),
419};
420
421void __init dove_uart3_init(void) 147void __init dove_uart3_init(void)
422{ 148{
423 platform_device_register(&dove_uart3); 149 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
150 IRQ_DOVE_UART_3, get_tclk());
424} 151}
425 152
426/***************************************************************************** 153/*****************************************************************************
427 * SPI0 154 * SPI
428 ****************************************************************************/ 155 ****************************************************************************/
429static struct orion_spi_info dove_spi0_data = {
430 .tclk = 0,
431};
432
433static struct resource dove_spi0_resources[] = {
434 {
435 .start = DOVE_SPI0_PHYS_BASE,
436 .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
437 .flags = IORESOURCE_MEM,
438 }, {
439 .start = IRQ_DOVE_SPI0,
440 .end = IRQ_DOVE_SPI0,
441 .flags = IORESOURCE_IRQ,
442 },
443};
444
445static struct platform_device dove_spi0 = {
446 .name = "orion_spi",
447 .id = 0,
448 .resource = dove_spi0_resources,
449 .dev = {
450 .platform_data = &dove_spi0_data,
451 },
452 .num_resources = ARRAY_SIZE(dove_spi0_resources),
453};
454
455void __init dove_spi0_init(void) 156void __init dove_spi0_init(void)
456{ 157{
457 platform_device_register(&dove_spi0); 158 orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
458} 159}
459 160
460/*****************************************************************************
461 * SPI1
462 ****************************************************************************/
463static struct orion_spi_info dove_spi1_data = {
464 .tclk = 0,
465};
466
467static struct resource dove_spi1_resources[] = {
468 {
469 .start = DOVE_SPI1_PHYS_BASE,
470 .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
471 .flags = IORESOURCE_MEM,
472 }, {
473 .start = IRQ_DOVE_SPI1,
474 .end = IRQ_DOVE_SPI1,
475 .flags = IORESOURCE_IRQ,
476 },
477};
478
479static struct platform_device dove_spi1 = {
480 .name = "orion_spi",
481 .id = 1,
482 .resource = dove_spi1_resources,
483 .dev = {
484 .platform_data = &dove_spi1_data,
485 },
486 .num_resources = ARRAY_SIZE(dove_spi1_resources),
487};
488
489void __init dove_spi1_init(void) 161void __init dove_spi1_init(void)
490{ 162{
491 platform_device_register(&dove_spi1); 163 orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
492} 164}
493 165
494/***************************************************************************** 166/*****************************************************************************
495 * I2C 167 * I2C
496 ****************************************************************************/ 168 ****************************************************************************/
497static struct mv64xxx_i2c_pdata dove_i2c_data = {
498 .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
499 .freq_n = 3,
500 .timeout = 1000, /* Default timeout of 1 second */
501};
502
503static struct resource dove_i2c_resources[] = {
504 {
505 .name = "i2c base",
506 .start = DOVE_I2C_PHYS_BASE,
507 .end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
508 .flags = IORESOURCE_MEM,
509 }, {
510 .name = "i2c irq",
511 .start = IRQ_DOVE_I2C,
512 .end = IRQ_DOVE_I2C,
513 .flags = IORESOURCE_IRQ,
514 },
515};
516
517static struct platform_device dove_i2c = {
518 .name = MV64XXX_I2C_CTLR_NAME,
519 .id = 0,
520 .num_resources = ARRAY_SIZE(dove_i2c_resources),
521 .resource = dove_i2c_resources,
522 .dev = {
523 .platform_data = &dove_i2c_data,
524 },
525};
526
527void __init dove_i2c_init(void) 169void __init dove_i2c_init(void)
528{ 170{
529 platform_device_register(&dove_i2c); 171 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
530} 172}
531 173
532/***************************************************************************** 174/*****************************************************************************
@@ -554,208 +196,22 @@ struct sys_timer dove_timer = {
554}; 196};
555 197
556/***************************************************************************** 198/*****************************************************************************
557 * XOR
558 ****************************************************************************/
559static struct mv_xor_platform_shared_data dove_xor_shared_data = {
560 .dram = &dove_mbus_dram_info,
561};
562
563/*****************************************************************************
564 * XOR 0 199 * XOR 0
565 ****************************************************************************/ 200 ****************************************************************************/
566static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
567
568static struct resource dove_xor0_shared_resources[] = {
569 {
570 .name = "xor 0 low",
571 .start = DOVE_XOR0_PHYS_BASE,
572 .end = DOVE_XOR0_PHYS_BASE + 0xff,
573 .flags = IORESOURCE_MEM,
574 }, {
575 .name = "xor 0 high",
576 .start = DOVE_XOR0_HIGH_PHYS_BASE,
577 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
578 .flags = IORESOURCE_MEM,
579 },
580};
581
582static struct platform_device dove_xor0_shared = {
583 .name = MV_XOR_SHARED_NAME,
584 .id = 0,
585 .dev = {
586 .platform_data = &dove_xor_shared_data,
587 },
588 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
589 .resource = dove_xor0_shared_resources,
590};
591
592static struct resource dove_xor00_resources[] = {
593 [0] = {
594 .start = IRQ_DOVE_XOR_00,
595 .end = IRQ_DOVE_XOR_00,
596 .flags = IORESOURCE_IRQ,
597 },
598};
599
600static struct mv_xor_platform_data dove_xor00_data = {
601 .shared = &dove_xor0_shared,
602 .hw_id = 0,
603 .pool_size = PAGE_SIZE,
604};
605
606static struct platform_device dove_xor00_channel = {
607 .name = MV_XOR_NAME,
608 .id = 0,
609 .num_resources = ARRAY_SIZE(dove_xor00_resources),
610 .resource = dove_xor00_resources,
611 .dev = {
612 .dma_mask = &dove_xor0_dmamask,
613 .coherent_dma_mask = DMA_BIT_MASK(64),
614 .platform_data = &dove_xor00_data,
615 },
616};
617
618static struct resource dove_xor01_resources[] = {
619 [0] = {
620 .start = IRQ_DOVE_XOR_01,
621 .end = IRQ_DOVE_XOR_01,
622 .flags = IORESOURCE_IRQ,
623 },
624};
625
626static struct mv_xor_platform_data dove_xor01_data = {
627 .shared = &dove_xor0_shared,
628 .hw_id = 1,
629 .pool_size = PAGE_SIZE,
630};
631
632static struct platform_device dove_xor01_channel = {
633 .name = MV_XOR_NAME,
634 .id = 1,
635 .num_resources = ARRAY_SIZE(dove_xor01_resources),
636 .resource = dove_xor01_resources,
637 .dev = {
638 .dma_mask = &dove_xor0_dmamask,
639 .coherent_dma_mask = DMA_BIT_MASK(64),
640 .platform_data = &dove_xor01_data,
641 },
642};
643
644void __init dove_xor0_init(void) 201void __init dove_xor0_init(void)
645{ 202{
646 platform_device_register(&dove_xor0_shared); 203 orion_xor0_init(&dove_mbus_dram_info,
647 204 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
648 /* 205 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
649 * two engines can't do memset simultaneously, this limitation
650 * satisfied by removing memset support from one of the engines.
651 */
652 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
653 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
654 platform_device_register(&dove_xor00_channel);
655
656 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
657 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
658 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
659 platform_device_register(&dove_xor01_channel);
660} 206}
661 207
662/***************************************************************************** 208/*****************************************************************************
663 * XOR 1 209 * XOR 1
664 ****************************************************************************/ 210 ****************************************************************************/
665static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
666
667static struct resource dove_xor1_shared_resources[] = {
668 {
669 .name = "xor 0 low",
670 .start = DOVE_XOR1_PHYS_BASE,
671 .end = DOVE_XOR1_PHYS_BASE + 0xff,
672 .flags = IORESOURCE_MEM,
673 }, {
674 .name = "xor 0 high",
675 .start = DOVE_XOR1_HIGH_PHYS_BASE,
676 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
677 .flags = IORESOURCE_MEM,
678 },
679};
680
681static struct platform_device dove_xor1_shared = {
682 .name = MV_XOR_SHARED_NAME,
683 .id = 1,
684 .dev = {
685 .platform_data = &dove_xor_shared_data,
686 },
687 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
688 .resource = dove_xor1_shared_resources,
689};
690
691static struct resource dove_xor10_resources[] = {
692 [0] = {
693 .start = IRQ_DOVE_XOR_10,
694 .end = IRQ_DOVE_XOR_10,
695 .flags = IORESOURCE_IRQ,
696 },
697};
698
699static struct mv_xor_platform_data dove_xor10_data = {
700 .shared = &dove_xor1_shared,
701 .hw_id = 0,
702 .pool_size = PAGE_SIZE,
703};
704
705static struct platform_device dove_xor10_channel = {
706 .name = MV_XOR_NAME,
707 .id = 2,
708 .num_resources = ARRAY_SIZE(dove_xor10_resources),
709 .resource = dove_xor10_resources,
710 .dev = {
711 .dma_mask = &dove_xor1_dmamask,
712 .coherent_dma_mask = DMA_BIT_MASK(64),
713 .platform_data = &dove_xor10_data,
714 },
715};
716
717static struct resource dove_xor11_resources[] = {
718 [0] = {
719 .start = IRQ_DOVE_XOR_11,
720 .end = IRQ_DOVE_XOR_11,
721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct mv_xor_platform_data dove_xor11_data = {
726 .shared = &dove_xor1_shared,
727 .hw_id = 1,
728 .pool_size = PAGE_SIZE,
729};
730
731static struct platform_device dove_xor11_channel = {
732 .name = MV_XOR_NAME,
733 .id = 3,
734 .num_resources = ARRAY_SIZE(dove_xor11_resources),
735 .resource = dove_xor11_resources,
736 .dev = {
737 .dma_mask = &dove_xor1_dmamask,
738 .coherent_dma_mask = DMA_BIT_MASK(64),
739 .platform_data = &dove_xor11_data,
740 },
741};
742
743void __init dove_xor1_init(void) 211void __init dove_xor1_init(void)
744{ 212{
745 platform_device_register(&dove_xor1_shared); 213 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
746 214 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
747 /*
748 * two engines can't do memset simultaneously, this limitation
749 * satisfied by removing memset support from one of the engines.
750 */
751 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
752 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
753 platform_device_register(&dove_xor10_channel);
754
755 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
756 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
757 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
758 platform_device_register(&dove_xor11_channel);
759} 215}
760 216
761/***************************************************************************** 217/*****************************************************************************
@@ -833,14 +289,6 @@ void __init dove_init(void)
833#endif 289#endif
834 dove_setup_cpu_mbus(); 290 dove_setup_cpu_mbus();
835 291
836 dove_ge00_shared_data.t_clk = tclk;
837 dove_uart0_data[0].uartclk = tclk;
838 dove_uart1_data[0].uartclk = tclk;
839 dove_uart2_data[0].uartclk = tclk;
840 dove_uart3_data[0].uartclk = tclk;
841 dove_spi0_data.tclk = tclk;
842 dove_spi1_data.tclk = tclk;
843
844 /* internal devices that every board has */ 292 /* internal devices that every board has */
845 dove_rtc_init(); 293 dove_rtc_init();
846 dove_xor0_init(); 294 dove_xor0_init();
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index c66c76346904..51e0e411c9cb 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -11,24 +11,17 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/gpio.h> 12#include <linux/gpio.h>
13#include <linux/io.h> 13#include <linux/io.h>
14 14#include <plat/mpp.h>
15#include <mach/dove.h> 15#include <mach/dove.h>
16
17#include "mpp.h" 16#include "mpp.h"
18 17
19#define MPP_NR_REGS 4
20#define MPP_CTRL(i) ((i) == 3 ? \
21 DOVE_MPP_CTRL4_VIRT_BASE : \
22 DOVE_MPP_VIRT_BASE + (i) * 4)
23#define PMU_SIG_REGS 2
24#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
25
26struct dove_mpp_grp { 18struct dove_mpp_grp {
27 int start; 19 int start;
28 int end; 20 int end;
29}; 21};
30 22
31static struct dove_mpp_grp dove_mpp_grp[] = { 23/* Map a group to a range of GPIO pins in that group */
24static const struct dove_mpp_grp dove_mpp_grp[] = {
32 [MPP_24_39] = { 25 [MPP_24_39] = {
33 .start = 24, 26 .start = 24,
34 .end = 39, 27 .end = 39,
@@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
38 .end = 45, 31 .end = 45,
39 }, 32 },
40 [MPP_46_51] = { 33 [MPP_46_51] = {
41 .start = 40, 34 .start = 46,
42 .end = 45, 35 .end = 51,
43 }, 36 },
44 [MPP_58_61] = { 37 [MPP_58_61] = {
45 .start = 58, 38 .start = 58,
@@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
51 }, 44 },
52}; 45};
53 46
47/* Enable gpio for a range of pins. mode should be a combination of
48 GPIO_OUTPUT_OK | GPIO_INPUT_OK */
54static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) 49static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
55{ 50{
56 int i; 51 int i;
@@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
59 orion_gpio_set_valid(i, gpio_mode); 54 orion_gpio_set_valid(i, gpio_mode);
60} 55}
61 56
57/* Dump all the extra MPP registers. The platform code will dump the
58 registers for pins 0-23. */
62static void dove_mpp_dump_regs(void) 59static void dove_mpp_dump_regs(void)
63{ 60{
64#ifdef DEBUG 61 pr_debug("PMU_CTRL4_CTRL: %08x\n",
65 int i; 62 readl(DOVE_MPP_CTRL4_VIRT_BASE));
66 63
67 pr_debug("MPP_CTRL regs:"); 64 pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
68 for (i = 0; i < MPP_NR_REGS; i++) 65 readl(DOVE_PMU_MPP_GENERAL_CTRL));
69 printk(" %08x", readl(MPP_CTRL(i)));
70 printk("\n");
71 66
72 pr_debug("PMU_SIG_CTRL regs:");
73 for (i = 0; i < PMU_SIG_REGS; i++)
74 printk(" %08x", readl(PMU_SIG_CTRL(i)));
75 printk("\n");
76
77 pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
78 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); 67 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
79#endif
80} 68}
81 69
82static void dove_mpp_cfg_nfc(int sel) 70static void dove_mpp_cfg_nfc(int sel)
@@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel)
92 80
93static void dove_mpp_cfg_au1(int sel) 81static void dove_mpp_cfg_au1(int sel)
94{ 82{
95 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 83 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
96 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); 84 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
97 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); 85 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
98 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); 86 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
@@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
128 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); 116 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
129} 117}
130 118
131static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) 119/* Configure the group registers, enabling GPIO if sel indicates the
132{ 120 pin is to be used for GPIO */
133 int start = dove_mpp_grp[num].start; 121static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
134 int end = dove_mpp_grp[num].end;
135 int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
136
137 *mpp_ctrl &= ~(0x1 << num);
138 *mpp_ctrl |= sel << num;
139
140 dove_mpp_gpio_mode(start, end, gpio_mode);
141}
142
143void __init dove_mpp_conf(unsigned int *mpp_list)
144{ 122{
145 u32 mpp_ctrl[MPP_NR_REGS]; 123 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
146 u32 pmu_mpp_ctrl = 0; 124 int gpio_mode;
147 u32 pmu_sig_ctrl[PMU_SIG_REGS];
148 int i;
149
150 for (i = 0; i < MPP_NR_REGS; i++)
151 mpp_ctrl[i] = readl(MPP_CTRL(i));
152
153 for (i = 0; i < PMU_SIG_REGS; i++)
154 pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
155
156 pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
157 125
158 dove_mpp_dump_regs(); 126 for ( ; *mpp_grp_list; mpp_grp_list++) {
159 127 unsigned int num = MPP_NUM(*mpp_grp_list);
160 for ( ; *mpp_list != MPP_END; mpp_list++) { 128 unsigned int sel = MPP_SEL(*mpp_grp_list);
161 unsigned int num = MPP_NUM(*mpp_list);
162 unsigned int sel = MPP_SEL(*mpp_list);
163 int shift, gpio_mode;
164
165 if (num > MPP_MAX) {
166 pr_err("dove: invalid MPP number (%u)\n", num);
167 continue;
168 }
169
170 if (*mpp_list & MPP_NFC_MASK) {
171 dove_mpp_cfg_nfc(sel);
172 continue;
173 }
174 129
175 if (*mpp_list & MPP_AU1_MASK) { 130 if (num > MPP_GRP_MAX) {
176 dove_mpp_cfg_au1(sel); 131 pr_err("dove: invalid MPP GRP number (%u)\n", num);
177 continue; 132 continue;
178 } 133 }
179 134
180 if (*mpp_list & MPP_GRP_MASK) { 135 mpp_ctrl4 &= ~(0x1 << num);
181 dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]); 136 mpp_ctrl4 |= sel << num;
182 continue;
183 }
184
185 shift = (num & 7) << 2;
186 if (*mpp_list & MPP_PMU_MASK) {
187 pmu_mpp_ctrl |= (0x1 << num);
188 pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
189 pmu_sig_ctrl[num / 8] |= 0xf << shift;
190 gpio_mode = 0;
191 } else {
192 mpp_ctrl[num / 8] &= ~(0xf << shift);
193 mpp_ctrl[num / 8] |= sel << shift;
194 gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
195 }
196 137
197 orion_gpio_set_valid(num, gpio_mode); 138 gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
139 dove_mpp_gpio_mode(dove_mpp_grp[num].start,
140 dove_mpp_grp[num].end, gpio_mode);
198 } 141 }
142 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
143}
199 144
200 for (i = 0; i < MPP_NR_REGS; i++) 145/* Configure the various MPP pins on Dove */
201 writel(mpp_ctrl[i], MPP_CTRL(i)); 146void __init dove_mpp_conf(unsigned int *mpp_list,
147 unsigned int *mpp_grp_list,
148 unsigned int grp_au1_52_57,
149 unsigned int grp_nfc_64_71)
150{
151 dove_mpp_dump_regs();
202 152
203 for (i = 0; i < PMU_SIG_REGS; i++) 153 /* Use platform code for pins 0-23 */
204 writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i)); 154 orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
205 155
206 writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL); 156 dove_mpp_conf_grp(mpp_grp_list);
157 dove_mpp_cfg_au1(grp_au1_52_57);
158 dove_mpp_cfg_nfc(grp_nfc_64_71);
207 159
208 dove_mpp_dump_regs(); 160 dove_mpp_dump_regs();
209} 161}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
index 2a43ce413b15..fbec7c52bfac 100644
--- a/arch/arm/mach-dove/mpp.h
+++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
1#ifndef __ARCH_DOVE_MPP_CODED_H 1#ifndef __ARCH_DOVE_MPP_CODED_H
2#define __ARCH_DOVE_MPP_CODED_H 2#define __ARCH_DOVE_MPP_CODED_H
3 3
4#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \ 4#define MPP(_num, _sel, _in, _out) ( \
5/* MPP/group number */ ((_num) & 0xff) | \ 5 /* MPP number */ ((_num) & 0xff) | \
6/* MPP select value */ (((_mode) & 0xf) << 8) | \ 6 /* MPP select value */ (((_sel) & 0xf) << 8) | \
7/* MPP PMU */ ((!!(_pmu)) << 12) | \ 7 /* may be input signal */ ((!!(_in)) << 12) | \
8/* group flag */ ((!!(_grp)) << 13) | \ 8 /* may be output signal */ ((!!(_out)) << 13))
9/* AU1 flag */ ((!!(_au1)) << 14) | \ 9
10/* NFCE flag */ ((!!(_nfc)) << 15)) 10#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
11 11#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
12#define MPP_MAX 71 12#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
13 13#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
14#define MPP_NUM(x) ((x) & 0xff) 14
15#define MPP_SEL(x) (((x) >> 8) & 0xf) 15#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
16 16#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
17#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0) 17#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
18#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0) 18#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
19#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0) 19
20#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1) 20#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
21 21#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
22#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1) 22#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
23 23#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
24#define MPP_PMU_DRIVE_0 0x1 24#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
25#define MPP_PMU_DRIVE_1 0x2 25
26#define MPP_PMU_SDI 0x3 26#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
27#define MPP_PMU_CPU_PWRDWN 0x4 27#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
28#define MPP_PMU_STBY_PWRDWN 0x5 28#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
29#define MPP_PMU_CORE_PWR_GOOD 0x8 29#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
30#define MPP_PMU_BAT_FAULT 0xa 30#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
31#define MPP_PMU_EXT0_WU 0xb 31#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
32#define MPP_PMU_EXT1_WU 0xc 32
33#define MPP_PMU_EXT2_WU 0xd 33#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
34#define MPP_PMU_BLINK 0xe 34#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
35#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0) 35#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
36 36#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
37#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0) 37
38#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0) 38#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
39#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0) 39#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
40#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1) 40#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
41 41#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
42#define MPP0_GPIO0 MPP_PIN(0, 0x0) 42
43#define MPP0_UA2_RTSn MPP_PIN(0, 0x2) 43#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
44#define MPP0_SDIO0_CD MPP_PIN(0, 0x3) 44#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
45#define MPP0_LCD0_PWM MPP_PIN(0, 0xf) 45#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
46 46#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
47#define MPP1_GPIO1 MPP_PIN(1, 0x0) 47
48#define MPP1_UA2_CTSn MPP_PIN(1, 0x2) 48#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
49#define MPP1_SDIO0_WP MPP_PIN(1, 0x3) 49#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
50#define MPP1_LCD1_PWM MPP_PIN(1, 0xf) 50#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
51 51#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
52#define MPP2_GPIO2 MPP_PIN(2, 0x0) 52
53#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1) 53#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
54#define MPP2_UA2_TXD MPP_PIN(2, 0x2) 54#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
55#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3) 55
56#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4) 56#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
57 57#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
58#define MPP3_GPIO3 MPP_PIN(3, 0x0) 58
59#define MPP3_SATA_ACT MPP_PIN(3, 0x1) 59#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
60#define MPP3_UA2_RXD MPP_PIN(3, 0x2) 60#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
61#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3) 61
62#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4) 62#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
63#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf) 63#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
64 64#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
65#define MPP4_GPIO4 MPP_PIN(4, 0x0) 65#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
66#define MPP4_UA3_RTSn MPP_PIN(4, 0x2) 66#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
67#define MPP4_SDIO1_CD MPP_PIN(4, 0x3) 67#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
68#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4) 68
69 69#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
70#define MPP5_GPIO5 MPP_PIN(5, 0x0) 70#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
71#define MPP5_UA3_CTSn MPP_PIN(5, 0x2) 71#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
72#define MPP5_SDIO1_WP MPP_PIN(5, 0x3) 72#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
73#define MPP5_SPI_1_CS MPP_PIN(5, 0x4) 73#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
74 74
75#define MPP6_GPIO6 MPP_PIN(6, 0x0) 75#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
76#define MPP6_UA3_TXD MPP_PIN(6, 0x2) 76#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
77#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3) 77#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
78#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4) 78#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
79 79#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
80#define MPP7_GPIO7 MPP_PIN(7, 0x0) 80
81#define MPP7_UA3_RXD MPP_PIN(7, 0x2) 81#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
82#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3) 82#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
83#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4) 83#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
84 84#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
85#define MPP8_GPIO8 MPP_PIN(8, 0x0) 85
86#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1) 86#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
87 87#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
88#define MPP9_GPIO9 MPP_PIN(9, 0x0) 88#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
89#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5) 89#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
90 90
91#define MPP10_GPIO10 MPP_PIN(10, 0x0) 91#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
92#define MPP10_SSP_SCLK MPP_PIN(10, 0x5) 92#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
93 93#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
94#define MPP11_GPIO11 MPP_PIN(11, 0x0) 94#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
95#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1) 95#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
96#define MPP11_SATA_ACT MPP_PIN(11, 0x2) 96
97#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3) 97#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
98#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4) 98#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
99#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5) 99#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
100 100#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
101#define MPP12_GPIO12 MPP_PIN(12, 0x0) 101#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
102#define MPP12_SATA_ACT MPP_PIN(12, 0x1) 102#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
103#define MPP12_UA2_RTSn MPP_PIN(12, 0x2) 103
104#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3) 104#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
105#define MPP12_SDIO1_CD MPP_PIN(12, 0x4) 105#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
106 106#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
107#define MPP13_GPIO13 MPP_PIN(13, 0x0) 107#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
108#define MPP13_UA2_CTSn MPP_PIN(13, 0x2) 108#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
109#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3) 109
110#define MPP13_SDIO1WP MPP_PIN(13, 0x4) 110#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
111#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5) 111#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
112 112#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
113#define MPP14_GPIO14 MPP_PIN(14, 0x0) 113#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
114#define MPP14_UA2_TXD MPP_PIN(14, 0x2) 114
115#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4) 115#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
116#define MPP14_SSP_RXD MPP_PIN(14, 0x5) 116#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
117 117#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
118#define MPP15_GPIO15 MPP_PIN(15, 0x0) 118#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
119#define MPP15_UA2_RXD MPP_PIN(15, 0x2) 119#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
120#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4) 120#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
121#define MPP15_SSP_SFRM MPP_PIN(15, 0x5) 121
122 122#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
123#define MPP16_GPIO16 MPP_PIN(16, 0x0) 123#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
124#define MPP16_UA3_RTSn MPP_PIN(16, 0x2) 124#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
125#define MPP16_SDIO0_CD MPP_PIN(16, 0x3) 125#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
126#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4) 126#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
127#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5) 127#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
128 128#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
129#define MPP17_GPIO17 MPP_PIN(17, 0x0) 129
130#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1) 130#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
131#define MPP17_UA3_CTSn MPP_PIN(17, 0x2) 131#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
132#define MPP17_SDIO0_WP MPP_PIN(17, 0x3) 132#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
133#define MPP17_TW_SDA2 MPP_PIN(17, 0x4) 133#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
134#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5) 134#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
135 135#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
136#define MPP18_GPIO18 MPP_PIN(18, 0x0) 136#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
137#define MPP18_UA3_TXD MPP_PIN(18, 0x2) 137
138#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3) 138#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
139#define MPP18_LCD0_PWM MPP_PIN(18, 0x4) 139#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
140#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5) 140#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
141 141#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
142#define MPP19_GPIO19 MPP_PIN(19, 0x0) 142#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
143#define MPP19_UA3_RXD MPP_PIN(19, 0x2) 143#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
144#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3) 144
145#define MPP19_TW_SCK2 MPP_PIN(19, 0x4) 145#define MPP_MAX 23
146 146
147#define MPP20_GPIO20 MPP_PIN(20, 0x0) 147#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
148#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
149#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
150#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
151#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
152#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
153
154#define MPP21_GPIO21 MPP_PIN(21, 0x0)
155#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
156#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
157#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
158#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
159#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
160#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
161
162#define MPP22_GPIO22 MPP_PIN(22, 0x0)
163#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
164#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
165#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
166#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
167#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
168#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
169
170#define MPP23_GPIO23 MPP_PIN(23, 0x0)
171#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
172#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
173#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
174#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
175#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
176 148
177/* for MPP groups _num is a group index */ 149/* for MPP groups _num is a group index */
178enum dove_mpp_grp_idx { 150enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
181 MPP_46_51 = 1, 153 MPP_46_51 = 1,
182 MPP_58_61 = 5, 154 MPP_58_61 = 5,
183 MPP_62_63 = 4, 155 MPP_62_63 = 4,
156 MPP_GRP_MAX = 5,
184}; 157};
185 158
186#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1) 159#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
187#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0) 160#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
188 161
189#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1) 162#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
190#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0) 163#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
191 164
192#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1) 165#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
193#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0) 166#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
194 167
195#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1) 168#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
196#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0) 169#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
197 170
198#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1) 171#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
199#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0) 172#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
200 173
201/* The MPP[64:71] control differs from other groups */ 174/* The MPP[64:71] control differs from other groups */
202#define MPP64_71_GPO MPP_GRP_NFC(0x1) 175#define MPP_GRP_NFC_64_71_GPO 0x1
203#define MPP64_71_NFC MPP_GRP_NFC(0x0) 176#define MPP_GRP_NFC_64_71_NFC 0x0
204 177
205/* 178/*
206 * The MPP[52:57] functionality is encoded by 4 bits in different 179 * The MPP[52:57] functionality is encoded by 4 bits in different
207 * registers. The _num field in this case encodes those bits in 180 * registers. The _num field in this case encodes those bits in
208 * correspodence with Table 135 of 88AP510 Functional specification 181 * correspodence with Table 135 of 88AP510 Functional specification
209 */ 182 */
210#define MPP52_57_AU1 MPP_GRP_AU1(0x0) 183#define MPP_GRP_AU1_52_57_AU1 0x0
211#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2) 184#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
212#define MPP52_57_GPIO MPP_GRP_AU1(0xa) 185#define MPP_GRP_AU1_52_57_GPIO 0xa
213#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb) 186#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
214#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc) 187#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
215#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe) 188#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
216#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf) 189#define MPP_GRP_AU1_52_57_SSP_TW 0xf
217 190
218void dove_mpp_conf(unsigned int *mpp_list); 191void dove_mpp_conf(unsigned int *mpp_list,
192 unsigned int *mpp_grp_list,
193 unsigned int grp_au1_52_57,
194 unsigned int grp_nfc_64_71);
219 195
220#endif /* __ARCH_DOVE_MPP_CODED_H */ 196#endif /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index a5a9ff70b198..415dce37b88c 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -356,29 +356,6 @@ static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
356 return 0; 356 return 0;
357} 357}
358 358
359static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
360{
361 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
362 u8 data_reg, data_dir_reg;
363 int gpio, i;
364
365 data_reg = __raw_readb(ep93xx_chip->data_reg);
366 data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
367
368 gpio = ep93xx_chip->chip.base;
369 for (i = 0; i < chip->ngpio; i++, gpio++) {
370 int is_out = data_dir_reg & (1 << i);
371 int irq = gpio_to_irq(gpio);
372
373 seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n",
374 chip->label, i, gpio,
375 gpiochip_is_requested(chip, i) ? : "",
376 is_out ? "out" : "in ",
377 (data_reg & (1<< i)) ? "hi" : "lo",
378 (!is_out && irq>= 0) ? "(interrupt)" : "");
379 }
380}
381
382#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ 359#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
383 { \ 360 { \
384 .chip = { \ 361 .chip = { \
@@ -387,7 +364,6 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
387 .direction_output = ep93xx_gpio_direction_output, \ 364 .direction_output = ep93xx_gpio_direction_output, \
388 .get = ep93xx_gpio_get, \ 365 .get = ep93xx_gpio_get, \
389 .set = ep93xx_gpio_set, \ 366 .set = ep93xx_gpio_set, \
390 .dbg_show = ep93xx_gpio_dbg_show, \
391 .base = base_gpio, \ 367 .base = base_gpio, \
392 .ngpio = 8, \ 368 .ngpio = 8, \
393 }, \ 369 }, \
diff --git a/arch/arm/mach-exynos4/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h
deleted file mode 100644
index a463dcebcfd3..000000000000
--- a/arch/arm/mach-exynos4/include/mach/smp.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/smp.h
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/smp.h
4*/
5
6#ifndef ASM_ARCH_SMP_H
7#define ASM_ARCH_SMP_H __FILE__
8
9#include <asm/hardware/gic.h>
10
11/*
12 * We use IRQ1 as the IPI
13 */
14static inline void smp_cross_call(const struct cpumask *mask, int ipi)
15{
16 gic_raise_softirq(mask, ipi);
17}
18
19#endif
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index f488b66d6806..5a2758ab055e 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -59,8 +59,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
59 unsigned int cascade_irq, combiner_irq; 59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status; 60 unsigned long status;
61 61
62 /* primary controller ack'ing */ 62 chained_irq_enter(chip, desc);
63 chip->irq_ack(&desc->irq_data);
64 63
65 spin_lock(&irq_controller_lock); 64 spin_lock(&irq_controller_lock);
66 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); 65 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
79 generic_handle_irq(cascade_irq); 78 generic_handle_irq(cascade_irq);
80 79
81 out: 80 out:
82 /* primary controller unmasking */ 81 chained_irq_exit(chip, desc);
83 chip->irq_unmask(&desc->irq_data);
84} 82}
85 83
86static struct irq_chip combiner_chip = { 84static struct irq_chip combiner_chip = {
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 6d35878ec1aa..c5e65a02be8d 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23 23
24#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
25#include <asm/hardware/gic.h>
25#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
26#include <asm/unified.h> 27#include <asm/unified.h>
27 28
@@ -104,7 +105,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
104 * the boot monitor to read the system wide flags register, 105 * the boot monitor to read the system wide flags register,
105 * and branch to the address found there. 106 * and branch to the address found there.
106 */ 107 */
107 smp_cross_call(cpumask_of(cpu), 1); 108 gic_raise_softirq(cpumask_of(cpu), 1);
108 109
109 timeout = jiffies + (1 * HZ); 110 timeout = jiffies + (1 * HZ);
110 while (time_before(jiffies, timeout)) { 111 while (time_before(jiffies, timeout)) {
@@ -147,6 +148,8 @@ void __init smp_init_cpus(void)
147 148
148 for (i = 0; i < ncores; i++) 149 for (i = 0; i < ncores; i++)
149 set_cpu_possible(i, true); 150 set_cpu_possible(i, true);
151
152 set_smp_cross_call(gic_raise_softirq);
150} 153}
151 154
152void __init platform_smp_prepare_cpus(unsigned int max_cpus) 155void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
index 5483f61a8061..0efa26247235 100644
--- a/arch/arm/mach-gemini/include/mach/uncompress.h
+++ b/arch/arm/mach-gemini/include/mach/uncompress.h
@@ -16,7 +16,7 @@
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18 18
19static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE; 19static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE;
20 20
21/* 21/*
22 * The following code assumes the serial port has already been 22 * The following code assumes the serial port has already been
diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
index 9d3687651462..b0b3baec9acf 100644
--- a/arch/arm/mach-h720x/include/mach/memory.h
+++ b/arch/arm/mach-h720x/include/mach/memory.h
@@ -13,7 +13,6 @@
13 * There should not be more than (0xd0000000 - 0xc0000000) 13 * There should not be more than (0xd0000000 - 0xc0000000)
14 * bytes of RAM. 14 * bytes of RAM.
15 */ 15 */
16#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) 16#define ARM_DMA_ZONE_SIZE SZ_256M
17#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
18 17
19#endif 18#endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 56b930a13443..59c97a331136 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,5 +1,15 @@
1config IMX_HAVE_DMA_V1 1config IMX_HAVE_DMA_V1
2 bool 2 bool
3#
4# ARCH_MX31 and ARCH_MX35 are left for compatibility
5# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
6# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
7# more sensible) names are used: SOC_IMX31 and SOC_IMX35
8config ARCH_MX31
9 bool
10
11config ARCH_MX35
12 bool
3 13
4config SOC_IMX1 14config SOC_IMX1
5 bool 15 bool
@@ -31,6 +41,24 @@ config SOC_IMX27
31 select IMX_HAVE_IOMUX_V1 41 select IMX_HAVE_IOMUX_V1
32 select MXC_AVIC 42 select MXC_AVIC
33 43
44config SOC_IMX31
45 bool
46 select CPU_V6
47 select IMX_HAVE_PLATFORM_MXC_RNGA
48 select ARCH_MXC_AUDMUX_V2
49 select ARCH_MX31
50 select MXC_AVIC
51
52config SOC_IMX35
53 bool
54 select CPU_V6
55 select ARCH_MXC_IOMUX_V3
56 select ARCH_MXC_AUDMUX_V2
57 select HAVE_EPIT
58 select ARCH_MX35
59 select MXC_AVIC
60
61
34if ARCH_MX1 62if ARCH_MX1
35 63
36comment "MX1 platforms:" 64comment "MX1 platforms:"
@@ -40,6 +68,7 @@ config MACH_MXLADS
40config ARCH_MX1ADS 68config ARCH_MX1ADS
41 bool "MX1ADS platform" 69 bool "MX1ADS platform"
42 select MACH_MXLADS 70 select MACH_MXLADS
71 select SOC_IMX1
43 select IMX_HAVE_PLATFORM_IMX_I2C 72 select IMX_HAVE_PLATFORM_IMX_I2C
44 select IMX_HAVE_PLATFORM_IMX_UART 73 select IMX_HAVE_PLATFORM_IMX_UART
45 help 74 help
@@ -51,6 +80,13 @@ config MACH_SCB9328
51 help 80 help
52 Say Y here if you are using a Synertronixx scb9328 board 81 Say Y here if you are using a Synertronixx scb9328 board
53 82
83config MACH_APF9328
84 bool "APF9328"
85 select SOC_IMX1
86 select IMX_HAVE_PLATFORM_IMX_UART
87 help
88 Say Yes here if you are using the Armadeus APF9328 development board
89
54endif 90endif
55 91
56if ARCH_MX2 92if ARCH_MX2
@@ -129,6 +165,7 @@ choice
129 165
130config MACH_EUKREA_MBIMXSD25_BASEBOARD 166config MACH_EUKREA_MBIMXSD25_BASEBOARD
131 bool "Eukrea MBIMXSD development board" 167 bool "Eukrea MBIMXSD development board"
168 select IMX_HAVE_PLATFORM_GPIO_KEYS
132 select IMX_HAVE_PLATFORM_IMX_SSI 169 select IMX_HAVE_PLATFORM_IMX_SSI
133 help 170 help
134 This adds board specific devices that can be found on Eukrea's 171 This adds board specific devices that can be found on Eukrea's
@@ -254,6 +291,7 @@ config MACH_MX27_3DS
254config MACH_IMX27_VISSTRIM_M10 291config MACH_IMX27_VISSTRIM_M10
255 bool "Vista Silicon i.MX27 Visstrim_m10" 292 bool "Vista Silicon i.MX27 Visstrim_m10"
256 select SOC_IMX27 293 select SOC_IMX27
294 select IMX_HAVE_PLATFORM_GPIO_KEYS
257 select IMX_HAVE_PLATFORM_IMX_I2C 295 select IMX_HAVE_PLATFORM_IMX_I2C
258 select IMX_HAVE_PLATFORM_IMX_SSI 296 select IMX_HAVE_PLATFORM_IMX_SSI
259 select IMX_HAVE_PLATFORM_IMX_UART 297 select IMX_HAVE_PLATFORM_IMX_UART
@@ -314,3 +352,251 @@ config MACH_IMX27IPCAM
314 configurations for the board and its peripherals. 352 configurations for the board and its peripherals.
315 353
316endif 354endif
355
356if ARCH_MX3
357
358comment "MX31 platforms:"
359
360config MACH_MX31ADS
361 bool "Support MX31ADS platforms"
362 select SOC_IMX31
363 select IMX_HAVE_PLATFORM_IMX_I2C
364 select IMX_HAVE_PLATFORM_IMX_SSI
365 select IMX_HAVE_PLATFORM_IMX_UART
366 default y
367 help
368 Include support for MX31ADS platform. This includes specific
369 configurations for the board and its peripherals.
370
371config MACH_MX31ADS_WM1133_EV1
372 bool "Support Wolfson Microelectronics 1133-EV1 module"
373 depends on MACH_MX31ADS
374 depends on MFD_WM8350_I2C
375 depends on REGULATOR_WM8350
376 select MFD_WM8350_CONFIG_MODE_0
377 select MFD_WM8352_CONFIG_MODE_0
378 help
379 Include support for the Wolfson Microelectronics 1133-EV1 PMU
380 and audio module for the MX31ADS platform.
381
382config MACH_MX31LILLY
383 bool "Support MX31 LILLY-1131 platforms (INCO startec)"
384 select SOC_IMX31
385 select IMX_HAVE_PLATFORM_IMX_UART
386 select IMX_HAVE_PLATFORM_IPU_CORE
387 select IMX_HAVE_PLATFORM_MXC_EHCI
388 select IMX_HAVE_PLATFORM_MXC_MMC
389 select IMX_HAVE_PLATFORM_SPI_IMX
390 select MXC_ULPI if USB_ULPI
391 help
392 Include support for mx31 based LILLY1131 modules. This includes
393 specific configurations for the board and its peripherals.
394
395config MACH_MX31LITE
396 bool "Support MX31 LITEKIT (LogicPD)"
397 select SOC_IMX31
398 select MXC_ULPI if USB_ULPI
399 select IMX_HAVE_PLATFORM_IMX2_WDT
400 select IMX_HAVE_PLATFORM_IMX_UART
401 select IMX_HAVE_PLATFORM_MXC_EHCI
402 select IMX_HAVE_PLATFORM_MXC_MMC
403 select IMX_HAVE_PLATFORM_MXC_NAND
404 select IMX_HAVE_PLATFORM_MXC_RTC
405 select IMX_HAVE_PLATFORM_SPI_IMX
406 help
407 Include support for MX31 LITEKIT platform. This includes specific
408 configurations for the board and its peripherals.
409
410config MACH_PCM037
411 bool "Support Phytec pcm037 (i.MX31) platforms"
412 select SOC_IMX31
413 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
414 select IMX_HAVE_PLATFORM_IMX2_WDT
415 select IMX_HAVE_PLATFORM_IMX_I2C
416 select IMX_HAVE_PLATFORM_IMX_UART
417 select IMX_HAVE_PLATFORM_IPU_CORE
418 select IMX_HAVE_PLATFORM_MXC_EHCI
419 select IMX_HAVE_PLATFORM_MXC_MMC
420 select IMX_HAVE_PLATFORM_MXC_NAND
421 select IMX_HAVE_PLATFORM_MXC_W1
422 select MXC_ULPI if USB_ULPI
423 help
424 Include support for Phytec pcm037 platform. This includes
425 specific configurations for the board and its peripherals.
426
427config MACH_PCM037_EET
428 bool "Support pcm037 EET board extensions"
429 depends on MACH_PCM037
430 select IMX_HAVE_PLATFORM_GPIO_KEYS
431 select IMX_HAVE_PLATFORM_SPI_IMX
432 help
433 Add support for PCM037 EET baseboard extensions. If you are using the
434 OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
435 command-line parameter.
436
437config MACH_MX31_3DS
438 bool "Support MX31PDK (3DS)"
439 select SOC_IMX31
440 select MXC_DEBUG_BOARD
441 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
442 select IMX_HAVE_PLATFORM_IMX2_WDT
443 select IMX_HAVE_PLATFORM_IMX_I2C
444 select IMX_HAVE_PLATFORM_IMX_KEYPAD
445 select IMX_HAVE_PLATFORM_IMX_UART
446 select IMX_HAVE_PLATFORM_IPU_CORE
447 select IMX_HAVE_PLATFORM_MXC_EHCI
448 select IMX_HAVE_PLATFORM_MXC_NAND
449 select IMX_HAVE_PLATFORM_SPI_IMX
450 select MXC_ULPI if USB_ULPI
451 help
452 Include support for MX31PDK (3DS) platform. This includes specific
453 configurations for the board and its peripherals.
454
455config MACH_MX31_3DS_MXC_NAND_USE_BBT
456 bool "Make the MXC NAND driver use the in flash Bad Block Table"
457 depends on MACH_MX31_3DS
458 depends on MTD_NAND_MXC
459 help
460 Enable this if you want that the MXC NAND driver uses the in flash
461 Bad Block Table to know what blocks are bad instead of scanning the
462 entire flash looking for bad block markers.
463
464config MACH_MX31MOBOARD
465 bool "Support mx31moboard platforms (EPFL Mobots group)"
466 select SOC_IMX31
467 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
468 select IMX_HAVE_PLATFORM_IMX_I2C
469 select IMX_HAVE_PLATFORM_IMX_UART
470 select IMX_HAVE_PLATFORM_IPU_CORE
471 select IMX_HAVE_PLATFORM_MXC_EHCI
472 select IMX_HAVE_PLATFORM_MXC_MMC
473 select IMX_HAVE_PLATFORM_SPI_IMX
474 select MXC_ULPI if USB_ULPI
475 help
476 Include support for mx31moboard platform. This includes specific
477 configurations for the board and its peripherals.
478
479config MACH_QONG
480 bool "Support Dave/DENX QongEVB-LITE platform"
481 select SOC_IMX31
482 select IMX_HAVE_PLATFORM_IMX_UART
483 help
484 Include support for Dave/DENX QongEVB-LITE platform. This includes
485 specific configurations for the board and its peripherals.
486
487config MACH_ARMADILLO5X0
488 bool "Support Atmark Armadillo-500 Development Base Board"
489 select SOC_IMX31
490 select IMX_HAVE_PLATFORM_GPIO_KEYS
491 select IMX_HAVE_PLATFORM_IMX_I2C
492 select IMX_HAVE_PLATFORM_IMX_UART
493 select IMX_HAVE_PLATFORM_IPU_CORE
494 select IMX_HAVE_PLATFORM_MXC_EHCI
495 select IMX_HAVE_PLATFORM_MXC_MMC
496 select IMX_HAVE_PLATFORM_MXC_NAND
497 select MXC_ULPI if USB_ULPI
498 help
499 Include support for Atmark Armadillo-500 platform. This includes
500 specific configurations for the board and its peripherals.
501
502config MACH_KZM_ARM11_01
503 bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
504 select SOC_IMX31
505 select IMX_HAVE_PLATFORM_IMX_UART
506 help
507 Include support for KZM-ARM11-01. This includes specific
508 configurations for the board and its peripherals.
509
510config MACH_BUG
511 bool "Support Buglabs BUGBase platform"
512 select SOC_IMX31
513 select IMX_HAVE_PLATFORM_IMX_UART
514 default y
515 help
516 Include support for BUGBase 1.3 platform. This includes specific
517 configurations for the board and its peripherals.
518
519comment "MX35 platforms:"
520
521config MACH_PCM043
522 bool "Support Phytec pcm043 (i.MX35) platforms"
523 select SOC_IMX35
524 select IMX_HAVE_PLATFORM_FLEXCAN
525 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
526 select IMX_HAVE_PLATFORM_IMX2_WDT
527 select IMX_HAVE_PLATFORM_IMX_I2C
528 select IMX_HAVE_PLATFORM_IMX_SSI
529 select IMX_HAVE_PLATFORM_IMX_UART
530 select IMX_HAVE_PLATFORM_IPU_CORE
531 select IMX_HAVE_PLATFORM_MXC_EHCI
532 select IMX_HAVE_PLATFORM_MXC_NAND
533 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
534 select MXC_ULPI if USB_ULPI
535 help
536 Include support for Phytec pcm043 platform. This includes
537 specific configurations for the board and its peripherals.
538
539config MACH_MX35_3DS
540 bool "Support MX35PDK platform"
541 select SOC_IMX35
542 select MXC_DEBUG_BOARD
543 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
544 select IMX_HAVE_PLATFORM_IMX2_WDT
545 select IMX_HAVE_PLATFORM_IMX_I2C
546 select IMX_HAVE_PLATFORM_IMX_UART
547 select IMX_HAVE_PLATFORM_MXC_EHCI
548 select IMX_HAVE_PLATFORM_MXC_NAND
549 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
550 help
551 Include support for MX35PDK platform. This includes specific
552 configurations for the board and its peripherals.
553
554config MACH_EUKREA_CPUIMX35
555 bool "Support Eukrea CPUIMX35 Platform"
556 select SOC_IMX35
557 select IMX_HAVE_PLATFORM_FLEXCAN
558 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
559 select IMX_HAVE_PLATFORM_IMX2_WDT
560 select IMX_HAVE_PLATFORM_IMX_I2C
561 select IMX_HAVE_PLATFORM_IMX_UART
562 select IMX_HAVE_PLATFORM_MXC_EHCI
563 select IMX_HAVE_PLATFORM_MXC_NAND
564 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
565 select MXC_ULPI if USB_ULPI
566 help
567 Include support for Eukrea CPUIMX35 platform. This includes
568 specific configurations for the board and its peripherals.
569
570choice
571 prompt "Baseboard"
572 depends on MACH_EUKREA_CPUIMX35
573 default MACH_EUKREA_MBIMXSD35_BASEBOARD
574
575config MACH_EUKREA_MBIMXSD35_BASEBOARD
576 bool "Eukrea MBIMXSD development board"
577 select IMX_HAVE_PLATFORM_GPIO_KEYS
578 select IMX_HAVE_PLATFORM_IMX_SSI
579 select IMX_HAVE_PLATFORM_IPU_CORE
580 help
581 This adds board specific devices that can be found on Eukrea's
582 MBIMXSD evaluation board.
583
584endchoice
585
586config MACH_VPR200
587 bool "Support VPR200 platform"
588 select SOC_IMX35
589 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
590 select IMX_HAVE_PLATFORM_GPIO_KEYS
591 select IMX_HAVE_PLATFORM_IMX2_WDT
592 select IMX_HAVE_PLATFORM_IMX_UART
593 select IMX_HAVE_PLATFORM_IMX_I2C
594 select IMX_HAVE_PLATFORM_IPU_CORE
595 select IMX_HAVE_PLATFORM_MXC_EHCI
596 select IMX_HAVE_PLATFORM_MXC_NAND
597 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
598 help
599 Include support for VPR200 platform. This includes specific
600 configurations for the board and its peripherals.
601
602endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b85794d27991..e9eb36dad888 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,9 +1,3 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o 1obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
8 2
9obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o 3obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
@@ -14,18 +8,27 @@ obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o 8obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o 9obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
16 10
11obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
12obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
13obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
14
17# Support for CMOS sensor interface 15# Support for CMOS sensor interface
18obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o 16obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
19 17
18# i.MX1 based machines
20obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o 19obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
21obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o 20obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
21obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
22 22
23# i.MX21 based machines
23obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 24obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
24 25
26# i.MX25 based machines
25obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o 27obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
26obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o 28obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
27obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o 29obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
28 30
31# i.MX27 based machines
29obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 32obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
30obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o 33obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
31obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 34obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
@@ -37,3 +40,24 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
37obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 40obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
38obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o 41obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
39obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o 42obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
43
44# i.MX31 based machines
45obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
46obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
47obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
48obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
49obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
50obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
51obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
52 mx31moboard-marxbot.o mx31moboard-smartbot.o
53obj-$(CONFIG_MACH_QONG) += mach-qong.o
54obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
55obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
56obj-$(CONFIG_MACH_BUG) += mach-bug.o
57
58# i.MX35 based machines
59obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
60obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
61obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
62obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
63obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 3953d60bff0b..ebee18b3884c 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -13,3 +13,7 @@ initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
13zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 13zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
14params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 14params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
15initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 15initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
16
17zreladdr-$(CONFIG_ARCH_MX3) := 0x80008000
18params_phys-$(CONFIG_ARCH_MX3) := 0x80000100
19initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
new file mode 100644
index 000000000000..69d1322add3c
--- /dev/null
+++ b/arch/arm/mach-imx/cache-l2x0.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 * Juergen Beisert <j.beisert@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/err.h>
13#include <linux/kernel.h>
14
15#include <asm/hardware/cache-l2x0.h>
16
17#include <mach/hardware.h>
18
19static int mxc_init_l2x0(void)
20{
21 void __iomem *l2x0_base;
22 void __iomem *clkctl_base;
23
24 if (!cpu_is_mx31() && !cpu_is_mx35())
25 return 0;
26
27/*
28 * First of all, we must repair broken chip settings. There are some
29 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
30 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
31 * Workaraound is to setup the correct register setting prior enabling the
32 * L2 cache. This should not hurt already working CPUs, as they are using the
33 * same value.
34 */
35#define L2_MEM_VAL 0x10
36
37 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
38 if (clkctl_base != NULL) {
39 writel(0x00000515, clkctl_base + L2_MEM_VAL);
40 iounmap(clkctl_base);
41 } else {
42 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
43 }
44
45 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
46 if (IS_ERR(l2x0_base)) {
47 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
48 PTR_ERR(l2x0_base));
49 return 0;
50 }
51
52 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
53
54 return 0;
55}
56arch_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
index d423cac8cab7..25f343fca2b9 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -32,7 +32,7 @@
32#include <mach/mx31.h> 32#include <mach/mx31.h>
33#include <mach/common.h> 33#include <mach/common.h>
34 34
35#include "crm_regs.h" 35#include "crmregs-imx31.h"
36 36
37#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ 37#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
38 38
@@ -627,4 +627,3 @@ int __init mx31_clocks_init(unsigned long fref)
627 627
628 return 0; 628 return 0;
629} 629}
630
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index 448a038cd1ec..5a4cc1ea405b 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -547,4 +547,3 @@ int __init mx35_clocks_init()
547 547
548 return 0; 548 return 0;
549} 549}
550
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-imx/cpu-imx31.c
index d1d339576fdf..a3780700a882 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * MX3 CPU type detection 2 * MX31 CPU type detection
3 * 3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 * 5 *
@@ -17,14 +17,12 @@
17unsigned int mx31_cpu_rev; 17unsigned int mx31_cpu_rev;
18EXPORT_SYMBOL(mx31_cpu_rev); 18EXPORT_SYMBOL(mx31_cpu_rev);
19 19
20struct mx3_cpu_type { 20static struct {
21 u8 srev; 21 u8 srev;
22 const char *name; 22 const char *name;
23 const char *v; 23 const char *v;
24 unsigned int rev; 24 unsigned int rev;
25}; 25} mx31_cpu_type[] __initdata = {
26
27static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
28 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, 26 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
29 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, 27 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
30 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, 28 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
@@ -57,33 +55,3 @@ void __init mx31_read_cpu_rev(void)
57 55
58 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); 56 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
59} 57}
60
61unsigned int mx35_cpu_rev;
62EXPORT_SYMBOL(mx35_cpu_rev);
63
64void __init mx35_read_cpu_rev(void)
65{
66 u32 rev;
67 char *srev;
68
69 rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
70 switch (rev) {
71 case 0x00:
72 mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
73 srev = "1.0";
74 break;
75 case 0x10:
76 mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
77 srev = "2.0";
78 break;
79 case 0x11:
80 mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
81 srev = "2.1";
82 break;
83 default:
84 mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
85 srev = "unknown";
86 }
87
88 printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
89}
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
new file mode 100644
index 000000000000..6637cd819ecb
--- /dev/null
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -0,0 +1,44 @@
1/*
2 * MX35 CPU type detection
3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/io.h>
13#include <mach/hardware.h>
14#include <mach/iim.h>
15
16unsigned int mx35_cpu_rev;
17EXPORT_SYMBOL(mx35_cpu_rev);
18
19void __init mx35_read_cpu_rev(void)
20{
21 u32 rev;
22 char *srev;
23
24 rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
25 switch (rev) {
26 case 0x00:
27 mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
28 srev = "1.0";
29 break;
30 case 0x10:
31 mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
32 srev = "2.0";
33 break;
34 case 0x11:
35 mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
36 srev = "2.1";
37 break;
38 default:
39 mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
40 srev = "unknown";
41 }
42
43 printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
44}
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-imx/crmregs-imx31.h
index 37a8a07beda3..37a8a07beda3 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-imx/crmregs-imx31.h
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index da593657ff3f..3aad1e70de96 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,21 +9,21 @@
9#include <mach/mx1.h> 9#include <mach/mx1.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst; 12extern const struct imx_imx_fb_data imx1_imx_fb_data;
13#define imx1_add_imx_fb(pdata) \ 13#define imx1_add_imx_fb(pdata) \
14 imx_add_imx_fb(&imx1_imx_fb_data, pdata) 14 imx_add_imx_fb(&imx1_imx_fb_data, pdata)
15 15
16extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; 16extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
17#define imx1_add_imx_i2c(pdata) \ 17#define imx1_add_imx_i2c(pdata) \
18 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) 18 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
19 19
20extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst; 20extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
21#define imx1_add_imx_uart(id, pdata) \ 21#define imx1_add_imx_uart(id, pdata) \
22 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) 22 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
23#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) 23#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
24#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) 24#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
25 25
26extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst; 26extern const struct imx_spi_imx_data imx1_cspi_data[];
27#define imx1_add_cspi(id, pdata) \ 27#define imx1_add_cspi(id, pdata) \
28 imx_add_spi_imx(&imx1_cspi_data[id], pdata) 28 imx_add_spi_imx(&imx1_cspi_data[id], pdata)
29 29
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 16744d2d9b81..2628e0c474dc 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,31 +9,31 @@
9#include <mach/mx21.h> 9#include <mach/mx21.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst; 12extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
13#define imx21_add_imx21_hcd(pdata) \ 13#define imx21_add_imx21_hcd(pdata) \
14 imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) 14 imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
15 15
16extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst; 16extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
17#define imx21_add_imx2_wdt(pdata) \ 17#define imx21_add_imx2_wdt(pdata) \
18 imx_add_imx2_wdt(&imx21_imx2_wdt_data) 18 imx_add_imx2_wdt(&imx21_imx2_wdt_data)
19 19
20extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst; 20extern const struct imx_imx_fb_data imx21_imx_fb_data;
21#define imx21_add_imx_fb(pdata) \ 21#define imx21_add_imx_fb(pdata) \
22 imx_add_imx_fb(&imx21_imx_fb_data, pdata) 22 imx_add_imx_fb(&imx21_imx_fb_data, pdata)
23 23
24extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; 24extern const struct imx_imx_i2c_data imx21_imx_i2c_data;
25#define imx21_add_imx_i2c(pdata) \ 25#define imx21_add_imx_i2c(pdata) \
26 imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) 26 imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
27 27
28extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst; 28extern const struct imx_imx_keypad_data imx21_imx_keypad_data;
29#define imx21_add_imx_keypad(pdata) \ 29#define imx21_add_imx_keypad(pdata) \
30 imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) 30 imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
31 31
32extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; 32extern const struct imx_imx_ssi_data imx21_imx_ssi_data[];
33#define imx21_add_imx_ssi(id, pdata) \ 33#define imx21_add_imx_ssi(id, pdata) \
34 imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) 34 imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
35 35
36extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; 36extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[];
37#define imx21_add_imx_uart(id, pdata) \ 37#define imx21_add_imx_uart(id, pdata) \
38 imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) 38 imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
39#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata) 39#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
@@ -41,19 +41,19 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
41#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) 41#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
42#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) 42#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
43 43
44extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst; 44extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[];
45#define imx21_add_mxc_mmc(id, pdata) \ 45#define imx21_add_mxc_mmc(id, pdata) \
46 imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) 46 imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
47 47
48extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; 48extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
49#define imx21_add_mxc_nand(pdata) \ 49#define imx21_add_mxc_nand(pdata) \
50 imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) 50 imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
51 51
52extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst; 52extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
53#define imx21_add_mxc_w1(pdata) \ 53#define imx21_add_mxc_w1(pdata) \
54 imx_add_mxc_w1(&imx21_mxc_w1_data) 54 imx_add_mxc_w1(&imx21_mxc_w1_data)
55 55
56extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; 56extern const struct imx_spi_imx_data imx21_cspi_data[];
57#define imx21_add_cspi(id, pdata) \ 57#define imx21_add_cspi(id, pdata) \
58 imx_add_spi_imx(&imx21_cspi_data[id], pdata) 58 imx_add_spi_imx(&imx21_cspi_data[id], pdata)
59#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata) 59#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index b591d72f6037..efa0761c508d 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -9,48 +9,48 @@
9#include <mach/mx25.h> 9#include <mach/mx25.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fec_data imx25_fec_data __initconst; 12extern const struct imx_fec_data imx25_fec_data;
13#define imx25_add_fec(pdata) \ 13#define imx25_add_fec(pdata) \
14 imx_add_fec(&imx25_fec_data, pdata) 14 imx_add_fec(&imx25_fec_data, pdata)
15 15
16extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst; 16extern const struct imx_flexcan_data imx25_flexcan_data[];
17#define imx25_add_flexcan(id, pdata) \ 17#define imx25_add_flexcan(id, pdata) \
18 imx_add_flexcan(&imx25_flexcan_data[id], pdata) 18 imx_add_flexcan(&imx25_flexcan_data[id], pdata)
19#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata) 19#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
20#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata) 20#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
21 21
22extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst; 22extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
23#define imx25_add_fsl_usb2_udc(pdata) \ 23#define imx25_add_fsl_usb2_udc(pdata) \
24 imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) 24 imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
25 25
26extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst; 26extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
27#define imx25_add_imxdi_rtc(pdata) \ 27#define imx25_add_imxdi_rtc(pdata) \
28 imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) 28 imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
29 29
30extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst; 30extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
31#define imx25_add_imx2_wdt(pdata) \ 31#define imx25_add_imx2_wdt(pdata) \
32 imx_add_imx2_wdt(&imx25_imx2_wdt_data) 32 imx_add_imx2_wdt(&imx25_imx2_wdt_data)
33 33
34extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst; 34extern const struct imx_imx_fb_data imx25_imx_fb_data;
35#define imx25_add_imx_fb(pdata) \ 35#define imx25_add_imx_fb(pdata) \
36 imx_add_imx_fb(&imx25_imx_fb_data, pdata) 36 imx_add_imx_fb(&imx25_imx_fb_data, pdata)
37 37
38extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; 38extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
39#define imx25_add_imx_i2c(id, pdata) \ 39#define imx25_add_imx_i2c(id, pdata) \
40 imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata) 40 imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
41#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata) 41#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
42#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) 42#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
43#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) 43#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
44 44
45extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst; 45extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
46#define imx25_add_imx_keypad(pdata) \ 46#define imx25_add_imx_keypad(pdata) \
47 imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) 47 imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
48 48
49extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; 49extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
50#define imx25_add_imx_ssi(id, pdata) \ 50#define imx25_add_imx_ssi(id, pdata) \
51 imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) 51 imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
52 52
53extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; 53extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
54#define imx25_add_imx_uart(id, pdata) \ 54#define imx25_add_imx_uart(id, pdata) \
55 imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) 55 imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
56#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata) 56#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
@@ -59,33 +59,32 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
59#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) 59#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
60#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) 60#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
61 61
62extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst; 62extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
63#define imx25_add_mx2_camera(pdata) \ 63#define imx25_add_mx2_camera(pdata) \
64 imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) 64 imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
65 65
66extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst; 66extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
67#define imx25_add_mxc_ehci_otg(pdata) \ 67#define imx25_add_mxc_ehci_otg(pdata) \
68 imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) 68 imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
69extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst; 69extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
70#define imx25_add_mxc_ehci_hs(pdata) \ 70#define imx25_add_mxc_ehci_hs(pdata) \
71 imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) 71 imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
72 72
73extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; 73extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
74#define imx25_add_mxc_nand(pdata) \ 74#define imx25_add_mxc_nand(pdata) \
75 imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) 75 imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
76 76
77extern const struct imx_sdhci_esdhc_imx_data 77extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
78imx25_sdhci_esdhc_imx_data[] __initconst;
79#define imx25_add_sdhci_esdhc_imx(id, pdata) \ 78#define imx25_add_sdhci_esdhc_imx(id, pdata) \
80 imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) 79 imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
81 80
82extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; 81extern const struct imx_spi_imx_data imx25_cspi_data[];
83#define imx25_add_spi_imx(id, pdata) \ 82#define imx25_add_spi_imx(id, pdata) \
84 imx_add_spi_imx(&imx25_cspi_data[id], pdata) 83 imx_add_spi_imx(&imx25_cspi_data[id], pdata)
85#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) 84#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
86#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) 85#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
87#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) 86#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
88 87
89extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst; 88extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
90#define imx25_add_mxc_pwm(id) \ 89#define imx25_add_mxc_pwm(id) \
91 imx_add_mxc_pwm(&imx25_mxc_pwm_data[id]) 90 imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index f1272d4b5a33..7f97a3cdd41d 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -9,35 +9,35 @@
9#include <mach/mx27.h> 9#include <mach/mx27.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fec_data imx27_fec_data __initconst; 12extern const struct imx_fec_data imx27_fec_data;
13#define imx27_add_fec(pdata) \ 13#define imx27_add_fec(pdata) \
14 imx_add_fec(&imx27_fec_data, pdata) 14 imx_add_fec(&imx27_fec_data, pdata)
15 15
16extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst; 16extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
17#define imx27_add_fsl_usb2_udc(pdata) \ 17#define imx27_add_fsl_usb2_udc(pdata) \
18 imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) 18 imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
19 19
20extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst; 20extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
21#define imx27_add_imx2_wdt(pdata) \ 21#define imx27_add_imx2_wdt(pdata) \
22 imx_add_imx2_wdt(&imx27_imx2_wdt_data) 22 imx_add_imx2_wdt(&imx27_imx2_wdt_data)
23 23
24extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst; 24extern const struct imx_imx_fb_data imx27_imx_fb_data;
25#define imx27_add_imx_fb(pdata) \ 25#define imx27_add_imx_fb(pdata) \
26 imx_add_imx_fb(&imx27_imx_fb_data, pdata) 26 imx_add_imx_fb(&imx27_imx_fb_data, pdata)
27 27
28extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; 28extern const struct imx_imx_i2c_data imx27_imx_i2c_data[];
29#define imx27_add_imx_i2c(id, pdata) \ 29#define imx27_add_imx_i2c(id, pdata) \
30 imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) 30 imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
31 31
32extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst; 32extern const struct imx_imx_keypad_data imx27_imx_keypad_data;
33#define imx27_add_imx_keypad(pdata) \ 33#define imx27_add_imx_keypad(pdata) \
34 imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) 34 imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
35 35
36extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; 36extern const struct imx_imx_ssi_data imx27_imx_ssi_data[];
37#define imx27_add_imx_ssi(id, pdata) \ 37#define imx27_add_imx_ssi(id, pdata) \
38 imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) 38 imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
39 39
40extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; 40extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
41#define imx27_add_imx_uart(id, pdata) \ 41#define imx27_add_imx_uart(id, pdata) \
42 imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) 42 imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
43#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata) 43#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
@@ -47,30 +47,30 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
47#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) 47#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
48#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) 48#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
49 49
50extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst; 50extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
51#define imx27_add_mx2_camera(pdata) \ 51#define imx27_add_mx2_camera(pdata) \
52 imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) 52 imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
53 53
54extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst; 54extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
55#define imx27_add_mxc_ehci_otg(pdata) \ 55#define imx27_add_mxc_ehci_otg(pdata) \
56 imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) 56 imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
57extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst; 57extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[];
58#define imx27_add_mxc_ehci_hs(id, pdata) \ 58#define imx27_add_mxc_ehci_hs(id, pdata) \
59 imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) 59 imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
60 60
61extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst; 61extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[];
62#define imx27_add_mxc_mmc(id, pdata) \ 62#define imx27_add_mxc_mmc(id, pdata) \
63 imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) 63 imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
64 64
65extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; 65extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
66#define imx27_add_mxc_nand(pdata) \ 66#define imx27_add_mxc_nand(pdata) \
67 imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) 67 imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
68 68
69extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst; 69extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
70#define imx27_add_mxc_w1(pdata) \ 70#define imx27_add_mxc_w1(pdata) \
71 imx_add_mxc_w1(&imx27_mxc_w1_data) 71 imx_add_mxc_w1(&imx27_mxc_w1_data)
72 72
73extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; 73extern const struct imx_spi_imx_data imx27_cspi_data[];
74#define imx27_add_cspi(id, pdata) \ 74#define imx27_add_cspi(id, pdata) \
75 imx_add_spi_imx(&imx27_cspi_data[id], pdata) 75 imx_add_spi_imx(&imx27_cspi_data[id], pdata)
76#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) 76#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index 40f4e848a671..dbe940d9c53a 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -9,30 +9,30 @@
9#include <mach/mx31.h> 9#include <mach/mx31.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst; 12extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
13#define imx31_add_fsl_usb2_udc(pdata) \ 13#define imx31_add_fsl_usb2_udc(pdata) \
14 imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) 14 imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
15 15
16extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst; 16extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
17#define imx31_add_imx2_wdt(pdata) \ 17#define imx31_add_imx2_wdt(pdata) \
18 imx_add_imx2_wdt(&imx31_imx2_wdt_data) 18 imx_add_imx2_wdt(&imx31_imx2_wdt_data)
19 19
20extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; 20extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
21#define imx31_add_imx_i2c(id, pdata) \ 21#define imx31_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) 22 imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
23#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata) 23#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
24#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) 24#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
25#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) 25#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
26 26
27extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst; 27extern const struct imx_imx_keypad_data imx31_imx_keypad_data;
28#define imx31_add_imx_keypad(pdata) \ 28#define imx31_add_imx_keypad(pdata) \
29 imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) 29 imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
30 30
31extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; 31extern const struct imx_imx_ssi_data imx31_imx_ssi_data[];
32#define imx31_add_imx_ssi(id, pdata) \ 32#define imx31_add_imx_ssi(id, pdata) \
33 imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) 33 imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
34 34
35extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; 35extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
36#define imx31_add_imx_uart(id, pdata) \ 36#define imx31_add_imx_uart(id, pdata) \
37 imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) 37 imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
38#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) 38#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
@@ -41,26 +41,38 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
41#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) 41#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
42#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) 42#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
43 43
44extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst; 44extern const struct imx_ipu_core_data imx31_ipu_core_data;
45#define imx31_add_ipu_core(pdata) \
46 imx_add_ipu_core(&imx31_ipu_core_data, pdata)
47#define imx31_alloc_mx3_camera(pdata) \
48 imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
49#define imx31_add_mx3_sdc_fb(pdata) \
50 imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata)
51
52extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data;
45#define imx31_add_mxc_ehci_otg(pdata) \ 53#define imx31_add_mxc_ehci_otg(pdata) \
46 imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) 54 imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
47extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst; 55extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[];
48#define imx31_add_mxc_ehci_hs(id, pdata) \ 56#define imx31_add_mxc_ehci_hs(id, pdata) \
49 imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) 57 imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
50 58
51extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst; 59extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[];
52#define imx31_add_mxc_mmc(id, pdata) \ 60#define imx31_add_mxc_mmc(id, pdata) \
53 imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) 61 imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
54 62
55extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; 63extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
56#define imx31_add_mxc_nand(pdata) \ 64#define imx31_add_mxc_nand(pdata) \
57 imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) 65 imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
58 66
59extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst; 67extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
68#define imx31_add_mxc_rtc(pdata) \
69 imx_add_mxc_rtc(&imx31_mxc_rtc_data)
70
71extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
60#define imx31_add_mxc_w1(pdata) \ 72#define imx31_add_mxc_w1(pdata) \
61 imx_add_mxc_w1(&imx31_mxc_w1_data) 73 imx_add_mxc_w1(&imx31_mxc_w1_data)
62 74
63extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; 75extern const struct imx_spi_imx_data imx31_cspi_data[];
64#define imx31_add_cspi(id, pdata) \ 76#define imx31_add_cspi(id, pdata) \
65 imx_add_spi_imx(&imx31_cspi_data[id], pdata) 77 imx_add_spi_imx(&imx31_cspi_data[id], pdata)
66#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) 78#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index d545d86cc202..234cbd3c18af 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -9,67 +9,74 @@
9#include <mach/mx35.h> 9#include <mach/mx35.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fec_data imx35_fec_data __initconst; 12extern const struct imx_fec_data imx35_fec_data;
13#define imx35_add_fec(pdata) \ 13#define imx35_add_fec(pdata) \
14 imx_add_fec(&imx35_fec_data, pdata) 14 imx_add_fec(&imx35_fec_data, pdata)
15 15
16extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst; 16extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
17#define imx35_add_fsl_usb2_udc(pdata) \ 17#define imx35_add_fsl_usb2_udc(pdata) \
18 imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) 18 imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
19 19
20extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst; 20extern const struct imx_flexcan_data imx35_flexcan_data[];
21#define imx35_add_flexcan(id, pdata) \ 21#define imx35_add_flexcan(id, pdata) \
22 imx_add_flexcan(&imx35_flexcan_data[id], pdata) 22 imx_add_flexcan(&imx35_flexcan_data[id], pdata)
23#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata) 23#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
24#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) 24#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
25 25
26extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst; 26extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
27#define imx35_add_imx2_wdt(pdata) \ 27#define imx35_add_imx2_wdt(pdata) \
28 imx_add_imx2_wdt(&imx35_imx2_wdt_data) 28 imx_add_imx2_wdt(&imx35_imx2_wdt_data)
29 29
30extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; 30extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
31#define imx35_add_imx_i2c(id, pdata) \ 31#define imx35_add_imx_i2c(id, pdata) \
32 imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata) 32 imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
33#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata) 33#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
34#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) 34#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) 35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
36 36
37extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; 37extern const struct imx_imx_keypad_data imx35_imx_keypad_data;
38#define imx35_add_imx_keypad(pdata) \ 38#define imx35_add_imx_keypad(pdata) \
39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) 39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
40 40
41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; 41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[];
42#define imx35_add_imx_ssi(id, pdata) \ 42#define imx35_add_imx_ssi(id, pdata) \
43 imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) 43 imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
44 44
45extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; 45extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
46#define imx35_add_imx_uart(id, pdata) \ 46#define imx35_add_imx_uart(id, pdata) \
47 imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) 47 imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
48#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) 48#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
49#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) 49#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
50#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) 50#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
51 51
52extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst; 52extern const struct imx_ipu_core_data imx35_ipu_core_data;
53#define imx35_add_ipu_core(pdata) \
54 imx_add_ipu_core(&imx35_ipu_core_data, pdata)
55#define imx35_alloc_mx3_camera(pdata) \
56 imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
57#define imx35_add_mx3_sdc_fb(pdata) \
58 imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata)
59
60extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data;
53#define imx35_add_mxc_ehci_otg(pdata) \ 61#define imx35_add_mxc_ehci_otg(pdata) \
54 imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) 62 imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
55extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst; 63extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data;
56#define imx35_add_mxc_ehci_hs(pdata) \ 64#define imx35_add_mxc_ehci_hs(pdata) \
57 imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) 65 imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
58 66
59extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; 67extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
60#define imx35_add_mxc_nand(pdata) \ 68#define imx35_add_mxc_nand(pdata) \
61 imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) 69 imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
62 70
63extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst; 71extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
64#define imx35_add_mxc_w1(pdata) \ 72#define imx35_add_mxc_w1(pdata) \
65 imx_add_mxc_w1(&imx35_mxc_w1_data) 73 imx_add_mxc_w1(&imx35_mxc_w1_data)
66 74
67extern const struct imx_sdhci_esdhc_imx_data 75extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
68imx35_sdhci_esdhc_imx_data[] __initconst;
69#define imx35_add_sdhci_esdhc_imx(id, pdata) \ 76#define imx35_add_sdhci_esdhc_imx(id, pdata) \
70 imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) 77 imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
71 78
72extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; 79extern const struct imx_spi_imx_data imx35_cspi_data[];
73#define imx35_add_cspi(id, pdata) \ 80#define imx35_add_cspi(id, pdata) \
74 imx_add_spi_imx(&imx35_cspi_data[id], pdata) 81 imx_add_spi_imx(&imx35_cspi_data[id], pdata)
75#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) 82#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index 314a983ac614..faad0f15ac7f 100644
--- a/arch/arm/mach-mx3/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -80,4 +80,3 @@ int mx31_initialize_usb_hw(int port, unsigned int flags)
80 80
81 return 0; 81 return 0;
82} 82}
83
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 33983a478c6b..001ec3971f5d 100644
--- a/arch/arm/mach-mx3/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -77,4 +77,3 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
77 77
78 return 0; 78 return 0;
79} 79}
80
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index fa5288018ba7..5911281da5f5 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
32#include <mach/common.h> 32#include <mach/common.h>
33#include <mach/iomux-mx27.h> 33#include <mach/iomux-mx27.h>
34#include <mach/hardware.h> 34#include <mach/hardware.h>
35#include <mach/spi.h>
36#include <mach/audmux.h> 35#include <mach/audmux.h>
37 36
38#include "devices-imx27.h" 37#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 6269053505f7..f9ef04acdab1 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -22,7 +22,6 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/leds.h> 23#include <linux/leds.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/gpio_keys.h>
26#include <linux/input.h> 25#include <linux/input.h>
27#include <video/platform_lcd.h> 26#include <video/platform_lcd.h>
28 27
@@ -32,9 +31,7 @@
32#include <asm/mach-types.h> 31#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
34#include <mach/mx25.h> 33#include <mach/mx25.h>
35#include <mach/imx-uart.h>
36#include <mach/audmux.h> 34#include <mach/audmux.h>
37#include <mach/esdhc.h>
38 35
39#include "devices-imx25.h" 36#include "devices-imx25.h"
40 37
@@ -208,23 +205,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
208 }, 205 },
209}; 206};
210 207
211static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { 208static const struct gpio_keys_platform_data
209 eukrea_mbimxsd_button_data __initconst = {
212 .buttons = eukrea_mbimxsd_gpio_buttons, 210 .buttons = eukrea_mbimxsd_gpio_buttons,
213 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), 211 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
214}; 212};
215 213
216static struct platform_device eukrea_mbimxsd_button_device = {
217 .name = "gpio-keys",
218 .id = -1,
219 .num_resources = 0,
220 .dev = {
221 .platform_data = &eukrea_mbimxsd_button_data,
222 }
223};
224
225static struct platform_device *platform_devices[] __initdata = { 214static struct platform_device *platform_devices[] __initdata = {
226 &eukrea_mbimxsd_leds_gpio, 215 &eukrea_mbimxsd_leds_gpio,
227 &eukrea_mbimxsd_button_device,
228 &eukrea_mbimxsd_lcd_powerdev, 216 &eukrea_mbimxsd_lcd_powerdev,
229}; 217};
230 218
@@ -299,4 +287,5 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
299 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); 287 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
300 288
301 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 289 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
290 imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
302} 291}
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 2e288b38b4ad..4909ea05855a 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -26,7 +26,6 @@
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/leds.h> 27#include <linux/leds.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h> 29#include <linux/input.h>
31#include <video/platform_lcd.h> 30#include <video/platform_lcd.h>
32#include <linux/i2c.h> 31#include <linux/i2c.h>
@@ -38,15 +37,10 @@
38 37
39#include <mach/hardware.h> 38#include <mach/hardware.h>
40#include <mach/common.h> 39#include <mach/common.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx35.h> 40#include <mach/iomux-mx35.h>
43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
45#include <mach/audmux.h> 41#include <mach/audmux.h>
46#include <mach/esdhc.h>
47 42
48#include "devices-imx35.h" 43#include "devices-imx35.h"
49#include "devices.h"
50 44
51static const struct fb_videomode fb_modedb[] = { 45static const struct fb_videomode fb_modedb[] = {
52 { 46 {
@@ -101,12 +95,11 @@ static const struct fb_videomode fb_modedb[] = {
101 }, 95 },
102}; 96};
103 97
104static struct ipu_platform_data mx3_ipu_data = { 98static const struct ipu_platform_data mx3_ipu_data __initconst = {
105 .irq_base = MXC_IPU_IRQ_START, 99 .irq_base = MXC_IPU_IRQ_START,
106}; 100};
107 101
108static struct mx3fb_platform_data mx3fb_pdata = { 102static struct mx3fb_platform_data mx3fb_pdata __initdata = {
109 .dma_dev = &mx3_ipu.dev,
110 .name = "CMO-QVGA", 103 .name = "CMO-QVGA",
111 .mode = fb_modedb, 104 .mode = fb_modedb,
112 .num_modes = ARRAY_SIZE(fb_modedb), 105 .num_modes = ARRAY_SIZE(fb_modedb),
@@ -223,23 +216,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
223 }, 216 },
224}; 217};
225 218
226static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { 219static const struct gpio_keys_platform_data
220 eukrea_mbimxsd_button_data __initconst = {
227 .buttons = eukrea_mbimxsd_gpio_buttons, 221 .buttons = eukrea_mbimxsd_gpio_buttons,
228 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), 222 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
229}; 223};
230 224
231static struct platform_device eukrea_mbimxsd_button_device = {
232 .name = "gpio-keys",
233 .id = -1,
234 .num_resources = 0,
235 .dev = {
236 .platform_data = &eukrea_mbimxsd_button_data,
237 }
238};
239
240static struct platform_device *platform_devices[] __initdata = { 225static struct platform_device *platform_devices[] __initdata = {
241 &eukrea_mbimxsd_leds_gpio, 226 &eukrea_mbimxsd_leds_gpio,
242 &eukrea_mbimxsd_button_device,
243 &eukrea_mbimxsd_lcd_powerdev, 227 &eukrea_mbimxsd_lcd_powerdev,
244}; 228};
245 229
@@ -292,8 +276,8 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
292#endif 276#endif
293 277
294 imx35_add_imx_uart1(&uart_pdata); 278 imx35_add_imx_uart1(&uart_pdata);
295 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 279 imx35_add_ipu_core(&mx3_ipu_data);
296 mxc_register_device(&mx3_fb, &mx3fb_pdata); 280 imx35_add_mx3_sdc_fb(&mx3fb_pdata);
297 281
298 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 282 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
299 283
@@ -315,4 +299,5 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
315 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); 299 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
316 300
317 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 301 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
302 imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
318} 303}
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index cf8f8099ebd7..cf8f8099ebd7 100644
--- a/arch/arm/mach-mx3/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
new file mode 100644
index 000000000000..15e45c84e371
--- /dev/null
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -0,0 +1,144 @@
1/*
2 * linux/arch/arm/mach-imx/mach-apf9328.c
3 *
4 * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com>
5 *
6 * This work is based on mach-scb9328.c which is:
7 * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
8 * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/dm9000.h>
21
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/time.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/irqs.h>
29#include <mach/iomux-mx1.h>
30
31#include "devices-imx1.h"
32
33static const int apf9328_pins[] __initconst = {
34 /* UART1 */
35 PC9_PF_UART1_CTS,
36 PC10_PF_UART1_RTS,
37 PC11_PF_UART1_TXD,
38 PC12_PF_UART1_RXD,
39 /* UART2 */
40 PB28_PF_UART2_CTS,
41 PB29_PF_UART2_RTS,
42 PB30_PF_UART2_TXD,
43 PB31_PF_UART2_RXD,
44};
45
46/*
47 * The APF9328 can have up to 32MB NOR Flash
48 */
49static struct resource flash_resource = {
50 .start = MX1_CS0_PHYS,
51 .end = MX1_CS0_PHYS + SZ_32M - 1,
52 .flags = IORESOURCE_MEM,
53};
54
55static struct physmap_flash_data apf9328_flash_data = {
56 .width = 2,
57};
58
59static struct platform_device apf9328_flash_device = {
60 .name = "physmap-flash",
61 .id = 0,
62 .dev = {
63 .platform_data = &apf9328_flash_data,
64 },
65 .resource = &flash_resource,
66 .num_resources = 1,
67};
68
69/*
70 * APF9328 has a DM9000 Ethernet controller
71 */
72static struct dm9000_plat_data dm9000_setup = {
73 .flags = DM9000_PLATF_16BITONLY
74};
75
76static struct resource dm9000_resources[] = {
77 {
78 .start = MX1_CS4_PHYS + 0x00C00000,
79 .end = MX1_CS4_PHYS + 0x00C00001,
80 .flags = IORESOURCE_MEM,
81 }, {
82 .start = MX1_CS4_PHYS + 0x00C00002,
83 .end = MX1_CS4_PHYS + 0x00C00003,
84 .flags = IORESOURCE_MEM,
85 }, {
86 .start = IRQ_GPIOB(14),
87 .end = IRQ_GPIOB(14),
88 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
89 },
90};
91
92static struct platform_device dm9000x_device = {
93 .name = "dm9000",
94 .id = 0,
95 .num_resources = ARRAY_SIZE(dm9000_resources),
96 .resource = dm9000_resources,
97 .dev = {
98 .platform_data = &dm9000_setup,
99 }
100};
101
102/* --- SERIAL RESSOURCE --- */
103static const struct imxuart_platform_data uart0_pdata __initconst = {
104 .flags = 0,
105};
106
107static const struct imxuart_platform_data uart1_pdata __initconst = {
108 .flags = IMXUART_HAVE_RTSCTS,
109};
110
111static struct platform_device *devices[] __initdata = {
112 &apf9328_flash_device,
113 &dm9000x_device,
114};
115
116static void __init apf9328_init(void)
117{
118 mxc_gpio_setup_multiple_pins(apf9328_pins,
119 ARRAY_SIZE(apf9328_pins),
120 "APF9328");
121
122 imx1_add_imx_uart0(&uart0_pdata);
123 imx1_add_imx_uart1(&uart1_pdata);
124
125 platform_add_devices(devices, ARRAY_SIZE(devices));
126}
127
128static void __init apf9328_timer_init(void)
129{
130 mx1_clocks_init(32768);
131}
132
133static struct sys_timer apf9328_timer = {
134 .init = apf9328_timer_init,
135};
136
137MACHINE_START(APF9328, "Armadeus APF9328")
138 /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
139 .map_io = mx1_map_io,
140 .init_early = imx1_init_early,
141 .init_irq = mx1_init_irq,
142 .timer = &apf9328_timer,
143 .init_machine = apf9328_init,
144MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 226829bf7c25..ffb40ff619b1 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -34,7 +34,6 @@
34#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
35#include <linux/io.h> 35#include <linux/io.h>
36#include <linux/input.h> 36#include <linux/input.h>
37#include <linux/gpio_keys.h>
38#include <linux/i2c.h> 37#include <linux/i2c.h>
39#include <linux/usb/otg.h> 38#include <linux/usb/otg.h>
40#include <linux/usb/ulpi.h> 39#include <linux/usb/ulpi.h>
@@ -49,13 +48,10 @@
49 48
50#include <mach/common.h> 49#include <mach/common.h>
51#include <mach/iomux-mx3.h> 50#include <mach/iomux-mx3.h>
52#include <mach/ipu.h>
53#include <mach/mx3fb.h>
54#include <mach/ulpi.h> 51#include <mach/ulpi.h>
55 52
56#include "devices-imx31.h" 53#include "devices-imx31.h"
57#include "devices.h" 54#include "crmregs-imx31.h"
58#include "crm_regs.h"
59 55
60static int armadillo5x0_pins[] = { 56static int armadillo5x0_pins[] = {
61 /* UART1 */ 57 /* UART1 */
@@ -280,20 +276,12 @@ static struct gpio_keys_button armadillo5x0_buttons[] = {
280 } 276 }
281}; 277};
282 278
283static struct gpio_keys_platform_data armadillo5x0_button_data = { 279static const struct gpio_keys_platform_data
280 armadillo5x0_button_data __initconst = {
284 .buttons = armadillo5x0_buttons, 281 .buttons = armadillo5x0_buttons,
285 .nbuttons = ARRAY_SIZE(armadillo5x0_buttons), 282 .nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
286}; 283};
287 284
288static struct platform_device armadillo5x0_button_device = {
289 .name = "gpio-keys",
290 .id = -1,
291 .num_resources = 0,
292 .dev = {
293 .platform_data = &armadillo5x0_button_data,
294 }
295};
296
297/* 285/*
298 * NAND Flash 286 * NAND Flash
299 */ 287 */
@@ -383,12 +371,11 @@ static const struct fb_videomode fb_modedb[] = {
383 }, 371 },
384}; 372};
385 373
386static struct ipu_platform_data mx3_ipu_data = { 374static const struct ipu_platform_data mx3_ipu_data __initconst = {
387 .irq_base = MXC_IPU_IRQ_START, 375 .irq_base = MXC_IPU_IRQ_START,
388}; 376};
389 377
390static struct mx3fb_platform_data mx3fb_pdata = { 378static struct mx3fb_platform_data mx3fb_pdata __initdata = {
391 .dma_dev = &mx3_ipu.dev,
392 .name = "CRT-VGA", 379 .name = "CRT-VGA",
393 .mode = fb_modedb, 380 .mode = fb_modedb,
394 .num_modes = ARRAY_SIZE(fb_modedb), 381 .num_modes = ARRAY_SIZE(fb_modedb),
@@ -496,7 +483,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
496 483
497static struct platform_device *devices[] __initdata = { 484static struct platform_device *devices[] __initdata = {
498 &armadillo5x0_smc911x_device, 485 &armadillo5x0_smc911x_device,
499 &armadillo5x0_button_device,
500}; 486};
501 487
502/* 488/*
@@ -508,6 +494,7 @@ static void __init armadillo5x0_init(void)
508 ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); 494 ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
509 495
510 platform_add_devices(devices, ARRAY_SIZE(devices)); 496 platform_add_devices(devices, ARRAY_SIZE(devices));
497 imx_add_gpio_keys(&armadillo5x0_button_data);
511 imx31_add_imx_i2c1(NULL); 498 imx31_add_imx_i2c1(NULL);
512 499
513 /* Register UART */ 500 /* Register UART */
@@ -521,8 +508,8 @@ static void __init armadillo5x0_init(void)
521 imx31_add_mxc_mmc(0, &sdhc_pdata); 508 imx31_add_mxc_mmc(0, &sdhc_pdata);
522 509
523 /* Register FB */ 510 /* Register FB */
524 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 511 imx31_add_ipu_core(&mx3_ipu_data);
525 mxc_register_device(&mx3_fb, &mx3fb_pdata); 512 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
526 513
527 /* Register NOR Flash */ 514 /* Register NOR Flash */
528 mxc_register_device(&armadillo5x0_nor_flash, 515 mxc_register_device(&armadillo5x0_nor_flash,
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index d137d7078ee9..42e4f078a19c 100644
--- a/arch/arm/mach-mx3/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -20,7 +20,6 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21 21
22#include <mach/iomux-mx3.h> 22#include <mach/iomux-mx3.h>
23#include <mach/imx-uart.h>
24#include <mach/hardware.h> 23#include <mach/hardware.h>
25#include <mach/common.h> 24#include <mach/common.h>
26 25
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 759299bb035b..46a2e41d43d2 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -38,7 +38,6 @@
38#include <mach/common.h> 38#include <mach/common.h>
39#include <mach/hardware.h> 39#include <mach/hardware.h>
40#include <mach/iomux-mx27.h> 40#include <mach/iomux-mx27.h>
41#include <mach/mxc_nand.h>
42#include <mach/ulpi.h> 41#include <mach/ulpi.h>
43 42
44#include "devices-imx27.h" 43#include "devices-imx27.h"
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index ec63d998f647..3f8ef825fa6f 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -41,10 +41,8 @@
41#include <mach/hardware.h> 41#include <mach/hardware.h>
42#include <mach/common.h> 42#include <mach/common.h>
43#include <mach/iomux-mx35.h> 43#include <mach/iomux-mx35.h>
44#include <mach/mxc_nand.h>
45 44
46#include "devices-imx35.h" 45#include "devices-imx35.h"
47#include "devices.h"
48 46
49static const struct imxuart_platform_data uart_pdata __initconst = { 47static const struct imxuart_platform_data uart_pdata __initconst = {
50 .flags = IMXUART_HAVE_RTSCTS, 48 .flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 9da8d18eeb00..148cff2819b9 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -36,8 +36,6 @@
36#include <asm/mach/map.h> 36#include <asm/mach/map.h>
37#include <mach/common.h> 37#include <mach/common.h>
38#include <mach/mx25.h> 38#include <mach/mx25.h>
39#include <mach/mxc_nand.h>
40#include <mach/imxfb.h>
41#include <mach/iomux-mx25.h> 39#include <mach/iomux-mx25.h>
42 40
43#include "devices-imx25.h" 41#include "devices-imx25.h"
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index d7e0d219726a..7ae43b1ec517 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -27,7 +27,6 @@
27#include <linux/mtd/physmap.h> 27#include <linux/mtd/physmap.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/i2c/pca953x.h> 29#include <linux/i2c/pca953x.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h> 30#include <linux/input.h>
32#include <linux/gpio.h> 31#include <linux/gpio.h>
33#include <linux/delay.h> 32#include <linux/delay.h>
@@ -130,19 +129,12 @@ static struct gpio_keys_button visstrim_gpio_keys[] = {
130 } 129 }
131}; 130};
132 131
133static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = { 132static const struct gpio_keys_platform_data
133 visstrim_gpio_keys_platform_data __initconst = {
134 .buttons = visstrim_gpio_keys, 134 .buttons = visstrim_gpio_keys,
135 .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), 135 .nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
136}; 136};
137 137
138static struct platform_device visstrim_gpio_keys_device = {
139 .name = "gpio-keys",
140 .id = -1,
141 .dev = {
142 .platform_data = &visstrim_gpio_keys_platform_data,
143 },
144};
145
146/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ 138/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
147static int visstrim_m10_sdhc1_init(struct device *dev, 139static int visstrim_m10_sdhc1_init(struct device *dev,
148 irq_handler_t detect_irq, void *data) 140 irq_handler_t detect_irq, void *data)
@@ -186,7 +178,6 @@ static struct platform_device visstrim_m10_nor_mtd_device = {
186}; 178};
187 179
188static struct platform_device *platform_devices[] __initdata = { 180static struct platform_device *platform_devices[] __initdata = {
189 &visstrim_gpio_keys_device,
190 &visstrim_m10_nor_mtd_device, 181 &visstrim_m10_nor_mtd_device,
191}; 182};
192 183
@@ -255,6 +246,7 @@ static void __init visstrim_m10_board_init(void)
255 imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); 246 imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
256 imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); 247 imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
257 imx27_add_fec(NULL); 248 imx27_add_fec(NULL);
249 imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
258 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 250 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
259} 251}
260 252
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index d35621d62b4d..1ecae20cf4e3 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -39,7 +39,6 @@
39#include <mach/iomux-mx3.h> 39#include <mach/iomux-mx3.h>
40 40
41#include "devices-imx31.h" 41#include "devices-imx31.h"
42#include "devices.h"
43 42
44#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ 43#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
45 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ 44 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 47cf56ac6d5b..38ec5cbbda9b 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -25,7 +25,6 @@
25 25
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/i2c.h>
29#include <mach/iomux-mx1.h> 28#include <mach/iomux-mx1.h>
30#include <mach/irqs.h> 29#include <mach/irqs.h>
31 30
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index fa52a1086eae..74ac88978ddd 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -25,7 +25,6 @@
25#include <asm/mach/time.h> 25#include <asm/mach/time.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27#include <mach/iomux-mx21.h> 27#include <mach/iomux-mx21.h>
28#include <mach/mxc_nand.h>
29 28
30#include "devices-imx21.h" 29#include "devices-imx21.h"
31 30
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 06da438282aa..58ea3fdf0911 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -29,7 +29,6 @@
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/input/matrix_keypad.h>
33#include <linux/usb/otg.h> 32#include <linux/usb/otg.h>
34 33
35#include <mach/hardware.h> 34#include <mach/hardware.h>
@@ -103,6 +102,8 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
103 MX25_PAD_SD1_DATA1__SD1_DATA1, 102 MX25_PAD_SD1_DATA1__SD1_DATA1,
104 MX25_PAD_SD1_DATA2__SD1_DATA2, 103 MX25_PAD_SD1_DATA2__SD1_DATA2,
105 MX25_PAD_SD1_DATA3__SD1_DATA3, 104 MX25_PAD_SD1_DATA3__SD1_DATA3,
105 MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
106 MX25_PAD_A15__GPIO_2_1, /* CardDetect */
106 107
107 /* I2C1 */ 108 /* I2C1 */
108 MX25_PAD_I2C1_CLK__I2C1_CLK, 109 MX25_PAD_I2C1_CLK__I2C1_CLK,
@@ -208,6 +209,14 @@ static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
208 .bitrate = 100000, 209 .bitrate = 100000,
209}; 210};
210 211
212#define SD1_GPIO_WP IMX_GPIO_NR(2, 0)
213#define SD1_GPIO_CD IMX_GPIO_NR(2, 1)
214
215static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
216 .wp_gpio = SD1_GPIO_WP,
217 .cd_gpio = SD1_GPIO_CD,
218};
219
211static void __init mx25pdk_init(void) 220static void __init mx25pdk_init(void)
212{ 221{
213 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, 222 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -225,7 +234,7 @@ static void __init mx25pdk_init(void)
225 imx25_add_fec(&mx25_fec_pdata); 234 imx25_add_fec(&mx25_fec_pdata);
226 imx25_add_imx_keypad(&mx25pdk_keymap_data); 235 imx25_add_imx_keypad(&mx25pdk_keymap_data);
227 236
228 imx25_add_sdhci_esdhc_imx(0, NULL); 237 imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
229 imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); 238 imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
230} 239}
231 240
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 367d1e4384c7..1db79506f5e4 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -29,7 +29,6 @@
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30#include <mach/gpio.h> 30#include <mach/gpio.h>
31#include <mach/iomux-mx27.h> 31#include <mach/iomux-mx27.h>
32#include <mach/mxc_nand.h>
33 32
34#include "devices-imx27.h" 33#include "devices-imx27.h"
35 34
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 034be624d35c..9b982449cb52 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -39,13 +39,8 @@
39#include <mach/iomux-mx3.h> 39#include <mach/iomux-mx3.h>
40#include <mach/3ds_debugboard.h> 40#include <mach/3ds_debugboard.h>
41#include <mach/ulpi.h> 41#include <mach/ulpi.h>
42#include <mach/mmc.h>
43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
45#include <mach/mx3_camera.h>
46 42
47#include "devices-imx31.h" 43#include "devices-imx31.h"
48#include "devices.h"
49 44
50/* CPLD IRQ line for external uart, external ethernet etc */ 45/* CPLD IRQ line for external uart, external ethernet etc */
51#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) 46#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
@@ -178,22 +173,37 @@ static struct gpio mx31_3ds_camera_gpios[] = {
178 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, 173 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
179}; 174};
180 175
181static int __init mx31_3ds_camera_alloc_dma(void) 176static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
177 .flags = MX3_CAMERA_DATAWIDTH_10,
178 .mclk_10khz = 2600,
179};
180
181static int __init mx31_3ds_init_camera(void)
182{ 182{
183 int dma; 183 int dma, ret = -ENOMEM;
184 struct platform_device *pdev =
185 imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
186
187 if (IS_ERR(pdev))
188 return PTR_ERR(pdev);
184 189
185 if (!mx3_camera_base) 190 if (!mx3_camera_base)
186 return -ENOMEM; 191 goto err;
187 192
188 dma = dma_declare_coherent_memory(&mx3_camera.dev, 193 dma = dma_declare_coherent_memory(&pdev->dev,
189 mx3_camera_base, mx3_camera_base, 194 mx3_camera_base, mx3_camera_base,
190 MX31_3DS_CAMERA_BUF_SIZE, 195 MX31_3DS_CAMERA_BUF_SIZE,
191 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); 196 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
192 197
193 if (!(dma & DMA_MEMORY_MAP)) 198 if (!(dma & DMA_MEMORY_MAP))
194 return -ENOMEM; 199 goto err;
195 200
196 return 0; 201 ret = platform_device_add(pdev);
202 if (ret)
203err:
204 platform_device_put(pdev);
205
206 return ret;
197} 207}
198 208
199static int mx31_3ds_camera_power(struct device *dev, int on) 209static int mx31_3ds_camera_power(struct device *dev, int on)
@@ -241,12 +251,6 @@ static struct platform_device mx31_3ds_ov2640 = {
241 }, 251 },
242}; 252};
243 253
244struct mx3_camera_pdata mx31_3ds_camera_pdata = {
245 .dma_dev = &mx3_ipu.dev,
246 .flags = MX3_CAMERA_DATAWIDTH_10,
247 .mclk_10khz = 2600,
248};
249
250/* 254/*
251 * FB support 255 * FB support
252 */ 256 */
@@ -273,8 +277,7 @@ static struct ipu_platform_data mx3_ipu_data = {
273 .irq_base = MXC_IPU_IRQ_START, 277 .irq_base = MXC_IPU_IRQ_START,
274}; 278};
275 279
276static struct mx3fb_platform_data mx3fb_pdata = { 280static struct mx3fb_platform_data mx3fb_pdata __initdata = {
277 .dma_dev = &mx3_ipu.dev,
278 .name = "Epson-VGA", 281 .name = "Epson-VGA",
279 .mode = fb_modedb, 282 .mode = fb_modedb,
280 .num_modes = ARRAY_SIZE(fb_modedb), 283 .num_modes = ARRAY_SIZE(fb_modedb),
@@ -723,8 +726,8 @@ static void __init mx31_3ds_init(void)
723 imx31_add_mxc_mmc(0, &sdhc1_pdata); 726 imx31_add_mxc_mmc(0, &sdhc1_pdata);
724 727
725 imx31_add_spi_imx0(&spi0_pdata); 728 imx31_add_spi_imx0(&spi0_pdata);
726 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 729 imx31_add_ipu_core(&mx3_ipu_data);
727 mxc_register_device(&mx3_fb, &mx3fb_pdata); 730 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
728 731
729 /* CSI */ 732 /* CSI */
730 /* Camera power: default - off */ 733 /* Camera power: default - off */
@@ -735,10 +738,7 @@ static void __init mx31_3ds_init(void)
735 iclink_ov2640.power = NULL; 738 iclink_ov2640.power = NULL;
736 } 739 }
737 740
738 if (!mx31_3ds_camera_alloc_dma()) 741 mx31_3ds_init_camera();
739 mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
740 else
741 pr_err("Failed to allocate dma memory for camera");
742} 742}
743 743
744static void __init mx31_3ds_timer_init(void) 744static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 3d095d69bc68..f4dee0254634 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -38,7 +38,6 @@
38#endif 38#endif
39 39
40#include "devices-imx31.h" 40#include "devices-imx31.h"
41#include "devices.h"
42 41
43/* PBC Board interrupt status register */ 42/* PBC Board interrupt status register */
44#define PBC_INTSTATUS 0x000016 43#define PBC_INTSTATUS 0x000016
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index ed95745163b8..410e676ae087 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -46,7 +46,6 @@
46#include <mach/ulpi.h> 46#include <mach/ulpi.h>
47 47
48#include "devices-imx31.h" 48#include "devices-imx31.h"
49#include "devices.h"
50 49
51/* 50/*
52 * This file contains module-specific initialization routines for LILLY-1131. 51 * This file contains module-specific initialization routines for LILLY-1131.
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 24a21a384bf1..ac9b4cad320e 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -44,7 +44,6 @@
44#include <mach/ulpi.h> 44#include <mach/ulpi.h>
45 45
46#include "devices-imx31.h" 46#include "devices-imx31.h"
47#include "devices.h"
48 47
49/* 48/*
50 * This file contains the module-specific initialization routines. 49 * This file contains the module-specific initialization routines.
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 3a021b01161d..eaa51e49ca95 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -27,6 +27,7 @@
27#include <linux/mfd/mc13783.h> 27#include <linux/mfd/mc13783.h>
28#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
29#include <linux/types.h> 29#include <linux/types.h>
30#include <linux/memblock.h>
30 31
31#include <linux/usb/otg.h> 32#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h> 33#include <linux/usb/ulpi.h>
@@ -39,13 +40,9 @@
39#include <mach/common.h> 40#include <mach/common.h>
40#include <mach/hardware.h> 41#include <mach/hardware.h>
41#include <mach/iomux-mx3.h> 42#include <mach/iomux-mx3.h>
42#include <mach/ipu.h>
43#include <mach/mx3_camera.h>
44#include <mach/spi.h>
45#include <mach/ulpi.h> 43#include <mach/ulpi.h>
46 44
47#include "devices-imx31.h" 45#include "devices-imx31.h"
48#include "devices.h"
49 46
50static unsigned int moboard_pins[] = { 47static unsigned int moboard_pins[] = {
51 /* UART0 */ 48 /* UART0 */
@@ -102,7 +99,7 @@ static unsigned int moboard_pins[] = {
102}; 99};
103 100
104static struct physmap_flash_data mx31moboard_flash_data = { 101static struct physmap_flash_data mx31moboard_flash_data = {
105 .width = 2, 102 .width = 2,
106}; 103};
107 104
108static struct resource mx31moboard_flash_resource = { 105static struct resource mx31moboard_flash_resource = {
@@ -194,8 +191,8 @@ static struct regulator_init_data sdhc_vreg_data = {
194 191
195static struct regulator_consumer_supply cam_consumers[] = { 192static struct regulator_consumer_supply cam_consumers[] = {
196 { 193 {
197 .dev = &mx3_camera.dev, 194 .dev_name = "mx3_camera.0",
198 .supply = "cam_vcc", 195 .supply = "cam_vcc",
199 }, 196 },
200}; 197};
201 198
@@ -430,9 +427,9 @@ static int __init moboard_usbh2_init(void)
430 427
431static struct gpio_led mx31moboard_leds[] = { 428static struct gpio_led mx31moboard_leds[] = {
432 { 429 {
433 .name = "coreboard-led-0:red:running", 430 .name = "coreboard-led-0:red:running",
434 .default_trigger = "heartbeat", 431 .default_trigger = "heartbeat",
435 .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), 432 .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
436 }, { 433 }, {
437 .name = "coreboard-led-1:red", 434 .name = "coreboard-led-1:red",
438 .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0), 435 .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
@@ -446,7 +443,7 @@ static struct gpio_led mx31moboard_leds[] = {
446}; 443};
447 444
448static struct gpio_led_platform_data mx31moboard_led_pdata = { 445static struct gpio_led_platform_data mx31moboard_led_pdata = {
449 .num_leds = ARRAY_SIZE(mx31moboard_leds), 446 .num_leds = ARRAY_SIZE(mx31moboard_leds),
450 .leds = mx31moboard_leds, 447 .leds = mx31moboard_leds,
451}; 448};
452 449
@@ -458,7 +455,7 @@ static struct platform_device mx31moboard_leds_device = {
458 }, 455 },
459}; 456};
460 457
461static struct ipu_platform_data mx3_ipu_data = { 458static const struct ipu_platform_data mx3_ipu_data __initconst = {
462 .irq_base = MXC_IPU_IRQ_START, 459 .irq_base = MXC_IPU_IRQ_START,
463}; 460};
464 461
@@ -467,37 +464,39 @@ static struct platform_device *devices[] __initdata = {
467 &mx31moboard_leds_device, 464 &mx31moboard_leds_device,
468}; 465};
469 466
470static struct mx3_camera_pdata camera_pdata = { 467static struct mx3_camera_pdata camera_pdata __initdata = {
471 .dma_dev = &mx3_ipu.dev,
472 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, 468 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
473 .mclk_10khz = 4800, 469 .mclk_10khz = 4800,
474}; 470};
475 471
476#define CAMERA_BUF_SIZE (4*1024*1024) 472static phys_addr_t mx3_camera_base __initdata;
473#define MX3_CAMERA_BUF_SIZE SZ_4M
477 474
478static int __init mx31moboard_cam_alloc_dma(const size_t buf_size) 475static int __init mx31moboard_init_cam(void)
479{ 476{
480 dma_addr_t dma_handle; 477 int dma, ret = -ENOMEM;
481 void *buf; 478 struct platform_device *pdev;
482 int dma;
483
484 if (buf_size < 2 * 1024 * 1024)
485 return -EINVAL;
486 479
487 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); 480 imx31_add_ipu_core(&mx3_ipu_data);
488 if (!buf) {
489 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
490 return -ENOMEM;
491 }
492 481
493 memset(buf, 0, buf_size); 482 pdev = imx31_alloc_mx3_camera(&camera_pdata);
483 if (IS_ERR(pdev))
484 return PTR_ERR(pdev);
494 485
495 dma = dma_declare_coherent_memory(&mx3_camera.dev, 486 dma = dma_declare_coherent_memory(&pdev->dev,
496 dma_handle, dma_handle, buf_size, 487 mx3_camera_base, mx3_camera_base,
488 MX3_CAMERA_BUF_SIZE,
497 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); 489 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
490 if (!(dma & DMA_MEMORY_MAP))
491 goto err;
492
493 ret = platform_device_add(pdev);
494 if (ret)
495err:
496 platform_device_put(pdev);
497
498 return ret;
498 499
499 /* The way we call dma_declare_coherent_memory only a malloc can fail */
500 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
501} 500}
502 501
503static int mx31moboard_baseboard; 502static int mx31moboard_baseboard;
@@ -529,9 +528,7 @@ static void __init mx31moboard_init(void)
529 528
530 imx31_add_mxc_mmc(0, &sdhc1_pdata); 529 imx31_add_mxc_mmc(0, &sdhc1_pdata);
531 530
532 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 531 mx31moboard_init_cam();
533 if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
534 mxc_register_device(&mx3_camera, &camera_pdata);
535 532
536 usb_xcvr_reset(); 533 usb_xcvr_reset();
537 534
@@ -565,9 +562,19 @@ struct sys_timer mx31moboard_timer = {
565 .init = mx31moboard_timer_init, 562 .init = mx31moboard_timer_init,
566}; 563};
567 564
565static void __init mx31moboard_reserve(void)
566{
567 /* reserve 4 MiB for mx3-camera */
568 mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
569 MX3_CAMERA_BUF_SIZE);
570 memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
571 memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
572}
573
568MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 574MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
569 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 575 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
570 .boot_params = MX3x_PHYS_OFFSET + 0x100, 576 .boot_params = MX3x_PHYS_OFFSET + 0x100,
577 .reserve = mx31moboard_reserve,
571 .map_io = mx31_map_io, 578 .map_io = mx31_map_io,
572 .init_early = imx31_init_early, 579 .init_early = imx31_init_early,
573 .init_irq = mx31_init_irq, 580 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index ff5fe231b8d6..882880ac1bbc 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -42,7 +42,6 @@
42#include <mach/3ds_debugboard.h> 42#include <mach/3ds_debugboard.h>
43 43
44#include "devices-imx35.h" 44#include "devices-imx35.h"
45#include "devices.h"
46 45
47#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1) 46#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
48 47
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 69787c30c320..2774541511e7 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -29,7 +29,6 @@
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <mach/iomux-mx27.h> 31#include <mach/iomux-mx27.h>
32#include <mach/mxc_nand.h>
33#include <linux/i2c/pca953x.h> 32#include <linux/i2c/pca953x.h>
34 33
35#include "devices-imx27.h" 34#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 63e182556778..bbddc5a11c43 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -37,7 +37,6 @@
37#include <mach/iomux-mx27.h> 37#include <mach/iomux-mx27.h>
38#include <asm/mach/time.h> 38#include <asm/mach/time.h>
39#include <mach/audmux.h> 39#include <mach/audmux.h>
40#include <mach/mxc_nand.h>
41#include <mach/irqs.h> 40#include <mach/irqs.h>
42#include <mach/ulpi.h> 41#include <mach/ulpi.h>
43 42
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index f07d3bded674..89c213b81295 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -31,6 +31,7 @@
31#include <linux/usb/otg.h> 31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h> 32#include <linux/usb/ulpi.h>
33#include <linux/gfp.h> 33#include <linux/gfp.h>
34#include <linux/memblock.h>
34 35
35#include <media/soc_camera.h> 36#include <media/soc_camera.h>
36 37
@@ -41,13 +42,9 @@
41#include <mach/common.h> 42#include <mach/common.h>
42#include <mach/hardware.h> 43#include <mach/hardware.h>
43#include <mach/iomux-mx3.h> 44#include <mach/iomux-mx3.h>
44#include <mach/ipu.h>
45#include <mach/mx3_camera.h>
46#include <mach/mx3fb.h>
47#include <mach/ulpi.h> 45#include <mach/ulpi.h>
48 46
49#include "devices-imx31.h" 47#include "devices-imx31.h"
50#include "devices.h"
51#include "pcm037.h" 48#include "pcm037.h"
52 49
53static enum pcm037_board_variant pcm037_instance = PCM037_PCM970; 50static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
@@ -404,35 +401,35 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
404 .exit = pcm970_sdhc1_exit, 401 .exit = pcm970_sdhc1_exit,
405}; 402};
406 403
407struct mx3_camera_pdata camera_pdata = { 404struct mx3_camera_pdata camera_pdata __initdata = {
408 .dma_dev = &mx3_ipu.dev,
409 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, 405 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
410 .mclk_10khz = 2000, 406 .mclk_10khz = 2000,
411}; 407};
412 408
413static int __init pcm037_camera_alloc_dma(const size_t buf_size) 409static phys_addr_t mx3_camera_base __initdata;
414{ 410#define MX3_CAMERA_BUF_SIZE SZ_4M
415 dma_addr_t dma_handle;
416 void *buf;
417 int dma;
418
419 if (buf_size < 2 * 1024 * 1024)
420 return -EINVAL;
421 411
422 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); 412static int __init pcm037_init_camera(void)
423 if (!buf) { 413{
424 pr_err("%s: cannot allocate camera buffer-memory\n", __func__); 414 int dma, ret = -ENOMEM;
425 return -ENOMEM; 415 struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
426 }
427 416
428 memset(buf, 0, buf_size); 417 if (IS_ERR(pdev))
418 return PTR_ERR(pdev);
429 419
430 dma = dma_declare_coherent_memory(&mx3_camera.dev, 420 dma = dma_declare_coherent_memory(&pdev->dev,
431 dma_handle, dma_handle, buf_size, 421 mx3_camera_base, mx3_camera_base,
422 MX3_CAMERA_BUF_SIZE,
432 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); 423 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
424 if (!(dma & DMA_MEMORY_MAP))
425 goto err;
426
427 ret = platform_device_add(pdev);
428 if (ret)
429err:
430 platform_device_put(pdev);
433 431
434 /* The way we call dma_declare_coherent_memory only a malloc can fail */ 432 return ret;
435 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
436} 433}
437 434
438static struct platform_device *devices[] __initdata = { 435static struct platform_device *devices[] __initdata = {
@@ -442,7 +439,7 @@ static struct platform_device *devices[] __initdata = {
442 &pcm037_mt9v022, 439 &pcm037_mt9v022,
443}; 440};
444 441
445static struct ipu_platform_data mx3_ipu_data = { 442static const struct ipu_platform_data mx3_ipu_data __initconst = {
446 .irq_base = MXC_IPU_IRQ_START, 443 .irq_base = MXC_IPU_IRQ_START,
447}; 444};
448 445
@@ -500,7 +497,6 @@ static const struct fb_videomode fb_modedb[] = {
500}; 497};
501 498
502static struct mx3fb_platform_data mx3fb_pdata = { 499static struct mx3fb_platform_data mx3fb_pdata = {
503 .dma_dev = &mx3_ipu.dev,
504 .name = "Sharp-LQ035Q7DH06-QVGA", 500 .name = "Sharp-LQ035Q7DH06-QVGA",
505 .mode = fb_modedb, 501 .mode = fb_modedb,
506 .num_modes = ARRAY_SIZE(fb_modedb), 502 .num_modes = ARRAY_SIZE(fb_modedb),
@@ -638,8 +634,8 @@ static void __init pcm037_init(void)
638 634
639 imx31_add_mxc_nand(&pcm037_nand_board_info); 635 imx31_add_mxc_nand(&pcm037_nand_board_info);
640 imx31_add_mxc_mmc(0, &sdhc_pdata); 636 imx31_add_mxc_mmc(0, &sdhc_pdata);
641 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 637 imx31_add_ipu_core(&mx3_ipu_data);
642 mxc_register_device(&mx3_fb, &mx3fb_pdata); 638 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
643 639
644 /* CSI */ 640 /* CSI */
645 /* Camera power: default - off */ 641 /* Camera power: default - off */
@@ -649,8 +645,7 @@ static void __init pcm037_init(void)
649 else 645 else
650 iclink_mt9t031.power = NULL; 646 iclink_mt9t031.power = NULL;
651 647
652 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024)) 648 pcm037_init_camera();
653 mxc_register_device(&mx3_camera, &camera_pdata);
654 649
655 platform_device_register(&pcm970_sja1000); 650 platform_device_register(&pcm970_sja1000);
656 651
@@ -680,9 +675,19 @@ struct sys_timer pcm037_timer = {
680 .init = pcm037_timer_init, 675 .init = pcm037_timer_init,
681}; 676};
682 677
678static void __init pcm037_reserve(void)
679{
680 /* reserve 4 MiB for mx3-camera */
681 mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
682 MX3_CAMERA_BUF_SIZE);
683 memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
684 memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
685}
686
683MACHINE_START(PCM037, "Phytec Phycore pcm037") 687MACHINE_START(PCM037, "Phytec Phycore pcm037")
684 /* Maintainer: Pengutronix */ 688 /* Maintainer: Pengutronix */
685 .boot_params = MX3x_PHYS_OFFSET + 0x100, 689 .boot_params = MX3x_PHYS_OFFSET + 0x100,
690 .reserve = pcm037_reserve,
686 .map_io = mx31_map_io, 691 .map_io = mx31_map_io,
687 .init_early = imx31_init_early, 692 .init_early = imx31_init_early,
688 .init_irq = mx31_init_irq, 693 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index df6fb07d037e..1b7606bef8f4 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -7,19 +7,16 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9#include <linux/gpio.h> 9#include <linux/gpio.h>
10#include <linux/gpio_keys.h>
11#include <linux/input.h> 10#include <linux/input.h>
12#include <linux/platform_device.h> 11#include <linux/platform_device.h>
13#include <linux/spi/spi.h> 12#include <linux/spi/spi.h>
14 13
15#include <mach/common.h> 14#include <mach/common.h>
16#include <mach/iomux-mx3.h> 15#include <mach/iomux-mx3.h>
17#include <mach/spi.h>
18 16
19#include <asm/mach-types.h> 17#include <asm/mach-types.h>
20 18
21#include "pcm037.h" 19#include "pcm037.h"
22#include "devices.h"
23#include "devices-imx31.h" 20#include "devices-imx31.h"
24 21
25static unsigned int pcm037_eet_pins[] = { 22static unsigned int pcm037_eet_pins[] = {
@@ -156,20 +153,13 @@ static struct gpio_keys_button pcm037_gpio_keys[] = {
156 }, 153 },
157}; 154};
158 155
159static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = { 156static const struct gpio_keys_platform_data
157 pcm037_gpio_keys_platform_data __initconst = {
160 .buttons = pcm037_gpio_keys, 158 .buttons = pcm037_gpio_keys,
161 .nbuttons = ARRAY_SIZE(pcm037_gpio_keys), 159 .nbuttons = ARRAY_SIZE(pcm037_gpio_keys),
162 .rep = 0, /* No auto-repeat */ 160 .rep = 0, /* No auto-repeat */
163}; 161};
164 162
165static struct platform_device pcm037_gpio_keys_device = {
166 .name = "gpio-keys",
167 .id = -1,
168 .dev = {
169 .platform_data = &pcm037_gpio_keys_platform_data,
170 },
171};
172
173static int __init eet_init_devices(void) 163static int __init eet_init_devices(void)
174{ 164{
175 if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET) 165 if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
@@ -182,9 +172,8 @@ static int __init eet_init_devices(void)
182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); 172 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
183 imx31_add_spi_imx0(&pcm037_spi1_pdata); 173 imx31_add_spi_imx0(&pcm037_spi1_pdata);
184 174
185 platform_device_register(&pcm037_gpio_keys_device); 175 imx_add_gpio_keys(&pcm037_gpio_keys_platform_data);
186 176
187 return 0; 177 return 0;
188} 178}
189
190late_initcall(eet_init_devices); 179late_initcall(eet_init_devices);
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 4cbce6d0fef1..853bb871c7ed 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -36,7 +36,6 @@
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/iomux-mx27.h> 38#include <mach/iomux-mx27.h>
39#include <mach/mxc_nand.h>
40#include <mach/ulpi.h> 39#include <mach/ulpi.h>
41 40
42#include "devices-imx27.h" 41#include "devices-imx27.h"
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 036ba1a4704b..026441628dfa 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -36,14 +36,10 @@
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/common.h> 37#include <mach/common.h>
38#include <mach/iomux-mx35.h> 38#include <mach/iomux-mx35.h>
39#include <mach/ipu.h>
40#include <mach/mx3fb.h>
41#include <mach/ulpi.h> 39#include <mach/ulpi.h>
42#include <mach/audmux.h> 40#include <mach/audmux.h>
43#include <mach/esdhc.h>
44 41
45#include "devices-imx35.h" 42#include "devices-imx35.h"
46#include "devices.h"
47 43
48static const struct fb_videomode fb_modedb[] = { 44static const struct fb_videomode fb_modedb[] = {
49 { 45 {
@@ -81,12 +77,11 @@ static const struct fb_videomode fb_modedb[] = {
81 }, 77 },
82}; 78};
83 79
84static struct ipu_platform_data mx3_ipu_data = { 80static const struct ipu_platform_data mx3_ipu_data __initconst = {
85 .irq_base = MXC_IPU_IRQ_START, 81 .irq_base = MXC_IPU_IRQ_START,
86}; 82};
87 83
88static struct mx3fb_platform_data mx3fb_pdata = { 84static struct mx3fb_platform_data mx3fb_pdata __initdata = {
89 .dma_dev = &mx3_ipu.dev,
90 .name = "Sharp-LQ035Q7", 85 .name = "Sharp-LQ035Q7",
91 .mode = fb_modedb, 86 .mode = fb_modedb,
92 .num_modes = ARRAY_SIZE(fb_modedb), 87 .num_modes = ARRAY_SIZE(fb_modedb),
@@ -127,12 +122,12 @@ static struct at24_platform_data board_eeprom = {
127}; 122};
128 123
129static struct i2c_board_info pcm043_i2c_devices[] = { 124static struct i2c_board_info pcm043_i2c_devices[] = {
130 { 125 {
131 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ 126 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
132 .platform_data = &board_eeprom, 127 .platform_data = &board_eeprom,
133 }, { 128 }, {
134 I2C_BOARD_INFO("pcf8563", 0x51), 129 I2C_BOARD_INFO("pcf8563", 0x51),
135 } 130 },
136}; 131};
137 132
138static struct platform_device *devices[] __initdata = { 133static struct platform_device *devices[] __initdata = {
@@ -390,8 +385,8 @@ static void __init pcm043_init(void)
390 385
391 imx35_add_imx_i2c0(&pcm043_i2c0_data); 386 imx35_add_imx_i2c0(&pcm043_i2c0_data);
392 387
393 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 388 imx35_add_ipu_core(&mx3_ipu_data);
394 mxc_register_device(&mx3_fb, &mx3fb_pdata); 389 imx35_add_mx3_sdc_fb(&mx3fb_pdata);
395 390
396 if (otg_mode_host) { 391 if (otg_mode_host) {
397 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | 392 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 17f758b77623..c16328715939 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -33,24 +33,23 @@
33#include <mach/iomux-mx3.h> 33#include <mach/iomux-mx3.h>
34 34
35#include "devices-imx31.h" 35#include "devices-imx31.h"
36#include "devices.h"
37 36
38/* FPGA defines */ 37/* FPGA defines */
39#define QONG_FPGA_VERSION(major, minor, rev) \ 38#define QONG_FPGA_VERSION(major, minor, rev) \
40 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) 39 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
41 40
42#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR 41#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
43#define QONG_FPGA_PERIPH_SIZE (1 << 24) 42#define QONG_FPGA_PERIPH_SIZE (1 << 24)
44 43
45#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR 44#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
46#define QONG_FPGA_CTRL_SIZE 0x10 45#define QONG_FPGA_CTRL_SIZE 0x10
47/* FPGA control registers */ 46/* FPGA control registers */
48#define QONG_FPGA_CTRL_VERSION 0x00 47#define QONG_FPGA_CTRL_VERSION 0x00
49 48
50#define QONG_DNET_ID 1 49#define QONG_DNET_ID 1
51#define QONG_DNET_BASEADDR \ 50#define QONG_DNET_BASEADDR \
52 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE) 51 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
53#define QONG_DNET_SIZE 0x00001000 52#define QONG_DNET_SIZE 0x00001000
54 53
55#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) 54#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
56 55
@@ -166,15 +165,15 @@ static struct platform_nand_data qong_nand_data = {
166 .options = 0, 165 .options = 0,
167 }, 166 },
168 .ctrl = { 167 .ctrl = {
169 .cmd_ctrl = qong_nand_cmd_ctrl, 168 .cmd_ctrl = qong_nand_cmd_ctrl,
170 .dev_ready = qong_nand_device_ready, 169 .dev_ready = qong_nand_device_ready,
171 .select_chip = qong_nand_select_chip, 170 .select_chip = qong_nand_select_chip,
172 } 171 }
173}; 172};
174 173
175static struct resource qong_nand_resource = { 174static struct resource qong_nand_resource = {
176 .start = MX31_CS3_BASE_ADDR, 175 .start = MX31_CS3_BASE_ADDR,
177 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, 176 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
178 .flags = IORESOURCE_MEM, 177 .flags = IORESOURCE_MEM,
179}; 178};
180 179
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 47a69cbc31a8..d74e3473d236 100644
--- a/arch/arm/mach-mx3/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -32,16 +32,12 @@
32#include <mach/common.h> 32#include <mach/common.h>
33#include <mach/iomux-mx35.h> 33#include <mach/iomux-mx35.h>
34#include <mach/irqs.h> 34#include <mach/irqs.h>
35#include <mach/ipu.h>
36#include <mach/mx3fb.h>
37 35
38#include <linux/i2c.h> 36#include <linux/i2c.h>
39#include <linux/i2c/at24.h> 37#include <linux/i2c/at24.h>
40#include <linux/mfd/mc13xxx.h> 38#include <linux/mfd/mc13xxx.h>
41#include <linux/gpio_keys.h>
42 39
43#include "devices-imx35.h" 40#include "devices-imx35.h"
44#include "devices.h"
45 41
46#define GPIO_LCDPWR IMX_GPIO_NR(1, 2) 42#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
47#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) 43#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
@@ -91,12 +87,11 @@ static const struct fb_videomode fb_modedb[] = {
91 } 87 }
92}; 88};
93 89
94static struct ipu_platform_data mx3_ipu_data = { 90static const struct ipu_platform_data mx3_ipu_data __initconst = {
95 .irq_base = MXC_IPU_IRQ_START, 91 .irq_base = MXC_IPU_IRQ_START,
96}; 92};
97 93
98static struct mx3fb_platform_data mx3fb_pdata = { 94static struct mx3fb_platform_data mx3fb_pdata __initdata = {
99 .dma_dev = &mx3_ipu.dev,
100 .name = "PT0708048", 95 .name = "PT0708048",
101 .mode = fb_modedb, 96 .mode = fb_modedb,
102 .num_modes = ARRAY_SIZE(fb_modedb), 97 .num_modes = ARRAY_SIZE(fb_modedb),
@@ -141,18 +136,12 @@ static struct gpio_keys_button vpr200_gpio_keys_table[] = {
141 {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE}, 136 {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
142}; 137};
143 138
144static struct gpio_keys_platform_data vpr200_gpio_keys_data = { 139static const struct gpio_keys_platform_data
140 vpr200_gpio_keys_data __initconst = {
145 .buttons = vpr200_gpio_keys_table, 141 .buttons = vpr200_gpio_keys_table,
146 .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table), 142 .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
147}; 143};
148 144
149static struct platform_device vpr200_device_gpiokeys = {
150 .name = "gpio-keys",
151 .dev = {
152 .platform_data = &vpr200_gpio_keys_data,
153 }
154};
155
156static struct mc13xxx_platform_data vpr200_pmic = { 145static struct mc13xxx_platform_data vpr200_pmic = {
157 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, 146 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
158}; 147};
@@ -271,7 +260,6 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
271 260
272static struct platform_device *devices[] __initdata = { 261static struct platform_device *devices[] __initdata = {
273 &vpr200_flash, 262 &vpr200_flash,
274 &vpr200_device_gpiokeys,
275}; 263};
276 264
277/* 265/*
@@ -283,6 +271,7 @@ static void __init vpr200_board_init(void)
283 271
284 imx35_add_fec(NULL); 272 imx35_add_fec(NULL);
285 imx35_add_imx2_wdt(NULL); 273 imx35_add_imx2_wdt(NULL);
274 imx_add_gpio_keys(&vpr200_gpio_keys_data);
286 275
287 platform_add_devices(devices, ARRAY_SIZE(devices)); 276 platform_add_devices(devices, ARRAY_SIZE(devices));
288 277
@@ -299,8 +288,8 @@ static void __init vpr200_board_init(void)
299 imx35_add_imx_uart0(NULL); 288 imx35_add_imx_uart0(NULL);
300 imx35_add_imx_uart2(NULL); 289 imx35_add_imx_uart2(NULL);
301 290
302 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 291 imx35_add_ipu_core(&mx3_ipu_data);
303 mxc_register_device(&mx3_fb, &mx3fb_pdata); 292 imx35_add_mx3_sdc_fb(&mx3fb_pdata);
304 293
305 imx35_add_fsl_usb2_udc(&otg_device_pdata); 294 imx35_add_fsl_usb2_udc(&otg_device_pdata);
306 imx35_add_mxc_ehci_hs(&usb_host_pdata); 295 imx35_add_mxc_ehci_hs(&usb_host_pdata);
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
new file mode 100644
index 000000000000..86b9b45864d2
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx31.c
@@ -0,0 +1,66 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/iomux-v3.h>
29#include <mach/gpio.h>
30#include <mach/irqs.h>
31
32static struct map_desc mx31_io_desc[] __initdata = {
33 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
34 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
35 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
36 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
38};
39
40/*
41 * This function initializes the memory map. It is called during the
42 * system startup to create static physical to virtual memory mappings
43 * for the IO modules.
44 */
45void __init mx31_map_io(void)
46{
47 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
48}
49
50void __init imx31_init_early(void)
51{
52 mxc_set_cpu_type(MXC_CPU_MX31);
53 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
54}
55
56static struct mxc_gpio_port imx31_gpio_ports[] = {
57 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
58 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
59 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
60};
61
62void __init mx31_init_irq(void)
63{
64 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
65 mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
66}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
new file mode 100644
index 000000000000..c880e6d1ae55
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx35.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25#include <asm/hardware/cache-l2x0.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-v3.h>
30#include <mach/gpio.h>
31#include <mach/irqs.h>
32
33static struct map_desc mx35_io_desc[] __initdata = {
34 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
35 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
36 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
38 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
39};
40
41void __init mx35_map_io(void)
42{
43 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
44}
45
46void __init imx35_init_early(void)
47{
48 mxc_set_cpu_type(MXC_CPU_MX35);
49 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
50 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
51}
52
53static struct mxc_gpio_port imx35_gpio_ports[] = {
54 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
55 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
56 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
57};
58
59void __init mx35_init_irq(void)
60{
61 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
62 mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
63}
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index 8f1a38ebf5c8..7d26f766a4ee 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -34,11 +34,8 @@
34#include <mach/common.h> 34#include <mach/common.h>
35#include <mach/iomux-mx3.h> 35#include <mach/iomux-mx3.h>
36#include <mach/board-mx31lilly.h> 36#include <mach/board-mx31lilly.h>
37#include <mach/mx3fb.h>
38#include <mach/ipu.h>
39 37
40#include "devices-imx31.h" 38#include "devices-imx31.h"
41#include "devices.h"
42 39
43/* 40/*
44 * This file contains board-specific initialization routines for the 41 * This file contains board-specific initialization routines for the
@@ -164,13 +161,13 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
164}; 161};
165 162
166/* Framebuffer support */ 163/* Framebuffer support */
167static struct ipu_platform_data ipu_data __initdata = { 164static const struct ipu_platform_data ipu_data __initconst = {
168 .irq_base = MXC_IPU_IRQ_START, 165 .irq_base = MXC_IPU_IRQ_START,
169}; 166};
170 167
171static const struct fb_videomode fb_modedb = { 168static const struct fb_videomode fb_modedb = {
172 /* 640x480 TFT panel (IPS-056T) */ 169 /* 640x480 TFT panel (IPS-056T) */
173 .name = "CRT-VGA", 170 .name = "CRT-VGA",
174 .refresh = 64, 171 .refresh = 64,
175 .xres = 640, 172 .xres = 640,
176 .yres = 480, 173 .yres = 480,
@@ -187,7 +184,6 @@ static const struct fb_videomode fb_modedb = {
187}; 184};
188 185
189static struct mx3fb_platform_data fb_pdata __initdata = { 186static struct mx3fb_platform_data fb_pdata __initdata = {
190 .dma_dev = &mx3_ipu.dev,
191 .name = "CRT-VGA", 187 .name = "CRT-VGA",
192 .mode = &fb_modedb, 188 .mode = &fb_modedb,
193 .num_modes = 1, 189 .num_modes = 1,
@@ -202,8 +198,8 @@ static void __init mx31lilly_init_fb(void)
202 return; 198 return;
203 } 199 }
204 200
205 mxc_register_device(&mx3_ipu, &ipu_data); 201 imx31_add_ipu_core(&ipu_data);
206 mxc_register_device(&mx3_fb, &fb_pdata); 202 imx31_add_mx3_sdc_fb(&fb_pdata);
207 gpio_direction_output(LCD_VCC_EN_GPIO, 1); 203 gpio_direction_output(LCD_VCC_EN_GPIO, 1);
208} 204}
209 205
@@ -218,4 +214,3 @@ void __init mx31lilly_db_init(void)
218 imx31_add_mxc_mmc(0, &mmc_pdata); 214 imx31_add_mxc_mmc(0, &mmc_pdata);
219 mx31lilly_init_fb(); 215 mx31lilly_init_fb();
220} 216}
221
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index 3124ea837ac7..5aa053edc17c 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -37,7 +37,6 @@
37#include <mach/board-mx31lite.h> 37#include <mach/board-mx31lite.h>
38 38
39#include "devices-imx31.h" 39#include "devices-imx31.h"
40#include "devices.h"
41 40
42/* 41/*
43 * This file contains board-specific initialization routines for the 42 * This file contains board-specific initialization routines for the
@@ -200,5 +199,5 @@ void __init mx31lite_db_init(void)
200 imx31_add_spi_imx0(&spi0_pdata); 199 imx31_add_spi_imx0(&spi0_pdata);
201 platform_device_register(&litekit_led_device); 200 platform_device_register(&litekit_led_device);
202 imx31_add_imx2_wdt(NULL); 201 imx31_add_imx2_wdt(NULL);
203 mxc_register_device(&imx_rtc_device0, NULL); 202 imx31_add_mxc_rtc(NULL);
204} 203}
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 6410b9c48a02..0aa25364360d 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -28,7 +28,6 @@
28#include <mach/ulpi.h> 28#include <mach/ulpi.h>
29 29
30#include "devices-imx31.h" 30#include "devices-imx31.h"
31#include "devices.h"
32 31
33static unsigned int devboard_pins[] = { 32static unsigned int devboard_pins[] = {
34 /* UART1 */ 33 /* UART1 */
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index 57f7b00cb709..bb639cbda4e5 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -26,14 +26,12 @@
26 26
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx3.h> 29#include <mach/iomux-mx3.h>
31#include <mach/ulpi.h> 30#include <mach/ulpi.h>
32 31
33#include <media/soc_camera.h> 32#include <media/soc_camera.h>
34 33
35#include "devices-imx31.h" 34#include "devices-imx31.h"
36#include "devices.h"
37 35
38static unsigned int marxbot_pins[] = { 36static unsigned int marxbot_pins[] = {
39 /* SDHC2 */ 37 /* SDHC2 */
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index 35f806e737c1..fabb801e7994 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -32,7 +32,6 @@
32#include <media/soc_camera.h> 32#include <media/soc_camera.h>
33 33
34#include "devices-imx31.h" 34#include "devices-imx31.h"
35#include "devices.h"
36 35
37static unsigned int smartbot_pins[] = { 36static unsigned int smartbot_pins[] = {
38 /* UART1 */ 37 /* UART1 */
diff --git a/arch/arm/mach-mx3/pcm037.h b/arch/arm/mach-imx/pcm037.h
index d6929721a5fd..d6929721a5fd 100644
--- a/arch/arm/mach-mx3/pcm037.h
+++ b/arch/arm/mach-imx/pcm037.h
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index d701d32a07f1..dfd18f3b50e8 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -4,6 +4,7 @@ menu "Integrator Options"
4 4
5config ARCH_INTEGRATOR_AP 5config ARCH_INTEGRATOR_AP
6 bool "Support Integrator/AP and Integrator/PP2 platforms" 6 bool "Support Integrator/AP and Integrator/PP2 platforms"
7 select CLKSRC_MMIO
7 select MIGHT_HAVE_PCI 8 select MIGHT_HAVE_PCI
8 help 9 help
9 Include support for the ARM(R) Integrator/AP and 10 Include support for the ARM(R) Integrator/AP and
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index d3e96451529c..2fbbdd5eac35 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,6 +31,7 @@
31#include <linux/clockchips.h> 31#include <linux/clockchips.h>
32#include <linux/interrupt.h> 32#include <linux/interrupt.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/mtd/physmap.h>
34 35
35#include <mach/hardware.h> 36#include <mach/hardware.h>
36#include <mach/platform.h> 37#include <mach/platform.h>
@@ -43,7 +44,6 @@
43#include <mach/lm.h> 44#include <mach/lm.h>
44 45
45#include <asm/mach/arch.h> 46#include <asm/mach/arch.h>
46#include <asm/mach/flash.h>
47#include <asm/mach/irq.h> 47#include <asm/mach/irq.h>
48#include <asm/mach/map.h> 48#include <asm/mach/map.h>
49#include <asm/mach/time.h> 49#include <asm/mach/time.h>
@@ -222,7 +222,7 @@ device_initcall(irq_syscore_init);
222#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) 222#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
223#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) 223#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
224 224
225static int ap_flash_init(void) 225static int ap_flash_init(struct platform_device *dev)
226{ 226{
227 u32 tmp; 227 u32 tmp;
228 228
@@ -239,7 +239,7 @@ static int ap_flash_init(void)
239 return 0; 239 return 0;
240} 240}
241 241
242static void ap_flash_exit(void) 242static void ap_flash_exit(struct platform_device *dev)
243{ 243{
244 u32 tmp; 244 u32 tmp;
245 245
@@ -255,15 +255,14 @@ static void ap_flash_exit(void)
255 } 255 }
256} 256}
257 257
258static void ap_flash_set_vpp(int on) 258static void ap_flash_set_vpp(struct platform_device *pdev, int on)
259{ 259{
260 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; 260 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
261 261
262 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); 262 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
263} 263}
264 264
265static struct flash_platform_data ap_flash_data = { 265static struct physmap_flash_data ap_flash_data = {
266 .map_name = "cfi_probe",
267 .width = 4, 266 .width = 4,
268 .init = ap_flash_init, 267 .init = ap_flash_init,
269 .exit = ap_flash_exit, 268 .exit = ap_flash_exit,
@@ -277,7 +276,7 @@ static struct resource cfi_flash_resource = {
277}; 276};
278 277
279static struct platform_device cfi_flash_device = { 278static struct platform_device cfi_flash_device = {
280 .name = "armflash", 279 .name = "physmap-flash",
281 .id = 0, 280 .id = 0,
282 .dev = { 281 .dev = {
283 .platform_data = &ap_flash_data, 282 .platform_data = &ap_flash_data,
@@ -335,25 +334,9 @@ static void __init ap_init(void)
335 334
336static unsigned long timer_reload; 335static unsigned long timer_reload;
337 336
338static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
339
340static cycle_t timersp_read(struct clocksource *cs)
341{
342 return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
343}
344
345static struct clocksource clocksource_timersp = {
346 .name = "timer2",
347 .rating = 200,
348 .read = timersp_read,
349 .mask = CLOCKSOURCE_MASK(16),
350 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
351};
352
353static void integrator_clocksource_init(u32 khz) 337static void integrator_clocksource_init(u32 khz)
354{ 338{
355 struct clocksource *cs = &clocksource_timersp; 339 void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
356 void __iomem *base = clksrc_base;
357 u32 ctrl = TIMER_CTRL_ENABLE; 340 u32 ctrl = TIMER_CTRL_ENABLE;
358 341
359 if (khz >= 1500) { 342 if (khz >= 1500) {
@@ -364,7 +347,8 @@ static void integrator_clocksource_init(u32 khz)
364 writel(ctrl, base + TIMER_CTRL); 347 writel(ctrl, base + TIMER_CTRL);
365 writel(0xffff, base + TIMER_LOAD); 348 writel(0xffff, base + TIMER_LOAD);
366 349
367 clocksource_register_khz(cs, khz); 350 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
351 khz * 1000, 200, 16, clocksource_mmio_readl_down);
368} 352}
369 353
370static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; 354static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 9e3ce26023e8..4eb03ab5cb46 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/gfp.h> 23#include <linux/gfp.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <linux/mtd/physmap.h>
25 26
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <mach/platform.h> 28#include <mach/platform.h>
@@ -35,7 +36,6 @@
35#include <mach/lm.h> 36#include <mach/lm.h>
36 37
37#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
38#include <asm/mach/flash.h>
39#include <asm/mach/irq.h> 39#include <asm/mach/irq.h>
40#include <asm/mach/map.h> 40#include <asm/mach/map.h>
41#include <asm/mach/time.h> 41#include <asm/mach/time.h>
@@ -229,17 +229,24 @@ static struct clk cp_auxclk = {
229 .vcoreg = CM_AUXOSC, 229 .vcoreg = CM_AUXOSC,
230}; 230};
231 231
232static struct clk sp804_clk = {
233 .rate = 1000000,
234};
235
232static struct clk_lookup cp_lookups[] = { 236static struct clk_lookup cp_lookups[] = {
233 { /* CLCD */ 237 { /* CLCD */
234 .dev_id = "mb:c0", 238 .dev_id = "mb:c0",
235 .clk = &cp_auxclk, 239 .clk = &cp_auxclk,
240 }, { /* SP804 timers */
241 .dev_id = "sp804",
242 .clk = &sp804_clk,
236 }, 243 },
237}; 244};
238 245
239/* 246/*
240 * Flash handling. 247 * Flash handling.
241 */ 248 */
242static int intcp_flash_init(void) 249static int intcp_flash_init(struct platform_device *dev)
243{ 250{
244 u32 val; 251 u32 val;
245 252
@@ -250,7 +257,7 @@ static int intcp_flash_init(void)
250 return 0; 257 return 0;
251} 258}
252 259
253static void intcp_flash_exit(void) 260static void intcp_flash_exit(struct platform_device *dev)
254{ 261{
255 u32 val; 262 u32 val;
256 263
@@ -259,7 +266,7 @@ static void intcp_flash_exit(void)
259 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 266 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
260} 267}
261 268
262static void intcp_flash_set_vpp(int on) 269static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
263{ 270{
264 u32 val; 271 u32 val;
265 272
@@ -271,8 +278,7 @@ static void intcp_flash_set_vpp(int on)
271 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 278 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
272} 279}
273 280
274static struct flash_platform_data intcp_flash_data = { 281static struct physmap_flash_data intcp_flash_data = {
275 .map_name = "cfi_probe",
276 .width = 4, 282 .width = 4,
277 .init = intcp_flash_init, 283 .init = intcp_flash_init,
278 .exit = intcp_flash_exit, 284 .exit = intcp_flash_exit,
@@ -286,7 +292,7 @@ static struct resource intcp_flash_resource = {
286}; 292};
287 293
288static struct platform_device intcp_flash_device = { 294static struct platform_device intcp_flash_device = {
289 .name = "armflash", 295 .name = "physmap-flash",
290 .id = 0, 296 .id = 0,
291 .dev = { 297 .dev = {
292 .platform_data = &intcp_flash_data, 298 .platform_data = &intcp_flash_data,
@@ -476,8 +482,8 @@ static void __init intcp_timer_init(void)
476 writel(0, TIMER1_VA_BASE + TIMER_CTRL); 482 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
477 writel(0, TIMER2_VA_BASE + TIMER_CTRL); 483 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
478 484
479 sp804_clocksource_init(TIMER2_VA_BASE); 485 sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
480 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1); 486 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
481} 487}
482 488
483static struct sys_timer cp_timer = { 489static struct sys_timer cp_timer = {
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
index b247551b6f5a..4fd715496f45 100644
--- a/arch/arm/mach-iop32x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
7#include <linux/serial_reg.h> 7#include <linux/serial_reg.h>
8#include <mach/hardware.h> 8#include <mach/hardware.h>
9 9
10static volatile u8 *uart_base; 10volatile u8 *uart_base;
11 11
12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) 12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
13 13
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
index b42423f63302..f99bb848c5a1 100644
--- a/arch/arm/mach-iop33x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
7#include <linux/serial_reg.h> 7#include <linux/serial_reg.h>
8#include <mach/hardware.h> 8#include <mach/hardware.h>
9 9
10static volatile u32 *uart_base; 10volatile u32 *uart_base;
11 11
12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) 12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
13 13
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index a54b3db80366..e9a589395723 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
342 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); 342 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
343} 343}
344 344
345/*
346 * Only first 64MB of memory can be accessed via PCI.
347 * We use GFP_DMA to allocate safe buffers to do map/unmap.
348 * This is really ugly and we need a better way of specifying
349 * DMA-capable regions of memory.
350 */
351void __init ixp4xx_adjust_zones(unsigned long *zone_size,
352 unsigned long *zhole_size)
353{
354 unsigned int sz = SZ_64M >> PAGE_SHIFT;
355
356 /*
357 * Only adjust if > 64M on current system
358 */
359 if (zone_size[0] <= sz)
360 return;
361
362 zone_size[1] = zone_size[0] - sz;
363 zone_size[0] = sz;
364 zhole_size[1] = zhole_size[0];
365 zhole_size[0] = 0;
366}
367
368void __init ixp4xx_pci_preinit(void) 345void __init ixp4xx_pci_preinit(void)
369{ 346{
370 unsigned long cpuid = read_cpuid_id(); 347 unsigned long cpuid = read_cpuid_id();
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index ed19bc314318..74ed81a3cb1a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -419,26 +419,14 @@ static void notrace ixp4xx_update_sched_clock(void)
419/* 419/*
420 * clocksource 420 * clocksource
421 */ 421 */
422static cycle_t ixp4xx_get_cycles(struct clocksource *cs)
423{
424 return *IXP4XX_OSTS;
425}
426
427static struct clocksource clocksource_ixp4xx = {
428 .name = "OSTS",
429 .rating = 200,
430 .read = ixp4xx_get_cycles,
431 .mask = CLOCKSOURCE_MASK(32),
432 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
433};
434
435unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; 422unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
436EXPORT_SYMBOL(ixp4xx_timer_freq); 423EXPORT_SYMBOL(ixp4xx_timer_freq);
437static void __init ixp4xx_clocksource_init(void) 424static void __init ixp4xx_clocksource_init(void)
438{ 425{
439 init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq); 426 init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
440 427
441 clocksource_register_hz(&clocksource_ixp4xx, ixp4xx_timer_freq); 428 clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32,
429 clocksource_mmio_readl_up);
442} 430}
443 431
444/* 432/*
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 6d388c9d0e20..34e79404671a 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -14,16 +14,8 @@
14 */ 14 */
15#define PLAT_PHYS_OFFSET UL(0x00000000) 15#define PLAT_PHYS_OFFSET UL(0x00000000)
16 16
17#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) 17#ifdef CONFIG_PCI
18 18#define ARM_DMA_ZONE_SIZE SZ_64M
19void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
20
21#define arch_adjust_zones(size, holes) \
22 ixp4xx_adjust_zones(size, holes)
23
24#define ISA_DMA_THRESHOLD (SZ_64M - 1)
25#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
26
27#endif 19#endif
28 20
29#endif 21#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 2db0078a8cf2..219d7c1dcdba 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -19,7 +19,7 @@
19 19
20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) 20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
21 21
22static volatile u32* uart_base; 22volatile u32* uart_base;
23 23
24static inline void putc(int c) 24static inline void putc(int c)
25{ 25{
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 20e71df3e3bb..f3248cfbe51d 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -13,11 +13,9 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/mv643xx_i2c.h>
18#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
19#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
20#include <linux/spi/orion_spi.h> 18#include <linux/dma-mapping.h>
21#include <net/dsa.h> 19#include <net/dsa.h>
22#include <asm/page.h> 20#include <asm/page.h>
23#include <asm/timex.h> 21#include <asm/timex.h>
@@ -28,11 +26,9 @@
28#include <mach/bridge-regs.h> 26#include <mach/bridge-regs.h>
29#include <plat/audio.h> 27#include <plat/audio.h>
30#include <plat/cache-feroceon-l2.h> 28#include <plat/cache-feroceon-l2.h>
31#include <plat/ehci-orion.h>
32#include <plat/mvsdio.h> 29#include <plat/mvsdio.h>
33#include <plat/mv_xor.h>
34#include <plat/orion_nand.h> 30#include <plat/orion_nand.h>
35#include <plat/orion_wdt.h> 31#include <plat/common.h>
36#include <plat/time.h> 32#include <plat/time.h>
37#include "common.h" 33#include "common.h"
38 34
@@ -69,210 +65,52 @@ void __init kirkwood_map_io(void)
69 * registered. Some reserved bits must be set to 1. 65 * registered. Some reserved bits must be set to 1.
70 */ 66 */
71unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; 67unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
72
73
74/*****************************************************************************
75 * EHCI
76 ****************************************************************************/
77static struct orion_ehci_data kirkwood_ehci_data = {
78 .dram = &kirkwood_mbus_dram_info,
79 .phy_version = EHCI_PHY_NA,
80};
81
82static u64 ehci_dmamask = 0xffffffffUL;
83 68
84 69
85/***************************************************************************** 70/*****************************************************************************
86 * EHCI0 71 * EHCI0
87 ****************************************************************************/ 72 ****************************************************************************/
88static struct resource kirkwood_ehci_resources[] = {
89 {
90 .start = USB_PHYS_BASE,
91 .end = USB_PHYS_BASE + 0x0fff,
92 .flags = IORESOURCE_MEM,
93 }, {
94 .start = IRQ_KIRKWOOD_USB,
95 .end = IRQ_KIRKWOOD_USB,
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100static struct platform_device kirkwood_ehci = {
101 .name = "orion-ehci",
102 .id = 0,
103 .dev = {
104 .dma_mask = &ehci_dmamask,
105 .coherent_dma_mask = 0xffffffff,
106 .platform_data = &kirkwood_ehci_data,
107 },
108 .resource = kirkwood_ehci_resources,
109 .num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
110};
111
112void __init kirkwood_ehci_init(void) 73void __init kirkwood_ehci_init(void)
113{ 74{
114 kirkwood_clk_ctrl |= CGC_USB0; 75 kirkwood_clk_ctrl |= CGC_USB0;
115 platform_device_register(&kirkwood_ehci); 76 orion_ehci_init(&kirkwood_mbus_dram_info,
77 USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
116} 78}
117 79
118 80
119/***************************************************************************** 81/*****************************************************************************
120 * GE00 82 * GE00
121 ****************************************************************************/ 83 ****************************************************************************/
122struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
123 .dram = &kirkwood_mbus_dram_info,
124};
125
126static struct resource kirkwood_ge00_shared_resources[] = {
127 {
128 .name = "ge00 base",
129 .start = GE00_PHYS_BASE + 0x2000,
130 .end = GE00_PHYS_BASE + 0x3fff,
131 .flags = IORESOURCE_MEM,
132 }, {
133 .name = "ge00 err irq",
134 .start = IRQ_KIRKWOOD_GE00_ERR,
135 .end = IRQ_KIRKWOOD_GE00_ERR,
136 .flags = IORESOURCE_IRQ,
137 },
138};
139
140static struct platform_device kirkwood_ge00_shared = {
141 .name = MV643XX_ETH_SHARED_NAME,
142 .id = 0,
143 .dev = {
144 .platform_data = &kirkwood_ge00_shared_data,
145 },
146 .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
147 .resource = kirkwood_ge00_shared_resources,
148};
149
150static struct resource kirkwood_ge00_resources[] = {
151 {
152 .name = "ge00 irq",
153 .start = IRQ_KIRKWOOD_GE00_SUM,
154 .end = IRQ_KIRKWOOD_GE00_SUM,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct platform_device kirkwood_ge00 = {
160 .name = MV643XX_ETH_NAME,
161 .id = 0,
162 .num_resources = 1,
163 .resource = kirkwood_ge00_resources,
164 .dev = {
165 .coherent_dma_mask = 0xffffffff,
166 },
167};
168
169void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) 84void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
170{ 85{
171 kirkwood_clk_ctrl |= CGC_GE0; 86 kirkwood_clk_ctrl |= CGC_GE0;
172 eth_data->shared = &kirkwood_ge00_shared;
173 kirkwood_ge00.dev.platform_data = eth_data;
174 87
175 platform_device_register(&kirkwood_ge00_shared); 88 orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
176 platform_device_register(&kirkwood_ge00); 89 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
90 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
177} 91}
178 92
179 93
180/***************************************************************************** 94/*****************************************************************************
181 * GE01 95 * GE01
182 ****************************************************************************/ 96 ****************************************************************************/
183struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
184 .dram = &kirkwood_mbus_dram_info,
185 .shared_smi = &kirkwood_ge00_shared,
186};
187
188static struct resource kirkwood_ge01_shared_resources[] = {
189 {
190 .name = "ge01 base",
191 .start = GE01_PHYS_BASE + 0x2000,
192 .end = GE01_PHYS_BASE + 0x3fff,
193 .flags = IORESOURCE_MEM,
194 }, {
195 .name = "ge01 err irq",
196 .start = IRQ_KIRKWOOD_GE01_ERR,
197 .end = IRQ_KIRKWOOD_GE01_ERR,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device kirkwood_ge01_shared = {
203 .name = MV643XX_ETH_SHARED_NAME,
204 .id = 1,
205 .dev = {
206 .platform_data = &kirkwood_ge01_shared_data,
207 },
208 .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
209 .resource = kirkwood_ge01_shared_resources,
210};
211
212static struct resource kirkwood_ge01_resources[] = {
213 {
214 .name = "ge01 irq",
215 .start = IRQ_KIRKWOOD_GE01_SUM,
216 .end = IRQ_KIRKWOOD_GE01_SUM,
217 .flags = IORESOURCE_IRQ,
218 },
219};
220
221static struct platform_device kirkwood_ge01 = {
222 .name = MV643XX_ETH_NAME,
223 .id = 1,
224 .num_resources = 1,
225 .resource = kirkwood_ge01_resources,
226 .dev = {
227 .coherent_dma_mask = 0xffffffff,
228 },
229};
230
231void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) 97void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
232{ 98{
99
233 kirkwood_clk_ctrl |= CGC_GE1; 100 kirkwood_clk_ctrl |= CGC_GE1;
234 eth_data->shared = &kirkwood_ge01_shared;
235 kirkwood_ge01.dev.platform_data = eth_data;
236 101
237 platform_device_register(&kirkwood_ge01_shared); 102 orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
238 platform_device_register(&kirkwood_ge01); 103 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
104 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
239} 105}
240 106
241 107
242/***************************************************************************** 108/*****************************************************************************
243 * Ethernet switch 109 * Ethernet switch
244 ****************************************************************************/ 110 ****************************************************************************/
245static struct resource kirkwood_switch_resources[] = {
246 {
247 .start = 0,
248 .end = 0,
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct platform_device kirkwood_switch_device = {
254 .name = "dsa",
255 .id = 0,
256 .num_resources = 0,
257 .resource = kirkwood_switch_resources,
258};
259
260void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) 111void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
261{ 112{
262 int i; 113 orion_ge00_switch_init(d, irq);
263
264 if (irq != NO_IRQ) {
265 kirkwood_switch_resources[0].start = irq;
266 kirkwood_switch_resources[0].end = irq;
267 kirkwood_switch_device.num_resources = 1;
268 }
269
270 d->netdev = &kirkwood_ge00.dev;
271 for (i = 0; i < d->nr_chips; i++)
272 d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
273 kirkwood_switch_device.dev.platform_data = d;
274
275 platform_device_register(&kirkwood_switch_device);
276} 114}
277 115
278 116
@@ -325,53 +163,23 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
325/***************************************************************************** 163/*****************************************************************************
326 * SoC RTC 164 * SoC RTC
327 ****************************************************************************/ 165 ****************************************************************************/
328static struct resource kirkwood_rtc_resource = {
329 .start = RTC_PHYS_BASE,
330 .end = RTC_PHYS_BASE + SZ_16 - 1,
331 .flags = IORESOURCE_MEM,
332};
333
334static void __init kirkwood_rtc_init(void) 166static void __init kirkwood_rtc_init(void)
335{ 167{
336 platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); 168 orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
337} 169}
338 170
339 171
340/***************************************************************************** 172/*****************************************************************************
341 * SATA 173 * SATA
342 ****************************************************************************/ 174 ****************************************************************************/
343static struct resource kirkwood_sata_resources[] = {
344 {
345 .name = "sata base",
346 .start = SATA_PHYS_BASE,
347 .end = SATA_PHYS_BASE + 0x5000 - 1,
348 .flags = IORESOURCE_MEM,
349 }, {
350 .name = "sata irq",
351 .start = IRQ_KIRKWOOD_SATA,
352 .end = IRQ_KIRKWOOD_SATA,
353 .flags = IORESOURCE_IRQ,
354 },
355};
356
357static struct platform_device kirkwood_sata = {
358 .name = "sata_mv",
359 .id = 0,
360 .dev = {
361 .coherent_dma_mask = 0xffffffff,
362 },
363 .num_resources = ARRAY_SIZE(kirkwood_sata_resources),
364 .resource = kirkwood_sata_resources,
365};
366
367void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) 175void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
368{ 176{
369 kirkwood_clk_ctrl |= CGC_SATA0; 177 kirkwood_clk_ctrl |= CGC_SATA0;
370 if (sata_data->n_ports > 1) 178 if (sata_data->n_ports > 1)
371 kirkwood_clk_ctrl |= CGC_SATA1; 179 kirkwood_clk_ctrl |= CGC_SATA1;
372 sata_data->dram = &kirkwood_mbus_dram_info; 180
373 kirkwood_sata.dev.platform_data = sata_data; 181 orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
374 platform_device_register(&kirkwood_sata); 182 SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
375} 183}
376 184
377 185
@@ -391,14 +199,14 @@ static struct resource mvsdio_resources[] = {
391 }, 199 },
392}; 200};
393 201
394static u64 mvsdio_dmamask = 0xffffffffUL; 202static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
395 203
396static struct platform_device kirkwood_sdio = { 204static struct platform_device kirkwood_sdio = {
397 .name = "mvsdio", 205 .name = "mvsdio",
398 .id = -1, 206 .id = -1,
399 .dev = { 207 .dev = {
400 .dma_mask = &mvsdio_dmamask, 208 .dma_mask = &mvsdio_dmamask,
401 .coherent_dma_mask = 0xffffffff, 209 .coherent_dma_mask = DMA_BIT_MASK(32),
402 }, 210 },
403 .num_resources = ARRAY_SIZE(mvsdio_resources), 211 .num_resources = ARRAY_SIZE(mvsdio_resources),
404 .resource = mvsdio_resources, 212 .resource = mvsdio_resources,
@@ -423,424 +231,84 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
423/***************************************************************************** 231/*****************************************************************************
424 * SPI 232 * SPI
425 ****************************************************************************/ 233 ****************************************************************************/
426static struct orion_spi_info kirkwood_spi_plat_data = {
427};
428
429static struct resource kirkwood_spi_resources[] = {
430 {
431 .start = SPI_PHYS_BASE,
432 .end = SPI_PHYS_BASE + SZ_512 - 1,
433 .flags = IORESOURCE_MEM,
434 },
435};
436
437static struct platform_device kirkwood_spi = {
438 .name = "orion_spi",
439 .id = 0,
440 .resource = kirkwood_spi_resources,
441 .dev = {
442 .platform_data = &kirkwood_spi_plat_data,
443 },
444 .num_resources = ARRAY_SIZE(kirkwood_spi_resources),
445};
446
447void __init kirkwood_spi_init() 234void __init kirkwood_spi_init()
448{ 235{
449 kirkwood_clk_ctrl |= CGC_RUNIT; 236 kirkwood_clk_ctrl |= CGC_RUNIT;
450 platform_device_register(&kirkwood_spi); 237 orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
451} 238}
452 239
453 240
454/***************************************************************************** 241/*****************************************************************************
455 * I2C 242 * I2C
456 ****************************************************************************/ 243 ****************************************************************************/
457static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
458 .freq_m = 8, /* assumes 166 MHz TCLK */
459 .freq_n = 3,
460 .timeout = 1000, /* Default timeout of 1 second */
461};
462
463static struct resource kirkwood_i2c_resources[] = {
464 {
465 .start = I2C_PHYS_BASE,
466 .end = I2C_PHYS_BASE + 0x1f,
467 .flags = IORESOURCE_MEM,
468 }, {
469 .start = IRQ_KIRKWOOD_TWSI,
470 .end = IRQ_KIRKWOOD_TWSI,
471 .flags = IORESOURCE_IRQ,
472 },
473};
474
475static struct platform_device kirkwood_i2c = {
476 .name = MV64XXX_I2C_CTLR_NAME,
477 .id = 0,
478 .num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
479 .resource = kirkwood_i2c_resources,
480 .dev = {
481 .platform_data = &kirkwood_i2c_pdata,
482 },
483};
484
485void __init kirkwood_i2c_init(void) 244void __init kirkwood_i2c_init(void)
486{ 245{
487 platform_device_register(&kirkwood_i2c); 246 orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
488} 247}
489 248
490 249
491/***************************************************************************** 250/*****************************************************************************
492 * UART0 251 * UART0
493 ****************************************************************************/ 252 ****************************************************************************/
494static struct plat_serial8250_port kirkwood_uart0_data[] = {
495 {
496 .mapbase = UART0_PHYS_BASE,
497 .membase = (char *)UART0_VIRT_BASE,
498 .irq = IRQ_KIRKWOOD_UART_0,
499 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
500 .iotype = UPIO_MEM,
501 .regshift = 2,
502 .uartclk = 0,
503 }, {
504 },
505};
506
507static struct resource kirkwood_uart0_resources[] = {
508 {
509 .start = UART0_PHYS_BASE,
510 .end = UART0_PHYS_BASE + 0xff,
511 .flags = IORESOURCE_MEM,
512 }, {
513 .start = IRQ_KIRKWOOD_UART_0,
514 .end = IRQ_KIRKWOOD_UART_0,
515 .flags = IORESOURCE_IRQ,
516 },
517};
518
519static struct platform_device kirkwood_uart0 = {
520 .name = "serial8250",
521 .id = 0,
522 .dev = {
523 .platform_data = kirkwood_uart0_data,
524 },
525 .resource = kirkwood_uart0_resources,
526 .num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
527};
528 253
529void __init kirkwood_uart0_init(void) 254void __init kirkwood_uart0_init(void)
530{ 255{
531 platform_device_register(&kirkwood_uart0); 256 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
257 IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
532} 258}
533 259
534 260
535/***************************************************************************** 261/*****************************************************************************
536 * UART1 262 * UART1
537 ****************************************************************************/ 263 ****************************************************************************/
538static struct plat_serial8250_port kirkwood_uart1_data[] = {
539 {
540 .mapbase = UART1_PHYS_BASE,
541 .membase = (char *)UART1_VIRT_BASE,
542 .irq = IRQ_KIRKWOOD_UART_1,
543 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
544 .iotype = UPIO_MEM,
545 .regshift = 2,
546 .uartclk = 0,
547 }, {
548 },
549};
550
551static struct resource kirkwood_uart1_resources[] = {
552 {
553 .start = UART1_PHYS_BASE,
554 .end = UART1_PHYS_BASE + 0xff,
555 .flags = IORESOURCE_MEM,
556 }, {
557 .start = IRQ_KIRKWOOD_UART_1,
558 .end = IRQ_KIRKWOOD_UART_1,
559 .flags = IORESOURCE_IRQ,
560 },
561};
562
563static struct platform_device kirkwood_uart1 = {
564 .name = "serial8250",
565 .id = 1,
566 .dev = {
567 .platform_data = kirkwood_uart1_data,
568 },
569 .resource = kirkwood_uart1_resources,
570 .num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
571};
572
573void __init kirkwood_uart1_init(void) 264void __init kirkwood_uart1_init(void)
574{ 265{
575 platform_device_register(&kirkwood_uart1); 266 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
267 IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
576} 268}
577 269
578
579/***************************************************************************** 270/*****************************************************************************
580 * Cryptographic Engines and Security Accelerator (CESA) 271 * Cryptographic Engines and Security Accelerator (CESA)
581 ****************************************************************************/ 272 ****************************************************************************/
582
583static struct resource kirkwood_crypto_res[] = {
584 {
585 .name = "regs",
586 .start = CRYPTO_PHYS_BASE,
587 .end = CRYPTO_PHYS_BASE + 0xffff,
588 .flags = IORESOURCE_MEM,
589 }, {
590 .name = "sram",
591 .start = KIRKWOOD_SRAM_PHYS_BASE,
592 .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
593 .flags = IORESOURCE_MEM,
594 }, {
595 .name = "crypto interrupt",
596 .start = IRQ_KIRKWOOD_CRYPTO,
597 .end = IRQ_KIRKWOOD_CRYPTO,
598 .flags = IORESOURCE_IRQ,
599 },
600};
601
602static struct platform_device kirkwood_crypto_device = {
603 .name = "mv_crypto",
604 .id = -1,
605 .num_resources = ARRAY_SIZE(kirkwood_crypto_res),
606 .resource = kirkwood_crypto_res,
607};
608
609void __init kirkwood_crypto_init(void) 273void __init kirkwood_crypto_init(void)
610{ 274{
611 kirkwood_clk_ctrl |= CGC_CRYPTO; 275 kirkwood_clk_ctrl |= CGC_CRYPTO;
612 platform_device_register(&kirkwood_crypto_device); 276 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
277 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
613} 278}
614 279
615 280
616/***************************************************************************** 281/*****************************************************************************
617 * XOR
618 ****************************************************************************/
619static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
620 .dram = &kirkwood_mbus_dram_info,
621};
622
623static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
624
625
626/*****************************************************************************
627 * XOR0 282 * XOR0
628 ****************************************************************************/ 283 ****************************************************************************/
629static struct resource kirkwood_xor0_shared_resources[] = {
630 {
631 .name = "xor 0 low",
632 .start = XOR0_PHYS_BASE,
633 .end = XOR0_PHYS_BASE + 0xff,
634 .flags = IORESOURCE_MEM,
635 }, {
636 .name = "xor 0 high",
637 .start = XOR0_HIGH_PHYS_BASE,
638 .end = XOR0_HIGH_PHYS_BASE + 0xff,
639 .flags = IORESOURCE_MEM,
640 },
641};
642
643static struct platform_device kirkwood_xor0_shared = {
644 .name = MV_XOR_SHARED_NAME,
645 .id = 0,
646 .dev = {
647 .platform_data = &kirkwood_xor_shared_data,
648 },
649 .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
650 .resource = kirkwood_xor0_shared_resources,
651};
652
653static struct resource kirkwood_xor00_resources[] = {
654 [0] = {
655 .start = IRQ_KIRKWOOD_XOR_00,
656 .end = IRQ_KIRKWOOD_XOR_00,
657 .flags = IORESOURCE_IRQ,
658 },
659};
660
661static struct mv_xor_platform_data kirkwood_xor00_data = {
662 .shared = &kirkwood_xor0_shared,
663 .hw_id = 0,
664 .pool_size = PAGE_SIZE,
665};
666
667static struct platform_device kirkwood_xor00_channel = {
668 .name = MV_XOR_NAME,
669 .id = 0,
670 .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
671 .resource = kirkwood_xor00_resources,
672 .dev = {
673 .dma_mask = &kirkwood_xor_dmamask,
674 .coherent_dma_mask = DMA_BIT_MASK(64),
675 .platform_data = &kirkwood_xor00_data,
676 },
677};
678
679static struct resource kirkwood_xor01_resources[] = {
680 [0] = {
681 .start = IRQ_KIRKWOOD_XOR_01,
682 .end = IRQ_KIRKWOOD_XOR_01,
683 .flags = IORESOURCE_IRQ,
684 },
685};
686
687static struct mv_xor_platform_data kirkwood_xor01_data = {
688 .shared = &kirkwood_xor0_shared,
689 .hw_id = 1,
690 .pool_size = PAGE_SIZE,
691};
692
693static struct platform_device kirkwood_xor01_channel = {
694 .name = MV_XOR_NAME,
695 .id = 1,
696 .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
697 .resource = kirkwood_xor01_resources,
698 .dev = {
699 .dma_mask = &kirkwood_xor_dmamask,
700 .coherent_dma_mask = DMA_BIT_MASK(64),
701 .platform_data = &kirkwood_xor01_data,
702 },
703};
704
705static void __init kirkwood_xor0_init(void) 284static void __init kirkwood_xor0_init(void)
706{ 285{
707 kirkwood_clk_ctrl |= CGC_XOR0; 286 kirkwood_clk_ctrl |= CGC_XOR0;
708 platform_device_register(&kirkwood_xor0_shared);
709 287
710 /* 288 orion_xor0_init(&kirkwood_mbus_dram_info,
711 * two engines can't do memset simultaneously, this limitation 289 XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
712 * satisfied by removing memset support from one of the engines. 290 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
713 */
714 dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
715 dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
716 platform_device_register(&kirkwood_xor00_channel);
717
718 dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
719 dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
720 dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
721 platform_device_register(&kirkwood_xor01_channel);
722} 291}
723 292
724 293
725/***************************************************************************** 294/*****************************************************************************
726 * XOR1 295 * XOR1
727 ****************************************************************************/ 296 ****************************************************************************/
728static struct resource kirkwood_xor1_shared_resources[] = {
729 {
730 .name = "xor 1 low",
731 .start = XOR1_PHYS_BASE,
732 .end = XOR1_PHYS_BASE + 0xff,
733 .flags = IORESOURCE_MEM,
734 }, {
735 .name = "xor 1 high",
736 .start = XOR1_HIGH_PHYS_BASE,
737 .end = XOR1_HIGH_PHYS_BASE + 0xff,
738 .flags = IORESOURCE_MEM,
739 },
740};
741
742static struct platform_device kirkwood_xor1_shared = {
743 .name = MV_XOR_SHARED_NAME,
744 .id = 1,
745 .dev = {
746 .platform_data = &kirkwood_xor_shared_data,
747 },
748 .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
749 .resource = kirkwood_xor1_shared_resources,
750};
751
752static struct resource kirkwood_xor10_resources[] = {
753 [0] = {
754 .start = IRQ_KIRKWOOD_XOR_10,
755 .end = IRQ_KIRKWOOD_XOR_10,
756 .flags = IORESOURCE_IRQ,
757 },
758};
759
760static struct mv_xor_platform_data kirkwood_xor10_data = {
761 .shared = &kirkwood_xor1_shared,
762 .hw_id = 0,
763 .pool_size = PAGE_SIZE,
764};
765
766static struct platform_device kirkwood_xor10_channel = {
767 .name = MV_XOR_NAME,
768 .id = 2,
769 .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
770 .resource = kirkwood_xor10_resources,
771 .dev = {
772 .dma_mask = &kirkwood_xor_dmamask,
773 .coherent_dma_mask = DMA_BIT_MASK(64),
774 .platform_data = &kirkwood_xor10_data,
775 },
776};
777
778static struct resource kirkwood_xor11_resources[] = {
779 [0] = {
780 .start = IRQ_KIRKWOOD_XOR_11,
781 .end = IRQ_KIRKWOOD_XOR_11,
782 .flags = IORESOURCE_IRQ,
783 },
784};
785
786static struct mv_xor_platform_data kirkwood_xor11_data = {
787 .shared = &kirkwood_xor1_shared,
788 .hw_id = 1,
789 .pool_size = PAGE_SIZE,
790};
791
792static struct platform_device kirkwood_xor11_channel = {
793 .name = MV_XOR_NAME,
794 .id = 3,
795 .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
796 .resource = kirkwood_xor11_resources,
797 .dev = {
798 .dma_mask = &kirkwood_xor_dmamask,
799 .coherent_dma_mask = DMA_BIT_MASK(64),
800 .platform_data = &kirkwood_xor11_data,
801 },
802};
803
804static void __init kirkwood_xor1_init(void) 297static void __init kirkwood_xor1_init(void)
805{ 298{
806 kirkwood_clk_ctrl |= CGC_XOR1; 299 kirkwood_clk_ctrl |= CGC_XOR1;
807 platform_device_register(&kirkwood_xor1_shared);
808 300
809 /* 301 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
810 * two engines can't do memset simultaneously, this limitation 302 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
811 * satisfied by removing memset support from one of the engines.
812 */
813 dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
814 dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
815 platform_device_register(&kirkwood_xor10_channel);
816
817 dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
818 dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
819 dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
820 platform_device_register(&kirkwood_xor11_channel);
821} 303}
822 304
823 305
824/***************************************************************************** 306/*****************************************************************************
825 * Watchdog 307 * Watchdog
826 ****************************************************************************/ 308 ****************************************************************************/
827static struct orion_wdt_platform_data kirkwood_wdt_data = {
828 .tclk = 0,
829};
830
831static struct platform_device kirkwood_wdt_device = {
832 .name = "orion_wdt",
833 .id = -1,
834 .dev = {
835 .platform_data = &kirkwood_wdt_data,
836 },
837 .num_resources = 0,
838};
839
840static void __init kirkwood_wdt_init(void) 309static void __init kirkwood_wdt_init(void)
841{ 310{
842 kirkwood_wdt_data.tclk = kirkwood_tclk; 311 orion_wdt_init(kirkwood_tclk);
843 platform_device_register(&kirkwood_wdt_device);
844} 312}
845 313
846 314
@@ -984,11 +452,6 @@ void __init kirkwood_init(void)
984{ 452{
985 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", 453 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
986 kirkwood_id(), kirkwood_tclk); 454 kirkwood_id(), kirkwood_tclk);
987 kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
988 kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
989 kirkwood_spi_plat_data.tclk = kirkwood_tclk;
990 kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
991 kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
992 kirkwood_i2s_data.tclk = kirkwood_tclk; 455 kirkwood_i2s_data.tclk = kirkwood_tclk;
993 456
994 /* 457 /*
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 9da2eb59180b..2bf8161e3b51 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -51,6 +51,7 @@
51#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 51#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
52#define IRQ_KIRKWOOD_GE00_ERR 46 52#define IRQ_KIRKWOOD_GE00_ERR 46
53#define IRQ_KIRKWOOD_GE01_ERR 47 53#define IRQ_KIRKWOOD_GE01_ERR 47
54#define IRQ_KIRKWOOD_RTC 53
54 55
55/* 56/*
56 * KIRKWOOD General Purpose Pins 57 * KIRKWOOD General Purpose Pins
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 7ce201848067..b0a7d979a8ed 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/gpio.h> 15#include <asm/gpio.h>
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <plat/mpp.h>
17#include "common.h" 18#include "common.h"
18#include "mpp.h" 19#include "mpp.h"
19 20
@@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void)
36 return 0; 37 return 0;
37} 38}
38 39
39#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
40#define MPP_NR_REGS (1 + MPP_MAX/8)
41
42void __init kirkwood_mpp_conf(unsigned int *mpp_list) 40void __init kirkwood_mpp_conf(unsigned int *mpp_list)
43{ 41{
44 u32 mpp_ctrl[MPP_NR_REGS]; 42 orion_mpp_conf(mpp_list, kirkwood_variant(),
45 unsigned int variant_mask; 43 MPP_MAX, DEV_BUS_VIRT_BASE);
46 int i;
47
48 variant_mask = kirkwood_variant();
49 if (!variant_mask)
50 return;
51
52 printk(KERN_DEBUG "initial MPP regs:");
53 for (i = 0; i < MPP_NR_REGS; i++) {
54 mpp_ctrl[i] = readl(MPP_CTRL(i));
55 printk(" %08x", mpp_ctrl[i]);
56 }
57 printk("\n");
58
59 for ( ; *mpp_list; mpp_list++) {
60 unsigned int num = MPP_NUM(*mpp_list);
61 unsigned int sel = MPP_SEL(*mpp_list);
62 int shift, gpio_mode;
63
64 if (num > MPP_MAX) {
65 printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
66 "number (%u)\n", num);
67 continue;
68 }
69 if (!(*mpp_list & variant_mask)) {
70 printk(KERN_WARNING
71 "kirkwood_mpp_conf: requested MPP%u config "
72 "unavailable on this hardware\n", num);
73 continue;
74 }
75
76 shift = (num & 7) << 2;
77 mpp_ctrl[num / 8] &= ~(0xf << shift);
78 mpp_ctrl[num / 8] |= sel << shift;
79
80 gpio_mode = 0;
81 if (*mpp_list & MPP_INPUT_MASK)
82 gpio_mode |= GPIO_INPUT_OK;
83 if (*mpp_list & MPP_OUTPUT_MASK)
84 gpio_mode |= GPIO_OUTPUT_OK;
85 if (sel != 0)
86 gpio_mode = 0;
87 orion_gpio_set_valid(num, gpio_mode);
88 }
89
90 printk(KERN_DEBUG " final MPP regs:");
91 for (i = 0; i < MPP_NR_REGS; i++) {
92 writel(mpp_ctrl[i], MPP_CTRL(i));
93 printk(" %08x", mpp_ctrl[i]);
94 }
95 printk("\n");
96} 44}
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index 9b0a94d85c3e..ac787957e2d9 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -22,14 +22,8 @@
22 /* available on F6281 */ ((!!(_F6281)) << 17) | \ 22 /* available on F6281 */ ((!!(_F6281)) << 17) | \
23 /* available on F6282 */ ((!!(_F6282)) << 18)) 23 /* available on F6282 */ ((!!(_F6282)) << 18))
24 24
25#define MPP_NUM(x) ((x) & 0xff)
26#define MPP_SEL(x) (((x) >> 8) & 0xf)
27
28 /* num sel i o 6180 6190 6192 6281 6282 */ 25 /* num sel i o 6180 6190 6192 6281 6282 */
29 26
30#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
31#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
32
33#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 ) 27#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
34#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 ) 28#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
35#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 ) 29#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index e41e909cf8f4..5f02664db812 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -13,7 +13,7 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h> 16#include <linux/dma-mapping.h>
17#include <asm/page.h> 17#include <asm/page.h>
18#include <asm/timex.h> 18#include <asm/timex.h>
19#include <asm/mach/map.h> 19#include <asm/mach/map.h>
@@ -22,6 +22,7 @@
22#include <mach/loki.h> 22#include <mach/loki.h>
23#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
24#include <plat/time.h> 24#include <plat/time.h>
25#include <plat/common.h>
25#include "common.h" 26#include "common.h"
26 27
27/***************************************************************************** 28/*****************************************************************************
@@ -43,116 +44,28 @@ void __init loki_map_io(void)
43 44
44 45
45/***************************************************************************** 46/*****************************************************************************
46 * GE0 47 * GE00
47 ****************************************************************************/ 48 ****************************************************************************/
48struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
49 .t_clk = LOKI_TCLK,
50 .dram = &loki_mbus_dram_info,
51};
52
53static struct resource loki_ge0_shared_resources[] = {
54 {
55 .name = "ge0 base",
56 .start = GE0_PHYS_BASE + 0x2000,
57 .end = GE0_PHYS_BASE + 0x3fff,
58 .flags = IORESOURCE_MEM,
59 },
60};
61
62static struct platform_device loki_ge0_shared = {
63 .name = MV643XX_ETH_SHARED_NAME,
64 .id = 0,
65 .dev = {
66 .platform_data = &loki_ge0_shared_data,
67 },
68 .num_resources = 1,
69 .resource = loki_ge0_shared_resources,
70};
71
72static struct resource loki_ge0_resources[] = {
73 {
74 .name = "ge0 irq",
75 .start = IRQ_LOKI_GBE_A_INT,
76 .end = IRQ_LOKI_GBE_A_INT,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct platform_device loki_ge0 = {
82 .name = MV643XX_ETH_NAME,
83 .id = 0,
84 .num_resources = 1,
85 .resource = loki_ge0_resources,
86 .dev = {
87 .coherent_dma_mask = 0xffffffff,
88 },
89};
90
91void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) 49void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
92{ 50{
93 eth_data->shared = &loki_ge0_shared;
94 loki_ge0.dev.platform_data = eth_data;
95
96 writel(0x00079220, GE0_VIRT_BASE + 0x20b0); 51 writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
97 platform_device_register(&loki_ge0_shared); 52
98 platform_device_register(&loki_ge0); 53 orion_ge00_init(eth_data, &loki_mbus_dram_info,
54 GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
55 0, LOKI_TCLK);
99} 56}
100 57
101 58
102/***************************************************************************** 59/*****************************************************************************
103 * GE1 60 * GE01
104 ****************************************************************************/ 61 ****************************************************************************/
105struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
106 .t_clk = LOKI_TCLK,
107 .dram = &loki_mbus_dram_info,
108};
109
110static struct resource loki_ge1_shared_resources[] = {
111 {
112 .name = "ge1 base",
113 .start = GE1_PHYS_BASE + 0x2000,
114 .end = GE1_PHYS_BASE + 0x3fff,
115 .flags = IORESOURCE_MEM,
116 },
117};
118
119static struct platform_device loki_ge1_shared = {
120 .name = MV643XX_ETH_SHARED_NAME,
121 .id = 1,
122 .dev = {
123 .platform_data = &loki_ge1_shared_data,
124 },
125 .num_resources = 1,
126 .resource = loki_ge1_shared_resources,
127};
128
129static struct resource loki_ge1_resources[] = {
130 {
131 .name = "ge1 irq",
132 .start = IRQ_LOKI_GBE_B_INT,
133 .end = IRQ_LOKI_GBE_B_INT,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device loki_ge1 = {
139 .name = MV643XX_ETH_NAME,
140 .id = 1,
141 .num_resources = 1,
142 .resource = loki_ge1_resources,
143 .dev = {
144 .coherent_dma_mask = 0xffffffff,
145 },
146};
147
148void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) 62void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
149{ 63{
150 eth_data->shared = &loki_ge1_shared;
151 loki_ge1.dev.platform_data = eth_data;
152
153 writel(0x00079220, GE1_VIRT_BASE + 0x20b0); 64 writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
154 platform_device_register(&loki_ge1_shared); 65
155 platform_device_register(&loki_ge1); 66 orion_ge01_init(eth_data, &loki_mbus_dram_info,
67 GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
68 0, LOKI_TCLK);
156} 69}
157 70
158 71
@@ -187,7 +100,7 @@ static struct platform_device loki_sas = {
187 .name = "mvsas", 100 .name = "mvsas",
188 .id = 0, 101 .id = 0,
189 .dev = { 102 .dev = {
190 .coherent_dma_mask = 0xffffffff, 103 .coherent_dma_mask = DMA_BIT_MASK(32),
191 }, 104 },
192 .num_resources = ARRAY_SIZE(loki_sas_resources), 105 .num_resources = ARRAY_SIZE(loki_sas_resources),
193 .resource = loki_sas_resources, 106 .resource = loki_sas_resources,
@@ -203,88 +116,19 @@ void __init loki_sas_init(void)
203/***************************************************************************** 116/*****************************************************************************
204 * UART0 117 * UART0
205 ****************************************************************************/ 118 ****************************************************************************/
206static struct plat_serial8250_port loki_uart0_data[] = {
207 {
208 .mapbase = UART0_PHYS_BASE,
209 .membase = (char *)UART0_VIRT_BASE,
210 .irq = IRQ_LOKI_UART0,
211 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
212 .iotype = UPIO_MEM,
213 .regshift = 2,
214 .uartclk = LOKI_TCLK,
215 }, {
216 },
217};
218
219static struct resource loki_uart0_resources[] = {
220 {
221 .start = UART0_PHYS_BASE,
222 .end = UART0_PHYS_BASE + 0xff,
223 .flags = IORESOURCE_MEM,
224 }, {
225 .start = IRQ_LOKI_UART0,
226 .end = IRQ_LOKI_UART0,
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231static struct platform_device loki_uart0 = {
232 .name = "serial8250",
233 .id = 0,
234 .dev = {
235 .platform_data = loki_uart0_data,
236 },
237 .resource = loki_uart0_resources,
238 .num_resources = ARRAY_SIZE(loki_uart0_resources),
239};
240
241void __init loki_uart0_init(void) 119void __init loki_uart0_init(void)
242{ 120{
243 platform_device_register(&loki_uart0); 121 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
122 IRQ_LOKI_UART0, LOKI_TCLK);
244} 123}
245 124
246
247/***************************************************************************** 125/*****************************************************************************
248 * UART1 126 * UART1
249 ****************************************************************************/ 127 ****************************************************************************/
250static struct plat_serial8250_port loki_uart1_data[] = {
251 {
252 .mapbase = UART1_PHYS_BASE,
253 .membase = (char *)UART1_VIRT_BASE,
254 .irq = IRQ_LOKI_UART1,
255 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
256 .iotype = UPIO_MEM,
257 .regshift = 2,
258 .uartclk = LOKI_TCLK,
259 }, {
260 },
261};
262
263static struct resource loki_uart1_resources[] = {
264 {
265 .start = UART1_PHYS_BASE,
266 .end = UART1_PHYS_BASE + 0xff,
267 .flags = IORESOURCE_MEM,
268 }, {
269 .start = IRQ_LOKI_UART1,
270 .end = IRQ_LOKI_UART1,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
275static struct platform_device loki_uart1 = {
276 .name = "serial8250",
277 .id = 1,
278 .dev = {
279 .platform_data = loki_uart1_data,
280 },
281 .resource = loki_uart1_resources,
282 .num_resources = ARRAY_SIZE(loki_uart1_resources),
283};
284
285void __init loki_uart1_init(void) 128void __init loki_uart1_init(void)
286{ 129{
287 platform_device_register(&loki_uart1); 130 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
131 IRQ_LOKI_UART1, LOKI_TCLK);
288} 132}
289 133
290 134
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 6162ac308c20..b42c909bbeeb 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -31,19 +31,6 @@
31#include <mach/platform.h> 31#include <mach/platform.h>
32#include "common.h" 32#include "common.h"
33 33
34static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
35{
36 return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
37}
38
39static struct clocksource lpc32xx_clksrc = {
40 .name = "lpc32xx_clksrc",
41 .rating = 300,
42 .read = lpc32xx_clksrc_read,
43 .mask = CLOCKSOURCE_MASK(32),
44 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
45};
46
47static int lpc32xx_clkevt_next_event(unsigned long delta, 34static int lpc32xx_clkevt_next_event(unsigned long delta,
48 struct clock_event_device *dev) 35 struct clock_event_device *dev)
49{ 36{
@@ -170,7 +157,9 @@ static void __init lpc32xx_timer_init(void)
170 __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); 157 __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
171 __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, 158 __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
172 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); 159 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
173 clocksource_register_hz(&lpc32xx_clksrc, clkrate); 160
161 clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
162 "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
174} 163}
175 164
176struct sys_timer lpc32xx_timer = { 165struct sys_timer lpc32xx_timer = {
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index 85bd8a2d84b5..d6daeb7e4ef1 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -14,7 +14,7 @@
14#define UART2_BASE (APB_PHYS_BASE + 0x17000) 14#define UART2_BASE (APB_PHYS_BASE + 0x17000)
15#define UART3_BASE (APB_PHYS_BASE + 0x18000) 15#define UART3_BASE (APB_PHYS_BASE + 0x18000)
16 16
17static volatile unsigned long *UART; 17volatile unsigned long *UART;
18 18
19static inline void putc(char c) 19static inline void putc(char c)
20{ 20{
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 56a964e52ad3..cc9c4fd7cccc 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -27,6 +27,9 @@
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30
31#include <asm/mach/irq.h>
32
30#include <mach/msm_iomap.h> 33#include <mach/msm_iomap.h>
31#include "gpiomux.h" 34#include "gpiomux.h"
32 35
@@ -309,8 +312,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
309 */ 312 */
310static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) 313static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
311{ 314{
312 struct irq_data *data = irq_desc_get_irq_data(desc);
313 unsigned long i; 315 unsigned long i;
316 struct irq_chip *chip = irq_desc_get_chip(desc);
317
318 chained_irq_enter(chip, desc);
314 319
315 for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); 320 for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
316 i < NR_GPIO_IRQS; 321 i < NR_GPIO_IRQS;
@@ -319,7 +324,8 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
319 generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, 324 generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
320 i)); 325 i));
321 } 326 }
322 data->chip->irq_ack(data); 327
328 chained_irq_exit(chip, desc);
323} 329}
324 330
325static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 331static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
deleted file mode 100644
index 3c01000ecc80..000000000000
--- a/arch/arm/mach-msm/include/mach/smp.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_SMP_H
14#define __ASM_ARCH_MSM_SMP_H
15
16#include <asm/hardware/gic.h>
17
18static inline void smp_cross_call(const struct cpumask *mask, int ipi)
19{
20 gic_raise_softirq(mask, ipi);
21}
22
23#endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 0f427bc94447..2034098cf015 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -119,7 +119,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
119 * the boot monitor to read the system wide flags register, 119 * the boot monitor to read the system wide flags register,
120 * and branch to the address found there. 120 * and branch to the address found there.
121 */ 121 */
122 smp_cross_call(cpumask_of(cpu), 1); 122 gic_raise_softirq(cpumask_of(cpu), 1);
123 123
124 timeout = jiffies + (1 * HZ); 124 timeout = jiffies + (1 * HZ);
125 while (time_before(jiffies, timeout)) { 125 while (time_before(jiffies, timeout)) {
@@ -151,6 +151,8 @@ void __init smp_init_cpus(void)
151 151
152 for (i = 0; i < NR_CPUS; i++) 152 for (i = 0; i < NR_CPUS; i++)
153 set_cpu_possible(i, true); 153 set_cpu_possible(i, true);
154
155 set_smp_cross_call(gic_raise_softirq);
154} 156}
155 157
156void __init platform_smp_prepare_cpus(unsigned int max_cpus) 158void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 44fb4e55be0d..23d3980ef59d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -13,8 +13,6 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/mv643xx_i2c.h>
18#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
19#include <linux/ethtool.h> 17#include <linux/ethtool.h>
20#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -22,11 +20,12 @@
22#include <mach/mv78xx0.h> 20#include <mach/mv78xx0.h>
23#include <mach/bridge-regs.h> 21#include <mach/bridge-regs.h>
24#include <plat/cache-feroceon-l2.h> 22#include <plat/cache-feroceon-l2.h>
25#include <plat/ehci-orion.h>
26#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
27#include <plat/time.h> 24#include <plat/time.h>
25#include <plat/common.h>
28#include "common.h" 26#include "common.h"
29 27
28static int get_tclk(void);
30 29
31/***************************************************************************** 30/*****************************************************************************
32 * Common bits 31 * Common bits
@@ -168,285 +167,62 @@ void __init mv78xx0_map_io(void)
168/***************************************************************************** 167/*****************************************************************************
169 * EHCI 168 * EHCI
170 ****************************************************************************/ 169 ****************************************************************************/
171static struct orion_ehci_data mv78xx0_ehci_data = {
172 .dram = &mv78xx0_mbus_dram_info,
173 .phy_version = EHCI_PHY_NA,
174};
175
176static u64 ehci_dmamask = 0xffffffffUL;
177
178
179/*****************************************************************************
180 * EHCI0
181 ****************************************************************************/
182static struct resource mv78xx0_ehci0_resources[] = {
183 {
184 .start = USB0_PHYS_BASE,
185 .end = USB0_PHYS_BASE + 0x0fff,
186 .flags = IORESOURCE_MEM,
187 }, {
188 .start = IRQ_MV78XX0_USB_0,
189 .end = IRQ_MV78XX0_USB_0,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device mv78xx0_ehci0 = {
195 .name = "orion-ehci",
196 .id = 0,
197 .dev = {
198 .dma_mask = &ehci_dmamask,
199 .coherent_dma_mask = 0xffffffff,
200 .platform_data = &mv78xx0_ehci_data,
201 },
202 .resource = mv78xx0_ehci0_resources,
203 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
204};
205
206void __init mv78xx0_ehci0_init(void) 170void __init mv78xx0_ehci0_init(void)
207{ 171{
208 platform_device_register(&mv78xx0_ehci0); 172 orion_ehci_init(&mv78xx0_mbus_dram_info,
173 USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
209} 174}
210 175
211 176
212/***************************************************************************** 177/*****************************************************************************
213 * EHCI1 178 * EHCI1
214 ****************************************************************************/ 179 ****************************************************************************/
215static struct resource mv78xx0_ehci1_resources[] = {
216 {
217 .start = USB1_PHYS_BASE,
218 .end = USB1_PHYS_BASE + 0x0fff,
219 .flags = IORESOURCE_MEM,
220 }, {
221 .start = IRQ_MV78XX0_USB_1,
222 .end = IRQ_MV78XX0_USB_1,
223 .flags = IORESOURCE_IRQ,
224 },
225};
226
227static struct platform_device mv78xx0_ehci1 = {
228 .name = "orion-ehci",
229 .id = 1,
230 .dev = {
231 .dma_mask = &ehci_dmamask,
232 .coherent_dma_mask = 0xffffffff,
233 .platform_data = &mv78xx0_ehci_data,
234 },
235 .resource = mv78xx0_ehci1_resources,
236 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
237};
238
239void __init mv78xx0_ehci1_init(void) 180void __init mv78xx0_ehci1_init(void)
240{ 181{
241 platform_device_register(&mv78xx0_ehci1); 182 orion_ehci_1_init(&mv78xx0_mbus_dram_info,
183 USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
242} 184}
243 185
244 186
245/***************************************************************************** 187/*****************************************************************************
246 * EHCI2 188 * EHCI2
247 ****************************************************************************/ 189 ****************************************************************************/
248static struct resource mv78xx0_ehci2_resources[] = {
249 {
250 .start = USB2_PHYS_BASE,
251 .end = USB2_PHYS_BASE + 0x0fff,
252 .flags = IORESOURCE_MEM,
253 }, {
254 .start = IRQ_MV78XX0_USB_2,
255 .end = IRQ_MV78XX0_USB_2,
256 .flags = IORESOURCE_IRQ,
257 },
258};
259
260static struct platform_device mv78xx0_ehci2 = {
261 .name = "orion-ehci",
262 .id = 2,
263 .dev = {
264 .dma_mask = &ehci_dmamask,
265 .coherent_dma_mask = 0xffffffff,
266 .platform_data = &mv78xx0_ehci_data,
267 },
268 .resource = mv78xx0_ehci2_resources,
269 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
270};
271
272void __init mv78xx0_ehci2_init(void) 190void __init mv78xx0_ehci2_init(void)
273{ 191{
274 platform_device_register(&mv78xx0_ehci2); 192 orion_ehci_2_init(&mv78xx0_mbus_dram_info,
193 USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
275} 194}
276 195
277 196
278/***************************************************************************** 197/*****************************************************************************
279 * GE00 198 * GE00
280 ****************************************************************************/ 199 ****************************************************************************/
281struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
282 .t_clk = 0,
283 .dram = &mv78xx0_mbus_dram_info,
284};
285
286static struct resource mv78xx0_ge00_shared_resources[] = {
287 {
288 .name = "ge00 base",
289 .start = GE00_PHYS_BASE + 0x2000,
290 .end = GE00_PHYS_BASE + 0x3fff,
291 .flags = IORESOURCE_MEM,
292 }, {
293 .name = "ge err irq",
294 .start = IRQ_MV78XX0_GE_ERR,
295 .end = IRQ_MV78XX0_GE_ERR,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct platform_device mv78xx0_ge00_shared = {
301 .name = MV643XX_ETH_SHARED_NAME,
302 .id = 0,
303 .dev = {
304 .platform_data = &mv78xx0_ge00_shared_data,
305 },
306 .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
307 .resource = mv78xx0_ge00_shared_resources,
308};
309
310static struct resource mv78xx0_ge00_resources[] = {
311 {
312 .name = "ge00 irq",
313 .start = IRQ_MV78XX0_GE00_SUM,
314 .end = IRQ_MV78XX0_GE00_SUM,
315 .flags = IORESOURCE_IRQ,
316 },
317};
318
319static struct platform_device mv78xx0_ge00 = {
320 .name = MV643XX_ETH_NAME,
321 .id = 0,
322 .num_resources = 1,
323 .resource = mv78xx0_ge00_resources,
324 .dev = {
325 .coherent_dma_mask = 0xffffffff,
326 },
327};
328
329void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 200void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
330{ 201{
331 eth_data->shared = &mv78xx0_ge00_shared; 202 orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
332 mv78xx0_ge00.dev.platform_data = eth_data; 203 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
333 204 IRQ_MV78XX0_GE_ERR, get_tclk());
334 platform_device_register(&mv78xx0_ge00_shared);
335 platform_device_register(&mv78xx0_ge00);
336} 205}
337 206
338 207
339/***************************************************************************** 208/*****************************************************************************
340 * GE01 209 * GE01
341 ****************************************************************************/ 210 ****************************************************************************/
342struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
343 .t_clk = 0,
344 .dram = &mv78xx0_mbus_dram_info,
345 .shared_smi = &mv78xx0_ge00_shared,
346};
347
348static struct resource mv78xx0_ge01_shared_resources[] = {
349 {
350 .name = "ge01 base",
351 .start = GE01_PHYS_BASE + 0x2000,
352 .end = GE01_PHYS_BASE + 0x3fff,
353 .flags = IORESOURCE_MEM,
354 },
355};
356
357static struct platform_device mv78xx0_ge01_shared = {
358 .name = MV643XX_ETH_SHARED_NAME,
359 .id = 1,
360 .dev = {
361 .platform_data = &mv78xx0_ge01_shared_data,
362 },
363 .num_resources = 1,
364 .resource = mv78xx0_ge01_shared_resources,
365};
366
367static struct resource mv78xx0_ge01_resources[] = {
368 {
369 .name = "ge01 irq",
370 .start = IRQ_MV78XX0_GE01_SUM,
371 .end = IRQ_MV78XX0_GE01_SUM,
372 .flags = IORESOURCE_IRQ,
373 },
374};
375
376static struct platform_device mv78xx0_ge01 = {
377 .name = MV643XX_ETH_NAME,
378 .id = 1,
379 .num_resources = 1,
380 .resource = mv78xx0_ge01_resources,
381 .dev = {
382 .coherent_dma_mask = 0xffffffff,
383 },
384};
385
386void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 211void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
387{ 212{
388 eth_data->shared = &mv78xx0_ge01_shared; 213 orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
389 mv78xx0_ge01.dev.platform_data = eth_data; 214 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
390 215 NO_IRQ, get_tclk());
391 platform_device_register(&mv78xx0_ge01_shared);
392 platform_device_register(&mv78xx0_ge01);
393} 216}
394 217
395 218
396/***************************************************************************** 219/*****************************************************************************
397 * GE10 220 * GE10
398 ****************************************************************************/ 221 ****************************************************************************/
399struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
400 .t_clk = 0,
401 .dram = &mv78xx0_mbus_dram_info,
402 .shared_smi = &mv78xx0_ge00_shared,
403};
404
405static struct resource mv78xx0_ge10_shared_resources[] = {
406 {
407 .name = "ge10 base",
408 .start = GE10_PHYS_BASE + 0x2000,
409 .end = GE10_PHYS_BASE + 0x3fff,
410 .flags = IORESOURCE_MEM,
411 },
412};
413
414static struct platform_device mv78xx0_ge10_shared = {
415 .name = MV643XX_ETH_SHARED_NAME,
416 .id = 2,
417 .dev = {
418 .platform_data = &mv78xx0_ge10_shared_data,
419 },
420 .num_resources = 1,
421 .resource = mv78xx0_ge10_shared_resources,
422};
423
424static struct resource mv78xx0_ge10_resources[] = {
425 {
426 .name = "ge10 irq",
427 .start = IRQ_MV78XX0_GE10_SUM,
428 .end = IRQ_MV78XX0_GE10_SUM,
429 .flags = IORESOURCE_IRQ,
430 },
431};
432
433static struct platform_device mv78xx0_ge10 = {
434 .name = MV643XX_ETH_NAME,
435 .id = 2,
436 .num_resources = 1,
437 .resource = mv78xx0_ge10_resources,
438 .dev = {
439 .coherent_dma_mask = 0xffffffff,
440 },
441};
442
443void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) 222void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
444{ 223{
445 u32 dev, rev; 224 u32 dev, rev;
446 225
447 eth_data->shared = &mv78xx0_ge10_shared;
448 mv78xx0_ge10.dev.platform_data = eth_data;
449
450 /* 226 /*
451 * On the Z0, ge10 and ge11 are internally connected back 227 * On the Z0, ge10 and ge11 are internally connected back
452 * to back, and not brought out. 228 * to back, and not brought out.
@@ -458,65 +234,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
458 eth_data->duplex = DUPLEX_FULL; 234 eth_data->duplex = DUPLEX_FULL;
459 } 235 }
460 236
461 platform_device_register(&mv78xx0_ge10_shared); 237 orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
462 platform_device_register(&mv78xx0_ge10); 238 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
239 NO_IRQ, get_tclk());
463} 240}
464 241
465 242
466/***************************************************************************** 243/*****************************************************************************
467 * GE11 244 * GE11
468 ****************************************************************************/ 245 ****************************************************************************/
469struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
470 .t_clk = 0,
471 .dram = &mv78xx0_mbus_dram_info,
472 .shared_smi = &mv78xx0_ge00_shared,
473};
474
475static struct resource mv78xx0_ge11_shared_resources[] = {
476 {
477 .name = "ge11 base",
478 .start = GE11_PHYS_BASE + 0x2000,
479 .end = GE11_PHYS_BASE + 0x3fff,
480 .flags = IORESOURCE_MEM,
481 },
482};
483
484static struct platform_device mv78xx0_ge11_shared = {
485 .name = MV643XX_ETH_SHARED_NAME,
486 .id = 3,
487 .dev = {
488 .platform_data = &mv78xx0_ge11_shared_data,
489 },
490 .num_resources = 1,
491 .resource = mv78xx0_ge11_shared_resources,
492};
493
494static struct resource mv78xx0_ge11_resources[] = {
495 {
496 .name = "ge11 irq",
497 .start = IRQ_MV78XX0_GE11_SUM,
498 .end = IRQ_MV78XX0_GE11_SUM,
499 .flags = IORESOURCE_IRQ,
500 },
501};
502
503static struct platform_device mv78xx0_ge11 = {
504 .name = MV643XX_ETH_NAME,
505 .id = 3,
506 .num_resources = 1,
507 .resource = mv78xx0_ge11_resources,
508 .dev = {
509 .coherent_dma_mask = 0xffffffff,
510 },
511};
512
513void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) 246void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
514{ 247{
515 u32 dev, rev; 248 u32 dev, rev;
516 249
517 eth_data->shared = &mv78xx0_ge11_shared;
518 mv78xx0_ge11.dev.platform_data = eth_data;
519
520 /* 250 /*
521 * On the Z0, ge10 and ge11 are internally connected back 251 * On the Z0, ge10 and ge11 are internally connected back
522 * to back, and not brought out. 252 * to back, and not brought out.
@@ -528,293 +258,68 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
528 eth_data->duplex = DUPLEX_FULL; 258 eth_data->duplex = DUPLEX_FULL;
529 } 259 }
530 260
531 platform_device_register(&mv78xx0_ge11_shared); 261 orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
532 platform_device_register(&mv78xx0_ge11); 262 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
263 NO_IRQ, get_tclk());
533} 264}
534 265
535/***************************************************************************** 266/*****************************************************************************
536 * I2C bus 0 267 * I2C
537 ****************************************************************************/
538
539static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
540 .freq_m = 8, /* assumes 166 MHz TCLK */
541 .freq_n = 3,
542 .timeout = 1000, /* Default timeout of 1 second */
543};
544
545static struct resource mv78xx0_i2c_0_resources[] = {
546 {
547 .start = I2C_0_PHYS_BASE,
548 .end = I2C_0_PHYS_BASE + 0x1f,
549 .flags = IORESOURCE_MEM,
550 }, {
551 .start = IRQ_MV78XX0_I2C_0,
552 .end = IRQ_MV78XX0_I2C_0,
553 .flags = IORESOURCE_IRQ,
554 },
555};
556
557
558static struct platform_device mv78xx0_i2c_0 = {
559 .name = MV64XXX_I2C_CTLR_NAME,
560 .id = 0,
561 .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
562 .resource = mv78xx0_i2c_0_resources,
563 .dev = {
564 .platform_data = &mv78xx0_i2c_0_pdata,
565 },
566};
567
568/*****************************************************************************
569 * I2C bus 1
570 ****************************************************************************/ 268 ****************************************************************************/
571
572static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
573 .freq_m = 8, /* assumes 166 MHz TCLK */
574 .freq_n = 3,
575 .timeout = 1000, /* Default timeout of 1 second */
576};
577
578static struct resource mv78xx0_i2c_1_resources[] = {
579 {
580 .start = I2C_1_PHYS_BASE,
581 .end = I2C_1_PHYS_BASE + 0x1f,
582 .flags = IORESOURCE_MEM,
583 }, {
584 .start = IRQ_MV78XX0_I2C_1,
585 .end = IRQ_MV78XX0_I2C_1,
586 .flags = IORESOURCE_IRQ,
587 },
588};
589
590
591static struct platform_device mv78xx0_i2c_1 = {
592 .name = MV64XXX_I2C_CTLR_NAME,
593 .id = 1,
594 .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
595 .resource = mv78xx0_i2c_1_resources,
596 .dev = {
597 .platform_data = &mv78xx0_i2c_1_pdata,
598 },
599};
600
601void __init mv78xx0_i2c_init(void) 269void __init mv78xx0_i2c_init(void)
602{ 270{
603 platform_device_register(&mv78xx0_i2c_0); 271 orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
604 platform_device_register(&mv78xx0_i2c_1); 272 orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
605} 273}
606 274
607/***************************************************************************** 275/*****************************************************************************
608 * SATA 276 * SATA
609 ****************************************************************************/ 277 ****************************************************************************/
610static struct resource mv78xx0_sata_resources[] = {
611 {
612 .name = "sata base",
613 .start = SATA_PHYS_BASE,
614 .end = SATA_PHYS_BASE + 0x5000 - 1,
615 .flags = IORESOURCE_MEM,
616 }, {
617 .name = "sata irq",
618 .start = IRQ_MV78XX0_SATA,
619 .end = IRQ_MV78XX0_SATA,
620 .flags = IORESOURCE_IRQ,
621 },
622};
623
624static struct platform_device mv78xx0_sata = {
625 .name = "sata_mv",
626 .id = 0,
627 .dev = {
628 .coherent_dma_mask = 0xffffffff,
629 },
630 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
631 .resource = mv78xx0_sata_resources,
632};
633
634void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 278void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
635{ 279{
636 sata_data->dram = &mv78xx0_mbus_dram_info; 280 orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
637 mv78xx0_sata.dev.platform_data = sata_data; 281 SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
638 platform_device_register(&mv78xx0_sata);
639} 282}
640 283
641 284
642/***************************************************************************** 285/*****************************************************************************
643 * UART0 286 * UART0
644 ****************************************************************************/ 287 ****************************************************************************/
645static struct plat_serial8250_port mv78xx0_uart0_data[] = {
646 {
647 .mapbase = UART0_PHYS_BASE,
648 .membase = (char *)UART0_VIRT_BASE,
649 .irq = IRQ_MV78XX0_UART_0,
650 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
651 .iotype = UPIO_MEM,
652 .regshift = 2,
653 .uartclk = 0,
654 }, {
655 },
656};
657
658static struct resource mv78xx0_uart0_resources[] = {
659 {
660 .start = UART0_PHYS_BASE,
661 .end = UART0_PHYS_BASE + 0xff,
662 .flags = IORESOURCE_MEM,
663 }, {
664 .start = IRQ_MV78XX0_UART_0,
665 .end = IRQ_MV78XX0_UART_0,
666 .flags = IORESOURCE_IRQ,
667 },
668};
669
670static struct platform_device mv78xx0_uart0 = {
671 .name = "serial8250",
672 .id = 0,
673 .dev = {
674 .platform_data = mv78xx0_uart0_data,
675 },
676 .resource = mv78xx0_uart0_resources,
677 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
678};
679
680void __init mv78xx0_uart0_init(void) 288void __init mv78xx0_uart0_init(void)
681{ 289{
682 platform_device_register(&mv78xx0_uart0); 290 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
291 IRQ_MV78XX0_UART_0, get_tclk());
683} 292}
684 293
685 294
686/***************************************************************************** 295/*****************************************************************************
687 * UART1 296 * UART1
688 ****************************************************************************/ 297 ****************************************************************************/
689static struct plat_serial8250_port mv78xx0_uart1_data[] = {
690 {
691 .mapbase = UART1_PHYS_BASE,
692 .membase = (char *)UART1_VIRT_BASE,
693 .irq = IRQ_MV78XX0_UART_1,
694 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
695 .iotype = UPIO_MEM,
696 .regshift = 2,
697 .uartclk = 0,
698 }, {
699 },
700};
701
702static struct resource mv78xx0_uart1_resources[] = {
703 {
704 .start = UART1_PHYS_BASE,
705 .end = UART1_PHYS_BASE + 0xff,
706 .flags = IORESOURCE_MEM,
707 }, {
708 .start = IRQ_MV78XX0_UART_1,
709 .end = IRQ_MV78XX0_UART_1,
710 .flags = IORESOURCE_IRQ,
711 },
712};
713
714static struct platform_device mv78xx0_uart1 = {
715 .name = "serial8250",
716 .id = 1,
717 .dev = {
718 .platform_data = mv78xx0_uart1_data,
719 },
720 .resource = mv78xx0_uart1_resources,
721 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
722};
723
724void __init mv78xx0_uart1_init(void) 298void __init mv78xx0_uart1_init(void)
725{ 299{
726 platform_device_register(&mv78xx0_uart1); 300 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
301 IRQ_MV78XX0_UART_1, get_tclk());
727} 302}
728 303
729 304
730/***************************************************************************** 305/*****************************************************************************
731 * UART2 306 * UART2
732 ****************************************************************************/ 307 ****************************************************************************/
733static struct plat_serial8250_port mv78xx0_uart2_data[] = {
734 {
735 .mapbase = UART2_PHYS_BASE,
736 .membase = (char *)UART2_VIRT_BASE,
737 .irq = IRQ_MV78XX0_UART_2,
738 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
739 .iotype = UPIO_MEM,
740 .regshift = 2,
741 .uartclk = 0,
742 }, {
743 },
744};
745
746static struct resource mv78xx0_uart2_resources[] = {
747 {
748 .start = UART2_PHYS_BASE,
749 .end = UART2_PHYS_BASE + 0xff,
750 .flags = IORESOURCE_MEM,
751 }, {
752 .start = IRQ_MV78XX0_UART_2,
753 .end = IRQ_MV78XX0_UART_2,
754 .flags = IORESOURCE_IRQ,
755 },
756};
757
758static struct platform_device mv78xx0_uart2 = {
759 .name = "serial8250",
760 .id = 2,
761 .dev = {
762 .platform_data = mv78xx0_uart2_data,
763 },
764 .resource = mv78xx0_uart2_resources,
765 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
766};
767
768void __init mv78xx0_uart2_init(void) 308void __init mv78xx0_uart2_init(void)
769{ 309{
770 platform_device_register(&mv78xx0_uart2); 310 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
311 IRQ_MV78XX0_UART_2, get_tclk());
771} 312}
772 313
773
774/***************************************************************************** 314/*****************************************************************************
775 * UART3 315 * UART3
776 ****************************************************************************/ 316 ****************************************************************************/
777static struct plat_serial8250_port mv78xx0_uart3_data[] = {
778 {
779 .mapbase = UART3_PHYS_BASE,
780 .membase = (char *)UART3_VIRT_BASE,
781 .irq = IRQ_MV78XX0_UART_3,
782 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
783 .iotype = UPIO_MEM,
784 .regshift = 2,
785 .uartclk = 0,
786 }, {
787 },
788};
789
790static struct resource mv78xx0_uart3_resources[] = {
791 {
792 .start = UART3_PHYS_BASE,
793 .end = UART3_PHYS_BASE + 0xff,
794 .flags = IORESOURCE_MEM,
795 }, {
796 .start = IRQ_MV78XX0_UART_3,
797 .end = IRQ_MV78XX0_UART_3,
798 .flags = IORESOURCE_IRQ,
799 },
800};
801
802static struct platform_device mv78xx0_uart3 = {
803 .name = "serial8250",
804 .id = 3,
805 .dev = {
806 .platform_data = mv78xx0_uart3_data,
807 },
808 .resource = mv78xx0_uart3_resources,
809 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
810};
811
812void __init mv78xx0_uart3_init(void) 317void __init mv78xx0_uart3_init(void)
813{ 318{
814 platform_device_register(&mv78xx0_uart3); 319 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
320 IRQ_MV78XX0_UART_3, get_tclk());
815} 321}
816 322
817
818/***************************************************************************** 323/*****************************************************************************
819 * Time handling 324 * Time handling
820 ****************************************************************************/ 325 ****************************************************************************/
@@ -895,13 +400,4 @@ void __init mv78xx0_init(void)
895#ifdef CONFIG_CACHE_FEROCEON_L2 400#ifdef CONFIG_CACHE_FEROCEON_L2
896 feroceon_l2_init(is_l2_writethrough()); 401 feroceon_l2_init(is_l2_writethrough());
897#endif 402#endif
898
899 mv78xx0_ge00_shared_data.t_clk = tclk;
900 mv78xx0_ge01_shared_data.t_clk = tclk;
901 mv78xx0_ge10_shared_data.t_clk = tclk;
902 mv78xx0_ge11_shared_data.t_clk = tclk;
903 mv78xx0_uart0_data[0].uartclk = tclk;
904 mv78xx0_uart1_data[0].uartclk = tclk;
905 mv78xx0_uart2_data[0].uartclk = tclk;
906 mv78xx0_uart3_data[0].uartclk = tclk;
907} 403}
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 65b72c454cb0..59b7686b9209 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/mpp.h>
15#include <asm/gpio.h> 16#include <asm/gpio.h>
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17#include "common.h" 18#include "common.h"
@@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void)
31 return 0; 32 return 0;
32} 33}
33 34
34#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
35#define MPP_NR_REGS (1 + MPP_MAX/8)
36
37void __init mv78xx0_mpp_conf(unsigned int *mpp_list) 35void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
38{ 36{
39 u32 mpp_ctrl[MPP_NR_REGS]; 37 orion_mpp_conf(mpp_list, mv78xx0_variant(),
40 unsigned int variant_mask; 38 MPP_MAX, DEV_BUS_VIRT_BASE);
41 int i;
42
43 variant_mask = mv78xx0_variant();
44 if (!variant_mask)
45 return;
46
47 printk(KERN_DEBUG "initial MPP regs:");
48 for (i = 0; i < MPP_NR_REGS; i++) {
49 mpp_ctrl[i] = readl(MPP_CTRL(i));
50 printk(" %08x", mpp_ctrl[i]);
51 }
52 printk("\n");
53
54 for ( ; *mpp_list; mpp_list++) {
55 unsigned int num = MPP_NUM(*mpp_list);
56 unsigned int sel = MPP_SEL(*mpp_list);
57 int shift, gpio_mode;
58
59 if (num > MPP_MAX) {
60 printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP "
61 "number (%u)\n", num);
62 continue;
63 }
64 if (!(*mpp_list & variant_mask)) {
65 printk(KERN_WARNING
66 "mv78xx0_mpp_conf: requested MPP%u config "
67 "unavailable on this hardware\n", num);
68 continue;
69 }
70
71 shift = (num & 7) << 2;
72 mpp_ctrl[num / 8] &= ~(0xf << shift);
73 mpp_ctrl[num / 8] |= sel << shift;
74
75 gpio_mode = 0;
76 if (*mpp_list & MPP_INPUT_MASK)
77 gpio_mode |= GPIO_INPUT_OK;
78 if (*mpp_list & MPP_OUTPUT_MASK)
79 gpio_mode |= GPIO_OUTPUT_OK;
80 if (sel != 0)
81 gpio_mode = 0;
82 orion_gpio_set_valid(num, gpio_mode);
83 }
84
85 printk(KERN_DEBUG " final MPP regs:");
86 for (i = 0; i < MPP_NR_REGS; i++) {
87 writel(mpp_ctrl[i], MPP_CTRL(i));
88 printk(" %08x", mpp_ctrl[i]);
89 }
90 printk("\n");
91} 39}
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index 80840b781eaa..b61b50927123 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -19,14 +19,8 @@
19 /* may be output signal */ ((!!(_out)) << 13) | \ 19 /* may be output signal */ ((!!(_out)) << 13) | \
20 /* available on A0 */ ((!!(_78100_A0)) << 14)) 20 /* available on A0 */ ((!!(_78100_A0)) << 14))
21 21
22#define MPP_NUM(x) ((x) & 0xff)
23#define MPP_SEL(x) (((x) >> 8) & 0xf)
24
25 /* num sel i o 78100_A0 */ 22 /* num sel i o 78100_A0 */
26 23
27#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0)
28#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0)
29
30#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) 24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
31 25
32#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) 26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
deleted file mode 100644
index 340809a7d233..000000000000
--- a/arch/arm/mach-mx3/Kconfig
+++ /dev/null
@@ -1,257 +0,0 @@
1if ARCH_MX3
2
3# ARCH_MX31 and ARCH_MX35 are left for compatibility
4# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
5# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
6# more sensible) names are used: SOC_IMX31 and SOC_IMX35
7config ARCH_MX31
8 bool
9
10config ARCH_MX35
11 bool
12
13config SOC_IMX31
14 bool
15 select IMX_HAVE_PLATFORM_MXC_RNGA
16 select ARCH_MXC_AUDMUX_V2
17 select ARCH_MX31
18 select MXC_AVIC
19
20config SOC_IMX35
21 bool
22 select ARCH_MXC_IOMUX_V3
23 select ARCH_MXC_AUDMUX_V2
24 select HAVE_EPIT
25 select ARCH_MX35
26 select MXC_AVIC
27
28comment "MX3 platforms:"
29
30config MACH_MX31ADS
31 bool "Support MX31ADS platforms"
32 select SOC_IMX31
33 select IMX_HAVE_PLATFORM_IMX_I2C
34 select IMX_HAVE_PLATFORM_IMX_SSI
35 select IMX_HAVE_PLATFORM_IMX_UART
36 default y
37 help
38 Include support for MX31ADS platform. This includes specific
39 configurations for the board and its peripherals.
40
41config MACH_MX31ADS_WM1133_EV1
42 bool "Support Wolfson Microelectronics 1133-EV1 module"
43 depends on MACH_MX31ADS
44 depends on MFD_WM8350_I2C
45 depends on REGULATOR_WM8350
46 select MFD_WM8350_CONFIG_MODE_0
47 select MFD_WM8352_CONFIG_MODE_0
48 help
49 Include support for the Wolfson Microelectronics 1133-EV1 PMU
50 and audio module for the MX31ADS platform.
51
52config MACH_PCM037
53 bool "Support Phytec pcm037 (i.MX31) platforms"
54 select SOC_IMX31
55 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
56 select IMX_HAVE_PLATFORM_IMX2_WDT
57 select IMX_HAVE_PLATFORM_IMX_I2C
58 select IMX_HAVE_PLATFORM_IMX_UART
59 select IMX_HAVE_PLATFORM_MXC_EHCI
60 select IMX_HAVE_PLATFORM_MXC_MMC
61 select IMX_HAVE_PLATFORM_MXC_NAND
62 select IMX_HAVE_PLATFORM_MXC_W1
63 select MXC_ULPI if USB_ULPI
64 help
65 Include support for Phytec pcm037 platform. This includes
66 specific configurations for the board and its peripherals.
67
68config MACH_PCM037_EET
69 bool "Support pcm037 EET board extensions"
70 depends on MACH_PCM037
71 select IMX_HAVE_PLATFORM_SPI_IMX
72 help
73 Add support for PCM037 EET baseboard extensions. If you are using the
74 OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
75 command-line parameter.
76
77config MACH_MX31LITE
78 bool "Support MX31 LITEKIT (LogicPD)"
79 select SOC_IMX31
80 select MXC_ULPI if USB_ULPI
81 select IMX_HAVE_PLATFORM_IMX2_WDT
82 select IMX_HAVE_PLATFORM_IMX_UART
83 select IMX_HAVE_PLATFORM_MXC_EHCI
84 select IMX_HAVE_PLATFORM_MXC_MMC
85 select IMX_HAVE_PLATFORM_MXC_NAND
86 select IMX_HAVE_PLATFORM_SPI_IMX
87 help
88 Include support for MX31 LITEKIT platform. This includes specific
89 configurations for the board and its peripherals.
90
91config MACH_MX31_3DS
92 bool "Support MX31PDK (3DS)"
93 select SOC_IMX31
94 select MXC_DEBUG_BOARD
95 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
96 select IMX_HAVE_PLATFORM_IMX2_WDT
97 select IMX_HAVE_PLATFORM_IMX_I2C
98 select IMX_HAVE_PLATFORM_IMX_KEYPAD
99 select IMX_HAVE_PLATFORM_IMX_UART
100 select IMX_HAVE_PLATFORM_MXC_EHCI
101 select IMX_HAVE_PLATFORM_MXC_NAND
102 select IMX_HAVE_PLATFORM_SPI_IMX
103 select MXC_ULPI if USB_ULPI
104 help
105 Include support for MX31PDK (3DS) platform. This includes specific
106 configurations for the board and its peripherals.
107
108config MACH_MX31_3DS_MXC_NAND_USE_BBT
109 bool "Make the MXC NAND driver use the in flash Bad Block Table"
110 depends on MACH_MX31_3DS
111 depends on MTD_NAND_MXC
112 help
113 Enable this if you want that the MXC NAND driver uses the in flash
114 Bad Block Table to know what blocks are bad instead of scanning the
115 entire flash looking for bad block markers.
116
117config MACH_MX31MOBOARD
118 bool "Support mx31moboard platforms (EPFL Mobots group)"
119 select SOC_IMX31
120 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
121 select IMX_HAVE_PLATFORM_IMX_I2C
122 select IMX_HAVE_PLATFORM_IMX_UART
123 select IMX_HAVE_PLATFORM_MXC_EHCI
124 select IMX_HAVE_PLATFORM_MXC_MMC
125 select IMX_HAVE_PLATFORM_SPI_IMX
126 select MXC_ULPI if USB_ULPI
127 help
128 Include support for mx31moboard platform. This includes specific
129 configurations for the board and its peripherals.
130
131config MACH_MX31LILLY
132 bool "Support MX31 LILLY-1131 platforms (INCO startec)"
133 select SOC_IMX31
134 select IMX_HAVE_PLATFORM_IMX_UART
135 select IMX_HAVE_PLATFORM_MXC_EHCI
136 select IMX_HAVE_PLATFORM_MXC_MMC
137 select IMX_HAVE_PLATFORM_SPI_IMX
138 select MXC_ULPI if USB_ULPI
139 help
140 Include support for mx31 based LILLY1131 modules. This includes
141 specific configurations for the board and its peripherals.
142
143config MACH_QONG
144 bool "Support Dave/DENX QongEVB-LITE platform"
145 select SOC_IMX31
146 select IMX_HAVE_PLATFORM_IMX_UART
147 help
148 Include support for Dave/DENX QongEVB-LITE platform. This includes
149 specific configurations for the board and its peripherals.
150
151config MACH_PCM043
152 bool "Support Phytec pcm043 (i.MX35) platforms"
153 select SOC_IMX35
154 select IMX_HAVE_PLATFORM_FLEXCAN
155 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
156 select IMX_HAVE_PLATFORM_IMX2_WDT
157 select IMX_HAVE_PLATFORM_IMX_I2C
158 select IMX_HAVE_PLATFORM_IMX_SSI
159 select IMX_HAVE_PLATFORM_IMX_UART
160 select IMX_HAVE_PLATFORM_MXC_EHCI
161 select IMX_HAVE_PLATFORM_MXC_NAND
162 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
163 select MXC_ULPI if USB_ULPI
164 help
165 Include support for Phytec pcm043 platform. This includes
166 specific configurations for the board and its peripherals.
167
168config MACH_ARMADILLO5X0
169 bool "Support Atmark Armadillo-500 Development Base Board"
170 select SOC_IMX31
171 select IMX_HAVE_PLATFORM_IMX_I2C
172 select IMX_HAVE_PLATFORM_IMX_UART
173 select IMX_HAVE_PLATFORM_MXC_EHCI
174 select IMX_HAVE_PLATFORM_MXC_MMC
175 select IMX_HAVE_PLATFORM_MXC_NAND
176 select MXC_ULPI if USB_ULPI
177 help
178 Include support for Atmark Armadillo-500 platform. This includes
179 specific configurations for the board and its peripherals.
180
181config MACH_MX35_3DS
182 bool "Support MX35PDK platform"
183 select SOC_IMX35
184 select MXC_DEBUG_BOARD
185 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
186 select IMX_HAVE_PLATFORM_IMX2_WDT
187 select IMX_HAVE_PLATFORM_IMX_I2C
188 select IMX_HAVE_PLATFORM_IMX_UART
189 select IMX_HAVE_PLATFORM_MXC_EHCI
190 select IMX_HAVE_PLATFORM_MXC_NAND
191 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
192 help
193 Include support for MX35PDK platform. This includes specific
194 configurations for the board and its peripherals.
195
196config MACH_KZM_ARM11_01
197 bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
198 select SOC_IMX31
199 select IMX_HAVE_PLATFORM_IMX_UART
200 help
201 Include support for KZM-ARM11-01. This includes specific
202 configurations for the board and its peripherals.
203
204config MACH_BUG
205 bool "Support Buglabs BUGBase platform"
206 select SOC_IMX31
207 select IMX_HAVE_PLATFORM_IMX_UART
208 default y
209 help
210 Include support for BUGBase 1.3 platform. This includes specific
211 configurations for the board and its peripherals.
212
213config MACH_EUKREA_CPUIMX35
214 bool "Support Eukrea CPUIMX35 Platform"
215 select SOC_IMX35
216 select IMX_HAVE_PLATFORM_FLEXCAN
217 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
218 select IMX_HAVE_PLATFORM_IMX2_WDT
219 select IMX_HAVE_PLATFORM_IMX_I2C
220 select IMX_HAVE_PLATFORM_IMX_UART
221 select IMX_HAVE_PLATFORM_MXC_EHCI
222 select IMX_HAVE_PLATFORM_MXC_NAND
223 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
224 select MXC_ULPI if USB_ULPI
225 help
226 Include support for Eukrea CPUIMX35 platform. This includes
227 specific configurations for the board and its peripherals.
228
229choice
230 prompt "Baseboard"
231 depends on MACH_EUKREA_CPUIMX35
232 default MACH_EUKREA_MBIMXSD35_BASEBOARD
233
234config MACH_EUKREA_MBIMXSD35_BASEBOARD
235 bool "Eukrea MBIMXSD development board"
236 select IMX_HAVE_PLATFORM_IMX_SSI
237 help
238 This adds board specific devices that can be found on Eukrea's
239 MBIMXSD evaluation board.
240
241endchoice
242
243config MACH_VPR200
244 bool "Support VPR200 platform"
245 select SOC_IMX35
246 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
247 select IMX_HAVE_PLATFORM_IMX2_WDT
248 select IMX_HAVE_PLATFORM_IMX_UART
249 select IMX_HAVE_PLATFORM_IMX_I2C
250 select IMX_HAVE_PLATFORM_MXC_EHCI
251 select IMX_HAVE_PLATFORM_MXC_NAND
252 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
253 help
254 Include support for VPR200 platform. This includes specific
255 configurations for the board and its peripherals.
256
257endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
deleted file mode 100644
index a54faf2cf5fa..000000000000
--- a/arch/arm/mach-mx3/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := mm.o devices.o cpu.o
8obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
9obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
10obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
11obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
12obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
13obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
14obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
15obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
16obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
17 mx31moboard-marxbot.o mx31moboard-smartbot.o
18obj-$(CONFIG_MACH_QONG) += mach-qong.o
19obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
20obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
21obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
22obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
23obj-$(CONFIG_MACH_BUG) += mach-bug.o
24obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
25obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
26obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot
deleted file mode 100644
index e1dd366f836b..000000000000
--- a/arch/arm/mach-mx3/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
deleted file mode 100644
index b6672db788fb..000000000000
--- a/arch/arm/mach-mx3/devices.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/serial.h>
24#include <linux/gpio.h>
25#include <mach/hardware.h>
26#include <mach/irqs.h>
27#include <mach/common.h>
28#include <mach/mx3_camera.h>
29
30#include "devices.h"
31
32/* i.MX31 Image Processing Unit */
33
34/* The resource order is important! */
35static struct resource mx3_ipu_rsrc[] = {
36 {
37 .start = MX3x_IPU_CTRL_BASE_ADDR,
38 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
39 .flags = IORESOURCE_MEM,
40 }, {
41 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
42 .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
43 .flags = IORESOURCE_MEM,
44 }, {
45 .start = MX3x_INT_IPU_SYN,
46 .end = MX3x_INT_IPU_SYN,
47 .flags = IORESOURCE_IRQ,
48 }, {
49 .start = MX3x_INT_IPU_ERR,
50 .end = MX3x_INT_IPU_ERR,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55struct platform_device mx3_ipu = {
56 .name = "ipu-core",
57 .id = -1,
58 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
59 .resource = mx3_ipu_rsrc,
60};
61
62static struct resource fb_resources[] = {
63 {
64 .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
65 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
66 .flags = IORESOURCE_MEM,
67 },
68};
69
70struct platform_device mx3_fb = {
71 .name = "mx3_sdc_fb",
72 .id = -1,
73 .num_resources = ARRAY_SIZE(fb_resources),
74 .resource = fb_resources,
75 .dev = {
76 .coherent_dma_mask = DMA_BIT_MASK(32),
77 },
78};
79
80static struct resource camera_resources[] = {
81 {
82 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
83 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
84 .flags = IORESOURCE_MEM,
85 },
86};
87
88struct platform_device mx3_camera = {
89 .name = "mx3-camera",
90 .id = 0,
91 .num_resources = ARRAY_SIZE(camera_resources),
92 .resource = camera_resources,
93 .dev = {
94 .coherent_dma_mask = DMA_BIT_MASK(32),
95 },
96};
97
98static struct resource imx_rtc_resources[] = {
99 {
100 .start = MX31_RTC_BASE_ADDR,
101 .end = MX31_RTC_BASE_ADDR + 0x3fff,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .start = MX31_INT_RTC,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110struct platform_device imx_rtc_device0 = {
111 .name = "mxc_rtc",
112 .id = -1,
113 .num_resources = ARRAY_SIZE(imx_rtc_resources),
114 .resource = imx_rtc_resources,
115};
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
deleted file mode 100644
index 121962c568d1..000000000000
--- a/arch/arm/mach-mx3/devices.h
+++ /dev/null
@@ -1,4 +0,0 @@
1extern struct platform_device mx3_ipu;
2extern struct platform_device mx3_fb;
3extern struct platform_device mx3_camera;
4extern struct platform_device imx_rtc_device0;
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
deleted file mode 100644
index 54d7174b4202..000000000000
--- a/arch/arm/mach-mx3/mm.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25#include <asm/hardware/cache-l2x0.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-v3.h>
30#include <mach/gpio.h>
31#include <mach/irqs.h>
32
33#ifdef CONFIG_SOC_IMX31
34static struct map_desc mx31_io_desc[] __initdata = {
35 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
36 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
38 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
39 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
40};
41
42/*
43 * This function initializes the memory map. It is called during the
44 * system startup to create static physical to virtual memory mappings
45 * for the IO modules.
46 */
47void __init mx31_map_io(void)
48{
49 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
50}
51
52void __init imx31_init_early(void)
53{
54 mxc_set_cpu_type(MXC_CPU_MX31);
55 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
56}
57
58static struct mxc_gpio_port imx31_gpio_ports[] = {
59 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
60 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
61 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
62};
63
64void __init mx31_init_irq(void)
65{
66 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
67 mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
68}
69#endif /* ifdef CONFIG_SOC_IMX31 */
70
71#ifdef CONFIG_SOC_IMX35
72static struct map_desc mx35_io_desc[] __initdata = {
73 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
74 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
75 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
76 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
77 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
78};
79
80void __init mx35_map_io(void)
81{
82 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
83}
84
85void __init imx35_init_early(void)
86{
87 mxc_set_cpu_type(MXC_CPU_MX35);
88 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
89 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
90}
91
92static struct mxc_gpio_port imx35_gpio_ports[] = {
93 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
94 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
95 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
96};
97
98void __init mx35_init_irq(void)
99{
100 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
101 mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
102}
103#endif /* ifdef CONFIG_SOC_IMX35 */
104
105#ifdef CONFIG_CACHE_L2X0
106static int mxc_init_l2x0(void)
107{
108 void __iomem *l2x0_base;
109 void __iomem *clkctl_base;
110/*
111 * First of all, we must repair broken chip settings. There are some
112 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
113 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
114 * Workaraound is to setup the correct register setting prior enabling the
115 * L2 cache. This should not hurt already working CPUs, as they are using the
116 * same value
117 */
118#define L2_MEM_VAL 0x10
119
120 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
121 if (clkctl_base != NULL) {
122 writel(0x00000515, clkctl_base + L2_MEM_VAL);
123 iounmap(clkctl_base);
124 } else {
125 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
126 }
127
128 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
129 if (IS_ERR(l2x0_base)) {
130 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
131 PTR_ERR(l2x0_base));
132 return 0;
133 }
134
135 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
136
137 return 0;
138}
139
140arch_initcall(mxc_init_l2x0);
141#endif
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 159340da9191..799fbc40e53c 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,11 +1,11 @@
1if ARCH_MX5 1if ARCH_MX503 || ARCH_MX51
2# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single 2# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
3# image. So for most time, SOC_IMX50/51/53 should be used. 3# image. So for most time, SOC_IMX50/51/53 should be used.
4 4
5config ARCH_MX50 5config ARCH_MX5
6 bool 6 bool
7 7
8config ARCH_MX51 8config ARCH_MX50
9 bool 9 bool
10 10
11config ARCH_MX53 11config ARCH_MX53
@@ -13,27 +13,54 @@ config ARCH_MX53
13 13
14config SOC_IMX50 14config SOC_IMX50
15 bool 15 bool
16 select CPU_V7
17 select ARM_L1_CACHE_SHIFT_6
16 select MXC_TZIC 18 select MXC_TZIC
17 select ARCH_MXC_IOMUX_V3 19 select ARCH_MXC_IOMUX_V3
18 select ARCH_MXC_AUDMUX_V2 20 select ARCH_MXC_AUDMUX_V2
19 select ARCH_HAS_CPUFREQ 21 select ARCH_HAS_CPUFREQ
22 select ARCH_MX5
20 select ARCH_MX50 23 select ARCH_MX50
21 24
22config SOC_IMX51 25config SOC_IMX51
23 bool 26 bool
27 select CPU_V7
28 select ARM_L1_CACHE_SHIFT_6
24 select MXC_TZIC 29 select MXC_TZIC
25 select ARCH_MXC_IOMUX_V3 30 select ARCH_MXC_IOMUX_V3
26 select ARCH_MXC_AUDMUX_V2 31 select ARCH_MXC_AUDMUX_V2
27 select ARCH_HAS_CPUFREQ 32 select ARCH_HAS_CPUFREQ
28 select ARCH_MX51 33 select ARCH_MX5
29 34
30config SOC_IMX53 35config SOC_IMX53
31 bool 36 bool
37 select CPU_V7
38 select ARM_L1_CACHE_SHIFT_6
32 select MXC_TZIC 39 select MXC_TZIC
33 select ARCH_MXC_IOMUX_V3 40 select ARCH_MXC_IOMUX_V3
41 select ARCH_MX5
34 select ARCH_MX53 42 select ARCH_MX53
35 43
36comment "MX5 platforms:" 44if ARCH_MX50_SUPPORTED
45#comment "i.MX50 machines:"
46
47config MACH_MX50_RDP
48 bool "Support MX50 reference design platform"
49 depends on BROKEN
50 select SOC_IMX50
51 select IMX_HAVE_PLATFORM_IMX_I2C
52 select IMX_HAVE_PLATFORM_IMX_UART
53 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
54 select IMX_HAVE_PLATFORM_SPI_IMX
55 select IMX_HAVE_PLATFORM_FEC
56 help
57 Include support for MX50 reference design platform (RDP) board. This
58 includes specific configurations for the board and its peripherals.
59
60endif # ARCH_MX50_SUPPORTED
61
62if ARCH_MX51
63comment "i.MX51 machines:"
37 64
38config MACH_MX51_BABBAGE 65config MACH_MX51_BABBAGE
39 bool "Support MX51 BABBAGE platforms" 66 bool "Support MX51 BABBAGE platforms"
@@ -136,6 +163,11 @@ config MACH_MX51_EFIKASB
136 Include support for Genesi Efika Smartbook. This includes specific 163 Include support for Genesi Efika Smartbook. This includes specific
137 configurations for the board and its peripherals. 164 configurations for the board and its peripherals.
138 165
166endif # ARCH_MX51
167
168if ARCH_MX53_SUPPORTED
169comment "i.MX53 machines:"
170
139config MACH_MX53_EVK 171config MACH_MX53_EVK
140 bool "Support MX53 EVK platforms" 172 bool "Support MX53 EVK platforms"
141 select SOC_IMX53 173 select SOC_IMX53
@@ -154,6 +186,7 @@ config MACH_MX53_SMD
154 select IMX_HAVE_PLATFORM_IMX2_WDT 186 select IMX_HAVE_PLATFORM_IMX2_WDT
155 select IMX_HAVE_PLATFORM_IMX_I2C 187 select IMX_HAVE_PLATFORM_IMX_I2C
156 select IMX_HAVE_PLATFORM_IMX_UART 188 select IMX_HAVE_PLATFORM_IMX_UART
189 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
157 help 190 help
158 Include support for MX53 SMD platform. This includes specific 191 Include support for MX53 SMD platform. This includes specific
159 configurations for the board and its peripherals. 192 configurations for the board and its peripherals.
@@ -170,17 +203,6 @@ config MACH_MX53_LOCO
170 Include support for MX53 LOCO platform. This includes specific 203 Include support for MX53 LOCO platform. This includes specific
171 configurations for the board and its peripherals. 204 configurations for the board and its peripherals.
172 205
173config MACH_MX50_RDP 206endif # ARCH_MX53_SUPPORTED
174 bool "Support MX50 reference design platform"
175 depends on BROKEN
176 select SOC_IMX50
177 select IMX_HAVE_PLATFORM_IMX_I2C
178 select IMX_HAVE_PLATFORM_IMX_UART
179 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
180 select IMX_HAVE_PLATFORM_SPI_IMX
181 select IMX_HAVE_PLATFORM_FEC
182 help
183 Include support for MX50 reference design platform (RDP) board. This
184 includes specific configurations for the board and its peripherals.
185 207
186endif 208endif
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index d0296a94c475..4efa02ee1639 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -23,13 +23,11 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/fsl_devices.h>
27 26
28#include <mach/eukrea-baseboards.h> 27#include <mach/eukrea-baseboards.h>
29#include <mach/common.h> 28#include <mach/common.h>
30#include <mach/hardware.h> 29#include <mach/hardware.h>
31#include <mach/iomux-mx51.h> 30#include <mach/iomux-mx51.h>
32#include <mach/mxc_ehci.h>
33 31
34#include <asm/irq.h> 32#include <asm/irq.h>
35#include <asm/setup.h> 33#include <asm/setup.h>
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 29b180823bf5..5ef25a596143 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -23,7 +23,6 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/fsl_devices.h>
27#include <linux/i2c-gpio.h> 26#include <linux/i2c-gpio.h>
28#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
29#include <linux/can/platform/mcp251x.h> 28#include <linux/can/platform/mcp251x.h>
@@ -32,7 +31,6 @@
32#include <mach/common.h> 31#include <mach/common.h>
33#include <mach/hardware.h> 32#include <mach/hardware.h>
34#include <mach/iomux-mx51.h> 33#include <mach/iomux-mx51.h>
35#include <mach/mxc_ehci.h>
36 34
37#include <asm/irq.h> 35#include <asm/irq.h>
38#include <asm/setup.h> 36#include <asm/setup.h>
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index dedf7f2d6d0f..11210e1ae42a 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -23,7 +23,6 @@
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/fsl_devices.h>
27 26
28#include <mach/common.h> 27#include <mach/common.h>
29#include <mach/hardware.h> 28#include <mach/hardware.h>
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index bea4e4135f9d..c7b3fabf50f9 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -16,9 +16,6 @@
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/fsl_devices.h>
20#include <linux/fec.h>
21#include <linux/gpio_keys.h>
22#include <linux/input.h> 19#include <linux/input.h>
23#include <linux/spi/flash.h> 20#include <linux/spi/flash.h>
24#include <linux/spi/spi.h> 21#include <linux/spi/spi.h>
@@ -26,7 +23,6 @@
26#include <mach/common.h> 23#include <mach/common.h>
27#include <mach/hardware.h> 24#include <mach/hardware.h>
28#include <mach/iomux-mx51.h> 25#include <mach/iomux-mx51.h>
29#include <mach/mxc_ehci.h>
30 26
31#include <asm/irq.h> 27#include <asm/irq.h>
32#include <asm/setup.h> 28#include <asm/setup.h>
@@ -208,18 +204,16 @@ static inline void babbage_usbhub_reset(void)
208{ 204{
209 int ret; 205 int ret;
210 206
211 /* Bring USB hub out of reset */ 207 /* Reset USB hub */
212 ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7"); 208 ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
209 GPIOF_OUT_INIT_LOW, "GPIO1_7");
213 if (ret) { 210 if (ret) {
214 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); 211 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
215 return; 212 return;
216 } 213 }
217 gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
218 214
219 /* USB HUB RESET - De-assert USB HUB RESET_N */ 215 msleep(2);
220 msleep(1); 216 /* Deassert reset */
221 gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
222 msleep(1);
223 gpio_set_value(BABBAGE_USB_HUB_RESET, 1); 217 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
224} 218}
225 219
@@ -361,7 +355,7 @@ static void __init mx51_babbage_init(void)
361 355
362 /* Set the PAD settings for the pwr key. */ 356 /* Set the PAD settings for the pwr key. */
363 mxc_iomux_v3_setup_pad(power_key); 357 mxc_iomux_v3_setup_pad(power_key);
364 imx51_add_gpio_keys(&imx_button_data); 358 imx_add_gpio_keys(&imx_button_data);
365 359
366 imx51_add_imx_i2c(0, &babbage_i2c_data); 360 imx51_add_imx_i2c(0, &babbage_i2c_data);
367 imx51_add_imx_i2c(1, &babbage_i2c_data); 361 imx51_add_imx_i2c(1, &babbage_i2c_data);
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index acab1911cb3c..6e362315291b 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -22,7 +22,6 @@
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/fsl_devices.h>
26#include <linux/spi/flash.h> 25#include <linux/spi/flash.h>
27#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
28#include <linux/mfd/mc13892.h> 27#include <linux/mfd/mc13892.h>
@@ -32,8 +31,6 @@
32#include <mach/common.h> 31#include <mach/common.h>
33#include <mach/hardware.h> 32#include <mach/hardware.h>
34#include <mach/iomux-mx51.h> 33#include <mach/iomux-mx51.h>
35#include <mach/i2c.h>
36#include <mach/mxc_ehci.h>
37 34
38#include <asm/irq.h> 35#include <asm/irq.h>
39#include <asm/setup.h> 36#include <asm/setup.h>
@@ -252,7 +249,7 @@ static void __init mx51_efikamx_init(void)
252 } 249 }
253 250
254 platform_device_register(&mx51_efikamx_leds_device); 251 platform_device_register(&mx51_efikamx_leds_device);
255 imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); 252 imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
256 253
257 if (system_rev == 0x11) { 254 if (system_rev == 0x11) {
258 gpio_request(EFIKAMX_RESET1_1, "reset"); 255 gpio_request(EFIKAMX_RESET1_1, "reset");
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index db04ce8462dc..474fc6e4c6df 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -22,7 +22,6 @@
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/fsl_devices.h>
26#include <linux/spi/flash.h> 25#include <linux/spi/flash.h>
27#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
28#include <linux/mfd/mc13892.h> 27#include <linux/mfd/mc13892.h>
@@ -35,8 +34,6 @@
35#include <mach/common.h> 34#include <mach/common.h>
36#include <mach/hardware.h> 35#include <mach/hardware.h>
37#include <mach/iomux-mx51.h> 36#include <mach/iomux-mx51.h>
38#include <mach/i2c.h>
39#include <mach/mxc_ehci.h>
40 37
41#include <asm/irq.h> 38#include <asm/irq.h>
42#include <asm/setup.h> 39#include <asm/setup.h>
@@ -260,7 +257,7 @@ static void __init efikasb_board_init(void)
260 imx51_add_sdhci_esdhc_imx(1, NULL); 257 imx51_add_sdhci_esdhc_imx(1, NULL);
261 258
262 platform_device_register(&mx51_efikasb_leds_device); 259 platform_device_register(&mx51_efikasb_leds_device);
263 imx51_add_gpio_keys(&mx51_efikasb_keys_data); 260 imx_add_gpio_keys(&mx51_efikasb_keys_data);
264 261
265} 262}
266 263
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 2af3f43f74db..f87d571882c6 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -21,7 +21,6 @@
21 21
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/fec.h>
25#include <linux/delay.h> 24#include <linux/delay.h>
26#include <linux/gpio.h> 25#include <linux/gpio.h>
27#include <linux/spi/flash.h> 26#include <linux/spi/flash.h>
@@ -31,7 +30,6 @@
31#include <asm/mach-types.h> 30#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
33#include <asm/mach/time.h> 32#include <asm/mach/time.h>
34#include <mach/imx-uart.h>
35#include <mach/iomux-mx53.h> 33#include <mach/iomux-mx53.h>
36 34
37#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) 35#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 6206b1191fe8..1b947e8c9c0c 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -20,13 +20,11 @@
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/fec.h>
24#include <linux/delay.h> 23#include <linux/delay.h>
25#include <linux/gpio.h> 24#include <linux/gpio.h>
26 25
27#include <mach/common.h> 26#include <mach/common.h>
28#include <mach/hardware.h> 27#include <mach/hardware.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx53.h> 28#include <mach/iomux-mx53.h>
31 29
32#include <asm/mach-types.h> 30#include <asm/mach-types.h>
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 31e173267edf..817c08938f55 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -20,13 +20,11 @@
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/fec.h>
24#include <linux/delay.h> 23#include <linux/delay.h>
25#include <linux/gpio.h> 24#include <linux/gpio.h>
26 25
27#include <mach/common.h> 26#include <mach/common.h>
28#include <mach/hardware.h> 27#include <mach/hardware.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx53.h> 28#include <mach/iomux-mx53.h>
31 29
32#include <asm/mach-types.h> 30#include <asm/mach-types.h>
@@ -52,6 +50,31 @@ static iomux_v3_cfg_t mx53_smd_pads[] = {
52 /* I2C1 */ 50 /* I2C1 */
53 MX53_PAD_CSI0_DAT8__I2C1_SDA, 51 MX53_PAD_CSI0_DAT8__I2C1_SDA,
54 MX53_PAD_CSI0_DAT9__I2C1_SCL, 52 MX53_PAD_CSI0_DAT9__I2C1_SCL,
53 /* SD1 */
54 MX53_PAD_SD1_CMD__ESDHC1_CMD,
55 MX53_PAD_SD1_CLK__ESDHC1_CLK,
56 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
57 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
58 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
59 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
60 /* SD2 */
61 MX53_PAD_SD2_CMD__ESDHC2_CMD,
62 MX53_PAD_SD2_CLK__ESDHC2_CLK,
63 MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
64 MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
65 MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
66 MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
67 /* SD3 */
68 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
69 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
70 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
71 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
72 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
73 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
74 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
75 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
76 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
77 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
55}; 78};
56 79
57static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { 80static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -97,6 +120,9 @@ static void __init mx53_smd_board_init(void)
97 imx53_add_fec(&mx53_smd_fec_data); 120 imx53_add_fec(&mx53_smd_fec_data);
98 imx53_add_imx2_wdt(0, NULL); 121 imx53_add_imx2_wdt(0, NULL);
99 imx53_add_imx_i2c(0, &mx53_smd_i2c_data); 122 imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
123 imx53_add_sdhci_esdhc_imx(0, NULL);
124 imx53_add_sdhci_esdhc_imx(1, NULL);
125 imx53_add_sdhci_esdhc_imx(2, NULL);
100} 126}
101 127
102static void __init mx53_smd_timer_init(void) 128static void __init mx53_smd_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index fdbc05ed5513..6b89c1bf4eb2 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1563,6 +1563,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1563 clk_enable(&iim_clk); 1563 clk_enable(&iim_clk);
1564 mx53_revision(); 1564 mx53_revision();
1565 clk_disable(&iim_clk); 1565 clk_disable(&iim_clk);
1566 mx53_display_revision();
1566 1567
1567 /* Set SDHC parents to be PLL2 */ 1568 /* Set SDHC parents to be PLL2 */
1568 clk_set_parent(&esdhc1_clk, &pll2_sw_clk); 1569 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 472bdfab2e55..86f87da59c64 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -166,6 +166,29 @@ int mx50_revision(void)
166} 166}
167EXPORT_SYMBOL(mx50_revision); 167EXPORT_SYMBOL(mx50_revision);
168 168
169void mx53_display_revision(void)
170{
171 int rev;
172 char *srev;
173 rev = mx53_revision();
174
175 switch (rev) {
176 case IMX_CHIP_REVISION_1_0:
177 srev = IMX_CHIP_REVISION_1_0_STRING;
178 break;
179 case IMX_CHIP_REVISION_2_0:
180 srev = IMX_CHIP_REVISION_2_0_STRING;
181 break;
182 case IMX_CHIP_REVISION_2_1:
183 srev = IMX_CHIP_REVISION_2_1_STRING;
184 break;
185 default:
186 srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
187 }
188 printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
189}
190EXPORT_SYMBOL(mx53_display_revision);
191
169static int __init post_cpu_init(void) 192static int __init post_cpu_init(void)
170{ 193{
171 unsigned int reg; 194 unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
index c9e42823c7e3..7216667eaafc 100644
--- a/arch/arm/mach-mx5/devices-imx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -21,14 +21,14 @@
21#include <mach/mx50.h> 21#include <mach/mx50.h>
22#include <mach/devices-common.h> 22#include <mach/devices-common.h>
23 23
24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; 24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
25#define imx50_add_imx_uart(id, pdata) \ 25#define imx50_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) 26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
27 27
28extern const struct imx_fec_data imx50_fec_data __initconst; 28extern const struct imx_fec_data imx50_fec_data;
29#define imx50_add_fec(pdata) \ 29#define imx50_add_fec(pdata) \
30 imx_add_fec(&imx50_fec_data, pdata) 30 imx_add_fec(&imx50_fec_data, pdata)
31 31
32extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst; 32extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
33#define imx50_add_imx_i2c(id, pdata) \ 33#define imx50_add_imx_i2c(id, pdata) \
34 imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata) 34 imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index 7fff485e5603..e11bc0e0ec49 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -9,49 +9,46 @@
9#include <mach/mx51.h> 9#include <mach/mx51.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fec_data imx51_fec_data __initconst; 12extern const struct imx_fec_data imx51_fec_data;
13#define imx51_add_fec(pdata) \ 13#define imx51_add_fec(pdata) \
14 imx_add_fec(&imx51_fec_data, pdata) 14 imx_add_fec(&imx51_fec_data, pdata)
15 15
16#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata) 16extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
17
18extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
19#define imx51_add_imx_i2c(id, pdata) \ 17#define imx51_add_imx_i2c(id, pdata) \
20 imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) 18 imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
21 19
22extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst; 20extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
23#define imx51_add_imx_ssi(id, pdata) \ 21#define imx51_add_imx_ssi(id, pdata) \
24 imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata) 22 imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
25 23
26extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; 24extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
27#define imx51_add_imx_uart(id, pdata) \ 25#define imx51_add_imx_uart(id, pdata) \
28 imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) 26 imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
29 27
30extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst; 28extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
31#define imx51_add_mxc_nand(pdata) \ 29#define imx51_add_mxc_nand(pdata) \
32 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) 30 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
33 31
34extern const struct imx_sdhci_esdhc_imx_data 32extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
35imx51_sdhci_esdhc_imx_data[] __initconst;
36#define imx51_add_sdhci_esdhc_imx(id, pdata) \ 33#define imx51_add_sdhci_esdhc_imx(id, pdata) \
37 imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) 34 imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
38 35
39extern const struct imx_spi_imx_data imx51_cspi_data __initconst; 36extern const struct imx_spi_imx_data imx51_cspi_data;
40#define imx51_add_cspi(pdata) \ 37#define imx51_add_cspi(pdata) \
41 imx_add_spi_imx(&imx51_cspi_data, pdata) 38 imx_add_spi_imx(&imx51_cspi_data, pdata)
42 39
43extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; 40extern const struct imx_spi_imx_data imx51_ecspi_data[];
44#define imx51_add_ecspi(id, pdata) \ 41#define imx51_add_ecspi(id, pdata) \
45 imx_add_spi_imx(&imx51_ecspi_data[id], pdata) 42 imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
46 43
47extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst; 44extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
48#define imx51_add_imx2_wdt(id, pdata) \ 45#define imx51_add_imx2_wdt(id, pdata) \
49 imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) 46 imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
50 47
51extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst; 48extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
52#define imx51_add_mxc_pwm(id) \ 49#define imx51_add_mxc_pwm(id) \
53 imx_add_mxc_pwm(&imx51_mxc_pwm_data[id]) 50 imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
54 51
55extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst; 52extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
56#define imx51_add_imx_keypad(pdata) \ 53#define imx51_add_imx_keypad(pdata) \
57 imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) 54 imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 9251008dad1f..48f4c8cc42f5 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -8,28 +8,27 @@
8#include <mach/mx53.h> 8#include <mach/mx53.h>
9#include <mach/devices-common.h> 9#include <mach/devices-common.h>
10 10
11extern const struct imx_fec_data imx53_fec_data __initconst; 11extern const struct imx_fec_data imx53_fec_data;
12#define imx53_add_fec(pdata) \ 12#define imx53_add_fec(pdata) \
13 imx_add_fec(&imx53_fec_data, pdata) 13 imx_add_fec(&imx53_fec_data, pdata)
14 14
15extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst; 15extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
16#define imx53_add_imx_uart(id, pdata) \ 16#define imx53_add_imx_uart(id, pdata) \
17 imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) 17 imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
18 18
19 19
20extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst; 20extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
21#define imx53_add_imx_i2c(id, pdata) \ 21#define imx53_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) 22 imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
23 23
24extern const struct imx_sdhci_esdhc_imx_data 24extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
25imx53_sdhci_esdhc_imx_data[] __initconst;
26#define imx53_add_sdhci_esdhc_imx(id, pdata) \ 25#define imx53_add_sdhci_esdhc_imx(id, pdata) \
27 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) 26 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
28 27
29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst; 28extern const struct imx_spi_imx_data imx53_ecspi_data[];
30#define imx53_add_ecspi(id, pdata) \ 29#define imx53_add_ecspi(id, pdata) \
31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata) 30 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
32 31
33extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst; 32extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
34#define imx53_add_imx2_wdt(id, pdata) \ 33#define imx53_add_imx2_wdt(id, pdata) \
35 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) 34 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index 4a8550529b04..97292d20f1f3 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -18,13 +18,11 @@
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/fsl_devices.h>
22#include <linux/i2c/tsc2007.h> 21#include <linux/i2c/tsc2007.h>
23#include <linux/leds.h> 22#include <linux/leds.h>
24 23
25#include <mach/common.h> 24#include <mach/common.h>
26#include <mach/hardware.h> 25#include <mach/hardware.h>
27#include <mach/imx-uart.h>
28#include <mach/iomux-mx51.h> 26#include <mach/iomux-mx51.h>
29 27
30#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index e6c1119c20ae..31c871ec46a6 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -27,7 +27,6 @@
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/leds.h> 28#include <linux/leds.h>
29#include <linux/platform_device.h> 29#include <linux/platform_device.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h> 30#include <linux/input.h>
32#include <linux/i2c.h> 31#include <linux/i2c.h>
33 32
@@ -38,7 +37,6 @@
38 37
39#include <mach/hardware.h> 38#include <mach/hardware.h>
40#include <mach/common.h> 39#include <mach/common.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx51.h> 40#include <mach/iomux-mx51.h>
43#include <mach/audmux.h> 41#include <mach/audmux.h>
44 42
@@ -108,23 +106,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
108 }, 106 },
109}; 107};
110 108
111static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { 109static const struct gpio_keys_platform_data
110 eukrea_mbimxsd_button_data __initconst = {
112 .buttons = eukrea_mbimxsd_gpio_buttons, 111 .buttons = eukrea_mbimxsd_gpio_buttons,
113 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), 112 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
114}; 113};
115 114
116static struct platform_device eukrea_mbimxsd_button_device = {
117 .name = "gpio-keys",
118 .id = -1,
119 .num_resources = 0,
120 .dev = {
121 .platform_data = &eukrea_mbimxsd_button_data,
122 }
123};
124
125static struct platform_device *platform_devices[] __initdata = { 115static struct platform_device *platform_devices[] __initdata = {
126 &eukrea_mbimxsd_leds_gpio, 116 &eukrea_mbimxsd_leds_gpio,
127 &eukrea_mbimxsd_button_device,
128}; 117};
129 118
130static const struct imxuart_platform_data uart_pdata __initconst = { 119static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -166,4 +155,5 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
166 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); 155 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
167 156
168 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 157 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
158 imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
169} 159}
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index d0c7075937cf..56739c23aca7 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -20,7 +20,6 @@
20#include <linux/input.h> 20#include <linux/input.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/fsl_devices.h>
24#include <linux/spi/flash.h> 23#include <linux/spi/flash.h>
25#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
26#include <linux/mfd/mc13892.h> 25#include <linux/mfd/mc13892.h>
@@ -30,8 +29,6 @@
30#include <mach/common.h> 29#include <mach/common.h>
31#include <mach/hardware.h> 30#include <mach/hardware.h>
32#include <mach/iomux-mx51.h> 31#include <mach/iomux-mx51.h>
33#include <mach/i2c.h>
34#include <mach/mxc_ehci.h>
35 32
36#include <linux/usb/otg.h> 33#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h> 34#include <linux/usb/ulpi.h>
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
deleted file mode 100644
index 8e5fa38ebb67..000000000000
--- a/arch/arm/mach-mxc91231/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
1if ARCH_MXC91231
2
3comment "MXC91231 platforms:"
4
5config MACH_MAGX_ZN5
6 bool "Support Motorola Zn5 GSM phone"
7 default n
8 help
9 Include support for Motorola Zn5 GSM phone.
10
11endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
deleted file mode 100644
index 011d5e197125..000000000000
--- a/arch/arm/mach-mxc91231/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-y := mm.o clock.o devices.o system.o iomux.o
2obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
deleted file mode 100644
index 9939a19d99a1..000000000000
--- a/arch/arm/mach-mxc91231/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x90008000
2params_phys-y := 0x90000100
3initrd_phys-y := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
deleted file mode 100644
index 9fab505f1eb1..000000000000
--- a/arch/arm/mach-mxc91231/clock.c
+++ /dev/null
@@ -1,640 +0,0 @@
1#include <linux/clk.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/io.h>
5#include <linux/clkdev.h>
6
7#include <mach/clock.h>
8#include <mach/hardware.h>
9#include <mach/common.h>
10
11#include <asm/bug.h>
12#include <asm/div64.h>
13
14#include "crm_regs.h"
15
16#define CRM_SMALL_DIVIDER(base, name) \
17 crm_small_divider(base, \
18 base ## _ ## name ## _OFFSET, \
19 base ## _ ## name ## _MASK)
20#define CRM_1DIVIDER(base, name) \
21 crm_divider(base, \
22 base ## _ ## name ## _OFFSET, \
23 base ## _ ## name ## _MASK, 1)
24#define CRM_16DIVIDER(base, name) \
25 crm_divider(base, \
26 base ## _ ## name ## _OFFSET, \
27 base ## _ ## name ## _MASK, 16)
28
29static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
30{
31 static const u32 crm_small_dividers[] = {
32 2, 3, 4, 5, 6, 8, 10, 12
33 };
34 u8 idx;
35
36 idx = (__raw_readl(reg) & mask) >> offset;
37 if (idx > 7)
38 return 1;
39
40 return crm_small_dividers[idx];
41}
42
43static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
44{
45 u32 div;
46 div = (__raw_readl(reg) & mask) >> offset;
47 return div ? div : z;
48}
49
50static int _clk_1bit_enable(struct clk *clk)
51{
52 u32 reg;
53
54 reg = __raw_readl(clk->enable_reg);
55 reg |= 1 << clk->enable_shift;
56 __raw_writel(reg, clk->enable_reg);
57
58 return 0;
59}
60
61static void _clk_1bit_disable(struct clk *clk)
62{
63 u32 reg;
64
65 reg = __raw_readl(clk->enable_reg);
66 reg &= ~(1 << clk->enable_shift);
67 __raw_writel(reg, clk->enable_reg);
68}
69
70static int _clk_3bit_enable(struct clk *clk)
71{
72 u32 reg;
73
74 reg = __raw_readl(clk->enable_reg);
75 reg |= 0x7 << clk->enable_shift;
76 __raw_writel(reg, clk->enable_reg);
77
78 return 0;
79}
80
81static void _clk_3bit_disable(struct clk *clk)
82{
83 u32 reg;
84
85 reg = __raw_readl(clk->enable_reg);
86 reg &= ~(0x7 << clk->enable_shift);
87 __raw_writel(reg, clk->enable_reg);
88}
89
90static unsigned long ckih_rate;
91
92static unsigned long clk_ckih_get_rate(struct clk *clk)
93{
94 return ckih_rate;
95}
96
97static struct clk ckih_clk = {
98 .get_rate = clk_ckih_get_rate,
99};
100
101static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
102{
103 return 2 * clk_get_rate(clk->parent);
104}
105
106static struct clk ckih_x2_clk = {
107 .parent = &ckih_clk,
108 .get_rate = clk_ckih_x2_get_rate,
109};
110
111static unsigned long clk_ckil_get_rate(struct clk *clk)
112{
113 return CKIL_CLK_FREQ;
114}
115
116static struct clk ckil_clk = {
117 .get_rate = clk_ckil_get_rate,
118};
119
120/* plls stuff */
121static struct clk mcu_pll_clk;
122static struct clk dsp_pll_clk;
123static struct clk usb_pll_clk;
124
125static struct clk *pll_clk(u8 sel)
126{
127 switch (sel) {
128 case 0:
129 return &mcu_pll_clk;
130 case 1:
131 return &dsp_pll_clk;
132 case 2:
133 return &usb_pll_clk;
134 }
135 BUG();
136}
137
138static void __iomem *pll_base(struct clk *clk)
139{
140 if (clk == &mcu_pll_clk)
141 return MXC_PLL0_BASE;
142 else if (clk == &dsp_pll_clk)
143 return MXC_PLL1_BASE;
144 else if (clk == &usb_pll_clk)
145 return MXC_PLL2_BASE;
146 BUG();
147}
148
149static unsigned long clk_pll_get_rate(struct clk *clk)
150{
151 const void __iomem *pllbase;
152 unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
153 long mfn, mfn_abs, mfd, pdf;
154 s64 temp;
155 pllbase = pll_base(clk);
156
157 pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
158 if (pll_hfsm == 0) {
159 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
160 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
161 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
162 } else {
163 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
164 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
165 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
166 }
167
168 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
169 mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
170 mfi = (mfi <= 5) ? 5 : mfi;
171 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
172 mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
173 mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
174
175 if (mfn < 0)
176 mfn_abs = -mfn;
177 else
178 mfn_abs = mfn;
179
180/* XXX: actually this asumes that ckih is fed to pll, but spec says
181 * that ckih_x2 is also possible. need to check this out.
182 */
183 ref_clk = clk_get_rate(&ckih_clk);
184
185 ref_clk *= 2;
186 ref_clk /= pdf + 1;
187
188 temp = (u64) ref_clk * mfn_abs;
189 do_div(temp, mfd);
190 if (mfn < 0)
191 temp = -temp;
192 temp += ref_clk * mfi;
193
194 return temp;
195}
196
197static int clk_pll_enable(struct clk *clk)
198{
199 void __iomem *ctl;
200 u32 reg;
201
202 ctl = pll_base(clk);
203 reg = __raw_readl(ctl);
204 reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
205 __raw_writel(reg, ctl);
206 do {
207 reg = __raw_readl(ctl);
208 } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
209 return 0;
210}
211
212static void clk_pll_disable(struct clk *clk)
213{
214 void __iomem *ctl;
215 u32 reg;
216
217 ctl = pll_base(clk);
218 reg = __raw_readl(ctl);
219 reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
220 __raw_writel(reg, ctl);
221}
222
223static struct clk mcu_pll_clk = {
224 .parent = &ckih_clk,
225 .get_rate = clk_pll_get_rate,
226 .enable = clk_pll_enable,
227 .disable = clk_pll_disable,
228};
229
230static struct clk dsp_pll_clk = {
231 .parent = &ckih_clk,
232 .get_rate = clk_pll_get_rate,
233 .enable = clk_pll_enable,
234 .disable = clk_pll_disable,
235};
236
237static struct clk usb_pll_clk = {
238 .parent = &ckih_clk,
239 .get_rate = clk_pll_get_rate,
240 .enable = clk_pll_enable,
241 .disable = clk_pll_disable,
242};
243/* plls stuff end */
244
245/* ap_ref_clk stuff */
246static struct clk ap_ref_clk;
247
248static unsigned long clk_ap_ref_get_rate(struct clk *clk)
249{
250 u32 ascsr, acsr;
251 u8 ap_pat_ref_div_2, ap_isel, acs, ads;
252
253 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
254 acsr = __raw_readl(MXC_CRMAP_ACSR);
255
256 /* 0 for ckih, 1 for ckih*2 */
257 ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
258 /* reg divider */
259 ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
260 /* undocumented, 1 for disabling divider */
261 ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
262 /* 0 for pat_ref, 1 for divider out */
263 acs = acsr & MXC_CRMAP_ACSR_ACS;
264
265 if (acs & !ads)
266 /* use divided clock */
267 return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
268
269 return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
270}
271
272static struct clk ap_ref_clk = {
273 .parent = &ckih_clk,
274 .get_rate = clk_ap_ref_get_rate,
275};
276/* ap_ref_clk stuff end */
277
278/* ap_pre_dfs_clk stuff */
279static struct clk ap_pre_dfs_clk;
280
281static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
282{
283 u32 acsr, ascsr;
284
285 acsr = __raw_readl(MXC_CRMAP_ACSR);
286 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
287
288 if (acsr & MXC_CRMAP_ACSR_ACS) {
289 u8 sel;
290 sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
291 MXC_CRMAP_ASCSR_APSEL_OFFSET;
292 return clk_get_rate(pll_clk(sel)) /
293 CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
294 }
295 return clk_get_rate(&ap_ref_clk);
296}
297
298static struct clk ap_pre_dfs_clk = {
299 .get_rate = clk_ap_pre_dfs_get_rate,
300};
301/* ap_pre_dfs_clk stuff end */
302
303/* usb_clk stuff */
304static struct clk usb_clk;
305
306static struct clk *clk_usb_parent(struct clk *clk)
307{
308 u32 acsr, ascsr;
309
310 acsr = __raw_readl(MXC_CRMAP_ACSR);
311 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
312
313 if (acsr & MXC_CRMAP_ACSR_ACS) {
314 u8 sel;
315 sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
316 MXC_CRMAP_ASCSR_USBSEL_OFFSET;
317 return pll_clk(sel);
318 }
319 return &ap_ref_clk;
320}
321
322static unsigned long clk_usb_get_rate(struct clk *clk)
323{
324 return clk_get_rate(clk->parent) /
325 CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
326}
327
328static struct clk usb_clk = {
329 .enable_reg = MXC_CRMAP_ACDER2,
330 .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
331 .get_rate = clk_usb_get_rate,
332 .enable = _clk_1bit_enable,
333 .disable = _clk_1bit_disable,
334};
335/* usb_clk stuff end */
336
337static unsigned long clk_ipg_get_rate(struct clk *clk)
338{
339 return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
340}
341
342static unsigned long clk_ahb_get_rate(struct clk *clk)
343{
344 return clk_get_rate(clk->parent) /
345 CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
346}
347
348static struct clk ipg_clk = {
349 .parent = &ap_pre_dfs_clk,
350 .get_rate = clk_ipg_get_rate,
351};
352
353static struct clk ahb_clk = {
354 .parent = &ap_pre_dfs_clk,
355 .get_rate = clk_ahb_get_rate,
356};
357
358/* perclk_clk stuff */
359static struct clk perclk_clk;
360
361static unsigned long clk_perclk_get_rate(struct clk *clk)
362{
363 u32 acder2;
364
365 acder2 = __raw_readl(MXC_CRMAP_ACDER2);
366 if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
367 return 2 * clk_get_rate(clk->parent);
368
369 return clk_get_rate(clk->parent);
370}
371
372static struct clk perclk_clk = {
373 .parent = &ckih_clk,
374 .get_rate = clk_perclk_get_rate,
375};
376/* perclk_clk stuff end */
377
378/* uart_clk stuff */
379static struct clk uart_clk[];
380
381static unsigned long clk_uart_get_rate(struct clk *clk)
382{
383 u32 div;
384
385 switch (clk->id) {
386 case 0:
387 case 1:
388 div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
389 break;
390 case 2:
391 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
392 break;
393 default:
394 BUG();
395 }
396 return clk_get_rate(clk->parent) / div;
397}
398
399static struct clk uart_clk[] = {
400 {
401 .id = 0,
402 .parent = &perclk_clk,
403 .enable_reg = MXC_CRMAP_APRA,
404 .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
405 .get_rate = clk_uart_get_rate,
406 .enable = _clk_1bit_enable,
407 .disable = _clk_1bit_disable,
408 }, {
409 .id = 1,
410 .parent = &perclk_clk,
411 .enable_reg = MXC_CRMAP_APRA,
412 .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
413 .get_rate = clk_uart_get_rate,
414 .enable = _clk_1bit_enable,
415 .disable = _clk_1bit_disable,
416 }, {
417 .id = 2,
418 .parent = &perclk_clk,
419 .enable_reg = MXC_CRMAP_APRA,
420 .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
421 .get_rate = clk_uart_get_rate,
422 .enable = _clk_1bit_enable,
423 .disable = _clk_1bit_disable,
424 },
425};
426/* uart_clk stuff end */
427
428/* sdhc_clk stuff */
429static struct clk nfc_clk;
430
431static unsigned long clk_nfc_get_rate(struct clk *clk)
432{
433 return clk_get_rate(clk->parent) /
434 CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
435}
436
437static struct clk nfc_clk = {
438 .parent = &ahb_clk,
439 .enable_reg = MXC_CRMAP_ACDER2,
440 .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
441 .get_rate = clk_nfc_get_rate,
442 .enable = _clk_1bit_enable,
443 .disable = _clk_1bit_disable,
444};
445/* sdhc_clk stuff end */
446
447/* sdhc_clk stuff */
448static struct clk sdhc_clk[];
449
450static struct clk *clk_sdhc_parent(struct clk *clk)
451{
452 u32 aprb;
453 u8 sel;
454 u32 mask;
455 int offset;
456
457 aprb = __raw_readl(MXC_CRMAP_APRB);
458
459 switch (clk->id) {
460 case 0:
461 mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
462 offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
463 break;
464 case 1:
465 mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
466 offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
467 break;
468 default:
469 BUG();
470 }
471 sel = (aprb & mask) >> offset;
472
473 switch (sel) {
474 case 0:
475 return &ckih_clk;
476 case 1:
477 return &ckih_x2_clk;
478 }
479 return &usb_clk;
480}
481
482static unsigned long clk_sdhc_get_rate(struct clk *clk)
483{
484 u32 div;
485
486 switch (clk->id) {
487 case 0:
488 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
489 break;
490 case 1:
491 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
492 break;
493 default:
494 BUG();
495 }
496
497 return clk_get_rate(clk->parent) / div;
498}
499
500static int clk_sdhc_enable(struct clk *clk)
501{
502 u32 amlpmre1, aprb;
503
504 amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
505 aprb = __raw_readl(MXC_CRMAP_APRB);
506 switch (clk->id) {
507 case 0:
508 amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
509 aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
510 break;
511 case 1:
512 amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
513 aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
514 break;
515 }
516 __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
517 __raw_writel(aprb, MXC_CRMAP_APRB);
518 return 0;
519}
520
521static void clk_sdhc_disable(struct clk *clk)
522{
523 u32 amlpmre1, aprb;
524
525 amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
526 aprb = __raw_readl(MXC_CRMAP_APRB);
527 switch (clk->id) {
528 case 0:
529 amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
530 aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
531 break;
532 case 1:
533 amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
534 aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
535 break;
536 }
537 __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
538 __raw_writel(aprb, MXC_CRMAP_APRB);
539}
540
541static struct clk sdhc_clk[] = {
542 {
543 .id = 0,
544 .get_rate = clk_sdhc_get_rate,
545 .enable = clk_sdhc_enable,
546 .disable = clk_sdhc_disable,
547 }, {
548 .id = 1,
549 .get_rate = clk_sdhc_get_rate,
550 .enable = clk_sdhc_enable,
551 .disable = clk_sdhc_disable,
552 },
553};
554/* sdhc_clk stuff end */
555
556/* wdog_clk stuff */
557static struct clk wdog_clk[] = {
558 {
559 .id = 0,
560 .parent = &ipg_clk,
561 .enable_reg = MXC_CRMAP_AMLPMRD,
562 .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
563 .enable = _clk_3bit_enable,
564 .disable = _clk_3bit_disable,
565 }, {
566 .id = 1,
567 .parent = &ipg_clk,
568 .enable_reg = MXC_CRMAP_AMLPMRD,
569 .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
570 .enable = _clk_3bit_enable,
571 .disable = _clk_3bit_disable,
572 },
573};
574/* wdog_clk stuff end */
575
576/* gpt_clk stuff */
577static struct clk gpt_clk = {
578 .parent = &ipg_clk,
579 .enable_reg = MXC_CRMAP_AMLPMRC,
580 .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
581 .enable = _clk_3bit_enable,
582 .disable = _clk_3bit_disable,
583};
584/* gpt_clk stuff end */
585
586/* cspi_clk stuff */
587static struct clk cspi_clk[] = {
588 {
589 .id = 0,
590 .parent = &ipg_clk,
591 .enable_reg = MXC_CRMAP_AMLPMRE2,
592 .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
593 .enable = _clk_3bit_enable,
594 .disable = _clk_3bit_disable,
595 }, {
596 .id = 1,
597 .parent = &ipg_clk,
598 .enable_reg = MXC_CRMAP_AMLPMRE1,
599 .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
600 .enable = _clk_3bit_enable,
601 .disable = _clk_3bit_disable,
602 },
603};
604/* cspi_clk stuff end */
605
606#define _REGISTER_CLOCK(d, n, c) \
607 { \
608 .dev_id = d, \
609 .con_id = n, \
610 .clk = &c, \
611 },
612
613static struct clk_lookup lookups[] = {
614 _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
615 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
616 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
617 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
618 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
619 _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
620 _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
621 _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
622};
623
624int __init mxc91231_clocks_init(unsigned long fref)
625{
626 void __iomem *gpt_base;
627
628 ckih_rate = fref;
629
630 usb_clk.parent = clk_usb_parent(&usb_clk);
631 sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
632 sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
633
634 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
635
636 gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
637 mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
638
639 return 0;
640}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
deleted file mode 100644
index b989baccd675..000000000000
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ /dev/null
@@ -1,394 +0,0 @@
1/*
2 * Copyright 2006 Freescale Semiconductor, Inc.
3 * Copyright 2006-2007 Motorola, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
17#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
18
19#define CKIL_CLK_FREQ 32768
20
21#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
22#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
23#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
24#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
25#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
26#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
27#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
28
29/* PLL Register Offsets */
30#define MXC_PLL_DP_CTL 0x00
31#define MXC_PLL_DP_CONFIG 0x04
32#define MXC_PLL_DP_OP 0x08
33#define MXC_PLL_DP_MFD 0x0C
34#define MXC_PLL_DP_MFN 0x10
35#define MXC_PLL_DP_HFS_OP 0x1C
36#define MXC_PLL_DP_HFS_MFD 0x20
37#define MXC_PLL_DP_HFS_MFN 0x24
38
39/* PLL Register Bit definitions */
40#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
41#define MXC_PLL_DP_CTL_ADE 0x800
42#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
43#define MXC_PLL_DP_CTL_HFSM 0x80
44#define MXC_PLL_DP_CTL_PRE 0x40
45#define MXC_PLL_DP_CTL_UPEN 0x20
46#define MXC_PLL_DP_CTL_RST 0x10
47#define MXC_PLL_DP_CTL_RCP 0x8
48#define MXC_PLL_DP_CTL_PLM 0x4
49#define MXC_PLL_DP_CTL_BRM0 0x2
50#define MXC_PLL_DP_CTL_LRF 0x1
51
52#define MXC_PLL_DP_OP_MFI_OFFSET 4
53#define MXC_PLL_DP_OP_MFI_MASK 0xF
54#define MXC_PLL_DP_OP_PDF_OFFSET 0
55#define MXC_PLL_DP_OP_PDF_MASK 0xF
56
57#define MXC_PLL_DP_MFD_OFFSET 0
58#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF
59
60#define MXC_PLL_DP_MFN_OFFSET 0
61#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF
62
63/* CRM AP Register Offsets */
64#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00)
65#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04)
66#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08)
67#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C)
68#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10)
69#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14)
70#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18)
71#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C)
72#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20)
73#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24)
74#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28)
75#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C)
76#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30)
77#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34)
78#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38)
79#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C)
80#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40)
81#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44)
82#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48)
83#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C)
84#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50)
85#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54)
86#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58)
87#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C)
88#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60)
89#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64)
90#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68)
91
92/* CRM AP Register Bit definitions */
93#define MXC_CRMAP_ASCSR_CRS 0x10000
94#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15
95#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000
96#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13
97#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13)
98#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11
99#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11)
100#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7
101#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7)
102#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5
103#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5)
104#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3
105#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3)
106#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2
107#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4
108#define MXC_CRMAP_ASCSR_APISEL 0x1
109
110#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8
111#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8)
112#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4
113#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4)
114#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0
115#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF
116
117#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30
118#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24
119#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24)
120#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14
121#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8
122#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8)
123#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6
124#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0
125#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F
126
127#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24
128#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24)
129#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20
130#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16
131#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16)
132#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12
133#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8
134#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8)
135#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5
136#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5)
137#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0
138#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF
139
140#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22
141#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22)
142#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19
143#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19)
144#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12
145#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12)
146#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9
147#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9)
148#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6
149#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6)
150#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3
151#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3)
152
153#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0
154#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7
155
156#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28
157#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28)
158#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22
159#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22)
160#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16
161#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16)
162#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12
163#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12)
164#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9
165#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9)
166#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6
167#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6)
168#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3
169#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3)
170#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0
171#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7
172
173#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22
174#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22)
175#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12
176#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12)
177#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9
178#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9)
179#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6
180#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6)
181#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0
182#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7
183
184#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28
185#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28)
186#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25
187#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25)
188#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22
189#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22)
190#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19
191#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19)
192#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16
193#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16)
194#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12
195#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12)
196#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9
197#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9)
198#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6
199#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6)
200#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3
201#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3)
202#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0
203#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7
204
205#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0
206#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7
207
208#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19
209#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19)
210#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16
211#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16)
212#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9
213#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9)
214#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6
215#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6)
216#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3
217#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3)
218#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0
219#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0)
220
221#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28
222#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28)
223#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22
224#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22)
225#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19
226#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19)
227#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16
228#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16)
229#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12
230#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12)
231#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9
232#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9)
233#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6
234#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6)
235#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3
236#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3)
237#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0
238#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7
239
240#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20
241#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20)
242
243#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29
244#define MXC_CRMAP_APRA_SIMEN_OFFSET 24
245#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17
246#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17)
247#define MXC_CRMAP_APRA_UART3EN_OFFSET 16
248#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
249#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13
250#define MXC_CRMAP_APRA_UART2EN_OFFSET 8
251#define MXC_CRMAP_APRA_UART1EN_OFFSET 0
252
253#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13
254#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13)
255#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9
256#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9)
257#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8
258#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5
259#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5)
260#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1
261#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1)
262#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0
263
264#define MXC_CRMAP_ACSR_ADS_OFFSET 8
265#define MXC_CRMAP_ACSR_ADS (0x1 << 8)
266#define MXC_CRMAP_ACSR_ACS 0x1
267
268#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8)
269#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8)
270#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8)
271#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8)
272#define MXC_CRMAP_ADCR_LFDF_OFFSET 8
273#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8)
274#define MXC_CRMAP_ADCR_ALT_PLL 0x80
275#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20
276#define MXC_CRMAP_ADCR_DIV_BYP 0x2
277#define MXC_CRMAP_ADCR_VSTAT 0x8
278#define MXC_CRMAP_ADCR_TSTAT 0x10
279#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10
280#define MXC_CRMAP_ADCR_CLK_ON 0x40
281
282#define MXC_CRMAP_ADFMR_FC_OFFSET 16
283#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16)
284#define MXC_CRMAP_ADFMR_MF_OFFSET 1
285#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1)
286#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1
287#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000
288
289#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18)
290#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16)
291#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12)
292#define MXC_CRMAP_ACR_CKOHD (1 << 11)
293#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8)
294#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8
295#define MXC_CRMAP_ACR_CKOD (1 << 7)
296#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4)
297
298/* AP Warm reset */
299#define MXC_CRMAP_AMCR_SW_AP (1 << 14)
300
301/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
302#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001
303#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003
304#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007
305#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000
306
307#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008
308#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018
309#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038
310#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000
311
312#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040
313#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0
314#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0
315#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000
316
317#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200
318#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600
319#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00
320#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000
321
322#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000
323#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000
324#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000
325#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000
326
327#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000
328#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000
329#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000
330#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000
331
332#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000
333#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000
334#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000
335#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000
336
337#define NUM_GATE_CTRL 6
338
339/* CRM COM Register Offsets */
340#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C)
341#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10)
342
343/* CRM COM Bit Definitions */
344#define MXC_CRMCOM_CSCR_PPD1 0x08000000
345#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18)
346#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17)
347#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8
348#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8)
349#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0
350#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3
351
352/* DSM Register Offsets */
353#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c)
354#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20)
355#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24)
356#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28)
357#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40)
358#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44)
359#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c)
360#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50)
361
362/* Bit definitions of various registers in DSM */
363#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008
364#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004
365#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002
366#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001
367#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000
368#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001
369#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003
370#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200
371#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001
372#define MXC_DSM_CONTROL0_RESTART 0x00000010
373/* Counter Block reset */
374#define MXC_DSM_CONTROL1_CB_RST 0x00000002
375/* State Machine reset */
376#define MXC_DSM_CONTROL1_SM_RST 0x00000004
377/* Bit needed to reset counter block */
378#define MXC_CONTROL1_RST_CNT32 0x00000008
379#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800
380#define MXC_DSM_CONTROL1_SLEEP 0x00000100
381#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000
382#define MXC_DSM_CTREN_CNT32 0x00000001
383
384/* Magic Fix enable bit */
385#define MXC_DSM_MGPER_EN_MGFX 0x80000000
386#define MXC_DSM_MGPER_PER_MASK 0x000003FF
387#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n)
388
389/* Address offsets of the CLKCTL registers */
390#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00)
391#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04)
392#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08)
393
394#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
deleted file mode 100644
index 027af4f0d18a..000000000000
--- a/arch/arm/mach-mxc91231/devices.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/gpio.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <mach/imx-uart.h>
27
28static struct resource uart0[] = {
29 {
30 .start = MXC91231_UART1_BASE_ADDR,
31 .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = MXC91231_INT_UART1_RX,
35 .end = MXC91231_INT_UART1_RX,
36 .flags = IORESOURCE_IRQ,
37 }, {
38 .start = MXC91231_INT_UART1_TX,
39 .end = MXC91231_INT_UART1_TX,
40 .flags = IORESOURCE_IRQ,
41 }, {
42 .start = MXC91231_INT_UART1_MINT,
43 .end = MXC91231_INT_UART1_MINT,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48struct platform_device mxc_uart_device0 = {
49 .name = "imx-uart",
50 .id = 0,
51 .resource = uart0,
52 .num_resources = ARRAY_SIZE(uart0),
53};
54
55static struct resource uart1[] = {
56 {
57 .start = MXC91231_UART2_BASE_ADDR,
58 .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
59 .flags = IORESOURCE_MEM,
60 }, {
61 .start = MXC91231_INT_UART2_RX,
62 .end = MXC91231_INT_UART2_RX,
63 .flags = IORESOURCE_IRQ,
64 }, {
65 .start = MXC91231_INT_UART2_TX,
66 .end = MXC91231_INT_UART2_TX,
67 .flags = IORESOURCE_IRQ,
68 }, {
69 .start = MXC91231_INT_UART2_MINT,
70 .end = MXC91231_INT_UART2_MINT,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75struct platform_device mxc_uart_device1 = {
76 .name = "imx-uart",
77 .id = 1,
78 .resource = uart1,
79 .num_resources = ARRAY_SIZE(uart1),
80};
81
82static struct resource uart2[] = {
83 {
84 .start = MXC91231_UART3_BASE_ADDR,
85 .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
86 .flags = IORESOURCE_MEM,
87 }, {
88 .start = MXC91231_INT_UART3_RX,
89 .end = MXC91231_INT_UART3_RX,
90 .flags = IORESOURCE_IRQ,
91 }, {
92 .start = MXC91231_INT_UART3_TX,
93 .end = MXC91231_INT_UART3_TX,
94 .flags = IORESOURCE_IRQ,
95 }, {
96 .start = MXC91231_INT_UART3_MINT,
97 .end = MXC91231_INT_UART3_MINT,
98 .flags = IORESOURCE_IRQ,
99
100 },
101};
102
103struct platform_device mxc_uart_device2 = {
104 .name = "imx-uart",
105 .id = 2,
106 .resource = uart2,
107 .num_resources = ARRAY_SIZE(uart2),
108};
109
110/* GPIO port description */
111static struct mxc_gpio_port mxc_gpio_ports[] = {
112 [0] = {
113 .chip.label = "gpio-0",
114 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
115 .irq = MXC91231_INT_GPIO1,
116 .virtual_irq_start = MXC_GPIO_IRQ_START,
117 },
118 [1] = {
119 .chip.label = "gpio-1",
120 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
121 .irq = MXC91231_INT_GPIO2,
122 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
123 },
124 [2] = {
125 .chip.label = "gpio-2",
126 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
127 .irq = MXC91231_INT_GPIO3,
128 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
129 },
130 [3] = {
131 .chip.label = "gpio-3",
132 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
133 .irq = MXC91231_INT_GPIO4,
134 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
135 },
136};
137
138int __init mxc91231_register_gpios(void)
139{
140 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
141}
142
143static struct resource mxc_nand_resources[] = {
144 {
145 .start = MXC91231_NFC_BASE_ADDR,
146 .end = MXC91231_NFC_BASE_ADDR + 0xfff,
147 .flags = IORESOURCE_MEM
148 }, {
149 .start = MXC91231_INT_NANDFC,
150 .end = MXC91231_INT_NANDFC,
151 .flags = IORESOURCE_IRQ
152 },
153};
154
155struct platform_device mxc_nand_device = {
156 .name = "mxc_nand",
157 .id = 0,
158 .num_resources = ARRAY_SIZE(mxc_nand_resources),
159 .resource = mxc_nand_resources,
160};
161
162static struct resource mxc_sdhc0_resources[] = {
163 {
164 .start = MXC91231_MMC_SDHC1_BASE_ADDR,
165 .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .start = MXC91231_INT_MMC_SDHC1,
169 .end = MXC91231_INT_MMC_SDHC1,
170 .flags = IORESOURCE_IRQ,
171 },
172};
173
174static struct resource mxc_sdhc1_resources[] = {
175 {
176 .start = MXC91231_MMC_SDHC2_BASE_ADDR,
177 .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
178 .flags = IORESOURCE_MEM,
179 }, {
180 .start = MXC91231_INT_MMC_SDHC2,
181 .end = MXC91231_INT_MMC_SDHC2,
182 .flags = IORESOURCE_IRQ,
183 },
184};
185
186struct platform_device mxc_sdhc_device0 = {
187 .name = "mxc-mmc",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
190 .resource = mxc_sdhc0_resources,
191};
192
193struct platform_device mxc_sdhc_device1 = {
194 .name = "mxc-mmc",
195 .id = 1,
196 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
197 .resource = mxc_sdhc1_resources,
198};
199
200static struct resource mxc_cspi0_resources[] = {
201 {
202 .start = MXC91231_CSPI1_BASE_ADDR,
203 .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
204 .flags = IORESOURCE_MEM,
205 }, {
206 .start = MXC91231_INT_CSPI1,
207 .end = MXC91231_INT_CSPI1,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212struct platform_device mxc_cspi_device0 = {
213 .name = "spi_imx",
214 .id = 0,
215 .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
216 .resource = mxc_cspi0_resources,
217};
218
219static struct resource mxc_cspi1_resources[] = {
220 {
221 .start = MXC91231_CSPI2_BASE_ADDR,
222 .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
223 .flags = IORESOURCE_MEM,
224 }, {
225 .start = MXC91231_INT_CSPI2,
226 .end = MXC91231_INT_CSPI2,
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231struct platform_device mxc_cspi_device1 = {
232 .name = "spi_imx",
233 .id = 1,
234 .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
235 .resource = mxc_cspi1_resources,
236};
237
238static struct resource mxc_wdog0_resources[] = {
239 {
240 .start = MXC91231_WDOG1_BASE_ADDR,
241 .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
242 .flags = IORESOURCE_MEM,
243 },
244};
245
246struct platform_device mxc_wdog_device0 = {
247 .name = "mxc-wdt",
248 .id = 0,
249 .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
250 .resource = mxc_wdog0_resources,
251};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
deleted file mode 100644
index 72a2136ce27d..000000000000
--- a/arch/arm/mach-mxc91231/devices.h
+++ /dev/null
@@ -1,13 +0,0 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4
5extern struct platform_device mxc_nand_device;
6
7extern struct platform_device mxc_sdhc_device0;
8extern struct platform_device mxc_sdhc_device1;
9
10extern struct platform_device mxc_cspi_device0;
11extern struct platform_device mxc_cspi_device1;
12
13extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
deleted file mode 100644
index 66fc41cbf2ca..000000000000
--- a/arch/arm/mach-mxc91231/iomux.c
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/iomux-mxc91231.h>
28
29/*
30 * IOMUX register (base) addresses
31 */
32#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
33#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
34#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000)
35#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000)
36#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200)
37
38#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600)
39#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004)
40
41static DEFINE_SPINLOCK(gpio_mux_lock);
42
43#define NB_PORTS ((PIN_MAX + 32) / 32)
44#define PIN_GLOBAL_NUM(pin) \
45 (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
46 ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \
47 ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
48
49unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
50/*
51 * set the mode for a IOMUX pin.
52 */
53int mxc_iomux_mode(unsigned int pin_mode)
54{
55 u32 side, field, l, mode, ret = 0;
56 void __iomem *reg;
57
58 side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
59 switch (side) {
60 case MUX_SIDE_AP:
61 reg = IOMUXSW_AP_MUX_CTL;
62 break;
63 case MUX_SIDE_SP:
64 reg = IOMUXSW_SP_MUX_CTL;
65 break;
66 default:
67 return -EINVAL;
68 }
69 reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
70 field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
71 mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
72
73 spin_lock(&gpio_mux_lock);
74
75 l = __raw_readl(reg);
76 l &= ~(0xff << (field * 8));
77 l |= mode << (field * 8);
78 __raw_writel(l, reg);
79
80 spin_unlock(&gpio_mux_lock);
81
82 return ret;
83}
84EXPORT_SYMBOL(mxc_iomux_mode);
85
86/*
87 * This function configures the pad value for a IOMUX pin.
88 */
89void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
90{
91 u32 padgrp, field, l;
92 void __iomem *reg;
93
94 padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
95 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
96 field = (pin + 2) % 3;
97
98 pr_debug("%s: reg offset = 0x%x, field = %d\n",
99 __func__, (pin + 2) / 3, field);
100
101 spin_lock(&gpio_mux_lock);
102
103 l = __raw_readl(reg);
104 l &= ~(0x1ff << (field * 10));
105 l |= config << (field * 10);
106 __raw_writel(l, reg);
107
108 spin_unlock(&gpio_mux_lock);
109}
110EXPORT_SYMBOL(mxc_iomux_set_pad);
111
112/*
113 * allocs a single pin:
114 * - reserves the pin so that it is not claimed by another driver
115 * - setups the iomux according to the configuration
116 */
117int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
118{
119 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
120 if (pad >= (PIN_MAX + 1)) {
121 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
122 pad, label ? label : "?");
123 return -EINVAL;
124 }
125
126 if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
127 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
128 pad, label ? label : "?");
129 return -EBUSY;
130 }
131 mxc_iomux_mode(pin_mode);
132
133 return 0;
134}
135EXPORT_SYMBOL(mxc_iomux_alloc_pin);
136
137int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
138 const char *label)
139{
140 const unsigned int *p = pin_list;
141 int i;
142 int ret = -EINVAL;
143
144 for (i = 0; i < count; i++) {
145 ret = mxc_iomux_alloc_pin(*p, label);
146 if (ret)
147 goto setup_error;
148 p++;
149 }
150 return 0;
151
152setup_error:
153 mxc_iomux_release_multiple_pins(pin_list, i);
154 return ret;
155}
156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
157
158void mxc_iomux_release_pin(unsigned int pin_mode)
159{
160 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
161
162 if (pad < (PIN_MAX + 1))
163 clear_bit(pad, mxc_pin_alloc_map);
164}
165EXPORT_SYMBOL(mxc_iomux_release_pin);
166
167void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
168{
169 const unsigned int *p = pin_list;
170 int i;
171
172 for (i = 0; i < count; i++) {
173 mxc_iomux_release_pin(*p);
174 p++;
175 }
176}
177EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
deleted file mode 100644
index f31a45e5a0b8..000000000000
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
3 *
4 * This file is released under the GPLv2 or later.
5 */
6
7#include <linux/irq.h>
8#include <linux/init.h>
9#include <linux/device.h>
10
11#include <asm/mach-types.h>
12#include <asm/mach/time.h>
13#include <asm/mach/arch.h>
14
15#include <mach/common.h>
16#include <mach/hardware.h>
17#include <mach/iomux-mxc91231.h>
18#include <mach/mmc.h>
19#include <mach/imx-uart.h>
20
21#include "devices.h"
22
23static struct imxuart_platform_data uart_pdata = {
24};
25
26static struct imxmmc_platform_data sdhc_pdata = {
27};
28
29static void __init zn5_init(void)
30{
31 pm_power_off = mxc91231_power_off;
32
33 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
34 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
35
36 mxc_register_device(&mxc_uart_device1, &uart_pdata);
37 mxc_register_device(&mxc_uart_device0, &uart_pdata);
38
39 mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
40
41 mxc_register_device(&mxc_wdog_device0, NULL);
42
43 return;
44}
45
46static void __init zn5_timer_init(void)
47{
48 mxc91231_clocks_init(26000000); /* 26mhz ckih */
49}
50
51struct sys_timer zn5_timer = {
52 .init = zn5_timer_init,
53};
54
55MACHINE_START(MAGX_ZN5, "Motorola Zn5")
56 .boot_params = MXC91231_PHYS_OFFSET + 0x100,
57 .map_io = mxc91231_map_io,
58 .init_early = mxc91231_init_early,
59 .init_irq = mxc91231_init_irq,
60 .timer = &zn5_timer,
61 .init_machine = zn5_init,
62MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
deleted file mode 100644
index a77f6daf6a26..000000000000
--- a/arch/arm/mach-mxc91231/mm.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MXC specific definitions
7 * Copyright 2006 Motorola, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/mm.h>
21#include <linux/init.h>
22#include <mach/hardware.h>
23#include <mach/common.h>
24#include <asm/pgtable.h>
25#include <asm/mach/map.h>
26
27/*
28 * This structure defines the MXC memory map.
29 */
30static struct map_desc mxc91231_io_desc[] __initdata = {
31 imx_map_entry(MXC91231, L2CC, MT_DEVICE),
32 imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
33 imx_map_entry(MXC91231, ROMP, MT_DEVICE),
34 imx_map_entry(MXC91231, AVIC, MT_DEVICE),
35 imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
36 imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
37 imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
38 imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
39};
40
41/*
42 * This function initializes the memory map. It is called during the
43 * system startup to create static physical to virtual memory map for
44 * the IO modules.
45 */
46void __init mxc91231_map_io(void)
47{
48 iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
49}
50
51void __init mxc91231_init_early(void)
52{
53 mxc_set_cpu_type(MXC_CPU_MXC91231);
54}
55
56int mxc91231_register_gpios(void);
57
58void __init mxc91231_init_irq(void)
59{
60 mxc91231_register_gpios();
61 mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
62}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
deleted file mode 100644
index 736f7efd874a..000000000000
--- a/arch/arm/mach-mxc91231/system.c
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
3 *
4 * This file is released under the GPLv2 or later.
5 */
6
7#include <linux/delay.h>
8#include <linux/io.h>
9
10#include <asm/proc-fns.h>
11#include <mach/hardware.h>
12
13#include "crm_regs.h"
14
15#define WDOG_WCR MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
16#define WDOG_WCR_OUT_ENABLE (1 << 6)
17#define WDOG_WCR_ASSERT (1 << 5)
18
19void mxc91231_power_off(void)
20{
21 u16 wcr;
22
23 wcr = __raw_readw(WDOG_WCR);
24 wcr |= WDOG_WCR_OUT_ENABLE;
25 wcr &= ~WDOG_WCR_ASSERT;
26 __raw_writew(wcr, WDOG_WCR);
27}
28
29void mxc91231_arch_reset(char mode, const char *cmd)
30{
31 u32 amcr;
32
33 /* Reset the AP using CRM */
34 amcr = __raw_readl(MXC_CRMAP_AMCR);
35 amcr &= ~MXC_CRMAP_AMCR_SW_AP;
36 __raw_writel(amcr, MXC_CRMAP_AMCR);
37
38 mdelay(10);
39 cpu_reset(0);
40}
41
42void mxc91231_prepare_idle(void)
43{
44 u32 crm_ctl;
45
46 /* Go to WAIT mode after WFI */
47 crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
48 crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
49 crm_ctl |= MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
50 __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
51}
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4522fbb235d5..f114960622e0 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -17,6 +17,16 @@ config SOC_IMX28
17 17
18comment "MXS platforms:" 18comment "MXS platforms:"
19 19
20config MACH_STMP378X_DEVB
21 bool "Support STMP378x_devb Platform"
22 select SOC_IMX23
23 select MXS_HAVE_AMBA_DUART
24 select MXS_HAVE_PLATFORM_AUART
25 select MXS_HAVE_PLATFORM_MXS_MMC
26 help
27 Include support for STMP378x-devb platform. This includes specific
28 configurations for the board and its peripherals.
29
20config MACH_MX23EVK 30config MACH_MX23EVK
21 bool "Support MX23EVK Platform" 31 bool "Support MX23EVK Platform"
22 select SOC_IMX23 32 select SOC_IMX23
@@ -24,7 +34,6 @@ config MACH_MX23EVK
24 select MXS_HAVE_PLATFORM_AUART 34 select MXS_HAVE_PLATFORM_AUART
25 select MXS_HAVE_PLATFORM_MXS_MMC 35 select MXS_HAVE_PLATFORM_MXS_MMC
26 select MXS_HAVE_PLATFORM_MXSFB 36 select MXS_HAVE_PLATFORM_MXSFB
27 default y
28 help 37 help
29 Include support for MX23EVK platform. This includes specific 38 Include support for MX23EVK platform. This includes specific
30 configurations for the board and its peripherals. 39 configurations for the board and its peripherals.
@@ -39,7 +48,6 @@ config MACH_MX28EVK
39 select MXS_HAVE_PLATFORM_MXS_MMC 48 select MXS_HAVE_PLATFORM_MXS_MMC
40 select MXS_HAVE_PLATFORM_MXSFB 49 select MXS_HAVE_PLATFORM_MXSFB
41 select MXS_OCOTP 50 select MXS_OCOTP
42 default y
43 help 51 help
44 Include support for MX28EVK platform. This includes specific 52 Include support for MX28EVK platform. This includes specific
45 configurations for the board and its peripherals. 53 configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 2f1f6141ca71..58e892376bf2 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o 7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o 8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
9 9
10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
10obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
11obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 12obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
12obj-$(CONFIG_MODULE_TX28) += module-tx28.o 13obj-$(CONFIG_MODULE_TX28) += module-tx28.o
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index c3577ea789ac..0163b6d83773 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -446,6 +446,8 @@ static struct clk_lookup lookups[] = {
446 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 446 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
447 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) 447 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
448 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) 448 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
449 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
450 _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
449 _REGISTER_CLOCK(NULL, "usb", usb_clk) 451 _REGISTER_CLOCK(NULL, "usb", usb_clk)
450 _REGISTER_CLOCK(NULL, "audio", audio_clk) 452 _REGISTER_CLOCK(NULL, "audio", audio_clk)
451 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk) 453 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index c473eddce8cf..79b94523954a 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -34,7 +34,7 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
34#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) 34#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata)
35#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) 35#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata)
36 36
37extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; 37extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
38#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) 38#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
39 39
40extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; 40extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
index eab3a06836d6..79222ec8ede1 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -22,13 +22,14 @@
22 [_id] = mxs_i2c_data_entry_single(soc, _id) 22 [_id] = mxs_i2c_data_entry_single(soc, _id)
23 23
24#ifdef CONFIG_SOC_IMX28 24#ifdef CONFIG_SOC_IMX28
25const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { 25const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
26 mxs_i2c_data_entry(MX28, 0), 26 mxs_i2c_data_entry(MX28, 0),
27 mxs_i2c_data_entry(MX28, 1), 27 mxs_i2c_data_entry(MX28, 1),
28}; 28};
29#endif 29#endif
30 30
31struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data) 31struct platform_device *__init mxs_add_mxs_i2c(
32 const struct mxs_mxs_i2c_data *data)
32{ 33{
33 struct resource res[] = { 34 struct resource res[] = {
34 { 35 {
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index c5137f14c364..7a37469ed5bf 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -65,13 +65,14 @@ struct platform_device *__init mxs_add_flexcan(
65 const struct flexcan_platform_data *pdata); 65 const struct flexcan_platform_data *pdata);
66 66
67/* i2c */ 67/* i2c */
68struct mxs_i2c_data { 68struct mxs_mxs_i2c_data {
69 int id; 69 int id;
70 resource_size_t iobase; 70 resource_size_t iobase;
71 resource_size_t errirq; 71 resource_size_t errirq;
72 resource_size_t dmairq; 72 resource_size_t dmairq;
73}; 73};
74struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data); 74struct platform_device * __init mxs_add_mxs_i2c(
75 const struct mxs_mxs_i2c_data *data);
75 76
76/* mmc */ 77/* mmc */
77#include <mach/mmc.h> 78#include <mach/mmc.h>
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index c0a18c23084a..599094bc99de 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -57,7 +57,7 @@
57#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) 57#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
58#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000) 58#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
59#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) 59#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
60#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) 60#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
61#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) 61#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
62#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) 62#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
63#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) 63#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index f12a1732d8b8..7f8bf6539646 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -20,7 +20,7 @@
20 20
21#include <asm/mach-types.h> 21#include <asm/mach-types.h>
22 22
23static unsigned long mxs_duart_base; 23unsigned long mxs_duart_base;
24 24
25#define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x))) 25#define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x)))
26 26
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 214e5b641bbc..3c2de33803ab 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -148,7 +148,7 @@ static void __init mx23evk_init(void)
148 mx23_add_auart0(); 148 mx23_add_auart0();
149 149
150 /* power on mmc slot by writing 0 to the gpio */ 150 /* power on mmc slot by writing 0 to the gpio */
151 ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT, 151 ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
152 "mmc0-slot-power"); 152 "mmc0-slot-power");
153 if (ret) 153 if (ret)
154 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); 154 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index bb329b9a2608..eacdc6b0e70a 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -375,13 +375,13 @@ static void __init mx28evk_init(void)
375 mx28_add_mxsfb(&mx28evk_mxsfb_pdata); 375 mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
376 376
377 /* power on mmc slot by writing 0 to the gpio */ 377 /* power on mmc slot by writing 0 to the gpio */
378 ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT, 378 ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
379 "mmc0-slot-power"); 379 "mmc0-slot-power");
380 if (ret) 380 if (ret)
381 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); 381 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
382 mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); 382 mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
383 383
384 ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_DIR_OUT, 384 ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW,
385 "mmc1-slot-power"); 385 "mmc1-slot-power");
386 if (ret) 386 if (ret)
387 pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); 387 pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
new file mode 100644
index 000000000000..7f38d82b69af
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -0,0 +1,120 @@
1/*
2 * board setup for STMP378x-Development-Board
3 *
4 * based on mx23evk board setup and information gained form the original
5 * plat-stmp based board setup, now converted to mach-mxs.
6 *
7 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/irq.h>
23#include <linux/spi/spi.h>
24
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/time.h>
28
29#include <mach/common.h>
30#include <mach/iomux-mx23.h>
31
32#include "devices-mx23.h"
33
34#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30)
35#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29)
36
37#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
38
39static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
40 /* duart (extended setup missing in old boardcode, too */
41 MX23_PAD_PWM0__DUART_RX,
42 MX23_PAD_PWM1__DUART_TX,
43
44 /* auart */
45 MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
46 MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
47 MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
48 MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
49
50 /* mmc */
51 MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
52 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
53 MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
54 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
55 MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
56 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
57 MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
58 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
59 MX23_PAD_SSP1_CMD__SSP1_CMD |
60 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
61 MX23_PAD_SSP1_DETECT__SSP1_DETECT |
62 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
63 MX23_PAD_SSP1_SCK__SSP1_SCK |
64 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
65 MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
66 MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
67};
68
69static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
70 .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
71};
72
73static struct spi_board_info spi_board_info[] __initdata = {
74#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
75 {
76 .modalias = "enc28j60",
77 .max_speed_hz = 6 * 1000 * 1000,
78 .bus_num = 1,
79 .chip_select = 0,
80 .platform_data = NULL,
81 },
82#endif
83};
84
85static void __init stmp378x_dvb_init(void)
86{
87 int ret;
88
89 mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
90 ARRAY_SIZE(stmp378x_dvb_pads));
91
92 mx23_add_duart();
93 mx23_add_auart0();
94
95 /* power on mmc slot */
96 ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
97 GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
98 if (ret)
99 pr_warn("could not power mmc (%d)\n", ret);
100
101 mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
102
103 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
104}
105
106static void __init stmp378x_dvb_timer_init(void)
107{
108 mx23_clocks_init();
109}
110
111static struct sys_timer stmp378x_dvb_timer = {
112 .init = stmp378x_dvb_timer_init,
113};
114
115MACHINE_START(STMP378X, "STMP378X")
116 .map_io = mx23_map_io,
117 .init_irq = mx23_init_irq,
118 .init_machine = stmp378x_dvb_init,
119 .timer = &stmp378x_dvb_timer,
120MACHINE_END
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 13647f301860..cace0d2e5a55 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -101,11 +101,6 @@ static cycle_t timrotv1_get_cycles(struct clocksource *cs)
101 & 0xffff0000) >> 16); 101 & 0xffff0000) >> 16);
102} 102}
103 103
104static cycle_t timrotv2_get_cycles(struct clocksource *cs)
105{
106 return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
107}
108
109static int timrotv1_set_next_event(unsigned long evt, 104static int timrotv1_set_next_event(unsigned long evt,
110 struct clock_event_device *dev) 105 struct clock_event_device *dev)
111{ 106{
@@ -230,8 +225,8 @@ static int __init mxs_clockevent_init(struct clk *timer_clk)
230static struct clocksource clocksource_mxs = { 225static struct clocksource clocksource_mxs = {
231 .name = "mxs_timer", 226 .name = "mxs_timer",
232 .rating = 200, 227 .rating = 200,
233 .read = timrotv2_get_cycles, 228 .read = timrotv1_get_cycles,
234 .mask = CLOCKSOURCE_MASK(32), 229 .mask = CLOCKSOURCE_MASK(16),
235 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 230 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
236}; 231};
237 232
@@ -239,12 +234,11 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
239{ 234{
240 unsigned int c = clk_get_rate(timer_clk); 235 unsigned int c = clk_get_rate(timer_clk);
241 236
242 if (timrot_is_v1()) { 237 if (timrot_is_v1())
243 clocksource_mxs.read = timrotv1_get_cycles; 238 clocksource_register_hz(&clocksource_mxs, c);
244 clocksource_mxs.mask = CLOCKSOURCE_MASK(16); 239 else
245 } 240 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
246 241 "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
247 clocksource_register_hz(&clocksource_mxs, c);
248 242
249 return 0; 243 return 0;
250} 244}
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index f12f22d09b6c..e24c141ba489 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -104,19 +104,6 @@ static struct irqaction netx_timer_irq = {
104 .handler = netx_timer_interrupt, 104 .handler = netx_timer_interrupt,
105}; 105};
106 106
107cycle_t netx_get_cycles(struct clocksource *cs)
108{
109 return readl(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
110}
111
112static struct clocksource clocksource_netx = {
113 .name = "netx_timer",
114 .rating = 200,
115 .read = netx_get_cycles,
116 .mask = CLOCKSOURCE_MASK(32),
117 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
118};
119
120/* 107/*
121 * Set up timer interrupt 108 * Set up timer interrupt
122 */ 109 */
@@ -150,7 +137,8 @@ static void __init netx_timer_init(void)
150 writel(NETX_GPIO_COUNTER_CTRL_RUN, 137 writel(NETX_GPIO_COUNTER_CTRL_RUN,
151 NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); 138 NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
152 139
153 clocksource_register_hz(&clocksource_netx, CLOCK_TICK_RATE); 140 clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
141 "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
154 142
155 netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 143 netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
156 netx_clockevent.shift); 144 netx_clockevent.shift);
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig
deleted file mode 100644
index dd0cd5ac4b8b..000000000000
--- a/arch/arm/mach-ns9xxx/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
1if ARCH_NS9XXX
2
3menu "NS9xxx Implementations"
4
5config NS9XXX_HAVE_SERIAL8250
6 bool
7
8config PROCESSOR_NS9360
9 bool
10
11config MODULE_CC9P9360
12 bool
13 select PROCESSOR_NS9360
14
15config BOARD_A9M9750DEV
16 select NS9XXX_HAVE_SERIAL8250
17 bool
18
19config BOARD_JSCC9P9360
20 bool
21
22config MACH_CC9P9360DEV
23 bool "ConnectCore 9P 9360 on an A9M9750 Devboard"
24 select MODULE_CC9P9360
25 select BOARD_A9M9750DEV
26 help
27 Say Y here if you are using the Digi ConnectCore 9P 9360
28 on an A9M9750 Development Board.
29
30config MACH_CC9P9360JS
31 bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard"
32 select MODULE_CC9P9360
33 select BOARD_JSCC9P9360
34 help
35 Say Y here if you are using the Digi ConnectCore 9P 9360
36 on an JSCC9P9360 Development Board.
37
38endmenu
39
40endif
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile
deleted file mode 100644
index 41efaf9ad50b..000000000000
--- a/arch/arm/mach-ns9xxx/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
1obj-y := clock.o generic.o gpio.o irq.o
2
3obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
4obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
5
6obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o
7
8obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
9obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
10
11# platform devices
12obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o
diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot
deleted file mode 100644
index 54654919229b..000000000000
--- a/arch/arm/mach-ns9xxx/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1zreladdr-y := 0x8000
2params_phys-y := 0x100
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
deleted file mode 100644
index e27687d53504..000000000000
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/board-a9m9750dev.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/irq.h>
12
13#include <asm/mach/map.h>
14#include <asm/gpio.h>
15
16#include <mach/board.h>
17#include <mach/processor-ns9360.h>
18#include <mach/regs-sys-ns9360.h>
19#include <mach/regs-mem.h>
20#include <mach/regs-bbu.h>
21#include <mach/regs-board-a9m9750dev.h>
22
23#include "board-a9m9750dev.h"
24
25static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
26 { /* FPGA on CS0 */
27 .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
28 .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
29 .length = NS9XXX_CS0STAT_LENGTH,
30 .type = MT_DEVICE,
31 },
32};
33
34void __init board_a9m9750dev_map_io(void)
35{
36 iotable_init(board_a9m9750dev_io_desc,
37 ARRAY_SIZE(board_a9m9750dev_io_desc));
38}
39
40static void a9m9750dev_fpga_ack_irq(struct irq_data *d)
41{
42 /* nothing */
43}
44
45static void a9m9750dev_fpga_mask_irq(struct irq_data *d)
46{
47 u8 ier;
48
49 ier = __raw_readb(FPGA_IER);
50
51 ier &= ~(1 << (d->irq - FPGA_IRQ(0)));
52
53 __raw_writeb(ier, FPGA_IER);
54}
55
56static void a9m9750dev_fpga_maskack_irq(struct irq_data *d)
57{
58 a9m9750dev_fpga_mask_irq(d);
59 a9m9750dev_fpga_ack_irq(d);
60}
61
62static void a9m9750dev_fpga_unmask_irq(struct irq_data *d)
63{
64 u8 ier;
65
66 ier = __raw_readb(FPGA_IER);
67
68 ier |= 1 << (d->irq - FPGA_IRQ(0));
69
70 __raw_writeb(ier, FPGA_IER);
71}
72
73static struct irq_chip a9m9750dev_fpga_chip = {
74 .irq_ack = a9m9750dev_fpga_ack_irq,
75 .irq_mask = a9m9750dev_fpga_mask_irq,
76 .irq_mask_ack = a9m9750dev_fpga_maskack_irq,
77 .irq_unmask = a9m9750dev_fpga_unmask_irq,
78};
79
80static void a9m9750dev_fpga_demux_handler(unsigned int irq,
81 struct irq_desc *desc)
82{
83 u8 stat = __raw_readb(FPGA_ISR);
84
85 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
86
87 while (stat != 0) {
88 int irqno = fls(stat) - 1;
89
90 stat &= ~(1 << irqno);
91
92 generic_handle_irq(FPGA_IRQ(irqno));
93 }
94
95 desc->irq_data.chip->irq_unmask(&desc->irq_data);
96}
97
98void __init board_a9m9750dev_init_irq(void)
99{
100 u32 eic;
101 int i;
102
103 if (gpio_request(11, "board a9m9750dev extirq2") == 0)
104 ns9360_gpio_configure(11, 0, 1);
105 else
106 printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
107 __func__);
108
109 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
110 irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
111 handle_level_irq);
112 set_irq_flags(i, IRQF_VALID);
113 }
114
115 /* IRQ_NS9XXX_EXT2: level sensitive + active low */
116 eic = __raw_readl(SYS_EIC(2));
117 REGSET(eic, SYS_EIC, PLTY, AL);
118 REGSET(eic, SYS_EIC, LVEDG, LEVEL);
119 __raw_writel(eic, SYS_EIC(2));
120
121 irq_set_chained_handler(IRQ_NS9XXX_EXT2,
122 a9m9750dev_fpga_demux_handler);
123}
124
125void __init board_a9m9750dev_init_machine(void)
126{
127 u32 reg;
128
129 /* setup static CS0: memory base ... */
130 reg = __raw_readl(SYS_SMCSSMB(0));
131 REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
132 __raw_writel(reg, SYS_SMCSSMB(0));
133
134 /* ... and mask */
135 reg = __raw_readl(SYS_SMCSSMM(0));
136 REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
137 REGSET(reg, SYS_SMCSSMM, CSEx, EN);
138 __raw_writel(reg, SYS_SMCSSMM(0));
139
140 /* setup static CS0: memory configuration */
141 reg = __raw_readl(MEM_SMC(0));
142 REGSET(reg, MEM_SMC, PSMC, OFF);
143 REGSET(reg, MEM_SMC, BSMC, OFF);
144 REGSET(reg, MEM_SMC, EW, OFF);
145 REGSET(reg, MEM_SMC, PB, 1);
146 REGSET(reg, MEM_SMC, PC, AL);
147 REGSET(reg, MEM_SMC, PM, DIS);
148 REGSET(reg, MEM_SMC, MW, 8);
149 __raw_writel(reg, MEM_SMC(0));
150
151 /* setup static CS0: timing */
152 __raw_writel(0x2, MEM_SMWED(0));
153 __raw_writel(0x2, MEM_SMOED(0));
154 __raw_writel(0x6, MEM_SMRD(0));
155 __raw_writel(0x6, MEM_SMWD(0));
156}
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.h b/arch/arm/mach-ns9xxx/board-a9m9750dev.h
deleted file mode 100644
index edc75abbc5dd..000000000000
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/board-a9m9750dev.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/init.h>
12
13void __init board_a9m9750dev_map_io(void);
14void __init board_a9m9750dev_init_machine(void);
15void __init board_a9m9750dev_init_irq(void);
diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.c b/arch/arm/mach-ns9xxx/board-jscc9p9360.c
deleted file mode 100644
index 4bd3eec04bfe..000000000000
--- a/arch/arm/mach-ns9xxx/board-jscc9p9360.c
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/board-jscc9p9360.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include "board-jscc9p9360.h"
12
13void __init board_jscc9p9360_init_machine(void)
14{
15 /* TODO: reserve GPIOs for push buttons, etc pp */
16}
17
diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.h b/arch/arm/mach-ns9xxx/board-jscc9p9360.h
deleted file mode 100644
index 1a81a074df45..000000000000
--- a/arch/arm/mach-ns9xxx/board-jscc9p9360.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/board-jscc9p9360.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/init.h>
12
13void __init board_jscc9p9360_init_machine(void);
diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c
deleted file mode 100644
index cf81cbc57544..000000000000
--- a/arch/arm/mach-ns9xxx/clock.c
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/clock.c
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/err.h>
12#include <linux/module.h>
13#include <linux/list.h>
14#include <linux/clk.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17#include <linux/semaphore.h>
18
19#include "clock.h"
20
21static LIST_HEAD(clocks);
22static DEFINE_SPINLOCK(clk_lock);
23
24struct clk *clk_get(struct device *dev, const char *id)
25{
26 struct clk *p, *ret = NULL, *retgen = NULL;
27 unsigned long flags;
28 int idno;
29
30 if (dev == NULL || dev->bus != &platform_bus_type)
31 idno = -1;
32 else
33 idno = to_platform_device(dev)->id;
34
35 spin_lock_irqsave(&clk_lock, flags);
36 list_for_each_entry(p, &clocks, node) {
37 if (strcmp(id, p->name) == 0) {
38 if (p->id == idno) {
39 if (!try_module_get(p->owner))
40 continue;
41 ret = p;
42 break;
43 } else if (p->id == -1)
44 /* remember match with id == -1 in case there is
45 * no clock for idno */
46 retgen = p;
47 }
48 }
49
50 if (!ret && retgen && try_module_get(retgen->owner))
51 ret = retgen;
52
53 if (ret)
54 ++ret->refcount;
55
56 spin_unlock_irqrestore(&clk_lock, flags);
57
58 return ret ? ret : ERR_PTR(-ENOENT);
59}
60EXPORT_SYMBOL(clk_get);
61
62void clk_put(struct clk *clk)
63{
64 module_put(clk->owner);
65 --clk->refcount;
66}
67EXPORT_SYMBOL(clk_put);
68
69static int clk_enable_unlocked(struct clk *clk)
70{
71 int ret = 0;
72 if (clk->parent) {
73 ret = clk_enable_unlocked(clk->parent);
74 if (ret)
75 return ret;
76 }
77
78 if (clk->usage++ == 0 && clk->endisable)
79 ret = clk->endisable(clk, 1);
80
81 return ret;
82}
83
84int clk_enable(struct clk *clk)
85{
86 int ret;
87 unsigned long flags;
88
89 spin_lock_irqsave(&clk_lock, flags);
90
91 ret = clk_enable_unlocked(clk);
92
93 spin_unlock_irqrestore(&clk_lock, flags);
94
95 return ret;
96}
97EXPORT_SYMBOL(clk_enable);
98
99static void clk_disable_unlocked(struct clk *clk)
100{
101 if (--clk->usage == 0 && clk->endisable)
102 clk->endisable(clk, 0);
103
104 if (clk->parent)
105 clk_disable_unlocked(clk->parent);
106}
107
108void clk_disable(struct clk *clk)
109{
110 unsigned long flags;
111
112 spin_lock_irqsave(&clk_lock, flags);
113
114 clk_disable_unlocked(clk);
115
116 spin_unlock_irqrestore(&clk_lock, flags);
117}
118EXPORT_SYMBOL(clk_disable);
119
120unsigned long clk_get_rate(struct clk *clk)
121{
122 if (clk->get_rate)
123 return clk->get_rate(clk);
124
125 if (clk->rate)
126 return clk->rate;
127
128 if (clk->parent)
129 return clk_get_rate(clk->parent);
130
131 return 0;
132}
133EXPORT_SYMBOL(clk_get_rate);
134
135int clk_register(struct clk *clk)
136{
137 unsigned long flags;
138
139 spin_lock_irqsave(&clk_lock, flags);
140
141 list_add(&clk->node, &clocks);
142
143 if (clk->parent)
144 ++clk->parent->refcount;
145
146 spin_unlock_irqrestore(&clk_lock, flags);
147
148 return 0;
149}
150
151int clk_unregister(struct clk *clk)
152{
153 int ret = 0;
154 unsigned long flags;
155
156 spin_lock_irqsave(&clk_lock, flags);
157
158 if (clk->usage || clk->refcount)
159 ret = -EBUSY;
160 else
161 list_del(&clk->node);
162
163 if (clk->parent)
164 --clk->parent->refcount;
165
166 spin_unlock_irqrestore(&clk_lock, flags);
167
168 return ret;
169}
170
171#if defined CONFIG_DEBUG_FS
172
173#include <linux/debugfs.h>
174#include <linux/seq_file.h>
175
176static int clk_debugfs_show(struct seq_file *s, void *null)
177{
178 unsigned long flags;
179 struct clk *p;
180
181 spin_lock_irqsave(&clk_lock, flags);
182
183 list_for_each_entry(p, &clocks, node)
184 seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n",
185 p->name, p->id, p->usage, p->refcount,
186 p->usage ? clk_get_rate(p) : 0);
187
188 spin_unlock_irqrestore(&clk_lock, flags);
189
190 return 0;
191}
192
193static int clk_debugfs_open(struct inode *inode, struct file *file)
194{
195 return single_open(file, clk_debugfs_show, NULL);
196}
197
198static const struct file_operations clk_debugfs_operations = {
199 .open = clk_debugfs_open,
200 .read = seq_read,
201 .llseek = seq_lseek,
202 .release = single_release,
203};
204
205static int __init clk_debugfs_init(void)
206{
207 struct dentry *dentry;
208
209 dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL,
210 &clk_debugfs_operations);
211 return IS_ERR(dentry) ? PTR_ERR(dentry) : 0;
212}
213subsys_initcall(clk_debugfs_init);
214
215#endif /* if defined CONFIG_DEBUG_FS */
diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h
deleted file mode 100644
index b86c30dd79eb..000000000000
--- a/arch/arm/mach-ns9xxx/clock.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/clock.h
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __NS9XXX_CLOCK_H
12#define __NS9XXX_CLOCK_H
13
14#include <linux/list.h>
15
16struct clk {
17 struct module *owner;
18 const char *name;
19 int id;
20
21 struct clk *parent;
22
23 unsigned long rate;
24 int (*endisable)(struct clk *, int enable);
25 unsigned long (*get_rate)(struct clk *);
26
27 struct list_head node;
28 unsigned long refcount;
29 unsigned long usage;
30};
31
32int clk_register(struct clk *clk);
33int clk_unregister(struct clk *clk);
34
35#endif /* ifndef __NS9XXX_CLOCK_H */
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c
deleted file mode 100644
index 1e0f467879cc..000000000000
--- a/arch/arm/mach-ns9xxx/generic.c
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/generic.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <asm/memory.h>
14
15#include "generic.h"
16
17void __init ns9xxx_init_machine(void)
18{
19}
diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h
deleted file mode 100644
index 82493191aad6..000000000000
--- a/arch/arm/mach-ns9xxx/generic.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/generic.h
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/time.h>
12#include <asm/mach/time.h>
13#include <linux/init.h>
14
15void __init ns9xxx_init_irq(void);
16void __init ns9xxx_init_machine(void);
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c
deleted file mode 100644
index 377330c1b250..000000000000
--- a/arch/arm/mach-ns9xxx/gpio-ns9360.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/gpio-ns9360.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/bug.h>
12#include <linux/errno.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16
17#include <mach/regs-bbu.h>
18#include <mach/processor-ns9360.h>
19
20#include "gpio-ns9360.h"
21
22static inline int ns9360_valid_gpio(unsigned gpio)
23{
24 return gpio <= 72;
25}
26
27static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio)
28{
29 if (gpio < 56)
30 return BBU_GCONFb1(gpio / 8);
31 else
32 /*
33 * this could be optimised away on
34 * ns9750 only builds, but it isn't ...
35 */
36 return BBU_GCONFb2((gpio - 56) / 8);
37}
38
39static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio)
40{
41 if (gpio < 32)
42 return BBU_GCTRL1;
43 else if (gpio < 64)
44 return BBU_GCTRL2;
45 else
46 /* this could be optimised away on ns9750 only builds */
47 return BBU_GCTRL3;
48}
49
50static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio)
51{
52 if (gpio < 32)
53 return BBU_GSTAT1;
54 else if (gpio < 64)
55 return BBU_GSTAT2;
56 else
57 /* this could be optimised away on ns9750 only builds */
58 return BBU_GSTAT3;
59}
60
61/*
62 * each gpio can serve for 4 different purposes [0..3]. These are called
63 * "functions" and passed in the parameter func. Functions 0-2 are always some
64 * special things, function 3 is GPIO. If func == 3 dir specifies input or
65 * output, and with inv you can enable an inverter (independent of func).
66 */
67int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func)
68{
69 void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio);
70 u32 confval;
71
72 confval = __raw_readl(conf);
73 REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
74 REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
75 REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
76 __raw_writel(confval, conf);
77
78 return 0;
79}
80
81int ns9360_gpio_configure(unsigned gpio, int inv, int func)
82{
83 if (likely(ns9360_valid_gpio(gpio))) {
84 if (func == 3) {
85 printk(KERN_WARNING "use gpio_direction_input "
86 "or gpio_direction_output\n");
87 return -EINVAL;
88 } else
89 return __ns9360_gpio_configure(gpio, 0, inv, func);
90 } else
91 return -EINVAL;
92}
93EXPORT_SYMBOL(ns9360_gpio_configure);
94
95int ns9360_gpio_get_value(unsigned gpio)
96{
97 void __iomem *stat = ns9360_gpio_get_gstataddr(gpio);
98 int ret;
99
100 ret = 1 & (__raw_readl(stat) >> (gpio & 31));
101
102 return ret;
103}
104
105void ns9360_gpio_set_value(unsigned gpio, int value)
106{
107 void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio);
108 u32 ctrlval;
109
110 ctrlval = __raw_readl(ctrl);
111
112 if (value)
113 ctrlval |= 1 << (gpio & 31);
114 else
115 ctrlval &= ~(1 << (gpio & 31));
116
117 __raw_writel(ctrlval, ctrl);
118}
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h
deleted file mode 100644
index 131cd1715caa..000000000000
--- a/arch/arm/mach-ns9xxx/gpio-ns9360.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/gpio-ns9360.h
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func);
12int ns9360_gpio_get_value(unsigned gpio);
13void ns9360_gpio_set_value(unsigned gpio, int value);
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c
deleted file mode 100644
index 5503ca09c4ae..000000000000
--- a/arch/arm/mach-ns9xxx/gpio.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/gpio.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/compiler.h>
13#include <linux/init.h>
14#include <linux/spinlock.h>
15#include <linux/module.h>
16#include <linux/bitops.h>
17
18#include <mach/gpio.h>
19#include <mach/processor.h>
20#include <mach/processor-ns9360.h>
21#include <asm/bug.h>
22#include <asm/types.h>
23
24#include "gpio-ns9360.h"
25
26#if defined(CONFIG_PROCESSOR_NS9360)
27#define GPIO_MAX 72
28#elif defined(CONFIG_PROCESSOR_NS9750)
29#define GPIO_MAX 49
30#endif
31
32/* protects BBU_GCONFx and BBU_GCTRLx */
33static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock);
34
35/* only access gpiores with atomic ops */
36static DECLARE_BITMAP(gpiores, GPIO_MAX + 1);
37
38static inline int ns9xxx_valid_gpio(unsigned gpio)
39{
40#if defined(CONFIG_PROCESSOR_NS9360)
41 if (processor_is_ns9360())
42 return gpio <= 72;
43 else
44#endif
45#if defined(CONFIG_PROCESSOR_NS9750)
46 if (processor_is_ns9750())
47 return gpio <= 49;
48 else
49#endif
50 {
51 BUG();
52 return 0;
53 }
54}
55
56int gpio_request(unsigned gpio, const char *label)
57{
58 if (likely(ns9xxx_valid_gpio(gpio)))
59 return test_and_set_bit(gpio, gpiores) ? -EBUSY : 0;
60 else
61 return -EINVAL;
62}
63EXPORT_SYMBOL(gpio_request);
64
65void gpio_free(unsigned gpio)
66{
67 might_sleep();
68 clear_bit(gpio, gpiores);
69 return;
70}
71EXPORT_SYMBOL(gpio_free);
72
73int gpio_direction_input(unsigned gpio)
74{
75 if (likely(ns9xxx_valid_gpio(gpio))) {
76 int ret = -EINVAL;
77 unsigned long flags;
78
79 spin_lock_irqsave(&gpio_lock, flags);
80#if defined(CONFIG_PROCESSOR_NS9360)
81 if (processor_is_ns9360())
82 ret = __ns9360_gpio_configure(gpio, 0, 0, 3);
83 else
84#endif
85 BUG();
86
87 spin_unlock_irqrestore(&gpio_lock, flags);
88
89 return ret;
90
91 } else
92 return -EINVAL;
93}
94EXPORT_SYMBOL(gpio_direction_input);
95
96int gpio_direction_output(unsigned gpio, int value)
97{
98 if (likely(ns9xxx_valid_gpio(gpio))) {
99 int ret = -EINVAL;
100 unsigned long flags;
101
102 gpio_set_value(gpio, value);
103
104 spin_lock_irqsave(&gpio_lock, flags);
105#if defined(CONFIG_PROCESSOR_NS9360)
106 if (processor_is_ns9360())
107 ret = __ns9360_gpio_configure(gpio, 1, 0, 3);
108 else
109#endif
110 BUG();
111
112 spin_unlock_irqrestore(&gpio_lock, flags);
113
114 return ret;
115 } else
116 return -EINVAL;
117}
118EXPORT_SYMBOL(gpio_direction_output);
119
120int gpio_get_value(unsigned gpio)
121{
122#if defined(CONFIG_PROCESSOR_NS9360)
123 if (processor_is_ns9360())
124 return ns9360_gpio_get_value(gpio);
125 else
126#endif
127 {
128 BUG();
129 return -EINVAL;
130 }
131}
132EXPORT_SYMBOL(gpio_get_value);
133
134void gpio_set_value(unsigned gpio, int value)
135{
136 unsigned long flags;
137 spin_lock_irqsave(&gpio_lock, flags);
138#if defined(CONFIG_PROCESSOR_NS9360)
139 if (processor_is_ns9360())
140 ns9360_gpio_set_value(gpio, value);
141 else
142#endif
143 BUG();
144
145 spin_unlock_irqrestore(&gpio_lock, flags);
146}
147EXPORT_SYMBOL(gpio_set_value);
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h
deleted file mode 100644
index 19ca6de46a45..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/board.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/board.h
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_BOARD_H
12#define __ASM_ARCH_BOARD_H
13
14#include <asm/mach-types.h>
15
16#define board_is_a9m9750dev() (0 \
17 || machine_is_cc9p9750dev() \
18 )
19
20#define board_is_a9mvali() (0 \
21 || machine_is_cc9p9750val() \
22 )
23
24#define board_is_jscc9p9210() (0 \
25 || machine_is_cc9p9210js() \
26 )
27
28#define board_is_jscc9p9215() (0 \
29 || machine_is_cc9p9215js() \
30 )
31
32#define board_is_jscc9p9360() (0 \
33 || machine_is_cc9p9360js() \
34 )
35
36#define board_is_uncbas() (0 \
37 || machine_is_cc7ucamry() \
38 )
39
40#endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
deleted file mode 100644
index 5a2acbdc3d67..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/debug-macro.S
3 * Copyright (C) 2006 by Digi International Inc.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 */
10#include <mach/hardware.h>
11#include <asm/memory.h>
12
13#include <mach/regs-board-a9m9750dev.h>
14
15 .macro addruart, rp, rv
16 ldr \rp, =NS9XXX_CSxSTAT_PHYS(0)
17 ldr \rv, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
18 .endm
19
20#define UART_SHIFT 2
21#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
deleted file mode 100644
index 71ca0319b547..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/entry-macro.S
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <mach/hardware.h>
12#include <mach/regs-sys-common.h>
13
14 .macro get_irqnr_preamble, base, tmp
15 ldr \base, =SYS_ISRADDR
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22 ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
23 cmp \irqstat, #0
24 ldrne \irqnr, [\base]
25 .endm
26
27 .macro disable_fiq
28 .endm
diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h
deleted file mode 100644
index 5eb349032579..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/gpio.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/gpio.h
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10*/
11#ifndef __ASM_ARCH_GPIO_H
12#define __ASM_ARCH_GPIO_H
13
14#include <asm/errno.h>
15
16int gpio_request(unsigned gpio, const char *label);
17
18void gpio_free(unsigned gpio);
19
20int ns9xxx_gpio_configure(unsigned gpio, int inv, int func);
21
22int gpio_direction_input(unsigned gpio);
23
24int gpio_direction_output(unsigned gpio, int value);
25
26int gpio_get_value(unsigned gpio);
27
28void gpio_set_value(unsigned gpio, int value);
29
30/*
31 * ns9xxx can use gpio pins to trigger an irq, but it's not generic
32 * enough to be supported by the gpio_to_irq/irq_to_gpio interface
33 */
34static inline int gpio_to_irq(unsigned gpio)
35{
36 return -EINVAL;
37}
38
39static inline int irq_to_gpio(unsigned irq)
40{
41 return -EINVAL;
42}
43
44/* get the cansleep() stubs */
45#include <asm-generic/gpio.h>
46
47#endif /* ifndef __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h
deleted file mode 100644
index 76631128e11c..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/hardware.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_HARDWARE_H
12#define __ASM_ARCH_HARDWARE_H
13
14/*
15 * NetSilicon NS9xxx internal mapping:
16 *
17 * physical <--> virtual
18 * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff
19 * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff
20 */
21#define io_p2v(x) (0xf0000000 \
22 + (((x) & 0xf0000000) >> 4) \
23 + ((x) & 0x00ffffff))
24
25#define io_v2p(x) ((((x) & 0x0f000000) << 4) \
26 + ((x) & 0x00ffffff))
27
28#define __REGSHIFT(mask) ((mask) & (-(mask)))
29
30#define __REGBIT(bit) ((u32)1 << (bit))
31#define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit))
32#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask))
33
34#ifndef __ASSEMBLY__
35
36# define __REG(x) ((void __iomem __force *)io_p2v((x)))
37# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
38
39# define __REGSET(var, field, value) \
40 ((var) = (((var) & ~((field) & ~(value))) | (value)))
41
42# define REGSET(var, reg, field, value) \
43 __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value)
44
45# define REGSET_IDX(var, reg, field, idx, value) \
46 __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx)))
47
48# define REGSETIM(var, reg, field, value) \
49 __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value)))
50
51# define REGSETIM_IDX(var, reg, field, idx, value) \
52 __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value)))
53
54# define __REGGET(var, field) \
55 (((var) & (field)))
56
57# define REGGET(var, reg, field) \
58 __REGGET(var, reg ## _ ## field)
59
60# define REGGET_IDX(var, reg, field, idx) \
61 __REGGET(var, reg ## _ ## field((idx)))
62
63# define REGGETIM(var, reg, field) \
64 __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
65
66# define REGGETIM_IDX(var, reg, field, idx) \
67 __REGGET(var, reg ## _ ## field((idx))) / \
68 __REGSHIFT(reg ## _ ## field((idx)))
69
70#else
71
72# define __REG(x) io_p2v(x)
73# define __REG2(x, y) io_p2v((x) + 4 * (y))
74
75#endif
76
77#endif /* ifndef __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
deleted file mode 100644
index f08451d2e1bc..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/io.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_IO_H
12#define __ASM_ARCH_IO_H
13
14#define IO_SPACE_LIMIT 0xffffffff /* XXX */
15
16#define __io(a) __typesafe_io(a)
17#define __mem_pci(a) (a)
18#define __mem_isa(a) (IO_BASE + (a))
19
20#endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h
deleted file mode 100644
index 13483949e210..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/irqs.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/irqs.h
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14/* NetSilicon 9360 */
15#define IRQ_NS9XXX_WATCHDOG 0
16#define IRQ_NS9XXX_AHBBUSERR 1
17#define IRQ_NS9360_BBUSAGG 2
18/* irq 3 is reserved for NS9360 */
19#define IRQ_NS9XXX_ETHRX 4
20#define IRQ_NS9XXX_ETHTX 5
21#define IRQ_NS9XXX_ETHPHY 6
22#define IRQ_NS9360_LCD 7
23#define IRQ_NS9360_SERBRX 8
24#define IRQ_NS9360_SERBTX 9
25#define IRQ_NS9360_SERARX 10
26#define IRQ_NS9360_SERATX 11
27#define IRQ_NS9360_SERCRX 12
28#define IRQ_NS9360_SERCTX 13
29#define IRQ_NS9360_I2C 14
30#define IRQ_NS9360_BBUSDMA 15
31#define IRQ_NS9360_TIMER0 16
32#define IRQ_NS9360_TIMER1 17
33#define IRQ_NS9360_TIMER2 18
34#define IRQ_NS9360_TIMER3 19
35#define IRQ_NS9360_TIMER4 20
36#define IRQ_NS9360_TIMER5 21
37#define IRQ_NS9360_TIMER6 22
38#define IRQ_NS9360_TIMER7 23
39#define IRQ_NS9360_RTC 24
40#define IRQ_NS9360_USBHOST 25
41#define IRQ_NS9360_USBDEVICE 26
42#define IRQ_NS9360_IEEE1284 27
43#define IRQ_NS9XXX_EXT0 28
44#define IRQ_NS9XXX_EXT1 29
45#define IRQ_NS9XXX_EXT2 30
46#define IRQ_NS9XXX_EXT3 31
47
48#define BBUS_IRQ(irq) (32 + irq)
49
50#define IRQ_BBUS_DMA BBUS_IRQ(0)
51#define IRQ_BBUS_SERBRX BBUS_IRQ(2)
52#define IRQ_BBUS_SERBTX BBUS_IRQ(3)
53#define IRQ_BBUS_SERARX BBUS_IRQ(4)
54#define IRQ_BBUS_SERATX BBUS_IRQ(5)
55#define IRQ_BBUS_SERCRX BBUS_IRQ(6)
56#define IRQ_BBUS_SERCTX BBUS_IRQ(7)
57#define IRQ_BBUS_SERDRX BBUS_IRQ(8)
58#define IRQ_BBUS_SERDTX BBUS_IRQ(9)
59#define IRQ_BBUS_I2C BBUS_IRQ(10)
60#define IRQ_BBUS_1284 BBUS_IRQ(11)
61#define IRQ_BBUS_UTIL BBUS_IRQ(12)
62#define IRQ_BBUS_RTC BBUS_IRQ(13)
63#define IRQ_BBUS_USBHST BBUS_IRQ(14)
64#define IRQ_BBUS_USBDEV BBUS_IRQ(15)
65#define IRQ_BBUS_AHBDMA1 BBUS_IRQ(24)
66#define IRQ_BBUS_AHBDMA2 BBUS_IRQ(25)
67
68/*
69 * these Interrupts are specific for the a9m9750dev board.
70 * They are generated by an FPGA that interrupts the CPU on
71 * IRQ_NS9360_EXT2
72 */
73#define FPGA_IRQ(irq) (64 + irq)
74
75#define IRQ_FPGA_UARTA FPGA_IRQ(0)
76#define IRQ_FPGA_UARTB FPGA_IRQ(1)
77#define IRQ_FPGA_UARTC FPGA_IRQ(2)
78#define IRQ_FPGA_UARTD FPGA_IRQ(3)
79#define IRQ_FPGA_TOUCH FPGA_IRQ(4)
80#define IRQ_FPGA_CF FPGA_IRQ(5)
81#define IRQ_FPGA_CAN0 FPGA_IRQ(6)
82#define IRQ_FPGA_CAN1 FPGA_IRQ(7)
83
84#define NR_IRQS 72
85
86#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h
deleted file mode 100644
index 5c65aee6e7a9..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/memory.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/memory.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10*/
11#ifndef __ASM_ARCH_MEMORY_H
12#define __ASM_ARCH_MEMORY_H
13
14/* x in [0..3] */
15#define NS9XXX_CSxSTAT_PHYS(x) UL(((x) + 4) << 28)
16
17#define NS9XXX_CS0STAT_LENGTH UL(0x1000)
18#define NS9XXX_CS1STAT_LENGTH UL(0x1000)
19#define NS9XXX_CS2STAT_LENGTH UL(0x1000)
20#define NS9XXX_CS3STAT_LENGTH UL(0x1000)
21
22#define PLAT_PHYS_OFFSET UL(0x00000000)
23
24#endif
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h
deleted file mode 100644
index 628e9752589b..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/module.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/module.h
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_MODULE_H
12#define __ASM_ARCH_MODULE_H
13
14#include <asm/mach-types.h>
15
16#define module_is_cc7ucamry() (0 \
17 || machine_is_cc7ucamry() \
18 )
19
20#define module_is_cc9c() (0 \
21 )
22
23#define module_is_cc9p9210() (0 \
24 || machine_is_cc9p9210() \
25 || machine_is_cc9p9210js() \
26 )
27
28#define module_is_cc9p9215() (0 \
29 || machine_is_cc9p9215() \
30 || machine_is_cc9p9215js() \
31 )
32
33#define module_is_cc9p9360() (0 \
34 || machine_is_cc9p9360dev() \
35 || machine_is_cc9p9360js() \
36 )
37
38#define module_is_cc9p9750() (0 \
39 || machine_is_a9m9750() \
40 || machine_is_cc9p9750js() \
41 || machine_is_cc9p9750val() \
42 )
43
44#define module_is_ccw9c() (0 \
45 )
46
47#define module_is_inc20otter() (0 \
48 || machine_is_inc20otter() \
49 )
50
51#define module_is_otter() (0 \
52 || machine_is_otter() \
53 )
54
55#endif /* ifndef __ASM_ARCH_MODULE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
deleted file mode 100644
index f41deda5129e..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_PROCESSORNS9360_H
12#define __ASM_ARCH_PROCESSORNS9360_H
13
14#include <linux/init.h>
15
16void ns9360_reset(char mode);
17
18unsigned long ns9360_systemclock(void) __attribute__((const));
19
20static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
21static inline unsigned long ns9360_cpuclock(void)
22{
23 return ns9360_systemclock() / 2;
24}
25
26void __init ns9360_map_io(void);
27
28extern struct sys_timer ns9360_timer;
29
30int ns9360_gpio_configure(unsigned gpio, int inv, int func);
31
32#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h
deleted file mode 100644
index 9f77f746a386..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/processor.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/processor.h
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_PROCESSOR_H
12#define __ASM_ARCH_PROCESSOR_H
13
14#include <mach/module.h>
15
16#define processor_is_ns9210() (0 \
17 || module_is_cc7ucamry() \
18 || module_is_cc9p9210() \
19 || module_is_inc20otter() \
20 || module_is_otter() \
21 )
22
23#define processor_is_ns9215() (0 \
24 || module_is_cc9p9215() \
25 )
26
27#define processor_is_ns9360() (0 \
28 || module_is_cc9p9360() \
29 || module_is_cc9c() \
30 || module_is_ccw9c() \
31 )
32
33#define processor_is_ns9750() (0 \
34 || module_is_cc9p9750() \
35 )
36
37#define processor_is_ns921x() (0 \
38 || processor_is_ns9210() \
39 || processor_is_ns9215() \
40 )
41
42#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
deleted file mode 100644
index af227c058fb9..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_REGSBBU_H
12#define __ASM_ARCH_REGSBBU_H
13
14#include <mach/hardware.h>
15
16/* BBus Utility */
17
18/* GPIO Configuration Registers block 1 */
19/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
20 * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register
21 * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
22#define BBU_GCONFb1(x) __REG2(0x90600010, (x))
23#define BBU_GCONFb2(x) __REG2(0x90600100, (x))
24
25#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2))
26#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
27#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1)
28#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2))
29#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0)
30#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1)
31#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
32#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0)
33#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1)
34#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2)
35#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3)
36
37#define BBU_GCTRL1 __REG(0x90600030)
38#define BBU_GCTRL2 __REG(0x90600034)
39#define BBU_GCTRL3 __REG(0x90600120)
40
41#define BBU_GSTAT1 __REG(0x90600040)
42#define BBU_GSTAT2 __REG(0x90600044)
43#define BBU_GSTAT3 __REG(0x90600130)
44
45#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
deleted file mode 100644
index cd1593693f56..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_REGSBOARDA9M9750_H
12#define __ASM_ARCH_REGSBOARDA9M9750_H
13
14#include <mach/hardware.h>
15
16#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0))
17#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08)
18#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
19#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
20
21#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
22#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
23
24#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
deleted file mode 100644
index f1625bf8cdce..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/regs-mem.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_REGSMEM_H
12#define __ASM_ARCH_REGSMEM_H
13
14#include <mach/hardware.h>
15
16/* Memory Module */
17
18/* Control register */
19#define MEM_CTRL __REG(0xa0700000)
20
21/* Status register */
22#define MEM_STAT __REG(0xa0700004)
23
24/* Configuration register */
25#define MEM_CONF __REG(0xa0700008)
26
27/* Dynamic Memory Control register */
28#define MEM_DMCTRL __REG(0xa0700020)
29
30/* Dynamic Memory Refresh Timer */
31#define MEM_DMRT __REG(0xa0700024)
32
33/* Dynamic Memory Read Configuration register */
34#define MEM_DMRC __REG(0xa0700028)
35
36/* Dynamic Memory Precharge Command Period (tRP) */
37#define MEM_DMPCP __REG(0xa0700030)
38
39/* Dynamic Memory Active to Precharge Command Period (tRAS) */
40#define MEM_DMAPCP __REG(0xa0700034)
41
42/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
43#define MEM_DMSRET __REG(0xa0700038)
44
45/* Dynamic Memory Last Data Out to Active Time (tAPR) */
46#define MEM_DMLDOAT __REG(0xa070003c)
47
48/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
49#define MEM_DMDIACT __REG(0xa0700040)
50
51/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
52#define MEM_DMWRT __REG(0xa0700044)
53
54/* Dynamic Memory Active to Active Command Period (tRC) */
55#define MEM_DMAACP __REG(0xa0700048)
56
57/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
58#define MEM_DMARP __REG(0xa070004c)
59
60/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
61#define MEM_DMESRAC __REG(0xa0700050)
62
63/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
64#define MEM_DMABAABT __REG(0xa0700054)
65
66/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
67#define MEM_DMLMACT __REG(0xa0700058)
68
69/* Static Memory Extended Wait */
70#define MEM_SMEW __REG(0xa0700080)
71
72/* Dynamic Memory Configuration Register x */
73#define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3)
74
75/* Dynamic Memory RAS and CAS Delay x */
76#define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3)
77
78/* Static Memory Configuration Register x */
79#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
80
81/* Static Memory Configuration Register x: Write protect */
82#define MEM_SMC_PSMC __REGBIT(20)
83#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0)
84#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1)
85
86/* Static Memory Configuration Register x: Buffer enable */
87#define MEM_SMC_BSMC __REGBIT(19)
88#define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0)
89#define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1)
90
91/* Static Memory Configuration Register x: Extended Wait */
92#define MEM_SMC_EW __REGBIT(8)
93#define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0)
94#define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1)
95
96/* Static Memory Configuration Register x: Byte lane state */
97#define MEM_SMC_PB __REGBIT(7)
98#define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0)
99#define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1)
100
101/* Static Memory Configuration Register x: Chip select polarity */
102#define MEM_SMC_PC __REGBIT(6)
103#define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0)
104#define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1)
105
106/* static memory configuration register x: page mode*/
107#define MEM_SMC_PM __REGBIT(3)
108#define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0)
109#define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1)
110
111/* static memory configuration register x: Memory width */
112#define MEM_SMC_MW __REGBITS(1, 0)
113#define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0)
114#define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1)
115#define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2)
116
117/* Static Memory Write Enable Delay x */
118#define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3)
119
120/* Static Memory Output Enable Delay x */
121#define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3)
122
123/* Static Memory Read Delay x */
124#define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3)
125
126/* Static Memory Page Mode Read Delay 0 */
127#define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3)
128
129/* Static Memory Write Delay */
130#define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3)
131
132/* Static Memory Turn Round Delay x */
133#define MEM_SWT(x) __REG2(0xa0700218, (x) << 3)
134
135#endif /* ifndef __ASM_ARCH_REGSMEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
deleted file mode 100644
index 14f91dfd5736..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_REGSSYSCOMMON_H
13#define __ASM_ARCH_REGSSYSCOMMON_H
14#include <mach/hardware.h>
15
16/* Interrupt Vector Address Register Level x */
17#define SYS_IVA(x) __REG2(0xa09000c4, (x))
18
19/* Interrupt Configuration registers */
20#define SYS_IC(x) __REG2(0xa0900144, (x))
21
22/* ISRADDR */
23#define SYS_ISRADDR __REG(0xa0900164)
24
25/* Interrupt Status Active */
26#define SYS_ISA __REG(0xa0900168)
27
28/* Interrupt Status Raw */
29#define SYS_ISR __REG(0xa090016c)
30
31#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
deleted file mode 100644
index 8ff254d9901c..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_REGSSYSNS9360_H
12#define __ASM_ARCH_REGSSYSNS9360_H
13
14#include <mach/hardware.h>
15
16/* System Control Module */
17
18/* AHB Arbiter Gen Configuration */
19#define SYS_AHBAGENCONF __REG(0xa0900000)
20
21/* BRC */
22#define SYS_BRC(x) __REG2(0xa0900004, (x))
23
24/* Timer x Reload Count register */
25#define SYS_TRC(x) __REG2(0xa0900044, (x))
26
27/* Timer x Read register */
28#define SYS_TR(x) __REG2(0xa0900084, (x))
29
30/* Timer Interrupt Status register */
31#define SYS_TIS __REG(0xa0900170)
32
33/* PLL Configuration register */
34#define SYS_PLL __REG(0xa0900188)
35
36/* PLL FS status */
37#define SYS_PLL_FS __REGBITS(24, 23)
38
39/* PLL ND status */
40#define SYS_PLL_ND __REGBITS(20, 16)
41
42/* PLL Configuration register: PLL SW change */
43#define SYS_PLL_SWC __REGBIT(15)
44#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0)
45#define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1)
46
47/* Timer x Control register */
48#define SYS_TC(x) __REG2(0xa0900190, (x))
49
50/* Timer x Control register: Timer enable */
51#define SYS_TCx_TEN __REGBIT(15)
52#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0)
53#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1)
54
55/* Timer x Control register: CPU debug mode */
56#define SYS_TCx_TDBG __REGBIT(10)
57#define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0)
58#define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1)
59
60/* Timer x Control register: Interrupt clear */
61#define SYS_TCx_INTC __REGBIT(9)
62#define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0)
63#define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1)
64
65/* Timer x Control register: Timer clock select */
66#define SYS_TCx_TLCS __REGBITS(8, 6)
67#define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */
68#define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */
69#define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */
70#define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */
71#define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */
72#define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */
73#define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */
74#define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7)
75
76/* Timer x Control register: Timer mode */
77#define SYS_TCx_TM __REGBITS(5, 4)
78#define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */
79#define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */
80#define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */
81#define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */
82
83/* Timer x Control register: Interrupt select */
84#define SYS_TCx_INTS __REGBIT(3)
85#define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0)
86#define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1)
87
88/* Timer x Control register: Up/down select */
89#define SYS_TCx_UDS __REGBIT(2)
90#define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0)
91#define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1)
92
93/* Timer x Control register: 32- or 16-bit timer */
94#define SYS_TCx_TSZ __REGBIT(1)
95#define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0)
96#define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1)
97
98/* Timer x Control register: Reload enable */
99#define SYS_TCx_REN __REGBIT(0)
100#define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0)
101#define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1)
102
103/* System Memory Chip Select x Dynamic Memory Base */
104#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1)
105
106/* System Memory Chip Select x Dynamic Memory Mask */
107#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1)
108
109/* System Memory Chip Select x Static Memory Base */
110#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1)
111
112/* System Memory Chip Select x Static Memory Base: Chip select x base */
113#define SYS_SMCSSMB_CSxB __REGBITS(31, 12)
114
115/* System Memory Chip Select x Static Memory Mask */
116#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1)
117
118/* System Memory Chip Select x Static Memory Mask: Chip select x mask */
119#define SYS_SMCSSMM_CSxM __REGBITS(31, 12)
120
121/* System Memory Chip Select x Static Memory Mask: Chip select x enable */
122#define SYS_SMCSSMM_CSEx __REGBIT(0)
123#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0)
124#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1)
125
126/* General purpose, user-defined ID register */
127#define SYS_GENID __REG(0xa0900210)
128
129/* External Interrupt x Control register */
130#define SYS_EIC(x) __REG2(0xa0900214, (x))
131
132/* External Interrupt x Control register: Status */
133#define SYS_EIC_STS __REGBIT(3)
134
135/* External Interrupt x Control register: Clear */
136#define SYS_EIC_CLR __REGBIT(2)
137
138/* External Interrupt x Control register: Polarity */
139#define SYS_EIC_PLTY __REGBIT(1)
140#define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0)
141#define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1)
142
143/* External Interrupt x Control register: Level edge */
144#define SYS_EIC_LVEDG __REGBIT(0)
145#define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0)
146#define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1)
147
148#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h
deleted file mode 100644
index 1561588ca364..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/system.h
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H
13
14#include <asm/proc-fns.h>
15#include <mach/processor.h>
16#include <mach/processor-ns9360.h>
17
18static inline void arch_idle(void)
19{
20 cpu_do_idle();
21}
22
23static inline void arch_reset(char mode, const char *cmd)
24{
25#ifdef CONFIG_PROCESSOR_NS9360
26 if (processor_is_ns9360())
27 ns9360_reset(mode);
28 else
29#endif
30 BUG();
31
32 BUG();
33}
34
35#endif /* ifndef __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h
deleted file mode 100644
index 734a8d8bd578..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/timex.h
3 *
4 * Copyright (C) 2005-2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_TIMEX_H
12#define __ASM_ARCH_TIMEX_H
13
14/*
15 * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h.
16 * See there for an explanation.
17 */
18#define CLOCK_TICK_RATE 12000000
19
20#endif /* ifndef __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
deleted file mode 100644
index 770a68c46e81..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/uncompress.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_UNCOMPRESS_H
12#define __ASM_ARCH_UNCOMPRESS_H
13
14#include <linux/io.h>
15
16#define __REG(x) ((void __iomem __force *)(x))
17
18static void putc_dummy(char c, void __iomem *base)
19{
20 /* nothing */
21}
22
23static int timeout;
24
25static void putc_ns9360(char c, void __iomem *base)
26{
27 do {
28 if (timeout)
29 --timeout;
30
31 if (__raw_readl(base + 8) & (1 << 3)) {
32 __raw_writeb(c, base + 16);
33 timeout = 0x10000;
34 break;
35 }
36 } while (timeout);
37}
38
39static void putc_a9m9750dev(char c, void __iomem *base)
40{
41 do {
42 if (timeout)
43 --timeout;
44
45 if (__raw_readb(base + 5) & (1 << 5)) {
46 __raw_writeb(c, base);
47 timeout = 0x10000;
48 break;
49 }
50 } while (timeout);
51
52}
53
54static void putc_ns921x(char c, void __iomem *base)
55{
56 do {
57 if (timeout)
58 --timeout;
59
60 if (!(__raw_readl(base) & (1 << 11))) {
61 __raw_writeb(c, base + 0x0028);
62 timeout = 0x10000;
63 break;
64 }
65 } while (timeout);
66}
67
68#define MSCS __REG(0xA0900184)
69
70#define NS9360_UARTA __REG(0x90200040)
71#define NS9360_UARTB __REG(0x90200000)
72#define NS9360_UARTC __REG(0x90300000)
73#define NS9360_UARTD __REG(0x90300040)
74
75#define NS9360_UART_ENABLED(base) \
76 (__raw_readl(NS9360_UARTA) & (1 << 31))
77
78#define A9M9750DEV_UARTA __REG(0x40000000)
79
80#define NS921XSYS_CLOCK __REG(0xa090017c)
81#define NS921X_UARTA __REG(0x90010000)
82#define NS921X_UARTB __REG(0x90018000)
83#define NS921X_UARTC __REG(0x90020000)
84#define NS921X_UARTD __REG(0x90028000)
85
86#define NS921X_UART_ENABLED(base) \
87 (__raw_readl((base) + 0x1000) & (1 << 29))
88
89static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
90{
91 timeout = 0x10000;
92 if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
93 /* ns9360 or ns9750 */
94 if (NS9360_UART_ENABLED(NS9360_UARTA)) {
95 *putc = putc_ns9360;
96 *base = NS9360_UARTA;
97 return;
98 } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
99 *putc = putc_ns9360;
100 *base = NS9360_UARTB;
101 return;
102 } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
103 *putc = putc_ns9360;
104 *base = NS9360_UARTC;
105 return;
106 } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
107 *putc = putc_ns9360;
108 *base = NS9360_UARTD;
109 return;
110 } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
111 *putc = putc_a9m9750dev;
112 *base = A9M9750DEV_UARTA;
113 return;
114 }
115 } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
116 /* ns921x */
117 u32 clock = __raw_readl(NS921XSYS_CLOCK);
118
119 if ((clock & (1 << 1)) &&
120 NS921X_UART_ENABLED(NS921X_UARTA)) {
121 *putc = putc_ns921x;
122 *base = NS921X_UARTA;
123 return;
124 } else if ((clock & (1 << 2)) &&
125 NS921X_UART_ENABLED(NS921X_UARTB)) {
126 *putc = putc_ns921x;
127 *base = NS921X_UARTB;
128 return;
129 } else if ((clock & (1 << 3)) &&
130 NS921X_UART_ENABLED(NS921X_UARTC)) {
131 *putc = putc_ns921x;
132 *base = NS921X_UARTC;
133 return;
134 } else if ((clock & (1 << 4)) &&
135 NS921X_UART_ENABLED(NS921X_UARTD)) {
136 *putc = putc_ns921x;
137 *base = NS921X_UARTD;
138 return;
139 }
140 }
141
142 *putc = putc_dummy;
143}
144
145void (*myputc)(char, void __iomem *);
146void __iomem *base;
147
148static void putc(char c)
149{
150 myputc(c, base);
151}
152
153static void arch_decomp_setup(void)
154{
155 autodetect(&myputc, &base);
156}
157#define arch_decomp_wdog()
158
159static void flush(void)
160{
161 /* nothing */
162}
163
164#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
deleted file mode 100644
index c8651974c4b0..000000000000
--- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#ifndef __ASM_ARCH_VMALLOC_H
12#define __ASM_ARCH_VMALLOC_H
13
14#define VMALLOC_END (0xf0000000UL)
15
16#endif /* ifndef __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
deleted file mode 100644
index 37ab0a2b83ad..000000000000
--- a/arch/arm/mach-ns9xxx/irq.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/irq.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/interrupt.h>
12#include <linux/kernel_stat.h>
13#include <linux/io.h>
14#include <asm/mach/irq.h>
15#include <mach/regs-sys-common.h>
16#include <mach/irqs.h>
17#include <mach/board.h>
18
19#include "generic.h"
20
21/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */
22#define irq2prio(i) (i)
23#define prio2irq(p) (p)
24
25static void ns9xxx_mask_irq(struct irq_data *d)
26{
27 /* XXX: better use cpp symbols */
28 int prio = irq2prio(d->irq);
29 u32 ic = __raw_readl(SYS_IC(prio / 4));
30 ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
31 __raw_writel(ic, SYS_IC(prio / 4));
32}
33
34static void ns9xxx_eoi_irq(struct irq_data *d)
35{
36 __raw_writel(0, SYS_ISRADDR);
37}
38
39static void ns9xxx_unmask_irq(struct irq_data *d)
40{
41 /* XXX: better use cpp symbols */
42 int prio = irq2prio(d->irq);
43 u32 ic = __raw_readl(SYS_IC(prio / 4));
44 ic |= 1 << (7 + 8 * (3 - (prio & 3)));
45 __raw_writel(ic, SYS_IC(prio / 4));
46}
47
48static struct irq_chip ns9xxx_chip = {
49 .irq_eoi = ns9xxx_eoi_irq,
50 .irq_mask = ns9xxx_mask_irq,
51 .irq_unmask = ns9xxx_unmask_irq,
52};
53
54void __init ns9xxx_init_irq(void)
55{
56 int i;
57
58 /* disable all IRQs */
59 for (i = 0; i < 8; ++i)
60 __raw_writel(prio2irq(4 * i) << 24 |
61 prio2irq(4 * i + 1) << 16 |
62 prio2irq(4 * i + 2) << 8 |
63 prio2irq(4 * i + 3),
64 SYS_IC(i));
65
66 for (i = 0; i < 32; ++i)
67 __raw_writel(prio2irq(i), SYS_IVA(i));
68
69 for (i = 0; i <= 31; ++i) {
70 irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
71 set_irq_flags(i, IRQF_VALID);
72 irq_set_status_flags(i, IRQ_LEVEL);
73 }
74}
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
deleted file mode 100644
index 2858417d8d8a..000000000000
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <asm/mach/arch.h>
12#include <asm/mach-types.h>
13
14#include <mach/processor-ns9360.h>
15
16#include "board-a9m9750dev.h"
17#include "generic.h"
18
19static void __init mach_cc9p9360dev_map_io(void)
20{
21 ns9360_map_io();
22 board_a9m9750dev_map_io();
23}
24
25static void __init mach_cc9p9360dev_init_irq(void)
26{
27 ns9xxx_init_irq();
28 board_a9m9750dev_init_irq();
29}
30
31static void __init mach_cc9p9360dev_init_machine(void)
32{
33 ns9xxx_init_machine();
34 board_a9m9750dev_init_machine();
35}
36
37MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard")
38 .map_io = mach_cc9p9360dev_map_io,
39 .init_irq = mach_cc9p9360dev_init_irq,
40 .init_machine = mach_cc9p9360dev_init_machine,
41 .timer = &ns9360_timer,
42 .boot_params = 0x100,
43MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
deleted file mode 100644
index 729f68da4293..000000000000
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/mach-cc9p9360js.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <asm/mach/arch.h>
12#include <asm/mach-types.h>
13
14#include <mach/processor-ns9360.h>
15
16#include "board-jscc9p9360.h"
17#include "generic.h"
18
19static void __init mach_cc9p9360js_init_machine(void)
20{
21 ns9xxx_init_machine();
22 board_jscc9p9360_init_machine();
23}
24
25MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
26 .map_io = ns9360_map_io,
27 .init_irq = ns9xxx_init_irq,
28 .init_machine = mach_cc9p9360js_init_machine,
29 .timer = &ns9360_timer,
30 .boot_params = 0x100,
31MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c
deleted file mode 100644
index 463e92465fda..000000000000
--- a/arch/arm/mach-ns9xxx/plat-serial8250.c
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/plat-serial8250.c
3 *
4 * Copyright (C) 2008 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/platform_device.h>
12#include <linux/serial_8250.h>
13#include <linux/slab.h>
14
15#include <mach/regs-board-a9m9750dev.h>
16#include <mach/board.h>
17
18#define DRIVER_NAME "serial8250"
19
20static int __init ns9xxx_plat_serial8250_init(void)
21{
22 struct plat_serial8250_port *pdata;
23 struct platform_device *pdev;
24 int ret = -ENOMEM;
25 int i;
26
27 if (!board_is_a9m9750dev())
28 return -ENODEV;
29
30 pdev = platform_device_alloc(DRIVER_NAME, 0);
31 if (!pdev)
32 goto err;
33
34 pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL);
35 if (!pdata)
36 goto err;
37
38 pdev->dev.platform_data = pdata;
39
40 pdata[0].iobase = FPGA_UARTA_BASE;
41 pdata[1].iobase = FPGA_UARTB_BASE;
42 pdata[2].iobase = FPGA_UARTC_BASE;
43 pdata[3].iobase = FPGA_UARTD_BASE;
44
45 for (i = 0; i < 4; ++i) {
46 pdata[i].membase = (void __iomem *)pdata[i].iobase;
47 pdata[i].mapbase = pdata[i].iobase;
48 pdata[i].iotype = UPIO_MEM;
49 pdata[i].uartclk = 18432000;
50 pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
51 }
52
53 pdata[0].irq = IRQ_FPGA_UARTA;
54 pdata[1].irq = IRQ_FPGA_UARTB;
55 pdata[2].irq = IRQ_FPGA_UARTC;
56 pdata[3].irq = IRQ_FPGA_UARTD;
57
58 ret = platform_device_add(pdev);
59 if (ret) {
60err:
61 platform_device_put(pdev);
62
63 printk(KERN_WARNING "Could not add %s (errno=%d)\n",
64 DRIVER_NAME, ret);
65 }
66
67 return 0;
68}
69
70arch_initcall(ns9xxx_plat_serial8250_init);
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c
deleted file mode 100644
index aed1999d24fc..000000000000
--- a/arch/arm/mach-ns9xxx/processor-ns9360.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/processor-ns9360.c
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/io.h>
12#include <linux/kernel.h>
13
14#include <asm/page.h>
15#include <asm/mach/map.h>
16#include <mach/processor-ns9360.h>
17#include <mach/regs-sys-ns9360.h>
18
19void ns9360_reset(char mode)
20{
21 u32 reg;
22
23 reg = __raw_readl(SYS_PLL) >> 16;
24 REGSET(reg, SYS_PLL, SWC, YES);
25 __raw_writel(reg, SYS_PLL);
26}
27
28#define CRYSTAL 29491200 /* Hz */
29unsigned long ns9360_systemclock(void)
30{
31 u32 pll = __raw_readl(SYS_PLL);
32 return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
33 >> REGGETIM(pll, SYS_PLL, FS);
34}
35
36static struct map_desc ns9360_io_desc[] __initdata = {
37 { /* BBus */
38 .virtual = io_p2v(0x90000000),
39 .pfn = __phys_to_pfn(0x90000000),
40 .length = 0x00700000,
41 .type = MT_DEVICE,
42 }, { /* AHB */
43 .virtual = io_p2v(0xa0100000),
44 .pfn = __phys_to_pfn(0xa0100000),
45 .length = 0x00900000,
46 .type = MT_DEVICE,
47 },
48};
49
50void __init ns9360_map_io(void)
51{
52 iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc));
53}
diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c
deleted file mode 100644
index 9ca32f55728b..000000000000
--- a/arch/arm/mach-ns9xxx/time-ns9360.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/*
2 * arch/arm/mach-ns9xxx/time-ns9360.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/jiffies.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/stringify.h>
15#include <linux/clocksource.h>
16#include <linux/clockchips.h>
17
18#include <mach/processor-ns9360.h>
19#include <mach/regs-sys-ns9360.h>
20#include <mach/irqs.h>
21#include <mach/system.h>
22#include "generic.h"
23
24#define TIMER_CLOCKSOURCE 0
25#define TIMER_CLOCKEVENT 1
26static u32 latch;
27
28static cycle_t ns9360_clocksource_read(struct clocksource *cs)
29{
30 return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
31}
32
33static struct clocksource ns9360_clocksource = {
34 .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE),
35 .rating = 300,
36 .read = ns9360_clocksource_read,
37 .mask = CLOCKSOURCE_MASK(32),
38 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
39};
40
41static void ns9360_clockevent_setmode(enum clock_event_mode mode,
42 struct clock_event_device *clk)
43{
44 u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
45
46 switch (mode) {
47 case CLOCK_EVT_MODE_PERIODIC:
48 __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
49 REGSET(tc, SYS_TCx, REN, EN);
50 REGSET(tc, SYS_TCx, INTS, EN);
51 REGSET(tc, SYS_TCx, TEN, EN);
52 break;
53
54 case CLOCK_EVT_MODE_ONESHOT:
55 REGSET(tc, SYS_TCx, REN, DIS);
56 REGSET(tc, SYS_TCx, INTS, EN);
57
58 /* fall through */
59
60 case CLOCK_EVT_MODE_UNUSED:
61 case CLOCK_EVT_MODE_SHUTDOWN:
62 case CLOCK_EVT_MODE_RESUME:
63 default:
64 REGSET(tc, SYS_TCx, TEN, DIS);
65 break;
66 }
67
68 __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
69}
70
71static int ns9360_clockevent_setnextevent(unsigned long evt,
72 struct clock_event_device *clk)
73{
74 u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
75
76 if (REGGET(tc, SYS_TCx, TEN)) {
77 REGSET(tc, SYS_TCx, TEN, DIS);
78 __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
79 }
80
81 REGSET(tc, SYS_TCx, TEN, EN);
82
83 __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT));
84
85 __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
86
87 return 0;
88}
89
90static struct clock_event_device ns9360_clockevent_device = {
91 .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
92 .shift = 20,
93 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
94 .set_mode = ns9360_clockevent_setmode,
95 .set_next_event = ns9360_clockevent_setnextevent,
96};
97
98static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id)
99{
100 int timerno = irq - IRQ_NS9360_TIMER0;
101 u32 tc;
102
103 struct clock_event_device *evt = &ns9360_clockevent_device;
104
105 /* clear irq */
106 tc = __raw_readl(SYS_TC(timerno));
107 if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) {
108 REGSET(tc, SYS_TCx, TEN, DIS);
109 __raw_writel(tc, SYS_TC(timerno));
110 }
111 REGSET(tc, SYS_TCx, INTC, SET);
112 __raw_writel(tc, SYS_TC(timerno));
113 REGSET(tc, SYS_TCx, INTC, UNSET);
114 __raw_writel(tc, SYS_TC(timerno));
115
116 evt->event_handler(evt);
117
118 return IRQ_HANDLED;
119}
120
121static struct irqaction ns9360_clockevent_action = {
122 .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
123 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
124 .handler = ns9360_clockevent_handler,
125};
126
127static void __init ns9360_timer_init(void)
128{
129 int tc;
130
131 tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE));
132 if (REGGET(tc, SYS_TCx, TEN)) {
133 REGSET(tc, SYS_TCx, TEN, DIS);
134 __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
135 }
136
137 __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE));
138
139 REGSET(tc, SYS_TCx, TEN, EN);
140 REGSET(tc, SYS_TCx, TDBG, STOP);
141 REGSET(tc, SYS_TCx, TLCS, CPU);
142 REGSET(tc, SYS_TCx, TM, IEE);
143 REGSET(tc, SYS_TCx, INTS, DIS);
144 REGSET(tc, SYS_TCx, UDS, UP);
145 REGSET(tc, SYS_TCx, TSZ, 32);
146 REGSET(tc, SYS_TCx, REN, EN);
147
148 __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
149
150 clocksource_register_hz(&ns9360_clocksource, ns9360_cpuclock());
151
152 latch = SH_DIV(ns9360_cpuclock(), HZ, 0);
153
154 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
155 REGSET(tc, SYS_TCx, TEN, DIS);
156 REGSET(tc, SYS_TCx, TDBG, STOP);
157 REGSET(tc, SYS_TCx, TLCS, CPU);
158 REGSET(tc, SYS_TCx, TM, IEE);
159 REGSET(tc, SYS_TCx, INTS, DIS);
160 REGSET(tc, SYS_TCx, UDS, DOWN);
161 REGSET(tc, SYS_TCx, TSZ, 32);
162 REGSET(tc, SYS_TCx, REN, EN);
163 __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
164
165 ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(),
166 NSEC_PER_SEC, ns9360_clockevent_device.shift);
167 ns9360_clockevent_device.max_delta_ns =
168 clockevent_delta2ns(-1, &ns9360_clockevent_device);
169 ns9360_clockevent_device.min_delta_ns =
170 clockevent_delta2ns(1, &ns9360_clockevent_device);
171
172 ns9360_clockevent_device.cpumask = cpumask_of(0);
173 clockevents_register_device(&ns9360_clockevent_device);
174
175 setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT,
176 &ns9360_clockevent_action);
177}
178
179struct sys_timer ns9360_timer = {
180 .init = ns9360_timer_init,
181};
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
index 73082cd61e84..381cb9baadd5 100644
--- a/arch/arm/mach-nuc93x/include/mach/uncompress.h
+++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h
@@ -27,7 +27,7 @@
27#define arch_decomp_wdog() 27#define arch_decomp_wdog()
28 28
29#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) 29#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
30static u32 * uart_base = (u32 *)UART0_PA; 30static u32 * const uart_base = (u32 *)UART0_PA;
31 31
32static void putc(int ch) 32static void putc(int ch)
33{ 33{
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index acd161666408..1749cb37dda0 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -13,7 +13,7 @@
13#include <plat/tc.h> 13#include <plat/tc.h>
14#include <plat/flash.h> 14#include <plat/flash.h>
15 15
16void omap1_set_vpp(struct map_info *map, int enable) 16void omap1_set_vpp(struct platform_device *pdev, int enable)
17{ 17{
18 static int count; 18 static int count;
19 u32 l; 19 u32 l;
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 6885d2fac183..03e1e1062ad4 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -68,49 +68,50 @@ typedef struct {
68} omap_mpu_timer_regs_t; 68} omap_mpu_timer_regs_t;
69 69
70#define omap_mpu_timer_base(n) \ 70#define omap_mpu_timer_base(n) \
71((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ 71((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
72 (n)*OMAP_MPU_TIMER_OFFSET)) 72 (n)*OMAP_MPU_TIMER_OFFSET))
73 73
74static inline unsigned long notrace omap_mpu_timer_read(int nr) 74static inline unsigned long notrace omap_mpu_timer_read(int nr)
75{ 75{
76 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 76 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
77 return timer->read_tim; 77 return readl(&timer->read_tim);
78} 78}
79 79
80static inline void omap_mpu_set_autoreset(int nr) 80static inline void omap_mpu_set_autoreset(int nr)
81{ 81{
82 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 82 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
83 83
84 timer->cntl = timer->cntl | MPU_TIMER_AR; 84 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
85} 85}
86 86
87static inline void omap_mpu_remove_autoreset(int nr) 87static inline void omap_mpu_remove_autoreset(int nr)
88{ 88{
89 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 89 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
90 90
91 timer->cntl = timer->cntl & ~MPU_TIMER_AR; 91 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
92} 92}
93 93
94static inline void omap_mpu_timer_start(int nr, unsigned long load_val, 94static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
95 int autoreset) 95 int autoreset)
96{ 96{
97 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 97 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
98 unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST); 98 unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
99 99
100 if (autoreset) timerflags |= MPU_TIMER_AR; 100 if (autoreset)
101 timerflags |= MPU_TIMER_AR;
101 102
102 timer->cntl = MPU_TIMER_CLOCK_ENABLE; 103 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
103 udelay(1); 104 udelay(1);
104 timer->load_tim = load_val; 105 writel(load_val, &timer->load_tim);
105 udelay(1); 106 udelay(1);
106 timer->cntl = timerflags; 107 writel(timerflags, &timer->cntl);
107} 108}
108 109
109static inline void omap_mpu_timer_stop(int nr) 110static inline void omap_mpu_timer_stop(int nr)
110{ 111{
111 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 112 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
112 113
113 timer->cntl &= ~MPU_TIMER_ST; 114 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
114} 115}
115 116
116/* 117/*
@@ -189,38 +190,11 @@ static __init void omap_init_mpu_timer(unsigned long rate)
189 * --------------------------------------------------------------------------- 190 * ---------------------------------------------------------------------------
190 */ 191 */
191 192
192static unsigned long omap_mpu_timer2_overflows;
193
194static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
195{
196 omap_mpu_timer2_overflows++;
197 return IRQ_HANDLED;
198}
199
200static struct irqaction omap_mpu_timer2_irq = {
201 .name = "mpu_timer2",
202 .flags = IRQF_DISABLED,
203 .handler = omap_mpu_timer2_interrupt,
204};
205
206static cycle_t mpu_read(struct clocksource *cs)
207{
208 return ~omap_mpu_timer_read(1);
209}
210
211static struct clocksource clocksource_mpu = {
212 .name = "mpu_timer2",
213 .rating = 300,
214 .read = mpu_read,
215 .mask = CLOCKSOURCE_MASK(32),
216 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
217};
218
219static DEFINE_CLOCK_DATA(cd); 193static DEFINE_CLOCK_DATA(cd);
220 194
221static inline unsigned long long notrace _omap_mpu_sched_clock(void) 195static inline unsigned long long notrace _omap_mpu_sched_clock(void)
222{ 196{
223 u32 cyc = mpu_read(&clocksource_mpu); 197 u32 cyc = ~omap_mpu_timer_read(1);
224 return cyc_to_sched_clock(&cd, cyc, (u32)~0); 198 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
225} 199}
226 200
@@ -238,21 +212,22 @@ static unsigned long long notrace omap_mpu_sched_clock(void)
238 212
239static void notrace mpu_update_sched_clock(void) 213static void notrace mpu_update_sched_clock(void)
240{ 214{
241 u32 cyc = mpu_read(&clocksource_mpu); 215 u32 cyc = ~omap_mpu_timer_read(1);
242 update_sched_clock(&cd, cyc, (u32)~0); 216 update_sched_clock(&cd, cyc, (u32)~0);
243} 217}
244 218
245static void __init omap_init_clocksource(unsigned long rate) 219static void __init omap_init_clocksource(unsigned long rate)
246{ 220{
221 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
247 static char err[] __initdata = KERN_ERR 222 static char err[] __initdata = KERN_ERR
248 "%s: can't register clocksource!\n"; 223 "%s: can't register clocksource!\n";
249 224
250 setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
251 omap_mpu_timer_start(1, ~0, 1); 225 omap_mpu_timer_start(1, ~0, 1);
252 init_sched_clock(&cd, mpu_update_sched_clock, 32, rate); 226 init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);
253 227
254 if (clocksource_register_hz(&clocksource_mpu, rate)) 228 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
255 printk(err, clocksource_mpu.name); 229 300, 32, clocksource_mmio_readl_down))
230 printk(err, "mpu_timer2");
256} 231}
257 232
258static void __init omap_mpu_timer_init(void) 233static void __init omap_mpu_timer_init(void)
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index de441c05a6a6..e4bd87619734 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -33,4 +33,11 @@ extern void __iomem *gic_dist_base_addr;
33extern void __init gic_init_irq(void); 33extern void __init gic_init_irq(void);
34extern void omap_smc1(u32 fn, u32 arg); 34extern void omap_smc1(u32 fn, u32 arg);
35 35
36#ifdef CONFIG_SMP
37/* Needed for secondary core boot */
38extern void omap_secondary_startup(void);
39extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
40extern void omap_auxcoreboot_addr(u32 cpu_addr);
41extern u32 omap_read_auxcoreboot0(void);
42#endif
36#endif 43#endif
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 237e4530abf2..3af2b7a1045e 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -73,83 +73,18 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
73 return __raw_readl(bank->base_reg + reg); 73 return __raw_readl(bank->base_reg + reg);
74} 74}
75 75
76static int previous_irq;
77
78/*
79 * On 34xx we can get occasional spurious interrupts if the ack from
80 * an interrupt handler does not get posted before we unmask. Warn about
81 * the interrupt handlers that need to flush posted writes.
82 */
83static int omap_check_spurious(unsigned int irq)
84{
85 u32 sir, spurious;
86
87 sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
88 spurious = sir >> 7;
89
90 if (spurious) {
91 printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
92 "posted write for irq %i\n",
93 irq, sir, previous_irq);
94 return spurious;
95 }
96
97 return 0;
98}
99
100/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 76/* XXX: FIQ and additional INTC support (only MPU at the moment) */
101static void omap_ack_irq(struct irq_data *d) 77static void omap_ack_irq(struct irq_data *d)
102{ 78{
103 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); 79 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
104} 80}
105 81
106static void omap_mask_irq(struct irq_data *d)
107{
108 unsigned int irq = d->irq;
109 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
110
111 if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
112 int spurious = 0;
113
114 /*
115 * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
116 * it is the highest irq number?
117 */
118 if (irq == INT_34XX_GPT12_IRQ)
119 spurious = omap_check_spurious(irq);
120
121 if (!spurious)
122 previous_irq = irq;
123 }
124
125 irq &= (IRQ_BITS_PER_REG - 1);
126
127 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
128}
129
130static void omap_unmask_irq(struct irq_data *d)
131{
132 unsigned int irq = d->irq;
133 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
134
135 irq &= (IRQ_BITS_PER_REG - 1);
136
137 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
138}
139
140static void omap_mask_ack_irq(struct irq_data *d) 82static void omap_mask_ack_irq(struct irq_data *d)
141{ 83{
142 omap_mask_irq(d); 84 irq_gc_mask_disable_reg(d);
143 omap_ack_irq(d); 85 omap_ack_irq(d);
144} 86}
145 87
146static struct irq_chip omap_irq_chip = {
147 .name = "INTC",
148 .irq_ack = omap_mask_ack_irq,
149 .irq_mask = omap_mask_irq,
150 .irq_unmask = omap_unmask_irq,
151};
152
153static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) 88static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
154{ 89{
155 unsigned long tmp; 90 unsigned long tmp;
@@ -186,11 +121,31 @@ int omap_irq_pending(void)
186 return 0; 121 return 0;
187} 122}
188 123
124static __init void
125omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
126{
127 struct irq_chip_generic *gc;
128 struct irq_chip_type *ct;
129
130 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
131 handle_level_irq);
132 ct = gc->chip_types;
133 ct->chip.irq_ack = omap_mask_ack_irq;
134 ct->chip.irq_mask = irq_gc_mask_disable_reg;
135 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
136
137 ct->regs.ack = INTC_CONTROL;
138 ct->regs.enable = INTC_MIR_CLEAR0;
139 ct->regs.disable = INTC_MIR_SET0;
140 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
141 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
142}
143
189void __init omap_init_irq(void) 144void __init omap_init_irq(void)
190{ 145{
191 unsigned long nr_of_irqs = 0; 146 unsigned long nr_of_irqs = 0;
192 unsigned int nr_banks = 0; 147 unsigned int nr_banks = 0;
193 int i; 148 int i, j;
194 149
195 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 150 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
196 unsigned long base = 0; 151 unsigned long base = 0;
@@ -215,17 +170,15 @@ void __init omap_init_irq(void)
215 170
216 omap_irq_bank_init_one(bank); 171 omap_irq_bank_init_one(bank);
217 172
173 for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
174 omap_alloc_gc(bank->base_reg + j, i, 32);
175
218 nr_of_irqs += bank->nr_irqs; 176 nr_of_irqs += bank->nr_irqs;
219 nr_banks++; 177 nr_banks++;
220 } 178 }
221 179
222 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n", 180 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
223 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); 181 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
224
225 for (i = 0; i < nr_of_irqs; i++) {
226 irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
227 set_irq_flags(i, IRQF_VALID);
228 }
229} 182}
230 183
231#ifdef CONFIG_ARCH_OMAP3 184#ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index b66cfe8bc464..ecfe93c4b585 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <asm/cacheflush.h> 23#include <asm/cacheflush.h>
24#include <asm/hardware/gic.h>
24#include <asm/smp_scu.h> 25#include <asm/smp_scu.h>
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <mach/omap4-common.h> 27#include <mach/omap4-common.h>
@@ -63,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
63 omap_modify_auxcoreboot0(0x200, 0xfffffdff); 64 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
64 flush_cache_all(); 65 flush_cache_all();
65 smp_wmb(); 66 smp_wmb();
66 smp_cross_call(cpumask_of(cpu), 1); 67 gic_raise_softirq(cpumask_of(cpu), 1);
67 68
68 /* 69 /*
69 * Now the secondary core is starting up let it run its 70 * Now the secondary core is starting up let it run its
@@ -118,6 +119,8 @@ void __init smp_init_cpus(void)
118 119
119 for (i = 0; i < ncores; i++) 120 for (i = 0; i < ncores; i++)
120 set_cpu_possible(i, true); 121 set_cpu_possible(i, true);
122
123 set_smp_cross_call(gic_raise_softirq);
121} 124}
122 125
123void __init platform_smp_prepare_cpus(unsigned int max_cpus) 126void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 986c3bf4e6b8..0ab531d047fc 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -13,12 +13,11 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
16#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
17#include <linux/mbus.h> 18#include <linux/mbus.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/mv643xx_i2c.h> 19#include <linux/mv643xx_i2c.h>
20#include <linux/ata_platform.h> 20#include <linux/ata_platform.h>
21#include <linux/spi/orion_spi.h>
22#include <net/dsa.h> 21#include <net/dsa.h>
23#include <asm/page.h> 22#include <asm/page.h>
24#include <asm/setup.h> 23#include <asm/setup.h>
@@ -29,11 +28,9 @@
29#include <mach/bridge-regs.h> 28#include <mach/bridge-regs.h>
30#include <mach/hardware.h> 29#include <mach/hardware.h>
31#include <mach/orion5x.h> 30#include <mach/orion5x.h>
32#include <plat/ehci-orion.h>
33#include <plat/mv_xor.h>
34#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
35#include <plat/orion_wdt.h>
36#include <plat/time.h> 32#include <plat/time.h>
33#include <plat/common.h>
37#include "common.h" 34#include "common.h"
38 35
39/***************************************************************************** 36/*****************************************************************************
@@ -70,530 +67,124 @@ void __init orion5x_map_io(void)
70 67
71 68
72/***************************************************************************** 69/*****************************************************************************
73 * EHCI
74 ****************************************************************************/
75static struct orion_ehci_data orion5x_ehci_data = {
76 .dram = &orion5x_mbus_dram_info,
77 .phy_version = EHCI_PHY_ORION,
78};
79
80static u64 ehci_dmamask = 0xffffffffUL;
81
82
83/*****************************************************************************
84 * EHCI0 70 * EHCI0
85 ****************************************************************************/ 71 ****************************************************************************/
86static struct resource orion5x_ehci0_resources[] = {
87 {
88 .start = ORION5X_USB0_PHYS_BASE,
89 .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
90 .flags = IORESOURCE_MEM,
91 }, {
92 .start = IRQ_ORION5X_USB0_CTRL,
93 .end = IRQ_ORION5X_USB0_CTRL,
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static struct platform_device orion5x_ehci0 = {
99 .name = "orion-ehci",
100 .id = 0,
101 .dev = {
102 .dma_mask = &ehci_dmamask,
103 .coherent_dma_mask = 0xffffffff,
104 .platform_data = &orion5x_ehci_data,
105 },
106 .resource = orion5x_ehci0_resources,
107 .num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
108};
109
110void __init orion5x_ehci0_init(void) 72void __init orion5x_ehci0_init(void)
111{ 73{
112 platform_device_register(&orion5x_ehci0); 74 orion_ehci_init(&orion5x_mbus_dram_info,
75 ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
113} 76}
114 77
115 78
116/***************************************************************************** 79/*****************************************************************************
117 * EHCI1 80 * EHCI1
118 ****************************************************************************/ 81 ****************************************************************************/
119static struct resource orion5x_ehci1_resources[] = {
120 {
121 .start = ORION5X_USB1_PHYS_BASE,
122 .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
123 .flags = IORESOURCE_MEM,
124 }, {
125 .start = IRQ_ORION5X_USB1_CTRL,
126 .end = IRQ_ORION5X_USB1_CTRL,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct platform_device orion5x_ehci1 = {
132 .name = "orion-ehci",
133 .id = 1,
134 .dev = {
135 .dma_mask = &ehci_dmamask,
136 .coherent_dma_mask = 0xffffffff,
137 .platform_data = &orion5x_ehci_data,
138 },
139 .resource = orion5x_ehci1_resources,
140 .num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
141};
142
143void __init orion5x_ehci1_init(void) 82void __init orion5x_ehci1_init(void)
144{ 83{
145 platform_device_register(&orion5x_ehci1); 84 orion_ehci_1_init(&orion5x_mbus_dram_info,
85 ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
146} 86}
147 87
148 88
149/***************************************************************************** 89/*****************************************************************************
150 * GigE 90 * GE00
151 ****************************************************************************/ 91 ****************************************************************************/
152struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
153 .dram = &orion5x_mbus_dram_info,
154};
155
156static struct resource orion5x_eth_shared_resources[] = {
157 {
158 .start = ORION5X_ETH_PHYS_BASE + 0x2000,
159 .end = ORION5X_ETH_PHYS_BASE + 0x3fff,
160 .flags = IORESOURCE_MEM,
161 }, {
162 .start = IRQ_ORION5X_ETH_ERR,
163 .end = IRQ_ORION5X_ETH_ERR,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device orion5x_eth_shared = {
169 .name = MV643XX_ETH_SHARED_NAME,
170 .id = 0,
171 .dev = {
172 .platform_data = &orion5x_eth_shared_data,
173 },
174 .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
175 .resource = orion5x_eth_shared_resources,
176};
177
178static struct resource orion5x_eth_resources[] = {
179 {
180 .name = "eth irq",
181 .start = IRQ_ORION5X_ETH_SUM,
182 .end = IRQ_ORION5X_ETH_SUM,
183 .flags = IORESOURCE_IRQ,
184 },
185};
186
187static struct platform_device orion5x_eth = {
188 .name = MV643XX_ETH_NAME,
189 .id = 0,
190 .num_resources = 1,
191 .resource = orion5x_eth_resources,
192 .dev = {
193 .coherent_dma_mask = 0xffffffff,
194 },
195};
196
197void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 92void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
198{ 93{
199 eth_data->shared = &orion5x_eth_shared; 94 orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
200 orion5x_eth.dev.platform_data = eth_data; 95 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
201 96 IRQ_ORION5X_ETH_ERR, orion5x_tclk);
202 platform_device_register(&orion5x_eth_shared);
203 platform_device_register(&orion5x_eth);
204} 97}
205 98
206 99
207/***************************************************************************** 100/*****************************************************************************
208 * Ethernet switch 101 * Ethernet switch
209 ****************************************************************************/ 102 ****************************************************************************/
210static struct resource orion5x_switch_resources[] = {
211 {
212 .start = 0,
213 .end = 0,
214 .flags = IORESOURCE_IRQ,
215 },
216};
217
218static struct platform_device orion5x_switch_device = {
219 .name = "dsa",
220 .id = 0,
221 .num_resources = 0,
222 .resource = orion5x_switch_resources,
223};
224
225void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) 103void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
226{ 104{
227 int i; 105 orion_ge00_switch_init(d, irq);
228
229 if (irq != NO_IRQ) {
230 orion5x_switch_resources[0].start = irq;
231 orion5x_switch_resources[0].end = irq;
232 orion5x_switch_device.num_resources = 1;
233 }
234
235 d->netdev = &orion5x_eth.dev;
236 for (i = 0; i < d->nr_chips; i++)
237 d->chip[i].mii_bus = &orion5x_eth_shared.dev;
238 orion5x_switch_device.dev.platform_data = d;
239
240 platform_device_register(&orion5x_switch_device);
241} 106}
242 107
243 108
244/***************************************************************************** 109/*****************************************************************************
245 * I2C 110 * I2C
246 ****************************************************************************/ 111 ****************************************************************************/
247static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
248 .freq_m = 8, /* assumes 166 MHz TCLK */
249 .freq_n = 3,
250 .timeout = 1000, /* Default timeout of 1 second */
251};
252
253static struct resource orion5x_i2c_resources[] = {
254 {
255 .start = I2C_PHYS_BASE,
256 .end = I2C_PHYS_BASE + 0x1f,
257 .flags = IORESOURCE_MEM,
258 }, {
259 .start = IRQ_ORION5X_I2C,
260 .end = IRQ_ORION5X_I2C,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device orion5x_i2c = {
266 .name = MV64XXX_I2C_CTLR_NAME,
267 .id = 0,
268 .num_resources = ARRAY_SIZE(orion5x_i2c_resources),
269 .resource = orion5x_i2c_resources,
270 .dev = {
271 .platform_data = &orion5x_i2c_pdata,
272 },
273};
274
275void __init orion5x_i2c_init(void) 112void __init orion5x_i2c_init(void)
276{ 113{
277 platform_device_register(&orion5x_i2c); 114 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
115
278} 116}
279 117
280 118
281/***************************************************************************** 119/*****************************************************************************
282 * SATA 120 * SATA
283 ****************************************************************************/ 121 ****************************************************************************/
284static struct resource orion5x_sata_resources[] = {
285 {
286 .name = "sata base",
287 .start = ORION5X_SATA_PHYS_BASE,
288 .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
289 .flags = IORESOURCE_MEM,
290 }, {
291 .name = "sata irq",
292 .start = IRQ_ORION5X_SATA,
293 .end = IRQ_ORION5X_SATA,
294 .flags = IORESOURCE_IRQ,
295 },
296};
297
298static struct platform_device orion5x_sata = {
299 .name = "sata_mv",
300 .id = 0,
301 .dev = {
302 .coherent_dma_mask = 0xffffffff,
303 },
304 .num_resources = ARRAY_SIZE(orion5x_sata_resources),
305 .resource = orion5x_sata_resources,
306};
307
308void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 122void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
309{ 123{
310 sata_data->dram = &orion5x_mbus_dram_info; 124 orion_sata_init(sata_data, &orion5x_mbus_dram_info,
311 orion5x_sata.dev.platform_data = sata_data; 125 ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
312 platform_device_register(&orion5x_sata);
313} 126}
314 127
315 128
316/***************************************************************************** 129/*****************************************************************************
317 * SPI 130 * SPI
318 ****************************************************************************/ 131 ****************************************************************************/
319static struct orion_spi_info orion5x_spi_plat_data = {
320 .tclk = 0,
321 .enable_clock_fix = 1,
322};
323
324static struct resource orion5x_spi_resources[] = {
325 {
326 .name = "spi base",
327 .start = SPI_PHYS_BASE,
328 .end = SPI_PHYS_BASE + 0x1f,
329 .flags = IORESOURCE_MEM,
330 },
331};
332
333static struct platform_device orion5x_spi = {
334 .name = "orion_spi",
335 .id = 0,
336 .dev = {
337 .platform_data = &orion5x_spi_plat_data,
338 },
339 .num_resources = ARRAY_SIZE(orion5x_spi_resources),
340 .resource = orion5x_spi_resources,
341};
342
343void __init orion5x_spi_init() 132void __init orion5x_spi_init()
344{ 133{
345 platform_device_register(&orion5x_spi); 134 orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
346} 135}
347 136
348 137
349/***************************************************************************** 138/*****************************************************************************
350 * UART0 139 * UART0
351 ****************************************************************************/ 140 ****************************************************************************/
352static struct plat_serial8250_port orion5x_uart0_data[] = {
353 {
354 .mapbase = UART0_PHYS_BASE,
355 .membase = (char *)UART0_VIRT_BASE,
356 .irq = IRQ_ORION5X_UART0,
357 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
358 .iotype = UPIO_MEM,
359 .regshift = 2,
360 .uartclk = 0,
361 }, {
362 },
363};
364
365static struct resource orion5x_uart0_resources[] = {
366 {
367 .start = UART0_PHYS_BASE,
368 .end = UART0_PHYS_BASE + 0xff,
369 .flags = IORESOURCE_MEM,
370 }, {
371 .start = IRQ_ORION5X_UART0,
372 .end = IRQ_ORION5X_UART0,
373 .flags = IORESOURCE_IRQ,
374 },
375};
376
377static struct platform_device orion5x_uart0 = {
378 .name = "serial8250",
379 .id = PLAT8250_DEV_PLATFORM,
380 .dev = {
381 .platform_data = orion5x_uart0_data,
382 },
383 .resource = orion5x_uart0_resources,
384 .num_resources = ARRAY_SIZE(orion5x_uart0_resources),
385};
386
387void __init orion5x_uart0_init(void) 141void __init orion5x_uart0_init(void)
388{ 142{
389 platform_device_register(&orion5x_uart0); 143 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
144 IRQ_ORION5X_UART0, orion5x_tclk);
390} 145}
391 146
392
393/***************************************************************************** 147/*****************************************************************************
394 * UART1 148 * UART1
395 ****************************************************************************/ 149 ****************************************************************************/
396static struct plat_serial8250_port orion5x_uart1_data[] = {
397 {
398 .mapbase = UART1_PHYS_BASE,
399 .membase = (char *)UART1_VIRT_BASE,
400 .irq = IRQ_ORION5X_UART1,
401 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
402 .iotype = UPIO_MEM,
403 .regshift = 2,
404 .uartclk = 0,
405 }, {
406 },
407};
408
409static struct resource orion5x_uart1_resources[] = {
410 {
411 .start = UART1_PHYS_BASE,
412 .end = UART1_PHYS_BASE + 0xff,
413 .flags = IORESOURCE_MEM,
414 }, {
415 .start = IRQ_ORION5X_UART1,
416 .end = IRQ_ORION5X_UART1,
417 .flags = IORESOURCE_IRQ,
418 },
419};
420
421static struct platform_device orion5x_uart1 = {
422 .name = "serial8250",
423 .id = PLAT8250_DEV_PLATFORM1,
424 .dev = {
425 .platform_data = orion5x_uart1_data,
426 },
427 .resource = orion5x_uart1_resources,
428 .num_resources = ARRAY_SIZE(orion5x_uart1_resources),
429};
430
431void __init orion5x_uart1_init(void) 150void __init orion5x_uart1_init(void)
432{ 151{
433 platform_device_register(&orion5x_uart1); 152 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
153 IRQ_ORION5X_UART1, orion5x_tclk);
434} 154}
435 155
436
437/***************************************************************************** 156/*****************************************************************************
438 * XOR engine 157 * XOR engine
439 ****************************************************************************/ 158 ****************************************************************************/
440struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
441 .dram = &orion5x_mbus_dram_info,
442};
443
444static struct resource orion5x_xor_shared_resources[] = {
445 {
446 .name = "xor low",
447 .start = ORION5X_XOR_PHYS_BASE,
448 .end = ORION5X_XOR_PHYS_BASE + 0xff,
449 .flags = IORESOURCE_MEM,
450 }, {
451 .name = "xor high",
452 .start = ORION5X_XOR_PHYS_BASE + 0x200,
453 .end = ORION5X_XOR_PHYS_BASE + 0x2ff,
454 .flags = IORESOURCE_MEM,
455 },
456};
457
458static struct platform_device orion5x_xor_shared = {
459 .name = MV_XOR_SHARED_NAME,
460 .id = 0,
461 .dev = {
462 .platform_data = &orion5x_xor_shared_data,
463 },
464 .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
465 .resource = orion5x_xor_shared_resources,
466};
467
468static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
469
470static struct resource orion5x_xor0_resources[] = {
471 [0] = {
472 .start = IRQ_ORION5X_XOR0,
473 .end = IRQ_ORION5X_XOR0,
474 .flags = IORESOURCE_IRQ,
475 },
476};
477
478static struct mv_xor_platform_data orion5x_xor0_data = {
479 .shared = &orion5x_xor_shared,
480 .hw_id = 0,
481 .pool_size = PAGE_SIZE,
482};
483
484static struct platform_device orion5x_xor0_channel = {
485 .name = MV_XOR_NAME,
486 .id = 0,
487 .num_resources = ARRAY_SIZE(orion5x_xor0_resources),
488 .resource = orion5x_xor0_resources,
489 .dev = {
490 .dma_mask = &orion5x_xor_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(64),
492 .platform_data = &orion5x_xor0_data,
493 },
494};
495
496static struct resource orion5x_xor1_resources[] = {
497 [0] = {
498 .start = IRQ_ORION5X_XOR1,
499 .end = IRQ_ORION5X_XOR1,
500 .flags = IORESOURCE_IRQ,
501 },
502};
503
504static struct mv_xor_platform_data orion5x_xor1_data = {
505 .shared = &orion5x_xor_shared,
506 .hw_id = 1,
507 .pool_size = PAGE_SIZE,
508};
509
510static struct platform_device orion5x_xor1_channel = {
511 .name = MV_XOR_NAME,
512 .id = 1,
513 .num_resources = ARRAY_SIZE(orion5x_xor1_resources),
514 .resource = orion5x_xor1_resources,
515 .dev = {
516 .dma_mask = &orion5x_xor_dmamask,
517 .coherent_dma_mask = DMA_BIT_MASK(64),
518 .platform_data = &orion5x_xor1_data,
519 },
520};
521
522void __init orion5x_xor_init(void) 159void __init orion5x_xor_init(void)
523{ 160{
524 platform_device_register(&orion5x_xor_shared); 161 orion_xor0_init(&orion5x_mbus_dram_info,
525 162 ORION5X_XOR_PHYS_BASE,
526 /* 163 ORION5X_XOR_PHYS_BASE + 0x200,
527 * two engines can't do memset simultaneously, this limitation 164 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
528 * satisfied by removing memset support from one of the engines.
529 */
530 dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
531 dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
532 platform_device_register(&orion5x_xor0_channel);
533
534 dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
535 dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
536 dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
537 platform_device_register(&orion5x_xor1_channel);
538} 165}
539 166
540static struct resource orion5x_crypto_res[] = { 167/*****************************************************************************
541 { 168 * Cryptographic Engines and Security Accelerator (CESA)
542 .name = "regs", 169 ****************************************************************************/
543 .start = ORION5X_CRYPTO_PHYS_BASE, 170static void __init orion5x_crypto_init(void)
544 .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
545 .flags = IORESOURCE_MEM,
546 }, {
547 .name = "sram",
548 .start = ORION5X_SRAM_PHYS_BASE,
549 .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
550 .flags = IORESOURCE_MEM,
551 }, {
552 .name = "crypto interrupt",
553 .start = IRQ_ORION5X_CESA,
554 .end = IRQ_ORION5X_CESA,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559static struct platform_device orion5x_crypto_device = {
560 .name = "mv_crypto",
561 .id = -1,
562 .num_resources = ARRAY_SIZE(orion5x_crypto_res),
563 .resource = orion5x_crypto_res,
564};
565
566static int __init orion5x_crypto_init(void)
567{ 171{
568 int ret; 172 int ret;
569 173
570 ret = orion5x_setup_sram_win(); 174 ret = orion5x_setup_sram_win();
571 if (ret) 175 if (ret)
572 return ret; 176 return;
573 177
574 return platform_device_register(&orion5x_crypto_device); 178 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
179 SZ_8K, IRQ_ORION5X_CESA);
575} 180}
576 181
577/***************************************************************************** 182/*****************************************************************************
578 * Watchdog 183 * Watchdog
579 ****************************************************************************/ 184 ****************************************************************************/
580static struct orion_wdt_platform_data orion5x_wdt_data = {
581 .tclk = 0,
582};
583
584static struct platform_device orion5x_wdt_device = {
585 .name = "orion_wdt",
586 .id = -1,
587 .dev = {
588 .platform_data = &orion5x_wdt_data,
589 },
590 .num_resources = 0,
591};
592
593void __init orion5x_wdt_init(void) 185void __init orion5x_wdt_init(void)
594{ 186{
595 orion5x_wdt_data.tclk = orion5x_tclk; 187 orion_wdt_init(orion5x_tclk);
596 platform_device_register(&orion5x_wdt_device);
597} 188}
598 189
599 190
@@ -685,11 +276,6 @@ void __init orion5x_init(void)
685 orion5x_id(&dev, &rev, &dev_name); 276 orion5x_id(&dev, &rev, &dev_name);
686 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); 277 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
687 278
688 orion5x_eth_shared_data.t_clk = orion5x_tclk;
689 orion5x_spi_plat_data.tclk = orion5x_tclk;
690 orion5x_uart0_data[0].uartclk = orion5x_tclk;
691 orion5x_uart1_data[0].uartclk = orion5x_tclk;
692
693 /* 279 /*
694 * Setup Orion address map 280 * Setup Orion address map
695 */ 281 */
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 425807579303..19cf5bf99f1b 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -267,28 +267,28 @@ static struct platform_device d2net_gpio_buttons = {
267 * General Setup 267 * General Setup
268 ****************************************************************************/ 268 ****************************************************************************/
269 269
270static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { 270static unsigned int d2net_mpp_modes[] __initdata = {
271 { 0, MPP_GPIO }, /* Board ID (bit 0) */ 271 MPP0_GPIO, /* Board ID (bit 0) */
272 { 1, MPP_GPIO }, /* Board ID (bit 1) */ 272 MPP1_GPIO, /* Board ID (bit 1) */
273 { 2, MPP_GPIO }, /* Board ID (bit 2) */ 273 MPP2_GPIO, /* Board ID (bit 2) */
274 { 3, MPP_GPIO }, /* SATA 0 power */ 274 MPP3_GPIO, /* SATA 0 power */
275 { 4, MPP_UNUSED }, 275 MPP4_UNUSED,
276 { 5, MPP_GPIO }, /* Fan fail detection */ 276 MPP5_GPIO, /* Fan fail detection */
277 { 6, MPP_GPIO }, /* Red front LED */ 277 MPP6_GPIO, /* Red front LED */
278 { 7, MPP_UNUSED }, 278 MPP7_UNUSED,
279 { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ 279 MPP8_GPIO, /* Rear power switch (on|auto) */
280 { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ 280 MPP9_GPIO, /* Rear power switch (auto|off) */
281 { 10, MPP_UNUSED }, 281 MPP10_UNUSED,
282 { 11, MPP_UNUSED }, 282 MPP11_UNUSED,
283 { 12, MPP_GPIO }, /* SATA 1 power */ 283 MPP12_GPIO, /* SATA 1 power */
284 { 13, MPP_UNUSED }, 284 MPP13_UNUSED,
285 { 14, MPP_SATA_LED }, /* SATA 0 active */ 285 MPP14_SATA_LED, /* SATA 0 active */
286 { 15, MPP_SATA_LED }, /* SATA 1 active */ 286 MPP15_SATA_LED, /* SATA 1 active */
287 { 16, MPP_GPIO }, /* Blue front LED blink control */ 287 MPP16_GPIO, /* Blue front LED blink control */
288 { 17, MPP_UNUSED }, 288 MPP17_UNUSED,
289 { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ 289 MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
290 { 19, MPP_UNUSED }, 290 MPP19_UNUSED,
291 { -1 } 291 0,
292 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ 292 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
293 /* 23: Blue front LED off */ 293 /* 23: Blue front LED off */
294 /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ 294 /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index b7d4591214e0..f95d3cb01cbf 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -298,28 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
298/***************************************************************************** 298/*****************************************************************************
299 * General Setup 299 * General Setup
300 ****************************************************************************/ 300 ****************************************************************************/
301static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = { 301static unsigned int db88f5281_mpp_modes[] __initdata = {
302 { 0, MPP_GPIO }, /* USB Over Current */ 302 MPP0_GPIO, /* USB Over Current */
303 { 1, MPP_GPIO }, /* USB Vbat input */ 303 MPP1_GPIO, /* USB Vbat input */
304 { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */ 304 MPP2_PCI_ARB, /* PCI_REQn[2] */
305 { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */ 305 MPP3_PCI_ARB, /* PCI_GNTn[2] */
306 { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */ 306 MPP4_PCI_ARB, /* PCI_REQn[3] */
307 { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */ 307 MPP5_PCI_ARB, /* PCI_GNTn[3] */
308 { 6, MPP_GPIO }, /* JP0, CON17.2 */ 308 MPP6_GPIO, /* JP0, CON17.2 */
309 { 7, MPP_GPIO }, /* JP1, CON17.1 */ 309 MPP7_GPIO, /* JP1, CON17.1 */
310 { 8, MPP_GPIO }, /* JP2, CON11.2 */ 310 MPP8_GPIO, /* JP2, CON11.2 */
311 { 9, MPP_GPIO }, /* JP3, CON11.3 */ 311 MPP9_GPIO, /* JP3, CON11.3 */
312 { 10, MPP_GPIO }, /* RTC int */ 312 MPP10_GPIO, /* RTC int */
313 { 11, MPP_GPIO }, /* Baud Rate Generator */ 313 MPP11_GPIO, /* Baud Rate Generator */
314 { 12, MPP_GPIO }, /* PCI int 1 */ 314 MPP12_GPIO, /* PCI int 1 */
315 { 13, MPP_GPIO }, /* PCI int 2 */ 315 MPP13_GPIO, /* PCI int 2 */
316 { 14, MPP_NAND }, /* NAND_REn[2] */ 316 MPP14_NAND, /* NAND_REn[2] */
317 { 15, MPP_NAND }, /* NAND_WEn[2] */ 317 MPP15_NAND, /* NAND_WEn[2] */
318 { 16, MPP_UART }, /* UART1_RX */ 318 MPP16_UART, /* UART1_RX */
319 { 17, MPP_UART }, /* UART1_TX */ 319 MPP17_UART, /* UART1_TX */
320 { 18, MPP_UART }, /* UART1_CTSn */ 320 MPP18_UART, /* UART1_CTSn */
321 { 19, MPP_UART }, /* UART1_RTSn */ 321 MPP19_UART, /* UART1_RTSn */
322 { -1 }, 322 0,
323}; 323};
324 324
325static void __init db88f5281_init(void) 325static void __init db88f5281_init(void)
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 90ab022eabeb..855e0e77d563 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -385,76 +385,76 @@ static struct mv_sata_platform_data dns323_sata_data = {
385/**************************************************************************** 385/****************************************************************************
386 * General Setup 386 * General Setup
387 */ 387 */
388static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = { 388static unsigned int dns323a_mpp_modes[] __initdata = {
389 { 0, MPP_PCIE_RST_OUTn }, 389 MPP0_PCIE_RST_OUTn,
390 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 390 MPP1_GPIO, /* right amber LED (sata ch0) */
391 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 391 MPP2_GPIO, /* left amber LED (sata ch1) */
392 { 3, MPP_UNUSED }, 392 MPP3_UNUSED,
393 { 4, MPP_GPIO }, /* power button LED */ 393 MPP4_GPIO, /* power button LED */
394 { 5, MPP_GPIO }, /* power button LED */ 394 MPP5_GPIO, /* power button LED */
395 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ 395 MPP6_GPIO, /* GMT G751-2f overtemp */
396 { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ 396 MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
397 { 8, MPP_GPIO }, /* triggers power off */ 397 MPP8_GPIO, /* triggers power off */
398 { 9, MPP_GPIO }, /* power button switch */ 398 MPP9_GPIO, /* power button switch */
399 { 10, MPP_GPIO }, /* reset button switch */ 399 MPP10_GPIO, /* reset button switch */
400 { 11, MPP_UNUSED }, 400 MPP11_UNUSED,
401 { 12, MPP_UNUSED }, 401 MPP12_UNUSED,
402 { 13, MPP_UNUSED }, 402 MPP13_UNUSED,
403 { 14, MPP_UNUSED }, 403 MPP14_UNUSED,
404 { 15, MPP_UNUSED }, 404 MPP15_UNUSED,
405 { 16, MPP_UNUSED }, 405 MPP16_UNUSED,
406 { 17, MPP_UNUSED }, 406 MPP17_UNUSED,
407 { 18, MPP_UNUSED }, 407 MPP18_UNUSED,
408 { 19, MPP_UNUSED }, 408 MPP19_UNUSED,
409 { -1 }, 409 0,
410}; 410};
411 411
412static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = { 412static unsigned int dns323b_mpp_modes[] __initdata = {
413 { 0, MPP_UNUSED }, 413 MPP0_UNUSED,
414 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 414 MPP1_GPIO, /* right amber LED (sata ch0) */
415 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 415 MPP2_GPIO, /* left amber LED (sata ch1) */
416 { 3, MPP_GPIO }, /* system up flag */ 416 MPP3_GPIO, /* system up flag */
417 { 4, MPP_GPIO }, /* power button LED */ 417 MPP4_GPIO, /* power button LED */
418 { 5, MPP_GPIO }, /* power button LED */ 418 MPP5_GPIO, /* power button LED */
419 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ 419 MPP6_GPIO, /* GMT G751-2f overtemp */
420 { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ 420 MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
421 { 8, MPP_GPIO }, /* triggers power off */ 421 MPP8_GPIO, /* triggers power off */
422 { 9, MPP_GPIO }, /* power button switch */ 422 MPP9_GPIO, /* power button switch */
423 { 10, MPP_GPIO }, /* reset button switch */ 423 MPP10_GPIO, /* reset button switch */
424 { 11, MPP_UNUSED }, 424 MPP11_UNUSED,
425 { 12, MPP_SATA_LED }, 425 MPP12_SATA_LED,
426 { 13, MPP_SATA_LED }, 426 MPP13_SATA_LED,
427 { 14, MPP_SATA_LED }, 427 MPP14_SATA_LED,
428 { 15, MPP_SATA_LED }, 428 MPP15_SATA_LED,
429 { 16, MPP_UNUSED }, 429 MPP16_UNUSED,
430 { 17, MPP_UNUSED }, 430 MPP17_UNUSED,
431 { 18, MPP_UNUSED }, 431 MPP18_UNUSED,
432 { 19, MPP_UNUSED }, 432 MPP19_UNUSED,
433 { -1 }, 433 0,
434}; 434};
435 435
436static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = { 436static unsigned int dns323c_mpp_modes[] __initdata = {
437 { 0, MPP_GPIO }, /* ? input */ 437 MPP0_GPIO, /* ? input */
438 { 1, MPP_GPIO }, /* input power switch (0 = pressed) */ 438 MPP1_GPIO, /* input power switch (0 = pressed) */
439 { 2, MPP_GPIO }, /* output power off */ 439 MPP2_GPIO, /* output power off */
440 { 3, MPP_UNUSED }, /* ? output */ 440 MPP3_UNUSED, /* ? output */
441 { 4, MPP_UNUSED }, /* ? output */ 441 MPP4_UNUSED, /* ? output */
442 { 5, MPP_UNUSED }, /* ? output */ 442 MPP5_UNUSED, /* ? output */
443 { 6, MPP_UNUSED }, /* ? output */ 443 MPP6_UNUSED, /* ? output */
444 { 7, MPP_UNUSED }, /* ? output */ 444 MPP7_UNUSED, /* ? output */
445 { 8, MPP_GPIO }, /* i/o right amber LED */ 445 MPP8_GPIO, /* i/o right amber LED */
446 { 9, MPP_GPIO }, /* i/o left amber LED */ 446 MPP9_GPIO, /* i/o left amber LED */
447 { 10, MPP_GPIO }, /* input */ 447 MPP10_GPIO, /* input */
448 { 11, MPP_UNUSED }, 448 MPP11_UNUSED,
449 { 12, MPP_SATA_LED }, 449 MPP12_SATA_LED,
450 { 13, MPP_SATA_LED }, 450 MPP13_SATA_LED,
451 { 14, MPP_SATA_LED }, 451 MPP14_SATA_LED,
452 { 15, MPP_SATA_LED }, 452 MPP15_SATA_LED,
453 { 16, MPP_UNUSED }, 453 MPP16_UNUSED,
454 { 17, MPP_GPIO }, /* power button LED */ 454 MPP17_GPIO, /* power button LED */
455 { 18, MPP_GPIO }, /* fan speed bit 0 */ 455 MPP18_GPIO, /* fan speed bit 0 */
456 { 19, MPP_GPIO }, /* fan speed bit 1 */ 456 MPP19_GPIO, /* fan speed bit 1 */
457 { -1 }, 457 0,
458}; 458};
459 459
460/* Rev C1 Fan speed notes: 460/* Rev C1 Fan speed notes:
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index d037a90c216c..b67cff0d4cfe 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -180,31 +180,31 @@ static struct platform_device edmini_v2_gpio_buttons = {
180/***************************************************************************** 180/*****************************************************************************
181 * General Setup 181 * General Setup
182 ****************************************************************************/ 182 ****************************************************************************/
183static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = { 183static unsigned int edminiv2_mpp_modes[] __initdata = {
184 { 0, MPP_UNUSED }, 184 MPP0_UNUSED,
185 { 1, MPP_UNUSED }, 185 MPP1_UNUSED,
186 { 2, MPP_UNUSED }, 186 MPP2_UNUSED,
187 { 3, MPP_GPIO }, /* RTC interrupt */ 187 MPP3_GPIO, /* RTC interrupt */
188 { 4, MPP_UNUSED }, 188 MPP4_UNUSED,
189 { 5, MPP_UNUSED }, 189 MPP5_UNUSED,
190 { 6, MPP_UNUSED }, 190 MPP6_UNUSED,
191 { 7, MPP_UNUSED }, 191 MPP7_UNUSED,
192 { 8, MPP_UNUSED }, 192 MPP8_UNUSED,
193 { 9, MPP_UNUSED }, 193 MPP9_UNUSED,
194 { 10, MPP_UNUSED }, 194 MPP10_UNUSED,
195 { 11, MPP_UNUSED }, 195 MPP11_UNUSED,
196 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 196 MPP12_SATA_LED, /* SATA 0 presence */
197 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 197 MPP13_SATA_LED, /* SATA 1 presence */
198 { 14, MPP_SATA_LED }, /* SATA 0 active */ 198 MPP14_SATA_LED, /* SATA 0 active */
199 { 15, MPP_SATA_LED }, /* SATA 1 active */ 199 MPP15_SATA_LED, /* SATA 1 active */
200 /* 16: Power LED control (0 = On, 1 = Off) */ 200 /* 16: Power LED control (0 = On, 1 = Off) */
201 { 16, MPP_GPIO }, 201 MPP16_GPIO,
202 /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */ 202 /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
203 { 17, MPP_GPIO }, 203 MPP17_GPIO,
204 /* 18: Power button status (0 = Released, 1 = Pressed) */ 204 /* 18: Power button status (0 = Released, 1 = Pressed) */
205 { 18, MPP_GPIO }, 205 MPP18_GPIO,
206 { 19, MPP_UNUSED }, 206 MPP19_UNUSED,
207 { -1 } 207 0,
208}; 208};
209 209
210static void __init edmini_v2_init(void) 210static void __init edmini_v2_init(void)
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 47497c76162a..c0eb6462633f 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -315,28 +315,28 @@ static void kurobox_pro_power_off(void)
315/***************************************************************************** 315/*****************************************************************************
316 * General Setup 316 * General Setup
317 ****************************************************************************/ 317 ****************************************************************************/
318static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = { 318static unsigned int kurobox_pro_mpp_modes[] __initdata = {
319 { 0, MPP_UNUSED }, 319 MPP0_UNUSED,
320 { 1, MPP_UNUSED }, 320 MPP1_UNUSED,
321 { 2, MPP_GPIO }, /* GPIO Micon */ 321 MPP2_GPIO, /* GPIO Micon */
322 { 3, MPP_GPIO }, /* GPIO Rtc */ 322 MPP3_GPIO, /* GPIO Rtc */
323 { 4, MPP_UNUSED }, 323 MPP4_UNUSED,
324 { 5, MPP_UNUSED }, 324 MPP5_UNUSED,
325 { 6, MPP_NAND }, /* NAND Flash REn */ 325 MPP6_NAND, /* NAND Flash REn */
326 { 7, MPP_NAND }, /* NAND Flash WEn */ 326 MPP7_NAND, /* NAND Flash WEn */
327 { 8, MPP_UNUSED }, 327 MPP8_UNUSED,
328 { 9, MPP_UNUSED }, 328 MPP9_UNUSED,
329 { 10, MPP_UNUSED }, 329 MPP10_UNUSED,
330 { 11, MPP_UNUSED }, 330 MPP11_UNUSED,
331 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 331 MPP12_SATA_LED, /* SATA 0 presence */
332 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 332 MPP13_SATA_LED, /* SATA 1 presence */
333 { 14, MPP_SATA_LED }, /* SATA 0 active */ 333 MPP14_SATA_LED, /* SATA 0 active */
334 { 15, MPP_SATA_LED }, /* SATA 1 active */ 334 MPP15_SATA_LED, /* SATA 1 active */
335 { 16, MPP_UART }, /* UART1 RXD */ 335 MPP16_UART, /* UART1 RXD */
336 { 17, MPP_UART }, /* UART1 TXD */ 336 MPP17_UART, /* UART1 TXD */
337 { 18, MPP_UART }, /* UART1 CTSn */ 337 MPP18_UART, /* UART1 CTSn */
338 { 19, MPP_UART }, /* UART1 RTSn */ 338 MPP19_UART, /* UART1 RTSn */
339 { -1 }, 339 0,
340}; 340};
341 341
342static void __init kurobox_pro_init(void) 342static void __init kurobox_pro_init(void)
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6ae12aa6d759..5065803ca82a 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -251,28 +251,28 @@ static struct platform_device lschl_fan_device = {
251 * GPIO Data 251 * GPIO Data
252 ****************************************************************************/ 252 ****************************************************************************/
253 253
254static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = { 254static unsigned int lschl_mpp_modes[] __initdata = {
255 { 0, MPP_GPIO }, /* LED POWER */ 255 MPP0_GPIO, /* LED POWER */
256 { 1, MPP_GPIO }, /* HDD POWER */ 256 MPP1_GPIO, /* HDD POWER */
257 { 2, MPP_GPIO }, /* LED ALARM */ 257 MPP2_GPIO, /* LED ALARM */
258 { 3, MPP_GPIO }, /* LED INFO */ 258 MPP3_GPIO, /* LED INFO */
259 { 4, MPP_UNUSED }, 259 MPP4_UNUSED,
260 { 5, MPP_UNUSED }, 260 MPP5_UNUSED,
261 { 6, MPP_GPIO }, /* FAN LOCK */ 261 MPP6_GPIO, /* FAN LOCK */
262 { 7, MPP_GPIO }, /* SW INIT */ 262 MPP7_GPIO, /* SW INIT */
263 { 8, MPP_GPIO }, /* SW POWER */ 263 MPP8_GPIO, /* SW POWER */
264 { 9, MPP_GPIO }, /* USB POWER */ 264 MPP9_GPIO, /* USB POWER */
265 { 10, MPP_GPIO }, /* SW AUTO POWER */ 265 MPP10_GPIO, /* SW AUTO POWER */
266 { 11, MPP_UNUSED }, 266 MPP11_UNUSED,
267 { 12, MPP_UNUSED }, 267 MPP12_UNUSED,
268 { 13, MPP_UNUSED }, 268 MPP13_UNUSED,
269 { 14, MPP_GPIO }, /* FAN HIGH */ 269 MPP14_GPIO, /* FAN HIGH */
270 { 15, MPP_GPIO }, /* SW FUNC */ 270 MPP15_GPIO, /* SW FUNC */
271 { 16, MPP_GPIO }, /* FAN LOW */ 271 MPP16_GPIO, /* FAN LOW */
272 { 17, MPP_GPIO }, /* LED FUNC */ 272 MPP17_GPIO, /* LED FUNC */
273 { 18, MPP_UNUSED }, 273 MPP18_UNUSED,
274 { 19, MPP_UNUSED }, 274 MPP19_UNUSED,
275 { -1 }, 275 0,
276}; 276};
277 277
278static void __init lschl_init(void) 278static void __init lschl_init(void)
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 7adafd79cf98..8503d0a42d41 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -200,28 +200,28 @@ static void ls_hgl_power_off(void)
200 200
201#define LS_HGL_GPIO_HDD_POWER 1 201#define LS_HGL_GPIO_HDD_POWER 1
202 202
203static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = { 203static unsigned int ls_hgl_mpp_modes[] __initdata = {
204 { 0, MPP_GPIO }, /* LED_PWR */ 204 MPP0_GPIO, /* LED_PWR */
205 { 1, MPP_GPIO }, /* HDD_PWR */ 205 MPP1_GPIO, /* HDD_PWR */
206 { 2, MPP_GPIO }, /* LED_ALARM */ 206 MPP2_GPIO, /* LED_ALARM */
207 { 3, MPP_GPIO }, /* LED_INFO */ 207 MPP3_GPIO, /* LED_INFO */
208 { 4, MPP_UNUSED }, 208 MPP4_UNUSED,
209 { 5, MPP_UNUSED }, 209 MPP5_UNUSED,
210 { 6, MPP_GPIO }, /* FAN_LCK */ 210 MPP6_GPIO, /* FAN_LCK */
211 { 7, MPP_GPIO }, /* INIT */ 211 MPP7_GPIO, /* INIT */
212 { 8, MPP_GPIO }, /* POWER */ 212 MPP8_GPIO, /* POWER */
213 { 9, MPP_GPIO }, /* USB_PWR */ 213 MPP9_GPIO, /* USB_PWR */
214 { 10, MPP_GPIO }, /* AUTO_POWER */ 214 MPP10_GPIO, /* AUTO_POWER */
215 { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ 215 MPP11_UNUSED, /* LED_ETH (dummy) */
216 { 12, MPP_UNUSED }, 216 MPP12_UNUSED,
217 { 13, MPP_UNUSED }, 217 MPP13_UNUSED,
218 { 14, MPP_UNUSED }, 218 MPP14_UNUSED,
219 { 15, MPP_GPIO }, /* FUNC */ 219 MPP15_GPIO, /* FUNC */
220 { 16, MPP_UNUSED }, 220 MPP16_UNUSED,
221 { 17, MPP_GPIO }, /* LED_FUNC */ 221 MPP17_GPIO, /* LED_FUNC */
222 { 18, MPP_UNUSED }, 222 MPP18_UNUSED,
223 { 19, MPP_UNUSED }, 223 MPP19_UNUSED,
224 { -1 }, 224 0,
225}; 225};
226 226
227static void __init ls_hgl_init(void) 227static void __init ls_hgl_init(void)
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 869958f5c394..9c82723c05c0 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -201,28 +201,28 @@ static void lsmini_power_off(void)
201#define LSMINI_GPIO_HDD_POWER0 1 201#define LSMINI_GPIO_HDD_POWER0 1
202#define LSMINI_GPIO_HDD_POWER1 19 202#define LSMINI_GPIO_HDD_POWER1 19
203 203
204static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = { 204static unsigned int lsmini_mpp_modes[] __initdata = {
205 { 0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */ 205 MPP0_UNUSED, /* LED_RESERVE1 (unused) */
206 { 1, MPP_GPIO }, /* HDD_PWR */ 206 MPP1_GPIO, /* HDD_PWR */
207 { 2, MPP_GPIO }, /* LED_ALARM */ 207 MPP2_GPIO, /* LED_ALARM */
208 { 3, MPP_GPIO }, /* LED_INFO */ 208 MPP3_GPIO, /* LED_INFO */
209 { 4, MPP_UNUSED }, 209 MPP4_UNUSED,
210 { 5, MPP_UNUSED }, 210 MPP5_UNUSED,
211 { 6, MPP_UNUSED }, 211 MPP6_UNUSED,
212 { 7, MPP_UNUSED }, 212 MPP7_UNUSED,
213 { 8, MPP_UNUSED }, 213 MPP8_UNUSED,
214 { 9, MPP_GPIO }, /* LED_FUNC */ 214 MPP9_GPIO, /* LED_FUNC */
215 { 10, MPP_UNUSED }, 215 MPP10_UNUSED,
216 { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ 216 MPP11_UNUSED, /* LED_ETH (dummy) */
217 { 12, MPP_UNUSED }, 217 MPP12_UNUSED,
218 { 13, MPP_UNUSED }, 218 MPP13_UNUSED,
219 { 14, MPP_GPIO }, /* LED_PWR */ 219 MPP14_GPIO, /* LED_PWR */
220 { 15, MPP_GPIO }, /* FUNC */ 220 MPP15_GPIO, /* FUNC */
221 { 16, MPP_GPIO }, /* USB_PWR */ 221 MPP16_GPIO, /* USB_PWR */
222 { 17, MPP_GPIO }, /* AUTO_POWER */ 222 MPP17_GPIO, /* AUTO_POWER */
223 { 18, MPP_GPIO }, /* POWER */ 223 MPP18_GPIO, /* POWER */
224 { 19, MPP_GPIO }, /* HDD_PWR1 */ 224 MPP19_GPIO, /* HDD_PWR1 */
225 { -1 }, 225 0,
226}; 226};
227 227
228static void __init lsmini_init(void) 228static void __init lsmini_init(void)
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 2288207726e4..f12c41b98d46 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -12,154 +12,34 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/gpio.h>
16#include <mach/hardware.h> 15#include <mach/hardware.h>
17#include "common.h" 16#include <plat/mpp.h>
18#include "mpp.h" 17#include "mpp.h"
18#include "common.h"
19 19
20static int is_5181l(void) 20static unsigned int __init orion5x_variant(void)
21{
22 u32 dev;
23 u32 rev;
24
25 orion5x_pcie_id(&dev, &rev);
26
27 return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
28}
29
30static int is_5182(void)
31{ 21{
32 u32 dev; 22 u32 dev;
33 u32 rev; 23 u32 rev;
34 24
35 orion5x_pcie_id(&dev, &rev); 25 orion5x_pcie_id(&dev, &rev);
36 26
37 return !!(dev == MV88F5182_DEV_ID); 27 if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0)
38} 28 return MPP_F5181_MASK;
39 29
40static int is_5281(void) 30 if (dev == MV88F5182_DEV_ID)
41{ 31 return MPP_F5182_MASK;
42 u32 dev;
43 u32 rev;
44 32
45 orion5x_pcie_id(&dev, &rev); 33 if (dev == MV88F5281_DEV_ID)
34 return MPP_F5281_MASK;
46 35
47 return !!(dev == MV88F5281_DEV_ID); 36 printk(KERN_ERR "MPP setup: unknown orion5x variant "
37 "(dev %#x rev %#x)\n", dev, rev);
38 return 0;
48} 39}
49 40
50static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type) 41void __init orion5x_mpp_conf(unsigned int *mpp_list)
51{ 42{
52 switch (type) { 43 orion_mpp_conf(mpp_list, orion5x_variant(),
53 case MPP_UNUSED: 44 MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
54 case MPP_GPIO:
55 if (mpp == 0)
56 return 3;
57 if (mpp >= 1 && mpp <= 15)
58 return 0;
59 if (mpp >= 16 && mpp <= 19) {
60 if (is_5182())
61 return 5;
62 if (type == MPP_UNUSED)
63 return 0;
64 }
65 return -1;
66
67 case MPP_PCIE_RST_OUTn:
68 if (mpp == 0)
69 return 0;
70 return -1;
71
72 case MPP_PCI_ARB:
73 if (mpp >= 0 && mpp <= 7)
74 return 2;
75 return -1;
76
77 case MPP_PCI_PMEn:
78 if (mpp == 2)
79 return 3;
80 return -1;
81
82 case MPP_GIGE:
83 if (mpp >= 8 && mpp <= 19)
84 return 1;
85 return -1;
86
87 case MPP_NAND:
88 if (is_5182() || is_5281()) {
89 if (mpp >= 4 && mpp <= 7)
90 return 4;
91 if (mpp >= 12 && mpp <= 17)
92 return 4;
93 }
94 return -1;
95
96 case MPP_PCI_CLK:
97 if (is_5181l() && mpp >= 6 && mpp <= 7)
98 return 5;
99 return -1;
100
101 case MPP_SATA_LED:
102 if (is_5182()) {
103 if (mpp >= 4 && mpp <= 7)
104 return 5;
105 if (mpp >= 12 && mpp <= 15)
106 return 5;
107 }
108 return -1;
109
110 case MPP_UART:
111 if (mpp >= 16 && mpp <= 19)
112 return 0;
113 return -1;
114 }
115
116 printk(KERN_INFO "unknown MPP type %d\n", type);
117
118 return -1;
119}
120
121void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
122{
123 u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
124 u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
125 u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
126
127 for ( ; mode->mpp >= 0; mode++) {
128 u32 *reg;
129 int num_type;
130 int shift;
131
132 if (mode->mpp >= 0 && mode->mpp <= 7)
133 reg = &mpp_0_7_ctrl;
134 else if (mode->mpp >= 8 && mode->mpp <= 15)
135 reg = &mpp_8_15_ctrl;
136 else if (mode->mpp >= 16 && mode->mpp <= 19)
137 reg = &mpp_16_19_ctrl;
138 else {
139 printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
140 "(%d)\n", mode->mpp);
141 continue;
142 }
143
144 num_type = determine_type_encoding(mode->mpp, mode->type);
145 if (num_type < 0) {
146 printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
147 "combination (%d, %d)\n", mode->mpp,
148 mode->type);
149 continue;
150 }
151
152 shift = (mode->mpp & 7) << 2;
153 *reg &= ~(0xf << shift);
154 *reg |= (num_type & 0xf) << shift;
155
156 if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182()))
157 orion_gpio_set_unused(mode->mpp);
158
159 orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
160 }
161
162 writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
163 writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
164 writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
165} 45}
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index 290e610dc012..eac68978a2c2 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -1,74 +1,129 @@
1#ifndef __ARCH_ORION5X_MPP_H 1#ifndef __ARCH_ORION5X_MPP_H
2#define __ARCH_ORION5X_MPP_H 2#define __ARCH_ORION5X_MPP_H
3 3
4enum orion5x_mpp_type { 4#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
5 /* 5 /* MPP number */ ((_num) & 0xff) | \
6 * This MPP is unused. 6 /* MPP select value */ (((_sel) & 0xf) << 8) | \
7 */ 7 /* may be input signal */ ((!!(_in)) << 12) | \
8 MPP_UNUSED, 8 /* may be output signal */ ((!!(_out)) << 13) | \
9 9 /* available on F5181l */ ((!!(_F5181l)) << 14) | \
10 /* 10 /* available on F5182 */ ((!!(_F5182)) << 15) | \
11 * This MPP pin is used as a generic GPIO pin. Valid for 11 /* available on F5281 */ ((!!(_F5281)) << 16))
12 * MPPs 0-15 and device bus data pins 16-31. On 5182, also
13 * valid for MPPs 16-19.
14 */
15 MPP_GPIO,
16
17 /*
18 * This MPP is used as PCIe_RST_OUTn pin. Valid for
19 * MPP 0 only.
20 */
21 MPP_PCIE_RST_OUTn,
22
23 /*
24 * This MPP is used as PCI arbiter pin (REQn/GNTn).
25 * Valid for MPPs 0-7 only.
26 */
27 MPP_PCI_ARB,
28
29 /*
30 * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
31 */
32 MPP_PCI_PMEn,
33
34 /*
35 * This MPP is used as GigE half-duplex (COL, CRS) or GMII
36 * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
37 * MPPs 8-19 only.
38 */
39 MPP_GIGE,
40
41 /*
42 * This MPP is used as NAND REn/WEn pin. Valid for MPPs
43 * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
44 */
45 MPP_NAND,
46
47 /*
48 * This MPP is used as a PCI clock output pin. Valid for
49 * MPPs 6-7 only, and only on the 5181l.
50 */
51 MPP_PCI_CLK,
52
53 /*
54 * This MPP is used as a SATA presence/activity LED.
55 * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
56 */
57 MPP_SATA_LED,
58
59 /*
60 * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
61 * Valid for MPPs 16-19 only.
62 */
63 MPP_UART,
64};
65
66struct orion5x_mpp_mode {
67 int mpp;
68 enum orion5x_mpp_type type;
69};
70
71void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
72 12
13 /* num sel i o 5181 5182 5281 */
14
15#define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
16#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
17#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
18
19#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
20#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
21#define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
22#define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
23
24#define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1)
25#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1)
26#define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
27
28#define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1)
29#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1)
30#define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1)
31#define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1)
32
33#define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1)
34#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1)
35#define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1)
36
37#define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1)
38#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1)
39#define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1)
40#define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1)
41#define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0)
42
43#define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1)
44#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1)
45#define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1)
46#define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1)
47#define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0)
48
49#define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1)
50#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1)
51#define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1)
52#define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1)
53#define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0)
54#define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0)
55
56#define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1)
57#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1)
58#define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1)
59#define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1)
60#define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0)
61#define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0)
62
63#define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1)
64#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1)
65#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
66
67#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1)
68#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1)
69#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1)
70
71#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1)
72#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1)
73#define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1)
74
75#define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1)
76#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1)
77#define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1)
78
79#define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1)
80#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1)
81#define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1)
82#define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1)
83#define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0)
84
85#define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1)
86#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1)
87#define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1)
88#define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1)
89#define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0)
90
91#define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1)
92#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1)
93#define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1)
94#define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1)
95#define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0)
96
97#define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1)
98#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1)
99#define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1)
100#define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1)
101#define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0)
102
103#define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1)
104#define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0)
105#define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1)
106#define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1)
107#define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1)
108
109#define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1)
110#define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0)
111#define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1)
112#define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1)
113#define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1)
114
115#define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1)
116#define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0)
117#define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1)
118#define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1)
119
120#define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1)
121#define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0)
122#define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1)
123#define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1)
124
125#define MPP_MAX 19
126
127void orion5x_mpp_conf(unsigned int *mpp_list);
73 128
74#endif 129#endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index b43b208153cb..59263b73d1e4 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -193,28 +193,28 @@ static void mss2_power_off(void)
193/**************************************************************************** 193/****************************************************************************
194 * General Setup 194 * General Setup
195 ****************************************************************************/ 195 ****************************************************************************/
196static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = { 196static unsigned int mss2_mpp_modes[] __initdata = {
197 { 0, MPP_GPIO }, /* Power LED */ 197 MPP0_GPIO, /* Power LED */
198 { 1, MPP_GPIO }, /* Error LED */ 198 MPP1_GPIO, /* Error LED */
199 { 2, MPP_UNUSED }, 199 MPP2_UNUSED,
200 { 3, MPP_GPIO }, /* RTC interrupt */ 200 MPP3_GPIO, /* RTC interrupt */
201 { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/ 201 MPP4_GPIO, /* HDD ind. (Single/Dual)*/
202 { 5, MPP_GPIO }, /* HD0 5V control */ 202 MPP5_GPIO, /* HD0 5V control */
203 { 6, MPP_GPIO }, /* HD0 12V control */ 203 MPP6_GPIO, /* HD0 12V control */
204 { 7, MPP_GPIO }, /* HD1 5V control */ 204 MPP7_GPIO, /* HD1 5V control */
205 { 8, MPP_GPIO }, /* HD1 12V control */ 205 MPP8_GPIO, /* HD1 12V control */
206 { 9, MPP_UNUSED }, 206 MPP9_UNUSED,
207 { 10, MPP_GPIO }, /* Fan control */ 207 MPP10_GPIO, /* Fan control */
208 { 11, MPP_GPIO }, /* Power button */ 208 MPP11_GPIO, /* Power button */
209 { 12, MPP_GPIO }, /* Reset button */ 209 MPP12_GPIO, /* Reset button */
210 { 13, MPP_UNUSED }, 210 MPP13_UNUSED,
211 { 14, MPP_SATA_LED }, /* SATA 0 active */ 211 MPP14_SATA_LED, /* SATA 0 active */
212 { 15, MPP_SATA_LED }, /* SATA 1 active */ 212 MPP15_SATA_LED, /* SATA 1 active */
213 { 16, MPP_UNUSED }, 213 MPP16_UNUSED,
214 { 17, MPP_UNUSED }, 214 MPP17_UNUSED,
215 { 18, MPP_UNUSED }, 215 MPP18_UNUSED,
216 { 19, MPP_UNUSED }, 216 MPP19_UNUSED,
217 { -1 }, 217 0,
218}; 218};
219 219
220static void __init mss2_init(void) 220static void __init mss2_init(void)
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index c55d071707f5..63ff10c3c464 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -108,28 +108,28 @@ static struct platform_device mv2120_button_device = {
108/**************************************************************************** 108/****************************************************************************
109 * General Setup 109 * General Setup
110 ****************************************************************************/ 110 ****************************************************************************/
111static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = { 111static unsigned int mv2120_mpp_modes[] __initdata = {
112 { 0, MPP_GPIO }, /* Sys status LED */ 112 MPP0_GPIO, /* Sys status LED */
113 { 1, MPP_GPIO }, /* Sys error LED */ 113 MPP1_GPIO, /* Sys error LED */
114 { 2, MPP_GPIO }, /* OverTemp interrupt */ 114 MPP2_GPIO, /* OverTemp interrupt */
115 { 3, MPP_GPIO }, /* RTC interrupt */ 115 MPP3_GPIO, /* RTC interrupt */
116 { 4, MPP_GPIO }, /* V_LED 5V */ 116 MPP4_GPIO, /* V_LED 5V */
117 { 5, MPP_GPIO }, /* V_LED 3.3V */ 117 MPP5_GPIO, /* V_LED 3.3V */
118 { 6, MPP_UNUSED }, 118 MPP6_UNUSED,
119 { 7, MPP_UNUSED }, 119 MPP7_UNUSED,
120 { 8, MPP_GPIO }, /* SATA 0 fail LED */ 120 MPP8_GPIO, /* SATA 0 fail LED */
121 { 9, MPP_GPIO }, /* SATA 1 fail LED */ 121 MPP9_GPIO, /* SATA 1 fail LED */
122 { 10, MPP_UNUSED }, 122 MPP10_UNUSED,
123 { 11, MPP_UNUSED }, 123 MPP11_UNUSED,
124 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 124 MPP12_SATA_LED, /* SATA 0 presence */
125 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 125 MPP13_SATA_LED, /* SATA 1 presence */
126 { 14, MPP_SATA_LED }, /* SATA 0 active */ 126 MPP14_SATA_LED, /* SATA 0 active */
127 { 15, MPP_SATA_LED }, /* SATA 1 active */ 127 MPP15_SATA_LED, /* SATA 1 active */
128 { 16, MPP_UNUSED }, 128 MPP16_UNUSED,
129 { 17, MPP_GPIO }, /* Reset button */ 129 MPP17_GPIO, /* Reset button */
130 { 18, MPP_GPIO }, /* Power button */ 130 MPP18_GPIO, /* Power button */
131 { 19, MPP_GPIO }, /* Power off */ 131 MPP19_GPIO, /* Power off */
132 { -1 }, 132 0,
133}; 133};
134 134
135static struct i2c_board_info __initdata mv2120_i2c_rtc = { 135static struct i2c_board_info __initdata mv2120_i2c_rtc = {
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index a5930f83958b..e43b39cc7fe9 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -339,28 +339,28 @@ static struct platform_device net2big_gpio_buttons = {
339 * General Setup 339 * General Setup
340 ****************************************************************************/ 340 ****************************************************************************/
341 341
342static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = { 342static unsigned int net2big_mpp_modes[] __initdata = {
343 { 0, MPP_GPIO }, /* Raid mode (bit 0) */ 343 MPP0_GPIO, /* Raid mode (bit 0) */
344 { 1, MPP_GPIO }, /* USB port 2 fuse (0 = Fail, 1 = Ok) */ 344 MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
345 { 2, MPP_GPIO }, /* Raid mode (bit 1) */ 345 MPP2_GPIO, /* Raid mode (bit 1) */
346 { 3, MPP_GPIO }, /* Board ID (bit 0) */ 346 MPP3_GPIO, /* Board ID (bit 0) */
347 { 4, MPP_GPIO }, /* Fan activity (0 = Off, 1 = On) */ 347 MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */
348 { 5, MPP_GPIO }, /* Fan fail detection */ 348 MPP5_GPIO, /* Fan fail detection */
349 { 6, MPP_GPIO }, /* Red front LED (0 = Off, 1 = On) */ 349 MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */
350 { 7, MPP_GPIO }, /* Disable initial blinking on front LED */ 350 MPP7_GPIO, /* Disable initial blinking on front LED */
351 { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ 351 MPP8_GPIO, /* Rear power switch (on|auto) */
352 { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ 352 MPP9_GPIO, /* Rear power switch (auto|off) */
353 { 10, MPP_GPIO }, /* SATA 1 red LED (0 = Off, 1 = On) */ 353 MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */
354 { 11, MPP_GPIO }, /* SATA 0 red LED (0 = Off, 1 = On) */ 354 MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */
355 { 12, MPP_GPIO }, /* Board ID (bit 1) */ 355 MPP12_GPIO, /* Board ID (bit 1) */
356 { 13, MPP_GPIO }, /* SATA 1 blue LED blink control */ 356 MPP13_GPIO, /* SATA 1 blue LED blink control */
357 { 14, MPP_SATA_LED }, 357 MPP14_SATA_LED,
358 { 15, MPP_SATA_LED }, 358 MPP15_SATA_LED,
359 { 16, MPP_GPIO }, /* Blue front LED control */ 359 MPP16_GPIO, /* Blue front LED control */
360 { 17, MPP_GPIO }, /* SATA 0 blue LED blink control */ 360 MPP17_GPIO, /* SATA 0 blue LED blink control */
361 { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ 361 MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
362 { 19, MPP_GPIO }, /* SATA{0,1} power On/Off request */ 362 MPP19_GPIO, /* SATA{0,1} power On/Off request */
363 { -1 } 363 0,
364 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ 364 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
365 /* 23: SATA 0 power status */ 365 /* 23: SATA 0 power status */
366 /* 24: Board power off */ 366 /* 24: Board power off */
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 34310ab56e29..9eec7c2375e9 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -64,28 +64,28 @@ static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
64/***************************************************************************** 64/*****************************************************************************
65 * General Setup 65 * General Setup
66 ****************************************************************************/ 66 ****************************************************************************/
67static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = { 67static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = {
68 { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */ 68 MPP0_GPIO, /* LED1 CardBus LED (front panel) */
69 { 1, MPP_GPIO }, /* PCI_intA */ 69 MPP1_GPIO, /* PCI_intA */
70 { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/ 70 MPP2_GPIO, /* Hard Reset / Factory Init*/
71 { 3, MPP_GPIO }, /* FXS or DAA select */ 71 MPP3_GPIO, /* FXS or DAA select */
72 { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */ 72 MPP4_GPIO, /* LED6 - phone LED (front panel) */
73 { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */ 73 MPP5_GPIO, /* LED5 - phone LED (front panel) */
74 { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ 74 MPP6_PCI_CLK, /* CPU PCI refclk */
75 { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ 75 MPP7_PCI_CLK, /* PCI/PCIe refclk */
76 { 8, MPP_GPIO }, /* CardBus reset */ 76 MPP8_GPIO, /* CardBus reset */
77 { 9, MPP_GPIO }, /* GE_RXERR */ 77 MPP9_GPIO, /* GE_RXERR */
78 { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */ 78 MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */
79 { 11, MPP_GPIO }, /* Lifeline control */ 79 MPP11_GPIO, /* Lifeline control */
80 { 12, MPP_GIGE }, /* GE_TXD[4] */ 80 MPP12_GIGE, /* GE_TXD[4] */
81 { 13, MPP_GIGE }, /* GE_TXD[5] */ 81 MPP13_GIGE, /* GE_TXD[5] */
82 { 14, MPP_GIGE }, /* GE_TXD[6] */ 82 MPP14_GIGE, /* GE_TXD[6] */
83 { 15, MPP_GIGE }, /* GE_TXD[7] */ 83 MPP15_GIGE, /* GE_TXD[7] */
84 { 16, MPP_GIGE }, /* GE_RXD[4] */ 84 MPP16_GIGE, /* GE_RXD[4] */
85 { 17, MPP_GIGE }, /* GE_RXD[5] */ 85 MPP17_GIGE, /* GE_RXD[5] */
86 { 18, MPP_GIGE }, /* GE_RXD[6] */ 86 MPP18_GIGE, /* GE_RXD[6] */
87 { 19, MPP_GIGE }, /* GE_RXD[7] */ 87 MPP19_GIGE, /* GE_RXD[7] */
88 { -1 }, 88 0,
89}; 89};
90 90
91static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { 91static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c1f79fa014ed..0cc90bbfd326 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -65,28 +65,28 @@ static struct platform_device rd88f5181l_ge_nor_boot_flash = {
65/***************************************************************************** 65/*****************************************************************************
66 * General Setup 66 * General Setup
67 ****************************************************************************/ 67 ****************************************************************************/
68static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = { 68static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
69 { 0, MPP_GPIO }, /* LED1 */ 69 MPP0_GPIO, /* LED1 */
70 { 1, MPP_GPIO }, /* LED5 */ 70 MPP1_GPIO, /* LED5 */
71 { 2, MPP_GPIO }, /* LED4 */ 71 MPP2_GPIO, /* LED4 */
72 { 3, MPP_GPIO }, /* LED3 */ 72 MPP3_GPIO, /* LED3 */
73 { 4, MPP_GPIO }, /* PCI_intA */ 73 MPP4_GPIO, /* PCI_intA */
74 { 5, MPP_GPIO }, /* RTC interrupt */ 74 MPP5_GPIO, /* RTC interrupt */
75 { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ 75 MPP6_PCI_CLK, /* CPU PCI refclk */
76 { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ 76 MPP7_PCI_CLK, /* PCI/PCIe refclk */
77 { 8, MPP_GPIO }, /* 88e6131 interrupt */ 77 MPP8_GPIO, /* 88e6131 interrupt */
78 { 9, MPP_GPIO }, /* GE_RXERR */ 78 MPP9_GPIO, /* GE_RXERR */
79 { 10, MPP_GPIO }, /* PCI_intB */ 79 MPP10_GPIO, /* PCI_intB */
80 { 11, MPP_GPIO }, /* LED2 */ 80 MPP11_GPIO, /* LED2 */
81 { 12, MPP_GIGE }, /* GE_TXD[4] */ 81 MPP12_GIGE, /* GE_TXD[4] */
82 { 13, MPP_GIGE }, /* GE_TXD[5] */ 82 MPP13_GIGE, /* GE_TXD[5] */
83 { 14, MPP_GIGE }, /* GE_TXD[6] */ 83 MPP14_GIGE, /* GE_TXD[6] */
84 { 15, MPP_GIGE }, /* GE_TXD[7] */ 84 MPP15_GIGE, /* GE_TXD[7] */
85 { 16, MPP_GIGE }, /* GE_RXD[4] */ 85 MPP16_GIGE, /* GE_RXD[4] */
86 { 17, MPP_GIGE }, /* GE_RXD[5] */ 86 MPP17_GIGE, /* GE_RXD[5] */
87 { 18, MPP_GIGE }, /* GE_RXD[6] */ 87 MPP18_GIGE, /* GE_RXD[6] */
88 { 19, MPP_GIGE }, /* GE_RXD[7] */ 88 MPP19_GIGE, /* GE_RXD[7] */
89 { -1 }, 89 0,
90}; 90};
91 91
92static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = { 92static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 4fc46772a087..48da39b9bdb0 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -241,28 +241,28 @@ static struct mv_sata_platform_data rd88f5182_sata_data = {
241/***************************************************************************** 241/*****************************************************************************
242 * General Setup 242 * General Setup
243 ****************************************************************************/ 243 ****************************************************************************/
244static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = { 244static unsigned int rd88f5182_mpp_modes[] __initdata = {
245 { 0, MPP_GPIO }, /* Debug Led */ 245 MPP0_GPIO, /* Debug Led */
246 { 1, MPP_GPIO }, /* Reset Switch */ 246 MPP1_GPIO, /* Reset Switch */
247 { 2, MPP_UNUSED }, 247 MPP2_UNUSED,
248 { 3, MPP_GPIO }, /* RTC Int */ 248 MPP3_GPIO, /* RTC Int */
249 { 4, MPP_GPIO }, 249 MPP4_GPIO,
250 { 5, MPP_GPIO }, 250 MPP5_GPIO,
251 { 6, MPP_GPIO }, /* PCI_intA */ 251 MPP6_GPIO, /* PCI_intA */
252 { 7, MPP_GPIO }, /* PCI_intB */ 252 MPP7_GPIO, /* PCI_intB */
253 { 8, MPP_UNUSED }, 253 MPP8_UNUSED,
254 { 9, MPP_UNUSED }, 254 MPP9_UNUSED,
255 { 10, MPP_UNUSED }, 255 MPP10_UNUSED,
256 { 11, MPP_UNUSED }, 256 MPP11_UNUSED,
257 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 257 MPP12_SATA_LED, /* SATA 0 presence */
258 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 258 MPP13_SATA_LED, /* SATA 1 presence */
259 { 14, MPP_SATA_LED }, /* SATA 0 active */ 259 MPP14_SATA_LED, /* SATA 0 active */
260 { 15, MPP_SATA_LED }, /* SATA 1 active */ 260 MPP15_SATA_LED, /* SATA 1 active */
261 { 16, MPP_UNUSED }, 261 MPP16_UNUSED,
262 { 17, MPP_UNUSED }, 262 MPP17_UNUSED,
263 { 18, MPP_UNUSED }, 263 MPP18_UNUSED,
264 { 19, MPP_UNUSED }, 264 MPP19_UNUSED,
265 { -1 }, 265 0,
266}; 266};
267 267
268static void __init rd88f5182_init(void) 268static void __init rd88f5182_init(void)
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index b080c6966d10..ad2eba9286ad 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -27,7 +27,6 @@
27#include <asm/mach/pci.h> 27#include <asm/mach/pci.h>
28#include <mach/orion5x.h> 28#include <mach/orion5x.h>
29#include "common.h" 29#include "common.h"
30#include "mpp.h"
31 30
32static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { 31static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
33 .phy_addr = -1, 32 .phy_addr = -1,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 616004143912..29ce826c3c21 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -295,28 +295,28 @@ static void tsp2_power_off(void)
295/***************************************************************************** 295/*****************************************************************************
296 * General Setup 296 * General Setup
297 ****************************************************************************/ 297 ****************************************************************************/
298static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = { 298static unsigned int tsp2_mpp_modes[] __initdata = {
299 { 0, MPP_PCIE_RST_OUTn }, 299 MPP0_PCIE_RST_OUTn,
300 { 1, MPP_UNUSED }, 300 MPP1_UNUSED,
301 { 2, MPP_UNUSED }, 301 MPP2_UNUSED,
302 { 3, MPP_UNUSED }, 302 MPP3_UNUSED,
303 { 4, MPP_NAND }, /* BOOT NAND Flash REn */ 303 MPP4_NAND, /* BOOT NAND Flash REn */
304 { 5, MPP_NAND }, /* BOOT NAND Flash WEn */ 304 MPP5_NAND, /* BOOT NAND Flash WEn */
305 { 6, MPP_NAND }, /* BOOT NAND Flash HREn[0] */ 305 MPP6_NAND, /* BOOT NAND Flash HREn[0] */
306 { 7, MPP_NAND }, /* BOOT NAND Flash WEn[0] */ 306 MPP7_NAND, /* BOOT NAND Flash WEn[0] */
307 { 8, MPP_GPIO }, /* MICON int */ 307 MPP8_GPIO, /* MICON int */
308 { 9, MPP_GPIO }, /* RTC int */ 308 MPP9_GPIO, /* RTC int */
309 { 10, MPP_UNUSED }, 309 MPP10_UNUSED,
310 { 11, MPP_GPIO }, /* PCI Int A */ 310 MPP11_GPIO, /* PCI Int A */
311 { 12, MPP_UNUSED }, 311 MPP12_UNUSED,
312 { 13, MPP_GPIO }, /* UPS on UART0 enable */ 312 MPP13_GPIO, /* UPS on UART0 enable */
313 { 14, MPP_GPIO }, /* UPS low battery detection */ 313 MPP14_GPIO, /* UPS low battery detection */
314 { 15, MPP_UNUSED }, 314 MPP15_UNUSED,
315 { 16, MPP_UART }, /* UART1 RXD */ 315 MPP16_UART, /* UART1 RXD */
316 { 17, MPP_UART }, /* UART1 TXD */ 316 MPP17_UART, /* UART1 TXD */
317 { 18, MPP_UART }, /* UART1 CTSn */ 317 MPP18_UART, /* UART1 CTSn */
318 { 19, MPP_UART }, /* UART1 RTSn */ 318 MPP19_UART, /* UART1 RTSn */
319 { -1 }, 319 0,
320}; 320};
321 321
322static void __init tsp2_init(void) 322static void __init tsp2_init(void)
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index e6d64494d3de..47162fd5f044 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -244,28 +244,28 @@ static struct mv_sata_platform_data qnap_ts209_sata_data = {
244 244
245 * General Setup 245 * General Setup
246 ****************************************************************************/ 246 ****************************************************************************/
247static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = { 247static unsigned int ts209_mpp_modes[] __initdata = {
248 { 0, MPP_UNUSED }, 248 MPP0_UNUSED,
249 { 1, MPP_GPIO }, /* USB copy button */ 249 MPP1_GPIO, /* USB copy button */
250 { 2, MPP_GPIO }, /* Load defaults button */ 250 MPP2_GPIO, /* Load defaults button */
251 { 3, MPP_GPIO }, /* GPIO RTC */ 251 MPP3_GPIO, /* GPIO RTC */
252 { 4, MPP_UNUSED }, 252 MPP4_UNUSED,
253 { 5, MPP_UNUSED }, 253 MPP5_UNUSED,
254 { 6, MPP_GPIO }, /* PCI Int A */ 254 MPP6_GPIO, /* PCI Int A */
255 { 7, MPP_GPIO }, /* PCI Int B */ 255 MPP7_GPIO, /* PCI Int B */
256 { 8, MPP_UNUSED }, 256 MPP8_UNUSED,
257 { 9, MPP_UNUSED }, 257 MPP9_UNUSED,
258 { 10, MPP_UNUSED }, 258 MPP10_UNUSED,
259 { 11, MPP_UNUSED }, 259 MPP11_UNUSED,
260 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 260 MPP12_SATA_LED, /* SATA 0 presence */
261 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 261 MPP13_SATA_LED, /* SATA 1 presence */
262 { 14, MPP_SATA_LED }, /* SATA 0 active */ 262 MPP14_SATA_LED, /* SATA 0 active */
263 { 15, MPP_SATA_LED }, /* SATA 1 active */ 263 MPP15_SATA_LED, /* SATA 1 active */
264 { 16, MPP_UART }, /* UART1 RXD */ 264 MPP16_UART, /* UART1 RXD */
265 { 17, MPP_UART }, /* UART1 TXD */ 265 MPP17_UART, /* UART1 TXD */
266 { 18, MPP_GPIO }, /* SW_RST */ 266 MPP18_GPIO, /* SW_RST */
267 { 19, MPP_UNUSED }, 267 MPP19_UNUSED,
268 { -1 }, 268 0,
269}; 269};
270 270
271static void __init qnap_ts209_init(void) 271static void __init qnap_ts209_init(void)
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 9eac8192d923..5aacc7ac5cf4 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -242,28 +242,28 @@ static struct platform_device qnap_ts409_button_device = {
242/***************************************************************************** 242/*****************************************************************************
243 * General Setup 243 * General Setup
244 ****************************************************************************/ 244 ****************************************************************************/
245static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = { 245static unsigned int ts409_mpp_modes[] __initdata = {
246 { 0, MPP_UNUSED }, 246 MPP0_UNUSED,
247 { 1, MPP_UNUSED }, 247 MPP1_UNUSED,
248 { 2, MPP_UNUSED }, 248 MPP2_UNUSED,
249 { 3, MPP_UNUSED }, 249 MPP3_UNUSED,
250 { 4, MPP_GPIO }, /* HDD 1 status */ 250 MPP4_GPIO, /* HDD 1 status */
251 { 5, MPP_GPIO }, /* HDD 2 status */ 251 MPP5_GPIO, /* HDD 2 status */
252 { 6, MPP_GPIO }, /* HDD 3 status */ 252 MPP6_GPIO, /* HDD 3 status */
253 { 7, MPP_GPIO }, /* HDD 4 status */ 253 MPP7_GPIO, /* HDD 4 status */
254 { 8, MPP_UNUSED }, 254 MPP8_UNUSED,
255 { 9, MPP_UNUSED }, 255 MPP9_UNUSED,
256 { 10, MPP_GPIO }, /* RTC int */ 256 MPP10_GPIO, /* RTC int */
257 { 11, MPP_UNUSED }, 257 MPP11_UNUSED,
258 { 12, MPP_UNUSED }, 258 MPP12_UNUSED,
259 { 13, MPP_UNUSED }, 259 MPP13_UNUSED,
260 { 14, MPP_GPIO }, /* SW_RST */ 260 MPP14_GPIO, /* SW_RST */
261 { 15, MPP_GPIO }, /* USB copy button */ 261 MPP15_GPIO, /* USB copy button */
262 { 16, MPP_UART }, /* UART1 RXD */ 262 MPP16_UART, /* UART1 RXD */
263 { 17, MPP_UART }, /* UART1 TXD */ 263 MPP17_UART, /* UART1 TXD */
264 { 18, MPP_UNUSED }, 264 MPP18_UNUSED,
265 { 19, MPP_UNUSED }, 265 MPP19_UNUSED,
266 { -1 }, 266 0,
267}; 267};
268 268
269static void __init qnap_ts409_init(void) 269static void __init qnap_ts409_init(void)
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index edb1dd2d1611..6b7b54116f30 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -557,27 +557,27 @@ static struct kobj_attribute ts78xx_fpga_attr =
557/***************************************************************************** 557/*****************************************************************************
558 * General Setup 558 * General Setup
559 ****************************************************************************/ 559 ****************************************************************************/
560static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { 560static unsigned int ts78xx_mpp_modes[] __initdata = {
561 { 0, MPP_UNUSED }, 561 MPP0_UNUSED,
562 { 1, MPP_GPIO }, /* JTAG Clock */ 562 MPP1_GPIO, /* JTAG Clock */
563 { 2, MPP_GPIO }, /* JTAG Data In */ 563 MPP2_GPIO, /* JTAG Data In */
564 { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */ 564 MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
565 { 4, MPP_GPIO }, /* JTAG Data Out */ 565 MPP4_GPIO, /* JTAG Data Out */
566 { 5, MPP_GPIO }, /* JTAG TMS */ 566 MPP5_GPIO, /* JTAG TMS */
567 { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ 567 MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
568 { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */ 568 MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
569 { 8, MPP_UNUSED }, 569 MPP8_UNUSED,
570 { 9, MPP_UNUSED }, 570 MPP9_UNUSED,
571 { 10, MPP_UNUSED }, 571 MPP10_UNUSED,
572 { 11, MPP_UNUSED }, 572 MPP11_UNUSED,
573 { 12, MPP_UNUSED }, 573 MPP12_UNUSED,
574 { 13, MPP_UNUSED }, 574 MPP13_UNUSED,
575 { 14, MPP_UNUSED }, 575 MPP14_UNUSED,
576 { 15, MPP_UNUSED }, 576 MPP15_UNUSED,
577 { 16, MPP_UART }, 577 MPP16_UART,
578 { 17, MPP_UART }, 578 MPP17_UART,
579 { 18, MPP_UART }, 579 MPP18_UART,
580 { 19, MPP_UART }, 580 MPP19_UART,
581 /* 581 /*
582 * MPP[20] PCI Clock Out 1 582 * MPP[20] PCI Clock Out 1
583 * MPP[21] PCI Clock Out 0 583 * MPP[21] PCI Clock Out 0
@@ -586,7 +586,7 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
586 * MPP[24] Unused 586 * MPP[24] Unused
587 * MPP[25] Unused 587 * MPP[25] Unused
588 */ 588 */
589 { -1 }, 589 0,
590}; 590};
591 591
592static void __init ts78xx_init(void) 592static void __init ts78xx_init(void)
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 4e5216be0745..444a1c7fdfd6 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -24,28 +24,28 @@
24#include "common.h" 24#include "common.h"
25#include "mpp.h" 25#include "mpp.h"
26 26
27static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = { 27static unsigned int wnr854t_mpp_modes[] __initdata = {
28 { 0, MPP_GPIO }, /* Power LED green (0=on) */ 28 MPP0_GPIO, /* Power LED green (0=on) */
29 { 1, MPP_GPIO }, /* Reset Button (0=off) */ 29 MPP1_GPIO, /* Reset Button (0=off) */
30 { 2, MPP_GPIO }, /* Power LED blink (0=off) */ 30 MPP2_GPIO, /* Power LED blink (0=off) */
31 { 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */ 31 MPP3_GPIO, /* WAN Status LED amber (0=off) */
32 { 4, MPP_GPIO }, /* PCI int */ 32 MPP4_GPIO, /* PCI int */
33 { 5, MPP_GPIO }, /* ??? */ 33 MPP5_GPIO, /* ??? */
34 { 6, MPP_GPIO }, /* ??? */ 34 MPP6_GPIO, /* ??? */
35 { 7, MPP_GPIO }, /* ??? */ 35 MPP7_GPIO, /* ??? */
36 { 8, MPP_UNUSED }, /* ??? */ 36 MPP8_UNUSED, /* ??? */
37 { 9, MPP_GIGE }, /* GE_RXERR */ 37 MPP9_GIGE, /* GE_RXERR */
38 { 10, MPP_UNUSED }, /* ??? */ 38 MPP10_UNUSED, /* ??? */
39 { 11, MPP_UNUSED }, /* ??? */ 39 MPP11_UNUSED, /* ??? */
40 { 12, MPP_GIGE }, /* GE_TXD[4] */ 40 MPP12_GIGE, /* GE_TXD[4] */
41 { 13, MPP_GIGE }, /* GE_TXD[5] */ 41 MPP13_GIGE, /* GE_TXD[5] */
42 { 14, MPP_GIGE }, /* GE_TXD[6] */ 42 MPP14_GIGE, /* GE_TXD[6] */
43 { 15, MPP_GIGE }, /* GE_TXD[7] */ 43 MPP15_GIGE, /* GE_TXD[7] */
44 { 16, MPP_GIGE }, /* GE_RXD[4] */ 44 MPP16_GIGE, /* GE_RXD[4] */
45 { 17, MPP_GIGE }, /* GE_RXD[5] */ 45 MPP17_GIGE, /* GE_RXD[5] */
46 { 18, MPP_GIGE }, /* GE_RXD[6] */ 46 MPP18_GIGE, /* GE_RXD[6] */
47 { 19, MPP_GIGE }, /* GE_RXD[7] */ 47 MPP19_GIGE, /* GE_RXD[7] */
48 { -1 }, 48 0,
49}; 49};
50 50
51/* 51/*
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fab79d09cc5c..d1952be0ae1c 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -101,28 +101,28 @@ static struct platform_device wrt350n_v2_button_device = {
101/* 101/*
102 * General setup 102 * General setup
103 */ 103 */
104static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = { 104static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
105 { 0, MPP_GPIO }, /* Power LED green (0=on) */ 105 MPP0_GPIO, /* Power LED green (0=on) */
106 { 1, MPP_GPIO }, /* Security LED (0=on) */ 106 MPP1_GPIO, /* Security LED (0=on) */
107 { 2, MPP_GPIO }, /* Internal Button (0=on) */ 107 MPP2_GPIO, /* Internal Button (0=on) */
108 { 3, MPP_GPIO }, /* Reset Button (0=on) */ 108 MPP3_GPIO, /* Reset Button (0=on) */
109 { 4, MPP_GPIO }, /* PCI int */ 109 MPP4_GPIO, /* PCI int */
110 { 5, MPP_GPIO }, /* Power LED orange (0=on) */ 110 MPP5_GPIO, /* Power LED orange (0=on) */
111 { 6, MPP_GPIO }, /* USB LED (0=on) */ 111 MPP6_GPIO, /* USB LED (0=on) */
112 { 7, MPP_GPIO }, /* Wireless LED (0=on) */ 112 MPP7_GPIO, /* Wireless LED (0=on) */
113 { 8, MPP_UNUSED }, /* ??? */ 113 MPP8_UNUSED, /* ??? */
114 { 9, MPP_GIGE }, /* GE_RXERR */ 114 MPP9_GIGE, /* GE_RXERR */
115 { 10, MPP_UNUSED }, /* ??? */ 115 MPP10_UNUSED, /* ??? */
116 { 11, MPP_UNUSED }, /* ??? */ 116 MPP11_UNUSED, /* ??? */
117 { 12, MPP_GIGE }, /* GE_TXD[4] */ 117 MPP12_GIGE, /* GE_TXD[4] */
118 { 13, MPP_GIGE }, /* GE_TXD[5] */ 118 MPP13_GIGE, /* GE_TXD[5] */
119 { 14, MPP_GIGE }, /* GE_TXD[6] */ 119 MPP14_GIGE, /* GE_TXD[6] */
120 { 15, MPP_GIGE }, /* GE_TXD[7] */ 120 MPP15_GIGE, /* GE_TXD[7] */
121 { 16, MPP_GIGE }, /* GE_RXD[4] */ 121 MPP16_GIGE, /* GE_RXD[4] */
122 { 17, MPP_GIGE }, /* GE_RXD[5] */ 122 MPP17_GIGE, /* GE_RXD[5] */
123 { 18, MPP_GIGE }, /* GE_RXD[6] */ 123 MPP18_GIGE, /* GE_RXD[6] */
124 { 19, MPP_GIGE }, /* GE_RXD[7] */ 124 MPP19_GIGE, /* GE_RXD[7] */
125 { -1 }, 125 0,
126}; 126};
127 127
128/* 128/*
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 8b1a30959fae..1afc0fb7d6d5 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -29,33 +29,6 @@
29unsigned long it8152_base_address; 29unsigned long it8152_base_address;
30static int cmx2xx_it8152_irq_gpio; 30static int cmx2xx_it8152_irq_gpio;
31 31
32/*
33 * Only first 64MB of memory can be accessed via PCI.
34 * We use GFP_DMA to allocate safe buffers to do map/unmap.
35 * This is really ugly and we need a better way of specifying
36 * DMA-capable regions of memory.
37 */
38void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
39 unsigned long *zhole_size)
40{
41 unsigned int sz = SZ_64M >> PAGE_SHIFT;
42
43 if (machine_is_armcore()) {
44 pr_info("Adjusting zones for CM-X2XX\n");
45
46 /*
47 * Only adjust if > 64M on current system
48 */
49 if (zone_size[0] <= sz)
50 return;
51
52 zone_size[1] = zone_size[0] - sz;
53 zone_size[0] = sz;
54 zhole_size[1] = zhole_size[0];
55 zhole_size[0] = 0;
56 }
57}
58
59static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) 32static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
60{ 33{
61 /* clear our parent irq */ 34 /* clear our parent irq */
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 9cdcca597924..f941a495a4a8 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -735,7 +735,7 @@ static struct platform_device bq24022 = {
735 * StrataFlash 735 * StrataFlash
736 */ 736 */
737 737
738static void hx4700_set_vpp(struct map_info *map, int vpp) 738static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
739{ 739{
740 gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp); 740 gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
741} 741}
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 7f68724dcc27..07734f37f8fd 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -17,14 +17,8 @@
17 */ 17 */
18#define PLAT_PHYS_OFFSET UL(0xa0000000) 18#define PLAT_PHYS_OFFSET UL(0xa0000000)
19 19
20#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 20#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
21void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); 21#define ARM_DMA_ZONE_SIZE SZ_64M
22
23#define arch_adjust_zones(size, holes) \
24 cmx2xx_pci_adjust_zones(size, holes)
25
26#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
27#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
28#endif 22#endif
29 23
30#endif 24#endif
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 759b851ec985..5519a34b667f 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -16,9 +16,9 @@
16#define BTUART_BASE (0x40200000) 16#define BTUART_BASE (0x40200000)
17#define STUART_BASE (0x40700000) 17#define STUART_BASE (0x40700000)
18 18
19static unsigned long uart_base; 19unsigned long uart_base;
20static unsigned int uart_shift; 20unsigned int uart_shift;
21static unsigned int uart_is_pxa; 21unsigned int uart_is_pxa;
22 22
23static inline unsigned char uart_read(int offset) 23static inline unsigned char uart_read(int offset)
24{ 24{
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 9984ef70bd79..e1920572948a 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -662,7 +662,7 @@ static struct pxaohci_platform_data magician_ohci_info = {
662 * StrataFlash 662 * StrataFlash
663 */ 663 */
664 664
665static void magician_set_vpp(struct map_info *map, int vpp) 665static void magician_set_vpp(struct platform_device *pdev, int vpp)
666{ 666{
667 gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); 667 gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
668} 668}
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 428da3ff33a5..de684701449c 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -105,19 +105,6 @@ static struct clock_event_device ckevt_pxa_osmr0 = {
105 .set_mode = pxa_osmr0_set_mode, 105 .set_mode = pxa_osmr0_set_mode,
106}; 106};
107 107
108static cycle_t pxa_read_oscr(struct clocksource *cs)
109{
110 return OSCR;
111}
112
113static struct clocksource cksrc_pxa_oscr0 = {
114 .name = "oscr0",
115 .rating = 200,
116 .read = pxa_read_oscr,
117 .mask = CLOCKSOURCE_MASK(32),
118 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
119};
120
121static struct irqaction pxa_ost0_irq = { 108static struct irqaction pxa_ost0_irq = {
122 .name = "ost0", 109 .name = "ost0",
123 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 110 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
@@ -134,7 +121,6 @@ static void __init pxa_timer_init(void)
134 121
135 init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); 122 init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
136 123
137 clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4);
138 clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); 124 clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
139 ckevt_pxa_osmr0.max_delta_ns = 125 ckevt_pxa_osmr0.max_delta_ns =
140 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); 126 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
@@ -144,7 +130,8 @@ static void __init pxa_timer_init(void)
144 130
145 setup_irq(IRQ_OST0, &pxa_ost0_irq); 131 setup_irq(IRQ_OST0, &pxa_ost0_irq);
146 132
147 clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate); 133 clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
134 clocksource_mmio_readl_up);
148 clockevents_register_device(&ckevt_pxa_osmr0); 135 clockevents_register_device(&ckevt_pxa_osmr0);
149} 136}
150 137
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 75dbc8791d05..5c23450d2d1d 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -31,6 +31,7 @@
31#include <linux/amba/mmci.h> 31#include <linux/amba/mmci.h>
32#include <linux/gfp.h> 32#include <linux/gfp.h>
33#include <linux/clkdev.h> 33#include <linux/clkdev.h>
34#include <linux/mtd/physmap.h>
34 35
35#include <asm/system.h> 36#include <asm/system.h>
36#include <mach/hardware.h> 37#include <mach/hardware.h>
@@ -41,7 +42,6 @@
41#include <asm/hardware/icst.h> 42#include <asm/hardware/icst.h>
42 43
43#include <asm/mach/arch.h> 44#include <asm/mach/arch.h>
44#include <asm/mach/flash.h>
45#include <asm/mach/irq.h> 45#include <asm/mach/irq.h>
46#include <asm/mach/map.h> 46#include <asm/mach/map.h>
47 47
@@ -56,48 +56,9 @@
56 56
57#include "core.h" 57#include "core.h"
58 58
59#ifdef CONFIG_ZONE_DMA
60/*
61 * Adjust the zones if there are restrictions for DMA access.
62 */
63void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
64{
65 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
66
67 if (!machine_is_realview_pbx() || size[0] <= dma_size)
68 return;
69
70 size[ZONE_NORMAL] = size[0] - dma_size;
71 size[ZONE_DMA] = dma_size;
72 hole[ZONE_NORMAL] = hole[0];
73 hole[ZONE_DMA] = 0;
74}
75#endif
76
77
78#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) 59#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
79 60
80static int realview_flash_init(void) 61static void realview_flash_set_vpp(struct platform_device *pdev, int on)
81{
82 u32 val;
83
84 val = __raw_readl(REALVIEW_FLASHCTRL);
85 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
86 __raw_writel(val, REALVIEW_FLASHCTRL);
87
88 return 0;
89}
90
91static void realview_flash_exit(void)
92{
93 u32 val;
94
95 val = __raw_readl(REALVIEW_FLASHCTRL);
96 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
97 __raw_writel(val, REALVIEW_FLASHCTRL);
98}
99
100static void realview_flash_set_vpp(int on)
101{ 62{
102 u32 val; 63 u32 val;
103 64
@@ -109,16 +70,13 @@ static void realview_flash_set_vpp(int on)
109 __raw_writel(val, REALVIEW_FLASHCTRL); 70 __raw_writel(val, REALVIEW_FLASHCTRL);
110} 71}
111 72
112static struct flash_platform_data realview_flash_data = { 73static struct physmap_flash_data realview_flash_data = {
113 .map_name = "cfi_probe",
114 .width = 4, 74 .width = 4,
115 .init = realview_flash_init,
116 .exit = realview_flash_exit,
117 .set_vpp = realview_flash_set_vpp, 75 .set_vpp = realview_flash_set_vpp,
118}; 76};
119 77
120struct platform_device realview_flash_device = { 78struct platform_device realview_flash_device = {
121 .name = "armflash", 79 .name = "physmap-flash",
122 .id = 0, 80 .id = 0,
123 .dev = { 81 .dev = {
124 .platform_data = &realview_flash_data, 82 .platform_data = &realview_flash_data,
@@ -315,6 +273,10 @@ static struct clk ref24_clk = {
315 .rate = 24000000, 273 .rate = 24000000,
316}; 274};
317 275
276static struct clk sp804_clk = {
277 .rate = 1000000,
278};
279
318static struct clk dummy_apb_pclk; 280static struct clk dummy_apb_pclk;
319 281
320static struct clk_lookup lookups[] = { 282static struct clk_lookup lookups[] = {
@@ -357,7 +319,10 @@ static struct clk_lookup lookups[] = {
357 }, { /* SSP */ 319 }, { /* SSP */
358 .dev_id = "dev:ssp0", 320 .dev_id = "dev:ssp0",
359 .clk = &ref24_clk, 321 .clk = &ref24_clk,
360 } 322 }, { /* SP804 timers */
323 .dev_id = "sp804",
324 .clk = &sp804_clk,
325 },
361}; 326};
362 327
363void __init realview_init_early(void) 328void __init realview_init_early(void)
@@ -545,8 +510,8 @@ void __init realview_timer_init(unsigned int timer_irq)
545 writel(0, timer2_va_base + TIMER_CTRL); 510 writel(0, timer2_va_base + TIMER_CTRL);
546 writel(0, timer3_va_base + TIMER_CTRL); 511 writel(0, timer3_va_base + TIMER_CTRL);
547 512
548 sp804_clocksource_init(timer3_va_base); 513 sp804_clocksource_init(timer3_va_base, "timer3");
549 sp804_clockevents_init(timer0_va_base, timer_irq); 514 sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
550} 515}
551 516
552/* 517/*
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index e05fc2c4c080..1759fa673eea 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -29,13 +29,8 @@
29#define PLAT_PHYS_OFFSET UL(0x00000000) 29#define PLAT_PHYS_OFFSET UL(0x00000000)
30#endif 30#endif
31 31
32#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) 32#ifdef CONFIG_ZONE_DMA
33extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); 33#define ARM_DMA_ZONE_SIZE SZ_256M
34#define arch_adjust_zones(size, hole) \
35 realview_adjust_zones(size, hole)
36
37#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1)
38#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
39#endif 34#endif
40 35
41#ifdef CONFIG_SPARSEMEM 36#ifdef CONFIG_SPARSEMEM
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
deleted file mode 100644
index c8221b38ee7c..000000000000
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11 gic_raise_softirq(mask, ipi);
12}
13
14#endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 23919229e12d..963bf0d8119a 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15 15
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <asm/hardware/gic.h>
17#include <asm/mach-types.h> 18#include <asm/mach-types.h>
18#include <asm/smp_scu.h> 19#include <asm/smp_scu.h>
19#include <asm/unified.h> 20#include <asm/unified.h>
@@ -61,6 +62,8 @@ void __init smp_init_cpus(void)
61 62
62 for (i = 0; i < ncores; i++) 63 for (i = 0; i < ncores; i++)
63 set_cpu_possible(i, true); 64 set_cpu_possible(i, true);
65
66 set_smp_cross_call(gic_raise_softirq);
64} 67}
65 68
66void __init platform_smp_prepare_cpus(unsigned int max_cpus) 69void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index 8c9e2c7161c6..9cd9bcdad6cc 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -66,12 +66,12 @@ extern __attribute__((pure)) struct param_struct *params(void);
66#define params (params()) 66#define params (params())
67 67
68#ifndef STANDALONE_DEBUG 68#ifndef STANDALONE_DEBUG
69static unsigned long video_num_cols; 69unsigned long video_num_cols;
70static unsigned long video_num_rows; 70unsigned long video_num_rows;
71static unsigned long video_x; 71unsigned long video_x;
72static unsigned long video_y; 72unsigned long video_y;
73static unsigned char bytes_per_char_v; 73unsigned char bytes_per_char_v;
74static int white; 74int white;
75 75
76/* 76/*
77 * This does not append a newline 77 * This does not append a newline
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
index 598d130633dc..ad9f750f1e55 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -32,7 +32,7 @@
32 32
33#include "nor-simtec.h" 33#include "nor-simtec.h"
34 34
35static void simtec_nor_vpp(struct map_info *map, int vpp) 35static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
36{ 36{
37 unsigned int val; 37 unsigned int val;
38 unsigned long flags; 38 unsigned long flags;
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 67a145d440f3..97660c8141ae 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -58,12 +58,7 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
58 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); 58 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
59 59
60 /* add the timer sub-irqs */ 60 /* add the timer sub-irqs */
61 61 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
62 s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
63 s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
64 s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
65 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
66 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
67 62
68 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); 63 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
69} 64}
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index c65b229aab23..1608faf870ff 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -24,8 +24,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
24 24
25/* uart setup */ 25/* uart setup */
26 26
27static unsigned int fifo_mask; 27unsigned int fifo_mask;
28static unsigned int fifo_max; 28unsigned int fifo_max;
29 29
30/* forward declerations */ 30/* forward declerations */
31 31
@@ -43,7 +43,7 @@ static void arch_detect_cpu(void);
43/* how many bytes we allow into the FIFO at a time in FIFO mode */ 43/* how many bytes we allow into the FIFO at a time in FIFO mode */
44#define FIFO_MAX (14) 44#define FIFO_MAX (14)
45 45
46static unsigned long uart_base; 46unsigned long uart_base;
47 47
48static __inline__ void get_uart_base(void) 48static __inline__ void get_uart_base(void)
49{ 49{
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index a44da6a2916c..cff31ee246b7 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -14,18 +14,8 @@
14 */ 14 */
15#define PLAT_PHYS_OFFSET UL(0xc0000000) 15#define PLAT_PHYS_OFFSET UL(0xc0000000)
16 16
17#ifndef __ASSEMBLY__
18
19#ifdef CONFIG_SA1111 17#ifdef CONFIG_SA1111
20void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); 18#define ARM_DMA_ZONE_SIZE SZ_1M
21
22#define arch_adjust_zones(size, holes) \
23 sa1111_adjust_zones(size, holes)
24
25#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1)
26#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M)
27
28#endif
29#endif 19#endif
30 20
31/* 21/*
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index ae4f3d80416f..fa6602491d54 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -92,25 +92,11 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
92static struct clock_event_device ckevt_sa1100_osmr0 = { 92static struct clock_event_device ckevt_sa1100_osmr0 = {
93 .name = "osmr0", 93 .name = "osmr0",
94 .features = CLOCK_EVT_FEAT_ONESHOT, 94 .features = CLOCK_EVT_FEAT_ONESHOT,
95 .shift = 32,
96 .rating = 200, 95 .rating = 200,
97 .set_next_event = sa1100_osmr0_set_next_event, 96 .set_next_event = sa1100_osmr0_set_next_event,
98 .set_mode = sa1100_osmr0_set_mode, 97 .set_mode = sa1100_osmr0_set_mode,
99}; 98};
100 99
101static cycle_t sa1100_read_oscr(struct clocksource *s)
102{
103 return OSCR;
104}
105
106static struct clocksource cksrc_sa1100_oscr = {
107 .name = "oscr",
108 .rating = 200,
109 .read = sa1100_read_oscr,
110 .mask = CLOCKSOURCE_MASK(32),
111 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
112};
113
114static struct irqaction sa1100_timer_irq = { 100static struct irqaction sa1100_timer_irq = {
115 .name = "ost0", 101 .name = "ost0",
116 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 102 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
@@ -120,14 +106,13 @@ static struct irqaction sa1100_timer_irq = {
120 106
121static void __init sa1100_timer_init(void) 107static void __init sa1100_timer_init(void)
122{ 108{
123 OIER = 0; /* disable any timer interrupts */ 109 OIER = 0;
124 OSSR = 0xf; /* clear status on all timers */ 110 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
125 111
126 init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32, 112 init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32,
127 3686400, SC_MULT, SC_SHIFT); 113 3686400, SC_MULT, SC_SHIFT);
128 114
129 ckevt_sa1100_osmr0.mult = 115 clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
130 div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
131 ckevt_sa1100_osmr0.max_delta_ns = 116 ckevt_sa1100_osmr0.max_delta_ns =
132 clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); 117 clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
133 ckevt_sa1100_osmr0.min_delta_ns = 118 ckevt_sa1100_osmr0.min_delta_ns =
@@ -136,7 +121,8 @@ static void __init sa1100_timer_init(void)
136 121
137 setup_irq(IRQ_OST0, &sa1100_timer_irq); 122 setup_irq(IRQ_OST0, &sa1100_timer_irq);
138 123
139 clocksource_register_hz(&cksrc_sa1100_oscr, CLOCK_TICK_RATE); 124 clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
125 clocksource_mmio_readl_up);
140 clockevents_register_device(&ckevt_sa1100_osmr0); 126 clockevents_register_device(&ckevt_sa1100_osmr0);
141} 127}
142 128
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index 9afb17000008..4c0831f83b0c 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -17,25 +17,7 @@
17 */ 17 */
18#define PLAT_PHYS_OFFSET UL(0x08000000) 18#define PLAT_PHYS_OFFSET UL(0x08000000)
19 19
20#ifndef __ASSEMBLY__ 20#define ARM_DMA_ZONE_SIZE SZ_4M
21
22static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size)
23{
24 /* Only the first 4 MB (=1024 Pages) are usable for DMA */
25 /* See dev / -> .properties in OpenFirmware. */
26 zone_size[1] = zone_size[0] - 1024;
27 zone_size[0] = 1024;
28 zhole_size[1] = zhole_size[0];
29 zhole_size[0] = 0;
30}
31
32#define arch_adjust_zones(size, holes) \
33 __arch_adjust_zones(size, holes)
34
35#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1)
36#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M)
37
38#endif
39 21
40/* 22/*
41 * Cache flushing area 23 * Cache flushing area
diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h
deleted file mode 100644
index 50db94e927ad..000000000000
--- a/arch/arm/mach-shmobile/include/mach/smp.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __MACH_SMP_H
2#define __MACH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11#if defined(CONFIG_ARM_GIC)
12 gic_raise_softirq(mask, ipi);
13#endif
14}
15
16#endif
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 65e879bab4dc..f3888feb1c68 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -16,6 +16,7 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <asm/hardware/gic.h>
19#include <asm/localtimer.h> 20#include <asm/localtimer.h>
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <mach/common.h> 22#include <mach/common.h>
@@ -57,6 +58,8 @@ void __init smp_init_cpus(void)
57 58
58 for (i = 0; i < ncores; i++) 59 for (i = 0; i < ncores; i++)
59 set_cpu_possible(i, true); 60 set_cpu_possible(i, true);
61
62 set_smp_cross_call(gic_raise_softirq);
60} 63}
61 64
62void __init platform_smp_prepare_cpus(unsigned int max_cpus) 65void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 20d1317cc486..2cee6b0de371 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -4,9 +4,26 @@
4 4
5if ARCH_SPEAR3XX 5if ARCH_SPEAR3XX
6 6
7choice 7menu "SPEAr3xx Implementations"
8 prompt "SPEAr3XX Family" 8config BOARD_SPEAR300_EVB
9 default MACH_SPEAR300 9 bool "SPEAr300 Evaluation Board"
10 select MACH_SPEAR300
11 help
12 Supports ST SPEAr300 Evaluation Board
13
14config BOARD_SPEAR310_EVB
15 bool "SPEAr310 Evaluation Board"
16 select MACH_SPEAR310
17 help
18 Supports ST SPEAr310 Evaluation Board
19
20config BOARD_SPEAR320_EVB
21 bool "SPEAr320 Evaluation Board"
22 select MACH_SPEAR320
23 help
24 Supports ST SPEAr320 Evaluation Board
25
26endmenu
10 27
11config MACH_SPEAR300 28config MACH_SPEAR300
12 bool "SPEAr300" 29 bool "SPEAr300"
@@ -23,11 +40,4 @@ config MACH_SPEAR320
23 help 40 help
24 Supports ST SPEAr320 Machine 41 Supports ST SPEAr320 Machine
25 42
26endchoice
27
28# Adding SPEAr3XX machine specific configuration files
29source "arch/arm/mach-spear3xx/Kconfig300"
30source "arch/arm/mach-spear3xx/Kconfig310"
31source "arch/arm/mach-spear3xx/Kconfig320"
32
33endif #ARCH_SPEAR3XX 43endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300
deleted file mode 100644
index c519a05b4ab4..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig300
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# SPEAr300 machine configuration file
3#
4
5if MACH_SPEAR300
6
7choice
8 prompt "SPEAr300 Boards"
9 default BOARD_SPEAR300_EVB
10
11config BOARD_SPEAR300_EVB
12 bool "SPEAr300 Evaluation Board"
13 help
14 Supports ST SPEAr300 Evaluation Board
15endchoice
16
17endif #MACH_SPEAR300
diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310
deleted file mode 100644
index 60e7442d75bd..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig310
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# SPEAr310 machine configuration file
3#
4
5if MACH_SPEAR310
6
7choice
8 prompt "SPEAr310 Boards"
9 default BOARD_SPEAR310_EVB
10
11config BOARD_SPEAR310_EVB
12 bool "SPEAr310 Evaluation Board"
13 help
14 Supports ST SPEAr310 Evaluation Board
15endchoice
16
17endif #MACH_SPEAR310
diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320
deleted file mode 100644
index 1c1d438399b8..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig320
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# SPEAr320 machine configuration file
3#
4
5if MACH_SPEAR320
6
7choice
8 prompt "SPEAr320 Boards"
9 default BOARD_SPEAR320_EVB
10
11config BOARD_SPEAR320_EVB
12 bool "SPEAr320 Evaluation Board"
13 help
14 Supports ST SPEAr320 Evaluation Board
15endchoice
16
17endif #MACH_SPEAR320
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 98bc7edc95a6..f67860cd649f 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -13,6 +13,7 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <asm/mach-types.h>
16#include <plat/clock.h> 17#include <plat/clock.h>
17#include <mach/misc_regs.h> 18#include <mach/misc_regs.h>
18 19
@@ -688,56 +689,71 @@ static struct clk_lookup spear_clk_lookups[] = {
688 { .dev_id = "adc", .clk = &adc_clk}, 689 { .dev_id = "adc", .clk = &adc_clk},
689 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, 690 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
690 { .dev_id = "gpio", .clk = &gpio_clk}, 691 { .dev_id = "gpio", .clk = &gpio_clk},
691#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 692};
692 { .dev_id = "physmap-flash", .clk = &emi_clk},
693#endif
694#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
695 defined(CONFIG_MACH_SPEAR320)
696 { .con_id = "fsmc", .clk = &fsmc_clk},
697#endif
698
699/* common clocks to spear310 and spear320 */
700#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
701 { .dev_id = "uart1", .clk = &uart1_clk},
702 { .dev_id = "uart2", .clk = &uart2_clk},
703#endif
704
705 /* common clock to spear300 and spear320 */
706#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
707 { .dev_id = "clcd", .clk = &clcd_clk},
708 { .dev_id = "sdhci", .clk = &sdhci_clk},
709#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
710 693
711 /* spear300 machine specific clock structures */ 694/* array of all spear 300 clock lookups */
712#ifdef CONFIG_MACH_SPEAR300 695#ifdef CONFIG_MACH_SPEAR300
696static struct clk_lookup spear300_clk_lookups[] = {
697 { .dev_id = "clcd", .clk = &clcd_clk},
698 { .con_id = "fsmc", .clk = &fsmc_clk},
713 { .dev_id = "gpio1", .clk = &gpio1_clk}, 699 { .dev_id = "gpio1", .clk = &gpio1_clk},
714 { .dev_id = "keyboard", .clk = &kbd_clk}, 700 { .dev_id = "keyboard", .clk = &kbd_clk},
701 { .dev_id = "sdhci", .clk = &sdhci_clk},
702};
715#endif 703#endif
716 704
717 /* spear310 machine specific clock structures */ 705/* array of all spear 310 clock lookups */
718#ifdef CONFIG_MACH_SPEAR310 706#ifdef CONFIG_MACH_SPEAR310
707static struct clk_lookup spear310_clk_lookups[] = {
708 { .con_id = "fsmc", .clk = &fsmc_clk},
709 { .con_id = "emi", .clk = &emi_clk},
710 { .dev_id = "uart1", .clk = &uart1_clk},
711 { .dev_id = "uart2", .clk = &uart2_clk},
719 { .dev_id = "uart3", .clk = &uart3_clk}, 712 { .dev_id = "uart3", .clk = &uart3_clk},
720 { .dev_id = "uart4", .clk = &uart4_clk}, 713 { .dev_id = "uart4", .clk = &uart4_clk},
721 { .dev_id = "uart5", .clk = &uart5_clk}, 714 { .dev_id = "uart5", .clk = &uart5_clk},
722 715};
723#endif 716#endif
724 /* spear320 machine specific clock structures */ 717
718/* array of all spear 320 clock lookups */
725#ifdef CONFIG_MACH_SPEAR320 719#ifdef CONFIG_MACH_SPEAR320
720static struct clk_lookup spear320_clk_lookups[] = {
721 { .dev_id = "clcd", .clk = &clcd_clk},
722 { .con_id = "fsmc", .clk = &fsmc_clk},
723 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
724 { .con_id = "emi", .clk = &emi_clk},
725 { .dev_id = "pwm", .clk = &pwm_clk},
726 { .dev_id = "sdhci", .clk = &sdhci_clk},
726 { .dev_id = "c_can_platform.0", .clk = &can0_clk}, 727 { .dev_id = "c_can_platform.0", .clk = &can0_clk},
727 { .dev_id = "c_can_platform.1", .clk = &can1_clk}, 728 { .dev_id = "c_can_platform.1", .clk = &can1_clk},
728 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
729 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, 729 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
730 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, 730 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
731 { .dev_id = "pwm", .clk = &pwm_clk}, 731 { .dev_id = "uart1", .clk = &uart1_clk},
732#endif 732 { .dev_id = "uart2", .clk = &uart2_clk},
733}; 733};
734#endif
734 735
735void __init clk_init(void) 736void __init spear3xx_clk_init(void)
736{ 737{
737 int i; 738 int i, cnt;
739 struct clk_lookup *lookups;
740
741 if (machine_is_spear300()) {
742 cnt = ARRAY_SIZE(spear300_clk_lookups);
743 lookups = spear300_clk_lookups;
744 } else if (machine_is_spear310()) {
745 cnt = ARRAY_SIZE(spear310_clk_lookups);
746 lookups = spear310_clk_lookups;
747 } else {
748 cnt = ARRAY_SIZE(spear320_clk_lookups);
749 lookups = spear320_clk_lookups;
750 }
738 751
739 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) 752 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
740 clk_register(&spear_clk_lookups[i]); 753 clk_register(&spear_clk_lookups[i]);
741 754
742 recalc_root_clocks(); 755 for (i = 0; i < cnt; i++)
756 clk_register(&lookups[i]);
757
758 clk_init();
743} 759}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 8e30636909ef..b8f31c3935f7 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,16 +27,16 @@
27 * Following GPT channels will be used as clock source and clockevent 27 * Following GPT channels will be used as clock source and clockevent
28 */ 28 */
29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE 29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
30#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 30#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
31#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32 32
33/* Add spear3xx family device structure declarations here */ 33/* Add spear3xx family device structure declarations here */
34extern struct amba_device gpio_device; 34extern struct amba_device spear3xx_gpio_device;
35extern struct amba_device uart_device; 35extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 36extern struct sys_timer spear3xx_timer;
37 37
38/* Add spear3xx family function declarations here */ 38/* Add spear3xx family function declarations here */
39void __init clk_init(void); 39void __init spear3xx_clk_init(void);
40void __init spear_setup_timer(void); 40void __init spear_setup_timer(void);
41void __init spear3xx_map_io(void); 41void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 42void __init spear3xx_init_irq(void);
@@ -60,81 +60,80 @@ void __init spear3xx_init(void);
60#define PMX_TIMER_1_2_MASK (1 << 0) 60#define PMX_TIMER_1_2_MASK (1 << 0)
61 61
62/* pad mux devices */ 62/* pad mux devices */
63extern struct pmx_dev pmx_firda; 63extern struct pmx_dev spear3xx_pmx_firda;
64extern struct pmx_dev pmx_i2c; 64extern struct pmx_dev spear3xx_pmx_i2c;
65extern struct pmx_dev pmx_ssp_cs; 65extern struct pmx_dev spear3xx_pmx_ssp_cs;
66extern struct pmx_dev pmx_ssp; 66extern struct pmx_dev spear3xx_pmx_ssp;
67extern struct pmx_dev pmx_mii; 67extern struct pmx_dev spear3xx_pmx_mii;
68extern struct pmx_dev pmx_gpio_pin0; 68extern struct pmx_dev spear3xx_pmx_gpio_pin0;
69extern struct pmx_dev pmx_gpio_pin1; 69extern struct pmx_dev spear3xx_pmx_gpio_pin1;
70extern struct pmx_dev pmx_gpio_pin2; 70extern struct pmx_dev spear3xx_pmx_gpio_pin2;
71extern struct pmx_dev pmx_gpio_pin3; 71extern struct pmx_dev spear3xx_pmx_gpio_pin3;
72extern struct pmx_dev pmx_gpio_pin4; 72extern struct pmx_dev spear3xx_pmx_gpio_pin4;
73extern struct pmx_dev pmx_gpio_pin5; 73extern struct pmx_dev spear3xx_pmx_gpio_pin5;
74extern struct pmx_dev pmx_uart0_modem; 74extern struct pmx_dev spear3xx_pmx_uart0_modem;
75extern struct pmx_dev pmx_uart0; 75extern struct pmx_dev spear3xx_pmx_uart0;
76extern struct pmx_dev pmx_timer_3_4; 76extern struct pmx_dev spear3xx_pmx_timer_3_4;
77extern struct pmx_dev pmx_timer_1_2; 77extern struct pmx_dev spear3xx_pmx_timer_1_2;
78 78
79#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 79#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
80/* padmux plgpio devices */ 80/* padmux plgpio devices */
81extern struct pmx_dev pmx_plgpio_0_1; 81extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
82extern struct pmx_dev pmx_plgpio_2_3; 82extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
83extern struct pmx_dev pmx_plgpio_4_5; 83extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
84extern struct pmx_dev pmx_plgpio_6_9; 84extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
85extern struct pmx_dev pmx_plgpio_10_27; 85extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
86extern struct pmx_dev pmx_plgpio_28; 86extern struct pmx_dev spear3xx_pmx_plgpio_28;
87extern struct pmx_dev pmx_plgpio_29; 87extern struct pmx_dev spear3xx_pmx_plgpio_29;
88extern struct pmx_dev pmx_plgpio_30; 88extern struct pmx_dev spear3xx_pmx_plgpio_30;
89extern struct pmx_dev pmx_plgpio_31; 89extern struct pmx_dev spear3xx_pmx_plgpio_31;
90extern struct pmx_dev pmx_plgpio_32; 90extern struct pmx_dev spear3xx_pmx_plgpio_32;
91extern struct pmx_dev pmx_plgpio_33; 91extern struct pmx_dev spear3xx_pmx_plgpio_33;
92extern struct pmx_dev pmx_plgpio_34_36; 92extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
93extern struct pmx_dev pmx_plgpio_37_42; 93extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
94extern struct pmx_dev pmx_plgpio_43_44_47_48; 94extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
95extern struct pmx_dev pmx_plgpio_45_46_49_50; 95extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
96#endif 96#endif
97 97
98extern struct pmx_driver pmx_driver;
99
100/* spear300 declarations */ 98/* spear300 declarations */
101#ifdef CONFIG_MACH_SPEAR300 99#ifdef CONFIG_MACH_SPEAR300
102/* Add spear300 machine device structure declarations here */ 100/* Add spear300 machine device structure declarations here */
103extern struct amba_device gpio1_device; 101extern struct amba_device spear300_gpio1_device;
104 102
105/* pad mux modes */ 103/* pad mux modes */
106extern struct pmx_mode nand_mode; 104extern struct pmx_mode spear300_nand_mode;
107extern struct pmx_mode nor_mode; 105extern struct pmx_mode spear300_nor_mode;
108extern struct pmx_mode photo_frame_mode; 106extern struct pmx_mode spear300_photo_frame_mode;
109extern struct pmx_mode lend_ip_phone_mode; 107extern struct pmx_mode spear300_lend_ip_phone_mode;
110extern struct pmx_mode hend_ip_phone_mode; 108extern struct pmx_mode spear300_hend_ip_phone_mode;
111extern struct pmx_mode lend_wifi_phone_mode; 109extern struct pmx_mode spear300_lend_wifi_phone_mode;
112extern struct pmx_mode hend_wifi_phone_mode; 110extern struct pmx_mode spear300_hend_wifi_phone_mode;
113extern struct pmx_mode ata_pabx_wi2s_mode; 111extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
114extern struct pmx_mode ata_pabx_i2s_mode; 112extern struct pmx_mode spear300_ata_pabx_i2s_mode;
115extern struct pmx_mode caml_lcdw_mode; 113extern struct pmx_mode spear300_caml_lcdw_mode;
116extern struct pmx_mode camu_lcd_mode; 114extern struct pmx_mode spear300_camu_lcd_mode;
117extern struct pmx_mode camu_wlcd_mode; 115extern struct pmx_mode spear300_camu_wlcd_mode;
118extern struct pmx_mode caml_lcd_mode; 116extern struct pmx_mode spear300_caml_lcd_mode;
119 117
120/* pad mux devices */ 118/* pad mux devices */
121extern struct pmx_dev pmx_fsmc_2_chips; 119extern struct pmx_dev spear300_pmx_fsmc_2_chips;
122extern struct pmx_dev pmx_fsmc_4_chips; 120extern struct pmx_dev spear300_pmx_fsmc_4_chips;
123extern struct pmx_dev pmx_keyboard; 121extern struct pmx_dev spear300_pmx_keyboard;
124extern struct pmx_dev pmx_clcd; 122extern struct pmx_dev spear300_pmx_clcd;
125extern struct pmx_dev pmx_telecom_gpio; 123extern struct pmx_dev spear300_pmx_telecom_gpio;
126extern struct pmx_dev pmx_telecom_tdm; 124extern struct pmx_dev spear300_pmx_telecom_tdm;
127extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk; 125extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
128extern struct pmx_dev pmx_telecom_camera; 126extern struct pmx_dev spear300_pmx_telecom_camera;
129extern struct pmx_dev pmx_telecom_dac; 127extern struct pmx_dev spear300_pmx_telecom_dac;
130extern struct pmx_dev pmx_telecom_i2s; 128extern struct pmx_dev spear300_pmx_telecom_i2s;
131extern struct pmx_dev pmx_telecom_boot_pins; 129extern struct pmx_dev spear300_pmx_telecom_boot_pins;
132extern struct pmx_dev pmx_telecom_sdhci_4bit; 130extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
133extern struct pmx_dev pmx_telecom_sdhci_8bit; 131extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
134extern struct pmx_dev pmx_gpio1; 132extern struct pmx_dev spear300_pmx_gpio1;
135 133
136/* Add spear300 machine function declarations here */ 134/* Add spear300 machine function declarations here */
137void __init spear300_init(void); 135void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
136 u8 pmx_dev_count);
138 137
139#endif /* CONFIG_MACH_SPEAR300 */ 138#endif /* CONFIG_MACH_SPEAR300 */
140 139
@@ -143,17 +142,18 @@ void __init spear300_init(void);
143/* Add spear310 machine device structure declarations here */ 142/* Add spear310 machine device structure declarations here */
144 143
145/* pad mux devices */ 144/* pad mux devices */
146extern struct pmx_dev pmx_emi_cs_0_1_4_5; 145extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
147extern struct pmx_dev pmx_emi_cs_2_3; 146extern struct pmx_dev spear310_pmx_emi_cs_2_3;
148extern struct pmx_dev pmx_uart1; 147extern struct pmx_dev spear310_pmx_uart1;
149extern struct pmx_dev pmx_uart2; 148extern struct pmx_dev spear310_pmx_uart2;
150extern struct pmx_dev pmx_uart3_4_5; 149extern struct pmx_dev spear310_pmx_uart3_4_5;
151extern struct pmx_dev pmx_fsmc; 150extern struct pmx_dev spear310_pmx_fsmc;
152extern struct pmx_dev pmx_rs485_0_1; 151extern struct pmx_dev spear310_pmx_rs485_0_1;
153extern struct pmx_dev pmx_tdm0; 152extern struct pmx_dev spear310_pmx_tdm0;
154 153
155/* Add spear310 machine function declarations here */ 154/* Add spear310 machine function declarations here */
156void __init spear310_init(void); 155void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
156 u8 pmx_dev_count);
157 157
158#endif /* CONFIG_MACH_SPEAR310 */ 158#endif /* CONFIG_MACH_SPEAR310 */
159 159
@@ -162,37 +162,38 @@ void __init spear310_init(void);
162/* Add spear320 machine device structure declarations here */ 162/* Add spear320 machine device structure declarations here */
163 163
164/* pad mux modes */ 164/* pad mux modes */
165extern struct pmx_mode auto_net_smii_mode; 165extern struct pmx_mode spear320_auto_net_smii_mode;
166extern struct pmx_mode auto_net_mii_mode; 166extern struct pmx_mode spear320_auto_net_mii_mode;
167extern struct pmx_mode auto_exp_mode; 167extern struct pmx_mode spear320_auto_exp_mode;
168extern struct pmx_mode small_printers_mode; 168extern struct pmx_mode spear320_small_printers_mode;
169 169
170/* pad mux devices */ 170/* pad mux devices */
171extern struct pmx_dev pmx_clcd; 171extern struct pmx_dev spear320_pmx_clcd;
172extern struct pmx_dev pmx_emi; 172extern struct pmx_dev spear320_pmx_emi;
173extern struct pmx_dev pmx_fsmc; 173extern struct pmx_dev spear320_pmx_fsmc;
174extern struct pmx_dev pmx_spp; 174extern struct pmx_dev spear320_pmx_spp;
175extern struct pmx_dev pmx_sdhci; 175extern struct pmx_dev spear320_pmx_sdhci;
176extern struct pmx_dev pmx_i2s; 176extern struct pmx_dev spear320_pmx_i2s;
177extern struct pmx_dev pmx_uart1; 177extern struct pmx_dev spear320_pmx_uart1;
178extern struct pmx_dev pmx_uart1_modem; 178extern struct pmx_dev spear320_pmx_uart1_modem;
179extern struct pmx_dev pmx_uart2; 179extern struct pmx_dev spear320_pmx_uart2;
180extern struct pmx_dev pmx_touchscreen; 180extern struct pmx_dev spear320_pmx_touchscreen;
181extern struct pmx_dev pmx_can; 181extern struct pmx_dev spear320_pmx_can;
182extern struct pmx_dev pmx_sdhci_led; 182extern struct pmx_dev spear320_pmx_sdhci_led;
183extern struct pmx_dev pmx_pwm0; 183extern struct pmx_dev spear320_pmx_pwm0;
184extern struct pmx_dev pmx_pwm1; 184extern struct pmx_dev spear320_pmx_pwm1;
185extern struct pmx_dev pmx_pwm2; 185extern struct pmx_dev spear320_pmx_pwm2;
186extern struct pmx_dev pmx_pwm3; 186extern struct pmx_dev spear320_pmx_pwm3;
187extern struct pmx_dev pmx_ssp1; 187extern struct pmx_dev spear320_pmx_ssp1;
188extern struct pmx_dev pmx_ssp2; 188extern struct pmx_dev spear320_pmx_ssp2;
189extern struct pmx_dev pmx_mii1; 189extern struct pmx_dev spear320_pmx_mii1;
190extern struct pmx_dev pmx_smii0; 190extern struct pmx_dev spear320_pmx_smii0;
191extern struct pmx_dev pmx_smii1; 191extern struct pmx_dev spear320_pmx_smii1;
192extern struct pmx_dev pmx_i2c1; 192extern struct pmx_dev spear320_pmx_i2c1;
193 193
194/* Add spear320 machine function declarations here */ 194/* Add spear320 machine function declarations here */
195void __init spear320_init(void); 195void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
196 u8 pmx_dev_count);
196 197
197#endif /* CONFIG_MACH_SPEAR320 */ 198#endif /* CONFIG_MACH_SPEAR320 */
198 199
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index a1a7f481866d..6e265442808e 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -15,138 +15,140 @@
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* SPEAr3xx IRQ definitions */
18#define IRQ_HW_ACCEL_MOD_0 0 18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define IRQ_INTRCOMM_RAS_ARM 1 19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define IRQ_CPU_GPT1_1 2 20#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define IRQ_CPU_GPT1_2 3 21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define IRQ_BASIC_GPT1_1 4 22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define IRQ_BASIC_GPT1_2 5 23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define IRQ_BASIC_GPT2_1 6 24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define IRQ_BASIC_GPT2_2 7 25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define IRQ_BASIC_DMA 8 26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define IRQ_BASIC_SMI 9 27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define IRQ_BASIC_RTC 10 28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define IRQ_BASIC_GPIO 11 29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define IRQ_BASIC_WDT 12 30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define IRQ_DDR_CONTROLLER 13 31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define IRQ_SYS_ERROR 14 32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define IRQ_WAKEUP_RCV 15 33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define IRQ_JPEG 16 34#define SPEAR3XX_IRQ_JPEG 16
35#define IRQ_IRDA 17 35#define SPEAR3XX_IRQ_IRDA 17
36#define IRQ_ADC 18 36#define SPEAR3XX_IRQ_ADC 18
37#define IRQ_UART 19 37#define SPEAR3XX_IRQ_UART 19
38#define IRQ_SSP 20 38#define SPEAR3XX_IRQ_SSP 20
39#define IRQ_I2C 21 39#define SPEAR3XX_IRQ_I2C 21
40#define IRQ_MAC_1 22 40#define SPEAR3XX_IRQ_MAC_1 22
41#define IRQ_MAC_2 23 41#define SPEAR3XX_IRQ_MAC_2 23
42#define IRQ_USB_DEV 24 42#define SPEAR3XX_IRQ_USB_DEV 24
43#define IRQ_USB_H_OHCI_0 25 43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define IRQ_USB_H_EHCI_0 26 44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0 45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define IRQ_USB_H_OHCI_1 27 46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define IRQ_GEN_RAS_1 28 47#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define IRQ_GEN_RAS_2 29 48#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define IRQ_GEN_RAS_3 30 49#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define IRQ_HW_ACCEL_MOD_1 31 50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define IRQ_VIC_END 32 51#define SPEAR3XX_IRQ_VIC_END 32
52 52
53#define VIRQ_START IRQ_VIC_END 53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 54
55/* SPEAr300 Virtual irq definitions */ 55/* SPEAr300 Virtual irq definitions */
56#ifdef CONFIG_MACH_SPEAR300
57/* IRQs sharing IRQ_GEN_RAS_1 */ 56/* IRQs sharing IRQ_GEN_RAS_1 */
58#define VIRQ_IT_PERS_S (VIRQ_START + 0) 57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
59#define VIRQ_IT_CHANGE_S (VIRQ_START + 1) 58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
60#define VIRQ_I2S (VIRQ_START + 2) 59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
61#define VIRQ_TDM (VIRQ_START + 3) 60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
62#define VIRQ_CAMERA_L (VIRQ_START + 4) 61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
63#define VIRQ_CAMERA_F (VIRQ_START + 5) 62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
64#define VIRQ_CAMERA_V (VIRQ_START + 6) 63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
65#define VIRQ_KEYBOARD (VIRQ_START + 7) 64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
66#define VIRQ_GPIO1 (VIRQ_START + 8) 65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
67 66
68/* IRQs sharing IRQ_GEN_RAS_3 */ 67/* IRQs sharing IRQ_GEN_RAS_3 */
69#define IRQ_CLCD IRQ_GEN_RAS_3 68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
70 69
71/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
72#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM 71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
73
74/* GPIO pins virtual irqs */
75#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9)
76#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
77#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
78 72
79/* SPEAr310 Virtual irq definitions */ 73/* SPEAr310 Virtual irq definitions */
80#elif defined(CONFIG_MACH_SPEAR310)
81/* IRQs sharing IRQ_GEN_RAS_1 */ 74/* IRQs sharing IRQ_GEN_RAS_1 */
82#define VIRQ_SMII0 (VIRQ_START + 0) 75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
83#define VIRQ_SMII1 (VIRQ_START + 1) 76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
84#define VIRQ_SMII2 (VIRQ_START + 2) 77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
85#define VIRQ_SMII3 (VIRQ_START + 3) 78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
86#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4) 79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
87#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5) 80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
88#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6) 81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
89#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7) 82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
90 83
91/* IRQs sharing IRQ_GEN_RAS_2 */ 84/* IRQs sharing IRQ_GEN_RAS_2 */
92#define VIRQ_UART1 (VIRQ_START + 8) 85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
93#define VIRQ_UART2 (VIRQ_START + 9) 86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
94#define VIRQ_UART3 (VIRQ_START + 10) 87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
95#define VIRQ_UART4 (VIRQ_START + 11) 88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
96#define VIRQ_UART5 (VIRQ_START + 12) 89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
97 90
98/* IRQs sharing IRQ_GEN_RAS_3 */ 91/* IRQs sharing IRQ_GEN_RAS_3 */
99#define VIRQ_EMI (VIRQ_START + 13) 92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
100#define VIRQ_PLGPIO (VIRQ_START + 14) 93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
101 94
102/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
103#define VIRQ_TDM_HDLC (VIRQ_START + 15) 96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
104#define VIRQ_RS485_0 (VIRQ_START + 16) 97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
105#define VIRQ_RS485_1 (VIRQ_START + 17) 98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
106
107/* GPIO pins virtual irqs */
108#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18)
109 99
110/* SPEAr320 Virtual irq definitions */ 100/* SPEAr320 Virtual irq definitions */
111#else
112/* IRQs sharing IRQ_GEN_RAS_1 */ 101/* IRQs sharing IRQ_GEN_RAS_1 */
113#define VIRQ_EMI (VIRQ_START + 0) 102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
114#define VIRQ_CLCD (VIRQ_START + 1) 103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
115#define VIRQ_SPP (VIRQ_START + 2) 104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
116 105
117/* IRQs sharing IRQ_GEN_RAS_2 */ 106/* IRQs sharing IRQ_GEN_RAS_2 */
118#define IRQ_SDHCI IRQ_GEN_RAS_2 107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
119 108
120/* IRQs sharing IRQ_GEN_RAS_3 */ 109/* IRQs sharing IRQ_GEN_RAS_3 */
121#define VIRQ_PLGPIO (VIRQ_START + 3) 110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
122#define VIRQ_I2S_PLAY (VIRQ_START + 4) 111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
123#define VIRQ_I2S_REC (VIRQ_START + 5) 112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
124 113
125/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
126#define VIRQ_CANU (VIRQ_START + 6) 115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
127#define VIRQ_CANL (VIRQ_START + 7) 116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
128#define VIRQ_UART1 (VIRQ_START + 8) 117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
129#define VIRQ_UART2 (VIRQ_START + 9) 118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
130#define VIRQ_SSP1 (VIRQ_START + 10) 119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
131#define VIRQ_SSP2 (VIRQ_START + 11) 120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
132#define VIRQ_SMII0 (VIRQ_START + 12) 121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
133#define VIRQ_MII1_SMII1 (VIRQ_START + 13) 122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
134#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14) 123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
135#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15) 124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
136#define VIRQ_I2C (VIRQ_START + 16) 125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
137
138/* GPIO pins virtual irqs */
139#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17)
140 126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
141#endif 138#endif
142 139
143/* PLGPIO Virtual IRQs */ 140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
144#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
145#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8) 144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
146#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102) 145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
147#endif 149#endif
148 150
149#define VIRQ_END SPEAR_GPIO_INT_END 151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
150#define NR_IRQS VIRQ_END 152#define NR_IRQS SPEAR3XX_VIRQ_END
151 153
152#endif /* __MACH_IRQS_H */ 154#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index c723515f8853..3b6ea0729040 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -20,19 +20,19 @@
20#define SPEAR300_TELECOM_BASE UL(0x50000000) 20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21 21
22/* Interrupt registers offsets and masks */ 22/* Interrupt registers offsets and masks */
23#define INT_ENB_MASK_REG 0x54 23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define INT_STS_MASK_REG 0x58 24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define IT_PERS_S_IRQ_MASK (1 << 0) 25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define IT_CHANGE_S_IRQ_MASK (1 << 1) 26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define I2S_IRQ_MASK (1 << 2) 27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define TDM_IRQ_MASK (1 << 3) 28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define CAMERA_L_IRQ_MASK (1 << 4) 29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define CAMERA_F_IRQ_MASK (1 << 5) 30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define CAMERA_V_IRQ_MASK (1 << 6) 31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define KEYBOARD_IRQ_MASK (1 << 7) 32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define GPIO1_IRQ_MASK (1 << 8) 33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34 34
35#define SHIRQ_RAS1_MASK 0x1FF 35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36 36
37#define SPEAR300_CLCD_BASE UL(0x60000000) 37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000) 38#define SPEAR300_SDHCI_BASE UL(0x70000000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1e853479b8cd..1567d0da725f 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -29,29 +29,29 @@
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) 29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30 30
31/* Interrupt registers offsets and masks */ 31/* Interrupt registers offsets and masks */
32#define INT_STS_MASK_REG 0x04 32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SMII0_IRQ_MASK (1 << 0) 33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SMII1_IRQ_MASK (1 << 1) 34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SMII2_IRQ_MASK (1 << 2) 35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SMII3_IRQ_MASK (1 << 3) 36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define WAKEUP_SMII0_IRQ_MASK (1 << 4) 37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define WAKEUP_SMII1_IRQ_MASK (1 << 5) 38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define WAKEUP_SMII2_IRQ_MASK (1 << 6) 39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define WAKEUP_SMII3_IRQ_MASK (1 << 7) 40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define UART1_IRQ_MASK (1 << 8) 41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define UART2_IRQ_MASK (1 << 9) 42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define UART3_IRQ_MASK (1 << 10) 43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define UART4_IRQ_MASK (1 << 11) 44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define UART5_IRQ_MASK (1 << 12) 45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define EMI_IRQ_MASK (1 << 13) 46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define TDM_HDLC_IRQ_MASK (1 << 14) 47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define RS485_0_IRQ_MASK (1 << 15) 48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define RS485_1_IRQ_MASK (1 << 16) 49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50 50
51#define SHIRQ_RAS1_MASK 0x000FF 51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SHIRQ_RAS2_MASK 0x01F00 52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SHIRQ_RAS3_MASK 0x02000 53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55 55
56#endif /* __MACH_SPEAR310_H */ 56#endif /* __MACH_SPEAR310_H */
57 57
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 940f0d85d959..8cfa83fa1296 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -36,31 +36,31 @@
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) 36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37 37
38/* Interrupt registers offsets and masks */ 38/* Interrupt registers offsets and masks */
39#define INT_STS_MASK_REG 0x04 39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define INT_CLR_MASK_REG 0x04 40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define INT_ENB_MASK_REG 0x08 41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define GPIO_IRQ_MASK (1 << 0) 42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define I2S_PLAY_IRQ_MASK (1 << 1) 43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define I2S_REC_IRQ_MASK (1 << 2) 44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define EMI_IRQ_MASK (1 << 7) 45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define CLCD_IRQ_MASK (1 << 8) 46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPP_IRQ_MASK (1 << 9) 47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SDHCI_IRQ_MASK (1 << 10) 48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define CAN_U_IRQ_MASK (1 << 11) 49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define CAN_L_IRQ_MASK (1 << 12) 50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define UART1_IRQ_MASK (1 << 13) 51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define UART2_IRQ_MASK (1 << 14) 52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SSP1_IRQ_MASK (1 << 15) 53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SSP2_IRQ_MASK (1 << 16) 54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SMII0_IRQ_MASK (1 << 17) 55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define MII1_SMII1_IRQ_MASK (1 << 18) 56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define WAKEUP_SMII0_IRQ_MASK (1 << 19) 57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) 58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define I2C1_IRQ_MASK (1 << 21) 59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60 60
61#define SHIRQ_RAS1_MASK 0x000380 61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SHIRQ_RAS3_MASK 0x000007 62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64 64
65#endif /* __MACH_SPEAR320_H */ 65#endif /* __MACH_SPEAR320_H */
66 66
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 2697e65adf86..a5e46b4ade20 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -40,86 +40,86 @@
40#define CAML_LCD_MODE (1 << 12) 40#define CAML_LCD_MODE (1 << 12)
41#define ALL_MODES 0x1FFF 41#define ALL_MODES 0x1FFF
42 42
43struct pmx_mode nand_mode = { 43struct pmx_mode spear300_nand_mode = {
44 .id = NAND_MODE, 44 .id = NAND_MODE,
45 .name = "nand mode", 45 .name = "nand mode",
46 .mask = 0x00, 46 .mask = 0x00,
47}; 47};
48 48
49struct pmx_mode nor_mode = { 49struct pmx_mode spear300_nor_mode = {
50 .id = NOR_MODE, 50 .id = NOR_MODE,
51 .name = "nor mode", 51 .name = "nor mode",
52 .mask = 0x01, 52 .mask = 0x01,
53}; 53};
54 54
55struct pmx_mode photo_frame_mode = { 55struct pmx_mode spear300_photo_frame_mode = {
56 .id = PHOTO_FRAME_MODE, 56 .id = PHOTO_FRAME_MODE,
57 .name = "photo frame mode", 57 .name = "photo frame mode",
58 .mask = 0x02, 58 .mask = 0x02,
59}; 59};
60 60
61struct pmx_mode lend_ip_phone_mode = { 61struct pmx_mode spear300_lend_ip_phone_mode = {
62 .id = LEND_IP_PHONE_MODE, 62 .id = LEND_IP_PHONE_MODE,
63 .name = "lend ip phone mode", 63 .name = "lend ip phone mode",
64 .mask = 0x03, 64 .mask = 0x03,
65}; 65};
66 66
67struct pmx_mode hend_ip_phone_mode = { 67struct pmx_mode spear300_hend_ip_phone_mode = {
68 .id = HEND_IP_PHONE_MODE, 68 .id = HEND_IP_PHONE_MODE,
69 .name = "hend ip phone mode", 69 .name = "hend ip phone mode",
70 .mask = 0x04, 70 .mask = 0x04,
71}; 71};
72 72
73struct pmx_mode lend_wifi_phone_mode = { 73struct pmx_mode spear300_lend_wifi_phone_mode = {
74 .id = LEND_WIFI_PHONE_MODE, 74 .id = LEND_WIFI_PHONE_MODE,
75 .name = "lend wifi phone mode", 75 .name = "lend wifi phone mode",
76 .mask = 0x05, 76 .mask = 0x05,
77}; 77};
78 78
79struct pmx_mode hend_wifi_phone_mode = { 79struct pmx_mode spear300_hend_wifi_phone_mode = {
80 .id = HEND_WIFI_PHONE_MODE, 80 .id = HEND_WIFI_PHONE_MODE,
81 .name = "hend wifi phone mode", 81 .name = "hend wifi phone mode",
82 .mask = 0x06, 82 .mask = 0x06,
83}; 83};
84 84
85struct pmx_mode ata_pabx_wi2s_mode = { 85struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86 .id = ATA_PABX_WI2S_MODE, 86 .id = ATA_PABX_WI2S_MODE,
87 .name = "ata pabx wi2s mode", 87 .name = "ata pabx wi2s mode",
88 .mask = 0x07, 88 .mask = 0x07,
89}; 89};
90 90
91struct pmx_mode ata_pabx_i2s_mode = { 91struct pmx_mode spear300_ata_pabx_i2s_mode = {
92 .id = ATA_PABX_I2S_MODE, 92 .id = ATA_PABX_I2S_MODE,
93 .name = "ata pabx i2s mode", 93 .name = "ata pabx i2s mode",
94 .mask = 0x08, 94 .mask = 0x08,
95}; 95};
96 96
97struct pmx_mode caml_lcdw_mode = { 97struct pmx_mode spear300_caml_lcdw_mode = {
98 .id = CAML_LCDW_MODE, 98 .id = CAML_LCDW_MODE,
99 .name = "caml lcdw mode", 99 .name = "caml lcdw mode",
100 .mask = 0x0C, 100 .mask = 0x0C,
101}; 101};
102 102
103struct pmx_mode camu_lcd_mode = { 103struct pmx_mode spear300_camu_lcd_mode = {
104 .id = CAMU_LCD_MODE, 104 .id = CAMU_LCD_MODE,
105 .name = "camu lcd mode", 105 .name = "camu lcd mode",
106 .mask = 0x0D, 106 .mask = 0x0D,
107}; 107};
108 108
109struct pmx_mode camu_wlcd_mode = { 109struct pmx_mode spear300_camu_wlcd_mode = {
110 .id = CAMU_WLCD_MODE, 110 .id = CAMU_WLCD_MODE,
111 .name = "camu wlcd mode", 111 .name = "camu wlcd mode",
112 .mask = 0x0E, 112 .mask = 0x0E,
113}; 113};
114 114
115struct pmx_mode caml_lcd_mode = { 115struct pmx_mode spear300_caml_lcd_mode = {
116 .id = CAML_LCD_MODE, 116 .id = CAML_LCD_MODE,
117 .name = "caml lcd mode", 117 .name = "caml lcd mode",
118 .mask = 0x0F, 118 .mask = 0x0F,
119}; 119};
120 120
121/* devices */ 121/* devices */
122struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { 122static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123 { 123 {
124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -127,14 +127,14 @@ struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
127 }, 127 },
128}; 128};
129 129
130struct pmx_dev pmx_fsmc_2_chips = { 130struct pmx_dev spear300_pmx_fsmc_2_chips = {
131 .name = "fsmc_2_chips", 131 .name = "fsmc_2_chips",
132 .modes = pmx_fsmc_2_chips_modes, 132 .modes = pmx_fsmc_2_chips_modes,
133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), 133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134 .enb_on_reset = 1, 134 .enb_on_reset = 1,
135}; 135};
136 136
137struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { 137static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138 { 138 {
139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -142,14 +142,14 @@ struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
142 }, 142 },
143}; 143};
144 144
145struct pmx_dev pmx_fsmc_4_chips = { 145struct pmx_dev spear300_pmx_fsmc_4_chips = {
146 .name = "fsmc_4_chips", 146 .name = "fsmc_4_chips",
147 .modes = pmx_fsmc_4_chips_modes, 147 .modes = pmx_fsmc_4_chips_modes,
148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), 148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149 .enb_on_reset = 1, 149 .enb_on_reset = 1,
150}; 150};
151 151
152struct pmx_dev_mode pmx_keyboard_modes[] = { 152static struct pmx_dev_mode pmx_keyboard_modes[] = {
153 { 153 {
154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | 154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -159,14 +159,14 @@ struct pmx_dev_mode pmx_keyboard_modes[] = {
159 }, 159 },
160}; 160};
161 161
162struct pmx_dev pmx_keyboard = { 162struct pmx_dev spear300_pmx_keyboard = {
163 .name = "keyboard", 163 .name = "keyboard",
164 .modes = pmx_keyboard_modes, 164 .modes = pmx_keyboard_modes,
165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes), 165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166 .enb_on_reset = 1, 166 .enb_on_reset = 1,
167}; 167};
168 168
169struct pmx_dev_mode pmx_clcd_modes[] = { 169static struct pmx_dev_mode pmx_clcd_modes[] = {
170 { 170 {
171 .ids = PHOTO_FRAME_MODE, 171 .ids = PHOTO_FRAME_MODE,
172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , 172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
@@ -177,14 +177,14 @@ struct pmx_dev_mode pmx_clcd_modes[] = {
177 }, 177 },
178}; 178};
179 179
180struct pmx_dev pmx_clcd = { 180struct pmx_dev spear300_pmx_clcd = {
181 .name = "clcd", 181 .name = "clcd",
182 .modes = pmx_clcd_modes, 182 .modes = pmx_clcd_modes,
183 .mode_count = ARRAY_SIZE(pmx_clcd_modes), 183 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
184 .enb_on_reset = 1, 184 .enb_on_reset = 1,
185}; 185};
186 186
187struct pmx_dev_mode pmx_telecom_gpio_modes[] = { 187static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188 { 188 {
189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, 189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190 .mask = PMX_MII_MASK, 190 .mask = PMX_MII_MASK,
@@ -204,14 +204,14 @@ struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
204 }, 204 },
205}; 205};
206 206
207struct pmx_dev pmx_telecom_gpio = { 207struct pmx_dev spear300_pmx_telecom_gpio = {
208 .name = "telecom_gpio", 208 .name = "telecom_gpio",
209 .modes = pmx_telecom_gpio_modes, 209 .modes = pmx_telecom_gpio_modes,
210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), 210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211 .enb_on_reset = 1, 211 .enb_on_reset = 1,
212}; 212};
213 213
214struct pmx_dev_mode pmx_telecom_tdm_modes[] = { 214static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215 { 215 {
216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE 217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
@@ -222,14 +222,14 @@ struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
222 }, 222 },
223}; 223};
224 224
225struct pmx_dev pmx_telecom_tdm = { 225struct pmx_dev spear300_pmx_telecom_tdm = {
226 .name = "telecom_tdm", 226 .name = "telecom_tdm",
227 .modes = pmx_telecom_tdm_modes, 227 .modes = pmx_telecom_tdm_modes,
228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), 228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229 .enb_on_reset = 1, 229 .enb_on_reset = 1,
230}; 230};
231 231
232struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { 232static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233 { 233 {
234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | 234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE 235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
@@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
239 }, 239 },
240}; 240};
241 241
242struct pmx_dev pmx_telecom_spi_cs_i2c_clk = { 242struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243 .name = "telecom_spi_cs_i2c_clk", 243 .name = "telecom_spi_cs_i2c_clk",
244 .modes = pmx_telecom_spi_cs_i2c_clk_modes, 244 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), 245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246 .enb_on_reset = 1, 246 .enb_on_reset = 1,
247}; 247};
248 248
249struct pmx_dev_mode pmx_telecom_camera_modes[] = { 249static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250 { 250 {
251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE, 251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252 .mask = PMX_MII_MASK, 252 .mask = PMX_MII_MASK,
@@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_telecom_camera_modes[] = {
256 }, 256 },
257}; 257};
258 258
259struct pmx_dev pmx_telecom_camera = { 259struct pmx_dev spear300_pmx_telecom_camera = {
260 .name = "telecom_camera", 260 .name = "telecom_camera",
261 .modes = pmx_telecom_camera_modes, 261 .modes = pmx_telecom_camera_modes,
262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), 262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263 .enb_on_reset = 1, 263 .enb_on_reset = 1,
264}; 264};
265 265
266struct pmx_dev_mode pmx_telecom_dac_modes[] = { 266static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267 { 267 {
268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269 | CAMU_WLCD_MODE | CAML_LCD_MODE, 269 | CAMU_WLCD_MODE | CAML_LCD_MODE,
@@ -271,14 +271,14 @@ struct pmx_dev_mode pmx_telecom_dac_modes[] = {
271 }, 271 },
272}; 272};
273 273
274struct pmx_dev pmx_telecom_dac = { 274struct pmx_dev spear300_pmx_telecom_dac = {
275 .name = "telecom_dac", 275 .name = "telecom_dac",
276 .modes = pmx_telecom_dac_modes, 276 .modes = pmx_telecom_dac_modes,
277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), 277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278 .enb_on_reset = 1, 278 .enb_on_reset = 1,
279}; 279};
280 280
281struct pmx_dev_mode pmx_telecom_i2s_modes[] = { 281static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282 { 282 {
283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE 283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -288,14 +288,14 @@ struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
288 }, 288 },
289}; 289};
290 290
291struct pmx_dev pmx_telecom_i2s = { 291struct pmx_dev spear300_pmx_telecom_i2s = {
292 .name = "telecom_i2s", 292 .name = "telecom_i2s",
293 .modes = pmx_telecom_i2s_modes, 293 .modes = pmx_telecom_i2s_modes,
294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), 294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295 .enb_on_reset = 1, 295 .enb_on_reset = 1,
296}; 296};
297 297
298struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { 298static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299 { 299 {
300 .ids = NAND_MODE | NOR_MODE, 300 .ids = NAND_MODE | NOR_MODE,
301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | 301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -303,14 +303,14 @@ struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
303 }, 303 },
304}; 304};
305 305
306struct pmx_dev pmx_telecom_boot_pins = { 306struct pmx_dev spear300_pmx_telecom_boot_pins = {
307 .name = "telecom_boot_pins", 307 .name = "telecom_boot_pins",
308 .modes = pmx_telecom_boot_pins_modes, 308 .modes = pmx_telecom_boot_pins_modes,
309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), 309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310 .enb_on_reset = 1, 310 .enb_on_reset = 1,
311}; 311};
312 312
313struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { 313static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314 { 314 {
315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -323,14 +323,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
323 }, 323 },
324}; 324};
325 325
326struct pmx_dev pmx_telecom_sdhci_4bit = { 326struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327 .name = "telecom_sdhci_4bit", 327 .name = "telecom_sdhci_4bit",
328 .modes = pmx_telecom_sdhci_4bit_modes, 328 .modes = pmx_telecom_sdhci_4bit_modes,
329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), 329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330 .enb_on_reset = 1, 330 .enb_on_reset = 1,
331}; 331};
332 332
333struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { 333static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334 { 334 {
335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -342,14 +342,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
342 }, 342 },
343}; 343};
344 344
345struct pmx_dev pmx_telecom_sdhci_8bit = { 345struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346 .name = "telecom_sdhci_8bit", 346 .name = "telecom_sdhci_8bit",
347 .modes = pmx_telecom_sdhci_8bit_modes, 347 .modes = pmx_telecom_sdhci_8bit_modes,
348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), 348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349 .enb_on_reset = 1, 349 .enb_on_reset = 1,
350}; 350};
351 351
352struct pmx_dev_mode pmx_gpio1_modes[] = { 352static struct pmx_dev_mode pmx_gpio1_modes[] = {
353 { 353 {
354 .ids = PHOTO_FRAME_MODE, 354 .ids = PHOTO_FRAME_MODE,
355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | 355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -357,7 +357,7 @@ struct pmx_dev_mode pmx_gpio1_modes[] = {
357 }, 357 },
358}; 358};
359 359
360struct pmx_dev pmx_gpio1 = { 360struct pmx_dev spear300_pmx_gpio1 = {
361 .name = "arm gpio1", 361 .name = "arm gpio1",
362 .modes = pmx_gpio1_modes, 362 .modes = pmx_gpio1_modes,
363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes), 363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
@@ -365,60 +365,60 @@ struct pmx_dev pmx_gpio1 = {
365}; 365};
366 366
367/* pmx driver structure */ 367/* pmx driver structure */
368struct pmx_driver pmx_driver = { 368static struct pmx_driver pmx_driver = {
369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, 369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371}; 371};
372 372
373/* spear3xx shared irq */ 373/* spear3xx shared irq */
374struct shirq_dev_config shirq_ras1_config[] = { 374static struct shirq_dev_config shirq_ras1_config[] = {
375 { 375 {
376 .virq = VIRQ_IT_PERS_S, 376 .virq = SPEAR300_VIRQ_IT_PERS_S,
377 .enb_mask = IT_PERS_S_IRQ_MASK, 377 .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
378 .status_mask = IT_PERS_S_IRQ_MASK, 378 .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
379 }, { 379 }, {
380 .virq = VIRQ_IT_CHANGE_S, 380 .virq = SPEAR300_VIRQ_IT_CHANGE_S,
381 .enb_mask = IT_CHANGE_S_IRQ_MASK, 381 .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
382 .status_mask = IT_CHANGE_S_IRQ_MASK, 382 .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
383 }, { 383 }, {
384 .virq = VIRQ_I2S, 384 .virq = SPEAR300_VIRQ_I2S,
385 .enb_mask = I2S_IRQ_MASK, 385 .enb_mask = SPEAR300_I2S_IRQ_MASK,
386 .status_mask = I2S_IRQ_MASK, 386 .status_mask = SPEAR300_I2S_IRQ_MASK,
387 }, { 387 }, {
388 .virq = VIRQ_TDM, 388 .virq = SPEAR300_VIRQ_TDM,
389 .enb_mask = TDM_IRQ_MASK, 389 .enb_mask = SPEAR300_TDM_IRQ_MASK,
390 .status_mask = TDM_IRQ_MASK, 390 .status_mask = SPEAR300_TDM_IRQ_MASK,
391 }, { 391 }, {
392 .virq = VIRQ_CAMERA_L, 392 .virq = SPEAR300_VIRQ_CAMERA_L,
393 .enb_mask = CAMERA_L_IRQ_MASK, 393 .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
394 .status_mask = CAMERA_L_IRQ_MASK, 394 .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
395 }, { 395 }, {
396 .virq = VIRQ_CAMERA_F, 396 .virq = SPEAR300_VIRQ_CAMERA_F,
397 .enb_mask = CAMERA_F_IRQ_MASK, 397 .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
398 .status_mask = CAMERA_F_IRQ_MASK, 398 .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
399 }, { 399 }, {
400 .virq = VIRQ_CAMERA_V, 400 .virq = SPEAR300_VIRQ_CAMERA_V,
401 .enb_mask = CAMERA_V_IRQ_MASK, 401 .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
402 .status_mask = CAMERA_V_IRQ_MASK, 402 .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
403 }, { 403 }, {
404 .virq = VIRQ_KEYBOARD, 404 .virq = SPEAR300_VIRQ_KEYBOARD,
405 .enb_mask = KEYBOARD_IRQ_MASK, 405 .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
406 .status_mask = KEYBOARD_IRQ_MASK, 406 .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
407 }, { 407 }, {
408 .virq = VIRQ_GPIO1, 408 .virq = SPEAR300_VIRQ_GPIO1,
409 .enb_mask = GPIO1_IRQ_MASK, 409 .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
410 .status_mask = GPIO1_IRQ_MASK, 410 .status_mask = SPEAR300_GPIO1_IRQ_MASK,
411 }, 411 },
412}; 412};
413 413
414struct spear_shirq shirq_ras1 = { 414static struct spear_shirq shirq_ras1 = {
415 .irq = IRQ_GEN_RAS_1, 415 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
416 .dev_config = shirq_ras1_config, 416 .dev_config = shirq_ras1_config,
417 .dev_count = ARRAY_SIZE(shirq_ras1_config), 417 .dev_count = ARRAY_SIZE(shirq_ras1_config),
418 .regs = { 418 .regs = {
419 .enb_reg = INT_ENB_MASK_REG, 419 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
420 .status_reg = INT_STS_MASK_REG, 420 .status_reg = SPEAR300_INT_STS_MASK_REG,
421 .status_reg_mask = SHIRQ_RAS1_MASK, 421 .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
422 .clear_reg = -1, 422 .clear_reg = -1,
423 }, 423 },
424}; 424};
@@ -427,10 +427,10 @@ struct spear_shirq shirq_ras1 = {
427/* arm gpio1 device registration */ 427/* arm gpio1 device registration */
428static struct pl061_platform_data gpio1_plat_data = { 428static struct pl061_platform_data gpio1_plat_data = {
429 .gpio_base = 8, 429 .gpio_base = 8,
430 .irq_base = SPEAR_GPIO1_INT_BASE, 430 .irq_base = SPEAR300_GPIO1_INT_BASE,
431}; 431};
432 432
433struct amba_device gpio1_device = { 433struct amba_device spear300_gpio1_device = {
434 .dev = { 434 .dev = {
435 .init_name = "gpio1", 435 .init_name = "gpio1",
436 .platform_data = &gpio1_plat_data, 436 .platform_data = &gpio1_plat_data,
@@ -440,11 +440,12 @@ struct amba_device gpio1_device = {
440 .end = SPEAR300_GPIO_BASE + SZ_4K - 1, 440 .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
441 .flags = IORESOURCE_MEM, 441 .flags = IORESOURCE_MEM,
442 }, 442 },
443 .irq = {VIRQ_GPIO1, NO_IRQ}, 443 .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
444}; 444};
445 445
446/* spear300 routines */ 446/* spear300 routines */
447void __init spear300_init(void) 447void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
448 u8 pmx_dev_count)
448{ 449{
449 int ret = 0; 450 int ret = 0;
450 451
@@ -460,6 +461,10 @@ void __init spear300_init(void)
460 } 461 }
461 462
462 /* pmx initialization */ 463 /* pmx initialization */
464 pmx_driver.mode = pmx_mode;
465 pmx_driver.devs = pmx_devs;
466 pmx_driver.devs_count = pmx_dev_count;
467
463 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); 468 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
464 if (pmx_driver.base) { 469 if (pmx_driver.base) {
465 ret = pmx_register(&pmx_driver); 470 ret = pmx_register(&pmx_driver);
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 42d2253ef540..69006f694220 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -19,26 +19,26 @@
19/* padmux devices to enable */ 19/* padmux devices to enable */
20static struct pmx_dev *pmx_devs[] = { 20static struct pmx_dev *pmx_devs[] = {
21 /* spear3xx specific devices */ 21 /* spear3xx specific devices */
22 &pmx_i2c, 22 &spear3xx_pmx_i2c,
23 &pmx_ssp_cs, 23 &spear3xx_pmx_ssp_cs,
24 &pmx_ssp, 24 &spear3xx_pmx_ssp,
25 &pmx_mii, 25 &spear3xx_pmx_mii,
26 &pmx_uart0, 26 &spear3xx_pmx_uart0,
27 27
28 /* spear300 specific devices */ 28 /* spear300 specific devices */
29 &pmx_fsmc_2_chips, 29 &spear300_pmx_fsmc_2_chips,
30 &pmx_clcd, 30 &spear300_pmx_clcd,
31 &pmx_telecom_sdhci_4bit, 31 &spear300_pmx_telecom_sdhci_4bit,
32 &pmx_gpio1, 32 &spear300_pmx_gpio1,
33}; 33};
34 34
35static struct amba_device *amba_devs[] __initdata = { 35static struct amba_device *amba_devs[] __initdata = {
36 /* spear3xx specific devices */ 36 /* spear3xx specific devices */
37 &gpio_device, 37 &spear3xx_gpio_device,
38 &uart_device, 38 &spear3xx_uart_device,
39 39
40 /* spear300 specific devices */ 40 /* spear300 specific devices */
41 &gpio1_device, 41 &spear300_gpio1_device,
42}; 42};
43 43
44static struct platform_device *plat_devs[] __initdata = { 44static struct platform_device *plat_devs[] __initdata = {
@@ -51,13 +51,9 @@ static void __init spear300_evb_init(void)
51{ 51{
52 unsigned int i; 52 unsigned int i;
53 53
54 /* padmux initialization, must be done before spear300_init */
55 pmx_driver.mode = &photo_frame_mode;
56 pmx_driver.devs = pmx_devs;
57 pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
58
59 /* call spear300 machine init function */ 54 /* call spear300 machine init function */
60 spear300_init(); 55 spear300_init(&spear300_photo_frame_mode, pmx_devs,
56 ARRAY_SIZE(pmx_devs));
61 57
62 /* Add Platform Devices */ 58 /* Add Platform Devices */
63 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); 59 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 5c0a67b60c2a..9004cf9f01bf 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -22,112 +22,112 @@
22#define PAD_MUX_CONFIG_REG 0x08 22#define PAD_MUX_CONFIG_REG 0x08
23 23
24/* devices */ 24/* devices */
25struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { 25static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
26 { 26 {
27 .ids = 0x00, 27 .ids = 0x00,
28 .mask = PMX_TIMER_3_4_MASK, 28 .mask = PMX_TIMER_3_4_MASK,
29 }, 29 },
30}; 30};
31 31
32struct pmx_dev pmx_emi_cs_0_1_4_5 = { 32struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
33 .name = "emi_cs_0_1_4_5", 33 .name = "emi_cs_0_1_4_5",
34 .modes = pmx_emi_cs_0_1_4_5_modes, 34 .modes = pmx_emi_cs_0_1_4_5_modes,
35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), 35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
36 .enb_on_reset = 1, 36 .enb_on_reset = 1,
37}; 37};
38 38
39struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { 39static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
40 { 40 {
41 .ids = 0x00, 41 .ids = 0x00,
42 .mask = PMX_TIMER_1_2_MASK, 42 .mask = PMX_TIMER_1_2_MASK,
43 }, 43 },
44}; 44};
45 45
46struct pmx_dev pmx_emi_cs_2_3 = { 46struct pmx_dev spear310_pmx_emi_cs_2_3 = {
47 .name = "emi_cs_2_3", 47 .name = "emi_cs_2_3",
48 .modes = pmx_emi_cs_2_3_modes, 48 .modes = pmx_emi_cs_2_3_modes,
49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), 49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
50 .enb_on_reset = 1, 50 .enb_on_reset = 1,
51}; 51};
52 52
53struct pmx_dev_mode pmx_uart1_modes[] = { 53static struct pmx_dev_mode pmx_uart1_modes[] = {
54 { 54 {
55 .ids = 0x00, 55 .ids = 0x00,
56 .mask = PMX_FIRDA_MASK, 56 .mask = PMX_FIRDA_MASK,
57 }, 57 },
58}; 58};
59 59
60struct pmx_dev pmx_uart1 = { 60struct pmx_dev spear310_pmx_uart1 = {
61 .name = "uart1", 61 .name = "uart1",
62 .modes = pmx_uart1_modes, 62 .modes = pmx_uart1_modes,
63 .mode_count = ARRAY_SIZE(pmx_uart1_modes), 63 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
64 .enb_on_reset = 1, 64 .enb_on_reset = 1,
65}; 65};
66 66
67struct pmx_dev_mode pmx_uart2_modes[] = { 67static struct pmx_dev_mode pmx_uart2_modes[] = {
68 { 68 {
69 .ids = 0x00, 69 .ids = 0x00,
70 .mask = PMX_TIMER_1_2_MASK, 70 .mask = PMX_TIMER_1_2_MASK,
71 }, 71 },
72}; 72};
73 73
74struct pmx_dev pmx_uart2 = { 74struct pmx_dev spear310_pmx_uart2 = {
75 .name = "uart2", 75 .name = "uart2",
76 .modes = pmx_uart2_modes, 76 .modes = pmx_uart2_modes,
77 .mode_count = ARRAY_SIZE(pmx_uart2_modes), 77 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
78 .enb_on_reset = 1, 78 .enb_on_reset = 1,
79}; 79};
80 80
81struct pmx_dev_mode pmx_uart3_4_5_modes[] = { 81static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
82 { 82 {
83 .ids = 0x00, 83 .ids = 0x00,
84 .mask = PMX_UART0_MODEM_MASK, 84 .mask = PMX_UART0_MODEM_MASK,
85 }, 85 },
86}; 86};
87 87
88struct pmx_dev pmx_uart3_4_5 = { 88struct pmx_dev spear310_pmx_uart3_4_5 = {
89 .name = "uart3_4_5", 89 .name = "uart3_4_5",
90 .modes = pmx_uart3_4_5_modes, 90 .modes = pmx_uart3_4_5_modes,
91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), 91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92 .enb_on_reset = 1, 92 .enb_on_reset = 1,
93}; 93};
94 94
95struct pmx_dev_mode pmx_fsmc_modes[] = { 95static struct pmx_dev_mode pmx_fsmc_modes[] = {
96 { 96 {
97 .ids = 0x00, 97 .ids = 0x00,
98 .mask = PMX_SSP_CS_MASK, 98 .mask = PMX_SSP_CS_MASK,
99 }, 99 },
100}; 100};
101 101
102struct pmx_dev pmx_fsmc = { 102struct pmx_dev spear310_pmx_fsmc = {
103 .name = "fsmc", 103 .name = "fsmc",
104 .modes = pmx_fsmc_modes, 104 .modes = pmx_fsmc_modes,
105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes), 105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106 .enb_on_reset = 1, 106 .enb_on_reset = 1,
107}; 107};
108 108
109struct pmx_dev_mode pmx_rs485_0_1_modes[] = { 109static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110 { 110 {
111 .ids = 0x00, 111 .ids = 0x00,
112 .mask = PMX_MII_MASK, 112 .mask = PMX_MII_MASK,
113 }, 113 },
114}; 114};
115 115
116struct pmx_dev pmx_rs485_0_1 = { 116struct pmx_dev spear310_pmx_rs485_0_1 = {
117 .name = "rs485_0_1", 117 .name = "rs485_0_1",
118 .modes = pmx_rs485_0_1_modes, 118 .modes = pmx_rs485_0_1_modes,
119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), 119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120 .enb_on_reset = 1, 120 .enb_on_reset = 1,
121}; 121};
122 122
123struct pmx_dev_mode pmx_tdm0_modes[] = { 123static struct pmx_dev_mode pmx_tdm0_modes[] = {
124 { 124 {
125 .ids = 0x00, 125 .ids = 0x00,
126 .mask = PMX_MII_MASK, 126 .mask = PMX_MII_MASK,
127 }, 127 },
128}; 128};
129 129
130struct pmx_dev pmx_tdm0 = { 130struct pmx_dev spear310_pmx_tdm0 = {
131 .name = "tdm0", 131 .name = "tdm0",
132 .modes = pmx_tdm0_modes, 132 .modes = pmx_tdm0_modes,
133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes), 133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
@@ -135,122 +135,122 @@ struct pmx_dev pmx_tdm0 = {
135}; 135};
136 136
137/* pmx driver structure */ 137/* pmx driver structure */
138struct pmx_driver pmx_driver = { 138static struct pmx_driver pmx_driver = {
139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140}; 140};
141 141
142/* spear3xx shared irq */ 142/* spear3xx shared irq */
143struct shirq_dev_config shirq_ras1_config[] = { 143static struct shirq_dev_config shirq_ras1_config[] = {
144 { 144 {
145 .virq = VIRQ_SMII0, 145 .virq = SPEAR310_VIRQ_SMII0,
146 .status_mask = SMII0_IRQ_MASK, 146 .status_mask = SPEAR310_SMII0_IRQ_MASK,
147 }, { 147 }, {
148 .virq = VIRQ_SMII1, 148 .virq = SPEAR310_VIRQ_SMII1,
149 .status_mask = SMII1_IRQ_MASK, 149 .status_mask = SPEAR310_SMII1_IRQ_MASK,
150 }, { 150 }, {
151 .virq = VIRQ_SMII2, 151 .virq = SPEAR310_VIRQ_SMII2,
152 .status_mask = SMII2_IRQ_MASK, 152 .status_mask = SPEAR310_SMII2_IRQ_MASK,
153 }, { 153 }, {
154 .virq = VIRQ_SMII3, 154 .virq = SPEAR310_VIRQ_SMII3,
155 .status_mask = SMII3_IRQ_MASK, 155 .status_mask = SPEAR310_SMII3_IRQ_MASK,
156 }, { 156 }, {
157 .virq = VIRQ_WAKEUP_SMII0, 157 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
158 .status_mask = WAKEUP_SMII0_IRQ_MASK, 158 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
159 }, { 159 }, {
160 .virq = VIRQ_WAKEUP_SMII1, 160 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
161 .status_mask = WAKEUP_SMII1_IRQ_MASK, 161 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
162 }, { 162 }, {
163 .virq = VIRQ_WAKEUP_SMII2, 163 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
164 .status_mask = WAKEUP_SMII2_IRQ_MASK, 164 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
165 }, { 165 }, {
166 .virq = VIRQ_WAKEUP_SMII3, 166 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
167 .status_mask = WAKEUP_SMII3_IRQ_MASK, 167 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
168 }, 168 },
169}; 169};
170 170
171struct spear_shirq shirq_ras1 = { 171static struct spear_shirq shirq_ras1 = {
172 .irq = IRQ_GEN_RAS_1, 172 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
173 .dev_config = shirq_ras1_config, 173 .dev_config = shirq_ras1_config,
174 .dev_count = ARRAY_SIZE(shirq_ras1_config), 174 .dev_count = ARRAY_SIZE(shirq_ras1_config),
175 .regs = { 175 .regs = {
176 .enb_reg = -1, 176 .enb_reg = -1,
177 .status_reg = INT_STS_MASK_REG, 177 .status_reg = SPEAR310_INT_STS_MASK_REG,
178 .status_reg_mask = SHIRQ_RAS1_MASK, 178 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
179 .clear_reg = -1, 179 .clear_reg = -1,
180 }, 180 },
181}; 181};
182 182
183struct shirq_dev_config shirq_ras2_config[] = { 183static struct shirq_dev_config shirq_ras2_config[] = {
184 { 184 {
185 .virq = VIRQ_UART1, 185 .virq = SPEAR310_VIRQ_UART1,
186 .status_mask = UART1_IRQ_MASK, 186 .status_mask = SPEAR310_UART1_IRQ_MASK,
187 }, { 187 }, {
188 .virq = VIRQ_UART2, 188 .virq = SPEAR310_VIRQ_UART2,
189 .status_mask = UART2_IRQ_MASK, 189 .status_mask = SPEAR310_UART2_IRQ_MASK,
190 }, { 190 }, {
191 .virq = VIRQ_UART3, 191 .virq = SPEAR310_VIRQ_UART3,
192 .status_mask = UART3_IRQ_MASK, 192 .status_mask = SPEAR310_UART3_IRQ_MASK,
193 }, { 193 }, {
194 .virq = VIRQ_UART4, 194 .virq = SPEAR310_VIRQ_UART4,
195 .status_mask = UART4_IRQ_MASK, 195 .status_mask = SPEAR310_UART4_IRQ_MASK,
196 }, { 196 }, {
197 .virq = VIRQ_UART5, 197 .virq = SPEAR310_VIRQ_UART5,
198 .status_mask = UART5_IRQ_MASK, 198 .status_mask = SPEAR310_UART5_IRQ_MASK,
199 }, 199 },
200}; 200};
201 201
202struct spear_shirq shirq_ras2 = { 202static struct spear_shirq shirq_ras2 = {
203 .irq = IRQ_GEN_RAS_2, 203 .irq = SPEAR3XX_IRQ_GEN_RAS_2,
204 .dev_config = shirq_ras2_config, 204 .dev_config = shirq_ras2_config,
205 .dev_count = ARRAY_SIZE(shirq_ras2_config), 205 .dev_count = ARRAY_SIZE(shirq_ras2_config),
206 .regs = { 206 .regs = {
207 .enb_reg = -1, 207 .enb_reg = -1,
208 .status_reg = INT_STS_MASK_REG, 208 .status_reg = SPEAR310_INT_STS_MASK_REG,
209 .status_reg_mask = SHIRQ_RAS2_MASK, 209 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
210 .clear_reg = -1, 210 .clear_reg = -1,
211 }, 211 },
212}; 212};
213 213
214struct shirq_dev_config shirq_ras3_config[] = { 214static struct shirq_dev_config shirq_ras3_config[] = {
215 { 215 {
216 .virq = VIRQ_EMI, 216 .virq = SPEAR310_VIRQ_EMI,
217 .status_mask = EMI_IRQ_MASK, 217 .status_mask = SPEAR310_EMI_IRQ_MASK,
218 }, 218 },
219}; 219};
220 220
221struct spear_shirq shirq_ras3 = { 221static struct spear_shirq shirq_ras3 = {
222 .irq = IRQ_GEN_RAS_3, 222 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
223 .dev_config = shirq_ras3_config, 223 .dev_config = shirq_ras3_config,
224 .dev_count = ARRAY_SIZE(shirq_ras3_config), 224 .dev_count = ARRAY_SIZE(shirq_ras3_config),
225 .regs = { 225 .regs = {
226 .enb_reg = -1, 226 .enb_reg = -1,
227 .status_reg = INT_STS_MASK_REG, 227 .status_reg = SPEAR310_INT_STS_MASK_REG,
228 .status_reg_mask = SHIRQ_RAS3_MASK, 228 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
229 .clear_reg = -1, 229 .clear_reg = -1,
230 }, 230 },
231}; 231};
232 232
233struct shirq_dev_config shirq_intrcomm_ras_config[] = { 233static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
234 { 234 {
235 .virq = VIRQ_TDM_HDLC, 235 .virq = SPEAR310_VIRQ_TDM_HDLC,
236 .status_mask = TDM_HDLC_IRQ_MASK, 236 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
237 }, { 237 }, {
238 .virq = VIRQ_RS485_0, 238 .virq = SPEAR310_VIRQ_RS485_0,
239 .status_mask = RS485_0_IRQ_MASK, 239 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
240 }, { 240 }, {
241 .virq = VIRQ_RS485_1, 241 .virq = SPEAR310_VIRQ_RS485_1,
242 .status_mask = RS485_1_IRQ_MASK, 242 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
243 }, 243 },
244}; 244};
245 245
246struct spear_shirq shirq_intrcomm_ras = { 246static struct spear_shirq shirq_intrcomm_ras = {
247 .irq = IRQ_INTRCOMM_RAS_ARM, 247 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
248 .dev_config = shirq_intrcomm_ras_config, 248 .dev_config = shirq_intrcomm_ras_config,
249 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 249 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
250 .regs = { 250 .regs = {
251 .enb_reg = -1, 251 .enb_reg = -1,
252 .status_reg = INT_STS_MASK_REG, 252 .status_reg = SPEAR310_INT_STS_MASK_REG,
253 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, 253 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
254 .clear_reg = -1, 254 .clear_reg = -1,
255 }, 255 },
256}; 256};
@@ -258,7 +258,8 @@ struct spear_shirq shirq_intrcomm_ras = {
258/* Add spear310 specific devices here */ 258/* Add spear310 specific devices here */
259 259
260/* spear310 routines */ 260/* spear310 routines */
261void __init spear310_init(void) 261void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
262 u8 pmx_dev_count)
262{ 263{
263 void __iomem *base; 264 void __iomem *base;
264 int ret = 0; 265 int ret = 0;
@@ -296,6 +297,10 @@ void __init spear310_init(void)
296 297
297 /* pmx initialization */ 298 /* pmx initialization */
298 pmx_driver.base = base; 299 pmx_driver.base = base;
300 pmx_driver.mode = pmx_mode;
301 pmx_driver.devs = pmx_devs;
302 pmx_driver.devs_count = pmx_dev_count;
303
299 ret = pmx_register(&pmx_driver); 304 ret = pmx_register(&pmx_driver);
300 if (ret) 305 if (ret)
301 printk(KERN_ERR "padmux: registeration failed. err no: %d\n", 306 printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 2d7f333bd67b..c8684ce1f9b3 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -19,31 +19,31 @@
19/* padmux devices to enable */ 19/* padmux devices to enable */
20static struct pmx_dev *pmx_devs[] = { 20static struct pmx_dev *pmx_devs[] = {
21 /* spear3xx specific devices */ 21 /* spear3xx specific devices */
22 &pmx_i2c, 22 &spear3xx_pmx_i2c,
23 &pmx_ssp, 23 &spear3xx_pmx_ssp,
24 &pmx_gpio_pin0, 24 &spear3xx_pmx_gpio_pin0,
25 &pmx_gpio_pin1, 25 &spear3xx_pmx_gpio_pin1,
26 &pmx_gpio_pin2, 26 &spear3xx_pmx_gpio_pin2,
27 &pmx_gpio_pin3, 27 &spear3xx_pmx_gpio_pin3,
28 &pmx_gpio_pin4, 28 &spear3xx_pmx_gpio_pin4,
29 &pmx_gpio_pin5, 29 &spear3xx_pmx_gpio_pin5,
30 &pmx_uart0, 30 &spear3xx_pmx_uart0,
31 31
32 /* spear310 specific devices */ 32 /* spear310 specific devices */
33 &pmx_emi_cs_0_1_4_5, 33 &spear310_pmx_emi_cs_0_1_4_5,
34 &pmx_emi_cs_2_3, 34 &spear310_pmx_emi_cs_2_3,
35 &pmx_uart1, 35 &spear310_pmx_uart1,
36 &pmx_uart2, 36 &spear310_pmx_uart2,
37 &pmx_uart3_4_5, 37 &spear310_pmx_uart3_4_5,
38 &pmx_fsmc, 38 &spear310_pmx_fsmc,
39 &pmx_rs485_0_1, 39 &spear310_pmx_rs485_0_1,
40 &pmx_tdm0, 40 &spear310_pmx_tdm0,
41}; 41};
42 42
43static struct amba_device *amba_devs[] __initdata = { 43static struct amba_device *amba_devs[] __initdata = {
44 /* spear3xx specific devices */ 44 /* spear3xx specific devices */
45 &gpio_device, 45 &spear3xx_gpio_device,
46 &uart_device, 46 &spear3xx_uart_device,
47 47
48 /* spear310 specific devices */ 48 /* spear310 specific devices */
49}; 49};
@@ -58,13 +58,8 @@ static void __init spear310_evb_init(void)
58{ 58{
59 unsigned int i; 59 unsigned int i;
60 60
61 /* padmux initialization, must be done before spear310_init */
62 pmx_driver.mode = NULL;
63 pmx_driver.devs = pmx_devs;
64 pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
65
66 /* call spear310 machine init function */ 61 /* call spear310 machine init function */
67 spear310_init(); 62 spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
68 63
69 /* Add Platform Devices */ 64 /* Add Platform Devices */
70 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); 65 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 741c1f414cbd..ee29bef43074 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -29,88 +29,88 @@
29#define SMALL_PRINTERS_MODE (1 << 3) 29#define SMALL_PRINTERS_MODE (1 << 3)
30#define ALL_MODES 0xF 30#define ALL_MODES 0xF
31 31
32struct pmx_mode auto_net_smii_mode = { 32struct pmx_mode spear320_auto_net_smii_mode = {
33 .id = AUTO_NET_SMII_MODE, 33 .id = AUTO_NET_SMII_MODE,
34 .name = "Automation Networking SMII Mode", 34 .name = "Automation Networking SMII Mode",
35 .mask = 0x00, 35 .mask = 0x00,
36}; 36};
37 37
38struct pmx_mode auto_net_mii_mode = { 38struct pmx_mode spear320_auto_net_mii_mode = {
39 .id = AUTO_NET_MII_MODE, 39 .id = AUTO_NET_MII_MODE,
40 .name = "Automation Networking MII Mode", 40 .name = "Automation Networking MII Mode",
41 .mask = 0x01, 41 .mask = 0x01,
42}; 42};
43 43
44struct pmx_mode auto_exp_mode = { 44struct pmx_mode spear320_auto_exp_mode = {
45 .id = AUTO_EXP_MODE, 45 .id = AUTO_EXP_MODE,
46 .name = "Automation Expanded Mode", 46 .name = "Automation Expanded Mode",
47 .mask = 0x02, 47 .mask = 0x02,
48}; 48};
49 49
50struct pmx_mode small_printers_mode = { 50struct pmx_mode spear320_small_printers_mode = {
51 .id = SMALL_PRINTERS_MODE, 51 .id = SMALL_PRINTERS_MODE,
52 .name = "Small Printers Mode", 52 .name = "Small Printers Mode",
53 .mask = 0x03, 53 .mask = 0x03,
54}; 54};
55 55
56/* devices */ 56/* devices */
57struct pmx_dev_mode pmx_clcd_modes[] = { 57static struct pmx_dev_mode pmx_clcd_modes[] = {
58 { 58 {
59 .ids = AUTO_NET_SMII_MODE, 59 .ids = AUTO_NET_SMII_MODE,
60 .mask = 0x0, 60 .mask = 0x0,
61 }, 61 },
62}; 62};
63 63
64struct pmx_dev pmx_clcd = { 64struct pmx_dev spear320_pmx_clcd = {
65 .name = "clcd", 65 .name = "clcd",
66 .modes = pmx_clcd_modes, 66 .modes = pmx_clcd_modes,
67 .mode_count = ARRAY_SIZE(pmx_clcd_modes), 67 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
68 .enb_on_reset = 1, 68 .enb_on_reset = 1,
69}; 69};
70 70
71struct pmx_dev_mode pmx_emi_modes[] = { 71static struct pmx_dev_mode pmx_emi_modes[] = {
72 { 72 {
73 .ids = AUTO_EXP_MODE, 73 .ids = AUTO_EXP_MODE,
74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, 74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
75 }, 75 },
76}; 76};
77 77
78struct pmx_dev pmx_emi = { 78struct pmx_dev spear320_pmx_emi = {
79 .name = "emi", 79 .name = "emi",
80 .modes = pmx_emi_modes, 80 .modes = pmx_emi_modes,
81 .mode_count = ARRAY_SIZE(pmx_emi_modes), 81 .mode_count = ARRAY_SIZE(pmx_emi_modes),
82 .enb_on_reset = 1, 82 .enb_on_reset = 1,
83}; 83};
84 84
85struct pmx_dev_mode pmx_fsmc_modes[] = { 85static struct pmx_dev_mode pmx_fsmc_modes[] = {
86 { 86 {
87 .ids = ALL_MODES, 87 .ids = ALL_MODES,
88 .mask = 0x0, 88 .mask = 0x0,
89 }, 89 },
90}; 90};
91 91
92struct pmx_dev pmx_fsmc = { 92struct pmx_dev spear320_pmx_fsmc = {
93 .name = "fsmc", 93 .name = "fsmc",
94 .modes = pmx_fsmc_modes, 94 .modes = pmx_fsmc_modes,
95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes), 95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
96 .enb_on_reset = 1, 96 .enb_on_reset = 1,
97}; 97};
98 98
99struct pmx_dev_mode pmx_spp_modes[] = { 99static struct pmx_dev_mode pmx_spp_modes[] = {
100 { 100 {
101 .ids = SMALL_PRINTERS_MODE, 101 .ids = SMALL_PRINTERS_MODE,
102 .mask = 0x0, 102 .mask = 0x0,
103 }, 103 },
104}; 104};
105 105
106struct pmx_dev pmx_spp = { 106struct pmx_dev spear320_pmx_spp = {
107 .name = "spp", 107 .name = "spp",
108 .modes = pmx_spp_modes, 108 .modes = pmx_spp_modes,
109 .mode_count = ARRAY_SIZE(pmx_spp_modes), 109 .mode_count = ARRAY_SIZE(pmx_spp_modes),
110 .enb_on_reset = 1, 110 .enb_on_reset = 1,
111}; 111};
112 112
113struct pmx_dev_mode pmx_sdhci_modes[] = { 113static struct pmx_dev_mode pmx_sdhci_modes[] = {
114 { 114 {
115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | 115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
116 SMALL_PRINTERS_MODE, 116 SMALL_PRINTERS_MODE,
@@ -118,42 +118,42 @@ struct pmx_dev_mode pmx_sdhci_modes[] = {
118 }, 118 },
119}; 119};
120 120
121struct pmx_dev pmx_sdhci = { 121struct pmx_dev spear320_pmx_sdhci = {
122 .name = "sdhci", 122 .name = "sdhci",
123 .modes = pmx_sdhci_modes, 123 .modes = pmx_sdhci_modes,
124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes), 124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
125 .enb_on_reset = 1, 125 .enb_on_reset = 1,
126}; 126};
127 127
128struct pmx_dev_mode pmx_i2s_modes[] = { 128static struct pmx_dev_mode pmx_i2s_modes[] = {
129 { 129 {
130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
131 .mask = PMX_UART0_MODEM_MASK, 131 .mask = PMX_UART0_MODEM_MASK,
132 }, 132 },
133}; 133};
134 134
135struct pmx_dev pmx_i2s = { 135struct pmx_dev spear320_pmx_i2s = {
136 .name = "i2s", 136 .name = "i2s",
137 .modes = pmx_i2s_modes, 137 .modes = pmx_i2s_modes,
138 .mode_count = ARRAY_SIZE(pmx_i2s_modes), 138 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
139 .enb_on_reset = 1, 139 .enb_on_reset = 1,
140}; 140};
141 141
142struct pmx_dev_mode pmx_uart1_modes[] = { 142static struct pmx_dev_mode pmx_uart1_modes[] = {
143 { 143 {
144 .ids = ALL_MODES, 144 .ids = ALL_MODES,
145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, 145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
146 }, 146 },
147}; 147};
148 148
149struct pmx_dev pmx_uart1 = { 149struct pmx_dev spear320_pmx_uart1 = {
150 .name = "uart1", 150 .name = "uart1",
151 .modes = pmx_uart1_modes, 151 .modes = pmx_uart1_modes,
152 .mode_count = ARRAY_SIZE(pmx_uart1_modes), 152 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
153 .enb_on_reset = 1, 153 .enb_on_reset = 1,
154}; 154};
155 155
156struct pmx_dev_mode pmx_uart1_modem_modes[] = { 156static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
157 { 157 {
158 .ids = AUTO_EXP_MODE, 158 .ids = AUTO_EXP_MODE,
159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | 159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
@@ -165,42 +165,42 @@ struct pmx_dev_mode pmx_uart1_modem_modes[] = {
165 }, 165 },
166}; 166};
167 167
168struct pmx_dev pmx_uart1_modem = { 168struct pmx_dev spear320_pmx_uart1_modem = {
169 .name = "uart1_modem", 169 .name = "uart1_modem",
170 .modes = pmx_uart1_modem_modes, 170 .modes = pmx_uart1_modem_modes,
171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), 171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
172 .enb_on_reset = 1, 172 .enb_on_reset = 1,
173}; 173};
174 174
175struct pmx_dev_mode pmx_uart2_modes[] = { 175static struct pmx_dev_mode pmx_uart2_modes[] = {
176 { 176 {
177 .ids = ALL_MODES, 177 .ids = ALL_MODES,
178 .mask = PMX_FIRDA_MASK, 178 .mask = PMX_FIRDA_MASK,
179 }, 179 },
180}; 180};
181 181
182struct pmx_dev pmx_uart2 = { 182struct pmx_dev spear320_pmx_uart2 = {
183 .name = "uart2", 183 .name = "uart2",
184 .modes = pmx_uart2_modes, 184 .modes = pmx_uart2_modes,
185 .mode_count = ARRAY_SIZE(pmx_uart2_modes), 185 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
186 .enb_on_reset = 1, 186 .enb_on_reset = 1,
187}; 187};
188 188
189struct pmx_dev_mode pmx_touchscreen_modes[] = { 189static struct pmx_dev_mode pmx_touchscreen_modes[] = {
190 { 190 {
191 .ids = AUTO_NET_SMII_MODE, 191 .ids = AUTO_NET_SMII_MODE,
192 .mask = PMX_SSP_CS_MASK, 192 .mask = PMX_SSP_CS_MASK,
193 }, 193 },
194}; 194};
195 195
196struct pmx_dev pmx_touchscreen = { 196struct pmx_dev spear320_pmx_touchscreen = {
197 .name = "touchscreen", 197 .name = "touchscreen",
198 .modes = pmx_touchscreen_modes, 198 .modes = pmx_touchscreen_modes,
199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), 199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
200 .enb_on_reset = 1, 200 .enb_on_reset = 1,
201}; 201};
202 202
203struct pmx_dev_mode pmx_can_modes[] = { 203static struct pmx_dev_mode pmx_can_modes[] = {
204 { 204 {
205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, 205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
@@ -208,28 +208,28 @@ struct pmx_dev_mode pmx_can_modes[] = {
208 }, 208 },
209}; 209};
210 210
211struct pmx_dev pmx_can = { 211struct pmx_dev spear320_pmx_can = {
212 .name = "can", 212 .name = "can",
213 .modes = pmx_can_modes, 213 .modes = pmx_can_modes,
214 .mode_count = ARRAY_SIZE(pmx_can_modes), 214 .mode_count = ARRAY_SIZE(pmx_can_modes),
215 .enb_on_reset = 1, 215 .enb_on_reset = 1,
216}; 216};
217 217
218struct pmx_dev_mode pmx_sdhci_led_modes[] = { 218static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
219 { 219 {
220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
221 .mask = PMX_SSP_CS_MASK, 221 .mask = PMX_SSP_CS_MASK,
222 }, 222 },
223}; 223};
224 224
225struct pmx_dev pmx_sdhci_led = { 225struct pmx_dev spear320_pmx_sdhci_led = {
226 .name = "sdhci_led", 226 .name = "sdhci_led",
227 .modes = pmx_sdhci_led_modes, 227 .modes = pmx_sdhci_led_modes,
228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), 228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
229 .enb_on_reset = 1, 229 .enb_on_reset = 1,
230}; 230};
231 231
232struct pmx_dev_mode pmx_pwm0_modes[] = { 232static struct pmx_dev_mode pmx_pwm0_modes[] = {
233 { 233 {
234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
235 .mask = PMX_UART0_MODEM_MASK, 235 .mask = PMX_UART0_MODEM_MASK,
@@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_pwm0_modes[] = {
239 }, 239 },
240}; 240};
241 241
242struct pmx_dev pmx_pwm0 = { 242struct pmx_dev spear320_pmx_pwm0 = {
243 .name = "pwm0", 243 .name = "pwm0",
244 .modes = pmx_pwm0_modes, 244 .modes = pmx_pwm0_modes,
245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes), 245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
246 .enb_on_reset = 1, 246 .enb_on_reset = 1,
247}; 247};
248 248
249struct pmx_dev_mode pmx_pwm1_modes[] = { 249static struct pmx_dev_mode pmx_pwm1_modes[] = {
250 { 250 {
251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
252 .mask = PMX_UART0_MODEM_MASK, 252 .mask = PMX_UART0_MODEM_MASK,
@@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_pwm1_modes[] = {
256 }, 256 },
257}; 257};
258 258
259struct pmx_dev pmx_pwm1 = { 259struct pmx_dev spear320_pmx_pwm1 = {
260 .name = "pwm1", 260 .name = "pwm1",
261 .modes = pmx_pwm1_modes, 261 .modes = pmx_pwm1_modes,
262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes), 262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
263 .enb_on_reset = 1, 263 .enb_on_reset = 1,
264}; 264};
265 265
266struct pmx_dev_mode pmx_pwm2_modes[] = { 266static struct pmx_dev_mode pmx_pwm2_modes[] = {
267 { 267 {
268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
269 .mask = PMX_SSP_CS_MASK, 269 .mask = PMX_SSP_CS_MASK,
@@ -273,105 +273,105 @@ struct pmx_dev_mode pmx_pwm2_modes[] = {
273 }, 273 },
274}; 274};
275 275
276struct pmx_dev pmx_pwm2 = { 276struct pmx_dev spear320_pmx_pwm2 = {
277 .name = "pwm2", 277 .name = "pwm2",
278 .modes = pmx_pwm2_modes, 278 .modes = pmx_pwm2_modes,
279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes), 279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
280 .enb_on_reset = 1, 280 .enb_on_reset = 1,
281}; 281};
282 282
283struct pmx_dev_mode pmx_pwm3_modes[] = { 283static struct pmx_dev_mode pmx_pwm3_modes[] = {
284 { 284 {
285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
286 .mask = PMX_MII_MASK, 286 .mask = PMX_MII_MASK,
287 }, 287 },
288}; 288};
289 289
290struct pmx_dev pmx_pwm3 = { 290struct pmx_dev spear320_pmx_pwm3 = {
291 .name = "pwm3", 291 .name = "pwm3",
292 .modes = pmx_pwm3_modes, 292 .modes = pmx_pwm3_modes,
293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes), 293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
294 .enb_on_reset = 1, 294 .enb_on_reset = 1,
295}; 295};
296 296
297struct pmx_dev_mode pmx_ssp1_modes[] = { 297static struct pmx_dev_mode pmx_ssp1_modes[] = {
298 { 298 {
299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
300 .mask = PMX_MII_MASK, 300 .mask = PMX_MII_MASK,
301 }, 301 },
302}; 302};
303 303
304struct pmx_dev pmx_ssp1 = { 304struct pmx_dev spear320_pmx_ssp1 = {
305 .name = "ssp1", 305 .name = "ssp1",
306 .modes = pmx_ssp1_modes, 306 .modes = pmx_ssp1_modes,
307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes), 307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
308 .enb_on_reset = 1, 308 .enb_on_reset = 1,
309}; 309};
310 310
311struct pmx_dev_mode pmx_ssp2_modes[] = { 311static struct pmx_dev_mode pmx_ssp2_modes[] = {
312 { 312 {
313 .ids = AUTO_NET_SMII_MODE, 313 .ids = AUTO_NET_SMII_MODE,
314 .mask = PMX_MII_MASK, 314 .mask = PMX_MII_MASK,
315 }, 315 },
316}; 316};
317 317
318struct pmx_dev pmx_ssp2 = { 318struct pmx_dev spear320_pmx_ssp2 = {
319 .name = "ssp2", 319 .name = "ssp2",
320 .modes = pmx_ssp2_modes, 320 .modes = pmx_ssp2_modes,
321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes), 321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
322 .enb_on_reset = 1, 322 .enb_on_reset = 1,
323}; 323};
324 324
325struct pmx_dev_mode pmx_mii1_modes[] = { 325static struct pmx_dev_mode pmx_mii1_modes[] = {
326 { 326 {
327 .ids = AUTO_NET_MII_MODE, 327 .ids = AUTO_NET_MII_MODE,
328 .mask = 0x0, 328 .mask = 0x0,
329 }, 329 },
330}; 330};
331 331
332struct pmx_dev pmx_mii1 = { 332struct pmx_dev spear320_pmx_mii1 = {
333 .name = "mii1", 333 .name = "mii1",
334 .modes = pmx_mii1_modes, 334 .modes = pmx_mii1_modes,
335 .mode_count = ARRAY_SIZE(pmx_mii1_modes), 335 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
336 .enb_on_reset = 1, 336 .enb_on_reset = 1,
337}; 337};
338 338
339struct pmx_dev_mode pmx_smii0_modes[] = { 339static struct pmx_dev_mode pmx_smii0_modes[] = {
340 { 340 {
341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, 341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
342 .mask = PMX_MII_MASK, 342 .mask = PMX_MII_MASK,
343 }, 343 },
344}; 344};
345 345
346struct pmx_dev pmx_smii0 = { 346struct pmx_dev spear320_pmx_smii0 = {
347 .name = "smii0", 347 .name = "smii0",
348 .modes = pmx_smii0_modes, 348 .modes = pmx_smii0_modes,
349 .mode_count = ARRAY_SIZE(pmx_smii0_modes), 349 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
350 .enb_on_reset = 1, 350 .enb_on_reset = 1,
351}; 351};
352 352
353struct pmx_dev_mode pmx_smii1_modes[] = { 353static struct pmx_dev_mode pmx_smii1_modes[] = {
354 { 354 {
355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, 355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
356 .mask = PMX_MII_MASK, 356 .mask = PMX_MII_MASK,
357 }, 357 },
358}; 358};
359 359
360struct pmx_dev pmx_smii1 = { 360struct pmx_dev spear320_pmx_smii1 = {
361 .name = "smii1", 361 .name = "smii1",
362 .modes = pmx_smii1_modes, 362 .modes = pmx_smii1_modes,
363 .mode_count = ARRAY_SIZE(pmx_smii1_modes), 363 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
364 .enb_on_reset = 1, 364 .enb_on_reset = 1,
365}; 365};
366 366
367struct pmx_dev_mode pmx_i2c1_modes[] = { 367static struct pmx_dev_mode pmx_i2c1_modes[] = {
368 { 368 {
369 .ids = AUTO_EXP_MODE, 369 .ids = AUTO_EXP_MODE,
370 .mask = 0x0, 370 .mask = 0x0,
371 }, 371 },
372}; 372};
373 373
374struct pmx_dev pmx_i2c1 = { 374struct pmx_dev spear320_pmx_i2c1 = {
375 .name = "i2c1", 375 .name = "i2c1",
376 .modes = pmx_i2c1_modes, 376 .modes = pmx_i2c1_modes,
377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes), 377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
@@ -379,131 +379,131 @@ struct pmx_dev pmx_i2c1 = {
379}; 379};
380 380
381/* pmx driver structure */ 381/* pmx driver structure */
382struct pmx_driver pmx_driver = { 382static struct pmx_driver pmx_driver = {
383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, 383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
385}; 385};
386 386
387/* spear3xx shared irq */ 387/* spear3xx shared irq */
388struct shirq_dev_config shirq_ras1_config[] = { 388static struct shirq_dev_config shirq_ras1_config[] = {
389 { 389 {
390 .virq = VIRQ_EMI, 390 .virq = SPEAR320_VIRQ_EMI,
391 .status_mask = EMI_IRQ_MASK, 391 .status_mask = SPEAR320_EMI_IRQ_MASK,
392 .clear_mask = EMI_IRQ_MASK, 392 .clear_mask = SPEAR320_EMI_IRQ_MASK,
393 }, { 393 }, {
394 .virq = VIRQ_CLCD, 394 .virq = SPEAR320_VIRQ_CLCD,
395 .status_mask = CLCD_IRQ_MASK, 395 .status_mask = SPEAR320_CLCD_IRQ_MASK,
396 .clear_mask = CLCD_IRQ_MASK, 396 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
397 }, { 397 }, {
398 .virq = VIRQ_SPP, 398 .virq = SPEAR320_VIRQ_SPP,
399 .status_mask = SPP_IRQ_MASK, 399 .status_mask = SPEAR320_SPP_IRQ_MASK,
400 .clear_mask = SPP_IRQ_MASK, 400 .clear_mask = SPEAR320_SPP_IRQ_MASK,
401 }, 401 },
402}; 402};
403 403
404struct spear_shirq shirq_ras1 = { 404static struct spear_shirq shirq_ras1 = {
405 .irq = IRQ_GEN_RAS_1, 405 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
406 .dev_config = shirq_ras1_config, 406 .dev_config = shirq_ras1_config,
407 .dev_count = ARRAY_SIZE(shirq_ras1_config), 407 .dev_count = ARRAY_SIZE(shirq_ras1_config),
408 .regs = { 408 .regs = {
409 .enb_reg = -1, 409 .enb_reg = -1,
410 .status_reg = INT_STS_MASK_REG, 410 .status_reg = SPEAR320_INT_STS_MASK_REG,
411 .status_reg_mask = SHIRQ_RAS1_MASK, 411 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
412 .clear_reg = INT_CLR_MASK_REG, 412 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
413 .reset_to_clear = 1, 413 .reset_to_clear = 1,
414 }, 414 },
415}; 415};
416 416
417struct shirq_dev_config shirq_ras3_config[] = { 417static struct shirq_dev_config shirq_ras3_config[] = {
418 { 418 {
419 .virq = VIRQ_PLGPIO, 419 .virq = SPEAR320_VIRQ_PLGPIO,
420 .enb_mask = GPIO_IRQ_MASK, 420 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
421 .status_mask = GPIO_IRQ_MASK, 421 .status_mask = SPEAR320_GPIO_IRQ_MASK,
422 .clear_mask = GPIO_IRQ_MASK, 422 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
423 }, { 423 }, {
424 .virq = VIRQ_I2S_PLAY, 424 .virq = SPEAR320_VIRQ_I2S_PLAY,
425 .enb_mask = I2S_PLAY_IRQ_MASK, 425 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
426 .status_mask = I2S_PLAY_IRQ_MASK, 426 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
427 .clear_mask = I2S_PLAY_IRQ_MASK, 427 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
428 }, { 428 }, {
429 .virq = VIRQ_I2S_REC, 429 .virq = SPEAR320_VIRQ_I2S_REC,
430 .enb_mask = I2S_REC_IRQ_MASK, 430 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
431 .status_mask = I2S_REC_IRQ_MASK, 431 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
432 .clear_mask = I2S_REC_IRQ_MASK, 432 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
433 }, 433 },
434}; 434};
435 435
436struct spear_shirq shirq_ras3 = { 436static struct spear_shirq shirq_ras3 = {
437 .irq = IRQ_GEN_RAS_3, 437 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
438 .dev_config = shirq_ras3_config, 438 .dev_config = shirq_ras3_config,
439 .dev_count = ARRAY_SIZE(shirq_ras3_config), 439 .dev_count = ARRAY_SIZE(shirq_ras3_config),
440 .regs = { 440 .regs = {
441 .enb_reg = INT_ENB_MASK_REG, 441 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
442 .reset_to_enb = 1, 442 .reset_to_enb = 1,
443 .status_reg = INT_STS_MASK_REG, 443 .status_reg = SPEAR320_INT_STS_MASK_REG,
444 .status_reg_mask = SHIRQ_RAS3_MASK, 444 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
445 .clear_reg = INT_CLR_MASK_REG, 445 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
446 .reset_to_clear = 1, 446 .reset_to_clear = 1,
447 }, 447 },
448}; 448};
449 449
450struct shirq_dev_config shirq_intrcomm_ras_config[] = { 450static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
451 { 451 {
452 .virq = VIRQ_CANU, 452 .virq = SPEAR320_VIRQ_CANU,
453 .status_mask = CAN_U_IRQ_MASK, 453 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
454 .clear_mask = CAN_U_IRQ_MASK, 454 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
455 }, { 455 }, {
456 .virq = VIRQ_CANL, 456 .virq = SPEAR320_VIRQ_CANL,
457 .status_mask = CAN_L_IRQ_MASK, 457 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
458 .clear_mask = CAN_L_IRQ_MASK, 458 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
459 }, { 459 }, {
460 .virq = VIRQ_UART1, 460 .virq = SPEAR320_VIRQ_UART1,
461 .status_mask = UART1_IRQ_MASK, 461 .status_mask = SPEAR320_UART1_IRQ_MASK,
462 .clear_mask = UART1_IRQ_MASK, 462 .clear_mask = SPEAR320_UART1_IRQ_MASK,
463 }, { 463 }, {
464 .virq = VIRQ_UART2, 464 .virq = SPEAR320_VIRQ_UART2,
465 .status_mask = UART2_IRQ_MASK, 465 .status_mask = SPEAR320_UART2_IRQ_MASK,
466 .clear_mask = UART2_IRQ_MASK, 466 .clear_mask = SPEAR320_UART2_IRQ_MASK,
467 }, { 467 }, {
468 .virq = VIRQ_SSP1, 468 .virq = SPEAR320_VIRQ_SSP1,
469 .status_mask = SSP1_IRQ_MASK, 469 .status_mask = SPEAR320_SSP1_IRQ_MASK,
470 .clear_mask = SSP1_IRQ_MASK, 470 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
471 }, { 471 }, {
472 .virq = VIRQ_SSP2, 472 .virq = SPEAR320_VIRQ_SSP2,
473 .status_mask = SSP2_IRQ_MASK, 473 .status_mask = SPEAR320_SSP2_IRQ_MASK,
474 .clear_mask = SSP2_IRQ_MASK, 474 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
475 }, { 475 }, {
476 .virq = VIRQ_SMII0, 476 .virq = SPEAR320_VIRQ_SMII0,
477 .status_mask = SMII0_IRQ_MASK, 477 .status_mask = SPEAR320_SMII0_IRQ_MASK,
478 .clear_mask = SMII0_IRQ_MASK, 478 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
479 }, { 479 }, {
480 .virq = VIRQ_MII1_SMII1, 480 .virq = SPEAR320_VIRQ_MII1_SMII1,
481 .status_mask = MII1_SMII1_IRQ_MASK, 481 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
482 .clear_mask = MII1_SMII1_IRQ_MASK, 482 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
483 }, { 483 }, {
484 .virq = VIRQ_WAKEUP_SMII0, 484 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
485 .status_mask = WAKEUP_SMII0_IRQ_MASK, 485 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
486 .clear_mask = WAKEUP_SMII0_IRQ_MASK, 486 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
487 }, { 487 }, {
488 .virq = VIRQ_WAKEUP_MII1_SMII1, 488 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
489 .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 489 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
490 .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 490 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
491 }, { 491 }, {
492 .virq = VIRQ_I2C, 492 .virq = SPEAR320_VIRQ_I2C1,
493 .status_mask = I2C1_IRQ_MASK, 493 .status_mask = SPEAR320_I2C1_IRQ_MASK,
494 .clear_mask = I2C1_IRQ_MASK, 494 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
495 }, 495 },
496}; 496};
497 497
498struct spear_shirq shirq_intrcomm_ras = { 498static struct spear_shirq shirq_intrcomm_ras = {
499 .irq = IRQ_INTRCOMM_RAS_ARM, 499 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
500 .dev_config = shirq_intrcomm_ras_config, 500 .dev_config = shirq_intrcomm_ras_config,
501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
502 .regs = { 502 .regs = {
503 .enb_reg = -1, 503 .enb_reg = -1,
504 .status_reg = INT_STS_MASK_REG, 504 .status_reg = SPEAR320_INT_STS_MASK_REG,
505 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, 505 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
506 .clear_reg = INT_CLR_MASK_REG, 506 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
507 .reset_to_clear = 1, 507 .reset_to_clear = 1,
508 }, 508 },
509}; 509};
@@ -511,7 +511,8 @@ struct spear_shirq shirq_intrcomm_ras = {
511/* Add spear320 specific devices here */ 511/* Add spear320 specific devices here */
512 512
513/* spear320 routines */ 513/* spear320 routines */
514void __init spear320_init(void) 514void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
515 u8 pmx_dev_count)
515{ 516{
516 void __iomem *base; 517 void __iomem *base;
517 int ret = 0; 518 int ret = 0;
@@ -543,6 +544,10 @@ void __init spear320_init(void)
543 544
544 /* pmx initialization */ 545 /* pmx initialization */
545 pmx_driver.base = base; 546 pmx_driver.base = base;
547 pmx_driver.mode = pmx_mode;
548 pmx_driver.devs = pmx_devs;
549 pmx_driver.devs_count = pmx_dev_count;
550
546 ret = pmx_register(&pmx_driver); 551 ret = pmx_register(&pmx_driver);
547 if (ret) 552 if (ret)
548 printk(KERN_ERR "padmux: registeration failed. err no: %d\n", 553 printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 8213e4b66c14..a12b353940d6 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -19,28 +19,28 @@
19/* padmux devices to enable */ 19/* padmux devices to enable */
20static struct pmx_dev *pmx_devs[] = { 20static struct pmx_dev *pmx_devs[] = {
21 /* spear3xx specific devices */ 21 /* spear3xx specific devices */
22 &pmx_i2c, 22 &spear3xx_pmx_i2c,
23 &pmx_ssp, 23 &spear3xx_pmx_ssp,
24 &pmx_mii, 24 &spear3xx_pmx_mii,
25 &pmx_uart0, 25 &spear3xx_pmx_uart0,
26 26
27 /* spear320 specific devices */ 27 /* spear320 specific devices */
28 &pmx_fsmc, 28 &spear320_pmx_fsmc,
29 &pmx_sdhci, 29 &spear320_pmx_sdhci,
30 &pmx_i2s, 30 &spear320_pmx_i2s,
31 &pmx_uart1, 31 &spear320_pmx_uart1,
32 &pmx_uart2, 32 &spear320_pmx_uart2,
33 &pmx_can, 33 &spear320_pmx_can,
34 &pmx_pwm0, 34 &spear320_pmx_pwm0,
35 &pmx_pwm1, 35 &spear320_pmx_pwm1,
36 &pmx_pwm2, 36 &spear320_pmx_pwm2,
37 &pmx_mii1, 37 &spear320_pmx_mii1,
38}; 38};
39 39
40static struct amba_device *amba_devs[] __initdata = { 40static struct amba_device *amba_devs[] __initdata = {
41 /* spear3xx specific devices */ 41 /* spear3xx specific devices */
42 &gpio_device, 42 &spear3xx_gpio_device,
43 &uart_device, 43 &spear3xx_uart_device,
44 44
45 /* spear320 specific devices */ 45 /* spear320 specific devices */
46}; 46};
@@ -55,13 +55,9 @@ static void __init spear320_evb_init(void)
55{ 55{
56 unsigned int i; 56 unsigned int i;
57 57
58 /* padmux initialization, must be done before spear320_init */
59 pmx_driver.mode = &auto_net_mii_mode;
60 pmx_driver.devs = pmx_devs;
61 pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
62
63 /* call spear320 machine init function */ 58 /* call spear320 machine init function */
64 spear320_init(); 59 spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
60 ARRAY_SIZE(pmx_devs));
65 61
66 /* Add Platform Devices */ 62 /* Add Platform Devices */
67 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); 63 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index d3ba8ca1bc59..10af45da86a0 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -25,10 +25,10 @@
25/* gpio device registration */ 25/* gpio device registration */
26static struct pl061_platform_data gpio_plat_data = { 26static struct pl061_platform_data gpio_plat_data = {
27 .gpio_base = 0, 27 .gpio_base = 0,
28 .irq_base = SPEAR_GPIO_INT_BASE, 28 .irq_base = SPEAR3XX_GPIO_INT_BASE,
29}; 29};
30 30
31struct amba_device gpio_device = { 31struct amba_device spear3xx_gpio_device = {
32 .dev = { 32 .dev = {
33 .init_name = "gpio", 33 .init_name = "gpio",
34 .platform_data = &gpio_plat_data, 34 .platform_data = &gpio_plat_data,
@@ -38,11 +38,11 @@ struct amba_device gpio_device = {
38 .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1, 38 .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
39 .flags = IORESOURCE_MEM, 39 .flags = IORESOURCE_MEM,
40 }, 40 },
41 .irq = {IRQ_BASIC_GPIO, NO_IRQ}, 41 .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
42}; 42};
43 43
44/* uart device registration */ 44/* uart device registration */
45struct amba_device uart_device = { 45struct amba_device spear3xx_uart_device = {
46 .dev = { 46 .dev = {
47 .init_name = "uart", 47 .init_name = "uart",
48 }, 48 },
@@ -51,7 +51,7 @@ struct amba_device uart_device = {
51 .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1, 51 .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
52 .flags = IORESOURCE_MEM, 52 .flags = IORESOURCE_MEM,
53 }, 53 },
54 .irq = {IRQ_UART, NO_IRQ}, 54 .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
55}; 55};
56 56
57/* Do spear3xx familiy common initialization part here */ 57/* Do spear3xx familiy common initialization part here */
@@ -97,215 +97,215 @@ void __init spear3xx_map_io(void)
97 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); 97 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
98 98
99 /* This will initialize clock framework */ 99 /* This will initialize clock framework */
100 clk_init(); 100 spear3xx_clk_init();
101} 101}
102 102
103/* pad multiplexing support */ 103/* pad multiplexing support */
104/* devices */ 104/* devices */
105struct pmx_dev_mode pmx_firda_modes[] = { 105static struct pmx_dev_mode pmx_firda_modes[] = {
106 { 106 {
107 .ids = 0xffffffff, 107 .ids = 0xffffffff,
108 .mask = PMX_FIRDA_MASK, 108 .mask = PMX_FIRDA_MASK,
109 }, 109 },
110}; 110};
111 111
112struct pmx_dev pmx_firda = { 112struct pmx_dev spear3xx_pmx_firda = {
113 .name = "firda", 113 .name = "firda",
114 .modes = pmx_firda_modes, 114 .modes = pmx_firda_modes,
115 .mode_count = ARRAY_SIZE(pmx_firda_modes), 115 .mode_count = ARRAY_SIZE(pmx_firda_modes),
116 .enb_on_reset = 0, 116 .enb_on_reset = 0,
117}; 117};
118 118
119struct pmx_dev_mode pmx_i2c_modes[] = { 119static struct pmx_dev_mode pmx_i2c_modes[] = {
120 { 120 {
121 .ids = 0xffffffff, 121 .ids = 0xffffffff,
122 .mask = PMX_I2C_MASK, 122 .mask = PMX_I2C_MASK,
123 }, 123 },
124}; 124};
125 125
126struct pmx_dev pmx_i2c = { 126struct pmx_dev spear3xx_pmx_i2c = {
127 .name = "i2c", 127 .name = "i2c",
128 .modes = pmx_i2c_modes, 128 .modes = pmx_i2c_modes,
129 .mode_count = ARRAY_SIZE(pmx_i2c_modes), 129 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
130 .enb_on_reset = 0, 130 .enb_on_reset = 0,
131}; 131};
132 132
133struct pmx_dev_mode pmx_ssp_cs_modes[] = { 133static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
134 { 134 {
135 .ids = 0xffffffff, 135 .ids = 0xffffffff,
136 .mask = PMX_SSP_CS_MASK, 136 .mask = PMX_SSP_CS_MASK,
137 }, 137 },
138}; 138};
139 139
140struct pmx_dev pmx_ssp_cs = { 140struct pmx_dev spear3xx_pmx_ssp_cs = {
141 .name = "ssp_chip_selects", 141 .name = "ssp_chip_selects",
142 .modes = pmx_ssp_cs_modes, 142 .modes = pmx_ssp_cs_modes,
143 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), 143 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
144 .enb_on_reset = 0, 144 .enb_on_reset = 0,
145}; 145};
146 146
147struct pmx_dev_mode pmx_ssp_modes[] = { 147static struct pmx_dev_mode pmx_ssp_modes[] = {
148 { 148 {
149 .ids = 0xffffffff, 149 .ids = 0xffffffff,
150 .mask = PMX_SSP_MASK, 150 .mask = PMX_SSP_MASK,
151 }, 151 },
152}; 152};
153 153
154struct pmx_dev pmx_ssp = { 154struct pmx_dev spear3xx_pmx_ssp = {
155 .name = "ssp", 155 .name = "ssp",
156 .modes = pmx_ssp_modes, 156 .modes = pmx_ssp_modes,
157 .mode_count = ARRAY_SIZE(pmx_ssp_modes), 157 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
158 .enb_on_reset = 0, 158 .enb_on_reset = 0,
159}; 159};
160 160
161struct pmx_dev_mode pmx_mii_modes[] = { 161static struct pmx_dev_mode pmx_mii_modes[] = {
162 { 162 {
163 .ids = 0xffffffff, 163 .ids = 0xffffffff,
164 .mask = PMX_MII_MASK, 164 .mask = PMX_MII_MASK,
165 }, 165 },
166}; 166};
167 167
168struct pmx_dev pmx_mii = { 168struct pmx_dev spear3xx_pmx_mii = {
169 .name = "mii", 169 .name = "mii",
170 .modes = pmx_mii_modes, 170 .modes = pmx_mii_modes,
171 .mode_count = ARRAY_SIZE(pmx_mii_modes), 171 .mode_count = ARRAY_SIZE(pmx_mii_modes),
172 .enb_on_reset = 0, 172 .enb_on_reset = 0,
173}; 173};
174 174
175struct pmx_dev_mode pmx_gpio_pin0_modes[] = { 175static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
176 { 176 {
177 .ids = 0xffffffff, 177 .ids = 0xffffffff,
178 .mask = PMX_GPIO_PIN0_MASK, 178 .mask = PMX_GPIO_PIN0_MASK,
179 }, 179 },
180}; 180};
181 181
182struct pmx_dev pmx_gpio_pin0 = { 182struct pmx_dev spear3xx_pmx_gpio_pin0 = {
183 .name = "gpio_pin0", 183 .name = "gpio_pin0",
184 .modes = pmx_gpio_pin0_modes, 184 .modes = pmx_gpio_pin0_modes,
185 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), 185 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
186 .enb_on_reset = 0, 186 .enb_on_reset = 0,
187}; 187};
188 188
189struct pmx_dev_mode pmx_gpio_pin1_modes[] = { 189static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
190 { 190 {
191 .ids = 0xffffffff, 191 .ids = 0xffffffff,
192 .mask = PMX_GPIO_PIN1_MASK, 192 .mask = PMX_GPIO_PIN1_MASK,
193 }, 193 },
194}; 194};
195 195
196struct pmx_dev pmx_gpio_pin1 = { 196struct pmx_dev spear3xx_pmx_gpio_pin1 = {
197 .name = "gpio_pin1", 197 .name = "gpio_pin1",
198 .modes = pmx_gpio_pin1_modes, 198 .modes = pmx_gpio_pin1_modes,
199 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), 199 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
200 .enb_on_reset = 0, 200 .enb_on_reset = 0,
201}; 201};
202 202
203struct pmx_dev_mode pmx_gpio_pin2_modes[] = { 203static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
204 { 204 {
205 .ids = 0xffffffff, 205 .ids = 0xffffffff,
206 .mask = PMX_GPIO_PIN2_MASK, 206 .mask = PMX_GPIO_PIN2_MASK,
207 }, 207 },
208}; 208};
209 209
210struct pmx_dev pmx_gpio_pin2 = { 210struct pmx_dev spear3xx_pmx_gpio_pin2 = {
211 .name = "gpio_pin2", 211 .name = "gpio_pin2",
212 .modes = pmx_gpio_pin2_modes, 212 .modes = pmx_gpio_pin2_modes,
213 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), 213 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
214 .enb_on_reset = 0, 214 .enb_on_reset = 0,
215}; 215};
216 216
217struct pmx_dev_mode pmx_gpio_pin3_modes[] = { 217static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
218 { 218 {
219 .ids = 0xffffffff, 219 .ids = 0xffffffff,
220 .mask = PMX_GPIO_PIN3_MASK, 220 .mask = PMX_GPIO_PIN3_MASK,
221 }, 221 },
222}; 222};
223 223
224struct pmx_dev pmx_gpio_pin3 = { 224struct pmx_dev spear3xx_pmx_gpio_pin3 = {
225 .name = "gpio_pin3", 225 .name = "gpio_pin3",
226 .modes = pmx_gpio_pin3_modes, 226 .modes = pmx_gpio_pin3_modes,
227 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), 227 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
228 .enb_on_reset = 0, 228 .enb_on_reset = 0,
229}; 229};
230 230
231struct pmx_dev_mode pmx_gpio_pin4_modes[] = { 231static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
232 { 232 {
233 .ids = 0xffffffff, 233 .ids = 0xffffffff,
234 .mask = PMX_GPIO_PIN4_MASK, 234 .mask = PMX_GPIO_PIN4_MASK,
235 }, 235 },
236}; 236};
237 237
238struct pmx_dev pmx_gpio_pin4 = { 238struct pmx_dev spear3xx_pmx_gpio_pin4 = {
239 .name = "gpio_pin4", 239 .name = "gpio_pin4",
240 .modes = pmx_gpio_pin4_modes, 240 .modes = pmx_gpio_pin4_modes,
241 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), 241 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
242 .enb_on_reset = 0, 242 .enb_on_reset = 0,
243}; 243};
244 244
245struct pmx_dev_mode pmx_gpio_pin5_modes[] = { 245static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
246 { 246 {
247 .ids = 0xffffffff, 247 .ids = 0xffffffff,
248 .mask = PMX_GPIO_PIN5_MASK, 248 .mask = PMX_GPIO_PIN5_MASK,
249 }, 249 },
250}; 250};
251 251
252struct pmx_dev pmx_gpio_pin5 = { 252struct pmx_dev spear3xx_pmx_gpio_pin5 = {
253 .name = "gpio_pin5", 253 .name = "gpio_pin5",
254 .modes = pmx_gpio_pin5_modes, 254 .modes = pmx_gpio_pin5_modes,
255 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), 255 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
256 .enb_on_reset = 0, 256 .enb_on_reset = 0,
257}; 257};
258 258
259struct pmx_dev_mode pmx_uart0_modem_modes[] = { 259static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
260 { 260 {
261 .ids = 0xffffffff, 261 .ids = 0xffffffff,
262 .mask = PMX_UART0_MODEM_MASK, 262 .mask = PMX_UART0_MODEM_MASK,
263 }, 263 },
264}; 264};
265 265
266struct pmx_dev pmx_uart0_modem = { 266struct pmx_dev spear3xx_pmx_uart0_modem = {
267 .name = "uart0_modem", 267 .name = "uart0_modem",
268 .modes = pmx_uart0_modem_modes, 268 .modes = pmx_uart0_modem_modes,
269 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), 269 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
270 .enb_on_reset = 0, 270 .enb_on_reset = 0,
271}; 271};
272 272
273struct pmx_dev_mode pmx_uart0_modes[] = { 273static struct pmx_dev_mode pmx_uart0_modes[] = {
274 { 274 {
275 .ids = 0xffffffff, 275 .ids = 0xffffffff,
276 .mask = PMX_UART0_MASK, 276 .mask = PMX_UART0_MASK,
277 }, 277 },
278}; 278};
279 279
280struct pmx_dev pmx_uart0 = { 280struct pmx_dev spear3xx_pmx_uart0 = {
281 .name = "uart0", 281 .name = "uart0",
282 .modes = pmx_uart0_modes, 282 .modes = pmx_uart0_modes,
283 .mode_count = ARRAY_SIZE(pmx_uart0_modes), 283 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
284 .enb_on_reset = 0, 284 .enb_on_reset = 0,
285}; 285};
286 286
287struct pmx_dev_mode pmx_timer_3_4_modes[] = { 287static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
288 { 288 {
289 .ids = 0xffffffff, 289 .ids = 0xffffffff,
290 .mask = PMX_TIMER_3_4_MASK, 290 .mask = PMX_TIMER_3_4_MASK,
291 }, 291 },
292}; 292};
293 293
294struct pmx_dev pmx_timer_3_4 = { 294struct pmx_dev spear3xx_pmx_timer_3_4 = {
295 .name = "timer_3_4", 295 .name = "timer_3_4",
296 .modes = pmx_timer_3_4_modes, 296 .modes = pmx_timer_3_4_modes,
297 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), 297 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
298 .enb_on_reset = 0, 298 .enb_on_reset = 0,
299}; 299};
300 300
301struct pmx_dev_mode pmx_timer_1_2_modes[] = { 301static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
302 { 302 {
303 .ids = 0xffffffff, 303 .ids = 0xffffffff,
304 .mask = PMX_TIMER_1_2_MASK, 304 .mask = PMX_TIMER_1_2_MASK,
305 }, 305 },
306}; 306};
307 307
308struct pmx_dev pmx_timer_1_2 = { 308struct pmx_dev spear3xx_pmx_timer_1_2 = {
309 .name = "timer_1_2", 309 .name = "timer_1_2",
310 .modes = pmx_timer_1_2_modes, 310 .modes = pmx_timer_1_2_modes,
311 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), 311 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
@@ -314,210 +314,210 @@ struct pmx_dev pmx_timer_1_2 = {
314 314
315#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 315#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
316/* plgpios devices */ 316/* plgpios devices */
317struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { 317static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
318 { 318 {
319 .ids = 0x00, 319 .ids = 0x00,
320 .mask = PMX_FIRDA_MASK, 320 .mask = PMX_FIRDA_MASK,
321 }, 321 },
322}; 322};
323 323
324struct pmx_dev pmx_plgpio_0_1 = { 324struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
325 .name = "plgpio 0 and 1", 325 .name = "plgpio 0 and 1",
326 .modes = pmx_plgpio_0_1_modes, 326 .modes = pmx_plgpio_0_1_modes,
327 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), 327 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
328 .enb_on_reset = 1, 328 .enb_on_reset = 1,
329}; 329};
330 330
331struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { 331static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
332 { 332 {
333 .ids = 0x00, 333 .ids = 0x00,
334 .mask = PMX_UART0_MASK, 334 .mask = PMX_UART0_MASK,
335 }, 335 },
336}; 336};
337 337
338struct pmx_dev pmx_plgpio_2_3 = { 338struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
339 .name = "plgpio 2 and 3", 339 .name = "plgpio 2 and 3",
340 .modes = pmx_plgpio_2_3_modes, 340 .modes = pmx_plgpio_2_3_modes,
341 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), 341 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
342 .enb_on_reset = 1, 342 .enb_on_reset = 1,
343}; 343};
344 344
345struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { 345static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
346 { 346 {
347 .ids = 0x00, 347 .ids = 0x00,
348 .mask = PMX_I2C_MASK, 348 .mask = PMX_I2C_MASK,
349 }, 349 },
350}; 350};
351 351
352struct pmx_dev pmx_plgpio_4_5 = { 352struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
353 .name = "plgpio 4 and 5", 353 .name = "plgpio 4 and 5",
354 .modes = pmx_plgpio_4_5_modes, 354 .modes = pmx_plgpio_4_5_modes,
355 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), 355 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
356 .enb_on_reset = 1, 356 .enb_on_reset = 1,
357}; 357};
358 358
359struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { 359static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
360 { 360 {
361 .ids = 0x00, 361 .ids = 0x00,
362 .mask = PMX_SSP_MASK, 362 .mask = PMX_SSP_MASK,
363 }, 363 },
364}; 364};
365 365
366struct pmx_dev pmx_plgpio_6_9 = { 366struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
367 .name = "plgpio 6 to 9", 367 .name = "plgpio 6 to 9",
368 .modes = pmx_plgpio_6_9_modes, 368 .modes = pmx_plgpio_6_9_modes,
369 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), 369 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
370 .enb_on_reset = 1, 370 .enb_on_reset = 1,
371}; 371};
372 372
373struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { 373static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
374 { 374 {
375 .ids = 0x00, 375 .ids = 0x00,
376 .mask = PMX_MII_MASK, 376 .mask = PMX_MII_MASK,
377 }, 377 },
378}; 378};
379 379
380struct pmx_dev pmx_plgpio_10_27 = { 380struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
381 .name = "plgpio 10 to 27", 381 .name = "plgpio 10 to 27",
382 .modes = pmx_plgpio_10_27_modes, 382 .modes = pmx_plgpio_10_27_modes,
383 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), 383 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
384 .enb_on_reset = 1, 384 .enb_on_reset = 1,
385}; 385};
386 386
387struct pmx_dev_mode pmx_plgpio_28_modes[] = { 387static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
388 { 388 {
389 .ids = 0x00, 389 .ids = 0x00,
390 .mask = PMX_GPIO_PIN0_MASK, 390 .mask = PMX_GPIO_PIN0_MASK,
391 }, 391 },
392}; 392};
393 393
394struct pmx_dev pmx_plgpio_28 = { 394struct pmx_dev spear3xx_pmx_plgpio_28 = {
395 .name = "plgpio 28", 395 .name = "plgpio 28",
396 .modes = pmx_plgpio_28_modes, 396 .modes = pmx_plgpio_28_modes,
397 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), 397 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
398 .enb_on_reset = 1, 398 .enb_on_reset = 1,
399}; 399};
400 400
401struct pmx_dev_mode pmx_plgpio_29_modes[] = { 401static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
402 { 402 {
403 .ids = 0x00, 403 .ids = 0x00,
404 .mask = PMX_GPIO_PIN1_MASK, 404 .mask = PMX_GPIO_PIN1_MASK,
405 }, 405 },
406}; 406};
407 407
408struct pmx_dev pmx_plgpio_29 = { 408struct pmx_dev spear3xx_pmx_plgpio_29 = {
409 .name = "plgpio 29", 409 .name = "plgpio 29",
410 .modes = pmx_plgpio_29_modes, 410 .modes = pmx_plgpio_29_modes,
411 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), 411 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
412 .enb_on_reset = 1, 412 .enb_on_reset = 1,
413}; 413};
414 414
415struct pmx_dev_mode pmx_plgpio_30_modes[] = { 415static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
416 { 416 {
417 .ids = 0x00, 417 .ids = 0x00,
418 .mask = PMX_GPIO_PIN2_MASK, 418 .mask = PMX_GPIO_PIN2_MASK,
419 }, 419 },
420}; 420};
421 421
422struct pmx_dev pmx_plgpio_30 = { 422struct pmx_dev spear3xx_pmx_plgpio_30 = {
423 .name = "plgpio 30", 423 .name = "plgpio 30",
424 .modes = pmx_plgpio_30_modes, 424 .modes = pmx_plgpio_30_modes,
425 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), 425 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
426 .enb_on_reset = 1, 426 .enb_on_reset = 1,
427}; 427};
428 428
429struct pmx_dev_mode pmx_plgpio_31_modes[] = { 429static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
430 { 430 {
431 .ids = 0x00, 431 .ids = 0x00,
432 .mask = PMX_GPIO_PIN3_MASK, 432 .mask = PMX_GPIO_PIN3_MASK,
433 }, 433 },
434}; 434};
435 435
436struct pmx_dev pmx_plgpio_31 = { 436struct pmx_dev spear3xx_pmx_plgpio_31 = {
437 .name = "plgpio 31", 437 .name = "plgpio 31",
438 .modes = pmx_plgpio_31_modes, 438 .modes = pmx_plgpio_31_modes,
439 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), 439 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
440 .enb_on_reset = 1, 440 .enb_on_reset = 1,
441}; 441};
442 442
443struct pmx_dev_mode pmx_plgpio_32_modes[] = { 443static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
444 { 444 {
445 .ids = 0x00, 445 .ids = 0x00,
446 .mask = PMX_GPIO_PIN4_MASK, 446 .mask = PMX_GPIO_PIN4_MASK,
447 }, 447 },
448}; 448};
449 449
450struct pmx_dev pmx_plgpio_32 = { 450struct pmx_dev spear3xx_pmx_plgpio_32 = {
451 .name = "plgpio 32", 451 .name = "plgpio 32",
452 .modes = pmx_plgpio_32_modes, 452 .modes = pmx_plgpio_32_modes,
453 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), 453 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
454 .enb_on_reset = 1, 454 .enb_on_reset = 1,
455}; 455};
456 456
457struct pmx_dev_mode pmx_plgpio_33_modes[] = { 457static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
458 { 458 {
459 .ids = 0x00, 459 .ids = 0x00,
460 .mask = PMX_GPIO_PIN5_MASK, 460 .mask = PMX_GPIO_PIN5_MASK,
461 }, 461 },
462}; 462};
463 463
464struct pmx_dev pmx_plgpio_33 = { 464struct pmx_dev spear3xx_pmx_plgpio_33 = {
465 .name = "plgpio 33", 465 .name = "plgpio 33",
466 .modes = pmx_plgpio_33_modes, 466 .modes = pmx_plgpio_33_modes,
467 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), 467 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
468 .enb_on_reset = 1, 468 .enb_on_reset = 1,
469}; 469};
470 470
471struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { 471static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
472 { 472 {
473 .ids = 0x00, 473 .ids = 0x00,
474 .mask = PMX_SSP_CS_MASK, 474 .mask = PMX_SSP_CS_MASK,
475 }, 475 },
476}; 476};
477 477
478struct pmx_dev pmx_plgpio_34_36 = { 478struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
479 .name = "plgpio 34 to 36", 479 .name = "plgpio 34 to 36",
480 .modes = pmx_plgpio_34_36_modes, 480 .modes = pmx_plgpio_34_36_modes,
481 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), 481 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
482 .enb_on_reset = 1, 482 .enb_on_reset = 1,
483}; 483};
484 484
485struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { 485static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
486 { 486 {
487 .ids = 0x00, 487 .ids = 0x00,
488 .mask = PMX_UART0_MODEM_MASK, 488 .mask = PMX_UART0_MODEM_MASK,
489 }, 489 },
490}; 490};
491 491
492struct pmx_dev pmx_plgpio_37_42 = { 492struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
493 .name = "plgpio 37 to 42", 493 .name = "plgpio 37 to 42",
494 .modes = pmx_plgpio_37_42_modes, 494 .modes = pmx_plgpio_37_42_modes,
495 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), 495 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
496 .enb_on_reset = 1, 496 .enb_on_reset = 1,
497}; 497};
498 498
499struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { 499static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
500 { 500 {
501 .ids = 0x00, 501 .ids = 0x00,
502 .mask = PMX_TIMER_1_2_MASK, 502 .mask = PMX_TIMER_1_2_MASK,
503 }, 503 },
504}; 504};
505 505
506struct pmx_dev pmx_plgpio_43_44_47_48 = { 506struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
507 .name = "plgpio 43, 44, 47 and 48", 507 .name = "plgpio 43, 44, 47 and 48",
508 .modes = pmx_plgpio_43_44_47_48_modes, 508 .modes = pmx_plgpio_43_44_47_48_modes,
509 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), 509 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
510 .enb_on_reset = 1, 510 .enb_on_reset = 1,
511}; 511};
512 512
513struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { 513static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
514 { 514 {
515 .ids = 0x00, 515 .ids = 0x00,
516 .mask = PMX_TIMER_3_4_MASK, 516 .mask = PMX_TIMER_3_4_MASK,
517 }, 517 },
518}; 518};
519 519
520struct pmx_dev pmx_plgpio_45_46_49_50 = { 520struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
521 .name = "plgpio 45, 46, 49 and 50", 521 .name = "plgpio 45, 46, 49 and 50",
522 .modes = pmx_plgpio_45_46_49_50_modes, 522 .modes = pmx_plgpio_45_46_49_50_modes,
523 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), 523 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index bddba034f862..ff4ae5ba00f1 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -4,17 +4,18 @@
4 4
5if ARCH_SPEAR6XX 5if ARCH_SPEAR6XX
6 6
7choice 7menu "SPEAr6xx Implementations"
8 prompt "SPEAr6XX Family" 8config BOARD_SPEAR600_EVB
9 default MACH_SPEAR600 9 bool "SPEAr600 Evaluation Board"
10 select MACH_SPEAR600
11 help
12 Supports ST SPEAr600 Evaluation Board
13
14endmenu
10 15
11config MACH_SPEAR600 16config MACH_SPEAR600
12 bool "SPEAr600" 17 bool "SPEAr600"
13 help 18 help
14 Supports ST SPEAr600 Machine 19 Supports ST SPEAr600 Machine
15endchoice
16
17# Adding SPEAr6XX machine specific configuration files
18source "arch/arm/mach-spear6xx/Kconfig600"
19 20
20endif #ARCH_SPEAR6XX 21endif #ARCH_SPEAR6XX
diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600
deleted file mode 100644
index 9e19f65eb78e..000000000000
--- a/arch/arm/mach-spear6xx/Kconfig600
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# SPEAr600 machine configuration file
3#
4
5if MACH_SPEAR600
6
7choice
8 prompt "SPEAr600 Boards"
9 default BOARD_SPEAR600_EVB
10
11config BOARD_SPEAR600_EVB
12 bool "SPEAr600 Evaluation Board"
13 help
14 Supports ST SPEAr600 Evaluation Board
15endchoice
16
17endif #MACH_SPEAR600
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 88b748b5be80..ac70e0d88fef 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -671,12 +671,12 @@ static struct clk_lookup spear_clk_lookups[] = {
671 { .dev_id = "gpio2", .clk = &gpio2_clk}, 671 { .dev_id = "gpio2", .clk = &gpio2_clk},
672}; 672};
673 673
674void __init clk_init(void) 674void __init spear6xx_clk_init(void)
675{ 675{
676 int i; 676 int i;
677 677
678 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) 678 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
679 clk_register(&spear_clk_lookups[i]); 679 clk_register(&spear_clk_lookups[i]);
680 680
681 recalc_root_clocks(); 681 clk_init();
682} 682}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 94cf4a648b57..183f0238c5e2 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -39,7 +39,7 @@ void __init spear6xx_map_io(void);
39void __init spear6xx_init_irq(void); 39void __init spear6xx_init_irq(void);
40void __init spear6xx_init(void); 40void __init spear6xx_init(void);
41void __init spear600_init(void); 41void __init spear600_init(void);
42void __init clk_init(void); 42void __init spear6xx_clk_init(void);
43 43
44/* Add spear600 machine device structure declarations here */ 44/* Add spear600 machine device structure declarations here */
45 45
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 981812961ac7..e0f6628c8b2c 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -148,7 +148,7 @@ void __init spear6xx_map_io(void)
148 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); 148 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
149 149
150 /* This will initialize clock framework */ 150 /* This will initialize clock framework */
151 clk_init(); 151 spear6xx_clk_init();
152} 152}
153 153
154static void __init spear6xx_timer_init(void) 154static void __init spear6xx_timer_init(void)
diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile
deleted file mode 100644
index d156f76b379f..000000000000
--- a/arch/arm/mach-stmp378x/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
2obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot
deleted file mode 100644
index 1568ad404d59..000000000000
--- a/arch/arm/mach-stmp378x/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
3initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
deleted file mode 100644
index 731a92286da2..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Low-level IRQ helper macros for Freescale STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23
24 mov \base, #0xf0000000 @ vm address of IRQ controller
25 ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
26 cmp \irqnr, #0x7f
27 moveqs \irqnr, #0 @ Zero flag set for no IRQ
28
29 .endm
30
31 .macro get_irqnr_preamble, base, tmp
32 .endm
33
34 .macro arch_ret_to_user, tmp1, tmp2
35 .endm
diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h
deleted file mode 100644
index cc59673becdd..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/irqs.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * Freescale STMP378X interrupts
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19#define IRQ_DEBUG_UART 0
20#define IRQ_COMMS_RX 1
21#define IRQ_COMMS_TX 1
22#define IRQ_SSP2_ERROR 2
23#define IRQ_VDD5V 3
24#define IRQ_HEADPHONE_SHORT 4
25#define IRQ_DAC_DMA 5
26#define IRQ_DAC_ERROR 6
27#define IRQ_ADC_DMA 7
28#define IRQ_ADC_ERROR 8
29#define IRQ_SPDIF_DMA 9
30#define IRQ_SAIF2_DMA 9
31#define IRQ_SPDIF_ERROR 10
32#define IRQ_SAIF1_IRQ 10
33#define IRQ_SAIF2_IRQ 10
34#define IRQ_USB_CTRL 11
35#define IRQ_USB_WAKEUP 12
36#define IRQ_GPMI_DMA 13
37#define IRQ_SSP1_DMA 14
38#define IRQ_SSP_ERROR 15
39#define IRQ_GPIO0 16
40#define IRQ_GPIO1 17
41#define IRQ_GPIO2 18
42#define IRQ_SAIF1_DMA 19
43#define IRQ_SSP2_DMA 20
44#define IRQ_ECC8_IRQ 21
45#define IRQ_RTC_ALARM 22
46#define IRQ_UARTAPP_TX_DMA 23
47#define IRQ_UARTAPP_INTERNAL 24
48#define IRQ_UARTAPP_RX_DMA 25
49#define IRQ_I2C_DMA 26
50#define IRQ_I2C_ERROR 27
51#define IRQ_TIMER0 28
52#define IRQ_TIMER1 29
53#define IRQ_TIMER2 30
54#define IRQ_TIMER3 31
55#define IRQ_BATT_BRNOUT 32
56#define IRQ_VDDD_BRNOUT 33
57#define IRQ_VDDIO_BRNOUT 34
58#define IRQ_VDD18_BRNOUT 35
59#define IRQ_TOUCH_DETECT 36
60#define IRQ_LRADC_CH0 37
61#define IRQ_LRADC_CH1 38
62#define IRQ_LRADC_CH2 39
63#define IRQ_LRADC_CH3 40
64#define IRQ_LRADC_CH4 41
65#define IRQ_LRADC_CH5 42
66#define IRQ_LRADC_CH6 43
67#define IRQ_LRADC_CH7 44
68#define IRQ_LCDIF_DMA 45
69#define IRQ_LCDIF_ERROR 46
70#define IRQ_DIGCTL_DEBUG_TRAP 47
71#define IRQ_RTC_1MSEC 48
72#define IRQ_DRI_DMA 49
73#define IRQ_DRI_ATTENTION 50
74#define IRQ_GPMI_ATTENTION 51
75#define IRQ_IR 52
76#define IRQ_DCP_VMI 53
77#define IRQ_DCP 54
78#define IRQ_BCH 56
79#define IRQ_PXP 57
80#define IRQ_UARTAPP2_TX_DMA 58
81#define IRQ_UARTAPP2_INTERNAL 59
82#define IRQ_UARTAPP2_RX_DMA 60
83#define IRQ_VDAC_DETECT 61
84#define IRQ_VDD5V_DROOP 64
85#define IRQ_DCDC4P2_BO 65
86
87
88#define NR_REAL_IRQS 128
89#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
90
91/* All interrupts are FIQ capable */
92#define FIQ_START IRQ_DEBUG_UART
93
94/* Hard disk IRQ is a GPMI attention IRQ */
95#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h
deleted file mode 100644
index 93f952d35969..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/pins.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Freescale STMP378X SoC pin multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_PINS_H
19#define __ASM_ARCH_PINS_H
20
21/*
22 * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
23 * interface this pin belongs to.
24 */
25
26/* Bank 0 */
27#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
28#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
29#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
30#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
31#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
32#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
33#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
34#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
35#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
36#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
37#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
38#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
39#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
40#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
41#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
42#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
43#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
44#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
45#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
46#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
47#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
48#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
49#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
50#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
51#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
52#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
53#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
54#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
55#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
56#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
57#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
58#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
59
60/* Bank 1 */
61#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
62#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
63#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
64#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
65#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
66#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
67#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
68#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
69#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
70#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
71#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
72#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
73#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
74#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
75#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
76#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
77#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
78#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
79#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
80#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
81#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
82#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
83#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
84#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
85#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
86#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
87#define PINID_PWM0 STMP3XXX_PINID(1, 26)
88#define PINID_PWM1 STMP3XXX_PINID(1, 27)
89#define PINID_PWM2 STMP3XXX_PINID(1, 28)
90#define PINID_PWM3 STMP3XXX_PINID(1, 29)
91#define PINID_PWM4 STMP3XXX_PINID(1, 30)
92
93/* Bank 2 */
94#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
95#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
96#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
97#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
98#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
99#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
100#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
101#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
102#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
103#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
104#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
105#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
106#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
107#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
108#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
109#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
110#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
111#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
112#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
113#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
114#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
115#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
116#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
117#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
118#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
119#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
120#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
121#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
122#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
123#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
124#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
125#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
126
127/* Bank 3 */
128#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
129#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
130#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
131#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
132#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
133#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
134#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
135#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
136#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
137#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
138#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
139#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
140#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
141#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
142#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
143#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
144#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
145#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
146#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
147#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
148#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
149#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
150
151#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
deleted file mode 100644
index dbcf85b6ac2a..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * stmp378x: APBH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBH
22#define _MACH_REGS_APBH
23
24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25#define REGS_APBH_PHYS 0x80004000
26#define REGS_APBH_SIZE 0x2000
27
28#define HW_APBH_CTRL0 0x0
29#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
30#define BP_APBH_CTRL0_RESET_CHANNEL 16
31#define BM_APBH_CTRL0_CLKGATE 0x40000000
32#define BM_APBH_CTRL0_SFTRST 0x80000000
33
34#define HW_APBH_CTRL1 0x10
35#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
36#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
37
38#define HW_APBH_CTRL2 0x20
39
40#define HW_APBH_DEVSEL 0x30
41
42#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
43#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
44#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
45#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
46#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
47#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
48#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
49#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
50#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
51#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
52#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
53#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
54#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
55#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
56#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
57#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
58
59#define HW_APBH_CHn_NXTCMDAR 0x50
60
61#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
62#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
63#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
64#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
65#define BM_APBH_CHn_CMD_COMMAND 0x00000003
66#define BP_APBH_CHn_CMD_COMMAND 0
67#define BM_APBH_CHn_CMD_CHAIN 0x00000004
68#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
69#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
70#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
71#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
72#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
73#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
74#define BP_APBH_CHn_CMD_CMDWORDS 12
75#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
76#define BP_APBH_CHn_CMD_XFER_COUNT 16
77
78#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
79#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
80#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
81#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
82#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
83#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
84#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
85#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
86#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
87#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
88#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
89#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
90#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
91#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
92#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
93#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
94
95#define HW_APBH_CHn_SEMA 0x80
96#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
97#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
98#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
99#define BP_APBH_CHn_SEMA_PHORE 16
100
101#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
deleted file mode 100644
index 3b934a4d27f0..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * stmp378x: APBX register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBX
22#define _MACH_REGS_APBX
23
24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25#define REGS_APBX_PHYS 0x80024000
26#define REGS_APBX_SIZE 0x2000
27
28#define HW_APBX_CTRL0 0x0
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_CTRL2 0x20
35
36#define HW_APBX_CHANNEL_CTRL 0x30
37#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
38#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
39
40#define HW_APBX_DEVSEL 0x40
41
42#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
43#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
44#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
45#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
46#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
47#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
48#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
49#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
50#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
51#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
52#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
53#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
54#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
55#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
56#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
57#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
58
59#define HW_APBX_CHn_NXTCMDAR 0x110
60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
61#define BP_APBX_CHn_CMD_COMMAND 0
62#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
63#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
64#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
65#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
66#define BM_APBX_CHn_CMD_CHAIN 0x00000004
67#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
68#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
69#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
70#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
71#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
72#define BP_APBX_CHn_CMD_CMDWORDS 12
73#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
74#define BP_APBX_CHn_CMD_XFER_COUNT 16
75
76#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
77#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
78#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
79#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
80#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
81#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
82#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
83#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
84#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
85#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
86#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
87#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
88#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
89#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
90#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
91#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
92
93#define HW_APBX_CHn_BAR 0x130
94
95#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
96#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
97#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
98#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
99#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
100#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
101#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
102#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
103#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
104#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
105#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
106#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
107#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
108#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
109#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
110#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
111
112#define HW_APBX_CHn_SEMA 0x140
113#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
114#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
115#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
116#define BP_APBX_CHn_SEMA_PHORE 16
117
118#endif
119
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
deleted file mode 100644
index 641ac6126f83..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp378x: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22#define REGS_AUDIOIN_PHYS 0x8004C000
23#define REGS_AUDIOIN_SIZE 0x2000
24
25#define HW_AUDIOIN_CTRL 0x0
26#define BM_AUDIOIN_CTRL_RUN 0x00000001
27#define BP_AUDIOIN_CTRL_RUN 0
28#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
32#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOIN_STAT 0x10
36
37#define HW_AUDIOIN_ADCSRR 0x20
38
39#define HW_AUDIOIN_ADCVOLUME 0x30
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
42#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
43#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
44
45#define HW_AUDIOIN_ADCDEBUG 0x40
46
47#define HW_AUDIOIN_ADCVOL 0x50
48#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
49#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
50#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
51#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
52#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
53#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
54#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
55#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
56#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
57
58#define HW_AUDIOIN_MICLINE 0x60
59
60#define HW_AUDIOIN_ANACLKCTRL 0x70
61#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
62
63#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
deleted file mode 100644
index f533e23694a0..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * stmp378x: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22#define REGS_AUDIOOUT_PHYS 0x80048000
23#define REGS_AUDIOOUT_SIZE 0x2000
24
25#define HW_AUDIOOUT_CTRL 0x0
26#define BM_AUDIOOUT_CTRL_RUN 0x00000001
27#define BP_AUDIOOUT_CTRL_RUN 0
28#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
32#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOOUT_STAT 0x10
36
37#define HW_AUDIOOUT_DACSRR 0x20
38#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
39#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
40#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
41#define BP_AUDIOOUT_DACSRR_SRC_INT 16
42#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
43#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
44#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
45#define BP_AUDIOOUT_DACSRR_BASEMULT 28
46
47#define HW_AUDIOOUT_DACVOLUME 0x30
48#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
49#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
50#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
51
52#define HW_AUDIOOUT_DACDEBUG 0x40
53
54#define HW_AUDIOOUT_HPVOL 0x50
55#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
56#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
57
58#define HW_AUDIOOUT_PWRDN 0x70
59#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
60#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
61#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
62#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
63#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
64#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
65#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
66
67#define HW_AUDIOOUT_REFCTRL 0x80
68#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
69#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
70#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
71#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
72#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
73#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
74#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
75#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
76#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
77#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
78#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
79#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
80#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
81
82#define HW_AUDIOOUT_ANACTRL 0x90
83#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
84#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
85
86#define HW_AUDIOOUT_TEST 0xA0
87#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
88#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
89
90#define HW_AUDIOOUT_BISTCTRL 0xB0
91
92#define HW_AUDIOOUT_BISTSTAT0 0xC0
93
94#define HW_AUDIOOUT_BISTSTAT1 0xD0
95
96#define HW_AUDIOOUT_ANACLKCTRL 0xE0
97#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
98
99#define HW_AUDIOOUT_DATA 0xF0
100
101#define HW_AUDIOOUT_SPEAKERCTRL 0x100
102#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
103
104#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
deleted file mode 100644
index 532d24650717..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * stmp378x: BCH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
22#define REGS_BCH_PHYS 0x8000A000
23#define REGS_BCH_SIZE 0x2000
24
25#define HW_BCH_CTRL 0x0
26#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_BCH_CTRL_COMPLETE_IRQ 0
28#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
29
30#define HW_BCH_STATUS0 0x10
31#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
32#define BM_BCH_STATUS0_CORRECTED 0x00000008
33#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
34#define BP_BCH_STATUS0_STATUS_BLK0 8
35#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
36#define BP_BCH_STATUS0_COMPLETED_CE 16
37
38#define HW_BCH_LAYOUTSELECT 0x70
39
40#define HW_BCH_FLASH0LAYOUT0 0x80
41#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
42#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
43#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
44#define BP_BCH_FLASH0LAYOUT0_ECC0 12
45#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
46#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
47#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
48#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
49#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
50#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
51#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
52#define BP_BCH_FLASH0LAYOUT1_ECCN 12
53#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
54#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
55
56#define HW_BCH_BLOCKNAME 0x150
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
deleted file mode 100644
index 7c546afd57a3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * stmp378x: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
23
24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
25#define REGS_CLKCTRL_PHYS 0x80040000
26#define REGS_CLKCTRL_SIZE 0x2000
27
28#define HW_CLKCTRL_PLLCTRL0 0x0
29#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
30
31#define HW_CLKCTRL_CPU 0x20
32#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
33#define BP_CLKCTRL_CPU_DIV_CPU 0
34
35#define HW_CLKCTRL_HBUS 0x30
36#define BM_CLKCTRL_HBUS_DIV 0x0000001F
37#define BP_CLKCTRL_HBUS_DIV 0
38#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
39
40#define HW_CLKCTRL_XBUS 0x40
41
42#define HW_CLKCTRL_XTAL 0x50
43#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
44
45#define HW_CLKCTRL_PIX 0x60
46#define BM_CLKCTRL_PIX_DIV 0x00000FFF
47#define BP_CLKCTRL_PIX_DIV 0
48#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
49
50#define HW_CLKCTRL_SSP 0x70
51
52#define HW_CLKCTRL_GPMI 0x80
53
54#define HW_CLKCTRL_SPDIF 0x90
55
56#define HW_CLKCTRL_EMI 0xA0
57#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
58#define BP_CLKCTRL_EMI_DIV_EMI 0
59#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
60#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
61#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
62#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
63
64#define HW_CLKCTRL_IR 0xB0
65
66#define HW_CLKCTRL_SAIF 0xC0
67
68#define HW_CLKCTRL_TV 0xD0
69
70#define HW_CLKCTRL_ETM 0xE0
71
72#define HW_CLKCTRL_FRAC 0xF0
73#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
74#define BP_CLKCTRL_FRAC_EMIFRAC 8
75#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
76#define BP_CLKCTRL_FRAC_PIXFRAC 16
77#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
78
79#define HW_CLKCTRL_FRAC1 0x100
80
81#define HW_CLKCTRL_CLKSEQ 0x110
82#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
83
84#define HW_CLKCTRL_RESET 0x120
85#define BM_CLKCTRL_RESET_DIG 0x00000001
86#define BP_CLKCTRL_RESET_DIG 0
87
88#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
deleted file mode 100644
index fdedd00c0e28..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * stmp378x: DCP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
22#define REGS_DCP_PHYS 0x80028000
23#define REGS_DCP_SIZE 0x2000
24
25#define HW_DCP_CTRL 0x0
26#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
27#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
28#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
29#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
30#define BM_DCP_CTRL_CLKGATE 0x40000000
31#define BM_DCP_CTRL_SFTRST 0x80000000
32
33#define HW_DCP_STAT 0x10
34#define BM_DCP_STAT_IRQ 0x0000000F
35#define BP_DCP_STAT_IRQ 0
36
37#define HW_DCP_CHANNELCTRL 0x20
38#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
39#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
40
41#define HW_DCP_CONTEXT 0x50
42#define BM_DCP_PACKET1_INTERRUPT 0x00000001
43#define BP_DCP_PACKET1_INTERRUPT 0
44#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
45#define BM_DCP_PACKET1_CHAIN 0x00000004
46#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
47#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
48#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
49#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
50#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
51#define BM_DCP_PACKET1_OTP_KEY 0x00000400
52#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
53#define BM_DCP_PACKET1_HASH_INIT 0x00001000
54#define BM_DCP_PACKET1_HASH_TERM 0x00002000
55#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
56#define BP_DCP_PACKET2_CIPHER_SELECT 0
57#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
58#define BP_DCP_PACKET2_CIPHER_MODE 4
59#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
60#define BP_DCP_PACKET2_KEY_SELECT 8
61#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
62#define BP_DCP_PACKET2_HASH_SELECT 16
63#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
64#define BP_DCP_PACKET2_CIPHER_CFG 24
65
66#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
67#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
68#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
69#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
70
71#define HW_DCP_CHnCMDPTR 0x100
72
73#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
74#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
75#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
76#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
77
78#define HW_DCP_CHnSEMA 0x110
79#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
80#define BP_DCP_CHnSEMA_INCREMENT 0
81
82#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
83#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
84#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
85#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
86
87#define HW_DCP_CHnSTAT 0x120
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
deleted file mode 100644
index 5293005523b3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * stmp378x: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22#define REGS_DIGCTL_PHYS 0x8001C000
23#define REGS_DIGCTL_SIZE 0x2000
24
25#define HW_DIGCTL_CTRL 0x0
26#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
27
28#define HW_DIGCTL_ARMCACHE 0x2B0
29#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
30#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
31#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
32#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
33#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
34#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
35#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
36#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
37#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
38#define BP_DIGCTL_ARMCACHE_VALID_SS 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
deleted file mode 100644
index 02851431677c..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * stmp378x: DRAM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
22#define REGS_DRAM_PHYS 0x800E0000
23#define REGS_DRAM_SIZE 0x2000
24
25#define HW_DRAM_CTL06 0x18
26
27#define HW_DRAM_CTL08 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
deleted file mode 100644
index da25f7e397e5..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * stmp378x: DRI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
22#define REGS_DRI_PHYS 0x80074000
23#define REGS_DRI_SIZE 0x2000
24
25#define HW_DRI_CTRL 0x0
26#define BM_DRI_CTRL_RUN 0x00000001
27#define BP_DRI_CTRL_RUN 0
28#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
29#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
30#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
31#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
32#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
33#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
34#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
35#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
36#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
37#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
38#define BM_DRI_CTRL_CLKGATE 0x40000000
39#define BM_DRI_CTRL_SFTRST 0x80000000
40
41#define HW_DRI_TIMING 0x10
42#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
43#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
44#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
45#define BP_DRI_TIMING_PILOT_REP_RATE 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
deleted file mode 100644
index cc353bec331b..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * stmp378x: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22#define REGS_ECC8_PHYS 0x80008000
23#define REGS_ECC8_SIZE 0x2000
24
25#define HW_ECC8_CTRL 0x0
26#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_ECC8_CTRL_COMPLETE_IRQ 0
28#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
29#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
30
31#define HW_ECC8_STATUS0 0x10
32#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
33#define BM_ECC8_STATUS0_CORRECTED 0x00000008
34#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
35#define BP_ECC8_STATUS0_STATUS_AUX 8
36#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
37#define BP_ECC8_STATUS0_COMPLETED_CE 16
38
39#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
deleted file mode 100644
index 98773fc33d7b..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * stmp378x: EMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
22#define REGS_EMI_PHYS 0x80020000
23#define REGS_EMI_SIZE 0x2000
24
25#define HW_EMI_STAT 0x10
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
deleted file mode 100644
index 2cc8bbe91687..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * stmp378x: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
33#define BP_GPMI_CTRL0_ADDRESS 17
34#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
35#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
36#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
37#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
38#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
39#define BP_GPMI_CTRL0_COMMAND_MODE 24
40#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
41#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
42#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
43#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
44#define BM_GPMI_CTRL0_RUN 0x20000000
45#define BM_GPMI_CTRL0_CLKGATE 0x40000000
46#define BM_GPMI_CTRL0_SFTRST 0x80000000
47#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
48#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
49#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
50#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
51#define BP_GPMI_ECCCTRL_ECC_CMD 13
52#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
53#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
54#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
55#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
56
57#define HW_GPMI_CTRL1 0x60
58#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
59#define BP_GPMI_CTRL1_GPMI_MODE 0
60#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
61#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
62#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
63#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
64#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
65#define BP_GPMI_CTRL1_RDN_DELAY 12
66#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
67
68#define HW_GPMI_TIMING0 0x70
69#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
70#define BP_GPMI_TIMING0_DATA_SETUP 0
71#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
72#define BP_GPMI_TIMING0_DATA_HOLD 8
73#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
74#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
75
76#define HW_GPMI_TIMING1 0x80
77#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
78#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
deleted file mode 100644
index 13a234c99433..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * stmp378x: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
deleted file mode 100644
index f996e80f40e7..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * stmp378x: ICOLL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
25#define REGS_ICOLL_PHYS 0x80000000
26#define REGS_ICOLL_SIZE 0x2000
27
28#define HW_ICOLL_VECTOR 0x0
29
30#define HW_ICOLL_LEVELACK 0x10
31#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
32#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
33
34#define HW_ICOLL_CTRL 0x20
35#define BM_ICOLL_CTRL_CLKGATE 0x40000000
36#define BM_ICOLL_CTRL_SFTRST 0x80000000
37
38#define HW_ICOLL_STAT 0x70
39
40#define HW_ICOLL_INTERRUPTn 0x120
41
42#define HW_ICOLL_INTERRUPTn 0x120
43#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
44
45#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
deleted file mode 100644
index a5b4ef10fab8..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * stmp378x: IR register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
22#define REGS_IR_PHYS 0x80078000
23#define REGS_IR_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
deleted file mode 100644
index 9cdbef4badc3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * stmp378x: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_RUN 0x00000001
27#define BP_LCDIF_CTRL_RUN 0
28#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
29#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
30#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
31#define BP_LCDIF_CTRL_WORD_LENGTH 8
32#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
33#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
34#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
35#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
36#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
37#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
38#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
39#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
40#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
41#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
42#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
43#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
44#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
45#define BM_LCDIF_CTRL_CLKGATE 0x40000000
46#define BM_LCDIF_CTRL_SFTRST 0x80000000
47
48#define HW_LCDIF_CTRL1 0x10
49#define BM_LCDIF_CTRL1_RESET 0x00000001
50#define BP_LCDIF_CTRL1_RESET 0
51#define BM_LCDIF_CTRL1_MODE86 0x00000002
52#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
53#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
54#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
55#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
56#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
57#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
58#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
59#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
60#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
61#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
62
63#define HW_LCDIF_TRANSFER_COUNT 0x20
64#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
65#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
66#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
67#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
68
69#define HW_LCDIF_CUR_BUF 0x30
70
71#define HW_LCDIF_NEXT_BUF 0x40
72
73#define HW_LCDIF_TIMING 0x60
74
75#define HW_LCDIF_VDCTRL0 0x70
76#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
77#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
78#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
79#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
80#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
81#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
82#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
83#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
84#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
85#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
86
87#define HW_LCDIF_VDCTRL1 0x80
88#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
89#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
90
91#define HW_LCDIF_VDCTRL2 0x90
92#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
93#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
94#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
95#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
96
97#define HW_LCDIF_VDCTRL3 0xA0
98#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
99#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
100#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
101#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
102
103#define HW_LCDIF_VDCTRL4 0xB0
104#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
105#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
106#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
107
108#define HW_LCDIF_DVICTRL0 0xC0
109#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
110#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
111#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
112#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
113#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
114#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
115
116#define HW_LCDIF_DVICTRL1 0xD0
117#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
118#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
119#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
120#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
121#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
122#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
123
124#define HW_LCDIF_DVICTRL2 0xE0
125#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
126#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
127#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
128#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
129#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
130#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
131
132#define HW_LCDIF_DVICTRL3 0xF0
133#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
134#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
135#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
136#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
137
138#define HW_LCDIF_DVICTRL4 0x100
139#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
140#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
141#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
142#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
143#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
144#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
145#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
146#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
147
148#define HW_LCDIF_CSC_COEFF0 0x110
149#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
150#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
151#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
152#define BP_LCDIF_CSC_COEFF0_C0 16
153
154#define HW_LCDIF_CSC_COEFF1 0x120
155#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
156#define BP_LCDIF_CSC_COEFF1_C1 0
157#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
158#define BP_LCDIF_CSC_COEFF1_C2 16
159
160#define HW_LCDIF_CSC_COEFF2 0x130
161#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
162#define BP_LCDIF_CSC_COEFF2_C3 0
163#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
164#define BP_LCDIF_CSC_COEFF2_C4 16
165
166#define HW_LCDIF_CSC_COEFF3 0x140
167#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
168#define BP_LCDIF_CSC_COEFF3_C5 0
169#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
170#define BP_LCDIF_CSC_COEFF3_C6 16
171
172#define HW_LCDIF_CSC_COEFF4 0x150
173#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
174#define BP_LCDIF_CSC_COEFF4_C7 0
175#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
176#define BP_LCDIF_CSC_COEFF4_C8 16
177
178#define HW_LCDIF_CSC_OFFSET 0x160
179#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
180#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
181#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
182#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
183
184#define HW_LCDIF_CSC_LIMIT 0x170
185#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
186#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
187#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
188#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
189#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
190#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
191#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
192#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
193
194#define HW_LCDIF_STAT 0x1D0
195#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
deleted file mode 100644
index cb8cb06f8277..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * stmp378x: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22#define REGS_LRADC_PHYS 0x80050000
23#define REGS_LRADC_SIZE 0x2000
24
25#define HW_LRADC_CTRL0 0x0
26#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
27#define BP_LRADC_CTRL0_SCHEDULE 0
28#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
29#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
30#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
31#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
32#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
33#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
34#define BM_LRADC_CTRL0_CLKGATE 0x40000000
35#define BM_LRADC_CTRL0_SFTRST 0x80000000
36
37#define HW_LRADC_CTRL1 0x10
38#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
39#define BP_LRADC_CTRL1_LRADC0_IRQ 0
40#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
41#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
42#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
43#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
44#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
45#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
46
47#define HW_LRADC_CTRL2 0x20
48#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
49#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
50#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
51#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
52#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
53#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
54
55#define HW_LRADC_CTRL3 0x30
56#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
57#define BP_LRADC_CTRL3_CYCLE_TIME 8
58
59#define HW_LRADC_STATUS 0x40
60#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
61#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
62
63#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
64#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
65#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
66#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
67#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
68#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
69#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
70#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
71
72#define HW_LRADC_CHn 0x50
73#define BM_LRADC_CHn_VALUE 0x0003FFFF
74#define BP_LRADC_CHn_VALUE 0
75#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
76#define BP_LRADC_CHn_NUM_SAMPLES 24
77#define BM_LRADC_CHn_ACCUMULATE 0x20000000
78
79#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
80#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
81#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
82#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
83
84#define HW_LRADC_DELAYn 0xD0
85#define BM_LRADC_DELAYn_DELAY 0x000007FF
86#define BP_LRADC_DELAYn_DELAY 0
87#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
88#define BP_LRADC_DELAYn_LOOP_COUNT 11
89#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
90#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
91#define BM_LRADC_DELAYn_KICK 0x00100000
92#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
93#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
94
95#define HW_LRADC_CTRL4 0x140
96#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
97#define BP_LRADC_CTRL4_LRADC6SELECT 24
98#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
99#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
deleted file mode 100644
index f0af64d9937e..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * stmp378x: OCOTP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
22#define REGS_OCOTP_PHYS 0x8002C000
23#define REGS_OCOTP_SIZE 0x2000
24
25#define HW_OCOTP_CTRL 0x0
26#define BM_OCOTP_CTRL_BUSY 0x00000100
27#define BM_OCOTP_CTRL_ERROR 0x00000200
28#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
29#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
30#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
31#define BP_OCOTP_CTRL_WR_UNLOCK 16
32
33#define HW_OCOTP_DATA 0x10
34
35#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
36#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
37#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
38#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
39
40#define HW_OCOTP_CUSTn 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
deleted file mode 100644
index 50d90ea1b136..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * stmp378x: PINCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
23
24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
25#define REGS_PINCTRL_PHYS 0x80018000
26#define REGS_PINCTRL_SIZE 0x2000
27
28#define HW_PINCTRL_MUXSEL0 0x100
29#define HW_PINCTRL_MUXSEL1 0x110
30#define HW_PINCTRL_MUXSEL2 0x120
31#define HW_PINCTRL_MUXSEL3 0x130
32#define HW_PINCTRL_MUXSEL4 0x140
33#define HW_PINCTRL_MUXSEL5 0x150
34#define HW_PINCTRL_MUXSEL6 0x160
35#define HW_PINCTRL_MUXSEL7 0x170
36
37#define HW_PINCTRL_DRIVE0 0x200
38#define HW_PINCTRL_DRIVE1 0x210
39#define HW_PINCTRL_DRIVE2 0x220
40#define HW_PINCTRL_DRIVE3 0x230
41#define HW_PINCTRL_DRIVE4 0x240
42#define HW_PINCTRL_DRIVE5 0x250
43#define HW_PINCTRL_DRIVE6 0x260
44#define HW_PINCTRL_DRIVE7 0x270
45#define HW_PINCTRL_DRIVE8 0x280
46#define HW_PINCTRL_DRIVE9 0x290
47#define HW_PINCTRL_DRIVE10 0x2A0
48#define HW_PINCTRL_DRIVE11 0x2B0
49#define HW_PINCTRL_DRIVE12 0x2C0
50#define HW_PINCTRL_DRIVE13 0x2D0
51#define HW_PINCTRL_DRIVE14 0x2E0
52
53#define HW_PINCTRL_PULL0 0x400
54#define HW_PINCTRL_PULL1 0x410
55#define HW_PINCTRL_PULL2 0x420
56#define HW_PINCTRL_PULL3 0x430
57
58#define HW_PINCTRL_DOUT0 0x500
59#define HW_PINCTRL_DOUT1 0x510
60#define HW_PINCTRL_DOUT2 0x520
61
62#define HW_PINCTRL_DIN0 0x600
63#define HW_PINCTRL_DIN1 0x610
64#define HW_PINCTRL_DIN2 0x620
65
66#define HW_PINCTRL_DOE0 0x700
67#define HW_PINCTRL_DOE1 0x710
68#define HW_PINCTRL_DOE2 0x720
69
70#define HW_PINCTRL_PIN2IRQ0 0x800
71#define HW_PINCTRL_PIN2IRQ1 0x810
72#define HW_PINCTRL_PIN2IRQ2 0x820
73
74#define HW_PINCTRL_IRQEN0 0x900
75#define HW_PINCTRL_IRQEN1 0x910
76#define HW_PINCTRL_IRQEN2 0x920
77
78#define HW_PINCTRL_IRQLEVEL0 0xA00
79#define HW_PINCTRL_IRQLEVEL1 0xA10
80#define HW_PINCTRL_IRQLEVEL2 0xA20
81
82#define HW_PINCTRL_IRQPOL0 0xB00
83#define HW_PINCTRL_IRQPOL1 0xB10
84#define HW_PINCTRL_IRQPOL2 0xB20
85
86#define HW_PINCTRL_IRQSTAT0 0xC00
87#define HW_PINCTRL_IRQSTAT1 0xC10
88#define HW_PINCTRL_IRQSTAT2 0xC20
89
90#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h
deleted file mode 100644
index e454c830f076..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-power.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp378x: POWER register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
23
24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
25#define REGS_POWER_PHYS 0x80044000
26#define REGS_POWER_SIZE 0x2000
27
28#define HW_POWER_CTRL 0x0
29#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
30#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
31#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
32#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
33#define BM_POWER_CTRL_CLKGATE 0x40000000
34
35#define HW_POWER_5VCTRL 0x10
36#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
37
38#define HW_POWER_MINPWR 0x20
39
40#define HW_POWER_CHARGE 0x30
41
42#define HW_POWER_VDDDCTRL 0x40
43
44#define HW_POWER_VDDACTRL 0x50
45
46#define HW_POWER_VDDIOCTRL 0x60
47#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
48#define BP_POWER_VDDIOCTRL_TRG 0
49
50#define HW_POWER_STS 0xC0
51#define BM_POWER_STS_VBUSVALID 0x00000002
52#define BM_POWER_STS_BVALID 0x00000004
53#define BM_POWER_STS_AVALID 0x00000008
54#define BM_POWER_STS_DC_OK 0x00000200
55
56#define HW_POWER_RESET 0x100
57
58#define HW_POWER_DEBUG 0x110
59#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
60#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
61#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
62
63#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
deleted file mode 100644
index 0d0f9e56ec77..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * stmp378x: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22#define REGS_PWM_PHYS 0x80064000
23#define REGS_PWM_SIZE 0x2000
24
25#define HW_PWM_CTRL 0x0
26#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
27#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
28
29#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
30#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
31#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
32#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
33
34#define HW_PWM_ACTIVEn 0x10
35#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
36#define BP_PWM_ACTIVEn_ACTIVE 0
37#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
38#define BP_PWM_ACTIVEn_INACTIVE 16
39
40#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
41#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
42#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
43#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
44
45#define HW_PWM_PERIODn 0x20
46#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
47#define BP_PWM_PERIODn_PERIOD 0
48#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
49#define BP_PWM_PERIODn_ACTIVE_STATE 16
50#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
51#define BP_PWM_PERIODn_INACTIVE_STATE 18
52#define BM_PWM_PERIODn_CDIV 0x00700000
53#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
deleted file mode 100644
index 54d297896de8..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 * stmp378x: PXP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
22#define REGS_PXP_PHYS 0x8002A000
23#define REGS_PXP_SIZE 0x2000
24
25#define HW_PXP_CTRL 0x0
26#define BM_PXP_CTRL_ENABLE 0x00000001
27#define BP_PXP_CTRL_ENABLE 0
28#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
29#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
30#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
31#define BM_PXP_CTRL_ROTATE 0x00000300
32#define BP_PXP_CTRL_ROTATE 8
33#define BM_PXP_CTRL_HFLIP 0x00000400
34#define BM_PXP_CTRL_VFLIP 0x00000800
35#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
36#define BP_PXP_CTRL_S0_FORMAT 12
37#define BM_PXP_CTRL_SCALE 0x00040000
38#define BM_PXP_CTRL_CROP 0x00080000
39
40#define HW_PXP_STAT 0x10
41#define BM_PXP_STAT_IRQ 0x00000001
42#define BP_PXP_STAT_IRQ 0
43
44#define HW_PXP_RGBBUF 0x20
45
46#define HW_PXP_RGBSIZE 0x40
47#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
48#define BP_PXP_RGBSIZE_HEIGHT 0
49#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
50#define BP_PXP_RGBSIZE_WIDTH 12
51
52#define HW_PXP_S0BUF 0x50
53
54#define HW_PXP_S0UBUF 0x60
55
56#define HW_PXP_S0VBUF 0x70
57
58#define HW_PXP_S0PARAM 0x80
59#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
60#define BP_PXP_S0PARAM_HEIGHT 0
61#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
62#define BP_PXP_S0PARAM_WIDTH 8
63#define BM_PXP_S0PARAM_YBASE 0x00FF0000
64#define BP_PXP_S0PARAM_YBASE 16
65#define BM_PXP_S0PARAM_XBASE 0xFF000000
66#define BP_PXP_S0PARAM_XBASE 24
67
68#define HW_PXP_S0BACKGROUND 0x90
69
70#define HW_PXP_S0CROP 0xA0
71#define BM_PXP_S0CROP_HEIGHT 0x000000FF
72#define BP_PXP_S0CROP_HEIGHT 0
73#define BM_PXP_S0CROP_WIDTH 0x0000FF00
74#define BP_PXP_S0CROP_WIDTH 8
75#define BM_PXP_S0CROP_YBASE 0x00FF0000
76#define BP_PXP_S0CROP_YBASE 16
77#define BM_PXP_S0CROP_XBASE 0xFF000000
78#define BP_PXP_S0CROP_XBASE 24
79
80#define HW_PXP_S0SCALE 0xB0
81#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
82#define BP_PXP_S0SCALE_XSCALE 0
83#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
84#define BP_PXP_S0SCALE_YSCALE 16
85
86#define HW_PXP_CSCCOEFF0 0xD0
87
88#define HW_PXP_CSCCOEFF1 0xE0
89
90#define HW_PXP_CSCCOEFF2 0xF0
91
92#define HW_PXP_S0COLORKEYLOW 0x180
93
94#define HW_PXP_S0COLORKEYHIGH 0x190
95
96#define HW_PXP_OL0 (0x200 + 0 * 0x40)
97#define HW_PXP_OL1 (0x200 + 1 * 0x40)
98#define HW_PXP_OL2 (0x200 + 2 * 0x40)
99#define HW_PXP_OL3 (0x200 + 3 * 0x40)
100#define HW_PXP_OL4 (0x200 + 4 * 0x40)
101#define HW_PXP_OL5 (0x200 + 5 * 0x40)
102#define HW_PXP_OL6 (0x200 + 6 * 0x40)
103#define HW_PXP_OL7 (0x200 + 7 * 0x40)
104
105#define HW_PXP_OLn 0x200
106
107#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
108#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
109#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
110#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
111#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
112#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
113#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
114#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
115
116#define HW_PXP_OLnSIZE 0x210
117#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
118#define BP_PXP_OLnSIZE_HEIGHT 0
119#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
120#define BP_PXP_OLnSIZE_WIDTH 8
121
122#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
123#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
124#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
125#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
126#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
127#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
128#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
129#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
130
131#define HW_PXP_OLnPARAM 0x220
132#define BM_PXP_OLnPARAM_ENABLE 0x00000001
133#define BP_PXP_OLnPARAM_ENABLE 0
134#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
135#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
136#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
137#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
138#define BP_PXP_OLnPARAM_FORMAT 4
139#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
140#define BP_PXP_OLnPARAM_ALPHA 8
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
deleted file mode 100644
index b8dbd6742d98..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * stmp378x: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
57#define BP_RTC_PERSISTENT1_GENERAL 0
58
59#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
deleted file mode 100644
index 6df41762c2a3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * stmp378x: SAIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SAIF_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
deleted file mode 100644
index 801539848c28..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * stmp378x: SPDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
22#define REGS_SPDIF_PHYS 0x80054000
23#define REGS_SPDIF_SIZE 0x2000
24
25#define HW_SPDIF_CTRL 0x0
26#define BM_SPDIF_CTRL_RUN 0x00000001
27#define BP_SPDIF_CTRL_RUN 0
28#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
32#define BM_SPDIF_CTRL_CLKGATE 0x40000000
33#define BM_SPDIF_CTRL_SFTRST 0x80000000
34
35#define HW_SPDIF_STAT 0x10
36
37#define HW_SPDIF_FRAMECTRL 0x20
38
39#define HW_SPDIF_SRR 0x30
40#define BM_SPDIF_SRR_RATE 0x000FFFFF
41#define BP_SPDIF_SRR_RATE 0
42#define BM_SPDIF_SRR_BASEMULT 0x70000000
43#define BP_SPDIF_SRR_BASEMULT 28
44
45#define HW_SPDIF_DEBUG 0x40
46
47#define HW_SPDIF_DATA 0x50
48
49#define HW_SPDIF_VERSION 0x60
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
deleted file mode 100644
index 28aacf0f58ed..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * stmp378x: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
24#define REGS_SSP2_PHYS 0x80034000
25#define REGS_SSP_SIZE 0x2000
26
27#define HW_SSP_CTRL0 0x0
28#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_SSP_CTRL0_XFER_COUNT 0
30#define BM_SSP_CTRL0_ENABLE 0x00010000
31#define BM_SSP_CTRL0_GET_RESP 0x00020000
32#define BM_SSP_CTRL0_LONG_RESP 0x00080000
33#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
34#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
35#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
36#define BP_SSP_CTRL0_BUS_WIDTH 22
37#define BM_SSP_CTRL0_DATA_XFER 0x01000000
38#define BM_SSP_CTRL0_READ 0x02000000
39#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
40#define BM_SSP_CTRL0_LOCK_CS 0x08000000
41#define BM_SSP_CTRL0_RUN 0x20000000
42#define BM_SSP_CTRL0_CLKGATE 0x40000000
43#define BM_SSP_CTRL0_SFTRST 0x80000000
44
45#define HW_SSP_CMD0 0x10
46#define BM_SSP_CMD0_CMD 0x000000FF
47#define BP_SSP_CMD0_CMD 0
48#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
49#define BP_SSP_CMD0_BLOCK_COUNT 8
50#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
51#define BP_SSP_CMD0_BLOCK_SIZE 16
52#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
53#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
54#define BP_SSP_CMD1_CMD_ARG 0
55
56#define HW_SSP_TIMING 0x50
57#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
58#define BP_SSP_TIMING_CLOCK_RATE 0
59#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
60#define BP_SSP_TIMING_CLOCK_DIVIDE 8
61#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
62#define BP_SSP_TIMING_TIMEOUT 16
63
64#define HW_SSP_CTRL1 0x60
65#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
66#define BP_SSP_CTRL1_SSP_MODE 0
67#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
68#define BP_SSP_CTRL1_WORD_LENGTH 4
69#define BM_SSP_CTRL1_POLARITY 0x00000200
70#define BM_SSP_CTRL1_PHASE 0x00000400
71#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
72#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
74#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
75#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
77#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
79#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
81#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
83#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
84#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
85
86#define HW_SSP_DATA 0x70
87
88#define HW_SSP_SDRESP0 0x80
89
90#define HW_SSP_SDRESP1 0x90
91
92#define HW_SSP_SDRESP2 0xA0
93
94#define HW_SSP_SDRESP3 0xB0
95
96#define HW_SSP_STATUS 0xC0
97#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
98#define BM_SSP_STATUS_TIMEOUT 0x00001000
99#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
100#define BM_SSP_STATUS_RESP_ERR 0x00008000
101#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
102#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
deleted file mode 100644
index 08343a8b5566..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * stmp378x: SYDMA register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
22#define REGS_SYDMA_PHYS 0x80026000
23#define REGS_SYDMA_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
deleted file mode 100644
index b5527957c67f..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * stmp378x: TIMROT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_TIMROT
22#define _MACH_REGS_TIMROT
23
24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25#define REGS_TIMROT_PHYS 0x80068000
26#define REGS_TIMROT_SIZE 0x2000
27
28#define HW_TIMROT_ROTCTRL 0x0
29#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
30#define BP_TIMROT_ROTCTRL_SELECT_A 0
31#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
32#define BP_TIMROT_ROTCTRL_SELECT_B 4
33#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
34#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
35#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
36#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
37#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
38#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
39#define BP_TIMROT_ROTCTRL_DIVIDER 16
40#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
41#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
42#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
43
44#define HW_TIMROT_ROTCOUNT 0x10
45#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
46#define BP_TIMROT_ROTCOUNT_UPDOWN 0
47
48#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
49#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
50#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
51
52#define HW_TIMROT_TIMCTRLn 0x20
53#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
54#define BP_TIMROT_TIMCTRLn_SELECT 0
55#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
56#define BP_TIMROT_TIMCTRLn_PRESCALE 4
57#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
58#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
59#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
60#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
61
62#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
63#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
64#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
65
66#define HW_TIMROT_TIMCOUNTn 0x30
67
68#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
deleted file mode 100644
index 7f895cb34350..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * stmp378x: TVENC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
22#define REGS_TVENC_PHYS 0x80038000
23#define REGS_TVENC_SIZE 0x2000
24
25#define HW_TVENC_CTRL 0x0
26#define BM_TVENC_CTRL_CLKGATE 0x40000000
27#define BM_TVENC_CTRL_SFTRST 0x80000000
28
29#define HW_TVENC_CONFIG 0x10
30#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
31#define BP_TVENC_CONFIG_ENCD_MODE 0
32#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
33#define BP_TVENC_CONFIG_SYNC_MODE 4
34#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
35#define BM_TVENC_CONFIG_CGAIN 0x0000C000
36#define BP_TVENC_CONFIG_CGAIN 14
37#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
38#define BP_TVENC_CONFIG_YGAIN_SEL 16
39#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
40
41#define HW_TVENC_SYNCOFFSET 0x30
42
43#define HW_TVENC_COLORSUB0 0xC0
44
45#define HW_TVENC_COLORBURST 0x140
46#define BM_TVENC_COLORBURST_PBA 0x00FF0000
47#define BP_TVENC_COLORBURST_PBA 16
48#define BM_TVENC_COLORBURST_NBA 0xFF000000
49#define BP_TVENC_COLORBURST_NBA 24
50
51#define HW_TVENC_MACROVISION0 0x150
52
53#define HW_TVENC_MACROVISION1 0x160
54
55#define HW_TVENC_MACROVISION2 0x170
56
57#define HW_TVENC_MACROVISION3 0x180
58
59#define HW_TVENC_MACROVISION4 0x190
60
61#define HW_TVENC_DACCTRL 0x1A0
62#define BM_TVENC_DACCTRL_RVAL 0x00000070
63#define BP_TVENC_DACCTRL_RVAL 4
64#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
65#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
66#define BM_TVENC_DACCTRL_GAINUP 0x00040000
67#define BM_TVENC_DACCTRL_GAINDN 0x00080000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
deleted file mode 100644
index a251e68bb3a1..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * stmp378x: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000)
24#define REGS_UARTAPP2_PHYS 0x8006E000
25#define REGS_UARTAPP_SIZE 0x2000
26
27#define HW_UARTAPP_CTRL0 0x0
28#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_UARTAPP_CTRL0_XFER_COUNT 0
30#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
31#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
32#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
33#define BM_UARTAPP_CTRL0_RUN 0x20000000
34#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
35#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
36#define BP_UARTAPP_CTRL1_XFER_COUNT 0
37#define BM_UARTAPP_CTRL1_RUN 0x10000000
38
39#define HW_UARTAPP_CTRL2 0x20
40#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
41#define BP_UARTAPP_CTRL2_UARTEN 0
42#define BM_UARTAPP_CTRL2_TXE 0x00000100
43#define BM_UARTAPP_CTRL2_RXE 0x00000200
44#define BM_UARTAPP_CTRL2_RTS 0x00000800
45#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
46#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
47#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
48#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
49#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
50
51#define HW_UARTAPP_LINECTRL 0x30
52#define BM_UARTAPP_LINECTRL_BRK 0x00000001
53#define BP_UARTAPP_LINECTRL_BRK 0
54#define BM_UARTAPP_LINECTRL_PEN 0x00000002
55#define BM_UARTAPP_LINECTRL_EPS 0x00000004
56#define BM_UARTAPP_LINECTRL_STP2 0x00000008
57#define BM_UARTAPP_LINECTRL_FEN 0x00000010
58#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
59#define BP_UARTAPP_LINECTRL_WLEN 5
60#define BM_UARTAPP_LINECTRL_SPS 0x00000080
61#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
62#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
63#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
64#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
65
66#define HW_UARTAPP_INTR 0x50
67#define BM_UARTAPP_INTR_CTSMIS 0x00000002
68#define BM_UARTAPP_INTR_RTIS 0x00000040
69#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
70#define BM_UARTAPP_INTR_RXIEN 0x00100000
71#define BM_UARTAPP_INTR_RTIEN 0x00400000
72
73#define HW_UARTAPP_DATA 0x60
74
75#define HW_UARTAPP_STAT 0x70
76#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
77#define BP_UARTAPP_STAT_RXCOUNT 0
78#define BM_UARTAPP_STAT_FERR 0x00010000
79#define BM_UARTAPP_STAT_PERR 0x00020000
80#define BM_UARTAPP_STAT_BERR 0x00040000
81#define BM_UARTAPP_STAT_OERR 0x00080000
82#define BM_UARTAPP_STAT_RXFE 0x01000000
83#define BM_UARTAPP_STAT_TXFF 0x02000000
84#define BM_UARTAPP_STAT_TXFE 0x08000000
85#define BM_UARTAPP_STAT_CTS 0x10000000
86
87#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb552a9..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
deleted file mode 100644
index 25112c1aa608..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * stmp378x: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
23#define REGS_USBCTRL_SIZE 0x2000
24
25#define HW_USBCTRL_USBCMD 0x140
26#define BM_USBCTRL_USBCMD_RS 0x00000001
27#define BP_USBCTRL_USBCMD_RS 0
28#define BM_USBCTRL_USBCMD_RST 0x00000002
29
30#define HW_USBCTRL_USBINTR 0x148
31#define BM_USBCTRL_USBINTR_UE 0x00000001
32#define BP_USBCTRL_USBINTR_UE 0
33
34#define HW_USBCTRL_PORTSC1 0x184
35#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
36
37#define HW_USBCTRL_OTGSC 0x1A4
38#define BM_USBCTRL_OTGSC_ID 0x00000100
39#define BM_USBCTRL_OTGSC_IDIS 0x00010000
40#define BM_USBCTRL_OTGSC_IDIE 0x01000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
deleted file mode 100644
index 11f3b732dc92..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * stmp378x: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22#define REGS_USBPHY_PHYS 0x8007C000
23#define REGS_USBPHY_SIZE 0x2000
24
25#define HW_USBPHY_PWD 0x0
26
27#define HW_USBPHY_CTRL 0x30
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
deleted file mode 100644
index c2f9fe04c112..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * Freescale STMP378X platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/dma-mapping.h>
23
24#include <asm/dma.h>
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/irq.h>
30#include <asm/mach/map.h>
31#include <asm/mach/time.h>
32
33#include <mach/pins.h>
34#include <mach/pinmux.h>
35#include <mach/dma.h>
36#include <mach/hardware.h>
37#include <mach/system.h>
38#include <mach/platform.h>
39#include <mach/stmp3xxx.h>
40#include <mach/regs-icoll.h>
41#include <mach/regs-apbh.h>
42#include <mach/regs-apbx.h>
43#include <mach/regs-pxp.h>
44#include <mach/regs-i2c.h>
45
46#include "stmp378x.h"
47/*
48 * IRQ handling
49 */
50static void stmp378x_ack_irq(struct irq_data *d)
51{
52 /* Tell ICOLL to release IRQ line */
53 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
54
55 /* ACK current interrupt */
56 __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
57 REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
58
59 /* Barrier */
60 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
61}
62
63static void stmp378x_mask_irq(struct irq_data *d)
64{
65 /* IRQ disable */
66 stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
67 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
68}
69
70static void stmp378x_unmask_irq(struct irq_data *d)
71{
72 /* IRQ enable */
73 stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
74 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
75}
76
77static struct irq_chip stmp378x_chip = {
78 .irq_ack = stmp378x_ack_irq,
79 .irq_mask = stmp378x_mask_irq,
80 .irq_unmask = stmp378x_unmask_irq,
81};
82
83void __init stmp378x_init_irq(void)
84{
85 stmp3xxx_init_irq(&stmp378x_chip);
86}
87
88/*
89 * DMA interrupt handling
90 */
91void stmp3xxx_arch_dma_enable_interrupt(int channel)
92{
93 void __iomem *c1, *c2;
94
95 switch (STMP3XXX_DMA_BUS(channel)) {
96 case STMP3XXX_BUS_APBH:
97 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
98 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
99 break;
100
101 case STMP3XXX_BUS_APBX:
102 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
103 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
104 break;
105
106 default:
107 return;
108 }
109 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
110 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
111}
112EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
113
114void stmp3xxx_arch_dma_clear_interrupt(int channel)
115{
116 void __iomem *c1, *c2;
117
118 switch (STMP3XXX_DMA_BUS(channel)) {
119 case STMP3XXX_BUS_APBH:
120 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
121 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
122 break;
123
124 case STMP3XXX_BUS_APBX:
125 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
126 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
127 break;
128
129 default:
130 return;
131 }
132 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
133 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
134}
135EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
136
137int stmp3xxx_arch_dma_is_interrupt(int channel)
138{
139 int r = 0;
140
141 switch (STMP3XXX_DMA_BUS(channel)) {
142 case STMP3XXX_BUS_APBH:
143 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
144 (1 << STMP3XXX_DMA_CHANNEL(channel));
145 break;
146
147 case STMP3XXX_BUS_APBX:
148 r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
149 (1 << STMP3XXX_DMA_CHANNEL(channel));
150 break;
151 }
152 return r;
153}
154EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
155
156void stmp3xxx_arch_dma_reset_channel(int channel)
157{
158 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
159 void __iomem *c0;
160 u32 mask;
161
162 switch (STMP3XXX_DMA_BUS(channel)) {
163 case STMP3XXX_BUS_APBH:
164 c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
165 mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
166 break;
167 case STMP3XXX_BUS_APBX:
168 c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
169 mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
170 break;
171 default:
172 return;
173 }
174
175 /* Reset channel and wait for it to complete */
176 stmp3xxx_setl(mask, c0);
177 while (__raw_readl(c0) & mask)
178 cpu_relax();
179}
180EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
181
182void stmp3xxx_arch_dma_freeze(int channel)
183{
184 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
185 u32 mask = 1 << chbit;
186
187 switch (STMP3XXX_DMA_BUS(channel)) {
188 case STMP3XXX_BUS_APBH:
189 stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
190 break;
191 case STMP3XXX_BUS_APBX:
192 stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
193 break;
194 }
195}
196EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
197
198void stmp3xxx_arch_dma_unfreeze(int channel)
199{
200 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
201 u32 mask = 1 << chbit;
202
203 switch (STMP3XXX_DMA_BUS(channel)) {
204 case STMP3XXX_BUS_APBH:
205 stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
206 break;
207 case STMP3XXX_BUS_APBX:
208 stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
209 break;
210 }
211}
212EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
213
214/*
215 * The registers are all very closely mapped, so we might as well map them all
216 * with a single mapping
217 *
218 * Logical Physical
219 * f0000000 80000000 On-chip registers
220 * f1000000 00000000 32k on-chip SRAM
221 */
222
223static struct map_desc stmp378x_io_desc[] __initdata = {
224 {
225 .virtual = (u32)STMP3XXX_REGS_BASE,
226 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
227 .length = STMP3XXX_REGS_SIZE,
228 .type = MT_DEVICE,
229 },
230 {
231 .virtual = (u32)STMP3XXX_OCRAM_BASE,
232 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
233 .length = STMP3XXX_OCRAM_SIZE,
234 .type = MT_DEVICE,
235 },
236};
237
238
239static u64 common_dmamask = DMA_BIT_MASK(32);
240
241/*
242 * devices that are present only on stmp378x, not on all 3xxx boards:
243 * PxP
244 * I2C
245 */
246static struct resource pxp_resource[] = {
247 {
248 .flags = IORESOURCE_MEM,
249 .start = REGS_PXP_PHYS,
250 .end = REGS_PXP_PHYS + REGS_PXP_SIZE,
251 }, {
252 .flags = IORESOURCE_IRQ,
253 .start = IRQ_PXP,
254 .end = IRQ_PXP,
255 },
256};
257
258struct platform_device stmp378x_pxp = {
259 .name = "stmp3xxx-pxp",
260 .id = -1,
261 .dev = {
262 .dma_mask = &common_dmamask,
263 .coherent_dma_mask = DMA_BIT_MASK(32),
264 },
265 .num_resources = ARRAY_SIZE(pxp_resource),
266 .resource = pxp_resource,
267};
268
269static struct resource i2c_resources[] = {
270 {
271 .flags = IORESOURCE_IRQ,
272 .start = IRQ_I2C_ERROR,
273 .end = IRQ_I2C_ERROR,
274 }, {
275 .flags = IORESOURCE_MEM,
276 .start = REGS_I2C_PHYS,
277 .end = REGS_I2C_PHYS + REGS_I2C_SIZE,
278 }, {
279 .flags = IORESOURCE_DMA,
280 .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
281 .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
282 },
283};
284
285struct platform_device stmp378x_i2c = {
286 .name = "i2c_stmp3xxx",
287 .id = 0,
288 .dev = {
289 .dma_mask = &common_dmamask,
290 .coherent_dma_mask = DMA_BIT_MASK(32),
291 },
292 .resource = i2c_resources,
293 .num_resources = ARRAY_SIZE(i2c_resources),
294};
295
296void __init stmp378x_map_io(void)
297{
298 iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
299}
diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h
deleted file mode 100644
index 0dc15b3c891f..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X internal functions and data declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __MACH_STMP378X_H
19#define __MACH_STMP378X_H
20
21void stmp378x_map_io(void);
22void stmp378x_init_irq(void);
23
24extern struct platform_device stmp378x_pxp, stmp378x_i2c;
25#endif /* __MACH_STMP378X_COMMON_H */
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
deleted file mode 100644
index 06158848afd9..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x_devb.c
+++ /dev/null
@@ -1,332 +0,0 @@
1/*
2 * Freescale STMP378X development board support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/spi/spi.h>
26
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31#include <mach/pins.h>
32#include <mach/pinmux.h>
33#include <mach/platform.h>
34#include <mach/stmp3xxx.h>
35#include <mach/mmc.h>
36#include <mach/gpmi.h>
37
38#include "stmp378x.h"
39
40static struct platform_device *devices[] = {
41 &stmp3xxx_dbguart,
42 &stmp3xxx_appuart,
43 &stmp3xxx_watchdog,
44 &stmp3xxx_touchscreen,
45 &stmp3xxx_rtc,
46 &stmp3xxx_keyboard,
47 &stmp3xxx_framebuffer,
48 &stmp3xxx_backlight,
49 &stmp3xxx_rotdec,
50 &stmp3xxx_persistent,
51 &stmp3xxx_dcp_bootstream,
52 &stmp3xxx_dcp,
53 &stmp3xxx_battery,
54 &stmp378x_pxp,
55 &stmp378x_i2c,
56};
57
58static struct pin_desc i2c_pins_desc[] = {
59 { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
60 { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
61};
62
63static struct pin_group i2c_pins = {
64 .pins = i2c_pins_desc,
65 .nr_pins = ARRAY_SIZE(i2c_pins_desc),
66};
67
68static struct pin_desc dbguart_pins_0[] = {
69 { PINID_PWM0, PIN_FUN3, },
70 { PINID_PWM1, PIN_FUN3, },
71};
72
73static struct pin_group dbguart_pins[] = {
74 [0] = {
75 .pins = dbguart_pins_0,
76 .nr_pins = ARRAY_SIZE(dbguart_pins_0),
77 },
78};
79
80static int dbguart_pins_control(int id, int request)
81{
82 int r = 0;
83
84 if (request)
85 r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
86 else
87 stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
88 return r;
89}
90
91static struct pin_desc appuart_pins_0[] = {
92 { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
93 { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
94 { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
95 { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
96};
97
98static struct pin_desc appuart_pins_1[] = {
99#if 0 /* enable these when second appuart will be connected */
100 { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
101 { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
102 { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
103 { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
104#endif
105};
106
107static struct pin_desc mmc_pins_desc[] = {
108 { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
109 { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
110 { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
111 { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
112 { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
113 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
114 { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
115};
116
117static struct pin_group mmc_pins = {
118 .pins = mmc_pins_desc,
119 .nr_pins = ARRAY_SIZE(mmc_pins_desc),
120};
121
122static int stmp3xxxmmc_get_wp(void)
123{
124 return gpio_get_value(PINID_PWM4);
125}
126
127static int stmp3xxxmmc_hw_init_ssp1(void)
128{
129 int ret;
130
131 ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
132 if (ret)
133 goto out;
134
135 /* Configure write protect GPIO pin */
136 ret = gpio_request(PINID_PWM4, "mmc wp");
137 if (ret)
138 goto out_wp;
139
140 gpio_direction_input(PINID_PWM4);
141
142 /* Configure POWER pin as gpio to drive power to MMC slot */
143 ret = gpio_request(PINID_PWM3, "mmc power");
144 if (ret)
145 goto out_power;
146
147 gpio_direction_output(PINID_PWM3, 0);
148 mdelay(100);
149
150 return 0;
151
152out_power:
153 gpio_free(PINID_PWM4);
154out_wp:
155 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
156out:
157 return ret;
158}
159
160static void stmp3xxxmmc_hw_release_ssp1(void)
161{
162 gpio_free(PINID_PWM3);
163 gpio_free(PINID_PWM4);
164 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
165}
166
167static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
168{
169 stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
170}
171
172static unsigned long
173stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
174{
175 struct clk *ssp, *parent;
176 char *p;
177 long r;
178
179 ssp = clk_get(NULL, "ssp");
180
181 /* using SSP1, no timeout, clock rate 1 */
182 writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
183 BF(0xFFFF, SSP_TIMING_TIMEOUT),
184 base + HW_SSP_TIMING);
185
186 p = (hz > 1000000) ? "io" : "osc_24M";
187 parent = clk_get(NULL, p);
188 clk_set_parent(ssp, parent);
189 r = clk_set_rate(ssp, 2 * hz / 1000);
190 clk_put(parent);
191 clk_put(ssp);
192
193 return hz;
194}
195
196static struct stmp3xxxmmc_platform_data mmc_data = {
197 .hw_init = stmp3xxxmmc_hw_init_ssp1,
198 .hw_release = stmp3xxxmmc_hw_release_ssp1,
199 .get_wp = stmp3xxxmmc_get_wp,
200 .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1,
201 .setclock = stmp3xxxmmc_setclock_ssp1,
202};
203
204
205static struct pin_group appuart_pins[] = {
206 [0] = {
207 .pins = appuart_pins_0,
208 .nr_pins = ARRAY_SIZE(appuart_pins_0),
209 },
210 [1] = {
211 .pins = appuart_pins_1,
212 .nr_pins = ARRAY_SIZE(appuart_pins_1),
213 },
214};
215
216static struct pin_desc ssp1_pins_desc[] = {
217 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
218 { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
219 { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
220 { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
221};
222
223static struct pin_desc ssp2_pins_desc[] = {
224 { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
225 { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
226 { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
227 { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
228};
229
230static struct pin_group ssp1_pins = {
231 .pins = ssp1_pins_desc,
232 .nr_pins = ARRAY_SIZE(ssp1_pins_desc),
233};
234
235static struct pin_group ssp2_pins = {
236 .pins = ssp1_pins_desc,
237 .nr_pins = ARRAY_SIZE(ssp2_pins_desc),
238};
239
240static struct pin_desc gpmi_pins_desc[] = {
241 { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
242 { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
243 { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
244 { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
245 { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
246 { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
247 { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
248 { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
249 { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
250 { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
251 { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
252 { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
253 { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
254 { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
255 { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
256 { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
257 { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
258 { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
259 { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
260 { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
261};
262
263static struct pin_group gpmi_pins = {
264 .pins = gpmi_pins_desc,
265 .nr_pins = ARRAY_SIZE(gpmi_pins_desc),
266};
267
268static struct mtd_partition gpmi_partitions[] = {
269 [0] = {
270 .name = "boot",
271 .size = 10 * SZ_1M,
272 .offset = 0,
273 },
274 [1] = {
275 .name = "data",
276 .size = MTDPART_SIZ_FULL,
277 .offset = MTDPART_OFS_APPEND,
278 },
279};
280
281static struct gpmi_platform_data gpmi_data = {
282 .pins = &gpmi_pins,
283 .nr_parts = ARRAY_SIZE(gpmi_partitions),
284 .parts = gpmi_partitions,
285 .part_types = { "cmdline", NULL },
286};
287
288static struct spi_board_info spi_board_info[] __initdata = {
289#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
290 {
291 .modalias = "enc28j60",
292 .max_speed_hz = 6 * 1000 * 1000,
293 .bus_num = 1,
294 .chip_select = 0,
295 .platform_data = NULL,
296 },
297#endif
298};
299
300static void __init stmp378x_devb_init(void)
301{
302 stmp3xxx_pinmux_init(NR_REAL_IRQS);
303
304 /* init stmp3xxx platform */
305 stmp3xxx_init();
306
307 stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
308 stmp3xxx_appuart.dev.platform_data = appuart_pins;
309 stmp3xxx_mmc.dev.platform_data = &mmc_data;
310 stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
311 stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
312 stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
313 stmp378x_i2c.dev.platform_data = &i2c_pins;
314
315 /* register spi devices */
316 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
317
318 /* add board's devices */
319 platform_add_devices(devices, ARRAY_SIZE(devices));
320
321 /* add devices selected by command line ssp1= and ssp2= options */
322 stmp3xxx_ssp1_device_register();
323 stmp3xxx_ssp2_device_register();
324}
325
326MACHINE_START(STMP378X, "STMP378X")
327 .boot_params = 0x40000100,
328 .map_io = stmp378x_map_io,
329 .init_irq = stmp378x_init_irq,
330 .timer = &stmp3xxx_timer,
331 .init_machine = stmp378x_devb_init,
332MACHINE_END
diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile
deleted file mode 100644
index 57deffd09fbf..000000000000
--- a/arch/arm/mach-stmp37xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o
2obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o
diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot
deleted file mode 100644
index 1568ad404d59..000000000000
--- a/arch/arm/mach-stmp37xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
3initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
deleted file mode 100644
index fed2787b6c34..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Low-level IRQ helper macros for Freescale STMP37XX
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23
24 mov \base, #0xf0000000 @ vm address of IRQ controller
25 ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT
26 cmp \irqnr, #0x3f
27 movne \irqstat, #0 @ Ack this IRQ
28 strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
29 moveqs \irqnr, #0 @ Zero flag set for no IRQ
30
31 .endm
32
33 .macro get_irqnr_preamble, base, tmp
34 .endm
35
36 .macro arch_ret_to_user, tmp1, tmp2
37 .endm
diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h
deleted file mode 100644
index 98f12938550d..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/irqs.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Freescale STMP37XX interrupts
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef _ASM_ARCH_IRQS_H
19#define _ASM_ARCH_IRQS_H
20
21#define IRQ_DEBUG_UART 0
22#define IRQ_COMMS_RX 1
23#define IRQ_COMMS_TX 1
24#define IRQ_SSP2_ERROR 2
25#define IRQ_VDD5V 3
26#define IRQ_HEADPHONE_SHORT 4
27#define IRQ_DAC_DMA 5
28#define IRQ_DAC_ERROR 6
29#define IRQ_ADC_DMA 7
30#define IRQ_ADC_ERROR 8
31#define IRQ_SPDIF_DMA 9
32#define IRQ_SAIF2_DMA 9
33#define IRQ_SPDIF_ERROR 10
34#define IRQ_SAIF1_IRQ 10
35#define IRQ_SAIF2_IRQ 10
36#define IRQ_USB_CTRL 11
37#define IRQ_USB_WAKEUP 12
38#define IRQ_GPMI_DMA 13
39#define IRQ_SSP1_DMA 14
40#define IRQ_SSP_ERROR 15
41#define IRQ_GPIO0 16
42#define IRQ_GPIO1 17
43#define IRQ_GPIO2 18
44#define IRQ_SAIF1_DMA 19
45#define IRQ_SSP2_DMA 20
46#define IRQ_ECC8_IRQ 21
47#define IRQ_RTC_ALARM 22
48#define IRQ_UARTAPP_TX_DMA 23
49#define IRQ_UARTAPP_INTERNAL 24
50#define IRQ_UARTAPP_RX_DMA 25
51#define IRQ_I2C_DMA 26
52#define IRQ_I2C_ERROR 27
53#define IRQ_TIMER0 28
54#define IRQ_TIMER1 29
55#define IRQ_TIMER2 30
56#define IRQ_TIMER3 31
57#define IRQ_BATT_BRNOUT 32
58#define IRQ_VDDD_BRNOUT 33
59#define IRQ_VDDIO_BRNOUT 34
60#define IRQ_VDD18_BRNOUT 35
61#define IRQ_TOUCH_DETECT 36
62#define IRQ_LRADC_CH0 37
63#define IRQ_LRADC_CH1 38
64#define IRQ_LRADC_CH2 39
65#define IRQ_LRADC_CH3 40
66#define IRQ_LRADC_CH4 41
67#define IRQ_LRADC_CH5 42
68#define IRQ_LRADC_CH6 43
69#define IRQ_LRADC_CH7 44
70#define IRQ_LCDIF_DMA 45
71#define IRQ_LCDIF_ERROR 46
72#define IRQ_DIGCTL_DEBUG_TRAP 47
73#define IRQ_RTC_1MSEC 48
74#define IRQ_DRI_DMA 49
75#define IRQ_DRI_ATTENTION 50
76#define IRQ_GPMI_ATTENTION 51
77#define IRQ_IR 52
78#define IRQ_DCP_VMI 53
79#define IRQ_DCP 54
80#define IRQ_RESERVED_55 55
81#define IRQ_RESERVED_56 56
82#define IRQ_RESERVED_57 57
83#define IRQ_RESERVED_58 58
84#define IRQ_RESERVED_59 59
85#define SW_IRQ_60 60
86#define SW_IRQ_61 61
87#define SW_IRQ_62 62
88#define SW_IRQ_63 63
89
90#define NR_REAL_IRQS 64
91#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
92
93/* TIMER and BRNOUT are FIQ capable */
94#define FIQ_START IRQ_TIMER0
95
96/* Hard disk IRQ is a GPMI attention IRQ */
97#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
98
99#endif /* _ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h
deleted file mode 100644
index d56de0c471d8..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/pins.h
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * Freescale STMP37XX SoC pin multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_PINS_H
19#define __ASM_ARCH_PINS_H
20
21/*
22 * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
23 * interface this pin belongs to.
24 */
25
26/* Bank 0 */
27#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
28#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
29#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
30#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
31#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
32#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
33#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
34#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
35#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
36#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
37#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
38#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
39#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
40#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
41#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
42#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
43#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16)
44#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17)
45#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18)
46#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
47#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20)
48#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21)
49#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22)
50#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23)
51#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
52#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
53#define PINID_UART2_CTS STMP3XXX_PINID(0, 26)
54#define PINID_UART2_RTS STMP3XXX_PINID(0, 27)
55#define PINID_UART2_RX STMP3XXX_PINID(0, 28)
56#define PINID_UART2_TX STMP3XXX_PINID(0, 29)
57
58/* Bank 1 */
59#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
60#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
61#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
62#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
63#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
64#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
65#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
66#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
67#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
68#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
69#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
70#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
71#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
72#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
73#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
74#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
75#define PINID_LCD_RESET STMP3XXX_PINID(1, 16)
76#define PINID_LCD_RS STMP3XXX_PINID(1, 17)
77#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18)
78#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19)
79#define PINID_LCD_CS STMP3XXX_PINID(1, 20)
80#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21)
81#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22)
82#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23)
83#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24)
84#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25)
85#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26)
86#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27)
87#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28)
88
89/* Bank 2 */
90#define PINID_PWM0 STMP3XXX_PINID(2, 0)
91#define PINID_PWM1 STMP3XXX_PINID(2, 1)
92#define PINID_PWM2 STMP3XXX_PINID(2, 2)
93#define PINID_PWM3 STMP3XXX_PINID(2, 3)
94#define PINID_PWM4 STMP3XXX_PINID(2, 4)
95#define PINID_I2C_SCL STMP3XXX_PINID(2, 5)
96#define PINID_I2C_SDA STMP3XXX_PINID(2, 6)
97#define PINID_ROTTARYA STMP3XXX_PINID(2, 7)
98#define PINID_ROTTARYB STMP3XXX_PINID(2, 8)
99#define PINID_EMI_CKE STMP3XXX_PINID(2, 9)
100#define PINID_EMI_RASN STMP3XXX_PINID(2, 10)
101#define PINID_EMI_CASN STMP3XXX_PINID(2, 11)
102#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12)
103#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13)
104#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14)
105#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15)
106#define PINID_EMI_A00 STMP3XXX_PINID(2, 16)
107#define PINID_EMI_A01 STMP3XXX_PINID(2, 17)
108#define PINID_EMI_A02 STMP3XXX_PINID(2, 18)
109#define PINID_EMI_A03 STMP3XXX_PINID(2, 19)
110#define PINID_EMI_A04 STMP3XXX_PINID(2, 20)
111#define PINID_EMI_A05 STMP3XXX_PINID(2, 21)
112#define PINID_EMI_A06 STMP3XXX_PINID(2, 22)
113#define PINID_EMI_A07 STMP3XXX_PINID(2, 23)
114#define PINID_EMI_A08 STMP3XXX_PINID(2, 24)
115#define PINID_EMI_A09 STMP3XXX_PINID(2, 25)
116#define PINID_EMI_A10 STMP3XXX_PINID(2, 26)
117#define PINID_EMI_A11 STMP3XXX_PINID(2, 27)
118#define PINID_EMI_A12 STMP3XXX_PINID(2, 28)
119#define PINID_EMI_A13 STMP3XXX_PINID(2, 29)
120#define PINID_EMI_A14 STMP3XXX_PINID(2, 30)
121#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
122
123/* Bank 3 */
124#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
125#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
126#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
127#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
128#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
129#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
130#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
131#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
132#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
133#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
134#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
135#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
136#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
137#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
138#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
139#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
140#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16)
141#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17)
142#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18)
143#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19)
144#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
145#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
146
147#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
deleted file mode 100644
index a323aa9a21f2..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * stmp37xx: APBH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBH
22#define _MACH_REGS_APBH
23
24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25
26#define HW_APBH_CTRL0 0x0
27#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
28#define BP_APBH_CTRL0_RESET_CHANNEL 16
29#define BM_APBH_CTRL0_CLKGATE 0x40000000
30#define BM_APBH_CTRL0_SFTRST 0x80000000
31
32#define HW_APBH_CTRL1 0x10
33#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
34#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
35
36#define HW_APBH_DEVSEL 0x20
37
38#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
39#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
40#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
41#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
42#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
43#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
44#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
45#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
46#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
47#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
48#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
49#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
50#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
51#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
52#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
53#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
54
55#define HW_APBH_CHn_NXTCMDAR 0x50
56
57#define BM_APBH_CHn_CMD_MODE 0x00000003
58#define BP_APBH_CHn_CMD_MODE 0x00000001
59#define BV_APBH_CHn_CMD_MODE_NOOP 0
60#define BV_APBH_CHn_CMD_MODE_WRITE 1
61#define BV_APBH_CHn_CMD_MODE_READ 2
62#define BV_APBH_CHn_CMD_MODE_SENSE 3
63#define BM_APBH_CHn_CMD_CHAIN 0x00000004
64#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
65#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
66#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
67#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
68#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
69#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
70#define BP_APBH_CHn_CMD_CMDWORDS 12
71#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
72#define BP_APBH_CHn_CMD_XFER_COUNT 16
73
74#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
75#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
76#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
77#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
78#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
79#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
80#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
81#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
82#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
83#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
84#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
85#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
86#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
87#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
88#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
89#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
90
91#define HW_APBH_CHn_SEMA 0x80
92#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
93#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
94#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
95#define BP_APBH_CHn_SEMA_PHORE 16
96
97#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
deleted file mode 100644
index 6d080cd5b702..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * stmp37xx: APBX register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBX
22#define _MACH_REGS_APBX
23
24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25
26#define HW_APBX_CTRL0 0x0
27#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
28#define BP_APBX_CTRL0_RESET_CHANNEL 16
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_DEVSEL 0x20
35
36#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
37#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
38#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
39#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
40#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
41#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
42#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
43#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
44#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
45#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
46#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
47#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
48#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
49#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
50#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
51#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
52
53#define HW_APBX_CHn_NXTCMDAR 0x50
54#define BM_APBX_CHn_CMD_MODE 0x00000003
55#define BP_APBX_CHn_CMD_MODE 0x00000001
56#define BV_APBX_CHn_CMD_MODE_NOOP 0
57#define BV_APBX_CHn_CMD_MODE_WRITE 1
58#define BV_APBX_CHn_CMD_MODE_READ 2
59#define BV_APBX_CHn_CMD_MODE_SENSE 3
60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
61#define BP_APBX_CHn_CMD_COMMAND 0
62#define BM_APBX_CHn_CMD_CHAIN 0x00000004
63#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
64#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
65#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
66#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
67#define BP_APBX_CHn_CMD_CMDWORDS 12
68#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
69#define BP_APBX_CHn_CMD_XFER_COUNT 16
70
71#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
72#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
73#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
74#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
75#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
76#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
77#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
78#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
79#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
80#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
81#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
82#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
83#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
84#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
85#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
86#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
87
88#define HW_APBX_CHn_BAR 0x70
89
90#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
91#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
92#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
93#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
94#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
95#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
96#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
97#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
98#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
99#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
100#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
101#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
102#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
103#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
104#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
105#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
106
107#define HW_APBX_CHn_SEMA 0x80
108#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
109#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
110#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
111#define BP_APBX_CHn_SEMA_PHORE 16
112
113#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
deleted file mode 100644
index 3b511f947a53..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * stmp37xx: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22
23#define HW_AUDIOIN_CTRL 0x0
24#define BM_AUDIOIN_CTRL_RUN 0x00000001
25#define BP_AUDIOIN_CTRL_RUN 0
26#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
30#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOIN_STAT 0x10
34
35#define HW_AUDIOIN_ADCSRR 0x20
36
37#define HW_AUDIOIN_ADCVOLUME 0x30
38#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
39#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
42
43#define HW_AUDIOIN_ADCDEBUG 0x40
44
45#define HW_AUDIOIN_ADCVOL 0x50
46#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
47#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
48#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
49#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
50#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
51#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
52#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
53#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
54#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
55
56#define HW_AUDIOIN_MICLINE 0x60
57
58#define HW_AUDIOIN_ANACLKCTRL 0x70
59#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
60
61#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
deleted file mode 100644
index ca1942b8a3e9..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * stmp37xx: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22
23#define HW_AUDIOOUT_CTRL 0x0
24#define BM_AUDIOOUT_CTRL_RUN 0x00000001
25#define BP_AUDIOOUT_CTRL_RUN 0
26#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
30#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOOUT_STAT 0x10
34
35#define HW_AUDIOOUT_DACSRR 0x20
36#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
37#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
38#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
39#define BP_AUDIOOUT_DACSRR_SRC_INT 16
40#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
41#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
42#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
43#define BP_AUDIOOUT_DACSRR_BASEMULT 28
44
45#define HW_AUDIOOUT_DACVOLUME 0x30
46#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
47#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
48#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
49
50#define HW_AUDIOOUT_DACDEBUG 0x40
51
52#define HW_AUDIOOUT_HPVOL 0x50
53#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
54#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
55
56#define HW_AUDIOOUT_PWRDN 0x70
57#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
58#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
59#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
60#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
61#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
62#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
63#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
64
65#define HW_AUDIOOUT_REFCTRL 0x80
66#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
67#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
68#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
69#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
70#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
71#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
72#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
73#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
74#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
75#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
76#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
77#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
78#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
79
80#define HW_AUDIOOUT_ANACTRL 0x90
81#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
82#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
83
84#define HW_AUDIOOUT_TEST 0xA0
85#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
86#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
87
88#define HW_AUDIOOUT_BISTCTRL 0xB0
89
90#define HW_AUDIOOUT_BISTSTAT0 0xC0
91
92#define HW_AUDIOOUT_BISTSTAT1 0xD0
93
94#define HW_AUDIOOUT_ANACLKCTRL 0xE0
95#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
96
97#define HW_AUDIOOUT_DATA 0xF0
98
99#define HW_AUDIOOUT_LINEOUTCTRL 0x100
100#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
101#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
102#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
103#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
104#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
105#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
106#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
107#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
108#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
109#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
110
111#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
deleted file mode 100644
index 47f5c92fdaf6..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * stmp37xx: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
23
24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
25
26#define HW_CLKCTRL_PLLCTRL0 0x0
27#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
28
29#define HW_CLKCTRL_CPU 0x20
30#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
31#define BP_CLKCTRL_CPU_DIV_CPU 0
32
33#define HW_CLKCTRL_HBUS 0x30
34#define BM_CLKCTRL_HBUS_DIV 0x0000001F
35#define BP_CLKCTRL_HBUS_DIV 0
36
37#define HW_CLKCTRL_XBUS 0x40
38
39#define HW_CLKCTRL_XTAL 0x50
40
41#define HW_CLKCTRL_PIX 0x60
42#define BM_CLKCTRL_PIX_DIV 0x00007FFF
43#define BP_CLKCTRL_PIX_DIV 0
44#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
45
46#define HW_CLKCTRL_SSP 0x70
47
48#define HW_CLKCTRL_GPMI 0x80
49
50#define HW_CLKCTRL_SPDIF 0x90
51
52#define HW_CLKCTRL_EMI 0xA0
53
54#define HW_CLKCTRL_IR 0xB0
55
56#define HW_CLKCTRL_SAIF 0xC0
57
58#define HW_CLKCTRL_FRAC 0xD0
59#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
60#define BP_CLKCTRL_FRAC_EMIFRAC 8
61#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
62#define BP_CLKCTRL_FRAC_PIXFRAC 16
63#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
64
65#define HW_CLKCTRL_CLKSEQ 0xE0
66#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
67
68#define HW_CLKCTRL_RESET 0xF0
69#define BM_CLKCTRL_RESET_DIG 0x00000001
70#define BP_CLKCTRL_RESET_DIG 0
71
72#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
deleted file mode 100644
index ba1bbe265c20..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * stmp37xx: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22
23#define HW_DIGCTL_CTRL 0x0
24#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
deleted file mode 100644
index 3b6d990a3af5..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * stmp37xx: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22
23#define HW_ECC8_CTRL 0x0
24#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
25#define BP_ECC8_CTRL_COMPLETE_IRQ 0
26#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
27#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
28
29#define HW_ECC8_STATUS0 0x10
30#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
31#define BM_ECC8_STATUS0_CORRECTED 0x00000008
32#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
33#define BP_ECC8_STATUS0_STATUS_AUX 8
34#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
35#define BP_ECC8_STATUS0_COMPLETED_CE 16
36
37#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
deleted file mode 100644
index f2b304f54490..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp37xx: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
33#define BP_GPMI_CTRL0_COMMAND_MODE 24
34#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
35#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
36#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
37#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
38#define BM_GPMI_CTRL0_RUN 0x20000000
39#define BM_GPMI_CTRL0_CLKGATE 0x40000000
40#define BM_GPMI_CTRL0_SFTRST 0x80000000
41#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
42#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
43#define BP_GPMI_ECCCTRL_ECC_CMD 13
44
45#define HW_GPMI_CTRL1 0x60
46#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
47#define BP_GPMI_CTRL1_GPMI_MODE 0
48#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
49#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
50#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
51#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
52#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
53#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
54
55#define HW_GPMI_TIMING0 0x70
56#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
57#define BP_GPMI_TIMING0_DATA_SETUP 0
58#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
59#define BP_GPMI_TIMING0_DATA_HOLD 8
60
61#define HW_GPMI_TIMING1 0x80
62#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
63#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
deleted file mode 100644
index 35882a9b8bc5..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * stmp37xx: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
deleted file mode 100644
index 3b7c92239e20..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * stmp37xx: ICOLL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
25
26#define HW_ICOLL_VECTOR 0x0
27
28#define HW_ICOLL_LEVELACK 0x10
29
30#define HW_ICOLL_CTRL 0x20
31#define BM_ICOLL_CTRL_CLKGATE 0x40000000
32#define BM_ICOLL_CTRL_SFTRST 0x80000000
33
34#define HW_ICOLL_STAT 0x30
35
36#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
37#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
38#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
39#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
40
41#define HW_ICOLL_PRIORITYn 0x60
42
43#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
deleted file mode 100644
index 72514e8b0737..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * stmp37xx: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
27#define BP_LCDIF_CTRL_COUNT 0
28#define BM_LCDIF_CTRL_RUN 0x00010000
29#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
30#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
31#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
32#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
33#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
34#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
35#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
36#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
37#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
38#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
39#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
40#define BM_LCDIF_CTRL_CLKGATE 0x40000000
41#define BM_LCDIF_CTRL_SFTRST 0x80000000
42
43#define HW_LCDIF_CTRL1 0x10
44#define BM_LCDIF_CTRL1_RESET 0x00000001
45#define BP_LCDIF_CTRL1_RESET 0
46#define BM_LCDIF_CTRL1_MODE86 0x00000002
47#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
48#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
49#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
50#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
51#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
52#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
53#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
54#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
55
56#define HW_LCDIF_TIMING 0x20
57
58#define HW_LCDIF_VDCTRL0 0x30
59#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
60#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
61#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
62#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
63#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
64#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
65#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
66#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
67#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
68#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
69
70#define HW_LCDIF_VDCTRL1 0x40
71#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
72#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
73#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
74#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
75
76#define HW_LCDIF_VDCTRL2 0x50
77#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
78#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
79#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
80#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
81#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
82#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
83
84#define HW_LCDIF_VDCTRL3 0x60
85#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
86#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
87#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
88#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
89#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
deleted file mode 100644
index cc7b4702d1cd..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * stmp37xx: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22
23#define HW_LRADC_CTRL0 0x0
24#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
25#define BP_LRADC_CTRL0_SCHEDULE 0
26#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
27#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
28#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
29#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
30#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
31#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
32#define BM_LRADC_CTRL0_CLKGATE 0x40000000
33#define BM_LRADC_CTRL0_SFTRST 0x80000000
34
35#define HW_LRADC_CTRL1 0x10
36#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
37#define BP_LRADC_CTRL1_LRADC0_IRQ 0
38#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
39#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
40#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
41#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
42#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
43#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
44
45#define HW_LRADC_CTRL2 0x20
46#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
47#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
48#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
49#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
50#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
51#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
52
53#define HW_LRADC_CTRL3 0x30
54#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
55#define BP_LRADC_CTRL3_CYCLE_TIME 8
56
57#define HW_LRADC_STATUS 0x40
58#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
59#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
60
61#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
62#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
63#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
64#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
65#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
66#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
67#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
68#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
69
70#define HW_LRADC_CHn 0x50
71#define BM_LRADC_CHn_VALUE 0x0003FFFF
72#define BP_LRADC_CHn_VALUE 0
73#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
74#define BP_LRADC_CHn_NUM_SAMPLES 24
75#define BM_LRADC_CHn_ACCUMULATE 0x20000000
76
77#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
78#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
79#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
80#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
81
82#define HW_LRADC_DELAYn 0xD0
83#define BM_LRADC_DELAYn_DELAY 0x000007FF
84#define BP_LRADC_DELAYn_DELAY 0
85#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
86#define BP_LRADC_DELAYn_LOOP_COUNT 11
87#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
88#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
89#define BM_LRADC_DELAYn_KICK 0x00100000
90#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
91#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
92
93#define HW_LRADC_CTRL4 0x140
94#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
95#define BP_LRADC_CTRL4_LRADC6SELECT 24
96#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
97#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
deleted file mode 100644
index d5efce2388c7..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * stmp37xx: PINCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
23
24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
25
26#define HW_PINCTRL_MUXSEL0 0x100
27#define HW_PINCTRL_MUXSEL1 0x110
28#define HW_PINCTRL_MUXSEL2 0x120
29#define HW_PINCTRL_MUXSEL3 0x130
30#define HW_PINCTRL_MUXSEL4 0x140
31#define HW_PINCTRL_MUXSEL5 0x150
32#define HW_PINCTRL_MUXSEL6 0x160
33#define HW_PINCTRL_MUXSEL7 0x170
34
35#define HW_PINCTRL_DRIVE0 0x200
36#define HW_PINCTRL_DRIVE1 0x210
37#define HW_PINCTRL_DRIVE2 0x220
38#define HW_PINCTRL_DRIVE3 0x230
39#define HW_PINCTRL_DRIVE4 0x240
40#define HW_PINCTRL_DRIVE5 0x250
41#define HW_PINCTRL_DRIVE6 0x260
42#define HW_PINCTRL_DRIVE7 0x270
43#define HW_PINCTRL_DRIVE8 0x280
44#define HW_PINCTRL_DRIVE9 0x290
45#define HW_PINCTRL_DRIVE10 0x2A0
46#define HW_PINCTRL_DRIVE11 0x2B0
47#define HW_PINCTRL_DRIVE12 0x2C0
48#define HW_PINCTRL_DRIVE13 0x2D0
49#define HW_PINCTRL_DRIVE14 0x2E0
50
51#define HW_PINCTRL_PULL0 0x300
52#define HW_PINCTRL_PULL1 0x310
53#define HW_PINCTRL_PULL2 0x320
54#define HW_PINCTRL_PULL3 0x330
55
56#define HW_PINCTRL_DOUT0 0x400
57#define HW_PINCTRL_DOUT1 0x410
58#define HW_PINCTRL_DOUT2 0x420
59
60#define HW_PINCTRL_DIN0 0x500
61#define HW_PINCTRL_DIN1 0x510
62#define HW_PINCTRL_DIN2 0x520
63
64#define HW_PINCTRL_DOE0 0x600
65#define HW_PINCTRL_DOE1 0x610
66#define HW_PINCTRL_DOE2 0x620
67
68#define HW_PINCTRL_PIN2IRQ0 0x700
69#define HW_PINCTRL_PIN2IRQ1 0x710
70#define HW_PINCTRL_PIN2IRQ2 0x720
71
72#define HW_PINCTRL_IRQEN0 0x800
73#define HW_PINCTRL_IRQEN1 0x810
74#define HW_PINCTRL_IRQEN2 0x820
75
76#define HW_PINCTRL_IRQLEVEL0 0x900
77#define HW_PINCTRL_IRQLEVEL1 0x910
78#define HW_PINCTRL_IRQLEVEL2 0x920
79
80#define HW_PINCTRL_IRQPOL0 0xA00
81#define HW_PINCTRL_IRQPOL1 0xA10
82#define HW_PINCTRL_IRQPOL2 0xA20
83
84#define HW_PINCTRL_IRQSTAT0 0xB00
85#define HW_PINCTRL_IRQSTAT1 0xB10
86#define HW_PINCTRL_IRQSTAT2 0xB20
87
88#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
deleted file mode 100644
index 0e733d74a229..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * stmp37xx: POWER register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
23
24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
25
26#define HW_POWER_CTRL 0x0
27#define BM_POWER_CTRL_CLKGATE 0x40000000
28
29#define HW_POWER_5VCTRL 0x10
30
31#define HW_POWER_MINPWR 0x20
32
33#define HW_POWER_CHARGE 0x30
34
35#define HW_POWER_VDDDCTRL 0x40
36
37#define HW_POWER_VDDACTRL 0x50
38
39#define HW_POWER_VDDIOCTRL 0x60
40#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
41#define BP_POWER_VDDIOCTRL_TRG 0
42
43#define HW_POWER_STS 0xB0
44#define BM_POWER_STS_VBUSVALID 0x00000002
45#define BM_POWER_STS_BVALID 0x00000004
46#define BM_POWER_STS_AVALID 0x00000008
47#define BM_POWER_STS_DC_OK 0x00000100
48
49#define HW_POWER_RESET 0xE0
50
51#define HW_POWER_DEBUG 0xF0
52#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
53#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
54#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
55
56#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
deleted file mode 100644
index 15966a1b62e0..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * stmp37xx: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22
23#define HW_PWM_CTRL 0x0
24#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
25#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
26
27#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
28#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
29#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
30#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
31
32#define HW_PWM_ACTIVEn 0x10
33#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
34#define BP_PWM_ACTIVEn_ACTIVE 0
35#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
36#define BP_PWM_ACTIVEn_INACTIVE 16
37
38#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
39#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
40#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
41#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
42
43#define HW_PWM_PERIODn 0x20
44#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
45#define BP_PWM_PERIODn_PERIOD 0
46#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
47#define BP_PWM_PERIODn_ACTIVE_STATE 16
48#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
49#define BP_PWM_PERIODn_INACTIVE_STATE 18
50#define BM_PWM_PERIODn_CDIV 0x00700000
51#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
deleted file mode 100644
index fac40edc38a1..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * stmp37xx: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56
57#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
deleted file mode 100644
index cbde891a06c2..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * stmp37xx: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_PHYS 0x80034000
24#define REGS_SSP_SIZE 0x2000
25
26#define HW_SSP_CTRL0 0x0
27#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
28#define BP_SSP_CTRL0_XFER_COUNT 0
29#define BM_SSP_CTRL0_ENABLE 0x00010000
30#define BM_SSP_CTRL0_GET_RESP 0x00020000
31#define BM_SSP_CTRL0_LONG_RESP 0x00080000
32#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
33#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
34#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
35#define BP_SSP_CTRL0_BUS_WIDTH 22
36#define BM_SSP_CTRL0_DATA_XFER 0x01000000
37#define BM_SSP_CTRL0_READ 0x02000000
38#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
39#define BM_SSP_CTRL0_LOCK_CS 0x08000000
40#define BM_SSP_CTRL0_RUN 0x20000000
41#define BM_SSP_CTRL0_CLKGATE 0x40000000
42#define BM_SSP_CTRL0_SFTRST 0x80000000
43
44#define HW_SSP_CMD0 0x10
45#define BM_SSP_CMD0_CMD 0x000000FF
46#define BP_SSP_CMD0_CMD 0
47#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
48#define BP_SSP_CMD0_BLOCK_COUNT 8
49#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
50#define BP_SSP_CMD0_BLOCK_SIZE 16
51#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
52#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
53#define BP_SSP_CMD1_CMD_ARG 0
54
55#define HW_SSP_TIMING 0x50
56#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
57#define BP_SSP_TIMING_CLOCK_RATE 0
58#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
59#define BP_SSP_TIMING_CLOCK_DIVIDE 8
60#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
61#define BP_SSP_TIMING_TIMEOUT 16
62
63#define HW_SSP_CTRL1 0x60
64#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
65#define BP_SSP_CTRL1_SSP_MODE 0
66#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
67#define BP_SSP_CTRL1_WORD_LENGTH 4
68#define BM_SSP_CTRL1_POLARITY 0x00000200
69#define BM_SSP_CTRL1_PHASE 0x00000400
70#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
71#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
72#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
74#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
75#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
77#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
79#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
81#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
83#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
84
85#define HW_SSP_DATA 0x70
86
87#define HW_SSP_SDRESP0 0x80
88
89#define HW_SSP_SDRESP1 0x90
90
91#define HW_SSP_SDRESP2 0xA0
92
93#define HW_SSP_SDRESP3 0xB0
94
95#define HW_SSP_STATUS 0xC0
96#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
97#define BM_SSP_STATUS_TIMEOUT 0x00001000
98#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
99#define BM_SSP_STATUS_RESP_ERR 0x00008000
100#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
101#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
deleted file mode 100644
index 4af0f6edfa78..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * stmp37xx: TIMROT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_TIMROT
22#define _MACH_REGS_TIMROT
23
24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25
26#define HW_TIMROT_ROTCTRL 0x0
27#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
28#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
29
30#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
31#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
32#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
33
34#define HW_TIMROT_TIMCTRLn 0x20
35#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
36#define BP_TIMROT_TIMCTRLn_SELECT 0
37#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
38#define BP_TIMROT_TIMCTRLn_PRESCALE 4
39#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
40#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
41#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
42#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
43
44#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
45#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
46#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
47
48#define HW_TIMROT_TIMCOUNTn 0x30
49#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
deleted file mode 100644
index 0594275d860c..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * stmp37xx: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP_SIZE 0x2000
24
25#define HW_UARTAPP_CTRL0 0x0
26#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_UARTAPP_CTRL0_XFER_COUNT 0
28#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
29#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
30#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
31#define BM_UARTAPP_CTRL0_RUN 0x20000000
32#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
33#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
34#define BP_UARTAPP_CTRL1_XFER_COUNT 0
35#define BM_UARTAPP_CTRL1_RUN 0x10000000
36
37#define HW_UARTAPP_CTRL2 0x20
38#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
39#define BP_UARTAPP_CTRL2_UARTEN 0
40#define BM_UARTAPP_CTRL2_TXE 0x00000100
41#define BM_UARTAPP_CTRL2_RXE 0x00000200
42#define BM_UARTAPP_CTRL2_RTS 0x00000800
43#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
44#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
45#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
46#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
47#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
48
49#define HW_UARTAPP_LINECTRL 0x30
50#define BM_UARTAPP_LINECTRL_BRK 0x00000001
51#define BP_UARTAPP_LINECTRL_BRK 0
52#define BM_UARTAPP_LINECTRL_PEN 0x00000002
53#define BM_UARTAPP_LINECTRL_EPS 0x00000004
54#define BM_UARTAPP_LINECTRL_STP2 0x00000008
55#define BM_UARTAPP_LINECTRL_FEN 0x00000010
56#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
57#define BP_UARTAPP_LINECTRL_WLEN 5
58#define BM_UARTAPP_LINECTRL_SPS 0x00000080
59#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
60#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
61#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
62#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
63
64#define HW_UARTAPP_INTR 0x50
65#define BM_UARTAPP_INTR_CTSMIS 0x00000002
66#define BM_UARTAPP_INTR_RTIS 0x00000040
67#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
68#define BM_UARTAPP_INTR_RXIEN 0x00100000
69#define BM_UARTAPP_INTR_RTIEN 0x00400000
70
71#define HW_UARTAPP_DATA 0x60
72
73#define HW_UARTAPP_STAT 0x70
74#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
75#define BP_UARTAPP_STAT_RXCOUNT 0
76#define BM_UARTAPP_STAT_FERR 0x00010000
77#define BM_UARTAPP_STAT_PERR 0x00020000
78#define BM_UARTAPP_STAT_BERR 0x00040000
79#define BM_UARTAPP_STAT_OERR 0x00080000
80#define BM_UARTAPP_STAT_RXFE 0x01000000
81#define BM_UARTAPP_STAT_TXFF 0x02000000
82#define BM_UARTAPP_STAT_TXFE 0x08000000
83#define BM_UARTAPP_STAT_CTS 0x10000000
84
85#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb552a9..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
deleted file mode 100644
index 9145e22df32c..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * stmp37xx: USBCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTL_PHYS 0x80000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
deleted file mode 100644
index 1a2ae9cbdfed..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * stmp37xx: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
deleted file mode 100644
index b7fce0fbc560..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * stmp37xx: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22
23#define HW_USBPHY_PWD 0x0
24
25#define HW_USBPHY_CTRL 0x30
26#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
27#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c
deleted file mode 100644
index a9aed06ff376..000000000000
--- a/arch/arm/mach-stmp37xx/stmp37xx.c
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * Freescale STMP37XX platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/device.h>
22#include <linux/platform_device.h>
23#include <linux/irq.h>
24#include <linux/io.h>
25
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/map.h>
32#include <asm/mach/time.h>
33
34#include <mach/stmp3xxx.h>
35#include <mach/dma.h>
36
37#include <mach/platform.h>
38#include <mach/regs-icoll.h>
39#include <mach/regs-apbh.h>
40#include <mach/regs-apbx.h>
41#include "stmp37xx.h"
42
43/*
44 * IRQ handling
45 */
46static void stmp37xx_ack_irq(struct irq_data *d)
47{
48 /* Disable IRQ */
49 stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
50 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
51
52 /* ACK current interrupt */
53 __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
54
55 /* Barrier */
56 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
57}
58
59static void stmp37xx_mask_irq(struct irq_data *d)
60{
61 /* IRQ disable */
62 stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
63 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
64}
65
66static void stmp37xx_unmask_irq(struct irq_data *d)
67{
68 /* IRQ enable */
69 stmp3xxx_setl(0x04 << ((d->irq % 4) * 8),
70 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
71}
72
73static struct irq_chip stmp37xx_chip = {
74 .irq_ack = stmp37xx_ack_irq,
75 .irq_mask = stmp37xx_mask_irq,
76 .irq_unmask = stmp37xx_unmask_irq,
77};
78
79void __init stmp37xx_init_irq(void)
80{
81 stmp3xxx_init_irq(&stmp37xx_chip);
82}
83
84/*
85 * DMA interrupt handling
86 */
87void stmp3xxx_arch_dma_enable_interrupt(int channel)
88{
89 switch (STMP3XXX_DMA_BUS(channel)) {
90 case STMP3XXX_BUS_APBH:
91 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
92 REGS_APBH_BASE + HW_APBH_CTRL1);
93 break;
94
95 case STMP3XXX_BUS_APBX:
96 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
97 REGS_APBX_BASE + HW_APBX_CTRL1);
98 break;
99 }
100}
101EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
102
103void stmp3xxx_arch_dma_clear_interrupt(int channel)
104{
105 switch (STMP3XXX_DMA_BUS(channel)) {
106 case STMP3XXX_BUS_APBH:
107 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
108 REGS_APBH_BASE + HW_APBH_CTRL1);
109 break;
110
111 case STMP3XXX_BUS_APBX:
112 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
113 REGS_APBX_BASE + HW_APBX_CTRL1);
114 break;
115 }
116}
117EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
118
119int stmp3xxx_arch_dma_is_interrupt(int channel)
120{
121 int r = 0;
122
123 switch (STMP3XXX_DMA_BUS(channel)) {
124 case STMP3XXX_BUS_APBH:
125 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
126 (1 << STMP3XXX_DMA_CHANNEL(channel));
127 break;
128
129 case STMP3XXX_BUS_APBX:
130 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
131 (1 << STMP3XXX_DMA_CHANNEL(channel));
132 break;
133 }
134 return r;
135}
136EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
137
138void stmp3xxx_arch_dma_reset_channel(int channel)
139{
140 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
141
142 switch (STMP3XXX_DMA_BUS(channel)) {
143 case STMP3XXX_BUS_APBH:
144 /* Reset channel and wait for it to complete */
145 stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
146 REGS_APBH_BASE + HW_APBH_CTRL0);
147 while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
148 (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
149 cpu_relax();
150 break;
151
152 case STMP3XXX_BUS_APBX:
153 stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
154 REGS_APBX_BASE + HW_APBX_CTRL0);
155 while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
156 (chbit << BP_APBX_CTRL0_RESET_CHANNEL))
157 cpu_relax();
158 break;
159 }
160}
161EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
162
163void stmp3xxx_arch_dma_freeze(int channel)
164{
165 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
166
167 switch (STMP3XXX_DMA_BUS(channel)) {
168 case STMP3XXX_BUS_APBH:
169 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
170 break;
171 case STMP3XXX_BUS_APBX:
172 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
173 break;
174 }
175}
176EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
177
178void stmp3xxx_arch_dma_unfreeze(int channel)
179{
180 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
181
182 switch (STMP3XXX_DMA_BUS(channel)) {
183 case STMP3XXX_BUS_APBH:
184 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
185 break;
186 case STMP3XXX_BUS_APBX:
187 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
188 break;
189 }
190}
191EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
192
193/*
194 * The registers are all very closely mapped, so we might as well map them all
195 * with a single mapping
196 *
197 * Logical Physical
198 * f0000000 80000000 On-chip registers
199 * f1000000 00000000 32k on-chip SRAM
200 */
201static struct map_desc stmp37xx_io_desc[] __initdata = {
202 {
203 .virtual = (u32)STMP3XXX_REGS_BASE,
204 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
205 .length = SZ_1M,
206 .type = MT_DEVICE
207 },
208 {
209 .virtual = (u32)STMP3XXX_OCRAM_BASE,
210 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
211 .length = STMP3XXX_OCRAM_SIZE,
212 .type = MT_DEVICE,
213 },
214};
215
216void __init stmp37xx_map_io(void)
217{
218 iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
219}
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h
deleted file mode 100644
index 0b75fb796a64..000000000000
--- a/arch/arm/mach-stmp37xx/stmp37xx.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X internal functions and data declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __MACH_STMP37XX_H
19#define __MACH_STMP37XX_H
20
21void stmp37xx_map_io(void);
22void stmp37xx_init_irq(void);
23
24#endif /* __MACH_STMP37XX_H */
diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
deleted file mode 100644
index 311d8552d362..000000000000
--- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Freescale STMP37XX development board support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <asm/setup.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25
26#include <mach/stmp3xxx.h>
27#include <mach/pins.h>
28#include <mach/pinmux.h>
29#include "stmp37xx.h"
30
31/*
32 * List of STMP37xx development board specific devices
33 */
34static struct platform_device *stmp37xx_devb_devices[] = {
35 &stmp3xxx_dbguart,
36 &stmp3xxx_appuart,
37};
38
39static struct pin_desc dbguart_pins_0[] = {
40 { PINID_PWM0, PIN_FUN3, },
41 { PINID_PWM1, PIN_FUN3, },
42};
43
44struct pin_desc appuart_pins_0[] = {
45 { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
46 { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
47 { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
48 { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
49};
50
51static struct pin_group appuart_pins[] = {
52 [0] = {
53 .pins = appuart_pins_0,
54 .nr_pins = ARRAY_SIZE(appuart_pins_0),
55 },
56 /* 37xx has the only app uart */
57};
58
59static struct pin_group dbguart_pins[] = {
60 [0] = {
61 .pins = dbguart_pins_0,
62 .nr_pins = ARRAY_SIZE(dbguart_pins_0),
63 },
64};
65
66static int dbguart_pins_control(int id, int request)
67{
68 int r = 0;
69
70 if (request)
71 r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
72 else
73 stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
74 return r;
75}
76
77
78static void __init stmp37xx_devb_init(void)
79{
80 stmp3xxx_pinmux_init(NR_REAL_IRQS);
81
82 /* Init STMP3xxx platform */
83 stmp3xxx_init();
84
85 stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
86 stmp3xxx_appuart.dev.platform_data = appuart_pins;
87
88 /* Add STMP37xx development board devices */
89 platform_add_devices(stmp37xx_devb_devices,
90 ARRAY_SIZE(stmp37xx_devb_devices));
91}
92
93MACHINE_START(STMP37XX, "STMP37XX")
94 .boot_params = 0x40000100,
95 .map_io = stmp37xx_map_io,
96 .init_irq = stmp37xx_init_irq,
97 .timer = &stmp3xxx_timer,
98 .init_machine = stmp37xx_devb_init,
99MACHINE_END
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c
index e0a8d609afe1..a96babe83771 100644
--- a/arch/arm/mach-tcc8k/time.c
+++ b/arch/arm/mach-tcc8k/time.c
@@ -25,19 +25,6 @@
25 25
26static void __iomem *timer_base; 26static void __iomem *timer_base;
27 27
28static cycle_t tcc_get_cycles(struct clocksource *cs)
29{
30 return __raw_readl(timer_base + TC32MCNT_OFFS);
31}
32
33static struct clocksource clocksource_tcc = {
34 .name = "tcc_tc32",
35 .rating = 200,
36 .read = tcc_get_cycles,
37 .mask = CLOCKSOURCE_MASK(32),
38 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
39};
40
41static int tcc_set_next_event(unsigned long evt, 28static int tcc_set_next_event(unsigned long evt,
42 struct clock_event_device *unused) 29 struct clock_event_device *unused)
43{ 30{
@@ -102,7 +89,8 @@ static int __init tcc_clockevent_init(struct clk *clock)
102{ 89{
103 unsigned int c = clk_get_rate(clock); 90 unsigned int c = clk_get_rate(clock);
104 91
105 clocksource_register_hz(&clocksource_tcc, c); 92 clocksource_mmio_init(timer_base + TC32MCNT_OFFS, "tcc_tc32", c,
93 200, 32, clocksource_mmio_readl_up);
106 94
107 clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC, 95 clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
108 clockevent_tcc.shift); 96 clockevent_tcc.shift);
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1afe05038c27..823c703e573c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,7 @@
1obj-y += common.o 1obj-y += common.o
2obj-y += devices.o 2obj-y += devices.o
3obj-y += io.o 3obj-y += io.o
4obj-y += irq.o legacy_irq.o 4obj-y += irq.o
5obj-y += clock.o 5obj-y += clock.o
6obj-y += timer.o 6obj-y += timer.o
7obj-y += gpio.o 7obj-y += gpio.o
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 65a1aba6823d..919d63837736 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -24,6 +24,8 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26 26
27#include <asm/mach/irq.h>
28
27#include <mach/iomap.h> 29#include <mach/iomap.h>
28#include <mach/suspend.h> 30#include <mach/suspend.h>
29 31
@@ -221,8 +223,9 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
221 int port; 223 int port;
222 int pin; 224 int pin;
223 int unmasked = 0; 225 int unmasked = 0;
226 struct irq_chip *chip = irq_desc_get_chip(desc);
224 227
225 desc->irq_data.chip->irq_ack(&desc->irq_data); 228 chained_irq_enter(chip, desc);
226 229
227 bank = irq_get_handler_data(irq); 230 bank = irq_get_handler_data(irq);
228 231
@@ -241,7 +244,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
241 */ 244 */
242 if (lvl & (0x100 << pin)) { 245 if (lvl & (0x100 << pin)) {
243 unmasked = 1; 246 unmasked = 1;
244 desc->irq_data.chip->irq_unmask(&desc->irq_data); 247 chained_irq_exit(chip, desc);
245 } 248 }
246 249
247 generic_handle_irq(gpio_to_irq(gpio + pin)); 250 generic_handle_irq(gpio_to_irq(gpio + pin));
@@ -249,7 +252,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
249 } 252 }
250 253
251 if (!unmasked) 254 if (!unmasked)
252 desc->irq_data.chip->irq_unmask(&desc->irq_data); 255 chained_irq_exit(chip, desc);
253 256
254} 257}
255 258
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
deleted file mode 100644
index d898c0e3d905..000000000000
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/legacy_irq.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
19#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
20
21void tegra_legacy_mask_irq(unsigned int irq);
22void tegra_legacy_unmask_irq(unsigned int irq);
23void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
24void tegra_legacy_force_irq_set(unsigned int irq);
25void tegra_legacy_force_irq_clr(unsigned int irq);
26int tegra_legacy_force_irq_status(unsigned int irq);
27void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
28unsigned long tegra_legacy_vfiq(int nr);
29unsigned long tegra_legacy_class(int nr);
30int tegra_legacy_irq_set_wake(int irq, int enable);
31void tegra_legacy_irq_set_lp1_wake_mask(void);
32void tegra_legacy_irq_restore_mask(void);
33void tegra_init_legacy_irq(void);
34
35#endif
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
deleted file mode 100644
index c8221b38ee7c..000000000000
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11 gic_raise_softirq(mask, ipi);
12}
13
14#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4330d8995b27..4956c3cea731 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (C) 2010 Google, Inc. 2 * Copyright (C) 2011 Google, Inc.
3 * 3 *
4 * Author: 4 * Author:
5 * Colin Cross <ccross@google.com> 5 * Colin Cross <ccross@android.com>
6 * 6 *
7 * Copyright (C) 2010, NVIDIA Corporation 7 * Copyright (C) 2010, NVIDIA Corporation
8 * 8 *
@@ -18,8 +18,6 @@
18 */ 18 */
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/interrupt.h> 21#include <linux/interrupt.h>
24#include <linux/irq.h> 22#include <linux/irq.h>
25#include <linux/io.h> 23#include <linux/io.h>
@@ -27,134 +25,110 @@
27#include <asm/hardware/gic.h> 25#include <asm/hardware/gic.h>
28 26
29#include <mach/iomap.h> 27#include <mach/iomap.h>
30#include <mach/legacy_irq.h>
31#include <mach/suspend.h>
32 28
33#include "board.h" 29#include "board.h"
34 30
35#define PMC_CTRL 0x0 31#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
36#define PMC_CTRL_LATCH_WAKEUPS (1 << 5) 32#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
37#define PMC_WAKE_MASK 0xc 33#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
38#define PMC_WAKE_LEVEL 0x10 34
39#define PMC_WAKE_STATUS 0x14 35#define ICTLR_CPU_IEP_VFIQ 0x08
40#define PMC_SW_WAKE_STATUS 0x18 36#define ICTLR_CPU_IEP_FIR 0x14
41#define PMC_DPD_SAMPLE 0x20 37#define ICTLR_CPU_IEP_FIR_SET 0x18
38#define ICTLR_CPU_IEP_FIR_CLR 0x1c
39
40#define ICTLR_CPU_IER 0x20
41#define ICTLR_CPU_IER_SET 0x24
42#define ICTLR_CPU_IER_CLR 0x28
43#define ICTLR_CPU_IEP_CLASS 0x2C
44
45#define ICTLR_COP_IER 0x30
46#define ICTLR_COP_IER_SET 0x34
47#define ICTLR_COP_IER_CLR 0x38
48#define ICTLR_COP_IEP_CLASS 0x3c
49
50#define NUM_ICTLRS 4
51#define FIRST_LEGACY_IRQ 32
52
53static void __iomem *ictlr_reg_base[] = {
54 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
55 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
56 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
57 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
58};
42 59
43static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 60static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
61{
62 void __iomem *base;
63 u32 mask;
44 64
45static u32 tegra_lp0_wake_enb; 65 BUG_ON(irq < FIRST_LEGACY_IRQ ||
46static u32 tegra_lp0_wake_level; 66 irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
47static u32 tegra_lp0_wake_level_any;
48 67
49static void (*tegra_gic_mask_irq)(struct irq_data *d); 68 base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
50static void (*tegra_gic_unmask_irq)(struct irq_data *d); 69 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
51static void (*tegra_gic_ack_irq)(struct irq_data *d);
52 70
53/* ensures that sufficient time is passed for a register write to 71 __raw_writel(mask, base + reg);
54 * serialize into the 32KHz domain */
55static void pmc_32kwritel(u32 val, unsigned long offs)
56{
57 writel(val, pmc + offs);
58 udelay(130);
59} 72}
60 73
61int tegra_set_lp1_wake(int irq, int enable) 74static void tegra_mask(struct irq_data *d)
62{ 75{
63 return tegra_legacy_irq_set_wake(irq, enable); 76 if (d->irq < FIRST_LEGACY_IRQ)
77 return;
78
79 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
64} 80}
65 81
66void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) 82static void tegra_unmask(struct irq_data *d)
67{ 83{
68 u32 temp; 84 if (d->irq < FIRST_LEGACY_IRQ)
69 u32 status; 85 return;
70 u32 lvl;
71
72 wake_level &= wake_enb;
73 wake_any &= wake_enb;
74 86
75 wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb); 87 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
76 wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
77
78 wake_enb |= tegra_lp0_wake_enb;
79
80 pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
81 temp = readl(pmc + PMC_CTRL);
82 temp |= PMC_CTRL_LATCH_WAKEUPS;
83 pmc_32kwritel(temp, PMC_CTRL);
84 temp &= ~PMC_CTRL_LATCH_WAKEUPS;
85 pmc_32kwritel(temp, PMC_CTRL);
86 status = readl(pmc + PMC_SW_WAKE_STATUS);
87 lvl = readl(pmc + PMC_WAKE_LEVEL);
88
89 /* flip the wakeup trigger for any-edge triggered pads
90 * which are currently asserting as wakeups */
91 lvl ^= status;
92 lvl &= wake_any;
93
94 wake_level |= lvl;
95
96 writel(wake_level, pmc + PMC_WAKE_LEVEL);
97 /* Enable DPD sample to trigger sampling pads data and direction
98 * in which pad will be driven during lp0 mode*/
99 writel(0x1, pmc + PMC_DPD_SAMPLE);
100
101 writel(wake_enb, pmc + PMC_WAKE_MASK);
102} 88}
103 89
104static void tegra_mask(struct irq_data *d) 90static void tegra_ack(struct irq_data *d)
105{ 91{
106 tegra_gic_mask_irq(d); 92 if (d->irq < FIRST_LEGACY_IRQ)
107 tegra_legacy_mask_irq(d->irq); 93 return;
108}
109 94
110static void tegra_unmask(struct irq_data *d) 95 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
111{
112 tegra_gic_unmask_irq(d);
113 tegra_legacy_unmask_irq(d->irq);
114} 96}
115 97
116static void tegra_ack(struct irq_data *d) 98static void tegra_eoi(struct irq_data *d)
117{ 99{
118 tegra_legacy_force_irq_clr(d->irq); 100 if (d->irq < FIRST_LEGACY_IRQ)
119 tegra_gic_ack_irq(d); 101 return;
102
103 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
120} 104}
121 105
122static int tegra_retrigger(struct irq_data *d) 106static int tegra_retrigger(struct irq_data *d)
123{ 107{
124 tegra_legacy_force_irq_set(d->irq); 108 if (d->irq < FIRST_LEGACY_IRQ)
109 return 0;
110
111 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
112
125 return 1; 113 return 1;
126} 114}
127 115
128static struct irq_chip tegra_irq = {
129 .name = "PPI",
130 .irq_ack = tegra_ack,
131 .irq_mask = tegra_mask,
132 .irq_unmask = tegra_unmask,
133 .irq_retrigger = tegra_retrigger,
134};
135
136void __init tegra_init_irq(void) 116void __init tegra_init_irq(void)
137{ 117{
138 struct irq_chip *gic; 118 int i;
139 unsigned int i;
140 int irq;
141 119
142 tegra_init_legacy_irq(); 120 for (i = 0; i < NUM_ICTLRS; i++) {
121 void __iomem *ictlr = ictlr_reg_base[i];
122 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
123 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
124 }
125
126 gic_arch_extn.irq_ack = tegra_ack;
127 gic_arch_extn.irq_eoi = tegra_eoi;
128 gic_arch_extn.irq_mask = tegra_mask;
129 gic_arch_extn.irq_unmask = tegra_unmask;
130 gic_arch_extn.irq_retrigger = tegra_retrigger;
143 131
144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 132 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 133 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
146
147 gic = irq_get_chip(29);
148 tegra_gic_unmask_irq = gic->irq_unmask;
149 tegra_gic_mask_irq = gic->irq_mask;
150 tegra_gic_ack_irq = gic->irq_ack;
151#ifdef CONFIG_SMP
152 tegra_irq.irq_set_affinity = gic->irq_set_affinity;
153#endif
154
155 for (i = 0; i < INT_MAIN_NR; i++) {
156 irq = INT_PRI_BASE + i;
157 irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
158 set_irq_flags(irq, IRQF_VALID);
159 }
160} 134}
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
deleted file mode 100644
index 38eb719a4f53..000000000000
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * arch/arm/mach-tegra/legacy_irq.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <mach/iomap.h>
21#include <mach/irqs.h>
22#include <mach/legacy_irq.h>
23
24#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
25#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
26#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
27
28#define ICTLR_CPU_IEP_VFIQ 0x08
29#define ICTLR_CPU_IEP_FIR 0x14
30#define ICTLR_CPU_IEP_FIR_SET 0x18
31#define ICTLR_CPU_IEP_FIR_CLR 0x1c
32
33#define ICTLR_CPU_IER 0x20
34#define ICTLR_CPU_IER_SET 0x24
35#define ICTLR_CPU_IER_CLR 0x28
36#define ICTLR_CPU_IEP_CLASS 0x2C
37
38#define ICTLR_COP_IER 0x30
39#define ICTLR_COP_IER_SET 0x34
40#define ICTLR_COP_IER_CLR 0x38
41#define ICTLR_COP_IEP_CLASS 0x3c
42
43#define NUM_ICTLRS 4
44
45static void __iomem *ictlr_reg_base[] = {
46 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
47 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
48 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
49 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
50};
51
52static u32 tegra_legacy_wake_mask[4];
53static u32 tegra_legacy_saved_mask[4];
54
55/* When going into deep sleep, the CPU is powered down, taking the GIC with it
56 In order to wake, the wake interrupts need to be enabled in the legacy
57 interrupt controller. */
58void tegra_legacy_unmask_irq(unsigned int irq)
59{
60 void __iomem *base;
61 pr_debug("%s: %d\n", __func__, irq);
62
63 irq -= 32;
64 base = ictlr_reg_base[irq>>5];
65 writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
66}
67
68void tegra_legacy_mask_irq(unsigned int irq)
69{
70 void __iomem *base;
71 pr_debug("%s: %d\n", __func__, irq);
72
73 irq -= 32;
74 base = ictlr_reg_base[irq>>5];
75 writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
76}
77
78void tegra_legacy_force_irq_set(unsigned int irq)
79{
80 void __iomem *base;
81 pr_debug("%s: %d\n", __func__, irq);
82
83 irq -= 32;
84 base = ictlr_reg_base[irq>>5];
85 writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
86}
87
88void tegra_legacy_force_irq_clr(unsigned int irq)
89{
90 void __iomem *base;
91 pr_debug("%s: %d\n", __func__, irq);
92
93 irq -= 32;
94 base = ictlr_reg_base[irq>>5];
95 writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
96}
97
98int tegra_legacy_force_irq_status(unsigned int irq)
99{
100 void __iomem *base;
101 pr_debug("%s: %d\n", __func__, irq);
102
103 irq -= 32;
104 base = ictlr_reg_base[irq>>5];
105 return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
106}
107
108void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
109{
110 void __iomem *base;
111 pr_debug("%s: %d\n", __func__, irq);
112
113 irq -= 32;
114 base = ictlr_reg_base[irq>>5];
115 writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
116}
117
118unsigned long tegra_legacy_vfiq(int nr)
119{
120 void __iomem *base;
121 base = ictlr_reg_base[nr];
122 return readl(base + ICTLR_CPU_IEP_VFIQ);
123}
124
125unsigned long tegra_legacy_class(int nr)
126{
127 void __iomem *base;
128 base = ictlr_reg_base[nr];
129 return readl(base + ICTLR_CPU_IEP_CLASS);
130}
131
132int tegra_legacy_irq_set_wake(int irq, int enable)
133{
134 irq -= 32;
135 if (enable)
136 tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31);
137 else
138 tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31));
139
140 return 0;
141}
142
143void tegra_legacy_irq_set_lp1_wake_mask(void)
144{
145 void __iomem *base;
146 int i;
147
148 for (i = 0; i < NUM_ICTLRS; i++) {
149 base = ictlr_reg_base[i];
150 tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER);
151 writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER);
152 }
153}
154
155void tegra_legacy_irq_restore_mask(void)
156{
157 void __iomem *base;
158 int i;
159
160 for (i = 0; i < NUM_ICTLRS; i++) {
161 base = ictlr_reg_base[i];
162 writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER);
163 }
164}
165
166void tegra_init_legacy_irq(void)
167{
168 int i;
169
170 for (i = 0; i < NUM_ICTLRS; i++) {
171 void __iomem *ictlr = ictlr_reg_base[i];
172 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
173 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
174 }
175}
176
177#ifdef CONFIG_PM
178static u32 cop_ier[NUM_ICTLRS];
179static u32 cpu_ier[NUM_ICTLRS];
180static u32 cpu_iep[NUM_ICTLRS];
181
182void tegra_irq_suspend(void)
183{
184 unsigned long flags;
185 int i;
186
187 local_irq_save(flags);
188 for (i = 0; i < NUM_ICTLRS; i++) {
189 void __iomem *ictlr = ictlr_reg_base[i];
190 cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
191 cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
192 cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
193 writel(~0, ictlr + ICTLR_COP_IER_CLR);
194 }
195 local_irq_restore(flags);
196}
197
198void tegra_irq_resume(void)
199{
200 unsigned long flags;
201 int i;
202
203 local_irq_save(flags);
204 for (i = 0; i < NUM_ICTLRS; i++) {
205 void __iomem *ictlr = ictlr_reg_base[i];
206 writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
207 writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
208 writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
209 writel(0, ictlr + ICTLR_COP_IEP_CLASS);
210 writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
211 writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
212 }
213 local_irq_restore(flags);
214}
215#endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index ec1f68924edf..b8ae3c978dee 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <asm/hardware/gic.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
@@ -122,6 +123,8 @@ void __init smp_init_cpus(void)
122 123
123 for (i = 0; i < ncores; i++) 124 for (i = 0; i < ncores; i++)
124 cpu_set(i, cpu_possible_map); 125 cpu_set(i, cpu_possible_map);
126
127 set_smp_cross_call(gic_raise_softirq);
125} 128}
126 129
127void __init platform_smp_prepare_cpus(unsigned int max_cpus) 130void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 0fcb1eb4214d..90350420c4e9 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -98,11 +98,6 @@ static void tegra_timer_set_mode(enum clock_event_mode mode,
98 } 98 }
99} 99}
100 100
101static cycle_t tegra_clocksource_read(struct clocksource *cs)
102{
103 return timer_readl(TIMERUS_CNTR_1US);
104}
105
106static struct clock_event_device tegra_clockevent = { 101static struct clock_event_device tegra_clockevent = {
107 .name = "timer0", 102 .name = "timer0",
108 .rating = 300, 103 .rating = 300,
@@ -111,14 +106,6 @@ static struct clock_event_device tegra_clockevent = {
111 .set_mode = tegra_timer_set_mode, 106 .set_mode = tegra_timer_set_mode,
112}; 107};
113 108
114static struct clocksource tegra_clocksource = {
115 .name = "timer_us",
116 .rating = 300,
117 .read = tegra_clocksource_read,
118 .mask = CLOCKSOURCE_MASK(32),
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
120};
121
122static DEFINE_CLOCK_DATA(cd); 109static DEFINE_CLOCK_DATA(cd);
123 110
124/* 111/*
@@ -234,7 +221,8 @@ static void __init tegra_init_timer(void)
234 init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, 221 init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
235 1000000, SC_MULT, SC_SHIFT); 222 1000000, SC_MULT, SC_SHIFT);
236 223
237 if (clocksource_register_hz(&tegra_clocksource, 1000000)) { 224 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
225 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
238 printk(KERN_ERR "Failed to register clocksource\n"); 226 printk(KERN_ERR "Failed to register clocksource\n");
239 BUG(); 227 BUG();
240 } 228 }
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 3ec58bd2d6e4..891cf44591e0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -333,20 +333,6 @@ static struct irqaction u300_timer_irq = {
333 .handler = u300_timer_interrupt, 333 .handler = u300_timer_interrupt,
334}; 334};
335 335
336/* Use general purpose timer 2 as clock source */
337static cycle_t u300_get_cycles(struct clocksource *cs)
338{
339 return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
340}
341
342static struct clocksource clocksource_u300_1mhz = {
343 .name = "GPT2",
344 .rating = 300, /* Reasonably fast and accurate clock source */
345 .read = u300_get_cycles,
346 .mask = CLOCKSOURCE_MASK(32), /* 32 bits */
347 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
348};
349
350/* 336/*
351 * Override the global weak sched_clock symbol with this 337 * Override the global weak sched_clock symbol with this
352 * local implementation which uses the clocksource to get some 338 * local implementation which uses the clocksource to get some
@@ -422,7 +408,9 @@ static void __init u300_timer_init(void)
422 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, 408 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
423 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); 409 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
424 410
425 if (clocksource_register_hz(&clocksource_u300_1mhz, rate)) 411 /* Use general purpose timer 2 as clock source */
412 if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
413 "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
426 printk(KERN_ERR "timer: failed to initialize clock " 414 printk(KERN_ERR "timer: failed to initialize clock "
427 "source %s\n", clocksource_u300_1mhz.name); 415 "source %s\n", clocksource_u300_1mhz.name);
428 416
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
deleted file mode 100644
index ca2b15b1b3b1..000000000000
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is based ARM realview platform.
3 * Copyright (C) ARM Limited.
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9#ifndef ASMARM_ARCH_SMP_H
10#define ASMARM_ARCH_SMP_H
11
12#include <asm/hardware/gic.h>
13
14/* This is required to wakeup the secondary core */
15extern void u8500_secondary_startup(void);
16
17/*
18 * We use IRQ1 as the IPI
19 */
20static inline void smp_cross_call(const struct cpumask *mask, int ipi)
21{
22 gic_raise_softirq(mask, ipi);
23}
24#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index ab0fe1432fae..088b550c40df 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -24,7 +24,7 @@
24#include <linux/amba/serial.h> 24#include <linux/amba/serial.h>
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27static u32 ux500_uart_base; 27u32 ux500_uart_base;
28 28
29static void putc(const char c) 29static void putc(const char c)
30{ 30{
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 4fff4d408417..0c527fe2cebb 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -18,10 +18,14 @@
18#include <linux/io.h> 18#include <linux/io.h>
19 19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/hardware/gic.h>
21#include <asm/smp_scu.h> 22#include <asm/smp_scu.h>
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23#include <mach/setup.h> 24#include <mach/setup.h>
24 25
26/* This is called from headsmp.S to wakeup the secondary core */
27extern void u8500_secondary_startup(void);
28
25/* 29/*
26 * control for which core is the next to come out of the secondary 30 * control for which core is the next to come out of the secondary
27 * boot "holding pen" 31 * boot "holding pen"
@@ -94,7 +98,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
94 */ 98 */
95 write_pen_release(cpu); 99 write_pen_release(cpu);
96 100
97 smp_cross_call(cpumask_of(cpu), 1); 101 gic_raise_softirq(cpumask_of(cpu), 1);
98 102
99 timeout = jiffies + (1 * HZ); 103 timeout = jiffies + (1 * HZ);
100 while (time_before(jiffies, timeout)) { 104 while (time_before(jiffies, timeout)) {
@@ -162,6 +166,8 @@ void __init smp_init_cpus(void)
162 166
163 for (i = 0; i < ncores; i++) 167 for (i = 0; i < ncores; i++)
164 set_cpu_possible(i, true); 168 set_cpu_possible(i, true);
169
170 set_smp_cross_call(gic_raise_softirq);
165} 171}
166 172
167void __init platform_smp_prepare_cpus(unsigned int max_cpus) 173void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index eb7ffa0ee8b5..0c99cf076c63 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -32,6 +32,7 @@
32#include <linux/io.h> 32#include <linux/io.h>
33#include <linux/gfp.h> 33#include <linux/gfp.h>
34#include <linux/clkdev.h> 34#include <linux/clkdev.h>
35#include <linux/mtd/physmap.h>
35 36
36#include <asm/system.h> 37#include <asm/system.h>
37#include <asm/irq.h> 38#include <asm/irq.h>
@@ -42,7 +43,6 @@
42#include <asm/mach-types.h> 43#include <asm/mach-types.h>
43 44
44#include <asm/mach/arch.h> 45#include <asm/mach/arch.h>
45#include <asm/mach/flash.h>
46#include <asm/mach/irq.h> 46#include <asm/mach/irq.h>
47#include <asm/mach/time.h> 47#include <asm/mach/time.h>
48#include <asm/mach/map.h> 48#include <asm/mach/map.h>
@@ -190,27 +190,7 @@ void __init versatile_map_io(void)
190 190
191#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) 191#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
192 192
193static int versatile_flash_init(void) 193static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
194{
195 u32 val;
196
197 val = __raw_readl(VERSATILE_FLASHCTRL);
198 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
199 __raw_writel(val, VERSATILE_FLASHCTRL);
200
201 return 0;
202}
203
204static void versatile_flash_exit(void)
205{
206 u32 val;
207
208 val = __raw_readl(VERSATILE_FLASHCTRL);
209 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
210 __raw_writel(val, VERSATILE_FLASHCTRL);
211}
212
213static void versatile_flash_set_vpp(int on)
214{ 194{
215 u32 val; 195 u32 val;
216 196
@@ -222,11 +202,8 @@ static void versatile_flash_set_vpp(int on)
222 __raw_writel(val, VERSATILE_FLASHCTRL); 202 __raw_writel(val, VERSATILE_FLASHCTRL);
223} 203}
224 204
225static struct flash_platform_data versatile_flash_data = { 205static struct physmap_flash_data versatile_flash_data = {
226 .map_name = "cfi_probe",
227 .width = 4, 206 .width = 4,
228 .init = versatile_flash_init,
229 .exit = versatile_flash_exit,
230 .set_vpp = versatile_flash_set_vpp, 207 .set_vpp = versatile_flash_set_vpp,
231}; 208};
232 209
@@ -237,7 +214,7 @@ static struct resource versatile_flash_resource = {
237}; 214};
238 215
239static struct platform_device versatile_flash_device = { 216static struct platform_device versatile_flash_device = {
240 .name = "armflash", 217 .name = "physmap-flash",
241 .id = 0, 218 .id = 0,
242 .dev = { 219 .dev = {
243 .platform_data = &versatile_flash_data, 220 .platform_data = &versatile_flash_data,
@@ -375,6 +352,10 @@ static struct clk ref24_clk = {
375 .rate = 24000000, 352 .rate = 24000000,
376}; 353};
377 354
355static struct clk sp804_clk = {
356 .rate = 1000000,
357};
358
378static struct clk dummy_apb_pclk; 359static struct clk dummy_apb_pclk;
379 360
380static struct clk_lookup lookups[] = { 361static struct clk_lookup lookups[] = {
@@ -411,7 +392,10 @@ static struct clk_lookup lookups[] = {
411 }, { /* CLCD */ 392 }, { /* CLCD */
412 .dev_id = "dev:20", 393 .dev_id = "dev:20",
413 .clk = &osc4_clk, 394 .clk = &osc4_clk,
414 } 395 }, { /* SP804 timers */
396 .dev_id = "sp804",
397 .clk = &sp804_clk,
398 },
415}; 399};
416 400
417/* 401/*
@@ -764,8 +748,8 @@ static void __init versatile_timer_init(void)
764 writel(0, TIMER2_VA_BASE + TIMER_CTRL); 748 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
765 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 749 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
766 750
767 sp804_clocksource_init(TIMER3_VA_BASE); 751 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
768 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1); 752 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
769} 753}
770 754
771struct sys_timer versatile_timer = { 755struct sys_timer versatile_timer = {
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index ebc22e759325..765a71ff7f3b 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -71,8 +71,9 @@ static void __init ct_ca9x4_timer_init(void)
71 writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL); 71 writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
72 writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL); 72 writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
73 73
74 sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1)); 74 sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
75 sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0); 75 sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
76 "ct-timer0");
76} 77}
77 78
78static struct sys_timer ct_ca9x4_timer = { 79static struct sys_timer ct_ca9x4_timer = {
@@ -141,10 +142,22 @@ static struct clk osc1_clk = {
141 .rate = 24000000, 142 .rate = 24000000,
142}; 143};
143 144
145static struct clk ct_sp804_clk = {
146 .rate = 1000000,
147};
148
144static struct clk_lookup lookups[] = { 149static struct clk_lookup lookups[] = {
145 { /* CLCD */ 150 { /* CLCD */
146 .dev_id = "ct:clcd", 151 .dev_id = "ct:clcd",
147 .clk = &osc1_clk, 152 .clk = &osc1_clk,
153 }, { /* SP804 timers */
154 .dev_id = "sp804",
155 .con_id = "ct-timer0",
156 .clk = &ct_sp804_clk,
157 }, { /* SP804 timers */
158 .dev_id = "sp804",
159 .con_id = "ct-timer1",
160 .clk = &ct_sp804_clk,
148 }, 161 },
149}; 162};
150 163
@@ -210,6 +223,8 @@ static void ct_ca9x4_init_cpu_map(void)
210 223
211 for (i = 0; i < ncores; ++i) 224 for (i = 0; i < ncores; ++i)
212 set_cpu_possible(i, true); 225 set_cpu_possible(i, true);
226
227 set_smp_cross_call(gic_raise_softirq);
213} 228}
214 229
215static void ct_ca9x4_smp_enable(unsigned int max_cpus) 230static void ct_ca9x4_smp_enable(unsigned int max_cpus)
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
deleted file mode 100644
index 4c05e4a9713a..000000000000
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __MACH_SMP_H
2#define __MACH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11 gic_raise_softirq(mask, ipi);
12}
13#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index ba46e8e07437..285edcd2da2a 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -13,11 +13,11 @@
13#include <linux/sysdev.h> 13#include <linux/sysdev.h>
14#include <linux/usb/isp1760.h> 14#include <linux/usb/isp1760.h>
15#include <linux/clkdev.h> 15#include <linux/clkdev.h>
16#include <linux/mtd/physmap.h>
16 17
17#include <asm/mach-types.h> 18#include <asm/mach-types.h>
18#include <asm/sizes.h> 19#include <asm/sizes.h>
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
20#include <asm/mach/flash.h>
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23#include <asm/hardware/arm_timer.h> 23#include <asm/hardware/arm_timer.h>
@@ -65,8 +65,9 @@ static void __init v2m_timer_init(void)
65 writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); 65 writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
66 writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); 66 writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
67 67
68 sp804_clocksource_init(MMIO_P2V(V2M_TIMER1)); 68 sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
69 sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0); 69 sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
70 "v2m-timer0");
70} 71}
71 72
72static struct sys_timer v2m_timer = { 73static struct sys_timer v2m_timer = {
@@ -206,27 +207,13 @@ static struct platform_device v2m_usb_device = {
206 .dev.platform_data = &v2m_usb_config, 207 .dev.platform_data = &v2m_usb_config,
207}; 208};
208 209
209static int v2m_flash_init(void) 210static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
210{
211 writel(0, MMIO_P2V(V2M_SYS_FLASH));
212 return 0;
213}
214
215static void v2m_flash_exit(void)
216{
217 writel(0, MMIO_P2V(V2M_SYS_FLASH));
218}
219
220static void v2m_flash_set_vpp(int on)
221{ 211{
222 writel(on != 0, MMIO_P2V(V2M_SYS_FLASH)); 212 writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
223} 213}
224 214
225static struct flash_platform_data v2m_flash_data = { 215static struct physmap_flash_data v2m_flash_data = {
226 .map_name = "cfi_probe",
227 .width = 4, 216 .width = 4,
228 .init = v2m_flash_init,
229 .exit = v2m_flash_exit,
230 .set_vpp = v2m_flash_set_vpp, 217 .set_vpp = v2m_flash_set_vpp,
231}; 218};
232 219
@@ -243,7 +230,7 @@ static struct resource v2m_flash_resources[] = {
243}; 230};
244 231
245static struct platform_device v2m_flash_device = { 232static struct platform_device v2m_flash_device = {
246 .name = "armflash", 233 .name = "physmap-flash",
247 .id = -1, 234 .id = -1,
248 .resource = v2m_flash_resources, 235 .resource = v2m_flash_resources,
249 .num_resources = ARRAY_SIZE(v2m_flash_resources), 236 .num_resources = ARRAY_SIZE(v2m_flash_resources),
@@ -333,6 +320,10 @@ static struct clk osc2_clk = {
333 .rate = 24000000, 320 .rate = 24000000,
334}; 321};
335 322
323static struct clk v2m_sp804_clk = {
324 .rate = 1000000,
325};
326
336static struct clk dummy_apb_pclk; 327static struct clk dummy_apb_pclk;
337 328
338static struct clk_lookup v2m_lookups[] = { 329static struct clk_lookup v2m_lookups[] = {
@@ -363,6 +354,14 @@ static struct clk_lookup v2m_lookups[] = {
363 }, { /* CLCD */ 354 }, { /* CLCD */
364 .dev_id = "mb:clcd", 355 .dev_id = "mb:clcd",
365 .clk = &osc1_clk, 356 .clk = &osc1_clk,
357 }, { /* SP804 timers */
358 .dev_id = "sp804",
359 .con_id = "v2m-timer0",
360 .clk = &v2m_sp804_clk,
361 }, { /* SP804 timers */
362 .dev_id = "sp804",
363 .con_id = "v2m-timer1",
364 .clk = &v2m_sp804_clk,
366 }, 365 },
367}; 366};
368 367
diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h
index 56f1a74d7016..03130212ace2 100644
--- a/arch/arm/mach-w90x900/include/mach/uncompress.h
+++ b/arch/arm/mach-w90x900/include/mach/uncompress.h
@@ -27,7 +27,7 @@
27#define arch_decomp_wdog() 27#define arch_decomp_wdog()
28 28
29#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) 29#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
30static volatile u32 * uart_base = (u32 *)UART0_PA; 30static volatile u32 * const uart_base = (u32 *)UART0_PA;
31 31
32static void putc(int ch) 32static void putc(int ch)
33{ 33{
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index 4b089cb930dc..a2c4e2d0a0d4 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -43,7 +43,6 @@
43#define PRESCALE 0x63 /* Divider = prescale + 1 */ 43#define PRESCALE 0x63 /* Divider = prescale + 1 */
44 44
45#define TDR_SHIFT 24 45#define TDR_SHIFT 24
46#define TDR_MASK ((1 << TDR_SHIFT) - 1)
47 46
48static unsigned int timer0_load; 47static unsigned int timer0_load;
49 48
@@ -143,19 +142,6 @@ static void __init nuc900_clockevents_init(void)
143 clockevents_register_device(&nuc900_clockevent_device); 142 clockevents_register_device(&nuc900_clockevent_device);
144} 143}
145 144
146static cycle_t nuc900_get_cycles(struct clocksource *cs)
147{
148 return (~__raw_readl(REG_TDR1)) & TDR_MASK;
149}
150
151static struct clocksource clocksource_nuc900 = {
152 .name = "nuc900-timer1",
153 .rating = 200,
154 .read = nuc900_get_cycles,
155 .mask = CLOCKSOURCE_MASK(TDR_SHIFT),
156 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
157};
158
159static void __init nuc900_clocksource_init(void) 145static void __init nuc900_clocksource_init(void)
160{ 146{
161 unsigned int val; 147 unsigned int val;
@@ -175,7 +161,8 @@ static void __init nuc900_clocksource_init(void)
175 val |= (COUNTEN | PERIOD | PRESCALE); 161 val |= (COUNTEN | PERIOD | PRESCALE);
176 __raw_writel(val, REG_TCSR1); 162 __raw_writel(val, REG_TCSR1);
177 163
178 clocksource_register_hz(&clocksource_nuc900, rate); 164 clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200,
165 TDR_SHIFT, clocksource_mmio_readl_down);
179} 166}
180 167
181static void __init nuc900_timer_init(void) 168static void __init nuc900_timer_init(void)
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 2b269c955524..1a8d4aa821be 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -253,8 +253,8 @@ void __sync_icache_dcache(pte_t pteval)
253 253
254 if (!test_and_set_bit(PG_dcache_clean, &page->flags)) 254 if (!test_and_set_bit(PG_dcache_clean, &page->flags))
255 __flush_dcache_page(mapping, page); 255 __flush_dcache_page(mapping, page);
256 /* pte_exec() already checked above for non-aliasing VIPT cache */ 256
257 if (cache_is_vipt_nonaliasing() || pte_exec(pteval)) 257 if (pte_exec(pteval))
258 __flush_icache_all(); 258 __flush_icache_all();
259} 259}
260#endif 260#endif
@@ -275,7 +275,8 @@ void __sync_icache_dcache(pte_t pteval)
275 * kernel cache lines for later. Otherwise, we assume we have 275 * kernel cache lines for later. Otherwise, we assume we have
276 * aliasing mappings. 276 * aliasing mappings.
277 * 277 *
278 * Note that we disable the lazy flush for SMP. 278 * Note that we disable the lazy flush for SMP configurations where
279 * the cache maintenance operations are not automatically broadcasted.
279 */ 280 */
280void flush_dcache_page(struct page *page) 281void flush_dcache_page(struct page *page)
281{ 282{
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index e591513bb53e..76f82ae44efb 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -201,6 +201,20 @@ static void __init arm_bootmem_init(unsigned long start_pfn,
201 } 201 }
202} 202}
203 203
204#ifdef CONFIG_ZONE_DMA
205static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole,
206 unsigned long dma_size)
207{
208 if (size[0] <= dma_size)
209 return;
210
211 size[ZONE_NORMAL] = size[0] - dma_size;
212 size[ZONE_DMA] = dma_size;
213 hole[ZONE_NORMAL] = hole[0];
214 hole[ZONE_DMA] = 0;
215}
216#endif
217
204static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, 218static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
205 unsigned long max_high) 219 unsigned long max_high)
206{ 220{
@@ -243,11 +257,18 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
243#endif 257#endif
244 } 258 }
245 259
260#ifdef ARM_DMA_ZONE_SIZE
261#ifndef CONFIG_ZONE_DMA
262#error ARM_DMA_ZONE_SIZE set but no DMA zone to limit allocations
263#endif
264
246 /* 265 /*
247 * Adjust the sizes according to any special requirements for 266 * Adjust the sizes according to any special requirements for
248 * this machine type. 267 * this machine type.
249 */ 268 */
250 arch_adjust_zones(zone_size, zhole_size); 269 arm_adjust_dma_zone(zone_size, zhole_size,
270 ARM_DMA_ZONE_SIZE >> PAGE_SHIFT);
271#endif
251 272
252 free_area_init_node(0, zone_size, min, zhole_size); 273 free_area_init_node(0, zone_size, min, zhole_size);
253} 274}
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7c99cb4c8e4f..ab17cc0d3fa7 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -175,11 +175,6 @@ cpu_v6_name:
175 .asciz "ARMv6-compatible processor" 175 .asciz "ARMv6-compatible processor"
176 .size cpu_v6_name, . - cpu_v6_name 176 .size cpu_v6_name, . - cpu_v6_name
177 177
178 .type cpu_pj4_name, #object
179cpu_pj4_name:
180 .asciz "Marvell PJ4 processor"
181 .size cpu_pj4_name, . - cpu_pj4_name
182
183 .align 178 .align
184 179
185 __CPUINIT 180 __CPUINIT
@@ -305,32 +300,3 @@ __v6_proc_info:
305 .long v6_user_fns 300 .long v6_user_fns
306 .long v6_cache_fns 301 .long v6_cache_fns
307 .size __v6_proc_info, . - __v6_proc_info 302 .size __v6_proc_info, . - __v6_proc_info
308
309 .type __pj4_v6_proc_info, #object
310__pj4_v6_proc_info:
311 .long 0x560f5810
312 .long 0xff0ffff0
313 ALT_SMP(.long \
314 PMD_TYPE_SECT | \
315 PMD_SECT_AP_WRITE | \
316 PMD_SECT_AP_READ | \
317 PMD_FLAGS_SMP)
318 ALT_UP(.long \
319 PMD_TYPE_SECT | \
320 PMD_SECT_AP_WRITE | \
321 PMD_SECT_AP_READ | \
322 PMD_FLAGS_UP)
323 .long PMD_TYPE_SECT | \
324 PMD_SECT_XN | \
325 PMD_SECT_AP_WRITE | \
326 PMD_SECT_AP_READ
327 b __v6_setup
328 .long cpu_arch_name
329 .long cpu_elf_name
330 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
331 .long cpu_pj4_name
332 .long v6_processor_functions
333 .long v6wbi_tlb_fns
334 .long v6_user_fns
335 .long v6_cache_fns
336 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index b0cb4258e382..a5353fc0793f 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,13 +4,18 @@ source "arch/arm/plat-mxc/devices/Kconfig"
4 4
5menu "Freescale MXC Implementations" 5menu "Freescale MXC Implementations"
6 6
7config ARCH_MX50_SUPPORTED
8 bool
9
10config ARCH_MX53_SUPPORTED
11 bool
12
7choice 13choice
8 prompt "Freescale CPU family:" 14 prompt "Freescale CPU family:"
9 default ARCH_MX3 15 default ARCH_MX3
10 16
11config ARCH_MX1 17config ARCH_MX1
12 bool "MX1-based" 18 bool "MX1-based"
13 select SOC_IMX1
14 help 19 help
15 This enables support for systems based on the Freescale i.MX1 family 20 This enables support for systems based on the Freescale i.MX1 family
16 21
@@ -26,29 +31,26 @@ config ARCH_MX25
26 31
27config ARCH_MX3 32config ARCH_MX3
28 bool "MX3-based" 33 bool "MX3-based"
29 select CPU_V6
30 help 34 help
31 This enables support for systems based on the Freescale i.MX3 family 35 This enables support for systems based on the Freescale i.MX3 family
32 36
33config ARCH_MXC91231 37config ARCH_MX503
34 bool "MXC91231-based" 38 bool "i.MX50 + i.MX53"
35 select CPU_V6 39 select ARCH_MX50_SUPPORTED
36 select MXC_AVIC 40 select ARCH_MX53_SUPPORTED
37 help 41 help
38 This enables support for systems based on the Freescale MXC91231 family 42 This enables support for machines using Freescale's i.MX50 and i.MX51
43 processors.
39 44
40config ARCH_MX5 45config ARCH_MX51
41 bool "MX5-based" 46 bool "i.MX51"
42 select CPU_V7 47 select ARCH_MX51_SUPPORTED
43 select ARM_L1_CACHE_SHIFT_6
44 help 48 help
45 This enables support for systems based on the Freescale i.MX51 family 49 This enables support for systems based on the Freescale i.MX51 family
46 50
47endchoice 51endchoice
48 52
49source "arch/arm/mach-imx/Kconfig" 53source "arch/arm/mach-imx/Kconfig"
50source "arch/arm/mach-mx3/Kconfig"
51source "arch/arm/mach-mxc91231/Kconfig"
52source "arch/arm/mach-mx5/Kconfig" 54source "arch/arm/mach-mx5/Kconfig"
53 55
54endmenu 56endmenu
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index b9ab1d58b5e7..bd294add932c 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -24,7 +24,6 @@ config IMX_HAVE_PLATFORM_IMXDI_RTC
24 24
25config IMX_HAVE_PLATFORM_IMX_FB 25config IMX_HAVE_PLATFORM_IMX_FB
26 bool 26 bool
27 select HAVE_FB_IMX
28 27
29config IMX_HAVE_PLATFORM_IMX_I2C 28config IMX_HAVE_PLATFORM_IMX_I2C
30 bool 29 bool
@@ -41,6 +40,9 @@ config IMX_HAVE_PLATFORM_IMX_UART
41config IMX_HAVE_PLATFORM_IMX_UDC 40config IMX_HAVE_PLATFORM_IMX_UDC
42 bool 41 bool
43 42
43config IMX_HAVE_PLATFORM_IPU_CORE
44 bool
45
44config IMX_HAVE_PLATFORM_MX1_CAMERA 46config IMX_HAVE_PLATFORM_MX1_CAMERA
45 bool 47 bool
46 48
@@ -63,6 +65,9 @@ config IMX_HAVE_PLATFORM_MXC_RNGA
63 bool 65 bool
64 select ARCH_HAS_RNGA 66 select ARCH_HAS_RNGA
65 67
68config IMX_HAVE_PLATFORM_MXC_RTC
69 bool
70
66config IMX_HAVE_PLATFORM_MXC_W1 71config IMX_HAVE_PLATFORM_MXC_W1
67 bool 72 bool
68 73
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 75cd2ece9053..ad2922acf480 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
12obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o 12obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
13obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o 13obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
14obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o 14obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
15obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
15obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o 16obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
16obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o 17obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
17obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o 18obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
19obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o 20obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
20obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o 21obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
21obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o 22obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
23obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
22obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o 24obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
23obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o 25obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
24obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o 26obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c
new file mode 100644
index 000000000000..edf65034aea5
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2011 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_ipu_core_entry_single(soc) \
13{ \
14 .iobase = soc ## _IPU_CTRL_BASE_ADDR, \
15 .synirq = soc ## _INT_IPU_SYN, \
16 .errirq = soc ## _INT_IPU_ERR, \
17}
18
19#ifdef CONFIG_SOC_IMX31
20const struct imx_ipu_core_data imx31_ipu_core_data __initconst =
21 imx_ipu_core_entry_single(MX31);
22#endif
23
24#ifdef CONFIG_SOC_IMX35
25const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
26 imx_ipu_core_entry_single(MX35);
27#endif
28
29static struct platform_device *imx_ipu_coredev __initdata;
30
31struct platform_device *__init imx_add_ipu_core(
32 const struct imx_ipu_core_data *data,
33 const struct ipu_platform_data *pdata)
34{
35 /* The resource order is important! */
36 struct resource res[] = {
37 {
38 .start = data->iobase,
39 .end = data->iobase + 0x5f,
40 .flags = IORESOURCE_MEM,
41 }, {
42 .start = data->iobase + 0x88,
43 .end = data->iobase + 0xb3,
44 .flags = IORESOURCE_MEM,
45 }, {
46 .start = data->synirq,
47 .end = data->synirq,
48 .flags = IORESOURCE_IRQ,
49 }, {
50 .start = data->errirq,
51 .end = data->errirq,
52 .flags = IORESOURCE_IRQ,
53 },
54 };
55
56 return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
57 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
58}
59
60struct platform_device *__init imx_alloc_mx3_camera(
61 const struct imx_ipu_core_data *data,
62 const struct mx3_camera_pdata *pdata)
63{
64 struct resource res[] = {
65 {
66 .start = data->iobase + 0x60,
67 .end = data->iobase + 0x87,
68 .flags = IORESOURCE_MEM,
69 },
70 };
71 int ret = -ENOMEM;
72 struct platform_device *pdev;
73
74 if (IS_ERR_OR_NULL(imx_ipu_coredev))
75 return ERR_PTR(-ENODEV);
76
77 pdev = platform_device_alloc("mx3-camera", 0);
78 if (!pdev)
79 goto err;
80
81 pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
82 if (!pdev->dev.dma_mask)
83 goto err;
84
85 *pdev->dev.dma_mask = DMA_BIT_MASK(32);
86 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
87
88 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
89 if (ret)
90 goto err;
91
92 if (pdata) {
93 struct mx3_camera_pdata *copied_pdata;
94
95 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
96 if (ret) {
97err:
98 kfree(pdev->dev.dma_mask);
99 platform_device_put(pdev);
100 return ERR_PTR(-ENODEV);
101 }
102 copied_pdata = dev_get_platdata(&pdev->dev);
103 copied_pdata->dma_dev = &imx_ipu_coredev->dev;
104 }
105
106 return pdev;
107}
108
109struct platform_device *__init imx_add_mx3_sdc_fb(
110 const struct imx_ipu_core_data *data,
111 struct mx3fb_platform_data *pdata)
112{
113 struct resource res[] = {
114 {
115 .start = data->iobase + 0xb4,
116 .end = data->iobase + 0x1bf,
117 .flags = IORESOURCE_MEM,
118 },
119 };
120
121 if (IS_ERR_OR_NULL(imx_ipu_coredev))
122 return ERR_PTR(-ENODEV);
123
124 pdata->dma_dev = &imx_ipu_coredev->dev;
125
126 return imx_add_platform_device_dmamask("mx3_sdc_fb", -1,
127 res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
128 DMA_BIT_MASK(32));
129}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
new file mode 100644
index 000000000000..16d0ec4df5f6
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2010-2011 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_rtc_data_entry_single(soc) \
13 { \
14 .iobase = soc ## _RTC_BASE_ADDR, \
15 .irq = soc ## _INT_RTC, \
16 }
17
18#ifdef CONFIG_SOC_IMX31
19const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
20 imx_mxc_rtc_data_entry_single(MX31);
21#endif /* ifdef CONFIG_SOC_IMX31 */
22
23struct platform_device *__init imx_add_mxc_rtc(
24 const struct imx_mxc_rtc_data *data)
25{
26 struct resource res[] = {
27 {
28 .start = data->iobase,
29 .end = data->iobase + SZ_16K - 1,
30 .flags = IORESOURCE_MEM,
31 }, {
32 .start = data->irq,
33 .end = data->irq,
34 .flags = IORESOURCE_IRQ,
35 },
36 };
37
38 return imx_add_platform_device("mxc_rtc", -1,
39 res, ARRAY_SIZE(res), NULL, 0);
40}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index f4a60ab6763b..f97eb3615b2c 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -80,7 +80,7 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
80 80
81#ifdef CONFIG_SOC_IMX51 81#ifdef CONFIG_SOC_IMX51
82const struct imx_spi_imx_data imx51_cspi_data __initconst = 82const struct imx_spi_imx_data imx51_cspi_data __initconst =
83 imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); 83 imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K);
84 84
85const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { 85const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
86#define imx51_ecspi_data_entry(_id, _hwid) \ 86#define imx51_ecspi_data_entry(_id, _hwid) \
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index d69d343ff61f..d3467f818c33 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -83,26 +83,12 @@ static void epit_irq_acknowledge(void)
83 __raw_writel(EPITSR_OCIF, timer_base + EPITSR); 83 __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
84} 84}
85 85
86static cycle_t epit_read(struct clocksource *cs)
87{
88 return 0 - __raw_readl(timer_base + EPITCNR);
89}
90
91static struct clocksource clocksource_epit = {
92 .name = "epit",
93 .rating = 200,
94 .read = epit_read,
95 .mask = CLOCKSOURCE_MASK(32),
96 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
97};
98
99static int __init epit_clocksource_init(struct clk *timer_clk) 86static int __init epit_clocksource_init(struct clk *timer_clk)
100{ 87{
101 unsigned int c = clk_get_rate(timer_clk); 88 unsigned int c = clk_get_rate(timer_clk);
102 89
103 clocksource_register_hz(&clocksource_epit, c); 90 return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32,
104 91 clocksource_mmio_readl_down);
105 return 0;
106} 92}
107 93
108/* clock event */ 94/* clock event */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a22ebe11a602..da7991832af6 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -23,7 +23,6 @@ extern void mx35_map_io(void);
23extern void mx50_map_io(void); 23extern void mx50_map_io(void);
24extern void mx51_map_io(void); 24extern void mx51_map_io(void);
25extern void mx53_map_io(void); 25extern void mx53_map_io(void);
26extern void mxc91231_map_io(void);
27extern void imx1_init_early(void); 26extern void imx1_init_early(void);
28extern void imx21_init_early(void); 27extern void imx21_init_early(void);
29extern void imx25_init_early(void); 28extern void imx25_init_early(void);
@@ -33,7 +32,6 @@ extern void imx35_init_early(void);
33extern void imx50_init_early(void); 32extern void imx50_init_early(void);
34extern void imx51_init_early(void); 33extern void imx51_init_early(void);
35extern void imx53_init_early(void); 34extern void imx53_init_early(void);
36extern void mxc91231_init_early(void);
37extern void mxc_init_irq(void __iomem *); 35extern void mxc_init_irq(void __iomem *);
38extern void tzic_init_irq(void __iomem *); 36extern void tzic_init_irq(void __iomem *);
39extern void mx1_init_irq(void); 37extern void mx1_init_irq(void);
@@ -45,7 +43,6 @@ extern void mx35_init_irq(void);
45extern void mx50_init_irq(void); 43extern void mx50_init_irq(void);
46extern void mx51_init_irq(void); 44extern void mx51_init_irq(void);
47extern void mx53_init_irq(void); 45extern void mx53_init_irq(void);
48extern void mxc91231_init_irq(void);
49extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); 46extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
50extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 47extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
51extern int mx1_clocks_init(unsigned long fref); 48extern int mx1_clocks_init(unsigned long fref);
@@ -58,14 +55,11 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
58 unsigned long ckih1, unsigned long ckih2); 55 unsigned long ckih1, unsigned long ckih2);
59extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 56extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
60 unsigned long ckih1, unsigned long ckih2); 57 unsigned long ckih1, unsigned long ckih2);
61extern int mxc91231_clocks_init(unsigned long fref);
62extern int mxc_register_gpios(void); 58extern int mxc_register_gpios(void);
63extern int mxc_register_device(struct platform_device *pdev, void *data); 59extern int mxc_register_device(struct platform_device *pdev, void *data);
64extern void mxc_set_cpu_type(unsigned int type); 60extern void mxc_set_cpu_type(unsigned int type);
65extern void mxc_arch_reset_init(void __iomem *); 61extern void mxc_arch_reset_init(void __iomem *);
66extern void mxc91231_power_off(void);
67extern void mxc91231_arch_reset(int, const char *);
68extern void mxc91231_prepare_idle(void);
69extern void mx51_efikamx_reset(void); 62extern void mx51_efikamx_reset(void);
70extern int mx53_revision(void); 63extern int mx53_revision(void);
64extern int mx53_display_revision(void);
71#endif 65#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 3b3a37c25c56..8e8d175e5077 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -44,13 +44,6 @@
44#define UART_PADDR MX51_UART1_BASE_ADDR 44#define UART_PADDR MX51_UART1_BASE_ADDR
45#endif 45#endif
46 46
47#ifdef CONFIG_ARCH_MXC91231
48#ifdef UART_PADDR
49#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
50#endif
51#define UART_PADDR MXC91231_UART2_BASE_ADDR
52#endif
53
54#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) 47#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
55 48
56 .macro addruart, rp, rv 49 .macro addruart, rp, rv
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8658c9caa650..fa8477337f91 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -166,6 +166,24 @@ struct platform_device *__init imx_add_imx_udc(
166 const struct imx_imx_udc_data *data, 166 const struct imx_imx_udc_data *data,
167 const struct imxusb_platform_data *pdata); 167 const struct imxusb_platform_data *pdata);
168 168
169#include <mach/ipu.h>
170#include <mach/mx3fb.h>
171#include <mach/mx3_camera.h>
172struct imx_ipu_core_data {
173 resource_size_t iobase;
174 resource_size_t synirq;
175 resource_size_t errirq;
176};
177struct platform_device *__init imx_add_ipu_core(
178 const struct imx_ipu_core_data *data,
179 const struct ipu_platform_data *pdata);
180struct platform_device *__init imx_alloc_mx3_camera(
181 const struct imx_ipu_core_data *data,
182 const struct mx3_camera_pdata *pdata);
183struct platform_device *__init imx_add_mx3_sdc_fb(
184 const struct imx_ipu_core_data *data,
185 struct mx3fb_platform_data *pdata);
186
169#include <mach/mx1_camera.h> 187#include <mach/mx1_camera.h>
170struct imx_mx1_camera_data { 188struct imx_mx1_camera_data {
171 resource_size_t iobase; 189 resource_size_t iobase;
@@ -237,6 +255,15 @@ struct imx_mxc_pwm_data {
237struct platform_device *__init imx_add_mxc_pwm( 255struct platform_device *__init imx_add_mxc_pwm(
238 const struct imx_mxc_pwm_data *data); 256 const struct imx_mxc_pwm_data *data);
239 257
258/* mxc_rtc */
259struct imx_mxc_rtc_data {
260 resource_size_t iobase;
261 resource_size_t irq;
262};
263struct platform_device *__init imx_add_mxc_rtc(
264 const struct imx_mxc_rtc_data *data);
265
266/* mxc_w1 */
240struct imx_mxc_w1_data { 267struct imx_mxc_w1_data {
241 resource_size_t iobase; 268 resource_size_t iobase;
242}; 269};
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 26bb1bab4aeb..67d3e2bed065 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -86,15 +86,6 @@
86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
89 * mxc91231:
90 * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
91 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
92 * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
93 * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
94 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
95 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
96 * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
97 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
98 */ 89 */
99#define IMX_IO_P2V(x) ( \ 90#define IMX_IO_P2V(x) ( \
100 0xf4000000 + \ 91 0xf4000000 + \
@@ -104,6 +95,8 @@
104 95
105#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) 96#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
106 97
98#include <mach/mxc.h>
99
107#ifdef CONFIG_ARCH_MX5 100#ifdef CONFIG_ARCH_MX5
108#include <mach/mx50.h> 101#include <mach/mx50.h>
109#include <mach/mx51.h> 102#include <mach/mx51.h>
@@ -134,12 +127,6 @@
134# include <mach/mx25.h> 127# include <mach/mx25.h>
135#endif 128#endif
136 129
137#ifdef CONFIG_ARCH_MXC91231
138# include <mach/mxc91231.h>
139#endif
140
141#include <mach/mxc.h>
142
143#define imx_map_entry(soc, name, _type) { \ 130#define imx_map_entry(soc, name, _type) { \
144 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ 131 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
145 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ 132 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index b4f2de769466..4347a87d2bb0 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,19 +14,26 @@
14/* Allow IO space to be anywhere in the memory */ 14/* Allow IO space to be anywhere in the memory */
15#define IO_SPACE_LIMIT 0xffffffff 15#define IO_SPACE_LIMIT 0xffffffff
16 16
17#ifdef CONFIG_ARCH_MX3 17#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
18#define __arch_ioremap __mx3_ioremap 18#include <mach/hardware.h>
19
20#define __arch_ioremap __imx_ioremap
19#define __arch_iounmap __iounmap 21#define __arch_iounmap __iounmap
20 22
23#define addr_in_module(addr, mod) \
24 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
25
21static inline void __iomem * 26static inline void __iomem *
22__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) 27__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
23{ 28{
24 if (mtype == MT_DEVICE) { 29 if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
25 /* Access all peripherals below 0x80000000 as nonshared device 30 /*
26 * but leave l2cc alone. 31 * Access all peripherals below 0x80000000 as nonshared device
32 * on mx3, but leave l2cc alone. Otherwise cache corruptions
33 * can occur.
27 */ 34 */
28 if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || 35 if (phys_addr < 0x80000000 &&
29 (phys_addr >= 0x30000000 + SZ_1M))) 36 !addr_in_module(phys_addr, MX3x_L2CC))
30 mtype = MT_DEVICE_NONSHARED; 37 mtype = MT_DEVICE_NONSHARED;
31 } 38 }
32 39
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index d7f52c91f82e..2e5244de7ff5 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -89,13 +89,16 @@
89#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) 89#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
90 90
91#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) 91#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
92#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
92#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) 93#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
93 94
94#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL) 95#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
96#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
95#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL) 97#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
96#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL) 98#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
97 99
98#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL) 100#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
101#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
99#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) 102#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
100#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) 103#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
101 104
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
deleted file mode 100644
index bf28df0d58b7..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_IOMUX_MXC91231_H__
18#define __MACH_IOMUX_MXC91231_H__
19
20/*
21 * various IOMUX output functions
22 */
23
24#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
25#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
26#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
27#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
28#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
29#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
30#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
31#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
32#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
33#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
34#define IOMUX_ICONFIG_FUNC 2 /* used as function */
35#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
36#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
37
38#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
39#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
40#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
41#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
42
43/*
44 * setups a single pin:
45 * - reserves the pin so that it is not claimed by another driver
46 * - setups the iomux according to the configuration
47 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
48 */
49int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
50/*
51 * setups mutliple pins
52 * convenient way to call the above function with tables
53 */
54int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
55 const char *label);
56
57/*
58 * releases a single pin:
59 * - make it available for a future use by another driver
60 * - frees the GPIO if the pin was configured as GPIO
61 * - DOES NOT reconfigure the IOMUX in its reset state
62 */
63void mxc_iomux_release_pin(unsigned int pin_mode);
64/*
65 * releases multiple pins
66 * convenvient way to call the above function with tables
67 */
68void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
69
70#define MUX_SIDE_AP (0)
71#define MUX_SIDE_SP (1)
72
73#define MUX_SIDE_SHIFT (26)
74#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT)
75
76#define MUX_GPIO_PORT_SHIFT (23)
77#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT)
78
79#define MUX_GPIO_PIN_SHIFT (20)
80#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT)
81
82#define MUX_REG_SHIFT (15)
83#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT)
84
85#define MUX_FIELD_SHIFT (13)
86#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT)
87
88#define MUX_PADGRP_SHIFT (8)
89#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT)
90
91#define MUX_PIN_MASK (0xffffff << 8)
92
93#define GPIO_PORT_MAX (3)
94
95#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
96 (((side) << MUX_SIDE_SHIFT) | \
97 (gport << MUX_GPIO_PORT_SHIFT) | \
98 ((gpin) << MUX_GPIO_PIN_SHIFT) | \
99 ((ctlreg) << MUX_REG_SHIFT) | \
100 ((ctlfield) << MUX_FIELD_SHIFT) | \
101 ((padgrp) << MUX_PADGRP_SHIFT))
102
103#define MUX_MODE_OUT_SHIFT (4)
104#define MUX_MODE_IN_SHIFT (0)
105#define MUX_MODE_SHIFT (0)
106#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT)
107
108#define IOMUX_MODE(pin, mode) \
109 (pin | (mode << MUX_MODE_SHIFT))
110
111enum iomux_pins {
112 /* AP Side pins */
113 MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24),
114 MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24),
115 MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24),
116 MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24),
117 MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24),
118 MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24),
119 MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24),
120 MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28),
121 MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28),
122 MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28),
123 MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28),
124 MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9),
125 MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9),
126 MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9),
127 MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9),
128 MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9),
129 MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9),
130 MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9),
131 MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9),
132 MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28),
133 MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28),
134 MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28),
135 MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28),
136 MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28),
137 MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28),
138 MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28),
139 MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28),
140 MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28),
141 MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28),
142 MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28),
143 MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28),
144 MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28),
145 MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28),
146 MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28),
147 MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28),
148 MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28),
149 MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28),
150 MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28),
151 MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28),
152 MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28),
153 MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28),
154 MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28),
155 MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28),
156 MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28),
157 MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28),
158 MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28),
159 MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28),
160 MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28),
161 MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28),
162 MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28),
163 MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10),
164 MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10),
165 MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10),
166 MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10),
167 MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11),
168 MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11),
169 MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11),
170 MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11),
171 MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11),
172 MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21),
173 MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21),
174 MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21),
175 MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21),
176 MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21),
177 MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21),
178 MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21),
179 MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21),
180 MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21),
181 MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21),
182 MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21),
183 MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21),
184 MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21),
185 MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21),
186 MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12),
187 MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12),
188 MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9),
189 MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9),
190 MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9),
191 MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9),
192 MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9),
193 MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28),
194 MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28),
195 MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9),
196 MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9),
197 MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9),
198 MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22),
199 MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22),
200 MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22),
201 MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22),
202 MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23),
203 MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23),
204 MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23),
205 MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23),
206 MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28),
207 MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28),
208 MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28),
209 MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28),
210 MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10),
211 MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10),
212 MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10),
213 MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10),
214 MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11),
215 MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11),
216 MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11),
217
218 /* Shared pins */
219 MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28),
220 MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28),
221 MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28),
222 MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28),
223 MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28),
224 MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28),
225 MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28),
226 MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28),
227 MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28),
228 MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28),
229 MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28),
230 MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28),
231 MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28),
232 MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28),
233 MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28),
234 MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28),
235 MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25),
236 MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25),
237 MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25),
238 MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25),
239 MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25),
240 MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25),
241 MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26),
242 MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26),
243 MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26),
244 MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26),
245 MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28),
246 MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13),
247 MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13),
248 MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13),
249 MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13),
250 MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13),
251 MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26),
252 MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26),
253 MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28),
254 MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28),
255 MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28),
256 MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28),
257 MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28),
258 MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28),
259 MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28),
260};
261
262#define PIN_AP_MAX (104)
263#define PIN_SP_MAX (41)
264
265#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX)
266
267/*
268 * Convenience values for use with mxc_iomux_mode()
269 *
270 * Format here is MXC91231_PIN_(pin name)__(function)
271 */
272
273#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
274 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
275#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
276 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
277#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
278 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
279#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
280 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
281
282
283#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index a3d930d3e65d..35c89bcdf758 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -35,8 +35,6 @@
35#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_SOC_IMX51 36#elif defined CONFIG_SOC_IMX51
37#define MXC_GPIO_IRQS (32 * 4) 37#define MXC_GPIO_IRQS (32 * 4)
38#elif defined CONFIG_ARCH_MXC91231
39#define MXC_GPIO_IRQS (32 * 4)
40#elif defined CONFIG_ARCH_MX3 38#elif defined CONFIG_ARCH_MX3
41#define MXC_GPIO_IRQS (32 * 3) 39#define MXC_GPIO_IRQS (32 * 3)
42#endif 40#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 5d51cbb98893..11be5cdbdd1a 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -19,7 +19,6 @@
19#define MX50_PHYS_OFFSET UL(0x70000000) 19#define MX50_PHYS_OFFSET UL(0x70000000)
20#define MX51_PHYS_OFFSET UL(0x90000000) 20#define MX51_PHYS_OFFSET UL(0x90000000)
21#define MX53_PHYS_OFFSET UL(0x70000000) 21#define MX53_PHYS_OFFSET UL(0x70000000)
22#define MXC91231_PHYS_OFFSET UL(0x90000000)
23 22
24#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 23#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
25# if defined CONFIG_ARCH_MX1 24# if defined CONFIG_ARCH_MX1
@@ -32,8 +31,6 @@
32# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET 31# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET
33# elif defined CONFIG_ARCH_MX3 32# elif defined CONFIG_ARCH_MX3
34# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET 33# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MXC91231
36# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET
37# elif defined CONFIG_ARCH_MX50 34# elif defined CONFIG_ARCH_MX50
38# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET 35# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET
39# elif defined CONFIG_ARCH_MX51 36# elif defined CONFIG_ARCH_MX51
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index cbc43ad5ef48..1dc1c522601b 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -60,8 +60,8 @@
60#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) 60#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
61#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) 61#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
62#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) 62#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
63#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) 63#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
64#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) 64#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
65#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) 65#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
66#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) 66#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
67#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) 67#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index ace17864575e..9d2a1ef84de2 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -337,17 +337,4 @@
337#define MX53_INT_GPIO7_LOW 107 337#define MX53_INT_GPIO7_LOW 107
338#define MX53_INT_GPIO7_HIGH 108 338#define MX53_INT_GPIO7_HIGH 108
339 339
340/* silicon revisions specific to i.MX53 */
341#define MX53_CHIP_REV_1_0 0x10
342#define MX53_CHIP_REV_1_1 0x11
343#define MX53_CHIP_REV_1_2 0x12
344#define MX53_CHIP_REV_1_3 0x13
345#define MX53_CHIP_REV_2_0 0x20
346#define MX53_CHIP_REV_2_1 0x21
347#define MX53_CHIP_REV_2_2 0x22
348#define MX53_CHIP_REV_2_3 0x23
349#define MX53_CHIP_REV_3_0 0x30
350#define MX53_CHIP_REV_3_1 0x31
351#define MX53_CHIP_REV_3_2 0x32
352
353#endif /* ifndef __MACH_MX53_H__ */ 340#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 1aea818d9d31..4ac53ce97c24 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -35,7 +35,6 @@
35#define MXC_CPU_MX50 50 35#define MXC_CPU_MX50 50
36#define MXC_CPU_MX51 51 36#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53 37#define MXC_CPU_MX53 53
38#define MXC_CPU_MXC91231 91231
39 38
40#define IMX_CHIP_REVISION_1_0 0x10 39#define IMX_CHIP_REVISION_1_0 0x10
41#define IMX_CHIP_REVISION_1_1 0x11 40#define IMX_CHIP_REVISION_1_1 0x11
@@ -177,18 +176,6 @@ extern unsigned int __mxc_cpu_type;
177# define cpu_is_mx53() (0) 176# define cpu_is_mx53() (0)
178#endif 177#endif
179 178
180#ifdef CONFIG_ARCH_MXC91231
181# ifdef mxc_cpu_type
182# undef mxc_cpu_type
183# define mxc_cpu_type __mxc_cpu_type
184# else
185# define mxc_cpu_type MXC_CPU_MXC91231
186# endif
187# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231)
188#else
189# define cpu_is_mxc91231() (0)
190#endif
191
192#ifndef __ASSEMBLY__ 179#ifndef __ASSEMBLY__
193 180
194struct cpu_op { 181struct cpu_op {
@@ -207,14 +194,7 @@ enum mxc_cpu_pwr_mode {
207extern struct cpu_op *(*get_cpu_op)(int *op); 194extern struct cpu_op *(*get_cpu_op)(int *op);
208#endif 195#endif
209 196
210#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 197#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
211/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
212#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
213#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
214#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
215#endif
216
217#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
218#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) 198#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
219 199
220#endif /* __ASM_ARCH_MXC_H__ */ 200#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
deleted file mode 100644
index 765190fe6332..000000000000
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ /dev/null
@@ -1,256 +0,0 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * - Platform specific register memory map
4 *
5 * Copyright 2005-2007 Motorola, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#ifndef __MACH_MXC91231_H__
18#define __MACH_MXC91231_H__
19
20/*
21 * L2CC
22 */
23#define MXC91231_L2CC_BASE_ADDR 0x30000000
24#define MXC91231_L2CC_SIZE SZ_64K
25
26/*
27 * AIPS 1
28 */
29#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
30#define MXC91231_AIPS1_SIZE SZ_1M
31
32#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
33#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
34#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
35#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
36#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
37#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
38#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
39#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
40#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
41#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
42#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
43#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
44#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
45#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
46#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
47#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
48#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
49
50/*
51 * AIPS 2
52 */
53#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
54#define MXC91231_AIPS2_SIZE SZ_1M
55
56#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
57#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
58#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
59#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
60#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
61#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
62#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
63#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
64#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
65#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
66#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
67#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
68#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
69#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
70#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
71#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
72#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
73#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
74
75/*
76 * SPBA global module 0
77 */
78#define MXC91231_SPBA0_BASE_ADDR 0x50000000
79#define MXC91231_SPBA0_SIZE SZ_1M
80
81#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
82#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
83#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
84#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
85#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
86#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
87#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
88#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
89#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
90#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
91#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
92#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
93#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
94#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
95#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
96#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
97#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
98#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
99#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
100#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
101#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
102#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
103
104/*
105 * SPBA global module 1
106 */
107#define MXC91231_SPBA1_BASE_ADDR 0x52000000
108#define MXC91231_SPBA1_SIZE SZ_1M
109
110#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
111#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
112
113/*!
114 * Defines for SPBA modules
115 */
116#define MXC91231_SPBA_SDHC1 0x04
117#define MXC91231_SPBA_SDHC2 0x08
118#define MXC91231_SPBA_UART3 0x0C
119#define MXC91231_SPBA_CSPI2 0x10
120#define MXC91231_SPBA_SSI2 0x14
121#define MXC91231_SPBA_SIM 0x18
122#define MXC91231_SPBA_IIM 0x1C
123#define MXC91231_SPBA_CTI_SDMA 0x20
124#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
125#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
126#define MXC91231_SPBA_CSPI1 0x30
127#define MXC91231_SPBA_MQSPI 0x34
128#define MXC91231_SPBA_EL1T 0x38
129#define MXC91231_SPBA_IOMUX 0x40
130#define MXC91231_SPBA_CRM_COM 0x44
131#define MXC91231_SPBA_CRM_AP 0x48
132#define MXC91231_SPBA_PLL0 0x4C
133#define MXC91231_SPBA_PLL1 0x50
134#define MXC91231_SPBA_PLL2 0x54
135#define MXC91231_SPBA_GPIO4 0x58
136#define MXC91231_SPBA_SAHARA 0x5C
137
138/*
139 * ROMP and AVIC
140 */
141#define MXC91231_ROMP_BASE_ADDR 0x60000000
142#define MXC91231_ROMP_SIZE SZ_64K
143
144#define MXC91231_AVIC_BASE_ADDR 0x68000000
145#define MXC91231_AVIC_SIZE SZ_64K
146
147/*
148 * NAND, SDRAM, WEIM, M3IF, EMI controllers
149 */
150#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
151#define MXC91231_X_MEMC_SIZE SZ_64K
152
153#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
154#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
155#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
156#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
157#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
158
159/*
160 * Memory regions and CS
161 * CPLD is connected on CS4
162 * CS5 is TP1021 or it is not connected
163 * */
164#define MXC91231_FB_RAM_BASE_ADDR 0x78000000
165#define MXC91231_FB_RAM_SIZE SZ_256K
166#define MXC91231_CSD0_BASE_ADDR 0x80000000
167#define MXC91231_CSD1_BASE_ADDR 0x90000000
168#define MXC91231_CS0_BASE_ADDR 0xA0000000
169#define MXC91231_CS1_BASE_ADDR 0xA8000000
170#define MXC91231_CS2_BASE_ADDR 0xB0000000
171#define MXC91231_CS3_BASE_ADDR 0xB2000000
172#define MXC91231_CS4_BASE_ADDR 0xB4000000
173#define MXC91231_CS5_BASE_ADDR 0xB6000000
174
175/*
176 * This macro defines the physical to virtual address mapping for all the
177 * peripheral modules. It is used by passing in the physical address as x
178 * and returning the virtual address.
179 */
180#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
181#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
182
183/*
184 * Interrupt numbers
185 */
186#define MXC91231_INT_GPIO3 0
187#define MXC91231_INT_EL1T_CI 1
188#define MXC91231_INT_EL1T_RFCI 2
189#define MXC91231_INT_EL1T_RFI 3
190#define MXC91231_INT_EL1T_MCU 4
191#define MXC91231_INT_EL1T_IPI 5
192#define MXC91231_INT_MU_GEN 6
193#define MXC91231_INT_GPIO4 7
194#define MXC91231_INT_MMC_SDHC2 8
195#define MXC91231_INT_MMC_SDHC1 9
196#define MXC91231_INT_I2C 10
197#define MXC91231_INT_SSI2 11
198#define MXC91231_INT_SSI1 12
199#define MXC91231_INT_CSPI2 13
200#define MXC91231_INT_CSPI1 14
201#define MXC91231_INT_RTIC 15
202#define MXC91231_INT_SAHARA 15
203#define MXC91231_INT_HAC 15
204#define MXC91231_INT_UART3_RX 16
205#define MXC91231_INT_UART3_TX 17
206#define MXC91231_INT_UART3_MINT 18
207#define MXC91231_INT_ECT 19
208#define MXC91231_INT_SIM_IPB 20
209#define MXC91231_INT_SIM_DATA 21
210#define MXC91231_INT_RNGA 22
211#define MXC91231_INT_DSM_AP 23
212#define MXC91231_INT_KPP 24
213#define MXC91231_INT_RTC 25
214#define MXC91231_INT_PWM 26
215#define MXC91231_INT_GEMK_AP 27
216#define MXC91231_INT_EPIT 28
217#define MXC91231_INT_GPT 29
218#define MXC91231_INT_UART2_RX 30
219#define MXC91231_INT_UART2_TX 31
220#define MXC91231_INT_UART2_MINT 32
221#define MXC91231_INT_NANDFC 33
222#define MXC91231_INT_SDMA 34
223#define MXC91231_INT_USB_WAKEUP 35
224#define MXC91231_INT_USB_SOF 36
225#define MXC91231_INT_PMU_EVTMON 37
226#define MXC91231_INT_USB_FUNC 38
227#define MXC91231_INT_USB_DMA 39
228#define MXC91231_INT_USB_CTRL 40
229#define MXC91231_INT_IPU_ERR 41
230#define MXC91231_INT_IPU_SYN 42
231#define MXC91231_INT_UART1_RX 43
232#define MXC91231_INT_UART1_TX 44
233#define MXC91231_INT_UART1_MINT 45
234#define MXC91231_INT_IIM 46
235#define MXC91231_INT_MU_RX_OR 47
236#define MXC91231_INT_MU_TX_OR 48
237#define MXC91231_INT_SCC_SCM 49
238#define MXC91231_INT_SCC_SMN 50
239#define MXC91231_INT_GPIO2 51
240#define MXC91231_INT_GPIO1 52
241#define MXC91231_INT_MQSPI1 53
242#define MXC91231_INT_MQSPI2 54
243#define MXC91231_INT_WDOG2 55
244#define MXC91231_INT_EXT_INT7 56
245#define MXC91231_INT_EXT_INT6 57
246#define MXC91231_INT_EXT_INT5 58
247#define MXC91231_INT_EXT_INT4 59
248#define MXC91231_INT_EXT_INT3 60
249#define MXC91231_INT_EXT_INT2 61
250#define MXC91231_INT_EXT_INT1 62
251#define MXC91231_INT_EXT_INT0 63
252
253#define MXC91231_MAX_INT_LINES 63
254#define MXC91231_MAX_EXT_LINES 8
255
256#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 0417da9f710d..51f02a9d41a3 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -24,12 +24,6 @@ extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
24 24
25static inline void arch_idle(void) 25static inline void arch_idle(void)
26{ 26{
27#ifdef CONFIG_ARCH_MXC91231
28 if (cpu_is_mxc91231()) {
29 /* Need this to set DSM low-power mode */
30 mxc91231_prepare_idle();
31 }
32#endif
33 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ 27 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
34 if (cpu_is_mx31() || cpu_is_mx35()) { 28 if (cpu_is_mx31() || cpu_is_mx35()) {
35 unsigned long reg = 0; 29 unsigned long reg = 0;
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 2d9624697cc9..d61d5c74817c 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,8 +26,6 @@
26#define CLOCK_TICK_RATE 16000000 26#define CLOCK_TICK_RATE 16000000
27#elif defined CONFIG_ARCH_MX5 27#elif defined CONFIG_ARCH_MX5
28#define CLOCK_TICK_RATE 8000000 28#define CLOCK_TICK_RATE 8000000
29#elif defined CONFIG_ARCH_MXC91231
30#define CLOCK_TICK_RATE 13000000
31#endif 29#endif
32 30
33#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ 31#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 4864b0afd440..d85e2d1c0324 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -21,7 +21,7 @@
21 21
22#include <asm/mach-types.h> 22#include <asm/mach-types.h>
23 23
24static unsigned long uart_base; 24unsigned long uart_base;
25 25
26#define UART(x) (*(volatile unsigned long *)(uart_base + (x))) 26#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
27 27
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3455fc0575a6..8024f2ac177c 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -37,12 +37,6 @@ void arch_reset(char mode, const char *cmd)
37{ 37{
38 unsigned int wcr_enable; 38 unsigned int wcr_enable;
39 39
40#ifdef CONFIG_ARCH_MXC91231
41 if (cpu_is_mxc91231()) {
42 mxc91231_arch_reset(mode, cmd);
43 return;
44 }
45#endif
46#ifdef CONFIG_MACH_MX51_EFIKAMX 40#ifdef CONFIG_MACH_MX51_EFIKAMX
47 if (machine_is_mx51_efikamx()) { 41 if (machine_is_mx51_efikamx()) {
48 mx51_efikamx_reset(); 42 mx51_efikamx_reset();
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 2237ff8b434f..4b0fe285e83c 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -54,7 +54,7 @@
54#define MX2_TSTAT_CAPT (1 << 1) 54#define MX2_TSTAT_CAPT (1 << 1)
55#define MX2_TSTAT_COMP (1 << 0) 55#define MX2_TSTAT_COMP (1 << 0)
56 56
57/* MX31, MX35, MX25, MXC91231, MX5 */ 57/* MX31, MX35, MX25, MX5 */
58#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 58#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
59#define V2_TCTL_CLK_IPG (1 << 6) 59#define V2_TCTL_CLK_IPG (1 << 6)
60#define V2_TCTL_FRR (1 << 9) 60#define V2_TCTL_FRR (1 << 9)
@@ -106,56 +106,32 @@ static void gpt_irq_acknowledge(void)
106 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); 106 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
107} 107}
108 108
109static cycle_t dummy_get_cycles(struct clocksource *cs) 109static void __iomem *sched_clock_reg;
110{
111 return 0;
112}
113
114static cycle_t mx1_2_get_cycles(struct clocksource *cs)
115{
116 return __raw_readl(timer_base + MX1_2_TCN);
117}
118
119static cycle_t v2_get_cycles(struct clocksource *cs)
120{
121 return __raw_readl(timer_base + V2_TCN);
122}
123
124static struct clocksource clocksource_mxc = {
125 .name = "mxc_timer1",
126 .rating = 200,
127 .read = dummy_get_cycles,
128 .mask = CLOCKSOURCE_MASK(32),
129 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
130};
131 110
132static DEFINE_CLOCK_DATA(cd); 111static DEFINE_CLOCK_DATA(cd);
133unsigned long long notrace sched_clock(void) 112unsigned long long notrace sched_clock(void)
134{ 113{
135 cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); 114 cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
136 115
137 return cyc_to_sched_clock(&cd, cyc, (u32)~0); 116 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
138} 117}
139 118
140static void notrace mxc_update_sched_clock(void) 119static void notrace mxc_update_sched_clock(void)
141{ 120{
142 cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); 121 cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
143 update_sched_clock(&cd, cyc, (u32)~0); 122 update_sched_clock(&cd, cyc, (u32)~0);
144} 123}
145 124
146static int __init mxc_clocksource_init(struct clk *timer_clk) 125static int __init mxc_clocksource_init(struct clk *timer_clk)
147{ 126{
148 unsigned int c = clk_get_rate(timer_clk); 127 unsigned int c = clk_get_rate(timer_clk);
128 void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
149 129
150 if (timer_is_v2()) 130 sched_clock_reg = reg;
151 clocksource_mxc.read = v2_get_cycles;
152 else
153 clocksource_mxc.read = mx1_2_get_cycles;
154 131
155 init_sched_clock(&cd, mxc_update_sched_clock, 32, c); 132 init_sched_clock(&cd, mxc_update_sched_clock, 32, c);
156 clocksource_register_hz(&clocksource_mxc, c); 133 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
157 134 clocksource_mmio_readl_up);
158 return 0;
159} 135}
160 136
161/* clock event */ 137/* clock event */
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index 187f4e84bb22..18296ee68802 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -5,6 +5,7 @@
5config PLAT_NOMADIK 5config PLAT_NOMADIK
6 bool 6 bool
7 depends on ARCH_NOMADIK || ARCH_U8500 7 depends on ARCH_NOMADIK || ARCH_U8500
8 select CLKSRC_MMIO
8 default y 9 default y
9 help 10 help
10 Common platform code for Nomadik and other ST-Ericsson 11 Common platform code for Nomadik and other ST-Ericsson
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index f49748eca1a3..307b8131aa8c 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,8 @@
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/slab.h> 24#include <linux/slab.h>
25 25
26#include <asm/mach/irq.h>
27
26#include <plat/pincfg.h> 28#include <plat/pincfg.h>
27#include <mach/hardware.h> 29#include <mach/hardware.h>
28#include <mach/gpio.h> 30#include <mach/gpio.h>
@@ -681,13 +683,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
681 struct irq_chip *host_chip = irq_get_chip(irq); 683 struct irq_chip *host_chip = irq_get_chip(irq);
682 unsigned int first_irq; 684 unsigned int first_irq;
683 685
684 if (host_chip->irq_mask_ack) 686 chained_irq_enter(host_chip, desc);
685 host_chip->irq_mask_ack(&desc->irq_data);
686 else {
687 host_chip->irq_mask(&desc->irq_data);
688 if (host_chip->irq_ack)
689 host_chip->irq_ack(&desc->irq_data);
690 }
691 687
692 nmk_chip = irq_get_handler_data(irq); 688 nmk_chip = irq_get_handler_data(irq);
693 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 689 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
@@ -698,7 +694,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
698 status &= ~BIT(bit); 694 status &= ~BIT(bit);
699 } 695 }
700 696
701 host_chip->irq_unmask(&desc->irq_data); 697 chained_irq_exit(host_chip, desc);
702} 698}
703 699
704static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 700static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 41723402006b..ef74e157a9d5 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -26,29 +26,6 @@
26void __iomem *mtu_base; /* Assigned by machine code */ 26void __iomem *mtu_base; /* Assigned by machine code */
27 27
28/* 28/*
29 * Kernel assumes that sched_clock can be called early
30 * but the MTU may not yet be initialized.
31 */
32static cycle_t nmdk_read_timer_dummy(struct clocksource *cs)
33{
34 return 0;
35}
36
37/* clocksource: MTU decrements, so we negate the value being read. */
38static cycle_t nmdk_read_timer(struct clocksource *cs)
39{
40 return -readl(mtu_base + MTU_VAL(0));
41}
42
43static struct clocksource nmdk_clksrc = {
44 .name = "mtu_0",
45 .rating = 200,
46 .read = nmdk_read_timer_dummy,
47 .mask = CLOCKSOURCE_MASK(32),
48 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
49};
50
51/*
52 * Override the global weak sched_clock symbol with this 29 * Override the global weak sched_clock symbol with this
53 * local implementation which uses the clocksource to get some 30 * local implementation which uses the clocksource to get some
54 * better resolution when scheduling the kernel. 31 * better resolution when scheduling the kernel.
@@ -172,12 +149,10 @@ void __init nmdk_timer_init(void)
172 writel(0, mtu_base + MTU_BGLR(0)); 149 writel(0, mtu_base + MTU_BGLR(0));
173 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); 150 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
174 151
175 /* Now the clock source is ready */ 152 if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
176 nmdk_clksrc.read = nmdk_read_timer; 153 rate, 200, 32, clocksource_mmio_readl_down))
177
178 if (clocksource_register_hz(&nmdk_clksrc, rate))
179 pr_err("timer: failed to initialize clock source %s\n", 154 pr_err("timer: failed to initialize clock source %s\n",
180 nmdk_clksrc.name); 155 "mtu_0");
181 156
182 init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); 157 init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
183 158
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index cd5f993612fd..49a4c75243fc 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -12,12 +12,14 @@ choice
12config ARCH_OMAP1 12config ARCH_OMAP1
13 bool "TI OMAP1" 13 bool "TI OMAP1"
14 select CLKDEV_LOOKUP 14 select CLKDEV_LOOKUP
15 select CLKSRC_MMIO
15 help 16 help
16 "Systems based on omap7xx, omap15xx or omap16xx" 17 "Systems based on omap7xx, omap15xx or omap16xx"
17 18
18config ARCH_OMAP2PLUS 19config ARCH_OMAP2PLUS
19 bool "TI OMAP2/3/4" 20 bool "TI OMAP2/3/4"
20 select CLKDEV_LOOKUP 21 select CLKDEV_LOOKUP
22 select GENERIC_IRQ_CHIP
21 select OMAP_DM_TIMER 23 select OMAP_DM_TIMER
22 help 24 help
23 "Systems based on OMAP2, OMAP3 or OMAP4" 25 "Systems based on OMAP2, OMAP3 or OMAP4"
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index bd9e32187eab..efb869390199 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1137,8 +1137,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1137 struct gpio_bank *bank; 1137 struct gpio_bank *bank;
1138 u32 retrigger = 0; 1138 u32 retrigger = 0;
1139 int unmasked = 0; 1139 int unmasked = 0;
1140 struct irq_chip *chip = irq_desc_get_chip(desc);
1140 1141
1141 desc->irq_data.chip->irq_ack(&desc->irq_data); 1142 chained_irq_enter(chip, desc);
1142 1143
1143 bank = irq_get_handler_data(irq); 1144 bank = irq_get_handler_data(irq);
1144#ifdef CONFIG_ARCH_OMAP1 1145#ifdef CONFIG_ARCH_OMAP1
@@ -1195,7 +1196,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1195 configured, we could unmask GPIO bank interrupt immediately */ 1196 configured, we could unmask GPIO bank interrupt immediately */
1196 if (!level_mask && !unmasked) { 1197 if (!level_mask && !unmasked) {
1197 unmasked = 1; 1198 unmasked = 1;
1198 desc->irq_data.chip->irq_unmask(&desc->irq_data); 1199 chained_irq_exit(chip, desc);
1199 } 1200 }
1200 1201
1201 isr |= retrigger; 1202 isr |= retrigger;
@@ -1231,7 +1232,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1231 interrupt */ 1232 interrupt */
1232exit: 1233exit:
1233 if (!unmasked) 1234 if (!unmasked)
1234 desc->irq_data.chip->irq_unmask(&desc->irq_data); 1235 chained_irq_exit(chip, desc);
1235} 1236}
1236 1237
1237static void gpio_irq_shutdown(struct irq_data *d) 1238static void gpio_irq_shutdown(struct irq_data *d)
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
index 3e6327016b40..3083195123ea 100644
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ b/arch/arm/plat-omap/include/plat/flash.h
@@ -11,6 +11,6 @@
11 11
12#include <linux/mtd/map.h> 12#include <linux/mtd/map.h>
13 13
14extern void omap1_set_vpp(struct map_info *map, int enable); 14extern void omap1_set_vpp(struct platform_device *pdev, int enable);
15 15
16#endif 16#endif
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
deleted file mode 100644
index 7a10257909ef..000000000000
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * OMAP4 machine specific smp.h
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#ifndef OMAP_ARCH_SMP_H
18#define OMAP_ARCH_SMP_H
19
20#include <asm/hardware/gic.h>
21
22/* Needed for secondary core boot */
23extern void omap_secondary_startup(void);
24extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
25extern void omap_auxcoreboot_addr(u32 cpu_addr);
26extern u32 omap_read_auxcoreboot0(void);
27
28/*
29 * We use Soft IRQ1 as the IPI
30 */
31static inline void smp_cross_call(const struct cpumask *mask, int ipi)
32{
33 gic_raise_softirq(mask, ipi);
34}
35
36#endif
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 30b891c4a93f..565d2664f5a7 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -27,8 +27,8 @@
27 27
28#define MDR1_MODE_MASK 0x07 28#define MDR1_MODE_MASK 0x07
29 29
30static volatile u8 *uart_base; 30volatile u8 *uart_base;
31static int uart_shift; 31int uart_shift;
32 32
33/* 33/*
34 * Store the DEBUG_LL uart number into memory. 34 * Store the DEBUG_LL uart number into memory.
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 56021a72e10c..95a5fc53b6db 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o pcie.o time.o 5obj-y := irq.o pcie.o time.o common.o mpp.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
new file mode 100644
index 000000000000..9e5451b3c8e3
--- /dev/null
+++ b/arch/arm/plat-orion/common.c
@@ -0,0 +1,957 @@
1/*
2 * arch/arm/plat-orion/common.c
3 *
4 * Marvell Orion SoC common setup code used by multiple mach-/common.c
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <linux/serial_8250.h>
16#include <linux/mbus.h>
17#include <linux/ata_platform.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/mv643xx_i2c.h>
20#include <net/dsa.h>
21#include <linux/spi/orion_spi.h>
22#include <plat/orion_wdt.h>
23#include <plat/mv_xor.h>
24#include <plat/ehci-orion.h>
25
26/* Fill in the resources structure and link it into the platform
27 device structure. There is always a memory region, and nearly
28 always an interrupt.*/
29static void fill_resources(struct platform_device *device,
30 struct resource *resources,
31 resource_size_t mapbase,
32 resource_size_t size,
33 unsigned int irq)
34{
35 device->resource = resources;
36 device->num_resources = 1;
37 resources[0].flags = IORESOURCE_MEM;
38 resources[0].start = mapbase;
39 resources[0].end = mapbase + size;
40
41 if (irq != NO_IRQ) {
42 device->num_resources++;
43 resources[1].flags = IORESOURCE_IRQ;
44 resources[1].start = irq;
45 resources[1].end = irq;
46 }
47}
48
49/*****************************************************************************
50 * UART
51 ****************************************************************************/
52static void __init uart_complete(
53 struct platform_device *orion_uart,
54 struct plat_serial8250_port *data,
55 struct resource *resources,
56 unsigned int membase,
57 resource_size_t mapbase,
58 unsigned int irq,
59 unsigned int uartclk)
60{
61 data->mapbase = mapbase;
62 data->membase = (void __iomem *)membase;
63 data->irq = irq;
64 data->uartclk = uartclk;
65 orion_uart->dev.platform_data = data;
66
67 fill_resources(orion_uart, resources, mapbase, 0xff, irq);
68 platform_device_register(orion_uart);
69}
70
71/*****************************************************************************
72 * UART0
73 ****************************************************************************/
74static struct plat_serial8250_port orion_uart0_data[] = {
75 {
76 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
77 .iotype = UPIO_MEM,
78 .regshift = 2,
79 }, {
80 },
81};
82
83static struct resource orion_uart0_resources[2];
84
85static struct platform_device orion_uart0 = {
86 .name = "serial8250",
87 .id = PLAT8250_DEV_PLATFORM,
88};
89
90void __init orion_uart0_init(unsigned int membase,
91 resource_size_t mapbase,
92 unsigned int irq,
93 unsigned int uartclk)
94{
95 uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
96 membase, mapbase, irq, uartclk);
97}
98
99/*****************************************************************************
100 * UART1
101 ****************************************************************************/
102static struct plat_serial8250_port orion_uart1_data[] = {
103 {
104 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
105 .iotype = UPIO_MEM,
106 .regshift = 2,
107 }, {
108 },
109};
110
111static struct resource orion_uart1_resources[2];
112
113static struct platform_device orion_uart1 = {
114 .name = "serial8250",
115 .id = PLAT8250_DEV_PLATFORM1,
116};
117
118void __init orion_uart1_init(unsigned int membase,
119 resource_size_t mapbase,
120 unsigned int irq,
121 unsigned int uartclk)
122{
123 uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
124 membase, mapbase, irq, uartclk);
125}
126
127/*****************************************************************************
128 * UART2
129 ****************************************************************************/
130static struct plat_serial8250_port orion_uart2_data[] = {
131 {
132 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
133 .iotype = UPIO_MEM,
134 .regshift = 2,
135 }, {
136 },
137};
138
139static struct resource orion_uart2_resources[2];
140
141static struct platform_device orion_uart2 = {
142 .name = "serial8250",
143 .id = PLAT8250_DEV_PLATFORM2,
144};
145
146void __init orion_uart2_init(unsigned int membase,
147 resource_size_t mapbase,
148 unsigned int irq,
149 unsigned int uartclk)
150{
151 uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
152 membase, mapbase, irq, uartclk);
153}
154
155/*****************************************************************************
156 * UART3
157 ****************************************************************************/
158static struct plat_serial8250_port orion_uart3_data[] = {
159 {
160 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
161 .iotype = UPIO_MEM,
162 .regshift = 2,
163 }, {
164 },
165};
166
167static struct resource orion_uart3_resources[2];
168
169static struct platform_device orion_uart3 = {
170 .name = "serial8250",
171 .id = 3,
172};
173
174void __init orion_uart3_init(unsigned int membase,
175 resource_size_t mapbase,
176 unsigned int irq,
177 unsigned int uartclk)
178{
179 uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
180 membase, mapbase, irq, uartclk);
181}
182
183/*****************************************************************************
184 * SoC RTC
185 ****************************************************************************/
186static struct resource orion_rtc_resource[2];
187
188void __init orion_rtc_init(unsigned long mapbase,
189 unsigned long irq)
190{
191 orion_rtc_resource[0].start = mapbase;
192 orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
193 orion_rtc_resource[0].flags = IORESOURCE_MEM;
194 orion_rtc_resource[1].start = irq;
195 orion_rtc_resource[1].end = irq;
196 orion_rtc_resource[1].flags = IORESOURCE_IRQ;
197
198 platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
199}
200
201/*****************************************************************************
202 * GE
203 ****************************************************************************/
204static __init void ge_complete(
205 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
206 struct mbus_dram_target_info *mbus_dram_info, int tclk,
207 struct resource *orion_ge_resource, unsigned long irq,
208 struct platform_device *orion_ge_shared,
209 struct mv643xx_eth_platform_data *eth_data,
210 struct platform_device *orion_ge)
211{
212 orion_ge_shared_data->dram = mbus_dram_info;
213 orion_ge_shared_data->t_clk = tclk;
214 orion_ge_resource->start = irq;
215 orion_ge_resource->end = irq;
216 eth_data->shared = orion_ge_shared;
217 orion_ge->dev.platform_data = eth_data;
218
219 platform_device_register(orion_ge_shared);
220 platform_device_register(orion_ge);
221}
222
223/*****************************************************************************
224 * GE00
225 ****************************************************************************/
226struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
227
228static struct resource orion_ge00_shared_resources[] = {
229 {
230 .name = "ge00 base",
231 }, {
232 .name = "ge00 err irq",
233 },
234};
235
236static struct platform_device orion_ge00_shared = {
237 .name = MV643XX_ETH_SHARED_NAME,
238 .id = 0,
239 .dev = {
240 .platform_data = &orion_ge00_shared_data,
241 },
242};
243
244static struct resource orion_ge00_resources[] = {
245 {
246 .name = "ge00 irq",
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251static struct platform_device orion_ge00 = {
252 .name = MV643XX_ETH_NAME,
253 .id = 0,
254 .num_resources = 1,
255 .resource = orion_ge00_resources,
256 .dev = {
257 .coherent_dma_mask = DMA_BIT_MASK(32),
258 },
259};
260
261void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
262 struct mbus_dram_target_info *mbus_dram_info,
263 unsigned long mapbase,
264 unsigned long irq,
265 unsigned long irq_err,
266 int tclk)
267{
268 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
269 mapbase + 0x2000, SZ_16K - 1, irq_err);
270 ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk,
271 orion_ge00_resources, irq, &orion_ge00_shared,
272 eth_data, &orion_ge00);
273}
274
275/*****************************************************************************
276 * GE01
277 ****************************************************************************/
278struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = {
279 .shared_smi = &orion_ge00_shared,
280};
281
282static struct resource orion_ge01_shared_resources[] = {
283 {
284 .name = "ge01 base",
285 }, {
286 .name = "ge01 err irq",
287 },
288};
289
290static struct platform_device orion_ge01_shared = {
291 .name = MV643XX_ETH_SHARED_NAME,
292 .id = 1,
293 .dev = {
294 .platform_data = &orion_ge01_shared_data,
295 },
296};
297
298static struct resource orion_ge01_resources[] = {
299 {
300 .name = "ge01 irq",
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305static struct platform_device orion_ge01 = {
306 .name = MV643XX_ETH_NAME,
307 .id = 1,
308 .num_resources = 1,
309 .resource = orion_ge01_resources,
310 .dev = {
311 .coherent_dma_mask = DMA_BIT_MASK(32),
312 },
313};
314
315void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
316 struct mbus_dram_target_info *mbus_dram_info,
317 unsigned long mapbase,
318 unsigned long irq,
319 unsigned long irq_err,
320 int tclk)
321{
322 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
323 mapbase + 0x2000, SZ_16K - 1, irq_err);
324 ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk,
325 orion_ge01_resources, irq, &orion_ge01_shared,
326 eth_data, &orion_ge01);
327}
328
329/*****************************************************************************
330 * GE10
331 ****************************************************************************/
332struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = {
333 .shared_smi = &orion_ge00_shared,
334};
335
336static struct resource orion_ge10_shared_resources[] = {
337 {
338 .name = "ge10 base",
339 }, {
340 .name = "ge10 err irq",
341 },
342};
343
344static struct platform_device orion_ge10_shared = {
345 .name = MV643XX_ETH_SHARED_NAME,
346 .id = 1,
347 .dev = {
348 .platform_data = &orion_ge10_shared_data,
349 },
350};
351
352static struct resource orion_ge10_resources[] = {
353 {
354 .name = "ge10 irq",
355 .flags = IORESOURCE_IRQ,
356 },
357};
358
359static struct platform_device orion_ge10 = {
360 .name = MV643XX_ETH_NAME,
361 .id = 1,
362 .num_resources = 2,
363 .resource = orion_ge10_resources,
364 .dev = {
365 .coherent_dma_mask = DMA_BIT_MASK(32),
366 },
367};
368
369void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
370 struct mbus_dram_target_info *mbus_dram_info,
371 unsigned long mapbase,
372 unsigned long irq,
373 unsigned long irq_err,
374 int tclk)
375{
376 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
377 mapbase + 0x2000, SZ_16K - 1, irq_err);
378 ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk,
379 orion_ge10_resources, irq, &orion_ge10_shared,
380 eth_data, &orion_ge10);
381}
382
383/*****************************************************************************
384 * GE11
385 ****************************************************************************/
386struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = {
387 .shared_smi = &orion_ge00_shared,
388};
389
390static struct resource orion_ge11_shared_resources[] = {
391 {
392 .name = "ge11 base",
393 }, {
394 .name = "ge11 err irq",
395 },
396};
397
398static struct platform_device orion_ge11_shared = {
399 .name = MV643XX_ETH_SHARED_NAME,
400 .id = 1,
401 .dev = {
402 .platform_data = &orion_ge11_shared_data,
403 },
404};
405
406static struct resource orion_ge11_resources[] = {
407 {
408 .name = "ge11 irq",
409 .flags = IORESOURCE_IRQ,
410 },
411};
412
413static struct platform_device orion_ge11 = {
414 .name = MV643XX_ETH_NAME,
415 .id = 1,
416 .num_resources = 2,
417 .resource = orion_ge11_resources,
418 .dev = {
419 .coherent_dma_mask = DMA_BIT_MASK(32),
420 },
421};
422
423void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
424 struct mbus_dram_target_info *mbus_dram_info,
425 unsigned long mapbase,
426 unsigned long irq,
427 unsigned long irq_err,
428 int tclk)
429{
430 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
431 mapbase + 0x2000, SZ_16K - 1, irq_err);
432 ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk,
433 orion_ge11_resources, irq, &orion_ge11_shared,
434 eth_data, &orion_ge11);
435}
436
437/*****************************************************************************
438 * Ethernet switch
439 ****************************************************************************/
440static struct resource orion_switch_resources[] = {
441 {
442 .start = 0,
443 .end = 0,
444 .flags = IORESOURCE_IRQ,
445 },
446};
447
448static struct platform_device orion_switch_device = {
449 .name = "dsa",
450 .id = 0,
451 .num_resources = 0,
452 .resource = orion_switch_resources,
453};
454
455void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
456{
457 int i;
458
459 if (irq != NO_IRQ) {
460 orion_switch_resources[0].start = irq;
461 orion_switch_resources[0].end = irq;
462 orion_switch_device.num_resources = 1;
463 }
464
465 d->netdev = &orion_ge00.dev;
466 for (i = 0; i < d->nr_chips; i++)
467 d->chip[i].mii_bus = &orion_ge00_shared.dev;
468 orion_switch_device.dev.platform_data = d;
469
470 platform_device_register(&orion_switch_device);
471}
472
473/*****************************************************************************
474 * I2C
475 ****************************************************************************/
476static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
477 .freq_n = 3,
478 .timeout = 1000, /* Default timeout of 1 second */
479};
480
481static struct resource orion_i2c_resources[2];
482
483static struct platform_device orion_i2c = {
484 .name = MV64XXX_I2C_CTLR_NAME,
485 .id = 0,
486 .dev = {
487 .platform_data = &orion_i2c_pdata,
488 },
489};
490
491static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
492 .freq_n = 3,
493 .timeout = 1000, /* Default timeout of 1 second */
494};
495
496static struct resource orion_i2c_1_resources[2];
497
498static struct platform_device orion_i2c_1 = {
499 .name = MV64XXX_I2C_CTLR_NAME,
500 .id = 1,
501 .dev = {
502 .platform_data = &orion_i2c_1_pdata,
503 },
504};
505
506void __init orion_i2c_init(unsigned long mapbase,
507 unsigned long irq,
508 unsigned long freq_m)
509{
510 orion_i2c_pdata.freq_m = freq_m;
511 fill_resources(&orion_i2c, orion_i2c_resources, mapbase,
512 SZ_32 - 1, irq);
513 platform_device_register(&orion_i2c);
514}
515
516void __init orion_i2c_1_init(unsigned long mapbase,
517 unsigned long irq,
518 unsigned long freq_m)
519{
520 orion_i2c_1_pdata.freq_m = freq_m;
521 fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase,
522 SZ_32 - 1, irq);
523 platform_device_register(&orion_i2c_1);
524}
525
526/*****************************************************************************
527 * SPI
528 ****************************************************************************/
529static struct orion_spi_info orion_spi_plat_data;
530static struct resource orion_spi_resources;
531
532static struct platform_device orion_spi = {
533 .name = "orion_spi",
534 .id = 0,
535 .dev = {
536 .platform_data = &orion_spi_plat_data,
537 },
538};
539
540static struct orion_spi_info orion_spi_1_plat_data;
541static struct resource orion_spi_1_resources;
542
543static struct platform_device orion_spi_1 = {
544 .name = "orion_spi",
545 .id = 1,
546 .dev = {
547 .platform_data = &orion_spi_1_plat_data,
548 },
549};
550
551/* Note: The SPI silicon core does have interrupts. However the
552 * current Linux software driver does not use interrupts. */
553
554void __init orion_spi_init(unsigned long mapbase,
555 unsigned long tclk)
556{
557 orion_spi_plat_data.tclk = tclk;
558 fill_resources(&orion_spi, &orion_spi_resources,
559 mapbase, SZ_512 - 1, NO_IRQ);
560 platform_device_register(&orion_spi);
561}
562
563void __init orion_spi_1_init(unsigned long mapbase,
564 unsigned long tclk)
565{
566 orion_spi_1_plat_data.tclk = tclk;
567 fill_resources(&orion_spi_1, &orion_spi_1_resources,
568 mapbase, SZ_512 - 1, NO_IRQ);
569 platform_device_register(&orion_spi_1);
570}
571
572/*****************************************************************************
573 * Watchdog
574 ****************************************************************************/
575static struct orion_wdt_platform_data orion_wdt_data;
576
577static struct platform_device orion_wdt_device = {
578 .name = "orion_wdt",
579 .id = -1,
580 .dev = {
581 .platform_data = &orion_wdt_data,
582 },
583 .num_resources = 0,
584};
585
586void __init orion_wdt_init(unsigned long tclk)
587{
588 orion_wdt_data.tclk = tclk;
589 platform_device_register(&orion_wdt_device);
590}
591
592/*****************************************************************************
593 * XOR
594 ****************************************************************************/
595static struct mv_xor_platform_shared_data orion_xor_shared_data;
596
597static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
598
599void __init orion_xor_init_channels(
600 struct mv_xor_platform_data *orion_xor0_data,
601 struct platform_device *orion_xor0_channel,
602 struct mv_xor_platform_data *orion_xor1_data,
603 struct platform_device *orion_xor1_channel)
604{
605 /*
606 * two engines can't do memset simultaneously, this limitation
607 * satisfied by removing memset support from one of the engines.
608 */
609 dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);
610 dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);
611 platform_device_register(orion_xor0_channel);
612
613 dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);
614 dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);
615 dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);
616 platform_device_register(orion_xor1_channel);
617}
618
619/*****************************************************************************
620 * XOR0
621 ****************************************************************************/
622static struct resource orion_xor0_shared_resources[] = {
623 {
624 .name = "xor 0 low",
625 .flags = IORESOURCE_MEM,
626 }, {
627 .name = "xor 0 high",
628 .flags = IORESOURCE_MEM,
629 },
630};
631
632static struct platform_device orion_xor0_shared = {
633 .name = MV_XOR_SHARED_NAME,
634 .id = 0,
635 .dev = {
636 .platform_data = &orion_xor_shared_data,
637 },
638 .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
639 .resource = orion_xor0_shared_resources,
640};
641
642static struct resource orion_xor00_resources[] = {
643 [0] = {
644 .flags = IORESOURCE_IRQ,
645 },
646};
647
648static struct mv_xor_platform_data orion_xor00_data = {
649 .shared = &orion_xor0_shared,
650 .hw_id = 0,
651 .pool_size = PAGE_SIZE,
652};
653
654static struct platform_device orion_xor00_channel = {
655 .name = MV_XOR_NAME,
656 .id = 0,
657 .num_resources = ARRAY_SIZE(orion_xor00_resources),
658 .resource = orion_xor00_resources,
659 .dev = {
660 .dma_mask = &orion_xor_dmamask,
661 .coherent_dma_mask = DMA_BIT_MASK(64),
662 .platform_data = &orion_xor00_data,
663 },
664};
665
666static struct resource orion_xor01_resources[] = {
667 [0] = {
668 .flags = IORESOURCE_IRQ,
669 },
670};
671
672static struct mv_xor_platform_data orion_xor01_data = {
673 .shared = &orion_xor0_shared,
674 .hw_id = 1,
675 .pool_size = PAGE_SIZE,
676};
677
678static struct platform_device orion_xor01_channel = {
679 .name = MV_XOR_NAME,
680 .id = 1,
681 .num_resources = ARRAY_SIZE(orion_xor01_resources),
682 .resource = orion_xor01_resources,
683 .dev = {
684 .dma_mask = &orion_xor_dmamask,
685 .coherent_dma_mask = DMA_BIT_MASK(64),
686 .platform_data = &orion_xor01_data,
687 },
688};
689
690void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
691 unsigned long mapbase_low,
692 unsigned long mapbase_high,
693 unsigned long irq_0,
694 unsigned long irq_1)
695{
696 orion_xor_shared_data.dram = mbus_dram_info;
697
698 orion_xor0_shared_resources[0].start = mapbase_low;
699 orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
700 orion_xor0_shared_resources[1].start = mapbase_high;
701 orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
702
703 orion_xor00_resources[0].start = irq_0;
704 orion_xor00_resources[0].end = irq_0;
705 orion_xor01_resources[0].start = irq_1;
706 orion_xor01_resources[0].end = irq_1;
707
708 platform_device_register(&orion_xor0_shared);
709
710 orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,
711 &orion_xor01_data, &orion_xor01_channel);
712}
713
714/*****************************************************************************
715 * XOR1
716 ****************************************************************************/
717static struct resource orion_xor1_shared_resources[] = {
718 {
719 .name = "xor 1 low",
720 .flags = IORESOURCE_MEM,
721 }, {
722 .name = "xor 1 high",
723 .flags = IORESOURCE_MEM,
724 },
725};
726
727static struct platform_device orion_xor1_shared = {
728 .name = MV_XOR_SHARED_NAME,
729 .id = 1,
730 .dev = {
731 .platform_data = &orion_xor_shared_data,
732 },
733 .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
734 .resource = orion_xor1_shared_resources,
735};
736
737static struct resource orion_xor10_resources[] = {
738 [0] = {
739 .flags = IORESOURCE_IRQ,
740 },
741};
742
743static struct mv_xor_platform_data orion_xor10_data = {
744 .shared = &orion_xor1_shared,
745 .hw_id = 0,
746 .pool_size = PAGE_SIZE,
747};
748
749static struct platform_device orion_xor10_channel = {
750 .name = MV_XOR_NAME,
751 .id = 2,
752 .num_resources = ARRAY_SIZE(orion_xor10_resources),
753 .resource = orion_xor10_resources,
754 .dev = {
755 .dma_mask = &orion_xor_dmamask,
756 .coherent_dma_mask = DMA_BIT_MASK(64),
757 .platform_data = &orion_xor10_data,
758 },
759};
760
761static struct resource orion_xor11_resources[] = {
762 [0] = {
763 .flags = IORESOURCE_IRQ,
764 },
765};
766
767static struct mv_xor_platform_data orion_xor11_data = {
768 .shared = &orion_xor1_shared,
769 .hw_id = 1,
770 .pool_size = PAGE_SIZE,
771};
772
773static struct platform_device orion_xor11_channel = {
774 .name = MV_XOR_NAME,
775 .id = 3,
776 .num_resources = ARRAY_SIZE(orion_xor11_resources),
777 .resource = orion_xor11_resources,
778 .dev = {
779 .dma_mask = &orion_xor_dmamask,
780 .coherent_dma_mask = DMA_BIT_MASK(64),
781 .platform_data = &orion_xor11_data,
782 },
783};
784
785void __init orion_xor1_init(unsigned long mapbase_low,
786 unsigned long mapbase_high,
787 unsigned long irq_0,
788 unsigned long irq_1)
789{
790 orion_xor1_shared_resources[0].start = mapbase_low;
791 orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
792 orion_xor1_shared_resources[1].start = mapbase_high;
793 orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
794
795 orion_xor10_resources[0].start = irq_0;
796 orion_xor10_resources[0].end = irq_0;
797 orion_xor11_resources[0].start = irq_1;
798 orion_xor11_resources[0].end = irq_1;
799
800 platform_device_register(&orion_xor1_shared);
801
802 orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,
803 &orion_xor11_data, &orion_xor11_channel);
804}
805
806/*****************************************************************************
807 * EHCI
808 ****************************************************************************/
809static struct orion_ehci_data orion_ehci_data = {
810 .phy_version = EHCI_PHY_NA,
811};
812
813static u64 ehci_dmamask = DMA_BIT_MASK(32);
814
815
816/*****************************************************************************
817 * EHCI0
818 ****************************************************************************/
819static struct resource orion_ehci_resources[2];
820
821static struct platform_device orion_ehci = {
822 .name = "orion-ehci",
823 .id = 0,
824 .dev = {
825 .dma_mask = &ehci_dmamask,
826 .coherent_dma_mask = DMA_BIT_MASK(32),
827 .platform_data = &orion_ehci_data,
828 },
829};
830
831void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
832 unsigned long mapbase,
833 unsigned long irq)
834{
835 orion_ehci_data.dram = mbus_dram_info;
836 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
837 irq);
838
839 platform_device_register(&orion_ehci);
840}
841
842/*****************************************************************************
843 * EHCI1
844 ****************************************************************************/
845static struct resource orion_ehci_1_resources[2];
846
847static struct platform_device orion_ehci_1 = {
848 .name = "orion-ehci",
849 .id = 1,
850 .dev = {
851 .dma_mask = &ehci_dmamask,
852 .coherent_dma_mask = DMA_BIT_MASK(32),
853 .platform_data = &orion_ehci_data,
854 },
855};
856
857void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
858 unsigned long mapbase,
859 unsigned long irq)
860{
861 orion_ehci_data.dram = mbus_dram_info;
862 fill_resources(&orion_ehci_1, orion_ehci_1_resources,
863 mapbase, SZ_4K - 1, irq);
864
865 platform_device_register(&orion_ehci_1);
866}
867
868/*****************************************************************************
869 * EHCI2
870 ****************************************************************************/
871static struct resource orion_ehci_2_resources[2];
872
873static struct platform_device orion_ehci_2 = {
874 .name = "orion-ehci",
875 .id = 2,
876 .dev = {
877 .dma_mask = &ehci_dmamask,
878 .coherent_dma_mask = DMA_BIT_MASK(32),
879 .platform_data = &orion_ehci_data,
880 },
881};
882
883void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
884 unsigned long mapbase,
885 unsigned long irq)
886{
887 orion_ehci_data.dram = mbus_dram_info;
888 fill_resources(&orion_ehci_2, orion_ehci_2_resources,
889 mapbase, SZ_4K - 1, irq);
890
891 platform_device_register(&orion_ehci_2);
892}
893
894/*****************************************************************************
895 * SATA
896 ****************************************************************************/
897static struct resource orion_sata_resources[2] = {
898 {
899 .name = "sata base",
900 }, {
901 .name = "sata irq",
902 },
903};
904
905static struct platform_device orion_sata = {
906 .name = "sata_mv",
907 .id = 0,
908 .dev = {
909 .coherent_dma_mask = DMA_BIT_MASK(32),
910 },
911};
912
913void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
914 struct mbus_dram_target_info *mbus_dram_info,
915 unsigned long mapbase,
916 unsigned long irq)
917{
918 sata_data->dram = mbus_dram_info;
919 orion_sata.dev.platform_data = sata_data;
920 fill_resources(&orion_sata, orion_sata_resources,
921 mapbase, 0x5000 - 1, irq);
922
923 platform_device_register(&orion_sata);
924}
925
926/*****************************************************************************
927 * Cryptographic Engines and Security Accelerator (CESA)
928 ****************************************************************************/
929static struct resource orion_crypto_resources[] = {
930 {
931 .name = "regs",
932 }, {
933 .name = "crypto interrupt",
934 }, {
935 .name = "sram",
936 .flags = IORESOURCE_MEM,
937 },
938};
939
940static struct platform_device orion_crypto = {
941 .name = "mv_crypto",
942 .id = -1,
943};
944
945void __init orion_crypto_init(unsigned long mapbase,
946 unsigned long srambase,
947 unsigned long sram_size,
948 unsigned long irq)
949{
950 fill_resources(&orion_crypto, orion_crypto_resources,
951 mapbase, 0xffff, irq);
952 orion_crypto.num_resources = 3;
953 orion_crypto_resources[2].start = srambase;
954 orion_crypto_resources[2].end = srambase + sram_size - 1;
955
956 platform_device_register(&orion_crypto);
957}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index a431a138f402..5b4fffab1eb4 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -321,59 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
321 * polarity LEVEL mask 321 * polarity LEVEL mask
322 * 322 *
323 ****************************************************************************/ 323 ****************************************************************************/
324static void gpio_irq_ack(struct irq_data *d)
325{
326 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
327 int type = irqd_get_trigger_type(d);
328
329 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
330 int pin = d->irq - ochip->secondary_irq_base;
331
332 writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
333 }
334}
335
336static void gpio_irq_mask(struct irq_data *d)
337{
338 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
339 int type = irqd_get_trigger_type(d);
340 void __iomem *reg;
341 int pin;
342
343 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
344 reg = GPIO_EDGE_MASK(ochip);
345 else
346 reg = GPIO_LEVEL_MASK(ochip);
347
348 pin = d->irq - ochip->secondary_irq_base;
349
350 writel(readl(reg) & ~(1 << pin), reg);
351}
352
353static void gpio_irq_unmask(struct irq_data *d)
354{
355 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
356 int type = irqd_get_trigger_type(d);
357 void __iomem *reg;
358 int pin;
359
360 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
361 reg = GPIO_EDGE_MASK(ochip);
362 else
363 reg = GPIO_LEVEL_MASK(ochip);
364
365 pin = d->irq - ochip->secondary_irq_base;
366
367 writel(readl(reg) | (1 << pin), reg);
368}
369 324
370static int gpio_irq_set_type(struct irq_data *d, u32 type) 325static int gpio_irq_set_type(struct irq_data *d, u32 type)
371{ 326{
372 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); 327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328 struct irq_chip_type *ct = irq_data_get_chip_type(d);
329 struct orion_gpio_chip *ochip = gc->private;
373 int pin; 330 int pin;
374 u32 u; 331 u32 u;
375 332
376 pin = d->irq - ochip->secondary_irq_base; 333 pin = d->irq - gc->irq_base;
377 334
378 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); 335 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
379 if (!u) { 336 if (!u) {
@@ -382,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
382 return -EINVAL; 339 return -EINVAL;
383 } 340 }
384 341
385 /* 342 type &= IRQ_TYPE_SENSE_MASK;
386 * Set edge/level type. 343 if (type == IRQ_TYPE_NONE)
387 */
388 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
389 __irq_set_handler_locked(d->irq, handle_edge_irq);
390 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
391 __irq_set_handler_locked(d->irq, handle_level_irq);
392 } else {
393 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
394 d->irq, type);
395 return -EINVAL; 344 return -EINVAL;
396 } 345
346 /* Check if we need to change chip and handler */
347 if (!(ct->type & type))
348 if (irq_setup_alt_chip(d, type))
349 return -EINVAL;
397 350
398 /* 351 /*
399 * Configure interrupt polarity. 352 * Configure interrupt polarity.
@@ -425,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
425 return 0; 378 return 0;
426} 379}
427 380
428struct irq_chip orion_gpio_irq_chip = {
429 .name = "orion_gpio_irq",
430 .irq_ack = gpio_irq_ack,
431 .irq_mask = gpio_irq_mask,
432 .irq_unmask = gpio_irq_unmask,
433 .irq_set_type = gpio_irq_set_type,
434};
435
436void __init orion_gpio_init(int gpio_base, int ngpio, 381void __init orion_gpio_init(int gpio_base, int ngpio,
437 u32 base, int mask_offset, int secondary_irq_base) 382 u32 base, int mask_offset, int secondary_irq_base)
438{ 383{
439 struct orion_gpio_chip *ochip; 384 struct orion_gpio_chip *ochip;
440 int i; 385 struct irq_chip_generic *gc;
386 struct irq_chip_type *ct;
441 387
442 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) 388 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
443 return; 389 return;
@@ -471,15 +417,29 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
471 writel(0, GPIO_EDGE_MASK(ochip)); 417 writel(0, GPIO_EDGE_MASK(ochip));
472 writel(0, GPIO_LEVEL_MASK(ochip)); 418 writel(0, GPIO_LEVEL_MASK(ochip));
473 419
474 for (i = 0; i < ngpio; i++) { 420 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
475 unsigned int irq = secondary_irq_base + i; 421 ochip->base, handle_level_irq);
476 422 gc->private = ochip;
477 irq_set_chip_and_handler(irq, &orion_gpio_irq_chip, 423
478 handle_level_irq); 424 ct = gc->chip_types;
479 irq_set_chip_data(irq, ochip); 425 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
480 irq_set_status_flags(irq, IRQ_LEVEL); 426 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
481 set_irq_flags(irq, IRQF_VALID); 427 ct->chip.irq_mask = irq_gc_mask_clr_bit;
482 } 428 ct->chip.irq_unmask = irq_gc_mask_set_bit;
429 ct->chip.irq_set_type = gpio_irq_set_type;
430
431 ct++;
432 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
433 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
434 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
435 ct->chip.irq_ack = irq_gc_ack;
436 ct->chip.irq_mask = irq_gc_mask_clr_bit;
437 ct->chip.irq_unmask = irq_gc_mask_set_bit;
438 ct->chip.irq_set_type = gpio_irq_set_type;
439 ct->handler = handle_edge_irq;
440
441 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
442 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
483} 443}
484 444
485void orion_gpio_irq_handler(int pinoff) 445void orion_gpio_irq_handler(int pinoff)
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
new file mode 100644
index 000000000000..a63c357e2ab1
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -0,0 +1,117 @@
1/*
2 * arch/arm/plat-orion/include/plat/common.h
3 *
4 * Marvell Orion SoC common setup code used by different mach-/common.c
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __PLAT_COMMON_H
12#include <linux/mv643xx_eth.h>
13
14struct dsa_platform_data;
15
16void __init orion_uart0_init(unsigned int membase,
17 resource_size_t mapbase,
18 unsigned int irq,
19 unsigned int uartclk);
20
21void __init orion_uart1_init(unsigned int membase,
22 resource_size_t mapbase,
23 unsigned int irq,
24 unsigned int uartclk);
25
26void __init orion_uart2_init(unsigned int membase,
27 resource_size_t mapbase,
28 unsigned int irq,
29 unsigned int uartclk);
30
31void __init orion_uart3_init(unsigned int membase,
32 resource_size_t mapbase,
33 unsigned int irq,
34 unsigned int uartclk);
35
36void __init orion_rtc_init(unsigned long mapbase,
37 unsigned long irq);
38
39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
40 struct mbus_dram_target_info *mbus_dram_info,
41 unsigned long mapbase,
42 unsigned long irq,
43 unsigned long irq_err,
44 int tclk);
45
46void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
47 struct mbus_dram_target_info *mbus_dram_info,
48 unsigned long mapbase,
49 unsigned long irq,
50 unsigned long irq_err,
51 int tclk);
52
53void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
54 struct mbus_dram_target_info *mbus_dram_info,
55 unsigned long mapbase,
56 unsigned long irq,
57 unsigned long irq_err,
58 int tclk);
59
60void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
61 struct mbus_dram_target_info *mbus_dram_info,
62 unsigned long mapbase,
63 unsigned long irq,
64 unsigned long irq_err,
65 int tclk);
66
67void __init orion_ge00_switch_init(struct dsa_platform_data *d,
68 int irq);
69void __init orion_i2c_init(unsigned long mapbase,
70 unsigned long irq,
71 unsigned long freq_m);
72
73void __init orion_i2c_1_init(unsigned long mapbase,
74 unsigned long irq,
75 unsigned long freq_m);
76
77void __init orion_spi_init(unsigned long mapbase,
78 unsigned long tclk);
79
80void __init orion_spi_1_init(unsigned long mapbase,
81 unsigned long tclk);
82
83void __init orion_wdt_init(unsigned long tclk);
84
85void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
86 unsigned long mapbase_low,
87 unsigned long mapbase_high,
88 unsigned long irq_0,
89 unsigned long irq_1);
90
91void __init orion_xor1_init(unsigned long mapbase_low,
92 unsigned long mapbase_high,
93 unsigned long irq_0,
94 unsigned long irq_1);
95
96void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
97 unsigned long mapbase,
98 unsigned long irq);
99
100void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
101 unsigned long mapbase,
102 unsigned long irq);
103
104void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
105 unsigned long mapbase,
106 unsigned long irq);
107
108void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
109 struct mbus_dram_target_info *mbus_dram_info,
110 unsigned long mapbase,
111 unsigned long irq);
112
113void __init orion_crypto_init(unsigned long mapbase,
114 unsigned long srambase,
115 unsigned long sram_size,
116 unsigned long irq);
117#endif
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 5578b9803fc6..3075b9fdde83 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
39/* 39/*
40 * GPIO interrupt handling. 40 * GPIO interrupt handling.
41 */ 41 */
42extern struct irq_chip orion_gpio_irq_chip;
43void orion_gpio_irq_handler(int irqoff); 42void orion_gpio_irq_handler(int irqoff);
44 43
45 44
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
new file mode 100644
index 000000000000..723adce99f41
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -0,0 +1,34 @@
1/*
2 * arch/arm/plat-orion/include/plat/mpp.h
3 *
4 * Marvell Orion SoC MPP handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __PLAT_MPP_H
12#define __PLAT_MPP_H
13
14#define MPP_NUM(x) ((x) & 0xff)
15#define MPP_SEL(x) (((x) >> 8) & 0xf)
16
17/* This is the generic MPP macro, without any variant information.
18 Each machine architecture is expected to extend this with further
19 bit fields indicating which MPP configurations are valid for a
20 specific variant. */
21
22#define GENERIC_MPP(_num, _sel, _in, _out) ( \
23 /* MPP number */ ((_num) & 0xff) | \
24 /* MPP select value */ (((_sel) & 0xf) << 8) | \
25 /* may be input signal */ ((!!(_in)) << 12) | \
26 /* may be output signal */ ((!!(_out)) << 13))
27
28#define MPP_INPUT_MASK GENERIC_MPP(0, 0x0, 1, 0)
29#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1)
30
31void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
32 unsigned int mpp_max, unsigned int dev_bus);
33
34#endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index d8d638e09f8f..2d5b9c1ef389 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -14,52 +14,21 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/irq.h> 15#include <plat/irq.h>
16 16
17static void orion_irq_mask(struct irq_data *d)
18{
19 void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
20 u32 mask;
21
22 mask = readl(maskaddr);
23 mask &= ~(1 << (d->irq & 31));
24 writel(mask, maskaddr);
25}
26
27static void orion_irq_unmask(struct irq_data *d)
28{
29 void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
30 u32 mask;
31
32 mask = readl(maskaddr);
33 mask |= 1 << (d->irq & 31);
34 writel(mask, maskaddr);
35}
36
37static struct irq_chip orion_irq_chip = {
38 .name = "orion_irq",
39 .irq_mask = orion_irq_mask,
40 .irq_mask_ack = orion_irq_mask,
41 .irq_unmask = orion_irq_unmask,
42};
43
44void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) 17void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
45{ 18{
46 unsigned int i; 19 struct irq_chip_generic *gc;
20 struct irq_chip_type *ct;
47 21
48 /* 22 /*
49 * Mask all interrupts initially. 23 * Mask all interrupts initially.
50 */ 24 */
51 writel(0, maskaddr); 25 writel(0, maskaddr);
52 26
53 /* 27 gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
54 * Register IRQ sources. 28 handle_level_irq);
55 */ 29 ct = gc->chip_types;
56 for (i = 0; i < 32; i++) { 30 ct->chip.irq_mask = irq_gc_mask_clr_bit;
57 unsigned int irq = irq_start + i; 31 ct->chip.irq_unmask = irq_gc_mask_set_bit;
58 32 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
59 irq_set_chip_and_handler(irq, &orion_irq_chip, 33 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
60 handle_level_irq);
61 irq_set_chip_data(irq, maskaddr);
62 irq_set_status_flags(irq, IRQ_LEVEL);
63 set_irq_flags(irq, IRQF_VALID);
64 }
65} 34}
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
new file mode 100644
index 000000000000..91553432711d
--- /dev/null
+++ b/arch/arm/plat-orion/mpp.c
@@ -0,0 +1,78 @@
1/*
2 * arch/arm/plat-orion/mpp.c
3 *
4 * MPP functions for Marvell orion SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16#include <mach/hardware.h>
17#include <plat/mpp.h>
18
19/* Address of the ith MPP control register */
20static __init unsigned long mpp_ctrl_addr(unsigned int i,
21 unsigned long dev_bus)
22{
23 return dev_bus + (i) * 4;
24}
25
26
27void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
28 unsigned int mpp_max, unsigned int dev_bus)
29{
30 unsigned int mpp_nr_regs = (1 + mpp_max/8);
31 u32 mpp_ctrl[mpp_nr_regs];
32 int i;
33
34 printk(KERN_DEBUG "initial MPP regs:");
35 for (i = 0; i < mpp_nr_regs; i++) {
36 mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
37 printk(" %08x", mpp_ctrl[i]);
38 }
39 printk("\n");
40
41 for ( ; *mpp_list; mpp_list++) {
42 unsigned int num = MPP_NUM(*mpp_list);
43 unsigned int sel = MPP_SEL(*mpp_list);
44 int shift, gpio_mode;
45
46 if (num > mpp_max) {
47 printk(KERN_ERR "orion_mpp_conf: invalid MPP "
48 "number (%u)\n", num);
49 continue;
50 }
51 if (variant_mask & !(*mpp_list & variant_mask)) {
52 printk(KERN_WARNING
53 "orion_mpp_conf: requested MPP%u config "
54 "unavailable on this hardware\n", num);
55 continue;
56 }
57
58 shift = (num & 7) << 2;
59 mpp_ctrl[num / 8] &= ~(0xf << shift);
60 mpp_ctrl[num / 8] |= sel << shift;
61
62 gpio_mode = 0;
63 if (*mpp_list & MPP_INPUT_MASK)
64 gpio_mode |= GPIO_INPUT_OK;
65 if (*mpp_list & MPP_OUTPUT_MASK)
66 gpio_mode |= GPIO_OUTPUT_OK;
67 if (sel != 0)
68 gpio_mode = 0;
69 orion_gpio_set_valid(num, gpio_mode);
70 }
71
72 printk(KERN_DEBUG " final MPP regs:");
73 for (i = 0; i < mpp_nr_regs; i++) {
74 writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
75 printk(" %08x", mpp_ctrl[i]);
76 }
77 printk("\n");
78}
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 742b0323c57b..69a61367e4b8 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -81,24 +81,6 @@ static void __init setup_sched_clock(unsigned long tclk)
81} 81}
82 82
83/* 83/*
84 * Clocksource handling.
85 */
86static cycle_t orion_clksrc_read(struct clocksource *cs)
87{
88 return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
89}
90
91static struct clocksource orion_clksrc = {
92 .name = "orion_clocksource",
93 .rating = 300,
94 .read = orion_clksrc_read,
95 .mask = CLOCKSOURCE_MASK(32),
96 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
97};
98
99
100
101/*
102 * Clockevent handling. 84 * Clockevent handling.
103 */ 85 */
104static int 86static int
@@ -247,7 +229,8 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
247 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF); 229 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
248 u = readl(timer_base + TIMER_CTRL_OFF); 230 u = readl(timer_base + TIMER_CTRL_OFF);
249 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF); 231 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
250 clocksource_register_hz(&orion_clksrc, tclk); 232 clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
233 tclk, 300, 32, clocksource_mmio_readl_down);
251 234
252 /* 235 /*
253 * Setup clockevent timer (interrupt-driven). 236 * Setup clockevent timer (interrupt-driven).
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index cd6d67c8382a..135abda31c9a 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -41,72 +41,11 @@ struct s5p_gpioint_bank {
41 41
42LIST_HEAD(banks); 42LIST_HEAD(banks);
43 43
44static int s5p_gpioint_get_offset(struct irq_data *data) 44static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
45{ 45{
46 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); 46 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
47 return data->irq - chip->irq_base; 47 struct irq_chip_type *ct = gc->chip_types;
48} 48 unsigned int shift = (d->irq - gc->irq_base) << 2;
49
50static void s5p_gpioint_ack(struct irq_data *data)
51{
52 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
53 int group, offset, pend_offset;
54 unsigned int value;
55
56 group = chip->group;
57 offset = s5p_gpioint_get_offset(data);
58 pend_offset = REG_OFFSET(group);
59
60 value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
61 value |= BIT(offset);
62 __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
63}
64
65static void s5p_gpioint_mask(struct irq_data *data)
66{
67 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
68 int group, offset, mask_offset;
69 unsigned int value;
70
71 group = chip->group;
72 offset = s5p_gpioint_get_offset(data);
73 mask_offset = REG_OFFSET(group);
74
75 value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
76 value |= BIT(offset);
77 __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
78}
79
80static void s5p_gpioint_unmask(struct irq_data *data)
81{
82 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
83 int group, offset, mask_offset;
84 unsigned int value;
85
86 group = chip->group;
87 offset = s5p_gpioint_get_offset(data);
88 mask_offset = REG_OFFSET(group);
89
90 value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
91 value &= ~BIT(offset);
92 __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
93}
94
95static void s5p_gpioint_mask_ack(struct irq_data *data)
96{
97 s5p_gpioint_mask(data);
98 s5p_gpioint_ack(data);
99}
100
101static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
102{
103 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
104 int group, offset, con_offset;
105 unsigned int value;
106
107 group = chip->group;
108 offset = s5p_gpioint_get_offset(data);
109 con_offset = REG_OFFSET(group);
110 49
111 switch (type) { 50 switch (type) {
112 case IRQ_TYPE_EDGE_RISING: 51 case IRQ_TYPE_EDGE_RISING:
@@ -130,23 +69,12 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
130 return -EINVAL; 69 return -EINVAL;
131 } 70 }
132 71
133 value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset); 72 gc->type_cache &= ~(0x7 << shift);
134 value &= ~(0x7 << (offset * 0x4)); 73 gc->type_cache |= type << shift;
135 value |= (type << (offset * 0x4)); 74 writel(gc->type_cache, gc->reg_base + ct->regs.type);
136 __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
137
138 return 0; 75 return 0;
139} 76}
140 77
141static struct irq_chip s5p_gpioint = {
142 .name = "s5p_gpioint",
143 .irq_ack = s5p_gpioint_ack,
144 .irq_mask = s5p_gpioint_mask,
145 .irq_mask_ack = s5p_gpioint_mask_ack,
146 .irq_unmask = s5p_gpioint_unmask,
147 .irq_set_type = s5p_gpioint_set_type,
148};
149
150static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) 78static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
151{ 79{
152 struct s5p_gpioint_bank *bank = irq_get_handler_data(irq); 80 struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
@@ -179,9 +107,10 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
179static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) 107static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
180{ 108{
181 static int used_gpioint_groups = 0; 109 static int used_gpioint_groups = 0;
182 int irq, group = chip->group; 110 int group = chip->group;
183 int i;
184 struct s5p_gpioint_bank *bank = NULL; 111 struct s5p_gpioint_bank *bank = NULL;
112 struct irq_chip_generic *gc;
113 struct irq_chip_type *ct;
185 114
186 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) 115 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
187 return -ENOMEM; 116 return -ENOMEM;
@@ -211,19 +140,28 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
211 * chained GPIO irq has been successfully registered, allocate new gpio 140 * chained GPIO irq has been successfully registered, allocate new gpio
212 * int group and assign irq nubmers 141 * int group and assign irq nubmers
213 */ 142 */
214
215 chip->irq_base = S5P_GPIOINT_BASE + 143 chip->irq_base = S5P_GPIOINT_BASE +
216 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE; 144 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
217 used_gpioint_groups++; 145 used_gpioint_groups++;
218 146
219 bank->chips[group - bank->start] = chip; 147 bank->chips[group - bank->start] = chip;
220 for (i = 0; i < chip->chip.ngpio; i++) { 148
221 irq = chip->irq_base + i; 149 gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
222 irq_set_chip(irq, &s5p_gpioint); 150 (void __iomem *)GPIO_BASE(chip),
223 irq_set_handler_data(irq, chip); 151 handle_level_irq);
224 irq_set_handler(irq, handle_level_irq); 152 if (!gc)
225 set_irq_flags(irq, IRQF_VALID); 153 return -ENOMEM;
226 } 154 ct = gc->chip_types;
155 ct->chip.irq_ack = irq_gc_ack;
156 ct->chip.irq_mask = irq_gc_mask_set_bit;
157 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
158 ct->chip.irq_set_type = s5p_gpioint_set_type,
159 ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
160 ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
161 ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
162 irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
163 IRQ_GC_INIT_MASK_CACHE,
164 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
227 return 0; 165 return 0;
228} 166}
229 167
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index 5560b12035d1..a97c08957f49 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -64,11 +64,7 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
64 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); 64 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
65#endif 65#endif
66 66
67 s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); 67 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
68 s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
69 s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
70 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
71 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
72 68
73 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); 69 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
74} 70}
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 8090403eec0f..899a8cc011ff 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -290,7 +290,7 @@ static void __init s5p_clockevent_init(void)
290 setup_irq(irq_number, &s5p_clock_event_irq); 290 setup_irq(irq_number, &s5p_clock_event_irq);
291} 291}
292 292
293static cycle_t s5p_timer_read(struct clocksource *cs) 293static void __iomem *s5p_timer_reg(void)
294{ 294{
295 unsigned long offset = 0; 295 unsigned long offset = 0;
296 296
@@ -308,10 +308,17 @@ static cycle_t s5p_timer_read(struct clocksource *cs)
308 308
309 default: 309 default:
310 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); 310 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
311 return 0; 311 return NULL;
312 } 312 }
313 313
314 return (cycle_t) ~__raw_readl(S3C_TIMERREG(offset)); 314 return S3C_TIMERREG(offset);
315}
316
317static cycle_t s5p_timer_read(struct clocksource *cs)
318{
319 void __iomem *reg = s5p_timer_reg();
320
321 return (cycle_t) (reg ? ~__raw_readl(reg) : 0);
315} 322}
316 323
317/* 324/*
@@ -325,53 +332,22 @@ static DEFINE_CLOCK_DATA(cd);
325 332
326unsigned long long notrace sched_clock(void) 333unsigned long long notrace sched_clock(void)
327{ 334{
328 u32 cyc; 335 void __iomem *reg = s5p_timer_reg();
329 unsigned long offset = 0;
330
331 switch (timer_source.source_id) {
332 case S5P_PWM0:
333 case S5P_PWM1:
334 case S5P_PWM2:
335 case S5P_PWM3:
336 offset = (timer_source.source_id * 0x0c) + 0x14;
337 break;
338
339 case S5P_PWM4:
340 offset = 0x40;
341 break;
342 336
343 default: 337 if (!reg)
344 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
345 return 0; 338 return 0;
346 }
347 339
348 cyc = ~__raw_readl(S3C_TIMERREG(offset)); 340 return cyc_to_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
349 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
350} 341}
351 342
352static void notrace s5p_update_sched_clock(void) 343static void notrace s5p_update_sched_clock(void)
353{ 344{
354 u32 cyc; 345 void __iomem *reg = s5p_timer_reg();
355 unsigned long offset = 0;
356 346
357 switch (timer_source.source_id) { 347 if (!reg)
358 case S5P_PWM0: 348 return;
359 case S5P_PWM1:
360 case S5P_PWM2:
361 case S5P_PWM3:
362 offset = (timer_source.source_id * 0x0c) + 0x14;
363 break;
364
365 case S5P_PWM4:
366 offset = 0x40;
367 break;
368
369 default:
370 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
371 }
372 349
373 cyc = ~__raw_readl(S3C_TIMERREG(offset)); 350 update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
374 update_sched_clock(&cd, cyc, (u32)~0);
375} 351}
376 352
377struct clocksource time_clocksource = { 353struct clocksource time_clocksource = {
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index be72100b81b4..4d79519d19a4 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -8,6 +8,7 @@ config PLAT_SAMSUNG
8 bool 8 bool
9 depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P 9 depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
10 select NO_IOPORT 10 select NO_IOPORT
11 select GENERIC_IRQ_CHIP
11 default y 12 default y
12 help 13 help
13 Base platform code for all Samsung SoC based systems 14 Base platform code for all Samsung SoC based systems
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
index a90b53431b5b..5b9c42fd32d7 100644
--- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
@@ -10,4 +10,4 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); 13extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq);
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 7d6ed7263d57..ee48e12a1e72 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -18,8 +18,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
18 18
19/* uart setup */ 19/* uart setup */
20 20
21static unsigned int fifo_mask; 21unsigned int fifo_mask;
22static unsigned int fifo_max; 22unsigned int fifo_max;
23 23
24/* forward declerations */ 24/* forward declerations */
25 25
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 4d4e571af553..32582c0958e3 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -27,60 +27,6 @@
27/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] 27/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
28 * are consecutive when looking up the interrupt in the demux routines. 28 * are consecutive when looking up the interrupt in the demux routines.
29 */ 29 */
30
31static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
32{
33 struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
34 return uirq->regs;
35}
36
37static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
38{
39 return irq & 3;
40}
41
42static void s3c_irq_uart_mask(struct irq_data *data)
43{
44 void __iomem *regs = s3c_irq_uart_base(data);
45 unsigned int bit = s3c_irq_uart_bit(data->irq);
46 u32 reg;
47
48 reg = __raw_readl(regs + S3C64XX_UINTM);
49 reg |= (1 << bit);
50 __raw_writel(reg, regs + S3C64XX_UINTM);
51}
52
53static void s3c_irq_uart_maskack(struct irq_data *data)
54{
55 void __iomem *regs = s3c_irq_uart_base(data);
56 unsigned int bit = s3c_irq_uart_bit(data->irq);
57 u32 reg;
58
59 reg = __raw_readl(regs + S3C64XX_UINTM);
60 reg |= (1 << bit);
61 __raw_writel(reg, regs + S3C64XX_UINTM);
62 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
63}
64
65static void s3c_irq_uart_unmask(struct irq_data *data)
66{
67 void __iomem *regs = s3c_irq_uart_base(data);
68 unsigned int bit = s3c_irq_uart_bit(data->irq);
69 u32 reg;
70
71 reg = __raw_readl(regs + S3C64XX_UINTM);
72 reg &= ~(1 << bit);
73 __raw_writel(reg, regs + S3C64XX_UINTM);
74}
75
76static void s3c_irq_uart_ack(struct irq_data *data)
77{
78 void __iomem *regs = s3c_irq_uart_base(data);
79 unsigned int bit = s3c_irq_uart_bit(data->irq);
80
81 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
82}
83
84static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) 30static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
85{ 31{
86 struct s3c_uart_irq *uirq = desc->irq_data.handler_data; 32 struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
@@ -97,30 +43,25 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
97 generic_handle_irq(base + 3); 43 generic_handle_irq(base + 3);
98} 44}
99 45
100static struct irq_chip s3c_irq_uart = {
101 .name = "s3c-uart",
102 .irq_mask = s3c_irq_uart_mask,
103 .irq_unmask = s3c_irq_uart_unmask,
104 .irq_mask_ack = s3c_irq_uart_maskack,
105 .irq_ack = s3c_irq_uart_ack,
106};
107
108static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) 46static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
109{ 47{
110 void __iomem *reg_base = uirq->regs; 48 void __iomem *reg_base = uirq->regs;
111 unsigned int irq; 49 struct irq_chip_generic *gc;
112 int offs; 50 struct irq_chip_type *ct;
113 51
114 /* mask all interrupts at the start. */ 52 /* mask all interrupts at the start. */
115 __raw_writel(0xf, reg_base + S3C64XX_UINTM); 53 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
116 54
117 for (offs = 0; offs < 3; offs++) { 55 gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
118 irq = uirq->base_irq + offs; 56 handle_level_irq);
119 57 ct = gc->chip_types;
120 irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq); 58 ct->chip.irq_ack = irq_gc_ack;
121 irq_set_chip_data(irq, uirq); 59 ct->chip.irq_mask = irq_gc_mask_set_bit;
122 set_irq_flags(irq, IRQF_VALID); 60 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
123 } 61 ct->regs.ack = S3C64XX_UINTP;
62 ct->regs.mask = S3C64XX_UINTM;
63 irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
64 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
124 65
125 irq_set_handler_data(uirq->parent_irq, uirq); 66 irq_set_handler_data(uirq->parent_irq, uirq);
126 irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); 67 irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index d6ad66ab9290..a607546ddbd0 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -28,60 +28,43 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
28} 28}
29 29
30/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ 30/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
31 31static void s3c_irq_timer_ack(struct irq_data *d)
32static void s3c_irq_timer_mask(struct irq_data *data)
33{
34 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
35 u32 mask = (u32)data->chip_data;
36
37 reg &= 0x1f; /* mask out pending interrupts */
38 reg &= ~mask;
39 __raw_writel(reg, S3C64XX_TINT_CSTAT);
40}
41
42static void s3c_irq_timer_unmask(struct irq_data *data)
43{ 32{
44 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); 33 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
45 u32 mask = (u32)data->chip_data; 34 u32 mask = (1 << 5) << (d->irq - gc->irq_base);
46 35
47 reg &= 0x1f; /* mask out pending interrupts */ 36 irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
48 reg |= mask;
49 __raw_writel(reg, S3C64XX_TINT_CSTAT);
50} 37}
51 38
52static void s3c_irq_timer_ack(struct irq_data *data)
53{
54 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
55 u32 mask = (u32)data->chip_data;
56
57 reg &= 0x1f;
58 reg |= mask << 5;
59 __raw_writel(reg, S3C64XX_TINT_CSTAT);
60}
61
62static struct irq_chip s3c_irq_timer = {
63 .name = "s3c-timer",
64 .irq_mask = s3c_irq_timer_mask,
65 .irq_unmask = s3c_irq_timer_unmask,
66 .irq_ack = s3c_irq_timer_ack,
67};
68
69/** 39/**
70 * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ 40 * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
71 * @parent_irq: The parent IRQ on the VIC for the timer. 41 * @num: Number of timers to initialize
72 * @timer_irq: The IRQ to be used for the timer. 42 * @timer_irq: Base IRQ number to be used for the timers.
73 * 43 *
74 * Register the necessary IRQ chaining and support for the timer IRQs 44 * Register the necessary IRQ chaining and support for the timer IRQs
75 * chained of the VIC. 45 * chained of the VIC.
76 */ 46 */
77void __init s3c_init_vic_timer_irq(unsigned int parent_irq, 47void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
78 unsigned int timer_irq)
79{ 48{
49 unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
50 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
51 struct irq_chip_generic *s3c_tgc;
52 struct irq_chip_type *ct;
53 unsigned int i;
80 54
81 irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer); 55 s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
82 irq_set_handler_data(parent_irq, (void *)timer_irq); 56 S3C64XX_TINT_CSTAT, handle_level_irq);
57 ct = s3c_tgc->chip_types;
58 ct->chip.irq_mask = irq_gc_mask_clr_bit;
59 ct->chip.irq_unmask = irq_gc_mask_set_bit;
60 ct->chip.irq_ack = s3c_irq_timer_ack;
61 irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
62 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
63 /* Clear the upper bits of the mask_cache*/
64 s3c_tgc->mask_cache &= 0x1f;
83 65
84 irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq); 66 for (i = 0; i < num; i++, timer_irq++) {
85 irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); 67 irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
86 set_irq_flags(timer_irq, IRQF_VALID); 68 irq_set_handler_data(pirq[i], (void *)timer_irq);
69 }
87} 70}
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index bdbd7ec9cb6b..6fa474cb398e 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -903,6 +903,11 @@ void recalc_root_clocks(void)
903 spin_unlock_irqrestore(&clocks_lock, flags); 903 spin_unlock_irqrestore(&clocks_lock, flags);
904} 904}
905 905
906void __init clk_init(void)
907{
908 recalc_root_clocks();
909}
910
906#ifdef CONFIG_DEBUG_FS 911#ifdef CONFIG_DEBUG_FS
907/* 912/*
908 * debugfs support to trace clock tree hierarchy and attributes 913 * debugfs support to trace clock tree hierarchy and attributes
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index fcc0d0ad4a1f..0062bafef12d 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -224,6 +224,7 @@ struct clcd_rate_tbl {
224}; 224};
225 225
226/* platform specific clock functions */ 226/* platform specific clock functions */
227void __init clk_init(void);
227void clk_register(struct clk_lookup *cl); 228void clk_register(struct clk_lookup *cl);
228void recalc_root_clocks(void); 229void recalc_root_clocks(void);
229 230
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index dbb6e4fff79d..0c77e4298675 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -70,19 +70,6 @@ static void clockevent_set_mode(enum clock_event_mode mode,
70static int clockevent_next_event(unsigned long evt, 70static int clockevent_next_event(unsigned long evt,
71 struct clock_event_device *clk_event_dev); 71 struct clock_event_device *clk_event_dev);
72 72
73static cycle_t clocksource_read_cycles(struct clocksource *cs)
74{
75 return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
76}
77
78static struct clocksource clksrc = {
79 .name = "tmr1",
80 .rating = 200, /* its a pretty decent clock */
81 .read = clocksource_read_cycles,
82 .mask = 0xFFFF, /* 16 bits */
83 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
84};
85
86static void spear_clocksource_init(void) 73static void spear_clocksource_init(void)
87{ 74{
88 u32 tick_rate; 75 u32 tick_rate;
@@ -103,7 +90,8 @@ static void spear_clocksource_init(void)
103 writew(val, gpt_base + CR(CLKSRC)); 90 writew(val, gpt_base + CR(CLKSRC));
104 91
105 /* register the clocksource */ 92 /* register the clocksource */
106 clocksource_register_hz(&clksrc, tick_rate); 93 clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
94 200, 16, clocksource_mmio_readw_up);
107} 95}
108 96
109static struct clock_event_device clkevt = { 97static struct clock_event_device clkevt = {
diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig
deleted file mode 100644
index 2cf37c35951b..000000000000
--- a/arch/arm/plat-stmp3xxx/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
1if ARCH_STMP3XXX
2
3menu "Freescale STMP3xxx implementations"
4
5choice
6 prompt "Select STMP3xxx chip family"
7
8config ARCH_STMP37XX
9 bool "Freescale SMTP37xx"
10 select CPU_ARM926T
11 ---help---
12 STMP37xx refers to 3700 through 3769 chips
13
14config ARCH_STMP378X
15 bool "Freescale STMP378x"
16 select CPU_ARM926T
17 ---help---
18 STMP378x refers to 3780 through 3789 chips
19
20endchoice
21
22choice
23 prompt "Select STMP3xxx board type"
24
25config MACH_STMP37XX
26 depends on ARCH_STMP37XX
27 bool "Freescale STMP37xx development board"
28
29config MACH_STMP378X
30 depends on ARCH_STMP378X
31 bool "Freescale STMP378x development board"
32
33endchoice
34
35endmenu
36
37endif
diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile
deleted file mode 100644
index 31dd518f37a5..000000000000
--- a/arch/arm/plat-stmp3xxx/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4# Object file lists.
5obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
deleted file mode 100644
index 2e712e17ce72..000000000000
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ /dev/null
@@ -1,1134 +0,0 @@
1/*
2 * Clock manipulation routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/spinlock.h>
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clkdev.h>
29
30#include <asm/mach-types.h>
31#include <mach/platform.h>
32#include <mach/regs-clkctrl.h>
33
34#include "clock.h"
35
36static DEFINE_SPINLOCK(clocks_lock);
37
38static struct clk osc_24M;
39static struct clk pll_clk;
40static struct clk cpu_clk;
41static struct clk hclk;
42
43static int propagate_rate(struct clk *);
44
45static inline int clk_is_busy(struct clk *clk)
46{
47 return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
48}
49
50static inline int clk_good(struct clk *clk)
51{
52 return clk && !IS_ERR(clk) && clk->ops;
53}
54
55static int std_clk_enable(struct clk *clk)
56{
57 if (clk->enable_reg) {
58 u32 clk_reg = __raw_readl(clk->enable_reg);
59 if (clk->enable_negate)
60 clk_reg &= ~(1 << clk->enable_shift);
61 else
62 clk_reg |= (1 << clk->enable_shift);
63 __raw_writel(clk_reg, clk->enable_reg);
64 if (clk->enable_wait)
65 udelay(clk->enable_wait);
66 return 0;
67 } else
68 return -EINVAL;
69}
70
71static int std_clk_disable(struct clk *clk)
72{
73 if (clk->enable_reg) {
74 u32 clk_reg = __raw_readl(clk->enable_reg);
75 if (clk->enable_negate)
76 clk_reg |= (1 << clk->enable_shift);
77 else
78 clk_reg &= ~(1 << clk->enable_shift);
79 __raw_writel(clk_reg, clk->enable_reg);
80 return 0;
81 } else
82 return -EINVAL;
83}
84
85static int io_set_rate(struct clk *clk, u32 rate)
86{
87 u32 reg_frac, clkctrl_frac;
88 int i, ret = 0, mask = 0x1f;
89
90 clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
91
92 if (clkctrl_frac < 18 || clkctrl_frac > 35) {
93 ret = -EINVAL;
94 goto out;
95 }
96
97 reg_frac = __raw_readl(clk->scale_reg);
98 reg_frac &= ~(mask << clk->scale_shift);
99 __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
100 clk->scale_reg);
101 if (clk->busy_reg) {
102 for (i = 10000; i; i--)
103 if (!clk_is_busy(clk))
104 break;
105 if (!i)
106 ret = -ETIMEDOUT;
107 else
108 ret = 0;
109 }
110out:
111 return ret;
112}
113
114static long io_get_rate(struct clk *clk)
115{
116 long rate = clk->parent->rate * 18;
117 int mask = 0x1f;
118
119 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
120 clk->rate = rate;
121
122 return rate;
123}
124
125static long per_get_rate(struct clk *clk)
126{
127 long rate = clk->parent->rate;
128 long div;
129 const int mask = 0xff;
130
131 if (clk->enable_reg &&
132 !(__raw_readl(clk->enable_reg) & clk->enable_shift))
133 clk->rate = 0;
134 else {
135 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
136 if (div)
137 rate /= div;
138 clk->rate = rate;
139 }
140
141 return clk->rate;
142}
143
144static int per_set_rate(struct clk *clk, u32 rate)
145{
146 int ret = -EINVAL;
147 int div = (clk->parent->rate + rate - 1) / rate;
148 u32 reg_frac;
149 const int mask = 0xff;
150 int try = 10;
151 int i = -1;
152
153 if (div == 0 || div > mask)
154 goto out;
155
156 reg_frac = __raw_readl(clk->scale_reg);
157 reg_frac &= ~(mask << clk->scale_shift);
158
159 while (try--) {
160 __raw_writel(reg_frac | (div << clk->scale_shift),
161 clk->scale_reg);
162
163 if (clk->busy_reg) {
164 for (i = 10000; i; i--)
165 if (!clk_is_busy(clk))
166 break;
167 }
168 if (i)
169 break;
170 }
171
172 if (!i)
173 ret = -ETIMEDOUT;
174 else
175 ret = 0;
176
177out:
178 if (ret != 0)
179 printk(KERN_ERR "%s: error %d\n", __func__, ret);
180 return ret;
181}
182
183static long lcdif_get_rate(struct clk *clk)
184{
185 long rate = clk->parent->rate;
186 long div;
187 const int mask = 0xff;
188
189 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
190 if (div) {
191 rate /= div;
192 div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
193 BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
194 rate /= div;
195 }
196 clk->rate = rate;
197
198 return rate;
199}
200
201static int lcdif_set_rate(struct clk *clk, u32 rate)
202{
203 int ret = 0;
204 /*
205 * On 3700, we can get most timings exact by modifying ref_pix
206 * and the divider, but keeping the phase timings at 1 (2
207 * phases per cycle).
208 *
209 * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
210 * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
211 *
212 * ns_cycle >= 2*18e3/(18*480) = 25/6
213 * ns_cycle <= 2*35e3/(18*480) = 875/108
214 *
215 * Multiply the ns_cycle by 'div' to lengthen it until it fits the
216 * bounds. This is the divider we'll use after ref_pix.
217 *
218 * 6 * ns_cycle >= 25 * div
219 * 108 * ns_cycle <= 875 * div
220 */
221 u32 ns_cycle = 1000000 / rate;
222 u32 div, reg_val;
223 u32 lowest_result = (u32) -1;
224 u32 lowest_div = 0, lowest_fracdiv = 0;
225
226 for (div = 1; div < 256; ++div) {
227 u32 fracdiv;
228 u32 ps_result;
229 int lower_bound = 6 * ns_cycle >= 25 * div;
230 int upper_bound = 108 * ns_cycle <= 875 * div;
231 if (!lower_bound)
232 break;
233 if (!upper_bound)
234 continue;
235 /*
236 * Found a matching div. Calculate fractional divider needed,
237 * rounded up.
238 */
239 fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
240 ns_cycle + 1000 * div - 1) /
241 (1000 * div);
242 if (fracdiv < 18 || fracdiv > 35) {
243 ret = -EINVAL;
244 goto out;
245 }
246 /* Calculate the actual cycle time this results in */
247 ps_result = 6250 * div * fracdiv / 27;
248
249 /* Use the fastest result that doesn't break ns_cycle */
250 if (ps_result <= lowest_result) {
251 lowest_result = ps_result;
252 lowest_div = div;
253 lowest_fracdiv = fracdiv;
254 }
255 }
256
257 if (div >= 256 || lowest_result == (u32) -1) {
258 ret = -EINVAL;
259 goto out;
260 }
261 pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
262 "PIXCLK=%uMHz cycle=%u.%03uns\n",
263 lowest_fracdiv, lowest_div,
264 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
265 lowest_result / 1000, lowest_result % 1000);
266
267 /* Program ref_pix phase fractional divider */
268 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
269 reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
270 reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
271 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
272
273 /* Ungate PFD */
274 stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
275 REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
276
277 /* Program pix divider */
278 reg_val = __raw_readl(clk->scale_reg);
279 reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
280 reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
281 __raw_writel(reg_val, clk->scale_reg);
282
283 /* Wait for divider update */
284 if (clk->busy_reg) {
285 int i;
286 for (i = 10000; i; i--)
287 if (!clk_is_busy(clk))
288 break;
289 if (!i) {
290 ret = -ETIMEDOUT;
291 goto out;
292 }
293 }
294
295 /* Switch to ref_pix source */
296 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
297 reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
298 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
299
300out:
301 return ret;
302}
303
304
305static int cpu_set_rate(struct clk *clk, u32 rate)
306{
307 u32 reg_val;
308
309 if (rate < 24000)
310 return -EINVAL;
311 else if (rate == 24000) {
312 /* switch to the 24M source */
313 clk_set_parent(clk, &osc_24M);
314 } else {
315 int i;
316 u32 clkctrl_cpu = 1;
317 u32 c = clkctrl_cpu;
318 u32 clkctrl_frac = 1;
319 u32 val;
320 for ( ; c < 0x40; c++) {
321 u32 f = (pll_clk.rate*18/c + rate/2) / rate;
322 int s1, s2;
323
324 if (f < 18 || f > 35)
325 continue;
326 s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
327 s2 = pll_clk.rate*18/c/f - rate;
328 pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
329 if (abs(s1) > abs(s2)) {
330 clkctrl_cpu = c;
331 clkctrl_frac = f;
332 }
333 if (s2 == 0)
334 break;
335 };
336 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
337 clkctrl_cpu, clkctrl_frac);
338 if (c == 0x40) {
339 int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
340 rate;
341 if (abs(d) > 100 ||
342 clkctrl_frac < 18 || clkctrl_frac > 35)
343 return -EINVAL;
344 }
345
346 /* 4.6.2 */
347 val = __raw_readl(clk->scale_reg);
348 val &= ~(0x3f << clk->scale_shift);
349 val |= clkctrl_frac;
350 clk_set_parent(clk, &osc_24M);
351 udelay(10);
352 __raw_writel(val, clk->scale_reg);
353 /* ungate */
354 __raw_writel(1<<7, clk->scale_reg + 8);
355 /* write clkctrl_cpu */
356 clk->saved_div = clkctrl_cpu;
357
358 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
359 reg_val &= ~0x3F;
360 reg_val |= clkctrl_cpu;
361 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
362
363 for (i = 10000; i; i--)
364 if (!clk_is_busy(clk))
365 break;
366 if (!i) {
367 printk(KERN_ERR "couldn't set up CPU divisor\n");
368 return -ETIMEDOUT;
369 }
370 clk_set_parent(clk, &pll_clk);
371 clk->saved_div = 0;
372 udelay(10);
373 }
374 return 0;
375}
376
377static long cpu_get_rate(struct clk *clk)
378{
379 long rate = clk->parent->rate * 18;
380
381 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
382 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
383 rate = ((rate + 9) / 10) * 10;
384 clk->rate = rate;
385
386 return rate;
387}
388
389static long cpu_round_rate(struct clk *clk, u32 rate)
390{
391 unsigned long r = 0;
392
393 if (rate <= 24000)
394 r = 24000;
395 else {
396 u32 clkctrl_cpu = 1;
397 u32 clkctrl_frac;
398 do {
399 clkctrl_frac =
400 (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
401 if (clkctrl_frac > 35)
402 continue;
403 if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
404 rate / 10)
405 break;
406 } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate);
407 if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
408 clkctrl_cpu--;
409 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
410 clkctrl_cpu, clkctrl_frac);
411 if (clkctrl_frac < 18)
412 clkctrl_frac = 18;
413 if (clkctrl_frac > 35)
414 clkctrl_frac = 35;
415
416 r = pll_clk.rate * 18;
417 r /= clkctrl_frac;
418 r /= clkctrl_cpu;
419 r = 10 * ((r + 9) / 10);
420 }
421 return r;
422}
423
424static long emi_get_rate(struct clk *clk)
425{
426 long rate = clk->parent->rate * 18;
427
428 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
429 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
430 clk->rate = rate;
431
432 return rate;
433}
434
435static int clkseq_set_parent(struct clk *clk, struct clk *parent)
436{
437 int ret = -EINVAL;
438 int shift = 8;
439
440 /* bypass? */
441 if (parent == &osc_24M)
442 shift = 4;
443
444 if (clk->bypass_reg) {
445#ifdef CONFIG_ARCH_STMP378X
446 u32 hbus_val, cpu_val;
447
448 if (clk == &cpu_clk && shift == 4) {
449 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
450 HW_CLKCTRL_HBUS);
451 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
452 HW_CLKCTRL_CPU);
453
454 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
455 BM_CLKCTRL_HBUS_DIV);
456 clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
457 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
458 cpu_val |= 1;
459
460 if (machine_is_stmp378x()) {
461 __raw_writel(hbus_val,
462 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
463 __raw_writel(cpu_val,
464 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
465 hclk.rate = 0;
466 }
467 } else if (clk == &cpu_clk && shift == 8) {
468 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
469 HW_CLKCTRL_HBUS);
470 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
471 HW_CLKCTRL_CPU);
472 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
473 BM_CLKCTRL_HBUS_DIV);
474 hbus_val |= 2;
475 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
476 if (clk->saved_div)
477 cpu_val |= clk->saved_div;
478 else
479 cpu_val |= 2;
480
481 if (machine_is_stmp378x()) {
482 __raw_writel(hbus_val,
483 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
484 __raw_writel(cpu_val,
485 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
486 hclk.rate = 0;
487 }
488 }
489#endif
490 __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
491
492 ret = 0;
493 }
494
495 return ret;
496}
497
498static int hbus_set_rate(struct clk *clk, u32 rate)
499{
500 u8 div = 0;
501 int is_frac = 0;
502 u32 clkctrl_hbus;
503 struct clk *parent = clk->parent;
504
505 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
506 parent->rate);
507
508 if (rate > parent->rate)
509 return -EINVAL;
510
511 if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
512 parent->rate / rate < 32) {
513 pr_debug("%s: switching to fractional mode\n", __func__);
514 is_frac = 1;
515 }
516
517 if (is_frac)
518 div = (32 * rate + parent->rate / 2) / parent->rate;
519 else
520 div = (parent->rate + rate - 1) / rate;
521 pr_debug("%s: div calculated is %d\n", __func__, div);
522 if (!div || div > 0x1f)
523 return -EINVAL;
524
525 clk_set_parent(&cpu_clk, &osc_24M);
526 udelay(10);
527 clkctrl_hbus = __raw_readl(clk->scale_reg);
528 clkctrl_hbus &= ~0x3f;
529 clkctrl_hbus |= div;
530 clkctrl_hbus |= (is_frac << 5);
531
532 __raw_writel(clkctrl_hbus, clk->scale_reg);
533 if (clk->busy_reg) {
534 int i;
535 for (i = 10000; i; i--)
536 if (!clk_is_busy(clk))
537 break;
538 if (!i) {
539 printk(KERN_ERR "couldn't set up CPU divisor\n");
540 return -ETIMEDOUT;
541 }
542 }
543 clk_set_parent(&cpu_clk, &pll_clk);
544 __raw_writel(clkctrl_hbus, clk->scale_reg);
545 udelay(10);
546 return 0;
547}
548
549static long hbus_get_rate(struct clk *clk)
550{
551 long rate = clk->parent->rate;
552
553 if (__raw_readl(clk->scale_reg) & 0x20) {
554 rate *= __raw_readl(clk->scale_reg) & 0x1f;
555 rate /= 32;
556 } else
557 rate /= __raw_readl(clk->scale_reg) & 0x1f;
558 clk->rate = rate;
559
560 return rate;
561}
562
563static int xbus_set_rate(struct clk *clk, u32 rate)
564{
565 u16 div = 0;
566 u32 clkctrl_xbus;
567
568 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
569 clk->parent->rate);
570
571 div = (clk->parent->rate + rate - 1) / rate;
572 pr_debug("%s: div calculated is %d\n", __func__, div);
573 if (!div || div > 0x3ff)
574 return -EINVAL;
575
576 clkctrl_xbus = __raw_readl(clk->scale_reg);
577 clkctrl_xbus &= ~0x3ff;
578 clkctrl_xbus |= div;
579 __raw_writel(clkctrl_xbus, clk->scale_reg);
580 if (clk->busy_reg) {
581 int i;
582 for (i = 10000; i; i--)
583 if (!clk_is_busy(clk))
584 break;
585 if (!i) {
586 printk(KERN_ERR "couldn't set up xbus divisor\n");
587 return -ETIMEDOUT;
588 }
589 }
590 return 0;
591}
592
593static long xbus_get_rate(struct clk *clk)
594{
595 long rate = clk->parent->rate;
596
597 rate /= __raw_readl(clk->scale_reg) & 0x3ff;
598 clk->rate = rate;
599
600 return rate;
601}
602
603
604/* Clock ops */
605
606static struct clk_ops std_ops = {
607 .enable = std_clk_enable,
608 .disable = std_clk_disable,
609 .get_rate = per_get_rate,
610 .set_rate = per_set_rate,
611 .set_parent = clkseq_set_parent,
612};
613
614static struct clk_ops min_ops = {
615 .enable = std_clk_enable,
616 .disable = std_clk_disable,
617};
618
619static struct clk_ops cpu_ops = {
620 .enable = std_clk_enable,
621 .disable = std_clk_disable,
622 .get_rate = cpu_get_rate,
623 .set_rate = cpu_set_rate,
624 .round_rate = cpu_round_rate,
625 .set_parent = clkseq_set_parent,
626};
627
628static struct clk_ops io_ops = {
629 .enable = std_clk_enable,
630 .disable = std_clk_disable,
631 .get_rate = io_get_rate,
632 .set_rate = io_set_rate,
633};
634
635static struct clk_ops hbus_ops = {
636 .get_rate = hbus_get_rate,
637 .set_rate = hbus_set_rate,
638};
639
640static struct clk_ops xbus_ops = {
641 .get_rate = xbus_get_rate,
642 .set_rate = xbus_set_rate,
643};
644
645static struct clk_ops lcdif_ops = {
646 .enable = std_clk_enable,
647 .disable = std_clk_disable,
648 .get_rate = lcdif_get_rate,
649 .set_rate = lcdif_set_rate,
650 .set_parent = clkseq_set_parent,
651};
652
653static struct clk_ops emi_ops = {
654 .get_rate = emi_get_rate,
655};
656
657/* List of on-chip clocks */
658
659static struct clk osc_24M = {
660 .flags = FIXED_RATE | ENABLED,
661 .rate = 24000,
662};
663
664static struct clk pll_clk = {
665 .parent = &osc_24M,
666 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
667 .enable_shift = 16,
668 .enable_wait = 10,
669 .flags = FIXED_RATE | ENABLED,
670 .rate = 480000,
671 .ops = &min_ops,
672};
673
674static struct clk cpu_clk = {
675 .parent = &pll_clk,
676 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
677 .scale_shift = 0,
678 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
679 .bypass_shift = 7,
680 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
681 .busy_bit = 28,
682 .flags = RATE_PROPAGATES | ENABLED,
683 .ops = &cpu_ops,
684};
685
686static struct clk io_clk = {
687 .parent = &pll_clk,
688 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
689 .enable_shift = 31,
690 .enable_negate = 1,
691 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
692 .scale_shift = 24,
693 .flags = RATE_PROPAGATES | ENABLED,
694 .ops = &io_ops,
695};
696
697static struct clk hclk = {
698 .parent = &cpu_clk,
699 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
700 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
701 .bypass_shift = 7,
702 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
703 .busy_bit = 29,
704 .flags = RATE_PROPAGATES | ENABLED,
705 .ops = &hbus_ops,
706};
707
708static struct clk xclk = {
709 .parent = &osc_24M,
710 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
711 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
712 .busy_bit = 31,
713 .flags = RATE_PROPAGATES | ENABLED,
714 .ops = &xbus_ops,
715};
716
717static struct clk uart_clk = {
718 .parent = &xclk,
719 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
720 .enable_shift = 31,
721 .enable_negate = 1,
722 .flags = ENABLED,
723 .ops = &min_ops,
724};
725
726static struct clk audio_clk = {
727 .parent = &xclk,
728 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
729 .enable_shift = 30,
730 .enable_negate = 1,
731 .ops = &min_ops,
732};
733
734static struct clk pwm_clk = {
735 .parent = &xclk,
736 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
737 .enable_shift = 29,
738 .enable_negate = 1,
739 .ops = &min_ops,
740};
741
742static struct clk dri_clk = {
743 .parent = &xclk,
744 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
745 .enable_shift = 28,
746 .enable_negate = 1,
747 .ops = &min_ops,
748};
749
750static struct clk digctl_clk = {
751 .parent = &xclk,
752 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
753 .enable_shift = 27,
754 .enable_negate = 1,
755 .ops = &min_ops,
756};
757
758static struct clk timer_clk = {
759 .parent = &xclk,
760 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
761 .enable_shift = 26,
762 .enable_negate = 1,
763 .flags = ENABLED,
764 .ops = &min_ops,
765};
766
767static struct clk lcdif_clk = {
768 .parent = &pll_clk,
769 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
770 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
771 .busy_bit = 29,
772 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
773 .enable_shift = 31,
774 .enable_negate = 1,
775 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
776 .bypass_shift = 1,
777 .flags = NEEDS_SET_PARENT,
778 .ops = &lcdif_ops,
779};
780
781static struct clk ssp_clk = {
782 .parent = &io_clk,
783 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
784 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
785 .busy_bit = 29,
786 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
787 .enable_shift = 31,
788 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
789 .bypass_shift = 5,
790 .enable_negate = 1,
791 .flags = NEEDS_SET_PARENT,
792 .ops = &std_ops,
793};
794
795static struct clk gpmi_clk = {
796 .parent = &io_clk,
797 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
798 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
799 .busy_bit = 29,
800 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
801 .enable_shift = 31,
802 .enable_negate = 1,
803 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
804 .bypass_shift = 4,
805 .flags = NEEDS_SET_PARENT,
806 .ops = &std_ops,
807};
808
809static struct clk spdif_clk = {
810 .parent = &pll_clk,
811 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
812 .enable_shift = 31,
813 .enable_negate = 1,
814 .ops = &min_ops,
815};
816
817static struct clk emi_clk = {
818 .parent = &pll_clk,
819 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
820 .enable_shift = 31,
821 .enable_negate = 1,
822 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
823 .scale_shift = 8,
824 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
825 .busy_bit = 28,
826 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
827 .bypass_shift = 6,
828 .flags = ENABLED,
829 .ops = &emi_ops,
830};
831
832static struct clk ir_clk = {
833 .parent = &io_clk,
834 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
835 .enable_shift = 31,
836 .enable_negate = 1,
837 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
838 .bypass_shift = 3,
839 .ops = &min_ops,
840};
841
842static struct clk saif_clk = {
843 .parent = &pll_clk,
844 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
845 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
846 .busy_bit = 29,
847 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
848 .enable_shift = 31,
849 .enable_negate = 1,
850 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
851 .bypass_shift = 0,
852 .ops = &std_ops,
853};
854
855static struct clk usb_clk = {
856 .parent = &pll_clk,
857 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
858 .enable_shift = 18,
859 .enable_negate = 1,
860 .ops = &min_ops,
861};
862
863/* list of all the clocks */
864static struct clk_lookup onchip_clks[] = {
865 {
866 .con_id = "osc_24M",
867 .clk = &osc_24M,
868 }, {
869 .con_id = "pll",
870 .clk = &pll_clk,
871 }, {
872 .con_id = "cpu",
873 .clk = &cpu_clk,
874 }, {
875 .con_id = "hclk",
876 .clk = &hclk,
877 }, {
878 .con_id = "xclk",
879 .clk = &xclk,
880 }, {
881 .con_id = "io",
882 .clk = &io_clk,
883 }, {
884 .con_id = "uart",
885 .clk = &uart_clk,
886 }, {
887 .con_id = "audio",
888 .clk = &audio_clk,
889 }, {
890 .con_id = "pwm",
891 .clk = &pwm_clk,
892 }, {
893 .con_id = "dri",
894 .clk = &dri_clk,
895 }, {
896 .con_id = "digctl",
897 .clk = &digctl_clk,
898 }, {
899 .con_id = "timer",
900 .clk = &timer_clk,
901 }, {
902 .con_id = "lcdif",
903 .clk = &lcdif_clk,
904 }, {
905 .con_id = "ssp",
906 .clk = &ssp_clk,
907 }, {
908 .con_id = "gpmi",
909 .clk = &gpmi_clk,
910 }, {
911 .con_id = "spdif",
912 .clk = &spdif_clk,
913 }, {
914 .con_id = "emi",
915 .clk = &emi_clk,
916 }, {
917 .con_id = "ir",
918 .clk = &ir_clk,
919 }, {
920 .con_id = "saif",
921 .clk = &saif_clk,
922 }, {
923 .con_id = "usb",
924 .clk = &usb_clk,
925 },
926};
927
928static int __init propagate_rate(struct clk *clk)
929{
930 struct clk_lookup *cl;
931
932 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
933 cl++) {
934 if (unlikely(!clk_good(cl->clk)))
935 continue;
936 if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
937 cl->clk->ops->get_rate(cl->clk);
938 if (cl->clk->flags & RATE_PROPAGATES)
939 propagate_rate(cl->clk);
940 }
941 }
942
943 return 0;
944}
945
946/* Exported API */
947unsigned long clk_get_rate(struct clk *clk)
948{
949 if (unlikely(!clk_good(clk)))
950 return 0;
951
952 if (clk->rate != 0)
953 return clk->rate;
954
955 if (clk->ops->get_rate != NULL)
956 return clk->ops->get_rate(clk);
957
958 return clk_get_rate(clk->parent);
959}
960EXPORT_SYMBOL(clk_get_rate);
961
962long clk_round_rate(struct clk *clk, unsigned long rate)
963{
964 if (unlikely(!clk_good(clk)))
965 return 0;
966
967 if (clk->ops->round_rate)
968 return clk->ops->round_rate(clk, rate);
969
970 return 0;
971}
972EXPORT_SYMBOL(clk_round_rate);
973
974static inline int close_enough(long rate1, long rate2)
975{
976 return rate1 && !((rate2 - rate1) * 1000 / rate1);
977}
978
979int clk_set_rate(struct clk *clk, unsigned long rate)
980{
981 int ret = -EINVAL;
982
983 if (unlikely(!clk_good(clk)))
984 goto out;
985
986 if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
987 goto out;
988
989 else if (!close_enough(clk->rate, rate)) {
990 ret = clk->ops->set_rate(clk, rate);
991 if (ret < 0)
992 goto out;
993 clk->rate = rate;
994 if (clk->flags & RATE_PROPAGATES)
995 propagate_rate(clk);
996 } else
997 ret = 0;
998
999out:
1000 return ret;
1001}
1002EXPORT_SYMBOL(clk_set_rate);
1003
1004int clk_enable(struct clk *clk)
1005{
1006 unsigned long clocks_flags;
1007
1008 if (unlikely(!clk_good(clk)))
1009 return -EINVAL;
1010
1011 if (clk->parent)
1012 clk_enable(clk->parent);
1013
1014 spin_lock_irqsave(&clocks_lock, clocks_flags);
1015
1016 clk->usage++;
1017 if (clk->ops && clk->ops->enable)
1018 clk->ops->enable(clk);
1019
1020 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1021 return 0;
1022}
1023EXPORT_SYMBOL(clk_enable);
1024
1025static void local_clk_disable(struct clk *clk)
1026{
1027 if (unlikely(!clk_good(clk)))
1028 return;
1029
1030 if (clk->usage == 0 && clk->ops->disable)
1031 clk->ops->disable(clk);
1032
1033 if (clk->parent)
1034 local_clk_disable(clk->parent);
1035}
1036
1037void clk_disable(struct clk *clk)
1038{
1039 unsigned long clocks_flags;
1040
1041 if (unlikely(!clk_good(clk)))
1042 return;
1043
1044 spin_lock_irqsave(&clocks_lock, clocks_flags);
1045
1046 if ((--clk->usage) == 0 && clk->ops->disable)
1047 clk->ops->disable(clk);
1048
1049 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1050 if (clk->parent)
1051 clk_disable(clk->parent);
1052}
1053EXPORT_SYMBOL(clk_disable);
1054
1055/* Some additional API */
1056int clk_set_parent(struct clk *clk, struct clk *parent)
1057{
1058 int ret = -ENODEV;
1059 unsigned long clocks_flags;
1060
1061 if (unlikely(!clk_good(clk)))
1062 goto out;
1063
1064 if (!clk->ops->set_parent)
1065 goto out;
1066
1067 spin_lock_irqsave(&clocks_lock, clocks_flags);
1068
1069 ret = clk->ops->set_parent(clk, parent);
1070 if (!ret) {
1071 /* disable if usage count is 0 */
1072 local_clk_disable(parent);
1073
1074 parent->usage += clk->usage;
1075 clk->parent->usage -= clk->usage;
1076
1077 /* disable if new usage count is 0 */
1078 local_clk_disable(clk->parent);
1079
1080 clk->parent = parent;
1081 }
1082 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1083
1084out:
1085 return ret;
1086}
1087EXPORT_SYMBOL(clk_set_parent);
1088
1089struct clk *clk_get_parent(struct clk *clk)
1090{
1091 if (unlikely(!clk_good(clk)))
1092 return NULL;
1093 return clk->parent;
1094}
1095EXPORT_SYMBOL(clk_get_parent);
1096
1097static int __init clk_init(void)
1098{
1099 struct clk_lookup *cl;
1100 struct clk_ops *ops;
1101
1102 spin_lock_init(&clocks_lock);
1103
1104 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
1105 cl++) {
1106 if (cl->clk->flags & ENABLED)
1107 clk_enable(cl->clk);
1108 else
1109 local_clk_disable(cl->clk);
1110
1111 ops = cl->clk->ops;
1112
1113 if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
1114 ops && ops->set_rate)
1115 ops->set_rate(cl->clk, cl->clk->rate);
1116
1117 if (cl->clk->flags & FIXED_RATE) {
1118 if (cl->clk->flags & RATE_PROPAGATES)
1119 propagate_rate(cl->clk);
1120 } else {
1121 if (ops && ops->get_rate)
1122 ops->get_rate(cl->clk);
1123 }
1124
1125 if (cl->clk->flags & NEEDS_SET_PARENT) {
1126 if (ops && ops->set_parent)
1127 ops->set_parent(cl->clk, cl->clk->parent);
1128 }
1129 }
1130 clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
1131 return 0;
1132}
1133
1134arch_initcall(clk_init);
diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h
deleted file mode 100644
index a6611e1a3510..000000000000
--- a/arch/arm/plat-stmp3xxx/clock.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Clock control driver for Freescale STMP37XX/STMP378X - internal header file
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
19#define __ARCH_ARM_STMX3XXX_CLOCK_H__
20
21#ifndef __ASSEMBLER__
22
23struct clk_ops {
24 int (*enable) (struct clk *);
25 int (*disable) (struct clk *);
26 long (*get_rate) (struct clk *);
27 long (*round_rate) (struct clk *, u32);
28 int (*set_rate) (struct clk *, u32);
29 int (*set_parent) (struct clk *, struct clk *);
30};
31
32struct clk {
33 struct clk *parent;
34 u32 rate;
35 u32 flags;
36 u8 scale_shift;
37 u8 enable_shift;
38 u8 bypass_shift;
39 u8 busy_bit;
40 s8 usage;
41 int enable_wait;
42 int enable_negate;
43 u32 saved_div;
44 void __iomem *enable_reg;
45 void __iomem *scale_reg;
46 void __iomem *bypass_reg;
47 void __iomem *busy_reg;
48 struct clk_ops *ops;
49};
50
51#endif /* __ASSEMBLER__ */
52
53/* Flags */
54#define RATE_PROPAGATES (1<<0)
55#define NEEDS_INITIALIZATION (1<<1)
56#define PARENT_SET_RATE (1<<2)
57#define FIXED_RATE (1<<3)
58#define ENABLED (1<<4)
59#define NEEDS_SET_PARENT (1<<5)
60
61#endif
diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c
deleted file mode 100644
index 37b8a09148a4..000000000000
--- a/arch/arm/plat-stmp3xxx/core.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X core routines
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21
22#include <mach/stmp3xxx.h>
23#include <mach/platform.h>
24#include <mach/dma.h>
25#include <mach/regs-clkctrl.h>
26
27static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
28{
29 u32 c;
30 int timeout;
31
32 /* the process of software reset of IP block is done
33 in several steps:
34
35 - clear SFTRST and wait for block is enabled;
36 - clear clock gating (CLKGATE bit);
37 - set the SFTRST again and wait for block is in reset;
38 - clear SFTRST and wait for reset completion.
39 */
40 c = __raw_readl(hwreg);
41 c &= ~(1<<31); /* clear SFTRST */
42 __raw_writel(c, hwreg);
43 for (timeout = 1000000; timeout > 0; timeout--)
44 /* still in SFTRST state ? */
45 if ((__raw_readl(hwreg) & (1<<31)) == 0)
46 break;
47 if (timeout <= 0) {
48 printk(KERN_ERR"%s(%p): timeout when enabling\n",
49 __func__, hwreg);
50 return -ETIME;
51 }
52
53 c = __raw_readl(hwreg);
54 c &= ~(1<<30); /* clear CLKGATE */
55 __raw_writel(c, hwreg);
56
57 if (!just_enable) {
58 c = __raw_readl(hwreg);
59 c |= (1<<31); /* now again set SFTRST */
60 __raw_writel(c, hwreg);
61 for (timeout = 1000000; timeout > 0; timeout--)
62 /* poll until CLKGATE set */
63 if (__raw_readl(hwreg) & (1<<30))
64 break;
65 if (timeout <= 0) {
66 printk(KERN_ERR"%s(%p): timeout when resetting\n",
67 __func__, hwreg);
68 return -ETIME;
69 }
70
71 c = __raw_readl(hwreg);
72 c &= ~(1<<31); /* clear SFTRST */
73 __raw_writel(c, hwreg);
74 for (timeout = 1000000; timeout > 0; timeout--)
75 /* still in SFTRST state ? */
76 if ((__raw_readl(hwreg) & (1<<31)) == 0)
77 break;
78 if (timeout <= 0) {
79 printk(KERN_ERR"%s(%p): timeout when enabling "
80 "after reset\n", __func__, hwreg);
81 return -ETIME;
82 }
83
84 c = __raw_readl(hwreg);
85 c &= ~(1<<30); /* clear CLKGATE */
86 __raw_writel(c, hwreg);
87 }
88 for (timeout = 1000000; timeout > 0; timeout--)
89 /* still in SFTRST state ? */
90 if ((__raw_readl(hwreg) & (1<<30)) == 0)
91 break;
92
93 if (timeout <= 0) {
94 printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
95 __func__, hwreg);
96 return -ETIME;
97 }
98
99 return 0;
100}
101
102int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
103{
104 int try = 10;
105 int r;
106
107 while (try--) {
108 r = __stmp3xxx_reset_block(hwreg, just_enable);
109 if (!r)
110 break;
111 pr_debug("%s: try %d failed\n", __func__, 10 - try);
112 }
113 return r;
114}
115EXPORT_SYMBOL(stmp3xxx_reset_block);
116
117struct platform_device stmp3xxx_dbguart = {
118 .name = "stmp3xxx-dbguart",
119 .id = -1,
120};
121
122void __init stmp3xxx_init(void)
123{
124 /* Turn off auto-slow and other tricks */
125 stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
126
127 stmp3xxx_dma_init();
128}
diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c
deleted file mode 100644
index 68fed4b8746a..000000000000
--- a/arch/arm/plat-stmp3xxx/devices.c
+++ /dev/null
@@ -1,389 +0,0 @@
1/*
2* Freescale STMP37XX/STMP378X platform devices
3*
4* Embedded Alley Solutions, Inc <source@embeddedalley.com>
5*
6* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8*/
9
10/*
11* The code contained herein is licensed under the GNU General Public
12* License. You may obtain a copy of the GNU General Public License
13* Version 2 or later at the following locations:
14*
15* http://www.opensource.org/licenses/gpl-license.html
16* http://www.gnu.org/copyleft/gpl.html
17*/
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23
24#include <mach/dma.h>
25#include <mach/platform.h>
26#include <mach/stmp3xxx.h>
27#include <mach/regs-lcdif.h>
28#include <mach/regs-uartapp.h>
29#include <mach/regs-gpmi.h>
30#include <mach/regs-usbctrl.h>
31#include <mach/regs-ssp.h>
32#include <mach/regs-rtc.h>
33
34static u64 common_dmamask = DMA_BIT_MASK(32);
35
36static struct resource appuart_resources[] = {
37 {
38 .start = IRQ_UARTAPP_INTERNAL,
39 .end = IRQ_UARTAPP_INTERNAL,
40 .flags = IORESOURCE_IRQ,
41 }, {
42 .start = IRQ_UARTAPP_RX_DMA,
43 .end = IRQ_UARTAPP_RX_DMA,
44 .flags = IORESOURCE_IRQ,
45 }, {
46 .start = IRQ_UARTAPP_TX_DMA,
47 .end = IRQ_UARTAPP_TX_DMA,
48 .flags = IORESOURCE_IRQ,
49 }, {
50 .start = REGS_UARTAPP1_PHYS,
51 .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
52 .flags = IORESOURCE_MEM,
53 }, {
54 /* Rx DMA channel */
55 .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
56 .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
57 .flags = IORESOURCE_DMA,
58 }, {
59 /* Tx DMA channel */
60 .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
61 .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
62 .flags = IORESOURCE_DMA,
63 },
64};
65
66struct platform_device stmp3xxx_appuart = {
67 .name = "stmp3xxx-appuart",
68 .id = 0,
69 .resource = appuart_resources,
70 .num_resources = ARRAY_SIZE(appuart_resources),
71 .dev = {
72 .dma_mask = &common_dmamask,
73 .coherent_dma_mask = DMA_BIT_MASK(32),
74 },
75};
76
77struct platform_device stmp3xxx_watchdog = {
78 .name = "stmp3xxx_wdt",
79 .id = -1,
80};
81
82static struct resource ts_resource[] = {
83 {
84 .flags = IORESOURCE_IRQ,
85 .start = IRQ_TOUCH_DETECT,
86 .end = IRQ_TOUCH_DETECT,
87 }, {
88 .flags = IORESOURCE_IRQ,
89 .start = IRQ_LRADC_CH5,
90 .end = IRQ_LRADC_CH5,
91 },
92};
93
94struct platform_device stmp3xxx_touchscreen = {
95 .name = "stmp3xxx_ts",
96 .id = -1,
97 .resource = ts_resource,
98 .num_resources = ARRAY_SIZE(ts_resource),
99};
100
101/*
102* Keypad device
103*/
104struct platform_device stmp3xxx_keyboard = {
105 .name = "stmp3xxx-keyboard",
106 .id = -1,
107};
108
109static struct resource gpmi_resources[] = {
110 {
111 .flags = IORESOURCE_MEM,
112 .start = REGS_GPMI_PHYS,
113 .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
114 }, {
115 .flags = IORESOURCE_IRQ,
116 .start = IRQ_GPMI_DMA,
117 .end = IRQ_GPMI_DMA,
118 }, {
119 .flags = IORESOURCE_DMA,
120 .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
121 .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
122 },
123};
124
125struct platform_device stmp3xxx_gpmi = {
126 .name = "gpmi",
127 .id = -1,
128 .dev = {
129 .dma_mask = &common_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32),
131 },
132 .resource = gpmi_resources,
133 .num_resources = ARRAY_SIZE(gpmi_resources),
134};
135
136static struct resource mmc1_resource[] = {
137 {
138 .flags = IORESOURCE_MEM,
139 .start = REGS_SSP1_PHYS,
140 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
141 }, {
142 .flags = IORESOURCE_DMA,
143 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
144 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
145 }, {
146 .flags = IORESOURCE_IRQ,
147 .start = IRQ_SSP1_DMA,
148 .end = IRQ_SSP1_DMA,
149 }, {
150 .flags = IORESOURCE_IRQ,
151 .start = IRQ_SSP_ERROR,
152 .end = IRQ_SSP_ERROR,
153 },
154};
155
156struct platform_device stmp3xxx_mmc = {
157 .name = "stmp3xxx-mmc",
158 .id = 1,
159 .dev = {
160 .dma_mask = &common_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 },
163 .resource = mmc1_resource,
164 .num_resources = ARRAY_SIZE(mmc1_resource),
165};
166
167static struct resource usb_resources[] = {
168 {
169 .start = REGS_USBCTRL_PHYS,
170 .end = REGS_USBCTRL_PHYS + SZ_4K,
171 .flags = IORESOURCE_MEM,
172 }, {
173 .start = IRQ_USB_CTRL,
174 .end = IRQ_USB_CTRL,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179struct platform_device stmp3xxx_udc = {
180 .name = "fsl-usb2-udc",
181 .id = -1,
182 .dev = {
183 .dma_mask = &common_dmamask,
184 .coherent_dma_mask = DMA_BIT_MASK(32),
185 },
186 .resource = usb_resources,
187 .num_resources = ARRAY_SIZE(usb_resources),
188};
189
190struct platform_device stmp3xxx_ehci = {
191 .name = "fsl-ehci",
192 .id = -1,
193 .dev = {
194 .dma_mask = &common_dmamask,
195 .coherent_dma_mask = DMA_BIT_MASK(32),
196 },
197 .resource = usb_resources,
198 .num_resources = ARRAY_SIZE(usb_resources),
199};
200
201static struct resource rtc_resources[] = {
202 {
203 .start = REGS_RTC_PHYS,
204 .end = REGS_RTC_PHYS + REGS_RTC_SIZE,
205 .flags = IORESOURCE_MEM,
206 }, {
207 .start = IRQ_RTC_ALARM,
208 .end = IRQ_RTC_ALARM,
209 .flags = IORESOURCE_IRQ,
210 }, {
211 .start = IRQ_RTC_1MSEC,
212 .end = IRQ_RTC_1MSEC,
213 .flags = IORESOURCE_IRQ,
214 },
215};
216
217struct platform_device stmp3xxx_rtc = {
218 .name = "stmp3xxx-rtc",
219 .id = -1,
220 .resource = rtc_resources,
221 .num_resources = ARRAY_SIZE(rtc_resources),
222};
223
224static struct resource ssp1_resources[] = {
225 {
226 .start = REGS_SSP1_PHYS,
227 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .start = IRQ_SSP1_DMA,
231 .end = IRQ_SSP1_DMA,
232 .flags = IORESOURCE_IRQ,
233 }, {
234 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
235 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
236 .flags = IORESOURCE_DMA,
237 },
238};
239
240static struct resource ssp2_resources[] = {
241 {
242 .start = REGS_SSP2_PHYS,
243 .end = REGS_SSP2_PHYS + REGS_SSP_SIZE,
244 .flags = IORESOURCE_MEM,
245 }, {
246 .start = IRQ_SSP2_DMA,
247 .end = IRQ_SSP2_DMA,
248 .flags = IORESOURCE_IRQ,
249 }, {
250 .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
251 .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
252 .flags = IORESOURCE_DMA,
253 },
254};
255
256struct platform_device stmp3xxx_spi1 = {
257 .name = "stmp3xxx_ssp",
258 .id = 1,
259 .dev = {
260 .dma_mask = &common_dmamask,
261 .coherent_dma_mask = DMA_BIT_MASK(32),
262 },
263 .resource = ssp1_resources,
264 .num_resources = ARRAY_SIZE(ssp1_resources),
265};
266
267struct platform_device stmp3xxx_spi2 = {
268 .name = "stmp3xxx_ssp",
269 .id = 2,
270 .dev = {
271 .dma_mask = &common_dmamask,
272 .coherent_dma_mask = DMA_BIT_MASK(32),
273 },
274 .resource = ssp2_resources,
275 .num_resources = ARRAY_SIZE(ssp2_resources),
276};
277
278static struct resource fb_resource[] = {
279 {
280 .flags = IORESOURCE_IRQ,
281 .start = IRQ_LCDIF_DMA,
282 .end = IRQ_LCDIF_DMA,
283 }, {
284 .flags = IORESOURCE_IRQ,
285 .start = IRQ_LCDIF_ERROR,
286 .end = IRQ_LCDIF_ERROR,
287 }, {
288 .flags = IORESOURCE_MEM,
289 .start = REGS_LCDIF_PHYS,
290 .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
291 },
292};
293
294struct platform_device stmp3xxx_framebuffer = {
295 .name = "stmp3xxx-fb",
296 .id = -1,
297 .dev = {
298 .dma_mask = &common_dmamask,
299 .coherent_dma_mask = DMA_BIT_MASK(32),
300 },
301 .num_resources = ARRAY_SIZE(fb_resource),
302 .resource = fb_resource,
303};
304
305#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
306 static char *cmdline_device_##name; \
307 static int cmdline_device_##name##_setup(char *dev) \
308 { \
309 cmdline_device_##name = dev + 1; \
310 return 0; \
311 } \
312 __setup(#name, cmdline_device_##name##_setup); \
313 int stmp3xxx_##name##_device_register(void) \
314 { \
315 struct platform_device *d = NULL; \
316 if (!cmdline_device_##name || \
317 !strcmp(cmdline_device_##name, #dev1)) \
318 d = &stmp3xxx_##dev1; \
319 else if (!strcmp(cmdline_device_##name, #dev2)) \
320 d = &stmp3xxx_##dev2; \
321 else \
322 printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
323 #name, cmdline_device_##name); \
324 return d ? platform_device_register(d) : -ENOENT; \
325 }
326
327CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
328CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
329
330struct platform_device stmp3xxx_backlight = {
331 .name = "stmp3xxx-bl",
332 .id = -1,
333};
334
335struct platform_device stmp3xxx_rotdec = {
336 .name = "stmp3xxx-rotdec",
337 .id = -1,
338};
339
340struct platform_device stmp3xxx_persistent = {
341 .name = "stmp3xxx-persistent",
342 .id = -1,
343};
344
345struct platform_device stmp3xxx_dcp_bootstream = {
346 .name = "stmp3xxx-dcpboot",
347 .id = -1,
348 .dev = {
349 .dma_mask = &common_dmamask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
351 },
352};
353
354static struct resource dcp_resources[] = {
355 {
356 .start = IRQ_DCP_VMI,
357 .end = IRQ_DCP_VMI,
358 .flags = IORESOURCE_IRQ,
359 }, {
360 .start = IRQ_DCP,
361 .end = IRQ_DCP,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366struct platform_device stmp3xxx_dcp = {
367 .name = "stmp3xxx-dcp",
368 .id = -1,
369 .resource = dcp_resources,
370 .num_resources = ARRAY_SIZE(dcp_resources),
371 .dev = {
372 .dma_mask = &common_dmamask,
373 .coherent_dma_mask = DMA_BIT_MASK(32),
374 },
375};
376
377static struct resource battery_resource[] = {
378 {
379 .flags = IORESOURCE_IRQ,
380 .start = IRQ_VDD5V,
381 .end = IRQ_VDD5V,
382 },
383};
384
385struct platform_device stmp3xxx_battery = {
386 .name = "stmp3xxx-battery",
387 .resource = battery_resource,
388 .num_resources = ARRAY_SIZE(battery_resource),
389};
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
deleted file mode 100644
index b4dcf8c0477d..000000000000
--- a/arch/arm/plat-stmp3xxx/dma.c
+++ /dev/null
@@ -1,464 +0,0 @@
1/*
2 * DMA helper routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: dmitry pervushin <dpervushin@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/gfp.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/dmapool.h>
22#include <linux/sysdev.h>
23#include <linux/cpufreq.h>
24
25#include <asm/page.h>
26
27#include <mach/platform.h>
28#include <mach/dma.h>
29#include <mach/regs-apbx.h>
30#include <mach/regs-apbh.h>
31
32static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
33static const size_t pool_alignment = 8;
34static struct stmp3xxx_dma_user {
35 void *pool;
36 int inuse;
37 const char *name;
38} channels[MAX_DMA_CHANNELS];
39
40#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
41#define IS_USED(ch) (channels[ch].inuse)
42
43int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
44{
45 struct stmp3xxx_dma_user *user;
46 int err = 0;
47
48 user = channels + ch;
49 if (!IS_VALID_CHANNEL(ch)) {
50 err = -ENODEV;
51 goto out;
52 }
53 if (IS_USED(ch)) {
54 err = -EBUSY;
55 goto out;
56 }
57 /* Create a pool to allocate dma commands from */
58 user->pool = dma_pool_create(name, dev, pool_item_size,
59 pool_alignment, PAGE_SIZE);
60 if (user->pool == NULL) {
61 err = -ENOMEM;
62 goto out;
63 }
64 user->name = name;
65 user->inuse++;
66out:
67 return err;
68}
69EXPORT_SYMBOL(stmp3xxx_dma_request);
70
71int stmp3xxx_dma_release(int ch)
72{
73 struct stmp3xxx_dma_user *user = channels + ch;
74 int err = 0;
75
76 if (!IS_VALID_CHANNEL(ch)) {
77 err = -ENODEV;
78 goto out;
79 }
80 if (!IS_USED(ch)) {
81 err = -EBUSY;
82 goto out;
83 }
84 BUG_ON(user->pool == NULL);
85 dma_pool_destroy(user->pool);
86 user->inuse--;
87out:
88 return err;
89}
90EXPORT_SYMBOL(stmp3xxx_dma_release);
91
92int stmp3xxx_dma_read_semaphore(int channel)
93{
94 int sem = -1;
95
96 switch (STMP3XXX_DMA_BUS(channel)) {
97 case STMP3XXX_BUS_APBH:
98 sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
99 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
100 sem &= BM_APBH_CHn_SEMA_PHORE;
101 sem >>= BP_APBH_CHn_SEMA_PHORE;
102 break;
103
104 case STMP3XXX_BUS_APBX:
105 sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
106 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
107 sem &= BM_APBX_CHn_SEMA_PHORE;
108 sem >>= BP_APBX_CHn_SEMA_PHORE;
109 break;
110 default:
111 BUG();
112 }
113 return sem;
114}
115EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
116
117int stmp3xxx_dma_allocate_command(int channel,
118 struct stmp3xxx_dma_descriptor *descriptor)
119{
120 struct stmp3xxx_dma_user *user = channels + channel;
121 int err = 0;
122
123 if (!IS_VALID_CHANNEL(channel)) {
124 err = -ENODEV;
125 goto out;
126 }
127 if (!IS_USED(channel)) {
128 err = -EBUSY;
129 goto out;
130 }
131 if (descriptor == NULL) {
132 err = -EINVAL;
133 goto out;
134 }
135
136 /* Allocate memory for a command from the buffer */
137 descriptor->command =
138 dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
139
140 /* Check it worked */
141 if (!descriptor->command) {
142 err = -ENOMEM;
143 goto out;
144 }
145
146 memset(descriptor->command, 0, pool_item_size);
147out:
148 WARN_ON(err);
149 return err;
150}
151EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
152
153int stmp3xxx_dma_free_command(int channel,
154 struct stmp3xxx_dma_descriptor *descriptor)
155{
156 int err = 0;
157
158 if (!IS_VALID_CHANNEL(channel)) {
159 err = -ENODEV;
160 goto out;
161 }
162 if (!IS_USED(channel)) {
163 err = -EBUSY;
164 goto out;
165 }
166
167 /* Return the command memory to the pool */
168 dma_pool_free(channels[channel].pool, descriptor->command,
169 descriptor->handle);
170
171 /* Initialise descriptor so we're not tempted to use it */
172 descriptor->command = NULL;
173 descriptor->handle = 0;
174 descriptor->virtual_buf_ptr = NULL;
175 descriptor->next_descr = NULL;
176
177 WARN_ON(err);
178out:
179 return err;
180}
181EXPORT_SYMBOL(stmp3xxx_dma_free_command);
182
183void stmp3xxx_dma_go(int channel,
184 struct stmp3xxx_dma_descriptor *head, u32 semaphore)
185{
186 int ch = STMP3XXX_DMA_CHANNEL(channel);
187 void __iomem *c, *s;
188
189 switch (STMP3XXX_DMA_BUS(channel)) {
190 case STMP3XXX_BUS_APBH:
191 c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
192 s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
193 break;
194
195 case STMP3XXX_BUS_APBX:
196 c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
197 s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
198 break;
199
200 default:
201 return;
202 }
203
204 /* Set next command */
205 __raw_writel(head->handle, c);
206 /* Set counting semaphore (kicks off transfer). Assumes
207 peripheral has been set up correctly */
208 __raw_writel(semaphore, s);
209}
210EXPORT_SYMBOL(stmp3xxx_dma_go);
211
212int stmp3xxx_dma_running(int channel)
213{
214 switch (STMP3XXX_DMA_BUS(channel)) {
215 case STMP3XXX_BUS_APBH:
216 return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
217 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
218 BM_APBH_CHn_SEMA_PHORE;
219
220 case STMP3XXX_BUS_APBX:
221 return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
222 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
223 BM_APBX_CHn_SEMA_PHORE;
224 default:
225 BUG();
226 return 0;
227 }
228}
229EXPORT_SYMBOL(stmp3xxx_dma_running);
230
231/*
232 * Circular dma chain management
233 */
234void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
235{
236 int i;
237
238 for (i = 0; i < chain->total_count; i++)
239 stmp3xxx_dma_free_command(
240 STMP3XXX_DMA(chain->channel, chain->bus),
241 &chain->chain[i]);
242}
243EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
244
245int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
246 struct stmp3xxx_dma_descriptor descriptors[],
247 unsigned items)
248{
249 int i;
250 int err = 0;
251
252 if (items == 0)
253 return err;
254
255 for (i = 0; i < items; i++) {
256 err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
257 if (err) {
258 WARN_ON(err);
259 /*
260 * Couldn't allocate the whole chain.
261 * deallocate what has been allocated
262 */
263 if (i) {
264 do {
265 stmp3xxx_dma_free_command(ch,
266 &descriptors
267 [i]);
268 } while (i-- > 0);
269 }
270 return err;
271 }
272
273 /* link them! */
274 if (i > 0) {
275 descriptors[i - 1].next_descr = &descriptors[i];
276 descriptors[i - 1].command->next =
277 descriptors[i].handle;
278 }
279 }
280
281 /* make list circular */
282 descriptors[items - 1].next_descr = &descriptors[0];
283 descriptors[items - 1].command->next = descriptors[0].handle;
284
285 chain->total_count = items;
286 chain->chain = descriptors;
287 chain->free_index = 0;
288 chain->active_index = 0;
289 chain->cooked_index = 0;
290 chain->free_count = items;
291 chain->active_count = 0;
292 chain->cooked_count = 0;
293 chain->bus = STMP3XXX_DMA_BUS(ch);
294 chain->channel = STMP3XXX_DMA_CHANNEL(ch);
295 return err;
296}
297EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
298
299void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
300{
301 BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
302 chain->free_index = 0;
303 chain->active_index = 0;
304 chain->cooked_index = 0;
305 chain->free_count = chain->total_count;
306 chain->active_count = 0;
307 chain->cooked_count = 0;
308}
309EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
310
311void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
312 unsigned count)
313{
314 BUG_ON(chain->cooked_count < count);
315
316 chain->cooked_count -= count;
317 chain->cooked_index += count;
318 chain->cooked_index %= chain->total_count;
319 chain->free_count += count;
320}
321EXPORT_SYMBOL(stmp37xx_circ_advance_free);
322
323void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
324 unsigned count)
325{
326 void __iomem *c;
327 u32 mask_clr, mask;
328 BUG_ON(chain->free_count < count);
329
330 chain->free_count -= count;
331 chain->free_index += count;
332 chain->free_index %= chain->total_count;
333 chain->active_count += count;
334
335 switch (chain->bus) {
336 case STMP3XXX_BUS_APBH:
337 c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
338 mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
339 mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
340 break;
341 case STMP3XXX_BUS_APBX:
342 c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
343 mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
344 mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
345 break;
346 default:
347 BUG();
348 return;
349 }
350
351 /* Set counting semaphore (kicks off transfer). Assumes
352 peripheral has been set up correctly */
353 stmp3xxx_clearl(mask_clr, c);
354 stmp3xxx_setl(mask, c);
355}
356EXPORT_SYMBOL(stmp37xx_circ_advance_active);
357
358unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
359{
360 unsigned cooked;
361
362 cooked = chain->active_count -
363 stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
364
365 chain->active_count -= cooked;
366 chain->active_index += cooked;
367 chain->active_index %= chain->total_count;
368
369 chain->cooked_count += cooked;
370
371 return cooked;
372}
373EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
374
375void stmp3xxx_dma_set_alt_target(int channel, int function)
376{
377#if defined(CONFIG_ARCH_STMP37XX)
378 unsigned bits = 4;
379#elif defined(CONFIG_ARCH_STMP378X)
380 unsigned bits = 2;
381#else
382#error wrong arch
383#endif
384 int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
385 unsigned mask = (1<<bits) - 1;
386 void __iomem *c;
387
388 BUG_ON(function < 0 || function >= (1<<bits));
389 pr_debug("%s: channel = %d, using mask %x, "
390 "shift = %d\n", __func__, channel, mask, shift);
391
392 switch (STMP3XXX_DMA_BUS(channel)) {
393 case STMP3XXX_BUS_APBH:
394 c = REGS_APBH_BASE + HW_APBH_DEVSEL;
395 break;
396 case STMP3XXX_BUS_APBX:
397 c = REGS_APBX_BASE + HW_APBX_DEVSEL;
398 break;
399 default:
400 BUG();
401 }
402 stmp3xxx_clearl(mask << shift, c);
403 stmp3xxx_setl(mask << shift, c);
404}
405EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
406
407void stmp3xxx_dma_suspend(void)
408{
409 stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
410 stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
411}
412
413void stmp3xxx_dma_resume(void)
414{
415 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
416 REGS_APBH_BASE + HW_APBH_CTRL0);
417 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
418 REGS_APBX_BASE + HW_APBX_CTRL0);
419}
420
421#ifdef CONFIG_CPU_FREQ
422
423struct dma_notifier_block {
424 struct notifier_block nb;
425 void *data;
426};
427
428static int dma_cpufreq_notifier(struct notifier_block *self,
429 unsigned long phase, void *p)
430{
431 switch (phase) {
432 case CPUFREQ_POSTCHANGE:
433 stmp3xxx_dma_resume();
434 break;
435
436 case CPUFREQ_PRECHANGE:
437 stmp3xxx_dma_suspend();
438 break;
439
440 default:
441 break;
442 }
443
444 return NOTIFY_DONE;
445}
446
447static struct dma_notifier_block dma_cpufreq_nb = {
448 .nb = {
449 .notifier_call = dma_cpufreq_notifier,
450 },
451};
452#endif /* CONFIG_CPU_FREQ */
453
454void __init stmp3xxx_dma_init(void)
455{
456 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
457 REGS_APBH_BASE + HW_APBH_CTRL0);
458 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
459 REGS_APBX_BASE + HW_APBX_CTRL0);
460#ifdef CONFIG_CPU_FREQ
461 cpufreq_register_notifier(&dma_cpufreq_nb.nb,
462 CPUFREQ_TRANSITION_NOTIFIER);
463#endif /* CONFIG_CPU_FREQ */
464}
diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
deleted file mode 100644
index f9c39772d7c5..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#ifndef __ASM_MACH_CLKDEV_H
13#define __ASM_MACH_CLKDEV_H
14
15#define __clk_get(clk) ({ 1; })
16#define __clk_put(clk) do { } while (0)
17
18#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
deleted file mode 100644
index b4e205b95f2c..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/cputype.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X CPU type detection
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_CPU_H
19#define __ASM_PLAT_CPU_H
20
21#ifdef CONFIG_ARCH_STMP37XX
22#define cpu_is_stmp37xx() (1)
23#else
24#define cpu_is_stmp37xx() (0)
25#endif
26
27#ifdef CONFIG_ARCH_STMP378X
28#define cpu_is_stmp378x() (1)
29#else
30#define cpu_is_stmp378x() (0)
31#endif
32
33#endif /* __ASM_PLAT_CPU_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
deleted file mode 100644
index d3a0985c9681..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Debugging macro include header
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro addruart, rp, rv
20 mov \rp, #0x00070000
21 add \rv, \rp, #0xf0000000 @ virtual base
22 add \rp, \rp, #0x80000000 @ physical base
23 .endm
24
25 .macro senduart,rd,rx
26 strb \rd, [\rx, #0] @ data register at 0
27 .endm
28
29 .macro waituart,rd,rx
301001: ldr \rd, [\rx, #0x18] @ UARTFLG
31 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
32 bne 1001b
33 .endm
34
35 .macro busyuart,rd,rx
361001: ldr \rd, [\rx, #0x18] @ UARTFLG
37 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
38 bne 1001b
39 .endm
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
deleted file mode 100644
index 7c58557c6766..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/dma.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X DMA helper interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_DMA_H
19#define __ASM_PLAT_STMP3XXX_DMA_H
20
21#include <linux/platform_device.h>
22#include <linux/dmapool.h>
23
24#if !defined(MAX_PIO_WORDS)
25#define MAX_PIO_WORDS (15)
26#endif
27
28#define STMP3XXX_BUS_APBH 0
29#define STMP3XXX_BUS_APBX 1
30#define STMP3XXX_DMA_MAX_CHANNEL 16
31#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
32#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
33#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
34#define MAX_DMA_ADDRESS 0xffffffff
35#define MAX_DMA_CHANNELS 32
36
37struct stmp3xxx_dma_command {
38 u32 next;
39 u32 cmd;
40 union {
41 u32 buf_ptr;
42 u32 alternate;
43 };
44 u32 pio_words[MAX_PIO_WORDS];
45};
46
47struct stmp3xxx_dma_descriptor {
48 struct stmp3xxx_dma_command *command;
49 dma_addr_t handle;
50
51 /* The virtual address of the buffer pointer */
52 void *virtual_buf_ptr;
53 /* The next descriptor in a the DMA chain (optional) */
54 struct stmp3xxx_dma_descriptor *next_descr;
55};
56
57struct stmp37xx_circ_dma_chain {
58 unsigned total_count;
59 struct stmp3xxx_dma_descriptor *chain;
60
61 unsigned free_index;
62 unsigned free_count;
63 unsigned active_index;
64 unsigned active_count;
65 unsigned cooked_index;
66 unsigned cooked_count;
67
68 int bus;
69 unsigned channel;
70};
71
72static inline struct stmp3xxx_dma_descriptor
73 *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
74{
75 return &(chain->chain[chain->free_index]);
76}
77
78static inline struct stmp3xxx_dma_descriptor
79 *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
80{
81 return &(chain->chain[chain->cooked_index]);
82}
83
84int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
85int stmp3xxx_dma_release(int ch);
86int stmp3xxx_dma_allocate_command(int ch,
87 struct stmp3xxx_dma_descriptor *descriptor);
88int stmp3xxx_dma_free_command(int ch,
89 struct stmp3xxx_dma_descriptor *descriptor);
90void stmp3xxx_dma_continue(int channel, u32 semaphore);
91void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
92 u32 semaphore);
93int stmp3xxx_dma_running(int ch);
94int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
95 struct stmp3xxx_dma_descriptor descriptors[],
96 unsigned items);
97void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
98void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
99void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
100 unsigned count);
101void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
102 unsigned count);
103unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
104int stmp3xxx_dma_read_semaphore(int ch);
105void stmp3xxx_dma_init(void);
106void stmp3xxx_dma_set_alt_target(int ch, int target);
107void stmp3xxx_dma_suspend(void);
108void stmp3xxx_dma_resume(void);
109
110/*
111 * STMP37xx and STMP378x have different DMA control
112 * registers layout
113 */
114
115void stmp3xxx_arch_dma_freeze(int ch);
116void stmp3xxx_arch_dma_unfreeze(int ch);
117void stmp3xxx_arch_dma_reset_channel(int ch);
118void stmp3xxx_arch_dma_enable_interrupt(int ch);
119void stmp3xxx_arch_dma_clear_interrupt(int ch);
120int stmp3xxx_arch_dma_is_interrupt(int ch);
121
122static inline void stmp3xxx_dma_reset_channel(int ch)
123{
124 stmp3xxx_arch_dma_reset_channel(ch);
125}
126
127
128static inline void stmp3xxx_dma_freeze(int ch)
129{
130 stmp3xxx_arch_dma_freeze(ch);
131}
132
133static inline void stmp3xxx_dma_unfreeze(int ch)
134{
135 stmp3xxx_arch_dma_unfreeze(ch);
136}
137
138static inline void stmp3xxx_dma_enable_interrupt(int ch)
139{
140 stmp3xxx_arch_dma_enable_interrupt(ch);
141}
142
143static inline void stmp3xxx_dma_clear_interrupt(int ch)
144{
145 stmp3xxx_arch_dma_clear_interrupt(ch);
146}
147
148static inline int stmp3xxx_dma_is_interrupt(int ch)
149{
150 return stmp3xxx_arch_dma_is_interrupt(ch);
151}
152
153#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
deleted file mode 100644
index a8b579256170..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X GPIO interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_GPIO_H
19#define __ASM_PLAT_GPIO_H
20
21#define ARCH_NR_GPIOS (32 * 3)
22#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
23#define gpio_get_value(gpio) __gpio_get_value(gpio)
24#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
25
26#include <asm-generic/gpio.h>
27
28#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
deleted file mode 100644
index e166432910ad..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __MACH_GPMI_H
2
3#include <linux/mtd/partitions.h>
4#include <mach/regs-gpmi.h>
5
6struct gpmi_platform_data {
7 void *pins;
8 int nr_parts;
9 struct mtd_partition *parts;
10 const char *part_types[];
11};
12#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
deleted file mode 100644
index 47b8978405bc..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * This file contains the hardware definitions of the Freescale STMP3XXX
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_HARDWARE_H
19#define __ASM_ARCH_HARDWARE_H
20
21/*
22 * Where in virtual memory the IO devices (timers, system controllers
23 * and so on)
24 */
25#define IO_BASE 0xF0000000 /* VA of IO */
26#define IO_SIZE 0x00100000 /* How much? */
27#define IO_START 0x80000000 /* PA of IO */
28
29/* macro to get at IO space when running virtually */
30#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
31
32#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
deleted file mode 100644
index d08b1b7f3d1c..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19#define IO_SPACE_LIMIT 0xffffffff
20
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23#define __mem_isa(a) (a)
24
25#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
deleted file mode 100644
index 61fa54882e12..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/memory.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PLAT_PHYS_OFFSET UL(0x40000000)
21
22#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
deleted file mode 100644
index ba81e1543761..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/mmc.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _MACH_MMC_H
2#define _MACH_MMC_H
3
4#include <mach/regs-ssp.h>
5
6struct stmp3xxxmmc_platform_data {
7 int (*get_wp)(void);
8 unsigned long (*setclock)(void __iomem *base, unsigned long);
9 void (*cmd_pullup)(int);
10 int (*hw_init)(void);
11 void (*hw_release)(void);
12};
13
14#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
deleted file mode 100644
index cc5af82279ad..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __PINMUX_H
19#define __PINMUX_H
20
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <asm-generic/gpio.h>
25
26/* Pin definitions */
27#include "pins.h"
28#include <mach/pins.h>
29
30/*
31 * Each pin may be routed up to four different HW interfaces
32 * including GPIO
33 */
34enum pin_fun {
35 PIN_FUN1 = 0,
36 PIN_FUN2,
37 PIN_FUN3,
38 PIN_GPIO,
39};
40
41/*
42 * Each pin may have different output drive strength in range from
43 * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
44 */
45enum pin_strength {
46 PIN_4MA = 0,
47 PIN_8MA,
48 PIN_12MA,
49 PIN_16MA,
50 PIN_20MA,
51};
52
53/*
54 * Each pin can be programmed for 1.8V or 3.3V
55 */
56enum pin_voltage {
57 PIN_1_8V = 0,
58 PIN_3_3V,
59};
60
61/*
62 * Structure to define a group of pins and their parameters
63 */
64struct pin_desc {
65 unsigned id;
66 enum pin_fun fun;
67 enum pin_strength strength;
68 enum pin_voltage voltage;
69 unsigned pullup:1;
70};
71
72struct pin_group {
73 struct pin_desc *pins;
74 int nr_pins;
75};
76
77/* Set pin drive strength */
78void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
79 const char *label);
80
81/* Set pin voltage */
82void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
83 const char *label);
84
85/* Enable pull-up resistor for a pin */
86void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
87
88/*
89 * Request a pin ownership, only one module (identified by @label)
90 * may own a pin.
91 */
92int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
93
94/* Release pin */
95void stmp3xxx_release_pin(unsigned id, const char *label);
96
97void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
98
99/*
100 * Each bank is associated with a number of registers to control
101 * pin function, drive strength, voltage and pull-up reigster. The
102 * number of registers of a given type depends on the number of bits
103 * describin particular pin.
104 */
105#define HW_MUXSEL_NUM 2 /* registers per bank */
106#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
107#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
108#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
109#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
110
111#define HW_DRIVE_NUM 4 /* registers per bank */
112#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
113#define HW_DRIVE_PIN_NUM 8 /* pins per register */
114#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
115#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
116#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
117
118
119struct stmp3xxx_pinmux_bank {
120 struct gpio_chip chip;
121
122 /* Pins allocation map */
123 unsigned long pin_map;
124
125 /* Pin owner names */
126 const char *pin_labels[32];
127
128 /* Bank registers */
129 void __iomem *hw_muxsel[HW_MUXSEL_NUM];
130 void __iomem *hw_drive[HW_DRIVE_NUM];
131 void __iomem *hw_pull;
132
133 void __iomem *pin2irq,
134 *irqlevel,
135 *irqpolarity,
136 *irqen,
137 *irqstat;
138
139 /* HW MUXSEL register function bit values */
140 u8 functions[HW_MUXSEL_PINFUN_NUM];
141
142 /*
143 * HW DRIVE register strength bit values:
144 * 0xff - requested strength is not supported for this bank
145 */
146 u8 strengths[HW_DRIVE_PINDRV_NUM];
147
148 /* GPIO things */
149 void __iomem *hw_gpio_in,
150 *hw_gpio_out,
151 *hw_gpio_doe;
152 int irq, virq;
153};
154
155int __init stmp3xxx_pinmux_init(int virtual_irq_start);
156
157#endif /* __PINMUX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h
deleted file mode 100644
index c573318e1caa..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pins.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_PINS_H
19#define __ASM_PLAT_PINS_H
20
21#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
22#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
23#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
24
25/*
26 * Special invalid pin identificator to show a pin doesn't exist
27 */
28#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
29
30#endif /* __ASM_PLAT_PINS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
deleted file mode 100644
index 7007ddaa91eb..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/platform.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_PLAT_PLATFORM_H
15#define __ASM_PLAT_PLATFORM_H
16
17#ifndef __ASSEMBLER__
18#include <linux/io.h>
19#endif
20#include <asm/sizes.h>
21
22/* Virtual address where registers are mapped */
23#define STMP3XXX_REGS_PHBASE 0x80000000
24#ifdef __ASSEMBLER__
25#define STMP3XXX_REGS_BASE 0xF0000000
26#else
27#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
28#endif
29#define STMP3XXX_REGS_SIZE SZ_1M
30
31/* Virtual address where OCRAM is mapped */
32#define STMP3XXX_OCRAM_PHBASE 0x00000000
33#ifdef __ASSEMBLER__
34#define STMP3XXX_OCRAM_BASE 0xf1000000
35#else
36#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
37#endif
38#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
39
40#ifdef CONFIG_ARCH_STMP37XX
41#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
42#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
43#endif
44
45#ifdef CONFIG_ARCH_STMP378X
46#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
47#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
48#endif
49
50#define HW_STMP3XXX_SET 0x04
51#define HW_STMP3XXX_CLR 0x08
52#define HW_STMP3XXX_TOG 0x0c
53
54#ifndef __ASSEMBLER__
55static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
56{
57 __raw_writel(v, r + HW_STMP3XXX_CLR);
58}
59
60static inline void stmp3xxx_setl(u32 v, void __iomem *r)
61{
62 __raw_writel(v, r + HW_STMP3XXX_SET);
63}
64#endif
65
66#define BF(value, field) (((value) << BP_##field) & BM_##field)
67
68#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
deleted file mode 100644
index 2e300feaa4cf..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X core structure and function declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_H
19#define __ASM_PLAT_STMP3XXX_H
20
21#include <linux/irq.h>
22
23extern struct sys_timer stmp3xxx_timer;
24
25void stmp3xxx_init_irq(struct irq_chip *chip);
26void stmp3xxx_init(void);
27int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
28extern struct platform_device stmp3xxx_dbguart,
29 stmp3xxx_appuart,
30 stmp3xxx_watchdog,
31 stmp3xxx_touchscreen,
32 stmp3xxx_keyboard,
33 stmp3xxx_gpmi,
34 stmp3xxx_mmc,
35 stmp3xxx_udc,
36 stmp3xxx_ehci,
37 stmp3xxx_rtc,
38 stmp3xxx_spi1,
39 stmp3xxx_spi2,
40 stmp3xxx_backlight,
41 stmp3xxx_rotdec,
42 stmp3xxx_dcp,
43 stmp3xxx_dcp_bootstream,
44 stmp3xxx_persistent,
45 stmp3xxx_framebuffer,
46 stmp3xxx_battery;
47int stmp3xxx_ssp1_device_register(void);
48int stmp3xxx_ssp2_device_register(void);
49
50struct pin_group;
51void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
52int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
53
54#endif /* __ASM_PLAT_STMP3XXX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
deleted file mode 100644
index 28a988889319..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARCH_SYSTEM_H
17#define __ASM_ARCH_SYSTEM_H
18
19#include <asm/proc-fns.h>
20#include <mach/platform.h>
21#include <mach/regs-clkctrl.h>
22#include <mach/regs-power.h>
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30
31 cpu_do_idle();
32}
33
34static inline void arch_reset(char mode, const char *cmd)
35{
36 /* Set BATTCHRG to default value */
37 __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
38
39 /* Set MINPWR to default value */
40 __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
41
42 /* Reset digital side of chip (but not power or RTC) */
43 __raw_writel(BM_CLKCTRL_RESET_DIG,
44 REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
45
46 /* Should not return */
47}
48
49#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h
deleted file mode 100644
index 3373985d7a8e..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17/*
18 * System time clock is sourced from the 32k clock
19 */
20#define CLOCK_TICK_RATE (32768)
diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
deleted file mode 100644
index f79f5ee56cd4..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 *
3 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 */
6
7/*
8 * The code contained herein is licensed under the GNU General Public
9 * License. You may obtain a copy of the GNU General Public License
10 * Version 2 or later at the following locations:
11 *
12 * http://www.opensource.org/licenses/gpl-license.html
13 * http://www.gnu.org/copyleft/gpl.html
14 */
15#ifndef __ASM_PLAT_UNCOMPRESS_H
16#define __ASM_PLAT_UNCOMPRESS_H
17
18/*
19 * Register includes are for when the MMU enabled; we need to define our
20 * own stuff here for pre-MMU use
21 */
22#define UARTDBG_BASE 0x80070000
23#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
24
25/*
26 * This does not append a newline
27 */
28static void putc(char c)
29{
30 /* Wait for TX fifo empty */
31 while ((UART(6) & (1<<7)) == 0)
32 continue;
33
34 /* Write byte */
35 UART(0) = c;
36
37 /* Wait for last bit to exit the UART */
38 while (UART(6) & (1<<3))
39 continue;
40}
41
42static void flush(void)
43{
44}
45
46/*
47 * nothing to do
48 */
49#define arch_decomp_setup()
50
51#define arch_decomp_wdog()
52
53#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
deleted file mode 100644
index 943c1a29d641..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#define VMALLOC_END 0xf0000000UL
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
deleted file mode 100644
index 6fdf9acf82ed..000000000000
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X common interrupt handling code
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/sysdev.h>
23
24#include <mach/stmp3xxx.h>
25#include <mach/platform.h>
26#include <mach/regs-icoll.h>
27
28void __init stmp3xxx_init_irq(struct irq_chip *chip)
29{
30 unsigned int i, lv;
31
32 /* Reset the interrupt controller */
33 stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
34
35 /* Disable all interrupts initially */
36 for (i = 0; i < NR_REAL_IRQS; i++) {
37 chip->irq_mask(irq_get_irq_data(i));
38 irq_set_chip_and_handler(i, chip, handle_level_irq);
39 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
40 }
41
42 /* Ensure vector is cleared */
43 for (lv = 0; lv < 4; lv++)
44 __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
45 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
46
47 /* Barrier */
48 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
49}
50
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
deleted file mode 100644
index 3def03b3217d..000000000000
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ /dev/null
@@ -1,550 +0,0 @@
1/*
2 * Freescale STMP378X/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/sysdev.h>
23#include <linux/string.h>
24#include <linux/bitops.h>
25#include <linux/irq.h>
26
27#include <mach/hardware.h>
28#include <mach/platform.h>
29#include <mach/regs-pinctrl.h>
30#include <mach/pins.h>
31#include <mach/pinmux.h>
32
33#define NR_BANKS ARRAY_SIZE(pinmux_banks)
34static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
35 [0] = {
36 .hw_muxsel = {
37 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
38 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
39 },
40 .hw_drive = {
41 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
42 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
43 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
44 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
45 },
46 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
47 .functions = { 0x0, 0x1, 0x2, 0x3 },
48 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
49
50 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
51 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
52 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
53 .irq = IRQ_GPIO0,
54
55 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
56 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
57 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
58 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
59 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
60 },
61 [1] = {
62 .hw_muxsel = {
63 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
64 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
65 },
66 .hw_drive = {
67 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
68 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
69 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
70 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
71 },
72 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
73 .functions = { 0x0, 0x1, 0x2, 0x3 },
74 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
75
76 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
77 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
78 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
79 .irq = IRQ_GPIO1,
80
81 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
82 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
83 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
84 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
85 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
86 },
87 [2] = {
88 .hw_muxsel = {
89 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
90 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
91 },
92 .hw_drive = {
93 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
94 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
95 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
96 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
97 },
98 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
99 .functions = { 0x0, 0x1, 0x2, 0x3 },
100 .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
101
102 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
103 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
104 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
105 .irq = IRQ_GPIO2,
106
107 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
108 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
109 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
110 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
111 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
112 },
113 [3] = {
114 .hw_muxsel = {
115 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
116 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
117 },
118 .hw_drive = {
119 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
120 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
121 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
122 NULL,
123 },
124 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
125 .functions = {0x0, 0x1, 0x2, 0x3},
126 .strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
127 },
128};
129
130static inline struct stmp3xxx_pinmux_bank *
131stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
132{
133 unsigned b, p;
134
135 b = STMP3XXX_PINID_TO_BANK(id);
136 p = STMP3XXX_PINID_TO_PINNUM(id);
137 BUG_ON(b >= NR_BANKS);
138 if (bank)
139 *bank = b;
140 if (pin)
141 *pin = p;
142 return &pinmux_banks[b];
143}
144
145/* Check if requested pin is owned by caller */
146static int stmp3xxx_check_pin(unsigned id, const char *label)
147{
148 unsigned pin;
149 struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
150
151 if (!test_bit(pin, &pm->pin_map)) {
152 printk(KERN_WARNING
153 "%s: Accessing free pin %x, caller %s\n",
154 __func__, id, label);
155
156 return -EINVAL;
157 }
158
159 if (label && pm->pin_labels[pin] &&
160 strcmp(label, pm->pin_labels[pin])) {
161 printk(KERN_WARNING
162 "%s: Wrong pin owner %x, caller %s owner %s\n",
163 __func__, id, label, pm->pin_labels[pin]);
164
165 return -EINVAL;
166 }
167 return 0;
168}
169
170void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
171 const char *label)
172{
173 struct stmp3xxx_pinmux_bank *pbank;
174 void __iomem *hwdrive;
175 u32 shift, val;
176 u32 bank, pin;
177
178 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
179 pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
180 bank, pin, strength);
181
182 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
183 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
184 val = pbank->strengths[strength];
185 if (val == 0xff) {
186 printk(KERN_WARNING
187 "%s: strength is not supported for bank %d, caller %s",
188 __func__, bank, label);
189 return;
190 }
191
192 if (stmp3xxx_check_pin(id, label))
193 return;
194
195 pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
196 val << shift, hwdrive);
197 stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
198 stmp3xxx_setl(val << shift, hwdrive);
199}
200
201void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
202 const char *label)
203{
204 struct stmp3xxx_pinmux_bank *pbank;
205 void __iomem *hwdrive;
206 u32 shift;
207 u32 bank, pin;
208
209 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
210 pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
211 bank, pin, voltage);
212
213 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
214 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
215
216 if (stmp3xxx_check_pin(id, label))
217 return;
218
219 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
220 __func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
221 if (voltage == PIN_1_8V)
222 stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
223 else
224 stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
225}
226
227void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
228{
229 struct stmp3xxx_pinmux_bank *pbank;
230 void __iomem *hwpull;
231 u32 bank, pin;
232
233 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
234 pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
235 bank, pin, enable);
236
237 hwpull = pbank->hw_pull;
238
239 if (stmp3xxx_check_pin(id, label))
240 return;
241
242 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
243 __func__, 1 << pin, hwpull);
244 if (enable)
245 stmp3xxx_setl(1 << pin, hwpull);
246 else
247 stmp3xxx_clearl(1 << pin, hwpull);
248}
249
250int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
251{
252 struct stmp3xxx_pinmux_bank *pbank;
253 u32 bank, pin;
254 int ret = 0;
255
256 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
257 pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
258 bank, pin, fun);
259
260 if (test_bit(pin, &pbank->pin_map)) {
261 printk(KERN_WARNING
262 "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
263 __func__, bank, pin, label, pbank->pin_labels[pin]);
264 return -EBUSY;
265 }
266
267 set_bit(pin, &pbank->pin_map);
268 pbank->pin_labels[pin] = label;
269
270 stmp3xxx_set_pin_type(id, fun);
271
272 return ret;
273}
274
275void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
276{
277 struct stmp3xxx_pinmux_bank *pbank;
278 void __iomem *hwmux;
279 u32 shift, val;
280 u32 bank, pin;
281
282 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
283
284 hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
285 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
286
287 val = pbank->functions[fun];
288 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
289 pr_debug("%s: writing 0x%x to 0x%p register\n",
290 __func__, val << shift, hwmux);
291 stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
292 stmp3xxx_setl(val << shift, hwmux);
293}
294
295void stmp3xxx_release_pin(unsigned id, const char *label)
296{
297 struct stmp3xxx_pinmux_bank *pbank;
298 u32 bank, pin;
299
300 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
301 pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
302
303 if (stmp3xxx_check_pin(id, label))
304 return;
305
306 clear_bit(pin, &pbank->pin_map);
307 pbank->pin_labels[pin] = NULL;
308}
309
310int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
311{
312 struct pin_desc *pin;
313 int p;
314 int err = 0;
315
316 /* Allocate and configure pins */
317 for (p = 0; p < pin_group->nr_pins; p++) {
318 pr_debug("%s: #%d\n", __func__, p);
319 pin = &pin_group->pins[p];
320
321 err = stmp3xxx_request_pin(pin->id, pin->fun, label);
322 if (err)
323 goto out_err;
324
325 stmp3xxx_pin_strength(pin->id, pin->strength, label);
326 stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
327 stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
328 }
329
330 return 0;
331
332out_err:
333 /* Release allocated pins in case of error */
334 while (--p >= 0) {
335 pr_debug("%s: releasing #%d\n", __func__, p);
336 stmp3xxx_release_pin(pin_group->pins[p].id, label);
337 }
338 return err;
339}
340EXPORT_SYMBOL(stmp3xxx_request_pin_group);
341
342void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
343{
344 struct pin_desc *pin;
345 int p;
346
347 for (p = 0; p < pin_group->nr_pins; p++) {
348 pin = &pin_group->pins[p];
349 stmp3xxx_release_pin(pin->id, label);
350 }
351}
352EXPORT_SYMBOL(stmp3xxx_release_pin_group);
353
354static int stmp3xxx_irq_data_to_gpio(struct irq_data *d,
355 struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
356{
357 struct stmp3xxx_pinmux_bank *pm;
358
359 for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
360 if (pm->virq <= d->irq && d->irq < pm->virq + 32) {
361 *bank = pm;
362 *gpio = d->irq - pm->virq;
363 return 0;
364 }
365 return -ENOENT;
366}
367
368static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type)
369{
370 struct stmp3xxx_pinmux_bank *pm;
371 unsigned gpio;
372 int l, p;
373
374 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
375 switch (type) {
376 case IRQ_TYPE_EDGE_RISING:
377 l = 0; p = 1; break;
378 case IRQ_TYPE_EDGE_FALLING:
379 l = 0; p = 0; break;
380 case IRQ_TYPE_LEVEL_HIGH:
381 l = 1; p = 1; break;
382 case IRQ_TYPE_LEVEL_LOW:
383 l = 1; p = 0; break;
384 default:
385 pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
386 __func__, type);
387 return -ENXIO;
388 }
389
390 if (l)
391 stmp3xxx_setl(1 << gpio, pm->irqlevel);
392 else
393 stmp3xxx_clearl(1 << gpio, pm->irqlevel);
394 if (p)
395 stmp3xxx_setl(1 << gpio, pm->irqpolarity);
396 else
397 stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
398 return 0;
399}
400
401static void stmp3xxx_pin_ack_irq(struct irq_data *d)
402{
403 u32 stat;
404 struct stmp3xxx_pinmux_bank *pm;
405 unsigned gpio;
406
407 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
408 stat = __raw_readl(pm->irqstat) & (1 << gpio);
409 stmp3xxx_clearl(stat, pm->irqstat);
410}
411
412static void stmp3xxx_pin_mask_irq(struct irq_data *d)
413{
414 struct stmp3xxx_pinmux_bank *pm;
415 unsigned gpio;
416
417 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
418 stmp3xxx_clearl(1 << gpio, pm->irqen);
419 stmp3xxx_clearl(1 << gpio, pm->pin2irq);
420}
421
422static void stmp3xxx_pin_unmask_irq(struct irq_data *d)
423{
424 struct stmp3xxx_pinmux_bank *pm;
425 unsigned gpio;
426
427 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
428 stmp3xxx_setl(1 << gpio, pm->irqen);
429 stmp3xxx_setl(1 << gpio, pm->pin2irq);
430}
431
432static inline
433struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
434{
435 return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
436}
437
438static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
439{
440 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
441 return pm->virq + offset;
442}
443
444static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
445{
446 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
447 unsigned v;
448
449 v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
450 return v ? 1 : 0;
451}
452
453static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
454{
455 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
456
457 if (v)
458 stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
459 else
460 stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
461}
462
463static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
464{
465 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
466
467 stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
468 stmp3xxx_gpio_set(chip, offset, v);
469 return 0;
470}
471
472static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
473{
474 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
475
476 stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
477 return 0;
478}
479
480static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
481{
482 return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
483}
484
485static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
486{
487 stmp3xxx_release_pin(chip->base + offset, "gpio");
488}
489
490static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
491{
492 struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
493 int gpio_irq = pm->virq;
494 u32 stat = __raw_readl(pm->irqstat);
495
496 while (stat) {
497 if (stat & 1)
498 generic_handle_irq(gpio_irq);
499 gpio_irq++;
500 stat >>= 1;
501 }
502}
503
504static struct irq_chip gpio_irq_chip = {
505 .irq_ack = stmp3xxx_pin_ack_irq,
506 .irq_mask = stmp3xxx_pin_mask_irq,
507 .irq_unmask = stmp3xxx_pin_unmask_irq,
508 .irq_set_type = stmp3xxx_set_irqtype,
509};
510
511int __init stmp3xxx_pinmux_init(int virtual_irq_start)
512{
513 int b, r = 0;
514 struct stmp3xxx_pinmux_bank *pm;
515 int virq;
516
517 for (b = 0; b < 3; b++) {
518 /* only banks 0,1,2 are allowed to GPIO */
519 pm = pinmux_banks + b;
520 pm->chip.base = 32 * b;
521 pm->chip.ngpio = 32;
522 pm->chip.owner = THIS_MODULE;
523 pm->chip.can_sleep = 1;
524 pm->chip.exported = 1;
525 pm->chip.to_irq = stmp3xxx_gpio_to_irq;
526 pm->chip.direction_input = stmp3xxx_gpio_input;
527 pm->chip.direction_output = stmp3xxx_gpio_output;
528 pm->chip.get = stmp3xxx_gpio_get;
529 pm->chip.set = stmp3xxx_gpio_set;
530 pm->chip.request = stmp3xxx_gpio_request;
531 pm->chip.free = stmp3xxx_gpio_free;
532 pm->virq = virtual_irq_start + b * 32;
533
534 for (virq = pm->virq; virq < pm->virq; virq++) {
535 gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
536 irq_set_chip_and_handler(virq, &gpio_irq_chip,
537 handle_level_irq);
538 set_irq_flags(virq, IRQF_VALID);
539 }
540 r = gpiochip_add(&pm->chip);
541 if (r < 0)
542 break;
543 irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
544 irq_set_handler_data(pm->irq, pm);
545 }
546 return r;
547}
548
549MODULE_AUTHOR("Vladislav Buzov");
550MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
deleted file mode 100644
index c395630a6edc..000000000000
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * System timer for Freescale STMP37XX/STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/clocksource.h>
22#include <linux/clockchips.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/interrupt.h>
26
27#include <asm/mach/time.h>
28#include <mach/stmp3xxx.h>
29#include <mach/platform.h>
30#include <mach/regs-timrot.h>
31
32static irqreturn_t
33stmp3xxx_timer_interrupt(int irq, void *dev_id)
34{
35 struct clock_event_device *c = dev_id;
36
37 /* timer 0 */
38 if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
39 BM_TIMROT_TIMCTRLn_IRQ) {
40 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
41 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
42 c->event_handler(c);
43 }
44
45 /* timer 1 */
46 else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
47 & BM_TIMROT_TIMCTRLn_IRQ) {
48 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
49 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
50 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
51 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
52 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
53 }
54
55 return IRQ_HANDLED;
56}
57
58static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
59{
60 return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
61 & 0xFFFF0000) >> 16);
62}
63
64static int
65stmp3xxx_timrot_set_next_event(unsigned long delta,
66 struct clock_event_device *dev)
67{
68 /* reload the timer */
69 __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
70 return 0;
71}
72
73static void
74stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
75 struct clock_event_device *dev)
76{
77}
78
79static struct clock_event_device ckevt_timrot = {
80 .name = "timrot",
81 .features = CLOCK_EVT_FEAT_ONESHOT,
82 .shift = 32,
83 .set_next_event = stmp3xxx_timrot_set_next_event,
84 .set_mode = stmp3xxx_timrot_set_mode,
85};
86
87static struct clocksource cksrc_stmp3xxx = {
88 .name = "cksrc_stmp3xxx",
89 .rating = 250,
90 .read = stmp3xxx_clock_read,
91 .mask = CLOCKSOURCE_MASK(16),
92 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
93};
94
95static struct irqaction stmp3xxx_timer_irq = {
96 .name = "stmp3xxx_timer",
97 .flags = IRQF_DISABLED | IRQF_TIMER,
98 .handler = stmp3xxx_timer_interrupt,
99 .dev_id = &ckevt_timrot,
100};
101
102
103/*
104 * Set up timer interrupt, and return the current time in seconds.
105 */
106static void __init stmp3xxx_init_timer(void)
107{
108 ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
109 ckevt_timrot.shift);
110 ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
111 ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
112 ckevt_timrot.cpumask = cpumask_of(0);
113
114 stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
115
116 /* clear two timers */
117 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
118 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
119
120 /* configure them */
121 __raw_writel(
122 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
123 BM_TIMROT_TIMCTRLn_RELOAD |
124 BM_TIMROT_TIMCTRLn_UPDATE |
125 BM_TIMROT_TIMCTRLn_IRQ_EN,
126 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
127 __raw_writel(
128 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
129 BM_TIMROT_TIMCTRLn_RELOAD |
130 BM_TIMROT_TIMCTRLn_UPDATE |
131 BM_TIMROT_TIMCTRLn_IRQ_EN,
132 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
133
134 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
135 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
136 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
137
138 setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
139
140 clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE);
141 clockevents_register_device(&ckevt_timrot);
142}
143
144#ifdef CONFIG_PM
145
146void stmp3xxx_suspend_timer(void)
147{
148 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
149 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
150 stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
151 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
152}
153
154void stmp3xxx_resume_timer(void)
155{
156 stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
157 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
158 __raw_writel(
159 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
160 BM_TIMROT_TIMCTRLn_RELOAD |
161 BM_TIMROT_TIMCTRLn_UPDATE |
162 BM_TIMROT_TIMCTRLn_IRQ_EN,
163 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
164 __raw_writel(
165 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
166 BM_TIMROT_TIMCTRLn_RELOAD |
167 BM_TIMROT_TIMCTRLn_UPDATE |
168 BM_TIMROT_TIMCTRLn_IRQ_EN,
169 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
170 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
171 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
172 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
173}
174
175#else
176
177#define stmp3xxx_suspend_timer NULL
178#define stmp3xxx_resume_timer NULL
179
180#endif /* CONFIG_PM */
181
182struct sys_timer stmp3xxx_timer = {
183 .init = stmp3xxx_init_timer,
184 .suspend = stmp3xxx_suspend_timer,
185 .resume = stmp3xxx_resume_timer,
186};
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index ba3d471d4bcf..51ecfea09b27 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -16,6 +16,7 @@
16#include <linux/smp.h> 16#include <linux/smp.h>
17 17
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/hardware/gic.h>
19 20
20/* 21/*
21 * control for which core is the next to come out of the secondary 22 * control for which core is the next to come out of the secondary
@@ -83,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
83 * the boot monitor to read the system wide flags register, 84 * the boot monitor to read the system wide flags register,
84 * and branch to the address found there. 85 * and branch to the address found there.
85 */ 86 */
86 smp_cross_call(cpumask_of(cpu), 1); 87 gic_raise_softirq(cpumask_of(cpu), 1);
87 88
88 timeout = jiffies + (1 * HZ); 89 timeout = jiffies + (1 * HZ);
89 while (time_before(jiffies, timeout)) { 90 while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 7ca41f0a09b1..3b3776d0a1a7 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -17,7 +17,7 @@
17# XXX: the last 12 months. If your entry is missing please email rmk at 17# XXX: the last 12 months. If your entry is missing please email rmk at
18# XXX: <linux@arm.linux.org.uk> 18# XXX: <linux@arm.linux.org.uk>
19# 19#
20# Last update: Sun Mar 20 18:06:11 2011 20# Last update: Sat May 7 08:48:24 2011
21# 21#
22# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 22# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
23# 23#
@@ -377,6 +377,8 @@ davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157
377at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 377at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159
378omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 378omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160
379magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 379magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162
380btmavb101 MACH_BTMAVB101 BTMAVB101 2172
381btmawb101 MACH_BTMAWB101 BTMAWB101 2173
380omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 382omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178
381anw6410 MACH_ANW6410 ANW6410 2183 383anw6410 MACH_ANW6410 ANW6410 2183
382imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187 384imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187
@@ -400,6 +402,7 @@ d2net MACH_D2NET D2NET 2282
400bigdisk MACH_BIGDISK BIGDISK 2283 402bigdisk MACH_BIGDISK BIGDISK 2283
401at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 403at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288
402bcmring MACH_BCMRING BCMRING 2289 404bcmring MACH_BCMRING BCMRING 2289
405dp6xx MACH_DP6XX DP6XX 2302
403mahimahi MACH_MAHIMAHI MAHIMAHI 2304 406mahimahi MACH_MAHIMAHI MAHIMAHI 2304
404smdk6442 MACH_SMDK6442 SMDK6442 2324 407smdk6442 MACH_SMDK6442 SMDK6442 2324
405openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 408openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325
@@ -424,6 +427,7 @@ smdkv210 MACH_SMDKV210 SMDKV210 2456
424omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464 427omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464
425omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465 428omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465
426smartq7 MACH_SMARTQ7 SMARTQ7 2479 429smartq7 MACH_SMARTQ7 SMARTQ7 2479
430watson_efm_plugin MACH_WATSON_EFM_PLUGIN WATSON_EFM_PLUGIN 2491
427g4evm MACH_G4EVM G4EVM 2493 431g4evm MACH_G4EVM G4EVM 2493
428omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495 432omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495
429ts41x MACH_TS41X TS41X 2502 433ts41x MACH_TS41X TS41X 2502
@@ -433,6 +437,8 @@ mx28evk MACH_MX28EVK MX28EVK 2531
433smartq5 MACH_SMARTQ5 SMARTQ5 2534 437smartq5 MACH_SMARTQ5 SMARTQ5 2534
434davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 438davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548
435mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 439mxt_td60 MACH_MXT_TD60 MXT_TD60 2550
440riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576
441riot_x37 MACH_RIOT_X37 RIOT_X37 2578
436capc7117 MACH_CAPC7117 CAPC7117 2612 442capc7117 MACH_CAPC7117 CAPC7117 2612
437icontrol MACH_ICONTROL ICONTROL 2624 443icontrol MACH_ICONTROL ICONTROL 2624
438qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627 444qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627
@@ -445,6 +451,7 @@ spear320 MACH_SPEAR320 SPEAR320 2661
445aquila MACH_AQUILA AQUILA 2676 451aquila MACH_AQUILA AQUILA 2676
446sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678 452sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678
447msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679 453msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679
454ea2478devkit MACH_EA2478DEVKIT EA2478DEVKIT 2683
448terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697 455terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697
449msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703 456msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703
450msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704 457msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704
@@ -463,75 +470,16 @@ wbd222 MACH_WBD222 WBD222 2753
463msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755 470msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755
464msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756 471msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756
465tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758 472tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758
466ap420 MACH_AP420 AP420 2765 473nanos MACH_NANOS NANOS 2759
467davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767 474stamp9g45 MACH_STAMP9G45 STAMP9G45 2761
468msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768
469msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769
470esl_vamana MACH_ESL_VAMANA ESL_VAMANA 2770
471sbc35 MACH_SBC35 SBC35 2771
472mpx6446 MACH_MPX6446 MPX6446 2772
473oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773
474kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774
475ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775
476cns3420vb MACH_CNS3420VB CNS3420VB 2776 475cns3420vb MACH_CNS3420VB CNS3420VB 2776
477olympus MACH_OLYMPUS OLYMPUS 2778
478vortex MACH_VORTEX VORTEX 2779
479s5pc200 MACH_S5PC200 S5PC200 2780
480ecucore_9263 MACH_ECUCORE_9263 ECUCORE_9263 2781
481smdkc200 MACH_SMDKC200 SMDKC200 2782
482emsiso_sx27 MACH_EMSISO_SX27 EMSISO_SX27 2783
483apx_som9g45_ek MACH_APX_SOM9G45_EK APX_SOM9G45_EK 2784
484songshan MACH_SONGSHAN SONGSHAN 2785
485tianshan MACH_TIANSHAN TIANSHAN 2786
486vpx500 MACH_VPX500 VPX500 2787
487am3517sam MACH_AM3517SAM AM3517SAM 2788
488skat91_sim508 MACH_SKAT91_SIM508 SKAT91_SIM508 2789
489skat91_s3e MACH_SKAT91_S3E SKAT91_S3E 2790
490omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791 476omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
491df7220 MACH_DF7220 DF7220 2792
492nemini MACH_NEMINI NEMINI 2793
493t8200 MACH_T8200 T8200 2794
494apf51 MACH_APF51 APF51 2795
495dr_rc_unit MACH_DR_RC_UNIT DR_RC_UNIT 2796
496bordeaux MACH_BORDEAUX BORDEAUX 2797
497catania_b MACH_CATANIA_B CATANIA_B 2798
498mx51_ocean MACH_MX51_OCEAN MX51_OCEAN 2799
499ti8168evm MACH_TI8168EVM TI8168EVM 2800 477ti8168evm MACH_TI8168EVM TI8168EVM 2800
500neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801
501withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802
502dbps MACH_DBPS DBPS 2803
503pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805
504speedy MACH_SPEEDY SPEEDY 2806
505chrysaor MACH_CHRYSAOR CHRYSAOR 2807
506tango MACH_TANGO TANGO 2808
507synology_dsx11 MACH_SYNOLOGY_DSX11 SYNOLOGY_DSX11 2809
508hanlin_v3ext MACH_HANLIN_V3EXT HANLIN_V3EXT 2810
509hanlin_v5 MACH_HANLIN_V5 HANLIN_V5 2811
510hanlin_v3plus MACH_HANLIN_V3PLUS HANLIN_V3PLUS 2812
511iriver_story MACH_IRIVER_STORY IRIVER_STORY 2813
512irex_iliad MACH_IREX_ILIAD IREX_ILIAD 2814
513irex_dr1000 MACH_IREX_DR1000 IREX_DR1000 2815
514teton_bga MACH_TETON_BGA TETON_BGA 2816 478teton_bga MACH_TETON_BGA TETON_BGA 2816
515snapper9g45 MACH_SNAPPER9G45 SNAPPER9G45 2817
516tam3517 MACH_TAM3517 TAM3517 2818
517pdc100 MACH_PDC100 PDC100 2819
518eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820 479eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820
519eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821 480eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821
520eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822 481eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
521eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823 482eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
522p565 MACH_P565 P565 2824
523acer_a4 MACH_ACER_A4 ACER_A4 2825
524davinci_dm368_bip MACH_DAVINCI_DM368_BIP DAVINCI_DM368_BIP 2826
525eshare MACH_ESHARE ESHARE 2827
526wlbargn MACH_WLBARGN WLBARGN 2829
527bm170 MACH_BM170 BM170 2830
528netspace_mini_v2 MACH_NETSPACE_MINI_V2 NETSPACE_MINI_V2 2831
529netspace_plug_v2 MACH_NETSPACE_PLUG_V2 NETSPACE_PLUG_V2 2832
530siemens_l1 MACH_SIEMENS_L1 SIEMENS_L1 2833
531elv_lcu1 MACH_ELV_LCU1 ELV_LCU1 2834
532mcu1 MACH_MCU1 MCU1 2835
533omap3_tao3530 MACH_OMAP3_TAO3530 OMAP3_TAO3530 2836
534omap3_pcutouch MACH_OMAP3_PCUTOUCH OMAP3_PCUTOUCH 2837
535smdkc210 MACH_SMDKC210 SMDKC210 2838 483smdkc210 MACH_SMDKC210 SMDKC210 2838
536omap3_braillo MACH_OMAP3_BRAILLO OMAP3_BRAILLO 2839 484omap3_braillo MACH_OMAP3_BRAILLO OMAP3_BRAILLO 2839
537spyplug MACH_SPYPLUG SPYPLUG 2840 485spyplug MACH_SPYPLUG SPYPLUG 2840
@@ -973,9 +921,7 @@ isc3 MACH_ISC3 ISC3 3291
973rascal MACH_RASCAL RASCAL 3292 921rascal MACH_RASCAL RASCAL 3292
974hrefv60 MACH_HREFV60 HREFV60 3293 922hrefv60 MACH_HREFV60 HREFV60 3293
975tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294 923tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294
976pyramid_td MACH_PYRAMID_TD PYRAMID_TD 3295
977splendor MACH_SPLENDOR SPLENDOR 3296 924splendor MACH_SPLENDOR SPLENDOR 3296
978guf_planet MACH_GUF_PLANET GUF_PLANET 3297
979msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298 925msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298
980htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299 926htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299
981athene MACH_ATHENE ATHENE 3300 927athene MACH_ATHENE ATHENE 3300
@@ -1099,3 +1045,71 @@ ecuv5 MACH_ECUV5 ECUV5 3421
1099hsgx6d MACH_HSGX6D HSGX6D 3422 1045hsgx6d MACH_HSGX6D HSGX6D 3422
1100dawad7 MACH_DAWAD7 DAWAD7 3423 1046dawad7 MACH_DAWAD7 DAWAD7 3423
1101sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424 1047sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424
1048gt_i5700 MACH_GT_I5700 GT_I5700 3425
1049ctera_plug_c2 MACH_CTERA_PLUG_C2 CTERA_PLUG_C2 3426
1050marvelct MACH_MARVELCT MARVELCT 3427
1051ag11005 MACH_AG11005 AG11005 3428
1052vangogh MACH_VANGOGH VANGOGH 3430
1053matrix505 MACH_MATRIX505 MATRIX505 3431
1054oce_nigma MACH_OCE_NIGMA OCE_NIGMA 3432
1055t55 MACH_T55 T55 3433
1056bio3k MACH_BIO3K BIO3K 3434
1057expressct MACH_EXPRESSCT EXPRESSCT 3435
1058cardhu MACH_CARDHU CARDHU 3436
1059aruba MACH_ARUBA ARUBA 3437
1060bonaire MACH_BONAIRE BONAIRE 3438
1061nuc700evb MACH_NUC700EVB NUC700EVB 3439
1062nuc710evb MACH_NUC710EVB NUC710EVB 3440
1063nuc740evb MACH_NUC740EVB NUC740EVB 3441
1064nuc745evb MACH_NUC745EVB NUC745EVB 3442
1065transcede MACH_TRANSCEDE TRANSCEDE 3443
1066mora MACH_MORA MORA 3444
1067nda_evm MACH_NDA_EVM NDA_EVM 3445
1068timu MACH_TIMU TIMU 3446
1069expressh MACH_EXPRESSH EXPRESSH 3447
1070veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448
1071dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449
1072omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450
1073tritip MACH_TRITIP TRITIP 3451
1074sm1k MACH_SM1K SM1K 3452
1075monch MACH_MONCH MONCH 3453
1076curacao MACH_CURACAO CURACAO 3454
1077origen MACH_ORIGEN ORIGEN 3455
1078epc10 MACH_EPC10 EPC10 3456
1079sgh_i740 MACH_SGH_I740 SGH_I740 3457
1080tuna MACH_TUNA TUNA 3458
1081mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459
1082mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460
1083acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461
1084elke MACH_ELKE ELKE 3462
1085sbc6000x MACH_SBC6000X SBC6000X 3463
1086r1801e MACH_R1801E R1801E 3464
1087h1600 MACH_H1600 H1600 3465
1088mini210 MACH_MINI210 MINI210 3466
1089mini8168 MACH_MINI8168 MINI8168 3467
1090pc7308 MACH_PC7308 PC7308 3468
1091kmm2m01 MACH_KMM2M01 KMM2M01 3470
1092mx51erebus MACH_MX51EREBUS MX51EREBUS 3471
1093wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472
1094tuxrail MACH_TUXRAIL TUXRAIL 3473
1095arthur MACH_ARTHUR ARTHUR 3474
1096doorboy MACH_DOORBOY DOORBOY 3475
1097xarina MACH_XARINA XARINA 3476
1098roverx7 MACH_ROVERX7 ROVERX7 3477
1099sdvr MACH_SDVR SDVR 3478
1100acer_maya MACH_ACER_MAYA ACER_MAYA 3479
1101pico MACH_PICO PICO 3480
1102cwmx233 MACH_CWMX233 CWMX233 3481
1103cwam1808 MACH_CWAM1808 CWAM1808 3482
1104cwdm365 MACH_CWDM365 CWDM365 3483
1105mx51_moray MACH_MX51_MORAY MX51_MORAY 3484
1106thales_cbc MACH_THALES_CBC THALES_CBC 3485
1107bluepoint MACH_BLUEPOINT BLUEPOINT 3486
1108dir665 MACH_DIR665 DIR665 3487
1109acmerover1 MACH_ACMEROVER1 ACMEROVER1 3488
1110shooter_ct MACH_SHOOTER_CT SHOOTER_CT 3489
1111bliss MACH_BLISS BLISS 3490
1112blissc MACH_BLISSC BLISSC 3491
1113thales_adc MACH_THALES_ADC THALES_ADC 3492
1114ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493
1115atdgp318 MACH_ATDGP318 ATDGP318 3494