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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2008-04-23 20:48:40 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-04-28 12:14:32 -0400
commit4247417d8457b326ede001cb74af8570b5aa302b (patch)
treed52e4b8e5c7a8fe6d353234984d6414c9982b987 /arch
parent05a96fae433a662e12879b543a6838b6c2129402 (diff)
[MIPS] add DECstation I/O ASIC clocksource
Add DECstation I/O ASIC clocksource Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig4
-rw-r--r--arch/mips/dec/time.c2
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/csrc-ioasic.c65
4 files changed, 71 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 77e3d2402454..2e4ac657a4c3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -82,6 +82,7 @@ config MACH_DECSTATION
82 bool "DECstations" 82 bool "DECstations"
83 select BOOT_ELF32 83 select BOOT_ELF32
84 select CEVT_R4K 84 select CEVT_R4K
85 select CSRC_IOASIC
85 select CSRC_R4K 86 select CSRC_R4K
86 select CPU_DADDI_WORKAROUNDS if 64BIT 87 select CPU_DADDI_WORKAROUNDS if 64BIT
87 select CPU_R4000_WORKAROUNDS if 64BIT 88 select CPU_R4000_WORKAROUNDS if 64BIT
@@ -784,6 +785,9 @@ config CEVT_TXX9
784config CSRC_BCM1480 785config CSRC_BCM1480
785 bool 786 bool
786 787
788config CSRC_IOASIC
789 bool
790
787config CSRC_R4K 791config CSRC_R4K
788 bool 792 bool
789 793
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 60349062595a..0cbab8d0052b 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -165,7 +165,7 @@ void __init plat_time_init(void)
165 165
166 if (!cpu_has_counter && IOASIC) 166 if (!cpu_has_counter && IOASIC)
167 /* For pre-R4k systems we use the I/O ASIC's counter. */ 167 /* For pre-R4k systems we use the I/O ASIC's counter. */
168 clocksource_mips.read = dec_ioasic_hpt_read; 168 dec_ioasic_clocksource_init();
169 169
170 /* Set up the rate of periodic DS1287 interrupts. */ 170 /* Set up the rate of periodic DS1287 interrupts. */
171 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A); 171 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 87067e8fee9e..00ac35e501b3 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
14obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o 14obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
15obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 15obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
16obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 16obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
17obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
17obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 18obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
18obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 19obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
19obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 20obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
new file mode 100644
index 000000000000..1d5f63cf8997
--- /dev/null
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -0,0 +1,65 @@
1/*
2 * DEC I/O ASIC's counter clocksource
3 *
4 * Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/clocksource.h>
21#include <linux/init.h>
22
23#include <asm/ds1287.h>
24#include <asm/time.h>
25#include <asm/dec/ioasic.h>
26#include <asm/dec/ioasic_addrs.h>
27
28static cycle_t dec_ioasic_hpt_read(void)
29{
30 return ioasic_read(IO_REG_FCTR);
31}
32
33static struct clocksource clocksource_dec = {
34 .name = "dec-ioasic",
35 .read = dec_ioasic_hpt_read,
36 .mask = CLOCKSOURCE_MASK(32),
37 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
38};
39
40void __init dec_ioasic_clocksource_init(void)
41{
42 unsigned int freq;
43 u32 start, end;
44 int i = HZ / 10;
45
46
47 while (!ds1287_timer_state())
48 ;
49
50 start = dec_ioasic_hpt_read();
51
52 while (i--)
53 while (!ds1287_timer_state())
54 ;
55
56 end = dec_ioasic_hpt_read();
57
58 freq = (end - start) * 10;
59 printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
60
61 clocksource_dec.rating = 200 + freq / 10000000;
62 clocksource_set_clock(&clocksource_dec, freq);
63
64 clocksource_register(&clocksource_dec);
65}