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authorRalf Baechle <ralf@linux-mips.org>2005-10-06 12:39:32 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:36 -0400
commit101b3531a693ad890f33f2f04323592cd376616a (patch)
treeadb9410d492ee3dca0fd437191213a28e02edcf4 /arch
parent8afcb5d82934c83fb01664ae00eaff9de1d8d340 (diff)
Protect manipulation of c0_status against preemption and multithreading.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/kernel/ptrace.c39
-rw-r--r--arch/mips/kernel/ptrace32.c20
2 files changed, 47 insertions, 12 deletions
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 122433f835e3..fcceab8f2e00 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -33,6 +33,7 @@
33#include <asm/dsp.h> 33#include <asm/dsp.h>
34#include <asm/fpu.h> 34#include <asm/fpu.h>
35#include <asm/mipsregs.h> 35#include <asm/mipsregs.h>
36#include <asm/mipsmtregs.h>
36#include <asm/pgtable.h> 37#include <asm/pgtable.h>
37#include <asm/page.h> 38#include <asm/page.h>
38#include <asm/system.h> 39#include <asm/system.h>
@@ -126,10 +127,21 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
126 127
127 __put_user (child->thread.fpu.hard.fcr31, data + 64); 128 __put_user (child->thread.fpu.hard.fcr31, data + 64);
128 129
129 flags = read_c0_status(); 130 preempt_disable();
130 __enable_fpu(); 131 if (cpu_has_mipsmt) {
131 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); 132 unsigned int vpflags = dvpe();
132 write_c0_status(flags); 133 flags = read_c0_status();
134 __enable_fpu();
135 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
136 write_c0_status(flags);
137 evpe(vpflags);
138 } else {
139 flags = read_c0_status();
140 __enable_fpu();
141 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
142 write_c0_status(flags);
143 }
144 preempt_enable();
133 __put_user (tmp, data + 65); 145 __put_user (tmp, data + 65);
134 } else { 146 } else {
135 __put_user (child->thread.fpu.soft.fcr31, data + 64); 147 __put_user (child->thread.fpu.soft.fcr31, data + 64);
@@ -284,10 +296,21 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
284 if (!cpu_has_fpu) 296 if (!cpu_has_fpu)
285 break; 297 break;
286 298
287 flags = read_c0_status(); 299 preempt_disable();
288 __enable_fpu(); 300 if (cpu_has_mipsmt) {
289 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 301 unsigned int vpflags = dvpe();
290 write_c0_status(flags); 302 flags = read_c0_status();
303 __enable_fpu();
304 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
305 write_c0_status(flags);
306 evpe(vpflags);
307 } else {
308 flags = read_c0_status();
309 __enable_fpu();
310 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
311 write_c0_status(flags);
312 }
313 preempt_enable();
291 break; 314 break;
292 } 315 }
293 case DSP_BASE ... DSP_BASE + 5: { 316 case DSP_BASE ... DSP_BASE + 5: {
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index c28cdddd4c21..9a9b04972132 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -29,6 +29,7 @@
29#include <asm/dsp.h> 29#include <asm/dsp.h>
30#include <asm/fpu.h> 30#include <asm/fpu.h>
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/page.h> 34#include <asm/page.h>
34#include <asm/system.h> 35#include <asm/system.h>
@@ -191,10 +192,21 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
191 if (!cpu_has_fpu) 192 if (!cpu_has_fpu)
192 break; 193 break;
193 194
194 flags = read_c0_status(); 195 preempt_disable();
195 __enable_fpu(); 196 if (cpu_has_mipsmt) {
196 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 197 unsigned int vpflags = dvpe();
197 write_c0_status(flags); 198 flags = read_c0_status();
199 __enable_fpu();
200 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
201 write_c0_status(flags);
202 evpe(vpflags);
203 } else {
204 flags = read_c0_status();
205 __enable_fpu();
206 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
207 write_c0_status(flags);
208 }
209 preempt_enable();
198 break; 210 break;
199 } 211 }
200 case DSP_BASE ... DSP_BASE + 5: 212 case DSP_BASE ... DSP_BASE + 5: