diff options
author | Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> | 2010-10-18 17:32:48 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-21 09:53:39 -0500 |
commit | 47bb3b31ab2c95e275b850a291794a29aaaa31cd (patch) | |
tree | 4f759fc86d68c70f7c475ca1d74385eb9624f4ee /arch | |
parent | 9f15d2caca102c4b79e34562296bcbf982665cb2 (diff) |
ARM: 6451/1: sa1100: Fix checkpatch.pl issues in arch/arm/mach-sa1100/cpu-sa1110.c.
This patch fixes checkpatch.pl issues in
arch/arm/mach-sa1100/cpu-sa1110.c.
Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-sa1100/cpu-sa1110.c | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c index 8251af277c1a..675bf8ef97e8 100644 --- a/arch/arm/mach-sa1100/cpu-sa1110.c +++ b/arch/arm/mach-sa1100/cpu-sa1110.c | |||
@@ -185,11 +185,13 @@ sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz, | |||
185 | sd->mdrefr |= MDREFR_K1DB2; | 185 | sd->mdrefr |= MDREFR_K1DB2; |
186 | 186 | ||
187 | /* initial number of '1's in MDCAS + 1 */ | 187 | /* initial number of '1's in MDCAS + 1 */ |
188 | set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz)); | 188 | set_mdcas(sd->mdcas, sd_khz >= 62000, |
189 | ns_to_cycles(sdram->trcd, mem_khz)); | ||
189 | 190 | ||
190 | #ifdef DEBUG | 191 | #ifdef DEBUG |
191 | printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n", | 192 | printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n", |
192 | sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]); | 193 | sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], |
194 | sd->mdcas[2]); | ||
193 | #endif | 195 | #endif |
194 | } | 196 | } |
195 | 197 | ||
@@ -218,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram) | |||
218 | 220 | ||
219 | #ifdef DEBUG | 221 | #ifdef DEBUG |
220 | mdelay(250); | 222 | mdelay(250); |
221 | printk("new dri value = %d\n", dri); | 223 | printk(KERN_DEBUG "new dri value = %d\n", dri); |
222 | #endif | 224 | #endif |
223 | 225 | ||
224 | sdram_set_refresh(dri); | 226 | sdram_set_refresh(dri); |
@@ -237,7 +239,7 @@ static int sa1110_target(struct cpufreq_policy *policy, | |||
237 | unsigned long flags; | 239 | unsigned long flags; |
238 | unsigned int ppcr, unused; | 240 | unsigned int ppcr, unused; |
239 | 241 | ||
240 | switch(relation){ | 242 | switch (relation) { |
241 | case CPUFREQ_RELATION_L: | 243 | case CPUFREQ_RELATION_L: |
242 | ppcr = sa11x0_freq_to_ppcr(target_freq); | 244 | ppcr = sa11x0_freq_to_ppcr(target_freq); |
243 | if (sa11x0_ppcr_to_freq(ppcr) > policy->max) | 245 | if (sa11x0_ppcr_to_freq(ppcr) > policy->max) |
@@ -285,11 +287,10 @@ static int sa1110_target(struct cpufreq_policy *policy, | |||
285 | * We wait 20ms to be safe. | 287 | * We wait 20ms to be safe. |
286 | */ | 288 | */ |
287 | sdram_set_refresh(2); | 289 | sdram_set_refresh(2); |
288 | if (!irqs_disabled()) { | 290 | if (!irqs_disabled()) |
289 | msleep(20); | 291 | msleep(20); |
290 | } else { | 292 | else |
291 | mdelay(20); | 293 | mdelay(20); |
292 | } | ||
293 | 294 | ||
294 | /* | 295 | /* |
295 | * Reprogram the DRAM timings with interrupts disabled, and | 296 | * Reprogram the DRAM timings with interrupts disabled, and |
@@ -300,7 +301,7 @@ static int sa1110_target(struct cpufreq_policy *policy, | |||
300 | local_irq_save(flags); | 301 | local_irq_save(flags); |
301 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); | 302 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); |
302 | udelay(10); | 303 | udelay(10); |
303 | __asm__ __volatile__(" \n\ | 304 | __asm__ __volatile__("\n\ |
304 | b 2f \n\ | 305 | b 2f \n\ |
305 | .align 5 \n\ | 306 | .align 5 \n\ |
306 | 1: str %3, [%1, #0] @ MDCNFG \n\ | 307 | 1: str %3, [%1, #0] @ MDCNFG \n\ |
@@ -356,7 +357,8 @@ static struct sdram_params *sa1110_find_sdram(const char *name) | |||
356 | { | 357 | { |
357 | struct sdram_params *sdram; | 358 | struct sdram_params *sdram; |
358 | 359 | ||
359 | for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++) | 360 | for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); |
361 | sdram++) | ||
360 | if (strcmp(name, sdram->name) == 0) | 362 | if (strcmp(name, sdram->name) == 0) |
361 | return sdram; | 363 | return sdram; |
362 | 364 | ||
@@ -381,7 +383,7 @@ static int __init sa1110_clk_init(void) | |||
381 | if (machine_is_h3100()) | 383 | if (machine_is_h3100()) |
382 | name = "KM416S4030CT"; | 384 | name = "KM416S4030CT"; |
383 | if (machine_is_jornada720()) | 385 | if (machine_is_jornada720()) |
384 | name = "K4S281632B-1H"; | 386 | name = "K4S281632B-1H"; |
385 | if (machine_is_nanoengine()) | 387 | if (machine_is_nanoengine()) |
386 | name = "MT48LC8M16A2TG-75"; | 388 | name = "MT48LC8M16A2TG-75"; |
387 | } | 389 | } |